PIC18F6620T-I/PT [MICROCHIP]
8-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQFP64, 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-64;
| 型号： | PIC18F6620T-I/PT |
| 厂家： | 
MICROCHIP |
| 描述： | 8-BIT, FLASH, 25 MHz, RISC MICROCONTROLLER, PQFP64, 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-64 时钟 微控制器 外围集成电路 |
| 文件： | 总380页 (文件大小：6058K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18F6520/8520/6620/
8620/6720/8720
64/80-Pin High-Performance, 256 Kbit to 1 Mbit
Enhanced Flash Microcontrollers with A/D
High-Performance RISC CPU:
Analog Features:
• C compiler optimized architecture/instruction set:
- Source code compatible with the PIC16 and
PIC17 instruction sets
• Linear program memory addressing to 128 Kbytes
• Linear data memory addressing to 3840 bytes
• 1 Kbyte of data EEPROM
• 10-bit, up to 16-channel Analog-to-Digital
Converter (A/D):
- Conversion available during Sleep
• Programmable 16-level Low-Voltage Detection
(LVD) module:
- Supports interrupt on Low-Voltage Detection
• Programmable Brown-out Reset (PBOR)
• Dual analog comparators:
• Up to 10 MIPs operation:
- DC – 40 MHz osc./clock input
- 4 MHz – 10 MHz osc./clock input with PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 31-level, software accessible hardware stack
• 8 x 8 Single Cycle Hardware Multiplier
- Programmable input/output configuration
Special Microcontroller Features:
• 100,000 erase/write cycle Enhanced Flash
program memory typical
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• 1 second programming time
External Memory Interface
(PIC18F8X20 Devices Only):
• Flash/Data EEPROM Retention: > 40 years
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own On-Chip
RC Oscillator for reliable operation
• Programmable code protection
• Address capability of up to 2 Mbytes
• 16-bit interface
Peripheral Features:
• High current sink/source 25 mA/25 mA
• Four external interrupt pins
• Timer0 module: 8-bit/16-bit timer/counter
• Timer1 module: 16-bit timer/counter
• Timer2 module: 8-bit timer/counter
• Timer3 module: 16-bit timer/counter
• Timer4 module: 8-bit timer/counter
• Secondary oscillator clock option – Timer1/Timer3
• Five Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max. resolution 100 ns (TCY)
- PWM output: PWM resolution is 1 to 10-bit
• Master Synchronous Serial Port (MSSP) module
with two modes of operation:
• Power saving Sleep mode
• Selectable oscillator options including:
- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input
• In-Circuit Serial Programming™ (ICSP™) via
two pins
• MPLAB® In-Circuit Debug (ICD) via two pins
CMOS Technology:
• Low-power, high-speed Flash technology
• Fully static design
• Wide operating voltage range (2.0V to 5.5V)
• Industrial and Extended temperature ranges
- 3-wire SPI (supports all 4 SPI modes)
- I2C™ Master and Slave mode
• Two Addressable USART modules:
- Supports RS-485 and RS-232
• Parallel Slave Port (PSP) module
Program Memory
Data Memory
MSSP
10-bit
I/O A/D
(ch)
Max
FOSC
(MHz)
CCP
(PWM)
Timers
8-bit/16-bit Bus
Ext
Device
USART
# Single-Word SRAM EEPROM
Instructions (bytes) (bytes)
Master
Bytes
SPI
2
I C
PIC18F6520 32K
PIC18F6620 64K
PIC18F6720 128K
PIC18F8520 32K
PIC18F8620 64K
PIC18F8720 128K
16384
32768
65536
16384
32768
65536
2048
3840
3840
2048
3840
3840
1024
1024
1024
1024
1024
1024
52
52
52
68
68
68
12
12
12
16
16
16
5
5
5
5
5
5
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
2
2
2
2
2
2
2/3
2/3
2/3
2/3
2/3
2/3
N
N
N
Y
Y
Y
40
25
25
40
25
25
2003-2013 Microchip Technology Inc.
DS39609C-page 1
PIC18F6520/8520/6620/8620/6720/8720
Pin Diagrams
64-Pin TQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RB0/INT0
RE1/WR
RE0/RD
1
RB1/INT1
2
RB2/INT2
RG0/CCP3
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4
MCLR/VPP
RG4/CCP5
VSS
3
RB3/INT3
4
RB4/KBI0
5
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
6
7
PIC18F6520
PIC18F6620
PIC18F6720
8
OSC2/CLKO/RA6
OSC1/CLKI
VDD
9
VDD
10
11
12
13
14
15
16
RF7/SS
RB7/KBI3/PGD
RC5/SDO
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
RF3/AN8
RF2/AN7/C1OUT
Note 1: CCP2 is multiplexed with RC1 when CCP2MX is set.
DS39609C-page 2
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
Pin Diagrams (Continued)
80-Pin TQFP
RH2/A18
RH3/A19
1
2
RJ2/WRL
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RJ3/WRH
RB0/INT0
RB1/INT1
(3)
RE1/WR/AD9
RE0/RD/AD8
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
(3)
RG0/CCP3
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4
MCLR/VPP
RG4/CCP5
VSS
RB2/INT2
RB3/INT3/CCP2
RB4/KBI0
(1)
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI
VDD
RB7/KBI3/PGD
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
RJ7/UB
PIC18F8520
PIC18F8620
PIC18F8720
VDD
RF7/SS
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RF3/AN8
RF2/AN7/C1OUT
RH7/AN15
RH6/AN14
RJ6/LB
Note 1: CCP2 is multiplexed with RC1 when CCP2MX is set.
2: CCP2 is multiplexed by default with RE7 when the device is configured in Microcontroller mode.
3: PSP is available only in Microcontroller mode.
2003-2013 Microchip Technology Inc.
DS39609C-page 3
PIC18F6520/8520/6620/8620/6720/8720
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Oscillator Configurations ............................................................................................................................................................ 21
3.0 Reset.......................................................................................................................................................................................... 29
4.0 Memory Organization................................................................................................................................................................. 39
5.0 Flash Program Memory.............................................................................................................................................................. 61
6.0 External Memory Interface ......................................................................................................................................................... 71
7.0 Data EEPROM Memory ............................................................................................................................................................. 79
8.0 8 X 8 Hardware Multiplier........................................................................................................................................................... 85
9.0 Interrupts .................................................................................................................................................................................... 87
10.0 I/O Ports ................................................................................................................................................................................... 103
11.0 Timer0 Module ......................................................................................................................................................................... 131
12.0 Timer1 Module ......................................................................................................................................................................... 135
13.0 Timer2 Module ......................................................................................................................................................................... 141
14.0 Timer3 Module ......................................................................................................................................................................... 143
15.0 Timer4 Module ......................................................................................................................................................................... 147
16.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 149
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 157
18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 197
19.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 213
20.0 Comparator Module.................................................................................................................................................................. 223
21.0 Comparator Voltage Reference Module................................................................................................................................... 229
22.0 Low-Voltage Detect.................................................................................................................................................................. 233
23.0 Special Features of the CPU.................................................................................................................................................... 239
24.0 Instruction Set Summary.......................................................................................................................................................... 259
25.0 Development Support............................................................................................................................................................... 301
26.0 Electrical Characteristics .......................................................................................................................................................... 305
27.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 341
28.0 Packaging Information.............................................................................................................................................................. 355
Appendix A: Revision History............................................................................................................................................................. 361
Appendix B: Device Differences......................................................................................................................................................... 361
Appendix C: Conversion Considerations ........................................................................................................................................... 362
Appendix D: Migration from Mid-range to Enhanced Devices ........................................................................................................... 362
Appendix E: Migration from High-end to Enhanced Devices ............................................................................................................. 363
The Microchip Web Site..................................................................................................................................................................... 375
Customer Change Notification Service .............................................................................................................................................. 375
Customer Support.............................................................................................................................................................................. 375
Reader Response .............................................................................................................................................................................. 376
PIC18F6520/8520/6620/8620/6720/8720 Product Identification System .......................................................................................... 377
DS39609C-page 4
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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Microchip’s Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
2003-2013 Microchip Technology Inc.
DS39609C-page 5
PIC18F6520/8520/6620/8620/6720/8720
NOTES:
DS39609C-page 6
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
With the addition of new operating modes, the External
Memory Interface offers many new options, including:
1.0
DEVICE OVERVIEW
This document contains device specific information for
the following devices:
• Operating the microcontroller entirely from external
memory
• PIC18F6520
• PIC18F6620
• PIC18F6720
• PIC18F8520
• PIC18F8620
• PIC18F8720
• Using combinations of on-chip and external
memory, up to the 2-Mbyte limit
• Using external Flash memory for reprogrammable
application code, or large data tables
This family offers the same advantages of all PIC18
microcontrollers namely, high computational
• Using external RAM devices for storing large
amounts of variable data
–
performance at an economical price – with the addition of
high endurance Enhanced Flash program memory. The
PIC18FXX20 family also provides an enhanced range of
program memory options and versatile analog features
that make it ideal for complex, high-performance
applications.
1.1.3
EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 64-pin
members, between the 80-pin members, or even
jumping from 64-pin to 80-pin devices.
1.1
Key Features
1.1.1
EXPANDED MEMORY
The PIC18FXX20 family introduces the widest range of
on-chip, Enhanced Flash program memory available
on PIC® microcontrollers – up to 128 Kbyte (or 65,536
words), the largest ever offered by Microchip. For users
with more modest code requirements, the family also
includes members with 32 Kbyte or 64 Kbyte.
1.1.4
OTHER SPECIAL FEATURES
• Communications: The PIC18FXX20 family
incorporates a range of serial communications
peripherals, including 2 independent USARTs and
a Master SSP module, capable of both SPI and
I2C (Master and Slave) modes of operation. For
PIC18F8X20 devices, one of the general purpose
I/O ports can be reconfigured as an 8-bit Parallel
Slave Port for direct processor-to-processor
communications.
Other memory features are:
• Data RAM and Data EEPROM: The
PIC18FXX20 family also provides plenty of room
for application data. Depending on the device,
either 2048 or 3840 bytes of data RAM are
available. All devices have 1024 bytes of data
EEPROM for long-term retention of nonvolatile
data.
• CCP Modules: All devices in the family
incorporate five Capture/Compare/PWM modules
to maximize flexibility in control applications. Up
to four different time bases may be used to
perform several different operations at once.
• Memory Endurance: The Enhanced Flash cells
for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles – up to 100,000 for program memory and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 years.
• Analog Features: All devices in the family
feature 10-bit A/D converters, with up to 16 input
channels, as well as the ability to perform
conversions during Sleep mode. Also included
are dual analog comparators with programmable
input and output configuration, a programmable
Low-Voltage Detect module and a programmable
Brown-out Reset module.
1.1.2
EXTERNAL MEMORY INTERFACE
In the event that 128 Kbytes of program memory is
inadequate for an application, the PIC18F8X20
members of the family also implement an External
Memory Interface. This allows the controller’s internal
program counter to address a memory space of up to
2 Mbytes, permitting a level of data access that few
8-bit devices can claim.
• Self-programmability: These devices can write
to their own program memory spaces under inter-
nal software control. By using a bootloader routine
located in the protected Boot Block at the top of
program memory, it becomes possible to create
an application that can update itself in the field.
2003-2013 Microchip Technology Inc.
DS39609C-page 7
PIC18F6520/8520/6620/8620/6720/8720
3. A/D channels (12 for PIC18F6X20 devices,
1.2
Details on Individual Family
Members
16 for PIC18F8X20)
4. I/O pins (52 on PIC18F6X20 devices, 68 on
PIC18F8X20)
The PIC18FXX20 devices are available in 64-pin and
80-pin packages. They are differentiated from each
other in five ways:
5. External program memory interface (present
only on PIC18F8X20 devices)
1. Flash program memory (32 Kbytes for
All other features for devices in the PIC18FXX20 family
are identical. These are summarized in Table 1-1.
PIC18FX520
devices,
64 Kbytes
for
PIC18FX620 devices and 128 Kbytes for
PIC18FX720 devices)
Block diagrams of the PIC18F6X20 and PIC18F8X20
devices are provided in Figure 1-1 and Figure 1-2,
respectively. The pinouts for these device families are
listed in Table 1-2.
2. Data RAM (2048 bytes for PIC18FX520
devices, 3840 bytes for PIC18FX620 and
PIC18FX720 devices)
TABLE 1-1:
PIC18FXX20 DEVICE FEATURES
Features
PIC18F6520
PIC18F6620
PIC18F6720
PIC18F8520
PIC18F8620
PIC18F8720
Operating Frequency
DC – 40 MHz
32K
DC – 25 MHz
64K
DC – 25 MHz
128K
DC – 40 MHz
32K
DC – 25 MHz
64K
DC – 25 MHz
128K
Program Memory
(Bytes)
Program Memory
(Instructions)
16384
2048
1024
No
32768
3840
1024
No
65536
3840
1024
No
16384
2048
1024
Yes
32768
3840
1024
Yes
65536
3840
1024
Yes
Data Memory
(Bytes)
Data EEPROM
Memory (Bytes)
External Memory
Interface
Interrupt Sources
I/O Ports
17
17
17
18
18
18
Ports A, B, C, Ports A, B, C, D, Ports A, B, C, D, Ports A, B, C,
Ports A, B, C,
Ports A, B, C,
D, E, F, G
E, F, G
E, F, G
D, E, F, G, H, J D, E, F, G, H, J D, E, F, G, H, J
Timers
5
5
5
5
5
5
5
5
5
5
5
5
Capture/Compare/
PWM Modules
Serial Communications
MSSP,
MSSP,
MSSP,
MSSP,
MSSP,
MSSP,
Addressable
USART (2)
Addressable
USART (2)
Addressable
USART (2)
Addressable
USART (2)
Addressable
USART (2)
Addressable
USART (2)
Parallel Communications
PSP
PSP
PSP
PSP
PSP
PSP
10-bit Analog-to-Digital
Module
12 input
channels
12 input
channels
12 input
channels
16 input
channels
16 input
channels
16 input
channels
Resets (and Delays)
POR, BOR,
RESET
POR, BOR,
RESET
POR, BOR,
RESET
POR, BOR,
RESET
POR, BOR,
RESET
POR, BOR,
RESET
Instruction,
Stack Full,
Instruction,
Stack Full,
Instruction,
Stack Full,
Instruction,
Stack Full,
Instruction,
Stack Full,
Instruction,
Stack Full,
Stack Underflow Stack Underflow Stack Underflow Stack Underflow Stack Underflow Stack Underflow
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
Programmable
Yes
Yes
Yes
Yes
Yes
Yes
Low-Voltage Detect
Programmable
Yes
Yes
Yes
Yes
Yes
Yes
Brown-out Reset
Instruction Set
Package
77 Instructions 77 Instructions
64-pin TQFP 64-pin TQFP
77 Instructions 77 Instructions 77 Instructions 77 Instructions
64-pin TQFP 80-pin TQFP 80-pin TQFP 80-pin TQFP
DS39609C-page 8
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 1-1:
PIC18F6X20 BLOCK DIAGRAM
Data Bus<8>
PORTA
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
Table Pointer<21>
inc/dec logic
Data Latch
Data RAM
21
8
8
21
RA5/AN4/LVDIN
RA6
Address Latch
12
21
PCLATU PCLATH
PORTB
RB0/INT0
RB1/INT1
Address<12>
PCU PCH PCL
Program Counter
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
4
BSR
12
FSR0
FSR1
FSR2
4
Bank0, F
Address Latch
31 Level Stack
Program Memory
12
Data Latch
inc/dec
logic
Decode
PORTC
Table Latch
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
8
16
ROM Latch
IR
RC6/TX1/CK1
RC7/RX1/DT1
8
PORTD
PORTE
PRODH PRODL
8 x 8 Multiply
RD7/PSP7:RD0/PSP0
Instruction
Decode &
Control
8
3
RE0/RD
RE1/WR
RE2/CS
RE3
RE4
RE5
WREG
8
BITOP
8
8
Power-up
Timer
OSC2/CLKO
OSC1/CLKI
Oscillator
Start-up Timer
Timing
Generation
8
ALU<8>
RE6
RE7/CCP2
Power-on
Reset
8
Watchdog
Timer
PORTF
RF0/AN5
Precision
Band Gap
Reference
Brown-out
Reset
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
RF4/AN9
RF5/AN10/CVREF
RF6/AN11
RF7/SS
MCLR/VPP
VDD, VSS
PORTG
Synchronous
Serial Port
RG0/CCP3
Data
EEPROM
USART2
USART1
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4
RG4/CCP5
BOR
LVD
Timer2
CCP3
Timer3
Timer0
CCP1
Timer1
CCP2
Timer4
CCP5
10-bit
A/D
CCP4
Comparator
2003-2013 Microchip Technology Inc.
DS39609C-page 9
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 1-2:
PIC18F8X20 BLOCK DIAGRAM
Data Bus<8>
PORTA
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/LVDIN
RA6
Table Pointer<21>
21
Data Latch
8
8
Data RAM
21
inc/dec logic
Address Latch
12
PORTB
21
PCLATU PCLATH
RB0/INT0
RB1/INT1
RB2/INT2
Address<12>
PCU PCH PCL
Program Counter
RB3/INT3/CCP2
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
4
BSR
12
FSR0
FSR1
FSR2
4
Bank0, F
Address Latch
31 Level Stack
Program Memory
12
Data Latch
PORTC
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2
RC2/CCP1
inc/dec
logic
Decode
Table Latch
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
8
16
ROM Latch
IR
AD15:AD0, A19:A16(1)
PORTD
PORTE
RD7/PSP7/AD7:
RD0/PSP0/AD0
8
PRODH PRODL
8 x 8 Multiply
RE0/RD/AD8
RE1/WR/AD9
RE2/CS/AD10
RE3/AD11
Instruction
Decode &
Control
8
3
RE4/AD12
RE5/AD13
RE6/AD14
WREG
8
BITOP
8
8
Power-up
Timer
OSC2/CLKO
OSC1/CLKI
RE7/CCP2/AD15
Oscillator
Start-up Timer
Timing
Generation
8
PORTF
RF0/AN5
ALU<8>
Power-on
Reset
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
RF4/AN9
RF5/AN10/CVREF
RF6/AN11
8
Watchdog
Timer
Precision
Band Gap
Reference
Brown-out
Reset
RF7/SS
PORTG
RG0/CCP3
MCLR/VPP
VDD, VSS
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4
RG4/CCP5
PORTH
PORTJ
RH3/AD19:RH0/AD16
RH7/AN15:RH4/AN12
Synchronous
Serial Port
Data
EEPROM
USART1
USART2
RJ0/ALE
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
BOR
LVD
Timer2
Timer3
Timer0
Timer1
Timer4
RJ6/LB
RJ7/UB
10-bit
A/D
Comparator
CCP1
CCP2
CCP3
CCP4
CCP5
Note 1: External memory interface pins are physically multiplexed with PORTD (AD7:AD0), PORTE (AD15:AD8) and PORTH (A19:A16).
DS39609C-page 10
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
Pin Name
PIC18FXX20 PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Buffer
Type
Description
Type
PIC18F6X20 PIC18F8X20
MCLR/VPP
MCLR
7
9
Master Clear (input) or programming
voltage (output).
I
ST
Master Clear (Reset) input. This pin is
an active-low Reset to the device.
Programming voltage input.
VPP
P
OSC1/CLKI
OSC1
39
49
Oscillator crystal or external clock input.
Oscillator crystal input or external clock
source input. ST buffer when configured
in RC mode; otherwise CMOS.
I
I
CMOS/ST
CMOS
CLKI
External clock source input. Always
associated with pin function OSC1
(see OSC1/CLKI, OSC2/CLKO pins).
OSC2/CLKO/RA6
OSC2
40
50
Oscillator crystal or clock output.
Oscillator crystal output.
O
O
—
—
Connects to crystal or resonator in
Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO,
which has 1/4 the frequency of OSC1
and denotes the instruction cycle rate.
General purpose I/O pin.
CLKO
RA6
I/O
TTL
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
2003-2013 Microchip Technology Inc.
DS39609C-page 11
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
Pin Name
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Buffer
Type
Description
Type
PIC18F6X20 PIC18F8X20
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
24
23
22
30
29
28
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D reference voltage (Low) input.
RA3/AN3/VREF+
RA3
21
28
27
27
34
33
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
AN3
VREF+
RA4/T0CKI
RA4
I/O
I
ST/OD
ST
Digital I/O – Open-drain when
configured as output.
Timer0 external clock input.
T0CKI
RA5/AN4/LVDIN
RA5
I/O
TTL
Digital I/O.
AN4
LVDIN
I
I
Analog
Analog
Analog input 4.
Low-Voltage Detect input.
RA6
See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
DS39609C-page 12
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
Pin Name
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Buffer
Type
Description
Type
PIC18F6X20 PIC18F8X20
PORTB is a bidirectional I/O port. PORTB
can be software programmed for internal
weak pull-ups on all inputs.
RB0/INT0
RB0
48
47
46
45
58
57
56
55
I/O
I
TTL
ST
Digital I/O.
External interrupt 0.
INT0
RB1/INT1
RB1
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
INT1
RB2/INT2
RB2
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
INT2
RB3/INT3/CCP2
RB3
I/O
I/O
I/O
TTL
ST
ST
Digital I/O.
INT3
External interrupt 3.
Capture2 input, Compare2 output,
PWM2 output.
CCP2(1)
RB4/KBI0
RB4
44
43
54
53
I/O
I
TTL
ST
Digital I/O.
Interrupt-on-change pin.
KBI0
RB5/KBI1/PGM
RB5
I/O
I
TTL
ST
Digital I/O.
Interrupt-on-change pin.
KBI1
PGM
I/O
ST
Low-Voltage ICSP Programming enable
pin.
RB6/KBI2/PGC
RB6
42
37
52
47
I/O
I
I/O
TTL
ST
ST
Digital I/O.
KBI2
PGC
Interrupt-on-change pin.
In-Circuit Debugger and
ICSP programming clock.
RB7/KBI3/PGD
RB7
I/O
I/O
TTL
ST
Digital I/O.
KBI3
PGD
Interrupt-on-change pin.
In-Circuit Debugger and
ICSP programming data.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
2003-2013 Microchip Technology Inc.
DS39609C-page 13
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
Pin Name
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Buffer
Type
Description
Type
PIC18F6X20 PIC18F8X20
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
30
29
36
35
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/CCP2
RC1
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
T1OSI
Timer1 oscillator input.
Capture2 input/Compare2 output/
PWM2 output.
CCP2(2)
RC2/CCP1
RC2
33
34
43
44
I/O
I/O
ST
ST
Digital I/O.
Capture1 input/Compare1 output/
PWM1 output.
CCP1
RC3/SCK/SCL
RC3
I/O
I/O
ST
ST
Digital I/O.
Synchronous serial clock input/output
for SPI mode.
SCK
SCL
I/O
ST
Synchronous serial clock input/output
for I2C mode.
RC4/SDI/SDA
RC4
35
45
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I2C data I/O.
SDI
SDA
RC5/SDO
RC5
36
31
46
37
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO
RC6/TX1/CK1
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX1
CK1
USART 1 asynchronous transmit.
USART 1 synchronous clock
(see RX1/DT1).
RC7/RX1/DT1
RC7
32
38
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX1
DT1
USART 1 asynchronous receive.
USART 1 synchronous data
(see TX1/CK1).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
DS39609C-page 14
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
Pin Name
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Buffer
Type
Description
Type
PIC18F6X20 PIC18F8X20
PORTD is a bidirectional I/O port. These
pins have TTL input buffers when external
memory is enabled.
RD0/PSP0/AD0
RD0
58
55
54
53
52
51
50
49
72
69
68
67
66
65
64
63
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External memory address/data 0.
PSP0
AD0(3)
RD1/PSP1/AD1
RD1
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External memory address/data 1.
PSP1
AD1(3)
RD2/PSP2/AD2
RD2
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External memory address/data 2.
PSP2
AD2(3)
RD3/PSP3/AD3
RD3
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External memory address/data 3.
PSP3
AD3(3)
RD4/PSP4/AD4
RD4
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External memory address/data 4.
PSP4
AD4(3)
RD5/PSP5/AD5
RD5
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External memory address/data 5.
PSP5
AD5(3)
RD6/PSP6/AD6
RD6
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External memory address/data 6.
PSP6
AD6(3)
RD7/PSP7/AD7
RD7
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
External memory address/data 7.
PSP7
AD7(3)
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
2003-2013 Microchip Technology Inc.
DS39609C-page 15
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
Pin Name
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Buffer
Type
Description
Type
PIC18F6X20 PIC18F8X20
PORTE is a bidirectional I/O port.
RE0/RD/AD8
RE0
2
1
4
3
I/O
I
ST
TTL
Digital I/O.
Read control for Parallel Slave Port
(see WR and CS pins).
RD
AD8(3)
I/O
TTL
External memory address/data 8.
RE1/WR/AD9
RE1
I/O
I
ST
TTL
Digital I/O.
Write control for Parallel Slave Port
(see CS and RD pins).
WR
AD9(3)
I/O
TTL
External memory address/data 9.
RE2/CS/AD10
64
78
RE2
CS
I/O
I
ST
TTL
Digital I/O.
Chip select control for Parallel Slave
Port (see RD and WR).
AD10(3)
I/O
TTL
External memory address/data 10.
RE3/AD11
RE3
63
62
61
60
59
77
76
75
74
73
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 11.
AD11(3)
RE4/AD12
RE4
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 12.
AD12
RE5/AD13
RE5
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 13.
AD13(3)
RE6/AD14
RE6
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 14.
AD14(3)
RE7/CCP2/AD15
RE7
I/O
I/O
ST
ST
Digital I/O.
Capture2 input/Compare2 output/
PWM2 output.
CCP2(1,4)
AD15(3)
I/O
TTL
External memory address/data 15.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
DS39609C-page 16
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
Pin Name
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Buffer
Type
Description
Type
PIC18F6X20 PIC18F8X20
PORTF is a bidirectional I/O port.
RF0/AN5
RF0
18
17
24
23
I/O
I
ST
Analog
Digital I/O.
Analog input 5.
AN5
RF1/AN6/C2OUT
RF1
I/O
I
O
ST
Analog
ST
Digital I/O.
Analog input 6.
Comparator 2 output.
AN6
C2OUT
RF2/AN7/C1OUT
RF2
16
18
I/O
I
O
ST
Analog
ST
Digital I/O.
Analog input 7.
Comparator 1 output.
AN7
C1OUT
RF3/AN8
RF1
15
14
13
17
16
15
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
AN8
RF4/AN9
RF1
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
AN9
RF5/AN10/CVREF
RF1
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 10.
Comparator VREF output.
AN10
CVREF
RF6/AN11
RF6
12
11
14
13
I/O
I
ST
Analog
Digital I/O.
Analog input 11.
AN11
RF7/SS
RF7
I/O
I
ST
TTL
Digital I/O.
SPI slave select input.
SS
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
2003-2013 Microchip Technology Inc.
DS39609C-page 17
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
Pin Name
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Buffer
Type
Description
Type
PIC18F6X20 PIC18F8X20
PORTG is a bidirectional I/O port.
RG0/CCP3
RG0
3
4
5
6
I/O
I/O
ST
ST
Digital I/O.
Capture3 input/Compare3 output/
PWM3 output.
CCP3
RG1/TX2/CK2
RG1
I/O
O
I/O
ST
—
ST
Digital I/O.
TX2
CK2
USART 2 asynchronous transmit.
USART 2 synchronous clock
(see RX2/DT2).
RG2/RX2/DT2
RG2
5
7
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX2
DT2
USART 2 asynchronous receive.
USART 2 synchronous data
(see TX2/CK2).
RG3/CCP4
RG3
6
8
8
I/O
I/O
ST
ST
Digital I/O.
Capture4 input/Compare4 output/
PWM4 output.
CCP4
RG4/CCP5
RG4
10
I/O
I/O
ST
ST
Digital I/O.
Capture5 input/Compare5 output/
PWM5 output.
CCP5
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
DS39609C-page 18
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
Pin Name
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Buffer
Type
Description
Type
PIC18F6X20 PIC18F8X20
PORTH is a bidirectional I/O port(5)
.
RH0/A16
RH0
—
—
—
—
—
—
—
—
79
80
1
I/O
O
ST
TTL
Digital I/O.
External memory address 16.
A16
RH1/A17
RH1
I/O
O
ST
TTL
Digital I/O.
External memory address 17.
A17
RH2/A18
RH2
I/O
O
ST
TTL
Digital I/O.
External memory address 18.
A18
RH3/A19
RH3
2
I/O
O
ST
TTL
Digital I/O.
External memory address 19.
A19
RH4/AN12
RH4
22
21
20
19
I/O
I
ST
Analog
Digital I/O.
Analog input 12.
AN12
RH5/AN13
RH5
I/O
I
ST
Analog
Digital I/O.
Analog input 13.
AN13
RH6/AN14
RH6
I/O
I
ST
Analog
Digital I/O.
Analog input 14.
AN14
RH7/AN15
RH7
I/O
I
ST
Analog
Digital I/O.
Analog input 15.
AN15
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
2003-2013 Microchip Technology Inc.
DS39609C-page 19
PIC18F6520/8520/6620/8620/6720/8720
TABLE 1-2:
Pin Name
PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Buffer
Type
Description
Type
PIC18F6X20 PIC18F8X20
PORTJ is a bidirectional I/O port(5)
.
RJ0/ALE
RJ0
—
—
—
—
—
—
—
—
62
61
60
59
39
40
41
42
I/O
O
ST
TTL
Digital I/O.
External memory address latch enable.
ALE
RJ1/OE
RJ1
I/O
O
ST
TTL
Digital I/O.
External memory output enable.
OE
RJ2/WRL
RJ2
I/O
O
ST
TTL
Digital I/O.
External memory write low control.
WRL
RJ3/WRH
RJ3
I/O
O
ST
TTL
Digital I/O.
External memory write high control.
WRH
RJ4/BA0
RJ4
I/O
O
ST
TTL
Digital I/O.
External memory Byte Address 0 control.
BA0
RJ5/CE
RJ5
I/O
O
ST
TTL
Digital I/O.
External memory chip enable control.
CE
RJ6/LB
RJ6
I/O
O
ST
TTL
Digital I/O.
External memory low byte select.
LB
RJ7/UB
RJ7
I/O
O
ST
TTL
Digital I/O.
External memory high byte select.
UB
VSS
VDD
9, 25,
41, 56
11, 31,
51, 70
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
10, 26,
38, 57
12, 32,
48, 71
P
(6)
AVSS
20
19
26
25
P
P
—
—
Ground reference for analog modules.
Positive supply for analog modules.
(6)
AVDD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all operating modes except
Microcontroller).
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for
proper operation of the part in user or ICSP modes. See parameter D001A for details.
DS39609C-page 20
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TABLE 2-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
2.0
2.1
OSCILLATOR
CONFIGURATIONS
Ranges Tested:
Oscillator Types
Mode
Freq
C1
C2
The PIC18FXX20 devices can be operated in eight
different oscillator modes. The user can program three
configuration bits (FOSC2, FOSC1 and FOSC0) to
select one of these eight modes:
XT
455 kHz
2.0 MHz
4.0 MHz
68-100 pF
15-68 pF
15-68 pF
68-100 pF
15-68 pF
15-68 pF
HS
8.0 MHz
16.0 MHz
10-68 pF
10-22 pF
10-68 pF
10-22 pF
1. LP
Low-Power Crystal
2. XT
Crystal/Resonator
These values are for design guidance only.
See notes following this table.
3. HS
High-Speed Crystal/Resonator
4. HS+PLL
High-Speed Crystal/Resonator
with PLL enabled
Resonators Used:
2.0 MHz Murata Erie CSA2.00MG
4.0 MHz Murata Erie CSA4.00MG
8.0 MHz Murata Erie CSA8.00MT
16.0 MHz Murata Erie CSA16.00MX
0.5%
5. RC
External Resistor/Capacitor
0.5%
0.5%
0.5%
6. RCIO
External Resistor/Capacitor with
I/O pin enabled
7. EC
External Clock
All resonators used did not have built-in capacitors.
8. ECIO
External Clock with I/O pin
enabled
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
2.2
Crystal Oscillator/Ceramic
Resonators
2: When operating below 3V VDD, or when
using certain ceramic resonators at any
voltage, it may be necessary to use high
gain HS mode, try a lower frequency
resonator, or switch to a crystal oscillator.
In XT, LP, HS or HS+PLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
The PIC18FXX20 oscillator design requires the use of
a parallel cut crystal.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
Note:
Use of a series cut crystal may give a fre-
quency out of the crystal manufacturer’s
specifications.
appropriate
components,
performance.
values
or
of
verify
external
oscillator
FIGURE 2-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS, XT OR LP
CONFIGURATION)
(1)
C1
OSC1
To
Internal
Logic
(3)
RF
XTAL
Sleep
(2)
RS
(1)
C2
PIC18FXX20
OSC2
Note 1: See Table 2-1 and Table 2-2 for recommended
values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the oscillator mode chosen.
2003-2013 Microchip Technology Inc.
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TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
FIGURE 2-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LPOSCCONFIGURATION)
Ranges Tested:
Mode
Freq
C1
C2
OSC1
Clock from
Ext. System
LP
32 kHz
200 kHz
1 MHz
4 MHz
4 MHz
8 MHz
20 MHz
PIC18FXX20
OSC2
15-22 pF
15-22 pF
Open
XT
HS
15-22 pF
15-22 pF
15-22 pF
15-22 pF
2.3
RC Oscillator
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) val-
ues and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit, due
to normal process parameter variation. Furthermore,
the difference in lead frame capacitance between pack-
age types will also affect the oscillation frequency,
especially for low CEXT values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 2-3 shows how the
R/C combination is connected.
Capacitor values are for design guidance only.
These capacitors were tested with the above crystal
frequencies for basic start-up and operation. These
values are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following this table for additional
information.
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
2: When operating below 3V VDD, or when
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
FIGURE 2-3:
RC OSCILLATOR MODE
VDD
3: Since each resonator/crystal has its
own characteristics, the user should
consult the resonator/crystal manufac-
turer for appropriate values of external
REXT
Internal
OSC1
Clock
CEXT
VSS
components,
performance.
or
verify
oscillator
PIC18FXX20
OSC2/CLKO
FOSC/4
4: RS may be required to avoid overdriving
crystals with low drive level specification.
Recommended values: 3 k REXT 100 k
5: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
CEXT > 20 pF
The RCIO Oscillator mode functions like the RC mode,
except that the OSC2 pin becomes an additional
general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).
An external clock source may also be connected to the
OSC1 pin in the HS, XT and LP modes, as shown in
Figure 2-2.
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FIGURE 2-5:
EXTERNAL CLOCK INPUT
OPERATION
(ECIOCONFIGURATION)
2.4
External Clock Input
The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is a maximum
1.5 s start-up required after a Power-on Reset, or
wake-up from Sleep mode.
OSC1
Clock from
Ext. System
PIC18FXX20
I/O (OSC2)
RA6
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.
2.5
HS/PLL
A Phase Locked Loop circuit (PLL) is provided as a
programmable option for users that want to multiply the
frequency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high-frequency crystals.
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION
(EC CONFIGURATION)
OSC1
Clock from
Ext. System
The PLL is one of the modes of the FOSC<2:0> config-
uration bits. The oscillator mode is specified during
device programming.
PIC18FXX20
OSC2
FOSC/4
The PLL can only be enabled when the oscillator con-
figuration bits are programmed for HS mode. If they are
programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1. Also, PLL operation cannot be changed “on-
the-fly”. To enable or disable it, the controller must
either cycle through a Power-on Reset, or switch the
clock source from the main oscillator to the Timer1
oscillator and back again. See Section 2.6 “Oscillator
Switching Feature” for details on oscillator switching.
The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called TPLL.
FIGURE 2-6:
PLL BLOCK DIAGRAM
(from Configuration
bit Register)
HS Osc
PLL Enable
Phase
Comparator
OSC2
OSC1
FIN
Loop
Filter
VCO
FOUT
Crystal
Osc
SYSCLK
Divide by 4
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execution mode. Figure 2-7 shows a block diagram of
the system clock sources. The clock switching feature
is enabled by programming the Oscillator Switching
Enable (OSCSEN) bit in Configuration Register 1H to a
‘0’. Clock switching is disabled in an erased device.
See Section 12.0 “Timer1 Module” for further details
of the Timer1 oscillator. See Section 23.0 “Special
Features of the CPU” for Configuration register
details.
2.6
Oscillator Switching Feature
The PIC18FXX20 devices include a feature that allows
the system clock source to be switched from the main
oscillator to an alternate low-frequency clock source.
For the PIC18FXX20 devices, this alternate clock
source is the Timer1 oscillator. If a low-frequency
crystal (32 kHz, for example) has been attached to the
Timer1 oscillator pins and the Timer1 oscillator has
been enabled, the device can switch to a low-power
FIGURE 2-7:
DEVICE CLOCK SOURCES
PIC18FXX20
Main Oscillator
OSC2
TOSC/4
4 x PLL
Sleep
TOSC
TSCLK
OSC1
Timer1 Oscillator
T1OSO
TT1P
T1OSCEN
Clock
Source
Enable
Oscillator
T1OSI
Clock Source Option
for other Modules
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2.6.1
SYSTEM CLOCK SWITCH BIT
Note:
The Timer1 oscillator must be enabled
and operating to switch the system clock
source. The Timer1 oscillator is enabled
by setting the T1OSCEN bit in the Timer1
Control register (T1CON). If the Timer1
oscillator is not enabled, then any write to
the SCS bit will be ignored (SCS bit forced
cleared) and the main oscillator will
continue to be the system clock source.
The system clock source switching is performed under
software control. The system clock switch bit, SCS
(OSCCON<0>), controls the clock switching. When the
SCS bit is ‘0’, the system clock source comes from the
main oscillator that is selected by the FOSC configura-
tion bits in Configuration Register 1H. When the SCS
bit is set, the system clock source will come from the
Timer1 oscillator. The SCS bit is cleared on all forms of
Reset.
REGISTER 2-1:
OSCCON REGISTER
U-0
—
U-0
—
U-0
—
U-0
U-0
—
U-0
—
U-0
—
R/W-1
SCS
—
bit 7
bit 0
bit 7-1 Unimplemented: Read as ‘0’
bit 0 SCS: System Clock Switch bit
When OSCSEN Configuration bit = 0and T1OSCEN bit is set:
1= Switch to Timer1 oscillator/clock pin
0= Use primary oscillator/clock input pin
When OSCSEN and T1OSCEN are in other states:
Bit is forced clear.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is shown in Figure 2-8.
The Timer1 oscillator is assumed to be running all the
time. After the SCS bit is set, the processor is frozen at
the next occurring Q1 cycle. After eight synchronization
cycles are counted from the Timer1 oscillator, operation
resumes. No additional delays are required after the
synchronization cycles.
2.6.2
OSCILLATOR TRANSITIONS
PIC18FXX20 devices contain circuitry to prevent
“glitches” when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to. This
ensures that the new clock source is stable and that its
pulse width will not be less than the shortest pulse
width of the two clock sources.
FIGURE 2-8:
TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q1 Q2 Q3 Q4 Q1
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
TT1P
1
2
3
4
5
6
7
8
T1OSI
OSC1
TSCS
TOSC
Internal
System
Clock
TDLY
SCS
(OSCCON<0>)
Program
Counter
PC
PC + 2
PC + 4
Note 1:Delay on internal system clock is eight oscillator cycles for synchronization.
The sequence of events that takes place when switch-
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
If the main oscillator is configured for an external
crystal (HS, XT, LP), then the transition will take place
after an oscillator start-up time (TOST) has occurred. A
timing diagram, indicating the transition from the
Timer1 oscillator to the main oscillator for HS, XT and
LP modes, is shown in Figure 2-9.
FIGURE 2-9:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q1 Q2 Q3 Q4 Q1 Q2 Q3
Q3
Q4
Q1
TT1P
T1OSI
OSC1
1
2
3
4
5
6
7
8
TOST
TSCS
OSC2
TOSC
Internal
System Clock
SCS
(OSCCON<0>)
Program
Counter
PC + 6
PC
PC + 2
Note 1:TOST = 1024 TOSC (drawing not to scale).
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If the main oscillator is configured for HS-PLL mode, an
frequency. A timing diagram, indicating the transition
from the Timer1 oscillator to the main oscillator for
HS-PLL mode, is shown in Figure 2-10.
oscillator start-up time (TOST), plus an additional PLL
time-out (TPLL), will occur. The PLL time-out is typically
2 ms and allows the PLL to lock to the main oscillator
FIGURE 2-10:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
TT1P
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q4
Q1
T1OSI
OSC1
TOST
TPLL
OSC2
TSCS
TOSC
PLL Clock
Input
1
2
3
4
5
6
7
8
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter
PC
PC + 2
PC + 4
Note 1:TOST = 1024 TOSC (drawing not to scale).
If the main oscillator is configured in the RC, RCIO, EC
or ECIO modes, there is no oscillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram,
indicating the transition from the Timer1 oscillator to the
main oscillator for RC, RCIO, EC and ECIO modes, is
shown in Figure 2-11.
FIGURE 2-11:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3
Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
TT1P
T1OSI
OSC1
TOSC
6
1
4
5
7
8
2
3
OSC2
Internal System
Clock
SCS
(OSCCON<0>)
TSCS
Program
Counter
PC
PC + 2
PC + 4
Note 1:RC Oscillator mode assumed.
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2.7
Effects of Sleep Mode on the
On-Chip Oscillator
2.8
Power-up Delays
Power up delays are controlled by two timers so that no
external Reset circuitry is required for most
applications. The delays ensure that the device is kept
in Reset until the device power supply and clock are
stable. For additional information on Reset operation,
see Section 3.0 “Reset”.
When the device executes a SLEEPinstruction, the on-
chip clocks and oscillator are turned off and the device
is held at the beginning of an instruction cycle (Q1
state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, Sleep mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during Sleep will increase the current
consumed during Sleep. The user can wake from
Sleep through external Reset, Watchdog Timer Reset
or through an interrupt.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer (OST), intended to keep
the chip in Reset until the crystal oscillator is stable.
With the PLL enabled (HS/PLL Oscillator mode), the
time-out sequence following a Power-on Reset is differ-
ent from other oscillator modes. The time-out sequence
is as follows: First, the PWRT time-out is invoked after
a POR time delay has expired. Then, the Oscillator
Start-up Timer (OST) is invoked. However, this is still
not a sufficient amount of time to allow the PLL to lock
at high frequencies. The PWRT timer is used to provide
an additional fixed 2 ms (nominal) time-out to allow the
PLL ample time to lock to the incoming clock frequency.
TABLE 2-3:
OSC Mode
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin
OSC2 Pin
RC
Floating, external resistor should pull high
At logic low
RCIO
Floating, external resistor should pull high
Configured as PORTA, bit 6
Configured as PORTA, bit 6
At logic low
ECIO
Floating
Floating
EC
LP, XT and HS
Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
Note:
See Table 3-1 in Section 3.0 “Reset” for time-outs due to Sleep and MCLR Reset.
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Most registers are not affected by a WDT wake-up,
3.0
RESET
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 3-2.
These bits are used in software to determine the nature
of the Reset. See Table 3-3 for a full description of the
Reset states of all registers.
The PIC18FXX20 devices differentiate between
various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during Sleep
d) Watchdog Timer (WDT) Reset (during normal
operation)
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
e) Programmable Brown-out Reset (PBOR)
f) RESETInstruction
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses. The MCLR pin is not driven low by
any internal Resets, including the WDT.
g) Stack Full Reset
h) Stack Underflow Reset
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” on Power-on Reset, MCLR, WDT Reset, Brown-
out Reset, MCLR Reset during Sleep and by the
RESETinstruction.
FIGURE 3-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESETInstruction
Stack Full/Underflow Reset
Stack
Pointer
External Reset
WDT
Time-out
Reset
MCLR
WDT
Module
Sleep
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
S
BOREN
OST/PWRT
OST
10-bit Ripple Counter
Chip_Reset
Q
R
OSC1
PWRT
10-bit Ripple Counter
On-chip
RC OSC(1)
Enable PWRT
(2)
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 3-1 for time-out situations.
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3.1
Power-on Reset (POR)
3.3
Oscillator Start-up Timer (OST)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected. To take advantage of the POR
circuitry, tie the MCLR pin through a 1 k to 10 k
resistor to VDD. This will eliminate external RC
components usually needed to create a Power-on
Reset delay. A minimum rise rate for VDD is specified
(parameter D004). For a slow rise time, see Figure 3-2.
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycles (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or wake-up from
Sleep.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
3.4
PLL Lock Time-out
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to
provide a fixed time-out that is sufficient for the PLL to
lock to the main oscillator frequency. This PLL lock
time-out (TPLL) is typically 2 ms and follows the
oscillator start-up time-out.
FIGURE 3-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
VDD
3.5
Brown-out Reset (BOR)
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation will reset
the chip. A Reset may not occur if VDD falls below
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until VDD rises above
BVDD. If the Power-up Timer is enabled, it will be
invoked after VDD rises above BVDD; it then will keep
the chip in Reset for an additional time delay (parame-
ter #33). If VDD drops below BVDD while the Power-up
Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be initialized. Once
VDD rises above BVDD, the Power-up Timer will
execute the additional time delay.
D
R
R1
MCLR
PIC18FXX20
C
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 k is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 1 k to 10 k will limit any current flow-
ing into MCLR from external capacitor C, in
the event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
3.6
Time-out Sequence
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figures 3-3 through 3-7 depict time-out sequences on
power-up.
3.2
Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in Reset as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an accept-
able level. A configuration bit is provided to enable/
disable the PWRT.
Since the time-outs occur from the POR pulse, the
time-outs will expire if MCLR is kept low long enough.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXX20 device
operating in parallel.
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See DC
parameter #33 for details.
Table 3-2 shows the Reset conditions for some Special
Function Registers, while Table 3-3 shows the Reset
conditions for all of the registers.
DS39609C-page 30
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 3-1:
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2)
Wake-up from
Sleep or
Oscillator Switch
Oscillator
Configuration
Brown-out
PWRTE = 0
PWRTE = 1
HS with PLL enabled(1)
72 ms + 1024 TOSC
+ 2ms
1024 TOSC
+ 2 ms
72 ms(2) + 1024 TOSC
+ 2 ms
1024 TOSC + 2 ms
HS, XT, LP
EC
72 ms + 1024 TOSC
72 ms
1024 TOSC
1.5 s
—
72 ms(2) + 1024 TOSC
72 ms(2)
1024 TOSC
1.5 s(3)
—
External RC
72 ms
72 ms(2)
Note 1: 2 ms is the nominal time required for the 4xPLL to lock.
2: 72 ms is the nominal power-up timer delay, if implemented.
3: 1.5 s is the recovery time from Sleep. There is no recovery time from oscillator switch.
REGISTER 3-1:
RCON REGISTER BITS AND POSITIONS
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-1
POR
R/W-1
BOR
bit 7
Note 1: Refer to Section 4.14 “RCON Register” for bit definitions.
bit 0
TABLE 3-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
RCON
Register
Condition
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset
0000h
0000h
0--1 1100
0--u uuuu
1
u
1
u
1
u
0
u
0
u
u
u
u
u
MCLR Reset during normal
operation
Software Reset during normal
operation
0000h
0000h
0000h
0--0 uuuu
0--u uu11
0--u uu11
0
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
1
u
1
u
Stack Full Reset during normal
operation
Stack Underflow Reset during
normal operation
MCLR Reset during Sleep
WDT Reset
0000h
0000h
0--u 10uu
0--u 01uu
u--u 00uu
0--1 11u0
u--u 00uu
u
1
u
1
u
1
0
0
1
1
0
1
0
1
0
u
u
u
1
u
u
u
u
0
u
u
u
u
u
u
u
u
u
u
u
WDT Wake-up
PC + 2
0000h
PC + 2(1)
Brown-out Reset
Interrupt wake-up from Sleep
Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
2003-2013 Microchip Technology Inc.
DS39609C-page 31
PIC18F6520/8520/6620/8620/6720/8720
TABLE 3-3:
Register
TOSU
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets
Power-on Reset,
Brown-out Reset
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Applicable Devices
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 1111
1100 0000
N/A
---0 uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
uu-u uuuu(3)
---u uuuu
uuuu uuuu
PC + 2(2)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu uuuu(1)
uuuu uuuu(1)
N/A
PIC18F6X20 PIC18F8X20
---0 0000
TOSH
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 1111
1100 0000
N/A
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0 PIC18F6X20 PIC18F8X20
POSTDEC0 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
N/A
N/A
N/A
PREINC0
PLUSW0
FSR0H
FSR0L
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
xxxx xxxx
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
WREG
INDF1
POSTINC1 PIC18F6X20 PIC18F8X20
POSTDEC1 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
N/A
N/A
N/A
PREINC1
PLUSW1
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
N/A
N/A
N/A
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
DS39609C-page 32
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
Brown-out Reset
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Applicable Devices
FSR1H
FSR1L
BSR
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
---- xxxx
xxxx xxxx
---- 0000
N/A
---- uuuu
uuuu uuuu
---- 0000
N/A
---- uuuu
uuuu uuuu
---- uuuu
N/A
INDF2
POSTINC2 PIC18F6X20 PIC18F8X20
POSTDEC2 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
N/A
N/A
N/A
PREINC2
PLUSW2
FSR2H
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
---- ---0
--00 0101
---- ---0
0--q 11qq
xxxx xxxx
xxxx xxxx
0-00 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
1111 1111
---- ---0
--00 0101
---- ---0
0--q qquu
uuuu uuuu
uuuu uuuu
u-uu uuuu
0000 0000
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ---u
--uu uuuu
---- ---u
u--u qquu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
RCON(4)
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
2003-2013 Microchip Technology Inc.
DS39609C-page 33
PIC18F6520/8520/6620/8620/6720/8720
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
Brown-out Reset
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Register
Applicable Devices
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
xxxx xxxx
xxxx xxxx
--00 0000
--00 0000
0--- -000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 ----
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
---- --00
0000 0000
0000 0000
---- ----
xx-0 x000
uuuu uuuu
uuuu uuuu
--00 0000
--00 0000
0--- -000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 ----
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
---- --00
0000 0000
0000 0000
---- ----
uu-0 u000
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
u--- -uuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
---- --uu
uuuu uuuu
uuuu uuuu
---- ----
uu-0 u000
CCP1CON PIC18F6X20 PIC18F8X20
CCPR2H
CCPR2L
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
CCP2CON PIC18F6X20 PIC18F8X20
CCPR3H
CCPR3L
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
CCP3CON PIC18F6X20 PIC18F8X20
CVRCON
CMCON
TMR3H
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
TMR3L
T3CON
PSPCON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
EEADRH
EEADR
EEDATA
EECON2
EECON1
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
DS39609C-page 34
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
Brown-out Reset
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Applicable Devices
IPR3
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
--11 1111
--00 0000
--00 0000
-1-1 1111
-0-0 0000
-0-0 0000
0111 1111
0000 0000
0000 0000
0-00 --00
1111 1111
1111 1111
---1 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
-111 1111(5)
xxxx xxxx
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx(5)
--11 1111
--00 0000
--00 0000
-1-1 1111
-0-0 0000
-0-0 0000
0111 1111
0000 0000
0000 0000
0-00 --00
1111 1111
1111 1111
---1 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
-111 1111(5)
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
--uu uuuu
--uu uuuu
--uu uuuu
-u-u uuuu
-u-u uuuu(1)
-u-u uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu uuuu
u-uu --uu
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
MEMCON
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA(5,6)
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA(5,6)
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
2003-2013 Microchip Technology Inc.
DS39609C-page 35
PIC18F6520/8520/6620/8620/6720/8720
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
Brown-out Reset
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Register
Applicable Devices
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
xxxx xxxx
0000 xxxx
---x xxxx
x000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-x0x 0000(5)
0000 0000
1111 1111
-000 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
uuuu uuuu
0000 uuuu
uuuu uuuu
u000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u0u 0000(5)
0000 0000
1111 1111
-000 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
uuuu uuuu
uuuu uuuu
---u uuuu
u000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
PORTA(5,6) PIC18F6X20 PIC18F8X20
TMR4
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PR4
T4CON
CCPR4H
CCPR4L
CCP4CON PIC18F6X20 PIC18F8X20
CCPR5H
CCPR5L
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
CCP5CON PIC18F6X20 PIC18F8X20
SPBRG2
RCREG2
TXREG2
TXSTA2
RCSTA2
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
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FIGURE 3-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA 1 k RESISTOR)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 3-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 3-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
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FIGURE 3-6:
SLOW RISE TIME (MCLR TIED TO VDD VIA 1 kRESISTOR)
5V
0V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-7:
TIME-OUT SEQUENCE ON POR W/PLL ENABLED
(MCLR TIED TO VDD VIA 1 kRESISTOR)
VDD
MCLR
IINTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
TPLL
PLL TIME-OUT
INTERNAL RESET
Note:
TOST = 1024 clock cycles.
TPLL 2 ms max. First three stages of the PWRT timer.
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4.1.1
PIC18F8X20 PROGRAM MEMORY
MODES
4.0
MEMORY ORGANIZATION
There are three memory blocks in PIC18FXX20
devices. They are:
PIC18F8X20 devices differ significantly from their
PIC18 predecessors in their utilization of program
memory. In addition to available on-chip Flash program
memory, these controllers can also address up to
2 Mbytes of external program memory through the
External Memory Interface. There are four distinct
operating modes available to the controllers:
• Program Memory
• Data RAM
• Data EEPROM
Data and program memory use separate busses,
which allows for concurrent access of these blocks.
Additional detailed information for Flash program
memory and data EEPROM is provided in Section 5.0
“Flash Program Memory” and Section 7.0 “Data
EEPROM Memory”, respectively.
• Microprocessor (MP)
• Microprocessor with Boot Block (MPBB)
• Extended Microcontroller (EMC)
• Microcontroller (MC)
In addition to on-chip Flash, the PIC18F8X20 devices
are also capable of accessing external program mem-
ory through an external memory bus. Depending on the
selected operating mode (discussed in Section 4.1.1
“PIC18F8X20 Program Memory Modes”), the con-
trollers may access either internal or external program
memory exclusively, or both internal and external mem-
ory in selected blocks. Additional information on the
External Memory Interface is provided in Section 6.0
“External Memory Interface”.
The Program Memory mode is determined by setting
the two Least Significant bits of the CONFIG3L config-
uration byte, as shown in Register 4-1. (See also
Section 23.1 “Configuration Bits” for additional
details on the device configuration bits.)
The Program Memory modes operate as follows:
• The Microprocessor Mode permits access only
to external program memory; the contents of the
on-chip Flash memory are ignored. The 21-bit
program counter permits access to a 2-Mbyte
linear program memory space.
4.1
Program Memory Organization
• The Microprocessor with Boot Block Mode
accesses on-chip Flash memory from addresses
000000h to 0007FFh for PIC18F8520 devices
and from 000000h to 0001FFh for PIC18F8620
and PIC18F8720 devices. Above this, external
program memory is accessed all the way up to
the 2-Mbyte limit. Program execution automati-
cally switches between the two memories, as
required.
A 21-bit program counter is capable of addressing the
2-Mbyte program memory space. Accessing a location
between the physically implemented memory and the
2-Mbyte address will cause a read of all ‘0’s (a NOP
instruction).
Devices in the PIC18FXX20 family can be divided into
three groups, based on program memory size. The
PIC18FX520 devices (PIC18F6520 and PIC18F8520)
have 32 Kbytes of on-chip Flash memory, equivalent to
16,384 single-word instructions. The PIC18FX620
devices (PIC18F6620 and PIC18F8620) have
64 Kbytes of on-chip Flash memory, equivalent to
• The Microcontroller Mode accesses only on-
chip Flash memory. Attempts to read above the
physical limit of the on-chip Flash (7FFFh for the
PIC18F8520, 0FFFFh for the PIC18F8620,
1FFFFh for the PIC18F8720) causes a read of all
‘0’s (a NOPinstruction). The Microcontroller mode
is also the only operating mode available to
PIC18F6X20 devices.
32,768
single-word
instructions.
Finally,
the
PIC18FX720 devices (PIC18F6720 and PIC18F8720)
have 128 Kbytes of on-chip Flash memory, equivalent
to 65,536 single-word instructions.
For all devices, the Reset vector address is at 0000h
and the interrupt vector addresses are at 0008h and
0018h.
• The Extended Microcontroller Mode allows
access to both internal and external program
memories as a single block. The device can
access its entire on-chip Flash memory; above
this, the device accesses external program
memory up to the 2-Mbyte program space limit.
As with Boot Block mode, execution automatically
switches between the two memories, as required.
The program memory maps for all of the PIC18FXX20
devices are compared in Figure 4-1.
In all modes, the microcontroller has complete access
to data RAM and EEPROM.
Figure 4-2 compares the memory maps of the different
Program Memory modes. The differences between on-
chip and external memory access limitations are more
fully explained in Table 4-1.
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FIGURE 4-1:
INTERNAL PROGRAM MEMORY MAP AND STACK FOR PIC18FXX20 DEVICES
PC<20:0>
21
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
Stack Level 31
000000h
000008h
000000h
000008h
000000h
000008h
Reset Vector
High Priority
Interrupt Vector
000018h
000018h
000018h
Low Priority
Interrupt Vector
On-Chip Flash
Program Memory
On-Chip Flash
Program Memory
007FFFh
008000h
On-Chip Flash
Program Memory
00FFFFh
010000h
01FFFFh
020000h
Read ‘0’
Read ‘0’
Read ‘0’
1FFFFFh
200000h
1FFFFFh
200000h
1FFFFFh
200000h
PIC18FX520
(32 Kbyte)
PIC18FX620
(64 Kbyte)
PIC18FX720
(128 Kbyte)
Note:
Size of memory regions not to scale.
TABLE 4-1:
Operating Mode
Microprocessor
MEMORY ACCESS FOR PIC18F8X20 PROGRAM MEMORY MODES
Internal Program Memory
External Program Memory
Execution
From
Table Read
Execution
From
Table Read
From
Table Write To
Table Write To
From
No Access
Yes
No Access
Yes
No Access
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Microprocessor
with Boot Block
Microcontroller
Yes
Yes
Yes
Yes
Yes
Yes
No Access
Yes
No Access
Yes
No Access
Yes
Extended
Microcontroller
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REGISTER 4-1:
CONFIG3L CONFIGURATION BYTE
R/P-1
WAIT
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
PM1
R/P-1
PM0
bit 7
bit 0
bit 7
WAIT: External Bus Data Wait Enable bit
1= Wait selections unavailable, device will not wait
0= Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>)
bit 6-2
bit 1-0
Unimplemented: Read as ‘0’
PM1:PM0: Processor Data Memory Mode Select bits
11= Microcontroller mode
10= Microprocessor mode
01= Microcontroller with Boot Block mode
00= Extended Microcontroller mode
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
- n = Value after erase
FIGURE 4-2:
MEMORY MAPS FOR PIC18F8X20 PROGRAM MEMORY MODES
Microprocessor
with Boot Block
Mode (MPBB)
Extended
Microcontroller
Mode (EMC)
Microprocessor
Mode (MP)
Microcontroller
Mode (MC)
000000h
000000h
000000h
000000h
On-Chip
Program
Memory
(No
On-Chip
On-Chip
Program
Memory
On-Chip
Program
Memory
Program
Memory
access)
Boot
Boot+1
Boundary
Boundary+1
Boundary
Boundary+1
External
Program
Memory
Reads
‘0’s
External
Program
Memory
External
Program
Memory
1FFFFFh
1FFFFFh
1FFFFFh
1FFFFFh
External
Memory
External
Memory
On-Chip
Flash
On-Chip
Flash
External On-Chip
Memory Flash
On-Chip
Flash
Boundary Values for Microprocessor with Boot Block, Microcontroller and Extended Microcontroller modes(1)
Available
Memory Mode(s)
Device
Boot
Boot+1
Boundary
Boundary+1
PIC18F6520
PIC18F6620
PIC18F6720
PIC18F8520
PIC18F8620
PIC18F8720
0007FFh
0001FFh
0001FFh
0007FFh
0001FFh
0001FFh
000800h
000200h
000200h
000800h
000200h
000200h
007FFFh
00FFFFh
01FFFFh
007FFFh
00FFFFh
01FFFFh
008000h
010000h
020000h
008000h
010000h
020000h
MC
MC
MC
MP, MPBB, MC, EMC
MP, MPBB, MC, EMC
MP, MPBB, MC, EMC
Note 1: PIC18F6X20 devices are included here for completeness, to show the boundaries of their Boot Blocks and program memory spaces.
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4.2.2
RETURN STACK POINTER
(STKPTR)
4.2
Return Address Stack
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALLor RCALLinstruction is executed, or an interrupt
is Acknowledged. The PC value is pulled off the stack
on a RETURN, RETLWor a RETFIEinstruction. PCLATU
and PCLATH are not affected by any of the RETURNor
CALLinstructions.
The STKPTR register contains the stack pointer value,
the STKFUL (Stack Full) status bit and the STKUNF
(Stack Underflow) status bits. Register 4-2 shows the
STKPTR register. The value of the stack pointer can be
0 through 31. The stack pointer increments when val-
ues are pushed onto the stack and decrements when
values are popped off the stack. At Reset, the stack
pointer value will be ‘0’. The user may read and write
the stack pointer value. This feature can be used by a
Real-Time Operating System for return stack
maintenance.
The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, with the stack pointer initialized to
00000b after all Resets. There is no RAM associated
with stack pointer 00000b. This is only a Reset value.
During a CALLtype instruction, causing a push onto the
stack, the stack pointer is first incremented and the
RAM location pointed to by the stack pointer is written
with the contents of the PC. During a RETURN type
instruction, causing a pop from the stack, the contents
of the RAM location pointed to by the STKPTR are
transferred to the PC and then the stack pointer is
decremented.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit can only be cleared in software or
by a POR.
The action that takes place when the stack becomes
full, depends on the state of the STVREN (Stack Over-
flow Reset Enable) configuration bit. Refer to
Section 24.0 “Instruction Set Summary” for a
description of the device configuration bits. If STVREN
is set (default), the 31st push will push the (PC + 2)
value onto the stack, set the STKFUL bit and reset the
device. The STKFUL bit will remain set and the stack
pointer will be set to ‘0’.
The stack space is not part of either program or data
space. The stack pointer is readable and writable and
the address on the top of the stack is readable and writ-
able through SFR registers. Data can also be pushed
to, or popped from the stack using the top-of-stack
SFRs. Status bits indicate if the stack pointer is at, or
beyond the 31 levels provided.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
4.2.1
TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL, hold the
contents of the stack location pointed to by the
STKPTR register. This allows users to implement a
software stack if necessary. After a CALL, RCALL or
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
values can be placed on a user defined software stack.
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at ‘0’. The STKUNF bit will remain set
until cleared in software or a POR occurs.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken.
The user must disable the global interrupt enable bits
during this time to prevent inadvertent stack
operations.
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REGISTER 4-2:
STKPTR REGISTER
R/C-0
R/C-0
U-0
—
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
STKFUL(1) STKUNF(1)
bit 7
bit 0
bit 7
bit 6
STKFUL: Stack Full Flag bit
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit
1= Stack underflow occurred
0= Stack underflow did not occur
bit 5
Unimplemented: Read as ‘0’
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
FIGURE 4-3:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
11111
11110
11101
STKPTR<4:0>
TOSU
0x00
TOSH
0x1A
TOSL
0x34
00010
00011
0x001A34 00010
0x000D58 00001
00000
Top-of-Stack
4.2.3
PUSH AND POP INSTRUCTIONS
4.2.4
STACK FULL/UNDERFLOW RESETS
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program
execution, is a desirable option. To push the current PC
value onto the stack, a PUSH instruction can be
executed. This will increment the stack pointer and load
the current PC value onto the stack. TOSU, TOSH and
TOSL can then be modified to place a return address
on the stack.
These Resets are enabled by programming the
STVREN configuration bit. When the STVREN bit is
disabled, a full or underflow condition will set the
appropriate STKFUL or STKUNF bit, but not cause a
device Reset. When the STVREN bit is enabled, a full
or underflow condition will set the appropriate STKFUL
or STKUNF bit and then cause a device Reset. The
STKFUL or STKUNF bits are only cleared by the user
software or a POR Reset.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POP instruction. The POP
instruction discards the current TOS by decrementing
the stack pointer. The previous value pushed onto the
stack then becomes the TOS value.
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4.3
Fast Register Stack
4.4
PCL, PCLATH and PCLATU
A “fast interrupt return” option is available for interrupts.
A Fast Register Stack is provided for the Status, WREG
and BSR registers and is only one in depth. The stack
is not readable or writable and is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. The values in the
registers are then loaded back into the working regis-
ters, if the FAST RETURNinstruction is used to return
from the interrupt.
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21 bits
wide. The low byte is called the PCL register; this reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<15:8>
bits and is not directly readable or writable; updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits and is not directly
readable or writable; updates to the PCU register may
be performed through the PCLATU register.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the stack register values stored by the low priority
interrupt will be overwritten.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of the PCL is fixed to a value of
‘0’. The PC increments by 2 to address sequential
instructions in the program memory.
If high priority interrupts are not disabled during low
priority interrupts, users must save the key registers in
software during a low priority interrupt.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
If no interrupts are used, the fast register stack can be
used to restore the Status, WREG and BSR registers at
the end of a subroutine call. To use the fast register
stack for a subroutine call, a FAST CALL instruction
must be executed.
The contents of PCLATH and PCLATU will be trans-
ferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the
program counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 4.8.1
“Computed GOTO”).
Example 4-1 shows a source code example that uses
the fast register stack.
EXAMPLE 4-1:
FAST REGISTER STACK
CODE EXAMPLE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
4.5
Clocking Scheme/Instruction
Cycle
CALL SUB1, FAST
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-4.
SUB1
RETURN FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
FIGURE 4-4:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
Phase
Clock
Q4
PC
PC+2
PC+4
PC
OSC2/CLKO
(RC mode)
Execute INST (PC-2)
Fetch INST (PC)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+2)
Fetch INST (PC+4)
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A fetch cycle begins with the program counter (PC)
incrementing in Q1.
4.6
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined, such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 4-2).
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
EXAMPLE 4-2:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed”
from the pipeline, while the new instruction is being fetched and then executed.
word boundaries, the data contained in the instruction
4.7
Instructions in Program Memory
is a word address. The word address is written to
PC<20:1>, which accesses the desired byte address in
program memory. Instruction #2 in Figure 4-5 shows
how the instruction “GOTO 000006h” is encoded in the
program memory. Program branch instructions, which
encode a relative address offset, operate in the same
manner. The offset value stored in a branch instruction
represents the number of single-word instructions that
the PC will be offset by. Section 24.0 “Instruction Set
Summary” provides further details of the instruction
set.
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). Figure 4-5 shows an
example of how instruction words are stored in the pro-
gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ‘0’ (see Section 4.4 “PCL,
PCLATH and PCLATU”).
The CALL and GOTO instructions have an absolute
program memory address embedded into the
instruction. Since instructions are always stored on
FIGURE 4-5:
INSTRUCTIONS IN PROGRAM MEMORY
Word Address
LSB = 1
LSB = 0
Program Memory
Byte Locations
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
Instruction 1: MOVLW
055h
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
Instruction 2: GOTO
000006h
Instruction 3: MOVFF
123h, 456h
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word of the instruction is executed by itself (first word
was skipped), it will execute as a NOP. This action is
necessary when the two-word instruction is preceded
by a conditional instruction that changes the PC. A pro-
gram example that demonstrates this concept is shown
in Example 4-3. Refer to Section 24.0 “Instruction
Set Summary” for further details of the instruction set.
4.7.1
TWO-WORD INSTRUCTIONS
The PIC18FXX20 devices have four two-word instruc-
tions: MOVFF, CALL, GOTOand LFSR. The second word
of these instructions has the 4 MSBs set to ‘1’s and is
a special kind of NOPinstruction. The lower 12 bits of
the second word contain data to be used by the instruc-
tion. If the first word of the instruction is executed, the
data in the second word is accessed. If the second
EXAMPLE 4-3:
CASE 1:
TWO-WORD INSTRUCTIONS
Object Code
Source Code
0110 0110 0000 0000 TSTFSZ
1100 0001 0010 0011 MOVFF
1111 0100 0101 0110
REG1
; is RAM location 0?
REG1, REG2 ; No, execute 2-word instruction
; 2nd operand holds address of REG2
0010 0100 0000 0000 ADDWF
CASE 2:
REG3
; continue code
Object Code
Source Code
0110 0110 0000 0000 TSTFSZ
1100 0001 0010 0011 MOVFF
1111 0100 0101 0110
REG1
; is RAM location 0?
REG1, REG2 ; Yes
; 2nd operand becomes NOP
REG3 ; continue code
0010 0100 0000 0000 ADDWF
4.8.2
TABLE READS/TABLE WRITES
4.8
Look-up Tables
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Look-up tables are implemented two ways. These are:
• Computed GOTO
• Table Reads
Look-up table data may be stored 2 bytes per program
word by using table reads and writes. The Table Pointer
(TBLPTR) specifies the byte address and the Table
Latch (TABLAT) contains the data that is read from, or
written to program memory. Data is transferred to/from
program memory, one byte at a time.
4.8.1
COMPUTED GOTO
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL).
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCLinstruction. The next
instruction executed will be one of the RETLW 0xnn
instructions, that returns the value 0xnnto the calling
function.
A description of the table read/table write operation is
shown in Section 5.0 “Flash Program Memory”.
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
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4.9.1
GENERAL PURPOSE
REGISTER FILE
4.9
Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. The data
memory map is in turn divided into 16 banks of
256 bytes each. The lower 4 bits of the Bank Select
Register (BSR<3:0>) select which bank will be
accessed. The upper 4 bits of the BSR are not
implemented.
The register file can be accessed either directly or indi-
rectly. Indirect addressing operates using a File Select
Register and corresponding Indirect File Operand. The
operation of indirect addressing is shown in
Section 4.12 “Indirect Addressing, INDF and FSR
Registers”.
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
The data memory space contains both Special Func-
tion Registers (SFR) and General Purpose Registers
(GPR). The SFRs are used for control and status of the
controller and peripheral functions, while GPRs are
used for data storage and scratch pad operations in the
user’s application. The SFRs start at the last location of
Bank 15 (0FFFh) and extend downwards. Any remain-
ing space beyond the SFRs in the Bank may be imple-
mented as GPRs. GPRs start at the first location of
Data RAM is available for use as General Purpose
Registers by all instructions. The top section of Bank 15
(F60h to FFFh) contains SFRs. All other banks of data
memory contain GPR registers, starting with Bank 0.
4.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 4-2 and Table 4-3.
Bank
0 and grow upwards. Any read of an
unimplemented location will read as ‘0’s.
PIC18FX520 devices have 2048 bytes of data RAM,
extending from Bank 0 to Bank 7 (000h through 7FFh).
PIC18FX620 and PIC18FX720 devices have
3840 bytes of data RAM, extending from Bank 0 to
Bank 14 (000h through EFFh). The organization of the
data memory space for these devices is shown in
Figure 4-6 and Figure 4-7.
The SFRs can be classified into two sets: those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature. The
SFRs are typically distributed among the peripherals
whose functions they control.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSRn) and a corresponding Indi-
rect File Operand (INDFn). Each FSR holds a 12-bit
address value that can be used to access any location
in the data memory map without banking.
The unused SFR locations are unimplemented and
read as ‘0’s. The addresses for the SFRs are listed in
Table 4-2.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing, or by the use of the MOVFFinstruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 4.10
“Access Bank” provides a detailed description of the
Access RAM.
2003-2013 Microchip Technology Inc.
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FIGURE 4-6:
DATA MEMORY MAP FOR PIC18FX520 DEVICES
BSR<3:0>
Data Memory Map
000h
00h
Access RAM
GPRs
= 0000
05Fh
Bank 0
060h
FFh
00h
0FFh
100h
= 0001
= 0010
= 0011
GPRs
GPRs
Bank 1
Bank 2
FFh
00h
1FFh
200h
FFh
00h
2FFh
300h
Bank 3
to
Bank 6
GPRs
GPRs
= 0110
= 0111
Access Bank
FFh
00h
6FFh
700h
00h
Access RAM Low
5Fh
60h
Bank 7
Access RAM High
(SFRs)
FFh
7FFh
800h
FFh
= 1000
Unused,
Read as ‘0’
Bank 8
to
Bank 14
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 96 bytes are General
Purpose RAM (from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
= 1110
EFFh
F00h
00h
FFh
Unused
SFRs
= 1111
F5Fh
Bank 15
F60h
FFFh
When a = 1,
the BSR is used to specify the
RAM location that the instruction
uses.
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FIGURE 4-7:
DATA MEMORY MAP FOR PIC18FX620 AND PIC18FX720 DEVICES
BSR<3:0>
Data Memory Map
000h
00h
Access RAM
GPRs
= 0000
05Fh
Bank 0
060h
FFh
00h
0FFh
100h
= 0001
= 0010
GPRs
GPRs
Bank 1
Bank 2
Bank 3
FFh
00h
1FFh
200h
FFh
00h
2FFh
300h
= 0011
= 0100
= 0101
GPRs
GPRs
FFh
3FFh
400h
Bank 4
Access Bank
4FFh
500h
00h
Access RAM Low
5Fh
60h
Access RAM High
(SFRs)
FFh
Bank 5
to
Bank 13
GPRs
GPRs
When a = 0,
the BSR is ignored and the
Access Bank is used.
= 1101
= 1110
The first 96 bytes are General
Purpose RAM (from Bank 0).
The second 160 bytes are
Special Function Registers
(from Bank 15).
DFFh
E00h
00h
Bank 14
Bank 15
FFh
00h
EFFh
F00h
Unused
SFRs
= 1111
F5Fh
F60h
FFh
FFFh
When a = 1,
the BSR is used to specify the
RAM location that the instruction
uses.
2003-2013 Microchip Technology Inc.
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TABLE 4-2:
SPECIAL FUNCTION REGISTER MAP
Address
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
Name
TOSU
Address
FDFh
Name
INDF2(3)
Address
FBFh
FBEh
Name
Address
F9Fh
Name
IPR1
PIR1
PIE1
CCPR1H
CCPR1L
TOSH
FDEh POSTINC2(3)
FDDh POSTDEC2(3)
FDCh PREINC2(3)
FDBh PLUSW2(3)
F9Eh
TOSL
FBDh CCP1CON
F9Dh
F9Ch MEMCON(2)
STKPTR
PCLATU
PCLATH
PCL
FBCh
FBBh
CCPR2H
CCPR2L
(1)
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
—
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
FBAh CCP2CON
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
LATJ
FB9h
FB8h
CCPR3H
CCPR3L
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0(3)
FB7h CCP3CON
(1)
FB6h
—
FB5h CVRCON
(1)
—
FB4h
FB3h
FB2h
FB1h
CMCON
TMR3H
TMR3L
T3CON
OSCCON
LVDCON
WDTCON
RCON
FB0h PSPCON
LATH
TMR1H
TMR1L
T1CON
TMR2
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
EEADRH
EEADR
EEDATA
EECON2
EECON1
IPR3
LATG
FEEh POSTINC0(3)
FEDh POSTDEC0(3)
FECh PREINC0(3)
FEBh PLUSW0(3)
LATF
LATE
LATD
PR2
LATC
FEAh
FE9h
FE8h
FE7h
FE6h POSTINC1(3)
FE5h POSTDEC1(3)
FE4h PREINC1(3)
FE3h PLUSW1(3)
FSR0H
FSR0L
WREG
INDF1(3)
T2CON
SSPBUF
SSPADD
SSPSTAT
LATB
LATA
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
FC6h SSPCON1
FC5h SSPCON2
FC4h
FC3h
FC2h
FC1h
FC0h
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PIR3
PIE3
FE2h
FE1h
FE0h
FSR1H
FSR1L
BSR
IPR2
PIR2
PIE2
Note 1: Unimplemented registers are read as ‘0’.
2: This register is unused on PIC18F6X20 devices. Always maintain this register clear.
3: This is not a physical register.
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TABLE 4-2:
SPECIAL FUNCTION REGISTER MAP (CONTINUED)
Address
F7Fh
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F79h
F78h
F77h
F76h
F75h
F74h
Name
Address
F5Fh
Name
Address
F3Fh
Name
Address
F1Fh
Name
(1)
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1)
(1)
—
F5Eh
F5Dh
F5Ch
F5Bh
F5Ah
F59h
F58h
F57h
F56h
F55h
F54h
F53h
F52h
F51h
F50h
F4Fh
F4Eh
F4Dh
F4Ch
F4Bh
F4Ah
F49h
F48h
F47h
F46h
F45h
F44h
F43h
F42h
F41h
F40h
—
F3Eh
F3Dh
F3Ch
F3Bh
F3Ah
F39h
F38h
F37h
F36h
F35h
F34h
F33h
F32h
F31h
F30h
F2Fh
F2Eh
F2Dh
F2Ch
F2Bh
F2Ah
F29h
F28h
F27h
F26h
F25h
F24h
F23h
F22h
F21h
F20h
—
F1Eh
F1Dh
F1Ch
F1Bh
F1Ah
F19h
F18h
F17h
F16h
F15h
F14h
F13h
F12h
F11h
F10h
F0Fh
F0Eh
F0Dh
F0Ch
F0Bh
F0Ah
F09h
F08h
F07h
F06h
F05h
F04h
F03h
F02h
F01h
F00h
—
(1)
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1)
TMR4
PR4
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
T4CON
CCPR4H
CCPR4L
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
F73h CCP4CON
—
—
—
(1)
(1)
(1)
F72h
F71h
CCPR5H
CCPR5L
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
F70h CCP5CON
—
—
—
(1)
(1)
(1)
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
SPBRG2
RCREG2
TXREG2
TXSTA2
RCSTA2
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
—
—
—
(1)
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1)
(1)
—
—
—
—
(1)
(1)
(1)
(1)
—
—
—
—
Note 1: Unimplemented registers are read as ‘0’.
2: This register is not available on PIC18F6X20 devices.
3: This is not a physical register.
2003-2013 Microchip Technology Inc.
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TABLE 4-3:
File Name
TOSU
REGISTER FILE SUMMARY
Value on
POR, BOR on page:
Details
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 32, 42
0000 0000 32, 42
0000 0000 32, 42
00-0 0000 32, 43
--10 0000 32, 44
0000 0000 32, 44
0000 0000 32, 44
--00 0000 32, 64
0000 0000 32, 64
0000 0000 32, 64
0000 0000 32, 64
xxxx xxxx 32, 85
xxxx xxxx 32, 85
0000 0000 32, 89
1111 1111 32, 90
1100 0000 32, 91
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
Return Stack Pointer
bit 21
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
(2)
TBLPTRU
—
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL
TABLAT
PRODH
PRODL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
INTCON
INTCON2
INTCON3
INDF0
GIE/GIEH PEIE/GIEL
TMR0IE
INTEDG1
INT3IE
INT0IE
INTEDG2
INT2IE
RBIE
INTEDG3
INT1IE
TMR0IF
TMR0IP
INT3IF
INT0IF
INT3IP
INT2IF
RBIF
RBIP
RBPU
INTEDG0
INT1IP
INT2IP
INT1IF
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
n/a
n/a
57
57
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented
(not a physical register)
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented
(not a physical register)
n/a
57
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
n/a
n/a
57
57
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented
(not a physical register) – value of FSR0 offset by value in WREG
FSR0H
FSR0L
WREG
INDF1
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
---- 0000 32, 57
xxxx xxxx 32, 57
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
xxxx xxxx
32
57
57
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
n/a
n/a
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented
(not a physical register)
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented
(not a physical register)
n/a
n/a
n/a
57
57
57
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented
(not a physical register)
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented
(not a physical register) – value of FSR1 offset by value in WREG
FSR1H
FSR1L
BSR
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
---- 0000 33, 57
xxxx xxxx 33, 57
---- 0000 33, 56
Indirect Data Memory Address Pointer 1 Low Byte
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
n/a
n/a
57
57
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented
(not a physical register)
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented
(not a physical register)
n/a
57
Legend: x= unknown, u= unchanged, – = unimplemented, q= value depends on condition
Note 1:
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator
modes.
2:
3:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X20 devices; always maintain these clear.
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TABLE 4-3:
REGISTER FILE SUMMARY (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PREINC2
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented
(not a physical register)
n/a
n/a
57
57
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented
(not a physical register) – value of FSR2 offset by value in WREG
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
---- 0000 33, 57
xxxx xxxx 33, 57
---x xxxx 33, 59
0000 0000 33, 133
xxxx xxxx 33, 133
1111 1111 33, 131
---- ---0 25, 33
--00 0101 33, 235
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
STATUS
TMR0H
TMR0L
—
—
—
N
OV
Z
DC
C
Timer0 Register High Byte
Timer0 Register Low Byte
T0CON
OSCCON
LVDCON
WDTCON
RCON
TMR0ON
T08BIT
—
T0CS
—
T0SE
—
PSA
—
T0PS2
—
T0PS1
—
T0PS0
SCS
—
—
—
IRVST
—
LVDEN
—
LVDL3
—
LVDL2
—
LVDL1
—
LVDL0
—
—
SWDTE ---- ---0 33, 250
IPEN
—
—
RI
TO
PD
POR
BOR
0--1 11qq 33, 60,
101
TMR1H
Timer1 Register High Byte
Timer1 Register Low Byte
xxxx xxxx 33, 135
xxxx xxxx 33, 135
TMR1L
T1CON
RD16
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON 0-00 0000 33, 135
0000 0000 33, 141
TMR2
Timer2 Register
PR2
Timer2 Period Register
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON
1111 1111 33, 142
T2CON
—
T2CKPS1 T2CKPS0 -000 0000 33, 141
xxxx xxxx 33, 157
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
SSP Receive Buffer/Transmit Register
2
2
SSP Address Register in I C Slave mode. SSP Baud Rate Reload Register in I C Master mode.
0000 0000 33, 166
0000 0000 33, 158
SMP
WCOL
GCEN
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
SSPOV
ACKSTAT
SSPEN
ACKDT
CKP
SSPM3
RCEN
SSPM1
RSEN
SSPM0 0000 0000 33, 168
ACKEN
SEN
0000 0000 33, 169
xxxx xxxx 34, 215
xxxx xxxx 34, 215
--00 0000 34, 213
A/D Result Register High Byte
A/D Result Register Low Byte
—
—
—
—
—
CHS3
VCFG1
—
CHS2
VCFG0
—
CHS1
PCFG3
—
CHS0
PCFG2
ADCS2
GO/DONE
PCFG1
ADON
PCFG0 --00 0000 34, 214
ADCS0 0--- -000 34, 215
ADFM
ADCS1
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx 34, 151,
152
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx 34, 151,
152
CCP1CON
CCPR2H
—
—
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0 --00 0000 34, 149
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx 34, 151,
152
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx 34, 151,
152
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0 --00 0000 34, 149
Legend: x= unknown, u= unchanged, – = unimplemented, q= value depends on condition
Note 1:
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator
modes.
2:
3:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X20 devices; always maintain these clear.
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TABLE 4-3:
REGISTER FILE SUMMARY (CONTINUED)
Value on
POR, BOR on page:
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CCPR3H
CCPR3L
Capture/Compare/PWM Register 3 High Byte
Capture/Compare/PWM Register 3 Low Byte
xxxx xxxx 34, 151,
152
xxxx xxxx 34, 151,
152
CCP3CON
CVRCON
CMCON
TMR3H
TMR3L
T3CON
PSPCON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
EEADRH
EEADR
EEDATA
EECON2
EECON1
IPR3
—
—
DC3B1
CVRR
C2INV
DC3B0
CVRSS
C1INV
CCP3M3
CVR3
CIS
CCP3M2
CVR2
CCP3M1
CVR1
CCP3M0 --00 0000 34, 149
CVREN
C2OUT
CVROE
C1OUT
CVR0
CM0
0000 0000 34, 229
0000 0000 34, 223
xxxx xxxx 34, 143
xxxx xxxx 34, 143
CM2
CM1
Timer3 Register High Byte
Timer3 Register Low Byte
RD16
IBF
T3CCP2
OBF
T3CKPS1
IBOV
T3CKPS0
T3CCP1
—
T3SYNC
—
TMR3CS
—
TMR3ON 0000 0000 34, 143
PSPMODE
—
0000 ---- 34, 129
0000 0000 34, 205
0000 0000 34, 206
0000 0000 34, 204
0000 -010 34, 198
0000 000x 34, 199
USART1 Baud Rate Generator
USART1 Receive Register
USART1 Transmit Register
CSRC
SPEN
—
TX9
RX9
—
TXEN
SREN
—
SYNC
CREN
—
—
ADDEN
—
BRGH
FERR
—
TRMT
OERR
TX9D
RX9D
EE Adr Register High ---- --00 34, 79
0000 0000 34, 79
Data EEPROM Address Register
Data EEPROM Data Register
0000 0000 34, 79
Data EEPROM Control Register 2 (not a physical register)
---- ---- 34, 79
EEPGD
—
CFGS
—
—
RC2IP
RC2IF
RC2IE
—
FREE
TX2IP
TX2IF
TX2IE
EEIP
WRERR
TMR4IP
TMR4IF
TMR4IE
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
—
WREN
CCP5IP
CCP5IF
CCP5IE
LVDIP
WR
RD
xx-0 x000 34, 80
CCP4IP
CCP4IF
CCP4IE
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
WM1
CCP3IP --11 1111 35, 100
CCP3IF --00 0000 35, 94
CCP3IE --00 0000 35, 97
CCP2IP -1-1 1111 35, 99
CCP2IF -0-0 0000 35, 93
CCP2IE -0-0 0000 35, 96
TMR1IP 0111 1111 35, 98
TMR1IF 0000 0000 35, 92
TMR1IE 0000 0000 35, 95
PIR3
—
—
PIE3
—
—
IPR2
—
CMIP
CMIF
CMIE
ADIP
ADIF
ADIE
—
PIR2
—
—
EEIF
LVDIF
PIE2
—
—
EEIE
LVDIE
IPR1
PSPIP
PSPIF
PSPIE
EBDIS
RCIP
RCIF
RCIE
WAIT1
TXIP
CCP1IP
CCP1IF
CCP1IE
—
PIR1
TXIF
PIE1
TXIE
(3)
MEMCON
WAIT0
WM0
0-00 --00 35, 71
1111 1111 35, 125
1111 1111 35, 122
---1 1111 35, 120
1111 1111 35, 117
1111 1111 35, 114
1111 1111 35, 111
1111 1111 35, 109
1111 1111 35, 106
-111 1111 35, 103
(3)
TRISJ
Data Direction Control Register for PORTJ
Data Direction Control Register for PORTH
(3)
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
—
—
—
Data Direction Control Register for PORTG
Data Direction Control Register for PORTF
Data Direction Control Register for PORTE
Data Direction Control Register for PORTD
Data Direction Control Register for PORTC
Data Direction Control Register for PORTB
(1)
—
TRISA6
Data Direction Control Register for PORTA
Legend: x= unknown, u= unchanged, – = unimplemented, q= value depends on condition
Note 1:
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator
modes.
2:
3:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X20 devices; always maintain these clear.
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TABLE 4-3:
File Name
(3)
REGISTER FILE SUMMARY (CONTINUED)
Value on
POR, BOR on page:
Details
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LATJ
LATH
Read PORTJ Data Latch, Write PORTJ Data Latch
Read PORTH Data Latch, Write PORTH Data Latch
xxxx xxxx 35, 125
xxxx xxxx 35, 122
---x xxxx 35, 120
xxxx xxxx 35, 117
xxxx xxxx 35, 114
xxxx xxxx 35, 111
xxxx xxxx 35, 109
xxxx xxxx 35, 106
-xxx xxxx 35, 103
xxxx xxxx 36, 125
xxxx xxxx 36, 122
---x xxxx 36, 120
xxxx xxxx 36, 117
xxxx xxxx 36, 114
xxxx xxxx 36, 111
xxxx xxxx 36, 109
xxxx xxxx 36, 106
-x0x 0000 36, 103
0000 0000 36, 148
1111 1111 36, 148
(3)
LATG
LATF
LATE
LATD
LATC
LATB
LATA
PORTJ
—
—
—
Read PORTG Data Latch, Write PORTG Data Latch
Read PORTF Data Latch, Write PORTF Data Latch
Read PORTE Data Latch, Write PORTE Data Latch
Read PORTD Data Latch, Write PORTD Data Latch
Read PORTC Data Latch, Write PORTC Data Latch
Read PORTB Data Latch, Write PORTB Data Latch
(1)
(1)
—
LATA6
Read PORTA Data Latch, Write PORTA Data Latch
(3)
(3)
Read PORTJ pins, Write PORTJ Data Latch
Read PORTH pins, Write PORTH Data Latch
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
TMR4
—
—
—
Read PORTG pins, Write PORTG Data Latch
Read PORTF pins, Write PORTF Data Latch
Read PORTE pins, Write PORTE Data Latch
Read PORTD pins, Write PORTD Data Latch
Read PORTC pins, Write PORTC Data Latch
Read PORTB pins, Write PORTB Data Latch
(1)
(1)
—
RA6
Read PORTA pins, Write PORTA Data Latch
Timer4 Register
PR4
Timer4 Period Register
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON
T4CON
CCPR4H
—
T4CKPS1 T4CKPS0 -000 0000 36, 147
Capture/Compare/PWM Register 4 High Byte
xxxx xxxx 36, 151,
152
CCPR4L
Capture/Compare/PWM Register 4 Low Byte
xxxx xxxx 36, 151,
152
CCP4CON
CCPR5H
—
—
DC4B1
DC4B0
CCP4M3
CCP5M3
CCP4M2
CCP5M2
CCP4M1
CCP5M1
CCP4M0 0000 0000 36, 149
Capture/Compare/PWM Register 5 High Byte
xxxx xxxx 36, 151,
152
CCPR5L
Capture/Compare/PWM Register 5 Low Byte
xxxx xxxx 36, 151,
152
CCP5CON
SPBRG2
RCREG2
TXREG2
TXSTA2
—
—
DC5B1
DC5B0
CCP5M0 0000 0000 36, 149
0000 0000 36, 205
USART2 Baud Rate Generator
USART2 Receive Register
USART2 Transmit Register
0000 0000 36, 206
0000 0000 36, 204
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
—
BRGH
FERR
TRMT
OERR
TX9D
RX9D
0000 -010 36, 198
0000 000x 36, 199
RCSTA2
ADDEN
Legend: x= unknown, u= unchanged, – = unimplemented, q= value depends on condition
Note 1:
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator modes only and read ‘0’ in all other oscillator
modes.
2:
3:
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X20 devices; always maintain these clear.
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4.10
Access Bank
4.11 Bank Select Register (BSR)
The Access Bank is an architectural enhancement,
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
This data memory region can be used for:
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ‘0’s and
writes will have no effect.
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
A
MOVLB instruction has been provided in the
instruction set to assist in selecting banks.
• Faster evaluation/control of SFRs (no banking)
If the currently selected bank is not implemented, any
read will return all ‘0’s and all writes are ignored. The
Status register bits will be set/cleared as appropriate for
the instruction performed.
The Access Bank is comprised of the upper 160 bytes
in Bank 15 (SFRs) and the lower 96 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 4-7
indicates the Access RAM areas.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted by the ‘a’ bit (for
access bit).
A MOVFFinstruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 “Indirect Addressing, INDF and FSR
Registers” provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
When forced in the Access Bank (a = 0), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function Registers, so that these registers
can be accessed without any software overhead. This is
useful for testing status flags and modifying control bits.
FIGURE 4-8:
DIRECT ADDRESSING
Direct Addressing
(3)
From Opcode
BSR<3:0>
7
0
(2)
(3)
Bank Select
Location Select
00h
01h
100h
0Eh
E00h
0Fh
F00h
000h
Data
Memory(1)
0FFh
1FFh
EFFh
FFFh
Bank 0
Bank 1
Bank 14 Bank 15
Note 1: For register file map detail, see Table 4-2.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the
registers of the Access Bank.
3: The MOVFFinstruction embeds the entire 12-bit address in the instruction.
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the data from the address pointed to by
FSR1H:FSR1L. INDFn can be used in code anywhere
an operand can be used.
4.12 Indirect Addressing, INDF and
FSR Registers
Indirect addressing is a mode of addressing data mem-
ory, where the data memory address in the instruction
is not fixed. An FSR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 4-9
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address,
specified by the value of the FSR register.
If INDF0, INDF1 or INDF2 are read indirectly via an
FSR, all ‘0’s are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivalent to a NOPinstruction and the
Status bits are not affected.
4.12.1
INDIRECT ADDRESSING
OPERATION
Each FSR register has an INDF register associated
with it, plus four additional register addresses. Perform-
ing an operation on one of these five registers
determines how the FSR will be modified during
indirect addressing.
Indirect addressing is possible by using one of the
INDF registers. Any instruction using the INDF register
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself,
indirectly (FSR = 0), will read 00h. Writing to the INDF
register indirectly, results in a no operation. The FSR
register contains a 12-bit address, which is shown in
Figure 4-10.
When data access is done to one of the five INDFn
locations, the address selected will configure the FSRn
register to:
• Do nothing to FSRn after an indirect access
(no change) – INDFn.
The INDFn register is not a physical register. Address-
ing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer). This is indirect addressing.
• Auto-decrement FSRn after an indirect access
(post-decrement) – POSTDECn.
• Auto-increment FSRn after an indirect access
(post-increment) – POSTINCn.
Example 4-4 shows a simple use of indirect addressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.
• Auto-increment FSRn before an indirect access
(pre-increment) – PREINCn.
• Use the value in the WREG register as an offset
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access
(no change) – PLUSWn.
EXAMPLE 4-4:
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
LFSR FSR0 ,0x100
CLRF POSTINC0
;
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
Status register. For example, if the indirect address
causes the FSR to equal ‘0’, the Z bit will not be set.
NEXT
; Clear INDF
; register and
; inc pointer
; All done with
; Bank 1?
BTFSS FSR0H, 1
GOTO NEXT
Incrementing or decrementing an FSR affects all 12
bits. That is, when FSRnL overflows from an increment,
FSRnH will be incremented automatically.
; NO, clear next
; YES, continue
CONTINUE
Adding these features allows the FSRn to be used as a
stack pointer, in addition to its uses for table operations
in data memory.
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12 bits wide. To store the 12 bits of
addressing information, two 8-bit registers are
required. These indirect addressing registers are:
Each FSR has an address associated with it that
performs an indexed indirect access. When a data
access to this INDFn location (PLUSWn) occurs, the
FSRn is configured to add the signed value in the
WREG register and the value in FSR to form the
address before an indirect access. The FSR value is
not changed.
1. FSR0: composed of FSR0H:FSR0L
2. FSR1: composed of FSR1H:FSR1L
3. FSR2: composed of FSR2H:FSR2L
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register
being the address of the data. If an instruction writes a
value to INDF0, the value will be written to the address
pointed to by FSR0H:FSR0L. A read from INDF1 reads
If an FSR register contains a value that points to one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(Status bits are not affected).
If an indirect addressing operation is done where the tar-
get address is an FSRnH or FSRnL register, the write
operation will dominate over the pre- or post-increment/
decrement functions.
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FIGURE 4-9:
INDIRECT ADDRESSING OPERATION
0h
RAM
Instruction
Executed
Opcode
Address
12
FFFh
File Address = Access of an Indirect Addressing Register
BSR<3:0>
12
12
Instruction
Fetched
4
8
Opcode
FSR
File
FIGURE 4-10:
INDIRECT ADDRESSING
Indirect Addressing
11
FSR Register
0
Location Select
0000h
Data
Memory(1)
0FFFh
Note 1: For register file map detail, see Table 4-2.
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For example, CLRFSTATUSwill clear the upper three
bits and set the Z bit. This leaves the Status register as
4.13 Status Register
The Status register, shown in Register 4-3, contains the
arithmetic status of the ALU. The Status register can be
the destination for any instruction, as with any other reg-
ister. If the Status register is the destination for an
instruction that affects the Z, DC, C, OV or N bits, then
the write to these five bits is disabled. These bits are set
or cleared according to the device logic. Therefore, the
result of an instruction with the Status register as
destination may be different than intended.
000u u1uu(where u= unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFFand MOVWFinstructions are used to alter
the Status register, because these instructions do not
affect the Z, C, DC, OV or N bits from the Status regis-
ter. For other instructions not affecting any status bits,
see Table 24-1.
Note:
The C and DC bits operate as a borrow
and digit borrow bit respectively, in
subtraction.
REGISTER 4-3:
STATUS REGISTER
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
OV
R/W-x
Z
R/W-x
DC
R/W-x
C
N
bit 7
bit 0
bit 7-5
bit 4
Unimplemented: Read as ‘0’
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1= Result was negative
0= Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the
7-bit magnitude, which causes the sign bit (bit 7) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the
2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit
is loaded with either bit 4 or bit 3 of the source register.
bit 0
C: Carry/borrow bit
For ADDWF, ADDLW, SUBLWand SUBWFinstructions:
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the
2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit
is loaded with either the high or low-order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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4.14 RCON Register
Note 1: If the BOREN configuration bit is set
(Brown-out Reset enabled), the BOR bit
is ‘1’ on a Power-on Reset. After a Brown-
out Reset has occurred, the BOR bit will
be cleared and must be set by firmware to
indicate the occurrence of the next
Brown-out Reset.
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device Reset. These flags include the TO, PD, POR,
BOR and RI bits. This register is readable and writable.
2: It is recommended that the POR bit be set
after
a Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.
REGISTER 4-4:
RCON REGISTER
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5 Unimplemented: Read as ‘0’
bit 4
RI: RESETInstruction Flag bit
1= The RESETinstruction was not executed
0= The RESETinstruction was executed causing a device Reset
(must be set in software after a Brown-out Reset occurs)
bit 3
bit 2
bit 1
bit 0
TO: Watchdog Time-out Flag bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down Detection Flag bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= A Power-on Reset has not occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= A Brown-out Reset has not occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
5.0
FLASH PROGRAM MEMORY
The Flash program memory is readable, writable and
erasable, during normal operation over the entire VDD
range.
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Table read operations retrieve data from program mem-
ory and place it into the data RAM space. Figure 5-1
shows the operation of a table read with program
memory and data RAM.
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 8 bytes at a time. Program memory is erased
in blocks of 64 bytes at a time. A bulk erase operation
may not be issued from user code.
Table write operations store data from the data memory
space into holding registers in program memory. The
procedure to write the contents of the holding registers
into program memory is detailed in Section 5.5
“Writing to Flash Program Memory”. Figure 5-2
shows the operation of a table write with program
memory and data RAM.
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word aligned. Therefore, a table block
can start and end at any byte address. If a table write is
being used to write executable code into program
memory, program instructions will need to be word
aligned.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
5.1
Table Reads and Table Writes
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data
RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
FIGURE 5-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer points to a byte in program memory.
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FIGURE 5-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
Holding Registers
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by
TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in
Section 5.5 “Writing to Flash Program Memory”.
The FREE bit, when set, will allow a program memory
erase operation. When the FREE bit is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
5.2
Control Registers
Several control registers are used in conjunction with
the TBLRDand TBLWTinstructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal opera-
tion. In these situations, the user can check the
WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EEADR), due to Reset values of zero.
5.2.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
The WR control bit, initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation. The
inability to clear the WR bit in software prevents the
Control bit EEPGD determines if the access will be a
program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.
accidental or premature termination of
operation.
a write
Note:
Interrupt flag bit, EEIF in the PIR2 register,
is set when the write is complete. It must
be cleared in software.
Control bit CFGS determines if the access will be to the
configuration/calibration registers, or to program
memory/data EEPROM memory. When set, subse-
quent operations will operate on configuration regis-
ters, regardless of EEPGD (see Section 23.0 “Special
Features of the CPU”). When clear, memory selection
access is determined by EEPGD.
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REGISTER 5-1:
EECON1 REGISTER (ADDRESS FA6h)
R/W-x
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
EEPGD
WRERR
bit 7
bit 0
bit 7
bit 6
EEPGD: Flash Program or Data EEPROM Memory Select bit
1= Access Flash program memory
0= Access data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1= Access configuration registers
0= Access Flash program or data EEPROM memory
bit 5
bit 4
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0= Perform write only
bit 3
WRERR: Flash Program/Data EEPROM Error Flag bit
1= A write operation is prematurely terminated
(any Reset during self-timed programming in normal operation)
0= The write operation completed
Note:
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
bit 2
bit 1
WREN: Flash Program/Data EEPROM Write Enable bit
1= Allows write cycles to Flash program/data EEPROM
0= Inhibits write cycles to Flash program/data EEPROM
WR: Write Control bit
1= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write
cycle. (The operation is self-timed and the bit is cleared by hardware once write is
complete. The WR bit can only be set (not cleared) in software.)
0= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit
can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)
0= Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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5.2.2
TABLAT – TABLE LATCH REGISTER
5.2.4
TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program
memory and data RAM.
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the Table
Pointer determine which byte is read from program
memory into TABLAT.
5.2.3
TBLPTR – TABLE POINTER
REGISTER
When a TBLWTis executed, the three LSbs of the Table
Pointer (TBLPTR<2:0>) determine which of the eight
program memory holding registers is written to. When
the timed write to program memory (long write) begins,
the 19 MSbs of the Table Pointer, TBLPTR
(TBLPTR<21:3>), will determine which program mem-
ory block of 8 bytes is written to. For more detail, see
Section 5.5 “Writing to Flash Program Memory”.
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order 21
bits allow the device to address up to 2 Mbytes of
program memory space. The 22nd bit allows access to
the Device ID, the User ID and the configuration bits.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer (TBLPTR<21:6>) point to
the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
The Table Pointer, TBLPTR, is used by the TBLRDand
TBLWTinstructions. These instructions can update the
TBLPTR in one of four ways, based on the table oper-
ation. These operations are shown in Table 5-1. These
operations on the TBLPTR only affect the low-order
21 bits.
Figure 5-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 5-1:
Example
TBLRD*
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer
TBLPTR is not modified
TBLWT*
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
FIGURE 5-3:
TABLE POINTER BOUNDARIES BASED ON OPERATION
21
16 15
TBLPTRH
8
7
TBLPTRL
0
TBLPTRU
ERASE – TBLPTR<20:6>
WRITE – TBLPTR<21:3>
READ – TBLPTR<21:0>
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TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
5.3
Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and places it into data RAM. Table
reads from program memory are performed one byte at
a time.
automatically for the next table read operation.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 5-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 5-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Instruction Register
TABLAT
Read Register
FETCH
TBLRD
(IR)
EXAMPLE 5-1:
READING A FLASH PROGRAM MEMORY WORD
MOVLW
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; Load TBLPTR with the base
; address of the word
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
READ_WORD
TBLRD*+
MOVF
MOVWF
; read into TABLAT and increment
; get data
TABLAT, W
WORD_EVEN
TBLRD*+
MOVFW
MOVWF
; read into TABLAT and increment
; get data
TABLAT, W
WORD_ODD
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5.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
5.4
Erasing Flash Program Memory
The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP control, can larger blocks of program memory be
bulk erased. Word erase in the Flash array is not
supported.
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer with address of row being
erased.
When initiating an erase sequence from the micro-
controller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.
2. Set the EECON1 register for the erase
operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program
memory;
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash pro-
gram memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable interrupts.
4. Write 55h to EECON2.
5. Write AAh to EECON2.
For protection, the write initiate sequence for EECON2
must be used.
6. Set the WR bit. This will begin the row erase
cycle.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
8. Execute a NOP.
9. Re-enable interrupts.
EXAMPLE 5-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
ERASE_ROW
BSF
BCF
BSF
BSF
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
; point to Flash program memory
; access Flash program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
; write 55H
Required
Sequence
; write AAH
; start erase (CPU stall)
NOP
BSF
INTCON, GIE
; re-enable interrupts
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the holding registers are written. At the end of updating
8 registers, the EECON1 register must be written to, to
start the programming operation with a long write.
5.5
Writing to Flash Program Memory
The minimum programming block is 4 words or 8 bytes.
Word or byte programming is not supported.
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.
Table writes are used internally to load the holding reg-
isters needed to program the Flash memory. There are
8 holding registers used by the table writes for
programming.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device for byte or word operations.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction has to be executed 8 times for
each programming operation. All of the table write
operations will essentially be short writes, because only
FIGURE 5-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT
Write Register
8
8
8
8
TBLPTR = xxxxx0
TBLPTR = xxxxx1
TBLPTR = xxxxx2
TBLPTR = xxxxx7
Holding Register
Holding Register
Holding Register
Holding Register
Program Memory
9. Write 55h to EECON2.
10. Write AAh to EECON2.
5.5.1
FLASH PROGRAM MEMORY
WRITE SEQUENCE
11. Set the WR bit. This will begin the write cycle.
The sequence of events for programming an internal
program memory location should be:
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
1. Read 64 bytes into RAM.
13. Execute a NOP.
2. Update data values in RAM as necessary.
3. Load Table Pointer with address being erased.
4. Do the row erase procedure.
14. Re-enable interrupts.
15. Repeat steps 6-14 seven times, to write
64 bytes.
5. Load Table Pointer with address of first byte
being written.
16. Verify the memory (table read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 5-3.
6. Write the first 8 bytes into the holding registers
with auto-increment.
7. Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the eight bytes
in the holding register.
• clear the CFGS bit to access program
memory
• set WREN to enable byte writes
8. Disable interrupts.
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EXAMPLE 5-3:
WRITING TO FLASH PROGRAM MEMORY
MOVLW
D’64
; number of bytes in erase block
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
COUNTER
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; point to buffer
; Load TBLPTR with the base
; address of the memory block
READ_BLOCK
TBLRD*+
MOVF
MOVWF
; read into TABLAT, and inc
; get data
; store data
; done?
TABLAT, W
POSTINC0
DECFSZ COUNTER
BRA
READ_BLOCK
; repeat
MODIFY_WORD
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
DATA_ADDR_HIGH
FSR0H
DATA_ADDR_LOW
FSR0L
NEW_DATA_LOW
POSTINC0
NEW_DATA_HIGH
INDF0
; point to buffer
; update buffer word
ERASE_BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BCF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
; load TBLPTR with the base
; address of the memory block
; point to Flash program memory
; access Flash program memory
; enable write to memory
; enable Row Erase operation
; disable interrupts
EECON2
AAh
EECON2
EECON1, WR
; write 55H
Required
Sequence
; write AAH
; start erase (CPU stall)
NOP
BSF
TBLRD*-
INTCON, GIE
; re-enable interrupts
; dummy read decrement
WRITE_BUFFER_BACK
MOVLW
8
; number of write buffer groups of 8 bytes
; point to buffer
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
COUNTER_HI
BUFFER_ADDR_HIGH
FSR0H
BUFFER_ADDR_LOW
FSR0L
PROGRAM_LOOP
MOVLW
MOVWF
8
; number of bytes in holding register
COUNTER
WRITE_WORD_TO_HREGS
MOVFF
POSTINC0, WREG
; get low byte of buffer data
; present data to table latch
; write data, perform a short write
; to internal TBLWT holding register.
; loop until buffers are full
TBLWT+*
DECFSZ COUNTER
BRA WRITE_WORD_TO_HREGS
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EXAMPLE 5-3:
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
PROGRAM_MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
; write 55H
Required
Sequence
; write AAH
; start program (CPU stall)
NOP
BSF
INTCON, GIE
; re-enable interrupts
; loop until done
DECFSZ COUNTER_HI
BRA
BCF
PROGRAM_LOOP
EECON1, WREN
; disable write to memory
5.5.2
WRITE VERIFY
5.5.4
PROTECTION AGAINST
SPURIOUS WRITES
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 23.0 “Special Features of the
CPU” for more detail.
5.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
5.6
Flash Program Operation During
Code Protection
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. The WRERR bit is set when a
write operation is interrupted by a MCLR Reset, or a
WDT Time-out Reset during normal operation. In these
situations, users can check the WRERR bit and rewrite
the location.
See Section 23.0 “Special Features of the CPU” for
details on code protection of Flash program memory.
TABLE 5-2:
Name
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Value on
Value on
POR, BOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
--00 0000 --00 0000
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
TABLAT
INTCON
EECON2
EECON1
IPR2
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
RD
EEPROM Control Register 2 (not a physical register)
—
—
EEPGD
CFGS
CMIP
CMIF
CMIE
—
—
—
—
FREE
EEIP
EEIF
EEIE
WRERR WREN
WR
xx-0 x000 uu-0 u000
—
—
—
BCLIP
BCLIF
BCLIE
LVDIP
LVDIF
LVDIE
TMR3IP
TMR3IF
TMR3IE
CCP2IP ---1 1111 ---1 1111
CCP2IF ---0 0000 ---0 0000
PIR2
PIE2
CCP2IE ---0 0000 ---0 0000
Legend:
x= unknown, u= unchanged, r= reserved, - = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
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NOTES:
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6.1
Program Memory Modes and the
External Memory Interface
6.0
EXTERNAL MEMORY
INTERFACE
As previously noted, PIC18F8X20 controllers are
capable of operating in any one of four program
memory modes, using combinations of on-chip and
external program memory. The functions of the multi-
plexed port pins depend on the program memory
mode selected, as well as the setting of the EBDIS bit.
Note: The External Memory Interface is not
implemented on PIC18F6X20 (64-pin)
devices.
The External Memory Interface is a feature of the
PIC18F8X20 devices that allows the controller to
access external memory devices (such as Flash,
EPROM, SRAM, etc.) as program or data memory.
In Microprocessor Mode, the external bus is always
active and the port pins have only the external bus
function.
The physical implementation of the interface uses 27
pins. These pins are reserved for external address/data
bus functions; they are multiplexed with I/O port pins on
four ports. Three I/O ports are multiplexed with the
address/data bus, while the fourth port is multiplexed
with the bus control signals. The I/O port functions are
enabled when the EBDIS bit in the MEMCON register
is set (see Register 6-1). A list of the multiplexed pins
and their functions is provided in Table 6-1.
In Microcontroller Mode, the bus is not active and
the pins have their port functions only. Writes to the
MEMCOM register are not permitted.
In Microprocessor with Boot Block or Extended
Microcontroller Mode, the external program memory
bus shares I/O port functions on the pins. When the
device is fetching or doing table read/table write
operations on the external program memory space, the
pins will have the external bus function. If the device is
fetching and accessing internal program memory loca-
tions only, the EBDIS control bit will change the pins
from external memory to I/O port functions. When
EBDIS = 0, the pins function as the external bus.
When EBDIS = 1, the pins function as I/O ports.
As implemented in the PIC18F8X20 devices, the
interface operates in a similar manner to the external
memory interface introduced on PIC18C601/801
microcontrollers. The most notable difference is that
the interface on PIC18F8X20 devices only operates in
16-bit modes. The 8-bit mode is not supported.
For a more complete discussion of the operating modes
that use the external memory interface, refer to
Section 4.1.1 “PIC18F8X20 Program Memory
Modes”.
Note:
Maximum FOSC for the PIC18FX520 is
limited to 25 MHz when using the external
memory interface.
REGISTER 6-1:
MEMCON REGISTER
R/W-0
EBDIS
U-0
—
R/W-0
WAIT1
R/W-0
WAIT0
U-0
—
U-0
—
R/W-0
WM1
R/W-0
WM0
bit7
bit0
bit 7
EBDIS: External Bus Disable bit
1= External system bus disabled, all external bus drivers are mapped as I/O ports
0= External system bus enabled and I/O ports are disabled
bit 6
Unimplemented: Read as ‘0’
bit 5-4
WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits
11= Table reads and writes will wait 0 TCY
10= Table reads and writes will wait 1 TCY
01= Table reads and writes will wait 2 TCY
00= Table reads and writes will wait 3 TCY
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
WM<1:0>: TBLWRTOperation with 16-bit Bus bits
1x= Word Write mode: TABLAT<0> and TABLAT<1> word output, WRH active when
TABLAT<1> written
01= Byte Select mode: TABLAT data copied on both MSB and LSB, WRH and (UB or LB)
will activate
00= Byte Write mode: TABLAT data copied on both MSB and LSB, WRH or WRL will activate
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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If the device fetches or accesses external memory
while EBDIS = 1, the pins will switch to external bus. If
the EBDIS bit is set by a program executing from
external memory, the action of setting the bit will be
delayed until the program branches into the internal
memory. At that time, the pins will change from
external bus to I/O ports.
When the device is executing out of internal memory
(EBDIS = 0) in Microprocessor with Boot Block mode,
or Extended Microcontroller mode, the control signals
will NOT be active. They will go to a state where the
AD<15:0> and A<19:16> are tri-state; the CE, OE,
WRH, WRL, UB and LB signals are ‘1’ and ALE and
BA0 are ‘0’.
TABLE 6-1:
Name
PIC18F8X20 EXTERNAL BUS – I/O PORT FUNCTIONS
Port
Bit
Function
RD0/AD0
RD1/AD1
RD2/AD2
RD3/AD3
RD4/AD4
RD5/AD5
RD6/AD6
RD7/AD7
RE0/AD8
RE1/AD9
RE2/AD10
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE7/AD15
RH0/A16
RH1/A17
RH2/A18
RH3/A19
RJ0/ALE
RJ1/OE
PORTD
PORTD
PORTD
PORTD
PORTD
PORTD
PORTD
PORTD
PORTE
PORTE
PORTE
PORTE
PORTE
PORTE
PORTE
PORTE
PORTH
PORTH
PORTH
PORTH
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
PORTJ
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 0
bit 1
bit 2
bit 3
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Input/Output or System Bus Address bit 0 or Data bit 0.
Input/Output or System Bus Address bit 1 or Data bit 1.
Input/Output or System Bus Address bit 2 or Data bit 2.
Input/Output or System Bus Address bit 3 or Data bit 3.
Input/Output or System Bus Address bit 4 or Data bit 4.
Input/Output or System Bus Address bit 5 or Data bit 5.
Input/Output or System Bus Address bit 6 or Data bit 6.
Input/Output or System Bus Address bit 7 or Data bit 7.
Input/Output or System Bus Address bit 8 or Data bit 8.
Input/Output or System Bus Address bit 9 or Data bit 9.
Input/Output or System Bus Address bit 10 or Data bit 10.
Input/Output or System Bus Address bit 11 or Data bit 11.
Input/Output or System Bus Address bit 12 or Data bit 12.
Input/Output or System Bus Address bit 13 or Data bit 13.
Input/Output or System Bus Address bit 14 or Data bit 14.
Input/Output or System Bus Address bit 15 or Data bit 15.
Input/Output or System Bus Address bit 16.
Input/Output or System Bus Address bit 17.
Input/Output or System Bus Address bit 18.
Input/Output or System Bus Address bit 19.
Input/Output or System Bus Address Latch Enable (ALE) Control pin.
Input/Output or System Bus Output Enable (OE) Control pin.
Input/Output or System Bus Write Low (WRL) Control pin.
Input/Output or System Bus Write High (WRH) Control pin.
Input/Output or System Bus Byte Address bit 0.
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
Input/Output or System Bus Chip Enable (CE) Control pin.
Input/Output or System Bus Lower Byte Enable (LB) Control pin.
Input/Output or System Bus Upper Byte Enable (UB) Control pin.
RJ6/LB
RJ7/UB
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In Byte Select mode, JEDEC standard Flash memories
6.2
16-bit Mode
will require BA0 for the byte address line and one I/O
line to select between Byte and Word mode. The other
16-bit modes do not need BA0. JEDEC standard static
RAM memories will use the UB or LB signals for byte
selection.
The External Memory Interface implemented in
PIC18F8X20 devices operates only in 16-bit mode.
The mode selection is not software configurable, but is
programmed via the configuration bits.
The WM<1:0> bits in the MEMCON register determine
three types of connections in 16-bit mode. They are
referred to as:
6.2.1
16-BIT BYTE WRITE MODE
Figure 6-1 shows an example of 16-bit Byte Write
mode for PIC18F8X20 devices. This mode is used for
two separate 8-bit memories connected for 16-bit oper-
ation. This generally includes basic EPROM and Flash
devices. It allows table writes to byte-wide external
memories.
• 16-bit Byte Write
• 16-bit Word Write
• 16-bit Byte Select
These three different configurations allow the designer
maximum flexibility in using 8-bit and 16-bit memory
devices.
During a TBLWTinstruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
For all 16-bit modes, the Address Latch Enable (ALE)
pin indicates that the address bits A<15:0> are
available on the External Memory Interface bus.
Following the address latch, the Output Enable signal
(OE) will enable both bytes of program memory at once
to form a 16-bit instruction word. The Chip Enable
signal (CE) is active at any time that the microcontroller
accesses external memory, whether reading or writing;
it is inactive (asserted high) whenever the device is in
Sleep mode.
FIGURE 6-1:
16-BIT BYTE WRITE MODE EXAMPLE
D<7:0>
(MSB)
A<x:0>
(LSB)
PIC18F8X20
A<19:0>
D<15:8>
AD<7:0>
373
373
A<x:0>
D<7:0>
D<7:0>
CE
D<7:0>
CE
AD<15:8>
ALE
(1)
(1)
OE WR
OE WR
A<19:16>
CE
OE
WRH
WRL
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.
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During
a
TBLWT cycle to an odd address
6.2.2
16-BIT WORD WRITE MODE
(TBLPTR<0> = 1), the TABLAT data is presented on
the upper byte of the AD15:AD0 bus. The contents of
the holding latch are presented on the lower byte of the
AD15:AD0 bus.
Figure 6-2 shows an example of 16-bit Word Write
mode for PIC18F8X20 devices. This mode is used for
word-wide memories, which includes some of the
EPROM and Flash type memories. This mode allows
opcode fetches and table reads from all forms of 16-bit
memory and table writes to any type of word-wide
external memories. This method makes a distinction
between TBLWTcycles to even or odd addresses.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the LSb of TBLPTR, but it is left unconnected. Instead,
the UB and LB signals are active to select both bytes.
The obvious limitation to this method is that the table
write must be done in pairs on a specific word boundary
to correctly write a word location.
During
a
TBLWT cycle to an even address
(TBLPTR<0> = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is
tri-stated for the data portion of the bus cycle. No write
signals are activated.
FIGURE 6-2:
16-BIT WORD WRITE MODE EXAMPLE
PIC18F8X20
AD<7:0>
A<20:1>
D<15:0>
JEDEC Word
EPROM Memory
373
373
A<x:0>
D<15:0>
CE
(1)
OE
WR
AD<15:8>
ALE
A<19:16>
CE
OE
WRH
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.
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Flash and SRAM devices use different control signal
combinations to implement Byte Select mode. JEDEC
standard Flash memories require that a controller I/O
port pin be connected to the memory’s BYTE/WORD
pin to provide the select signal. They also use the BA0
signal from the controller as a byte address. JEDEC
standard static RAM memories, on the other hand, use
the UB or LB signals to select the byte.
6.2.3
16-BIT BYTE SELECT MODE
Figure 6-3 shows an example of 16-bit Byte Select
mode for PIC18F8X20 devices. This mode allows table
write operations to word-wide external memories with
byte selection capability. This generally includes both
word-wide Flash and SRAM devices.
During a TBLWTcycle, the TABLAT data is presented
on the upper and lower byte of the AD15:AD0 bus. The
WRH signal is strobed for each write cycle; the WRL
pin is not used. The BA0 or UB/LB signals are used to
select the byte to be written, based on the Least
Significant bit of the TBLPTR register.
FIGURE 6-3:
16-BIT BYTE SELECT MODE EXAMPLE
PIC18F8X20
A<20:1>
AD<7:0>
373
373
JEDEC Word
Flash Memory
A<x:1>
D<15:0>
D<15:0>
138
CE
A0
AD<15:8>
(1)
ALE
A<19:16>
OE
BYTE/WORD OE WR
WRH
A<20:1>
WRL
JEDEC Word
A<x:1>
SRAM Memory
BA0
I/O
D<15:0>
D<15:0>
CE
LB
LB
(1)
UB
OE WR
UB
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”.
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6.2.4
16-BIT MODE TIMING
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 6-4 through Figure 6-6.
FIGURE 6-4:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE)
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q4
Q1
Q4
Q2
Q4
Q3
Q4
Q4
Apparent Q
Actual Q
00h
0Ch
A<19:16>
3AABh
0E55h
9256h
AD<15:0>
CF33h
BA0
ALE
OE
WRH
‘1’
‘1’
WRL
CE
‘1’
‘0’
‘1’
‘0’
1 TCY Wait
Memory
Cycle
Opcode Fetch
MOVLW55h
Table Read
of 92h
from 007556h
from 199E67h
Instruction
Execution
TBLRDCycle 1
TBLRDCycle 2
FIGURE 6-5:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED
MICROCONTROLLER MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
0Ch
A<19:16>
CF33h
9256h
AD<15:0>
CE
ALE
OE
Opcode Fetch
TBLRD *
from 000100h
Opcode Fetch
MOVLW55h
from 000102h
TBLRD92h
from 199E67h
Opcode Fetch
ADDLW55h
from 000104h
Memory
Cycle
Instruction
Execution
INST(PC-2)
TBLRDCycle 1
TBLRDCycle 2
MOVLW
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FIGURE 6-6:
EXTERNAL MEMORY BUS TIMING FOR SLEEP (MICROPROCESSOR MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
00h
00h
A<19:16>
AD<15:0>
0E55h
0003h
3AAAh
3AABh
CE
ALE
OE
Memory
Cycle
Opcode Fetch
MOVLW55h
Opcode Fetch
SLEEP
Sleep Mode, Bus Inactive
from 007554h
from 007556h
Instruction
Execution
INST(PC-2)
SLEEP
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NOTES:
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7.1
EEADR and EEADRH
7.0
DATA EEPROM MEMORY
The address register pair can address up to a maxi-
mum of 1024 bytes of data EEPROM. The two Most
Significant bits of the address are stored in EEADRH,
while the remaining eight Least Significant bits are
stored in EEADR. The six Most Significant bits of
EEADRH are unused and are read as ‘0’.
The data EEPROM is readable and writable during
normal operation over the entire VDD range. The data
memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the
Special Function Registers (SFR).
There are five SFRs used to read and write the
program and data EEPROM memory. These registers
are:
7.2
EECON1 and EECON2 Registers
• EECON1
• EECON2
• EEDATA
• EEADRH
• EEADR
EECON1 is the control register for EEPROM memory
accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the EEPROM write sequence.
Control bits, RD and WR, initiate read and write opera-
tions, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at the
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
or premature termination of a write operation.
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write. EEADR and
EEADRH hold the address of the EEPROM location
being accessed. These devices have 1024 bytes of
data EEPROM with an address range from 00h to
3FFh.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset or a WDT Time-out Reset during normal opera-
tion. In these situations, the user can check the
WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EEADR) due to the Reset condition forcing the
contents of the registers to zero.
The EEPROM data memory is rated for high erase/
write cycles. A byte write automatically erases the loca-
tion and writes the new data (erase-before-write). The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature, as well as
from chip to chip. Please refer to parameter D122 (see
Section 26.0 “Electrical Characteristics”) for exact
limits.
Note:
Interrupt flag bit, EEIF in the PIR2 register,
is set when write is complete. It must be
cleared in software.
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REGISTER 7-1:
EECON1 REGISTER (ADDRESS FA6h)
R/W-x
R/W-x
CFGS
U-0
—
R/W-0
FREE
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
EEPGD
WRERR
bit 7
bit 0
bit 7
bit 6
EEPGD: Flash Program/Data EEPROM Memory Select bit
1= Access Flash program memory
0= Access data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1= Access configuration or calibration registers
0= Access Flash program or data EEPROM memory
bit 5
bit 4
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1= Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0= Perform write only
bit 3
WRERR: Flash Program/Data EEPROM Error Flag bit
1= A write operation is prematurely terminated
(any MCLR or any WDT Reset during self-timed programming in normal operation)
0= The write operation completed
Note:
When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows
tracing of the error condition.
bit 2
bit 1
WREN: Flash Program/Data EEPROM Write Enable bit
1= Allows write cycles to Flash program/data EEPROM
0= Inhibits write cycles to Flash program/data EEPROM
WR: Write Control bit
1= Initiates a data EEPROM erase/write cycle, or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0= Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD bit
can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)
0= Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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control bit (EECON1<6>) and then set the RD control
bit (EECON1<0>). The data is available for the very
next instruction cycle; therefore, the EEDATA register
7.3
Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADRH:EEADR register pair, clear the
EEPGD control bit (EECON1<7>), clear the CFGS
can be read by the next instruction. EEDATA will hold
this value until another read operation, or until it is
written to by the user (during a write operation).
EXAMPLE 7-1:
DATA EEPROM READ
MOVLW
MOVWF
MOVLW
MOVWF
BCF
DATA_EE_ADDRH
EEADRH
DATA_EE_ADDR
EEADR
EECON1, EEPGD ; Point to DATA memory
;
; Upper bits of Data Memory Address to read
;
; Lower bits of Data Memory Address to read
BCF
BSF
MOVF
EECON1, CFGS
EECON1, RD
EEDATA, W
; Access EEPROM
; EEPROM Read
; W = EEDATA
should be kept clear at all times, except when updating
the EEPROM. The WREN bit is not cleared
by hardware
7.4
Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADRH:EEADR register pair
and the data written to the EEDATA register. Then the
sequence in Example 7-2 must be followed to initiate
the write cycle.
After a write sequence has been initiated, EECON1,
EEADRH, EEADR and EEDATA cannot be modified.
The WR bit will be inhibited from being set unless the
WREN bit is set. Both WR and WREN cannot be set
with the same instruction.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. The user may either
enable this interrupt, or poll this bit. EEIF must be
cleared by software.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
execution (i.e., runaway programs). The WREN bit
EXAMPLE 7-2:
DATA EEPROM WRITE
MOVLW
DATA_EE_ADDRH
EEADRH
DATA_EE_ADDR
EEADR
DATA_EE_DATA
EEDATA
EECON1,EEPGD
EECON1,CFGS
EECON1,WREN
;
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
; Upper bits of Data Memory Address to write
;
; Lower bits of Data Memory Address to write
;
; Data Memory Value to write
; Point to DATA memory
; Access EEPROM
BCF
BSF
; Enable writes
BCF
INTCON,GIE
55h
EECON2
AAh
EECON2
; Disable Interrupts
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Enable Interrupts
MOVLW
MOVWF
MOVLW
MOVWF
BSF
Required
Sequence
EECON1,WR
INTCON,GIE
BSF
; User code execution
BCF
EECON1,WREN
; Disable writes on write complete (EEIF set)
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7.5
Write Verify
7.8
Using the Data EEPROM
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
The data EEPROM is a high endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program vari-
ables or other data that are updated often). Frequently
changing values will typically be updated more often
than specification D124. If this is not the case, an array
refresh must be performed. For this reason, variables
that change infrequently (such as constants, IDs,
calibration, etc.) should be stored in Flash program
memory.
7.6
Protection Against Spurious Write
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
A simple data EEPROM refresh routine is shown in
Example 7-3.
Note:
If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
7.7
Operation During Code-Protect
Data EEPROM memory has its own code-protect
mechanism. External read and write operations are
disabled if either of these mechanisms are enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect configuration bit. Refer to Section 23.0
“Special Features of the CPU” for additional
information.
EXAMPLE 7-3:
DATA EEPROM REFRESH ROUTINE
CLRF
CLRF
BCF
BCF
BCF
EEADR
EEADRH
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
; Start at address 0
;
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; Wait for write to complete
BSF
Loop
BSF
EECON1, RD
55h
EECON2
AAh
EECON2
EECON1, WR
EECON1, WR
$-2
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ EEADR, F
; Increment address
BRA
Loop
; Not zero, do it again
; Increment the high address
; Not zero, do it again
INCFSZ EEADRH, F
BRA
Loop
BCF
BSF
EECON1, WREN
INTCON, GIE
; Disable writes
; Enable interrupts
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TABLE 7-1:
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
INTCON
EEADRH
EEADR
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
—
TMR0IF
—
INT0IF
RBIF
0000 0000 0000 0000
—
—
—
—
EE Addr Register High ---- --00 ---- --00
0000 0000 0000 0000
EEPROM Address Register
EEPROM Data Register
EEDATA
0000 0000 0000 0000
EECON2 EEPROM Control Register 2 (not a physical register)
---- ---- ---- ----
EECON1
IPR2
EEPGD
CFGS
CMIP
CMIF
CMIE
—
—
—
—
FREE WRERR WREN
WR
RD
xx-0 x000 uu-0 u000
---1 1111 ---1 1111
---0 0000 ---0 0000
---0 0000 ---0 0000
—
—
—
EEIP
EEIF
EEIE
BCLIP
BCLIF
BCLIE
LVDIP
LVDIF
LVDIE
TMR3IP
TMR3IF
TMR3IE
CCP2IP
CCP2IF
CCP2IE
PIR2
PIE2
Legend:
x= unknown, u= unchanged, r= reserved, – = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
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8.2
Operation
8.0
8.1
8 X 8 HARDWARE MULTIPLIER
Introduction
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18FXX20 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored in the 16-bit product register
pair (PRODH:PRODL). The multiplier does not affect
any flags in the ALUSTA register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 8-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
MOVF
MULWF
ARG1, W
ARG2
;
• Higher computational throughput
; ARG1 * ARG2 ->
; PRODH:PRODL
• Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
EXAMPLE 8-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
MOVF
MULWF
ARG1, W
ARG2
;
Table 8-1 shows a performance comparison between
enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
BTFSC
SUBWF
ARG2, SB
PRODH, F
;
;
- ARG1
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
TABLE 8-1:
Routine
PERFORMANCE COMPARISON
Program
Time
Cycles
(Max)
Multiply Method
Memory
(Words)
@ 40 MHz @ 10 MHz @ 4 MHz
Without hardware multiply
Hardware multiply
13
1
69
1
6.9 s
100 ns
9.1 s
600 ns
24.2 s
2.8 s
25.4 s
4.0 s
27.6 s
400 ns
36.4 s
2.4 s
69 s
1 s
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
91 s
6 s
Without hardware multiply
Hardware multiply
21
28
52
35
242
28
254
40
96.8 s
11.2 s
102.6 s
16.0 s
242 s
28 s
254 s
40 s
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
2003-2013 Microchip Technology Inc.
DS39609C-page 85
PIC18F6520/8520/6620/8620/6720/8720
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 8-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 8-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
=
=
ARG1H:ARG1L ARG2H:ARG2L
16
EQUATION 8-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
(ARG1H ARG2H 2 ) +
8
(ARG1H ARG2L 2 ) +
8
(ARG1L ARG2H 2 ) +
(ARG1L ARG2L) +
(-1 ARG2H<7> ARG1H:ARG1L 2 ) +
(-1 ARG1H<7> ARG2H:ARG2L 2
16
RES3:RES0
=
=
ARG1H:ARG1L ARG2H:ARG2L
16
16
(ARG1H ARG2H 2 ) +
)
8
(ARG1H ARG2L 2 ) +
8
(ARG1L ARG2H 2 ) +
(ARG1L ARG2L)
EXAMPLE 8-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
EXAMPLE 8-3:
16 x 16 UNSIGNED
MULTIPLY ROUTINE
; ARG1L * ARG2L ->
; PRODH:PRODL
MOVF
MULWF
ARG1L, W
ARG2L
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
;
;
; ARG1L * ARG2L ->
; PRODH:PRODL
;
;
;
;
MOVFF
MOVFF
PRODH, RES1
PRODL, RES0
MOVF
MULWF
ARG1H, W
ARG2H
; ARG1H * ARG2H ->
;
;
; PRODH:PRODL
;
;
MOVF
MULWF
ARG1H, W
ARG2H
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF
MOVFF
PRODH, RES3
PRODL, RES2
;
;
MOVF
MULWF
ARG1L, W
ARG2H
; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF
MULWF
ARG1L, W
ARG2H
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
; ARG1L * ARG2H ->
; PRODH:PRODL
; Add cross
; products
MOVF
ADDWF
MOVF
PRODL,
RES1, F
PRODH, W
W
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
;
;
;
; Add cross
; products
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
;
;
;
;
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L ->
;
; PRODH:PRODL
MOVF
MULWF
ARG1H, W
ARG2L
;
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
; ARG1H * ARG2L ->
; PRODH:PRODL
; Add cross
; products
MOVF
ADDWF
MOVF
PRODL, W
RES1, F
PRODH, W
;
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
;
;
;
; Add cross
; products
ADDWFC RES2, F
CLRF WREG
ADDWFC RES3, F
;
;
;
;
;
BTFSS
BRA
MOVF
SUBWF
MOVF
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, W
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs’ Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
SUBWFB RES3
SIGN_ARG1
BTFSS
BRA
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
; ARG1H:ARG1L neg?
; no, done
;
;
;
MOVF
SUBWF
MOVF
ARG2H, W
SUBWFB RES3
;
CONT_CODE
:
DS39609C-page 86
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
When the IPEN bit is cleared (default state), the
9.0
INTERRUPTS
interrupt priority feature is disabled and interrupts are
compatible with PIC® mid-range devices. In Compati-
bility mode, the interrupt priority bits for each source
have no effect. INTCON<6> is the PEIE bit, which
enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.
The PIC18FXX20 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high or a low
priority level. The high priority interrupt vector is at
000008h, while the low priority interrupt vector is at
000018h. High priority interrupt events will override any
low priority interrupts that may be in progress.
There are thirteen registers which are used to control
interrupt operation. They are:
When an interrupt is responded to, the Global Interrupt
Enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt.
• RCON
• INTCON
• INTCON2
• INTCON3
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
• PIR1, PIR2, PIR3
• PIE1, PIE2, PIE3
• IPR1, IPR2, IPR3
It is recommended that the Microchip header files,
supplied with MPLAB® IDE, be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
Each interrupt source has three bits to control its
operation. The functions of these bits are:
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set. Setting the GIEL
bit (INTCON<6>) enables all interrupts that have the
priority bit cleared. When the interrupt flag, enable bit
and appropriate global interrupt enable bit are set, the
interrupt will vector immediately to address 000008h or
000018h, depending on the priority level. Individual
interrupts can be disabled through their corresponding
enable bits.
2003-2013 Microchip Technology Inc.
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FIGURE 9-1:
INTERRUPT LOGIC
Wake-up if in Sleep mode
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
Interrupt to CPU
Vector to Location
0008h
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
GIEH/GIE
TMR1IF
TMR1IE
TMR1IP
IPEN
IPEN
XXXXIF
XXXXIE
XXXXIP
GIEL/PEIE
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
TMR1IF
TMR1IE
TMR1IP
RBIF
RBIE
XXXXIF
XXXXIE
XXXXIP
GIEL/PEIE
RBIP
GIE/GEIH
INT1IF
INT1IE
INT1IP
Additional Peripheral Interrupts
INT2IF
INT2IE
INT2IP
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9.1
INTCON Registers
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
REGISTER 9-1:
INTCON REGISTER
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
INT0IF
R/W-x
RBIF
bit 0
GIE/GIEH PEIE/GIEL
bit 7
TMR0IE
INT0IE
TMR0IF
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1= Enables all unmasked interrupts
0= Disables all interrupts
When IPEN (RCON<7>) = 1:
1= Enables all high priority interrupts
0= Disables all interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN (RCON<7>) = 1:
1= Enables all low priority peripheral interrupts
0= Disables all low priority peripheral interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared in software)
0= The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Note:
A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003-2013 Microchip Technology Inc.
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REGISTER 9-2:
INTCON2 REGISTER
R/W-1
RBPU
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBIP
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
INT3IP
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG0: External Interrupt 0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG1: External Interrupt 1 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG2: External Interrupt 2 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG3: External Interrupt 3 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
INT3IP: INT3 External Interrupt Priority bit
1= High priority
0= Low priority
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
DS39609C-page 90
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REGISTER 9-3:
INTCON3 REGISTER
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
INT3IF
R/W-0
INT2IF
R/W-0
INT1IF
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INT2IP: INT2 External Interrupt Priority bit
1= High priority
0= Low priority
INT1IP: INT1 External Interrupt Priority bit
1= High priority
0= Low priority
INT3IE: INT3 External Interrupt Enable bit
1= Enables the INT3 external interrupt
0= Disables the INT3 external interrupt
INT2IE: INT2 External Interrupt Enable bit
1= Enables the INT2 external interrupt
0= Disables the INT2 external interrupt
INT1IE: INT1 External Interrupt Enable bit
1= Enables the INT1 external interrupt
0= Disables the INT1 external interrupt
INT3IF: INT3 External Interrupt Flag bit
1= The INT3 external interrupt occurred (must be cleared in software)
0= The INT3 external interrupt did not occur
INT2IF: INT2 External Interrupt Flag bit
1= The INT2 external interrupt occurred (must be cleared in software)
0= The INT2 external interrupt did not occur
INT1IF: INT1 External Interrupt Flag bit
1= The INT1 external interrupt occurred (must be cleared in software)
0= The INT1 external interrupt did not occur
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
2003-2013 Microchip Technology Inc.
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9.2
PIR Registers
Note 1: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Flag Registers (PIR1, PIR2 and PIR3).
2: User software should ensure the appropri-
ate interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
REGISTER 9-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0
PSPIF(1)
bit 7
R/W-0
ADIF
R-0
R-0
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
TMR1IF
bit 0
RC1IF
TX1IF
CCP1IF
TMR2IF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
RC1IF: USART1 Receive Interrupt Flag bit
1= The USART1 receive buffer, RCREG, is full (cleared when RCREG is read)
0= The USART1 receive buffer is empty
TX1IF: USART Transmit Interrupt Flag bit
1= The USART1 transmit buffer, TXREG, is empty (cleared when TXREG is written)
0= The USART1 transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39609C-page 92
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REGISTER 9-5:
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
U-0
—
R/W-0
CMIF
U-0
—
R/W-0
EEIF
R/W-0
BCLIF
R/W-0
LVDIF
R/W-0
R/W-0
CCP2IF
bit 0
TMR3IF
bit 7
bit 7
bit 6
Unimplemented: Read as ‘0’
CMIF: Comparator Interrupt Flag bit
1= The comparator input has changed (must be cleared in software)
0= The comparator input has not changed
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1= The write operation is complete (must be cleared in software)
0= The write operation is not complete, or has not been started
bit 3
BCLIF: Bus Collision Interrupt Flag bit
1= A bus collision occurred while the SSP module (configured in I2C Master mode)
was transmitting (must be cleared in software)
0= No bus collision occurred
bit 2
bit 1
bit 0
LVDIF: Low-Voltage Detect Interrupt Flag bit
1= A low-voltage condition occurred (must be cleared in software)
0= The device voltage is above the Low-Voltage Detect trip point
TMR3IF: TMR3 Overflow Interrupt Flag bit
1= TMR3 register overflowed (must be cleared in software)
0= TMR3 register did not overflow
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1= A TMR1 or TMR3 register capture occurred (must be cleared in software)
0= No TMR1 or TMR3 register capture occurred
Compare mode:
1= A TMR1 or TMR3 register compare match occurred (must be cleared in software)
0= No TMR1 or TMR3 register compare match occurred
PWM mode:
Unused in this mode.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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REGISTER 9-6:
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
U-0
—
U-0
—
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
CCP3IF
bit 0
RC2IF
TX2IF
TMR4IF
CCP5IF
CCP4IF
bit 7
bit 7- 6
bit 5
Unimplemented: Read as ‘0’
RC2IF: USART2 Receive Interrupt Flag bit
1= The USART2 receive buffer, RCREG, is full (cleared when RCREG is read)
0= The USART2 receive buffer is empty
bit 4
TX2IF: USART2 Transmit Interrupt Flag bit
1= The USART2 transmit buffer, TXREG, is empty (cleared when TXREG is written)
0= The USART2 transmit buffer is full
bit 3
TMR4IF: TMR3 Overflow Interrupt Flag bit
1= TMR4 register overflowed (must be cleared in software)
0= TMR4 register did not overflow
bit 2-0
CCPxIF: CCPx Interrupt Flag bit (CCP Modules 3, 4 and 5)
Capture mode:
1= A TMR1 or TMR3 register capture occurred (must be cleared in software)
0= No TMR1 or TMR3 register capture occurred
Compare mode:
1= A TMR1 or TMR3 register compare match occurred (must be cleared in software)
0= No TMR1 or TMR3 register compare match occurred
PWM mode:
Unused in this mode.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39609C-page 94
2003-2013 Microchip Technology Inc.
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9.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2 and PIE3).
When the IPEN bit (RCON<7>) is ‘0’, the PEIE bit must
be set to enable any of these peripheral interrupts.
REGISTER 9-7:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
PSPIE(1)
bit 7
R/W-0
ADIE
R/W-0
RC1IE
R/W-0
TX1IE
R/W-0
SSPIE
R/W-0
R/W-0
R/W-0
TMR1IE
bit 0
CCP1IE
TMR2IE
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RC1IE: USART1 Receive Interrupt Enable bit
1= Enables the USART1 receive interrupt
0= Disables the USART1 receive interrupt
TX1IE: USART1 Transmit Interrupt Enable bit
1= Enables the USART1 transmit interrupt
0= Disables the USART1 transmit interrupt
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1= Enables the MSSP interrupt
0= Disables the MSSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003-2013 Microchip Technology Inc.
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REGISTER 9-8:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0
—
R/W-0
CMIE
U-0
—
R/W-0
EEIE
R/W-0
BCLIE
R/W-0
LVDIE
R/W-0
R/W-0
TMR3IE
CCP2IE
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
CMIE: Comparator Interrupt Enable bit
1= Enables the comparator interrupt
0= Disables the comparator interrupt
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1= Enables the write operation interrupt
0= Disables the write operation interrupt
bit 3
bit 2
bit 1
bit 0
BCLIE: Bus Collision Interrupt Enable bit
1= Enables the bus collision interrupt
0= Disables the bus collision interrupt
LVDIE: Low-Voltage Detect Interrupt Enable bit
1= Enables the Low-Voltage Detect interrupt
0= Disables the Low-Voltage Detect interrupt
TMR3IE: TMR3 Overflow Interrupt Enable bit
1= Enables the TMR3 overflow interrupt
0= Disables the TMR3 overflow interrupt
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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REGISTER 9-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
—
U-0
—
R/W-0
RC2IE
R/W-0
TX2IE
R/W-0
R/W-0
R/W-0
R/W-0
TMR4IE
CCP5IE
CCP4IE
CCP3IE
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as ‘0’
RC2IE: USART2 Receive Interrupt Enable bit
1= Enables the USART2 receive interrupt
0= Disables the USART2 receive interrupt
bit 4
TX2IE: USART2 Transmit Interrupt Enable bit
1= Enables the USART2 transmit interrupt
0= Disables the USART2 transmit interrupt
bit 3
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1= Enables the TMR4 to PR4 match interrupt
0= Disables the TMR4 to PR4 match interrupt
bit 2-0
CCPxIE: CCPx Interrupt Enable bit (CCP Modules 3, 4 and 5)
1= Enables the CCPx interrupt
0= Disables the CCPx interrupt
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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9.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Priority Registers (IPR1, IPR2 and IPR3). The
operation of the priority bits requires that the Interrupt
Priority Enable (IPEN) bit be set.
REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1
PSPIP(1)
bit 7
R/W-1
ADIP
R/W-1
RC1IP
R/W-1
TX1IP
R/W-1
SSPIP
R/W-1
R/W-1
R/W-1
TMR1IP
bit 0
CCP1IP
TMR2IP
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit(1)
1= High priority
0= Low priority
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
RC1IP: USART1 Receive Interrupt Priority bit
1= High priority
0= Low priority
TX1IP: USART1 Transmit Interrupt Priority bit
1= High priority
0= Low priority
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1= High priority
0= Low priority
CCP1IP: CCP1 Interrupt Priority bit
1= High priority
0= Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
U-0
—
R/W-1
CMIP
U-0
—
R/W-1
EEIP
R/W-1
BCLIP
R/W-1
LVDIP
R/W-1
R/W-1
TMR3IP
CCP2IP
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
CMIP: Comparator Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
Unimplemented: Read as ‘0’
EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
bit 0
BCLIP: Bus Collision Interrupt Priority bit
1= High priority
0= Low priority
LVDIP: Low-Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
CCP2IP: CCP2 Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0
—
U-0
—
R/W-1
RC2IP
R/W-1
TX2IP
R/W-1
R/W-1
R/W-1
R/W-1
TMR4IP
CCP5IP
CCP4IP
CCP3IP
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as ‘0’
RC2IP: USART2 Receive Interrupt Priority bit
1= High priority
0= Low priority
bit 4
TX2IP: USART2 Transmit Interrupt Priority bit
1= High priority
0= Low priority
bit 3
TMR4IP: TMR4 to PR4 Match Interrupt Priority bit
1= High priority
0= Low priority
bit 2-0
CCPxIP: CCPx Interrupt Priority bit (CCP Modules 3, 4 and 5)
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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9.5
RCON Register
The RCON register contains the IPEN bit, which is
used to enable prioritized interrupts. The functions of
the other bits in this register are discussed in more
detail in Section 4.14 “RCON Register”.
REGISTER 9-13: RCON REGISTER
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
bit 7
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (PIC16 Compatibility mode)
bit 6-5 Unimplemented: Read as ‘0’
bit 4
bit 3
bit 2
bit 1
bit 0
RI: RESETInstruction Flag bit
For details of bit operation, see Register 4-4.
TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-4.
PD: Power-Down Detection Flag bit
For details of bit operation, see Register 4-4.
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-4.
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-4.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘0’ = Bit is cleared
x = Bit is unknown
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9.6
INT0 Interrupt
9.7
TMR0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered:
either rising, if the corresponding INTEDGx bit is set in
the INTCON2 register, or falling, if the INTEDGx bit is
clear. When a valid edge appears on the RBx/INTx pin,
the corresponding flag bit, INTxF, is set. This interrupt
can be disabled by clearing the corresponding enable
bit, INTxE. Flag bit, INTxF, must be cleared in software
in the Interrupt Service Routine before re-enabling the
interrupt. All external interrupts (INT0, INT1, INT2 and
INT3) can wake-up the processor from Sleep if bit
INTxIE was set prior to going into Sleep. If the Global
Interrupt Enable bit, GIE, is set, the processor will
branch to the interrupt vector following wake-up.
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh 00h) will set flag bit TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L regis-
ters (FFFFh 0000h) will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit, TMR0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP (INTCON2<2>). See
Section 11.0 “Timer0 Module” for further details on
the Timer0 module.
9.8
PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
The interrupt priority for INT, INT2 and INT3 is deter-
mined by the value contained in the interrupt priority
bits: INT1IP (INTCON3<6>), INT2IP (INTCON3<7>)
and INT3IP (INTCON2<1>). There is no priority bit
associated with INT0; it is always a high priority
interrupt source.
9.9
Context Saving During Interrupts
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, Status and BSR registers
are saved on the fast return stack. If a fast return from
interrupt is not used (see Section 4.3 “Fast Register
Stack”), the user may need to save the WREG, Status
and BSR registers in software. Depending on the user’s
application, other registers may also need to be saved.
Example 9-1 saves and restores the WREG, Status and
BSR registers during an Interrupt Service Routine.
EXAMPLE 9-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
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10.1 PORTA, TRISA and LATA
Registers
10.0 I/O PORTS
Depending on the device selected, there are either
seven or nine I/O ports available on PIC18FXX20
devices. Some of their pins are multiplexed with one or
more alternate functions from the other peripheral fea-
tures on the device. In general, when a peripheral is
enabled, that pin may not be used as a general
purpose I/O pin.
PORTA is a 7-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Each port has three registers for its operation. These
registers are:
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
• TRIS register (data direction register)
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register, read and write the latched output value for
PORTA.
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The Data Latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA4/
T0CKI pin is a Schmitt Trigger input and an open-drain
output. All other RA port pins have TTL input levels and
full CMOS output drivers.
A simplified version of a generic I/O port and its
operation is shown in Figure 10-1.
The RA6 pin is only enabled as a general I/O pin in
ECIO and RCIO Oscillator modes.
FIGURE 10-1:
SIMPLIFIED BLOCK
DIAGRAM OF PORT/LAT/
TRIS OPERATION
The other PORTA pins are multiplexed with analog
inputs and the analog VREF+ and VREF- inputs. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register 1).
RD LAT
TRIS
Note:
On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as ‘0’. RA6 and RA4 are configured as
digital inputs.
D
Q
WR LAT +
WR Port
CK
Data Latch
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Data Bus
RD Port
I/O pin
EXAMPLE 10-1:
INITIALIZING PORTA
CLRF
PORTA
LATA
0x0F
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
CLRF
MOVLW
MOVWF
MOVLW
; Configure A/D
ADCON1 ; for digital inputs
0xCF
; Value used to
; initialize data
; direction
MOVWF
TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
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FIGURE 10-2:
BLOCK DIAGRAM OF
RA3:RA0AND RA5PINS
FIGURE 10-3:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
RD LATA
RD LATA
Data
Bus
Data
Bus
D
Q
D
Q
Q
WR LATA
or
PORTA
WR LATA
or
PORTA
VDD
I/O pin(1)
Q
Data Latch
CK
CK
P
N
Data Latch
I/O pin(1)
D
Q
N
D
Q
VSS
WR TRISA
RD TRISA
Schmitt
Trigger
Input
WR TRISA
RD TRISA
CK
Q
VSS
Analog
Q
CK
TRIS Latch
TRIS Latch
Input
Buffer
Mode
TTL
Input
Buffer
Q
D
Q
D
EN
EN
RD PORTA
RD PORTA
TMR0 Clock Input
To A/D Converter and LVD Modules
Note 1: I/O pins have protection diodes to VDD and VSS.
Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 10-4:
BLOCK DIAGRAM OF RA6 PIN (WHEN ENABLED AS I/O)
ECRA6 or RCRA6 Enable
Data Bus
RD LATA
D
Q
Q
VDD
P
WR LATA or PORTA
CK
Data Latch
I/O pin(1)
N
D
Q
WR TRISA
VSS
CK
Q
TRIS Latch
TTL
Input
Buffer
TRISA
RD
ECRA6 or RCRA6 Enable
Q
D
EN
RD PORTA
Note 1: I/O pins have protection diodes to VDD and VSS.
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TABLE 10-1: PORTA FUNCTIONS
Name
RA0/AN0
Bit#
Buffer
Function
bit 0
bit 1
bit 2
bit 3
bit 4
TTL
TTL
TTL
TTL
ST
Input/output or analog input.
Input/output or analog input.
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
Input/output or analog input or VREF-.
Input/output or analog input or VREF+.
Input/output or external clock input for Timer0.
Output is open-drain type.
RA5/AN4/LVDIN
OSC2/CLKO/RA6
bit 5
TTL
Input/output or slave select input for synchronous serial port or analog
input, or Low-Voltage Detect input.
bit 6
TTL
OSC2 or clock output, or I/O pin.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTA
LATA
—
—
—
—
RA6
RA5
RA4
RA3
RA2
RA1
RA0
-x0x 0000 -u0u 0000
-xxx xxxx -uuu uuuu
-111 1111 -111 1111
LATA Data Output Register
PORTA Data Direction Register
TRISA
ADCON1
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, – = unimplemented locations read as ‘0’.
Shaded cells are not used by PORTA.
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A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
10.2 PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB3 can be configured by the configuration bit
CCP2MX, as the alternate peripheral pin for the CCP2
module. This is only available when the device is
configured in Microprocessor, Microprocessor with
Boot Block, or Extended Microcontroller operating
modes.
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register, read and write the latched output value for
PORTB.
The RB5 pin is used as the LVP programming pin.
When the LVP configuration bit is programmed, this pin
loses the I/O function and become a programming test
function.
EXAMPLE 10-2:
INITIALIZING PORTB
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
CLRF
LATB
; Alternate method
; to clear output
; data latches
Note:
When LVP is enabled, the weak pull-up on
RB5 is disabled.
MOVLW
MOVWF
0xCF
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
FIGURE 10-5:
BLOCK DIAGRAM OF
RB7:RB4 PINS
TRISB
VDD
RBPU(2)
Data Bus
Weak
Pull-up
P
Data Latch
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
D
Q
WR LATB
or PORTB
I/O pin(1)
CK
TRIS Latch
D
Q
WR TRISB
TTL
CK
Input
Buffer
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
ST
Buffer
RD TRISB
RD LATB
Four of the PORTB pins (RB3:RB0) are the external
interrupt pins, INT3 through INT0. In order to use these
pins as external interrupts, the corresponding TRISB
bit must be set to ‘1’.
Latch
Q
D
The other four PORTB pins (RB7:RB4) have an inter-
rupt-on-change feature. Only pins configured as inputs
can cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with Flag bit, RBIF (INTCON<0>).
RD PORTB
Set RBIF
Q1
EN
Q
D
RD PORTB
Q3
From other
RB7:RB4 pins
EN
RB7:RB5 in Serial Programming Mode
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (INTCON2<7>).
a) Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
b) Clear flag bit RBIF.
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FIGURE 10-6:
BLOCK DIAGRAM OF RB2:RB0 PINS
VDD
RBPU(2)
Weak
P
Pull-up
Data Latch
Data Bus
D
Q
I/O pin(1)
WR Port
CK
TRIS Latch
D
Q
TTL
Input
Buffer
WR TRIS
CK
RD TRIS
RD Port
Q
D
EN
INTx
RD Port
Schmitt Trigger
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
FIGURE 10-7:
BLOCK DIAGRAM OF RB3 PIN
VDD
RBPU(2)
Weak
Pull-up
P
CCP2MX
CCP Output(3)
1
0
VDD
P
Enable(3)
CCP Output
Data Latch
I/O pin(1)
Data Bus
D
Q
WR LATB or
WR PORTB
N
CK
TRIS Latch
D
VSS
TTL
Input
Buffer
WR TRISB
CK
Q
RD TRISB
RD LATB
D
Q
RD PORTB
EN
RD PORTB
CCP2 or INT3
Schmitt Trigger
Buffer
CCP2MX = 0
Note 1: I/O pin has diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
3: The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration register and the device
is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode.
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TABLE 10-3: PORTB FUNCTIONS
Name
RB0/INT0
Bit#
Buffer
Function
bit 0
TTL/ST(1) Input/output pin or external interrupt input 0.
Internal software programmable weak pull-up.
RB1/INT1
bit 1
bit 2
bit 3
TTL/ST(1) Input/output pin or external interrupt input 1.
Internal software programmable weak pull-up.
TTL/ST(1) Input/output pin or external interrupt input 2.
Internal software programmable weak pull-up.
TTL/ST(4) Input/output pin or external interrupt input 3. Capture2 input/Compare2
output/PWM output (when CCP2MX configuration bit is enabled, all
PIC18F8X20 operating modes except Microcontroller mode).
Internal software programmable weak pull-up.
RB2/INT2
RB3/INT3/CCP2(3)
RB4/KBI0
bit 4
bit 5
TTL
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
RB5/KBI1/PGM
TTL/ST(2) Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Low-voltage ICSP enable pin.
RB6/KBI2/PGC
RB7/KBI3/PGD
bit 6
bit 7
TTL/ST(2) Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Serial programming clock.
TTL/ST(2) Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: RC1 is the alternate assignment for CCP2 when CCP2MX is not set (all operating modes except
Microcontroller mode).
4: This buffer is a Schmitt Trigger input when configured as the CCP2 input.
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTB
LATB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 0000 0000 0000
LATB Data Output Register
TRISB
INTCON
PORTB Data Direction Register
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF INT0IF
RBIF
INTCON2
INTCON3
Legend:
RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP
INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF
RBIP
1111 1111 1111 1111
1100 0000 1100 0000
INT2IP
INT1IF
x= unknown, u= unchanged. Shaded cells are not used by PORTB.
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The pin override value is not loaded into the TRIS
register. This allows read-modify-write of the TRIS
register, without concern due to peripheral overrides.
10.3 PORTC, TRISC and LATC
Registers
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
RC1 is normally configured by configuration bit,
CCP2MX, as the default peripheral pin of the CCP2
module (default/erased state, CCP2MX = 1).
EXAMPLE 10-3:
INITIALIZING PORTC
CLRF
PORTC
; Initialize PORTC by
; clearing output
; data latches
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register, read and write the latched output value for
PORTC.
CLRF
LATC
; Alternate method
; to clear output
; data latches
MOVLW
MOVWF
0xCF
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
PORTC is multiplexed with several peripheral functions
(Table 10-5). PORTC pins have Schmitt Trigger input
buffers.
TRISC
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings.
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
FIGURE 10-8:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
PORTC/Peripheral Out Select
Peripheral Data Out
VDD
P
0
1
RD LATC
Data Bus
D
Q
Q
(1)
I/O pin
or
WR LATC
CK
WR PORTC
Data Latch
TRIS OVERRIDE
N
D
Q
Q
Pin
Override
Peripheral
VSS
TRIS
Override
Logic
WR TRISC
CK
RC0
Yes
Timer1 Osc for
Timer1/Timer3
TRIS Latch
RC1
Yes
Timer1 Osc for
Timer1/Timer3,
CCP2 I/O
RD TRISC
Schmitt
Trigger
Peripheral Output
RC2
RC3
Yes
Yes
CCP1 I/O
(2)
Enable
2
Q
D
SPI/I C
Master Clock
EN
2
RC4
RC5
RC6
Yes
Yes
Yes
I C Data Out
RD PORTC
SPI Data Out
Peripheral Data In
USART1 Async
Xmit, Sync Clock
Note 1: I/O pins have diode protection to VDD and VSS.
2: Peripheral Output Enable is only active if Peripheral Select is active.
RC7
Yes
USART1 Sync
Data Out
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TABLE 10-5: PORTC FUNCTIONS
Name
Bit# Buffer Type
Function
RC0/T1OSO/T13CKI
bit 0
ST
Input/output port pin, Timer1 oscillator output or Timer1/Timer3
clock input.
RC1/T1OSI/CCP2(1)
bit 1
ST
Input/output port pin, Timer1 oscillator input or Capture2 input/
Compare2 output/PWM output (when CCP2MX configuration bit is
disabled).
RC2/CCP1
bit 2
bit 3
ST
ST
Input/output port pin or Capture1 input/Compare1 output/
PWM1 output.
RC3 can also be the synchronous serial clock for both SPI and I2C
RC3/SCK/SCL
modes.
RC4/SDI/SDA
RC5/SDO
bit 4
bit 5
bit 6
ST
ST
ST
RC4 can also be the SPI data in (SPI mode) or data I/O (I2C mode).
Input/output port pin or synchronous serial port data output.
RC6/TX1/CK1
Input/output port pin, addressable USART1 asynchronous transmit or
addressable USART1 synchronous clock.
RC7/RX1/DT1
bit 7
ST
Input/output port pin, addressable USART1 asynchronous receive or
addressable USART1 synchronous data.
Legend: ST = Schmitt Trigger input
Note 1: RB3 is the alternate assignment for CCP2 when CCP2MX is set.
TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTC
LATC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
LATC Data Output Register
PORTC Data Direction Register
TRISC
Legend: x= unknown, u= unchanged
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PORTD can also be configured as an 8-bit wide micro-
10.4 PORTD, TRISD and LATD
processor port (Parallel Slave Port) by setting control
bit PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 10.10 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
Registers
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
EXAMPLE 10-4:
INITIALIZING PORTD
CLRF
PORTD
; Initialize PORTD by
; clearing output
; data latches
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register, read and write the latched output value for
PORTD.
CLRF
LATD
; Alternate method
; to clear output
; data latches
MOVLW
MOVWF
0xCF
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
TRISD
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
PORTD is multiplexed with the system bus as the
external memory interface; I/O port functions are only
available when the system bus is disabled, by setting
the EBDIS bit in the MEMCOM register
(MEMCON<7>). When operating as the external mem-
ory interface, PORTD is the low-order byte of the
multiplexed address/data bus (AD7:AD0).
FIGURE 10-9:
PORTD BLOCK DIAGRAM IN I/O PORT MODE
PORTD/CCP1 Select
PSPMODE
RD LATD
VDD
P
Data Bus
WR LATD
D
Q
Q
or
PORTD
CK
Data Latch
D
Q
I/O pin(1)
WR TRISD
PSP Write
RD TRISD
Q
CK
0
1
N
TRIS Latch
VSS
TTL Buffer
1
0
Q
D
EN
Schmitt Trigger
Input Buffer
RD PORTD
PSP Read
0
1
Note 1: I/O pins have diode protection to VDD and VSS.
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FIGURE 10-10:
PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
RD PORTD
RD LATD
Data Bus
(1)
I/O pin
Port
D
Q
0
1
Data
WR LATD
or PORTD
CK
Data Latch
D
Q
TTL
Input
Buffer
WR TRISD
CK
TRIS Latch
RD TRISD
Bus Enable
Data/TRIS Out
Drive Bus
System Bus
Control
Instruction Register
Instruction Read
Note 1: I/O pins have protection diodes to VDD and VSS.
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TABLE 10-7: PORTD FUNCTIONS
Name
Bit#
Buffer Type
Function
RD0/PSP0/AD0
RD1/PSP1/AD1
RD2/PSP2/AD2
RD3/PSP3/AD3
RD4/PSP4/AD4
RD5/PSP5/AD5
RD6/PSP6/AD6
RD7/PSP7/AD7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
Input/output port pin, Parallel Slave Port bit 0 or address/data bus bit 0.
Input/output port pin, Parallel Slave Port bit 1 or address/data bus bit 1.
Input/output port pin, Parallel Slave Port bit 2 or address/data bus bit 2.
Input/output port pin, Parallel Slave Port bit 3 or address/data bus bit 3.
Input/output port pin, Parallel Slave Port bit 4 or address/data bus bit 4.
Input/output port pin, Parallel Slave Port bit 5 or address/data bus bit 5.
Input/output port pin, Parallel Slave Port bit 6 or address/data bus bit 6.
Input/output port pin, Parallel Slave Port bit 7 or address/data bus bit 7.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel
Slave Port mode.
TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 ---- 0000 ----
LATD Data Output Register
PORTD Data Direction Register
TRISD
PSPCON
IBF
OBF
—
IBOV PSPMODE
WAIT1 WAIT0
—
—
—
—
—
—
MEMCON EBDIS
WM1
WM0 0-00 --00 0-00 --00
Legend: x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PORTD.
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When the Parallel Slave Port is active, three PORTE
10.5 PORTE, TRISE and LATE
Registers
pins (RE0/RD/AD8, RE1/WR/AD9 and RE2/CS/AD10)
function as its control inputs. This automatically occurs
when the PSPMODE bit (PSPCON<4>) is set. Users
must also make certain that bits TRISE<2:0> are set to
configure the pins as digital inputs and the ADCON1
register is configured for digital I/O. The PORTE PSP
control functions are summarized in Table 10-9.
PORTE is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISE bit (= 0)
will make the corresponding PORTE pin an output (i.e.,
put the contents of the output latch on the selected pin).
Pin RE7 can be configured as the alternate peripheral
pin for CCP module 2 when the device is operating in
Microcontroller mode. This is done by clearing the
configuration bit, CCP2MX, in configuration register,
CONFIG3H (CONFIG3H<0>).
Read-modify-write operations on the LATE register,
read and write the latched output value for PORTE.
PORTE is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output. PORTE is multiplexed with the CCP module
(Table 10-9).
Note:
For PIC18F8X20 (80-pin) devices operat-
ing in Extended Microcontroller mode,
PORTE defaults to the system bus on
Power-on Reset.
On PIC18F8X20 devices, PORTE is also multiplexed
with the system bus as the external memory interface;
the I/O bus is available only when the system bus is
disabled, by setting the EBDIS bit in the MEMCON
register (MEMCON<7>). If the device is configured in
Microprocessor or Extended Microcontroller mode,
then the PORTE<7:0> becomes the high byte of the
address/data bus for the external program memory
interface. In Microcontroller mode, the PORTE<2:0>
pins become the control inputs for the Parallel Slave
Port when bit PSPMODE (PSPCON<4>) is set. (Refer
to Section 4.1.1 “PIC18F8X20 Program Memory
Modes” for more information on program memory
modes.)
EXAMPLE 10-5:
INITIALIZING PORTE
CLRF
PORTE
; Initialize PORTE by
; clearing output
; data latches
CLRF
LATE
; Alternate method
; to clear output
; data latches
MOVLW
MOVWF
0x03
; Value used to
; initialize data
; direction
; Set RE1:RE0 as inputs
; RE7:RE2 as outputs
TRISE
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FIGURE 10-11:
PORTE BLOCK DIAGRAM IN I/O MODE
Peripheral Out Select
Peripheral Data Out
VDD
P
0
1
(1)
I/O pin
RD LATE
Data Bus
WR LATE
or WR PORTE
D
Q
Q
CK
Data Latch
N
D
Q
Q
TRIS OVERRIDE
VSS
TRIS
Override
WR TRISE
CK
Pin Override
Peripheral
TRIS Latch
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
External Bus
External Bus
External Bus
External Bus
External Bus
External Bus
External Bus
External Bus
RD TRISE
Schmitt
Trigger
Peripheral Enable
Q
D
EN
RD PORTE
Peripheral Data In
Note 1: I/O pins have diode protection to VDD and VSS.
FIGURE 10-12:
PORTE BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
RD PORTE
RD LATE
Data Bus
(1)
I/O pin
Port
0
1
D
Q
Data
WR LATE
or PORTE
CK
Data Latch
D
Q
TTL
WR TRISE
CK
Input
Buffer
TRIS Latch
RD TRISE
Bus Enable
Data/TRIS Out
Drive Bus
System Bus
Control
Instruction Register
Instruction Read
Note 1: I/O pins have protection diodes to VDD and VSS.
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TABLE 10-9:
Name
PORTE FUNCTIONS
Bit#
Buffer Type
Function
RE0/RD/AD8
RE1/WR/AD9
RE2/CS/AD10
bit 0
ST/TTL(1)
Input/output port pin, read control for Parallel Slave Port or
address/data bit 8
For RD (PSP Control mode):
1= Not a read operation
0= Read operation, reads PORTD register (if chip selected)
bit 1
bit 2
ST/TTL(1)
ST/TTL(1)
Input/output port pin, write control for Parallel Slave Port or
address/data bit 9
For WR (PSP Control mode):
1= Not a write operation
0= Write operation, writes PORTD register (if chip selected)
Input/output port pin, chip select control for Parallel Slave Port or
address/data bit 10
For CS (PSP Control mode):
1= Device is not selected
0= Device is selected
RE3/AD11
bit 3
bit 4
bit 5
bit 6
bit 7
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
Input/output port pin or address/data bit 11.
Input/output port pin or address/data bit 12.
Input/output port pin or address/data bit 13.
Input/output port pin or address/data bit 14.
RE4/AD12
RE5/AD13
RE6/AD14
RE7/CCP2/AD15
Input/output port pin, Capture2 input/Compare2 output/PWM output
(PIC18F8X20 devices in Microcontroller mode only) or
address/data bit 15.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O or CCP mode and TTL buffers when in System Bus or PSP
Control mode.
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
all other
Resets
TRISE
PORTE Data Direction Control Register
1111 1111
xxxx xxxx
1111 1111
uuuu uuuu
uuuu uuuu
0000 --00
0000 ----
PORTE
LATE
Read PORTE pin/Write PORTE Data Latch
Read PORTE Data Latch/Write PORTE Data Latch
xxxx xxxx
MEMCON
PSPCON
EBDIS
IBF
—
WAIT1
IBOV
WAIT0
—
—
—
—
WM1 WM0 0-00 --00
OBF
PSPMODE
—
—
0000 ----
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTE.
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EXAMPLE 10-6:
INITIALIZING PORTF
10.6 PORTF, LATF and TRISF Registers
CLRF
PORTF
; Initialize PORTF by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
;
PORTF is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISF. Setting a
TRISF bit (= 1) will make the corresponding PORTF pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISF bit (= 0) will
make the corresponding PORTF pin an output (i.e., put
the contents of the output latch on the selected pin).
CLRF
LATF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
0x07
CMCON
0x0F
; Turn off comparators
;
Read-modify-write operations on the LATF register,
read and write the latched output value for PORTF.
ADCON1 ; Set PORTF as digital I/O
0xCF
; Value used to
; initialize data
; direction
; Set RF3:RF0 as inputs
; RF5:RF4 as outputs
; RF7:RF6 as inputs
PORTF is multiplexed with several analog peripheral
functions, including the A/D converter inputs and
comparator inputs, outputs and voltage reference.
MOVWF
TRISF
Note 1: On a Power-on Reset, the RF6:RF0 pins
are configured as inputs and read as ‘0’.
2: To configure PORTF as digital I/O, turn off
comparators and set ADCON1 value.
FIGURE 10-13:
PORTF RF1/AN6/C2OUT, RF2/AN7/C1OUT PINS BLOCK DIAGRAM
Port/Comparator Select
Comparator Data Out
VDD
P
0
1
RD LATF
Q
Data Bus
D
I/O pin
WR LATF
or
WR PORTF
Q
CK
Data Latch
N
D
Q
Q
VSS
WR TRISF
CK
Analog
Input
Mode
TRIS Latch
Schmitt
Trigger
RD TRISF
Q
D
EN
RD PORTF
To A/D Converter
Note 1: I/O pins have diode protection to VDD and VSS.
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FIGURE 10-14:
RF6:RF3 AND RF0 PINS
BLOCK DIAGRAM
FIGURE 10-15:
RF7 PIN BLOCK
DIAGRAM
RD LATF
RD LATF
Data
Bus
Data
Bus
D
Q
D
Q
WR LATF or
WR PORTF
I/O pin
WR LATF
or
WR PORTF
VDD
CK
Data Latch
CK
Data Latch
Q
P
D
Q
N
I/O pin
Schmitt
Trigger
Input
D
Q
WR TRISF
CK
TRIS Latch
Buffer
WR TRISF
RD TRISF
VSS
Analog
CK
TRIS Latch
Q
TTL
Input
Buffer
Input
Mode
RD TRISF
ST
Input
Q
D
Buffer
Q
D
EN
RD PORTF
SS Input
EN
RD PORTF
To A/D Converter or Comparator Input
Note:
I/O pins have diode protection to VDD and VSS.
Note 1: I/O pins have diode protection to VDD and VSS.
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TABLE 10-11: PORTF FUNCTIONS
Name
RF0/AN5
Bit#
Buffer Type
Function
Input/output port pin or analog input.
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
ST
ST
ST
ST
ST
ST
RF1/AN6/C2OUT
RF2/AN7/C1OUT
RF3/AN8
Input/output port pin, analog input or comparator 2 output.
Input/output port pin, analog input or comparator 1 output.
Input/output port pin or analog input/comparator input.
Input/output port pin or analog input/comparator input.
RF4/AN9
RF5/AN10/CVREF
Input/output port pin, analog input/comparator input or
comparator reference output.
RF6/AN11
RF7/SS
bit 6
bit 7
ST
Input/output port pin or analog input/comparator input.
ST/TTL
Input/output port pin or slave select pin for synchronous serial port.
Legend: ST = Schmitt Trigger input, TTL = TTL input
TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISF
PORTF Data Direction Control Register
Read PORTF pin/Write PORTF Data Latch
Read PORTF Data Latch/Write PORTF Data Latch
1111 1111
xxxx xxxx
0000 0000
1111 1111
uuuu uuuu
uuuu uuuu
--00 0000
0000 0000
0000 0000
PORTF
LATF
ADCON1
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000
CMCON C2OUT C1OUT C2INV C1INV
CIS
CM2
CM1
CM0
0000 0000
0000 0000
CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTF.
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make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings.
10.7 PORTG, TRISG and LATG
Registers
PORTG is a 5-bit wide, bidirectional port. The corre-
sponding data direction register is TRISG. Setting a
TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISG bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
EXAMPLE 10-7:
INITIALIZING PORTG
The Data Latch register (LATG) is also memory
mapped. Read-modify-write operations on the LATG
register, read and write the latched output value for
PORTG.
CLRF
PORTG
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
CLRF
LATG
PORTG is multiplexed with both CCP and USART
functions (Table 10-13). PORTG pins have Schmitt
Trigger input buffers.
MOVLW
MOVWF
0x04
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
TRISG
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
FIGURE 10-16:
PORTG BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
PORTG/Peripheral Out Select
Peripheral Data Out
VDD
P
0
1
RD LATG
Data Bus
D
Q
Q
(1)
I/O pin
or
WR LATG
CK
WR PORTG
Data Latch
N
D
Q
Q
VSS
TRIS
Override
Logic
WR TRISG
CK
TRIS Latch
RD TRISG
Schmitt
Trigger
Peripheral Output
TRIS OVERRIDE
(2)
Enable
Pin
Override
Peripheral
Q
D
RG0
RG1
Yes
Yes
CCP3 I/O
EN
USART1 Async
Xmit, Sync Clock
RD PORTG
Peripheral Data In
RG2
Yes
USART1 Async
Rcv, Sync Data
Out
RG3
RG4
Yes
Yes
CCP4 I/O
CCP5 I/O
Note 1: I/O pins have diode protection to VDD and VSS.
2: Peripheral Output Enable is only active if Peripheral Select is active.
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TABLE 10-13: PORTG FUNCTIONS
Name
Bit#
Buffer Type
Function
RG0/CCP3
bit 0
bit 1
ST
ST
Input/output port pin or Capture3 input/Compare3 output/PWM3 output.
RG1/TX2/CK2
Input/output port pin, addressable USART2 asynchronous transmit or
addressable USART2 synchronous clock.
RG2/RX2/DT2
bit 2
ST
Input/output port pin, addressable USART2 asynchronous receive or
addressable USART2 synchronous data.
RG3/CCP4
RG4/CCP5
bit 3
bit 4
ST
ST
Input/output port pin or Capture4 input/Compare4 output/PWM4 output.
Input/output port pin or Capture5 input/Compare5 output/PWM5 output.
Legend: ST = Schmitt Trigger input
TABLE 10-14: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTG
LATG
—
—
—
—
—
—
—
—
—
Read PORTF pin/Write PORTF Data Latch
LATG Data Output Register
---x xxxx ---u uuuu
---x xxxx ---u uuuu
---1 1111 ---1 1111
TRISG
Data Direction Control Register for PORTG
Legend: x= unknown, u= unchanged
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FIGURE 10-17:
RH3:RH0 PINS BLOCK
DIAGRAM IN I/O MODE
10.8 PORTH, LATH and TRISH
Registers
Note:
PORTH is available only on PIC18F8X20
devices.
RD LATH
Data
Bus
PORTH is an 8-bit wide, bidirectional I/O port. The cor-
responding data direction register is TRISH. Setting a
TRISH bit (= 1) will make the corresponding PORTH
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISH bit (= 0)
will make the corresponding PORTH pin an output (i.e.,
put the contents of the output latch on the selected pin).
D
Q
I/O pin(1)
WR LATH
or
PORTH
CK
Data Latch
D
Q
Read-modify-write operations on the LATH register,
read and write the latched output value for PORTH.
Schmitt
Trigger
Input
WR TRISH
RD TRISH
CK
TRIS Latch
Buffer
Pins RH7:RH4 are multiplexed with analog inputs
AN15:AN12. Pins RH3:RH0 are multiplexed with the
system bus as the external memory interface; they are
the high-order address bits, A19:A16. By default, pins
RH7:RH4 are enabled as A/D inputs and pins
RH3:RH0 are enabled as the system address bus.
Register ADCON1 configures RH7:RH4 as I/O or A/D
inputs. Register MEMCON configures RH3:RH0 as I/O
or system bus pins.
Q
D
EN
RD PORTH
Note 1: On Power-on Reset, PORTH pins
RH7:RH4 default to A/D inputs and read
as ‘0’.
Note 1: I/O pins have diode protection to VDD and VSS.
2: On Power-on Reset, PORTH pins
FIGURE 10-18:
RH7:RH4 PINS BLOCK
DIAGRAM IN I/O MODE
RH3:RH0 default to system bus signals.
EXAMPLE 10-8:
INITIALIZING PORTH
RD LATH
CLRF
PORTH
; Initialize PORTH by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
;
Data
Bus
D
Q
CLRF
LATH
I/O pin(1)
WR LATH
or
PORTH
CK
Data Latch
MOVLW
MOVWF
MOVLW
0Fh
ADCON1
0CFh
;
D
Q
; Value used to
; initialize data
; direction
Schmitt
Trigger
Input
WR TRISH
CK
TRIS Latch
Buffer
MOVWF
TRISH
; Set RH3:RH0 as inputs
; RH5:RH4 as outputs
; RH7:RH6 as inputs
RD TRISH
Q
D
EN
RD PORTH
To A/D Converter
Note 1: I/O pins have diode protection to VDD and VSS.
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FIGURE 10-19:
RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
RD PORTH
RD LATD
Data Bus
I/O pin(1)
Port
D
Q
0
1
Data
WR LATH
or
PORTH
CK
Data Latch
D
Q
WR TRISH
RD TRISH
TTL
Input
Buffer
CK
TRIS Latch
External Enable
Address Out
System Bus
Control
Drive System
To Instruction Register
Instruction Read
Note 1: I/O pins have diode protection to VDD and VSS.
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TABLE 10-15: PORTH FUNCTIONS
Name
Bit#
Buffer Type
Function
RH0/A16
RH1/A17
RH2/A18
RH3/A19
RH4/AN12
RH5/AN13
RH6/AN14
RH7/AN15
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST
Input/output port pin or address bit 16 for external memory interface.
Input/output port pin or address bit 17 for external memory interface.
Input/output port pin or address bit 18 for external memory interface.
Input/output port pin or address bit 19 for external memory interface.
Input/output port pin or analog input channel 12.
ST
Input/output port pin or analog input channel 13.
ST
Input/output port pin or analog input channel 14.
ST
Input/output port pin or analog input channel 15.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel
Slave Port mode.
TABLE 10-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISH
PORTH Data Direction Control Register
Read PORTH pin/Write PORTH Data Latch
Read PORTH Data Latch/Write PORTH Data Latch
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
PORTH
LATH
ADCON1
—
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000
WAIT1 WAIT0 WM1 WM0 0-00 --00 0-00 --00
MEMCON EBDIS
—
—
Legend: x= unknown, u= unchanged, – = unimplemented. Shaded cells are not used by PORTH.
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FIGURE 10-20:
PORTJ BLOCK DIAGRAM
IN I/O MODE
10.9 PORTJ, TRISJ and LATJ
Registers
Note:
PORTJ is available only on PIC18F8X20
devices.
RD LATJ
Data
Bus
PORTJ is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISJ. Setting a
TRISJ bit (= 1) will make the corresponding PORTJ pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISJ bit (= 0) will
make the corresponding PORTJ pin an output (i.e., put
the contents of the output latch on the selected pin).
D
Q
I/O pin(1)
WR LATJ
or
PORTJ
CK
Data Latch
D
Q
Schmitt
Trigger
Input
The Data Latch register (LATJ) is also memory
mapped. Read-modify-write operations on the LATJ
register, read and write the latched output value for
PORTJ.
WR TRISJ
CK
TRIS Latch
Buffer
RD TRISJ
PORTJ is multiplexed with the system bus as the exter-
nal memory interface; I/O port functions are only avail-
able when the system bus is disabled. When operating
as the external memory interface, PORTJ provides the
control signal to external memory devices. The RJ5 pin
is not multiplexed with any system bus functions.
Q
D
EN
RD PORTJ
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTJ pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the corre-
sponding peripheral section for the correct TRIS bit
settings.
Note 1: I/O pins have diode protection to VDD and VSS.
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
EXAMPLE 10-9:
INITIALIZING PORTJ
CLRF
PORTJ
; Initialize PORTG by
; clearing output
; data latches
CLRF
LATJ
; Alternate method
; to clear output
; data latches
MOVLW
MOVWF
0xCF
; Value used to
; initialize data
; direction
; Set RJ3:RJ0 as inputs
; RJ5:RJ4 as output
; RJ7:RJ6 as inputs
TRISJ
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FIGURE 10-21:
RJ4:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
RD PORTJ
RD LATJ
Data Bus
I/O pin(1)
Port
D
Q
0
1
Data
WR LATJ
or
PORTJ
CK
Data Latch
D
Q
WR TRISJ
RD TRISJ
CK
TRIS Latch
Control Out
System Bus
Control
External Enable
Drive System
Note 1: I/O pins have diode protection to VDD and VSS.
FIGURE 10-22:
RJ7:RJ6 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
RD PORTJ
RD LATJ
Data Bus
I/O pin(1)
Port
D
Q
0
1
Data
WR LATJ
or
PORTJ
CK
Data Latch
D
Q
WR TRISJ
CK
TRIS Latch
RD TRISJ
UB/LB Out
WM = 01
System Bus
Control
Drive System
Note 1: I/O pins have diode protection to VDD and VSS.
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TABLE 10-17: PORTJ FUNCTIONS
Name
Bit#
Buffer Type
Function
RJ0/ALE
bit 0
ST
Input/output port pin or address latch enable control for external memory
interface.
RJ1/OE
RJ2/WRL
RJ3/WRH
RJ4/BA0
RJ5/CE
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
ST
ST
ST
ST
ST
ST
Input/output port pin or output enable control for external memory interface.
Input/output port pin or write low byte control for external memory interface.
Input/output port pin or write high byte control for external memory interface.
Input/output port pin or byte address 0 control for external memory interface.
Input/output port pin or chip enable control for external memory interface.
RJ6/LB
Input/output port pin or lower byte select control for external memory
interface.
RJ7/UB
bit 7
ST
Input/output port pin or upper byte select control for external memory
interface.
Legend: ST = Schmitt Trigger input
TABLE 10-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTJ
LATJ
Read PORTJ pin/Write PORTJ Data Latch
LATJ Data Output Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
TRISJ
Data Direction Control Register for PORTJ
Legend: x= unknown, u= unchanged
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FIGURE 10-23:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
10.10 Parallel Slave Port
PORTD also operates as an 8-bit wide Parallel Slave
Port, or microprocessor port, when control bit
PSPMODE (PSPCON<4>) is set. It is asynchronously
readable and writable by the external world through the
RD control input pin, RE0/RD/AD8 and the WR control
input pin, RE1/WR/AD9.
Data Bus
D
Q
RDx
pin
WR LATD
or
PORTD
CK
Note:
For PIC18F8X20 devices, the Parallel
Slave Port is available only in
Microcontroller mode.
TTL
Data Latch
Q
D
The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
bit PSPMODE enables port pin RE0/RD/AD8 to be the
RD input, RE1/WR/AD9 to be the WR input and RE2/
CS/AD10 to be the CS (Chip Select) input. For this
functionality, the corresponding data direction bits of
the TRISE register (TRISE<2:0>) must be configured
as inputs (set). The A/D port configuration bits,
PCFG2:PCFG0 (ADCON1<2:0>), must be set which
will configure pins RE2:RE0 as digital I/O.
RD PORTD
EN
TRIS Latch
RD LATD
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
The PORTE I/O pins become control inputs for the
microprocessor
port
when
bit
PSPMODE
(PSPCON<4>) is set. In this mode, the user must make
sure that the TRISE<2:0> bits are set (pins are config-
ured as digital inputs) and the ADCON1 is configured
for digital I/O. In this mode, the input buffers are TTL.
Read
RD
CS
TTL
Chip Select
TTL
Write
WR
TTL
Note: I/O pin has protection diodes to VDD and VSS.
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REGISTER 10-1: PSPCON REGISTER
R-0 R-0
IBF OBF
bit 7
R/W-0
IBOV
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
PSPMODE
bit 0
bit 7
bit 6
bit 5
IBF: Input Buffer Full Status bit
1= A word has been received and is waiting to be read by the CPU
0= No word has been received
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit
1= A write occurred when a previously input word has not been read
(must be cleared in software)
0= No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel Slave Port mode
0= General Purpose I/O mode
bit 3-0
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
FIGURE 10-24:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
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FIGURE 10-25:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
Port Data Latch when written; Port pins when read
LATD Data Output bits
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 0000 0000 0000
TRISD
PORTE
PORTD Data Direction bits
—
—
—
—
—
Read PORTE pin/
Write PORTE Data Latch
LATE
—
—
—
—
—
—
—
—
—
—
LATE Data Output bits
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 ---- 0000 ----
0000 0000 0000 0000
TRISE
PORTE Data Direction bits
PSPCON
INTCON
IBF
OBF
IBOV
TMR0IF
PSPMODE
INT0IE
—
—
—
—
GIE/
GIEH
PEIE/
GIEL
RBIE
TMR0IF
INT0IF
RBIF
(1)
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
CCP1IF TMR2IF
TMR1IF 0000 0000 0000 0000
(1)
(1)
PIE1
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111
IPR1
Legend:
x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices.
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Figure 11-1 shows a simplified block diagram of the
11.0 TIMER0 MODULE
Timer0 module in 8-bit mode and Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
The Timer0 module has the following features:
• Software selectable as an 8-bit or
16-bit timer/counter
The T0CON register (Register 11-1) is a readable and
writable register that controls all the aspects of Timer0,
including the prescale selection.
• Readable and writable
• Dedicated 8-bit software programmable prescaler
• Clock source selectable to be external or internal
• Interrupt-on-overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
• Edge select for external clock
REGISTER 11-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1
TMR0ON
bit 7
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
bit 0
T08BIT
bit 7
bit 6
bit 5
bit 4
bit 3
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
T08BIT: Timer0 8-bit/16-bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKO)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits
111= 1:256 prescale value
110= 1:128 prescale value
101= 1:64 prescale value
100= 1:32 prescale value
011= 1:16 prescale value
010= 1:8 prescale value
001= 1:4 prescale value
000= 1:2 prescale value
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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FIGURE 11-1:
TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus
TMR0
FOSC/4
0
1
8
0
Sync with
Internal
Clocks
RA4/T0CKI pin
Programmable
Prescaler
1
(2 TCY delay)
T0SE
3
PSA
Set Interrupt
Flag bit TMR0IF
on Overflow
T0PS2, T0PS1, T0PS0
T0CS
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 11-2:
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
FOSC/4
0
0
Sync with
Set Interrupt
Flag bit TMR0IF
on Overflow
TMR0
High Byte
Internal
Clocks
1
TMR0L
Programmable
Prescaler
RA4/T0CKI
pin
1
8
(2 TCY delay)
T0SE
3
Read TMR0L
Write TMR0L
PSA
T0PS2, T0PS1, T0PS0
T0CS
8
8
TMR0H
8
Data Bus<7:0>
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
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11.2.1
SWITCHING PRESCALER
ASSIGNMENT
11.1 Timer0 Operation
Timer0 can operate as a timer or as a counter.
The prescaler assignment is fully under software
control, (i.e., it can be changed “on-the-fly” during
program execution).
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 regis-
ter is written, the increment is inhibited for the following
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
11.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF bit. The interrupt can be masked by clearing
the TMR0IE bit. The TMR0IF bit must be cleared in
software by the Timer0 module Interrupt Service
Routine before re-enabling this interrupt. The TMR0
interrupt cannot awaken the processor from Sleep,
since the timer is shut-off during Sleep.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment, either on every
rising or falling edge of pin RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit (T0SE). Clearing the T0SE bit selects the
rising edge. Restrictions on the external clock input are
discussed below.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
11.4 16-Bit Mode Timer Reads
and Writes
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 11-2). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16 bits of Timer0 without
having to verify that the read of the high and low byte
were valid, due to a rollover between successive reads
of the high and low byte.
11.2 Prescaler
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not readable or writable.
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
A write to the high byte of Timer0 must also take place
through the TMR0H Buffer register. Timer0 high byte is
updated with the contents of TMR0H when a write
occurs to TMR0L. This allows all 16 bits of Timer0 to be
updated at once.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, x, ..., etc.) will clear the prescaler
count.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the
prescaler count, but will not change the
prescaler assignment.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Value on
all other
Resets
Value on
POR, BOR
Bit 1
Bit 0
TMR0L Timer0 Module Low Byte Register
TMR0H Timer0 Module High Byte Register
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000
T0CON
TRISA
TMR0ON
—
T08BIT
T0CS
T0SE
PSA
T0PS2 T0PS1 T0PS0 1111 1111 1111 1111
PORTA Data Direction Register
-111 1111 -111 1111
Legend: x= unknown, u= unchanged, – = unimplemented locations, read as ‘0’.
Shaded cells are not used by Timer0.
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Register 12-1 details the Timer1 Control register. This
12.0 TIMER1 MODULE
register controls the operating mode of the Timer1
module and contains the Timer1 Oscillator Enable bit
(T1OSCEN). Timer1 can be enabled or disabled by
setting or clearing control bit, TMR1ON (T1CON<0>).
The Timer1 module timer/counter has the following
features:
• 16-bit timer/counter
(two 8-bit registers: TMR1H and TMR1L)
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications, with only a minimal
addition of external components and code overhead.
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module special event trigger
Figure 12-1 is a simplified block diagram of the Timer1
module.
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
RD16
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
bit 7
bit 6
RD16: 16-bit Read/Write Mode Enable bit
1= Enables register read/write of Timer1 in one 16-bit operation
0= Enables register read/write of Timer1 in two 8-bit operations
Unimplemented: Read as ‘0’
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable bit
1= Timer1 oscillator is enabled
0= Timer1 oscillator is shut off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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When TMR1CS = 0, Timer1 increments every instruc-
12.1 Timer1 Operation
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored and the pins are read as ‘0’.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
Timer1 also has an internal “Reset input”. This
Reset can be generated by the CCP module
(see Section 16.0 “Capture/Compare/PWM (CCP)
Modules”).
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag Bit
Synchronized
TMR1
CLR
0
Clock Input
TMR1L
TMR1H
1
TMR1ON
On/Off
T1SYNC
T1OSC
1
T1OSO/T13CKI
T1OSI
Synchronize
det
T1OSCEN
Enable
Oscillator
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
(1)
0
2
Sleep Input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR1H
8
8
Write TMR1L
Read TMR1L
CCP Special Event Trigger
0
TMR1IF
Overflow
Interrupt
Synchronized
Clock Input
TMR1
8
CLR
Timer 1
High Byte
TMR1L
Flag bit
1
TMR1ON
On/Off
T1SYNC
T1OSC
T1OSO/T13CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FOSC/4
Internal
Clock
0
(1)
T1OSI
2
Sleep Input
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
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12.2.1
LOW-POWER TIMER1 OPTION
(PIC18FX520 DEVICES ONLY)
12.2 Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit, T1OSCEN (T1CON<3>). The oscil-
lator is a low-power oscillator, rated up to 200 kHz. It
will continue to run during Sleep. It is primarily intended
for a 32 kHz crystal. The circuit for a typical LP oscilla-
tor is shown in Figure 12-3. Table 12-1 shows the
capacitor selection for the Timer1 oscillator.
The Timer1 oscillator for PIC18LFX520 devices incor-
porates a low-power feature, which allows the oscillator
to automatically reduce its power consumption when
the microcontroller is in Sleep mode.
As high noise environments may cause excessive
oscillator instability in Sleep mode, this option is best
suited for low noise applications where power
conservation is an important design consideration. Due
to the low-power nature of the oscillator, it may also be
sensitive to rapidly changing signals in close proximity.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator
FIGURE 12-3:
EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
C1
33 pF
PIC18FXX20
If a high-speed circuit must be located near the oscilla-
tor (such as the CCP1 pin in output compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
T1OSI
XTAL
32.768 kHz
T1OSO
C2
33 pF
FIGURE 12-4:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
Note:
See the Notes with Table 12-1 for additional
information about capacitor selection.
VDD
VSS
TABLE 12-1: CAPACITOR SELECTION
FOR THE ALTERNATE
OSC1
OSC2
OSCILLATOR
Osc Type
Freq
C1
C2
LP
32 kHz
TBD(1)
TBD(1)
Crystal to be Tested:
RC0
RC1
32.768 kHz Epson C-001R32.768K-A 20 PPM
Note 1: Microchip suggests 33 pF as a starting
point in validating the oscillator circuit.
RC2
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
Note:
Not drawn to scale.
Note:
PIC18FX620/X720 devices have the
standard Timer1 oscillator permanently
selected. PIC18LFX620/X720 devices
have the low-power Timer1 oscillator
permanently selected.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
4: Capacitor values are for design guidance
only.
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12.3 Timer1 Interrupt
12.6 Using Timer1 as a
Real-Time Clock
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled/disabled by
setting/clearing TMR1 Interrupt Enable bit, TMR1IE
(PIE1<0>).
Adding an external LP oscillator to Timer1 (such as the
one described in Section 12.2 “Timer1 Oscillator”)
gives users the option to include RTC functionality to
their applications. This is accomplished with an inex-
pensive watch crystal to provide an accurate time base
and several lines of application code to calculate the
time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
12.4 Resetting Timer1 Using a CCP
Trigger Output
If the CCP module is configured in Compare mode
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to incre-
ment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow, triggers the interrupt and calls
the routine, which increments the seconds counter by
one; additional counters for minutes and hours are
incremented as the previous counter overflow.
to
generate
a
“special
event
trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1 and start an A/D conversion (if the A/D module
is enabled).
Note:
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to
preload it; the simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L
register pair effectively becomes the period register for
Timer1.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
12.5 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16 bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, is
valid, due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or writ-
able in this mode. All reads and writes must take place
through the Timer1 High Byte Buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The
prescaler is only cleared on writes to TMR1L.
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EXAMPLE 12-1:
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
RTCinit
MOVLW
MOVWF
CLRF
0x80
TMR1H
TMR1L
; Preload TMR1 register pair
; for 1 second overflow
MOVLW
MOVWF
CLRF
b’00001111’
T1OSC
secs
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
;
CLRF
mins
MOVLW
MOVWF
BSF
.12
hours
PIE1, TMR1IE
; Enable Timer1 interrupt
RETURN
RTCisr
BSF
BCF
INCF
MOVLW
TMR1H, 7
PIR1, TMR1IF
secs, F
.59
; Preload for 1 sec overflow
; Clear interrupt flag
; Increment seconds
; 60 seconds elapsed?
CPFSGT secs
RETURN
; No, done
CLRF
INCF
MOVLW
secs
mins, F
.59
; Clear seconds
; Increment minutes
; 60 minutes elapsed?
CPFSGT mins
RETURN
; No, done
CLRF
INCF
MOVLW
mins
hours, F
.23
; clear minutes
; Increment hours
; 24 hours elapsed?
CPFSGT hours
RETURN
; No, done
MOVLW
MOVWF
RETURN
.01
hours
; Reset hours to 1
; Done
TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111
PIE1
TXIE
TXIP
IPR1
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
T1CON
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
Legend:
x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
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13.1 Timer2 Operation
13.0 TIMER2 MODULE
Timer2 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable and is cleared on any device
Reset. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits,
T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out-
put of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt (latched in flag bit, TMR2IF (PIR1<1>)).
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
• SSP module optional use of TMR2 output to
generate clock shift
The prescaler and postscaler counters are cleared
when any of the following occurs:
Timer2 has a control register shown in Register 13-1.
Timer2 can be shut-off by clearing control bit, TMR2ON
(T2CON<2>), to minimize power consumption.
Figure 13-1 is a simplified block diagram of the Timer2
module. Register 13-1 shows the Timer2 Control regis-
ter. The prescaler and postscaler selection of Timer2
are controlled by this register.
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as ‘0’
bit 6-3 T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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13.2 Timer2 Interrupt
13.3 Output of TMR2
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
The output of TMR2 (before the postscaler) is fed to the
synchronous serial port module, which optionally uses
it to generate the shift clock.
FIGURE 13-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
TMR2
bit TMR2IF
(1)
Output
Prescaler
Reset
EQ
TMR2
FOSC/4
1:1, 1:4, 1:16
Postscaler
1:1 to 1:16
2
Comparator
PR2
T2CKPS1:T2CKPS0
4
T2OUTPS3:T2OUTPS0
Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.
TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111
0000 0000 0000 0000
PIE1
TXIE
TXIP
IPR1
TMR2
T2CON
PR2
Timer2 Module Register
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register 1111 1111 1111 1111
x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Legend:
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Figure 14-1 is a simplified block diagram of the Timer3
module.
14.0 TIMER3 MODULE
The Timer3 module timer/counter has the following
features:
Register 14-1 shows the Timer3 Control register. This
register controls the operating mode of the Timer3
module and sets the CCP clock source.
• 16-bit timer/counter
(two 8-bit registers; TMR3H and TMR3L)
Register 12-1 shows the Timer1 Control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 Oscillator
Enable bit (T1OSCEN), which can be a clock source for
Timer3.
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module trigger
REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0
RD16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 0
bit 7
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1= Enables register read/write of Timer3 in one 16-bit operation
0= Enables register read/write of Timer3 in two 8-bit operations
bit 6, 3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
11= Timer3 and Timer4 are the clock sources for CCP1 through CCP5
10= Timer3 and Timer4 are the clock sources for CCP3 through CCP5;
Timer1 and Timer2 are the clock sources for CCP1 and CCP2
01= Timer3 and Timer4 are the clock sources for CCP2 through CCP5;
Timer1 and Timer2 are the clock sources for CCP1
00= Timer1 and Timer2 are the clock sources for CCP1 through CCP5
bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 2
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1
bit 0
TMR3CS: Timer3 Clock Source Select bit
1= External clock input from Timer1 oscillator or T13CKI (on the rising edge after the
first falling edge)
0= Internal clock (FOSC/4)
TMR3ON: Timer3 On bit
1= Enables Timer3
0= Stops Timer3
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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When TMR3CS = 0, Timer3 increments every instruc-
14.1 Timer3 Operation
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored and the pins are read as ‘0’.
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
Timer3 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see Section 14.0
“Timer3 Module”).
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
CCP Special Trigger
T3CCPx
TMR3IF
Overflow
Interrupt
Synchronized
Clock Input
0
Flag bit
CLR
TMR3L
TMR3H
T1OSC
1
TMR3ON
On/Off
T3SYNC
(3)
T1OSO/
T13CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
FOSC/4
Internal
Clock
0
(1)
T1OSI
Oscillator
2
Sleep Input
TMR3CS
T3CKPS1:T3CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR3H
8
8
Write TMR3L
Read TMR3L
CCP Special Trigger
T3CCPx
0
Synchronized
Clock Input
8
TMR3
Set TMR3IF Flag bit
on Overflow
CLR
Timer3
High Byte
TMR3L
1
To Timer1 Clock Input
TMR3ON
On/Off
T3SYNC
T1OSC
T1OSO/
T13CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FOSC/4
Internal
Clock
0
(1)
T1OSI
2
Sleep Input
T3CKPS1:T3CKPS0
TMR3CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
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14.2 Timer1 Oscillator
14.4 Resetting Timer3 Using a CCP
Trigger Output
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON<3>) bit. The oscillator is a low-
power oscillator rated up to 200 kHz. See Section 12.0
“Timer1 Module” for further details.
If the CCP module is configured in Compare mode
to
generate
a
“special
event
trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer3.
Note:
The special event triggers from the CCP
module will not set interrupt flag bit,
TMR3IF (PIR1<0>).
14.3 Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit, TMR3IF
(PIR2<1>). This interrupt can be enabled/disabled by
setting/clearing TMR3 Interrupt Enable bit, TMR3IE
(PIE2<1>).
Timer3 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this Reset operation may not work. In the event that a
write to Timer3 coincides with a special event trigger
from CCP1, the write will take precedence. In this mode
of operation, the CCPR1H:CCPR1L register pair
effectively becomes the period register for Timer3.
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
EEIF
RBIE
BCLIF
BCLIE
BCLIP
TMR0IF INT0IF
RBIF
0000 0000 0000 0000
PIR2
—
—
—
—
—
—
—
—
—
LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000
PIE2
EEIE
EEIP
LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000
LVDIP TMR3IP CCP2IP ---1 1111 ---1 1111
IPR2
TMR3L
TMR3H
T1CON
T3CON
Legend:
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
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NOTES:
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15.1 Timer4 Operation
15.0 TIMER4 MODULE
Timer4 can be used as the PWM time base for the
PWM mode of the CCP module. The TMR4 register is
readable and writable and is cleared on any device
Reset. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4 or 1:16, selected by control bits
T4CKPS1:T4CKPS0 (T4CON<1:0>). The match out-
put of TMR4 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR4 interrupt, latched in flag bit, TMR4IF (PIR3<3>).
The Timer4 module timer has the following features:
• 8-bit timer (TMR4 register)
• 8-bit period register (PR4)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR4 match of PR4
Timer4 has a control register shown in Register 15-1.
Timer4 can be shut-off by clearing control bit, TMR4ON
(T4CON<2>), to minimize power consumption. The
prescaler and postscaler selection of Timer4 are also
controlled by this register. Figure 15-1 is a simplified
block diagram of the Timer4 module.
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR4 register
• a write to the T4CON register
• any device Reset (Power-on Reset, MCLR Reset,
Watchdog Timer Reset or Brown-out Reset)
TMR4 is not cleared when T4CON is written.
REGISTER 15-1: T4CON: TIMER4 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as ‘0’
bit 6-3 T4OUTPS3:T4OUTPS0: Timer4 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR4ON: Timer4 On bit
1= Timer4 is on
0= Timer4 is off
bit 1-0 T4CKPS1:T4CKPS0: Timer4 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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15.2 Timer4 Interrupt
15.3 Output of TMR4
The Timer4 module has an 8-bit period register, PR4,
which is both readable and writable. Timer4 increments
from 00h until it matches PR4 and then resets to 00h on
the next increment cycle. The PR4 register is initialized
to FFh upon Reset.
The output of TMR4 (before the postscaler) is used
only as a PWM time base for the CCP modules. It is not
used as a baud rate clock for the MSSP, as is the
Timer2 output.
FIGURE 15-1:
TIMER4 BLOCK DIAGRAM
Sets Flag
TMR4
bit TMR4IF
(1)
Output
Prescaler
Reset
EQ
TMR4
FOSC/4
1:1, 1:4, 1:16
Postscaler
1:1 to 1:16
2
Comparator
PR4
T4CKPS1:T4CKPS0
4
T4OUTPS3:T4OUTPS0
TABLE 15-1: REGISTERS ASSOCIATED WITH TIMER4 AS A TIMER/COUNTER
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX2IP
TX2IF
TX2IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
IPR3
—
—
—
—
—
—
RC2IP
RC2IF
RC2IE
TMR4IP
TMR4IF
TMR4IE
CCP5IP CCP4IP CCP3IP --11 1111 --00 0000
CCP5IF CCP4IF CCP3IF --00 0000 --00 0000
CCP5IE CCP4IE CCP3IE --00 0000 --00 0000
0000 0000 0000 0000
PIR3
PIE3
TMR4
T4CON
PR4
Timer4 Module Register
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000
Timer4 Period Register 1111 1111 1111 1111
x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4 module.
Legend:
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For the sake of clarity, CCP module operation in the
16.0 CAPTURE/COMPARE/PWM
following sections is described with respect to CCP1.
The descriptions can be applied (with the exception of
the special event triggers) to any of the modules.
(CCP) MODULES
The PIC18FXX20 devices all have five CCP (Capture/
Compare/PWM) modules. Each module contains a
16-bit register, which can operate as a 16-bit Capture
register, a 16-bit Compare register or a Pulse Width
Modulation (PWM) Master/Slave Duty Cycle register.
Table 16-1 shows the timer resources of the CCP
module modes.
Note:
Throughout this section, references to
register and bit names that may be associ-
ated with a specific CCP module are
referred to generically by the use of ‘x’ or
‘y’ in place of the specific module number.
Thus, “CCPxCON” might refer to the
control register for CCP1, CCP2, CCP3,
CCP4 or CCP5.
The operation of all CCP modules are identical, with
the exception of the special event trigger present on
CCP1 and CCP2.
REGISTER 16-1: CCPxCON REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
DCxB0
R/W-0
R/W-0
R/W-0
R/W-0
DCxB1
CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP Module x
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The
eight Most Significant bits (DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCP Module x Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCPx module)
0001= Reserved
0010= Compare mode, toggle output on match (CCPxIF bit is set)
0011= Reserved
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, Initialize CCP pin Low; on compare match, force CCP pin High
(CCPIF bit is set)
1001= Compare mode, Initialize CCP pin High; on compare match, force CCP pin Low
(CCPIF bit is set)
1010= Compare mode, Generate software interrupt on compare match (CCPIF bit is set,
(CCP pin is unaffected)
1011= Compare mode, trigger special event (CCPIF bit is set):
For CCP1 and CCP2:
Timer1 or Timer3 is reset on event.
For all other modules:
CCPx pin is unaffected and is configured as an I/O port
(same as CCPxM<3:0> = 1010, above).
11xx= PWM mode
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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TABLE 16-1: CCP MODE – TIMER
RESOURCE
16.1 CCP Module Configuration
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2 or Timer4
The assignment of a particular timer to a module is
determined by the Timer-to-CCP Enable bits in the
T3CON register (Register 14-1). Depending on the
configuration selected, up to four timers may be active
at once, with modules in the same configuration
(Capture/Compare or PWM) sharing timer resources.
The possible configurations are shown in Figure 16-1.
16.1.1
CCP MODULES AND TIMER
RESOURCES
The CCP modules utilize Timers 1, 2, 3 or 4, depending
on the mode selected. Timer1 and Timer3 are available
to modules in Capture or Compare modes, while
Timer2 and Timer4 are available for modules in PWM
mode.
FIGURE 16-1:
CCP AND TIMER INTERCONNECT CONFIGURATIONS
T3CCP<2:1> = 00
T3CCP<2:1> = 01
T3CCP<2:1> = 10
T3CCP<2:1> = 11
TMR1
TMR3
TMR1
TMR3
TMR1
TMR3
TMR1
TMR3
CCP1
CCP2
CCP3
CCP4
CCP5
CCP1
CCP1
CCP2
CCP1
CCP2
CCP3
CCP4
CCP5
CCP2
CCP3
CCP4
CCP5
CCP3
CCP4
CCP5
TMR2
TMR4
TMR2
TMR4
TMR2
TMR4
TMR2
TMR4
Timer1 is used for all Capture Timer1 and Timer2 are used Timer1 and Timer2 are used
for Capture and Compare or
all CCP modules. Timer2 is PWM operations for CCP1 PWM operations for CCP1
used for PWM operations for only (depending on selected and CCP2 only (depending on
Timer3 is used for all Capture
and Compare operations for
all CCP modules. Timer4 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common time
base.
and Compare operations for for Capture and Compare or
the mode selected for each
module). Both modules may
use a timer as a common time
base if they are both in
Capture/Compare or PWM
modes.
all CCP modules. Modules mode).
may share either timer
All other modules use either
resource as a common time
base.
Timer3 or Timer4. Modules
may share either timer
Timer3 and Timer4 are not resource as a common time
Timer1 and Timer2 are not
available.
available.
base, if they are in Capture/
Compare or PWM modes.
The other modules use either
Timer3 or Timer4. Modules
may share either timer
resource as a common time
base if they are in Capture/
Compare or PWM modes.
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16.2.3
SOFTWARE INTERRUPT
16.2 Capture Mode
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in operating mode.
In Capture mode, CCPR1H:CCPR1L captures the 16-bit
value of the TMR1 or TMR3 registers when an event
occurs on pin RC2/CCP1. An event is defined as one of
the following:
• every falling edge
• every rising edge
16.2.4
CCP PRESCALER
• every 4th rising edge
• every 16th rising edge
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
The event is selected by control bits, CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit, CCP1IF (PIR1<2>), is set; it must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten by the new captured value.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a
non-zero prescaler. Example 16-1 shows the
16.2.1
CCP PIN CONFIGURATION
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC<2> bit.
Note:
If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
EXAMPLE 16-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF
CCP1CON, F ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
16.2.2
TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode,
or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work. The
timer to be used with each CCP module is selected in the
T3CON register (see Section 16.1.1 “CCP Modules
and Timer Resources”).
; value and CCP ON
; Load CCP1CON with
; this value
MOVWF CCP1CON
FIGURE 16-2:
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
TMR3L
CCPR1L
TMR1L
Set Flag bit CCP1IF
T3CCP2
TMR3
Enable
Prescaler
1, 4, 16
CCP1 pin
CCPR1H
TMR1
and
Edge Detect
Enable
T3CCP2
TMR1H
CCP1CON<3:0>
Q’s
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16.3.2
TIMER1/TIMER3 MODE SELECTION
16.3 Compare Mode
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 register
pair value or the TMR3 register pair value. When a
match occurs, the CCP1 pin:
• is driven High
16.3.3
SOFTWARE INTERRUPT MODE
• is driven Low
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
• toggles output (high-to-low or low-to-high)
• remains unchanged
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0. At the same time, interrupt
flag bit CCP1IF (CCP2IF) is set.
16.3.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
16.3.1
CCP PIN CONFIGURATION
The special event trigger output of either CCP1 or
CCP2, resets the TMR1 or TMR3 register pair, depend-
ing on which timer resource is currently selected. This
allows the CCPR1 register to effectively be a 16-bit
programmable period register for Timer1 or Timer3.
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
Note:
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
The CCP2 Special Event Trigger will also start an A/D
conversion if the A/D module is enabled.
Note:
The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
FIGURE 16-3:
COMPARE MODE OPERATION BLOCK DIAGRAM
For CCP1 and CCP2 only, the Special Event Trigger will:
Reset Timer1 or Timer3, but not set Timer1 or Timer3 interrupt flag bit
and set bit GO/DONE (ADCON0<2>),
which starts an A/D conversion (CCP2 only)
Special Event Trigger
Set Flag bit CCP1IF
CCPR1H CCPR1L
Comparator
Q
S
R
Output
Logic
Match
RC2/CCP1 pin
TRISC<2>
Output Enable
1
0
CCP1CON<3:0>
Mode Select
T3CCP2
TMR1H TMR1L
TMR3H TMR3L
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TABLE 16-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
0000 0000 0000 0000
0--1 11qq 0--q qquu
IPEN
PSPIF
PSPIE
PSPIP
—
—
ADIF
ADIE
ADIP
CMIE
CMIF
CMIP
—
—
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
EEIE
EEIF
EEIP
TX2IF
TX2IE
TX2IP
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
TMR4IF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111
PIE1
IPR1
PIR2
LVDIF
LVDIE
LVDIP
TMR3IF CCP2IF -0-0 0000 ---0 0000
TMR3IE CCP2IE -0-0 0000 ---0 0000
TMR3IP CCP2IP -1-1 1111 ---1 1111
PIE2
—
—
IPR2
—
—
PIR3
—
RC2IF
RC2IE
RC2IP
CCP5IF CCP4IF CCP3IF --00 0000 --00 0000
PIE3
—
—
TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000
TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111
1111 1111 1111 1111
IPR3
—
—
TRISC
TMR1L
TMR1H
T1CON
TMR3H
TMR3L
T3CON
PORTC Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
Timer3 Register High Byte
Timer3 Register Low Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
(1)
CCPRxL
CCPRxH
Capture/Compare/PWM Register x (LSB)
Capture/Compare/PWM Register x (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
(1)
(1)
CCPxCON
—
—
DCxB1
DCxB0
CCPxM3 CCPxM2 CCPxM1 CCPxM0 --00 0000 --00 0000
Legend:
x= unknown, u= unchanged, – = unimplemented, read as ‘0’.
Shaded cells are not used by Capture and Compare, Timer1 or Timer3.
Note 1: Generic term for all of the identical registers of this name for all CCP modules, where ‘x’ identifies the individual module
(CCP1 through CCP5). Bit assignments and Reset values for all registers of the same generic name are identical.
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16.4.1
PWM PERIOD
16.4 PWM Mode
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
EQUATION 16-1:
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
PWM Period = (PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period].
Figure 16-4 shows a simplified block diagram of the
CCP module in PWM mode.
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 16.4.3
“Setup for PWM Operation”.
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
FIGURE 16-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
Note:
The Timer2 and Timer4 postscalers (see
Section 13.0 “Timer2 Module”) are not
used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
CCPR1H (Slave)
Comparator
16.4.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
Q
R
S
RC2/CCP1
(Note 1)
TMR2
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
EQUATION 16-2:
Note 1: 8-bit timer is concatenated with 2-bit internal Q
clock or 2 bits of the prescaler to create 10-bit
time base.
PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 Prescale Value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
A PWM output (Figure 16-5) has a time base (period)
and a time that the output stays high (duty cycle).
The frequency of the PWM is the inverse of the period
(1/period).
The CCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
doublebuffering is essential for glitchless PWM
operation.
FIGURE 16-5:
PWM OUTPUT
Period
When the CCPR1H and 2-bit latch match TMR2, con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
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The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
16.4.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
EQUATION 16-3:
1. Set the PWM period by writing to the PR2
register.
FOSC
log ---------------
FPWM
= ----------------------------- b i t s
log2
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
PWM Resolution (max)
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
Note:
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 16-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
FFh
4
1
1
3Fh
8
1
1Fh
7
1
FFh
FFh
10
17h
6.58
Maximum Resolution (bits)
14 10
12 10
TABLE 16-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
RCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RI
RBIE
TO
TMR0IF
PD
INT0IF
POR
RBIF
BOR
0000 0000 0000 0000
0--1 11qq 0--q qquu
IPEN
PSPIF
PSPIE
PSPIP
—
—
ADIF
ADIE
ADIP
CMIE
CMIF
CMIP
—
—
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
EEIE
EEIF
EEIP
TX2IF
TX2IE
TX2IP
SSPIF
SSPIE
SSPIP
BCLIF
BCLIE
BCLIP
TMR4IF
TMR4IE
TMR4IP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111
PIE1
IPR1
PIR2
LVDIF
LVDIE
LVDIP
TMR3IF CCP2IF -0-0 0000 ---0 0000
TMR3IE CCP2IE -0-0 0000 ---0 0000
TMR3IP CCP2IP -1-1 1111 ---1 1111
PIE2
—
—
IPR2
—
—
PIR3
—
RC2IF
RC2IE
RC2IP
CCP5IF CCP4IF CCP3IF --00 0000 --00 0000
CCP5IE CCP4IE CCP3IE --00 0000 --00 0000
CCP5IP CCP4IP CCP3IP --11 1111 --11 1111
0000 0000 0000 0000
PIE3
—
—
IPR3
—
—
TMR2
PR2
Timer2 Module Register
Timer2 Module Period Register
1111 1111 1111 1111
T2CON
T3CON
TMR4
PR4
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
RD16
Timer4 Register
0000 0000 uuuu uuuu
1111 1111 uuuu uuuu
Timer4 Period Register
T4CON
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 uuuu uuuu
(1)
CCPRxL
Capture/Compare/PWM Register x (LSB)
Capture/Compare/PWM Register x (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
(1)
CCPRxH
CCPxCON(1)
—
—
DCxB1
DCxB0
CCPxM3 CCPxM2 CCPxM1 CCPxM0 --00 0000 --00 0000
Legend:
x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM, Timer2, or Timer4.
Note 1: Generic term for all of the identical registers of this name for all CCP modules, where ‘x’ identifies the individual module
(CCP1 through CCP5). Bit assignments and Reset values for all registers of the same generic name are identical.
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NOTES:
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17.3 SPI Mode
17.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four modes
of SPI are supported. To accomplish communication,
typically three pins are used:
17.1 Master SSP (MSSP) Module
Overview
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RF7/SS
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
- Full Master mode
FIGURE 17-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
Internal
Data Bus
Read
Write
• Master mode
• Multi-Master mode
• Slave mode
SSPBUF reg
SSPSR reg
17.2 Control Registers
RC4/SDI/SDA
RC5/SDO
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2). The use
of these registers and their individual configuration bits
differ significantly, depending on whether the MSSP
module is operated in SPI or I2C mode.
Shift
Clock
bit0
RF7/SS
Control
Enable
SS
Additional details are provided under the individual
sections.
Edge
Select
2
Clock Select
SSPM3:SSPM0
SMP:CKE
2
4
TMR2 Output
RC3/SCK/
SCL
(
)
2
Edge
Select
TOSC
Prescaler
4, 16, 64
Data to TX/RX in SSPSR
TRIS bit
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SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
17.3.1
REGISTERS
The MSSP module has four registers for SPI mode
operation. These are:
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
• MSSP Control Register 1 (SSPCON1)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1 regis-
ter is readable and writable. The lower 6 bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 17-1: SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
bit 6
SMP: Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
CKE: SPI Clock Select bit
1= Transmit occurs on transition from active to Idle clock state
0= Transmit occurs on transition from Idle to active clock state
Note:
Polarity of clock state is set by the CKP bit (SSPCON1<4>).
bit 5
bit 4
D/A: Data/Address bit
Used in I2C mode only.
P: Stop bit
Used in I2C mode only. This bit is cleared when the MSSP module is disabled,
SSPEN is cleared.
bit 3
bit 2
bit 1
bit 0
S: Start bit
Used in I2C mode only.
R/W: Read/Write bit information
Used in I2C mode only.
UA: Update Address bit
Used in I2C mode only.
BF: Buffer Full Status bit (Receive mode only)
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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REGISTER 17-2: SSPCON1: MSSP CONTROL REGISTER1 (SPI MODE)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
bit 6
WCOL: Write Collision Detect bit (Transmit mode only)
1= The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0= No collision
SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow
(must be cleared in software).
0= No overflow
Note:
In Master mode, the overflow bit is not set, since each new reception (and
transmission) is initiated by writing to the SSPBUF register.
bit 5
bit 4
SSPEN: Synchronous Serial Port Enable bit
1= Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0= Disables serial port and configures these pins as I/O port pins
Note:
When enabled, these pins must be properly configured as input or output.
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level
0= Idle state for clock is a low level
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100= SPI Slave mode, clock = SCK pin, SS pin control enabled
0011= SPI Master mode, clock = TMR2 output/2
0010= SPI Master mode, clock = FOSC/64
0001= SPI Master mode, clock = FOSC/16
0000= SPI Master mode, clock = FOSC/4
Note:
Bit combinations not specifically listed here are either reserved, or implemented in
I2C mode only.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the Write Collision detect bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the follow-
ing write(s) to the SSPBUF register completed
successfully.
17.3.2
OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
Full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally, the MSSP interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 17-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
• Data input sample phase (middle or end of data
output time)
• Clock edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP consists of a Transmit/Receive Shift Regis-
ter (SSPSR) and a Buffer register (SSPBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPBUF holds the data that was written to the
SSPSR until the received data is ready. Once the 8 bits
of data have been received, that byte is moved to the
SSPBUF register. Then, the Buffer Full detect bit, BF
(SSPSTAT<0>) and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP Status register (SSPSTAT)
indicates the various status conditions.
EQUATION 17-1: LOADING THE SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF
BRA LOOP
;Has data been received (transmit complete)?
;No
MOVF SSPBUF, W
;WREG reg = contents of SSPBUF
MOVWF RXDATA
;Save in user RAM, if data is meaningful
MOVF TXDATA, W
MOVWF SSPBUF
;W reg = contents of TXDATA
;New data to transmit
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17.3.3
ENABLING SPI I/O
17.3.4
TYPICAL CONNECTION
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
Figure 17-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit
cleared
• Master sends data–Slave sends dummy data
• Master sends data–Slave sends data
• Master sends dummy data–Slave sends data
• SCK (Slave mode) must have TRISC<3> bit set
• SS must have TRISF<7> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 17-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
SDO
Shift Register
(SSPSR)
Shift Register
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
PROCESSOR 1
PROCESSOR 2
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Figure 17-3, Figure 17-5 and Figure 17-6, where the
MSB is transmitted first. In Master mode, the SPI clock
rate (bit rate) is user-programmable to be one of the
following:
17.3.5
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 17-2) is to
broadcast data by the software protocol.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 17-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
The clock polarity is selected by appropriately program-
ming the CKP bit (SSPCON1<4>). This then, would
give waveforms for SPI communication, as shown in
FIGURE 17-3:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
SDO
(CKE = 0)
bit 7
bit 7
bit 3
bit 3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 cycle
after Q2
SSPSR to
SSPBUF
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longer driven, even if in the middle of a transmitted
byte and becomes a floating output. External pull-up/
pull-down resistors may be desirable, depending on the
application.
17.3.6
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is set
to VDD.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
17.3.7
SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 04h). The pin must not be driven
low for the SS pin to function as an input. The Data
Latch must be high. When the SS pin is low, transmis-
sion and reception are enabled and the SDO pin is
driven. When the SS pin goes high, the SDO pin is no
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function),
since it cannot create a bus conflict.
FIGURE 17-4:
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit 6
bit 7
bit 7
bit 0
SDO
bit 7
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
SSPSR to
SSPBUF
after Q2
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FIGURE 17-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit 6
bit 2
bit 5
bit 4
bit 1
bit 0
SDO
bit 7
bit 3
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2
SSPSR to
SSPBUF
FIGURE 17-6:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
bit 6
bit 2
bit 5
bit 4
bit 1
bit 0
SDO
bit 7
bit 7
bit 3
SDI
(SMP = 0)
bit 0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2
SSPSR to
SSPBUF
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17.3.8
SLEEP OPERATION
17.3.10 BUS MODE COMPATIBILITY
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1: SPI BUS MODES
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
17.3.9
EFFECTS OF A RESET
There is also an SMP bit, which controls when the data
is sampled.
A Reset disables the MSSP module and terminates the
current transfer.
TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111
1111 1111 1111 1111
PIE1
IPR1
TRISC
TRISF
PORTC Data Direction Register
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3
Synchronous Serial Port Receive Buffer/Transmit Register
TRISF2
TRISF1 TRISF0 1111 1111 uuuu uuuu
xxxx xxxx uuuu uuuu
SSPBUF
SSPCON
SSPSTAT
Legend:
WCOL
SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1 SSPM0 0000 0000 0000 0000
UA
BF
0000 0000 0000 0000
x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
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2
17.4.1
REGISTERS
17.4 I C Mode
The MSSP module has six registers for I2C operation.
These are:
The MSSP module in I2C mode fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on Start and Stop bits in
hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) – Not directly
accessible
Two pins are used for data transfer:
• Serial clock (SCL) – RC3/SCK/SCL
• Serial data (SDA) – RC4/SDI/SDA
• MSSP Address Register (SSPADD)
SSPCON, SSPCON2 and SSPSTAT are the control
and status registers in I2C mode operation. The
SSPCON and SSPCON2 registers are readable and
writable. The lower six bits of the SSPSTAT are
read-only. The upper two bits of the SSPSTAT are
read/write.
The user must configure these pins as inputs or outputs
through the TRISC<4:3> bits.
FIGURE 17-7:
MSSP BLOCK DIAGRAM
(I2C MODE)
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
Internal
Data Bus
Read
Write
SSPADD register holds the slave device address
when the SSP is configured in I2C Slave mode. When
the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the Baud Rate
Generator reload value.
SSPBUF reg
RC3/SCK/SCL
Shift
Clock
In receive operations, SSPSR and SSPBUF together,
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
SSPSR reg
RC4/
SDI/
SDA
MSb
LSb
Addr Match
Match Detect
SSPADD reg
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
Set, Reset
S, P bits
(SSPSTAT reg)
Start and
Stop bit Detect
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REGISTER 17-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
bit 6
bit 5
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high-speed mode (400 kHz)
CKE: SMBus Select bit
In Master or Slave mode:
1= Enable SMBus specific inputs
0= Disable SMBus specific inputs
D/A: Data/Address bit
In Master mode:
Reserved.
In Slave mode:
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
bit 4
bit 3
bit 2
P: Stop bit
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
Note:
This bit is cleared on Reset and when SSPEN is cleared.
S: Start bit
1= Indicates that a Start bit has been detected last
0= Start bit was not detected last
Note:
This bit is cleared on Reset and when SSPEN is cleared.
R/W: Read/Write bit Information (I2C mode only)
In Slave mode:
1= Read
0= Write
Note:
This bit holds the R/W bit information following the last address match. This bit is only
valid from the address match to the next Start bit, Stop bit, or not ACK bit.
In Master mode:
1= Transmit is in progress
0= Transmit is not in progress
Note:
ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is
in active mode.
bit 1
bit 0
UA: Update Address bit (10-bit Slave mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
In Transmit mode:
1= SSPBUF is full
0= SSPBUF is empty
In Receive mode:
1= SSPBUF is full (does not include the ACK and Stop bits)
0= SSPBUF is empty (does not include the ACK and Stop bits)
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
In Master Transmit mode:
1= A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started (must be cleared in software)
0= No collision
In Slave Transmit mode:
1= The SSPBUF register is written while it is still transmitting the previous word (must be
cleared in software)
0= No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
bit 6
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1= A byte is received while the SSPBUF register is still holding the previous byte (must be
cleared in software)
0= No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
bit 5
bit 4
SSPEN: Synchronous Serial Port Enable bit
1= Enables the serial port and configures the SDA and SCL pins as the serial port pins
0= Disables serial port and configures these pins as I/O port pins
Note:
When enabled, the SDA and SCL pins must be properly configured as input or output.
CKP: SCK Release Control bit
In Slave mode:
1= Release clock
0= Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
1111= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
1110= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1011= I2C Firmware Controlled Master mode (Slave Idle)
1000= I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))
0111= I2C Slave mode, 10-bit address
0110= I2C Slave mode, 7-bit address
Note:
Bit combinations not specifically listed here are either reserved or implemented in
SPI mode only.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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REGISTER 17-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE)
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
ACKSTAT
ACKDT
ACKEN
bit 7
bit 0
bit 7
bit 6
bit 5
GCEN: General Call Enable bit (Slave mode only)
1= Enable interrupt when a general call address (0000h) is received in the SSPSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1= Not Acknowledge
0= Acknowledge
Note:
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
bit 4
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1= Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence Idle
bit 3
bit 2
bit 1
bit 0
RCEN: Receive Enable bit (Master mode only)
1= Enables Receive mode for I2C
0= Receive Idle
PEN: Stop Condition Enable bit (Master mode only)
1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0= Stop condition Idle
RSEN: Repeated Start Condition Enabled bit (Master mode only)
1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enabled/Stretch Enabled bit
In Master mode:
1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Start condition Idle
In Slave mode:
1= Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled)
0= Clock stretching is disabled
Note:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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17.4.2
OPERATION
17.4.3.1
Addressing
The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON<5>).
The SSPCON1 register allows control of the I2C oper-
ation. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
• I2C Master mode, clock = (FOSC/4) x (SSPADD + 1)
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All incom-
ing bits are sampled with the rising edge of the clock
(SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
• I2C Slave mode (7-bit address), with Start and
Stop bit interrupts enabled
• I2C Slave mode (10-bit address), with Start and
Stop bit interrupts enabled
• I2C Firmware Controlled Master mode, slave is
Idle
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits. To ensure proper operation
of the module, pull-up resistors must be provided
externally to the SCL and SDA pins.
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit BF is set.
3. An ACK pulse is generated.
4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is
set (interrupt is generated, if enabled) on the
falling edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two
MSbs of the address. The sequence of events for
10-bit address is as follows, with steps 7 through 9 for
the slave-transmitter:
17.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
1. Receive first (high) byte of address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
5. Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit UA.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
• The Buffer Full bit BF (SSPSTAT<0>) was set
before the transfer was received.
7. Receive Repeated Start condition.
• The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
and parameter #101.
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17.4.3.2
Reception
17.4.3.3
Transmission
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low, regardless of SEN (see Section 17.4.4 “Clock
Stretching”, for more detail). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data. The
transmit data must be loaded into the SSPBUF register,
which also loads the SSPSR register. Then pin RC3/
SCK/SCL should be enabled by setting bit CKP
(SSPCON1<4>). The eight data bits are shifted out on
the falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 17-9).
When the address byte overflow condition exists, then
the no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON1<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
If SEN is enabled (SSPCON1<0> = 1), RC3/SCK/SCL
will be held low (clock stretch) following each data
transfer. The clock must be released by setting bit
CKP (SSPCON<4>). See Section 17.4.4 “Clock
Stretching” for more detail.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is
complete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT regis-
ter) and the slave monitors for another occurrence of
the Start bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, pin RC3/SCK/SCL must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
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FIGURE 17-8:
I C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
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FIGURE 17-9:
I C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
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FIGURE 17-10:
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
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FIGURE 17-11:
I C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
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17.4.4
CLOCK STRETCHING
17.4.4.3
Clock Stretching for 7-bit Slave
Transmit Mode
Both 7- and 10-bit Slave modes implement automatic
clock stretching during a transmit sequence.
7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the
ninth clock, if the BF bit is clear. This occurs,
regardless of the state of the SEN bit.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.
The user’s ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 17-9).
17.4.4.1
Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPCON1 register is
automatically cleared, forcing the SCL output to be
held low. The CKP being cleared to ‘0’ will assert the
SCL line low. The CKP bit must be set in the user’s
ISR before reception is allowed to continue. By holding
the SCL line low, the user has time to service the ISR
and read the contents of the SSPBUF before the
master device can initiate another receive sequence.
This will prevent buffer overruns from occurring (see
Figure 17-13).
Note 1: If the user loads the contents of SSPBUF,
setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.
2: The CKP bit can be set in software,
regardless of the state of the BF bit.
17.4.4.4
Clock Stretching for 10-bit Slave
Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence, which contains the high-order bits
of the 10-bit address and the R/W bit set to ‘1’. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode and clock stretching is controlled as in 7-bit
Slave Transmit mode (see Figure 17-11).
Note 1: If the user reads the contents of the
SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.
2: The CKP bit can be set in software,
regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence, in order to prevent an overflow
condition.
17.4.4.2
Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)
In 10-bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
‘0’. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence, as described in 7-bit mode.
Note:
If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs and if
the user hasn’t cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a
data sequence, not an address sequence.
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already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum high time requirement for SCL (see
Figure 17-12).
17.4.4.5
Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already sam-
pled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
FIGURE 17-12:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
DX
DX-1
Master device
asserts clock
CKP
Master device
deasserts clock
WR
SSPCON
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FIGURE 17-13:
I C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
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FIGURE 17-14:
I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)
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If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit) and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
17.4.5
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set and the slave will begin receiving data after the
Acknowledge (Figure 17-15).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all ‘0’s with R/W = 0.
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is enabled (SSPCON2<7>
set). Following a Start bit detect, 8 bits are shifted into
the SSPSR and the address is compared against the
SSPADD. It is also compared to the general call
address and fixed in hardware.
FIGURE 17-15:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
Address is compared to General Call Address
after ACK, set interrupt
Receiving Data
D5 D4 D3 D2 D1
ACK
R/W = 0
General Call Address
ACK
SDA
SCL
D7 D6
D0
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
9
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
GCEN (SSPCON2<7>)
‘0’
‘1’
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17.4.6
MASTER MODE
Note:
The MSSP module, when configured in
I2C Master mode, does not allow queueing
of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start condi-
tion is complete. In this case, the SSPBUF
will not be written to and the WCOL bit will
be set, indicating that a write to the
SSPBUF did not occur.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset, or when the MSSP module is disabled.
Control of the I2C bus may be taken when the P bit is
set or the bus is Idle, with both the S and P bits clear.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP interrupt if enabled):
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit conditions.
• Start Condition
Once Master mode is enabled, the user has six
options.
• Stop Condition
• Data Transfer Byte Transmitted/received
• Acknowledge Transmit
• Repeated Start
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Configure the I2C port to receive data.
5. Generate an Acknowledge condition at the end
of a received byte of data.
6. Generate a Stop condition on SDA and SCL.
2
FIGURE 17-16:
MSSP BLOCK DIAGRAM (I C MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
SDA
Shift
Clock
SDA In
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate
SCL
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL In
Bus Collision
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
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I2C Master Mode Operation
A typical transmit sequence would go as follows:
17.4.6.1
1. The user generates a Start condition by setting
the Start enable bit, SEN (SSPCON2<0>).
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
2. SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
3. The user loads the SSPBUF with the slave
address to transmit.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
4. Address is shifted out the SDA pin until all 8 bits
are transmitted.
5. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
6. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an Acknowledge bit is transmitted.
Start and Stop conditions indicate the beginning and
end of transmission.
7. The user loads the SSPBUF with eight bits of
data.
8. Data is shifted out the SDA pin until all 8 bits are
transmitted.
9. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
10. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The Baud Rate Generator used for the SPI mode
operation is used to set the SCL clock frequency for
either 100 kHz, 400 kHz or 1 MHz I2C operation. See
Section 17.4.7 “Baud Rate Generator”, for more
information.
11. The user generates a Stop condition by setting
the Stop enable bit PEN (SSPCON2<2>).
12. Interrupt is generated once the Stop condition is
complete.
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Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
17.4.7
BAUD RATE GENERATOR
In I2C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically.
Table 15-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 17-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
BRG Down Counter
CLKO
FOSC/4
TABLE 17-3: I2C CLOCK RATE W/BRG
FSCL
FCY
FCY*2
BRG VALUE
(2 rollovers of BRG)
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
19h
20h
3Fh
0Ah
0Dh
28h
03h
0Ah
00h
400 kHz(1)
312.5 kHz
100 kHz
400 kHz(1)
308 kHz
100 kHz
333 kHz(1)
100 kHz
1 MHz(1)
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
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SCL pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and
begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count, in the
event that the clock is held low by an external device
(Figure 15-18).
17.4.7.1
Clock Arbitration
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
deasserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the
FIGURE 17-18:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL allowed to transition high
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
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17.4.8
I2C MASTER MODE START
CONDITION TIMING
17.4.8.1
WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
To initiate a Start condition, the user sets the Start Con-
dition Enable bit, SEN (SSPCON2<0>). If the SDA and
SCL pins are sampled high, the Baud Rate Generator
is reloaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the Baud Rate Generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low, while SCL is high, is the Start condition and
causes the S bit (SSPSTAT<3>) to be set. Following
this, the Baud Rate Generator is reloaded with the con-
tents of SSPADD<6:0> and resumes its count. When
the Baud Rate Generator times out (TBRG), the SEN bit
(SSPCON2<0>) will be automatically cleared by
hardware, the Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
Note:
If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I2C module is reset into its Idle state.
FIGURE 17-19:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
At completion of Start bit,
Write to SEN bit occurs here
SDA = 1,
SCL = 1
hardware clears SEN bit
and sets SSPIF bit
TBRG
TBRG
Write to SSPBUF occurs here
1st bit
2nd bit
SDA
TBRG
SCL
TBRG
S
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Immediately following the setting of the SSPIF bit, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).
17.4.9
I2C MASTER MODE REPEATED
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
(SSPCON2<1>) is programmed high and the I2C logic
module is in the Idle state. When the RSEN bit is set,
the SCL pin is asserted low. When the SCL pin is sam-
pled low, the Baud Rate Generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one Baud Rate
Generator count (TBRG). When the Baud Rate Genera-
tor times out, if SDA is sampled high, the SCL pin will
be deasserted (brought high). When SCL is sampled
high, the Baud Rate Generator is reloaded with the
contents of SSPADD<6:0> and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
17.4.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated Start
sequence is in progress, the WCOL is set and the
contents of the buffer are unchanged (the write does
not occur).
Note:
Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
Start condition is complete.
(SDA = 0) for one TBRG while SCL is high. Following
,
this, the RSEN bit (SSPCON2<1>) will be automatically
cleared and the Baud Rate Generator will not be
reloaded, leaving the SDA pin held low. As soon as a
Start condition is detected on the SDA and SCL pins,
the S bit (SSPSTAT<3>) will be set. The SSPIF bit will
notbesetuntiltheBaudRateGeneratorhastimedout.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL goes
from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data ‘1’.
FIGURE 17-20:
REPEAT START CONDITION WAVEFORM
S bit set by hardware (SSPSTAT<3>)
Write to SSPCON2
occurs here.
SDA = 1,
SCL (no change).
SDA = 1,
SCL = 1
At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF
TBRG
TBRG
TBRG
1st bit
SDA
Write to SSPBUF occurs here
TBRG
Falling edge of ninth clock
End of Xmit
SCL
TBRG
RSEN bit set
Sr = Repeated Start
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17.4.10 I2C MASTER MODE
17.4.10.3 ACKSTAT Status Flag
TRANSMISSION
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0) and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
Transmission of a data byte, a 7-bit address, or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification parameter
#106). SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high (see data setup time specification
parameter #107). When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time, after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received prop-
erly. The status of ACK is written into the ACKDT bit on
the falling edge of the ninth clock. If the master receives
an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 17-21).
17.4.11 I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN (SSPCON2<3>).
Note:
The MSSP module must be in an Idle state
before the RCEN bit is set, or the RCEN
bit will be disregarded.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes (high-to-low/
low-to-high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bit is set and the Baud Rate Gener-
ator is suspended from counting, holding SCL low. The
MSSP is now in Idle state, awaiting the next command.
When the buffer is read by the CPU, the BF flag bit is
automatically cleared. The user can then send an
Acknowledge bit at the end of reception by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>).
17.4.11.1 BF Status Flag
After the write to the SSPBUF, each address bit will be
shifted out on the falling edge of SCL, until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock, the master will deassert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared and the Baud Rate Generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
17.4.11.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
17.4.11.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
17.4.10.1 BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.
17.4.10.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
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2
FIGURE 17-21:
I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
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FIGURE 17-22:
I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
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17.4.12 ACKNOWLEDGE SEQUENCE
TIMING
17.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the Baud Rate Generator is reloaded and
counts down to ‘0’. When the Baud Rate Generator
times out, the SCL pin will be brought high and one
TBRG (Baud Rate Generator rollover count) later, the
SDA pin will be deasserted. When the SDA pin is sam-
pled high while SCL is high, the P bit (SSPSTAT<4>) is
set. A TBRG later, the PEN bit is cleared and the SSPIF
bit is set (Figure 17-24).
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 17-23).
17.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
17.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 17-23:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
TBRG
SDA
SCL
D0
ACK
8
9
SSPIF
Cleared in
software
SSPIF set at the end
of Acknowledge sequence
SSPIF set at the end
of receive
Cleared in
software
Note:
TBRG = one Baud Rate Generator period.
FIGURE 17-24:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1for TBRG, followed by SDA = 1for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
Write to SSPCON2
Set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
ACK
SDA
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
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17.4.14 SLEEP OPERATION
17.4.17 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
While in Sleep mode, the I2C module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 17-25).
17.4.15 EFFECT OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
17.4.16 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit (SSPSTAT<4>) is set, or the
bus is idle with both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the Stop condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
In multi-master operation, the SDA line must be moni-
tored for arbitration, to see if the signal level is the
expected output level. This check is performed in
hardware, with the result placed in the BCLIF bit.
If a Start, Repeated Start, Stop, or Acknowledge condi-
tion was in progress when the bus collision occurred,
the condition is aborted, the SDA and SCL lines are
deasserted and the respective control bits in the
SSPCON2 register are cleared. When the user ser-
vices the bus collision Interrupt Service Routine and if
the I2C bus is free, the user can resume communication
by asserting a Start condition.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
• A Repeated Start Condition
• An Acknowledge Condition
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determi-
nation of when the bus is free. Control of the I2C bus can
be taken when the P bit is set in the SSPSTAT register, or
the bus is Idle and the S and P bits are cleared.
FIGURE 17-25:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
SDA line pulled low
by another source
Data changes
while SCL = 0
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
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If the SDA pin is sampled low during this count, the
17.4.17.1 Bus Collision During a Start
Condition
BRG is reset and the SDA line is asserted early
(Figure 17-28). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to ‘0’ and during this time, if the SCL pin
is sampled as ‘0’, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 17-26).
b) SCL is sampled low before SDA is asserted low
(Figure 17-27).
During a Start condition, both the SDA and the SCL
pins are monitored.
Note:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus colli-
sion because the two masters must be
allowed to arbitrate the first address fol-
lowing the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
•
the MSSP module is reset to its Idle state
(Figure 17-26).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to ‘0’. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
FIGURE 17-26:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
SSP module reset into Idle state.
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
BCLIF
SSPIF and BCLIF are
cleared in software
S
SSPIF
SSPIF and BCLIF are
cleared in software
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FIGURE 17-27:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0before SDA = 0,
bus collision occurs. Set BCLIF.
SCL = 0before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
in software
S
‘0’
‘0’
‘0’
‘0’
SSPIF
FIGURE 17-28:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
S
SCL pulled low after BRG
Time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
‘0’
BCLIF
S
SSPIF
Interrupts cleared
in software
SDA = 0, SCL = 1
Set SSPIF
2003-2013 Microchip Technology Inc.
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If SDA is low, a bus collision has occurred (i.e., another
17.4.17.2 Bus Collision During a Repeated
Start Condition
master is attempting to transmit a data ‘0’, Figure 17-29).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
Figure 17-30.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user deasserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to ‘0’. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is complete.
FIGURE 17-29:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
‘0’
S
‘0’
SSPIF
FIGURE 17-30:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL.
BCLIF
RSEN
Interrupt cleared
in software
‘0’
S
SSPIF
DS39609C-page 194
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The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to ‘0’. After the BRG times out, SDA
is sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 17-31). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 17-32).
17.4.17.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 17-31:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
TBRG
TBRG
TBRG
low after TBRG,
set BCLIF
SDA
SDA asserted low
SCL
PEN
BCLIF
P
‘0’
‘0’
SSPIF
FIGURE 17-32:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
‘0’
‘0’
SSPIF
2003-2013 Microchip Technology Inc.
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NOTES:
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Register 18-1 shows the layout of the Transmit Status
18.0 ADDRESSABLE UNIVERSAL
and Control registers (TXSTAx) and Register 18-2
shows the layout of the Receive Status and Control
registers (RCSTAx). USART1 and USART2 each have
their own independent and distinct pairs of transmit and
receive control registers, which are identical to each
other apart from their names. Similarly, each USART
has its own distinct set of transmit, receive and baud
rate registers.
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module (also known as a Serial
Communications Interface or SCI) is one of the two
types of serial I/O modules available on PIC18FXX20
devices. Each device has two USARTs, which can be
configured independently of each other. Each can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices, such as
CRT terminals and personal computers, or as a half-
duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
Note:
Throughout this section, references to
register and bit names that may be associ-
ated with a specific USART module are
referred to generically by the use of ‘x’ in
place of the specific module number.
Thus, “RCSTAx” might refer to the receive
status register for either USART1 or
USART2.
The USART can be configured in the following modes:
• Asynchronous (full-duplex)
• Synchronous – Master (half-duplex)
• Synchronous – Slave (half-duplex)
The pins of USART1 and USART2 are multiplexed with
the functions of PORTC (RC6/TX1/CK1 and RC7/RX1/
DT1) and PORTG (RG1/TX2/CK2 and RG2/RX2/DT2),
respectively. In order to configure these pins as a
USART:
• For USART1:
- bit SPEN (RCSTA1<7>) must be set (= 1)
- bit TRISC<7> must be set (= 1)
- bit TRISC<6> must be cleared (= 0) for
Asynchronous and Synchronous Master
modes
- bit TRISC<6> must be set (= 1) for
Synchronous Slave mode
• For USART2:
- bit SPEN (RCSTA2<7>) must be set (= 1)
- bit TRISG<2> must be set (= 1)
- bit TRISG<1> must be cleared (= 0) for
Asynchronous and Synchronous Master
modes
- bit TRISC<6> must be set (= 1) for
Synchronous Slave mode
2003-2013 Microchip Technology Inc.
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REGISTER 18-1: TXSTAx: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
R/W-0
TX9D
TRMT
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note:
SREN/CREN overrides TXEN in Sync mode.
bit 4
SYNC: USART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3
bit 2
Unimplemented: Read as ‘0’
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode.
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of Transmit Data
Can be address/data bit or a parity bit.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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REGISTER 18-2: RCSTAx: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0= Serial port disabled
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enables interrupt and load of the receive buffer when RSR<8>
is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003-2013 Microchip Technology Inc.
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Example 18-1 shows the calculation of the baud rate
error for the following conditions:
18.1 USART Baud Rate Generator
(BRG)
• FOSC = 16 MHz
• Desired Baud Rate = 9600
• BRGH = 0
The BRG supports both the Asynchronous and
Synchronous modes of the USARTs. It is a dedicated
8-bit Baud Rate Generator. The SPBRG register
controls the period of a free running 8-bit timer. In Asyn-
chronous mode, bit BRGH (TXSTAx<2>) also controls
the baud rate. In Synchronous mode, bit BRGH is
ignored. Table 18-1 shows the formula for computation
of the baud rate for different USART modes, which only
apply in Master mode (internal clock).
• SYNC = 0
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the equation in Example 18-1 can reduce the
baud rate error in some cases.
Writing a new value to the SPBRGx register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRGx register can be calcu-
lated using the formula in Table 18-1. From this, the
error in baud rate can be determined.
18.1.1
SAMPLING
The data on the RXx pin (either RC7/RX1/DT1 or RG2/
RX2/DT2) is sampled three times by a majority detect
circuit to determine if a high or a low level is present at
the pin.
EXAMPLE 18-1:
CALCULATING BAUD RATE ERROR
Desired Baud Rate
=
FOSC/(64 (X + 1))
Solving for X:
X
X
X
=
=
=
((FOSC/Desired Baud Rate)/64 ) – 1
((16000000/9600)/64) – 1
[25.042] = 25
Calculated Baud Rate
=
=
16000000/(64 (25 + 1))
9615
Error
=
(Calculated Baud Rate – Desired Baud Rate)
Desired Baud Rate
=
=
(9615 – 9600)/9600
0.16%
TABLE 18-1: BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X + 1))
(Synchronous) Baud Rate = FOSC/(4(X + 1))
Baud Rate = FOSC/(16(X + 1))
N/A
Legend: X = value in SPBRGx (0 to 255)
TABLE 18-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TXSTAx
RCSTAx
CSRC
SPEN
TX9
RX9
TXEN SYNC
—
BRGH TRMT TX9D 0000 -010
0000 -010
0000 000x
0000 0000
SREN CREN ADDEN FERR OERR RX9D 0000 000x
0000 0000
Legend: x= unknown, – = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
SPBRGx Baud Rate Generator Register
Note 1: Register names generically refer to both of the identically named registers for the two USART modules,
where ‘x’ indicates the particular module. Bit names and Reset values are identical between modules.
DS39609C-page 200
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TABLE 18-3: BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 40 MHz
33 MHz
25 MHz
20 MHz
BAUD
RATE
(Kbps)
SPBRG
value
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
KBAUD ERROR
KBAUD ERROR
KBAUD
ERROR
KBAUD ERROR
(decimal)
0.3
1.2
NA
NA
-
-
-
NA
NA
-
-
-
NA
NA
-
-
-
NA
NA
-
-
-
-
-
-
-
2.4
NA
-
-
NA
-
-
NA
-
-
NA
-
-
9.6
NA
-
-
NA
-
-
-
NA
-
-
-
NA
-
-
19.2
76.8
96
NA
-
-
NA
-
NA
-
NA
-
-
76.92
96.15
303.03
500
+0.16
129
103
32
19
0
77.10
95.93
294.64
485.30
8250
32.23
+0.39
-0.07
-1.79
-2.94
-
106
85
27
16
0
77.16
96.15
297.62
480.77
6250
24.41
+0.47
+0.16
-0.79
-3.85
-
80
64
20
12
0
76.92
96.15
294.12
500
+0.16
64
51
16
9
+0.16
+0.16
300
500
HIGH
LOW
+1.01
-1.96
0
-
0
-
10000
39.06
5000
19.53
0
-
255
-
255
-
255
-
255
FOSC = 16 MHz
SPBRG
10 MHz
7.15909 MHz
5.0688 MHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
%
%
%
%
value
KBAUD ERROR
KBAUD ERROR
KBAUD
ERROR
KBAUD ERROR
(decimal)
(decimal)
0.3
1.2
NA
NA
-
-
-
NA
NA
-
-
-
NA
NA
-
-
-
-
NA
NA
-
-
-
-
-
-
2.4
NA
-
-
NA
-
-
NA
-
-
NA
-
-
9.6
NA
-
+0.16
+0.16
-0.79
+2.56
0
-
NA
-
+0.16
-1.36
+0.16
+4.17
0
-
9.62
+0.23
+0.23
+1.32
-1.88
-0.57
-10.51
-
185
92
22
18
5
9.60
0
0
131
65
16
12
3
19.2
76.8
96
19.23
76.92
95.24
307.70
500
207
51
41
12
7
19.23
75.76
96.15
312.50
500
129
32
25
7
19.24
77.82
94.20
298.35
447.44
1789.80
6.99
19.20
74.54
97.48
316.80
422.40
1267.20
4.95
-2.94
+1.54
+5.60
-15.52
-
300
500
HIGH
LOW
4
3
2
4000
15.63
-
0
2500
9.77
-
0
0
0
-
255
-
255
-
255
-
255
FOSC = 4 MHz
3.579545 MHz
1 MHz
32.768 kHz
BAUD
RATE
(Kbps)
SPBRG
value
SPBRG
value
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
KBAUD ERROR
KBAUD ERROR
KBAUD
ERROR
KBAUD ERROR
(decimal)
(decimal)
0.3
1.2
NA
NA
-
-
-
NA
NA
-
-
-
-
NA
1.20
2.40
9.62
19.23
83.33
83.33
250
-
-
207
103
25
12
2
0.30
1.17
2.73
8.20
NA
+1.14
26
-
-
+0.16
+0.16
+0.16
+0.16
+8.51
-13.19
-16.67
-
-2.48
6
2.4
NA
-
NA
-
-
+13.78
2
9.6
9.62
19.23
76.92
1000
333.33
500
+0.16
+0.16
+0.16
+4.17
+11.11
0
103
51
12
9
9.62
+0.23
-0.83
-2.90
+3.57
-0.57
-10.51
-
92
46
11
8
-14.67
0
19.2
76.8
96
19.04
74.57
99.43
298.30
447.44
894.89
3.50
-
-
-
-
-
-
-
-
NA
-
2
NA
-
300
500
HIGH
LOW
2
2
0
NA
-
-
1
1
NA
-
NA
1000
3.91
-
0
0
250
-
0
8.20
0.03
0
-
255
-
255
0.98
-
255
255
2003-2013 Microchip Technology Inc.
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TABLE 18-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 40 MHz
33 MHz
25 MHz
20 MHz
BAUD
RATE
(Kbps)
SPBRG
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
value
KBAUD ERROR
KBAUD
ERROR
KBAUD
ERROR
KBAUD ERROR
(decimal)
0.3
1.2
NA
NA
-
-
-
-
NA
NA
-
-
-
-
NA
NA
-
-
-
NA
NA
-
-
-
-
-
2.4
NA
-
-
2.40
-0.07
-0.54
-0.54
-4.09
+7.42
-14.06
-
214
53
26
6
2.40
9.53
19.53
78.13
97.66
NA
-0.15
162
40
19
4
2.40
+0.16
-1.36
+1.73
+1.73
+8.51
+4.17
-
129
32
15
3
9.6
9.62
18.94
78.13
89.29
312.50
625
+0.16
-1.36
+1.73
-6.99
+4.17
+25.00
-
64
32
7
9.55
-0.76
9.47
19.2
76.8
96
19.10
73.66
103.13
257.81
NA
+1.73
19.53
78.13
104.17
312.50
NA
+1.73
6
4
+1.73
3
2
300
500
HIGH
LOW
1
1
-
-
-
-
-
0
0
-
NA
-
-
625
0
515.63
2.01
-
0
390.63
1.53
0
312.50
1.22
-
0
2.44
-
255
-
255
255
-
255
FOSC = 16 MHz
SPBRG
10 MHz
7.15909 MHz
5.0688 MHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
%
%
%
%
value
KBAUD ERROR
KBAUD
ERROR
KBAUD
ERROR
KBAUD ERROR
(decimal)
(decimal)
0.3
1.2
NA
1.20
2.40
9.62
19.23
83.33
83.33
250
-
-
207
103
25
12
2
NA
1.20
-
-
129
64
15
7
NA
1.20
2.38
9.32
18.64
111.86
NA
-
-
92
46
11
5
NA
1.20
2.40
9.90
19.80
79.20
NA
-
-
65
32
7
+0.16
+0.16
+0.16
+0.16
+8.51
-13.19
-16.67
-
+0.16
+0.16
+1.73
+1.73
+1.73
-18.62
-47.92
-
+0.23
0
2.4
2.40
-0.83
0
9.6
9.77
-2.90
+3.13
19.2
76.8
96
19.53
78.13
78.13
156.25
NA
-2.90
+3.13
3
1
+45.65
0
+3.13
0
2
1
-
-
-
-
-
-
-
-
-
-
-
-
300
500
HIGH
LOW
0
0
NA
-
NA
-
NA
-
-
NA
-
NA
-
250
-
0
156.25
0.61
-
0
111.86
0.44
0
79.20
0.31
0
0.98
-
255
-
255
255
255
FOSC = 4 MHz
3.579545 MHz
1 MHz
32.768 kHz
BAUD
RATE
(Kbps)
SPBRG
value
SPBRG
value
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
KBAUD ERROR
KBAUD
ERROR
KBAUD
ERROR
KBAUD ERROR
(decimal)
(decimal)
0.3
1.2
0.30
1.20
2.40
8.93
20.83
62.50
NA
-0.16
207
51
25
6
0.30
1.19
2.43
9.32
18.64
55.93
NA
+0.23
185
46
22
5
0.30
1.20
2.23
7.81
15.63
NA
+0.16
51
12
6
0.26
NA
-14.67
1
+1.67
-0.83
+0.16
-
-
-
-
-
-
-
-
-
-
-
2.4
+1.67
+1.32
-6.99
NA
-
9.6
-6.99
-2.90
-18.62
1
NA
-
19.2
76.8
96
+8.51
2
-2.90
2
-18.62
0
NA
-
-18.62
0
-27.17
0
-
-
-
-
-
-
-
NA
-
-
-
-
-
-
-
-
-
-
-
-
-
NA
-
NA
-
300
500
HIGH
LOW
NA
-
NA
-
NA
-
NA
-
-
NA
-
NA
-
NA
-
NA
62.50
0.24
0
55.93
0.22
0
15.63
0.06
0
0.51
0.002
0
255
255
255
255
DS39609C-page 202
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 40 MHz
33 MHz
25 MHz
20 MHz
BAUD
RATE
(Kbps)
SPBRG
SPBRG
value
(decimal)
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
value
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
(decimal)
0.3
1.2
NA
NA
-
-
-
NA
NA
-
-
-
-
NA
NA
-
-
-
NA
NA
-
-
-
-
-
-
2.4
NA
-
-
NA
-
-
NA
-
-
NA
-
-
9.6
NA
-
+0.16
-1.36
+0.16
+4.17
0
-
9.60
-0.07
+0.39
-0.54
+2.31
-1.79
+3.13
-
214
106
26
20
6
9.59
-0.15
+0.47
+1.73
+1.73
+4.17
+4.17
-
162
80
19
15
4
9.62
+0.16
+0.16
+1.73
+0.16
+4.17
-16.67
-
129
64
15
12
3
19.2
76.8
96
19.23
75.76
96.15
312.50
500
129
32
25
7
19.28
76.39
98.21
294.64
515.63
2062.50
8,06
19.30
78.13
97.66
312.50
520.83
1562.50
6.10
19.23
78.13
96.15
312.50
416.67
1250
4.88
300
500
HIGH
LOW
4
3
2
2
2500
9.77
-
0
0
0
0
-
255
-
255
-
255
-
255
FOSC = 16 MHz
SPBRG
10 MHz
7.15909 MHz
5.0688 MHz
BAUD
RATE
(Kbps)
SPBRG
value
(decimal)
SPBRG
value
SPBRG
value
%
%
%
%
value
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
(decimal)
(decimal)
(decimal)
0.3
1.2
NA
NA
-
-
-
NA
NA
-
-
-
-
NA
NA
-
-
-
-
NA
NA
-
-
-
-
-
2.4
NA
-
+0.16
+0.16
+0.16
+4.17
+11.11
0
-
NA
-
-
2.41
+0.23
-0.83
+1.32
-2.90
-6.78
+49.15
-10.51
-
185
46
22
5
2.40
0
131
32
16
3
9.6
9.62
19.23
76.92
100
103
51
12
9
9.62
18.94
78.13
89.29
312.50
625
+0.16
-1.36
+1.73
-6.99
+4.17
+25.00
-
64
32
7
9.52
9.60
0
-2.94
+3.13
+10.00
+5.60
-
19.2
76.8
96
19.45
74.57
89.49
447.44
447.44
447.44
1.75
18.64
79.20
105.60
316.80
NA
6
4
2
300
500
HIGH
LOW
333.33
500
2
1
0
0
1
0
0
-
1000
3.91
-
0
625
0
0
316.80
1.24
-
0
-
255
2.44
-
255
-
255
-
255
FOSC = 4 MHz
3.579545 MHz
1 MHz
32.768 kHz
BAUD
RATE
(Kbps)
SPBRG
value
SPBRG
value
SPBRG
value
(decimal)
SPBRG
value
(decimal)
%
%
%
%
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
(decimal)
(decimal)
0.3
1.2
NA
1.20
2.40
9.62
19.23
NA
-
-
207
103
25
12
-
NA
1.20
-
+0.23
+0.23
+1.32
-2.90
-2.90
+16.52
-25.43
-
-
185
92
22
11
2
0.30
1.20
2.40
8.93
20.83
62.50
NA
+0.16
207
51
25
6
0.29
1.02
2.05
NA
-2.48
6
+0.16
+0.16
-14.67
1
2.4
+0.16
2.41
+0.16
-14.67
0
9.6
+0.16
9.73
-6.99
-
-
-
-
-
-
-
-
-
19.2
76.8
96
+0.16
18.64
74.57
111.86
223.72
NA
+8.51
2
NA
-
-
-
-
-
-
-
-18.62
0
NA
-
NA
-
1
-
-
-
-
-
-
NA
-
-
300
500
HIGH
LOW
NA
-
0
NA
-
NA
NA
-
-
NA
-
NA
-
250
0.98
0
55.93
0.22
-
0
62.50
0.24
0
2.05
0.008
0
255
-
255
255
255
2003-2013 Microchip Technology Inc.
DS39609C-page 203
PIC18F6520/8520/6620/8620/6720/8720
PIR3<4> for USART2), is set. This interrupt can be
18.2 USART Asynchronous Mode
enabled/disabled by setting/clearing enable bit, TXxIE
(PIE1<4> for USART1, PIE<4> for USART2). Flag bit
TXxIF will be set, regardless of the state of enable bit
TXxIE and cannot be cleared in software. It will reset
only when new data is loaded into the TXREGx register.
While flag bit TXIF indicates the status of the TXREGx
register, another bit, TRMT (TXSTAx<1>), shows the
status of the TSR register. Status bit TRMT is a read-only
bit, which is set when the TSR register is empty. No
interrupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
In this mode, the USARTs use standard Non-Return-to-
Zero (NRZ) format (one Start bit, eight or nine data bits
and one Stop bit). The most common data format is
8 bits. An on-chip dedicated 8-bit Baud Rate Generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. The USART’s transmitter and receiver are
functionally independent, but use the same data format
and baud rate. The Baud Rate Generator produces a
clock, either 16 or 64 times the bit shift rate, depending
on bit BRGH (TXSTAx<2>). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during Sleep.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set.
Asynchronous mode is selected by clearing bit SYNC
(TXSTAx<4>).
To set up an Asynchronous Transmission:
The USART Asynchronous module consists of the
following important elements:
1. Initialize the SPBRGx register for the appropri-
ate baud rate. If a high-speed baud rate is
desired, set bit BRGH (Section 18.1 “USART
Baud Rate Generator (BRG)”).
• Baud Rate Generator
• Sampling Circuit
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
• Asynchronous Transmitter
• Asynchronous Receiver
3. If interrupts are desired, set enable bit TXxIE in
the appropriate PIE register.
18.2.1
USART ASYNCHRONOUS
TRANSMITTER
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREGx. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the Stop
bit has been transmitted from the previous load. As
soon as the Stop bit is transmitted, the TSR is loaded
with new data from the TXREGx register (if available).
Once the TXREGx register transfers the data to the
TSR register (occurs in one TCY), the TXREGx register
is empty and flag bit, TXx1IF (PIR1<4> for USART1,
5. Enable the transmission by setting bit TXEN,
which will also set bit TXxIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREGx register (starts
transmission).
Note:
TXIF is not cleared immediately upon
loading data into the transmit buffer
TXREG. The flag bit becomes valid in the
second instruction cycle following the load
instruction.
FIGURE 18-1:
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXREG Register
TXIF
TXIE
8
MSb
(8)
LSb
Pin Buffer
and Control
0
TSR Register
TX pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
DS39609C-page 204
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 18-2:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX1/CK1 (pin)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 18-3:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
RC6/TX1/CK1 (pin)
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
TXIF bit
(Interrupt Reg. Flag)
Word 1
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 18-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF INT0IF
RBIF
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0111 1111 0111 1111
--00 0000 --00 0000
--00 0000 --00 0000
--11 1111 --11 1111
0000 000x 0000 000x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
—
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
TX1IF
TX1IE
TX1IP
SSPIF
CCP1IF TMR2IF TMR1IF
PIE1
SSPIE CCP1IE TMR2IE TMR1IE
SSPIP CCP1IP TMR2IP TMR1IP
IPR1
PIR3
TX2IF TMR4IF CCP5IF CCP4IF CCP3IF
TX2IE TMR4IE CCP5IE CCP4IE CCP3IE
TX2IP TMR4IP CCP5IP CCP4IP CCP3IP
PIE3
—
—
IPR3
—
—
(1)
(1)
RCSTAx
SPEN
RX9
CREN ADDEN
FERR
OERR
RX9D
TXREGx
USART Transmit Register
(1)
TXSTAx
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
(1)
SPBRGx Baud Rate Generator Register
Legend: x= unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and Reset values are identical between modules.
2003-2013 Microchip Technology Inc.
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PIC18F6520/8520/6620/8620/6720/8720
18.2.2
USART ASYNCHRONOUS
RECEIVER
18.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The USART receiver block diagram is shown in
Figure 18-4. The data is received on the pin (RC7/RX1/
DT1 or RG2/RX2/DT2) and drives the data recovery
block. The data recovery block is actually a high-speed
shifter operating at 16 times the baud rate, whereas the
main receive serial shifter operates at the bit rate or at
FOSC. This mode would typically be used in RS-232
systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGx register for the appropri-
ate baud rate. If a high-speed baud rate is
required, set the BRGH bit.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
To set up an Asynchronous Reception:
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 18.1 “USART Baud
Rate Generator (BRG)”).
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
7. The RCxIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCxIE and GIE bits are set.
3. If interrupts are desired, set enable bit RCxIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
8. Read the RCSTAx register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
6. Flag bit RCxIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCxIE was set.
9. Read RCREGx to determine if the device is
being addressed.
7. Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-4:
USART RECEIVE BLOCK DIAGRAM
FERR
OERR
CREN
x64 Baud Rate CLK
64
or
16
RSR Register
LSb
Start
MSb
SPBRG
0
1
7
Stop (8)
Baud Rate Generator
RX9
RX pin
Pin Buffer
Data
and Control
Recovery
RX9D
RCREG Register
FIFO
SPEN
8
Interrupt
RCIF
RCIE
Data Bus
DS39609C-page 206
2003-2013 Microchip Technology Inc.
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FIGURE 18-5:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX (pin)
bit 0 bit 1
Stop
bit
Stop
bit
bit 7/8 Stop
bit
bit 0
bit 7/8
bit 7/8
Rcv Shift
Reg
Rcv Buffer Reg
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 18-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE INT0IE
RBIE
TMR0IF INT0IF
RBIF
0000 0000
0000 0000
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
—
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
TXIF
TXIE
TXIP
SSPIF CCP1IF TMR2IF TMR1IF
SSPIE CCP1IE TMR2IE TMR1IE
SSPIP CCP1IP TMR2IP TMR1IP
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
TX2IF TMR4IF CCP5IF CCP4IF CCP3IF
TX2IE TMR4IE CCP5IE CCP4IE CCP3IE
TX2IP TMR4IP CCP5IP CCP4IP CCP3IP
—
—
—
—
(1)
RCSTAx
RCREGx
SPEN
RX9
CREN ADDEN
FERR
OERR
RX9D
(1)
USART Receive Register
CSRC TX9 TXEN
Baud Rate Generator Register
(1)
TXSTAx
SPBRGx
Legend:
SYNC
—
BRGH
TRMT
TX9D
(1)
x= unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and Reset values are identical between modules.
2003-2013 Microchip Technology Inc.
DS39609C-page 207
PIC18F6520/8520/6620/8620/6720/8720
set, regardless of the state of enable bit TXxIE and can-
18.3 USART Synchronous Master
Mode
not be cleared in software. It will reset only when new
data is loaded into the TXREGx register. While flag bit
TXxIF indicates the status of the TXREGx register,
another bit TRMT (TXSTAx<1>) shows the status of the
TSR register. TRMT is a read-only bit, which is set
when the TSR is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty. The TSR is not mapped in
data memory, so it is not available to the user.
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTAx<4>). In
addition, enable bit SPEN (RCSTAx<7>) is set in order
to configure the appropriate I/O pins to CK (clock) and
DT (data) lines, respectively. The Master mode indi-
cates that the processor transmits the master clock on
the CK line. The Master mode is entered by setting bit
CSRC (TXSTAx<7>).
To set up a Synchronous Master Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 18.1 “USART Baud Rate
Generator (BRG)”).
18.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXxIE in
the appropriate PIE register.
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREGx (if available). Once the
TXREGx register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREGx is empty and
interrupt bit TXxIF (PIR1<4> for USART1, PIR3<4> for
USART2) is set. The interrupt can be enabled/disabled
by setting/clearing enable bit TXxIE (PIE1<4> for
USART1, PIE3<4> for USART2). Flag bit TXxIF will be
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREGx register.
Note:
TXIF is not cleared immediately upon
loading data into the transmit buffer
TXREG. The flag bit becomes valid in the
second instruction cycle following the load
instruction.
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE INT0IE
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
0000 0000
0000 0000
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
—
RCIF
RCIE
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
TMR2IF
TMR1IF
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
RCIP
RC2IF
RC2IE
RC2IP
SREN
TX2IF TMR4IF CCP5IF
TX2IE TMR4IE CCP5IE
TX2IP TMR4IP CCP5IP
CCP4IF
CCP4IE
CCP4IP
OERR
CCP3IF
CCP3IE
CCP3IP
RX9D
—
—
—
—
(1)
RCSTAx
TXREGx
SPEN
RX9
CREN ADDEN
FERR
0000 000x
0000 0000
0000 -010
0000 0000
0000 000x
0000 0000
0000 -010
0000 0000
(1)
USART Transmit Register
CSRC TX9 TXEN
Baud Rate Generator Register
(1)
TXSTAx
SYNC
—
BRGH
TRMT
TX9D
(1)
SPBRGx
Legend:
x= unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and Reset values are identical between modules.
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FIGURE 18-6:
SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
RC7/RX1/DT1
pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
Word 1
RC6/TX1/CK1
pin
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words.
FIGURE 18-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX1/DT1 pin
bit 0
bit 2
bit 1
bit 6
bit 7
RC6/TX1/CK1 pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
2003-2013 Microchip Technology Inc.
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4. If interrupts are desired, set enable bit RCxIE in
the appropriate PIE register.
18.3.2
USART SYNCHRONOUS MASTER
RECEPTION
5. If 9-bit reception is desired, set bit RX9.
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTAx<5>) or enable bit CREN (RCSTAx<4>). Data
is sampled on the RXx pin (RC7/RX1/DT1 or RG2/RX2/
DT2) on the falling edge of the clock. If enable bit SREN
is set, only a single word is received. If enable bit CREN
is set, the reception is continuous until CREN is cleared.
If both bits are set, then CREN takes precedence.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCxIF will be set when
reception is complete and an interrupt will be
generated if the enable bit RCxIE was set.
8. Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
To set up a Synchronous Master Reception:
9. Read the 8-bit received data by reading the
RCREGx register.
1. Initialize the SPBRGx register for the appropri-
ate baud rate (Section 18.1 “USART Baud
Rate Generator (BRG)”).
10. If any error occurred, clear the error by clearing
bit CREN.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
3. Ensure bits CREN and SREN are clear.
TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
PIE1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF INT0IF
RBIF
0000 0000 0000 0000
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
—
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
TX1IF
TX1IE
TX1IP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111
IPR1
PIR3
PIE3
TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000
TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000
TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111
—
—
IPR3
—
—
(1)
RCSTAx
SPEN
RX9
CREN
ADDEN
FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
(1)
RCREGx
USART Receive Register
CSRC TX9
(1)
TXSTAx
SPBRGx
Legend:
TXEN
SYNC
—
BRGH
TRMT
TX9D
(1)
Baud Rate Generator Register
x= unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and Reset values are identical between modules.
FIGURE 18-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1 pin
RC6/TX1/CK1 pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Write to
bit SREN
SREN bit
CREN bit
‘0’
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
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To set up a Synchronous Slave Transmission:
18.4 USART Synchronous Slave Mode
1. Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the TXx pin (RC6/TX1/CK1 or RG1/TX2/CK2), instead
of being supplied internally in Master mode. TRISC<6>
must be set for this mode. This allows the device to
transfer or receive data while in Sleep mode. Slave
mode is entered by clearing bit CSRC (TXSTAx<7>).
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXxIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
18.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the Sleep
mode.
7. Start transmission by loading data to the
TXREGx register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXxIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREGx register will transfer the second
word to the TSR and flag bit TXxIF will now be
set.
e) If enable bit TXxIE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE INT0IE
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
0000 0000
0000 0000
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
—
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
TX1IF
TX1IE
TX1IP
SSPIF
SSPIE
SSPIP
TMR2IF
TMR1IF 0000 0000
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000
CCP1IP TMR2IP TMR1IP 0111 1111
TX2IF TMR4IF CCP5IF
CCP4IF
CCP3IF
--00 0000
—
—
TX2IE TMR4IE CCP5IE CCP4IE
TX2IP TMR4IP CCP5IP CCP4IP
CCP3IE --00 0000
CCP3IP --11 1111
—
—
(1)
RCSTAx
TXREGx
SPEN
RX9
CREN ADDEN
FERR
OERR
RX9D
0000 000x
0000 0000
0000 -010
0000 0000
(1)
USART Transmit Register
CSRC TX9 TXEN
Baud Rate Generator Register
(1)
TXSTAx
SYNC
—
BRGH
TRMT
TX9D
(1)
SPBRGx
Legend:
x= unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and Reset values are identical between modules.
2003-2013 Microchip Technology Inc.
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To set up a Synchronous Slave Reception:
18.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode and bit SREN, which is a “don’t care” in Slave
mode.
2. If interrupts are desired, set enable bit RCxIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
If receive is enabled by setting bit CREN prior to the
SLEEPinstruction, then a word may be received during
Sleep. On completely receiving the word, the RSR reg-
ister will transfer the data to the RCREG register and if
enable bit RCxIE bit is set, the interrupt generated will
wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector.
5. Flag bit RCxIF will be set when reception is
complete. An interrupt will be generated if
enable bit RCxIE was set.
6. Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREGx register.
8. If any error occurred, clear the error by clearing
bit CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 18-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
0000 0000
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
—
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
SSPIF
SSPIE
SSPIP
CCP1IF TMR2IF TMR1IF 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000
CCP1IP TMR2IP TMR1IP 0111 1111
0000 0000
0000 0000
0111 1111
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
TMR4IF CCP5IF CCP4IF CCP3IF --00 0000
TMR4IE CCP5IE CCP4IE CCP3IE --00 0000
TMR4IP CCP5IP CCP4IP CCP3IP --11 1111
—
—
—
—
(1)
RCSTAx
RCREGx
SPEN
RX9
ADDEN
FERR
OERR
RX9D
0000 000x
0000 0000
0000 -010
0000 0000
(1)
USART Receive Register
CSRC TX9 TXEN
Baud Rate Generator Register
(1)
TXSTAx
SPBRGx
Legend:
SYNC
—
BRGH
TRMT
TX9D
(1)
x= unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and Reset values are identical between modules.
DS39609C-page 212
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The module has five registers:
19.0 10-BIT ANALOG-TO-DIGITAL
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
CONVERTER (A/D) MODULE
The analog-to-digital (A/D) converter module has 12
inputs for the PIC18F6X20 devices and 16 for the
PIC18F8X20 devices. This module allows conversion
of an analog input signal to a corresponding 10-bit
digital number.
The ADCON0 register, shown in Register 19-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 19-2, configures the func-
tions of the port pins. The ADCON2 register, shown in
Register 19-3, configures the A/D clock source and
justification.
REGISTER 19-1: ADCON0 REGISTER
U-0
—
U-0
—
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
GO/DONE
bit 7
bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-2 CHS3:CHS0: Analog Channel Select bits
0000= Channel 0 (AN0)
0001= Channel 1 (AN1)
0010= Channel 2 (AN2)
0011= Channel 3 (AN3)
0100= Channel 4 (AN4)
0101= Channel 5 (AN5)
0110= Channel 6 (AN6)
0111= Channel 7 (AN7)
1000= Channel 8 (AN8)
1001= Channel 9 (AN9)
1010= Channel 10 (AN10)
1011= Channel 11 (AN11)
1100= Channel 12 (AN12)(1)
1101= Channel 13 (AN13)(1)
1110= Channel 14 (AN14)(1)
1111= Channel 15 (AN15)(1)
Note 1: These channels are not available on the PIC18F6X20 (64-pin) devices.
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress (setting this bit starts the A/D conversion, which is automatically
cleared by hardware when the A/D conversion is complete)
0= A/D conversion not in progress
ADON: A/D On bit
1= A/D converter module is enabled
0= A/D converter module is disabled
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
2003-2013 Microchip Technology Inc.
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PIC18F6520/8520/6620/8620/6720/8720
REGISTER 19-2: ADCON1 REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
VCFG1:VCFG0: Voltage Reference Configuration bits:
VCFG1
A/D VREF+
VCFG0
A/D VREF-
00
01
10
11
AVDD
AVSS
External VREF+
AVDD
AVSS
External VREF-
External VREF-
External VREF+
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits:
PCFG3
PCFG0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
A = Analog input
D = Digital I/O
Note: Shaded cells indicate A/D channels available only on PIC18F8X20 devices.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS39609C-page 214
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REGISTER 19-3: ADCON2 REGISTER
R/W-0 U-0
ADFM
bit 7
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
—
ADCS2
ADCS1
ADCS0
bit 0
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6-3
bit 2-0
Unimplemented: Read as ‘0’
ADCS1:ADCS0: A/D Conversion Clock Select bits
000= FOSC/2
001= FOSC/8
010= FOSC/32
011= FRC (clock derived from an RC oscillator = 1 MHz max)
100= FOSC/4
101= FOSC/16
110= FOSC/64
111= FRC (clock derived from an RC oscillator = 1 MHz max)
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS), or the voltage level on the RA3/AN3/
VREF+ pin and RA2/AN2/VREF- pin.
Each port pin associated with the A/D converter can be
configured as an analog input (RA3 can also be a
voltage reference), or as a digital I/O. The ADRESH
and ADRESL registers contain the result of the A/D
conversion. When the A/D conversion is complete, the
result is loaded into the ADRESH/ADRESL registers,
the GO/DONE bit (ADCON0 register) is cleared and
A/D interrupt flag bit, ADIF, is set. The block diagram of
the A/D module is shown in Figure 19-1.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion is aborted.
2003-2013 Microchip Technology Inc.
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FIGURE 19-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1111
AN15(1)
AN14(1)
1110
1101
1100
1011
1010
1001
AN13(1)
AN12(1)
AN11
AN10
AN9
AN8
AN7
AN6
1000
0111
0110
0101
0100
0011
0010
0001
0000
AN5
AN4
AN3
AN2
AN1
AN0
VAIN
(Input Voltage)
10-bit
Converter
A/D
VCFG1:VCFG0
VDD
VREF+
VREF-
Reference
Voltage
VSS
Note 1: Channels AN15 through AN12 are not available on PIC18F6X20 devices.
2: I/O pins have diode protection to VDD and VSS.
DS39609C-page 216
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The value in the ADRESH/ADRESL registers is not
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
modified for a Power-on Reset. The ADRESH/
ADRESL registers will contain unknown data after a
Power-on Reset.
• Set ADIE bit
• Set GIE bit
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 19.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started.
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0 register)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
The following steps should be followed to do an A/D
conversion:
7. For the next conversion, go to step 1 or step 2,
as required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
FIGURE 19-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC 1k
RSS
Rs
CPIN
ILEAKAGE
± 500 nA
VAIN
CHOLD = 120 pF
VT = 0.6V
5 pF
VSS
Legend: CPIN
= input capacitance
= threshold voltage
6V
5V
VDD 4V
VT
ILEAKAGE = leakage current at the pin due to
various junctions
3V
RIC
= interconnect resistance
= sampling switch
2V
SS
CHOLD
RSS
= sample/hold capacitance (from DAC)
= sampling switch resistance
5
6
7
8 9 10 11
Sampling Switch (k)
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Example 19-1 shows the calculation of the minimum
19.1 A/D Acquisition Requirements
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 19-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 k. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
CHOLD
Rs
Conversion Error
VDD
Temperature
VHOLD
=
=
=
=
=
120 pF
2.5 k
1/2 LSb
5V Rss = 7 k
50C (system max.)
0V @ time = 0
Note: When using external voltage references with
the A/D converter, the source impedance of
the external voltage references must be less
than 20 to obtain the A/D performance
specified in parameters A01-A06. Higher
reference source impedances will increase
both offset and gain errors. Resistive voltage
dividers will not provide a sufficiently low
source impedance.
Note:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
To calculate the minimum acquisition time,
Equation 19-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To maintain the best possible performance in
A/D conversions, external VREF inputs should
be buffered with an operational amplifier or
other low output impedance circuit.
If deviating from the operating conditions
specified for parameters A03-A06, the effect
of parameter A50 (VREF input current) must
be considered.
EQUATION 19-1: ACQUISITION TIME
TACQ
=
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 19-2: A/D MINIMUM CHARGING TIME
VHOLD =
or
(VREF – (VREF/2048)) • (1 – e(-Tc/CHOLD(RIC + RSS + RS))
)
TC
=
-(120 pF)(1 k + RSS + RS) ln(1/2047)
EXAMPLE 19-1:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
=
TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25C.
TACQ
TC
=
=
2 s + TC + [(Temp – 25C)(0.05 s/C)]
-CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 k + 7 k + 2.5 k) ln(0.0004885)
-120 pF (10.5 k) ln(0.0004885)
-1.26 s (-7.6241)
9.61 s
TACQ
=
2 s + 9.61 s + [(50C – 25C)(0.05 s/C)]
11.61 s + 1.25 s
12.86 s
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19.2 Selecting the A/D
19.3 Configuring Analog Port Pins
Conversion Clock
The ADCON1, TRISA, TRISF and TRISH registers
control the operation of the A/D port pins. The port pins
needed as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 12 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
• 2 TOSC
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
• 4 TOSC
• 8 TOSC
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert as an
analog input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal RC oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s.
2: Analog levels on any pin defined as a dig-
ital input may cause the input buffer to
consume current out of the device’s
specification limits.
Table 19-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 19-1: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Maximum Device Frequency
Operation
ADCS2:ADCS0
PIC18FXX20
PIC18LFXX20
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC
000
100
001
101
010
110
x11
1.25 MHz
2.50 MHz
5.00 MHz
10.0 MHz
20.0 MHz
40.0 MHz
—
666 kHz
1.33 MHz
2.67 MHz
5.33 MHz
10.67 MHz
21.33 MHz
—
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19.4 A/D Conversions
19.5 Use of the CCP2 Trigger
Figure 19-3 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conver-
sion. The A/D Result register pair will NOT be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the last value written to the ADRESH:ADRESL reg-
isters). After the A/D conversion is aborted, a 2 TAD wait
is required before the next acquisition is started. After
this 2 TAD wait, acquisition on the selected channel is
automatically started.
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D conversion and
the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition done before the “special
event trigger” sets the GO/DONE bit (starts a
conversion).
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D module,
but will still reset the Timer1 (or Timer3) counter.
FIGURE 19-3:
A/D CONVERSION TAD CYCLES
TCY - TAD
TAD7 TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6
b0
b5
b4
b3
b2
b1
b0
b7
b6
b8
b9
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
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TABLE 19-2: SUMMARY OF A/D REGISTERS
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
0000 0000
PIR1
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
CMIF
CMIE
CMIP
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
—
SSPIF CCP1IF
SSPIE CCP1IE
SSPIP CCP1IP
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TMR1IF 0000 0000
TMR1IE 0000 0000
TMR1IP 0111 1111
CCP2IF -0-- 0000
CCP2IE -0-- 0000
CCP2IP -0-- 0000
xxxx xxxx
0000 0000
0000 0000
0111 1111
-0-- 0000
-0-- 0000
-0-- 0000
uuuu uuuu
uuuu uuuu
--00 0000
--00 0000
0--- -000
--0u 0000
--11 1111
u000 0000
uuuu uuuu
1111 1111
0000 xxxx
uuuu uuuu
1111 1111
PIE1
IPR1
PIR2
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
PIE2
—
—
—
IPR2
—
—
—
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTF
LATF
A/D Result Register High Byte
A/D Result Register Low Byte
xxxx xxxx
—
—
—
—
CHS3
CHS3
CHS1
CHS0
GO/DONE
PCFG1
ADCS1
RA1
ADON
PCFG0
ADCS0
RA0
--00 0000
--00 0000
0--- -000
--0x 0000
--11 1111
x000 0000
xxxx xxxx
1111 1111
0000 xxxx
xxxx xxxx
1111 1111
VCFG1 VCFG0 PCFG3 PCFG2
ADFM
—
—
—
—
—
ADCS2
RA2
RA6
RA5
RA4
RA3
—
PORTA Data Direction Register
RF7
LATF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
TRISF
PORTF Data Direction Control Register
(1)
PORTH
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
(1)
LATH
LATH7
LATH6
LATH5
LATH4 LATH3
LATH2
LATH1
LATH0
(1)
TRISH
PORTH Data Direction Control Register
Legend:
x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: Only available on PIC18F8X20 devices.
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NOTES:
DS39609C-page 222
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The CMCON register, shown as Register 20-1, con-
20.0 COMPARATOR MODULE
trols the comparator input and output multiplexers. A
block diagram of the various comparator configurations
is shown in Figure 20-1.
The comparator module contains two analog compara-
tors. The inputs to the comparators are multiplexed
with the RF1 through RF6 pins. The on-chip voltage ref-
erence (Section 21.0 “Comparator Voltage Reference
Module”) can also be an input to the comparators.
REGISTER 20-1: CMCON REGISTER
R-0
R-0
R/W-0
C2INV
R/W-0
C1INV
R/W-0
CIS
R/W-0
CM2
R/W-0
CM1
R/W-0
CM0
C2OUT
C1OUT
bit 7
bit 0
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1= C2 VIN+ > C2 VIN-
0= C2 VIN+ < C2 VIN-
When C2INV = 1:
1= C2 VIN+ < C2 VIN-
0= C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1= C1 VIN+ > C1 VIN-
0= C1 VIN+ < C1 VIN-
When C1INV = 1:
1= C1 VIN+ < C1 VIN-
0= C1 VIN+ > C1 VIN-
bit 5
bit 4
bit 3
C2INV: Comparator 2 Output Inversion bit
1= C2 output inverted
0= C2 output not inverted
C1INV: Comparator 1 Output Inversion bit
1= C1 output inverted
0= C1 output not inverted
CIS: Comparator Input Switch bit
When CM2:CM0 = 110:
1= C1 VIN- connects to RF5/AN10
C2 VIN- connects to RF3/AN8
0= C1 VIN- connects to RF6/AN11
C2 VIN- connects to RF4/AN9
bit 2-0
CM2:CM0: Comparator Mode bits
Figure 20-1 shows the Comparator modes and the CM2:CM0 bit settings.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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be valid for the specified mode change delay shown in
the Electrical Specifications (Section 26.0 “Electrical
Characteristics”).
20.1 Comparator Configuration
There are eight modes of operation for the compara-
tors. The CMCON register is used to select these
modes. Figure 20-1 shows the eight possible modes.
The TRISF register controls the data direction of the
comparator pins for each mode. If the Comparator
mode is changed, the comparator output level may not
Note:
Comparator interrupts should be disabled
during Comparator mode change.
Otherwise, a false interrupt may occur.
a
FIGURE 20-1:
COMPARATOR I/O OPERATING MODES
Comparators Reset (POR Default Value)
Comparators Off
CM2:CM0 = 000
CM2:CM0 = 111
A
D
VIN-
VIN-
RF6/AN11
RF5/AN10
RF6/AN11
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
Off (Read as ‘0’)
C1
C2
C1
C2
VIN+
VIN+
A
D
RF5/AN10
A
A
D
VIN-
VIN-
RF4/AN9
RF3/AN8
RF4/AN9
VIN+
VIN+
D
RF3/AN8
Two Independent Comparators with Outputs
CM2:CM0 = 011
Two Independent Comparators
CM2:CM0 = 010
A
VIN-
A
VIN-
RF6/AN11
RF5/AN10
RF6/AN11
RF5/AN10
C1OUT
C2OUT
C1
C2
VIN+
A
C1OUT
C2OUT
C1
C2
VIN+
A
RF2/AN7/C1OUT
A
A
VIN-
A
VIN-
RF4/AN9
RF3/AN8
RF4/AN9
VIN+
VIN+
A
RF3/AN8
RF1/AN6/C2OUT
Two Common Reference Comparators
Two Common Reference Comparators with Outputs
CM2:CM0 = 100
CM2:CM0 = 101
A
A
VIN-
VIN-
RF6/AN11
RF5/AN10
RF6/AN11
RF5/AN10
C1OUT
C2OUT
C1OUT
C1
C2
C1
C2
VIN+
VIN+
A
A
RF2/AN7/C1OUT
A
D
VIN-
RF4/AN9
RF3/AN8
A
VIN-
VIN+
RF4/AN9
C2OUT
VIN+
D
RF3/AN8
RF1/AN6/C2OUT
Four Inputs Multiplexed to Two Comparators
One Independent Comparator with Output
CM2:CM0 = 110
CM2:CM0 = 001
A
A
A
VIN-
RF6/AN11
RF6/AN11
RF5/AN10
CIS = 0
CIS = 1
VIN-
A
C1OUT
C1
VIN+
RF5/AN10
C1OUT
C2OUT
C1
C2
VIN+
RF2/AN7/C1OUT
A
A
RF4/AN9
RF3/AN8
VIN-
CIS = 0
CIS = 1
VIN+
D
VIN-
RF4/AN9
Off (Read as ‘0’)
C2
VIN+
D
RF3/AN8
CVREF
From VREF Module
A = Analog Input, port reads zeros always
DS39609C-page 224
D = Digital Input
CIS (CMCON<3>) is the Comparator Input Switch
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20.3.2
INTERNAL REFERENCE SIGNAL
20.2 Comparator Operation
The comparator module also allows the selection of an
internally generated voltage reference for the compara-
tors. Section 21.0 “Comparator Voltage Reference
Module” contains a detailed description of the compar-
ator voltage reference module that provides this signal.
The internal reference signal is used when comparators
are in mode CM<2:0> = 110 (Figure 20-1). In this
mode, the internal voltage reference is applied to the
VIN+ pin of both comparators.
A single comparator is shown in Figure 20-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 20-2 represent
the uncertainty, due to input offsets and response time.
20.4 Comparator Response Time
20.3 Comparator Reference
Response time is the minimum time, after selecting a
new reference voltage or input source, before the com-
parator output has a valid level. If the internal reference
is changed, the maximum delay of the internal voltage
reference must be considered when using the compar-
ator outputs. Otherwise, the maximum delay of the
comparators should be used (Section 26.0 “Electrical
Characteristics”).
An external or internal reference signal may be used,
depending on the comparator operating mode. The
analog signal present at VIN- is compared to the signal
at VIN+ and the digital output of the comparator is
adjusted accordingly (Figure 20-2).
FIGURE 20-2:
SINGLE COMPARATOR
20.5 Comparator Outputs
VIN+
VIN-
+
Output
The comparator outputs are read through the CMCON
register. These bits are read-only. The comparator
outputs may also be directly output to the RF1 and RF2
I/O pins. When enabled, multiplexors in the output path
of the RF1 and RF2 pins will switch and the output of
each pin will be the unsynchronized output of the com-
parator. The uncertainty of each of the comparators is
related to the input offset voltage and the response time
given in the specifications. Figure 20-3 shows the
comparator output block diagram.
–
VIN-
VIN+
The TRISF bits will still function as an output enable/
disable for the RF1 and RF2 pins while in this mode.
Output
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<4:5>).
Note 1: When reading the port register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input, according to the
Schmitt Trigger input specification.
20.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same, or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
2: Analog levels on any pin defined as a dig-
ital input may cause the input buffer to
consume more current than is specified.
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FIGURE 20-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port pins
MULTIPLEX
+
-
CxINV
To RF1 or
RF2 pin
Bus
Data
Q
D
Read CMCON
EN
Set
CMIF
bit
Q
D
From
Other
Comparator
EN
CL
Read CMCON
Reset
20.6 Comparator Interrupts
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR
registers) interrupt flag may not get set.
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that occurred. The CMIF
bit (PIR registers) is the Comparator Interrupt Flag. The
CMIF bit must be reset by clearing ‘0’. Since it is also
possible to write a ‘1’ to this register, a simulated
interrupt may be initiated.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit CMIF.
The CMIE bit (PIE registers) and the PEIE bit (INTCON
register) must be set to enable the interrupt. In addition,
the GIE bit must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMIF bit
will still be set if an interrupt condition occurs.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
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20.7 Comparator Operation
20.9 Analog Input Connection
Considerations
During Sleep
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional, if enabled. This interrupt will
wake-up the device from Sleep mode, when enabled.
While the comparator is powered up, higher Sleep
currents than shown in the power-down current
specification will occur. Each operational comparator
will consume additional current, as shown in the com-
parator specifications. To minimize power consumption
while in Sleep mode, turn off the comparators
(CM<2:0> = 111) before entering Sleep. If the device
wakes up from Sleep, the contents of the CMCON
register are not affected.
A simplified circuit for an analog input is shown in
Figure 20-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up condition may
occur. A maximum source impedance of 10 k is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
20.8 Effects of a Reset
A device Reset forces the CMCON register to its Reset
state, causing the comparator module to be in the Com-
parator Reset mode, CM<2:0> = 000. This ensures
that all potential inputs are analog inputs. Device cur-
rent is minimized when analog inputs are present at
Reset time. The comparators will be powered down
during the Reset interval.
FIGURE 20-4:
COMPARATOR ANALOG INPUT MODEL
VDD
VT = 0.6V
RIC
RS < 10k
AIN
Comparator
Input
ILEAKAGE
±500 nA
CPIN
5 pF
VA
VT = 0.6V
VSS
Legend: CPIN
=
=
Input Capacitance
Threshold Voltage
VT
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
=
=
=
Interconnect Resistance
Source Impedance
Analog Voltage
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TABLE 20-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Value on
all other
Resets
Value on
POR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMCON C2OUT C1OUT C2INV C1INV
CIS
CM2
CM1
CM0
0000 0000 0000 0000
CVRCON CVREN CVROE CVRR CVRSS CVR3
CVR2
CVR1
CVR0 0000 0000 0000 0000
RBIF 0000 0000 0000 0000
INTCON
GIE/
PEIE/ TMR0IE INT0IE
GIEL
RBIE TMR0IF INT0IF
GIEH
PIR2
—
—
CMIF
CMIE
CMIP
RF6
—
—
—
—
BCLIF
BCLIE
BCLIP
RF3
LVDIF TMR3IF CCP2IF -0-- 0000 -0-- 0000
LVDIE TMR3IE CCP2IE -0-- 0000 -0-- 0000
LVDIP TMR3IP CCP2IP -1-- 1111 -1-- 1111
PIE2
IPR2
—
—
—
PORTF
LATF
TRISF
RF7
RF5
RF4
RF2
RF1
LATF1 LATF0 xxxx xxxx uuuu uuuu
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111
RF0
x000 0000 u000 0000
LATF7 LATF6 LATF5 LATF4 LATF3 LATF2
Legend: x= unknown, u= unchanged, – = unimplemented, read as ‘0’.
Shaded cells are unused by the comparator module.
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21.1 Configuring the Comparator
Voltage Reference
21.0 COMPARATOR VOLTAGE
REFERENCE MODULE
The comparator voltage reference can output 16 distinct
voltage levels for each range. The equations used to
calculate the output of the comparator voltage reference
are as follows:
The comparator voltage reference is a 16-tap resistor
ladder network that provides a selectable voltage refer-
ence. The resistor ladder is segmented to provide two
ranges of CVREF values and has a power-down function
to conserve power when the reference is not being used.
The CVRCON register controls the operation of the
reference as shown in Register 21-1. The block diagram
is given in Figure 21-1.
If CVRR = 1:
CVREF = (CVR<3:0>/24) x CVRSRC
If CVRR = 0:
CVREF = (CVRSRC x 1/4) + (CVR<3:0>/32) x CVRSRC
The comparator reference supply voltage can come
from either VDD or VSS, or the external VREF+ and
VREF- that are multiplexed with RA3 and RA2. The
comparator reference supply voltage is controlled by
the CVRSS bit.
The settling time of the comparator voltage reference
must be considered when changing the CVREF output
(Section 26.0 “Electrical Characteristics”).
Note: In order to select external VREF+ and VREF-
supply voltages, the Voltage Reference Con-
figuration bits (VCFG1:VCFG0) of the
ADCON1 register must be set appropriately.
REGISTER 21-1:
CVRCON REGISTER
R/W-0
R/W-0
R/W-0
CVRR
R/W-0
R/W-0
CVR3
R/W-0
CVR2
R/W-0
CVR1
R/W-0
CVR0
CVREN
CVROE
CVRSS
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3-0
CVREN: Comparator Voltage Reference Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down
CVROE: Comparator VREF Output Enable bit(1)
1= CVREF voltage level is also output on the RF5/AN10/CVREF pin
0= CVREF voltage is disconnected from the RF5/AN10/CVREF pin
CVRR: Comparator VREF Range Selection bit
1= 0.00 CVRSRC to 0.667 CVRSRC, with CVRSRC/24 step size (low range)
0= 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)
CVRSS: Comparator VREF Source Selection bit(2)
1= Comparator reference source CVRSRC = VREF+ – VREF-
0= Comparator reference source CVRSRC = VDD – VSS
CVR3:CVR0: Comparator VREF Value Selection bits (0 VR3:VR0 15)
When CVRR = 1:
CVREF = (CVR<3:0>/24) (CVRSRC)
When CVRR = 0:
CVREF = 1/4 (CVRSRC) + (CVR3:CVR0/32) (CVRSRC)
Note 1: If enabled for output, RF5 must also be configured as an input by setting TRISF<5>
to ‘1’.
2: In order to select external VREF+ and VREF- supply voltages, the Voltage
Reference Configuration bits (VCFG1:VCFG0) of the ADCON1 register must be
set appropriately.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
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FIGURE 21-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
VDD
VREF+
16 Stages
CVRSS = 1
CVRSS = 0
CVREN
R
R
R
8R
R
CVRR
CVRSS = 0
8R
CVRSS = 1
VREF-
CVR3
CVREF
(From CVRCON<3:0>)
CVR0
16-1 Analog Mux
Note: R is defined in Section 26.0 “Electrical Characteristics”.
21.2 Voltage Reference Accuracy/Error
21.4 Effects of a Reset
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 21-1) keep CVREF from approaching the refer-
ence source rails. The voltage reference is derived
from the reference source; therefore, the CVREF output
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 26.0 “Electrical Characteristics”.
A device Reset disables the voltage reference by
clearing bit CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit CVROE (CVRCON<6>) and selects the high-
voltage range by clearing bit CVRR (CVRCON<5>).
The VRSS value select bits, CVRCON<3:0>, are also
cleared.
21.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RF5 pin if the
TRISF<5> bit is set and the CVROE bit is set. Enabling
the voltage reference output onto the RF5 pin,
configured as a digital input, will increase current
consumption. Connecting RF5 as a digital output with
VRSS enabled will also increase current consumption.
21.3 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage refer-
ence output for external connections to VREF.
Figure 21-2 shows an example buffering technique.
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FIGURE 21-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
(1)
RF5
R
CVREF
+
–
Module
CVREF Output
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the Comparator Voltage Reference Configuration bits CVRCON<3:0> and CVRCON<5>.
TABLE 21-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Value on
Value on
POR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
CVRCON CVREN CVROE CVRR CVRSS CVR3
CVR2
CM2
CVR1
CM1
CVR0 0000 0000 0000 0000
CM0 0000 0000 0000 0000
CMCON
TRISF
C2OUT C1OUT C2INV C1INV
CIS
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111
Legend: x= unknown, u= unchanged, – = unimplemented, read as ‘0’.
Shaded cells are not used with the comparator voltage reference.
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The Low-Voltage Detect circuitry is completely under
22.0 LOW-VOLTAGE DETECT
software control. This allows the circuitry to be “turned
off” by the software, which minimizes the current
consumption for the device.
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application soft-
ware can do “housekeeping tasks” before the device
voltage exits the valid operating range. This can be
done using the Low-Voltage Detect module.
Figure 22-1 shows a possible application voltage curve
(typically for batteries). Over time, the device voltage
decreases. When the device voltage equals voltage VA,
the LVD logic generates an interrupt. This occurs at
time TA. The application software then has the time,
until the device voltage is no longer in valid operating
range, to shut down the system. Voltage point VB is the
minimum valid operating voltage specification. This
occurs at time TB. The difference TB – TA is the total
time for shutdown.
This module is a software programmable circuitry,
where a device voltage trip point can be specified.
When the voltage of the device becomes lower then the
specified point, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the inter-
rupt vector address and the software can then respond
to that interrupt source.
FIGURE 22-1:
TYPICAL LOW-VOLTAGE DETECT APPLICATION
VA
VB
Legend:
VA = LVD trip point
VB = Minimum valid device
operating voltage
TB
TA
Time
The block diagram for the LVD module is shown in
Figure 22-2. A comparator uses an internally gener-
ated reference voltage as the set point. When the
selected tap output of the device voltage crosses the
set point (is lower than), the LVDIF bit is set.
supply voltage is equal to the trip point, the voltage
tapped off of the resistor array is equal to the 1.2V
internal reference voltage generated by the voltage ref-
erence module. The comparator then generates an
interrupt signal, setting the LVDIF bit. This voltage is
software programmable to any one of 16 values (see
Figure 22-2). The trip point is selected by programming
the LVDL3:LVDL0 bits (LVDCON<3:0>).
Each node in the resistor divider represents a “trip
point” voltage. The “trip point” voltage is the minimum
supply voltage level at which the device can operate
before the LVD module asserts an interrupt. When the
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FIGURE 22-2:
LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM
VDD
LVDIN
LVD3:LVD0
LVDCON
Register
LVDIF
Internally Generated
LVDEN
Reference Voltage
(Parameter #D423)
The LVD module has an additional feature that allows
the user to supply the trip voltage to the module from
an external source. This mode is enabled when bits
LVDL3:LVDL0 are set to ‘1111’. In this state, the com-
parator input is multiplexed from the external input pin,
LVDIN (Figure 22-3). This gives users flexibility
because it allows them to configure the Low-Voltage
Detect interrupt to occur at any voltage in the valid
operating range.
FIGURE 22-3:
LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
VDD
VDD
LVD3:LVD0
LVDCON
Register
LVDIN
LVDEN
Externally Generated
Trip Point
LVD
VxEN
BODEN
EN
BGAP
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22.1 Control Register
The Low-Voltage Detect Control register controls the
operation of the Low-Voltage Detect circuitry.
REGISTER 22-1: LVDCON REGISTER
U-0
—
U-0
—
R-0
R/W-0
R/W-0
LVDL3
R/W-1
LVDL2
R/W-0
LVDL1
R/W-1
LVDL0
IRVST
LVDEN
bit 7
bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5
bit 4
IRVST: Internal Reference Voltage Stable Flag bit
1= Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified
voltage range
0= Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the
specified voltage range and the LVD interrupt should not be enabled
LVDEN: Low-Voltage Detect Power Enable bit
1= Enables LVD, powers up LVD circuit
0= Disables LVD, powers down LVD circuit
bit 3-0 LVDL3:LVDL0: Low-Voltage Detection Limit bits(2)
1111= External analog input is used (input comes from the LVDIN pin)
1110= 4.64V
1101= 4.33V
1100= 4.13V
1011= 3.92V
1010= 3.72V
1001= 3.61V
1000= 3.41V
0111= 3.1V
0110= 2.89V
0101= 2.78V
0100= 2.58V
0011= 2.47V
0010= 2.27V
0001= 2.06V
0000= Reserved
Note 1: LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage
of the device are not tested.
2: Typical values shown, see parameter D420 in Table 26-3 for more information.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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The following steps are needed to set up the LVD
module:
22.2 Operation
Depending on the power source for the device voltage,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be con-
stantly operating. To decrease the current require-
ments, the LVD circuitry only needs to be enabled for
short periods, where the voltage is checked. After
doing the check, the LVD module may be disabled.
1. Write the value to the LVDL3:LVDL0 bits
(LVDCON register), which selects the desired
LVD trip point.
2. Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared or the GIE bit is cleared).
3. Enable the LVD module (set the LVDEN bit in
the LVDCON register).
Each time that the LVD module is enabled, the circuitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
4. Wait for the LVD module to stabilize (the IRVST
bit to become set).
5. Clear the LVD interrupt flag, which may have
falsely become set, until the LVD module has
stabilized (clear the LVDIF bit).
6. Enable the LVD interrupt (set the LVDIE and the
GIE bits).
Figure 22-4 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 22-4:
LOW-VOLTAGE DETECT WAVEFORMS
CASE 1:
LVDIF may not be set
VDD
VLVD
LVDIF
Enable LVD
Internally Generated
Reference Stable
TIVRST
LVDIF cleared in software
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
TIVRST
Internally Generated
Reference Stable
LVDIF cleared in software
LVDIF cleared in software,
LVDIF remains set since LVD condition still exists
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22.2.1
REFERENCE VOLTAGE SET POINT
22.3 Operation During Sleep
The internal reference voltage of the LVD module,
specified in electrical specification parameter #D423,
may be used by other internal circuitry (the
Programmable Brown-out Reset). If these circuits are
disabled (lower current consumption), the reference
voltage circuit requires a time to become stable before a
low-voltage condition can be reliably detected. This time
is invariant of system clock speed. This start-up time is
specified in electrical specification parameter #36. The
low-voltage interrupt flag will not be enabled until a stable
reference voltage is reached. Refer to the waveform in
Figure 22-4.
When enabled, the LVD circuitry continues to operate
during Sleep. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wake-
up from Sleep. Device execution will continue from the
interrupt vector address if interrupts have been globally
enabled.
22.4 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the LVD module to be turned off.
22.2.2
CURRENT CONSUMPTION
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume static cur-
rent. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter #D022B.
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23.1 Configuration Bits
23.0 SPECIAL FEATURES OF THE
CPU
The configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select vari-
ous device configurations. These bits are mapped,
starting at program memory location 300000h.
There are several features intended to maximize sys-
tem reliability, minimize cost through elimination of
external components, provide power saving operating
modes and offer code protection. These are:
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h through
3FFFFFh), which can only be accessed using table
reads and table writes.
• Oscillator Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
Programming the configuration registers is done in a
manner similar to programming the Flash memory. The
EECON1 register WR bit starts a self-timed write to the
configuration register. In normal operation mode, a
TBLWT instruction with the TBLPTR pointed to the
configuration register sets up the address and the data
for the configuration register write. Setting the WR bit
starts a long write to the configuration register. The
configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWTinstruction
can write a ‘1’ or a ‘0’ into the cell.
• Watchdog Timer (WDT)
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming
All PIC18FXX20 devices have a Watchdog Timer,
which is permanently enabled via the configuration bits,
or software controlled. It runs off its own RC oscillator
for added reliability. There are two timers that offer
necessary delays on power-up. One is the Oscillator
Start-up Timer (OST), intended to keep the chip in
Reset until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT), which provides a fixed
delay on power-up only, designed to keep the part in
Reset while the power supply stabilizes. With these two
timers on-chip, most applications need no external
Reset circuitry.
Sleep mode is designed to offer a very low current
power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer Wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost, while the
LP crystal option saves power. A set of configuration
bits is used to select various options.
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TABLE 23-1: CONFIGURATION BITS AND DEVICE IDS
Default/
Unprogrammed
Value
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
—
—
—
—
—
—
—
—
OSCSEN
—
—
—
—
—
—
—
FOSC2
BORV0
FOSC1
BODEN
WDTPS0
PM1
FOSC0
PWRTEN
WDTEN
PM0
--1- -111
---- 1111
---- 1111
1--- --11
---- --11
1--- -1-1
1111 1111
11-- ----
1111 1111
111- ----
1111 1111
-1-- ----
(4)
—
—
—
—
—
BORV1
—
WDTPS2 WDTPS1
(1)
300004h CONFIG3L
WAIT
—
—
—
—
—
(3)
300005h CONFIG3H
r
CCP2MX
STVREN
CP0
300006h CONFIG4L DEBUG
—
LVP
CP2
—
—
CP1
—
(2)
(2)
(2)
(2)
300008h CONFIG5L CP7
CP6
CP5
CP4
—
CP3
—
300009h CONFIG5H
30000Ah CONFIG6L WRT7
30000Bh CONFIG6H WRTD
CPD
CPB
—
—
(2)
(2)
(2)
(2)
WRT6
WRTB
WRT5
WRT4
—
WRT3
—
WRT2
—
WRT1
—
WRT0
—
WRTC
(2)
(2)
(2)
(2)
30000Ch CONFIG7L EBTR7 EBTR6
EBTR5
EBTR4
—
EBTR3
—
EBTR2
—
EBTR1
—
EBTR0
—
30000Dh CONFIG7H
3FFFFEh DEVID1
3FFFFFh DEVID2
—
EBTRB
DEV1
DEV9
—
DEV2
DEV10
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
0000 0110
Legend:
x= unknown, u= unchanged, – = unimplemented, q= value depends on condition, r= reserved.
Shaded cells are unimplemented, read as ‘0’.
Note 1: Unimplemented in PIC18F6X20 devices; maintain this bit set.
2: Unimplemented in PIC18FX520 and PIC18FX620 devices; maintain this bit set.
3: Unimplemented in PIC18FX620 and PIC18FX720 devices; maintain this bit set.
4: See Register 23-13 for DEVID1 values.
REGISTER 23-1: CONFIG1H:CONFIGURATIONREGISTER1HIGH(BYTE ADDRESS300001h)
U-0
—
U-0
—
R/P-1
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
OSCSEN
FOSC2
FOSC1
FOSC0
bit 7
bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5 OSCSEN: Oscillator System Clock Switch Enable bit
1= Oscillator system clock switch option is disabled (main oscillator is source)
0= Timer1 Oscillator system clock switch option is enabled (oscillator switching is enabled)
bit 4-3 Unimplemented: Read as ‘0’
bit 2-0 FOSC2:FOSC0: Oscillator Selection bits
111= RC oscillator w/ OSC2 configured as RA6
110= HS oscillator with PLL enabled; clock frequency = (4 x FOSC)
101= EC oscillator w/ OSC2 configured as RA6
100= EC oscillator w/ OSC2 configured as divide-by-4 clock output
011= RC oscillator w/ OSC2 configured as divide-by-4 clock output
010= HS oscillator
001= XT oscillator
000= LP oscillator
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
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REGISTER 23-2: CONFIG2L:CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS300002h)
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
BORV1
BORV0 BOREN PWRTEN
bit 0
bit 7
bit 7-4 Unimplemented: Read as ‘0’
bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits
11= VBOR set to 2.5V
10= VBOR set to 2.7V
01= VBOR set to 4.2V
00= VBOR set to 4.5V
bit 1
bit 0
BOREN: Brown-out Reset Enable bit
1= Brown-out Reset enabled
0= Brown-out Reset disabled
PWRTEN: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
REGISTER 23-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 0
bit 7
bit 7-4 Unimplemented: Read as ‘0’
bit 3-1 WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits
111= 1:128
110= 1:64
101= 1:32
100= 1:16
011= 1:8
010= 1:4
001= 1:2
000= 1:1
bit 0
WDTEN: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
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REGISTER 23-4: CONFIG3L:CONFIGURATIONREGISTER3LOW(BYTEADDRESS300004h)(1)
R/P-1
WAIT
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
PM1
R/P-1
PM0
bit 7
bit 0
bit 7
WAIT: External Bus Data Wait Enable bit
1= Wait selections unavailable for table reads and table writes
0= Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits
(MEMCOM<5:4>)
bit 6-2 Unimplemented: Read as ‘0’
bit 1-0 PM1:PM0: Processor Mode Select bits
11= Microcontroller mode
10= Microprocessor mode
01= Microprocessor with Boot Block mode
00= Extended Microcontroller mode
Note 1: This register is unimplemented in PIC18F6X20 devices; maintain these bits set.
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
REGISTER 23-5: CONFIG3H:CONFIGURATIONREGISTER3HIGH(BYTE ADDRESS300005h)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
r(1)
R/P-1
CCP2MX
bit 0
bit 7
bit 7-2 Unimplemented: Read as ‘0’
bit 1
bit 0
Reserved: Read as unknown(1)
CCP2MX: CCP2 Mux bit
In Microcontroller mode:
1= CCP2 input/output is multiplexed with RC1
0= CCP2 input/output is multiplexed with RE7
In Microprocessor, Microprocessor with Boot Block and Extended Microcontroller modes
(PIC18F8X20 devices only):
1= CCP2 input/output is multiplexed with RC1
0= CCP2 input/output is multiplexed with RB3
Note 1: Unimplemented in PIC18FX620 and PIC18FX720 devices; read as ‘0’.
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
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REGISTER 23-6: CONFIG4L:CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS300006h)
R/P-1
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
LVP
U-0
—
R/P-1
STVREN
bit 0
DEBUG
bit 7
bit 7
DEBUG: Background Debugger Enable bit
1= Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins.
0= Background debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug.
bit 6-3 Unimplemented: Read as ‘0’
bit 2
LVP: Low-Voltage ICSP Enable bit
1= Low-voltage ICSP enabled
0= Low-voltage ICSP disabled
bit 1
bit 0
Unimplemented: Read as ‘0’
STVREN: Stack Full/Underflow Reset Enable bit
1= Stack full/underflow will cause Reset
0= Stack full/underflow will not cause Reset
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
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REGISTER 23-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
R/P-1
CP7(1)
R/P-1
CP6(1)
R/P-1
CP5(1)
R/P-1
CP4(1)
R/P-1
CP3
R/P-1
CP2
R/P-1
CP1
R/P-1
CP0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
CP7: Code Protection bit(1)
1= Block 7 (01C000-01FFFFh) not code-protected
0= Block 7 (01C000-01FFFFh) code-protected
CP6: Code Protection bit(1)
1= Block 6 (018000-01BFFFh) not code-protected
0= Block 6 (018000-01BFFFh) code-protected
CP5: Code Protection bit(1)
1= Block 5 (014000-017FFFh) not code-protected
0= Block 5 (014000-017FFFh) code-protected
CP4: Code Protection bit(1)
1= Block 4 (010000-013FFFh) not code-protected
0= Block 4 (010000-013FFFh) code-protected
CP3: Code Protection bit
For PIC18FX520 devices:
1= Block 3 (006000-007FFFh) not code-protected
0= Block 3 (006000-007FFFh) code-protected
For PIC18FX620 and PIC18FX720 devices:
1= Block 3 (00C000-00FFFFh) not code-protected
0= Block 3 (00C000-00FFFFh) code-protected
bit 2
bit 1
bit 0
CP2: Code Protection bit
For PIC18FX520 devices:
1= Block 2 (004000-005FFFh) not code-protected
0= Block 2 (004000-005FFFh) code-protected
For PIC18FX620 and PIC18FX720 devices:
1= Block 2 (008000-00BFFFh) not code-protected
0= Block 2 (008000-00BFFFh) code-protected
CP1: Code Protection bit
For PIC18FX520 devices:
1= Block 1 (002000-003FFFh) not code-protected
0= Block 1 (002000-003FFFh) code-protected
For PIC18FX620 and PIC18FX720 devices:
1= Block 1 (004000-007FFFh) not code-protected
0= Block 1 (004000-007FFFh) code-protected
CP0: Code Protection bit
For PIC18FX520 devices:
1= Block 0 (000800-001FFFh) not code-protected
0= Block 0 (000800-001FFFh) code-protected
For PIC18FX620 and PIC18FX720 devices:
1= Block 0 (000200-003FFFh) not code-protected
0= Block 0 (000200-003FFFh) code-protected
Note 1: Unimplemented in PIC18FX520 and PIC18FX620 devices; maintain this bit set.
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
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PIC18F6520/8520/6620/8620/6720/8720
REGISTER 23-8: CONFIG5H:CONFIGURATIONREGISTER5 HIGH(BYTEADDRESS300009h)
R/C-1
CPD
R/C-1
CPB
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
bit 7
bit 6
CPD: Data EEPROM Code Protection bit
1= Data EEPROM not code-protected
0= Data EEPROM code-protected
CPB: Boot Block Code Protection bit
For PIC18FX520 devices:
1= Boot Block (000000-0007FFh) not code-protected
0= Boot Block (000000-0007FFh) code-protected
For PIC18FX620 and PIC18FX720 devices:
1= Boot Block (000000-0001FFh) not code-protected
0= Boot Block (000000-0001FFh) code-protected
bit 5-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
C = Clearable bit
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
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PIC18F6520/8520/6620/8620/6720/8720
REGISTER 23-9: CONFIG6L:CONFIGURATIONREGISTER6 LOW(BYTE ADDRESS30000Ah)
R/P-1
WRT7(1) WRT6(1)
R/P-1
R/P-1
WRT5(1)
R/P-1
WRT4(1)
R/P-1
WRT3
R/P-1
WRT2
R/P-1
R/P-1
WRT1
WRT0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
WR7: Write Protection bit(1)
1= Block 7 (01C000-01FFFFh) not write-protected
0= Block 7 (01C000-01FFFFh) write-protected
WR6: Write Protection bit(1)
1= Block 6 (018000-01BFFFh) not write-protected
0= Block 6 (018000-01BFFFh) write-protected
WR5: Write Protection bit(1)
1= Block 5 (014000-017FFFh) not write-protected
0= Block 5 (014000-017FFFh) write-protected
WR4: Write Protection bit(1)
1= Block 4 (010000-013FFFh) not write-protected
0= Block 4 (010000-013FFFh) write-protected
WR3: Write Protection bit
For PIC18FX520 devices:
1= Block 3 (006000-007FFFh) not write-protected
0= Block 3 (006000-007FFFh) write-protected
For PIC18FX620 and PIC18FX720 devices:
1= Block 3 (00C000-00FFFFh) not write-protected
0= Block 3 (00C000-00FFFFh) write-protected
bit 2
bit 1
bit 0
WR2: Write Protection bit
For PIC18FX520 devices:
1= Block 2 (004000-005FFFh) not write-protected
0= Block 2 (004000-005FFFh) write-protected
For PIC18FX620 and PIC18FX720 devices:
1= Block 2 (008000-00BFFFh) not write-protected
0= Block 2 (008000-00BFFFh) write-protected
WR1: Write Protection bit
For PIC18FX520 devices:
1= Block 1 (002000-003FFFh) not write-protected
0= Block 1 (002000-003FFFh) write-protected
For PIC18FX620 and PIC18FX720 devices:
1= Block 1 (004000-007FFFh) not write-protected
0= Block 1 (004000-007FFFh) write-protected
WR0: Write Protection bit
For PIC18FX520 devices:
1= Block 0 (000800-001FFFh) not write-protected
0= Block 0 (000800-001FFFh) write-protected
For PIC18FX620 and PIC18FX720 devices:
1= Block 0 (000200-003FFFh) not write-protected
0= Block 0 (000200-003FFFh) write-protected
Note 1: Unimplemented in PIC18FX520 and PIC18FX620 devices; maintain this bit set.
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
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REGISTER 23-10: CONFIG6H:CONFIGURATION REGISTER 6 HIGH(BYTE ADDRESS30000Bh)
R/P-1
R/P-1
R-1
WRTC(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
WRTD
WRTB
bit 7
bit 0
bit 7
bit 6
WRTD: Data EEPROM Write Protection bit
1= Data EEPROM not write-protected
0= Data EEPROM write-protected
WRTB: Boot Block Write Protection bit
For PIC18FX520 devices:
1= Boot Block (000000-0007FFh) not write-protected
0= Boot Block (000000-0007FFh) write-protected
For PIC18FX620 and PIC18FX720 devices:
1= Boot Block (000000-0001FFh) not write-protected
0= Boot Block (000000-0001FFh) write-protected
bit 5
WRTC: Configuration Register Write Protection bit(1)
1= Configuration registers (300000-3000FFh) not write-protected
0= Configuration registers (300000-3000FFh) write-protected
Note 1: This bit is read-only and cannot be changed in user mode.
bit 4-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
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REGISTER 23-11: CONFIG7L:CONFIGURATIONREGISTER7 LOW(BYTE ADDRESS30000Ch)
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
EBTR7(1) EBTR6(1) EBTR5(1) EBTR4(1)
EBTR3
EBTR2
EBTR1
EBTR0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
EBTR7: Table Read Protection bit(1)
1= Block 3 (01C000-01FFFFh) not protected from table reads executed in other blocks
0= Block 3 (01C000-01FFFFh) protected from table reads executed in other blocks
EBTR6: Table Read Protection bit(1)
1= Block 2 (018000-01BFFFh) not protected from table reads executed in other blocks
0= Block 2 (018000-01BFFFh) protected from table reads executed in other blocks
EBTR5: Table Read Protection bit(1)
1= Block 1 (014000-017FFFh) not protected from table reads executed in other blocks
0= Block 1 (014000-017FFFh) protected from table reads executed in other blocks
EBTR4: Table Read Protection bit(1)
1= Block 0 (010000-013FFFh) not protected from table reads executed in other blocks
0= Block 0 (010000-013FFFh) protected from table reads executed in other blocks
EBTR3: Table Read Protection bit
For PIC18FX520 devices:
1= Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
0= Block 3 (006000-007FFFh) protected from table reads executed in other blocks
For PIC18FX620 and PIC18FX720 devices:
1= Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks
0= Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks
bit 2
bit 1
bit 0
EBTR2: Table Read Protection bit
For PIC18FX520 devices:
1= Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
0= Block 2 (004000-005FFFh) protected from table reads executed in other blocks
For PIC18FX620 and PIC18FX720 devices:
1= Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks
0= Block 2 (008000-00BFFFh) protected from table reads executed in other blocks
EBTR1: Table Read Protection bit
For PIC18FX520 devices:
1= Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
0= Block 1 (002000-003FFFh) protected from table reads executed in other blocks
For PIC18FX620 and PIC18FX720 devices:
1= Block 1 (004000-007FFFh) not protected from table reads executed in other blocks
0= Block 1 (004000-007FFFh) protected from table reads executed in other blocks
EBTR0: Table Read Protection bit
For PIC18FX520 devices:
1= Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
0= Block 0 (000800-001FFFh) protected from table reads executed in other blocks
For PIC18FX620 and PIC18FX720 devices:
1= Block 0 (000200-003FFFh) not protected from table reads executed in other blocks
0= Block 0 (000200-003FFFh) protected from table reads executed in other blocks
Note 1: Unimplemented in PIC18FX520 and PIC18FX620 devices; maintain this bit set.
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
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REGISTER 23-12: CONFIG7H:CONFIGURATION REGISTER 7 HIGH(BYTE ADDRESS30000Dh)
U-0
—
R/P-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
EBTRB
bit 7
bit 0
bit 7
bit 6
Unimplemented: Read as ‘0’
EBTRB: Boot Block Table Read Protection bit
For PIC18FX520 devices:
1= Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
0= Boot Block (000000-0007FFh) protected from table reads executed in other blocks
For PIC18FX620 and PIC18FX720 devices:
1= Boot Block (000000-0001FFh) not protected from table reads executed in other blocks
0= Boot Block (000000-0001FFh) protected from table reads executed in other blocks
bit 5-0 Unimplemented: Read as ‘0’
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
REGISTER 23-13: DEVICE ID REGISTER 1 FOR PIC18FXX20 DEVICES (ADDRESS 3FFFFEh)
R
R
R
R
R
R
R
R
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
bit 7-5 DEV2:DEV0: Device ID bits
000= PIC18F8720
001= PIC18F6720
010= PIC18F8620
011= PIC18F6620
bit 4-0 REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
REGISTER 23-14: DEVICE ID REGISTER 2 FOR PIC18FXX20 DEVICES (ADDRESS 3FFFFFh)
R
R
R
R
R
R
R
R
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 0
bit 7
bit 7-0 DEV10:DEV3: Device ID bits
These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part
number.
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
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The WDT time-out period values may be found in the
23.2 Watchdog Timer (WDT)
Electrical Specifications section under parameter #31.
Values for the WDT postscaler may be assigned using
the configuration bits.
The Watchdog Timer is a free running, on-chip RC
oscillator, which does not require any external com-
ponents. This RC oscillator is separate from the RC
oscillator of the OSC1/CLKI pin. That means that the
WDT will run, even if the clock on the OSC1/CLKI and
OSC2/CLKO/RA6 pins of the device has been stopped,
for example, by execution of a SLEEPinstruction.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler, if
assigned to the WDT and prevent it from
timing out and generating a device Reset
condition.
During normal operation, a WDT time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer wake-up). The TO bit in the RCON register
will be cleared upon a WDT time-out.
2: When a CLRWDT instruction is executed
and the postscaler is assigned to the
WDT, the postscaler count will be cleared,
but the postscaler assignment is not
changed.
The Watchdog Timer is enabled/disabled by a device
configuration bit. If the WDT is enabled, software exe-
cution may not disable this function. When the WDTEN
configuration bit is cleared, the SWDTEN bit enables/
disables the operation of the WDT.
23.2.1
CONTROL REGISTER
Register 23-15 shows the WDTCON register. This is a
readable and writable register, which contains a control
bit that allows software to override the WDT enable
configuration bit, only when the configuration bit has
disabled the WDT.
REGISTER 23-15: WDTCON REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SWDTEN
bit 0
bit 7
bit 7-1 Unimplemented: Read as ‘0’
bit 0
SWDTEN: Software Controlled Watchdog Timer Enable bit
1= Watchdog Timer is on
0= Watchdog Timer is turned off if the WDTEN configuration bit in the configuration register = 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
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23.2.2
WDT POSTSCALER
The WDT has a postscaler that can extend the WDT
Reset period. The postscaler is selected at the time of
the device programming by the value written to the
CONFIG2H Configuration register.
FIGURE 23-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDT Timer
Postscaler
8
WDTPS2:WDTPS0
8-to-1 MUX
WDTEN
Configuration bit
SWDTEN bit
WDT
Time-out
Note:
WDPS2:WDPS0 are bits in register CONFIG2H.
TABLE 23-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONFIG2H
RCON
—
IPEN
—
—
—
—
—
—
—
—
RI
—
WDTPS2 WDTPS2 WDTPS0
WDTEN
BOR
TO
—
PD
—
POR
—
WDTCON
SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
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External MCLR Reset will cause a device Reset. All
23.3 Power-down Mode (Sleep)
other events are considered a continuation of program
execution and will cause a “wake-up”. The TO and PD
bits in the RCON register can be used to determine the
cause of the device Reset. The PD bit, which is set on
power-up, is cleared when Sleep is invoked. The TO bit
is cleared if a WDT time-out occurred (and caused
wake-up).
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared, but
keeps running, the PD bit (RCON<3>) is cleared, the
TO (RCON<4>) bit is set and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low or high-impedance).
When the SLEEPinstruction is being executed, the next
instruction (PC + 2) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOPafter the SLEEPinstruction.
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are high-impedance inputs, high or low externally,
to avoid switching currents caused by floating inputs.
The T0CKI input should also be at VDD or VSS for low-
est current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
23.3.2
WAKE-UP USING INTERRUPTS
23.3.1
WAKE-UP FROM SLEEP
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
The device can wake-up from Sleep through one of the
following events:
1. External Reset input on MCLR pin.
• If an interrupt condition (interrupt flag bit and
interrupt enable bits are set) occurs before the
execution of a SLEEPinstruction, the SLEEP
instruction will complete as a NOP. Therefore, the
WDT and WDT postscaler will not be cleared, the
TO bit will not be set and PD bits will not be
cleared.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or a
peripheral interrupt.
The following peripheral interrupts can wake the device
from Sleep:
• If the interrupt condition occurs during or after
the execution of a SLEEPinstruction, the device
will immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
1. PSP read or write.
2. TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
3. TMR3 interrupt. Timer3 must be operating as an
asynchronous counter.
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
4. CCP Capture mode interrupt.
5. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
6. MSSP (Start/Stop) bit detect interrupt.
7. MSSP transmit or receive in Slave mode
(SPI/I2C).
8. USART RX or TX (Synchronous Slave mode).
9. A/D conversion (when A/D clock source is RC).
10. EEPROM write operation complete.
11. LVD interrupt.
To ensure that the WDT is cleared, a CLRWDTinstruction
should be executed before a SLEEPinstruction.
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.
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FIGURE 23-2:
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKO(4)
INT pin
(2)
TOST
INTF flag
(INTCON<1>)
Interrupt Latency(3)
GIEH bit
(INTCON<7>)
Processor in
Sleep
INSTRUCTION FLOW
PC
PC
PC+2
PC+4
PC+4
PC + 4
0008h
000Ah
Instruction
Fetched
Inst(0008h)
Inst(PC + 2)
Inst(PC + 4)
Inst(PC + 2)
Inst(000Ah)
Inst(PC) = Sleep
Instruction
Executed
Dummy Cycle
Dummy Cycle
Inst(0008h)
Sleep
Inst(PC - 1)
Note 1: XT, HS or LP Oscillator mode assumed.
2: GIE = 1assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
3: TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Oscillator modes.
4: CLKO is not available in these oscillator modes, but shown here for timing reference.
In the PIC18FXX20 family, the block size varies with
the size of the user program memory. For PIC18FX520
devices, program memory is divided into four blocks of
23.4 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC® devices. The user program memory is divided on
binary boundaries into individual blocks, each of which
has three separate code protection bits associated with
it:
8 Kbytes each. The first block is further divided into a
boot block of 2 Kbytes and a second block (Block 0) of
6 Kbytes, for a total of five blocks. The organization of
the blocks and their associated code protection bits are
shown in Figure 23-3.
For PIC18FX620 and PIC18FX720 devices, program
memory is divided into blocks of 16 Kbytes. The first
block is further divided into a boot block of 512 bytes
and a second block (Block 0) of 15.5 Kbytes, for a total
of nine blocks. This produces five blocks for 64-Kbyte
devices and nine for 128-Kbyte devices. The organiza-
tion of the blocks and their associated code protection
bits are shown in Figure 23-4.
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
The code protection bits are located in Configuration
Registers 5L through 7H. Their locations within the
registers are summarized in Table 23-3.
TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300008h
CONFIG5L
CONFIG5H
CP7(1)
CP6(1)
CP5(1)
CP4(1)
CP3
—
CP2
—
CP1
—
CP0
—
300009h
30000Ah
30000Bh
30000Ch
30000Dh
CPD
CPB
—
—
CONFIG6L WRT7(1) WRT6(1) WRT5(1) WRT4(1)
WRT3
WRT2
—
WRT1
—
WRT0
—
CONFIG6H WRTD WRTB WRTC
CONFIG7L EBTR7(1) EBTR6(1) EBTR5(1) EBTR4(1) EBTR3
—
—
EBTR2
—
EBTR1
—
EBTR0
—
CONFIG7H EBTRB
—
—
—
—
Legend: Shaded cells are unimplemented.
Note 1: Unimplemented in PIC18FX520 and PIC18FX620 devices.
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FIGURE 23-3:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18FX520 DEVICES
Address
Range
Block Code Protection
Controlled By:
32 Kbytes
000000h
0007FFh
Boot Block
Block 0
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
000800h
001FFFh
002000h
Block 1
Block 2
Block 3
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
003FFFh
004000h
005FFFh
006000h
007FFFh
008000h
Unimplemented
Read ‘0’s
1FFFFFh
FIGURE 23-4:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18FX620/X720 DEVICES
MEMORY SIZE/DEVICE
Block Code Protection
Controlled By:
64 Kbytes
128 Kbytes
Address
Range
(PIC18FX620)
(PIC18FX720)
000000h
0001FFh
Boot Block
Boot Block
Block 0
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
000200h
003FFFh
Block 0
Block 1
004000h
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
CP4, WRT4, EBTR4
CP5, WRT5, EBTR5
CP6, WRT6, EBTR6
CP7, WRT7, EBTR7
007FFFh
008000h
Block 2
Block 3
00BFFFh
00C000h
00FFFFh
010000h
013FFFh
014000h
017FFFh
018000h
Unimplemented
Read ‘0’s
01BFFFh
01C000h
01FFFFh
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side of that block is not allowed to read and will result
in reading ‘0’s. Figures 23-5 through 23-7 illustrate
table write and table read protection using devices with
a 16-Kbyte block size as the models. The principles
illustrated are identical for devices with an 8-Kbyte
block size.
23.4.1
PROGRAM MEMORY
CODE PROTECTION
The user memory may be read to, or written from, any
location using the table read and table write instruc-
tions. The device ID may be read with table reads. The
configuration registers may be read and written with the
table read and table write instructions.
Note:
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code pro-
tection bits are only set to ‘1’ by a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP or an external
programmer.
In user mode, the CPn bits have no direct effect. CPn
bits inhibit external reads and writes. A block of user
memory may be protected from table writes if the
WRTn configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the
EBTRn bit set to ‘0’, a table read instruction that
executes from within that block is allowed to read. A
table read instruction that executes from a location out-
FIGURE 23-5:
TABLE WRITE (WRTn) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0001FFh
000200h
WRTB, EBTRB = 11
TBLPTR = 000FFFh
PC = 003FFEh
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
TBLWT *
003FFFh
004000h
007FFFh
008000h
TBLWT *
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
PC = 008FFEh
00BFFFh
00C000h
00FFFFh
Results: All table writes disabled to Block n whenever WRTn = 0.
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FIGURE 23-6:
EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0001FFh
000200h
WRTB, EBTRB = 11
TBLPTR = 000FFFh
WRT0, EBTR0 = 10
003FFFh
004000h
TBLRD *
PC = 004FFEh
WRT1, EBTR1 = 11
007FFFh
008000h
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
00BFFFh
00C000h
00FFFFh
Results: All table reads from external blocks to Block n are disabled whenever EBTRn = 0.
TABLAT register returns a value of ‘0’.
FIGURE 23-7:
EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0001FFh
000200h
WRTB, EBTRB = 11
TBLPTR = 000FFFh
PC = 003FFEh
WRT0, EBTR0 = 10
TBLRD *
003FFFh
004000h
WRT1, EBTR1 = 11
007FFFh
008000h
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
00BFFFh
00C000h
00FFFFh
Results: Table reads permitted within Block n, even when EBTRBn = 0.
TABLAT register returns the value of the data at the location TBLPTR.
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23.4.2
DATA EEPROM
CODE PROTECTION
TABLE 23-4: DEBUGGER RESOURCES
I/O pins
RB6, RB7
2 levels
Stack
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits external writes to data EEPROM. The
CPU can continue to read and write data EEPROM,
regardless of the protection bit settings.
Program Memory
Data Memory
Last 576 bytes
Last 10 bytes
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
23.4.3
CONFIGURATION REGISTER
PROTECTION
The configuration registers can be write-protected. The
WRTC bit controls protection of the configuration regis-
ters. In user mode, the WRTC bit is readable only.
WRTC can only be written via ICSP or an external
programmer.
23.8 Low-Voltage ICSP Programming
The LVP bit in the CONFIG4L Configuration register
enables Low-Voltage ICSP Programming. This mode
allows the microcontroller to be programmed via ICSP
using a VDD source in the operating voltage range. This
only means that VPP does not have to be brought to
VIHH, but can instead be left at the normal operating
voltage. In this mode, the RB5/PGM pin is dedicated to
the programming function and ceases to be a general
purpose I/O pin. During programming, VDD is applied to
the MCLR/VPP pin. To enter Programming mode, VDD
must be applied to the RB5/PGM pin, provided the LVP
bit is set. The LVP bit defaults to a ‘1’ from the factory.
23.5 ID Locations
Eight memory locations (200000h-200007h) are
designated as ID locations, where the user can store
checksum or other code identification numbers. These
locations are accessible during normal execution
through the TBLRD and TBLWT instructions or during
program/verify. The ID locations can be read when the
device is code-protected.
Note 1: The High-Voltage Programming mode is
always available, regardless of the state
of the LVP bit, by applying VIHH to the
MCLR pin.
23.6
In-Circuit Serial Programming
PIC18FX520/X620/X720 microcontrollers can be seri-
ally programmed while in the end application circuit.
This is simply done with two lines for clock and data
and three other lines for power, ground and the
programming voltage. This allows customers to manu-
facture boards with unprogrammed devices and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
2: While in Low-Voltage ICSP mode, the
RB5 pin can no longer be used as a
general purpose I/O pin and should be
held low during normal operation.
3: When using Low-Voltage ICSP Program-
ming (LVP) and the pull-ups on PORTB are
enabled, bit 5 in the TRISB register must be
cleared to disable the pull-up on RB5 and
ensure the proper operation of the device.
Note:
When
performing
In-Circuit
Serial
Programming, verify that power is con-
nected to all VDD and AVDD pins of the
microcontroller and that all VSS and AVSS
pins are grounded.
If Low-Voltage Programming mode is not used, the LVP
bit can be programmed to a ‘0’ and RB5/PGM becomes
a digital I/O pin. However, the LVP bit may only be
programmed when programming is entered with VIHH
on MCLR/VPP.
23.7 In-Circuit Debugger
It should be noted that once the LVP bit is programmed
to ‘0’, only the High-Voltage Programming mode is
available and only High-Voltage Programming mode
can be used to program the device.
When the DEBUG bit in the CONFIG4L Configuration
register is programmed to a ‘0’, the In-Circuit Debugger
functionality is enabled. This function allows simple
debugging functions when used with MPLAB® IDE.
When the microcontroller has this feature enabled,
some of the resources are not available for general
use. Table 23-4 shows which features are consumed
by the background debugger.
When using Low-Voltage ICSP Programming, the part
must be supplied 4.5V to 5.5V if a bulk erase will be
executed. This includes reprogramming of the code-
protect bits from an on state to an off state. For all other
cases of Low-Voltage ICSP, the part may be
programmed at the normal operating voltage. This
means unique user IDs or user code can be
reprogrammed or added.
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NOTES:
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The literal instructions may use some of the following
operands:
24.0 INSTRUCTION SET SUMMARY
The PIC18 instruction set adds many enhancements to
the previous PIC MCU instruction sets, while maintain-
ing an easy migration from these PIC MCU instruction
sets.
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
Most instructions are a single program memory word
(16 bits), but there are three instructions that require
two program memory locations.
• No operand required
(specified by ‘—’)
The control instructions may use some of the following
operands:
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
• A program memory address (specified by ‘n’)
• The mode of the CALLor RETURNinstructions
(specified by ‘s’)
The instruction set is highly orthogonal and is grouped
into four basic categories:
• The mode of the table read and table write
instructions (specified by ‘m’)
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
• No operand required
(specified by ‘—’)
All instructions are a single word, except for three
double-word instructions. These three instructions
were made double-word instructions so that all the
required information is available in these 32 bits. In the
second word, the 4 MSbs are ‘1’s. If this second word
is executed as an instruction (by itself), it will execute
as a NOP.
• Control operations
The PIC18 instruction set summary in Table 24-1 lists
byte-oriented, bit-oriented, literal and control
operations. Table 24-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.
1. The file register (specified by ‘f’)
2. The destination of the result
(specified by ‘d’)
3. The accessed memory
(specified by ‘a’)
The file register designator ‘f’ specifies which file
register is to be used by the instruction.
The double-word instructions execute in two instruction
cycles.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If ‘d’ is zero, the
result is placed in the WREG register. If ‘d’ is one, the
result is placed in the file register specified in the
instruction.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
Two-word branch instructions (if true) would take 3 s.
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
Figure 24-1 shows the general formats that the
instructions can have.
2. The bit in the file register
(specified by ‘b’)
All examples use the format ‘nnh’ to represent a hexa-
decimal number, where ‘h’ signifies a hexadecimal
digit.
3. The accessed memory
(specified by ‘a’)
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register desig-
nator ‘f’ represents the number of the file in which the
bit is located.
The Instruction Set Summary, shown in Table 24-1,
lists the instructions recognized by the Microchip
Assembler (MPASMTM).
Section 24.1 “Instruction Set” provides a description
of each instruction.
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TABLE 24-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
BSR
d
Bit address within an 8-bit file register (0 to 7).
Bank Select Register. Used to select the current RAM bank.
Destination select bit
d = 0: store result in WREG
d = 1: store result in file register f
dest
f
Destination either the WREG register or the specified register file location.
8-bit Register file address (0x00 to 0xFF).
fs
12-bit Register file address (0x000 to 0xFFF). This is the source address.
12-bit Register file address (0x000 to 0xFFF). This is the destination address.
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
Label name.
fd
k
label
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
*
No Change to register (such as TBLPTR with table reads and writes)
Post-Increment register (such as TBLPTR with table reads and writes)
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
*+
*-
+*
n
The relative address (2’s complement number) for relative branch instructions, or the direct address for Call/
Branch and Return instructions.
PRODH
PRODL
s
Product of Multiply High Byte.
Product of Multiply Low Byte.
Fast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
u
Unused or Unchanged.
WREG
x
Working register (accumulator).
Don’t care (‘0’ or ‘1’).
The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all
Microchip software tools.
TBLPTR
TABLAT
TOS
21-bit Table Pointer (points to a Program Memory location).
8-bit Table Latch.
Top-of-Stack.
PC
Program Counter.
PCL
Program Counter Low Byte.
Program Counter High Byte.
Program Counter High Byte Latch.
Program Counter Upper Byte Latch.
Global Interrupt Enable bit.
Watchdog Timer.
PCH
PCLATH
PCLATU
GIE
WDT
TO
Time-out bit.
PD
Power-down bit.
C, DC, Z, OV, N
ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
Optional.
[
]
)
(
Contents.
< >
Assigned to.
Register bit field.
In the set of.
italics
User defined term (font is courier).
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FIGURE 24-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15 10
OPCODE f (FILE #)
Example Instruction
9
8
7
0
ADDWF MYREG, W, B
d
a
d = 0for result destination to be WREG register
d = 1for result destination to be file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
0
OPCODE
f (Source FILE #)
MOVFF MYREG1, MYREG2
15
12 11
1111
f (Destination FILE #)
f = 12-bit file register address
Bit-oriented file register operations
15 12 11 9 8
OPCODE b (BIT #)
7
0
BSF MYREG, bit, B
a
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0to force Access Bank
a = 1for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
0
MOVLW 0x7F
OPCODE
k (literal)
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
0
GOTO Label
OPCODE
12 11
n<7:0> (literal)
15
0
1111
n<19:8> (literal)
n = 20-bit immediate value
15
15
8
7
0
CALL MYFUNC
OPCODE
12 11
n<7:0> (literal)
S
0
n<19:8> (literal)
S = Fast bit
11 10
15
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
n<10:0> (literal)
15
OPCODE
8 7
n<7:0> (literal)
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TABLE 24-1: PIC18FXXXX INSTRUCTION SET
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
f, d, a Add WREG and f
f, d, a Add WREG and Carry bit to f
f, d, a AND WREG with f
1
1
1
1
1
0010 01da
0010 00da
0001 01da
0110 101a
0001 11da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff C, DC, Z, OV, N 1, 2
ffff C, DC, Z, OV, N 1, 2
ffff Z, N
ffff
1,2
2
f, a
Clear f
Z
COMF
f, d, a Complement f
ffff Z, N
ffff None
ffff None
ffff None
1, 2
4
4
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
f, a
f, a
f, a
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
1 (2 or 3) 0110 001a
1 (2 or 3) 0110 010a
1 (2 or 3) 0110 000a
1, 2
f, d, a Decrement f
1
0000 01da
ffff C, DC, Z, OV, N 1, 2, 3, 4
f, d, a Decrement f, Skip if 0
f, d, a Decrement f, Skip if Not 0
f, d, a Increment f
f, d, a Increment f, Skip if 0
f, d, a Increment f, Skip if Not 0
f, d, a Inclusive OR WREG with f
f, d, a Move f
1 (2 or 3) 0010 11da
1 (2 or 3) 0100 11da
1
1 (2 or 3) 0011 11da
1 (2 or 3) 0100 10da
1
1
2
ffff None
ffff None
1, 2, 3, 4
1, 2
0010 10da
ffff C, DC, Z, OV, N 1, 2, 3, 4
ffff None
ffff None
ffff Z, N
ffff Z, N
ffff None
ffff
4
1, 2
1, 2
1
0001 00da
0101 00da
1100 ffff
1111 ffff
0110 111a
0000 001a
0110 110a
0011 01da
0100 01da
0011 00da
0100 00da
0110 100a
0101 01da
MOVFF
f , f
Move f (source) to 1st word
s
d
s
f (destination) 2nd word
d
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
f, a
f, a
f, a
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
ffff None
ffff None
ffff C, DC, Z, OV, N 1, 2
ffff C, Z, N
f, d, a Rotate Left f through Carry
f, d, a Rotate Left f (No Carry)
f, d, a Rotate Right f through Carry
f, d, a Rotate Right f (No Carry)
ffff Z, N
ffff C, Z, N
ffff Z, N
ffff None
1, 2
f, a
Set f
f, d, a Subtract f from WREG with
borrow
ffff C, DC, Z, OV, N 1, 2
SUBWF
SUBWFB
f, d, a Subtract WREG from f
f, d, a Subtract WREG from f with
borrow
1
1
0101 11da
0101 10da
ffff
ffff
ffff C, DC, Z, OV, N
ffff C, DC, Z, OV, N 1, 2
SWAPF
TSTFSZ
XORWF
f, d, a Swap nibbles in f
1
0011 10da
ffff
ffff
ffff
ffff None
ffff None
ffff Z, N
4
1, 2
f, a
Test f, skip if 0
1 (2 or 3) 0110 011a
1
f, d, a Exclusive OR WREG with f
0001 10da
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a Bit Clear f
f, b, a Bit Set f
f, b, a Bit Test f, Skip if Clear
f, b, a Bit Test f, Skip if Set
f, d, a Bit Toggle f
1
1
1001 bbba
1000 bbba
ffff
ffff
ffff
ffff
ffff
ffff None
ffff None
ffff None
ffff None
ffff None
1, 2
1, 2
3, 4
3, 4
1, 2
1 (2 or 3) 1011 bbba
1 (2 or 3) 1010 bbba
1
0111 bbba
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOPunless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
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TABLE 24-1: PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
1 (2)
1110 0010
1110 0110
1110 0011
1110 0111
1110 0101
1110 0001
1110 0100
1101 0nnn
1110 0000
1110 110s
1111 kkkk
0000 0000
0000 0000
1110 1111
1111 kkkk
0000 0000
1111 xxxx
0000 0000
0000 0000
1101 1nnn
0000 0000
0000 0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
kkkk None
kkkk
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
1 (2)
2
CALL
CLRWDT
DAW
GOTO
—
—
n
1
1
2
0100 TO, PD
0111
C
kkkk None
kkkk
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
No Operation
1
1
1
1
2
1
2
0000 None
xxxx None
0110 None
0101 None
nnnn None
1111 All
4
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
s
000s GIE/GIEH,
PEIE/GIEL
RETLW
RETURN
SLEEP
k
s
—
Return with literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
0000 1100
0000 0000
0000 0000
kkkk
0001
0000
kkkk None
001s None
0011 TO, PD
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOPunless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
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TABLE 24-1: PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word
1
1
1
2
0000 1111 kkkk
0000 1011 kkkk
0000 1001 kkkk
1110 1110 00ff
1111 0000 kkkk
0000 0001 0000
0000 1110 kkkk
0000 1101 kkkk
0000 1100 kkkk
0000 1000 kkkk
0000 1010 kkkk
kkkk C, DC, Z, OV, N
kkkk Z, N
kkkk Z, N
kkkk None
kkkk
kkkk None
kkkk None
kkkk None
kkkk None
kkkk C, DC, Z, OV, N
kkkk Z, N
to FSRx
1st word
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
Exclusive OR literal with WREG
1
1
1
2
1
1
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
1000 None
1001 None
1010 None
1011 None
1100 None
1101 None
1110 None
1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
2 (5)
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an
external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOPunless the
first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory
locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
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24.1 Instruction Set
ADDLW
ADD literal to W
ADDWF
ADD W to f
Syntax:
[ label ] ADDLW
0 k 255
k
Syntax:
[ label ] ADDWF
f [,d [,a] f [,d [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 f 255
d [0,1]
a [0,1]
(W) + k W
N, OV, C, DC, Z
Operation:
(W) + (f) dest
0000
1111
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
Description:
The contents of W are added to the
8-bit literal ‘k’ and the result is
placed in W.
0010
01da
ffff
ffff
Description:
Add W to register ‘f’. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected. If ‘a’ is ‘1’,
the BSR is used.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
ADDLW
0x15
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
Write to
destination
W
=
0x10
After Instruction
W
=
0x25
ADDWF
REG, 0, 0
Example:
Before Instruction
W
REG
=
=
0x17
0xC2
After Instruction
W
REG
=
=
0xD9
0xC2
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ADDWFC
ADD W and Carry bit to f
ANDLW
AND literal with W
Syntax:
[ label ] ADDWFC
f [,d [,a]
Syntax:
[ label ] ANDLW
0 k 255
k
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
Operation:
Status Affected:
Encoding:
(W) .AND. k W
N, Z
Operation:
(W) + (f) + (C) dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
Description:
The contents of W are AND’ed with
the 8-bit literal ‘k’. The result is
placed in W.
0010
00da
ffff
ffff
Description:
Add W, the Carry flag and data
memory location ‘f’. If ‘d’ is ‘0’, the
result is placed in W. If ‘d’ is ‘1’, the
result is placed in data memory
location ‘f’. If ‘a’ is ‘0’, the Access
Bank will be selected. If ‘a’ is ‘1’, the
BSR will not be overridden.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
ANDLW
0x5F
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
W
=
0xA3
0x03
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
=
ADDWFC
REG, 0, 1
Example:
Before Instruction
Carry bit =
1
REG
W
=
=
0x02
0x4D
After Instruction
Carry bit =
0
0x02
0x50
REG
W
=
=
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ANDWF
AND W with f
BC
Branch if Carry
[ label ] BC
Syntax:
[ label ] ANDWF
f [,d [,a]
Syntax:
n
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
Operation:
-128 n 127
if Carry bit is ‘1’
(PC) + 2 + 2n PC
Operation:
(W) .AND. (f) dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ‘1’, then the
Description:
The contents of W are AND’ed with
register ‘f’. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected. If ‘a’ is ‘1’, the BSR will
not be overridden (default).
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
ANDWF
REG, 0, 0
Example:
Before Instruction
If No Jump:
Q1
W
REG
=
=
0x17
0xC2
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
After Instruction
W
REG
=
=
0x02
0xC2
HERE
BC
5
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Carry
=
=
=
=
1;
PC
address (HERE+12)
0;
If Carry
PC
address (HERE+2)
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BCF
Bit Clear f
BN
Branch if Negative
[ label ] BN
Syntax:
[ label ] BCF f,b[,a]
Syntax:
n
Operands:
0 f 255
0 b 7
a [0,1]
Operands:
Operation:
-128 n 127
if Negative bit is ‘1’
(PC) + 2 + 2n PC
Operation:
0 f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ‘1’, then the
program will branch.
Description:
Bit ‘b’ in register ‘f’ is cleared. If ‘a’
is ‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
Q1
Q2
Q3
Q4
register ‘f’
Decode
Read literal
‘n’
Process
Data
Write to PC
BCF
FLAG_REG, 7, 0
Example:
No
operation
No
operation
No
operation
No
operation
Before Instruction
FLAG_REG = 0xC7
If No Jump:
Q1
After Instruction
Q2
Q3
Q4
FLAG_REG = 0x47
Decode
Read literal
‘n’
Process
Data
No
operation
HERE
BN Jump
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative
=
=
=
=
1;
PC
address (Jump)
If Negative
PC
0;
address (HERE+2)
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BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
[ label ] BNC
-128 n 127
if Carry bit is ‘0’
n
Syntax:
[ label ] BNN
-128 n 127
n
Operands:
Operation:
Operands:
Operation:
if Negative bit is ‘0’
(PC) + 2 + 2n PC
(PC) + 2 + 2n PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ‘0’, then the
program will branch.
Description:
If the Negative bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
HERE
BNC Jump
HERE
BNN Jump
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Carry
=
=
=
=
0;
If Negative
=
=
=
=
0;
PC
address (Jump)
PC
address (Jump)
If Carry
PC
1;
If Negative
PC
1;
address (HERE+2)
address (HERE+2)
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BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
[ label ] BNOV
-128 n 127
n
Syntax:
[ label ] BNZ
-128 n 127
if Zero bit is ‘0’
n
Operands:
Operation:
Operands:
Operation:
if Overflow bit is ‘0’
(PC) + 2 + 2n PC
(PC) + 2 + 2n PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ‘0’, then the
program will branch.
Description:
If the Zero bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read literal
‘n’
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Decode
Read literal
‘n’
Process
Data
No
operation
HERE
BNOV Jump
HERE
BNZ Jump
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Overflow
=
=
=
=
0;
If Zero
=
=
=
=
0;
PC
address (Jump)
PC
address (Jump)
If Overflow
PC
1;
If Zero
PC
1;
address (HERE+2)
address (HERE+2)
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BRA
Unconditional Branch
[ label ] BRA
BSF
Bit Set f
Syntax:
n
Syntax:
[ label ] BSF f,b[,a]
Operands:
Operation:
Status Affected:
Encoding:
-1024 n 1023
(PC) + 2 + 2n PC
None
Operands:
0 f 255
0 b 7
a [0,1]
Operation:
1 f<b>
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
Description:
Add the 2’s complement number
‘2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a
two-cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’,
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1,
then the bank will be selected as
per the BSR value.
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
No
No
No
No
operation
operation
operation
operation
BSF
FLAG_REG, 7, 1
Example:
Before Instruction
HERE
BRA Jump
Example:
FLAG_REG
=
=
0x0A
0x8A
Before Instruction
After Instruction
FLAG_REG
PC
=
=
address (HERE)
address (Jump)
After Instruction
PC
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BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
[ label ] BTFSC f,b[,a]
Syntax:
[ label ] BTFSS f,b[,a]
Operands:
0 f 255
0 b 7
a [0,1]
Operands:
0 f 255
0 b < 7
a [0,1]
Operation:
skip if (f<b>) = 0
None
Operation:
skip if (f<b>) = 1
None
Status Affected:
Encoding:
Status Affected:
Encoding:
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit ‘b’ in register ‘f’ is ‘0’, then the
next instruction is skipped.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped.
If bit ‘b’ is ‘0’, then the next
If bit ‘b’ is ‘1’, then the next
instruction fetched during the current
instruction execution is discarded
and a NOPis executed instead,
making this a two-cycle instruction. If
‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected
as per the BSR value (default).
instruction fetched during the current
instruction execution is discarded
and a NOPis executed instead,
making this a two-cycle instruction. If
‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value. If
‘a’ = 1, then the bank will be selected
as per the BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Example:
Example:
Before Instruction
PC
Before Instruction
PC
=
address (HERE)
=
address (HERE)
After Instruction
After Instruction
If FLAG<1>
=
=
=
=
0;
If FLAG<1>
=
=
=
=
0;
PC
address (TRUE)
1;
PC
address (FALSE)
1;
If FLAG<1>
PC
If FLAG<1>
PC
address (FALSE)
address (TRUE)
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BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
[ label ] BTG f,b[,a]
Syntax:
[ label ] BOV
-128 n 127
n
Operands:
0 f 255
0 b < 7
a [0,1]
Operands:
Operation:
if Overflow bit is ‘1’
(PC) + 2 + 2n PC
Operation:
(f<b>) f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ‘1’, then the
program will branch.
Description:
Bit ‘b’ in data memory location ‘f’ is
inverted. If ‘a’ is ‘0’, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
Q1
Q2
Q3
Q4
register ‘f’
Decode
Read literal
‘n’
Process
Data
Write to PC
BTG
PORTC, 4, 0
Example:
No
operation
No
operation
No
operation
No
operation
Before Instruction:
PORTC
=
0111 0101 [0x75]
If No Jump:
Q1
After Instruction:
Q2
Q3
Q4
PORTC
=
0110 0101 [0x65]
Decode
Read literal
‘n’
Process
Data
No
operation
HERE
BOV Jump
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Overflow
=
=
=
=
1;
PC
address (Jump)
If Overflow
PC
0;
address (HERE+2)
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BZ
Branch if Zero
[ label ] BZ
CALL
Subroutine Call
Syntax:
n
Syntax:
[ label ] CALL k [,s]
Operands:
Operation:
-128 n 127
Operands:
0 k 1048575
s [0,1]
if Zero bit is ‘1’
(PC) + 2 + 2n PC
Operation:
(PC) + 4 TOS,
k PC<20:1>,
if s = 1
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
(W) WS,
(STATUS) STATUSS,
(BSR) BSRS
Description:
If the Zero bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2-Mbyte
memory range. First, return
address (PC+ 4) is pushed onto the
return stack. If ‘s’ = 1, the W,
Words:
Cycles:
1
1(2)
Status and BSR registers are also
pushed into their respective
Q Cycle Activity:
If Jump:
shadow registers, WS, STATUSS
and BSRS. If ‘s’ = 0, no update
occurs (default). Then, the 20-bit
value ‘k’ is loaded into PC<20:1>.
CALLis a two-cycle instruction.
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
2
2
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
No
operation
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal Push PC to Read literal
HERE
BZ Jump
Example:
‘k’<7:0>
stack
‘k’<19:8>,
Write to PC
Before Instruction
PC
=
address (HERE)
No
No
No
No
operation
operation
operation
operation
After Instruction
If Zero
=
=
=
=
1;
PC
address (Jump)
HERE
CALL THERE,1
Example:
If Zero
PC
0;
address (HERE+2)
Before Instruction
PC
=
address (HERE)
After Instruction
PC
=
=
=
=
address (THERE)
TOS
WS
address (HERE + 4)
W
BSR
BSRS
STATUSS = STATUS
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CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRF f [,a]
Syntax:
[ label ] CLRWDT
Operands:
0 f 255
a [0,1]
Operands:
Operation:
None
000h WDT,
000h WDT postscaler,
1 TO,
Operation:
000h f
1 Z
1 PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits
TO and PD are set.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
No
operation
Process
Data
No
operation
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
CLRWDT
Example:
CLRF
FLAG_REG,1
Example:
Before Instruction
WDT Counter
=
?
Before Instruction
FLAG_REG
=
=
0x5A
0x00
After Instruction
WDT Counter
WDT Postscaler
TO
=
=
=
=
0x00
After Instruction
FLAG_REG
0
1
1
PD
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COMF
Complement f
CPFSEQ
Compare f with W, skip if f = W
Syntax:
[ label ] COMF f [,d [,a]
Syntax:
[ label ] CPFSEQ f [,a]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
(f) – (W),
Operation:
(f) dest
skip if (f) = (W)
(unsigned comparison)
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register ‘f’ are com-
plemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Description:
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
If ‘f’ = W, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1,
then the bank will be selected as
per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
register ‘f’
Process
Data
Write to
1(2)
destination
Note: 3 cycles if skip and followed
by a 2-word instruction.
COMF
REG, 0, 0
Example:
Before Instruction
Q Cycle Activity:
Q1
REG
=
0x13
Q2
Q3
Q4
After Instruction
Decode
Read
register ‘f’
Process
Data
No
operation
REG
=
0x13
W
=
0xEC
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
CPFSEQ REG, 0
Example:
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
=
HERE
W
REG
=
=
?
?
After Instruction
If REG
PC
=
=
W;
Address (EQUAL)
If REG
PC
=
W;
Address (NEQUAL)
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CPFSGT
Compare f with W, skip if f > W
CPFSLT
Compare f with W, skip if f < W
Syntax:
[ label ] CPFSGT f [,a]
Syntax:
[ label ] CPFSLT f [,a]
Operands:
0 f 255
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
(f) W),
Operation:
(f) –W),
skip if (f) > (W)
skip if (f) < (W)
(unsigned comparison)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
010a
ffff
ffff
0110
000a
ffff
ffff
Description:
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
Description:
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
If the contents of ‘f’ are greater than
the contents of WREG, then the
fetched instruction is discarded and
a NOPis executed instead, making
this a two-cycle instruction. If ‘a’ is
‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
If the contents of ‘f’ are less than
the contents of W, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’
is ‘1’, the BSR will not be
overridden (default).
Words:
Cycles:
1
1(2)
Words:
Cycles:
1
Note: 3 cycles if skip and followed
by a 2-word instruction.
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
No
operation
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
If skip:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
If skip and followed by 2-word instruction:
No
No
No
No
Q1
Q2
Q3
Q4
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
Example:
HERE
CPFSGT REG, 0
Example:
NGREATER
GREATER
:
:
Before Instruction
PC
W
=
=
Address (HERE)
?
Before Instruction
After Instruction
PC
=
=
Address (HERE)
?
W
If REG
PC
If REG
PC
<
=
=
W;
Address (LESS)
W;
After Instruction
If REG
=
=
W;
Address (NLESS)
PC
Address (GREATER)
W;
If REG
PC
Address (NGREATER)
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DAW
Decimal Adjust W Register
DECF
Decrement f
Syntax:
[ label ] DAW
Syntax:
[ label ] DECF f [,d [,a]
Operands:
Operation:
None
Operands:
0 f 255
d [0,1]
a [0,1]
If [W<3:0> >9] or [DC = 1] then
(W<3:0>) + 6 W<3:0>;
else
Operation:
(f) – 1 dest
(W<3:0>) W<3:0>;
Status Affected:
Encoding:
C, DC, N, OV, Z
0000
01da
ffff
ffff
If [W<7:4> >9] or [C = 1] then
(W<7:4>) + 6 W<7:4>;
else
Description:
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in W. If ‘d’ is ‘1’,
the result is stored back in register
‘f’ (default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
(W<7:4>) W<7:4>;
Status Affected:
Encoding:
C
0000
0000
0000
0111
Description:
DAW adjusts the eight-bit value in
W, resulting from the earlier
addition of two variables (each in
packed BCD format) and produces
a correct packed BCD result.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register W
Process
Data
Write
W
DECF
CNT,
1, 0
Example:
Before Instruction
CNT
Z
=
=
0x01
0
DAW
Example1:
After Instruction
Before Instruction
CNT
=
=
0x00
1
W
=
=
=
0xA5
0
0
Z
C
DC
After Instruction
W
=
=
=
0x05
1
0
C
DC
Example 2:
Before Instruction
W
=
=
=
0xCE
0
0
C
DC
After Instruction
W
=
=
=
0x34
1
0
C
DC
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DECFSZ
Decrement f, skip if 0
DCFSNZ
Decrement f, skip if not 0
Syntax:
[ label ] DECFSZ f [,d [,a]]
Syntax:
[ label ] DCFSNZ f [,d [,a]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) – 1 dest,
skip if result = 0
Operation:
(f) – 1 dest,
skip if result 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
11da
ffff
ffff
0100
11da
ffff
ffff
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is ‘0’, the next
If the result is not ‘0’, the next
instruction which is already fetched
is discarded and a NOPis executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
instruction which is already fetched
is discarded and a NOPis executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
DECFSZ
GOTO
CNT, 1, 1
LOOP
HERE
ZERO
NZERO
DCFSNZ TEMP, 1, 0
:
:
Example:
Example:
CONTINUE
Before Instruction
Before Instruction
TEMP
PC
=
Address (HERE)
=
?
After Instruction
After Instruction
CNT
=
=
=
=
CNT - 1
0;
TEMP
If TEMP
PC
If TEMP
PC
=
=
=
=
TEMP - 1,
If CNT
0;
PC
Address (CONTINUE)
0;
Address (ZERO)
0;
Address (NZERO)
If CNT
PC
Address (HERE+2)
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GOTO
Unconditional Branch
INCF
Increment f
Syntax:
[ label ] GOTO k
0 k 1048575
k PC<20:1>
None
Syntax:
[ label ] INCF f [,d [,a]
Operands:
Operation:
Status Affected:
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) + 1 dest
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Status Affected:
Encoding:
C, DC, N, OV, Z
1110
1111
1111
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
0010
10da
ffff
ffff
19
Description:
GOTOallows an unconditional
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
branch anywhere within the entire
2-Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>.
GOTOis always a two-cycle
instruction.
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read literal
‘k’<7:0>
No
operation
Read literal
’k’<19:8>,
Write to PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
Read
register ‘f’
Process
Data
Write to
destination
GOTO THERE
Example:
INCF
CNT, 1, 0
Example:
After Instruction
Before Instruction
PC
=
Address (THERE)
CNT
=
0xFF
Z
=
=
=
0
?
?
C
DC
After Instruction
CNT
=
=
=
=
0x00
Z
1
1
1
C
DC
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INCFSZ
Increment f, skip if 0
INFSNZ
Increment f, skip if not 0
Syntax:
[ label ] INCFSZ f [,d [,a]
Syntax:
[ label ] INFSNZ f [,d [,a]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) + 1 dest,
skip if result = 0
Operation:
(f) + 1 dest,
skip if result 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0011
11da
ffff
ffff
0100
10da
ffff
ffff
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is ‘0’, the next
If the result is not ‘0’, the next
instruction which is already fetched
is discarded and a NOPis executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
instruction which is already fetched
is discarded and a NOPis executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1, 0
HERE
ZERO
NZERO
INFSNZ REG, 1, 0
Example:
Example:
Before Instruction
Before Instruction
PC
=
Address (HERE)
PC
=
Address (HERE)
After Instruction
After Instruction
CNT
If CNT
PC
If CNT
PC
=
=
=
=
CNT + 1
REG
If REG
PC
If REG
PC
=
=
=
=
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
0;
Address (ZERO)
0;
Address (NZERO)
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IORLW
Inclusive OR literal with W
IORWF
Inclusive OR W with f
Syntax:
[ label ] IORLW k
0 k 255
Syntax:
[ label ] IORWF f [,d [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 f 255
d [0,1]
a [0,1]
(W) .OR. k W
N, Z
Operation:
(W) .OR. (f) dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N, Z
Description:
The contents of W are OR’ed with
the eight-bit literal ‘k’. The result is
placed in W.
0001
00da
ffff
ffff
Description:
Inclusive OR W with register ‘f’. If
‘d’ is ‘0’, the result is placed in W. If
‘d’ is ‘1’, the result is placed back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
IORLW
0x35
Example:
Before Instruction
Q Cycle Activity:
Q1
W
=
0x9A
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
After Instruction
W
=
0xBF
IORWF RESULT, 0, 1
Example:
Before Instruction
RESULT =
0x13
0x91
W
=
After Instruction
RESULT =
0x13
0x93
W
=
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LFSR
Load FSR
MOVF
Move f
Syntax:
[ label ] LFSR f,k
Syntax:
[ label ] MOVF f [,d [,a]
Operands:
0 f 2
0 k 4095
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
k FSRf
Operation:
f dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N, Z
1110
1111
1110
0000
00ff
k kkk
11
kkkk
k kkk
0101
00da
ffff
ffff
7
Description:
The 12-bit literal ‘k’ is loaded into
the File Select Register pointed
to by ‘f’.
Description:
The contents of register ‘f’ are
moved to a destination dependent
upon the status of ‘d’. If ‘d’ is ‘0’, the
result is placed in W. If ‘d’ is ‘1’, the
result is placed back in register ‘f’
(default). Location ‘f’ can be
anywhere in the 256-byte bank. If
‘a’ is ‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’ MSB
Process
Data
Write literal
‘k’ MSB to
FSRfH
Decode
Read literal
‘k’ LSB
Process
Data
Write literal
‘k’ to FSRfL
Words:
Cycles:
1
1
LFSR 2, 0x3AB
Example:
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
FSR2H
FSR2L
=
=
0x03
0xAB
Decode
Read
register ‘f’
Process
Data
Write W
MOVF
REG, 0, 0
Example:
Before Instruction
REG
W
=
=
0x22
0xFF
After Instruction
REG
W
=
=
0x22
0x22
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MOVFF
Move f to f
MOVLB
Move literal to low nibble in BSR
Syntax:
[ label ] MOVFF fs,fd
Syntax:
[ label ] MOVLB k
0 k 255
k BSR
Operands:
0 fs 4095
0 fd 4095
Operands:
Operation:
Status Affected:
Encoding:
Operation:
(fs) fd
None
Status Affected:
None
0000
0001
kkkk
kkkk
Encoding:
1st word (source)
2nd word (destin.)
Description:
The 8-bit literal ‘k’ is loaded into
the Bank Select Register (BSR).
1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Words:
Cycles:
1
1
Description:
The contents of source register ‘fs’
are moved to destination register
‘fd’. Location of source ‘fs’ can be
anywhere in the 4096-byte data
space (000h to FFFh) and location
of destination ‘fd’ can also be
anywhere from 000h to FFFh.
Either source or destination can be
W (a useful special situation).
MOVFFis particularly useful for
transferring a data memory location
to a peripheral register (such as the
transmit buffer or an I/O port).
The MOVFFinstruction cannot use
the PCL, TOSU, TOSH or TOSL as
the destination register.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘k’
Process
Data
Write
literal ‘k’ to
BSR
MOVLB
5
Example:
Before Instruction
BSR register
=
=
0x02
0x05
After Instruction
BSR register
Words:
Cycles:
2
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
(src)
Process
Data
No
operation
Decode
No
operation,
No
operation
Write
register ‘f’
(dest)
No dummy
read
MOVFF
REG1, REG2
Example:
Before Instruction
REG1
REG2
=
=
0x33
0x11
After Instruction
REG1
REG2
=
=
0x33,
0x33
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MOVLW
Move literal to W
MOVWF
Move W to f
Syntax:
[ label ] MOVLW k
0 k 255
k W
Syntax:
[ label ] MOVWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 f 255
a [0,1]
Operation:
(W) f
None
Status Affected:
Encoding:
None
0000
1110
kkkk
kkkk
0110
111a
ffff
ffff
Description:
The eight-bit literal ‘k’ is loaded into
W.
Description:
Move data from W to register ‘f’.
Location ‘f’ can be anywhere in the
256-byte bank. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1,
then the bank will be selected as
per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1
MOVLW
0x5A
Example:
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
W
=
0x5A
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
MOVWF
REG, 0
Example:
Before Instruction
W
REG
=
=
0x4F
0xFF
After Instruction
W
REG
=
=
0x4F
0x4F
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MULLW
Multiply Literal with W
MULWF
Multiply W with f
Syntax:
[ label ] MULLW
0 k 255
k
Syntax:
[ label ] MULWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 f 255
a [0,1]
(W) x k PRODH:PRODL
Operation:
(W) x (f) PRODH:PRODL
None
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
Description:
An unsigned multiplication is
carried out between the contents
of W and the 8-bit literal ‘k’. The
16-bit result is placed in
PRODH:PRODL register pair.
PRODH contains the high byte.
W is unchanged.
None of the status flags are
affected.
Note that neither overflow nor
carry is possible in this
Description
An unsigned multiplication is
carried out between the contents
of W and the register file location
‘f’. The 16-bit result is stored in
the PRODH:PRODL register
pair. PRODH contains the high
byte.
Both W and ‘f’ are unchanged.
None of the status flags are
affected.
operation. A zero result is
possible but not detected.
Note that neither overflow nor
carry is possible in this
operation. A zero result is
possible but not detected. If ‘a’ is
‘0’, the Access Bank will be
selected, overriding the BSR
value. If ‘a’= 1, then the bank will
be selected as per the BSR
value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write
registers
PRODH:
PRODL
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
MULLW
0xC4
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register ‘f’
Process
Data
Write
W
PRODH
PRODL
=
=
=
0xE2
registers
PRODH:
PRODL
?
?
After Instruction
W
=
0xE2
0xAD
0x08
MULWF
REG, 1
Example:
PRODH
PRODL
=
=
Before Instruction
W
=
0xC4
0xB5
?
?
REG
=
=
=
PRODH
PRODL
After Instruction
W
=
=
=
=
0xC4
0xB5
0x8A
0x94
REG
PRODH
PRODL
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NEGF
Negate f
NOP
No Operation
Syntax:
[ label ] NEGF f [,a]
Syntax:
[ label ] NOP
None
Operands:
0 f 255
a [0,1]
Operands:
Operation:
Status Affected:
Encoding:
No operation
None
Operation:
( f ) + 1 f
Status Affected:
Encoding:
N, OV, C, DC, Z
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Words:
No operation.
Description:
Location ‘f’ is negated using two’s
complement. The result is placed in
the data memory location ‘f’. If ‘a’ is
‘0’, the Access Bank will be
1
1
Cycles:
Q Cycle Activity:
Q1
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value.
Q2
No
Q3
No
Q4
Decode
No
operation
operation
operation
Words:
Cycles:
1
1
Example:
None.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
NEGF
REG, 1
Example:
Before Instruction
REG
=
0011 1010 [0x3A]
1100 0110 [0xC6]
After Instruction
REG
=
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POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
[ label ] POP
None
Syntax:
[ label ] PUSH
None
Operands:
Operation:
Status Affected:
Encoding:
Operands:
Operation:
Status Affected:
Encoding:
(TOS) bit bucket
None
(PC+2) TOS
None
0000
0000
0000
0110
0000
0000
0000
0101
Description:
The TOS value is pulled off the
return stack and is discarded. The
TOS value then becomes the
previous value that was pushed
onto the return stack.
This instruction is provided to
enable the user to properly manage
the return stack to incorporate a
software stack.
Description:
The PC+2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows
implementing a software stack by
modifying TOS and then pushing it
onto the return stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
PUSH PC+2
onto return
stack
No
operation
No
operation
Q2
Q3
Q4
Decode
No
operation
POP TOS
value
No
operation
PUSH
Example:
POP
GOTO
Example:
Before Instruction
NEW
TOS
PC
=
=
00345Ah
000124h
Before Instruction
TOS
=
=
0031A2h
014332h
After Instruction
Stack (1 level down)
PC
=
=
=
000126h
000126h
00345Ah
TOS
After Instruction
Stack (1 level down)
TOS
PC
=
=
014332h
NEW
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RCALL
Relative Call
RESET
Reset
Syntax:
[ label ] RCALL
-1024 n 1023
(PC) + 2 TOS,
n
Syntax:
[ label ] RESET
Operands:
Operation:
Operands:
Operation:
None
Reset all registers and flags that
are affected by a MCLR Reset.
(PC) + 2 + 2n PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
1101
1nnn
nnnn
nnnn
0000
0000
1111
1111
Description:
Subroutine call with a jump up to
1K from the current location. First,
return address (PC+2) is pushed
onto the stack. Then, add the 2’s
complement number ‘2n’ to the PC.
Since the PC will have incremented
to fetch the next instruction, the
new address will be PC+2+2n. This
instruction is a two-cycle
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
No
No
Reset
operation
operation
instruction.
Words:
Cycles:
1
2
RESET
Example:
After Instruction
Registers =
Reset Value
Reset Value
Q Cycle Activity:
Q1
Flags*
=
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to PC
Push PC to
stack
No
No
No
No
operation
operation
operation
operation
HERE
RCALL
Jump
Example:
Before Instruction
PC
=
Address (HERE)
After Instruction
PC
=
Address (Jump)
Address (HERE+2)
TOS =
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RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
[ label ] RETFIE [s]
s [0,1]
Syntax:
[ label ] RETLW k
0 k 255
Operands:
Operation:
Operands:
Operation:
(TOS) PC,
k W,
1 GIE/GIEH or PEIE/GIEL,
if s = 1
(TOS) PC,
PCLATU, PCLATH are unchanged
(WS) W,
(STATUSS) STATUS,
(BSRS) BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged
Description:
W is loaded with the eight-bit literal
‘k’. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
Status Affected:
Encoding:
GIE/GIEH, PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from Interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit. If ‘s’ = 1, the contents of
the shadow registers, WS,
STATUSS and BSRS, are loaded
into their corresponding registers,
W, Status and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Pop PC
from stack,
Write to W
No
operation
No
No
No
operation
operation
operation
Words:
Cycles:
1
2
Example:
CALL TABLE ; W contains table
; offset value
Q Cycle Activity:
Q1
; W now has
; table value
Q2
Q3
Q4
:
Decode
No
operation
No
operation
Pop PC
from stack
TABLE
ADDWF PCL ; W = offset
Set GIEH or
GIEL
RETLW k0
RETLW k1
:
; Begin table
;
No
operation
No
operation
No
operation
No
operation
:
RETLW kn
; End of table
RETFIE
1
Example:
Before Instruction
After Interrupt
W
=
0x07
PC
=
=
=
=
=
TOS
WS
After Instruction
W
BSR
STATUS
GIE/GIEH, PEIE/GIEL
BSRS
W
=
value of kn
STATUSS
1
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RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
[ label ] RETURN [s]
s [0,1]
Syntax:
[ label ] RLCF f [,d [,a]
Operands:
Operation:
Operands:
0 f 255
d [0,1]
a [0,1]
(TOS) PC,
if s = 1
(WS) W,
Operation:
(f<n>) dest<n+1>,
(f<7>) C,
(C) dest<0>
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
Status Affected:
Encoding:
C, N, Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counter. If ‘s’ = 1, the contents of
the shadow registers, WS,
STATUSS and BSRS, are loaded
into their corresponding registers,
W, Status and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
register f
C
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
No
Process
Data
Pop PC
from stack
operation
Decode
Read
Process
Write to
No
No
No
No
register ‘f’
Data
destination
operation
operation
operation
operation
RLCF
REG, 0, 0
Example:
Before Instruction
RETURN
Example:
REG
C
=
=
1110 0110
0
After Interrupt
PC = TOS
After Instruction
REG
=
=
=
1110 0110
1100 1100
1
W
C
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RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
Syntax:
[ label ] RLNCF f [,d [,a]
Syntax:
[ label ] RRCF f [,d [,a]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f<n>) dest<n+1>,
(f<7>) dest<0>
Operation:
(f<n>) dest<n-1>,
(f<0>) C,
(C) dest<7>
Status Affected:
Encoding:
N, Z
Status Affected:
Encoding:
C, N, Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ‘f’ are
rotated one bit to the left. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register
‘f’ (default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
Description:
The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
register f
Words:
Cycles:
1
1
register f
C
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ‘f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
Process
Write to
register ‘f’
Data
destination
RLNCF
REG, 1, 0
Example:
Before Instruction
RRCF
REG, 0, 0
Example:
REG
=
1010 1011
0101 0111
After Instruction
Before Instruction
REG
=
REG
C
=
=
1110 0110
0
After Instruction
REG
=
=
=
1110 0110
0111 0011
0
W
C
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RRNCF
Rotate Right f (no carry)
SETF
Set f
Syntax:
[ label ] RRNCF f [,d [,a]
Syntax:
[ label ] SETF f [,a]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
FFh f
Operation:
(f<n>) dest<n-1>,
(f<0>) dest<7>
Status Affected:
Encoding:
None
0110
100a
ffff
ffff
Status Affected:
Encoding:
N, Z
Description:
The contents of the specified
0100
00da
ffff
ffff
register are set to FFh. If ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
Description:
The contents of register ‘f’ are
rotated one bit to the right. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is
‘1’, the result is placed back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Words:
Cycles:
1
1
SETF
REG,1
Example:
Before Instruction
Q Cycle Activity:
Q1
REG
=
=
0x5A
0xFF
Q2
Q3
Q4
After Instruction
REG
Decode
Read
register ‘f’
Process
Data
Write to
destination
RRNCF
REG, 1, 0
Example 1:
Before Instruction
REG
=
1101 0111
1110 1011
RRNCF REG, 0, 0
After Instruction
REG
=
Example 2:
Before Instruction
W
REG
=
=
?
1101 0111
After Instruction
W
REG
=
=
1110 1011
1101 0111
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SLEEP
Enter SLEEP mode
SUBFWB
Subtract f from W with borrow
Syntax:
[ label ] SLEEP
Syntax:
[ label ] SUBFWB f [,d [,a]
Operands:
Operation:
None
Operands:
0 f 255
d [0,1]
a [0,1]
00h WDT,
0 WDT postscaler,
1 TO,
Operation:
(W) – (f) – (C) dest
0 PD
Status Affected:
Encoding:
N, OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register ‘f’ and Carry flag
(borrow) from W (2’s complement
method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored in register ‘f’ (default). If ‘a’ is
‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ is ‘1’, then the bank will be
selected as per the BSR value
(default).
Description:
The Power-down status bit (PD) is
cleared. The Time-out status bit
(TO) is set. Watchdog Timer and
its postscaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
No
operation
Process
Data
Go to
Sleep
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
SLEEP
Example:
Before Instruction
SUBFWB
REG, 1, 0
Example 1:
TO
=
?
PD
=
?
Before Instruction
After Instruction
REG
=
3
2
1
W
=
=
TO
=
1 †
C
PD
=
0
After Instruction
REG
W
C
=
=
=
=
=
FF
2
† If WDT causes wake-up, this bit is cleared.
0
Z
0
1
N
; result is negative
SUBFWB
REG, 0, 0
Example 2:
Before Instruction
REG
W
C
=
=
=
2
5
1
After Instruction
REG
W
C
=
=
=
=
=
2
3
1
0
0
Z
N
; result is positive
SUBFWB
REG, 1, 0
Example 3:
Before Instruction
REG
W
C
=
=
=
1
2
0
After Instruction
REG
W
C
=
=
=
=
=
0
2
1
1
0
Z
; result is zero
N
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SUBLW
Subtract W from literal
SUBWF
Syntax:
Subtract W from f
Syntax:
[ label ] SUBLW k
0 k 255
[ label ] SUBWF f [,d [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 f 255
d [0,1]
a [0,1]
k – (W) W
N, OV, C, DC, Z
Operation:
(f) – (W) dest
0000
1000
kkkk
kkkk
Status Affected:
Encoding:
N, OV, C, DC, Z
Description:
W is subtracted from the eight-bit
literal ‘k’. The result is placed in
W.
0101
11da
ffff
ffff
Description:
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’,
the result is stored in W. If ‘d’ is
‘1’, the result is stored back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
SUBLW 0x02
Example 1:
Words:
Cycles:
1
1
Before Instruction
W
=
1
?
C
=
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
W
C
Z
=
=
=
=
1
Decode
Read
register ‘f’
Process
Data
Write to
destination
1
0
0
; result is positive
N
SUBWF
REG, 1, 0
Example 1:
SUBLW 0x02
Example 2:
Before Instruction
Before Instruction
REG
=
=
=
3
2
?
W
C
=
=
2
?
W
C
After Instruction
After Instruction
REG
W
C
=
=
=
=
=
1
2
1
0
0
W
C
Z
=
=
=
=
0
1
1
0
; result is zero
; result is positive
Z
N
N
SUBLW 0x02
Example 3:
SUBWF
REG, 0, 0
Example 2:
Before Instruction
Before Instruction
W
C
=
=
3
?
REG
W
C
=
=
=
2
2
?
After Instruction
W
C
Z
=
=
=
=
FF ; (2’s complement)
After Instruction
0
0
1
; result is negative
REG
W
C
Z
N
=
=
=
=
=
2
0
1
1
0
N
; result is zero
SUBWF
REG, 1, 0
Example 3:
Before Instruction
REG
=
=
=
1
2
?
W
C
After Instruction
REG
W
C
=
=
=
=
=
FFh ;(2’s complement)
2
0
0
1
; result is negative
Z
N
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SUBWFB
Syntax:
Subtract W from f with Borrow
SWAPF
Swap f
Syntax:
[ label ] SWAPF f [,d [,a]
[ label ] SUBWFB f [,d [,a]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f<3:0>) dest<7:4>,
(f<7:4>) dest<3:0>
Operation:
(f) – (W) – (C) dest
Status Affected: N, OV, C, DC, Z
Status Affected:
Encoding:
None
0101
10da
ffff
ffff
Encoding:
0011
10da
ffff
ffff
Description:
Subtract W and the Carry flag
(borrow) from register ‘f’ (2’s com-
plement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding the
BSR value. If ‘a’ is ‘1’, then the bank
will be selected as per the BSR
value (default).
Description:
The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is
‘1’, the result is placed in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Decode
Read
register ‘f’
Process
Data
Write to
destination
SUBWFB REG, 1, 0
Example 1:
SWAPF
REG, 1, 0
Example:
Before Instruction
Before Instruction
REG
=
=
=
0x19
0x0D
1
(0001 1001)
(0000 1101)
REG
=
0x53
0x35
W
C
After Instruction
After Instruction
REG
=
REG
=
=
=
=
=
0x0C
(0000 1011)
(0000 1101)
W
0x0D
C
1
0
0
Z
N
; result is positive
SUBWFB REG, 0, 0
Example 2:
Before Instruction
REG
W
C
=
=
=
0x1B
0x1A
0
(0001 1011)
(0001 1010)
After Instruction
REG
W
C
=
=
=
=
=
0x1B
(0001 1011)
0x00
1
1
0
Z
; result is zero
N
SUBWFB REG, 1, 0
Example 3:
Before Instruction
REG
W
C
=
=
=
0x03
0x0E
1
(0000 0011)
(0000 1101)
After Instruction
REG
=
0xF5
(1111 0100)
; [2’s comp]
W
=
=
=
=
0x0E
(0000 1101)
C
Z
N
0
0
1
; result is negative
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TBLRD
Table Read
TBLRD
Table Read (Continued)
TBLRD *+ ;
Syntax:
[ label ] TBLRD ( *; *+; *-; +*)
Example 1:
Operands:
Operation:
None
Before Instruction
TABLAT
TBLPTR
MEMORY(0x00A356)
=
=
=
0x55
0x00A356
0x34
if TBLRD *,
(Prog Mem (TBLPTR)) TABLAT;
TBLPTR – No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) + 1 TBLPTR;
if TBLRD *-,
After Instruction
TABLAT
TBLPTR
=
=
0x34
0x00A357
TBLRD +* ;
Example 2:
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) – 1 TBLPTR;
if TBLRD +*,
(TBLPTR) + 1 TBLPTR;
(Prog Mem (TBLPTR)) TABLAT;
Before Instruction
TABLAT
TBLPTR
=
=
=
=
0xAA
0x01A357
0x12
MEMORY(0x01A357)
MEMORY(0x01A358)
0x34
After Instruction
Status Affected:None
TABLAT
TBLPTR
=
=
0x34
0x01A358
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Encoding:
Description:
This instruction is used to read the
contents of Program Memory (P.M.). To
address the Program Memory, a pointer
called Table Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2-Mbyte address
range.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLRDinstruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
No
No
operation
operation
operation
No
No operation
No
No operation
operation (Read Program operation (Write TABLAT)
Memory)
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TBLWT
Table Write
TBLWT Table Write (Continued)
Syntax:
[ label ] TBLWT ( *; *+; *-; +*)
Words: 1
Operands:
Operation:
None
Cycles: 2
if TBLWT*,
Q Cycle Activity:
(TABLAT) Holding Register;
TBLPTR – No Change;
if TBLWT*+,
Q1
Q2
Q3
Q4
Decode
No
No
No
operation
operation
operation
(TABLAT) Holding Register;
(TBLPTR) + 1 TBLPTR;
if TBLWT*-,
(TABLAT) Holding Register;
(TBLPTR) – 1 TBLPTR;
if TBLWT+*,
No
operation
No
operation
(Read
No
operation
No
operation
(Write to
Holding
Register )
TABLAT)
(TBLPTR) + 1 TBLPTR;
(TABLAT) Holding Register;
Example 1:
TBLWT *+;
Status Affected: None
Before Instruction
0000
0000
0000
11nn
Encoding:
TABLAT
TBLPTR
=
=
0x55
nn=0 *
=1 *+
=2 *-
=3 +*
0x00A356
HOLDING REGISTER
(0x00A356)
=
0xFF
After Instructions (table write completion)
TABLAT
=
0x55
Description:
This instruction uses the 3 LSBs of
TBLPTR to determine which of the
8 holding registers the TABLAT is
written to. The holding registers are
used to program the contents of
Program Memory (P.M.). (Refer
to Section 5.0 “Flash Program
Memory” for additional details on
programming Flash memory.)
The TBLPTR (a 21-bit pointer) points
to each byte in the Program Memory.
TBLPTR has a 2-Mbyte address
range. The LSb of the TBLPTR
selects which byte of the program
memory location to access.
TBLPTR
=
0x00A357
HOLDING REGISTER
(0x00A356)
=
0x55
Example 2:
TBLWT +*;
Before Instruction
TABLAT
TBLPTR
HOLDING REGISTER
(0x01389A)
HOLDING REGISTER
(0x01389B)
=
=
0x34
0x01389A
=
=
0xFF
0xFF
After Instruction (table write completion)
TABLAT
TBLPTR
HOLDING REGISTER
(0x01389A)
HOLDING REGISTER
(0x01389B)
=
=
0x34
0x01389B
=
=
0xFF
0x34
TBLPTR[0] = 0: LeastSignificant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLWT instruction can modify
the value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
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TSTFSZ
Test f, skip if 0
XORLW
Exclusive OR literal with W
Syntax:
[ label ] TSTFSZ f [,a]
Syntax:
[ label ] XORLW k
0 k 255
Operands:
0 f 255
a [0,1]
Operands:
Operation:
Status Affected:
Encoding:
(W) .XOR. k W
N, Z
Operation:
skip if f = 0
None
Status Affected:
Encoding:
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
Description:
The contents of W are XOR’ed
with the 8-bit literal ‘k’. The result
is placed in W.
Description:
If ‘f’ = 0, the next instruction,
fetched during the current
instruction execution is discarded
and a NOPis executed, making this
a two-cycle instruction. If ‘a’ is ‘0’,
the Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
Write to W
Words:
Cycles:
1
1(2)
Example:
XORLW 0xAF
= 0xB5
Note: 3 cycles if skip and followed
by a 2-word instruction.
Before Instruction
W
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
W
=
0x1A
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NZERO
ZERO
TSTFSZ CNT, 1
:
:
Example:
Before Instruction
PC
=
Address (HERE)
After Instruction
If CNT
=
=
=
0x00,
PC
Address (ZERO)
0x00,
If CNT
PC
Address (NZERO)
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XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF f [,d [,a]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(W) .XOR. (f) dest
Status Affected:
Encoding:
N, Z
0001
10da
ffff
ffff
Description:
Exclusive OR the contents of W
with register ‘f’. If ‘d’ is ‘0’, the result
is stored in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
XORWF
REG, 1, 0
Example:
Before Instruction
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
=
=
0x1A
0xB5
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25.1 MPLAB Integrated Development
Environment Software
25.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• A single graphical interface to all debugging tools
- Simulator
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- Programmer (sold separately)
- HI-TECH C® for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Customizable data windows with direct edit of
contents
• Simulators
• High-level source code debugging
• Mouse over variable inspection
- MPLAB SIM Software Simulator
• Emulators
• Drag and drop variables from source to watch
windows
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
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25.2 MPLAB C Compilers for Various
Device Families
25.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
25.3 HI-TECH C for Various Device
Families
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
25.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
25.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• MPLAB IDE compatibility
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
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25.7 MPLAB SIM Software Simulator
25.9 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
25.10 PICkit 3 In-Circuit Debugger/
Programmer and
25.8 MPLAB REAL ICE In-Circuit
Emulator System
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
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25.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
25.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
Development Environment (IDE) the PICkit™
2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
25.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS39609C-page 304
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
26.0 ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk byall ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin, rather
than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2003-2013 Microchip Technology Inc.
DS39609C-page 305
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 26-1:
PIC18F6520/8520VOLTAGE-FREQUENCYGRAPH(INDUSTRIAL,EXTENDED)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18FX520
4.2V
3.5V
3.0V
2.5V
2.0V
FMAX (Extended)
FMAX
Frequency
FMAX = 40 MHz for PIC18F6520/8520 in Microcontroller mode.
FMAX (Extended) = 25 MHz for PIC18F6520/8520 in modes other than Microcontroller mode.
FIGURE 26-2:
PIC18LF6520/8520 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
PIC18LFX520
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
FMAX
4 MHz
Frequency
For PIC18F6520/8520 in Microcontroller mode:
FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN 4.2V;
FMAX = 40 MHz, if VDDAPPMIN > 4.2V.
For PIC18F8X8X in modes other than Microcontroller mode:
FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN 4.2V;
FMAX = 25 MHz, if VDDAPPMIN > 4.2V.
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
DS39609C-page 306
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 26-3:
PIC18F6620/6720/8620/8720 VOLTAGE-FREQUENCY GRAPH
(INDUSTRIAL, EXTENDED)
6.0V
5.5V
5.0V
PIC18FX620/X720
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
FMAX (Extended)
FMAX
Frequency
FMAX = 25 MHz in Microcontroller mode.
FMAX (Extended) = 16 MHz for PIC18F6520/8520 in modes other than Microcontroller mode.
FIGURE 26-4:
PIC18LF6620/6720/8620/8720 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18LFX620/X720
4.2V
3.5V
3.0V
2.5V
2.0V
FMAX
4 MHz
Frequency
In Microcontroller mode:
FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN 4.2V;
FMAX = 25 MHz, if VDDAPPMIN > 4.2V.
In modes other than Microcontroller mode:
FMAX = (5.45 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN 4.2V;
FMAX = 16 MHz, if VDDAPPMIN > 4.2V.
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
2003-2013 Microchip Technology Inc.
DS39609C-page 307
PIC18F6520/8520/6620/8620/6720/8720
26.1 DC Characteristics: Supply Voltage
PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended)
PIC18LF6520/8520/6620/8620/6720/8720 (Industrial)
PIC18LF6520/8520/6620/8620/6720/8720
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18F6520/8520/6620/8620/6720/8720
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
(Industrial, Extended)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
D001 VDD
Supply Voltage
PIC18LFXX20
2.0
4.2
—
—
—
—
5.5
5.5
V
V
V
V
HS, XT, RC and LP Oscillator mode
PIC18FXX20
Analog Supply Voltage
RAM Data Retention
D001A AVDD
D002 VDR
VDD – 0.3
1.5
VDD + 0.3
—
(1)
Voltage
D003 VPOR
D004 SVDD
D005 VBOR
VDD Start Voltage
to ensure internal
Power-on Reset signal
—
—
—
0.7
—
V
See section on Power-on Reset for details
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
V/ms See section on Power-on Reset for details
Brown-out Reset Voltage
BORV1:BORV0 = 11
BORV1:BORV0 = 10
BORV1:BORV0 = 01
BORV1:BORV0 = 00
N/A
2.64
4.11
4.41
—
—
—
—
N/A
2.92
4.55
4.87
V
V
V
V
Reserved
Legend:
Shading of rows is to assist in readability of the table.
Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.
DS39609C-page 308
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended)
PIC18LF6520/8520/6620/8620/6720/8720 (Industrial)
PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C TA +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F6520/8520/6620/8620/6720/8720
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(1)
Power-down Current (IPD)
PIC18LFXX20 0.2
1
1
A
A
A
A
A
A
A
A
A
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V,
(Sleep mode)
0.2
1.2
5
PIC18LFXX20 0.4
1
VDD = 3.0V,
(Sleep mode)
0.4
1
1.8
8
All devices 0.7
2
VDD = 5.0V,
(Sleep mode)
0.7
3.0
2
15
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in k.
2003-2013 Microchip Technology Inc.
DS39609C-page 309
PIC18F6520/8520/6620/8620/6720/8720
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended)
PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) (Continued)
PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C TA +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F6520/8520/6620/8620/6720/8720
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD)
PIC18LFXX20 165
350
350
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
mA
mA
mA
-40°C
165
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
170
350
PIC18LFXX20 360
750
FOSC = 1 MHZ,
EC oscillator
340
750
300
750
All devices 800
1700
1700
1700
1200
1200
1300
730
700
PIC18LFXX20 600
600
640
PIC18LFXX20 1000 2500
1000 2500
FOSC = 4 MHz,
EC oscillator
1000 2500
All devices 2.2
5.0
5.0
5.0
2.1
2.0
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in k.
DS39609C-page 310
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended)
PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) (Continued)
PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C TA +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F6520/8520/6620/8620/6720/8720
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
(2,3)
Supply Current (IDD)
PIC18FX620, PIC18FX720 9.3
15
15
15
20
20
20
20
20
20
25
25
25
55
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
A
-40°C
9.5
+25°C
+85°C
VDD = 4.2V
VDD = 5.0V
VDD = 4.2V
10
FOSC = 25 MHZ,
EC oscillator
PIC18FX620, PIC18FX720 11.8
-40°C
12
12
+25°C
+85°C
PIC18FX520
PIC18FX520
16
16
16
19
19
19
15
-40°C
+25°C
+85°C
FOSC = 40 MHZ,
EC oscillator
-40°C
+25°C
VDD = 5.0V
VDD = 2.0V
+85°C
D014
PIC18FX620/X720
PIC18LF8520
-40°C to +85°C
FOSC = 32 kHz,
Timer1 as clock
13
20
50
—
—
18
35
A
A
A
A
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 4.2V
VDD = 4.2V
FOSC = 32 kHz,
Timer1 as clock
85
PIC18FXX20
200
250
FOSC = 32 kHz,
Timer1 as clock
A -40°C to +125°C
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in k.
2003-2013 Microchip Technology Inc.
DS39609C-page 311
PIC18F6520/8520/6620/8620/6720/8720
26.2 DC Characteristics: Power-Down and Supply Current
PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended)
PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) (Continued)
PIC18LF6520/8520/6620/8620/6720/8720 Standard Operating Conditions (unless otherwise stated)
(Industrial)
Operating temperature
-40°C TA +85°C for industrial
Standard Operating Conditions (unless otherwise stated)
PIC18F6520/8520/6620/8620/6720/8720
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
(Industrial, Extended)
Param
Device
No.
Typ
Max Units
Conditions
Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD)
D022
(IWDT)
Watchdog Timer
<1
<1
<1
3
2.0
1.5
3
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
-40C
+25C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
+85C
10
6
-40C
2.5
3
+25C
15
25
20
40
50
65
45
50
65
30
40
50
40
50
65
2.2
3.8
7.0
2
+85C
15
12
12
35
45
33
35
45
-40C
+25C
+85C
D022A
(IBOR)
Brown-out Reset
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
-40C to +85C
+25C
VDD = 3.0V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
D022B
(ILVD)
Low-Voltage Detect
D025
(IOSCB)
Timer1 Oscillator 5.2
VDD = 2.0V
VDD = 2.0V
VDD = 4.2V
PIC18LF8720/8620 5.2
-40C to +85C
32 kHz on Timer1
6.5
A -40C to +125C
PIC18F8520/8620/8720 6.5
A
A
+25C
6.5
-40C to +85C
VDD = 4.2V
32 kHz on Timer1
32 kHz on Timer1
6.5
A -40C to +125C
PIC18LF8520 1.8
A
A
+25C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
2.9
3.4
-40C to +85C
A -40C to +125C
+25C
+25C
+25C
D026
(IAD)
A/D Converter
<1
<1
<1
A
A
A
A/D on, not converting.
Device is in Sleep.
2
2
Legend:
Shading of rows is to assist in readability of the table.
Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in k.
DS39609C-page 312
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
26.3 DC Characteristics: PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended)
PIC18LF6520/8520/6620/8620/6720/8720 (Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
Sym
No.
Characteristic
Min
Max
Units
Conditions
VIL
Input Low Voltage
I/O ports:
with TTL buffer
D030
D030A
D031
VSS
—
0.15 VDD
0.8
V
V
VDD < 4.5V
4.5V VDD 5.5V
with Schmitt Trigger buffer
RC3 and RC4
VSS
VSS
0.2 VDD
0.3 VDD
V
V
D032
MCLR
VSS
VSS
0.2 VDD
0.2 VDD
V
V
D032A
OSC1 (in XT, HS and LP modes)
and T1OSI
D033
OSC1 (in RC and EC mode)(1)
Input High Voltage
I/O ports:
VSS
0.2 VDD
V
VIH
D040
D040A
D041
with TTL buffer
0.25 VDD + 0.8V
2.0
VDD
VDD
V
V
VDD < 4.5V
4.5V VDD 5.5V
with Schmitt Trigger buffer
RC3 and RC4
0.8 VDD
0.7 VDD
VDD
VDD
V
V
D042
MCLR, OSC1 (EC mode)
OSC1 and T1OSI
0.8 VDD
1.6
VDD
VDD
V
V
D042A
LP, XT, HS, HSPLL
modes(1)
D043
D060
OSC1 (RC mode)(1)
Input Leakage Current(2,3)
I/O ports
0.9 VDD
—
VDD
V
IIL
1
A VSS VPIN VDD,
Pin at high-impedance
D061
D063
MCLR
—
—
5
5
A VSS VPIN VDD
A VSS VPIN VDD
OSC1
IPU
Weak Pull-up Current
D070 IPURB PORTB weak pull-up current
50
400
A VDD = 5V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
2003-2013 Microchip Technology Inc.
DS39609C-page 313
PIC18F6520/8520/6620/8620/6720/8720
26.3 DC Characteristics: PIC18F6520/8520/6620/8620/6720/8720 (Industrial, Extended)
PIC18LF6520/8520/6620/8620/6720/8720 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
Sym
No.
Characteristic
Min
Max
Units
Conditions
VOL
Output Low Voltage
D080
I/O ports
—
—
—
—
0.6
0.6
0.6
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40C to +85C
D080A
D083
IOL = 7.0 mA, VDD = 4.5V,
-40C to +125C
OSC2/CLKO
(RC mode)
IOL = 1.6 mA, VDD = 4.5V,
-40C to +85C
D083A
IOL = 1.2 mA, VDD = 4.5V,
-40C to +125C
VOH
Output High Voltage(3)
D090
I/O ports
VDD – 0.7
VDD – 0.7
VDD – 0.7
VDD – 0.7
—
—
—
V
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40C to +85C
D090A
D092
IOH = -2.5 mA, VDD = 4.5V,
-40C to +125C
OSC2/CLKO
(RC mode)
—
IOH = -1.3 mA, VDD = 4.5V,
-40C to +85C
D092A
—
IOH = -1.0 mA, VDD = 4.5V,
-40C to +125C
D150 VOD
Open-Drain High Voltage
8.5
RA4 pin
Capacitive Loading Specs
on Output Pins
D100(4)
COSC2 OSC2 pin
—
15
pF In XT, HS and LP modes
when external clock is used
to drive OSC1
D101 CIO
D102 CB
All I/O pins and OSC2
(in RC mode)
—
—
50
pF To meet the AC Timing
Specifications
pF In I2C mode
SCL, SDA
400
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC device be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.
DS39609C-page 314
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TABLE 26-1: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).
Param
No.
Sym
Characteristics
Input Offset Voltage
Min
Typ
Max
Units
Comments
D300
D301
D302
VIOFF
—
0
± 5.0
—
± 10
VDD – 1.5
—
mV
V
VICM
Input Common Mode Voltage
Common Mode Rejection Ratio
Response Time(1)
CMRR
TRESP
55
—
—
dB
300
300A
150
400
600
ns
ns
PIC18FXX20
PIC18LFXX20
301
TMC2OV Comparator Mode Change to
Output Valid
—
—
10
s
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from
VSS to VDD.
TABLE 26-2: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).
Param
No.
Sym
Characteristics
Resolution
Min
Typ
Max
Units
Comments
D310
VRES
VDD/24
—
VDD/32
LSb
D311
VRAA
Absolute Accuracy
—
—
—
—
1/4
1/2
LSb Low Range (VRR = 1)
LSb High Range (VRR = 0)
D312
310
VRUR
TSET
Unit Resistor Value (R)
Settling Time(1)
—
—
2k
—
—
10
s
Note 1: Settling time measured while VRR = 1and VR<3:0> transitions from ‘0000’ to ‘1111’.
2003-2013 Microchip Technology Inc.
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FIGURE 26-5:
LOW-VOLTAGE DETECT CHARACTERISTICS
VDD
(LVDIF can be
cleared in software)
VLVD
(LVDIF set by hardware)
LVDIF
TABLE 26-3: LOW-VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Symbol
Characteristic
Min
Typ† Max
Units
Conditions
D420
LVD Voltage on VDD
Transition high-to-low
LVV = 0001 1.96
LVV = 0010 2.16
LVV = 0011 2.35
LVV = 0100 2.45
LVV = 0101 2.64
LVV = 0110 2.75
LVV = 0111 2.95
LVV = 1000 3.24
LVV = 1001 3.43
LVV = 1010 3.53
LVV = 1011 3.72
LVV = 1100 3.92
LVV = 1101 4.11
LVV = 1110 4.41
2.06
2.27
2.47
2.58
2.78
2.89
3.1
2.16
2.38
2.59
2.71
2.92
3.03
3.26
3.58
3.79
3.91
4.12
4.34
4.55
4.87
—
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
3.41
3.61
3.72
3.92
4.13
4.33
4.64
1.22
D423
VBG
Band Gap Reference Voltage Value
—
†
Production tested at TAMB = 25°C. Specifications over temperature limits ensured by characterization.
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TABLE 26-4: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
DC Characteristics
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
Sym
No.
Characteristic
Min
Typ†
Max Units
Conditions
Internal Program Memory
Programming Specifications
(Note 1)
D110
D112
D113
VPP
IPP
Voltage on MCLR/VPP pin
Current into MCLR/VPP pin
9.00
—
—
—
—
13.25
5
V
(Note 2)
A
mA
IDDP
Supply Current during
Programming
—
10
Data EEPROM Memory
Cell Endurance
D120
ED
100K
10K
1M
100K
—
—
—
E/W -40C to +85C
E/W +85C to +125C
D120A ED
Cell Endurance
D121 VDRW VDD for Read/Write
VMIN
5.5
V
Using EECON to read/write
VMIN = Minimum operating
voltage
D122 TDEW Erase/Write Cycle Time
D123 TRETD Characteristic Retention
D123A TRETD Characteristic Retention
Program Flash Memory
—
40
4
—
—
—
ms
—
—
Year -40C to +85C (Note 3)
Year 25C (Note 3)
100
D130
EP
Cell Endurance
Cell Endurance
VDD for Read
10K
1000
VMIN
100K
10K
—
—
—
E/W -40C to +85C
E/W +85C to +125C
D130A EP
D131
D132
VPR
VIE
5.5
V
VMIN = Minimum operating
voltage
VDD for Block Erase
4.5
4.5
—
—
5.5
5.5
V
V
Using ICSP port
Using ICSP port
D132A VIW
VDD for Externally Timed Erase
or Write
D132B VPEW VDD for Self-Timed Write
VMIN
—
5.5
V
VMIN = Minimum operating
voltage
D133
TIE
ICSP Block Erase Cycle Time
—
1
5
—
—
ms VDD > 4.5V
ms VDD > 4.5V
D133A TIW
ICSP Erase or Write Cycle Time
(externally timed)
—
D133A TIW
Self-Timed Write Cycle Time
—
40
2.5
—
—
—
—
ms
D134 TRETD Characteristic Retention
D134A TRETD Characteristic Retention
Year -40C to +85C (Note 3)
Year 25C (Note 3)
100
—
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: These specifications are for programming the on-chip program memory through the use of table write
instructions.
2: The pin may be kept in this range at times other than programming, but it is not recommended.
3: Retention time is valid, provided no other specifications are violated.
2003-2013 Microchip Technology Inc.
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26.4 AC (Timing) Characteristics
26.4.1
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
ck
cs
di
CCP1
CLKO
CS
osc
rd
OSC1
RD
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
Fall
P
R
V
Z
Period
H
High
Rise
I
L
Invalid (High-Impedance)
Low
Valid
High-Impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
Hold
SU
Setup
ST
DAT
STA
DATA input hold
Start condition
STO
Stop condition
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26.4.2
TIMING CONDITIONS
The temperature and voltages specified in Table 26-5
apply to all timing specifications unless otherwise
noted. Figure 26-6 specifies the load conditions for the
timing specifications.
TABLE 26-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
AC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 26.1 and
Section 26.3.
LC parts operate for industrial temperatures only.
FIGURE 26-6:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1 Load condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2/CLKO
and including D and E outputs as ports
VSS
2003-2013 Microchip Technology Inc.
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26.4.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 26-7:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
1
Q2
Q3
Q4
4
Q1
OSC1
CLKO
3
4
3
2
TABLE 26-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
(1)
1A
FOSC
External CLKI Frequency
DC
25
MHz
MHz
MHz
EC, ECIO, PIC18FX620/X720
(-40°C to +85°C)
DC
DC
40
25
EC, ECIO, PIC18FX520
(-40°C to +85°C)
EC, ECIO, PIC18FX520 using external
memory interface (-40°C to +85°C)
(1)
Oscillator Frequency
DC
0.1
4
4
4
MHz
MHz
MHz
MHz
MHz
RC oscillator
XT oscillator
25
10
6.25
HS oscillator
4
HS + PLL oscillator, PIC18FX520
6
HS + PLL oscillator, PIC18FX520 using
external memory interface
4
5
6.25
200
—
MHz
kHz
ns
HS + PLL oscillator, PIC18FX620/X720
LP Oscillator mode
(1)
1
TOSC
External CLKI Period
25
EC, ECIO, PIC18FX620/X720
(-40°C to +85°C)
EC, ECIO, PIC18FX520
(-40°C to +85°C)
160
—
ns
(1)
Oscillator Period
250
250
25
—
10,000
250
ns
ns
ns
ns
ns
s
RC oscillator
XT oscillator
HS oscillator
100
100
25
250
HS + PLL oscillator, PIC18FX520
HS + PLL oscillator, PIC18FX620/X720
LP oscillator
160
—
(1)
2
3
TCY
Instruction Cycle Time
100
30
2.5
10
—
—
—
ns
ns
s
ns
ns
ns
ns
TCY = 4/FOSC
XT oscillator
LP oscillator
HS oscillator
XT oscillator
LP oscillator
HS oscillator
TOSL,
TOSH
External Clock in (OSC1)
High or Low Time
—
—
4
TOSR,
TOSF
External Clock in (OSC1) Rise
or Fall Time
20
50
7.5
—
—
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All
specified values are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied
to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
DS39609C-page 320
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TABLE 26-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V)
Param
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
No.
—
—
—
—
FOSC
Oscillator Frequency Range
On-Chip VCO System Frequency
PLL Start-up Time (Lock Time)
CLKO Stability (Jitter)
4
—
—
—
—
10
40
2
MHz HS mode
FSYS
trc
16
—
-2
MHz HS mode
ms
%
CLK
+2
†
Data in “Typ” column is at 5V, 25C, unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 26-8:
CLKO AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKO
13
14
12
18
19
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
Refer to Figure 26-6 for load conditions.
Note:
2003-2013 Microchip Technology Inc.
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TABLE 26-8: CLKO AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units Conditions
10
TOSH2CKL OSC1 to CLKO
TOSH2CKH OSC1 to CLKO
—
75
75
35
35
—
—
—
50
—
—
—
10
—
10
—
—
—
—
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
11
—
200
12
TCKR
CLKO Rise Time
—
100
13
TCKF
CLKO Fall Time
—
100
14
TCKL2IOV
CLKO to Port Out Valid
—
0.5 TCY + 20
15
TIOV2CKH Port In Valid before CLKO
0.25 TCY + 25
—
—
16
TCKH2IOI
TOSH2IOV
TOSH2IOI
Port In Hold after CLKO
0
—
17
OSC1 (Q1 cycle) to Port Out Valid
150
—
18
OSC1 (Q2 cycle) to Port
PIC18FXX20
100
200
0
Input Invalid (I/O in hold time)
18A
19
PIC18LFXX20
—
VDD = 2.0V
TIOV2OSH Port Input Valid to OSC1 (I/O in setup time)
—
20
TIOR
Port Output Rise Time
Port Output Fall Time
INT pin High or Low Time
PIC18FXX20
PIC18LFXX20
PIC18FXX20
PIC18LFXX20
—
25
60
25
60
—
20A
21
—
VDD = 2.0V
VDD = 2.0V
TIOF
—
21A
22†
23†
24†
—
TINP
TCY
TCY
20
TRBP
TRCP
RB7:RB4 Change INT High or Low Time
RC7:RC4 Change INT High or Low Time
—
—
†
These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
FIGURE 26-9:
PROGRAM MEMORY READ TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
(1)
OSC1
A<19:16>
BA0
Address
Address
Address
Data from External
Address
AD<15:0>
163
162
150
151
160
155
161
166
167
168
169
ALE
CE
164
171
171A
OE
165
Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < +125°C unless otherwise stated.
Note 1: Maximum speed of FOSC is 25 MHz for external program memory read.
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TABLE 26-9: CLKO AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristics
Min
Typ
Max
Units
150
TADV2ALL Address Out Valid to ALE (address
0.25 TCY – 10
—
—
ns
setup time)
151
155
160
161
162
163
164
165
166
167
168
169
171
TALL2ADL ALE to Address Out Invalid (address hold time)
TALL2OEL ALE to OE
5
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
0.125 TCY
—
TADZ2OEL AD high-Z to OE (bus release to OE)
TOEH2ADD OE to AD Driven
0
—
—
—
0.125 TCY – 5
—
TADV2OEH LS Data Valid before OE (data setup time)
TOEH2ADL OE to Data In Invalid (data hold time)
TALH2ALL ALE Pulse Width
20
—
—
0
—
—
—
0.25 TCY
0.5 TCY
TCY
—
—
TOEL2OEH OE Pulse Width
0.5 TCY – 5
—
—
TALH2ALH ALE to ALE (cycle time)
—
TACC
TOE
Address Valid to Data Valid
0.75 TCY – 25
—
0.5 TCY – 25
0.625 TCY + 10
10
OE to Data Valid
—
TALL2OEH ALE to OE
0.625 TCY – 10
—
—
TALH2CSL Chip Enable Active to ALE
—
171A TUBL2OEH AD Valid to Chip Enable Active
0.25 TCY – 20
—
—
FIGURE 26-10:
PROGRAM MEMORY WRITE TIMING DIAGRAM
Q1
Q2
Q3
Q4
Q1
Q2
(1)
OSC1
A<19:16>
BA0
Address
Address
Address
166
Data
Address
AD<15:0>
153
150
151
156
ALE
CE
171
171A
154
WRH or
WRL
157A
157
UB or
LB
Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < +125°C unless otherwise stated.
Note 1: Maximum speed of FOSC is 25 MHz for external program memory read.
2003-2013 Microchip Technology Inc.
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TABLE 26-10: PROGRAM MEMORY WRITE TIMING REQUIREMENTS
Param
Symbol
Characteristics
Min
Typ
Max
Units
No.
150
TADV2ALL Address Out Valid to ALE (address setup time)
TALL2ADL ALE to Address Out Invalid (address hold time)
TWRH2ADL WRn to Data Out Invalid (data hold time)
TWRL WRn Pulse Width
0.25 TCY – 10
5
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
151
153
154
156
157
5
—
0.5 TCY – 5
0.5 TCY – 10
0.25 TCY
0.5 TCY
—
TADV2WRH Data Valid before WRn (data setup time)
TBSV2WRL Byte Select Valid before WRn (byte select setup
—
time)
157A
166
TWRH2BSI WRn to Byte Select Invalid (byte select hold time) 0.125 TCY – 5
—
TCY
—
—
—
10
—
ns
ns
ns
ns
TALH2ALH ALE to ALE (cycle time)
TALH2CSL Chip Enable Active to ALE
TUBL2OEH AD Valid to Chip Enable Active
—
—
171
171A
0.25 TCY – 20
—
FIGURE 26-11:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note:
Refer to Figure 26-6 for load conditions.
DS39609C-page 324
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FIGURE 26-12:
BROWN-OUT RESET TIMING
BVDD
VDD
35
VBGAP = 1.2V
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
36
TABLE 26-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TMCL
TWDT
MCLR Pulse Width (low)
2
7
—
—
s
31
Watchdog Timer Time-out Period (no
postscaler)
18
33
ms
32
33
34
TOST
Oscillation Start-up Timer Period
Power-up Timer Period
1024 TOSC
—
72
2
1024 TOSC
—
ms
s
TOSC = OSC1 period
TPWRT
28
—
132
—
TIOZ
I/O High-Impedance from MCLR Low
or Watchdog Timer Reset
35
36
TBOR
Brown-out Reset Pulse Width
200
—
—
—
s
s
VDD BVDD (see D005)
VDD VLVD
TIVRST
Time for Internal Reference
Voltage to become stable
20
50
37
TLVD
Low-Voltage Detect Pulse Width
200
—
—
s
FIGURE 26-13:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T13CKI
46
45
47
48
TMR0 or
TMR1
Note:
Refer to Figure 26-6 for load conditions.
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TABLE 26-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
40
TT0H
T0CKI High Pulse Width
No prescaler
With prescaler
No prescaler
With prescaler
No prescaler
With prescaler
0.5 TCY + 20
10
—
—
—
—
—
—
ns
ns
ns
ns
ns
41
42
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
0.5 TCY + 20
10
TCY + 10
Greater of:
20 ns or TCY + 40
N
ns N = prescale
value
(1, 2, 4,..., 256)
45
46
47
TT1H
TT1L
T13CKI
High Time
Synchronous, no prescaler
Synchronous, PIC18FXX20
0.5 TCY + 20
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
with prescaler
PIC18LFXX20
25
—
Asynchronous PIC18FXX20
PIC18LFXX20
30
—
50
0.5 TCY + 5
10
—
T13CKI
Low Time
Synchronous, no prescaler
—
Synchronous, PIC18FXX20
with prescaler
PIC18LFXX20
—
25
—
Asynchronous PIC18FXX20
PIC18LFXX20
30
—
TBD
TBD
—
TT1P
FT1
T13CKI
Input Period
Synchronous
Greater of:
20 ns or TCY + 40
N
ns N = prescale
value (1, 2, 4, 8)
Asynchronous
60
DC
—
50
ns
kHz
—
T13CKI Oscillator Input Frequency Range
48
TCKE2TMRI Delay from External T13CKI Clock Edge to
Timer Increment
2 TOSC
7 TOSC
FIGURE 26-14:
CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES)
CCPx
(Capture Mode)
50
51
52
54
CCPx
(Compare or PWM Mode)
53
Note:
Refer to Figure 26-6 for load conditions.
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TABLE 26-13: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
50
TCCL
CCPx Input Low No prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
Time
With
prescaler
PIC18FXX20
PIC18LFXX20
10
20
51
TCCH
CCPx Input High No prescaler
0.5 TCY + 20
Time
With
prescaler
PIC18FXX20
PIC18LFXX20
10
20
52
53
TCCP
TCCR
CCPx Input Period
3 TCY + 40
N
N = prescale
value (1, 4 or 16)
CCPx Output Rise Time
CCPx Output Fall Time
PIC18FXX20
PIC18LFXX20
PIC18FXX20
PIC18LFXX20
—
—
—
—
25
45
25
45
ns
ns
ns
ns
VDD = 2.0V
VDD = 2.0V
54
TCCF
FIGURE 26-15:
PARALLEL SLAVE PORT TIMING (PIC18F8X20)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note:
Refer to Figure 26-6 for load conditions.
2003-2013 Microchip Technology Inc.
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TABLE 26-14: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F8X20)
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
62
TDTV2WRH Data In Valid before WR or CS
20
25
—
—
ns
ns
(setup time)
Extended Temp. range
63
64
TWRH2DTI
TRDL2DTV
WR or CS to Data–In
Invalid (hold time)
PIC18FXX20
20
—
—
ns
ns
VDD = 2.0V
PIC18LFXX20 35
RD and CS to Data–Out Valid
—
—
80
90
ns
ns
Extended Temp. range
65
66
TRDH2DTI
TIBFINH
RD or CS to Data–Out Invalid
10
—
30
ns
Inhibit of the IBF flag bit being cleared from
3 TCY
WR or CS
FIGURE 26-16:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
75, 76
MSb In
74
LSb In
bit 6 - - - -1
73
Note: Refer to Figure 26-6 for load conditions.
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TABLE 26-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS to SCK or SCK Input
TCY
—
ns
TSSL2SCL
71
TSCH
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
SCK Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 1.5 TCY + 40
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
ns
75
TDOR
SDO Data Output Rise Time
PIC18FXX20
PIC18LFXX20
—
—
—
—
—
—
—
—
25
45
25
25
45
25
50
100
ns
ns VDD = 2.0V
76
78
TDOF
TSCR
SDO Data Output Fall Time
ns
SCK Output Rise Time
(Master mode)
PIC18FXX20
PIC18LFXX20
ns
ns VDD = 2.0V
79
80
TSCF
SCK Output Fall Time (Master mode)
ns
TSCH2DOV, SDO Data Output Valid after SCK PIC18FXX20
TSCL2DOV Edge
ns
PIC18LFXX20
ns VDD = 2.0V
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
FIGURE 26-17:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
bit 6 - - - - - -1
LSb
MSb
SDO
SDI
75, 76
LSb In
MSb In
74
bit 6 - - - -1
Note: Refer to Figure 26-6 for load conditions.
2003-2013 Microchip Technology Inc.
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TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param
No.
Symbol
TSCH
Characteristic
Min
Max Units Conditions
71
SCK Input High Time
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
(Slave mode)
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
SCK Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge of Byte 2 1.5 TCY + 40
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
ns
75
TDOR
SDO Data Output Rise Time
PIC18FXX20
PIC18LFXX20
—
—
25
45
25
25
45
25
50
100
—
ns
ns VDD = 2.0V
76
78
TDOF
TSCR
SDO Data Output Fall Time
—
ns
SCK Output Rise Time
(Master mode)
PIC18FXX20
PIC18LFXX20
—
ns
—
ns VDD = 2.0V
79
80
TSCF
SCK Output Fall Time (Master mode)
—
ns
TSCH2DOV, SDO Data Output Valid after SCK PIC18FXX20
TSCL2DOV Edge
—
ns
PIC18LFXX20
—
ns VDD = 2.0V
ns
81
TDOV2SCH, SDO Data Output Setup to SCK Edge
TDOV2SCL
TCY
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
FIGURE 26-18:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
LSb
MSb
SDO
SDI
bit 6 - - - - - -1
77
75, 76
MSb In
74
bit 6 - - - -1
LSb In
73
Note:
Refer to Figure 26-6 for load conditions.
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TABLE 26-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS to SCK or SCK Input
TCY
—
ns
TSSL2SCL
71
TSCH
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
TSCL
SCK Input Low Time
(Slave mode)
ns
72A
73
ns (Note 1)
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
—
—
ns (Note 2)
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
ns
75
TDOR
SDO Data Output Rise Time
PIC18FXX20
PIC18LFXX20
—
25
45
25
50
25
45
25
50
100
—
ns
—
ns VDD = 2.0V
76
77
78
TDOF
SDO Data Output Fall Time
—
ns
TSSH2DOZ SS to SDO Output High-Impedance
10
ns
TSCR
SCK Output Rise Time (Master mode) PIC18FXX20
PIC18LFXX20
—
ns
—
ns VDD = 2.0V
79
80
TSCF
SCK Output Fall Time (Master mode)
—
ns
TSCH2DOV, SDO Data Output Valid after SCK Edge PIC18FXX20
TSCL2DOV
—
—
ns
PIC18LFXX20
ns VDD = 2.0V
ns
83
TSCH2SSH, SS after SCK Edge
1.5 TCY + 40
TSCL2SSH
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
FIGURE 26-19:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
75, 76
77
MSb In
74
bit 6 - - - -1
LSb In
Note: Refer to Figure 26-6 for load conditions.
2003-2013 Microchip Technology Inc.
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TABLE 26-18: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS to SCK or SCK Input
TCY
—
ns
TSSL2SCL
71
TSCH
TSCL
TB2B
SCK Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
ns
SCK Input Low Time
(Slave mode)
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
75
TDOR
SDO Data Output Rise Time
PIC18FXX20
PIC18LFXX20
—
25
45
25
50
25
45
25
50
100
50
100
—
ns
—
ns VDD = 2.0V
76
77
78
TDOF
SDO Data Output Fall Time
—
ns
TSSH2DOZ SS to SDO Output High-Impedance
10
ns
TSCR
SCK Output Rise Time
(Master mode)
PIC18FXX20
PIC18LFXX20
—
ns
—
ns VDD = 2.0V
79
80
TSCF
SCK Output Fall Time (Master mode)
—
ns
TSCH2DOV, SDO Data Output Valid after SCK
TSCL2DOV Edge
PIC18FXX20
PIC18LFXX20
—
ns
—
ns VDD = 2.0V
82
83
TSSL2DOV SDO Data Output Valid after SS PIC18FXX20
—
—
ns
Edge
PIC18LFXX20
ns VDD = 2.0V
ns
TSCH2SSH, SS after SCK Edge
1.5 TCY + 40
TSCL2SSH
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
FIGURE 26-20:
I2C BUS START/STOP BITS TIMING
SCL
SDA
91
93
90
92
Stop
Condition
Start
Condition
Note: Refer to Figure 26-6 for load conditions.
DS39609C-page 332
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TABLE 26-19: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
ns
Only relevant for Repeated
Start condition
91
92
93
THD:STA Start Condition
Hold Time
4000
600
ns
ns
ns
After this period, the first
clock pulse is generated
TSU:STO Stop Condition
Setup Time
4700
600
THD:STO Stop Condition
Hold Time
4000
600
FIGURE 26-21:
I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 26-6 for load conditions.
2003-2013 Microchip Technology Inc.
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TABLE 26-20: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
100
THIGH
Clock High Time
100 kHz mode
4.0
0.6
—
—
—
—
s
s
400 kHz mode
SSP module
1.5 TCY
4.7
101
TLOW
Clock Low Time
100 kHz mode
s
s
PIC18FXX20 must operate
at a minimum of 1.5 MHz
400 kHz mode
1.3
—
PIC18FXX20 must operate
at a minimum of 10 MHz
SSP module
1.5 TCY
—
—
102
103
TR
TF
SDA and SCL Rise 100 kHz mode
1000
ns
ns
Time
400 kHz mode
20 + 0.1 CB 300
CB is specified to be from
10 to 400 pF
SDA and SCL Fall 100 kHz mode
Time
—
300
ns
ns
400 kHz mode
20 + 0.1 CB 300
CB is specified to be from
10 to 400 pF
90
TSU:STA
THD:STA
Start Condition
Setup Time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
s
s
s
s
ns
s
ns
ns
s
s
ns
ns
s
s
Only relevant for Repeated
Start condition
91
Start Condition
Hold Time
—
After this period, the first
clock pulse is generated
—
106
107
92
THD:DAT Data Input Hold
Time
—
0
0.9
—
TSU:DAT
TSU:STO
TAA
Data Input Setup
Time
250
100
4.7
0.6
—
(Note 2)
—
Stop Condition
Setup Time
—
—
109
110
Output Valid from
Clock
3500
—
(Note 1)
—
TBUF
Bus Free Time
4.7
1.3
—
Time the bus must be free
before a new transmission
can start
—
D102
CB
Bus Capacitive Loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement,
TSU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch the
LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
standard mode I2C bus specification), before the SCL line is released.
DS39609C-page 334
2003-2013 Microchip Technology Inc.
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FIGURE 26-22:
MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS
SCL
SDA
93
91
90
92
Stop
Condition
Start
Condition
Note: Refer to Figure 26-6 for load conditions.
TABLE 26-21: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for
Repeated Start condition
91
92
93
THD:STA Start Condition
Hold Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ns After this period, the first
clock pulse is generated
2(TOSC)(BRG + 1)
TSU:STO Stop Condition
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1) 2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ns
ns
2(TOSC)(BRG + 1)
THD:STO Stop Condition
Hold Time
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
FIGURE 26-23:
MASTER SSP I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 26-6 for load conditions.
2003-2013 Microchip Technology Inc.
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TABLE 26-22: MASTER SSP I2C BUS DATA REQUIREMENTS
Param
Symbol
Characteristic
Min
Max Units
Conditions
No.
100
THIGH
Clock High Time 100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
—
—
ms
ms
ms
ms
ms
ms
ns
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
101
102
103
90
TLOW
TR
Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
—
—
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
SDA and SCL
Rise Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
1000
300
300
300
300
100
—
CB is specified to be from
10 to 400 pF
20 + 0.1 CB
ns
—
ns
TF
SDA and SCL
Fall Time
—
20 + 0.1 CB
—
ns
CB is specified to be from
10 to 400 pF
ns
ns
TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1)
ms Only relevant for
Setup Time
Repeated Start condition
400 kHz mode 2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
91
THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1)
—
ms After this period, the first
Hold Time
clock pulse is generated
400 kHz mode 2(TOSC)(BRG + 1)
—
ms
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
ns
106
107
92
THD:DAT Data Input
Hold Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
0
—
0
0.9
—
ms
ns
TBD
250
100
TBD
TSU:DAT Data Input
Setup Time
—
ns
ns
(Note 2)
—
—
ns
TSU:STO Stop Condition
Setup Time
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
ms
ms
ms
ns
—
—
109
110
D102
TAA
TBUF
CB
Output Valid
from Clock
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
—
—
3500
1000
—
ns
—
ns
Bus Free Time
4.7
1.3
TBD
—
—
ms
ms
ms
pF
Time the bus must be free
before a new transmission
can start
—
—
Bus Capacitive Loading
400
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107 250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the
SCL line is released.
DS39609C-page 336
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FIGURE 26-24:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX1/CK1
pin
121
121
RC7/RX1/DT1
pin
120
Refer to Figure 26-6 for load conditions.
122
Note:
TABLE 26-23: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units Conditions
No.
120
TCKH2DTV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid
PIC18FXX20
PIC18LFXX20
—
—
—
—
—
—
40
100
20
ns
ns VDD = 2.0V
ns
121
122
TCKRF
TDTRF
Clock Out Rise Time and Fall Time PIC18FXX20
(Master mode)
PIC18LFXX20
50
ns VDD = 2.0V
ns
Data Out Rise Time and Fall Time
PIC18FXX20
PIC18LFXX20
20
50
ns VDD = 2.0V
FIGURE 26-25:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX1/CK1
pin
125
RC7/RX1/DT1
pin
126
Note: Refer to Figure 26-6 for load conditions.
TABLE 26-24: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TDTV2CKL SYNC RCV (MASTER & SLAVE)
Data Hold before CK (DT hold time)
10
15
—
—
ns
ns
126
TCKL2DTL Data Hold after CK (DT hold time)
2003-2013 Microchip Technology Inc.
DS39609C-page 337
PIC18F6520/8520/6620/8620/6720/8720
TABLE 26-25: A/D CONVERTER CHARACTERISTICS: PIC18FXX20 (INDUSTRIAL, EXTENDED)
PIC18LFXX20 (INDUSTRIAL)
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
A01
NR
Resolution
—
—
—
—
—
—
10
<±1
bit
A03
A04
A05
A06
A10
EIL
Integral Linearity Error
Differential Linearity Error
Gain Error
—
LSb VREF = VDD = 5.0V
LSb VREF = VDD = 5.0V
LSb VREF = VDD = 5.0V
LSb VREF = VDD = 5.0V
EDL
EG
—
<±1
—
—
<±1
EOFF
—
Offset Error
<±1.5
(2)
Monotonicity
guaranteed
—
VSS VAIN VREF
A20
A20A
VREF
Reference Voltage
(VREFH – VREFL)
1.8V
3V
—
—
—
—
V
V
VDD < 3.0V
VDD 3.0V
A21
A22
A25
A30
VREFH
VREFL
VAIN
Reference Voltage High
Reference Voltage Low
Analog Input Voltage
AVSS
AVSS – 0.3V
AVSS – 0.3V
—
—
AVDD + 0.3V
VREFH
V
V
V
(5)
—
(5)
(5)
—
AVDD + 0.3V
2.5
VDD 2.5V (Note 3)
ZAIN
Recommended Impedance of
Analog Voltage Source
—
k (Note 4)
A50
IREF
VREF Input Current (Note 1)
—
—
—
—
5
150
A During VAIN acquisition.
A During A/D conversion
cycle.
Note 1: Vss VAIN VREF
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
3: For VDD < 2.5V, VAIN should be limited to <.5 VDD.
4: Maximum allowed impedance for analog voltage source is 10 k. This requires higher acquisition times.
5: IVDD – AVDDI must be <3.0V and IAVSS – VSSI must be <0.3V.
FIGURE 26-26:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
NEW_DATA
TCY
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEPinstruction to be
executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
DS39609C-page 338
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
TABLE 26-26: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
PIC18FXX20
Min
Max
Units
Conditions
130
TAD
A/D Clock Period
1.6
3.0
2.0
3.0
11
20(5)
20(5)
6.0
s TOSC based, VREF 3.0V
s TOSC based, VREF full range
s A/D RC mode
PIC18LFXX20
PIC18FXX20
PIC18LFXX20
9.0
s A/D RC mode
131
132
TCNV
TACQ
Conversion Time
(not including acquisition time) (Note 1)
Acquisition Time (Note 3)
12
TAD
15
10
—
—
s -40C Temp +125C
s 0C Temp +125C
135
136
TSWC
TAMP
Switching Time from Convert Sample
Amplifier Settling Time (Note 2)
—
1
(Note 4)
—
s This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from the
last sampled voltage (as
stated on CHOLD).
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 19.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when
input voltage has changed more than 1 LSb.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels
is 50.
4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2003-2013 Microchip Technology Inc.
DS39609C-page 339
PIC18F6520/8520/6620/8620/6720/8720
NOTES:
DS39609C-page 340
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
27.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean + 3) or (mean –‘
3) respectively, where is a standard deviation, over the whole temperature range.
FIGURE 27-1:
TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
20
18
16
14
12
10
8
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
6
3.0V
4
2.5V
2
2.0V
0
4
6
8
10
12
14
16
18
20
22
24
26
FOSC (MHz)
FIGURE 27-2:
MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) INDUSTRIAL
20
18
16
14
12
10
8
5.5V
5.0V
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +85°C)
Minimum: mean – 3 (-40°C to +85°C)
4.5V
4.0V
3.5V
3.0V
6
4
2.5V
2
2.0V
0
4
6
8
10
12
14
16
18
20
22
24
26
FOSC (MHz)
2003-2013 Microchip Technology Inc.
DS39609C-page 341
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 27-3:
MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) EXTENDED
20
18
16
14
12
10
8
5.5V
5.0V
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
4.5V
4.0V
3.5V
3.0V
6
4
2.5V
2
2.0V
0
4
6
8
10
12
14
16
18
20
22
24
26
FOSC (MHz)
FIGURE 27-4:
TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE)
20
18
16
14
12
10
8
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
6
3.0V
4
2.5V
2
2.0V
0
4
6
8
10
12
14
16
18
20
22
24
26
FOSC (MHz)
DS39609C-page 342
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 27-5:
MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) INDUSTRIAL
20
18
16
14
12
10
8
5.5V
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +85°C)
Minimum: mean – 3 (-40°C to +85°C)
5.0V
4.5V
4.0V
3.5V
3.0V
6
4
2.5V
2
2.0V
0
4
6
8
10
12
14
16
18
20
22
24
26
FOSC (MHz)
FIGURE 27-6:
MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) EXTENDED
20
18
16
14
12
10
8
5.5V
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
5.0V
4.5V
4.0V
3.5V
3.0V
6
4
2.5V
2
2.0V
6.0
0
4.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
22.0
24.0
26.0
FOSC (MHz)
2003-2013 Microchip Technology Inc.
DS39609C-page 343
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 27-7:
TYPICAL IDD vs. FOSC OVER VDD (XT MODE)
3.0
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
2.5
2.0
1.5
1.0
0.5
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
FIGURE 27-8:
MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) INDUSTRIAL
3.0
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +85°C)
Minimum: mean – 3 (-40°C to +85°C)
2.5
2.0
1.5
1.0
0.5
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
DS39609C-page 344
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 27-9:
TYPICAL IDD vs. FOSC OVER VDD (LP MODE)
100
90
80
70
60
50
40
30
20
10
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0
0
10
20
30
40
50
60
70
80
90
100
FOSC (kHz)
FIGURE 27-10:
MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) INDUSTRIAL
120
Typical:
statistical mean @ 25°C
100
80
60
40
20
0
Maximum: mean + 3 (-40°C to +85°C)
Minimum: mean – 3 (-40°C to +85°C)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0
10
20
30
40
50
60
70
80
90
100
FOSC (kHz)
2003-2013 Microchip Technology Inc.
DS39609C-page 345
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 27-11:
MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) EXTENDED
300
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
5.5V
5.0V
250
200
150
100
50
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0
0
10
20
30
40
50
60
70
80
90
100
FOSC (kHz)
FIGURE 27-12:
TYPICAL IDD vs. FOSC OVER VDD (EC MODE)
18
Typical:
statistical mean @ 25°C
16
14
12
10
8
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
5.5V
5.0V
4.5V
4.0V
3.5V
6
3.0V
4
2.5V
2
2.0V
0
4
6
8
10
12
14
16
18
20
22
24
26
FOSC (MHz)
DS39609C-page 346
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 27-13:
MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)
18
5.5V
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
16
14
12
10
8
5.0V
4.5V
4.0V
3.5V
6
3.0V
4
2.5V
2
2.0V
0
4
6
8
10
12
14
16
18
20
22
24
26
FOSC (MHz)
FIGURE 27-14:
MAXIMUM IPD vs. VDD OVER TEMPERATURE
100
Max
(-40°C:+125°C)
10
Max
(-40°C:+85°C)
Typical:
statistical mean @ 25°C
1
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.1
Typ
(25°C)
0.01
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2003-2013 Microchip Technology Inc.
DS39609C-page 347
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 27-15:
TYPICAL AND MAXIMUM IPD vs. VDD OVER TEMPERATURE
(TIMER1 AS MAIN OSCILLATOR, 32.768 kHz, C1 AND C2 = 47 pF)
1000
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
100
Max
(-40°C:+125°C)
Max
(-40°C:+85°C)
10
Typ
(25°C)
1
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 27-16:
TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE (WDT ENABLED)
1000
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
Max
(-40°C:+125°C)
100
10
1
Max
(-40°C:+85°C)
Typ
(25°C)
0.1
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS39609C-page 348
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 27-17:
TYPICAL IDD vs. FOSC OVER VDD (EC MODE)
0.55
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
FIGURE 27-18:
MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)
0.55
Typical:
statistical mean @ 25°C
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
5.5V
5.0V
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
FOSC (MHz)
2003-2013 Microchip Technology Inc.
DS39609C-page 349
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 27-19:
TYPICAL IDD vs. FOSC OVER VDD (EC MODE) (PIC18F8520 DEVICES ONLY)
30
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
25
20
15
10
5
5.5V
5.0V
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
FIGURE 27-20:
MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) INDUSTRIAL
(PIC18F8520 DEVICES ONLY)
30
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +85°C)
Minimum: mean – 3 (-40°C to +85°C)
5.5V
5.0V
25
20
15
10
5
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
DS39609C-page 350
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 27-21:
MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) EXTENDED
(PIC18F8520 DEVICES ONLY)
20
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
18
16
14
12
10
8
5.5V
5.0V
4.5V
4.2V
4.0V
3.5V
3.0V
6
4
2.5V
2
2.0V
0
4
6
8
10
12
14
16
(MHz)
18
20
22
24
26
F
OSC
FIGURE 27-22:
TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE)
(PIC18F8520 DEVICES ONLY)
30
27
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
24
21
18
15
12
9
5.5V
5.0V
4.5V
4.2V
4.0V
3.5V
6
3.0V
3
2.5V
2.0V
0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
2003-2013 Microchip Technology Inc.
DS39609C-page 351
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 27-23:
MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) INDUSTRIAL
(PIC18F8520 DEVICES ONLY)
30
27
24
21
18
15
12
9
5.5V
5.0V
4.5V
Typical:
statistical mean @ 25°C
Maximum: mean + 3 (-40°C to +85°C)
Minimum: mean – 3 (-40°C to +85°C)
4.2V
4.0V
3.5V
3.0V
6
3
2.5V
2.0V
0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
FIGURE 27-24:
MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) EXTENDED
(PIC18F8520 DEVICES ONLY)
20
18
Typical:
statistical mean @ 25°C
16
14
12
10
8
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
5.5V
5.0V
4.5V
4.2V
4.0V
3.5V
3.0V
6
4
2.5V
2
2.0V
0
4
6
8
10
12
14
16
18
20
22
24
26
FOSC (MHz)
DS39609C-page 352
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
FIGURE 27-25:
A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40C TO +125C)
4
3.5
3
-40°C
+25°C
25C
2.5
2
+85°C
85C
1.5
1
0.5
0
+125°C
125C
2
2.5
3
3.5
4
4.5
5
5.5
VDD and VREFH (V)
FIGURE 27-26:
A/D NONLINEARITY vs. VREFH (VDD = 5V, -40C TO +125C)
3
2.5
2
1.5
1
Max (-40°C to +125°C)
TTyypp((+2255C°)C)
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
VREFH (V)
2003-2013 Microchip Technology Inc.
DS39609C-page 353
PIC18F6520/8520/6620/8620/6720/8720
NOTES:
DS39609C-page 354
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
28.0 PACKAGING INFORMATION
28.1 Package Marking Information
64-Lead TQFP (10x10x1 mm)
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18F6620
-I/PT
e
3
0410017
80-Lead TQFP (12x12x1 mm)
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC18F8720
-E/PT
e
3
0410017
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2003-2013 Microchip Technology Inc.
DS39609C-page 355
PIC18F6520/8520/6620/8620/6720/8720
28.2 Package Details
The following sections give the technical details of the packages.
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇMꢇꢘꢙꢚꢘꢙꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&
' ꢋꢄ( 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢏꢆꢌ4ꢆꢕꢈꢅ#ꢉꢆ*ꢃꢄꢕ!(ꢅꢏꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢒꢃꢌꢉꢋꢌꢍꢃꢏꢅꢂꢆꢌ4ꢆꢕꢃꢄꢕꢅꢗꢏꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢏ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢏꢁꢌꢋ'5ꢏꢆꢌ4ꢆꢕꢃꢄꢕ
D
D1
E
e
E1
N
b
1 2 3
NOTE 1
NOTE 2
α
A
c
φ
A2
A1
β
L
L1
6ꢄꢃ&!
ꢒꢚ77ꢚꢒ.ꢘ.ꢙꢗ
ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢅ7ꢃ'ꢃ&!
ꢒꢚ8
89ꢒ
;ꢔ
ꢓꢁ/ꢓꢅ1ꢗ+
M
ꢀꢁꢓꢓ
M
ꢒꢖ:
8"')ꢈꢉꢅꢋ%ꢅ7ꢈꢆ#!
7ꢈꢆ#ꢅꢂꢃ&ꢌꢍ
9 ꢈꢉꢆꢇꢇꢅ<ꢈꢃꢕꢍ&
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅꢘꢍꢃꢌ4ꢄꢈ!!
ꢗ&ꢆꢄ#ꢋ%%ꢅꢅ
3ꢋꢋ&ꢅ7ꢈꢄꢕ&ꢍ
8
ꢈ
ꢖ
ꢖꢎ
ꢖꢀ
7
M
ꢀꢁꢎꢓ
ꢀꢁꢓ/
ꢓꢁꢀ/
ꢓꢁꢜ/
ꢓꢁꢛ/
ꢓꢁꢓ/
ꢓꢁꢔ/
ꢓꢁ;ꢓ
3ꢋꢋ&ꢏꢉꢃꢄ&
3ꢋꢋ&ꢅꢖꢄꢕꢇꢈ
7ꢀ
ꢀ
ꢀꢁꢓꢓꢅꢙ.3
ꢐꢁ/ꢝ
ꢓꢝ
ꢜꢝ
9 ꢈꢉꢆꢇꢇꢅ?ꢃ#&ꢍ
9 ꢈꢉꢆꢇꢇꢅ7ꢈꢄꢕ&ꢍ
.
ꢑ
.ꢀ
ꢑꢀ
ꢌ
ꢀꢎꢁꢓꢓꢅ1ꢗ+
ꢀꢎꢁꢓꢓꢅ1ꢗ+
ꢀꢓꢁꢓꢓꢅ1ꢗ+
ꢀꢓꢁꢓꢓꢅ1ꢗ+
M
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅ?ꢃ#&ꢍ
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅ7ꢈꢄꢕ&ꢍ
7ꢈꢆ#ꢅꢘꢍꢃꢌ4ꢄꢈ!!
7ꢈꢆ#ꢅ?ꢃ#&ꢍ
ꢒꢋꢇ#ꢅꢑꢉꢆ%&ꢅꢖꢄꢕꢇꢈꢅꢘꢋꢏ
ꢒꢋꢇ#ꢅꢑꢉꢆ%&ꢅꢖꢄꢕꢇꢈꢅ1ꢋ&&ꢋ'
ꢓꢁꢓꢛ
ꢓꢁꢀꢜ
ꢀꢀꢝ
ꢓꢁꢎꢓ
ꢓꢁꢎꢜ
ꢀꢐꢝ
)
ꢁ
ꢓꢁꢎꢎ
ꢀꢎꢝ
ꢀꢎꢝ
ꢂ
ꢀꢀꢝ
ꢀꢐꢝ
' ꢋꢄꢊ(
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ +ꢍꢆ'%ꢈꢉ!ꢅꢆ&ꢅꢌꢋꢉꢄꢈꢉ!ꢅꢆꢉꢈꢅꢋꢏ&ꢃꢋꢄꢆꢇ,ꢅ!ꢃ-ꢈꢅ'ꢆꢊꢅ ꢆꢉꢊꢁ
ꢐꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢑꢀꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢒꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢓꢁꢎ/ꢅ''ꢅꢏꢈꢉꢅ!ꢃ#ꢈꢁ
ꢔꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢕꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢕꢅꢏꢈꢉꢅꢖꢗꢒ.ꢅ0ꢀꢔꢁ/ꢒꢁ
1ꢗ+2 1ꢆ!ꢃꢌꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢘꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢙ.32 ꢙꢈ%ꢈꢉꢈꢄꢌꢈꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢏ"ꢉꢏꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢒꢃꢌꢉꢋꢌꢍꢃꢏ ꢘꢈꢌꢍꢄꢋꢇꢋꢕꢊ ꢑꢉꢆ*ꢃꢄꢕ +ꢓꢔꢞꢓ@/1
DS39609C-page 356
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2013 Microchip Technology Inc.
DS39609C-page 357
PIC18F6520/8520/6620/8620/6720/8720
)ꢙꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇMꢇꢘ#ꢚꢘ#ꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&
' ꢋꢄ( 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢏꢆꢌ4ꢆꢕꢈꢅ#ꢉꢆ*ꢃꢄꢕ!(ꢅꢏꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢒꢃꢌꢉꢋꢌꢍꢃꢏꢅꢂꢆꢌ4ꢆꢕꢃꢄꢕꢅꢗꢏꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢏ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢏꢁꢌꢋ'5ꢏꢆꢌ4ꢆꢕꢃꢄꢕ
D
D1
E
e
E1
N
b
NOTE 1
123
α
NOTE 2
A
c
φ
A2
β
A1
L1
L
6ꢄꢃ&!
ꢒꢚ77ꢚꢒ.ꢘ.ꢙꢗ
ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢅ7ꢃ'ꢃ&!
ꢒꢚ8
M
ꢓꢁꢛ/
ꢓꢁꢓ/
ꢓꢁꢔ/
89ꢒ
@ꢓ
ꢓꢁ/ꢓꢅ1ꢗ+
M
ꢀꢁꢓꢓ
M
ꢒꢖ:
8"')ꢈꢉꢅꢋ%ꢅ7ꢈꢆ#!
7ꢈꢆ#ꢅꢂꢃ&ꢌꢍ
9 ꢈꢉꢆꢇꢇꢅ<ꢈꢃꢕꢍ&
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅꢘꢍꢃꢌ4ꢄꢈ!!
ꢗ&ꢆꢄ#ꢋ%%ꢅꢅ
3ꢋꢋ&ꢅ7ꢈꢄꢕ&ꢍ
8
ꢈ
ꢖ
ꢖꢎ
ꢖꢀ
7
ꢀꢁꢎꢓ
ꢀꢁꢓ/
ꢓꢁꢀ/
ꢓꢁꢜ/
ꢓꢁ;ꢓ
3ꢋꢋ&ꢏꢉꢃꢄ&
3ꢋꢋ&ꢅꢖꢄꢕꢇꢈ
7ꢀ
ꢀ
ꢀꢁꢓꢓꢅꢙ.3
ꢐꢁ/ꢝ
ꢓꢝ
ꢜꢝ
9 ꢈꢉꢆꢇꢇꢅ?ꢃ#&ꢍ
9 ꢈꢉꢆꢇꢇꢅ7ꢈꢄꢕ&ꢍ
.
ꢑ
.ꢀ
ꢑꢀ
ꢌ
ꢀꢔꢁꢓꢓꢅ1ꢗ+
ꢀꢔꢁꢓꢓꢅ1ꢗ+
ꢀꢎꢁꢓꢓꢅ1ꢗ+
ꢀꢎꢁꢓꢓꢅ1ꢗ+
M
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅ?ꢃ#&ꢍ
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅ7ꢈꢄꢕ&ꢍ
7ꢈꢆ#ꢅꢘꢍꢃꢌ4ꢄꢈ!!
7ꢈꢆ#ꢅ?ꢃ#&ꢍ
ꢒꢋꢇ#ꢅꢑꢉꢆ%&ꢅꢖꢄꢕꢇꢈꢅꢘꢋꢏ
ꢒꢋꢇ#ꢅꢑꢉꢆ%&ꢅꢖꢄꢕꢇꢈꢅ1ꢋ&&ꢋ'
ꢓꢁꢓꢛ
ꢓꢁꢀꢜ
ꢀꢀꢝ
ꢓꢁꢎꢓ
ꢓꢁꢎꢜ
ꢀꢐꢝ
)
ꢁ
ꢓꢁꢎꢎ
ꢀꢎꢝ
ꢀꢎꢝ
ꢂ
ꢀꢀꢝ
ꢀꢐꢝ
' ꢋꢄꢊ(
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ +ꢍꢆ'%ꢈꢉ!ꢅꢆ&ꢅꢌꢋꢉꢄꢈꢉ!ꢅꢆꢉꢈꢅꢋꢏ&ꢃꢋꢄꢆꢇ,ꢅ!ꢃ-ꢈꢅ'ꢆꢊꢅ ꢆꢉꢊꢁ
ꢐꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢑꢀꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢒꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢓꢁꢎ/ꢅ''ꢅꢏꢈꢉꢅ!ꢃ#ꢈꢁ
ꢔꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢕꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢕꢅꢏꢈꢉꢅꢖꢗꢒ.ꢅ0ꢀꢔꢁ/ꢒꢁ
1ꢗ+2 1ꢆ!ꢃꢌꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢘꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢙ.32 ꢙꢈ%ꢈꢉꢈꢄꢌꢈꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢏ"ꢉꢏꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢒꢃꢌꢉꢋꢌꢍꢃꢏ ꢘꢈꢌꢍꢄꢋꢇꢋꢕꢊ ꢑꢉꢆ*ꢃꢄꢕ +ꢓꢔꢞꢓꢛꢎ1
DS39609C-page 358
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2003-2013 Microchip Technology Inc.
DS39609C-page 359
PIC18F6520/8520/6620/8620/6720/8720
NOTES:
DS39609C-page 360
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
APPENDIX A: REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
Revision A (January 2003)
The differences between the devices listed in this data
sheet are shown in Table B-1.
Original data sheet for the PIC18FXX20 family which
includes PIC18F6520, PIC18F6620, PIC18F6720,
PIC18F8520, PIC18F8620 and PIC18F8720 devices.
This data sheet is based on the previous PIC18FXX20
Data Sheet (DS39580).
Revision B (January 2004)
This revision includes the DC and AC Characteristics
Graphs and Tables. The Electrical Specifications in
Section 26.0 “Electrical Characteristics” have been
updated and there have been minor corrections to the
data sheet text.
Revision C (November 2011)
This revision updated Section 28.0 “Packaging Infor-
mation”.
TABLE B-1:
Feature
DEVICE DIFFERENCES
PIC18F6520 PIC18F6620 PIC18F6720 PIC18F8520 PIC18F8620 PIC18F8720
On-Chip Program Memory
(Kbytes)
32
64
128
32
64
128
Data Memory (bytes)
Boot Block (bytes)
Timer1 Low-Power Option
I/O Ports
2048
2048
Yes
3840
512
No
3840
512
No
2048
2048
Yes
3840
512
No
3840
512
No
Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C, Ports A, B, C,
D, E, F, G
D, E, F, G
D, E, F, G D, E, F, G, H, J D, E, F, G, H, J D, E, F, G, H, J
A/D Channels
12
No
40
12
No
25
12
No
25
16
Yes
40
16
Yes
25
16
Yes
25
External Memory Interface
Maximum Operating
Frequency (MHz)
Package Types
64-pin TQFP 64-pin TQFP 64-pin TQFP 80-pin TQFP 80-pin TQFP 80-pin TQFP
2003-2013 Microchip Technology Inc.
DS39609C-page 361
PIC18F6520/8520/6620/8620/6720/8720
APPENDIX C: CONVERSION
CONSIDERATIONS
APPENDIX D: MIGRATION FROM
MID-RANGE TO
ENHANCED DEVICES
This appendix discusses the considerations for
converting from previous versions of a device to the
ones listed in this data sheet. Typically, these changes
are due to the differences in the process technology
used. An example of this type of conversion is from a
PIC17C756 to a PIC18F8720.
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442”. The changes discussed, while device
specific, are generally applicable to all mid-range to
enhanced device migrations.
Not Currently Available
This Application Note is available as Literature Number
DS00716.
DS39609C-page 362
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
APPENDIX E: MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
A detailed discussion of the migration pathway and dif-
ferences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration”. This Application Note is
available as Literature Number DS00726.
2003-2013 Microchip Technology Inc.
DS39609C-page 363
PIC18F6520/8520/6620/8620/6720/8720
NOTES:
DS39609C-page 364
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
INDEX
Baud Rate Generator .............................................. 183
Capture Mode Operation ......................................... 151
A
A/D ................................................................................... 213
A/D Converter Interrupt, Configuring ....................... 217
Acquisition Requirements ........................................ 218
Acquisition Time ....................................................... 218
ADCON0 Register .................................................... 213
ADCON1 Register .................................................... 213
ADCON2 Register .................................................... 213
ADRESH Register ............................................ 213, 215
ADRESL Register ............................................ 213, 215
Analog Port Pins ...................................................... 128
Analog Port Pins, Configuring .................................. 219
Associated Register Summary ................................. 221
Calculating Minimum Required Acquisition Time (Exam-
ple) ................................................................... 218
CCP2 Trigger ........................................................... 220
Configuring the Module ............................................ 217
Conversion Clock (Tad) ........................................... 219
Conversion Requirements ....................................... 339
Conversion Status (GO/DONE Bit) .......................... 215
Conversion Tad Cycles ............................................ 220
Conversions ............................................................. 220
Converter Characteristics ........................................ 338
Equations ................................................................. 218
Minimum Charging Time .......................................... 218
Special Event Trigger (CCP) .................................... 152
Special Event Trigger (CCP2) .................................. 220
Tad vs. Device Operating Frequencies (Table) ....... 219
Absolute Maximum Ratings ............................................. 305
AC (Timing) Characteristics ............................................. 318
Load Conditions for Device Timing Specifications ... 319
Parameter Symbology ............................................. 318
Temperature and Voltage Specifications ................. 319
Timing Conditions .................................................... 319
ACKSTAT Status Flag ..................................................... 187
ADCON0 Register ............................................................ 213
GO/DONE Bit ........................................................... 215
ADCON1 Register ............................................................ 213
ADCON2 Register ............................................................ 213
ADDLW ............................................................................ 265
Addressable Universal Synchronous Asynchronous Receiver
Transmitter (USART) ............................................... 197
ADDWF ............................................................................ 265
ADDWFC ......................................................................... 266
ADRESH Register .................................................... 213, 215
ADRESL Register .................................................... 213, 215
Analog-to-Digital Converter. See A/D.
Comparator Analog Input Model .............................. 227
Comparator I/O Operating Modes (Diagram) .......... 224
Comparator Output .................................................. 226
Comparator Voltage Reference ............................... 230
Compare Mode Operation ....................................... 152
Low-Voltage Detect (LVD) ....................................... 234
Low-Voltage Detect (LVD) with External Input ........ 234
2
MSSP (I C Master Mode) ........................................ 181
2
MSSP (I C Mode) .................................................... 166
MSSP (SPI Mode) ................................................... 157
On-Chip Reset Circuit ................................................ 29
PIC18F6X20 Architecture ............................................ 9
PIC18F8X20 Architecture .......................................... 10
PLL ............................................................................ 23
PORT/LAT/TRIS Operation ..................................... 103
PORTA
RA3:RA0 and RA5 Pins ................................... 104
RA4/T0CKI Pin ................................................ 104
RA6 Pin (as I/O) .............................................. 104
PORTB
RB2:RB0 Pins .................................................. 107
RB3 Pin ........................................................... 107
RB7:RB4 Pins .................................................. 106
PORTC (Peripheral Output Override) ...................... 109
PORTD and PORTE
Parallel Slave Port ........................................... 128
PORTD in I/O Port Mode ......................................... 111
PORTD in System Bus Mode .................................. 112
PORTE in I/O Mode ................................................. 115
PORTE in System Bus Mode .................................. 115
PORTF
RF1/AN6/C2OUT and RF2/AN5/C1OUT Pins . 117
RF6/RF3 and RF0 Pins ................................... 118
RF7 Pin ........................................................... 118
PORTG (Peripheral Output Override) ..................... 120
PORTH
RH3:RH0 Pins in System Bus Mode ....... 123
RH3:RH0 Pins in I/O Mode .............................. 122
RH7:RH4 Pins in I/O Mode .............................. 122
PORTJ
RJ4:RJ0 Pins in System Bus Mode ................. 126
RJ7:RJ6 Pins in System Bus Mode ................. 126
PORTJ in I/O Mode ................................................. 125
PWM Operation (Simplified) .................................... 154
Reads from Flash Program Memory ......................... 65
Single Comparator ................................................... 225
Table Read Operation ............................................... 61
Table Write Operation ............................................... 62
Table Writes to Flash Program Memory .................... 67
Timer0 in 16-bit Mode .............................................. 132
Timer0 in 8-bit Mode ................................................ 132
Timer1 ..................................................................... 136
Timer1 (16-bit R/W Mode) ....................................... 136
Timer2 ..................................................................... 142
Timer3 ..................................................................... 144
Timer3 in 16-bit R/W Mode ...................................... 144
Timer4 ..................................................................... 148
USART Receive ...................................................... 206
USART Transmit ..................................................... 204
Voltage Reference Output Buffer Example ............. 231
ANDLW ............................................................................ 266
ANDWF ............................................................................ 267
Assembler
MPASM Assembler .................................................. 302
B
Baud Rate Generator ....................................................... 183
BC .................................................................................... 267
BCF .................................................................................. 268
BF Status Flag ................................................................. 187
Block Diagrams
16-bit Byte Select Mode ............................................. 75
16-bit Byte Write Mode .............................................. 73
16-bit Word Write Mode ............................................. 74
A/D ........................................................................... 216
Analog Input Model .................................................. 217
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Watchdog Timer .......................................................251
BN ....................................................................................268
BNC ..................................................................................269
BNN ..................................................................................269
BNOV ...............................................................................270
BNZ ..................................................................................270
BOR. See Brown-out Reset.
BOV ..................................................................................273
BRA ..................................................................................271
BRG. See Baud Rate Generator.
Brown-out Reset (BOR) .....................................................30
BSF ..................................................................................271
BTFSC .............................................................................272
BTFSS ..............................................................................272
BTG ..................................................................................273
BZ .....................................................................................274
Loading the SSPBUF (SSPSR) Register ................. 160
Reading a Flash Program Memory Word .................. 65
Saving Status, WREG and BSR Registers in RAM . 102
Writing to Flash Program Memory ....................... 68–69
Code Protection ............................................................... 239
COMF .............................................................................. 276
Comparator ...................................................................... 223
Analog Input Connection Considerations ................ 227
Associated Registers ............................................... 228
Configuration ........................................................... 224
Effects of a Reset .................................................... 227
Interrupts ................................................................. 226
Operation ................................................................. 225
Operation During Sleep ........................................... 227
Outputs .................................................................... 225
Reference ................................................................ 225
External Signal ................................................ 225
C
Internal Signal .................................................. 225
C Compilers
Response Time ........................................................ 225
Comparator Specifications ............................................... 315
Comparator Voltage Reference ....................................... 229
Accuracy and Error .................................................. 230
Associated Registers ............................................... 231
Configuring .............................................................. 229
Connection Considerations ...................................... 230
Effects of a Reset .................................................... 230
Operation During Sleep ........................................... 230
Compare (CCP Module) .................................................. 152
Associated Registers ............................................... 153
CCP Pin Configuration ............................................. 152
CCPR1 Register ...................................................... 152
Software Interrupt .................................................... 152
Special Event Trigger .............................. 138, 145, 152
Timer1/Timer3 Mode Selection ................................ 152
Compare (CCP2 Module)
MPLAB C18 .............................................................302
CALL ................................................................................274
Capture (CCP Module) .....................................................151
Associated Registers ...............................................153
CCP Pin Configuration .............................................151
CCPR1H:CCPR1L Registers ...................................151
Software Interrupt ....................................................151
Timer1/Timer3 Mode Selection ................................151
Capture/Compare/PWM (CCP) ........................................149
Capture Mode. See Capture.
CCP Mode and Timer Resources ............................150
CCPRxH Register ....................................................150
CCPRxL Register .....................................................150
Compare Mode. See Compare.
Interconnect Configurations .....................................150
Module Configuration ...............................................150
PWM Mode. See PWM.
Special Event Trigger .............................................. 220
Configuration Bits ............................................................ 239
Context Saving During Interrupts ..................................... 102
Control Registers
Capture/Compare/PWM Requirements (All CCP Modules) ...
327
CLKO and I/O Timing Requirements ....................... 322, 323
Clocking Scheme/Instruction Cycle ....................................44
CLRF ................................................................................275
CLRWDT ..........................................................................275
Code Examples
EECON1 and EECON2 ............................................. 62
TABLAT (Table Latch) Register ................................. 64
TBLPTR (Table Pointer) Register .............................. 64
Conversion Considerations .............................................. 362
CPFSEQ .......................................................................... 276
CPFSGT .......................................................................... 277
CPFSLT ........................................................................... 277
Customer Change Notification Service ............................ 375
Customer Notification Service ......................................... 375
Customer Support ............................................................ 375
16 x 16 Signed Multiply Routine ................................86
16 x 16 Unsigned Multiply Routine ............................86
8 x 8 Signed Multiply Routine ....................................85
8 x 8 Unsigned Multiply Routine ................................85
Changing Between Capture Prescalers ...................151
Data EEPROM Read .................................................81
Data EEPROM Refresh Routine ................................82
Data EEPROM Write .................................................81
Erasing a Flash Program Memory Row .....................66
Fast Register Stack ....................................................44
How to Clear RAM (Bank 1) Using Indirect Addressing .
57
Implementing a Real-Time Clock using a Timer1 Inter-
rupt Service ......................................................139
Initializing PORTA ....................................................103
Initializing PORTB ....................................................106
Initializing PORTC ....................................................109
Initializing PORTD ....................................................111
Initializing PORTE ....................................................114
Initializing PORTF ....................................................117
Initializing PORTG ...................................................120
Initializing PORTH ....................................................122
Initializing PORTJ ....................................................125
D
Data EEPROM Memory
Associated Registers ................................................. 83
EEADR Register ........................................................ 79
EEADRH Register ..................................................... 79
EECON1 Register ...................................................... 79
EECON2 Register ...................................................... 79
Operation During Code-Protect ................................. 82
Protection Against Spurious Write ............................. 82
Reading ..................................................................... 81
Using ......................................................................... 82
Write Verify ................................................................ 82
Writing ....................................................................... 81
Data Memory ..................................................................... 47
General Purpose Registers ....................................... 47
Map for PIC18FX520 Devices ................................... 48
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Map for PIC18FX620/X720 Devices .......................... 49
Operation ................................................................... 85
Performance Comparison .......................................... 85
HS/PLL .............................................................................. 23
Special Function Registers ........................................ 47
DAW ................................................................................. 278
DC and AC Characteristics
Graphs and Tables .................................................. 341
DC Characteristics
PIC18FXX20 (Industrial and Extended), PIC18LFXX20
(Industrial) ........................................................ 313
Power-Down and Supply Current ............................ 309
Supply Voltage ......................................................... 308
DCFSNZ .......................................................................... 279
DECF ............................................................................... 278
DECFSZ ........................................................................... 279
Development Support ...................................................... 301
Device Differences ........................................................... 361
Direct Addressing ............................................................... 58
Direct Addressing ....................................................... 56
I
I/O Ports .......................................................................... 103
2
I C Bus Data Requirements (Slave Mode) ...................... 334
2
I C Bus Start/Stop Bits Requirements (Slave Mode) ....... 333
2
I C Mode
General Call Address Support ................................. 180
Master Mode
Operation ......................................................... 182
Read/Write Bit Information (R/W Bit) ............... 170, 171
Serial Clock (RC3/SCK/SCL) .................................. 171
ID Locations ............................................................. 239, 257
INCF ................................................................................ 280
INCFSZ ............................................................................ 281
In-Circuit Debugger .......................................................... 257
Resources (Table) ................................................... 257
In-Circuit Serial Programming (ICSP) ...................... 239, 257
Indirect Addressing ............................................................ 58
INDF and FSR Registers ........................................... 57
Operation ................................................................... 57
Indirect Addressing Operation ........................................... 58
Indirect File Operand ......................................................... 47
INFSNZ ............................................................................ 281
Instruction Cycle ................................................................ 44
Instruction Flow/Pipelining ................................................. 45
Instruction Format ............................................................ 261
Instruction Set .................................................................. 259
ADDLW .................................................................... 265
ADDWF ................................................................... 265
ADDWFC ................................................................. 266
ANDLW .................................................................... 266
ANDWF ................................................................... 267
BC ............................................................................ 267
BCF ......................................................................... 268
BN ............................................................................ 268
BNC ......................................................................... 269
BNN ......................................................................... 269
BNOV ...................................................................... 270
BNZ ......................................................................... 270
BOV ......................................................................... 273
BRA ......................................................................... 271
BSF .......................................................................... 271
BTFSC ..................................................................... 272
BTFSS ..................................................................... 272
BTG ......................................................................... 273
BZ ............................................................................ 274
CALL ........................................................................ 274
CLRF ....................................................................... 275
CLRWDT ................................................................. 275
COMF ...................................................................... 276
CPFSEQ .................................................................. 276
CPFSGT .................................................................. 277
CPFSLT ................................................................... 277
DAW ........................................................................ 278
DCFSNZ .................................................................. 279
DECF ....................................................................... 278
DECFSZ .................................................................. 279
GOTO ...................................................................... 280
INCF ........................................................................ 280
INCFSZ .................................................................... 281
INFSNZ .................................................................... 281
IORLW ..................................................................... 282
IORWF ..................................................................... 282
E
Electrical Characteristics .................................................. 305
Errata ................................................................................... 5
Example SPI Mode Requirements (Master Mode, CKE = 0) .
329
Example SPI Mode Requirements (Master Mode, CKE = 1) .
330
Example SPI Mode Requirements (Slave Mode, CKE = 0) ...
331
Example SPI Slave Mode Requirements (CKE = 1) ........ 332
Extended Microcontroller Mode ......................................... 71
External Clock Timing Requirements ............................... 320
External Memory Interface ................................................. 71
16-bit Byte Select Mode ............................................. 75
16-bit Byte Write Mode .............................................. 73
16-bit Mode ................................................................ 73
16-bit Mode Timing .................................................... 76
16-bit Word Write Mode ............................................. 74
PIC18F8X20 External Bus - I/O Port Functions ......... 72
Program Memory Modes and External Memory Interface
............................................................................ 71
F
Firmware Instructions ....................................................... 259
Flash Program Memory ..................................................... 61
Associated Registers ................................................. 69
Control Registers ....................................................... 62
Erase Sequence ........................................................ 66
Erasing ....................................................................... 66
Operation During Code-Protect ................................. 69
Reading ...................................................................... 65
Table Pointer
Boundaries Based on Operation ........................ 64
Table Pointer Boundaries .......................................... 64
Table Reads and Table Writes .................................. 61
Write Sequence ......................................................... 67
Writing To ................................................................... 67
Protection Against Spurious Writes ................... 69
Unexpected Termination .................................... 69
Write Verify ........................................................ 69
G
General Call Address Support ......................................... 180
GOTO .............................................................................. 280
H
Hardware Multiplier ............................................................ 85
Introduction ................................................................ 85
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LFSR ........................................................................283
MOVF .......................................................................283
MOVFF ....................................................................284
MOVLB ....................................................................284
MOVLW ...................................................................285
MOVWF ...................................................................285
MULLW ....................................................................286
MULWF ....................................................................286
NEGF .......................................................................287
NOP .........................................................................287
POP .........................................................................288
PUSH .......................................................................288
RCALL .....................................................................289
RESET .....................................................................289
RETFIE ....................................................................290
RETLW ....................................................................290
RETURN ..................................................................291
RLCF ........................................................................291
RLNCF .....................................................................292
RRCF .......................................................................292
RRNCF ....................................................................293
SETF ........................................................................293
SLEEP .....................................................................294
SUBFWB ..................................................................294
SUBLW ....................................................................295
SUBWF ....................................................................295
SUBWFB ..................................................................296
SWAPF ....................................................................296
TBLRD .....................................................................297
TBLWT .....................................................................298
TSTFSZ ...................................................................299
XORLW ....................................................................299
XORWF ....................................................................300
Summary Table ........................................................262
INT Interrupt (RB0/INT). See Interrupt Sources
Easy Migration ............................................................. 7
Expanded Memory ....................................................... 7
External Memory Interface ........................................... 7
Other Special Features ................................................ 7
L
LFSR ................................................................................ 283
Low-Voltage Detect ......................................................... 233
Characteristics ......................................................... 316
Converter Characteristics ........................................ 316
Effects of a Reset .................................................... 237
Operation ................................................................. 236
Current Consumption ...................................... 237
During Sleep .................................................... 237
Reference Voltage Set Point ........................... 237
Typical Application ................................................... 233
Low-Voltage ICSP Programming ..................................... 257
LVD. See Low-Voltage Detect. ........................................ 233
M
Master SSP (MSSP) Module
Overview .................................................................. 157
2
Master SSP I C Bus Data Requirements ........................ 336
2
Master SSP I C Bus Start/Stop Bits Requirements ......... 335
Master Synchronous Serial Port (MSSP). See MSSP.
Master Synchronous Serial Port. See MSSP
Memory Organization
Data Memory ............................................................. 47
Memory Programming Requirements .............................. 317
Microchip Internet Web Site ............................................. 375
Microcontroller Mode ......................................................... 71
Microprocessor Mode ........................................................ 71
Microprocessor with Boot Block Mode ............................... 71
Migration from High-End to Enhanced Devices ............... 363
Migration from Mid-Range to Enhanced Devices ............ 362
MOVF .............................................................................. 283
MOVFF ............................................................................ 284
MOVLB ............................................................................ 284
MOVLW ........................................................................... 285
MOVWF ........................................................................... 285
MPLAB ASM30 Assembler, Linker, Librarian .................. 302
MPLAB Integrated Development Environment Software . 301
MPLAB PM3 Device Programmer ................................... 304
MPLAB REAL ICE In-Circuit Emulator System ............... 303
MPLINK Object Linker/MPLIB Object Librarian ............... 302
MSSP ............................................................................... 157
ACK Pulse ....................................................... 170, 171
Clock Stretching ....................................................... 176
10-bit Slave Receive Mode (SEN = 1) ............. 176
INTCON Registers .............................................................89
2
Inter-Integrated Circuit. See I C
Internet Address ...............................................................375
Interrupt Sources ..............................................................239
A/D Conversion Complete .......................................217
Capture Complete (CCP) .........................................151
Compare Complete (CCP) .......................................152
INT0 .........................................................................102
Interrupt-on-Change (RB7:RB4) ..............................106
PORTB, Interrupt-on-Change ..................................102
RB0/INT Pin, External ..............................................102
TMR0 .......................................................................102
TMR0 Overflow ........................................................133
TMR1 Overflow ................................................ 135, 138
TMR2 to PR2 Match ................................................142
TMR2 to PR2 Match (PWM) ............................ 141, 154
TMR3 Overflow ................................................ 143, 145
TMR4 to PR4 Match ................................................148
TMR4 to PR4 Match (PWM) ....................................147
Interrupts ............................................................................87
Control Registers .......................................................89
Enable Registers ........................................................95
Flag Registers ............................................................92
Logic ..........................................................................88
Priority Registers ........................................................98
Reset Control Registers ...........................................101
IORLW .............................................................................282
IORWF .............................................................................282
IPR Registers .....................................................................98
10-bit Slave Transmit Mode ............................. 176
7-bit Slave Receive Mode (SEN = 1) ............... 176
7-bit Slave Transmit Mode ............................... 176
Clock Synchronization and the CKP bit ................... 177
Control Registers (general) ...................................... 157
Enabling SPI I/O ...................................................... 161
2
I C Mode ................................................................. 166
Acknowledge Sequence Timing ...................... 190
Baud Rate Generator ...................................... 183
Bus Collision
During a Repeated Start Condition .......... 194
Bus Collision During a Start Condition ............ 192
Bus Collision During a Stop Condition ............. 195
Clock Arbitration .............................................. 184
Effect of a Reset .............................................. 191
2
I C Clock Rate w/BRG .................................... 183
K
Master Mode .................................................... 181
Reception ................................................ 187
Key Features
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Repeated Start Timing ............................. 186
Master Mode Start Condition ........................... 185
Master Mode Transmission ............................. 187
Multi-Master Communication, Bus Collision and Ar-
bitration .................................................... 191
Multi-Master Mode ........................................... 191
Registers .......................................................... 166
Sleep Operation ............................................... 191
RE1/WR/AN6 Pin .................................................... 128
RE2/CS/AN7 Pin ..................................................... 128
Read Waveforms ..................................................... 130
Select (PSPMODE Bit) .................................... 111, 128
Write Waveforms ..................................................... 129
Parallel Slave Port Requirements (PIC18F8X20) ............ 328
PIE Registers ..................................................................... 95
Pin Functions
Stop Condition Timing ..................................... 190
I C Mode. See I C
AVDD .......................................................................... 20
AVSS .......................................................................... 20
MCLR/VPP ................................................................. 11
OSC1/CLKI ................................................................ 11
OSC2/CLKO/RA6 ...................................................... 11
RA0/AN0 .................................................................... 12
RA1/AN1 .................................................................... 12
RA2/AN2/VREF- ......................................................... 12
RA3/AN3/VREF+ ........................................................ 12
RA4/T0CKI ................................................................ 12
RA5/AN4/LVDIN ........................................................ 12
RA6 ............................................................................ 12
RB0/INT0 ................................................................... 13
RB1/INT1 ................................................................... 13
RB2/INT2 ................................................................... 13
RB3/INT3/CCP2 ........................................................ 13
RB4/KBI0 ................................................................... 13
RB5/KBI1/PGM .......................................................... 13
RB6/KBI2/PGC .......................................................... 13
RB7/KBI3/PGD .......................................................... 13
RC0/T1OSO/T13CKI ................................................. 14
RC1/T1OSI/CCP2 ..................................................... 14
RC2/CCP1 ................................................................. 14
RC3/SCK/SCL ........................................................... 14
RC4/SDI/SDA ............................................................ 14
RC5/SDO ................................................................... 14
RC6/TX1/CK1 ............................................................ 14
RC7/RX1/DT1 ............................................................ 14
RD0/PSP0/AD0 ......................................................... 15
RD1/PSP1/AD1 ......................................................... 15
RD2/PSP2/AD2 ......................................................... 15
RD3/PSP3/AD3 ......................................................... 15
RD4/PSP4/AD4 ......................................................... 15
RD5/PSP5/AD5 ......................................................... 15
RD6/PSP6/AD6 ......................................................... 15
RD7/PSP7/AD7 ......................................................... 15
RE0/RD/AD8 ............................................................. 16
RE1/WR/AD9 ............................................................. 16
RE2/CS/AD10 ............................................................ 16
RE3/AD11 .................................................................. 16
RE4/AD12 .................................................................. 16
RE5/AD13 .................................................................. 16
RE6/AD14 .................................................................. 16
RE7/CCP2/AD15 ....................................................... 16
RF0/AN5 .................................................................... 17
RF1/AN6/C2OUT ....................................................... 17
RF2/AN7/C1OUT ....................................................... 17
RF3/AN8 .................................................................... 17
RF4/AN9 .................................................................... 17
RF5/AN10/CVREF ...................................................... 17
RF6/AN11 .................................................................. 17
RF7/SS ...................................................................... 17
RG0/CCP3 ................................................................. 18
RG1/TX2/CK2 ............................................................ 18
RG2/RX2/DT2 ........................................................... 18
RG3/CCP4 ................................................................. 18
RG4/CCP5 ................................................................. 18
RH0/A16 .................................................................... 19
2
2
Module Operation .................................................... 170
Operation ................................................................. 160
Slave Mode .............................................................. 170
Addressing ....................................................... 170
Reception ......................................................... 171
Transmission ................................................... 171
SPI
Master Mode .................................................... 162
SPI Clock ......................................................... 162
SPI Master Mode ..................................................... 162
SPI Mode ................................................................. 157
SPI Mode. See SPI
SPI Slave Mode ....................................................... 163
Select Synchronization .................................... 163
SSPBUF Register .................................................... 162
SSPSR Register ...................................................... 162
Typical Connection .................................................. 161
MSSP Module
SPI Master./Slave Connection ................................. 161
MULLW ............................................................................ 286
MULWF ............................................................................ 286
N
NEGF ............................................................................... 287
NOP ................................................................................. 287
O
Opcode Field Descriptions ............................................... 260
OPTION_REG Register
PSA Bit ..................................................................... 133
T0CS Bit ................................................................... 133
T0PS2:T0PS0 Bits ................................................... 133
T0SE Bit ................................................................... 133
Oscillator Configuration ...................................................... 21
EC .............................................................................. 21
ECIO .......................................................................... 21
HS .............................................................................. 21
HS + PLL ................................................................... 21
LP ............................................................................... 21
RC .............................................................................. 21
RCIO .......................................................................... 21
XT .............................................................................. 21
Oscillator Selection .......................................................... 239
Oscillator Switching Feature .............................................. 24
Oscillator Transitions ................................................. 26
System Clock Switch Bit ............................................ 25
Oscillator, Timer1 ............................................. 135, 137, 145
Oscillator, Timer3 ............................................................. 143
Oscillator, WDT ................................................................ 250
P
Packaging Information ..................................................... 355
Details ...................................................................... 356
Marking .................................................................... 355
Parallel Slave Port (PSP) ......................................... 111, 128
Associated Registers ............................................... 130
RE0/RD/AN5 Pin ...................................................... 128
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RH1/A17 ....................................................................19
RH2/A18 ....................................................................19
RH3/A19 ....................................................................19
RH4/AN12 ..................................................................19
RH5/AN13 ..................................................................19
RH6/AN14 ..................................................................19
RH7/AN15 ..................................................................19
RJ0/ALE .....................................................................20
RJ1/OE ......................................................................20
RJ2/WRL ....................................................................20
RJ3/WRH ...................................................................20
RJ4/BA0 .....................................................................20
RJ5/CE .......................................................................20
RJ6/LB .......................................................................20
RJ7/UB .......................................................................20
VDD .............................................................................20
VSS .............................................................................20
PIR Registers .....................................................................92
PLL Clock Timing Specifications ......................................321
PLL Lock Time-out .............................................................30
Pointer, FSR .......................................................................57
POP ..................................................................................288
POR. See Power-on Reset.
PORTF Register ...................................................... 117
TRISF Register ........................................................ 117
PORTG
Associated Registers ............................................... 121
Functions ................................................................. 121
LATG Register ......................................................... 120
PORTG Register ...................................................... 120
TRISG Register ............................................... 120, 197
PORTH
Associated Registers ............................................... 124
Functions ................................................................. 124
LATH Register ......................................................... 122
PORTH Register ...................................................... 122
TRISH Register ........................................................ 122
PORTJ
Associated Registers ............................................... 127
Functions ................................................................. 127
LATJ Register .......................................................... 125
PORTJ Register ....................................................... 125
TRISJ Register ........................................................ 125
Postscaler, WDT
Assignment (PSA Bit) .............................................. 133
Rate Select (T0PS2:T0PS0 Bits) ............................. 133
Switching Between Timer0 and WDT ...................... 133
Power-down Mode. See Sleep.
PORTA
Associated Registers ...............................................105
Functions .................................................................105
LATA Register ..........................................................103
PORTA Register ......................................................103
TRISA Register ........................................................103
PORTB
Associated Registers ...............................................108
Functions .................................................................108
LATB Register ..........................................................106
PORTB Register ......................................................106
RB0/INT Pin, External ..............................................102
TRISB Register ........................................................106
PORTC
Power-on Reset (POR) ...................................................... 30
Oscillator Start-up Timer (OST) ................................. 30
Power-up Timer (PWRT) ........................................... 30
Time-out Sequence ................................................... 30
Prescaler, Capture ........................................................... 151
Prescaler, Timer0 ............................................................ 133
Assignment (PSA Bit) .............................................. 133
Rate Select (T0PS2:T0PS0 Bits) ............................. 133
Switching Between Timer0 and WDT ...................... 133
Prescaler, Timer2 ............................................................ 154
Product Identification System .......................................... 377
Program Counter
Associated Registers ...............................................110
Functions .................................................................110
LATC Register .........................................................109
PORTC Register ......................................................109
RC3/SCK/SCL Pin ...................................................171
TRISC Register ................................................ 109, 197
PORTD .............................................................................128
Associated Registers ...............................................113
Functions .................................................................113
LATD Register .........................................................111
Parallel Slave Port (PSP) Function ..........................111
PORTD Register ......................................................111
TRISD Register ........................................................111
PORTE
Analog Port Pins ......................................................128
Associated Registers ...............................................116
Functions .................................................................116
LATE Register ..........................................................114
PORTE Register ......................................................114
PSP Mode Select (PSPMODE Bit) ..................111, 128
RE0/RD/AN5 Pin ......................................................128
RE1/WR/AN6 Pin .....................................................128
RE2/CS/AN7 Pin ......................................................128
TRISE Register ........................................................114
PORTF
PCL, PCLATH and PCLATU Registers ..................... 44
Program Memory ............................................................... 39
Access for PIC18F8X20 Program Memory Modes .... 40
Instructions ................................................................ 45
Interrupt Vector .......................................................... 39
Map and Stack for PIC18FXX20 ................................ 40
Maps for PIC18F8X20 Program Memory Modes ....... 41
PIC18F8X20 Modes .................................................. 39
Reset Vector .............................................................. 39
Program Memory Write Timing Requirements ................ 324
Program Verification and Code Protection ...................... 253
Associated Registers ............................................... 253
Configuration Register Protection ............................ 257
Data EEPROM Code Protection .............................. 257
Memory Code Protection ......................................... 255
Programming, Device Instructions ................................... 259
PSP.See Parallel Slave Port.
Pulse Width Modulation. See PWM (CCP Module).
PUSH ............................................................................... 288
PWM (CCP Module) ........................................................ 154
Associated Registers ............................................... 155
CCPR1H:CCPR1L Registers ................................... 154
Duty Cycle ............................................................... 154
Example Frequencies/Resolutions .......................... 155
Period ...................................................................... 154
Setup for PWM Operation ........................................ 155
TMR2 to PR2 Match ........................................ 141, 154
TMR4 to PR4 Match ................................................ 147
Associated Registers ...............................................119
Functions .................................................................119
LATF Register ..........................................................117
DS39609C-page 370
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
Brown-out Reset (BOR) ........................................... 239
MCLR Reset .............................................................. 29
Q
Q Clock ............................................................................ 154
MCLR Reset during Sleep ......................................... 29
Oscillator Start-up Timer (OST) ............................... 239
Power-on Reset (POR) ...................................... 29, 239
Power-up Timer (PWRT) ......................................... 239
Programmable Brown-out Reset (PBOR) .................. 29
Reset Instruction ........................................................ 29
Stack Full Reset ........................................................ 29
Stack Underflow Reset .............................................. 29
Watchdog Timer (WDT) Reset .................................. 29
Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up
Timer and Brown-out Reset Requirements ............. 325
RETFIE ............................................................................ 290
RETLW ............................................................................ 290
RETURN .......................................................................... 291
Return Address Stack
R
RAM. See Data Memory
RC Oscillator ...................................................................... 22
RCALL ............................................................................. 289
RCON Registers .............................................................. 101
RCSTA Register
SPEN Bit .................................................................. 197
Reader Response ............................................................ 376
Register File ....................................................................... 47
Registers
ADCON0 (A/D Control 0) ......................................... 213
ADCON1 (A/D Control 1) ......................................... 214
ADCON2 (A/D Control 2) ......................................... 215
CCPxCON (Capture/Compare/PWM Control) ......... 149
CMCON (Comparator Control) ................................ 223
CONFIG1H (Configuration 1 High) .......................... 240
CONFIG2H (Configuration 2 High) .......................... 241
CONFIG2L (Configuration 2 Low) ............................ 241
CONFIG3H (Configuration 3 High) .......................... 242
CONFIG3L (Configuration 3 Low) ............................ 242
CONFIG3L (Configuration Byte) ................................ 41
CONFIG4L (Configuration 4 Low) ............................ 243
CONFIG5H (Configuration 5 High) .......................... 245
CONFIG5L (Configuration 5 Low) ............................ 244
CONFIG6H (Configuration 6 High) .......................... 247
CONFIG6L (Configuration 6 Low) ............................ 246
CONFIG7H (Configuration 7 High) .......................... 249
CONFIG7L (Configuration 7 Low) ............................ 248
CVRCON (Comparator Voltage Reference Control) 229
Device ID 1 .............................................................. 249
Device ID 2 .............................................................. 249
EECON1 (Data EEPROM Control 1) ................... 63, 80
INTCON (Interrupt Control) ........................................ 89
INTCON2 (Interrupt Control 2) ................................... 90
INTCON3 (Interrupt Control 3) ................................... 91
IPR1 (Peripheral Interrupt Priority 1) .......................... 98
IPR2 (Peripheral Interrupt Priority 2) .......................... 99
IPR3 (Peripheral Interrupt Priority 3) ........................ 100
LVDCON (Low-Voltage Detect Control) ................... 235
MEMCON (Memory Control) ...................................... 71
OSCCON ................................................................... 25
PIE1 (Peripheral Interrupt Enable 1) .......................... 95
PIE2 (Peripheral Interrupt Enable 2) .......................... 96
PIE3 (Peripheral Interrupt Enable 3) .......................... 97
PIR1 (Peripheral Interrupt Request 1) ....................... 92
PIR2 (Peripheral Interrupt Request 2) ....................... 93
PIR3 (Peripheral Interrupt Request 3) ....................... 94
PSPCON (Parallel Slave Port Control) Register ...... 129
RCON ........................................................................ 31
RCON (Reset Control) ....................................... 60, 101
RCSTAx (Receive Status and Control) .................... 199
and Associated Registers .......................................... 43
Revision History ............................................................... 361
RLCF ............................................................................... 291
RLNCF ............................................................................. 292
RRCF ............................................................................... 292
RRNCF ............................................................................ 293
S
SCI. See USART
SCK ................................................................................. 157
SDI ................................................................................... 157
SDO ................................................................................. 157
Serial Clock, SCK ............................................................ 157
Serial Communication Interface. See USART.
Serial Data In, SDI ........................................................... 157
Serial Data Out, SDO ...................................................... 157
Serial Peripheral Interface. See SPI
SETF ............................................................................... 293
Slave Select, SS .............................................................. 157
SLEEP ............................................................................. 294
Sleep ....................................................................... 239, 252
Software Simulator (MPLAB SIM) ................................... 303
Special Event Trigger. See Compare
Special Features of the CPU ........................................... 239
Configuration Registers ................................... 240–249
Special Function Registers ................................................ 47
Map ............................................................................ 50
SPI
Serial Clock ............................................................. 157
Serial Data In ........................................................... 157
Serial Data Out ........................................................ 157
Slave Select ............................................................. 157
SPI Mode ................................................................. 157
SPI Master/Slave Connection .......................................... 161
SPI Module
Associated Registers ............................................... 165
Bus Mode Compatibility ........................................... 165
Effects of a Reset .................................................... 165
Master/Slave Connection ........................................ 161
Slave Mode .............................................................. 163
Sleep Operation ....................................................... 165
SS .................................................................................... 157
SSP
2
SSPCON2 (MSSP Control 2, I C Mode) ................. 169
2
SSPSTAT (MSSP Status, I C Mode) ....................... 167
SSPSTAT (MSSP Status, SPI Mode) ...................... 158
Statis .......................................................................... 59
STKPTR (Stack Pointer) ............................................ 43
Summary .............................................................. 52–55
T1CON (Timer 1 Control) ......................................... 135
T3CON (Timer3 Control) .......................................... 143
TXSTAx (Transmit Status and Control) ................... 198
WDTCON (Watchdog Timer Control) ...................... 250
RESET ............................................................................. 289
Reset .......................................................................... 29, 239
TMR2 Output for Clock Shift ............................ 141, 142
TMR4 Output for Clock Shift .................................... 148
SSPOV Status Flag ......................................................... 187
SSPSTAT Register
R/W Bit ............................................................ 170, 171
Status Bits
Significance and Initialization Condition for RCON Reg-
2003-2013 Microchip Technology Inc.
DS39609C-page 371
PIC18F6520/8520/6620/8620/6720/8720
ister ....................................................................31
SUBFWB ..........................................................................294
SUBLW ............................................................................295
SUBWF ............................................................................295
SUBWFB ..........................................................................296
SWAPF ............................................................................296
Bus Collision During a Repeated Start Condition (Case
2) ..................................................................... 194
Bus Collision During a Stop Condition (Case 1) ...... 195
Bus Collision During a Stop Condition (Case 2) ...... 195
Bus Collision During Start Condition (SCL = 0) ....... 193
Bus Collision During Start Condition (SDA only) ..... 192
Bus Collision for Transmit and Acknowledge .......... 191
Capture/Compare/PWM (All CCP Modules) ............ 326
CLKO and I/O .......................................................... 321
Clock Synchronization ............................................. 177
Clock/Instruction Cycle .............................................. 44
Example SPI Master Mode (CKE = 0) ..................... 328
Example SPI Master Mode (CKE = 1) ..................... 329
Example SPI Slave Mode (CKE = 0) ....................... 330
Example SPI Slave Mode (CKE = 1) ....................... 331
External Clock (All Modes except PLL) ................... 320
External Memory Bus for Sleep (Microprocessor Mode)
77
T
Table Pointer Operations (table) ........................................64
TBLRD .............................................................................297
TBLWT .............................................................................298
Time-out in Various Situations ...........................................31
Timer0 ..............................................................................131
16-bit Mode Timer Reads and Writes ......................133
Associated Registers ...............................................133
Clock Source Edge Select (T0SE Bit) ......................133
Clock Source Select (T0CS Bit) ...............................133
Operation .................................................................133
Overflow Interrupt ....................................................133
Prescaler. See Prescaler, Timer0
Timer0 and Timer1 External Clock Requirements ...........326
Timer1 ..............................................................................135
16-bit Read/Write Mode ...........................................138
Associated Registers ...............................................139
Operation .................................................................136
Oscillator .......................................................... 135, 137
Overflow Interrupt ............................................ 135, 138
Special Event Trigger (CCP) ............................ 138, 152
TMR1H Register ......................................................135
TMR1L Register .......................................................135
Use as a Real-Time Clock .......................................138
Timer2 ..............................................................................141
Associated Registers ...............................................142
Operation .................................................................141
Postscaler. See Postscaler, Timer2
External Memory Bus for TBLRD (Extended Microcon-
troller Mode) ...................................................... 76
External Memory Bus for TBLRD (Microprocessor Mode)
............................................................................ 76
2
I C Bus Data ............................................................ 333
2
I C Bus Start/Stop Bits ............................................ 332
2
I C Master Mode (7 or 10-bit Transmission) ............ 188
2
I C Master Mode (7-bit Reception) .......................... 189
2
I C Master Mode First Start Bit Timing .................... 185
2
I C Slave Mode (10-bit Reception, SEN = 0) .......... 174
2
I C Slave Mode (10-bit Reception, SEN = 1) .......... 179
2
I C Slave Mode (10-bit Transmission) ..................... 175
2
I C Slave Mode (7-bit Reception, SEN = 0) ............ 172
2
I C Slave Mode (7-bit Reception, SEN = 1) ............ 178
2
I C Slave Mode (7-bit Transmission) ....................... 173
Low-Voltage Detect ................................................. 236
2
Master SSP I C Bus Data ........................................ 335
2
PR2 Register .................................................... 141, 154
Prescaler. See Prescaler, Timer2
Master SSP I C Bus Start/Stop Bits ........................ 335
Parallel Slave Port (PIC18F8X20) ........................... 327
Program Memory Read ........................................... 322
Program Memory Write ............................................ 323
PWM Output ............................................................ 154
Repeat Start Condition ............................................ 186
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) ............... 324
Slave Mode General Call Address Sequence (7 or 10-bit
Address Mode) ................................................ 180
Slave Synchronization ............................................. 163
Slow Rise Time (MCLR Tied to VDD via 1 kOhm Resistor)
............................................................................ 38
SPI Mode (Master Mode) ......................................... 162
SPI Mode (Slave Mode with CKE = 0) ..................... 164
SPI Mode (Slave Mode with CKE = 1) ..................... 164
Stop Condition Receive or Transmit Mode .............. 190
Synchronous Reception (Master Mode, SREN) ...... 210
Synchronous Transmission ..................................... 209
Synchronous Transmission (Through TXEN) .......... 209
Time-out Sequence on POR w/PLL Enabled (MCLR Tied
to VDD via 1 kOhm Resistor) ............................. 38
Time-out Sequence on Power-up (MCLR Not Tied to
VDD)
SSP Clock Shift ................................................ 141, 142
TMR2 Register .........................................................141
TMR2 to PR2 Match Interrupt ..................141, 142, 154
Timer3 ..............................................................................143
Associated Registers ...............................................145
Operation .................................................................144
Oscillator .......................................................... 143, 145
Overflow Interrupt ............................................ 143, 145
Special Event Trigger (CCP) ....................................145
TMR3H Register ......................................................143
TMR3L Register .......................................................143
Timer4 ..............................................................................147
Associated Registers ...............................................148
Operation .................................................................147
Postscaler. See Postscaler, Timer4
PR4 Register ............................................................147
Prescaler. See Prescaler, Timer4
SSP Clock Shift ........................................................148
TMR4 Register .........................................................147
TMR4 to PR4 Match Interrupt .......................... 147, 148
Timing Diagrams
A/D Conversion ........................................................338
Acknowledge Sequence ..........................................190
Baud Rate Generator with Clock Arbitration ............184
BRG Reset Due to SDA Arbitration During Start Condi-
tion ...................................................................193
Brown-out Reset (BOR) ...........................................325
Bus Collision During a Repeated Start Condition (Case
1) ......................................................................194
Case 1 ............................................................... 37
Case 2 ............................................................... 37
Time-out Sequence on Power-up (MCLR Tied to VDD via
1 kOhm Resistor) ............................................... 37
Timer0 and Timer1 External Clock .......................... 325
Timing for Transition Between Timer1 and OSC1 (HS
DS39609C-page 372
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
with PLL) ............................................................ 27
Transition Between Timer1 and OSC1 (HS, XT, LP) . 26
Transition Between Timer1 and OSC1 (RC, EC) ....... 27
Transition from OSC1 to Timer1 Oscillator ................ 26
USART Asynchronous Reception ............................ 207
USART Asynchronous Transmission ....................... 205
USART Asynchronous Transmission (Back to Back) ....
205
Time-out Period ....................................................... 250
WCOL .............................................................................. 185
WCOL Status Flag ................................... 185, 186, 187, 190
WDT Postscaler ............................................................... 250
WWW Address ................................................................ 375
WWW, On-Line Support ...................................................... 5
X
XORLW ........................................................................... 299
XORWF ........................................................................... 300
USART Synchronous Receive ( Master/Slave) ....... 337
USART SynchronousTransmission (Master/Slave) . 337
Wake-up from Sleep via Interrupt ............................ 253
TRISE Register
PSPMODE Bit .................................................. 111, 128
TSTFSZ ........................................................................... 299
Two-Word Instructions
Example Cases .......................................................... 46
TXSTA Register
BRGH Bit ................................................................. 200
U
Universal Synchronous Asynchronous Receiver Transmitter.
See USART
USART
Asynchronous Mode ................................................ 204
Associated Registers, Receive ........................ 207
Associated Registers, Transmit ....................... 205
Receiver ........................................................... 206
Setting up 9-bit Mode with Address Detect ...... 206
Transmitter ....................................................... 204
Baud Rate Generator (BRG) .................................... 200
Associated Registers ....................................... 200
Baud Rate Error, Calculating ........................... 200
Baud Rate Formula .......................................... 200
Baud Rates for Asynchronous Mode (BRGH = 0) .
202
Baud Rates for Asynchronous Mode (BRGH = 1) .
203
Baud Rates for Synchronous Mode ................. 201
High Baud Rate Select (BRGH Bit) ................. 200
Sampling .......................................................... 200
Serial Port Enable (SPEN Bit) .................................. 197
Synchronous Master Mode ...................................... 208
Associated Registers, Reception ..................... 210
Associated Registers, Transmit ....................... 208
Reception ......................................................... 210
Transmission ................................................... 208
Synchronous Slave Mode ........................................ 211
Associated Registers, Receive ........................ 212
Associated Registers, Transmit ....................... 211
Reception ......................................................... 212
Transmission ................................................... 211
USART Synchronous Receive Requirements ................. 337
USART Synchronous Transmission Requirements ......... 337
V
Voltage Reference Specifications .................................... 315
W
Wake-up from Sleep ................................................ 239, 252
Using Interrupts ........................................................ 252
Watchdog Timer (WDT) ........................................... 239, 250
Associated Registers ............................................... 251
Control Register ....................................................... 250
Postscaler ................................................................ 251
Programming Considerations .................................. 250
RC Oscillator ............................................................ 250
2003-2013 Microchip Technology Inc.
DS39609C-page 373
PIC18F6520/8520/6620/8620/6720/8720
DS39609C-page 374
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2003-2013 Microchip Technology Inc.
DS39609C-page 375
PIC18F6520/8520/6620/8620/6720/8720
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
RE:
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Reader Response
Total Pages Sent ________
From:
Name
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Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Literature Number: DS39609C
Application (optional):
Would you like a reply?
Y
N
Device: PIC18F6520/8520/6620/8620/6720/8720
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39609C-page 376
2003-2013 Microchip Technology Inc.
PIC18F6520/8520/6620/8620/6720/8720
PIC18F6520/8520/6620/8620/6720/8720 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
/XX
XXX
PART NO.
Device
Examples:
Temperature Package
Range
Pattern
a) PIC18LF6620-I/PT 301 = Industrial temp.,
TQFP package, Extended VDD limits,
QTP pattern #301.
b) PIC18F8720-I/PT = Industrial temp.,
TQFP package, normal VDD limits.
c) PIC18F8620-E/PT = Extended temp.,
TQFP package, standard VDD limits.
(1)
Device
PIC18F6520/8520/6620/8620/6720/8720
PIC18F6520/8520/6620/8620/6720/8720T
VDD range 4.2V to 5.5V
,
(2)
;
(1)
PIC18LF6520/8520/6620/8620/6720/8720
PIC18LF6520/8520/6620/8620/6720/8720T
VDD range 2.0V to 5.5V
,
(2)
;
Temperature
Range
I
E
=
=
-40C to +85C (Industrial)
-40C to +125C (Extended)
Note 1: F
LF = Extended Voltage Range
2: T in tape and reel
= Standard Voltage Range
Package
Pattern
PT
=
TQFP (Thin Quad Flatpack)
=
QTP, SQTP, Code or Special Requirements
(blank otherwise)
2003-2013 Microchip Technology Inc.
DS39609C-page 377
PIC18F6520/8520/6620/8620/6720/8720
NOTES:
DS39609C-page 378
2003-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
32
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2003-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769423
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2003-2013 Microchip Technology Inc.
DS39609C-page 379
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Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Korea - Seoul
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Los Angeles
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Fax: 886-7-330-9305
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
China - Xiamen
Tel: 905-673-0699
Fax: 905-673-6509
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
11/29/12
DS39609C-page 380
2003-2013 Microchip Technology Inc.
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