PIC18F6628 [MICROCHIP]
64/80-Pin, 1-Mbit,Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology;
| 型号： | PIC18F6628 |
| 厂家： | 
MICROCHIP |
| 描述： | 64/80-Pin, 1-Mbit,Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology 微控制器 |
| 文件： | 总60页 (文件大小：1129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18F8723 Family
Data Sheet
64/80-Pin, 1-Mbit,
Enhanced Flash Microcontrollers
with 12-Bit A/D and nanoWatt Technology
© 2007 Microchip Technology Inc.
Preliminary
DS39894A
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
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intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS39894A-page ii
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
64/80-Pin, 1-Mbit, Enhanced Flash Microcontrollers
with 12-Bit A/D and nanoWatt Technology
Peripheral Highlights:
Power-Managed Modes:
• 12-Bit, Up to 16-Channel Analog-to-Digital
Converter module (A/D):
• Run: CPU on, Peripherals on
• Idle: CPU off, Peripherals on
- Auto-acquisition capability
• Sleep: CPU off, Peripherals off
• Idle mode Currents Down to 15 μA Typical
• Sleep Current Down to 0.2 μA Typical
• Timer1 Oscillator: 1.8 μA, 32 kHz, 2V
• Watchdog Timer: 2.1 μA
- Conversion available during Sleep
• Two Master Synchronous Serial Port (MSSP)
modules supporting 2/3/4-Wire SPI (all four
modes) and I2C™ Master and Slave modes
• Two Capture/Compare/PWM (CCP) modules
• Three Enhanced Capture/Compare/PWM (ECCP)
modules:
Special Microcontroller Features:
• C Compiler Optimized Architecture:
- One, two or four PWM outputs
- Selectable polarity
- Optional extended instruction set designed to
optimize re-entrant code
- Programmable dead time
• 100,000 Erase/Write Cycle Enhanced Flash
Program Memory Typical
• 1,000,000 Erase/Write Cycle Data EEPROM
Memory Typical
• Flash/Data EEPROM Retention: 100 Years Typical
• Self-Programmable under Software Control
• Priority Levels for Interrupts
- Auto-shutdown and auto-restart
• Two Enhanced Addressable USART modules:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-wake-up on Start bit
- Auto-Baud Detect
• Dual Analog Comparators with Input Multiplexing
• High-Current Sink/Source 25 mA/25 mA
• Four Programmable External Interrupts
• Four Input Change Interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming™
(ICSP™) via Two Pins
• In-Circuit Debug (ICD) via Two Pins
• Wide Operating Voltage Range: 2.0V to 5.5V
• Fail-Safe Clock Monitor
External Memory Interface:
• Address Capability of Up to 2 Mbytes
• 8-Bit or 16-Bit Interface
• 8, 12, 16 and 20-Bit Address modes
• Two-Speed Oscillator Start-up
• nanoWatt Technology
Note:
This document is supplemented by the
“PIC18F8722 Family Data Sheet”
(DS39646). See Section 1.0 “Device
Overview”.
Program Memory
Data Memory
MSSP
CCP/
ECCP
(PWM)
12-Bit
A/D (ch)
Device
I/O
Flash # Single-Word SRAM EEPROM
(bytes) Instructions (bytes) (bytes)
Master
SPI
2
I C™
PIC18F6628 96K
PIC18F6723 128K
PIC18F8628 96K
PIC18F8723 128K
49152
65536
49152
65536
3936
3936
3936
3936
1024
1024
1024
1024
54
54
70
70
12
12
16
16
2/3
2/3
2/3
2/3
2
2
2
2
Y
Y
Y
Y
Y
Y
Y
Y
2
2
2
2
2
2
2
2
2/3
2/3
2/3
2/3
N
N
Y
Y
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 1
PIC18F8723
Pin Diagrams
64-Pin TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RB0/INT0
RE1/WR/P2C
RE0/RD/P2D
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG5/MCLR/VPP
RG4/CCP5/P1D
VSS
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RB1/INT1
2
RB2/INT2
3
RB3/INT3
4
RB4/KBI0
5
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
6
7
PIC18F6628
PIC18F6723
8
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
9
VDD
10
11
12
13
14
15
16
RF7/SS1
RF6/AN11
RB7/KBI3/PGD
RC5/SDO1
RF5/AN10/CVREF
RF4/AN9
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
RF3/AN8
RF2/AN7/C1OUT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit.
DS39894A-page 2
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723
Pin Diagrams (Continued)
80-Pin TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
RH2/A18
RH3/A19
RJ2/WRL
RJ3/WRH
RB0/INT0
RB1/INT1
1
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RE1/AD9/WR/P2C
RE0/AD8/RD/P2D
RG0/ECCP3/P3A
RG1/TX2/CK2
RG2/RX2/DT2
RG3/CCP4/P3D
RG5/MCLR/VPP
RG4/CCP5/P1D
VSS
3
4
RB2/INT2
RB3/INT3/ECCP2(1)/P2A(1)
5
6
RB4/KBI0
7
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
8
9
PIC18F8628
PIC18F8723
10
11
12
13
14
15
16
17
18
19
20
OSC2/CLKO/RA6
OSC1/CLKI/RA7
VDD
VDD
RF7/SS1
RB7/KBI3/PGD
RC5/SDO1
RF6/AN11
RF5/AN10/CVREF
RF4/AN9
RC4/SDI1/SDA1
RC3/SCK1/SCL1
RC2/ECCP1/P1A
RJ7/UB
RF3/AN8
RF2/AN7/C1OUT
RH7/AN15/P1B(2)
RH6/AN14/P1C(2)
RJ6/LB
40
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit and Processor mode settings.
2: P1B, P1C, P3B and P3C pin placement is determined by the ECCPMX Configuration bit.
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 3
PIC18F8723
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 29
3.0 Special Features of the CPU...................................................................................................................................................... 39
4.0 Electrical Characteristics ........................................................................................................................................................... 41
5.0 Packaging Information................................................................................................................................................................ 47
Appendix A: Revision History............................................................................................................................................................... 49
Appendix B: Device Differences........................................................................................................................................................... 49
Appendix C: Conversion Considerations ............................................................................................................................................. 50
Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................... 50
Appendix E: Migration From Mid-Range to Enhanced Devices........................................................................................................... 51
Appendix F: Migration From High-End to Enhanced Devices.............................................................................................................. 51
Index .................................................................................................................................................................................................... 53
The Microchip Web Site....................................................................................................................................................................... 55
Customer Change Notification Service ................................................................................................................................................ 55
Customer Support................................................................................................................................................................................ 55
Reader Response ................................................................................................................................................................................ 56
PIC18F8723 Family Product Identification System.............................................................................................................................. 57
DS39894A-page 4
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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welcome your feedback.
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To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 5
PIC18F8723
NOTES:
DS39894A-page 6
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
1.2
Details on Individual Family
Members
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
Devices in the PIC18F8723 family are available in
64-pin and 80-pin packages. Block diagrams for the
two groups are shown in Figure 1-1 and Figure 1-2.
• PIC18F6628
• PIC18F6723
• PIC18F8628
• PIC18F8723
• PIC18LF6628
• PIC18LF6723
• PIC18LF8628
• PIC18LF8723
The devices are differentiated from each other in the
following ways:
• Flash program memory (96 Kbytes for
PIC18FX628 devices and 128 Kbytes for
PIC18FX723).
Note: This data sheet documents only the devices’
features and specifications that are in addition
to the features and specifications of the
PIC18F8722 family devices. For information
on the features and specifications shared by
the PIC18F8723 family and PIC18F8722 fam-
ily devices, see the “PIC18F8722 Family Data
Sheet” (DS39646).
• A/D channels (12 for PIC18F6628/6723 devices
and 16 for PIC18F8628/8723 devices).
• I/O ports (seven bidirectional ports on
PIC18F6628/6723 devices and nine bidirectional
ports on PIC18F8628/8723 devices).
• External Memory Bus, configurable for 8 and
16-bit operation
The PIC18F8723 family of devices offers the
advantages of all PIC18 microcontrollers – namely, high
computational performance at an economical price –
with the addition of high-endurance, Enhanced Flash
program memory. In addition to these features, the
PIC18F8723 introduces design enhancements that
make these microcontrollers a logical choice for many
high-performance, power-sensitive applications.
All other features for devices in this family are identical.
These are summarized in Table 1-1.
The pinouts for all devices are listed in Table 1-2 and
Table 1-3.
Like all Microchip PIC18 devices, members of the
PIC18F8723 family are available as both standard and
low-voltage devices. Standard devices with Enhanced
Flash memory, designated with an “F” in the part
number (such as PIC18F6628), accommodate an
operating VDD range of 4.2V to 5.5V. Low-voltage
parts, designated by “LF” (such as PIC18LF6628),
function over an extended VDD range of 2.0V to 5.5V.
1.1
Special Features
• 12-Bit A/D Converter: The PIC18F8723 family
implements a 12-bit A/D Converter. A/D Converters
in both families incorporate programmable acquisi-
tion time. This allows for a channel to be selected
and a conversion to be initiated, without waiting for
a sampling period and thus, reducing code
overhead.
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 7
PIC18F8723 FAMILY
TABLE 1-1:
DEVICE FEATURES
Features
PIC18F6628
PIC18F6723
PIC18F8628
PIC18F8723
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
Data EEPROM Memory (Bytes)
Interrupt Sources
DC – 40 MHz
96K
DC – 40 MHz
128K
DC – 40 MHz
96K
DC – 40 MHz
128K
49152
3936
65536
3936
49152
3936
65536
3936
1024
1024
1024
1024
28
28
29
29
I/O Ports
Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G
Ports A, B, C, D, E,
F, G, H, J
Ports A, B, C, D, E,
F, G, H, J
Timers
5
2
5
2
5
2
5
2
Capture/Compare/PWM
Modules
Enhanced Capture/Compare/
PWM Modules
3
2
3
2
3
2
3
2
Enhanced USART
Serial Communications
MSSP,
MSSP,
MSSP,
MSSP,
Enhanced USART
Enhanced USART
Enhanced USART
Enhanced USART
Parallel Communications (PSP)
12-Bit Analog-to-Digital Module
Resets (and Delays)
Yes
Yes
Yes
Yes
12 Input Channels
12 Input Channels
16 Input Channels
16 Input Channels
POR, BOR,
POR, BOR,
POR, BOR,
POR, BOR,
RESETInstruction,
Stack Full, Stack
RESETInstruction,
Stack Full, Stack
RESETInstruction,
Stack Full, Stack
RESETInstruction,
Stack Full, Stack
Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST), Underflow (PWRT, OST),
MCLR (optional), WDT MCLR (optional), WDT MCLR (optional), WDT MCLR (optional), WDT
Programmable
Yes
Yes
Yes
Yes
High/Low-Voltage Detect
Programmable Brown-out
Reset
Yes
Yes
Yes
Yes
Instruction Set
75 Instructions;
75 Instructions;
75 Instructions;
75 Instructions;
83 with Extended
83 with Extended
83 with Extended
83 with Extended
Instruction Set Enabled Instruction Set Enabled Instruction Set Enabled Instruction Set Enabled
Packages
64-Pin TQFP
64-Pin TQFP
80-Pin TQFP
80-Pin TQFP
DS39894A-page 8
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
FIGURE 1-1:
PIC18F6628/6723 (64-PIN) BLOCK DIAGRAM
Data Bus<8>
Table Pointer<21>
inc/dec logic
21
PORTA
Data Latch
8
RA0:RA7(1)
8
Data Memory
(3.9 Kbytes)
PCLATU PCLATH
Address Latch
20
PCU PCH PCL
Program Counter
12
PORTB
Data Address<12>
RB0:RB7(1)
31 Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
Access
Bank
Program Memory
(48/64/96/128
Kbytes)
12
PORTC
Data Latch
RC0:RC7(1)
inc/dec
logic
8
Table Latch
Address
Decode
ROM Latch
IR
Instruction Bus <16>
PORTD
RD0:RD7(1)
8
State Machine
Control Signals
Instruction
Decode and
Control
PRODH PRODL
8 x 8 Multiply
PORTE
RE0:RE7(1)
3
8
OSC1(3)
Internal
Oscillator
Block
Power-up
Timer
BITOP
8
W
8
8
OSC2(3)
T1OSI
Oscillator
Start-up Timer
PORTF
INTRC
Oscillator
8
8
Power-on
Reset
RF0:RF7(1)
8 MHz
Oscillator
ALU<8>
8
Watchdog
Timer
T1OSO
Precision
Band Gap
Reference
Brown-out
Reset
MCLR(2)
VDD, VSS
Single-Supply
Programming
Fail-Safe
Clock Monitor
PORTG
In-Circuit
Debugger
RG0:RG5(1,2)
ADC
12-Bit
BOR
Timer0
ECCP3
Timer1
Timer2
CCP5
Timer3
Comparators
Timer4
HLVD
CCP4
MSSP1
MSSP2
ECCP1
ECCP2
EUSART1
EUSART2
Note 1: See Table 1-2 for I/O port pin descriptions.
2: RG5 is only available when MCLR functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as
digital I/O. For additional information, refer to Section 2.0 “Oscillator Configurations” of the “PIC18F8722 Family
Data Sheet” (DS39646).
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 9
PIC18F8723 FAMILY
FIGURE 1-2:
PIC18F8628/8723 (80-PIN) BLOCK DIAGRAM
Data Bus<8>
PORTA
Data Latch
Table Pointer<21>
inc/dec logic
8
RA0:RA7(1)
8
Data Memory
(3.9 Kbytes)
PCLATH
PCLATU
Address Latch
21
20
PORTB
PCU PCH PCL
Program Counter
RB0:RB7(1)
12
Data Address<12>
31 Level Stack
STKPTR
4
BSR
12
FSR0
FSR1
FSR2
4
Address Latch
PORTC
Access
Bank
Program Memory
(48/64/96/128
Kbytes)
RC0:RC7(1)
12
Data Latch
inc/dec
logic
8
PORTD
Table Latch
ROM Latch
RD0:RD7(1)
Address
Decode
Instruction Bus <16>
PORTE
IR
RE0:RE7(1)
AD15:AD0, A19:A16
(Multiplexed with PORTD,
PORTE and PORTH)
8
PORTF
PRODH PRODL
8 x 8 Multiply
Instruction
Decode &
Control
State Machine
Control Signals
RF0:RF7(1)
3
8
W
BITOP
8
8
PORTG
8
RG0:RG5(1,2)
OSC1(3)
OSC2(3)
Internal
Power-up
Timer
8
Oscillator
Block
8
Oscillator
Start-up Timer
ALU<8>
8
INTRC
Oscillator
PORTH
Power-on
Reset
T1OSI
RH0:RH7(1)
8 MHz
Oscillator
Watchdog
Timer
T1OSO
Precision
Band Gap
Reference
Brown-out
Reset
Fail-Safe
MCLR(2)
VDD, VSS
Single-Supply
Programming
PORTJ
RJ0:RJ7(1)
In-Circuit
Debugger
Clock Monitor
ADC
12-bit
BOR
HLVD
Timer0
ECCP3
Timer1
Timer2
CCP5
Timer3
Comparators
Timer4
ECCP1
ECCP2
CCP4
MSSP1
MSSP2
EUSART1
EUSART2
Note 1: See Table 1-3 for I/O port pin descriptions.
2: RG5 is only available when MCLR functionality is disabled.
3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as
digital I/O. For additional information, refer to Section 2.0 “Oscillator Configurations” of the “PIC18F8722 Family Data
Sheet” (DS39646).
DS39894A-page 10
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-2:
Pin Name
PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Buffer
Type
Description
Type
TQFP
RG5/MCLR/VPP
RG5
7
Master Clear (input) or programming voltage (input).
Digital input.
I
I
ST
ST
MCLR
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
VPP
P
I
Programming voltage input.
OSC1/CLKI/RA7
OSC1
39
40
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS
otherwise.
ST
CMOS
TTL
CLKI
I
External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
RA7
I/O
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
CLKO
RA6
I/O
TTL
General purpose I/O pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
P
= Input
= Power
O
= Output
I2C™
= I2C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 11
PIC18F8723 FAMILY
TABLE 1-2:
Pin Name
PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
24
23
22
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
21
I/O
TTL
Digital I/O.
AN3
VREF+
I
I
Analog
Analog
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
28
27
I/O
I
ST
ST
Digital I/O.
Timer0 external clock input.
T0CKI
RA5/AN4/HLVDIN
RA5
I/O
TTL
Digital I/O.
AN4
HLVDIN
I
I
Analog
Analog
Analog input 4.
High/Low-Voltage Detect input.
RA6
RA7
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
P
= Input
= Power
O
= Output
I2C™
= I2C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
DS39894A-page 12
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-2:
Pin Name
PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0
RB0
48
I/O
I
I
TTL
ST
ST
Digital I/O.
External interrupt 0.
PWM Fault input for ECCPx.
INT0
FLT0
RB1/INT1
RB1
47
46
45
44
43
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
INT1
RB2/INT2
RB2
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
INT2
RB3/INT3
RB3
I/O
I
TTL
ST
Digital I/O.
External interrupt 3.
INT3
RB4/KBI0
RB4
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
KBI0
RB5/KBI1/PGM
RB5
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
KBI1
PGM
RB6/KBI2/PGC
RB6
42
37
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
P
= Input
= Power
O
= Output
I2C™
= I2C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 13
PIC18F8723 FAMILY
TABLE 1-2:
Pin Name
PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
30
29
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/ECCP2/
P2A
RC1
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
T1OSI
Timer1 oscillator input.
Enhanced Capture 2 input/Compare 2 output/
PWM2 output.
ECCP2(1)
P2A(1)
O
—
ECCP2 PWM output A.
RC2/ECCP1/P1A
RC2
33
I/O
I/O
ST
ST
Digital I/O.
ECCP1
Enhanced Capture 1 input/Compare 1 output/
PWM1 output.
P1A
O
—
ECCP1 PWM output A.
RC3/SCK1/SCL1
RC3
34
35
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
SCK1
SCL1
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI1/SDA1
RC4
I/O
I
I/O
ST
ST
ST
Digital I/O.
SDI1
SDA1
SPI data in.
I2C data I/O.
RC5/SDO1
RC5
36
31
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO1
RC6/TX1/CK1
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX1
CK1
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
RC7/RX1/DT1
RC7
32
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX1
DT1
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
P
= Input
= Power
O
= Output
I2C™
= I2C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
DS39894A-page 14
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-2:
Pin Name
PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTD is a bidirectional I/O port.
RD0/PSP0
RD0
58
55
54
53
52
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP0
RD1/PSP1
RD1
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP1
RD2/PSP2
RD2
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP2
RD3/PSP3
RD3
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port data.
PSP3
RD4/PSP4/SDO2
RD4
I/O
I/O
O
ST
TTL
—
Digital I/O.
Parallel Slave Port data.
SPI data out.
PSP4
SDO2
RD5/PSP5/SDI2/
SDA2
51
50
49
RD5
PSP5
SDI2
SDA2
I/O
I/O
I
ST
TTL
ST
Digital I/O.
Parallel Slave Port data.
SPI data in.
I/O I2C/SMB
I2C™ data I/O.
RD6/PSP6/SCK2/
SCL2
RD6
PSP6
SCK2
SCL2
I/O
I/O
I/O
ST
TTL
ST
Digital I/O.
Parallel Slave Port data.
Synchronous serial clock input/output for SPI mode.
I/O I2C/SMB
Synchronous serial clock input/output for I2C mode.
RD7/PSP7/SS2
RD7
I/O
I/O
I
ST
TTL
TTL
Digital I/O.
Parallel Slave Port data.
SPI slave select input.
PSP7
SS2
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
P
= Input
= Power
O
= Output
I2C™
= I2C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 15
PIC18F8723 FAMILY
TABLE 1-2:
Pin Name
PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTE is a bidirectional I/O port.
RE0/RD/P2D
RE0
2
1
I/O
I
O
ST
TTL
—
Digital I/O.
Read control for Parallel Slave Port.
ECCP2 PWM output D.
RD
P2D
RE1/WR/P2C
RE1
I/O
I
O
ST
TTL
—
Digital I/O.
Write control for Parallel Slave Port.
ECCP2 PWM output C.
WR
P2C
RE2/CS/P2B
RE2
64
I/O
I
O
ST
TTL
—
Digital I/O.
Chip select control for Parallel Slave Port.
ECCP2 PWM output B.
CS
P2B
RE3/P3C
RE3
63
62
61
60
59
I/O
O
ST
—
Digital I/O.
ECCP3 PWM output C.
P3C
RE4/P3B
RE4
I/O
O
ST
—
Digital I/O.
ECCP3 PWM output B.
P3B
RE5/P1C
RE5
I/O
O
ST
—
Digital I/O.
ECCP1 PWM output C.
P1C
RE6/P1B
RE6
I/O
O
ST
—
Digital I/O.
ECCP1 PWM output B.
P1B
RE7/ECCP2/P2A
RE7
I/O
I/O
ST
ST
Digital I/O.
ECCP2(2)
Enhanced Capture 2 input/Compare 2 output/
PWM2 output.
ECCP2 PWM output A.
P2A(2)
O
—
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
P
= Input
= Power
O
= Output
I2C™
= I2C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
DS39894A-page 16
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-2:
Pin Name
PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTF is a bidirectional I/O port.
RF0/AN5
RF0
18
17
I/O
I
ST
Analog
Digital I/O.
Analog input 5.
AN5
RF1/AN6/C2OUT
RF1
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 6.
Comparator 2 output.
AN6
C2OUT
RF2/AN7/C1OUT
RF2
16
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 7.
Comparator 1 output.
AN7
C1OUT
RF3/AN8
RF3
15
14
13
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
AN8
RF4/AN9
RF4
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
AN9
RF5/AN10/CVREF
RF5
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 10.
Comparator reference voltage output.
AN10
CVREF
RF6/AN11
RF6
12
11
I/O
I
ST
Analog
Digital I/O.
Analog input 11.
AN11
RF7/SS1
RF7
I/O
I
ST
TTL
Digital I/O.
SPI slave select input.
SS1
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
P
= Input
= Power
O
= Output
I2C™
= I2C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 17
PIC18F8723 FAMILY
TABLE 1-2:
Pin Name
PIC18F6628/6723 (64-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTG is a bidirectional I/O port.
RG0/ECCP3/P3A
RG0
3
I/O
I/O
ST
ST
Digital I/O.
ECCP3
Enhanced Capture 3 input/Compare 3 output/
PWM3 output.
P3A
O
—
ECCP3 PWM output A.
RG1/TX2/CK2
RG1
4
5
6
8
I/O
O
I/O
ST
—
ST
Digital I/O.
TX2
CK2
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
RG2/RX2/DT2
RG2
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX2
DT2
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
RG3/CCP4/P3D
RG3
I/O
I/O
O
ST
ST
—
Digital I/O.
CCP4
P3D
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM output D.
RG4/CCP5/P1D
RG4
I/O
I/O
O
ST
ST
—
Digital I/O.
CCP5
P1D
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM output D.
RG5
VSS
See RG5/MCLR/VPP pin.
9, 25, 41, 56
P
P
P
P
—
—
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
VDD
10, 26, 38, 57
AVSS
AVDD
20
19
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS = CMOS compatible input or output
Analog = Analog input
I
P
= Input
= Power
O
= Output
I2C™
= I2C/SMBus input buffer
Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.
DS39894A-page 18
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-3:
Pin Name
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS
Pin Number
Pin
Buffer
Type
Description
Type
TQFP
RG5/MCLR/VPP
RG5
9
Master Clear (input) or programming voltage (input).
Digital input.
I
I
ST
ST
MCLR
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
VPP
P
I
Programming voltage input.
OSC1/CLKI/RA7
OSC1
49
50
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS
otherwise.
ST
CMOS
TTL
CLKI
I
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
RA7
I/O
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO, which has 1/4 the
frequency of OSC1 and denotes the
instruction cycle rate.
CLKO
RA6
I/O
TTL
General purpose I/O pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS
Analog
O
= CMOS compatible input or output
= Analog input
I
= Input
= Output
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 19
PIC18F8723 FAMILY
TABLE 1-3:
Pin Name
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
30
29
28
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
27
I/O
TTL
Digital I/O.
AN3
VREF+
I
I
Analog
Analog
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
34
33
I/O
I
ST
ST
Digital I/O.
Timer0 external clock input.
T0CKI
RA5/AN4/HLVDIN
RA5
I/O
TTL
Digital I/O.
AN4
HLVDIN
I
I
Analog
Analog
Analog input 4.
High/Low-Voltage Detect input.
RA6
RA7
See the OSC2/CLKO/RA6 pin.
See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS
Analog
O
= CMOS compatible input or output
= Analog input
= Output
I
= Input
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
DS39894A-page 20
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-3:
Pin Name
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0
RB0
58
I/O
I
I
TTL
ST
ST
Digital I/O.
External interrupt 0.
PWM Fault input for ECCPx.
INT0
FLT0
RB1/INT1
RB1
57
56
55
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
INT1
RB2/INT2
RB2
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
INT2
RB3/INT3/ECCP2/P2A
RB3
I/O
I
O
TTL
ST
—
Digital I/O.
External interrupt 3.
Enhanced Capture 2 input/Compare 2 output/
PWM2 output.
ECCP2 PWM output A.
INT3
ECCP2(1)
P2A(1)
O
—
RB4/KBI0
RB4
54
53
I/O
I
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
KBI0
RB5/KBI1/PGM
RB5
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP™ Programming enable pin.
KBI1
PGM
RB6/KBI2/PGC
RB6
52
47
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP™ programming clock pin.
KBI2
PGC
RB7/KBI3/PGD
RB7
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
KBI3
PGD
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS
Analog
O
= CMOS compatible input or output
= Analog input
I
= Input
= Output
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 21
PIC18F8723 FAMILY
TABLE 1-3:
Pin Name
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
36
35
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T13CKI
RC1/T1OSI/ECCP2/
P2A
RC1
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
T1OSI
Timer1 oscillator input.
Enhanced Capture 2 input/Compare 2 output/
PWM2 output.
ECCP2(2)
P2A(2)
O
—
ECCP2 PWM output A.
RC2/ECCP1/P1A
RC2
43
I/O
I/O
ST
ST
Digital I/O.
ECCP1
Enhanced Capture 1 input/Compare 1 output/
PWM1 output.
P1A
O
—
ECCP1 PWM output A.
RC3/SCK1/SCL1
RC3
44
45
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
SCK1
SCL1
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
RC4/SDI1/SDA1
RC4
I/O
I
I/O
ST
ST
ST
Digital I/O.
SDI1
SDA1
SPI data in.
I2C data I/O.
RC5/SDO1
RC5
46
37
I/O
O
ST
—
Digital I/O.
SPI data out.
SDO1
RC6/TX1/CK1
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX1
CK1
EUSART1 asynchronous transmit.
EUSART1 synchronous clock (see related RX1/DT1).
RC7/RX1/DT1
RC7
38
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX1
DT1
EUSART1 asynchronous receive.
EUSART1 synchronous data (see related TX1/CK1).
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS
Analog
O
= CMOS compatible input or output
= Analog input
I
= Input
= Output
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
DS39894A-page 22
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-3:
Pin Name
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTD is a bidirectional I/O port.
RD0/AD0/PSP0
RD0
72
69
68
67
66
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 0.
Parallel Slave Port data.
AD0
PSP0
RD1/AD1/PSP1
RD1
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 1.
Parallel Slave Port data.
AD1
PSP1
RD2/AD2/PSP2
RD2
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 2.
Parallel Slave Port data.
AD2
PSP2
RD3/AD3/PSP3
RD3
I/O
I/O
I/O
ST
TTL
TTL
Digital I/O.
External memory address/data 3.
Parallel Slave Port data.
AD3
PSP3
RD4/AD4/PSP4/SDO2
RD4
AD4
PSP4
SDO2
I/O
I/O
I/O
O
ST
TTL
TTL
—
Digital I/O.
External memory address/data 4.
Parallel Slave Port data.
SPI data out.
RD5/AD5/PSP5/
SDI2/SDA2
RD5
65
64
63
I/O
I/O
I/O
I
ST
TTL
TTL
ST
Digital I/O.
AD5
PSP5
SDI2
SDA2
External memory address/data 5.
Parallel Slave Port data.
SPI data in.
I/O I2C/SMB
I2C™ data I/O.
RD6/AD6/PSP6/
SCK2/SCL2
RD6
I/O
I/O
I/O
I/O
ST
TTL
TTL
ST
Digital I/O.
External memory address/data 6.
Parallel Slave Port data.
AD6
PSP6
SCK2
SCL2
Synchronous serial clock input/output for SPI mode.
I/O I2C/SMB
Synchronous serial clock input/output for I2C mode.
RD7/AD7/PSP7/SS2
RD7
AD7
PSP7
SS2
I/O
I/O
I/O
I
ST
Digital I/O.
TTL
TTL
TTL
External memory address/data 7.
Parallel Slave Port data.
SPI slave select input.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS
Analog
O
= CMOS compatible input or output
= Analog input
I
= Input
= Output
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 23
PIC18F8723 FAMILY
TABLE 1-3:
Pin Name
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTE is a bidirectional I/O port.
RE0/AD8/RD/P2D
4
3
RE0
AD8
RD
I/O
I/O
I
ST
TTL
TTL
—
Digital I/O.
External memory address/data 8.
Read control for Parallel Slave Port.
ECCP2 PWM output D.
P2D
O
RE1/AD9/WR/P2C
RE1
AD9
WR
I/O
I/O
I
ST
TTL
TTL
—
Digital I/O.
External memory address/data 9.
Write control for Parallel Slave Port.
ECCP2 PWM output C.
P2C
O
RE2/AD10/CS/P2B
78
RE2
AD10
CS
I/O
I/O
I
ST
TTL
TTL
—
Digital I/O.
External memory address/data 10.
Chip select control for Parallel Slave Port.
ECCP2 PWM output B.
P2B
O
RE3/AD11/P3C
RE3
77
76
75
74
73
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 11.
ECCP3 PWM output C.
AD11
P3C(4)
RE4/AD12/P3B
RE4
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 12.
ECCP3 PWM output B.
AD12
P3B(4)
RE5/AD13/P1C
RE5
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 13.
ECCP1 PWM output C.
AD13
P1C(4)
RE6/AD14/P1B
RE6
I/O
I/O
O
ST
TTL
—
Digital I/O.
External memory address/data 14.
ECCP1 PWM output B.
AD14
P1B(4)
RE7/AD15/ECCP2/
P2A
RE7
I/O
I/O
I/O
ST
TTL
ST
Digital I/O.
AD15
External memory address/data 15.
Enhanced Capture 2 input/Compare 2 output/
PWM2 output.
ECCP2(3)
P2A(3)
O
—
ECCP2 PWM output A.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS
Analog
O
= CMOS compatible input or output
= Analog input
I
= Input
= Output
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
DS39894A-page 24
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-3:
Pin Name
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTF is a bidirectional I/O port.
RF0/AN5
RF0
24
23
I/O
I
ST
Analog
Digital I/O.
Analog input 5.
AN5
RF1/AN6/C2OUT
RF1
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 6.
Comparator 2 output.
AN6
C2OUT
RF2/AN7/C1OUT
RF2
18
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 7.
Comparator 1 output.
AN7
C1OUT
RF3/AN8
RF3
17
16
15
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
AN8
RF4/AN9
RF4
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
AN9
RF5/AN10/CVREF
RF5
I/O
I
O
ST
Analog
Analog
Digital I/O.
Analog input 10.
Comparator reference voltage output.
AN10
CVREF
RF6/AN11
RF6
14
13
I/O
I
ST
Analog
Digital I/O.
Analog input 11.
AN11
RF7/SS1
RF7
I/O
I
ST
TTL
Digital I/O.
SPI slave select input.
SS1
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS
Analog
O
= CMOS compatible input or output
= Analog input
= Output
I
= Input
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 25
PIC18F8723 FAMILY
TABLE 1-3:
Pin Name
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTG is a bidirectional I/O port.
RG0/ECCP3/P3A
RG0
5
I/O
I/O
ST
ST
Digital I/O.
ECCP3
Enhanced Capture 3 input/Compare 3 output/
PWM3 output.
P3A
O
—
ECCP3 PWM output A.
RG1/TX2/CK2
RG1
6
7
I/O
O
I/O
ST
—
ST
Digital I/O.
TX2
CK2
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
RG2/RX2/DT2
RG2
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX2
DT2
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
RG3/CCP4/P3D
RG3
8
I/O
I/O
O
ST
ST
—
Digital I/O.
CCP4
P3D
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM output D.
RG4/CCP5/P1D
RG4
10
I/O
I/O
O
ST
ST
—
Digital I/O.
CCP5
P1D
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM output D.
RG5
See RG5/MCLR/VPP pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS
Analog
O
= CMOS compatible input or output
= Analog input
I
= Input
= Output
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
DS39894A-page 26
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
TABLE 1-3:
Pin Name
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTH is a bidirectional I/O port.
RH0/A16
RH0
79
80
1
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 16.
A16
RH1/A17
RH1
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 17.
A17
RH2/A18
RH2
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 18.
A18
RH3/A19
RH3
2
I/O
I/O
ST
TTL
Digital I/O.
External memory address/data 19.
A19
RH4/AN12/P3C
RH4
22
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 12.
ECCP3 PWM output C.
AN12
P3C(5)
RH5/AN13/P3B
RH5
21
20
19
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 13.
ECCP3 PWM output B.
AN13
P3B(5)
RH6/AN14/P1C
RH6
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 14.
ECCP1 PWM output C.
AN14
P1C(5)
RH7/AN15/P1B
RH7
I/O
I
O
ST
Analog
—
Digital I/O.
Analog input 15.
ECCP1 PWM output B.
AN15
P1B(5)
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS
Analog
O
= CMOS compatible input or output
= Analog input
= Output
I
= Input
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 27
PIC18F8723 FAMILY
TABLE 1-3:
Pin Name
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
TQFP
Pin
Type
Buffer
Type
Description
PORTJ is a bidirectional I/O port.
RJ0/ALE
RJ0
62
61
60
59
39
40
41
42
I/O
O
ST
—
Digital I/O.
External memory address latch enable.
ALE
RJ1/OE
RJ1
I/O
O
ST
—
Digital I/O.
External memory output enable.
OE
RJ2/WRL
RJ2
I/O
O
ST
—
Digital I/O.
External memory write low control.
WRL
RJ3/WRH
RJ3
I/O
O
ST
—
Digital I/O.
External memory write high control.
WRH
RJ4/BA0
RJ4
I/O
O
ST
—
Digital I/O.
External memory byte address 0 control.
BA0
RJ5/CE
RJ4
I/O
O
ST
—
Digital I/O
External memory chip enable control.
CE
RJ6/LB
RJ6
I/O
O
ST
—
Digital I/O.
External memory low byte control.
LB
RJ7/UB
RJ7
I/O
O
ST
—
Digital I/O.
External memory high byte control.
UB
VSS
11, 31, 51, 70
P
P
P
P
—
—
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
Ground reference for analog modules.
Positive supply for analog modules.
VDD
12, 32, 48, 71
AVSS
AVDD
26
25
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
CMOS
Analog
O
= CMOS compatible input or output
= Analog input
= Output
I
= Input
P
= Power
I2C™/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
DS39894A-page 28
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
The ADCON0 register, shown in Register 2-1, controls
the operation of the A/D module. The ADCON1
register, shown in Register 2-2, configures the
functions of the port pins. The ADCON2 register,
shown in Register 2-3, configures the A/D clock
source, programmed acquisition time and justification.
2.0
12-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has
12 inputs for the 64-pin devices (PIC18F6628/6723) and
16 for the 80-pin devices (PIC18F8628/8723). This
module allows conversion of an analog input signal to a
corresponding 12-bit digital number.
The module has five registers:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Control Register 2 (ADCON2)
REGISTER 2-1:
ADCON0: A/D CONTROL REGISTER 0
U-0
—
U-0
—
R/W-0
CHS3
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-2
Unimplemented: Read as ‘0’
CHS3:CHS0: Analog Channel Select bits
0000= Channel 0 (AN0)
0001= Channel 1 (AN1)
0010= Channel 2 (AN2)
0011= Channel 3 (AN3)
0100= Channel 4 (AN4)
0101= Channel 5 (AN5)
0110= Channel 6 (AN6)
0111= Channel 7 (AN7)
1000= Channel 8 (AN8)
1001= Channel 9 (AN9)
1010= Channel 10 (AN10)
1011= Channel 11 (AN11)
1100= Channel 12 (AN12)(1,2)
1101= Channel 13 (AN13)(1,2)
1110= Channel 14 (AN14)(1,2)
1111= Channel 15 (AN15)(1,2)
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress
0= A/D Idle
ADON: A/D On bit
1= A/D Converter module is enabled
0= A/D Converter module is disabled
Note 1: These channels are not implemented on PIC18F6628/6723 devices.
2: Performing a conversion on unimplemented channels will return a floating input measurement.
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 29
PIC18F8723 FAMILY
REGISTER 2-2:
ADCON1: A/D CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
VCFG1:VCFG0: Voltage Reference Configuration bits
A/D VREF+
A/D VREF-
00
01
10
11
AVDD
AVSS
External VREF+
AVDD
AVSS
External VREF-
External VREF-
External VREF+
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits:
PCFG<3:0>
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
A = Analog input
D = Digital I/O
Note 1: AN15 through AN12 are available only on PIC18F8628/8723 devices.
DS39894A-page 30
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
REGISTER 2-3:
ADCON2: A/D CONTROL REGISTER 2
R/W-0
ADFM
bit 7
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ADFM: A/D Result Format Select bit
1= Right justified
0= Left justified
bit 6
Unimplemented: Read as ‘0’
bit 5-3
ACQT2:ACQT0: A/D Acquisition Time Select bits
111= 20 TAD
110= 16 TAD
101= 12 TAD
100= 8 TAD
011= 6 TAD
010= 4 TAD
001= 2 TAD
(1)
000= 0 TAD
bit 2-0
ADCS2:ADCS0: A/D Conversion Clock Select bits
111= FRC (clock derived from A/D RC oscillator)(1)
110= FOSC/64
101= FOSC/16
100= FOSC/4
011= FRC (clock derived from A/D RC oscillator)(1)
010= FOSC/32
001= FOSC/8
000= FOSC/2
Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEPinstruction to be executed before starting a conversion.
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 31
PIC18F8723 FAMILY
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS), or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF-/CVREF pins.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D Converter can be
configured as an analog input or a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is cleared
and the A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 2-1.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
FIGURE 2-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1111
AN15(1)
1110
AN14(1)
1101
AN13(1)
1100
AN12(1)
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0101
AN5
0100
AN4
VAIN
0011
(Input Voltage)
12-Bit
A/D
Converter
AN3
0010
AN2
0001
VCFG1:VCFG0
AN1
(2)
0000
AVDD
AN0
X0
X1
1X
VREF+
VREF-
Reference
Voltage
0X
(2)
AVSS
Note 1: Channels AN12 through AN15 are not available on PIC18F6628/6723 devices.
2: I/O pins have diode protection to VDD and VSS.
DS39894A-page 32
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
The value in the ADRESH:ADRESL registers is
unknown following Power-on and Brown-out Resets and
is not affected by any other Reset.
5. Wait for A/D conversion to complete by either:
• Polling for the GO/DONE bit to be cleared
OR
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 2.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
FIGURE 2-2:
A/D TRANSFER FUNCTION
The following steps should be followed to perform an A/D
conversion:
FFFh
FFEh
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON2)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
003h
002h
001h
000h
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0<1>)
Analog Input Voltage
FIGURE 2-3:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
Rs
CPIN
5 pF
CHOLD = 25 pF
VSS
VAIN
ILEAKAGE
±100 nA
VT = 0.6V
Legend: CPIN
= Input Capacitance
= Threshold Voltage
6V
5V
4V
3V
2V
VT
ILEAKAGE = Leakage Current at the pin due to
various junctions
VDD
RIC
= Interconnect Resistance
SS
= Sampling Switch
CHOLD
RSS
= Sample/Hold Capacitance (from DAC)
= Sampling Switch Resistance
1
2
3
4
Sampling Switch (kΩ)
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 33
PIC18F8723 FAMILY
To calculate the minimum acquisition time, Equation 2-1
may be used. This equation assumes that 1/2 LSb error
is used (4096 steps for the 12-bit A/D). The 1/2 LSb error
is the maximum error allowed for the A/D to meet its
specified resolution.
2.1
A/D Acquisition Requirements
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 2-3. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor, CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the ana-
log input (due to pin leakage current). The maximum
recommended impedance for analog sources is
2.5 kΩ. After the analog input channel is selected
(changed), the channel must be sampled for at least
Example 2-3 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
≤
=
=
25 pF
2.5 kΩ
1/2 LSb
3V → Rss = 4 kΩ
85°C (system max.)
the minimum acquisition time before starting
conversion.
a
Note:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
EQUATION 2-1:
ACQUISITION TIME
TACQ
=
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 2-2:
A/D MINIMUM CHARGING TIME
VHOLD
or
TC
=
=
(VREF – (VREF/4096)) • (1 – e(-TC/CHOLD(RIC + RSS + RS))
)
– (CHOLD)(RIC + RSS + RS) ln(1/4096)
EQUATION 2-3:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
TAMP
TCOFF
=
=
=
TAMP + TC + TCOFF
0.2 µs
(Temp – 25°C)(0.02 µs/°C)
(85°C – 25°C)(0.02 µs/°C)
1.2 µs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 µs.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/4096) µs
-(25 pF) (1 kΩ + 4 kΩ + 2.5 kΩ) ln(0.0002441) µs
1.56 µs
TACQ
=
0.2 µs + 1.56 μs + 1.2 µs
2.96 µs
DS39894A-page 34
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
2.2
Selecting and Configuring
Acquisition Time
2.3
Selecting the A/D Conversion
Clock
The ADCON2 register allows the user to select an
acquisition time that occurs each time the GO/DONE
bit is set. It also gives users the option to use an
automatically determined acquisition time.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 13 TAD per 12-bit conversion.
The source of the A/D conversion clock is software
selectable. There are seven possible options for TAD:
Acquisition time may be set with the ACQT2:ACQT0
bits (ADCON2<5:3>), which provide a range of 2 to
20 TAD. When the GO/DONE bit is set, the A/D module
continues to sample the input for the selected acquisi-
tion time, then automatically begins a conversion.
Since the acquisition time is programmed, there may
be no need to wait for an acquisition time between
selecting a channel and setting the GO/DONE bit.
• 2 TOSC
• 4 TOSC
• 8 TOSC
• 16 TOSC
• 32 TOSC
• 64 TOSC
• Internal RC Oscillator
Manual
acquisition
is
selected
when
For correct A/D conversions, the A/D conversion clock
(TAD) must be as short as possible, but greater than the
minimum TAD (see parameter 130 for more
information).
ACQT2:ACQT0 = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT2:ACQT0 bits
and is compatible with devices that do not offer
programmable acquisition times.
Table 2-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
In either case, when the conversion is completed, the
GO/DONE bit is cleared, the ADIF flag is set and the
A/D begins sampling the currently selected channel
again. If an acquisition time is programmed, there is
nothing to indicate if the acquisition time has ended or
if the conversion has begun.
TABLE 2-1:
TAD vs. DEVICE OPERATING FREQUENCIES
Assumes TAD Min. = 0.8 μs
A/D Clock Source (TAD)
Operation
ADCS2:ADCS0
Maximum FOSC
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
RC(1)
000
100
001
101
010
110
x11
2.50 MHz
5.00 MHz
10.00 MHz
20.00 MHz
40.00 MHz
40.00 MHz
1.00 MHz(2)
Note 1: The RC source has a typical TAD time of 2.5 μs.
2: For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or a FOSC
divider should be used instead; otherwise, the A/D accuracy specification may not be met.
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 35
PIC18F8723 FAMILY
2.4
Operation in Power-Managed
Modes
2.5
Configuring Analog Port Pins
The ADCON1, TRISA, TRISF and TRISH registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ADCS2:ADCS0 bits in
ADCON2 should be updated in accordance with the
clock source to be used. The ACQT2:ACQT0 bits do
not need to be adjusted as the ADCS2:ADCS0 bits
adjust the TAD time for the new clock speed. After enter-
ing the mode, an A/D acquisition or conversion may be
started. Once started, the device should continue to be
clocked by the same clock source until the conversion
has been completed.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Analog con-
version on pins configured as digital pins
can be performed. The voltage on the pin
will be accurately converted.
2: Analog levels on any pin defined as a dig-
ital input may cause the digital input buffer
to consume current out of the device’s
specification limits.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
Operation in Sleep mode requires the A/D FRC clock to
be selected. If the ACQT2:ACQT0 bits are set to ‘000’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEPinstruction and entry to Sleep mode. The IDLEN
bit (OSCCON<7>) must have already been cleared
prior to starting the conversion.
DS39894A-page 36
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
After the A/D conversion is completed or aborted, a
2 TCY wait is required before the next acquisition can
be started. After this wait, acquisition on the selected
channel is automatically started.
2.6
A/D Conversions
Figure 2-4 shows the operation of the A/D Converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Code should wait at least 2 μs after
enabling the A/D before beginning an
acquisition and conversion cycle.
Figure 2-5 shows the operation of the A/D Converter
after the GO/DONE bit has been set, the
ACQT2:ACQT0 bits are set to ‘010’ and a 4 TAD acqui-
sition time has been selected before the conversion
starts.
2.7
Discharge
The discharge phase is used to initialize the value of
the holding capacitor. The array is discharged before
every sample. This feature helps to optimize the unity
gain amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
Clearing the GO/DONE bit during a conversion will abort
the current conversion. The A/D Result register pair will
NOT be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
FIGURE 2-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY – TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD12 TAD13 TAD1
b6
b3
b2
b1
b0
b11 b10
b9
Conversion starts
b8
b7
b5
b4
Discharge
(typically 200 ns)
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO/DONE bit
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input
FIGURE 2-5:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TAD Cycles
TACQT Cycles
6
7
8
9
10
b4 b3
11
b2
12
b1 b0
13 TAD1
1
2
3
4
1
2
3
4
5
b9
b8
b5
b10
b7
b6
b11
Automatic
Acquisition
Time
Discharge
(typically
200 ns)
Conversion starts
(Holding capacitor is disconnected)
Set GO/DONE bit
(Holding capacitor continues
acquiring input)
On the following cycle:
ADRESH:ADRESL are loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 37
PIC18F8723 FAMILY
desired location). The appropriate analog input chan-
nel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time selected before the Special Event Trigger
sets the GO/DONE bit (starts a conversion).
2.8
Use of the ECCP2 Trigger
An A/D conversion can be started by the Special Event
Trigger of the ECCP2 module. This requires that the
CCP2M3:CCP2M0
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion, and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automat-
ically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH:ADRESL to the
bits
(CCP2CON<3:0>)
be
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
TABLE 2-2:
Name
REGISTERS ASSOCIATED WITH A/D OPERATION
Reset
Values
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(3)
INTCON
PIR1
PIE1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TX1IF
TX1IE
TX1IP
EEIF
RBIE
TMR0IF
CCP1IF
CCP1IE
CCP1IP
HLVDIF
HLVDIE
HLVDIP
INT0IF
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
RBIF
(3)
PSPIF
PSPIE
ADIF
ADIE
ADIP
CMIF
CMIE
CMIP
RC1IF
RC1IE
RC1IP
—
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
(3)
(3)
IPR1
PIR2
PIE2
PSPIP
(3)
OSCFIF
OSCFIE
OSCFIP
(3)
—
EEIE
(3)
IPR2
—
EEIP
(3)
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
(3)
(3)
(3)
(3)
(3)
(3)
(3)
ADCON0
ADCON1
ADCON2
TRISA
—
—
—
—
—
CHS3
VCFG1
ACQT2
CHS2
VCFG0
ACQT1
TRISA4
TRISF4
TRISH4
CHS1
PCFG3
ACQT0
TRISA3
TRISF3
TRISH3
CHS0 GO/DONE ADON
PCFG2
ADCS2
TRISA2
TRISF2
TRISH2
PCFG1
ADCS1
TRISA1
TRISF1
TRISH1
PCFG0
ADCS0
TRISA0
TRISF0
TRISH0
ADFM
TRISA7(1) TRISA6(1) TRISA5
TRISF
TRISH(2)
TRISF7
TRISH7
TRISF6
TRISH6
TRISF5
TRISH5
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
2: These registers are not implemented on PIC18F6628/6723 devices.
3: For these Reset values, see the “PIC18F8722 Family Data Sheet” (DS39646).
DS39894A-page 38
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
3.1
Device ID Registers
3.0
SPECIAL FEATURES OF THE
CPU
The Device ID registers are “read-only” registers.
They identify the device type and revision to device
programmers and can be read by firmware using table
reads.
Note:
For additional details on the Configuration
bits, refer to Section 25.1 “Configuration
Bits” in the “PIC18F8722 Family Data
Sheet” (DS39646). Device ID information
presented in this section is for the
PIC18F8723 family only.
PIC18F8723 family devices include several features
intended to maximize reliability and minimize cost
through elimination of external components. These
include:
• Device ID Registers
TABLE 3-1:
DEVICE IDs
Default/
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unprogrammed
Value
(1)
3FFFFEh DEVID1
3FFFFFh DEVID2
DEV2
DEV1
DEV9
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
REV1
DEV4
REV0
DEV3
xxxx xxxx
(1)
DEV10
xxxx xxxx
Legend:
x= unknown
Note 1: See Register 3-1 and Register 3-2 for DEVID values. DEVID registers are read-only and cannot be programmed by the
user.
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 39
PIC18F8723 FAMILY
REGISTER 3-1:
DEVID1: DEVICE ID REGISTER 1 FOR PIC18F8723 FAMILY DEVICES
R
DEV2
bit 7
R
R
R
R
R
R
R
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 0
Legend:
R = Read-only bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-5
bit 4-0
DEV2:DEV0: Device ID bits
See Register 3-2 for a complete listing.
REV4:REV0: Revision ID bits
These bits are used to indicate the device revision.
REGISTER 3-2:
DEVID2: DEVICE ID REGISTER 2 FOR PIC18F8723 FAMILY DEVICES
R
DEV10
bit 7
R
R
R
R
R
R
R
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 0
Legend:
R = Read-only bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
-n = Value when device is unprogrammed
u = Unchanged from programmed state
bit 7-0
DEV10:DEV3: Device ID bits
DEV10:DEV3
(DEVID2<7:0>)
DEV2:DEV0
(DEVID1<7:5>)
Device
0100 1001
0100 1010
0100 1001
0100 1010
110
000
111
001
PIC18F6628
PIC18F6723
PIC18F8628
PIC18F8723
DS39894A-page 40
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
4.0
ELECTRICAL CHARACTERISTICS
Note: Other than some basic data, this section documents only the PIC18F8723 family’s specifications that differ
from those of the PIC18F8722 family devices. For detailed information on the electrical specifications shared
by the PIC18F8723 family and PIC18F8722 family devices, see the “PIC18F8722 Family Data Sheet”
(DS39646).
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the RG5/MCLR/VPP pin, inducing currents greater than 80 mA, may cause
latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the RG5/MCLR/
VPP pin, rather than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 41
PIC18F8723 FAMILY
FIGURE 4-1:
PIC18F8723 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18F8723 Family
4.2V
3.5V
3.0V
2.5V
2.0V
FMAX
Frequency
FMAX = 20 MHz in 8-Bit External Memory mode.
FMAX = 40 MHz in all other modes.
FIGURE 4-2:
PIC18F8723 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED)
6.0V
5.5V
5.0V
4.5V
4.0V
PIC18F8723 Family
4.2V
3.5V
3.0V
2.5V
2.0V
FMAX
Frequency
FMAX = 20 MHz in 8-Bit External Memory mode.
FMAX = 25 MHz in all other modes.
DS39894A-page 42
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
FIGURE 4-3:
PIC18LF8723 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V
5.5V
5.0V
PIC18LF8723 Family
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
FMAX
4 MHz
Frequency
In 8-Bit External Memory mode:
FMAX = (9.55 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz, if VDDAPPMIN ≤ 4.2V;
FMAX = 25 MHz, if VDDAPPMIN > 4.2V.
In all other modes:
FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz;
FMAX = 40 MHz, if VDDAPPMIN > 4.2V.
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 43
PIC18F8723 FAMILY
TABLE 4-1:
A/D CONVERTER CHARACTERISTICS: PIC18F8723 FAMILY (INDUSTRIAL)
Param
Sym
No.
Characteristic
Min
Typ
Max
Units
Conditions
A01
A03
NR
EIL
Resolution
—
—
—
—
—
—
—
—
—
—
12
±2.0
bit
ΔVREF ≥ 3.0V
Integral Linearity Error
<±1
LSB VDD = 3.0V ΔVREF ≥ 3.0V
LSB VDD = 5.0V
—
±2.0
A04
A06
A07
EDL
Differential Linearity Error
<±1
+1.5/-1.0
+1.5/-1.0
±5
LSB VDD = 3.0V ΔVREF ≥ 3.0V
LSB VDD = 5.0V
—
EOFF Offset Error
<±1
LSB VDD = 3.0V ΔVREF ≥ 3.0V
LSB VDD = 5.0V
—
±3
EGN
Gain Error
<±1
±1.25
±2.00
LSB VDD = 3.0V ΔVREF ≥ 3.0V
LSB VDD = 5.0V
—
Guaranteed
—
(1)
A10
A20
—
Monotonicity
—
V
VSS ≤ VAIN ≤ VREF
ΔVREF Reference Voltage Range
3
VDD – VSS
For 12-bit resolution
(VREFH – VREFL)
A21
A22
A25
A30
VREFH Reference Voltage High
VREFL Reference Voltage Low
VSS + 3.0V
VSS – 0.3V
VREFL
—
—
—
—
VDD + 0.3V
VDD – 3.0V
VREFH
V
V
For 12-bit resolution
For 12-bit resolution
VAIN
ZAIN
Analog Input Voltage
V
Recommended
—
2.5
kΩ
Impedance of Analog
Voltage Source
(2)
A50
IREF
VREF Input Current
—
—
—
—
5
150
μA
μA
During VAIN acquisition.
During A/D conversion
cycle.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
2: VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL current is from
the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.
DS39894A-page 44
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
FIGURE 4-4:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
131
130
Q4
A/D CLK(1)
132
. . .
. . .
11
10
9
3
2
1
0
A/D DATA
NEW_DATA
TCY
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEPinstruction
to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 4-2:
A/D CONVERSION REQUIREMENTS
Characteristic
Param
No.
Symbol
Min
Max
Units
Conditions
130
TAD
A/D Clock Period
PIC18FXXXX
0.8
1.4
12.5(1)
25.0(1)
μs TOSC based, VREF ≥ 3.0V
PIC18LFXXXX
μs VDD = 3.0V;
TOSC based, VREF full range
PIC18FXXXX
—
—
13
1
3
μs A/D RC mode
μs VDD = 3.0V; A/D RC mode
TAD
PIC18LFXXXX
131
TCNV
Conversion Time
14
(not including acquisition time)(2)
Acquisition Time(3)
132
135
137
TACQ
TSWC
TDIS
1.4
—
—
(Note 4)
—
μs
Switching Time from Convert → Sample
Discharge Time
0.2
μs
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES registers may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 45
PIC18F8723 FAMILY
NOTES:
DS39894A-page 46
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
5.0
PACKAGING INFORMATION
For packaging information, see the “PIC18F8722 Family
Data Sheet” (DS39646).
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 47
PIC18F8723 FAMILY
NOTES:
DS39894A-page 48
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
APPENDIX A: REVISION HISTORY
Revision A (August 2007)
APPENDIX B: DEVICE
DIFFERENCES
The differences between the devices listed in this data
sheet are shown in Table B-1.
Original data sheet for the PIC18F8723 family of
devices.
TABLE B-1:
PIC18F8723 FAMILY DEVICE DIFFERENCES
Features
PIC18F6628
PIC18F6723
PIC18F8628
PIC18F8723
Program Memory (Bytes)
Program Memory (Instructions)
Interrupt Sources
96K
49152
28
128K
65536
28
96K
49152
29
128K
65536
29
I/O Ports
Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E, Ports A, B, C, D, E,
F, G
F, G
F, G, H, J
F, G, H, J
Capture/Compare/PWM Modules
2
2
2
3
2
3
Enhanced
3
3
Capture/Compare/PWM Modules
Parallel Communications (PSP)
External Memory Bus
12-Bit Analog-to-Digital Module
Packages
Yes
No
Yes
No
Yes
Yes
Yes
Yes
12 Input Channels
64-Pin TQFP
12 Input Channels
64-Pin TQFP
16 Input Channels
80-Pin TQFP
16 Input Channels
80-Pin TQFP
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 49
PIC18F8723 FAMILY
APPENDIX C: CONVERSION
CONSIDERATIONS
APPENDIX D: MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
This appendix discusses the considerations for
converting from previous versions of a device to the
ones listed in this data sheet. Typically, these changes
are due to the differences in the process technology
used. An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
This section discusses how to migrate from a Baseline
device (i.e., PIC16C5X) to an Enhanced MCU device
(i.e., PIC18FXXX).
The following are the list of modifications over the
PIC16C5X microcontroller family:
Not Applicable
Not Currently Available
DS39894A-page 50
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
APPENDIX E: MIGRATION FROM
MID-RANGE TO
APPENDIX F: MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
ENHANCED DEVICES
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18FXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442”. The changes discussed, while device
specific, are generally applicable to all mid-range to
enhanced device migrations.
A detailed discussion of the migration pathway and
differences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18FXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration”.
This Application Note is available on our web site,
www.microchip.com, as Literature Number DS00726.
This Application Note is available on our web site,
www.microchip.com, as Literature Number DS00716.
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 51
PIC18F8723 FAMILY
NOTES:
DS39894A-page 52
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
INDEX
A
F
A/D...................................................................................... 29
A/D Converter Interrupt, Configuring .......................... 33
Acquisition Requirements ........................................... 34
ADCON0 Register....................................................... 29
ADCON1 Register....................................................... 29
ADCON2 Register....................................................... 29
ADRESH Register................................................. 29, 32
ADRESL Register ....................................................... 29
Analog Port Pins, Configuring..................................... 36
Associated Registers .................................................. 38
Configuring the Module............................................... 33
Conversion Clock (TAD) .............................................. 35
Conversion Status (GO/DONE Bit)............................. 32
Conversions................................................................ 37
Converter Characteristics ........................................... 44
Discharge.................................................................... 37
Operation in Power-Managed Modes ......................... 36
Selecting and Configuring Acquisition Time ............... 35
Special Event Trigger (ECCP2) .................................. 38
Transfer Function........................................................ 33
Use of the ECCP2 Trigger .......................................... 38
Absolute Maximum Ratings ................................................ 41
ADCON0 Register............................................................... 29
GO/DONE Bit.............................................................. 32
ADCON1 Register............................................................... 29
ADCON2 Register............................................................... 29
ADRESH Register............................................................... 29
ADRESL Register ......................................................... 29, 32
Analog-to-Digital Converter. See A/D.
Features Summary Table ..................................................... 1
I
Internet Address ................................................................. 55
Interrupt Sources
A/D Conversion Complete.......................................... 33
M
Microchip Internet Web Site................................................ 55
Migration From Baseline to Enhanced Devices.................. 50
Migration From High-End to Enhanced Devices................. 51
Migration From Mid-Range to Enhanced Devices.............. 51
More Information................................................................... 5
Customer Notification System ...................................... 5
Errata............................................................................ 5
O
Overview
External Memory Interface ........................................... 1
Features Summary Table............................................. 1
Peripheral Highlights .................................................... 1
Power-Managed Modes ............................................... 1
Special Microcontroller Features.................................. 1
P
Packaging Information........................................................ 47
Peripheral Highlights............................................................. 1
Pin Diagrams
64-Pin TQFP................................................................. 2
80-Pin TQFP................................................................. 3
Pin Functions
B
AVDD (64-pin) ............................................................. 18
AVDD (80-pin) ............................................................. 28
AVSS (64-pin).............................................................. 18
AVSS (80-pin).............................................................. 28
OSC1/CLKI/RA7................................................... 11, 19
OSC2/CLKO/RA6................................................. 11, 19
RA0/AN0............................................................... 12, 20
RA1/AN1............................................................... 12, 20
RA2/AN2/VREF- .................................................... 12, 20
RA3/AN3/VREF+ ................................................... 12, 20
RA4/T0CKI ........................................................... 12, 20
RA5/AN4/HLVDIN ................................................ 12, 20
RB0/INT0/FLT0 .................................................... 13, 21
RB1/INT1.............................................................. 13, 21
RB2/INT2.............................................................. 13, 21
RB3/INT3.................................................................... 13
RB3/INT3/ECCP2/P2A............................................... 21
RB4/KBI0.............................................................. 13, 21
RB5/KBI1/PGM..................................................... 13, 21
RB6/KBI2/PGC..................................................... 13, 21
RB7/KBI3/PGD..................................................... 13, 21
RC0/T1OSO/T13CKI............................................ 14, 22
RC1/T1OSI/ECCP2/P2A ...................................... 14, 22
RC2/ECCP1/P1A.................................................. 14, 22
RC3/SCK1/SCL1.................................................. 14, 22
RC4/SDI1/SDA1................................................... 14, 22
RC5/SDO1............................................................ 14, 22
RC6/TX1/CK1....................................................... 14, 22
RC7/RX1/DT1....................................................... 14, 22
RD0/AD0/PSP0 .......................................................... 23
RD0/PSP0 .................................................................. 15
Block Diagrams
A/D.............................................................................. 32
Analog Input Model..................................................... 33
PIC18F6628/6723......................................................... 9
PIC18F8628/8723....................................................... 10
C
Compare (ECCP2 Module)
Special Event Trigger.................................................. 38
Conversion Considerations................................................. 50
Customer Change Notification Service ............................... 55
Customer Notification Service............................................. 55
Customer Notification System............................................... 5
Customer Support............................................................... 55
D
Device Differences.............................................................. 49
Device ID Registers ............................................................ 39
Device Overview
Features (table)............................................................. 8
Special Features........................................................... 7
E
Electrical Characteristics..................................................... 41
Equations
A/D Acquisition Time................................................... 34
A/D Minimum Charging Time...................................... 34
Calculating the Minimum Required
Acquisition Time ................................................. 34
Errata .................................................................................... 5
External Memory Interface.................................................... 1
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 53
PIC18F8723 FAMILY
RD1/AD1/PSP1...........................................................23
RD1/PSP1...................................................................15
RD2/AD2/PSP2...........................................................23
RD2/PSP2...................................................................15
RD3/AD3/PSP3...........................................................23
RD3/PSP3...................................................................15
RD4/AD4/PSP4/SDO2................................................23
RD4/PSP4/SDO2........................................................15
RD5/AD5/PSP5/SDI2/SDA2 .......................................23
RD5/PSP5/SDI2/SDA2 ...............................................15
RD6/AD6/PSP6/SCK2/SCL2 ......................................23
RD6/PSP6/SCK2/SCL2 ..............................................15
RD7/AD7/PSP7/SS2...................................................23
RD7/PSP7/SS2...........................................................15
RE0/AD8/RD/P2D.......................................................24
RE0/RD/P2D...............................................................16
RE1/AD9/WR/P2C ......................................................24
RE1/WR/P2C ..............................................................16
RE2/AD10/CS/P2B .....................................................24
RE2/CS/P2D...............................................................16
RE3/AD11/P3C...........................................................24
RE3/P3C .....................................................................16
RE4/AD12/P3B ...........................................................24
RE4/P3B .....................................................................16
RE5/AD13/P1C...........................................................24
RE5/P1C .....................................................................16
RE6/AD14/P1B ...........................................................24
RE6/P1B .....................................................................16
RE7/AD15/ECCP2/P2A ..............................................24
RE7/ECCP2/P2A ........................................................16
RF0/AN5 ............................................................... 17, 25
RF1/AN6/C2OUT .................................................. 17, 25
RF2/AN7/C1OUT .................................................. 17, 25
RF3/AN8 ............................................................... 17, 25
RF4/AN9 ............................................................... 17, 25
RF5/AN10/CVREF.................................................. 17, 25
RF6/AN11 ............................................................. 17, 25
RF7/SS1 ............................................................... 17, 25
RG0/ECCP3/P3A.................................................. 18, 26
RG1/TX2/CK2....................................................... 18, 26
RG2/RX2/DT2....................................................... 18, 26
RG3/CCP4/P3D .................................................... 18, 26
RG4/CCP5/P1D .................................................... 18, 26
RG5....................................................................... 18, 26
RG5/MCLR/VPP .................................................... 11, 19
RH0/A16 .....................................................................27
RH1/A17 .....................................................................27
RH2/A18 .....................................................................27
RH3/A19 .....................................................................27
RH4/AN12/P3C...........................................................27
RH5/AN13/P3B...........................................................27
RH6/AN14/P1C...........................................................27
RH7/AN15/P1B...........................................................27
RJ0/ALE......................................................................28
RJ1/OE .......................................................................28
RJ2/WRL.....................................................................28
RJ3/WRH ....................................................................28
RJ4/BA0......................................................................28
RJ5/CE........................................................................28
RJ6/LB ........................................................................28
RJ7/UB........................................................................28
VDD..............................................................................28
VDD..............................................................................18
VSS..............................................................................28
VSS..............................................................................18
Pinout I/O Descriptions
PIC18F6628/6723 ...................................................... 11
PIC18F8628/8723 ...................................................... 19
Power-Managed Modes........................................................ 1
and A/D Operation...................................................... 36
Product Identification System ............................................. 57
R
Reader Response............................................................... 56
Registers
ADCON0 (A/D Control 0)............................................ 29
ADCON1 (A/D Control 1)............................................ 30
ADCON2 (A/D Control 2)............................................ 31
DEVID1 (Device ID 1)................................................. 40
DEVID2 (Device ID 2)................................................. 40
Revision History.................................................................. 49
S
Special Features of the CPU .............................................. 39
Device ID Registers.................................................... 39
Special Microcontroller Features .......................................... 1
T
Timing Diagrams
A/D Conversion........................................................... 45
Timing Diagrams and Specifications
A/D Conversion Requirements ................................... 45
V
Voltage-Frequency Graphs
Extended (PIC18F8723)............................................. 42
Industrial (PIC18F8723).............................................. 42
Industrial (PIC18LF8723)............................................ 43
W
Worldwide Sales and Service Offices................................. 58
WWW Address ................................................................... 55
WWW, On-Line Support ....................................................... 5
DS39894A-page 54
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://support.microchip.com
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 55
PIC18F8723 FAMILY
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
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RE:
From:
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City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
PIC18F8723 Family
DS39894A
Literature Number:
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39894A-page 56
Preliminary
© 2007 Microchip Technology Inc.
PIC18F8723 FAMILY
PIC18F8723 FAMILY PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
PIC18LF6723-I/PT 301 = Industrial temp.,
TQFP package, Extended VDD
limits, QTP pattern #301.
b)
PIC18F6723-E/PT = Extended temp.,
TQFP package, standard VDD limits.
Device(1) (2)
PIC18F6628/6723, PIC18F8628/8723,
VDD range 4.2V to 5.5V
PIC18LF6628/6723, PIC18LF6628/6723(
VDD range 2.0V to 5.5V
Temperature
Range
I
E
=
=
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
Package
Pattern
PT
=
TQFP (Thin Quad Flatpack)
Note 1:
2:
F
LF
T
=
=
=
Standard Voltage Range
Wide Voltage Range
in tape and reel TQFP
packages only.
QTP, SQTP, Code or Special Requirements
(blank otherwise)
© 2007 Microchip Technology Inc.
Preliminary
DS39894A-page 57
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Boston
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
06/25/07
DS39894A-page 58
Preliminary
© 2007 Microchip Technology Inc.
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