PIC18LC242T-/PT [MICROCHIP]
RISC MICROCONTROLLER;
| 型号： | PIC18LC242T-/PT |
| 厂家： | 
MICROCHIP |
| 描述： | RISC MICROCONTROLLER 外围集成电路 |
| 文件： | 总304页 (文件大小：4529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC18CXX2
High Performance Microcontrollers with 10-bit A/D
High Performance RISC CPU:
Pin Diagrams
DIP, Windowed CERDIP
• C compiler optimized architecture/instruction set
- Source code compatible with the PIC16CXX
instruction set
• Linear program memory addressing to 2 Mbytes
• Linear data memory addressing to 4 Kbytes
RB7
RB6
RB5
RB4
RB3/CCP2*
RB2/INT2
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
MCLR/VPP
RA0/AN0
2
3
RA1/AN1
RA2/AN2/VREF-
4
RA3/AN3/VREF+
RA4/T0CKI
5
6
On-Chip Program Memory
RB1/INT1
RB0/INT0
VDD
On-Chip
RAM
(bytes)
RA5/AN4/SS/LVDIN
7
8
9
Device
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
EPROM
(bytes)
# Single Word
Instructions
VSS
10
11
12
13
14
15
16
17
18
19
20
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
PIC18C242
PIC18C252
PIC18C442
16K
32K
16K
8192
16384
8192
512
1536
512
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
PIC18C452
32K
16384
1536
• Up to 10 MIPs operation:
- DC - 40 MHz osc./clock input
- 4 MHz - 10 MHz osc./clock input with PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
RC4/SDI/SDA
RD3/PSP3
RC3/SCK/SCL
RD0/PSP0
RD2/PSP2
RD1/PSP1
* RB3 is the alternate pin for the CCP2 pin multiplexing.
Note: Pin compatible with 40-pin PIC16C7X devices.
• 8 x 8 Single Cycle Hardware Multiplier
Analog Features:
Peripheral Features:
• Compatible 10-bit Analog-to-Digital Converter
module (A/D) with:
- Fast sampling rate
• High current sink/source 25 mA/25 mA
• Three external interrupt pins
- Conversion available during SLEEP
- DNL = ±1 LSb, INL = ±1 LSb
• Programmable Low Voltage Detection (LVD)
module
- Supports interrupt-on-low voltage detection
• Programmable Brown-out Reset (BOR)
• Timer0 module: 8-bit/16-bit timer/counter with
8-bit programmable prescaler
• Timer1 module: 16-bit timer/counter
• Timer2 module: 8-bit timer/counter with 8-bit
period register (time-base for PWM)
• Timer3 module: 16-bit timer/counter
• Secondary oscillator clock option - Timer1/Timer3
• Two Capture/Compare/PWM (CCP) modules.
CCP pins that can be configured as:
- Capture input: capture is 16-bit,
Special Microcontroller Features:
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options including:
- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input
• In-Circuit Serial Programming (ICSP™) via two pins
max. resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max. resolution 100 ns (TCY)
- PWM output: PWM resolution is 1- to 10-bit.
Max. PWM freq. @: 8-bit resolution = 156 kHz
10-bit resolution = 39 kHz
• Master Synchronous Serial Port (MSSP) module.
Two modes of operation:
- 3-wire SPI (supports all 4 SPI modes)
- I2C™ master and slave mode
CMOS Technology:
• Addressable USART module:
- Supports interrupt on Address bit
• Parallel Slave Port (PSP) module
• Low power, high speed EPROM technology
• Fully static design
• Wide operating voltage range (2.5V to 5.5V)
• Industrial and Extended temperature ranges
• Low power consumption
1999-2013 Microchip Technology Inc.
DS39026D-page 1
PIC18CXX2
Pin Diagrams
PLCC
39
38
37
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
7
RA4/T0CKI
8
RA5/AN4/SS/LVDIN
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
9
10
11
12
13
14
15
16
17
36
35
34
33
32
31
30
29
PIC18C4X2
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
NC
TQFP
NC
33
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
1
2
3
4
5
6
7
8
9
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
32
31
30
29
28
27
26
PIC18C4X2
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/LVDIN
RA4/T0CKI
VDD
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2*
25
24
23
10
11
* RB3 is the alternate pin for the CCP2 pin multiplexing.
Note: Pin compatible with 44-pin PIC16C7X devices.
DS39026D-page 2
1999-2013 Microchip Technology Inc.
PIC18CXX2
Pin Diagrams (Cont.’d)
DIP, JW
MCLR/VPP
RA0/AN0
1
2
3
4
5
6
7
8
RB7
RB6
RB5
RB4
RB3/CCP2*
RB2/INT2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
RB1/INT1
RB0/INT0
VDD
9
10
11
12
13
14
15
16
17
18
19
20
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
Note: Pin compatible with 40-pin PIC16C7X devices.
DIP, SOIC, JW
28
27
26
1
RB7
RB6
RB5
RB4
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
MCLR/VPP
RA0/AN0
RA1/AN1
2
3
4
5
6
7
8
9
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
25
24
23
22
21
20
19
18
17
16
15
RA5/AN4/SS/LVDIN
VSS
OSC1/CLKI
VSS
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
10
11
RC7/RX/DT
RC6/TX/CK
RC5/SDO
12
13
14
RC4/SDI/SDA
RC3/SCK/SCL
* RB3 is the alternate pin for the CCP2 pin multiplexing.
Note: Pin compatible with 28-pin PIC16C7X devices.
1999-2013 Microchip Technology Inc.
DS39026D-page 3
PIC18CXX2
Table of Contents
1.0 Device Overview......................................................................................................................................................................... 7
2.0 Oscillator Configurations........................................................................................................................................................... 17
3.0 Reset......................................................................................................................................................................................... 25
4.0 Memory Organization................................................................................................................................................................ 35
5.0 Table Reads/Table Writes ........................................................................................................................................................ 55
6.0 8 X 8 Hardware Multiplier.......................................................................................................................................................... 61
7.0 Interrupts................................................................................................................................................................................... 63
8.0 I/O Ports.................................................................................................................................................................................... 77
9.0 Timer0 Module.......................................................................................................................................................................... 93
10.0 Timer1 Module.......................................................................................................................................................................... 97
11.0 Timer2 Module........................................................................................................................................................................ 101
12.0 Timer3 Module........................................................................................................................................................................ 103
13.0 Capture/Compare/PWM (CCP) Modules................................................................................................................................ 107
14.0 Master Synchronous Serial Port (MSSP) Module................................................................................................................... 115
15.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ............................................................ 149
16.0 Compatible 10-bit Analog-to-Digital Converter (A/D) Module ................................................................................................. 165
17.0 Low Voltage Detect................................................................................................................................................................. 173
18.0 Special Features of the CPU .................................................................................................................................................. 179
19.0 Instruction Set Summary......................................................................................................................................................... 187
20.0 Development Support ............................................................................................................................................................. 229
21.0 Electrical Characteristics......................................................................................................................................................... 235
22.0 DC and AC Characteristics Graphs and Tables ..................................................................................................................... 263
23.0 Packaging Information ............................................................................................................................................................ 277
Appendix A: Revision History......................................................................................................................................................... 287
Appendix B: Device Differences..................................................................................................................................................... 287
Appendix C: Conversion Considerations........................................................................................................................................ 288
Appendix D: Migration from Baseline to Enhanced Devices.......................................................................................................... 288
Appendix E: Migration from Mid-Range to Enhanced Devices ...................................................................................................... 289
Appendix F: Migration from High-End to Enhanced Devices......................................................................................................... 289
Index ................................................................................................................................................................................................. 291
On-Line Support................................................................................................................................................................................ 299
Reader Response ............................................................................................................................................................................. 300
PIC18CXX2 Product Identification System ....................................................................................................................................... 301
DS39026D-page 4
1999-2013 Microchip Technology Inc.
PIC18CXX2
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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1999-2013 Microchip Technology Inc.
DS39026D-page 5
PIC18CXX2
NOTES:
DS39026D-page 6
1999-2013 Microchip Technology Inc.
PIC18CXX2
The following two figures are device block diagrams
sorted by pin count: 28-pin for Figure 1-1 and 40-pin for
Figure 1-2. The 28-pin and 40-pin pinouts are listed in
Table 1-2 and Table 1-3, respectively.
1.0
DEVICE OVERVIEW
This document contains device specific information for
the following four devices:
1. PIC18C242
2. PIC18C252
3. PIC18C442
4. PIC18C452
These devices come in 28-pin and 40-pin packages.
The 28-pin devices do not have a Parallel Slave Port
(PSP) implemented and the number of Analog-to-
Digital (A/D) converter input channels is reduced to 5.
An overview of features is shown in Table 1-1.
TABLE 1-1:
DEVICE FEATURES
Features
PIC18C242
PIC18C252
PIC18C442
PIC18C452
Operating Frequency
Program Memory (Bytes)
Program Memory (Instructions)
Data Memory (Bytes)
Interrupt Sources
DC - 40 MHz
DC - 40 MHz
DC - 40 MHz
DC - 40 MHz
32K
16K
32K
16K
8192
512
17
8192
16384
16384
1536
512
1536
16
16
17
I/O Ports
Ports A, B, C
Ports A, B, C
Ports A, B, C, D, E Ports A, B, C, D, E
Timers
4
2
4
2
4
2
4
2
Capture/Compare/PWM Modules
Serial Communications
MSSP,
Addressable
USART
MSSP,
Addressable
USART
MSSP,
Addressable
USART
MSSP,
Addressable
USART
Parallel Communications
10-bit Analog-to-Digital Module
RESETS (and Delays)
—
—
PSP
PSP
5 input channels
POR, BOR,
5 input channels
POR, BOR,
8 input channels
POR, BOR,
8 input channels
POR, BOR,
RESETInstruction, RESETInstruction, RESETInstruction, RESETInstruction,
Stack Full,
Stack Underflow
(PWRT, OST)
Stack Full,
Stack Underflow
(PWRT, OST)
Stack Full,
Stack Underflow
(PWRT, OST)
Stack Full,
Stack Underflow
(PWRT, OST)
Programmable Low Voltage
Detect
Yes
Yes
Yes
Yes
Programmable Brown-out Reset
Instruction Set
Yes
Yes
Yes
Yes
75 Instructions
75 Instructions
75 Instructions
75 Instructions
Packages
28-pin DIP
28-pin SOIC
28-pin JW
28-pin DIP
28-pin SOIC
28-pin JW
40-pin DIP
44-pin PLCC
44-pin TQFP
40-pin JW
40-pin DIP
44-pin PLCC
44-pin TQFP
40-pin JW
1999-2013 Microchip Technology Inc.
DS39026D-page 7
PIC18CXX2
FIGURE 1-1:
PIC18C2X2 BLOCK DIAGRAM
Data Bus<8>
PORTA
Table Pointer <2>
inc/dec logic
20
Data Latch
21
RA0/AN0
8
8
8
Data RAM
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RA6
21
21
Address Latch
12(2)
PCLATU PCLATH
Address Latch
Address<12>
Program Memory
(up to 2M Bytes)
PCU PCH PCL
Program Counter
4
BSR
12
4
Data Latch
Bank0, F
FSR0
FSR1
FSR2
31 Level Stack
12
16
inc/dec
logic
Decode
Table Latch
8
PORTB
ROM Latch
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2(1)
Instruction
Register
8
Instruction
Decode &
Control
RB7:RB4
PRODH PRODL
8 x 8 Multiply
OSC2/CLKO
OSC1/CLKI
3
Power-up
Timer
8
Timing
Generation
Oscillator
Start-up Timer
WREG
8
BIT OP
8
8
T1OSI
T1OSO
Power-on
Reset
8
Watchdog
Timer
4X PLL
PORTC
ALU<8>
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
8
Brown-out
Reset
Precision
Voltage
Reference
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
MCLR
VDD, VSS
A/D Converter
Timer0
CCP1
Timer1
Timer2
Timer3
Master
Synchronous
Serial Port
Addressable
USART
CCP2
Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFFinstruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations
are device dependent.
DS39026D-page 8
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 1-2:
PIC18C4X2 BLOCK DIAGRAM
Data Bus<8>
PORTA
RA0/AN0
RA1/AN1
Table Pointer <2>
Data Latch
21
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RA6
Data RAM
(up to 4K
address reach)
8
8
8
inc/dec logic
20
21
21
Address Latch
12(2)
PCLATU
PCLATH
Address Latch
Program Memory
(up to 2M Bytes)
Address<12>
PCH PCL
Program Counter
PCU
PORTB
4
BSR
12
4
Data Latch
Bank0, F
FSR0
FSR1
FSR2
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2(1)
31 Level Stack
12
16
inc/dec
logic
RB7:RB4
Decode
Table Latch
8
PORTC
ROM Latch
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
Instruction
Register
8
Instruction
Decode &
Control
RC6/TX/CK
RC7/RX/DT
PRODH PRODL
8 x 8 Multiply
OSC2/CLKO
OSC1/CLKI
3
Power-up
Timer
PORTD
8
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
Timing
Generation
Oscillator
Start-up Timer
WREG
8
BIT OP
8
8
T1OSI
T1OSO
Power-on
Reset
8
4X PLL
Watchdog
Timer
ALU<8>
8
Brown-out
Reset
Precision
Voltage
Reference
PORTE
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
MCLR
VDD, VSS
Timer0
CCP1
Timer1
Timer2
A/D Converter
Timer3
Master
Synchronous
Serial Port
Addressable
USART
CCP2
Parallel Slave Port
Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFFinstruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations
are device dependent.
1999-2013 Microchip Technology Inc.
DS39026D-page 9
PIC18CXX2
TABLE 1-2:
Pin Name
PIC18C2X2 PINOUT I/O DESCRIPTIONS
Pin Number
DIP SOIC
Pin
Type
Buffer
Type
Description
MCLR/VPP
MCLR
1
1
Master clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active low
RESET to the device.
I
ST
—
VPP
NC
P
Programming voltage input.
—
9
—
9
—
These pins should be left unconnected.
OSC1/CLKI
OSC1
Oscillator crystal or external clock input.
I
I
ST
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode. CMOS otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKIN,
OSC2/CLKOUT pins.)
CLKI
CMOS
OSC2/CLKO/RA6
OSC2
10
10
Oscillator crystal or clock output.
O
O
—
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKOUT which has 1/4
the frequency of OSC1, and denotes the instruction
cycle rate.
CLKO
RA6
I/O
TTL
General Purpose I/O pin.
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
2
3
4
2
3
4
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D Reference Voltage (Low) input.
RA3/AN3/VREF+
RA3
5
5
I/O
TTL
Digital I/O.
AN3
VREF+
I
I
Analog
Analog
Analog input 3.
A/D Reference Voltage (High) input.
RA4/T0CKI
RA4
6
7
6
7
I/O
I
ST/OD
ST
Digital I/O. Open drain when configured as output.
Timer0 external clock input.
T0CKI
RA5/AN4/SS/LVDIN
RA5
AN4
SS
I/O
TTL
Analog
ST
Digital I/O.
Analog input 4.
SPI Slave Select input.
Low Voltage Detect Input.
I
I
I
LVDIN
Analog
RA6
See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output
P = Power
OD = Open Drain (no P diode to VDD)
DS39026D-page 10
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 1-2:
Pin Name
PIC18C2X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin
Buffer
Type
Description
Type
DIP SOIC
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0
RB0
21
22
23
24
21
22
23
24
I/O
I
TTL
ST
Digital I/O.
External Interrupt 0.
INT0
RB1/INT1
RB1
I/O
I
TTL
ST
INT1
External Interrupt 1.
RB2/INT2
RB2
I/O
I
TTL
ST
Digital I/O.
External Interrupt 2.
INT2
RB3/CCP2
RB3
I/O
I/O
TTL
ST
Digital I/O.
CCP2
Capture2 input, Compare2 output, PWM2 output.
RB4
RB5
RB6
25
26
27
25
26
27
I/O
I/O
I/O
TTL
TTL
TTL
Digital I/O.
Interrupt-on-change pin.
Digital I/O.
Interrupt-on-change pin.
Digital I/O.
Interrupt-on-change pin.
ICSP programming clock.
I
ST
RB7
28
28
I/O
TTL
Digital I/O.
Interrupt-on-change pin.
ICSP programming data.
I/O
ST
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output
P = Power
OD = Open Drain (no P diode to VDD)
1999-2013 Microchip Technology Inc.
DS39026D-page 11
PIC18CXX2
TABLE 1-2:
PIC18C2X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
DIP SOIC
Pin
Type
Buffer
Type
Pin Name
Description
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC0
11
11
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
12
12
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
T1OSI
CCP2
RC2/CCP1
RC2
13
14
13
14
I/O
I/O
ST
ST
Digital I/O.
CCP1
Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
RC3
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
SCK
SCL
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RC4/SDI/SDA
RC4
15
15
I/O
I
I/O
ST
ST
ST
Digital I/O.
SDI
SDA
SPI Data In.
I2C Data I/O.
RC5/SDO
RC5
16
17
16
17
I/O
O
ST
—
Digital I/O.
SPI Data Out.
SDO
RC6/TX/CK
RC6
TX
CK
I/O
O
I/O
ST
—
ST
Digital I/O.
USART Asynchronous Transmit.
USART Synchronous Clock (see related RX/DT).
RC7/RX/DT
18
18
RC7
RX
DT
I/O
I
I/O
ST
ST
ST
Digital I/O.
USART Asynchronous Receive.
USART Synchronous Data (see related TX/CK).
VSS
VDD
8, 19 8, 19
20 20
P
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
CMOS = CMOS compatible input or output
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output
P = Power
OD = Open Drain (no P diode to VDD)
DS39026D-page 12
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 1-3:
Pin Name
PIC18C4X2 PINOUT I/O DESCRIPTIONS
Pin Number
Pin Buffer
Description
Type Type
DIP PLCC TQFP
MCLR/VPP
MCLR
1
2
18
Master clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active
low RESET to the device.
I
ST
—
VPP
NC
P
Programming voltage input.
—
—
These pins should be left unconnected.
OSC1/CLKI
OSC1
13
14
30
Oscillator crystal or external clock input.
I
I
ST
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKIN,
OSC2/CLKOUT pins.)
CLKI
CMOS
OSC2/CLKO/RA6
OSC2
14
15
31
Oscillator crystal output.
O
O
—
—
Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKOUT, which has
1/4 the frequency of OSC1 and denotes the instruction
cycle rate.
CLKO
RA6
I/O
TTL
General Purpose I/O pin.
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
2
3
4
3
4
5
19
20
21
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
AN0
RA1/AN1
RA1
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
AN1
RA2/AN2/VREF-
RA2
I/O
TTL
Digital I/O.
AN2
VREF-
I
I
Analog
Analog
Analog input 2.
A/D Reference Voltage (Low) input.
RA3/AN3/VREF+
RA3
5
6
22
I/O
TTL
Digital I/O.
AN3
VREF+
I
I
Analog
Analog
Analog input 3.
A/D Reference Voltage (High) input.
RA4/T0CKI
RA4
6
7
7
8
23
24
I/O
I
ST/OD
ST
Digital I/O. Open drain when configured as output.
Timer0 external clock input.
T0CKI
RA5/AN4/SS/LVDIN
RA5
AN4
SS
I/O
TTL
Analog
ST
Digital I/O.
Analog input 4.
SPI Slave Select input.
Low Voltage Detect Input.
I
I
I
LVDIN
Analog
RA6
See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output
P = Power
OD = Open Drain (no P diode to VDD)
1999-2013 Microchip Technology Inc.
DS39026D-page 13
PIC18CXX2
TABLE 1-3:
PIC18C4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
DIP PLCC TQFP
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.
RB0/INT0
RB0
33
34
35
36
36
37
38
39
8
9
I/O
I
TTL
ST
Digital I/O.
External Interrupt 0.
INT0
RB1/INT1
RB1
I/O
I
TTL
ST
INT1
External Interrupt 1.
RB2/INT2
RB2
10
11
I/O
I
TTL
ST
Digital I/O.
External Interrupt 2.
INT2
RB3/CCP2
RB3
I/O
I/O
TTL
ST
Digital I/O.
CCP2
Capture2 input, Compare2 output, PWM2 output.
RB4
RB5
RB6
37
38
39
41
42
43
14
15
16
I/O
I/O
TTL
TTL
Digital I/O. Interrupt-on-change pin.
Digital I/O. Interrupt-on-change pin.
I/O
I
TTL
ST
Digital I/O. Interrupt-on-change pin.
ICSP programming clock.
RB7
40
44
17
I/O
I/O
TTL
ST
Digital I/O. Interrupt-on-change pin.
ICSP programming data.
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output
P = Power
OD = Open Drain (no P diode to VDD)
DS39026D-page 14
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 1-3:
Pin Name
PIC18C4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Description
Type Type
DIP PLCC TQFP
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC0
15
16
18
32
35
I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
16
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
T1OSI
CCP2
RC2/CCP1
RC2
17
18
19
20
36
37
I/O
I/O
ST
ST
Digital I/O.
CCP1
Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
RC3
I/O
I/O
ST
ST
Digital I/O.
Synchronous serial clock input/output for
SPI mode.
SCK
SCL
I/O
ST
Synchronous serial clock input/output for
I2C mode.
RC4/SDI/SDA
RC4
23
25
42
I/O
I
I/O
ST
ST
ST
Digital I/O.
SDI
SDA
SPI Data In.
I2C Data I/O.
RC5/SDO
RC5
24
25
26
27
43
44
I/O
O
ST
—
Digital I/O.
SPI Data Out.
SDO
RC6/TX/CK
RC6
I/O
O
I/O
ST
—
ST
Digital I/O.
TX
CK
USART Asynchronous Transmit.
USART Synchronous Clock (see related RX/DT).
RC7/RX/DT
RC7
26
29
1
I/O
I
I/O
ST
ST
ST
Digital I/O.
RX
DT
USART Asynchronous Receive.
USART Synchronous Data (see related TX/CK).
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output
P = Power
OD = Open Drain (no P diode to VDD)
1999-2013 Microchip Technology Inc.
DS39026D-page 15
PIC18CXX2
TABLE 1-3:
PIC18C4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
Pin Buffer
Type Type
Pin Name
Description
DIP PLCC TQFP
PORTD is a bi-directional I/O port, or a Parallel Slave Port
(PSP) for interfacing to a microprocessor port. These pins
have TTL input buffers when PSP module is enabled.
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
19
20
21
22
27
28
29
30
21
22
23
24
30
31
32
33
38
39
40
41
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
TTL
Digital I/O.
Parallel Slave Port Data.
ST
TTL
Digital I/O.
Parallel Slave Port Data.
ST
TTL
Digital I/O.
Parallel Slave Port Data.
ST
TTL
Digital I/O.
Parallel Slave Port Data.
ST
TTL
Digital I/O.
Parallel Slave Port Data.
3
ST
TTL
Digital I/O.
Parallel Slave Port Data.
4
ST
TTL
Digital I/O.
Parallel Slave Port Data.
5
ST
Digital I/O.
TTL
Parallel Slave Port Data.
PORTE is a bi-directional I/O port.
RE0/RD/AN5
RE0
8
9
9
25
26
27
I/O
I/O
I/O
ST
TTL
Digital I/O.
RD
Read control for parallel slave port (see also WR
and CS pins).
Analog input 5.
AN5
Analog
RE1/WR/AN6
RE1
10
11
ST
TTL
Digital I/O.
WR
Write control for parallel slave port (see CS
and RD pins).
Analog input 6.
AN6
Analog
RE2/CS/AN7
RE2
10
ST
Digital I/O.
CS
TTL
Chip Select control for parallel slave port (see related
RD and WR).
AN7
VSS
Analog
—
Analog input 7.
12, 31 13, 34 6, 29
11, 32 12, 35 7, 28
P
P
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
VDD
—
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output
P = Power
OD = Open Drain (no P diode to VDD)
DS39026D-page 16
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 2-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
2.0
2.1
OSCILLATOR
CONFIGURATIONS
Ranges Tested:
Oscillator Types
Mode
Freq
C1
C2
The PIC18CXX2 can be operated in eight different
oscillator modes. The user can program three configu-
ration bits (FOSC2, FOSC1, and FOSC0) to select one
of these eight modes:
XT
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF 68 - 100 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
1. LP
Low Power Crystal
2. XT
Crystal/Resonator
These values are for design guidance only.
See notes following this table.
3. HS
High Speed Crystal/Resonator
4. HS + PLL
High Speed Crystal/Resonator
with x 4 PLL enabled
Resonators Used:
455 kHz Panasonic EFO-A455K04B
0.3%
5. RC
External Resistor/Capacitor
2.0 MHz
4.0 MHz
8.0 MHz
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
0.5%
0.5%
0.5%
0.5%
6. RCIO
External Resistor/Capacitor with
RA6 I/O pin enabled
7. EC
External Clock
8. ECIO
External Clock with RA6 I/O pin
enabled
16.0 MHz Murata Erie CSA16.00MX
All resonators used did not have built-in capacitors.
2.2
Crystal Oscillator/Ceramic
Resonators
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
In XT, LP, HS or HS-PLL oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
2: When operating below 3V VDD, it may be
necessary to use high gain HS mode on
lower frequency ceramic resonators.
The PIC18CXX2 oscillator design requires the use of a
parallel cut crystal.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents or verify oscillator performance.
Note: Use of a series cut crystal may give a fre-
quency out of the crystal manufacturers
specifications.
FIGURE 2-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS, XT OR LP
OSC CONFIGURATION)
(1)
C1
OSC1
To
Internal
Logic
(3)
RF
XTAL
SLEEP
(2)
RS
(1)
PIC18CXXX
C2
OSC2
Note 1: See Table 2-1 and Table 2-2 for recom-
mended values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the osc mode chosen.
1999-2013 Microchip Technology Inc.
DS39026D-page 17
PIC18CXX2
TABLE 2-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATORS
FIGURE 2-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP CONFIGURATION)
Ranges Tested:
Mode
Freq
C1
C2
OSC1
Clock from
Ext. System
LP
32.0 kHz
200 kHz
200 kHz
1.0 MHz
4.0 MHz
4.0 MHz
8.0 MHz
33 pF
15 pF
33 pF
15 pF
PIC18CXXX
OSC2
Open
XT
HS
47-68 pF
15 pF
47-68 pF
15 pF
2.3
RC Oscillator
15 pF
15 pF
15 pF
15 pF
For timing insensitive applications, the “RC” and
"RCIO" device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) val-
ues and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit due to
normal process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency, espe-
cially for low CEXT values. The user also needs to take
into account variation due to tolerance of external R
and C components used. Figure 2-3 shows how the
R/C combination is connected.
15-33 pF
15-33 pF
15-33 pF
15-33 pF
20.0
MHz
25.0
MHz
15-33 pF
15-33 pF
These values are for design guidance only.
See notes following this table.
Crystals Used
32.0 kHz
200 kHz
1.0 MHz
4.0 MHz
8.0 MHz
Epson C-001R32.768K-A ± 20 PPM
STD XTL 200.000kHz
ECS ECS-10-13-1
ECS ECS-40-20-1
± 20 PPM
± 50 PPM
± 50 PPM
In the RC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
Epson CA-301 8.000M-C ± 30 PPM
20.0 MHz Epson CA-301 20.000M-C ± 30 PPM
FIGURE 2-3:
RC OSCILLATOR MODE
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
VDD
REXT
Internal
OSC1
2: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
Clock
CEXT
VSS
PIC18CXXX
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents or verify oscillator performance.
OSC2/CLKO
FOSC/4
Recommended values:3 k REXT 100 k
CEXT > 20pF
An external clock source may also be connected to the
OSC1 pin in these modes, as shown in Figure 2-2.
The RCIO oscillator mode functions like the RC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).
DS39026D-page 18
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 2-5:
EXTERNAL CLOCK INPUT
OPERATION
(ECIOCONFIGURATION)
2.4
External Clock Input
The EC and ECIO oscillator modes require an external
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is no oscilla-
tor start-up time required after a Power-on Reset or
after a recovery from SLEEP mode.
OSC1
Clock from
Ext. System
PIC18CXXX
I/O (OSC2)
RA6
In the EC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
oscillator mode.
2.5
HS/PLL
A Phase Locked Loop circuit is provided as a program-
mable option for users that want to multiply the fre-
quency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high frequency crystals.
FIGURE 2-4:
EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
OSC1
Clock from
Ext. System
The PLL can only be enabled when the oscillator con-
figuration bits are programmed for HS mode. If they are
programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
PIC18CXXX
OSC2
FOSC/4
The ECIO oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO oscillator mode.
The PLL is one of the modes of the FOSC<2:0> config-
uration bits. The oscillator mode is specified during
device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called TPLL.
FIGURE 2-6:
PLL BLOCK DIAGRAM
(from Configuration
HS Osc
bit Register)
PLL Enable
Phase
Comparator
FIN
OSC2
Loop
Filter
VCO
Crystal
Osc
SYSCLK
FOUT
Divide by 4
OSC1
1999-2013 Microchip Technology Inc.
DS39026D-page 19
PIC18CXX2
been enabled, the device can switch to a low power
execution mode. Figure 2-7 shows a block diagram of
the system clock sources. The clock switching feature
is enabled by programming the Oscillator Switching
Enable (OSCSEN) bit in Configuration Register1H to a
’0’. Clock switching is disabled in an erased device.
See Section 9.0 for further details of the Timer1 oscilla-
tor. See Section 18.0 for Configuration Register details.
2.6
Oscillator Switching Feature
The PIC18CXX2 devices include a feature that allows
the system clock source to be switched from the main
oscillator to an alternate low frequency clock source.
For the PIC18CXX2 devices, this alternate clock
source is the Timer1 oscillator. If a low frequency crys-
tal (32 kHz, for example) has been attached to the
Timer1 oscillator pins and the Timer1 oscillator has
FIGURE 2-7:
DEVICE CLOCK SOURCES
PIC18CXXX
Main Oscillator
OSC2
TOSC/4
4 x PLL
SLEEP
TOSC
TT1P
TSCLK
OSC1
Timer1 Oscillator
T1OSO
T1OSCEN
Clock
Source
Enable
Oscillator
T1OSI
Clock Source option
for other modules
2.6.1
SYSTEM CLOCK SWITCH BIT
Note: The Timer1 oscillator must be enabled and
operating to switch the system clock
source. The Timer1 oscillator is enabled by
setting the T1OSCEN bit in the Timer1
control register (T1CON). If the Timer1
oscillator is not enabled, then any write to
the SCS bit will be ignored (SCS bit forced
cleared) and the main oscillator will con-
tinue to be the system clock source.
The system clock source switching is performed under
software control. The system clock switch bit, SCS
(OSCCON<0>) controls the clock switching. When the
SCS bit is’0’, the system clock source comes from the
main oscillator that is selected by the FOSC configura-
tion bits in Configuration Register1H. When the SCS bit
is set, the system clock source will come from the
Timer1 oscillator. The SCS bit is cleared on all forms of
RESET.
REGISTER 2-1:
OSCCON REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
SCS
bit 7
bit 0
bit 7-1
bit 0
Unimplemented: Read as '0'
SCS: System Clock Switch bit
When OSCSEN configuration bit = ’0’ and T1OSCEN bit is set:
1= Switch to Timer1 oscillator/clock pin
0= Use primary oscillator/clock input pin
When OSCSEN and T1OSCEN are in other states:
bit is forced clear
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS39026D-page 20
1999-2013 Microchip Technology Inc.
PIC18CXX2
A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is shown in
Figure 2-8. The Timer1 oscillator is assumed to be run-
ning all the time. After the SCS bit is set, the processor
is frozen at the next occurring Q1 cycle. After eight syn-
chronization cycles are counted from the Timer1 oscil-
lator, operation resumes. No additional delays are
required after the synchronization cycles.
2.6.2
OSCILLATOR TRANSITIONS
The PIC18CXX2 devices contain circuitry to prevent
"glitches" when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to. This
ensures that the new clock source is stable and that it’s
pulse width will not be less than the shortest pulse
width of the two clock sources.
FIGURE 2-8:
TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q1 Q2 Q3 Q4 Q1
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
TT1P
1
2
3
4
5
6
7
8
T1OSI
OSC1
Tscs
TOSC
Internal
System
Clock
TDLY
SCS
(OSCCON<0>)
Program
Counter
PC
PC + 2
PC + 4
Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.
The sequence of events that takes place when switch-
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
If the main oscillator is configured for an external crys-
tal (HS, XT, LP), then the transition will take place after
an oscillator start-up time (TOST) has occurred. A timing
diagram indicating the transition from the Timer1 oscil-
lator to the main oscillator for HS, XT and LP modes is
shown in Figure 2-9.
FIGURE 2-9:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q1 Q2 Q3 Q4 Q1 Q2 Q3
Q3
Q4
Q1
TT1P
T1OSI
OSC1
1
2
3
4
5
6
7
8
TOST
TSCS
OSC2
TOSC
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter
PC
PC + 2
PC + 6
Note 1: TOST = 1024TOSC (drawing not to scale).
1999-2013 Microchip Technology Inc.
DS39026D-page 21
PIC18CXX2
If the main oscillator is configured for HS-PLL mode, an
oscillator start-up time (TOST) plus an additional PLL
time-out (TPLL) will occur. The PLL time-out is typically
2 ms and allows the PLL to lock to the main oscillator
frequency. A timing diagram, indicating the transition
from the Timer1 oscillator to the main oscillator for
HS-PLL mode, is shown in Figure 2-10.
FIGURE 2-10:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
TT1P
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q4
Q1
T1OSI
OSC1
TOST
TPLL
OSC2
TSCS
TOSC
PLL Clock
Input
1
2
3
4
5
6
7
8
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter
PC
PC + 2
PC + 4
Note 1: TOST = 1024TOSC (drawing not to scale).
If the main oscillator is configured in the RC, RCIO, EC
or ECIO modes, there is no oscillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram, indi-
cating the transition from the Timer1 oscillator to the
main oscillator for RC, RCIO, EC and ECIO modes, is
shown in Figure 2-11.
FIGURE 2-11:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3
Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
TT1P
T1OSI
OSC1
TOSC
6
1
4
5
7
8
2
3
OSC2
Internal System
Clock
SCS
(OSCCON<0>)
TSCS
Program Counter
PC
PC + 2
PC + 4
Note 1: RC oscillator mode assumed.
DS39026D-page 22
1999-2013 Microchip Technology Inc.
PIC18CXX2
switching currents have been removed, SLEEP mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during SLEEP will increase the current
consumed during SLEEP. The user can wake from
SLEEP through external RESET, Watchdog Timer
Reset, or through an interrupt.
2.7
Effects of SLEEP Mode on the
On-chip Oscillator
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
TABLE 2-3:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC Mode
OSC1 Pin
OSC2 Pin
RC
Floating, external resistor should
pull high
At logic low
RCIO
Floating, external resistor should
pull high
Configured as PORTA, bit 6
ECIO
EC
Floating
Floating
Configured as PORTA, bit 6
At logic low
LP, XT, and HS
Feedback inverter disabled, at
quiescent voltage level
Feedback inverter disabled, at
quiescent voltage level
Note: See Table 3-1, in Section 3.0 RESET, for time-outs due to SLEEP and MCLR Reset.
With the PLL enabled (HS/PLL oscillator mode), the
2.8
Power-up Delays
time-out sequence following a Power-on Reset is differ-
ent from other oscillator modes. The time-out sequence
is as follows: First, the PWRT time-out is invoked after
a POR time delay has expired. Then, the Oscillator
Start-up Timer (OST) is invoked. However, this is still
not a sufficient amount of time to allow the PLL to lock
at high frequencies. The PWRT timer is used to provide
an additional fixed 2ms (nominal) time-out to allow the
PLL ample time to lock to the incoming clock frequency.
Power up delays are controlled by two timers, so that
no external RESET circuitry is required for most appli-
cations. The delays ensure that the device is kept in
RESET until the device power supply and clock are sta-
ble. For additional information on RESET operation,
see the “RESET” section.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer, OST, intended to keep the
chip in RESET until the crystal oscillator is stable.
1999-2013 Microchip Technology Inc.
DS39026D-page 23
PIC18CXX2
NOTES:
DS39026D-page 24
1999-2013 Microchip Technology Inc.
PIC18CXX2
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
RESET situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
RESET. See Table 3-3 for a full description of the
RESET states of all registers.
3.0
RESET
The PIC18CXX2 differentiates between various kinds
of RESET:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during SLEEP
d) Watchdog Timer (WDT) Reset (during normal
operation)
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
e) Programmable Brown-out Reset (BOR)
f) RESETInstruction
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
g) Stack Full Reset
h) Stack Underflow Reset
MCLR pin is not driven low by any internal RESETS,
including WDT.
Most registers are unaffected by a RESET. Their status
is unknown on POR and unchanged by all other
RESETS. The other registers are forced to a “RESET
state” on Power-on Reset, MCLR, WDT Reset, Brown-
out Reset, MCLR Reset during SLEEP, and by the
RESETinstruction.
FIGURE 3-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
External Reset
MCLR
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
S
BOREN
OST/PWRT
OST
10-bit Ripple Counter
Chip_Reset
Q
R
OSC1
PWRT
10-bit Ripple Counter
On-chip
RC OSC(1)
Enable PWRT
(2)
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: See Table 3-1 for time-out situations.
1999-2013 Microchip Technology Inc.
DS39026D-page 25
PIC18CXX2
3.1
Power-on Reset (POR)
3.3
Oscillator Start-up Timer (OST)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected. To take advantage of the POR cir-
cuitry, just tie the MCLR pin directly (or through a resis-
tor) to VDD. This will eliminate external RC components
usually needed to create a Power-on Reset delay. A
minimum rise rate for VDD is specified (parameter
D004). For a slow rise time, see Figure 3-2.
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
When the device starts normal operation (i.e., exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in reset until the operating condi-
tions are met.
3.4
PLL Lock Time-out
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to pro-
vide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(TPLL) is typically 2 ms and follows the oscillator start-
up time-out (OST).
FIGURE 3-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
3.5
Brown-out Reset (BOR)
VDD
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation will reset
the chip. A RESET may not occur if VDD falls below
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until VDD rises above
BVDD. The Power-up Timer will then be invoked and
will keep the chip in RESET an additional time delay
(parameter #33). If VDD drops below BVDD while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be initial-
ized. Once VDD rises above BVDD, the Power-up Timer
will execute the additional time delay.
D
R
R1
MCLR
PIC18CXXX
C
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 k is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3.6
Time-out Sequence
3: R1 = 100 to 1 k will limit any current flow-
ing into MCLR from external capacitor C in
the event of MCLR/VPP pin breakdown, due
to Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
3.2
Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in reset as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an accept-
able level. A configuration bit is provided to enable/
disable the PWRT.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18CXXX device oper-
ating in parallel.
Table 3-2 shows the RESET conditions for some
Special Function Registers, while Table 3-3 shows the
RESET conditions for all the registers.
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See DC
parameter #33 for details.
DS39026D-page 26
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 3-1:
Oscillator
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2)
Wake-up from
SLEEP or
Oscillator Switch
Brown-out(2)
Configuration
PWRTE = 0
PWRTE = 1
72 ms + 1024TOSC
+ 2ms
1024TOSC
+ 2 ms
72 ms + 1024TOSC
+ 2ms
HS with PLL enabled(1)
1024TOSC + 2 ms
HS, XT, LP
EC
72 ms + 1024TOSC
72 ms
1024TOSC
72 ms + 1024TOSC
72 ms
1024TOSC
—
—
—
—
External RC
72 ms
72 ms
Note 1: 2 ms is the nominal time required for the 4x PLL to lock.
2: 72 ms is the nominal Power-up Timer delay.
REGISTER 3-1:
RCON REGISTER BITS AND POSITIONS
R/W-0
IPEN
R/W-0
LWRT
U-0
—
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
Note: See Register 4-3 on page 53 for bit definitions.
TABLE 3-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
RCON
Register
Condition
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset
0000h
0000h
00-1 1100
00-u uuuu
1
u
1
u
1
u
0
u
0
u
u
u
u
u
MCLR Reset during normal
operation
Software Reset during normal
operation
0000h
0000h
0000h
0u-0 uuuu
0u-u uu11
0u-u uu11
0
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
1
u
1
u
Stack Full Reset during normal
operation
Stack Underflow Reset during
normal operation
MCLR Reset during SLEEP
WDT Reset
0000h
0000h
00-u 10uu
0u-u 01uu
uu-u 00uu
0u-1 11u0
uu-u 00uu
u
1
u
1
u
1
0
0
1
1
0
1
0
1
0
u
u
u
1
u
u
u
u
0
u
u
u
u
u
u
u
u
u
u
u
WDT Wake-up
PC + 2
0000h
PC + 2(1)
Brown-out Reset
Interrupt wake-up from SLEEP
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
1999-2013 Microchip Technology Inc.
DS39026D-page 27
PIC18CXX2
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
TOSU
TOSH
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
N/A
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
1111 -1-1
11-0 0-00
N/A
---0 uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
uu-u uuuu(3)
---u uuuu
uuuu uuuu
PC + 2(2)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu -u-u(1)
uu-u u-uu(1)
N/A
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU 242 442 252 452
TBLPTRH 242 442 252 452
TBLPTRL
TABLAT
PRODH
PRODL
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
INTCON
INTCON2
INTCON3
INDF0
POSTINC0 242 442 252 452
POSTDEC0 242 442 252 452
N/A
N/A
N/A
N/A
N/A
N/A
PREINC0
PLUSW0
FSR0H
FSR0L
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
xxxx xxxx
N/A
---- 0000
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
WREG
INDF1
POSTINC1 242 442 252 452
POSTDEC1 242 442 252 452
N/A
N/A
N/A
N/A
N/A
N/A
PREINC1
PLUSW1
242 442 252 452
242 442 252 452
N/A
N/A
N/A
N/A
N/A
N/A
Legend: u = unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’.
DS39026D-page 28
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESET Instruction
Stack Resets
FSR1H
FSR1L
BSR
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
---- 0000
xxxx xxxx
---- 0000
N/A
---- 0000
uuuu uuuu
---- 0000
N/A
---- uuuu
uuuu uuuu
---- uuuu
N/A
INDF2
POSTINC2 242 442 252 452
POSTDEC2 242 442 252 452
N/A
N/A
N/A
N/A
N/A
N/A
PREINC2
PLUSW2
FSR2H
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
1111 1111
---- ---0
--00 0101
---- ---0
00-1 11q0
xxxx xxxx
xxxx xxxx
0-00 0000
xxxx xxxx
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
---- 0000
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
1111 1111
---- ---0
--00 0101
---- ---0
00-1 qquu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ---u
--uu uuuu
---- ---u
uu-u qquu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
RCON(4, 6) 242 442 252 452
TMR1H
TMR1L
T1CON
TMR2
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1 242 442 252 452
SSPCON2 242 442 252 452
Legend: u = unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’.
1999-2013 Microchip Technology Inc.
DS39026D-page 29
PIC18CXX2
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
ADRESH
ADRESL
ADCON0
ADCON1
CCPR1H
CCPR1L
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
xxxx xxxx
xxxx xxxx
0000 0000
--0- 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 -01x
0000 000x
---- 1111
---- 0000
---- 0000
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
uuuu uuuu
uuuu uuuu
0000 0000
--0- 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 -01u
0000 000u
---- 1111
---- 0000
---- 0000
1111 1111
-111 1111
0000 0000
-000 0000
0000 0000
-000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
--u- uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
---- uuuu
---- uuuu(1)
---- uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu(1)
-uuu uuuu(1)
uuuu uuuu
-uuu uuuu
CCP1CON 242 442 252 452
CCPR2H
CCPR2L
242 442 252 452
242 442 252 452
CCP2CON 242 442 252 452
TMR3H
TMR3L
T3CON
SPBRG
RCREG
TXREG
TXSTA
RCSTA
IPR2
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
PIR2
PIE2
IPR1
PIR1
PIE1
Legend: u = unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’.
DS39026D-page 30
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESET Instruction
Stack Resets
TRISE
TRISD
TRISC
TRISB
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
0000 -111
1111 1111
1111 1111
1111 1111
-111 1111(5)
---- -xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx(5)
---- -000
xxxx xxxx
xxxx xxxx
xxxx xxxx
-x0x 0000(5)
0000 -111
1111 1111
1111 1111
1111 1111
-111 1111(5)
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
---- -000
uuuu uuuu
uuuu uuuu
uuuu uuuu
-u0u 0000(5)
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
TRISA(5, 7) 242 442 252 452
LATE
LATD
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
LATC
LATB
LATA(5, 7)
PORTE
PORTD
PORTC
PORTB
PORTA(5, 7) 242 442 252 452
Legend: u = unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’.
1999-2013 Microchip Technology Inc.
DS39026D-page 31
PIC18CXX2
FIGURE 3-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 3-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 3-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
DS39026D-page 32
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 3-6:
SLOW RISE TIME (MCLR TIED TO VDD)
5V
1V
0V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 3-7:
TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
IINTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
TPLL
PLL TIME-OUT
INTERNAL RESET
Note: TOST = 1024 clock cycles.
TPLL 2 ms max. First three stages of the PWRT timer.
1999-2013 Microchip Technology Inc.
DS39026D-page 33
PIC18CXX2
NOTES:
DS39026D-page 34
1999-2013 Microchip Technology Inc.
PIC18CXX2
4.0
MEMORY ORGANIZATION
There are two memory blocks in Enhanced MCU
devices. These memory blocks are:
• Program Memory
• Data Memory
Program and data memory use separate buses so that
concurrent access can occur.
4.1
Program Memory Organization
A 21-bit program counter is capable of addressing the
2-Mbyte program memory space. Accessing a location
between the physically implemented memory and the
2-Mbyte address will cause a read of all ’0’s (a NOP
instruction).
PIC18C252 and PIC18C452 have 32 Kbytes of
EPROM, while PIC18C242 and PIC18C442 have
16 Kbytes of EPROM. This means that PIC18CX52
devices can store up to 16K of single word instructions,
and PIC18CX42 devices can store up to 8K of single
word instructions.
The RESET vector address is at 0000h and the inter-
rupt vector addresses are at 0008h and 0018h.
Figure 4-1 shows the Program Memory Map for
PIC18C242/442 devices and Figure 4-2 shows the
Program Memory Map for PIC18C252/452 devices.
1999-2013 Microchip Technology Inc.
DS39026D-page 35
PIC18CXX2
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK FOR
PIC18C442/242
FIGURE 4-2:
PROGRAM MEMORY MAP
AND STACK FOR
PIC18C452/252
PC<20:0>
PC<20:0>
21
21
CALL,RCALL,RETURN
RETFIE,RETLW
CALL,RCALL,RETURN
RETFIE,RETLW
Stack Level 1
Stack Level 1
Stack Level 31
RESET Vector
Stack Level 31
RESET Vector
0000h
0000h
High Priority Interrupt Vector
Low Priority Interrupt Vector
High Priority Interrupt Vector
Low Priority Interrupt Vector
0008h
0018h
0008h
0018h
On-chip
Program Memory
3FFFh
4000h
On-chip
Program Memory
7FFFh
8000h
Read '0'
Read '0'
1FFFFFh
200000h
1FFFFFh
200000h
DS39026D-page 36
1999-2013 Microchip Technology Inc.
PIC18CXX2
4.2.2
RETURN STACK POINTER
(STKPTR)
4.2
Return Address Stack
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALLor RCALLinstruction is executed, or an interrupt
is acknowledged. The PC value is pulled off the stack
on a RETURN, RETLW or a RETFIE instruction.
PCLATUand PCLATHare not affected by any of the call
or return instructions.
The STKPTR register contains the stack pointer value,
the STKFUL (stack full) status bit, and the STKUNF
(stack underflow) status bits. Register 4-1 shows the
STKPTR register. The value of the stack pointer can be
0 through 31. The stack pointer increments when val-
ues are pushed onto the stack and decrements when
values are popped off the stack. At RESET, the stack
pointer value will be 0. The user may read and write the
stack pointer value. This feature can be used by a Real
Time Operating System for return stack maintenance.
The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, with the stack pointer initialized to
00000b after all RESETS. There is no RAM associated
with stack pointer 00000b. This is only a RESET value.
During a CALLtype instruction causing a push onto the
stack, the stack pointer is first incremented and the
RAM location pointed to by the stack pointer is written
with the contents of the PC. During a RETURN type
instruction causing a pop from the stack, the contents
of the RAM location pointed to by the STKPTR is trans-
ferred to the PC and then the stack pointer is
decremented.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit can only be cleared in software or
by a POR.
The action that takes place when the stack becomes
full, depends on the state of the STVREN (Stack Over-
flow Reset Enable) configuration bit. Refer to
Section 18.0 for a description of the device configura-
tion bits. If STVREN is set (default), the 31st push will
push the (PC + 2) value onto the stack, set the STKFUL
bit, and reset the device. The STKFUL bit will remain
set and the stack pointer will be set to 0.
The stack space is not part of either program or data
space. The stack pointer is readable and writable, and
the address on the top of the stack is readable and writ-
able through SFR registers. Data can also be pushed
to, or popped from, the stack, using the top-of-stack
SFRs. Status bits indicate if the stack pointer is at, or
beyond the 31 levels provided.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at 0. The STKUNF bit will remain set
until cleared in software or a POR occurs.
4.2.1
TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL hold the
contents of the stack location pointed to by the
STKPTR register. This allows users to implement a
software stack, if necessary. After a CALL, RCALLor
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
values can be placed on a user defined software stack.
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
Note: Returning a value of zero to the PC on an
underflow, has the effect of vectoring the
program to the RESET vector, where the
stack conditions can be verified and appro-
priate actions can be taken.
The user must disable the global interrupt enable bits
during this time to prevent inadvertent stack opera-
tions..
1999-2013 Microchip Technology Inc.
DS39026D-page 37
PIC18CXX2
REGISTER 4-1:
STKPTR REGISTER
R/C-0 R/C-0
U-0
—
R/W-0
SP4
R/W-0
SP3
R/W-0
SP2
R/W-0
SP1
R/W-0
SP0
STKFUL STKUNF
bit 7
bit 0
bit 7(1)
bit 6(1)
STKFUL: Stack Full Flag bit
1= Stack became full or overflowed
0= Stack has not become full or overflowed
STKUNF: Stack Underflow Flag bit
1= Stack underflow occurred
0= Stack underflow did not occur
Unimplemented: Read as '0'
bit 5
bit 4-0
SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
FIGURE 4-3:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack
11111
11110
11101
STKPTR<4:0>
00010
TOSU
0x00
TOSH
0x1A
TOSL
0x34
00011
0x001A34 00010
0x000D58 00001
00000
Top-of-Stack
4.2.3
PUSH AND POP INSTRUCTIONS
4.2.4
STACK FULL/UNDERFLOW RESETS
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program execu-
tion, is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the stack pointer and load the cur-
rent PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place a return address on the
stack.
These resets are enabled by programming the
STVREN configuration bit. When the STVREN bit is
disabled, a full or underflow condition will set the appro-
priate STKFUL or STKUNF bit, but not cause a device
RESET. When the STVREN bit is enabled, a full or
underflow will set the appropriate STKFUL or STKUNF
bit and then cause a device RESET. The STKFUL or
STKUNF bits are only cleared by the user software or
a POR Reset.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POPinstruction. The POPinstruc-
tion discards the current TOS by decrementing the
stack pointer. The previous value pushed onto the
stack then becomes the TOS value.
DS39026D-page 38
1999-2013 Microchip Technology Inc.
PIC18CXX2
4.3
Fast Register Stack
4.4
PCL, PCLATH and PCLATU
A "fast interrupt return" option is available for interrupts.
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers and are only one in depth.
The stack is not readable or writable and is loaded with
the current value of the corresponding register when
the processor vectors for an interrupt. The values in the
registers are then loaded back into the working regis-
ters, if the FAST RETURNinstruction is used to return
from the interrupt.
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<15:8>
bits and is not directly readable or writable. Updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits and is not directly
readable or writable. Updates to the PCU register may
be performed through the PCLATU register.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the stack register values stored by the low priority inter-
rupt will be overwritten.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of PCL is fixed to a value of ’0’.
The PC increments by 2 to address sequential instruc-
tions in the program memory.
If high priority interrupts are not disabled during low pri-
ority interrupts, users must save the key registers in
software during a low priority interrupt.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
If no interrupts are used, the fast register stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the fast register
stack for a subroutine call, a FAST CALL instruction
must be executed.
The contents of PCLATH and PCLATU will be trans-
ferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the pro-
gram counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 4.8.1).
Example 4-1 shows a source code example that uses
the fast register stack.
4.5
Clocking Scheme/Instruction
Cycle
EXAMPLE 4-1:
FAST REGISTER STACK
CODE EXAMPLE
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 4-4.
CALL SUB1, FAST
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
RETURN FAST
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
FIGURE 4-4:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
Phase
Clock
Q4
PC
PC
PC+2
PC+4
OSC2/CLKOUT
(RC mode)
Execute INST (PC-2)
Fetch INST (PC)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+2)
Fetch INST (PC+4)
1999-2013 Microchip Technology Inc.
DS39026D-page 39
PIC18CXX2
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
4.6
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO),
then two cycles are required to complete the instruction
(Example 4-2).
In the execution cycle, the fetched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
EXAMPLE 4-2:
INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
2. MOVWF PORTB
3. BRA SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush (NOP)
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
The CALLand GOTOinstructions have an absolute pro-
4.7
Instructions in Program Memory
gram memory address embedded into the instruction.
Since instructions are always stored on word bound-
aries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 4-5 shows how the
instruction “GOTO 000006h” is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner.
The offset value stored in a branch instruction repre-
sents the number of single word instructions that the
PC will be offset by. Section 19.0 provides further
details of the instruction set.
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB =’0’). Figure 4-5 shows an
example of how instruction words are stored in the pro-
gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ’0’ (see Section 4.4).
FIGURE 4-5:
INSTRUCTIONS IN PROGRAM MEMORY
Word Address
LSB = 1
LSB = 0
Program Memory
Byte Locations
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
Instruction 1:
Instruction 2:
0Fh
EFh
F0h
C1h
F4h
55h
03h
00h
23h
56h
MOVLW
GOTO
055h
000006h
Instruction 3:
MOVFF
123h, 456h
DS39026D-page 40
1999-2013 Microchip Technology Inc.
PIC18CXX2
second word of the instruction is executed by itself (first
word was skipped), it will execute as a NOP. This action
is necessary when the two-word instruction is preceded
by a conditional instruction that changes the PC. A pro-
gram example that demonstrates this concept is shown
in Example 4-3. Refer to Section 19.0 for further details
of the instruction set.
4.7.1
TWO-WORD INSTRUCTIONS
The PIC18CXX2 devices have four two-word instruc-
tions: MOVFF, CALL, GOTOand LFSR. The second
word of these instructions has the 4 MSBs set to 1’s
and is a special kind of NOPinstruction. The lower 12-
bits of the second word contain data to be used by the
instruction. If the first word of the instruction is exe-
cuted, the data in the second word is accessed. If the
EXAMPLE 4-3:
TWO-WORD INSTRUCTIONS
CASE 1:
Object Code
Source Code
TSTFSZ
MOVFF
REG1
; is RAM location 0?
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
CASE 2:
REG1, REG2 ; No, execute 2-word instruction
; 2nd operand holds address of REG2
ADDWF
REG3
REG1
; continue code
Object Code
Source Code
TSTFSZ
; is RAM location 0?
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
MOVFF
REG1, REG2 ; Yes
; 2nd operand becomes NOP
ADDWF
REG3
; continue code
4.8.2
TABLE READS/TABLE WRITES
4.8
Lookup Tables
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Lookup tables are implemented two ways. These are:
• Computed GOTO
• Table Reads
Lookup table data may be stored 2 bytes per program
word by using table reads and writes. The table pointer
(TBLPTR) specifies the byte address and the table
latch (TABLAT) contains the data that is read from, or
written to program memory. Data is transferred to/from
program memory one byte at a time.
4.8.1
COMPUTED GOTO
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL).
A lookup table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table, before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCLinstruction. The next
instruction executed will be one of the RETLW 0xnn
instructions that returns the value 0xnn to the calling
function.
A description of the Table Read/Table Write operation
is shown in Section 5.0.
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
1999-2013 Microchip Technology Inc.
DS39026D-page 41
PIC18CXX2
4.9.1
GENERAL PURPOSE REGISTER
FILE
4.9
Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 4-6
and Figure 4-7 show the data memory organization for
the PIC18CXX2 devices.
The register file can be accessed either directly, or indi-
rectly. Indirect addressing operates using the File
Select Registers (FSRn) and corresponding Indirect
File Operand (INDFn). The operation of indirect
addressing is shown in Section 4.12.
The data memory map is divided into as many as 16
banks that contain 256 bytes each. The lower 4 bits of
the Bank Select Register (BSR<3:0>) select which
bank will be accessed. The upper 4 bits for the BSR are
not implemented.
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other RESETS.
Data RAM is available for use as GPR registers by all
instructions. The top half of bank 15 (0xF80 to 0xFFF)
contains SFRs. All other banks of data memory contain
GPR registers, starting with bank 0.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratch pad operations in the user’s appli-
cation. The SFRs start at the last location of Bank 15
(0xFFF) and extend downwards. Any remaining space
beyond the SFRs in the Bank may be implemented as
GPRs. GPRs start at the first location of Bank 0 and
grow upwards. Any read of an unimplemented location
will read as ’0’s.
4.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and Peripheral Modules for control-
ling the desired operation of the device. These regis-
ters are implemented as static RAM. A list of these
registers is given in Table 4-1 and Table 4-2.
The SFRs can be classified into two sets; those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The entire data memory may be accessed directly, or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSRn) and corresponding Indirect
File Operand (INDFn). Each FSR holds a 12-bit
address value that can be used to access any location
in the Data Memory map without banking.
The SFRs are typically distributed among the peripher-
als whose functions they control.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing or by the use of the MOVFFinstruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
The unused SFR locations will be unimplemented and
read as '0's. See Table 4-1 for addresses for the SFRs.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 4.10 pro-
vides a detailed description of the Access RAM.
DS39026D-page 42
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 4-6:
BSR<3:0>
DATA MEMORY MAP FOR PIC18C242/442
Data Memory Map
000h
07Fh
080h
0FFh
100h
00h
Access RAM
GPR
= 0000b
= 0001b
Bank 0
Bank 1
FFh
00h
GPR
1FFh
200h
FFh
Access Bank
00h
Access RAM low
7Fh
80h
= 0010b
= 1110b
Access RAM high
FFh
Bank 2
to
Bank 14
Unused
Read ’00h’
(SFR’s)
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
EFFh
F00h
F7Fh
F80h
FFFh
00h
FFh
Unused
SFR
= 1111b
Bank 15
When a = 1,
the BSR is used to specify the
RAM location that the instruc-
tion uses.
1999-2013 Microchip Technology Inc.
DS39026D-page 43
PIC18CXX2
FIGURE 4-7:
DATA MEMORY MAP FOR PIC18C252/452
BSR<3:0>
Data Memory Map
000h
07Fh
080h
0FFh
00h
Access RAM
GPR
= 0000b
Bank 0
FFh
00h
100h
= 0001b
= 0010b
GPR
GPR
Bank 1
Bank 2
Bank 3
1FFh
200h
FFh
00h
2FFh
300h
FFh
00h
= 0011b
= 0100b
= 0101b
GPR
FFh
3FFh
400h
Access Bank
Bank 4
Bank 5
GPR
GPR
4FFh
500h
00h
7Fh
80h
Access RAM low
00h
FFh
Access RAM high
(SFR’s)
FFh
5FFh
600h
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
= 0110b
= 1110b
Bank 6
to
Bank 14
Unused
Read ’00h’
EFFh
F00h
F7Fh
F80h
FFFh
00h
FFh
Unused
SFR
= 1111b
Bank 15
When a = 1,
the BSR is used to specify the
RAM location that the instruc-
tion uses.
DS39026D-page 44
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 4-1:
SPECIAL FUNCTION REGISTER MAP
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
FEEh
FEDh
FECh
FEBh
FEAh
FE9h
FE8h
FE7h
FE6h
FE5h
FE4h
FE3h
FE2h
FE1h
FE0h
TOSU
TOSH
FDFh
FDEh
FDDh
FDCh
FDBh
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
INDF2(3)
POSTINC2(3)
POSTDEC2(3)
PREINC2(3)
PLUSW2(3)
FSR2H
FBFh
FBEh
FBDh
FBCh
FBBh
FBAh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
—
F9Fh
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
IPR1
PIR1
PIE1
—
TOSL
STKPTR
PCLATU
PCLATH
PCL
—
—
FSR2L
—
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
STATUS
TMR0H
—
—
—
—
TMR0L
—
TRISE(2)
TRISD(2)
TRISC
TRISB
TRISA
—
T0CON
—
PRODH
—
—
PRODL
OSCCON
LVDCON
WDTCON
RCON
TMR3H
TMR3L
T3CON
—
INTCON
INTCON2
INTCON3
INDF0(3)
POSTINC0(3)
POSTDEC0(3)
PREINC0(3)
PLUSW0(3)
FSR0H
—
TMR1H
SPBRG
RCREG
TXREG
TXSTA
RCSTA
—
—
TMR1L
—
T1CON
LATE(2)
LATD(2)
LATC
LATB
LATA
—
TMR2
PR2
T2CON
FSR0L
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
—
—
WREG
—
INDF1(3)
POSTINC1(3)
POSTDEC1(3)
PREINC1(3)
PLUSW1(3)
FSR1H
—
—
—
—
—
—
—
PORTE(2)
PORTD(2)
PORTC
PORTB
PORTA
—
IPR2
PIR2
PIE2
FSR1L
BSR
Note 1: Unimplemented registers are read as ’0’.
2: This register is not available on PIC18C2X2 devices.
3: This is not a physical register.
1999-2013 Microchip Technology Inc.
DS39026D-page 45
PIC18CXX2
TABLE 4-2:
REGISTER FILE SUMMARY
Value on
POR,
BOR
Details
on page:
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
---0 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
N/A
37
37
37
38
39
39
39
57
57
57
57
61
61
65
66
67
50
50
50
50
50
TOSH
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
TOSL
STKPTR
PCLATU
PCLATH
PCL
STKFUL
—
STKUNF
—
—
—
Return Stack Pointer
Holding Register for PC<20:16>
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
—
—
bit21(2)
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
GIE/GIEH PEIE/GIEL
TMR0IE
INTEDG1
—
INT0IE
INTEDG2
INT2IE
RBIE
—
TMR0IF
TMR0IP
—
INT0IF
—
RBIF
RBIP
RBPU
INTEDG0
INT1IP
INT2IP
INT1IE
INT2IF
INT1IF
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register)
POSTINC0
N/A
POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register)
N/A
PREINC0
PLUSW0
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)
N/A
Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) -
value of FSR0 offset by value in WREG
N/A
FSR0H
FSR0L
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
---- 0000
xxxx xxxx
xxxx xxxx
N/A
50
50
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
WREG
INDF1
Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register)
50
50
50
50
50
POSTINC1
N/A
POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register)
N/A
PREINC1
PLUSW1
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register)
N/A
Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) -
value of FSR1 offset by value in WREG
N/A
FSR1H
FSR1L
BSR
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
---- 0000
xxxx xxxx
---- 0000
N/A
50
50
49
50
50
50
50
50
Indirect Data Memory Address Pointer 1 Low Byte
—
—
—
—
Bank Select Register
INDF2
Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register)
POSTINC2
N/A
POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register)
N/A
PREINC2
PLUSW2
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register)
N/A
Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) -
value of FSR2 offset by value in WREG
N/A
FSR2H
FSR2L
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
---- 0000
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
---- ---0
--00 0101
50
50
52
95
95
93
20
175
Indirect Data Memory Address Pointer 2 Low Byte
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
Legend:
—
—
—
N
OV
Z
DC
C
Timer0 Register High Byte
Timer0 Register Low Byte
TMR0ON
T08BIT
—
T0CS
—
T0SE
—
PSA
—
T0PS2
—
T0PS1
—
T0PS0
SCS
—
—
—
IRVST
LVDEN
LVDL3
LVDL2
LVDL1
LVDL0
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only, and read '0' in all other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
DS39026D-page 46
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 4-2:
REGISTER FILE SUMMARY (CONTINUED)
Value on
Details
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
on page:
WDTCON
RCON
—
—
—
—
—
RI
—
—
—
SWDTE
BOR
---- ---0
0q-1 11qq
183
IPEN
LWRT
TO
PD
POR
53, 56,
74
TMR1H
Timer1 Register High Byte
Timer1 Register Low Byte
xxxx xxxx
xxxx xxxx
0-00 0000
0000 0000
1111 1111
97
97
TMR1L
T1CON
RD16
—
T1CKPS1
TOUTPS2
T1CKPS0
TOUTPS1
T1OSCEN
TOUTPS0
T1SYNC
TMR2ON
TMR1CS
T2CKPS1
TMR1ON
97
TMR2
Timer2 Register
101
PR2
Timer2 Period Register
TOUTPS3
102
T2CON
—
T2CKPS0 -000 0000
xxxx xxxx
101
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
TMR3H
SSP Receive Buffer/Transmit Register
SSP Address Register in I2C Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode.
121
0000 0000
128
SMP
WCOL
GCEN
CKE
D/A
P
S
R/W
SSPM2
PEN
UA
BF
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 00-0
00-- 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
116
SSPOV
ACKSTAT
SSPEN
ACKDT
CKP
SSPM3
RCEN
SSPM1
RSEN
SSPM0
SEN
118
ACKEN
120
A/D Result Register High Byte
A/D Result Register Low Byte
171,172
171,172
165
ADCS1
ADFM
ADCS0
ADCS2
CHS2
—
CHS1
—
CHS0
GO/DONE
PCFG2
—
ADON
PCFG3
PCFG1
PCFG0
166
Capture/Compare/PWM Register1 High Byte
Capture/Compare/PWM Register1 Low Byte
111, 113
111, 113
107
—
—
DC1B1
DC1B0
CCP1M3
CCP2M3
T3CCP1
CCP1M2
CCP2M2
T3SYNC
CCP1M1
CCP2M1
TMR3CS
CCP1M0
CCP2M0
TMR3ON
Capture/Compare/PWM Register2 High Byte
Capture/Compare/PWM Register2 Low Byte
111, 113
111, 113
107
—
—
DC2B1
DC2B0
Timer3 Register High Byte
Timer3 Register Low Byte
103
TMR3L
103
T3CON
RD16
T3CCP2
T3CKPS1
T3CKPS0
103
SPBRG
USART1 Baud Rate Generator
USART1 Receive Register
151
158,161,
163
RCREG
TXREG
0000 0000
0000 0000
156,159,
162
USART1 Transmit Register
TXSTA
RCSTA
CSRC
SPEN
TX9
RX9
TXEN
SREN
SYNC
CREN
—
BRGH
FERR
TRMT
OERR
TX9D
RX9D
0000 -010
0000 000x
149
150
ADDEN
Legend:
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only, and read '0' in all other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
1999-2013 Microchip Technology Inc.
DS39026D-page 47
PIC18CXX2
TABLE 4-2:
REGISTER FILE SUMMARY (CONTINUED)
Value on
POR,
BOR
Details
on page:
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IPR2
—
—
—
—
—
—
—
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
—
LVDIP
LVDIF
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
CCP2IP
CCP2IF
CCP2IE
TMR1IP
TMR1IF
TMR1IE
---- 1111
---- 0000
---- 0000
1111 1111
0000 0000
0000 0000
0000 -111
1111 1111
1111 1111
1111 1111
-111 1111
---- -xxx
73
69
71
72
68
70
88
85
83
80
77
87
PIR2
—
PIE2
—
—
—
—
LVDIE
IPR1
PSPIP
PSPIF
PSPIE
IBF
ADIP
ADIF
ADIE
OBF
RCIP
RCIF
RCIE
IBOV
TXIP
TXIF
TXIE
PSPMODE
CCP1IP
CCP1IF
CCP1IE
PIR1
PIE1
TRISE
TRISD
TRISC
TRISB
TRISA
LATE
Data Direction bits for PORTE
Data Direction Control Register for PORTD
Data Direction Control Register for PORTC
Data Direction Control Register for PORTB
—
—
TRISA6(1)
Data Direction Control Register for PORTA
—
—
—
—
Read PORTE Data Latch,
Write PORTE Data Latch
LATD
Read PORTD Data Latch, Write PORTD Data Latch
Read PORTC Data Latch, Write PORTC Data Latch
Read PORTB Data Latch, Write PORTB Data Latch
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
---- -000
xxxx xxxx
xxxx xxxx
xxxx xxxx
-x0x 0000
85
83
80
77
87
85
83
80
77
LATC
LATB
LATA
—
LATA6(1)
Read PORTA Data Latch, Write PORTA Data Latch(1)
PORTE
PORTD
PORTC
PORTB
PORTA
Read PORTE pins, Write PORTE Data Latch
Read PORTD pins, Write PORTD Data Latch
Read PORTC pins, Write PORTC Data Latch
Read PORTB pins, Write PORTB Data Latch
—
RA6(1)
Read PORTA pins, Write PORTA Data Latch(1)
Legend:
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only, and read '0' in all other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
DS39026D-page 48
1999-2013 Microchip Technology Inc.
PIC18CXX2
can be accessed without any software overhead. This
is useful for testing status flags and modifying control
bits.
4.10
Access Bank
The Access Bank is an architectural enhancement,
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
4.11 Bank Select Register (BSR)
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
This data memory region can be used for:
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ’0’s, and
writes will have no effect.
• Faster evaluation/control of SFRs (no banking)
The Access Bank is comprised of the upper 128 bytes
in Bank 15 (SFRs) and the lower 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 4-6
and Figure 4-7 indicate the Access RAM areas.
A MOVLBinstruction has been provided in the instruc-
tion set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all '0's and all writes are ignored. The
STATUS register bits will be set/cleared as appropriate
for the instruction performed.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted by the ’a’ bit (for
access bit).
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
When forced in the Access Bank (a = ’0’), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function registers, so that these registers
A MOVFFinstruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
FIGURE 4-8:
DIRECT ADDRESSING
Direct Addressing
(3)
From Opcode
BSR<3:0>
7
0
(2)
(3)
Bank Select
Location Select
00h
01h
100h
0Eh
E00h
0Fh
F00h
000h
Data
Memory(1)
0FFh
1FFh
EFFh
FFFh
Bank 0
Bank 1
Bank 14 Bank 15
Note 1: For register file map detail, see Table 4-1.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the reg-
isters of the Access Bank.
3: The MOVFFinstruction embeds the entire 12-bit address in the instruction.
1999-2013 Microchip Technology Inc.
DS39026D-page 49
PIC18CXX2
If INDF0, INDF1 or INDF2 are read indirectly via an
FSR, all '0's are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivalent to a NOPinstruction and the
STATUS bits are not affected.
4.12 Indirect Addressing, INDF and
FSR Registers
Indirect addressing is a mode of addressing data mem-
ory, where the data memory address in the instruction
is not fixed. An FSR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 4-9
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address,
specified by the value of the FSR register.
4.12.1
INDIRECT ADDRESSING
OPERATION
Each FSR register has an INDF register associated
with it, plus four additional register addresses. Perform-
ing an operation on one of these five registers deter-
mines how the FSR will be modified during indirect
addressing.
Indirect addressing is possible by using one of the
INDF registers. Any instruction using the INDF register
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself,
indirectly (FSR = '0'), will read 00h. Writing to the INDF
register indirectly, results in a no operation. The FSR
register contains a 12-bit address, which is shown in
Figure 4-10.
When data access is done to one of the five INDFn
locations, the address selected will configure the FSRn
register to:
• Do nothing to FSRn after an indirect access (no
change) - INDFn
• Auto-decrement FSRn after an indirect access
(post-decrement) - POSTDECn
The INDFn register is not a physical register. Address-
ing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer). This is indirect addressing.
• Auto-increment FSRn after an indirect access
(post-increment) - POSTINCn
• Auto-increment FSRn before an indirect access
(pre-increment) - PREINCn
Example 4-4 shows a simple use of indirect addressing
to clear the RAM in Bank1 (locations 100h-1FFh) in a
minimum number of instructions.
• Use the value in the WREG register as an offset
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) - PLUSWn
EXAMPLE 4-4:
HOW TO CLEAR RAM
(BANK1) USING INDIRECT
ADDRESSING
When using the auto-increment or auto-decrement fea-
tures, the effect on the FSR is not reflected in the
STATUS register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
LFSR FSR0, 0x100 ;
NEXT CLRF POSTINC0
; Clear INDF register
; & inc pointer
; All done w/ Bank1?
; NO, clear next
; YES, continue
Incrementing or decrementing an FSR affects all 12
bits. That is, when FSRnL overflows from an increment,
FSRnH will be incremented automatically.
BTFSS FSR0H, 1
GOTO NEXT
CONTINUE
Adding these features allows the FSRn to be used as a
stack pointer, in addition to its uses for table operations
in data memory.
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12-bit wide. To store the 12-bits of
addressing information, two 8-bit registers are
required. These indirect addressing registers are:
Each FSR has an address associated with it that per-
forms an indexed indirect access. When a data access
to this INDFn location (PLUSWn) occurs, the FSRn is
configured to add the signed value in the WREG regis-
ter and the value in FSR to form the address before an
indirect access. The FSR value is not changed.
1. FSR0: composed of FSR0H:FSR0L
2. FSR1: composed of FSR1H:FSR1L
3. FSR2: composed of FSR2H:FSR2L
If an FSR register contains a value that points to one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(STATUS bits are not affected).
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register
being the address of the data.
If an instruction writes a value to INDF0, the value will
be written to the address pointed to by FSR0H:FSR0L.
A read from INDF1 reads the data from the address
pointed to by FSR1H:FSR1L. INDFn can be used in
code anywhere an operand can be used.
DS39026D-page 50
1999-2013 Microchip Technology Inc.
PIC18CXX2
If an indirect addressing operation is done where the
target address is an FSRnH or FSRnL register, the
write operation will dominate over the pre- or post-
increment/decrement functions.
FIGURE 4-9:
INDIRECT ADDRESSING OPERATION
0h
RAM
Instruction
Executed
Opcode
Address
12
FFFh
File Address = access of an indirect addressing register
BSR<3:0>
12
12
Instruction
Fetched
4
8
Opcode
FSR
File
FIGURE 4-10:
INDIRECT ADDRESSING
Indirect Addressing
11
FSR Register
0
Location Select
0000h
Data
Memory(1)
0FFFh
Note 1: For register file map detail, see Table 4-1.
1999-2013 Microchip Technology Inc.
DS39026D-page 51
PIC18CXX2
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
4.13 STATUS Register
The STATUS register, shown in Register 4-2, contains
the arithmetic status of the ALU. The STATUS register
can be the destination for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV or N bits,
then the write to these five bits is disabled. These bits
are set or cleared according to the device logic. There-
fore, the result of an instruction with the STATUS regis-
ter as destination may be different than intended.
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF and MOVWF instructions are used to
alter the STATUS register, because these instructions
do not affect the Z, C, DC, OV or N bits from the
STATUS register. For other instructions not affecting
any status bits, see Table 19-2.
Note: The C and DC bits operate as a borrow and
digit borrow bit respectively, in subtraction.
REGISTER 4-2:
STATUS REGISTER
U-0
—
U-0
—
U-0
—
R/W-x
N
R/W-x
OV
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
bit 7-5
Unimplemented: Read as '0'
N: Negative bit
bit 4
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative, (ALU MSB = 1).
1= Result was negative
0= Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude, which causes the sign bit (bit7) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWFinstructions
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the bit 4 or bit 3 of the source register.
bit 0
C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWFinstructions
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS39026D-page 52
1999-2013 Microchip Technology Inc.
PIC18CXX2
.
4.13.1
RCON REGISTER
Note 1: If the BOREN configuration bit is set
(Brown-out Reset enabled), the BOR bit is
’1’ on a Power-on Reset. After a Brown-
out Reset has occurred, the BOR bit will
be clear and must be set by firmware to
indicate the occurrence of the next Brown-
out Reset.
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device RESET. These flags include the TO, PD, POR,
BOR and RI bits. This register is readable and writable.
If the BOREN configuration bit is clear
(Brown-out Reset disabled), BOR is
unknown after Power-on Reset and
Brown-out Reset conditions.
2: It is recommended that the POR bit be set
after
a Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.
REGISTER 4-3:
RCON REGISTER
R/W-0
IPEN
R/W-0
LWRT
U-0
—
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
bit 7
bit 6
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (16CXXX compatibility mode)
LWRT: Long Write Enable bit
1= Enable TBLWTto internal program memory
Once this bit is set, it can only be cleared by a POR or MCLR Reset.
0= Disable TBLWTto internal program memory; TBLWTonly to external program memory
bit 5
bit 4
Unimplemented: Read as '0'
RI: RESETInstruction Flag bit
1= The RESETinstruction was not executed
0= The RESETinstruction was executed causing a device RESET
(must be set in software after a Brown-out Reset occurs)
bit 3
bit 2
bit 1
TO: Watchdog Time-out Flag bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down Detection Flag bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= A Power-on Reset has not occurred
0= A Power-on Reset occurred
(must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1= A Brown-out Reset has not occurred
0= A Brown-out Reset occurred
(must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
1999-2013 Microchip Technology Inc.
DS39026D-page 53
PIC18CXX2
NOTES:
DS39026D-page 54
1999-2013 Microchip Technology Inc.
PIC18CXX2
Table Read operations retrieve data from program
memory and place it into the data memory space.
Figure 5-1 shows the operation of a Table Read with
program and data memory.
5.0
TABLE READS/TABLE WRITES
Enhanced devices have two memory spaces: the pro-
gram memory space and the data memory space. The
program memory space is 16-bits wide, while the data
memory space is 8 bits wide. Table Reads and Table
Writes have been provided to move data between
these two memory spaces through an 8-bit register
(TABLAT).
Table Write operations store data from the data mem-
ory space into program memory. Figure 5-2 shows the
operation of a Table Write with program and data
memory.
Table operations work with byte entities. A table block
containing data is not required to be word aligned, so a
table block can start and end at any byte address. If a
Table Write is being used to write an executable pro-
gram to program memory, program instructions will
need to be word aligned.
The operations that allow the processor to move data
between the data and program memory spaces are:
• Table Read (TBLRD)
• Table Write (TBLWT)
FIGURE 5-1:
TABLE READ OPERATION
Instruction: TBLRD*
Program Memory
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer points to a byte in program memory.
FIGURE 5-2:
TABLE WRITE OPERATION
Instruction: TBLWT*
Program Memory
(1)
Table Pointer
Table Latch (8-bit)
TABLAT
TBLPTRU TBLPTRH TBLPTRL
Program Memory
(TBLPTR)
Note 1: Table Pointer points to a byte in program memory.
1999-2013 Microchip Technology Inc.
DS39026D-page 55
PIC18CXX2
5.1.1
RCON REGISTER
5.1
Control Registers
The LWRT bit specifies the operation of Table Writes to
internal memory when the VPP voltage is applied to the
MCLR pin. When the LWRT bit is set, the controller
continues to execute user code, but long Table Writes
are allowed (for programming internal program mem-
ory) from user mode. The LWRT bit can be cleared only
by performing either a POR or MCLR Reset.
Several control registers are used in conjunction with
the TBLRDand TBLWTinstructions. These include the:
• TBLPTR registers
• TABLAT register
• RCON register
REGISTER 5-1:
RCON REGISTER (ADDRESS: FD0h)
R/W-0
IPEN
R/W-0
LWRT
U-0
—
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
bit 7
bit 6
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (16CXXX compatibility mode)
LWRT: Long Write Enable bit
1= Enable TBLWTto internal program memory
0= Disable TBLWTto internal program memory.
Note:
Only cleared on a POR or MCLR Reset.
This bit has no effect on TBLWTsto external program memory.
bit 5
bit 4
Unimplemented: Read as '0'
RI: RESETInstruction Flag bit
1= No RESETinstruction occurred
0= A RESETinstruction occurred
bit 3
bit 2
bit 1
bit 0
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= No Brown-out Reset or POR Reset occurred
0= A Brown-out Reset or POR Reset occurred
(must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS39026D-page 56
1999-2013 Microchip Technology Inc.
PIC18CXX2
5.1.2
TABLAT - TABLE LATCH REGISTER
5.1.3
TBLPTR - TABLE POINTER
REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program
memory and data memory.
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers (Table Pointer Upper Byte, High
Byte and Low Byte). These three registers
(TBLPTRU:TBLPTRH:TBLPTRL) join to form a 22-bit
wide pointer. The lower 21-bits allow the device to
address up to 2 Mbytes of program memory space. The
22nd bit allows access to the Device ID, the User ID
and the Configuration bits.
The Table Pointer, TBLPTR, is used by the TBLRD and
TBLWT instructions. These instructions can update the
TBLPTR in one of four ways, based on the table operation.
These operations are shown in Table 5-1. These opera-
tions on the TBLPTR only affect the lower 21-bits.
TABLE 5-1:
Example
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
When a Table Write occurs to an even program mem-
5.2
Internal Program Memory Read/
Writes
ory address (TBLPTR<0> = 0), the contents of TABLAT
are transferred to an internal holding register. This is
performed as a short write and the program memory
block is not actually programmed at this time. The hold-
ing register is not accessible by the user.
5.2.1
TABLE READ OVERVIEW (TBLRD)
The TBLRD instructions are used to read data from
program memory to data memory.
When a Table Write occurs to an odd program memory
address (TBLPTR<0>=1), a long write is started. Dur-
ing the long write, the contents of TABLAT are written
to the high byte of the program memory block and the
contents of the holding register are transferred to the
low byte of the program memory block.
TBLPTR points to a byte address in program space.
Executing TBLRDplaces the byte pointed to into TAB-
LAT. In addition, TBLPTR can be modified automati-
cally for the next Table Read operation.
Table Reads from program memory are performed one
byte at a time. The instruction will load TABLAT with the
one byte from program memory pointed to by TBLPTR.
Figure 5-3 shows the holding register and the program
memory write blocks.
If a single byte is to be programmed, the low (even)
byte of the destination program word should be read
using TBLRD*, modified or changed, if required, and
written back to the same address using TBLWT*+. The
high (odd) byte should be read using TBLRD*, modified
or changed if required, and written back to the same
address using TBLWT. A write to the odd address will
cause a long write to begin. This process ensures that
existing data in either byte will not be changed unless
desired.
5.2.2
INTERNAL PROGRAM MEMORY
WRITE BLOCK SIZE
The internal program memory of PIC18CXXX devices
is written in blocks. For PIC18CXX2 devices, the write
block size is 2 bytes. Consequently, Table Write opera-
tions to internal program memory are performed in
pairs, one byte at a time.
1999-2013 Microchip Technology Inc.
DS39026D-page 57
PIC18CXX2
FIGURE 5-3:
HOLDING REGISTER AND THE WRITE BLOCK
Program Memory (x 2-bits)
Block n
Write Block
MSB
Holding Register
Block n + 1
Block n + 2
The write to the MSB of the Write Block
causes the entire block to be written to pro-
gram memory. The program memory block
that is written depends on the address that is
written to in the MSB of the Write Block.
5.2.2.1
Operation
5.2.2.2
Sequence of Events
The long write is what actually programs words of data
into the internal memory. When a TBLWTto the MSB of
the write block occurs, instruction execution is halted.
During this time, programming voltage and the data
stored in internal latches is applied to program memory.
The sequence of events for programming an internal
program memory location should be:
1. Enable the interrupt that terminates the long
write. Disable all other interrupts.
2. Clear the source interrupt flag.
For a long write to occur:
3. If Interrupt Service Routine execution is desired
when the device wakes, enable global
interrupts.
1. MCLR/VPP pin must be at the programming
voltage
2. LWRT bit must be set
4. Set LWRT bit in the RCON register.
3. TBLWT to the address of the MSB of the write
block
5. Raise MCLR/VPP pin to the programming
voltage, VPP.
6. Clear the WDT (if enabled).
If the LWRT bit is clear, a short write will occur and pro-
gram memory will not be changed. If the TBLWTis not
to the MSB of the write block, then the programming
phase is not initiated.
7. Set the interrupt source to interrupt at the
required time.
8. Execute the Table Write for the lower (even)
byte. This will be a short write.
Setting the LWRT bit enables long writes when the
MCLR pin is taken to VPP voltage. Once the LWRT bit
is set, it can be cleared only by performing a POR or
MCLR Reset.
9. Execute the Table Write for the upper (odd) byte.
This will be a long write. The microcontroller will
then halt internal operations. (This is not the
same as SLEEP mode, as the clocks and
peripherals will continue to run.) The interrupt
will cause the microcontroller to resume
operation.
To ensure that the memory location has been well pro-
grammed, a minimum programming time is required.
The long write can be terminated after the program-
ming time has expired by a RESET or an interrupt.
Having only one interrupt source enabled to terminate
the long write ensures that no unintended interrupts will
prematurely terminate the long write.
10. If GIE was set, service the interrupt request.
11. Lower MCLR/VPP pin to VDD.
12. Verify the memory location (Table Read).
DS39026D-page 58
1999-2013 Microchip Technology Inc.
PIC18CXX2
Depending on the states of interrupt priority bits, the
GIE/GIEH bit or the PIE/GIEL bit, program execution
can either be vectored to the high or low priority Inter-
rupt Service Routine (ISR), or continue execution from
where programming commenced.
5.2.3
INTERRUPTS
The long write must be terminated by a RESET or any
interrupt.
The interrupt source must have its interrupt enable bit
set. When the source sets its interrupt flag, program-
ming will terminate. This will occur, regardless of the
settings of interrupt priority bits, the GIE/GIEH bit, or
the PIE/GIEL bit.
In either case, the interrupt flag will not be cleared
when programming is terminated and will need to be
cleared by the software.
TABLE 5-2:
LONG WRITE EXECUTION, INTERRUPT ENABLE BITS AND INTERRUPT RESULTS
GIE/
GIEH
PIE/
GIEL
Interrupt Interrupt
Priority
Action
Enable
Flag
0
Long write continues
even if interrupt flag becomes set.
X
X
X
X
X
X
(default)
Long write continues, will resume operations
when the interrupt flag is set.
X
0
X
0
1
1
0
1
Terminates long write, executes next instruction.
Interrupt flag not cleared.
(default) (default)
1
0
Terminates long write, executes next instruction.
Interrupt flag not cleared.
1
0
high priority
(default)
1
1
1
1
1
1
(default)
0
low
Terminates long write, executes next instruction.
Interrupt flag not cleared.
1
(default)
Terminates long write,
branches to low priority interrupt vector.
Interrupt flag can be cleared by ISR.
0
0
low
1
(default)
1
Terminates long write,
branches to high priority interrupt vector.
Interrupt flag can be cleared by ISR.
0
1
high priority
(default)
1
1
(default)
5.2.4
UNEXPECTED TERMINATION OF
WRITE OPERATIONS
If a write is terminated by an unplanned event such as
loss of power, an unexpected RESET, or an interrupt
that was not disabled, the memory location just pro-
grammed should be verified and reprogrammed if
needed.
1999-2013 Microchip Technology Inc.
DS39026D-page 59
PIC18CXX2
NOTES:
DS39026D-page 60
1999-2013 Microchip Technology Inc.
PIC18CXX2
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
6.0
6.1
8 X 8 HARDWARE MULTIPLIER
Introduction
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18CXX2 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored into the 16-bit product regis-
ter pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 6-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
TABLE 6-1:
Routine
PERFORMANCE COMPARISON
Multiply Method
Program
Memory
(Words)
Time
Cycles
(Max)
@ 40 MHz @ 10 MHz @ 4 MHz
Without hardware multiply
Hardware multiply
13
1
69
1
6.9 s
100 ns
9.1 s
600 ns
24.2 s
2.4 s
25.4 s
3.6 s
27.6 s
400 ns
36.4 s
2.4 s
69 s
1 s
8 x 8 unsigned
8 x 8 signed
Without hardware multiply
Hardware multiply
33
6
91
6
91 s
6 s
Without hardware multiply
Hardware multiply
21
24
52
36
242
24
254
36
96.8 s
9.6 s
242 s
24 s
254 s
36 s
16 x 16 unsigned
16 x 16 signed
Without hardware multiply
Hardware multiply
102.6 s
14.4 s
EXAMPLE 6-2:
8 x 8 SIGNED MULTIPLY
ROUTINE
6.2
Operation
Example 6-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
MOVF
ARG1,
ARG2
W
MULWF
; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC
SUBWF
ARG2, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
Example 6-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
;
- ARG1
MOVF
BTFSC
SUBWF
ARG2,
W
ARG1, SB
PRODH, F
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
EXAMPLE 6-1:
8 x 8 UNSIGNED
MULTIPLY ROUTINE
Example 6-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 6-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
MOVF
MULWF
ARG1, W
ARG2
;
; ARG1 * ARG2 ->
;
PRODH:PRODL
EQUATION 6-1:
16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
=
=
ARG1H:ARG1L ARG2H:ARG2L
16
(ARG1H ARG2H 2 )+
8
(ARG1H ARG2L 2 )+
8
(ARG1L ARG2H 2 )+
(ARG1L ARG2L)
1999-2013 Microchip Technology Inc.
DS39026D-page 61
PIC18CXX2
EXAMPLE 6-3:
16 x 16 UNSIGNED
EXAMPLE 6-4:
16 x 16 SIGNED
MULTIPLY ROUTINE
MULTIPLY ROUTINE
MOVF
MULWF
ARG1L, W
ARG2L
MOVF
MULWF
ARG1L, W
ARG2L
; ARG1L * ARG2L ->
; PRODH:PRODL
; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF
MOVFF
PRODH, RES1 ;
PRODL, RES0 ;
MOVFF
MOVFF
PRODH, RES1 ;
PRODL, RES0 ;
;
;
;
;
MOVF
MULWF
ARG1H, W
ARG2H
MOVF
MULWF
ARG1H, W
ARG2H
; ARG1H * ARG2H ->
; PRODH:PRODL
; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF
MOVFF
PRODH, RES3 ;
PRODL, RES2 ;
MOVFF
MOVFF
PRODH, RES3 ;
PRODL, RES2 ;
MOVF
ARG1L, W
MOVF
ARG1L, W
MULWF
ARG2H
; ARG1L * ARG2H ->
MULWF
ARG2H
; ARG1L * ARG2H ->
; PRODH:PRODL
; PRODH:PRODL
MOVF
PRODL, W
;
MOVF
PRODL, W
;
ADDWF
MOVF
RES1,
PRODH, W
F
; Add cross
; products
ADDWF
MOVF
RES1,
PRODH, W
F
; Add cross
; products
ADDWFC
CLRF
ADDWFC
RES2,
WREG,
RES3,
F
F
F
;
;
;
ADDWFC
CLRF
ADDWFC
RES2,
WREG,
RES3,
F
F
F
;
;
;
;
;
MOVF
MULWF
ARG1H, W
ARG2L
;
MOVF
MULWF
ARG1H, W
ARG2L
;
; ARG1H * ARG2L ->
; ARG1H * ARG2L ->
; PRODH:PRODL
; PRODH:PRODL
MOVF
PRODL, W
;
MOVF
PRODL, W
;
ADDWF
MOVF
ADDWFC
CLRF
RES1,
PRODH, W
RES2,
WREG,
RES3,
F
; Add cross
; products
;
;
;
ADDWF
MOVF
ADDWFC
CLRF
RES1,
F
; Add cross
; products
;
;
;
PRODH, W
RES2, F
WREG, F
RES3, F
F
F
F
ADDWFC
ADDWFC
;
;
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
Example 6-4 shows the sequence to do a 16 x 16
signed multiply. Equation 6-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs’ Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
SIGN_ARG1
BTFSS
BRA
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
EQUATION 6-2:
16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
MOVF
SUBWF
MOVF
RES3:RES0
SUBWFB
;
CONT_CODE
:
=
=
ARG1H:ARG1L ARG2H:ARG2L
16
(ARG1H ARG2H 2 )+
8
(ARG1H ARG2L 2 )+
8
(ARG1L ARG2H 2 )+
(ARG1L ARG2L)+
(-1 ARG2H<7> ARG1H:ARG1L 2 )+
(-1 ARG1H<7> ARG2H:ARG2L 2
16
16
)
DS39026D-page 62
1999-2013 Microchip Technology Inc.
PIC18CXX2
When the IPEN bit is cleared (default state), the inter-
rupt priority feature is disabled and interrupts are com-
patible with PIC® mid-range devices. In Compatibility
mode, the interrupt priority bits for each source have no
effect. INTCON<6> is the PEIE bit, which enables/dis-
ables all peripheral interrupt sources. INTCON<7> is
the GIE bit, which enables/disables all interrupt
sources. All interrupts branch to address 000008h in
Compatibility mode.
7.0
INTERRUPTS
The PIC18CXX2 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high priority
level, or a low priority level. The high priority interrupt
vector is at 000008h and the low priority interrupt vector
is at 000018h. High priority interrupt events will over-
ride any low priority interrupts that may be in progress.
There are ten registers which are used to control inter-
rupt operation. These registers are:
When an interrupt is responded to, the Global Interrupt
Enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH, or GIEL bit.
High priority interrupt sources can interrupt a low prior-
ity interrupt.
• RCON
• INTCON
• INTCON2
• INTCON3
• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
It is recommended that the Microchip header files sup-
plied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
Each interrupt source has three bits to control its oper-
ation. The functions of these bits are:
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts glo-
bally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set. Setting the GIEL
bit (INTCON<6>) enables all interrupts that have the
priority bit cleared. When the interrupt flag, enable bit
and appropriate global interrupt enable bit are set, the
interrupt will vector immediately to address 000008h or
000018h, depending on the priority level. Individual
interrupts can be disabled through their corresponding
enable bits.
1999-2013 Microchip Technology Inc.
DS39026D-page 63
PIC18CXX2
FIGURE 7-1:
INTERRUPT LOGIC
Wake-up if in SLEEP mode
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
Interrupt to CPU
Vector to location
0008h
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
GIEH/GIE
TMR1IF
TMR1IE
TMR1IP
IPE
IPEN
XXXXIF
XXXXIE
XXXXIP
GIEL/PEIE
IPEN
Additional Peripheral Interrupts
High Priority Interrupt Generation
Low Priority Interrupt Generation
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Interrupt to CPU
Vector to Location
0018h
TMR0IF
TMR0IE
TMR0IP
TMR1IF
TMR1IE
TMR1IP
RBIF
RBIE
RBIP
XXXXIF
XXXXIE
XXXXIP
GIEL\PEIE
INT0IF
INT0IE
INT1IF
INT1IE
INT1IP
Additional Peripheral Interrupts
INT2IF
INT2IE
INT2IP
DS39026D-page 64
1999-2013 Microchip Technology Inc.
PIC18CXX2
7.1
INTCON Registers
The INTCON Registers are readable and writable reg-
isters, which contains various enable, priority, and flag
bits.
REGISTER 7-1:
INTCON REGISTER
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
R/W-0
INT0IF
R/W-x
RBIF
bit 0
GIE/GIEH PEIE/GIEL
bit 7
TMR0IE
INT0IE
TMR0IF
bit 7
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked interrupts
0= Disables all interrupts
When IPEN = 1:
1= Enables all high priority interrupts
0= Disables all high priority interrupts
bit 6
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
When IPEN = 1:
1= Enables all low priority peripheral interrupts
0= Disables all low priority peripheral interrupts
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 overflow interrupt
0= Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1= Enables the INT0 external interrupt
0= Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1= The INT0 external interrupt occurred (must be cleared in software)
0= The INT0 external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
1999-2013 Microchip Technology Inc.
DS39026D-page 65
PIC18CXX2
REGISTER 7-2:
INTCON2 REGISTER
R/W-1
RBPU
R/W-1
R/W-1
R/W-1
U-0
—
R/W-1
U-0
—
R/W-1
RBIP
bit 0
INTEDG0 INTEDG1 INTEDG2
TMR0IP
bit 7
bit 7
bit 6
bit 5
bit 4
RBPU: PORTB Pull-up Enable bit
1= All PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG0:External Interrupt0 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG1: External Interrupt1 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
INTEDG2: External Interrupt2 Edge Select bit
1= Interrupt on rising edge
0= Interrupt on falling edge
bit 3
bit 2
Unimplemented: Read as '0'
TMR0IP: TMR0 Overflow Interrupt Priority bit
1= High priority
0= Low priority
bit 1
bit 0
Unimplemented: Read as '0'
RBIP: RB Port Change Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
DS39026D-page 66
1999-2013 Microchip Technology Inc.
PIC18CXX2
REGISTER 7-3:
INTCON3 REGISTER
R/W-1
R/W-1
U-0
—
R/W-0
R/W-0
U-0
—
R/W-0
INT2IF
R/W-0
INT1IF
INT2IP
INT1IP
INT2IE
INT1IE
bit 7
bit 0
bit 7
bit 6
INT2IP: INT2 External Interrupt Priority bit
1= High priority
0= Low priority
INT1IP: INT1 External Interrupt Priority bit
1= High priority
0= Low priority
bit 5
bit 4
Unimplemented: Read as '0'
INT2IE: INT2 External Interrupt Enable bit
1= Enables the INT2 external interrupt
0= Disables the INT2 external interrupt
bit 3
INT1IE: INT1 External Interrupt Enable bit
1= Enables the INT1 external interrupt
0= Disables the INT1 external interrupt
bit 2
bit 1
Unimplemented: Read as '0'
INT2IF: INT2 External Interrupt Flag bit
1= The INT2 external interrupt occurred
(must be cleared in software)
0= The INT2 external interrupt did not occur
bit 0
INT1IF: INT1 External Interrupt Flag bit
1= The INT1 external interrupt occurred
(must be cleared in software)
0= The INT1 external interrupt did not occur
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
1999-2013 Microchip Technology Inc.
DS39026D-page 67
PIC18CXX2
7.2
PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Flag Registers (PIR1, PIR2).
Note 1: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>).
2: User software should ensure the appropri-
ate interrupt flag bits are cleared prior to
enabling an interrupt, and after servicing
that interrupt.
REGISTER 7-4:
PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (PIR1)
R/W-0
PSPIF
R/W-0
ADIF
R-0
R-0
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
RCIF
TXIF
CCP1IF TMR2IF TMR1IF
bit 0
bit 7
bit 7
bit 6
bit 5
bit 4
bit 3
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1= The USART receive buffer, RCREG, is full (cleared when RCREG is read)
0= The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0= The USART transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1= The transmission/reception is complete (must be cleared in software)
0= Waiting to transmit/receive
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= MR1 register did not overflow
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset ’1’ = Bit is set
DS39026D-page 68
1999-2013 Microchip Technology Inc.
PIC18CXX2
REGISTER 7-5:
PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (PIR2)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
BCLIF
R/W-0
LVDIF
R/W-0
R/W-0
CCP2IF
bit 0
TMR3IF
bit 7
bit 7-4
bit 3
Unimplemented: Read as '0'
BCLIF: Bus Collision Interrupt Flag bit
1= A bus collision occurred (must be cleared in software)
0= No bus collision occurred
bit 2
bit 1
bit 0
LVDIF: Low Voltage Detect Interrupt Flag bit
1= A low voltage condition occurred (must be cleared in software)
0= The device voltage is above the Low Voltage Detect trip point
TMR3IF: TMR3 Overflow Interrupt Flag bit
1= TMR3 register overflowed (must be cleared in software)
0= TMR3 register did not overflow
CCP2IF: CCPx Interrupt Flag bit
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset ’1’ = Bit is set
1999-2013 Microchip Technology Inc.
DS39026D-page 69
PIC18CXX2
7.3
PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are two Peripheral Inter-
rupt Enable Registers (PIE1, PIE2). When IPEN = 0,
the PEIE bit must be set to enable any of these periph-
eral interrupts.
REGISTER 7-6:
PERIPHERAL INTERRUPT ENABLE REGISTER 1 (PIE1)
R/W-0
PSPIE
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
R/W-0
R/W-0
CCP1IE TMR2IE TMR1IE
bit 0
bit 7
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1= Enables the MSSP interrupt
0= Disables the MSSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39026D-page 70
1999-2013 Microchip Technology Inc.
PIC18CXX2
REGISTER 7-7:
PERIPHERAL INTERRUPT ENABLE REGISTER 2 (PIE2)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
BCLIE
R/W-0
LVDIE
R/W-0
R/W-0
TMR3IE
CCP2IE
bit 7
bit 0
bit 7-4
bit 3
Unimplemented: Read as '0'
BCLIE: Bus Collision Interrupt Enable bit
1= Enabled
0= Disabled
bit 2
bit 1
bit 0
LVDIE: Low Voltage Detect Interrupt Enable bit
1= Enabled
0= Disabled
TMR3IE: TMR3 Overflow Interrupt Enable bit
1= Enables the TMR3 overflow interrupt
0= Disables the TMR3 overflow interrupt
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
1999-2013 Microchip Technology Inc.
DS39026D-page 71
PIC18CXX2
7.4
IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are two Peripheral Inter-
rupt Priority Registers (IPR1, IPR2). The operation of
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 7-8:
PERIPHERAL INTERRUPT PRIORITY REGISTER 1 (IPR1)
R/W-1
PSPIP
R/W-1
ADIP
R/W-1
RCIP
R/W-1
TXIP
R/W-1
SSPIP
R/W-1
R/W-1
R/W-1
TMR1IP
bit 0
CCP1IP
TMR2IP
bit 7
bit 7
bit 6
bit 5
bit 4
PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit
1= High priority
0= Low priority
ADIP: A/D Converter Interrupt Priority bit
1= High priority
0= Low priority
RCIP: USART Receive Interrupt Priority bit
1= High priority
0= Low priority
TXIP: USART Transmit Interrupt Priority bit
1= High priority
0= Low priority
bit 3
bit 2
bit 1
bit 0
SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1= High priority
0= Low priority
CCP1IP: CCP1 Interrupt Priority bit
1= High priority
0= Low priority
TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1= High priority
0= Low priority
TMR1IP: TMR1 Overflow Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39026D-page 72
1999-2013 Microchip Technology Inc.
PIC18CXX2
REGISTER 7-9:
PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (IPR2)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
BCLIP
R/W-1
LVDIP
R/W-1
R/W-1
TMR3IP
CCP2IP
bit 7
bit 0
bit 7-4
bit 3
Unimplemented: Read as '0'
BCLIP: Bus Collision Interrupt Priority bit
1= High priority
0= Low priority
bit 2
bit 1
bit 0
LVDIP: Low Voltage Detect Interrupt Priority bit
1= High priority
0= Low priority
TMR3IP: TMR3 Overflow Interrupt Priority bit
1= High priority
0= Low priority
CCP2IP: CCP2 Interrupt Priority bit
1= High priority
0= Low priority
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
1999-2013 Microchip Technology Inc.
DS39026D-page 73
PIC18CXX2
7.5
RCON Register
The RCON register contains the bit which is used to
enable prioritized interrupts (IPEN).
REGISTER 7-10: RCON REGISTER
R/W-0
IPEN
R/W-0
LWRT
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-0
POR
R/W-0
BOR
bit 7
bit 0
bit 7
bit 6
IPEN: Interrupt Priority Enable bit
1= Enable priority levels on interrupts
0= Disable priority levels on interrupts (16CXXX compatibility mode)
LWRT: Long Write Enable bit
For details of bit operation, see Register 4-3
Unimplemented: Read as '0'
bit 5
bit 4
RI: RESETInstruction Flag bit
For details of bit operation, see Register 4-3
TO: Watchdog Time-out Flag bit
bit 3
bit 2
bit 1
bit 0
For details of bit operation, see Register 4-3
PD: Power-down Detection Flag bit
For details of bit operation, see Register 4-3
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-3
BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-3
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS39026D-page 74
1999-2013 Microchip Technology Inc.
PIC18CXX2
7.6
INT0 Interrupt
7.7
TMR0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge triggered: either rising, if the
corresponding INTEDGx bit is set in the INTCON2 reg-
ister, or falling, if the INTEDGx bit is clear. When a valid
edge appears on the RBx/INTx pin, the corresponding
flag bit INTxF is set. This interrupt can be disabled by
clearing the corresponding enable bit INTxE. Flag bit
INTxF must be cleared in software in the Interrupt Ser-
vice Routine before re-enabling the interrupt. All exter-
nal interrupts (INT0, INT1 and INT2) can wake-up the
processor from SLEEP, if bit INTxE was set prior to
going into SLEEP. If the global interrupt enable bit GIE
set, the processor will branch to the interrupt vector
following wake-up.
In 8-bit mode (which is the default), an overflow (FFh
00h) in the TMR0 register will set flag bit TMR0IF. In
16-bit mode, an overflow (FFFFh 0000h) in the
TMR0H:TMR0L registers will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit T0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2<2>). See Sec-
tion 8.0 for further details on the Timer0 module.
7.8
PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB Interrupt-on-change is
determined by the value contained in the interrupt pri-
ority bit, RBIP (INTCON2<0>).
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits, INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
7.9
Context Saving During Interrupts
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, STATUS and BSR regis-
ters are saved on the fast return stack. If a fast return
from interrupt is not used (see Section 4.3), the user
may need to save the WREG, STATUS and BSR regis-
ters in software. Depending on the user’s application,
other registers may also need to be saved. Example 7-1
saves and restores the WREG, STATUS and BSR regis-
ters during an Interrupt Service Routine.
EXAMPLE 7-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
MOVFF
MOVFF
;
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR located anywhere
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
; Restore BSR
; Restore WREG
; Restore STATUS
1999-2013 Microchip Technology Inc.
DS39026D-page 75
PIC18CXX2
NOTES:
DS39026D-page 76
1999-2013 Microchip Technology Inc.
PIC18CXX2
EXAMPLE 8-1:
INITIALIZING PORTA
8.0
I/O PORTS
CLRF PORTA
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; for digital inputs
; Value used to
; initialize data
; direction
; Set RA<3:0> as inputs
; RA<5:4> as outputs
Depending on the device selected, there are either five
ports, or three ports available. Some pins of the I/O
ports are multiplexed with an alternate function from
the peripheral features on the device. In general, when
a peripheral is enabled, that pin may not be used as a
general purpose I/O pin.
CLRF LATA
MOVLW 0x07
MOVWF ADCON1
MOVLW 0xCF
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
MOVWF TRISA
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The data latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
FIGURE 8-1:
BLOCK DIAGRAM OF
RA3:RA0AND RA5PINS
8.1
PORTA, TRISA and LATA
Registers
PORTA is a 6-bit wide, bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
RD LATA
Data
Bus
D
Q
VDD
WR LATA
Q
Data Latch
CK
or
P
PORTA
I/O pin(1)
N
Note: On a Power-on Reset, these pins are con-
D
Q
figured as digital inputs.
WR TRISA
VSS
Analog
Q
CK
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
Input
Mode
TRIS Latch
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register reads and writes the latched output value for
PORTA.
TTL
Input
Buffer
RD TRISA
Q
D
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA4/
T0CKI pin is a Schmitt Trigger input and an open drain
output. All other RA port pins have TTL input levels and
full CMOS output drivers.
EN
RD PORTA
SS Input (RA5 only)
To A/D Converter and LVD Modules
The other PORTA pins are multiplexed with analog
inputs and the analog VREF+ and VREF- inputs. The
operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register1).
Note 1: I/O pins have protection diodes to VDD and VSS.
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
1999-2013 Microchip Technology Inc.
DS39026D-page 77
PIC18CXX2
FIGURE 8-2:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
FIGURE 8-3:
BLOCKDIAGRAMOFRA6
ECRA6 or
RCRA6 Enable
Data
Bus
RD LATA
Data
Bus
RD LATA
D
Q
Q
D
Q
WR LATA
or
PORTA
CK
VDD
P
I/O pin(1)
N
WR LATA
or
PORTA
Data Latch
Q
CK
D
Q
VSS
Data Latch
I/O pin(1)
N
WR TRISA
D
Q
Q
CK
Schmitt
Trigger
Input
Buffer
TRIS Latch
WR
TRISA
VSS
Q
CK
ECRA6 or
TRIS Latch
RCRA6
RD TRISA
Enable
Data Bus
TTL
Input
Buffer
Q
D
RD TRISA
EN
RD PORTA
TMR0 Clock Input
Data Bus
Q
D
Note 1: I/O pins have protection diodes to VDD and VSS.
EN
RD PORTA
Note 1: I/O pins have protection diodes to VDD and VSS.
DS39026D-page 78
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 8-1:
Name
PORTA FUNCTIONS
Bit#
Buffer
Function
RA0/AN0
bit0
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
ST
Input/output or analog input.
Input/output or analog input.
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
Input/output or analog input or VREF-.
Input/output or analog input or VREF+.
Input/output or external clock input for Timer0.
Output is open drain type.
RA5/SS/AN4/LVDIN
OSC2/CLKO/RA6
bit5
bit6
TTL
TTL
Input/output or slave select input for synchronous serial port or analog
input, or low voltage detect input.
OSC2 or clock output or I/O pin.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 8-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on Valueon all
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other
RESETS
PORTA
LATA
—
—
—
RA6
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000 --0u 0000
--xx xxxx --uu uuuu
--11 1111 --11 1111
Latch A Data Output Register
PORTA Data Direction Register
TRISA
ADCON1 ADFM ADCS2
—
—
PCFG3 PCFG2
PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x= unknown, u= unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by PORTA.
1999-2013 Microchip Technology Inc.
DS39026D-page 79
PIC18CXX2
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
8.2
PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB3 can be configured by the configuration bit
CCP2MX as the alternate peripheral pin for the CCP2
module (CCP2MX = ‘0’).
Note: On a Power-on Reset, these pins are con-
figured as digital inputs.
FIGURE 8-4:
BLOCK DIAGRAM OF
RB7:RB4 PINS
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register reads and writes the latched output value for
PORTB.
VDD
RBPU(2)
Data Bus
Weak
Pull-up
P
EXAMPLE 8-2:
INITIALIZING PORTB
Data Latch
D
Q
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
I/O
WR LATB
or
PORTB
pin(1)
CK
TRIS Latch
CLRF
LATB
; Alternate method
; to clear output
; data latches
D
Q
WR TRISB
TTL
Input
Buffer
MOVLW 0xCF
; Value used to
; initialize data
; direction
CK
ST
Buffer
MOVWF TRISB
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
RD TRISB
RD LATB
Latch
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
Q
Q
D
EN
Q1
RD PORTB
Set RBIF
D
RD PORTB
Q3
Four of the PORTB pins, RB7:RB4, have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
From other
EN
RB7:RB4 pins
RBx/INTx
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2<7>).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
b) Clear flag bit RBIF.
DS39026D-page 80
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 8-5:
BLOCK DIAGRAM OF RB2:RB0 PINS
VDD
Weak
RBPU(2)
P
Pull-up
Data Latch
Data Bus
D
Q
I/O pin(1)
WR Port
CK
TRIS Latch
D
Q
TTL
Input
Buffer
WR TRIS
CK
RD TRIS
RD Port
Q
D
EN
RB0/INT
Schmitt Trigger Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
RD Port
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
FIGURE 8-6:
BLOCK DIAGRAM OF RB3
VDD
Weak
RBPU(2)
CCP2MX
P
Pull-up
CCP Output(3)
1
0
VDD
P
Enable
CCP Output(3)
Data Latch
I/O pin(1)
Data Bus
D
Q
WR LATB or
WR PORTB
N
CK
VSS
TRIS Latch
D
TTL
WR TRISB
Input
CK
Q
Buffer
RD TRISB
RD LATB
D
Q
EN
RD PORTB
RD PORTB
CCP2 Input(3)
Schmitt Trigger
Buffer
CCP2MX = 0
Note 1: I/O pin has diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>).
3: The CCP2 input/output is multiplexed with RB3, if the CCP2MX bit is enabled (=’0’) in the configuration register.
1999-2013 Microchip Technology Inc.
DS39026D-page 81
PIC18CXX2
TABLE 8-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
Function
RB0/INT0
bit0
TTL/ST(1)
Input/output pin or external interrupt input1. Internal software
programmable weak pull-up.
RB1/INT1
RB2/INT2
bit1
bit2
bit3
TTL/ST(1)
TTL/ST(1)
TTL/ST(4)
Input/output pin or external interrupt input2. Internal software
programmable weak pull-up.
Input/output pin or external interrupt input3. Internal software
programmable weak pull-up.
RB3/CCP2(3)
Input/output pin. Capture2 input/Compare2 output/PWM output when
CCP2MX configuration bit is enabled. Internal software
programmable weak pull-up.
RB4
RB5
RB6
RB7
bit4
bit5
bit6
bit7
TTL
Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up.
TTL
Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up.
TTL/ST(2)
TTL/ST(2)
Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up. Serial programming clock.
Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: A device configuration bit selects which I/O pin the CCP2 pin is multiplexed on.
4: This buffer is a Schmitt Trigger input when configured as the CCP2 input.
TABLE 8-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
POR,
Value on all
other
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
PORTB
LATB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
LATB Data Output Register
TRISB
INTCON
PORTB Data Direction Register
1111 1111
0000 000x
1111 1111
0000 000u
GIE/
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF INT0IF
RBIF
GIEH
INTCON2
RBPU INTEDG0 INTEDG1 INTEDG2
INT2IP INT1IP INT2IE
—
TMR0IP
—
—
RBIP
1111 -1-1
11-0 0-00
1111 -1-1
11-0 0-00
INTCON3
—
INT1IE
INT2IF
INT1IF
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS39026D-page 82
1999-2013 Microchip Technology Inc.
PIC18CXX2
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
8.3
PORTC, TRISC and LATC
Registers
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction Register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= 0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
RC1 is normally configured by the configuration bit
CCP2MX as the default peripheral pin for the CCP2
module (default/erased state, CCP2MX = ‘1’).
EXAMPLE 8-3:
INITIALIZING PORTC
CLRF
PORTC
; Initialize PORTC by
; clearing output
; data latches
Note: On a Power-on Reset, these pins are con-
CLRF
LATC
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
figured as digital inputs.
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register reads and writes the latched output value for
PORTC.
MOVLW 0xCF
MOVWF TRISC
PORTC is multiplexed with several peripheral functions
(Table 8-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to make
a pin an input. The user should refer to the correspond-
ing peripheral section for the correct TRIS bit settings.
FIGURE 8-7:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Port/Peripheral Select(2)
VDD
Peripheral Data Out
RD LATC
0
Data Latch
Data Bus
D
Q
P
WR LATC or
WR PORTC
1
I/O pin(1)
Q
CK
DDR Latch
D
Q
WR TRISC
RD TRISC
CK
Q
N
Schmitt
Trigger
VSS
Peripheral Output
Enable(3)
Q
D
EN
RD PORTC
Peripheral Data In
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port data (input) and peripheral output.
3: Peripheral Output Enable is only active if peripheral select is active.
1999-2013 Microchip Technology Inc.
DS39026D-page 83
PIC18CXX2
TABLE 8-5:
Name
PORTC FUNCTIONS
Bit# Buffer Type
Function
RC0/T1OSO/T1CKI bit0
ST
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2
bit1
Input/output port pin, Timer1 oscillator input, or Capture2 input/
Compare2 output/PWM output when CCP2MX configuration bit is
disabled.
RC2/CCP1
bit2
bit3
ST
ST
Input/output port pin or Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
RC3 can also be the synchronous serial clock for both SPI and
I2C modes.
RC4/SDI/SDA
RC5/SDO
bit4
bit5
bit6
ST
ST
ST
RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode).
Input/output port pin or Synchronous Serial Port Data output.
RC6/TX/CK
Input/output port pin, Addressable USART Asynchronous Transmit, or
Addressable USART Synchronous Clock.
RC7/RX/DT
bit7
ST
Input/output port pin, Addressable USART Asynchronous Receive, or
Addressable USART Synchronous Data.
Legend: ST = Schmitt Trigger input
TABLE 8-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on
POR,
Value on all
other
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
LATC
LATC Data Output Register
PORTC Data Direction Register
TRISC
Legend: x= unknown, u= unchanged
DS39026D-page 84
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 8-8:
PORTD BLOCK DIAGRAM
IN I/O PORT MODE
8.4
PORTD, TRISD and LATD
Registers
This section is only applicable to the PIC18C4X2
devices.
RD LATD
PORTD is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISD bit (= 0) will
make the corresponding PORTD pin an output (i.e., put
the contents of the output latch on the selected pin).
Data
Bus
D
Q
I/O pin(1)
WR LATD
or
PORTD
CK
Data Latch
D
Q
Note: On a Power-on Reset, these pins are con-
WR TRISD
Schmitt
Trigger
Input
CK
TRIS Latch
figured as digital inputs.
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register reads and writes the latched output value for
PORTD.
Buffer
RD TRISD
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
Q
D
EN
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL. See Section 8.6 for additional information on
the Parallel Slave Port (PSP).
RD PORTD
Note 1: I/O pins have diode protection to VDD and VSS.
EXAMPLE 8-4:
INITIALIZING PORTD
CLRF
PORTD ; Initialize PORTD by
; clearing output
; data latches
CLRF
LATD
; Alternate method
; to clear output
; data latches
MOVLW 0xCF
; Value used to
; initialize data
; direction
MOVWF TRISD
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
1999-2013 Microchip Technology Inc.
DS39026D-page 85
PIC18CXX2
TABLE 8-7:
Name
PORTD FUNCTIONS
Bit#
Buffer Type
Function
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
Input/output port pin or parallel slave port bit0.
Input/output port pin or parallel slave port bit1.
Input/output port pin or parallel slave port bit2.
Input/output port pin or parallel slave port bit3.
Input/output port pin or parallel slave port bit4.
Input/output port pin or parallel slave port bit5.
Input/output port pin or parallel slave port bit6.
Input/output port pin or parallel slave port bit7.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 8-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on
POR,
Value on all
other
Name Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
PORTD RD7 RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 -111 0000 -111
LATD
TRISD PORTD Data Direction Register
TRISE IBF OBF IBOV PSPMODE
LATD Data Output Register
—
PORTE Data Direction bits
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD.
DS39026D-page 86
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 8-9:
PORTEBLOCKDIAGRAM
IN I/O PORT MODE
8.5
PORTE, TRISE and LATE
Registers
This section is only applicable to the PIC18C4X2
devices.
RD LATE
PORTE is a 3-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e., put
the contents of the output latch on the selected pin).
Data
Bus
D
Q
I/O pin(1)
WR LATE
or
PORTE
CK
Data Latch
D
Q
Note: On a Power-on Reset, these pins are con-
WR TRISE
figured as digital inputs.
Schmitt
Trigger
Input
CK
TRIS Latch
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register reads and writes the latched output value for
PORTE.
Buffer
RD TRISE
PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7), which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
Q
D
EN
RD PORTE
Register 8-1 shows the TRISE register, which also con-
trols the parallel slave port operation.
To Analog Converter
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as '0's.
Note 1: I/O pins have diode protection to VDD and VSS.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Note: On a Power-on Reset, these pins are con-
figured as analog inputs.
EXAMPLE 8-5:
INITIALIZING PORTE
CLRF
PORTE
; Initialize PORTE by
; clearing output
; data latches
CLRF
LATE
; Alternate method
; to clear output
; data latches
MOVLW 0x07
; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVLW 0x03
; Value used to
; initialize data
; direction
MOVWF TRISC
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
1999-2013 Microchip Technology Inc.
DS39026D-page 87
PIC18CXX2
REGISTER 8-1:
TRISE REGISTER
R-0
IBF
R-0
R/W-0
IBOV
R/W-0
U-0
—
R/W-1
R/W-1
R/W-1
OBF
PSPMODE
TRISE2
TRISE1
TRISE0
bit 7
bit 0
bit 7
bit 6
bit 5
IBF: Input Buffer Full Status bit
1= A word has been received and waiting to be read by the CPU
0= No word has been received
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1= A write occurred when a previously input word has not been read
(must be cleared in software)
0= No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel Slave Port mode
0= General purpose I/O mode
bit 3
bit 2
Unimplemented: Read as '0'
TRISE2: RE2 Direction Control bit
1= Input
0= Output
bit 1
bit 0
TRISE1: RE1 Direction Control bit
1= Input
0= Output
TRISE0: RE0 Direction Control bit
1= Input
0= Output
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39026D-page 88
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 8-9:
Name
PORTE FUNCTIONS
Bit#
Buffer Type
Function
Input/output port pin or read control input in Parallel Slave Port mode
or analog input:
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
bit0
ST/TTL(1)
RD
1= Not a read operation
0= Read operation. Reads PORTD register (if chip selected).
Input/output port pin or write control input in Parallel Slave Port mode
or analog input:
bit1
bit2
ST/TTL(1)
ST/TTL(1)
WR
1= Not a write operation
0= Write operation. Writes PORTD register (if chip selected).
Input/output port pin or chip select control input in Parallel Slave Port
mode or analog input:
CS
1= Device is not selected
0= Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 8-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on
POR,
Value on all
other
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
PORTE
LATE
—
—
—
—
—
—
—
—
—
RE2
RE1
RE0
---- -000
---- -xxx
0000 -111
--0- -000
---- -000
---- -uuu
0000 -111
--0- -000
—
PSPMODE
—
LATE Data Output Register
PORTE Data Direction bits
TRISE
IBF
OBF
IBOV
—
—
ADCON1 ADFM ADCS2
PCFG3
PCFG2
PCFG1
PCFG0
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTE.
1999-2013 Microchip Technology Inc.
DS39026D-page 89
PIC18CXX2
FIGURE 8-10:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE
PORT)
8.6
Parallel Slave Port
The Parallel Slave Port is implemented on the 40-pin
devices only (PIC18C4X2).
PORTD operates as an 8-bit wide, parallel slave port,
or microprocessor port, when control bit PSPMODE
(TRISE<4>) is set. It is asynchronously readable and
writable by the external world through RD control input
pin RE0/RD and WR control input pin RE1/WR.
Data Bus
D
Q
RDx
pin
WR LATD
or
PORTD
CK
Data Latch
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). The A/D port config-
uration bits PCFG2:PCFG0 (ADCON1<2:0>) must be
set, which will configure pins RE2:RE0 as digital I/O.
TTL
Q
D
RD PORTD
EN
RD LATD
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
The PORTE I/O pins become control inputs for the
microprocessor port when bit PSPMODE (TRISE<4>)
is set. In this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs), and the ADCON1 is configured for digital I/O.
In this mode, the input buffers are TTL.
Read
RD
CS
WR
TTL
Chip Select
TTL
Write
TTL
Note: I/O pin has protection diodes to VDD and VSS.
FIGURE 8-11:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
DS39026D-page 90
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 8-12:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 8-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on all
other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
Port Data Latch when written; Port pins when read
LATD Data Output bits
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
---- -000 ---- -000
---- -xxx ---- -uuu
0000 -111 0000 -111
0000 000x 0000 000u
TRISD
PORTE
LATE
PORTD Data Direction bits
—
—
—
—
—
—
—
—
—
—
—
RE2
RE1
RE0
LATE Data Output bits
PORTE Data Direction bits
TRISE
IBF
OBF
IBOV
PSPMODE
GIE/
GIEH
PEIE/
GIEL
INTCON
TMR0IF
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
PSPIF
PSPIE
PSPIP
ADFM
ADIF
ADIE
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
—
SSPIF
SSPIE
SSPIP
CCP1IF TMR2IF
TMR1IF 0000 0000 0000 0000
PIE1
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
IPR1
ADIP
ADCON1
ADCS2
PCFG3 PCFG2
PCFG1
PCFG0
--0- -000 --0- -000
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port.
1999-2013 Microchip Technology Inc.
DS39026D-page 91
PIC18CXX2
NOTES:
DS39026D-page 92
1999-2013 Microchip Technology Inc.
PIC18CXX2
Figure 9-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 9-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
9.0
TIMER0 MODULE
The Timer0 module has the following features:
• Software selectable as an 8-bit or 16-bit timer/
counter
The T0CON register (Register 9-1) is a readable and
writable register that controls all the aspects of Timer0,
including the prescale selection.
• Readable and writable
• Dedicated 8-bit software programmable prescaler
• Clock source selectable to be external or internal
• Interrupt-on-overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
• Edge select for external clock
REGISTER 9-1:
T0CON: TIMER0 CONTROL REGISTER
R/W-1
TMR0ON
bit 7
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
T0PS2
R/W-1
T0PS1
R/W-1
T0PS0
T08BIT
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2:0
TMR0ON: Timer0 On/Off Control bit
1= Enables Timer0
0= Stops Timer0
T08BIT: Timer0 8-bit/16-bit Control bit
1= Timer0 is configured as an 8-bit timer/counter
0= Timer0 is configured as a 16-bit timer/counter
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Timer0 Prescaler Assignment bit
1= TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
T0PS2:T0PS0: Timer0 Prescaler Select bits
111= 1:256 prescale value
110= 1:128 prescale value
101= 1:64 prescale value
100= 1:32 prescale value
011= 1:16 prescale value
010= 1:8 prescale value
001= 1:4 prescale value
000= 1:2 prescale value
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
1999-2013 Microchip Technology Inc.
DS39026D-page 93
PIC18CXX2
FIGURE 9-1:
TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus
FOSC/4
0
1
8
0
Sync with
Internal
Clocks
TMR0
Programmable
Prescaler
RA4/T0CKI
pin
1
(2 TCY delay)
T0SE
3
PSA
Set Interrupt
Flag bit TMR0IF
on Overflow
T0PS2, T0PS1, T0PS0
T0CS
Note:
Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 9-2:
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
FOSC/4
0
0
Sync with
Set Interrupt
Flag bit TMR0IF
on Overflow
TMR0
High Byte
Internal
Clocks
1
TMR0L
Programmable
Prescaler
T0CKI pin
1
8
(2 TCY delay)
T0SE
3
Read TMR0L
Write TMR0L
T0PS2, T0PS1, T0PS0
T0CS
PSA
8
8
TMR0H
8
Data Bus<7:0>
Note:
Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
DS39026D-page 94
1999-2013 Microchip Technology Inc.
PIC18CXX2
9.2.1
SWITCHING PRESCALER ASSIGNMENT
9.1
Timer0 Operation
Timer0 can operate as a timer or as a counter.
The prescaler assignment is fully under software con-
trol (i.e., it can be changed “on-the-fly” during program
execution).
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 regis-
ter is written, the increment is inhibited for the following
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
9.3
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h in 8-bit mode, or FFFFh
to 0000h in 16-bit mode. This overflow sets the TMR0IF
bit. The interrupt can be masked by clearing the
TMR0IE bit. The TMR0IE bit must be cleared in soft-
ware by the Timer0 module Interrupt Service Routine
before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the processor from SLEEP, since the
timer is shut-off during SLEEP.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment either on every
rising, or falling edge of pin RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit (T0SE). Clearing the T0SE bit selects the ris-
ing edge. Restrictions on the external clock input are
discussed below.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
9.4
16-Bit Mode Timer Reads and
Writes
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 9-2). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16-bits of Timer0 without
having to verify that the read of the high and low byte
were valid due to a rollover between successive reads
of the high and low byte.
9.2
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module. The prescaler is not readable or
writable.
The PSA and T0PS2:T0PS0 bits determine the pres-
caler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4,..., 1:256 are
selectable.
A write to the high byte of Timer0 must also take place
through the TMR0H buffer register. Timer0 high byte is
updated with the contents of TMR0H when a write
occurs to TMR0L. This allows all 16-bits of Timer0 to be
updated at once.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF TMR0, MOVWF
TMR0, BSF TMR0, x....etc.) will clear the prescaler
count.
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
TABLE 9-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on all
Value on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other
POR, BOR
RESETS
TMR0L Timer0 Module’s Low Byte Register
TMR0H Timer0 Module’s High Byte Register
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 000x 0000 000u
1111 1111 1111 1111
--11 1111 --11 1111
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
PSA
TMR0IF INT0IF
T0PS2 T0PS1
RBIF
T0CON
TRISA
TMR0ON
—
T08BIT
—
T0CS
T0SE
T0PS0
PORTA Data Direction Register
Legend: x= unknown, u= unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
1999-2013 Microchip Technology Inc.
DS39026D-page 95
PIC18CXX2
NOTES:
DS39026D-page 96
1999-2013 Microchip Technology Inc.
PIC18CXX2
Figure 10-1 is a simplified block diagram of the Timer1
module.
10.0 TIMER1 MODULE
The Timer1 module timer/counter has the following
features:
Register 10-1 details the Timer1 control register. This
register controls the operating mode of the Timer1
module, and contains the Timer1 oscillator enable bit
(T1OSCEN). Timer1 can be enabled or disabled by set-
ting or clearing control bit TMR1ON (T1CON<0>).
• 16-bit timer/counter
(two 8-bit registers: TMR1H and TMR1L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module special event trigger
REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
RD16
bit 7
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
RD16: 16-bit Read/Write Mode Enable bit
1= Enables register Read/Write of TImer1 in one 16-bit operation
0= Enables register Read/Write of Timer1 in two 8-bit operations
bit 6
Unimplemented: Read as '0'
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable bit
1= Timer1 Oscillator is enabled
0= Timer1 Oscillator is shut-off
The oscillator inverter and feedback resistor are turned off to eliminate power drain.
T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
TMR1CS: Timer1 Clock Source Select bit
bit 1
bit 0
1= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
1999-2013 Microchip Technology Inc.
DS39026D-page 97
PIC18CXX2
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
10.1 Timer1 Operation
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
Timer1 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 13.0).
FIGURE 10-1:
TIMER1 BLOCK DIAGRAM
CCP Special Event Trigger
TMR1IF
Overflow
Interrupt
Flag bit
Synchronized
TMR1
CLR
0
Clock Input
TMR1L
TMR1H
1
TMR1ON
On/Off
T1SYNC
T1OSC
1
T1CKI/T1OSO
T1OSI
Synchronize
det
T1OSCEN
Enable
Oscillator
Prescaler
1, 2, 4, 8
FOSC/4
Internal
(1)
0
Clock
2
SLEEP Input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 10-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR1H
8
8
Write TMR1L
Read TMR1L
CCP Special Event Trigger
0
TMR1IF
Overflow
Interrupt
Synchronized
Clock Input
TMR1
8
CLR
Timer 1
High Byte
TMR1L
Flag bit
1
TMR1ON
T1SYNC
On/Off
T1OSC
T13CKI/T1OSO
T1OSI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
FOSC/4
Internal
Clock
Enable
0
(1)
Oscillator
2
SLEEP Input
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39026D-page 98
1999-2013 Microchip Technology Inc.
PIC18CXX2
10.2 Timer1 Oscillator
10.4 Resetting Timer1 using a CCP
Trigger Output
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 10-1 shows the capacitor
selection for the Timer1 oscillator.
If the CCP module is configured in compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
Note: The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
TABLE 10-1: CAPACITOR SELECTION FOR
THE ALTERNATE
OSCILLATOR
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
Osc Type
Freq.
C1
C2
LP
32 kHz
TBD(1)
TBD(1)
In this mode of operation, the CCPR1H:CCPR1L regis-
ters pair effectively becomes the period register for
Timer1.
Crystal to be Tested:
32.768 kHz Epson C-001R32.768K-A
20
PPM
10.5 Timer1 16-Bit Read/Write Mode
Note 1: Microchip suggests 33 pF as a starting
point in validating the oscillator circuit.
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
Timer1 can be configured for 16-bit reads and writes
(see Figure 10-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16-bits of
Timer1, without having to determine whether a read of
the high byte, followed by a read of the low byte, is
valid, due to a rollover between reads.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Capacitor values are for design guidance
only.
A write to the high byte of Timer1 must also take place
through the TMR1H buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
TMR1H is updated from the high byte when TMR1L is
read.
10.3 Timer1 Interrupt
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled/disabled by setting/clear-
ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
The high byte of Timer1 is not directly readable or writ-
able in this mode. All reads and writes must take place
through the Timer1 high byte buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The pres-
caler is only cleared on writes to TMR1L.
1999-2013 Microchip Technology Inc.
DS39026D-page 99
PIC18CXX2
TABLE 10-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/
TMR0IE
INT0IE
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
0000 000x 0000 000u
GIEL
(1)
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
TMR2IF
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
TMR1IP 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
(1)
(1)
PIE1
CCP1IE TMR2IE
CCP1IP TMR2IP
IPR1
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
T1CON RD16
xxxx xxxx uuuu uuuu
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
DS39026D-page 100
1999-2013 Microchip Technology Inc.
PIC18CXX2
11.1 Timer2 Operation
11.0 TIMER2 MODULE
Timer2 can be used as the PWM time-base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable, and is cleared on any device
RESET. The input clock (FOSC/4) has a prescale option
of 1:1, 1:4, or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out-
put of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)).
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
• SSP module optional use of TMR2 output to gen-
erate clock shift
The prescaler and postscaler counters are cleared
when any of the following occurs:
Timer2 has a control register shown in Register 11-1.
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Figure 11-1 is a simplified block diagram of the Timer2
module. Register 11-1 shows the Timer2 control regis-
ter. The prescaler and postscaler selection of Timer2
are controlled by this register.
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 11-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as '0'
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
1999-2013 Microchip Technology Inc.
DS39026D-page 101
PIC18CXX2
11.2 Timer2 Interrupt
11.3 Output of TMR2
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module, which optionally uses
it to generate the shift clock.
FIGURE 11-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
TMR2
Output(1)
bit TMR2IF
Prescaler
RESET
TMR2
FOSC/4
1:1, 1:4, 1:16
Postscaler
2
Comparator
PR2
1:16
1:1 to
EQ
T2CKPS1:T2CKPS0
4
TOUTPS3:TOUTPS0
Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock.
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
all other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PIR1
PIE1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR2IF
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
TMR1IP 0000 0000 0000 0000
0000 0000 0000 0000
(1)
(1)
TXIE
TXIP
CCP1IE TMR2IE
CCP1IP TMR2IP
IPR1
TMR2
T2CON
PR2
Timer2 Module Register
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register 1111 1111 1111 1111
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
DS39026D-page 102
1999-2013 Microchip Technology Inc.
PIC18CXX2
Figure 12-1 is a simplified block diagram of the Timer3
module.
12.0 TIMER3 MODULE
The Timer3 module timer/counter has the following
features:
Register 12-1 shows the Timer3 control register. This
register controls the operating mode of the Timer3
module and sets the CCP clock source.
• 16-bit timer/counter
(two 8-bit registers: TMR3H and TMR3L)
Register 10-1 shows the Timer1 control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 oscillator
enable bit (T1OSCEN), which can be a clock source for
Timer3.
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module trigger
REGISTER 12-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0
RD16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 0
bit 7
bit 7
RD16: 16-bit Read/Write Mode Enable
1= Enables register Read/Write of Timer3 in one 16-bit operation
0= Enables register Read/Write of Timer3 in two 8-bit operations
bit 6-3
T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x= Timer3 is the clock source for compare/capture CCP modules
01= Timer3 is the clock source for compare/capture of CCP2,
Timer1 is the clock source for compare/capture of CCP1
00= Timer1 is the clock source for compare/capture CCP modules
bit 5-4
bit 2
T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
TMR3CS: Timer3 Clock Source Select bit
bit 1
bit 0
1= External clock input from Timer1 oscillator or T1CKI
(on the rising edge after the first falling edge)
0= Internal clock (FOSC/4)
TMR3ON: Timer3 On bit
1= Enables Timer3
0= Stops Timer3
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
1999-2013 Microchip Technology Inc.
DS39026D-page 103
PIC18CXX2
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
12.1 Timer3 Operation
Timer3 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
Timer3 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 12.0).
FIGURE 12-1:
TIMER3 BLOCK DIAGRAM
CCP Special Trigger
T3CCPx
TMR3IF
Overflow
Interrupt
Synchronized
Clock Input
0
Flag bit
CLR
TMR3L
TMR3H
T1OSC
1
TMR3ON
On/Off
T3SYNC
(3)
T1OSO/
T13CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
FOSC/4
Internal
Clock
0
(1)
T1OSI
Oscillator
2
SLEEP Input
TMR3CS
T3CKPS1:T3CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
FIGURE 12-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus<7:0>
8
TMR3H
8
8
Write TMR3L
Read TMR3L
CCP Special Trigger
T3CCPx
0
Synchronized
Clock Input
8
TMR3
Set TMR3IF Flag bit
on Overflow
CLR
Timer3
High Byte
TMR3L
1
To Timer1 Clock Input
TMR3ON
On/Off
T3SYNC
T1OSC
T1OSO/
T13CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FOSC/4
Internal
Clock
0
(1)
T1OSI
2
SLEEP Input
T3CKPS1:T3CKPS0
TMR3CS
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS39026D-page 104
1999-2013 Microchip Technology Inc.
PIC18CXX2
12.2 Timer1 Oscillator
12.4 Resetting Timer3 Using a CCP
Trigger Output
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON<3>) bit. The oscillator is a low
power oscillator rated up to 200 KHz. See Section 10.0
for further details.
If the CCP module is configured in Compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer3.
Note: The special event triggers from the CCP
module will not set interrupt flag bit
TMR3IF (PIR1<0>).
12.3 Timer3 Interrupt
The TMR3 Register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR3IF (PIR2<1>).
This interrupt can be enabled/disabled by setting/clear-
ing TMR3 interrupt enable bit, TMR3IE (PIE2<1>).
Timer3 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this RESET operation may not work. In the event that a
write to Timer3 coincides with a special event trigger
from CCP1, the write will take precedence. In this mode
of operation, the CCPR1H:CCPR1L registers pair
effectively becomes the period register for Timer3.
TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE/
GIEH
PEIE/
GIEL
INTCON
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
PIR2
—
—
—
—
—
—
—
—
—
—
—
—
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
TMR3IF
TMR3IE
TMR3IP
CCP2IF 0000 0000 0000 0000
CCP2IE 0000 0000 0000 0000
CCP2IP 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
RD16
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON -000 0000 -uuu uuuu
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
1999-2013 Microchip Technology Inc.
DS39026D-page 105
PIC18CXX2
NOTES:
DS39026D-page 106
1999-2013 Microchip Technology Inc.
PIC18CXX2
The operation of CCP1 is identical to that of CCP2, with
the exception of the special event trigger. Therefore,
operation of a CCP module in the following sections is
described with respect to CCP1.
13.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register, or as a PWM
master/slave Duty Cycle register. Table 13-1 shows the
timer resources of the CCP module modes.
Table 13-2 shows the interaction of the CCP modules.
REGISTER 13-1: CCP1CON REGISTER/CCP2CON REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCxB1
DCxB0
CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as '0'
DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Mode Select bits
0000= Capture/Compare/PWM off (resets CCPx module)
0001= Reserved
0010= Compare mode, toggle output on match (CCPxIF bit is set)
0011= Reserved
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode,
Initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set)
1001= Compare mode,
Initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set)
1010= Compare mode,
Generate software interrupt on compare match (CCPIF bit is set, CCP pin is
unaffected)
1011= Compare mode,
Trigger special event (CCPIF bit is set)
11xx= PWM mode
Legend:
R = Readable bit
- n = Value at POR reset
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc.
DS39026D-page 107
PIC18CXX2
13.1 CCP1 Module
13.2 CCP2 Module
Capture/Compare/PWM Register 1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
TABLE 13-1: CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
TABLE 13-2: INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Capture
TMR1 or TMR3 time-base. Time-base can be different for each CCP.
Compare The compare could be configured for the special event trigger,
which clears either TMR1, or TMR3, depending upon which time-base is used.
Compare
Compare The compare(s) could be configured for the special event trigger,
which clears TMR1, or TMR3, depending upon which time-base is used.
PWM
PWM
PWM
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt).
None.
Capture
Compare None.
DS39026D-page 108
1999-2013 Microchip Technology Inc.
PIC18CXX2
13.3.3
SOFTWARE INTERRUPT
13.3 Capture Mode
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in operating mode.
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 or TMR3 registers when an
event occurs on pin RC2/CCP1. An event is defined as:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
13.3.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 13-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
13.3.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
Note: If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
EXAMPLE 13-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF
CCP1CON, F ; Turn CCP module off
13.3.2
TIMER1/TIMER3 MODE SELECTION
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
The timers that are to be used with the capture feature
(either Timer1 and/or Timer3) must be running in Timer
mode or Synchronized Counter mode. In Asynchro-
nous Counter mode, the capture operation may not
work. The timer to be used with each CCP module is
selected in the T3CON register.
; value and CCP ON
; Load CCP1CON with
; this value
MOVWF CCP1CON
FIGURE 13-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
TMR3H
TMR3L
CCPR1L
TMR1L
Set Flag bit CCP1IF
T3CCP2
T3CCP2
TMR3
Enable
Prescaler
1, 4, 16
CCP1 pin
CCPR1H
TMR1
Enable
and
Edge Detect
TMR1H
CCP1CON<3:0>
Q’s
Set Flag bit CCP2IF
T3CCP1
TMR3H
TMR3L
CCPR2L
TMR1L
T3CCP2
TMR3
Enable
Prescaler
1, 4, 16
CCP2 pin
CCPR2H
TMR1
Enable
and
Edge Detect
T3CCP2
T3CCP1
TMR1H
CCP2CON<3:0>
Q’s
1999-2013 Microchip Technology Inc.
DS39026D-page 109
PIC18CXX2
13.4.2
TIMER1/TIMER3 MODE SELECTION
13.4 Compare Mode
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against either the TMR1
register pair value or the TMR3 register pair value.
When a match occurs, the RC2/CCP1 (RC1/CCP2) pin
is:
13.4.3
SOFTWARE INTERRUPT MODE
• driven High
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
• driven Low
• toggle output (High to Low or Low to High)
• remains unchanged
13.4.4
SPECIAL EVENT TRIGGER
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit, CCP1IF (CCP2IF) is set.
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
13.4.1
CCP PIN CONFIGURATION
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The user must configure the CCPx pin as an output by
clearing the appropriate TRISC bit.
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
The special trigger output of CCPx resets either the
TMR1 or TMR3 register pair. Additionally, the CCP2
Special Event Trigger will start an A/D conversion if the
A/D module is enabled.
Note: The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
FIGURE 13-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger will:
Reset Timer1or Timer3, but not set Timer1 or Timer3 Interrupt Flag bit,
and set bit GO/DONE (ADCON0<2>)
which starts an A/D Conversion (CCP2 only)
Special Event Trigger
Set Flag bit CCP1IF
CCPR1H CCPR1L
Comparator
Q
S
R
Output
Logic
Match
RC2/CCP1
pin
TRISC<2>
Output Enable
1
0
CCP1CON<3:0>
Mode Select
T3CCP2
TMR1H TMR1L
TMR3H TMR3L
Special Event Trigger
Set Flag bit CCP2IF
Match
T3CCP1
T3CCP2
0
1
Q
S
R
Output
Logic
Comparator
RC1/CCP2
pin
TRISC<1>
Output Enable
CCPR2H CCPR2L
CCP2CON<3:0>
Mode Select
DS39026D-page 110
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 13-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PEIE/
GIEL
INTCON
GIE/GIEH
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PIR1
PSPIF
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
1111 1111 1111 1111
(1)
PIE1
PSPIE
(1)
IPR1
PSPIP
TRISC
TMR1L
TMR1H
T1CON
CCPR1L
PORTC Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Capture/Compare/PWM Register1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register1 (MSB)
CCP1CON
CCPR2L
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register2 (LSB)
CCPR2H Capture/Compare/PWM Register2 (MSB)
xxxx xxxx uuuu uuuu
CCP2CON
PIR2
—
—
—
—
—
—
—
—
DC2B1
—
DC2B0
—
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
TMR3IF CCP2IF 0000 0000 0000 0000
TMR3IE CCP2IE 0000 0000 0000 0000
TMR3IP CCP2IP 0000 0000 0000 0000
PIE2
—
—
IPR2
—
—
TMR3L
TMR3H
T3CON
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON -000 0000 -uuu uuuu
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
1999-2013 Microchip Technology Inc.
DS39026D-page 111
PIC18CXX2
13.5.1
PWM PERIOD
13.5 PWM Mode
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
PWM period = (PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
Figure 13-3 shows a simplified block diagram of the
CCP module in PWM mode.
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 13.5.3.
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note: The Timer2 postscaler (see Section 11.0)
is not used in the determination of the
PWM frequency. The postscaler could be
used to have a servo update rate at a dif-
ferent frequency than the PWM output.
FIGURE 13-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
13.5.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
CCPR1H (Slave)
Comparator
Q
R
S
RC2/CCP1
(Note 1)
TMR2
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 prescale value)
TRISC<2>
Comparator
PR2
Clear Timer,
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read only register.
CCP1 pin and
latch D.C.
Note:
8-bit timer is concatenated with 2-bit internal Q clock or
2 bits of the prescaler to create 10-bit time-base.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
A PWM output (Figure 13-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
FIGURE 13-4:
PWM OUTPUT
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
Period
FOSC
log ---------------
FPWM
= ----------------------------- b i t s
log2
PWM Resolution (max)
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TMR2 = PR2
DS39026D-page 112
1999-2013 Microchip Technology Inc.
PIC18CXX2
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
13.5.3
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
1. Set the PWM period by writing to the PR2
register.
5. Configure the CCP1 module for PWM operation.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
TABLE 13-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz
9.77 kHz
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
0xFF
14
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
12
0xFF
10
0x17
6.58
Maximum Resolution (bits)
TABLE 13-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
CCP1IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PIR1
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
TMR2IF
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
TMR1IP 0000 0000 0000 0000
1111 1111 1111 1111
(1)
(1)
PIE1
CCP1IE TMR2IE
CCP1IP TMR2IP
IPR1
TRISC
TMR2
PR2
PORTC Data Direction Register
Timer2 Module Register
0000 0000 0000 0000
Timer2 Module Period Register
1111 1111 1111 1111
T2CON
CCPR1L
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Capture/Compare/PWM Register1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register1 (MSB)
CCP1CON
CCPR2L
—
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register2 (LSB)
CCPR2H Capture/Compare/PWM Register2 (MSB)
CCP2CON DC2B1 DC2B0
xxxx xxxx uuuu uuuu
—
—
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
1999-2013 Microchip Technology Inc.
DS39026D-page 113
PIC18CXX2
NOTES:
DS39026D-page 114
1999-2013 Microchip Technology Inc.
PIC18CXX2
14.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
14.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPITM
)
• Inter-Integrated Circuit (I2CTM
)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
• Master mode
• Multi-Master mode
• Slave mode
1999-2013 Microchip Technology Inc.
DS39026D-page 115
PIC18CXX2
14.2 Control Registers
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2).
REGISTER 14-1: SSPSTAT: MSSP STATUS REGISTER
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
SMP: Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2C Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select bit
CKP = 0:
1= Data transmitted on rising edge of SCK
0= Data transmitted on falling edge of SCK
CKP = 1:
1= Data transmitted on falling edge of SCK
0= Data transmitted on rising edge of SCK
bit 5
bit 4
D/A: Data/Address bit (I2C mode only)
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
P: STOP bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a STOP bit has been detected last (this bit is '0' on RESET)
0= STOP bit was not detected last
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39026D-page 116
1999-2013 Microchip Technology Inc.
PIC18CXX2
REGISTER 14-1: SSPSTAT: MSSP STATUS REGISTER (CONTINUED)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 3
bit 2
S: START bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a START bit has been detected last (this bit is '0' on RESET)
0= START bit was not detected last
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from
the address match to the next START bit, STOP bit, or not ACK bit.
In I2C Slave mode:
1= Read
0= Write
In I2C Master mode:
1= Transmit is in progress
0= Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in
IDLE mode.
bit 1
bit 0
UA: Update Address bit (10-bit I2C mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I2C modes):
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
Transmit (I2C mode only):
1= Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0= Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
1999-2013 Microchip Technology Inc.
DS39026D-page 117
PIC18CXX2
REGISTER 14-2: SSPCON1: MSSP CONTROL REGISTER1
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
Master mode:
1= A write to the SSPBUF register was attempted while the I2C conditions were not valid for a
transmission to be started
0= No collision
Slave mode:
1= The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0= No collision
bit 6
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.
In Slave mode, the user must read the SSPBUF, even if only transmitting data to avoid
setting overflow.
In Master mode, the overflow bit is not set, since each new reception (and transmission) is
initiated by writing to the SSPBUF register (must be cleared in software).
0= No overflow
In I2C mode:
1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a
“don’t care” in Transmit mode (must be cleared in software).
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In both modes when enabled, these pins must be properly configured as input or output.
In SPI mode:
1= Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial
port pins
0= Disables serial port and configures these pins as I/O port pins
In I2C mode:
1= Enables the serial port and configures the SDA and SCL pins as the source of the
serial port pins
0= Disables serial port and configures these pins as I/O port pins
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39026D-page 118
1999-2013 Microchip Technology Inc.
PIC18CXX2
REGISTER 14-2: SSPCON1: MSSP CONTROL REGISTER1 (CONTINUED)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= Idle state for clock is a high level
0= Idle state for clock is a low level
In I2C Slave mode:
SCK release control
1= Enable clock
0= Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2C Master mode:
Unused in this mode
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110= I2C Slave mode, 7-bit address
0111= I2C Slave mode, 10-bit address
1000= I2C Master mode, clock = FOSC / (4 * (SSPADD+1))
1001= Reserved
1010= Reserved
1011= I2C firmware controlled Master mode (Slave idle)
1100= Reserved
1101= Reserved
1110= I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled
1111= I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
1999-2013 Microchip Technology Inc.
DS39026D-page 119
PIC18CXX2
REGISTER 14-3: SSPCON2: MSSP CONTROL REGISTER2
R/W-0
GCEN
R/W-0
R/W-0
R/W-0
R/W-0
RCEN
R/W-0
PEN
R/W-0
RSEN
R/W-0
SEN
ACKSTAT
ACKDT
ACKEN
bit 7
bit 0
bit 7
bit 6
GCEN: General Call Enable bit (In I2C Slave mode only)
1= Enable interrupt when a general call address (0000h) is received in the SSPSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (In I2C Master mode only)
In Master Transmit mode:
1= Acknowledge was not received from slave
0= Acknowledge was received from slave
bit 5
bit 4
ACKDT: Acknowledge Data bit (In I2C Master mode only)
In Master Receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of
a receive.
1= Not Acknowledge
0= Acknowledge
ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only)
In Master Receive mode:
1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence idle
bit 3
bit 2
RCEN: Receive Enable bit (In I2C Master mode only)
1= Enables Receive mode for I2C
0= Receive idle
PEN: STOP Condition Enable bit (In I2C Master mode only)
SCK Release Control:
1= Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0= STOP condition idle
bit 1
bit 0
RSEN: Repeated START Condition Enabled bit (In I2C Master mode only)
1= Initiate Repeated START condition on SDA and SCL pins.
Automatically cleared by hardware.
0= Repeated START condition idle
SEN: START Condition Enabled bit (In I2C Master mode only)
1= Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0= START condition idle
Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS39026D-page 120
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 14-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
14.3 SPI Mode
The SPI mode allows 8-bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish communi-
cation, typically three pins are used:
Internal
Data Bus
Read
Write
• Serial Data Out (SDO) - RC5/SDO
• Serial Data In (SDI) - RC4/SDI/SDA
• Serial Clock (SCK) - RC3/SCK/SCL/LVOIN
SSPBUF reg
Additionally, a fourth pin may be used when in a Slave
mode of operation:
SSPSR reg
Shift
SDI
bit0
• Slave Select (SS) - RA5/SS/AN4
Clock
14.3.1
OPERATION
SDO
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0>) and SSPSTAT<7:6>.
These control bits allow the following to be specified:
Control
Enable
SS
SS
Edge
Select
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
2
Clock Select
• Data input sample phase (middle or end of data
output time)
SSPM3:SSPM0
• Clock edge (output data on rising/falling edge of
SCK)
SMP:CKE
2
4
TMR2 output
(
)
2
• Clock Rate (Master mode only)
Edge
Select
TOSC
Prescaler
4, 16, 64
• Slave Select mode (Slave mode only)
SCK
Figure 14-1 shows the block diagram of the MSSP
module, when in SPI mode.
Data to TX/RX in SSPSR
TRIS bit
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register. Then the buffer full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are
set. This double buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored, and the write collision detect bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the follow-
ing write(s) to the SSPBUF register completed
successfully.
1999-2013 Microchip Technology Inc.
DS39026D-page 121
PIC18CXX2
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the MSSP Interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 14-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
EXAMPLE 14-1:
LOADING THE SSPBUF (SSPSR) REGISTER
LOOP BTFSS SSPSTAT, BF
GOTO LOOP
;Has data been received(transmit complete)?
;No
MOVF SSPBUF, W
;WREG reg = contents of SSPBUF
MOVWF RXDATA
;Save in user RAM, if data is meaningful
MOVF TXDATA, W
MOVWF SSPBUF
;W reg = contents of TXDATA
;New data to xmit
The SSPSR is not directly readable or writable, and
can only be accessed by addressing the SSPBUF reg-
ister. Additionally, the MSSP status register (SSPSTAT)
indicates the various status conditions.
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> bit cleared
14.3.2
ENABLING SPI I/O
• SCK (Master mode) must have TRISC<3> bit cleared
• SCK (Slave mode) must have TRISC<3> bit set
• SS must have TRISC<4> bit set
To enable the serial port, SSP enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers, and then set the SSPEN bit. This
configures the SDI, SDO, SCK, and SS pins as serial
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value.
DS39026D-page 122
1999-2013 Microchip Technology Inc.
PIC18CXX2
trollers would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
14.3.3
TYPICAL CONNECTION
Figure 14-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite
edge of the clock. Both processors should be pro-
grammed to same Clock Polarity (CKP), then both con-
• Master sends data—Slave sends dummy data
• Master sends data—Slave sends data
• Master sends dummy data—Slave sends data
FIGURE 14-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
SDO
Shift Register
(SSPSR)
Shift Register
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
PROCESSOR 1
PROCESSOR 2
1999-2013 Microchip Technology Inc.
DS39026D-page 123
PIC18CXX2
Figure 14-3, Figure 14-5, and Figure 14-6, where the
MSB is transmitted first. In Master mode, the SPI clock
rate (bit rate) is user programmable to be one of the
following:
14.3.4
MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 14-2) is to broad-
cast data by the software protocol.
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
This allows a maximum data rate (at 40 MHz) of 10.00
Mbps.
Figure 14-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
The clock polarity is selected by appropriately program-
ming the CKP bit (SSPCON1<4>). This then, would
give waveforms for SPI communication as shown in
FIGURE 14-3:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit6
bit6
bit2
bit2
bit5
bit5
bit4
bit4
bit1
bit1
bit0
bit0
SDO
(CKE = 0)
bit7
bit7
bit3
bit3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit0
bit7
Input
Sample
(SMP = 1)
SSPIF
Next Q4 cycle
after Q2
SSPSR to
SSPBUF
DS39026D-page 124
1999-2013 Microchip Technology Inc.
PIC18CXX2
the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte, and becomes a floating
output. External pull-up/pull-down resistors may be
desirable, depending on the application.
14.3.5
SLAVE MODE
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
2: If the SPI is used in Slave mode with CKE
set, then the SS pin control must be
enabled.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
When the SPI module resets, the bit counter is forced
to 0. This can be done by either forcing the SS pin to a
high level, or clearing the SSPEN bit.
14.3.6
SLAVE SELECT
SYNCHRONIZATION
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function),
since it cannot create a bus conflict.
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control
enabled (SSPCON1<3:0> = 04h). The pin must not
be driven low for the SS pin to function as an input.
The Data Latch must be high. When the SS pin is
low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
FIGURE 14-4:
SLAVE SYNCHRONIZATION WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit6
bit7
bit7
bit0
SDO
bit7
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
SSPSR to
SSPBUF
after Q2
1999-2013 Microchip Technology Inc.
DS39026D-page 125
PIC18CXX2
FIGURE 14-5:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
bit6
bit2
bit5
bit4
bit1
bit0
SDO
bit7
bit3
SDI
(SMP = 0)
bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2
SSPSR to
SSPBUF
FIGURE 14-6:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
not optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
bit6
bit2
bit5
bit4
bit1
bit0
SDO
bit7
bit7
bit3
SDI
(SMP = 0)
bit0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2
SSPSR to
SSPBUF
DS39026D-page 126
1999-2013 Microchip Technology Inc.
PIC18CXX2
14.3.7
SLEEP OPERATION
14.3.9
BUS MODE COMPATIBILITY
In Master mode, all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to transmit/
receive data.
Table 14-1 shows the compatibility between the stan-
dard SPI modes and the states of the CKP and CKE
control bits.
TABLE 14-1: SPI BUS MODES
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode, and data to be
shifted into the SPI transmit/receive shift register.
When all 8-bits have been received, the MSSP inter-
rupt flag bit will be set and if enabled, will wake the
device from SLEEP.
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
14.3.8
EFFECTS OF A RESET
There is also a SMP bit which controls when the data is
sampled.
A RESET disables the MSSP module and terminates
the current transfer.
TABLE 14-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH
PEIE/
GIEL
TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PIR1
PSPIF
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
SSPIP
CCP1IF
CCP1IE
CCP1IP
TMR2IF TMR1IF 0000 0000 0000 0000
TMR2IE TMR1IE 0000 0000 0000 0000
TMR2IP TMR1IP 0000 0000 0000 0000
1111 1111 1111 1111
(1)
PIE1
PSPIE
(1)
IPR1
PSPIP
TRISC
SSPBUF
SSPCON
TRISA
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
WCOL
—
SSPOV SSPEN
PORTA Data Direction Register
CKE D/A
CKP
SSPM3
SSPM2
R/W
SSPM1
SSPM0 0000 0000 0000 0000
--11 1111 --11 1111
SSPSTAT
SMP
P
S
UA
BF
0000 0000 0000 0000
Legend: x= unknown, u= unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
1999-2013 Microchip Technology Inc.
DS39026D-page 127
PIC18CXX2
The SSPCON1 register allows control of the I2C oper-
ation. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
• I2C Master mode, clock = OSC/4 (SSPADD +1)
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
2
14.4 MSSP I C Operation
The MSSP module in I2C mode, fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits
in hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
• I2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled
Two pins are used for data transfer. These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISC<4:3> bits.
• I2C Slave mode (10-bit address), with START and
STOP bit interrupts enabled
• I2C Firmware controlled master operation, slave
is idle
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to be inputs by set-
ting the appropriate TRISC bits.
The MSSP module functions are enabled by setting
MSSP enable bit SSPEN (SSPCON<5>).
FIGURE 14-7:
MSSP BLOCK DIAGRAM
(I2C MODE)
14.4.1
SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
Internal
Data Bus
Read
Write
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value cur-
rently in the SSPSR register.
SSPBUF reg
RC3/SCK/SCL
Shift
Clock
SSPSR reg
There are certain conditions that will cause the MSSP
module not to give this ACK pulse. These are if either
(or both):
RC4/
SDI/
SDA
MSb
LSb
Addr Match
Match Detect
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b) The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
SSPADD reg
START and
Set, Reset
S, P bits
(SSPSTAT reg)
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
STOP bit Detect
The MSSP module has six registers for I2C operation.
These are the:
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
and parameter #101.
• MSSP Control Register1 (SSPCON1)
• MSSP Control Register2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) - Not directly
accessible
• MSSP Address Register (SSPADD)
DS39026D-page 128
1999-2013 Microchip Technology Inc.
PIC18CXX2
14.4.1.1
Addressing
14.4.1.2
Reception
Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START con-
dition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
a) The SSPSR register value is loaded into the
SSPBUF register.
b) The buffer full bit BF is set.
c) An ACK pulse is generated.
14.4.1.3
Transmission
d) MSSP interrupt flag bit SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) on the falling
edge of the ninth SCL pulse.
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Then pin RC3/SCK/SCL should be enabled by set-
ting bit CKP (SSPCON<4>). The master must monitor
the SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 14-9).
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write so
the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘1111 0
A9 A8 0’, where A9 and A8are the two MSbs of the
address. The sequence of events for 10-bit address is
as follows, with steps 7-9 for slave-transmitter:
1. Receive first (high) byte of Address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
As a slave-transmitter, the ACK pulse from the
master-receiver is latched on the rising edge of the
ninth SCL input pulse. If the SDA line is high (not ACK),
then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset (resets
SSPSTAT register) and the slave monitors for another
occurrence of the START bit. If the SDA line was low
(ACK), the transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Pin RC3/SCK/SCL should be enabled by setting bit
CKP.
5. Update the SSPADD register with the first (high)
byte of Address. If match releases SCL line, this
will clear bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated START condition.
8. Receive first (high) byte of Address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
1999-2013 Microchip Technology Inc.
DS39026D-page 129
PIC18CXX2
FIGURE 14-8:
I2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address
A7 A6 A5 A4
R/W=0
Receiving Data
Receiving Data
ACK
Not ACK
D0
ACK
9
SDA
A3 A2 A1
D5
D2
D0
8
D5
D2
D7 D6
D4 D3
D1
7
D7 D6
D4 D3
D1
7
1
2
3
4
5
6
9
1
2
3
4
9
8
5
6
1
2
3
4
5
6
7
8
P
SCL
S
SSPIF
Bus Master
terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF register is read
SSPOV (SSPCON1<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
FIGURE 14-9:
I2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
R/W = 0
Receiving Address
A7 A6 A5 A4 A3 A2 A1
R/W = 1
ACK
Transmitting Data
Not ACK
SDA
SCL
D7 D6 D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
S
P
SCL held low
while CPU
responds to SSPIF
Data in
sampled
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is written in software
From SSP Interrupt
Service Routine
CKP (SSPCON1<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
DS39026D-page 130
1999-2013 Microchip Technology Inc.
PIC18CXX2
2
FIGURE 14-10:
I C SLAVE MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS)
1999-2013 Microchip Technology Inc.
DS39026D-page 131
PIC18CXX2
2
FIGURE 14-11:
I C SLAVE MODE WAVEFORM (RECEPTION 10-BIT ADDRESS)
DS39026D-page 132
1999-2013 Microchip Technology Inc.
PIC18CXX2
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit),
the SSPIF interrupt flag bit is set.
14.4.2
GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is such that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address which
can address all devices. When this address is used, all
devices should, in theory, respond with an acknowl-
edge.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit address mode, then the second
half of the address is not necessary, the UA bit will not
be set, and the slave will begin receiving data after the
Acknowledge (Figure 14-12).
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0.
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is enabled (SSPCON2<7>
is set). Following a START bit detect, 8-bits are shifted
into the SSPSR and the address is compared against
the SSPADD. It is also compared to the general call
address and fixed in hardware.
FIGURE 14-12:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
Address is compared to General Call Address
after ACK, set interrupt
Receiving Data
D5 D4 D3 D2 D1
ACK
R/W = 0
General Call Address
ACK
SDA
SCL
D7 D6
D0
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
9
S
SSPIF
BF (SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV (SSPCON1<6>)
GCEN (SSPCON2<7>)
'0'
'1'
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP interrupt, if enabled):
14.4.3
MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET or when the MSSP module is
disabled. Control of the I2C bus may be taken when the
P bit is set, or the bus is idle, with both the S and P bits
clear.
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge Transmit
• Repeated START
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
1999-2013 Microchip Technology Inc.
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PIC18CXX2
14.4.4
I2C MASTER MODE SUPPORT
Note: The MSSP module, when configured in I2C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
imitate transmission, before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. Once Master mode is enabled, the user
has six options.
1. Assert a START condition on SDA and SCL.
2. Assert a Repeated START condition on SDA
and SCL.
3. Write to the SSPBUF register initiating transmis-
sion of data/address.
4. Generate a STOP condition on SDA and SCL.
5. Configure the I2C port to receive data.
6. Generate an Acknowledge condition at the end
of a received byte of data.
2
FIGURE 14-13:
MSSP BLOCK DIAGRAM (I C MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
SDA
Shift
Clock
SDA in
MSb
LSb
START bit, STOP bit,
Acknowledge
Generate
SCL
START bit Detect
STOP bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL in
Bus Collision
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
DS39026D-page 134
1999-2013 Microchip Technology Inc.
PIC18CXX2
I2C Master Mode Operation
A typical transmit sequence would go as follows:
a) The user generates a START condition by set-
14.4.4.1
The master device generates all of the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a Repeated
START condition. Since the Repeated START condi-
tion is also the beginning of the next serial transfer, the
I2C bus will not be released.
ting
the
START
enable
bit,
SEN
(SSPCON2<0>).
b) SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
c) The user loads the SSPBUF with the address to
transmit.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic '0'. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the
end of a serial transfer.
d) Address is shifted out the SDA pin until all 8 bits
are transmitted.
e) The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
f) The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic '1'. Thus, the first byte transmitted is a 7-bit slave
address followed by a '1' to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an Acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of transmission.
g) The user loads the SSPBUF with eight bits of
data.
h) Data is shifted out the SDA pin until all 8 bits are
transmitted.
i) The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
j) The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The baud rate generator used for the SPI mode opera-
tion is now used to set the SCL clock frequency for
either 100 kHz, 400 kHz, or 1 MHz I2C operation. The
baud rate generator reload value is contained in the
lower 7 bits of the SSPADD register. The baud rate
generator will automatically begin counting on a write to
the SSPBUF. Once the given operation is complete,
(i.e., transmission of the last data bit is followed by
ACK), the internal clock will automatically stop counting
and the SCL pin will remain in its last state.
k) The user generates a STOP condition by setting
the STOP enable bit, PEN (SSPCON2<2>).
l) Interrupt is generated once the STOP condition
is complete.
1999-2013 Microchip Technology Inc.
DS39026D-page 135
PIC18CXX2
remented twice per instruction cycle (TCY) on the Q2
and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically. If Clock Arbitration is taking
place, for instance, the BRG will be reloaded when the
SCL pin is sampled high (Figure 14-15).
14.4.5
BAUD RATE GENERATOR
In I2C Master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 14-14). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is dec-
FIGURE 14-14:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
BRG Down Counter
CLKOUT
FOSC/4
FIGURE 14-15:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX-1
SCL de-asserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count.
BRG
Reload
DS39026D-page 136
1999-2013 Microchip Technology Inc.
PIC18CXX2
14.4.6
I2C MASTER MODE START
CONDITION TIMING
14.4.6.1
WCOL Status Flag
If the user writes the SSPBUF when a START
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
To initiate a START condition, the user sets the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate genera-
tor is reloaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low, while SCL is high, is the START condition
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (TBRG), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware, the baud rate generator is suspended
leaving the SDA line held low and the START condition
is complete.
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
Note: If, at the beginning of the START condition,
the SDA and SCL pins are already sam-
pled low, or if during the START condition,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF is set, the START condition is
aborted, and the I2C module is reset into its
IDLE state.
FIGURE 14-16:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
Write to SEN bit occurs here.
SDA = 1,
At completion of START bit,
Hardware clears SEN bit
and sets SSPIF bit
SCL = 1
TBRG
TBRG
Write to SSPBUF occurs here
2nd Bit
1st Bit
SDA
TBRG
SCL
TBRG
S
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DS39026D-page 137
PIC18CXX2
I2C MASTER MODE REPEATED
START CONDITION TIMING
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode), or eight bits of data (7-bit
mode).
14.4.7
A Repeated START condition occurs when the RSEN
bit (SSPCON2<1>) is programmed high and the I2C
logic module is in the idle state. When the RSEN bit is
set, the SCL pin is asserted low. When the SCL pin is
sampled low, the baud rate generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one baud rate
generator count (TBRG). When the baud rate generator
times out, if SDA is sampled high, the SCL pin will be
de-asserted (brought high). When SCL is sampled
high, the baud rate generator is reloaded with the con-
tents of SSPADD<6:0> and begins counting. SDA and
SCL must be sampled high for one TBRG. This action is
then followed by assertion of the SDA pin (SDA = 0) for
one TBRG, while SCL is high. Following this, the RSEN
bit (SSPCON2<1>) will be automatically cleared and
the baud rate generator will not be reloaded, leaving
the SDA pin held low. As soon as a START condition is
detected on the SDA and SCL pins, the S bit
(SSPSTAT<3>) will be set. The SSPIF bit will not be set
until the baud rate generator has timed out.
14.4.7.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated
START sequence is in progress, the WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated
START condition occurs if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
FIGURE 14-17:
REPEAT START CONDITION WAVEFORM
Set S (SSPSTAT<3>)
Write to SSPCON2
occurs here.
SDA = 1,
SDA = 1,
SCL = 1
At completion of START bit,
hardware clear RSEN bit
and set SSPIF
SCL (no change)
TBRG
TBRG
TBRG
1st Bit
SDA
Write to SSPBUF occurs here.
TBRG
Falling edge of ninth clock
End of Xmit
SCL
TBRG
Sr = Repeated START
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14.4.8
I2C MASTER MODE
TRANSMISSION
14.4.8.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0), and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
Transmission of a data byte, a 7-bit address, or the
other half of a 10-bit address, is accomplished by sim-
ply writing a value to the SSPBUF register. This action
will set the buffer full flag bit, BF, and allow the baud
rate generator to begin counting and start the next
transmission. Each bit of address/data will be shifted
out onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification parameter
106). SCL is held low for one baud rate generator roll-
over count (TBRG). Data should be valid before SCL is
released high (see Data setup time specification
parameter 107). When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
allowing the slave device being addressed to respond
with an ACK bit during the ninth bit time, if an address
match occurs, or if data was received properly. The sta-
tus of ACK is written into the ACKDT bit on the falling
edge of the ninth clock. If the master receives an
Acknowledge, the Acknowledge status bit, ACKSTAT,
is cleared. If not, the bit is set. After the ninth clock, the
SSPIF bit is set and the master clock (baud rate gener-
ator) is suspended until the next data byte is loaded into
the SSPBUF, leaving SCL low and SDA unchanged
(Figure 14-18).
14.4.9
I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
receive enable bit, RCEN (SSPCON2<3>).
Note: The MSSP module must be in an IDLE
state before the RCEN bit is set, or the
RCEN bit will be disregarded.
The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bit is set and the baud rate genera-
tor is suspended from counting, holding SCL low. The
MSSP is now in IDLE state, awaiting the next com-
mand. When the buffer is read by the CPU, the BF flag
bit is automatically cleared. The user can then send an
Acknowledge bit at the end of reception, by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>).
14.4.9.1
BF Status Flag
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock, the master will de-assert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared and the baud rate generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
14.4.9.2
SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
14.4.9.3
WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn’t occur).
14.4.8.1
BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared, when
all 8 bits are shifted out.
14.4.8.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress, (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
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2
FIGURE 14-18:
I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
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PIC18CXX2
2
FIGURE 14-19:
I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
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14.4.10 ACKNOWLEDGE SEQUENCE
TIMING
14.4.11 STOP CONDITION TIMING
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the STOP sequence enable
bit, PEN (SSPCON2<2>). At the end of a receive/trans-
mit, the SCL line is held low after the falling edge of the
ninth clock. When the PEN bit is set, the master will
assert the SDA line low. When the SDA line is sampled
low, the baud rate generator is reloaded and counts
down to 0. When the baud rate generator times out, the
SCL pin will be brought high, and one TBRG (baud rate
generator rollover count) later, the SDA pin will be
de-asserted. When the SDA pin is sampled high while
SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG
later, the PEN bit is cleared and the SSPIF bit is set
(Figure 14-21).
An Acknowledge sequence is enabled by setting the
Acknowledge
sequence
enable
bit,
ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
is presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The baud rate gen-
erator then counts for one rollover period (TBRG) and the
SCL pin is de-asserted (pulled high). When the SCL pin
is sampled high (clock arbitration), the baud rate gener-
ator counts for TBRG. The SCL pin is then pulled low. Fol-
lowing this, the ACKEN bit is automatically cleared, the
baud rate generator is turned off and the MSSP module
then goes into IDLE mode (Figure 14-20).
14.4.11.1 WCOL Status Flag
If the user writes the SSPBUF when a STOP sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
14.4.10.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 14-20:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
ACK
TBRG
SDA
SCL
D0
8
9
SSPIF
Cleared in
software
Set SSPIF at the end
of receive
Cleared in
software
Set SSPIF at the end
of Acknowledge sequence
Note: TBRG = one baud rate generator period.
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PIC18CXX2
FIGURE 14-21:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1 for Tbrg, followed by SDA = 1 for Tbrg
after SDA sampled high. P bit (SSPSTAT<4>) is set
Write to SSPCON2
Set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
ACK
SDA
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup STOP condition.
Note: TBRG = one baud rate generator period.
14.4.12 CLOCK ARBITRATION
14.4.13 SLEEP OPERATION
Clock arbitration occurs when the master, during any
receive, transmit, or Repeated START/STOP condi-
tion, de-asserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin is actually sampled high. When the SCL pin is
sampled high, the baud rate generator is reloaded with
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event that the clock
is held low by an external device (Figure 14-22).
While in SLEEP mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the MSSP interrupt is enabled).
14.4.14 EFFECT OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
FIGURE 14-22:
CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1, Load BRG with
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
SSPADD<6:0>, and start count
to measure high time interval
SCL = 1 BRG starts counting
clock high interval.
SCL
SCL line sampled once every machine cycle (TOSC² 4).
Hold off BRG until SCL is sampled high.
SDA
TBRG
TBRG
TBRG
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SDA is a '1' and the data sampled on the SDA pin = '0',
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its IDLE state (Figure 14-23).
14.4.15 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET, or
when the MSSP module is disabled. Control of the I2C
bus may be taken when the P bit (SSPSTAT<4>) is set,
or the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP interrupt will gener-
ate the interrupt when the STOP condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user services
the bus collision Interrupt Service Routine, and if the
I2C bus is free, the user can resume communication by
asserting a START condition.
In multi-master operation, the SDA line must be moni-
tored, for arbitration, to see if the signal level is the
expected output level. This check is performed in hard-
ware, with the result placed in the BCLIF bit.
If a START, Repeated START, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user ser-
vices the bus collision Interrupt Service Routine, and if
the I2C bus is free, the user can resume communication
by asserting a START condition.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A START Condition
• A Repeated START Condition
• An Acknowledge Condition
The master will continue to monitor the SDA and SCL
pins. If a STOP condition occurs, the SSPIF bit will be
set.
14.4.16 MULTI -MASTER
COMMUNICATION, BUS
COLLISION, AND BUS
ARBITRATION
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA by letting SDA float high and
another master asserts a '0'. When the SCL pin floats
high, data should be stable. If the expected data on
FIGURE 14-23:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
SDA line pulled low
by another source
Data changes
while SCL = 0
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
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PIC18CXX2
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 14-26). If, however, a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0, and during this time, if the SCL pins
are sampled as '0', a bus collision does not occur. At
the end of the BRG count, the SCLpin is asserted low.
14.4.16.1 Bus Collision During a START
Condition
During a START condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the START condition (Figure 14-24).
b) SCL is sampled low before SDA is asserted low
(Figure 14-25).
During a START condition, both the SDA and the SCL
pins are monitored.
Note: The reason that bus collision is not a factor
during a START condition, is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision, because the two masters must be
allowed to arbitrate the first address follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
START, or STOP conditions.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the START condition is aborted,
• the BCLIF flag is set, and
•
the MSSP module is reset to its IDLE state
(Figure 14-24).
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START condition.
FIGURE 14-24:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
. Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable START
condition if SDA = 1, SCL=1
SEN cleared automatically because of bus collision.
SSP module reset into idle state.
SDA sampled low before
START condition.
Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
BCLIF
SSPIF and BCLIF are
cleared in software
S
SSPIF
SSPIF and BCLIF are
cleared in software
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FIGURE 14-25:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
SCL
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1
SCL = 0 before SDA = 0,
Bus collision occurs, set BCLIF
SCL = 0 before BRG time-out,
Bus collision occurs, set BCLIF
BCLIF
Interrupt cleared
in software
S
'0'
'0'
'0'
'0'
SSPIF
FIGURE 14-26:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
S
SCL pulled low after BRG
Time-out
SEN
Set SEN, enable START
sequence if SDA = 1, SCL = 1
BCLIF
'0'
S
SSPIF
Interrupts cleared
in software
SDA = 0, SCL = 1
Set SSPIF
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PIC18CXX2
reloaded and begins counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs
because no two masters can assert SDA at exactly the
same time.
14.4.16.2 Bus Collision During a Repeated
START Condition
During a Repeated START condition, a bus collision
occurs if:
If SCL goes from high to low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ’1’ during the Repeated START condi-
tion, Figure 14-28.
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to trans-
mit a data ’1’.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is
complete.
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD<6:0>
and counts down to 0. The SCL pin is then de-asserted,
and when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit
a
data ’0’,
Figure 14-27). If SDA is sampled high, the BRG is
FIGURE 14-27:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared in software
'0'
S
'0'
SSPIF
FIGURE 14-28:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
BCLIF
RSEN
Set BCLIF. Release SDA and SCL.
Interrupt cleared
in software
'0'
S
SSPIF
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The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the baud rate generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data '0' (Figure 14-29). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master attempt-
ing to drive a data '0' (Figure 14-30).
14.4.16.3 Bus Collision During a STOP
Condition
Bus collision occurs during a STOP condition if:
a) After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is de-asserted, SCL is sam-
pled low before SDA goes high.
FIGURE 14-29:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
TBRG
TBRG
TBRG
low after TBRG,
Set BCLIF
SDA
SDA asserted low
SCL
PEN
BCLIF
P
'0'
'0'
SSPIF
FIGURE 14-30:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high
Set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
'0'
'0'
SSPIF
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The USART can be configured in the following modes:
15.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
In order to configure pins RC6/TX/CK and RC7/RX/DT
as the Universal Synchronous Asynchronous Receiver
Transmitter:
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
munications Interface or SCI.) The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT ter-
minals and personal computers, or it can be configured
as a half-duplex synchronous system that can commu-
nicate with peripheral devices, such as A/D or D/A inte-
grated circuits, serial EEPROMs, etc.
• bit SPEN (RCSTA<7>) must be set (= 1), and
• bits TRISC<7:6> must be cleared (= 0).
Register 15-1 shows the Transmit Status and Control
Register (TXSTA) and Register 15-2 shows the
Receive Status and Control Register (RCSTA).
REGISTER 15-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
R/W-0
TX9D
TRMT
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4
SYNC: USART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3
bit 2
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of transmit data. Can be Address/Data bit or a parity bit.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’0’ = Bit is cleared
x = Bit is unknown
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REGISTER 15-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
R-0
R-0
R-x
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0= Serial port disabled
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave:
Unused in this mode
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables continuous receive
0= Disables continuous receive
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enable interrupt and load of the receive buffer
when RSR<8> is set
0= Disables address detection, all bytes are received, and ninth bit can be used as parity bit
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of received data, can be Address/Data bit or a parity bit.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
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Example 15-1 shows the calculation of the baud rate
error for the following conditions:
15.1 USART Baud Rate Generator
(BRG)
• FOSC = 16 MHz
• Desired Baud Rate = 9600
• BRGH = 0
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 15-1 shows the formula for computation of the
baud rate for different USART modes, which only apply
in Master mode (internal clock).
• SYNC = 0
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 15-1. From this, the error in
baud rate can be determined.
15.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
EXAMPLE 15-1:
Desired Baud Rate
Solving for X:
CALCULATING BAUD RATE ERROR
=
FOSC / (64 (X + 1))
X
X
X
=
=
=
( (FOSC / Desired Baud rate) / 64 ) - 1
((16000000 / 9600) / 64) - 1
[25.042] = 25
Calculated Baud Rate
=
=
16000000 / (64 (25 + 1))
9615
Error
=
(Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
=
=
(9615 - 9600) / 9600
0.16%
TABLE 15-1: BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
Baud Rate = FOSC/(16(X+1))
NA
Legend: X = value in SPBRG (0 to 255)
TABLE 15-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on
POR,
Value on all
other
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
TXSTA
RCSTA
SPBRG
CSRC
SPEN
TX9
RX9
TXEN SYNC
—
BRGH TRMT TX9D 0000 -010
0000 -010
0000 -00x
0000 0000
SREN CREN ADDEN FERR OERR RX9D 0000 -00x
0000 0000
Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
1999-2013 Microchip Technology Inc.
DS39026D-page 151
PIC18CXX2
TABLE 15-3: BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 40 MHz
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 10 MHz
BAUD
RATE
(K)
SPBRG Actua
SPBRG Actual
SPBRG Actual
SPBRG
value
(decimal)
Actual
Rate (K) Error
%
%
Error
%
Error
%
Error
value
l Rate
(K)
value
Rate
(K)
value
Rate
(K)
(decimal)
(decimal)
(decimal)
0.3
1.2
NA
NA
—
—
—
—
—
0
—
—
NA
NA
—
—
—
—
NA
NA
—
—
—
—
NA
NA
—
—
—
—
2.4
NA
—
NA
—
—
NA
—
—
NA
—
—
9.6
NA
—
NA
—
—
NA
—
—
9.766
19.23
75.76
96.15
312.5
500
+1.73
+0.16
-1.36
+0.16
+4.17
0
255
129
32
25
7
19.2
76.8
96
NA
—
19.53
76.92
96.15
294.1
500
+1.73
+0.16
+0.16
-1.96
0
255
64
51
16
9
19.23
76.92
95.24
+0.16
+0.16
-0.79
207
51
41
12
7
76.92
96.15
303.03
500.00
39.06
129
103
32
19
255
0
0
300
500
HIGH
-0.01
0
307.69 +2.56
500
4000
0
4
—
—
5000
19.53
—
0
—
—
0
2500
9.766
—
0
LOW 10000.00
—
255
15.625
255
—
255
FOSC = 7.15909 MHz
FOSC = 5.0688 MHz
FOSC = 4 MHz
FOSC = 3.579545 MHz
BAUD
RATE Actual
SPBRG Actual
SPBRG Actual
SPBRG Actual
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
%
Error
(K)
Rate
(K)
value
Rate
(K)
value
Rate
(K)
value
Rate
(K)
(decimal)
(decimal)
(decimal)
0.3
1.2
NA
NA
—
—
—
—
NA
NA
—
—
—
—
NA
NA
—
—
——
—
NA
—
—
—
—
—
92
46
11
8
NA
2.4
NA
—
—
NA
—
—
NA
—
—
NA
—
9.6
9.622
19.24
77.82
94.20
298.3
NA
+0.23
+0.23
+1.32
-1.88
-0.57
—
185
92
22
18
5
9.6
0
131
65
15
12
3
9.615
+0.16
103
51
12
9
9.622
19.04
74.57
99.43
298.3
NA
+0.23
-0.83
-2.90
+3.57
-0.57
—
19.2
76.8
96
19.2
79.2
97.48
316.8
NA
0
19.231 +0.16
76.923 +0.16
+3.13
+1.54
+5.60
—
1000
NA
+4.17
—
300
500
—
2
—
—
NA
—
—
—
0
HIGH 1789.8
—
0
1267
4.950
—
0
100
—
0
894.9
3.496
—
LOW
6.991
—
255
—
255
3.906
—
255
—
255
FOSC = 1 MHz
FOSC = 32.768 kHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
value
SPBRG
value
(decimal)
%
Error
%
Error
Rate
(K)
(decimal)
0.3
1.2
NA
1.202
2.404
9.615
19.24
83.34
NA
—
+0.16
+0.16
+0.16
+0.16
+8.51
—
—
207
103
25
12
2
0.303
1.170
NA
+1.14
-2.48
—
26
6
2.4
—
—
—
—
—
—
—
0
9.6
NA
—
19.2
76.8
96
NA
—
NA
—
—
NA
—
300
500
HIGH
NA
—
—
NA
—
NA
—
—
NA
—
250
—
0
8.192
0.032
—
LOW 0.9766
—
255
—
255
DS39026D-page 152
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 15-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 40 MHz
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 10 MHz
BAUD
RATE Actual
SPBRG Actual
SPBRG Actual
SPBRG Actual
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
%
Error
(K)
Rate
(K)
value
Rate
(K)
value
Rate
(K)
value
Rate
(K)
(decimal)
(decimal)
(decimal)
0.3
1.2
NA
NA
—
—
—
255
64
32
7
NA
—
—
255
129
32
15
3
NA
1.202
2.404
9.615
19.23
83.33
NA
—
+0.16
+0.16
+0.16
+0.16
+8.51
—
—
207
103
25
12
2
NA
1.202
2.404
9.766
19.53
78.13
NA
—
+0.16
+0.16
+1.73
+1.73
+1.73
—
—
129
64
15
7
—
1.221
2.404
9.469
19.53
78.13
104.2
312.5
NA
+1.73
+0.16
-1.36
+1.73
+1.73
+8.51
+4.17
—
2.4
2.44
-1.70
-0.16
+1.38
-1.70
+7.52
-4.00
9.6
9.62
19.2
76.8
96
18.94
78.13
89.29
312.50
1
6
2
—
—
—
—
0
300
500
HIGH
1
0
NA
—
—
NA
—
625.00 -20.00
0
—
0
NA
—
—
NA
—
2.44
—
—
255
0
312.5
1.221
—
250
—
0
156.3
0.6104
—
LOW 625.00
—
255
0.977
—
255
—
255
FOSC = 7.15909 MHz
FOSC = 5.0688 MHz
FOSC = 4 MHz
FOSC = 3.579545 MHz
BAUD
RATE Actual
SPBRG Actual
SPBRG Actual
SPBRG Actual
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
%
Error
(K)
Rate
(K)
value
Rate
(K)
value
Rate
(K)
value
Rate
(K)
(decimal)
(decimal)
(decimal)
0.3
1.2
NA
1.203
2.380
9.322
18.64
NA
—
+0.23
-0.83
-2.90
-2.90
—
—
92
46
11
5
0.31
1.2
+3.13
0
255
65
32
7
0.3005
1.202
2.404
NA
-0.17
+1.67
+1.67
—
207
51
25
—
0.301
1.190
2.432
9.322
18.64
NA
+0.23
-0.83
+1.32
-2.90
-2.90
—
185
46
22
5
2.4
2.4
0
9.6
9.9
+3.13
+3.13
+3.13
—
19.2
76.8
96
19.8
79.2
NA
3
NA
—
—
2
—
—
—
—
0
0
NA
—
—
—
—
—
—
0
NA
—
—
—
—
0
NA
—
—
NA
—
300
500
HIGH
LOW
NA
—
NA
—
NA
—
—
NA
—
NA
—
NA
—
NA
—
—
NA
—
111.9
0.437
—
79.2
0.3094
—
62.500
3.906
—
0
55.93
0.2185
—
—
255
—
255
—
255
—
255
FOSC = 1 MHz
FOSC = 32.768 kHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
value
SPBRG
value
(decimal)
%
Error
%
Error
Rate
(K)
(decimal)
0.3
1.2
0.300
1.202
2.232
NA
+0.16
+0.16
-6.99
—
51
12
6
0.256
NA
-14.67
—
1
—
—
—
—
—
—
—
—
0
2.4
NA
—
9.6
—
—
—
—
—
—
0
NA
—
19.2
76.8
96
NA
—
NA
—
NA
—
NA
—
NA
—
NA
—
300
500
HIGH
NA
—
NA
—
NA
—
NA
—
15.63
—
0.512
0.0020
—
LOW 0.0610
—
255
—
255
1999-2013 Microchip Technology Inc.
DS39026D-page 153
PIC18CXX2
TABLE 15-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 40 MHz
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 10 MHz
BAUD
RATE Actual
SPBRG Actual
SPBRG Actual
SPBRG Actual
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
%
Error
(K)
Rate
(K)
value
Rate
(K)
value
Rate
(K)
value
Rate
(K)
(decimal)
(decimal)
(decimal)
9.6
19.2
38.4
57.6
115.2
250
9.77
19.23
38.46
58.14
113.64
250.00
625.00
-1.70
-0.16
-0.16
-0.93
+1.38
0
255
129
64
42
21
9
9.615
+0.16
129
64
32
21
10
4
9.615
+0.16
103
51
25
16
8
9.615
18.939
39.062
56.818
125
+0.16
-1.36
+1.7
-1.36
+8.51
—
64
32
15
10
4
19.230 +0.16
19.230 +0.16
38.461 +0.16
58.823 +2.12
37.878
56.818
113.63
250
-1.36
-1.36
-1.36
0
111.11
250
NA
-3.55
0
3
NA
—
0
625
0
3
625
0
1
—
—
—
625
0
1250 1250.00
0
1
1250
0
0
NA
—
NA
—
—
FOSC = 7.16MHz
FOSC = 5.068 MHz
FOSC = 4 MHz
FOSC = 3.579545 MHz
BAUD
RATE Actual
SPBRG Actual
SPBRG Actual
SPBRG Actual
SPBRG
value
(decimal)
%
Error
%
Error
%
Error
%
Error
(K)
Rate
(K)
value
Rate
(K)
value
Rate
(K)
value
Rate
(K)
(decimal)
(decimal)
(decimal)
9.6
9.520
-0.83
46
22
11
7
9.6
18.645
39.6
52.8
105.6
NA
0
32
16
7
NA
—
—
207
103
25
9.727
18.643
37.286
55.930
111.86
+1.32
-2.90
-2.90
-2.90
-2.90
22
11
5
19.2
38.4
57.6
19.454 +1.32
-2.94
+3.12
-8.33
-8.33
—
1.202
2.403
9.615
+0.17
+0.13
+0.16
37.286
55.930
-2.90
-2.90
5
3
115.2 111.860 -2.90
3
2
19.231 +0.16
12
1
250
625
NA
NA
NA
—
—
—
—
—
—
—
—
—
NA
NA
NA
—
—
—
—
223.72 -10.51
0
NA
—
—
NA
NA
—
—
—
—
1250
NA
—
—
FOSC = 1 MHz
FOSC = 32.768 kHz
BAUD
RATE
(K)
Actual
Rate
(K)
SPBRG Actual
value
SPBRG
value
(decimal)
%
Error
%
Error
Rate
(K)
(decimal)
9.6
19.2
38.4
57.6
115.2
250
8.928
-6.99
6
2
NA
NA
NA
NA
NA
NA
NA
NA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20.833 +8.51
31.25
62.5
NA
-18.61
+8.51
—
1
0
—
—
—
—
NA
—
625
NA
—
1250
NA
—
DS39026D-page 154
1999-2013 Microchip Technology Inc.
PIC18CXX2
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit, TXIE
( PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicated the sta-
tus of the TXREG register, another bit TRMT
(TXSTA<1>) shows the status of the TSR register. Sta-
tus bit TRMT is a read only bit, which is set when the
TSR register is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty.
15.2 USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-
zero (NRZ) format (one START bit, eight or nine data
bits and one STOP bit). The most common data format
is 8-bits. An on-chip dedicated 8-bit baud rate genera-
tor can be used to derive standard baud rate frequen-
cies from the oscillator. The USART transmits and
receives the LSb first. The USART’s transmitter and
receiver are functionally independent, but use the
same data format and baud rate. The baud rate gener-
ator produces a clock, either x16 or x64 of the bit shift
rate, depending on bit BRGH (TXSTA<2>). Parity is not
supported by the hardware, but can be implemented in
software (and stored as the ninth data bit). Asynchro-
nous mode is stopped during SLEEP.
Note 1: The TSR register is not mapped in data
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
The USART Asynchronous module consists of the fol-
lowing important elements:
is set.
To set up an asynchronous transmission:
• Baud Rate Generator
• Sampling Circuit
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 15.1).
• Asynchronous Transmitter
• Asynchronous Receiver
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
15.2.1
USART ASYNCHRONOUS
TRANSMITTER
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
The USART transmitter block diagram is shown in
Figure 15-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts trans-
mission).
FIGURE 15-1:
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXREG Register
TXIF
TXIE
8
MSb
(8)
LSb
Pin Buffer
and Control
0
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
1999-2013 Microchip Technology Inc.
DS39026D-page 155
PIC18CXX2
FIGURE 15-2:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(shift clock)
RC6/TX/CK (pin)
START Bit
Bit 0
Bit 1
Word 1
Bit 7/8
STOP Bit
TXIF bit
(Transmit buffer
reg. empty flag)
Word 1
Transmit Shift Reg
TRMT bit
(Transmit shift
reg. empty flag)
FIGURE 15-3:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG Output
(shift clock)
RC6/TX/CK (pin)
START Bit
START Bit
Word 2
Bit 0
Bit 1
Word 1
Bit 7/8
Bit 0
STOP Bit
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empty flag)
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
TABLE 15-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
POR,
BOR
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF
GIEL
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
RCIE
RCIP
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
PIE1
PSPIE(1) ADIE
PSPIP(1) ADIP
IPR1
RCSTA
TXREG
TXSTA
SPBRG
SPEN
USART Transmit Register
CSRC TX9 TXEN SYNC
Baud Rate Generator Register
RX9
SREN CREN ADDEN FERR
OERR
RX9D 0000 -00x 0000 -00x
0000 0000 0000 0000
—
BRGH TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
Legend: x= unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Transmission.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
DS39026D-page 156
1999-2013 Microchip Technology Inc.
PIC18CXX2
15.2.2
USART ASYNCHRONOUS
RECEIVER
15.2.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The receiver block diagram is shown in Figure 15-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate, or at FOSC. This mode would typi-
cally be used in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is required,
set the BRGH bit.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
To set up an Asynchronous Reception:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 15.1).
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit RCIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
7. The RCIF bit will be set when reception is com-
plete. The interrupt will be acknowledged if the
RCIE and GIE bits are set.
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read RCREG to determine if the device is being
addressed.
10. If any error occurred, clear the CREN bit.
8. Read the 8-bit received data by reading the
RCREG register.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
9. If any error occurred, clear the error by clearing
enable bit CREN.
FIGURE 15-4:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
64
or
16
RSR Register
LSb
MSb
Baud Rate Generator
STOP (8)
7
1
0
START
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
1999-2013 Microchip Technology Inc.
DS39026D-page 157
PIC18CXX2
FIGURE 15-5:
ASYNCHRONOUS RECEPTION
START
bit
START
bit
START
bit7/8 STOP bit
bit
RX (pin)
bit0
bit1
STOP
bit
STOP
bit
bit0
bit7/8
bit7/8
Rcv shift
reg
Rcv buffer reg
Word 2
RCREG
Word 1
RCREG
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing
the OERR (overrun) bit to be set.
TABLE 15-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
INTCON GIE/GIEH PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF
GIEL
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
PSPIE(1) ADIE
PSPIP(1) ADIP
ADIF
RCIF
RCIE
RCIP
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
IPR1
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
RCREG USART Receive Register
TXSTA
CSRC
TX9
TXEN SYNC
—
BRGH TRMT TX9D
SPBRG
Baud Rate Generator Register
Legend: x= unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
DS39026D-page 158
1999-2013 Microchip Technology Inc.
PIC18CXX2
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE, and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit, which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
15.3 USART Synchronous Master
Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner, (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
To set up a Synchronous Master Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 15.1).
15.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
The USART transmitter block diagram is shown in
Figure 15-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREG is empty and inter-
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
TABLE 15-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on
POR,
Value on all
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other
BOR
RESETS
GIE/
GIEH
PEIE/
GIEL
INTCON
TMR0IE INT0IE RBIE TMR0IF INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1) ADIF
PSPIE(1) ADIE
PSPIP(1) ADIP
RCIF
RCIE
RCIP
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
IPR1
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
TXREG USART Transmit Register
TXSTA CSRC TX9 TXEN SYNC
SPBRG Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Master Transmission.
—
BRGH
TRMT
TX9D
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
1999-2013 Microchip Technology Inc.
DS39026D-page 159
PIC18CXX2
FIGURE 15-6:
SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Bit 0
Bit 1
Bit 2
Bit 7
Bit 0
Bit 1
Word 2
Bit 7
RC7/RX/DT
pin
Word 1
RC6/TX/CK pin
Write to
TXREG reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt flag)
TRMT bit
'1'
'1'
TXEN bit
Note:
Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words.
FIGURE 15-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit0
bit2
bit1
bit6
bit7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
DS39026D-page 160
1999-2013 Microchip Technology Inc.
PIC18CXX2
3. Ensure bits CREN and SREN are clear.
15.3.2
USART SYNCHRONOUS MASTER
RECEPTION
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
To set up a Synchronous Master Reception:
9. Read the 8-bit received data by reading the
RCREG register.
1. Initialize the SPBRG register for the appropriate
baud rate (Section 15.1).
10. If any error occurred, clear the error by clearing
bit CREN.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
TABLE 15-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on Value on all
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other
RESETS
GIE/
GIEH
PEIE/
GIEL
INTCON
TMR0IE INT0IE RBIE TMR0IF INT0IF
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1) ADIF
PSPIE(1) ADIE
PSPIP(1) ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
PIE1
IPR1
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D 0000 -00x 0000 -00x
0000 0000 0000 0000
RCREG USART Receive Register
TXSTA CSRC TX9 TXEN SYNC
SPBRG Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Master Reception.
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
0000 0000 0000 0000
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
FIGURE 15-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Write to
bit SREN
SREN bit
CREN bit
'0'
'0'
RCIF bit
(interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = '1' and bit BRGH = '0'.
1999-2013 Microchip Technology Inc.
DS39026D-page 161
PIC18CXX2
To set up a Synchronous Slave Transmission:
15.4 USART Synchronous Slave Mode
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
15.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the SLEEP
mode.
7. Start transmission by loading data to the TXREG
register.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
e) If enable bit TXIE is set, the interrupt will wake the
chip from SLEEP. If the global interrupt is enabled,
the program will branch to the interrupt vector.
TABLE 15-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on
POR,
Value on all
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other
BOR
RESETS
INTCON
GIE/
GIEH
PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF
GIEL
RBIF 0000 000x 0000 000u
PIR1
PSPIF(1) ADIF
PSPIE(1) ADIE
PSPIP(1) ADIP
RCIF
RCIE
RCIP
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
PIE1
IPR1
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D 0000 -00x 0000 -00x
0000 0000 0000 0000
TXREG USART Transmit Register
TXSTA CSRC TX9 TXEN SYNC
SPBRG Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Slave Transmission.
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
0000 0000 0000 0000
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
DS39026D-page 162
1999-2013 Microchip Technology Inc.
PIC18CXX2
To set up a Synchronous Slave Reception:
15.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode and bit SREN, which is a “don't care” in Slave
mode.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
If receive is enabled by setting bit CREN prior to the
SLEEPinstruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register,
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector.
5. Flag bit RCIF will be set when reception is com-
plete. An interrupt will be generated if enable bit
RCIE was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
TABLE 15-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
INTCON
GIE/
GIEH
PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF
GIEL
RBIF 0000 000x 0000 000u
PIR1
PSPIF(1) ADIF
PSPIE(1) ADIE
PSPIP(1) ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
PIE1
IPR1
RCSTA
SPEN
RX9
SREN CREN ADDEN FERR
OERR
RX9D 0000 -00x 0000 -00x
0000 0000 0000 0000
RCREG USART Receive Register
TXSTA CSRC TX9 TXEN
SPBRG Baud Rate Generator Register
Legend: x= unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Slave Reception.
SYNC
—
BRGH TRMT
TX9D 0000 -010 0000 -010
0000 0000 0000 0000
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
1999-2013 Microchip Technology Inc.
DS39026D-page 163
PIC18CXX2
NOTES:
DS39026D-page 164
1999-2013 Microchip Technology Inc.
PIC18CXX2
The A/D module has four registers. These registers
are:
16.0 COMPATIBLE 10-BIT ANALOG-
TO-DIGITAL CONVERTER (A/D)
MODULE
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
The analog-to-digital (A/D) converter module has five
inputs for the PIC18C2x2 devices and eight for the
PIC18C4x2 devices. This module has the ADCON0
and ADCON1 register definitions that are compatible
with the mid-range A/D module.
The ADCON0 register, shown in Register 16-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 16-2, configures the func-
tions of the port pins.
The A/D allows conversion of an analog input signal to
a corresponding 10-bit digital number.
REGISTER 16-1: ADCON0 REGISTER
R/W-0
R/W-0
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
U-0
—
R/W-0
ADON
ADCS1
ADCS0
GO/DONE
bit 7
bit 0
bit 7-6
ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold)
ADCON1
<ADCS2> <ADCS1:ADCS0>
ADCON0
Clock Conversion
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
FOSC/2
FOSC/8
FOSC/32
FRC (clock derived from the internal A/D RC oscillator)
FOSC/4
FOSC/16
FOSC/64
FRC (clock derived from the internal A/D RC oscillator)
bit 5-3
CHS2:CHS0: Analog Channel Select bits
000= channel 0 (AN0)
001= channel 1 (AN1)
010= channel 2 (AN2)
011= channel 3 (AN3)
100= channel 4 (AN4)
101= channel 5 (AN5)
110= channel 6 (AN6)
111= channel 7 (AN7)
Note: The PIC18C2X2 devices do not implement the full 8 A/D channels; the unimplemented selections
are reserved. Do not select any unimplemented channel.
bit 2
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1= A/D conversion in progress (setting this bit starts the A/D conversion which is automatically
cleared by hardware when the A/D conversion is complete)
0= A/D conversion not in progress
bit 1
bit 0
Unimplemented: Read as '0'
ADON: A/D On bit
1= A/D converter module is powered up
0= A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
1999-2013 Microchip Technology Inc.
DS39026D-page 165
PIC18CXX2
REGISTER 16-2: ADCON1 REGISTER
R/W-0
ADFM
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
PCFG0
bit 0
ADCS2
PCFG3
PCFG2
PCFG1
bit 7
bit 7
bit 6
ADFM: A/D Result Format Select bit
1= Right justified. Six (6) Most Significant bits of ADRESH are read as ’0’.
0= Left justified. Six (6) Least Significant bits of ADRESL are read as ’0’.
ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold)
ADCON1
<ADCS2> <ADCS1:ADCS0>
ADCON0
Clock Conversion
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
FOSC/2
FOSC/8
FOSC/32
FRC (clock derived from the internal A/D RC oscillator)
FOSC/4
FOSC/16
FOSC/64
FRC (clock derived from the internal A/D RC oscillator)
bit 5-4
bit 3-0
Unimplemented: Read as '0'
PCFG3:PCFG0: A/D Port Configuration Control bits
PCFG AN7 AN6 AN5 AN4
AN3
AN2 AN1 AN0 VREF+ VREF- C / R
0000
0001
0010
0011
0100
0101
011x
1000
1001
1010
1011
1100
1101
1110
1111
A
A
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
D
D
D
A
A
A
A
A
D
D
D
A
VREF+
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
VDD
AN3
VDD
AN3
VDD
AN3
—
VSS
VSS
VSS
VSS
VSS
VSS
—
8 / 0
7 / 1
5 / 0
4 / 1
3 / 0
2 / 1
0 / 0
6 / 2
6 / 0
5 / 1
4 / 2
3 / 2
2 / 2
1 / 0
1 / 2
VREF+
A
VREF+
D
VREF+ VREF-
AN3
VDD
AN3
AN3
AN3
AN3
VDD
AN3
AN2
VSS
VSS
AN2
AN2
AN2
VSS
AN2
A
A
A
VREF+
VREF+ VREF-
VREF+ VREF-
VREF+ VREF-
D
D
VREF+ VREF-
A = Analog input D = Digital I/O
C/R = # of analog input channels/# of A/D voltage references
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
Note: On any device RESET, the port pins that are multiplexed with analog functions (ANx) are
forced to be an analog input.
DS39026D-page 166
1999-2013 Microchip Technology Inc.
PIC18CXX2
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS) or the voltage level on the RA3/AN3/
VREF+ pin and RA2/AN2/VREF-.
Each port pin associated with the A/D converter can be
configured as an analog input (RA3 can also be a volt-
age reference) or as a digital I/O.
The ADRESH and ADRESL registers contain the result
of the A/D conversion. When the A/D conversion is
complete, the result is loaded into the ADRESH/
ADRESL registers, the GO/DONE bit (ADCON0<2>) is
cleared, and A/D interrupt flag bit ADIF is set. The block
diagram of the A/D module is shown in Figure 16-1.
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To oper-
ate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off and
any conversion is aborted.
FIGURE 16-1:
A/D BLOCK DIAGRAM
CHS2:CHS0
111
AN7
110
AN6
101
AN5
100
AN4
VAIN
011
(Input Voltage)
AN3
010
AN2
10-bit
Converter
A/D
001
AN1
PCFG0
000
AN0
VDD
VREF+
VREF-
Reference
voltage
VSS
1999-2013 Microchip Technology Inc.
DS39026D-page 167
PIC18CXX2
The value that is in the ADRESH/ADRESL registers is
not modified for a Power-on Reset. The ADRESH/
ADRESL registers will contain unknown data after a
Power-on Reset.
16.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 16-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 k. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 16.1.
After this acquisition time has elapsed, the A/D conver-
sion can be started. The following steps should be fol-
lowed for doing an A/D conversion:
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
Note: When the conversion is started, the hold-
ing capacitor is disconnected from the
input pin.
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH/ADRESL);
clear bit ADIF if required.
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
FIGURE 16-2:
ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC 1k
RSS
Rs
CPIN
5 pF
I leakage
± 500 nA
VAIN
CHOLD = 120 pF
VT = 0.6V
VSS
Legend: CPIN
VT
= input capacitance
= threshold voltage
6V
5V
VDD 4V
I LEAKAGE = leakage current at the pin due to
various junctions
3V
2V
RIC
= interconnect resistance
= sampling switch
SS
CHOLD
= sample/hold capacitance (from DAC)
5
6 7 8 9 10 11
Sampling Switch (k)
DS39026D-page 168
1999-2013 Microchip Technology Inc.
PIC18CXX2
To calculate the minimum acquisition time,
Equation 16-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
EQUATION 16-1: ACQUISITION TIME
TACQ
=
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 16-2: A/D MINIMUM CHARGING TIME
VHOLD =
or
(VREF - (VREF/2048)) • (1 - e(-Tc/CHOLD(RIC + RSS + RS))
)
TC
=
-(120 pF)(1 k + RSS + RS) ln(1/2047)
Example 16-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system assump-
tions:
• CHOLD
• Rs
=
=
120 pF
2.5 k
• Conversion Error 1/2 LSb
• VDD
=
=
=
5V Rss = 7 k
50C (system max.)
0V @ time = 0
• Temperature
• VHOLD
EXAMPLE 16-1:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
=
TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25C.
TACQ
TC
=
=
2 s + Tc + [(Temp - 25C)(0.05 s/C)]
-CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 k + 7 k + 2.5 k) ln(0.0004885)
-120 pF (10.5 k) ln(0.0004885)
-1.26 s (-7.6241)
9.61 s
TACQ
=
2 s + 9.61 s + [(50C - 25C)(0.05 s/C)]
11.61 s + 1.25 s
12.86 s
1999-2013 Microchip Technology Inc.
DS39026D-page 169
PIC18CXX2
16.2 Selecting the A/D Conversion
Clock
16.3 Configuring Analog Port Pins
The ADCON1, TRISA and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their corresponding
TRIS bits set (input). If the TRIS bit is cleared (output),
the digital output level (VOH or VOL) will be converted.
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 12 TAD per 10-bit conversion.
The source of the A/D conversion clock is software
selectable. The seven possible options for TAD are:
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
• 2TOSC
• 4TOSC
• 8TOSC
Note 1: When reading the port register, all pins con-
figured as analog input channels will read as
cleared (a low level). Pins configured as dig-
ital inputs will convert an analog input. Ana-
log levels on a digitally configured input will
not affect the conversion accuracy.
• 16TOSC
• 32TOSC
• 64TOSC
• Internal RC oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s.
2: Analog levels on any pin that is defined as
a digital input (including the AN4:AN0
pins) may cause the input buffer to con-
sume current that is out of the devices
specification.
Table 16-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 16-1: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Device Frequency
Operation ADCS2:ADCS0
40 MHz
20 MHz
5 MHz
1.25 MHz
333.33 kHz
2TOSC
4TOSC
8TOSC
16TOSC
32TOSC
64TOSC
RC
000
100
001
101
010
110
011
50 ns
100 ns
200 ns
400 ns
800 ns
1.6 s
100 ns(2)
200 ns(2)
400 ns(2)
800 ns(2)
1.6 s
400 ns(2)
800 ns(2)
1.6 s
1.6 s
3.2 s
6 s
12 s
6.4 s
24 s(3)
48 s(3)
96 s(3)
192 s(3)
2 - 6 s(1)
3.2 s
12.8 s
25.6 s(3)
51.2 s(3)
2 - 6 s(1)
6.4 s
3.2 s
2 - 6 s(1)
12.8 s
2 - 6 s(1)
2 - 6 s(1)
Legend: Shaded cells are outside of recommended range.
Note 1: The RC source has a typical TAD time of 4 s.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
TABLE 16-2: TAD vs. DEVICE OPERATING FREQUENCIES (FOR EXTENDED, LC, DEVICES)
AD Clock Source (TAD)
Operation ADCS2:ADCS0
000
Device Frequency
4 MHz
2 MHz
1.25 MHz
333.33 kHz
2TOSC
500 ns(2)
1.0 s(2)
2.0 s(2)
4.0 s(2)
8.0 s
1.0 s(2)
2.0 s(2)
4.0 s
1.6 s(2)
3.2 s(2)
6.4 s
6 s
12 s
4TOSC
8TOSC
16TOSC
32TOSC
64TOSC
RC
100
001
101
010
110
011
24 s(3)
48 s(3)
96 s(3)
192 s(3)
3 - 9 s(1,4)
8.0 s
12.8 s
16.0 s
32.0 s
3 - 9 s(1,4)
25.6 s(3)
51.2 s(3)
3 - 9 s(1,4)
16.0 s
3 - 9 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The RC source has a typical TAD time of 6 s.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
DS39026D-page 170
1999-2013 Microchip Technology Inc.
PIC18CXX2
16.4 A/D Conversions
16.5 Use of the CCP2 Trigger
Figure 16-3 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conver-
sion. The A/D result register pair will NOT be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the last value written to the ADRESH:ADRESL reg-
isters). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, acquisition on the selected channel is
automatically started.
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as 1011and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D conversion and
the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition done before the “special
event trigger” sets the GO/DONE bit (starts a
conversion).
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D mod-
ule, but will still reset the Timer1 (or Timer3) counter.
FIGURE 16-3:
A/D CONVERSION TAD CYCLES
TCY - TAD
TAD7 TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6
b0
b5
b4
b3
b2
b1
b0
b7
b6
b8
b9
Conversion Starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
1999-2013 Microchip Technology Inc.
DS39026D-page 171
PIC18CXX2
TABLE 16-3: SUMMARY OF A/D REGISTERS
Value on all
other
RESETS
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE/
GIEH
PEIE/
GIEL
INTCON
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PIR1
PSPIF
PSPIE
PSPIP
—
ADIF
ADIE
ADIP
—
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
—
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
(1)
(1)
PIE1
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
IPR1
PIR2
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
TMR3IF CCP2IF ---- 0000 ---- 0000
TMR3IE CCP2IE ---- 0000 ---- 0000
TMR3IP CCP2IP ---- 0000 ---- 0000
xxxx xxxx uuuu uuuu
PIE2
—
—
—
—
IPR2
—
—
—
—
ADRESH
ADRESL
ADCON0
A/D Result Register
A/D Result Register
xxxx xxxx uuuu uuuu
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/
—
ADON
0000 00-0 0000 00-0
DONE
ADCON1
PORTA
TRISA
PORTE
LATE
ADFM
—
ADCS2
RA6
—
—
PCFG3 PCFG2
PCFG1
RA1
PCFG0 ---- -000 ---- -000
RA5
RA4
RA3
RA2
RA0
--0x 0000 --0u 0000
--11 1111 --11 1111
---- -000 ---- -000
---- -xxx ---- -uuu
0000 -111 0000 -111
—
PORTA Data Direction Register
—
—
—
—
—
—
—
—
—
—
RE2
RE1
RE0
—
LATE2
LATE1
LATE0
TRISE
IBF
OBF
IBOV
PSPMODE
PORTE Data Direction bits
Legend: x= unknown, u= unchanged, — = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
DS39026D-page 172
1999-2013 Microchip Technology Inc.
PIC18CXX2
The Low Voltage Detect circuitry is completely under
software control. This allows the circuitry to be “turned
off” by the software, which minimizes the current con-
sumption for the device.
17.0 LOW VOLTAGE DETECT
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application soft-
ware can do “housekeeping tasks” before the device
voltage exits the valid operating range. This can be
done using the Low Voltage Detect module.
Figure 17-1 shows a possible application voltage curve
(typically for batteries). Over time, the device voltage
decreases. When the device voltage equals voltage VA,
the LVD logic generates an interrupt. This occurs at
time TA. The application software then has the time,
until the device voltage is no longer in valid operating
range, to shut-down the system. Voltage point VB is the
minimum valid operating voltage specification. This
occurs at time TB. The difference TB - TA is the total
time for shut-down.
This module is a software programmable circuitry,
where a device voltage trip point can be specified.
When the voltage of the device becomes lower then the
specified point, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the inter-
rupt vector address and the software can then respond
to that interrupt source.
FIGURE 17-1:
TYPICAL LOW VOLTAGE DETECT APPLICATION
VA
VB
Legend:
VA = LVD trip point
VB = Minimum valid device
operating voltage
TB
TA
Time
The block diagram for the LVD module is shown in
Figure 17-2. A comparator uses an internally gener-
ated reference voltage as the set point. When the
selected tap output of the device voltage crosses the
set point (is lower than), the LVDIF bit is set.
supply voltage is equal to the trip point, the voltage
tapped off of the resistor array is equal to the 1.2V
internal reference voltage generated by the voltage
reference module. The comparator then generates an
interrupt signal setting the LVDIF bit. This voltage is
software programmable to any one of 16 values (see
Figure 17-2). The trip point is selected by program-
ming the LVDL3:LVDL0 bits (LVDCON<3:0>).
Each node in the resistor divider represents a “trip
point” voltage. The “trip point” voltage is the minimum
supply voltage level at which the device can operate
before the LVD module asserts an interrupt. When the
1999-2013 Microchip Technology Inc.
DS39026D-page 173
PIC18CXX2
FIGURE 17-2:
LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM
VDD
LVDIN
LVD Control
Register
LVDIF
Internally Generated
LVDEN
Nominal Reference Voltage
1.2V
The LVD module has an additional feature that allows
the user to supply the trip voltage to the module from
an external source. This mode is enabled when bits
LVDL3:LVDL0 are set to 1111. In this state, the com-
parator input is multiplexed from the external input pin
LVDIN (Figure 17-3).
This gives flexibility, because it allows a user to config-
ure the Low Voltage Detect interrupt to occur at any
voltage in the valid operating range.
FIGURE 17-3:
LOW VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
VDD
VDD
LVD Control
Register
LVDIN
LVDEN
Externally Generated
Trip Point
LVD
VxEN
BODEN
EN
BGAP
DS39026D-page 174
1999-2013 Microchip Technology Inc.
PIC18CXX2
17.1 Control Register
The Low Voltage Detect Control register controls the
operation of the Low Voltage Detect circuitry.
REGISTER 17-1: LVDCON REGISTER
U-0
—
U-0
—
R-0
R/W-0
R/W-0
LVDL3
R/W-1
LVDL2
R/W-0
LVDL1
R/W-1
LVDL0
IRVST
LVDEN
bit 7
bit 0
bit 7-6
bit 5
Unimplemented: Read as '0'
IRVST: Internal Reference Voltage Stable Flag bit
1= Indicates that the Low Voltage Detect logic will generate the interrupt flag at the
specified voltage range
0= Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the
specified voltage range and the LVD interrupt should not be enabled
bit 4
LVDEN: Low Voltage Detect Power Enable bit
1= Enables LVD, powers up LVD circuit
0= Disables LVD, powers down LVD circuit
bit 3-0
LVDL3:LVDL0: Low Voltage Detection Limit bits
1111= External analog input is used (input comes from the LVDIN pin)
1110= 4.5V min. - 4.77V max.
1101= 4.2V min. - 4.45V max.
1100= 4.0V min. - 4.24V max.
1011= 3.8V min. - 4.03V max.
1010= 3.6V min. - 3.82V max.
1001= 3.5V min. - 3.71V max.
1000= 3.3V min. - 3.50V max.
0111= 3.0V min. - 3.18V max.
0110= 2.8V min. - 2.97V max.
0101= 2.7V min. - 2.86V max.
0100= 2.5V min. - 2.65V max.
0011= 2.4V min. - 2.54V max.
0010= 2.2V min. - 2.33V max.
0001= 2.0V min. - 2.12V max.
0000= 1.8V min. - 1.91V max.
Note:
LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage
of the device are not tested.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
1999-2013 Microchip Technology Inc.
DS39026D-page 175
PIC18CXX2
The following steps are needed to set up the LVD module:
17.2 Operation
1. Write the value to the LVDL3:LVDL0 bits (LVD-
CON register), which selects the desired LVD
Trip Point.
Depending on the power source for the device voltage,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be con-
stantly operating. To decrease the current require-
ments, the LVD circuitry only needs to be enabled for
short periods, where the voltage is checked. After
doing the check, the LVD module may be disabled.
2. Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared, or the GIE bit is cleared).
3. Enable the LVD module (set the LVDEN bit in
the LVDCON register).
4. Wait for the LVD module to stabilize (the IRVST
bit to become set).
Each time that the LVD module is enabled, the circuitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
5. Clear the LVD interrupt flag, which may have
falsely become set until the LVD module has
stabilized (clear the LVDIF bit).
6. Enable the LVD interrupt (set the LVDIE and the
GIE bits).
Figure 17-4 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 17-4:
LOW VOLTAGE DETECT WAVEFORMS
CASE 1:
LVDIF may not be set
VDD
VLVD
LVDIF
Enable LVD
50 ms
Internally Generated
Reference stable
LVDIF cleared in software
CASE 2:
VDD
VLVD
LVDIF
Enable LVD
50 ms
Internally Generated
Reference stable
LVDIF cleared in software
LVDIF cleared in software,
LVDIF remains set since LVD condition still exists
DS39026D-page 176
1999-2013 Microchip Technology Inc.
PIC18CXX2
17.2.1
REFERENCE VOLTAGE SET POINT
17.3 Operation During SLEEP
The Internal Reference Voltage of the LVD module may
be used by other internal circuitry (the Programmable
Brown-out Reset). If these circuits are disabled (lower
current consumption), the reference voltage circuit
requires a time to become stable before a low voltage
condition can be reliably detected. This time is invariant
of system clock speed. This start-up time is specified in
electrical specification parameter #36. The low voltage
interrupt flag will not be enabled until a stable reference
voltage is reached. Refer to the waveform in Figure 17-4.
When enabled, the LVD circuitry continues to operate
during SLEEP. If the device voltage crosses the trip
point, the LVDIF bit will be set and the device will wake-
up from SLEEP. Device execution will continue from
the interrupt vector address, if interrupts have been glo-
bally enabled.
17.4 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the LVD module to be turned off.
17.2.2
CURRENT CONSUMPTION
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume static cur-
rent. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter #D022B.
1999-2013 Microchip Technology Inc.
DS39026D-page 177
PIC18CXX2
NOTES:
DS39026D-page 178
1999-2013 Microchip Technology Inc.
PIC18CXX2
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost, while the LP crystal option saves power. A set of
configuration bits are used to select various options.
18.0 SPECIAL FEATURES OF THE
CPU
There are several features intended to maximize sys-
tem reliability, minimize cost through elimination of
external components, provide power saving operating
modes and offer code protection. These are:
• OSC Selection
• RESET
18.1 Configuration Bits
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h - 3FFFFFh),
which can only be accessed using table reads and
table writes.
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-circuit Serial Programming
All PIC18CXX2 devices have a Watchdog Timer, which
is permanently enabled via the configuration bits or
software-controlled. It runs off its own RC oscillator for
added reliability. There are two timers that offer neces-
sary delays on power-up. One is the Oscillator Start-up
Timer (OST), intended to keep the chip in RESET until
the crystal oscillator is stable. The other is the Power-
up Timer (PWRT), which provides a fixed delay on
power-up only, designed to keep the part in RESET
while the power supply stabilizes. With these two tim-
ers on-chip, most applications need no external
RESET circuitry.
TABLE 18-1: CONFIGURATION BITS AND DEVICE IDS
Default/
Unprogrammed
Value
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300000h CONFIG1L
300001h CONFIG1H
300002h CONFIG2L
300003h CONFIG2H
300005h CONFIG3H
300006h CONFIG4L
3FFFFEh DEVID1
CP
—
CP
—
CP
OSCSEN
—
CP
—
CP
—
CP
CP
CP
1111 1111
111- -111
---- 1111
---- 1111
---- ---1
---- --11
0000 0000
0000 0010
FOSC2
BORV0
FOSC1
BODEN
FOSC0
PWRTEN
WDTEN
CCP2MX
STVREN
REV0
—
—
—
BORV1
—
—
—
—
WDTPS2 WDTPS1 WDTPS0
—
—
—
—
—
—
—
—
—
—
—
—
—
LVEN
REV1
DEV4
DEV2
DEV10
DEV1
DEV9
DEV0
DEV8
REV4
DEV7
REV3
DEV6
REV2
DEV5
3FFFFFh DEVID2
DEV3
Legend: x= unknown, u= unchanged, - = unimplemented, q= value depends on condition.
Shaded cells are unimplemented, read as ‘0’
1999-2013 Microchip Technology Inc.
DS39026D-page 179
PIC18CXX2
REGISTER 18-1: CONFIGURATION REGISTER 1 HIGH (CONFIG1H:BYTE ADDRESS 300001h)
R/P-1
R/P-1
R/P-1
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
Reserved Reserved OSCSEN
bit 7
FOSC2 FOSC1 FOSC0
bit 0
bit 7-6
bit 5
Reserved: Read as ’1’
OSCSEN: Oscillator System Clock Switch Enable bit
1= Oscillator system clock switch option is disabled (main oscillator is source)
0= Oscillator system clock switch option is enabled (oscillator switching is enabled)
bit 4-3
bit 2-0
Unimplemented: Read as ’0’
FOSC2:FOSC0: Oscillator Selection bits
111= RC oscillator w/OSC2 configured as RA6
110= HS oscillator with PLL enabled/Clock frequency = (4 x FOSC)
101= EC oscillator w/OSC2 configured as RA6
100= EC oscillator w/OSC2 configured as divide-by-4 clock output
011= RC oscillator
010= HS oscillator
001= XT oscillator
000= LP oscillator
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
REGISTER 18-2: CONFIGURATION REGISTER 1 LOW (CONFIG1L: BYTE ADDRESS 300000h)
R/P-1
CP
R/P-1
CP
R/P-1
CP
R/P-1
CP
R/P-1
CP
R/P-1
CP
R/P-1
CP
R/P-1
CP
bit 7
bit 0
bit 7-0
CP: Code Protection bits (apply when in Code Protected Microcontroller mode)
1= Program memory code protection off
0= All of program memory code protected
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
DS39026D-page 180
1999-2013 Microchip Technology Inc.
PIC18CXX2
REGISTER 18-3: CONFIGURATIONREGISTER2HIGH(CONFIG2H:BYTEADDRESS300003h)
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 0
bit 7
bit 7-4
bit 3-1
Unimplemented: Read as ’0’
WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits
111= 1:1
110= 1:2
101= 1:4
100= 1:8
011= 1:16
010= 1:32
001= 1:64
000= 1:128
bit 0
WDTEN: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
REGISTER 18-4: CONFIGURATION REGISTER 2 LOW (CONFIG2L:BYTE ADDRESS300002h)
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
R/P-1
R/P-1
BORV1
BORV0 BOREN PWRTEN
bit 0
bit 7
bit 7-4
bit 3-2
Unimplemented: Read as ’0’
BORV1:BORV0: Brown-out Reset Voltage bits
11= VBOR set to 2.5V
10= VBOR set to 2.7V
01= VBOR set to 4.2V
00= VBOR set to 4.5V
bit 1
bit 0
BOREN: Brown-out Reset Enable bit(1)
1= Brown-out Reset enabled
0= Brown-out Reset disabled
Note:
Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT),
regardless of the value of bit PWRTEN. Ensure the Power-up Timer is enabled any
time Brown-out Reset is enabled.
PWRTEN: Power-up Timer Enable bit(1)
1= PWRT disabled
0= PWRT enabled
Note:
Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT),
regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled any
time Brown-out Reset is enabled.
Legend:
R = Readable bit
P = Programmable bit
U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
1999-2013 Microchip Technology Inc.
DS39026D-page 181
PIC18CXX2
REGISTER 18-5: CONFIGURATION REGISTER 3HIGH (CONFIG3H:BYTE ADDRESS300005h)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
CCP2MX
bit 0
bit 7
bit 7-1
bit 0
Unimplemented: Read as ’0’
CCP2MX: CCP2 Mux bit
1= CCP2 input/output is multiplexed with RC1
0= CCP2 input/output is multiplexed with RB3
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
- n = Value when device is unprogrammed
REGISTER 18-6: CONFIGURATION REGISTER 4 LOW (CONFIG4L:BYTE ADDRESS300006h)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/P-1
R/P-1
Reserved STVREN
bit 0
bit 7
bit 7-2
bit 1
Unimplemented: Read as ’0’
Reserved: Maintain this bit set
bit 0
STVREN: Stack Full/Underflow Reset Enable bit
1= Stack Full/Underflow will cause RESET
0= Stack Full/Underflow will not cause RESET
Legend:
R = Readable bit
P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed
u = Unchanged from programmed state
DS39026D-page 182
1999-2013 Microchip Technology Inc.
PIC18CXX2
The WDT time-out period values may be found in the
Electrical Specifications section under parameter #31.
Values for the WDT postscaler may be assigned using
the configuration bits.
18.2 Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator, which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKI pin. That means that the WDT
will run, even if the clock on the OSC1/CLKI and OSC2/
CLKO/RA6 pins of the device has been stopped, for
example, by execution of a SLEEPinstruction.
Note: The CLRWDTand SLEEPinstructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out
and generating a device RESET condition.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the RCON register
will be cleared upon a WDT time-out.
Note: When a CLRWDT instruction is executed
and the postscaler is assigned to the WDT,
the postscaler count will be cleared, but the
postscaler assignment is not changed.
The Watchdog Timer is enabled/disabled by a device
configuration bit. If the WDT is enabled, software exe-
cution may not disable this function. When the WDTEN
configuration bit is cleared, the SWDTEN bit enables/
disables the operation of the WDT.
18.2.1
CONTROL REGISTER
Register 18-7 shows the WDTCON register. This is a
readable and writable register, which contains a control
bit that allows software to override the WDT enable
configuration bit, only when the configuration bit has
disabled the WDT.
REGISTER 18-7: WDTCON REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SWDTEN
bit 0
bit 7
bit 7-1
bit 0
Unimplemented: Read as ’0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1= Watchdog Timer is on
0= Watchdog Timer is turned off if the WDTEN configuration bit in the configuration
register = ’0’
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset
1999-2013 Microchip Technology Inc.
DS39026D-page 183
PIC18CXX2
18.2.2
WDT POSTSCALER
The WDT has a postscaler that can extend the WDT
Reset period. The postscaler is selected at the time of
device programming, by the value written to the
CONFIG2H configuration register.
FIGURE 18-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDT Timer
Postscaler
8
8 - to - 1 MUX
WDTPS2:WDTPS0
WDTEN
Configuration bit
SWDTEN bit
WDT
Time-out
Note: WDPS2:WDPS0 are bits in register CONFIG2H.
TABLE 18-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONFIG2H
RCON
—
IPEN
—
—
LWRT
—
—
—
—
—
RI
—
WDTPS2 WDTPS2 WDTPS0
WDTEN
BOR
TO
—
PD
—
POR
—
WDTCON
SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
DS39026D-page 184
1999-2013 Microchip Technology Inc.
PIC18CXX2
When the SLEEPinstruction is being executed, the next
instruction (PC + 2) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOPafter the SLEEPinstruction.
18.3 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared, but
keeps running, the PD bit (RCON<3>) is cleared, the
TO (RCON<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
18.3.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If an interrupt condition (interrupt flag bit and inter-
rupt enable bits are set) occurs before the execu-
tion of a SLEEPinstruction, the SLEEPinstruction
will complete as a NOP. Therefore, the WDT and
WDT postscaler will not be cleared, the TO bit will
not be set and PD bits will not be cleared.
The MCLR pin must be at a logic high level (VIHMC).
18.3.1
WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
• If the interrupt condition occurs during or after
the execution of a SLEEPinstruction, the device
will immediately wake up from SLEEP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
1. External RESET input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change, or a
Peripheral Interrupt.
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
The following peripheral interrupts can wake the device
from SLEEP:
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
1. PSP read or write.
2. TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
3. TMR3 interrupt. Timer3 must be operating as an
asynchronous counter.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
4. CCP capture mode interrupt.
5. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
6. MSSP (START/STOP) bit detect interrupt.
7. MSSP transmit or receive in Slave mode
(SPI/I2C).
8. USART RX or TX (Synchronous Slave mode).
9. A/D conversion (when A/D clock source is RC).
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and will cause a “wake-up”. The TO and PD
bits in the RCON register can be used to determine the
cause of the device RESET. The PD bit, which is set on
power-up, is cleared when SLEEPis invoked. The TO
bit is cleared, if a WDT time-out occurred (and caused
wake-up).
1999-2013 Microchip Technology Inc.
DS39026D-page 185
PIC18CXX2
FIGURE 18-2:
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
(2)
TOST
INTF Flag
Interrupt Latency(3)
(INTCON<1>)
GIEH bit
Processor in
SLEEP
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC+2
PC+4
PC+4
PC + 4
0008h
000Ah
Instruction
Inst(0008h)
Inst(PC + 2)
Inst(PC + 4)
Inst(000Ah)
Inst(PC) = SLEEP
Fetched
Instruction
Executed
Inst(PC + 2)
Dummy cycle
Dummy cycle
Inst(0008h)
SLEEP
Inst(PC - 1)
Note 1: XT, HS or LP oscillator mode assumed.
2: GIE = '1' assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
3: TOST = 1024TOSC (drawing not to scale) This delay will not occur for RC and EC osc modes.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
18.4 Program Verification/Code
Protection
18.6
In-Circuit Serial Programming
PIC18CXXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
Note: Microchip Technology does not recom-
mend code protecting windowed devices.
18.5 ID Locations
Five memory locations (200000h - 200004h) are desig-
nated as ID locations, where the user can store check-
sum or other code identification numbers. These
locations are accessible during normal execution
through the TBLRDinstruction or during program/verify.
The ID locations can be read when the device is code
protected.
DS39026D-page 186
1999-2013 Microchip Technology Inc.
PIC18CXX2
The control instructions may use some of the following
operands:
19.0 INSTRUCTION SET SUMMARY
The PIC18CXXX instruction set adds many enhance-
ments to the previous PIC instruction sets, while main-
taining an easy migration from these PIC MCU
instruction sets.
• A program memory address (specified by ‘n’)
• The mode of the Call or Return instructions
(specified by ‘s’)
• The mode of the Table Read and Table Write
instructions (specified by ‘m’)
Most instructions are a single program memory word
(16-bits), but there are three instructions that require
two program memory locations.
• No operand required (specified by ‘—’)
All instructions are a single word, except for three dou-
ble word instructions. These three instructions were
made double word instructions so that all the required
information is available in these 32-bits. In the second
word, the 4 MSb’s are 1’s. If this second word is exe-
cuted as an instruction (by itself), it will execute as a
NOP.
Each single word instruction is a 16-bit word divided
into an OPCODE, which specifies the instruction type
and one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
All single word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.
• Control operations
The PIC18CXXX instruction set summary in Table 19-2
lists byte-oriented, bit-oriented, literal and control
operations. Table 19-1 shows the opcode field descrip-
tions.
The double word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
Two word branch instructions (if true) would take 3 s.
Most byte-oriented instructions have three operands:
1. The file register (specified by ‘f’)
2. The destination of the result (specified by ‘d’)
3. The accessed memory (specified by ‘a’)
The file register designator 'f' specifies which file regis-
ter is to be used by the instruction.
Figure 19-1 shows the general formats that the instruc-
tions can have.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If 'd' is zero, the
result is placed in the WREG register. If 'd' is one, the
result is placed in the file register specified in the
instruction.
All examples use the format ‘nnh’ to represent a
hexadecimal number, where ‘h’signifies a hexadeci-
mal digit.
The Instruction Set Summary, shown in Table 19-2,
lists the instructions recognized by the Microchip
assembler (MPASMTM).
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
Section 19.1 provides a description of each instruction.
2. The bit in the file register (specified by ‘b’)
3. The accessed memory (specified by ‘a’)
The bit field designator 'b' selects the number of the bit
affected by the operation, while the file register desig-
nator 'f' represents the number of the file in which the
bit is located.
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FSR register to load the literal value
into (specified by ‘f’)
• No operand required (specified by ‘—’)
1999-2013 Microchip Technology Inc.
DS39026D-page 187
PIC18CXX2
TABLE 19-1: OPCODE FIELD DESCRIPTIONS
Field
Description
a
RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb
BSR
d
Bit address within an 8-bit file register (0 to 7)
Bank Select Register. Used to select the current RAM bank.
Destination select bit;
d = 0: store result in WREG,
d = 1: store result in file register f.
dest
f
Destination either the WREG register or the specified register file location
8-bit Register file address (0x00 to 0xFF)
fs
12-bit Register file address (0x000 to 0xFFF). This is the source address.
12-bit Register file address (0x000 to 0xFFF). This is the destination address.
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)
Label name
fd
k
label
mm
The mode of the TBLPTR register for the Table Read and Table Write instructions
Only used with Table Read and Table Write instructions:
*
No Change to register (such as TBLPTR with Table reads and writes)
Post-Increment register (such as TBLPTR with Table reads and writes)
Post-Decrement register (such as TBLPTR with Table reads and writes)
Pre-Increment register (such as TBLPTR with Table reads and writes)
*+
*-
+*
n
The relative address (2’s complement number) for relative branch instructions, or the direct address for
Call/Branch and Return instructions
PRODH
PRODL
s
Product of Multiply high byte
Product of Multiply low byte
Fast Call/Return mode select bit.
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
u
Unused or Unchanged
WREG
x
Working register (accumulator)
Don't care (0 or 1)
The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all
Microchip software tools.
TBLPTR
21-bit Table Pointer (points to a Program Memory location)
8-bit Table Latch
TABLAT
TOS
Top-of-Stack
PC
Program Counter
PCL
Program Counter Low Byte
Program Counter High Byte
Program Counter High Byte Latch
Program Counter Upper Byte Latch
Global Interrupt Enable bit
Watchdog Timer
PCH
PCLATH
PCLATU
GIE
WDT
TO
Time-out bit
PD
Power-down bit
C, DC, Z, OV, N
ALU status bits Carry, Digit Carry, Zero, Overflow, Negative
Optional
[
]
)
(
Contents
< >
Assigned to
Register bit field
In the set of
italics
User defined term (font is courier)
DS39026D-page 188
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 19-1:
GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
Example Instruction
15
10
OPCODE
9
8
7
0
ADDWF MYREG, W, B
d
a
f (FILE #)
d = 0 for result destination to be WREG register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Byte to Byte move operations (2-word)
15
12 11
0
0
OPCODE
f (Source FILE #)
MOVFF MYREG1, MYREG2
15
12 11
1111
f (Destination FILE #)
f = 12-bit file register address
Bit-oriented file register operations
15 12 11 9 8
OPCODE b (BIT #)
7
0
BSF MYREG, bit, B
a
f (FILE #)
b = 3-bit position of bit in file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
Literal operations
15
8
7
0
MOVLW 0x7F
OPCODE
k (literal)
k = 8-bit immediate value
Control operations
CALL, GOTO and Branch operations
15
8 7
0
GOTO Label
OPCODE
12 11
n<7:0> (literal)
15
0
1111
n<19:8> (literal)
n = 20-bit immediate value
15
15
8
7
0
CALL MYFUNC
OPCODE
12 11
n<7:0> (literal)
S
0
n<19:8> (literal)
S = Fast bit
11 10
15
0
0
BRA MYFUNC
BC MYFUNC
OPCODE
n<10:0> (literal)
15
OPCODE
8 7
n<7:0> (literal)
1999-2013 Microchip Technology Inc.
DS39026D-page 189
PIC18CXX2
TABLE 19-2: PIC18CXXX INSTRUCTION SET
16-bit Instruction Word
MSb LSb
Mnemonic,
Description
Operands
Status
Affected
Cycles
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
f, d, a Add WREG and f
1
1
1
1
1
0010 01da ffff ffff C, DC, Z, OV, N 1, 2
0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ADDWFC f, d, a Add WREG and Carry bit to f
ANDWF
CLRF
f, d, a AND WREG with f
f, a Clear f
f, d, a Complement f
0001 01da ffff ffff Z, N
0110 101a ffff ffff Z
0001 11da ffff ffff Z, N
1,2
2
1, 2
4
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
f, a
f, a
f, a
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
1 (2 or 3) 0110 001a ffff ffff None
1 (2 or 3) 0110 010a ffff ffff None
1 (2 or 3) 0110 000a ffff ffff None
4
1, 2
f, d, a Decrement f
1
0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ
DCFSNZ
INCF
f, d, a Decrement f, Skip if 0
f, d, a Decrement f, Skip if Not 0
f, d, a Increment f
1 (2 or 3) 0010 11da ffff ffff None
1 (2 or 3) 0100 11da ffff ffff None
1, 2, 3, 4
1, 2
1
0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ
INFSNZ
IORWF
MOVF
f, d, a Increment f, Skip if 0
f, d, a Increment f, Skip if Not 0
f, d, a Inclusive OR WREG with f
f, d, a Move f
fs, fd Move fs (source) to 1st word
fd (destination)2nd word
1 (2 or 3) 0011 11da ffff ffff None
1 (2 or 3) 0100 10da ffff ffff None
4
1, 2
1, 2
1
1
1
2
0001 00da ffff ffff Z, N
0101 00da ffff ffff Z, N
1100 ffff ffff ffff None
1111 ffff ffff ffff
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
f, a
f, a
f, a
Move WREG to f
Multiply WREG with f
Negate f
1
1
1
1
1
1
1
1
1
0110 111a ffff ffff None
0000 001a ffff ffff None
0110 110a ffff ffff C, DC, Z, OV, N 1, 2
0011 01da ffff ffff C, Z, N
0100 01da ffff ffff Z, N
0011 00da ffff ffff C, Z, N
0100 00da ffff ffff Z, N
0110 100a ffff ffff None
f, d, a Rotate Left f through Carry
f, d, a Rotate Left f (No Carry)
f, d, a Rotate Right f through Carry
f, d, a Rotate Right f (No Carry)
1, 2
RRNCF
SETF
f, a
Set f
SUBFWB f, d, a Subtract f from WREG with
borrow
0101 01da ffff ffff C, DC, Z, OV, N 1, 2
SUBWF
f, d, a Subtract WREG from f
1
1
0101 11da ffff ffff C, DC, Z, OV, N
0101 10da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with
borrow
SWAPF
TSTFSZ
XORWF
f, d, a Swap nibbles in f
f, a Test f, skip if 0
f, d, a Exclusive OR WREG with f
1
0011 10da ffff ffff None
4
1, 2
1 (2 or 3) 0110 011a ffff ffff None
1
0001 10da ffff ffff Z, N
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a Bit Clear f
f, b, a Bit Set f
f, b, a Bit Test f, Skip if Clear
f, b, a Bit Test f, Skip if Set
f, d, a Bit Toggle f
1
1
1001 bbba ffff ffff None
1000 bbba ffff ffff None
1, 2
1, 2
3, 4
3, 4
1, 2
1 (2 or 3) 1011 bbba ffff ffff None
1 (2 or 3) 1010 bbba ffff ffff None
1
0111 bbba ffff ffff None
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is
driven low by an external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP,
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39026D-page 190
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 19-2: PIC18CXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
16-bit Instruction Word
MSb LSb
Status
Affected
Description
Cycles
Notes
Operands
CONTROL OPERATIONS
BC
BN
n
n
n
n
n
n
n
n
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine1st word
2nd word
1 (2)
1110 0010 nnnn nnnn None
1110 0110 nnnn nnnn None
1110 0011 nnnn nnnn None
1110 0111 nnnn nnnn None
1110 0101 nnnn nnnn None
1110 0001 nnnn nnnn None
1110 0100 nnnn nnnn None
1101 0nnn nnnn nnnn None
1110 0000 nnnn nnnn None
1110 110s kkkk kkkk None
1111 kkkk kkkk kkkk
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
1 (2)
1 (2)
2
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
n
n, s
CALL
CLRWDT
DAW
GOTO
—
—
n
Clear Watchdog Timer
Decimal Adjust WREG
Go to address1st word
2nd word
1
1
2
0000 0000 0000 0100 TO, PD
0000 0000 0000 0111 C
1110 1111 kkkk kkkk None
1111 kkkk kkkk kkkk
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
—
—
—
—
n
No Operation
1
1
1
1
2
1
2
0000 0000 0000 0000 None
1111 xxxx xxxx xxxx None
0000 0000 0000 0110 None
0000 0000 0000 0101 None
1101 1nnn nnnn nnnn None
0000 0000 1111 1111 All
0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
No Operation (Note 4)
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device RESET
Return from interrupt enable
s
RETLW
RETURN
SLEEP
k
s
—
Return with literal in WREG
Return from Subroutine
Go into standby mode
2
2
1
0000 1100 kkkk kkkk None
0000 0000 0001 001s None
0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is
driven low by an external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP,
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
1999-2013 Microchip Technology Inc.
DS39026D-page 191
PIC18CXX2
TABLE 19-2: PIC18CXXX INSTRUCTION SET (CONTINUED)
16-bit Instruction Word
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
k
k
k
f, k
Add literal and WREG
1
1
1
2
0000 1111 kkkk
0000 1011 kkkk
0000 1001 kkkk
1110 1110 00ff
1111 0000 kkkk
0000 0001 0000
0000 1110 kkkk
0000 1101 kkkk
0000 1100 kkkk
0000 1000 kkkk
0000 1010 kkkk
kkkk C, DC, Z, OV, N
kkkk Z, N
kkkk Z, N
kkkk None
kkkk
kkkk None
kkkk None
kkkk None
kkkk None
kkkk C, DC, Z, OV, N
kkkk Z, N
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word
to FSRx 1st word
Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
k
k
k
1
1
1
2
1
Exclusive OR literal with WREG 1
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD*
Table Read
2
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
1000 None
1001 None
1010 None
1011 None
1100 None
1101 None
1110 None
1111 None
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment
2 (5)
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is
driven low by an external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP,
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39026D-page 192
1999-2013 Microchip Technology Inc.
PIC18CXX2
19.1 Instruction Set
ADDLW
ADD literal to WREG
ADDWF
ADD WREG to f
Syntax:
[ label ] ADDLW
0 k 255
k
Syntax:
[ label ] ADDWF
f [,d [,a] f [,d [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 f 255
d [0,1]
a [0,1]
(WREG) + k WREG
N,OV, C, DC, Z
Operation:
(WREG) + (f) dest
0000
1111
kkkk
kkkk
Status Affected:
Encoding:
N,OV, C, DC, Z
Description:
The contents of WREG are added
to the 8-bit literal 'k' and the result is
placed in WREG.
0010
01da
ffff
ffff
Description:
Add WREG to register 'f'. If 'd' is 0,
the result is stored in WREG. If 'd'
is 1, the result is stored back in reg-
ister 'f' (default). If ‘a’ is 0, the
Access Bank will be selected. If ‘a’
is 1, the BSR is used.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write to
WREG
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
ADDLW
0x15
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register 'f'
Process
Data
Write to
destination
WREG = 0x10
After Instruction
WREG = 0x25
ADDWF
REG, 0, 0
Example:
Before Instruction
WREG
REG
=
=
0x17
0xC2
After Instruction
WREG
REG
=
=
0xD9
0xC2
1999-2013 Microchip Technology Inc.
DS39026D-page 193
PIC18CXX2
ADDWFC
ADD WREG and Carry bit to f
ANDLW
AND literal with WREG
Syntax:
[ label ] ADDWFC
f [,d [,a]
Syntax:
[ label ] ANDLW
0 k 255
k
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
Operation:
Status Affected:
Encoding:
(WREG) .AND. k WREG
N,Z
Operation:
(WREG) + (f) + (C) dest
0000
1011
kkkk
kkkk
Status Affected:
Encoding:
N,OV, C, DC, Z
Description:
The contents of WREG are ANDed
with the 8-bit literal 'k'. The result is
placed in WREG.
0010
00da
ffff
ffff
Description:
Add WREG, the Carry Flag and data
memory location 'f'. If 'd' is 0, the
result is placed in WREG. If 'd' is 1,
the result is placed in data memory
location 'f'. If ‘a’ is 0, the Access
Bank will be selected. If ‘a’ is 1, the
BSR will not be overridden.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
'k'
Process
Data
Write to
WREG
Words:
Cycles:
1
1
ANDLW
0x5F
Example:
Q Cycle Activity:
Q1
Before Instruction
Q2
Q3
Q4
WREG
=
0xA3
0x03
Decode
Read
register 'f'
Process
Data
Write to
destination
After Instruction
WREG
=
ADDWFC
REG, 0, 1
Example:
Before Instruction
Carry bit=
1
REG
=
0x02
WREG
=
0x4D
After Instruction
Carry bit=
0
REG
=
0x02
WREG
=
0x50
DS39026D-page 194
1999-2013 Microchip Technology Inc.
PIC18CXX2
ANDWF
AND WREG with f
BC
Branch if Carry
[ label ] BC
Syntax:
[ label ] ANDWF
f [,d [,a]
Syntax:
n
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
Operation:
-128 n 127
if carry bit is ’1’
(PC) + 2 + 2n PC
Operation:
(WREG) .AND. (f) dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N,Z
1110
0010
nnnn
nnnn
0001
01da
ffff
ffff
Description:
If the Carry bit is ’1’, then the pro-
gram will branch.
Description:
The contents of WREG are AND’ed
with register 'f'. If 'd' is 0, the result
is stored in WREG. If 'd' is 1, the
result is stored back in register 'f'
(default). If ‘a’ is 0, the Access
Bank will be selected. If ‘a’ is 1, the
BSR will not be overridden
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
(default).
Words:
Cycles:
1
Words:
Cycles:
1
1
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
Decode
Read literal
'n'
Process
Data
Write to PC
No
No
No
No
operation
operation
operation
operation
ANDWF
REG, 0, 0
Example:
If No Jump:
Q1
Before Instruction
Q2
Q3
Q4
WREG
REG
=
=
0x17
0xC2
Decode
Read literal
'n'
Process
Data
No
operation
After Instruction
WREG
REG
=
=
0x02
0xC2
HERE
BC
5
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Carry
PC
If Carry
PC
=
=
=
1;
address (HERE+12)
0;
address (HERE+2)
1999-2013 Microchip Technology Inc.
DS39026D-page 195
PIC18CXX2
BCF
Bit Clear f
BN
Branch if Negative
[ label ] BN
Syntax:
[ label ] BCF f,b[,a]
Syntax:
n
Operands:
0 f 255
0 b 7
a [0,1]
Operands:
Operation:
-128 n 127
if negative bit is ’1’
(PC) + 2 + 2n PC
Operation:
0 f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0110
nnnn
nnnn
1001
bbba
ffff
ffff
Description:
If the Negative bit is ’1’, then the
program will branch.
Description:
Bit 'b' in register 'f' is cleared. If ‘a’
is 0, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
Q1
Q2
Q3
Q4
register 'f'
Decode
Read literal
'n'
Process
Data
Write to PC
BCF
FLAG_REG, 7, 0
Example:
No
operation
No
operation
No
operation
No
operation
Before Instruction
FLAG_REG = 0xC7
If No Jump:
Q1
After Instruction
Q2
Q3
Q4
FLAG_REG = 0x47
Decode
Read literal
'n'
Process
Data
No
operation
HERE
BN Jump
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Negative=
PC
If Negative
PC
1;
=
address (Jump)
0;
address (HERE+2)
=
DS39026D-page 196
1999-2013 Microchip Technology Inc.
PIC18CXX2
BNC
Branch if Not Carry
BNN
Branch if Not Negative
Syntax:
[ label ] BNC
-128 n 127
if carry bit is ’0’
n
Syntax:
[ label ] BNN
-128 n 127
n
Operands:
Operation:
Operands:
Operation:
if negative bit is ’0’
(PC) + 2 + 2n PC
(PC) + 2 + 2n PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0011
nnnn
nnnn
1110
0111
nnnn
nnnn
Description:
If the Carry bit is ’0’, then the pro-
gram will branch.
Description:
If the Negative bit is ’0’, then the
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
Write to PC
Decode
Read literal
'n'
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
No
operation
Decode
Read literal
'n'
Process
Data
No
operation
HERE
BNC Jump
HERE
BNN Jump
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Carry
PC
If Carry
PC
=
=
=
0;
If Negative
PC
If Negative=
PC
0;
address (Jump)
1;
address (HERE+2)
=
address (Jump)
1;
address (HERE+2)
=
1999-2013 Microchip Technology Inc.
DS39026D-page 197
PIC18CXX2
BNOV
Branch if Not Overflow
BNZ
Branch if Not Zero
Syntax:
[ label ] BNOV
-128 n 127
n
Syntax:
[ label ] BNZ
-128 n 127
if zero bit is ’0’
n
Operands:
Operation:
Operands:
Operation:
if overflow bit is ’0’
(PC) + 2 + 2n PC
(PC) + 2 + 2n PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0101
nnnn
nnnn
1110
0001
nnnn
nnnn
Description:
If the Overflow bit is ’0’, then the
program will branch.
Description:
If the Zero bit is ’0’, then the pro-
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Q Cycle Activity:
If Jump:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
Write to PC
Decode
Read literal
'n'
Process
Data
Write to PC
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If No Jump:
Q1
If No Jump:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
No
operation
Decode
Read literal
'n'
Process
Data
No
operation
HERE
BNOV Jump
HERE
BNZ Jump
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If Overflow=
PC
0;
If Zero
PC
If Zero
PC
=
=
=
0;
=
address (Jump)
1;
address (HERE+2)
address (Jump)
1;
address (HERE+2)
If Overflow
PC
=
DS39026D-page 198
1999-2013 Microchip Technology Inc.
PIC18CXX2
BRA
Unconditional Branch
[ label ] BRA
BSF
Bit Set f
Syntax:
n
Syntax:
[ label ] BSF f,b[,a]
Operands:
Operation:
Status Affected:
Encoding:
-1024 n 1023
(PC) + 2 + 2n PC
None
Operands:
0 f 255
0 b 7
a [0,1]
Operation:
1 f<b>
1101
0nnn
nnnn
nnnn
Status Affected:
Encoding:
None
Description:
Add the 2’s complement number
’2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is a two-
cycle instruction.
1000
bbba
ffff
ffff
Description:
Bit 'b' in register 'f' is set. If ‘a’ is 0
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value.
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
Write to PC
Decode
Read
register 'f'
Process
Data
Write
register 'f'
No
No
No
No
operation
operation
operation
operation
BSF
FLAG_REG, 7, 1
Example:
Before Instruction
HERE
BRA Jump
Example:
FLAG_REG=
0x0A
0x8A
Before Instruction
After Instruction
PC
=
=
address (HERE)
address (Jump)
FLAG_REG=
After Instruction
PC
1999-2013 Microchip Technology Inc.
DS39026D-page 199
PIC18CXX2
BTFSC
Bit Test File, Skip if Clear
BTFSS
Bit Test File, Skip if Set
Syntax:
[ label ] BTFSC f,b[,a]
Syntax:
[ label ] BTFSS f,b[,a]
Operands:
0 f 255
0 b 7
a [0,1]
Operands:
0 f 255
0 b < 7
a [0,1]
Operation:
skip if (f<b>) = 0
None
Operation:
skip if (f<b>) = 1
None
Status Affected:
Encoding:
Status Affected:
Encoding:
1011
bbba
ffff
ffff
1010
bbba
ffff
ffff
Description:
If bit 'b' in register ’f' is 0, then the
next instruction is skipped.
Description:
If bit 'b' in register 'f' is 1 then the next
instruction is skipped.
If bit 'b' is 0, then the next instruction
fetched during the current instruction
execution is discarded, and a NOPis
executed instead, making this a two-
cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
If bit 'b' is 1, then the next instruction
fetched during the current instruc-
tion execution, is discarded and a
NOPis executed instead, making this
a two-cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
Process Data
No
Decode
Read
Process Data
No
register 'f'
operation
register 'f'
operation
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Example:
Example:
Before Instruction
Before Instruction
PC
=
address (HERE)
PC
=
address (HERE)
After Instruction
After Instruction
If FLAG<1>
=
=
=
=
0;
If FLAG<1>
=
=
=
=
0;
PC
If FLAG<1>
PC
address (TRUE)
1;
address (FALSE)
PC
If FLAG<1>
PC
address (FALSE)
1;
address (TRUE)
DS39026D-page 200
1999-2013 Microchip Technology Inc.
PIC18CXX2
BTG
Bit Toggle f
BOV
Branch if Overflow
Syntax:
[ label ] BTG f,b[,a]
Syntax:
[ label ] BOV
-128 n 127
n
Operands:
0 f 255
0 b < 7
a [0,1]
Operands:
Operation:
if overflow bit is ’1’
(PC) + 2 + 2n PC
Operation:
(f<b>) f<b>
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
1110
0100
nnnn
nnnn
0111
bbba
ffff
ffff
Description:
If the Overflow bit is ’1’, then the
program will branch.
Description:
Bit 'b' in data memory location 'f' is
inverted. If ‘a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
Cycles:
1
1
Words:
Cycles:
1
1(2)
Q Cycle Activity:
Q1
Q Cycle Activity:
If Jump:
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
Q1
Q2
Q3
Q4
register 'f'
Decode
Read literal
'n'
Process
Data
Write to PC
BTG
PORTC, 4, 0
Example:
No
operation
No
operation
No
operation
No
operation
Before Instruction:
PORTC
=
0111 0101 [0x75]
If No Jump:
Q1
After Instruction:
Q2
Q3
Q4
PORTC
=
0110 0101 [0x65]
Decode
Read literal
'n'
Process
Data
No
operation
HERE
BOV Jump
Example:
Before Instruction
PC
=
address (HERE)
After Instruction
If Overflow=
PC
If Overflow
PC
1;
=
address (Jump)
0;
address (HERE+2)
=
1999-2013 Microchip Technology Inc.
DS39026D-page 201
PIC18CXX2
BZ
Branch if Zero
[ label ] BZ
CALL
Subroutine Call
Syntax:
n
Syntax:
[ label ] CALL k [,s]
Operands:
Operation:
-128 n 127
Operands:
0 k 1048575
s [0,1]
if Zero bit is ’1’
(PC) + 2 + 2n PC
Operation:
(PC) + 4 TOS,
k PC<20:1>,
if s = 1
(WREG) WS,
(STATUS) STATUSS,
(BSR) BSRS
Status Affected:
Encoding:
None
1110
0000
nnnn
nnnn
Description:
If the Zero bit is ’1’, then the pro-
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Status Affected:
None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
1110
1111
110s
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
19
Description:
Subroutine call of entire 2M byte
memory range. First, return
address (PC+ 4) is pushed onto the
return stack. If ’s’ = 1, the W,
Words:
Cycles:
1
1(2)
STATUS and BSR registers are
also pushed into their respective
shadow registers, WS, STATUSS
and BSRS. If 's' = 0, no update
occurs (default). Then the 20-bit
value ’k’ is loaded into PC<20:1>.
CALLis a two-cycle instruction.
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
2
2
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
No
operation
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal Push PC to Read literal
HERE
BZ Jump
Example:
'k'<7:0>,
stack
’k’<19:8>,
Write to PC
Before Instruction
PC
=
address (HERE)
No
No
No
No
operation
operation
operation
operation
After Instruction
If Zero
PC
If Zero
PC
=
=
=
1;
address (Jump)
0;
address (HERE+2)
HERE
CALL THERE,1
Example:
Before Instruction
PC
=
Address(HERE)
After Instruction
PC
TOS =
WS
BSRS=
=
Address(THERE)
Address (HERE + 4)
WREG
BSR
=
STATUSS = STATUS
DS39026D-page 202
1999-2013 Microchip Technology Inc.
PIC18CXX2
CLRF
Clear f
CLRWDT
Clear Watchdog Timer
Syntax:
[label] CLRF f [,a]
Syntax:
[ label ] CLRWDT
Operands:
0 f 255
a [0,1]
Operands:
Operation:
None
000h WDT,
000h WDT postscaler,
1 TO,
Operation:
000h f
1 Z
1 PD
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
TO, PD
0110
101a
ffff
ffff
0000
0000
0000
0100
Description:
Clears the contents of the specified
register. If ‘a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will
be selected as per the BSR value
(default).
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits
TO and PD are set.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
No
operation
Process
Data
No
operation
Decode
Read
register 'f'
Process
Data
Write
register 'f'
CLRWDT
Example:
CLRF
=
FLAG_REG,1
Example:
Before Instruction
WDT counter
=
=
?
Before Instruction
FLAG_REG
0x5A
0x00
After Instruction
WDT counter
WDT Postscaler =
TO
PD
0x00
After Instruction
0
1
1
FLAG_REG
=
=
=
1999-2013 Microchip Technology Inc.
DS39026D-page 203
PIC18CXX2
Compare f with WREG,
skip if f = WREG
CPFSEQ
COMF
Complement f
Syntax:
[ label ] COMF f [,d [,a]
Syntax:
[ label ] CPFSEQ f [,a]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
(f) – (WREG),
Operation:
(f) dest
skip if (f) = (WREG)
(unsigned comparison)
Status Affected:
Encoding:
N,Z
Status Affected:
Encoding:
None
0001
11da
ffff
ffff
0110
001a
ffff
ffff
Description:
The contents of register 'f' are com-
plemented. If 'd' is 0, the result is
stored in WREG. If 'd' is 1, the
result is stored back in register 'f'
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
Compares the contents of data
memory location 'f' to the contents
of WREG by performing an
unsigned subtraction.
If 'f' = WREG, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Words:
Cycles:
1
Decode
Read
register 'f'
Process
Data
Write to
1(2)
destination
Note: 3 cycles if skip and followed
by a 2-word instruction.
COMF
REG, 0, 0
Example:
Before Instruction
Q Cycle Activity:
Q1
REG
=
0x13
Q2
Q3
Q4
After Instruction
Decode
Read
register 'f'
Process
Data
No
operation
REG
=
0x13
0xEC
WREG
=
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
CPFSEQ REG, 0
Example:
NEQUAL
EQUAL
:
:
Before Instruction
PC Address
=
HERE
WREG
REG
=
=
?
?
After Instruction
If REG
PC
=
=
WREG;
Address (EQUAL)
If REG
PC
WREG;
Address (NEQUAL)
=
DS39026D-page 204
1999-2013 Microchip Technology Inc.
PIC18CXX2
Compare f with WREG,
skip if f > WREG
Compare f with WREG,
skip if f < WREG
CPFSGT
CPFSLT
Syntax:
[ label ] CPFSGT f [,a]
Syntax:
[ label ] CPFSLT f [,a]
Operands:
0 f 255
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
(f) WREG),
Operation:
(f) –WREG),
skip if (f) > (WREG)
skip if (f) < (WREG)
(unsigned comparison)
(unsigned comparison)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0110
010a
ffff
ffff
0110
000a
ffff
ffff
Description:
Compares the contents of data
memory location 'f' to the contents
of the WREG by performing an
unsigned subtraction.
Description:
Compares the contents of data
memory location 'f' to the contents
of WREG by performing an
unsigned subtraction.
If the contents of 'f' are greater than
the contents of WREG, then the
fetched instruction is discarded and
a NOPis executed instead, making
this a two-cycle instruction. If ‘a’ is
0, the Access Bank will be
If the contents of 'f' are less than
the contents of WREG, then the
fetched instruction is discarded and
a NOPis executed instead, making
this a two-cycle instruction. If ‘a’ is
0, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
selected. If ’a’ is 1, the BSR will not
be overridden (default).
Words:
Cycles:
1
1(2)
Words:
Cycles:
1
Note: 3 cycles if skip and followed
by a 2-word instruction.
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register 'f'
Process
Data
No
operation
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
If skip:
Q1
No
operation
No
operation
No
operation
No
operation
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
If skip and followed by 2-word instruction:
No
No
No
No
Q1
Q2
Q3
Q4
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NLESS
LESS
CPFSLT REG, 1
:
:
Example:
HERE
CPFSGT REG, 0
Example:
NGREATER
GREATER
:
:
Before Instruction
PC
W
=
=
Address (HERE)
?
Before Instruction
After Instruction
PC
=
=
Address (HERE)
?
WREG
If REG
PC
<
WREG;
Address (LESS)
=
After Instruction
If REG
PC
=
WREG;
Address (NLESS)
If REG
PC
>
=
WREG;
Address (GREATER)
If REG
PC
WREG;
Address (NGREATER)
=
1999-2013 Microchip Technology Inc.
DS39026D-page 205
PIC18CXX2
DAW
Decimal Adjust WREG Register
DECF
Decrement f
Syntax:
[label] DAW
Syntax:
[ label ] DECF f [,d [,a]
Operands:
Operation:
None
Operands:
0 f 255
d [0,1]
a [0,1]
If [WREG<3:0> >9] or [DC = 1] then
(WREG<3:0>) + 6 WREG<3:0>;
else
Operation:
(f) – 1 dest
(WREG<3:0>) WREG<3:0>;
Status Affected:
Encoding:
C,DC,N,OV,Z
0000
01da
ffff
ffff
If [WREG<7:4> >9] or [C = 1] then
(WREG<7:4>) + 6 WREG<7:4>;
else
Description:
Decrement register 'f'. If 'd' is 0, the
result is stored in WREG. If 'd' is 1,
the result is stored back in register
'f' (default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (default).
(WREG<7:4>) WREG<7:4>;
Status Affected:
Encoding:
C
0000
0000
0000
0111
Description:
DAW adjusts the eight-bit value in
WREG, resulting from the earlier
addition of two variables (each in
packed BCD format) and produces
a correct packed BCD result.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
WREG
Process
Data
Write
WREG
DECF
CNT,
1, 0
Example:
Before Instruction
CNT
Z
=
=
0x01
0
DAW
Example1:
Before Instruction
After Instruction
CNT
Z
=
=
0x00
1
WREG
C
DC
=
=
=
0xA5
0
0
After Instruction
WREG
=
0x05
C
DC
=
=
1
0
Example 2:
Before Instruction
WREG
=
0xCE
C
DC
=
=
0
0
After Instruction
WREG
=
0x34
C
DC
=
=
1
0
DS39026D-page 206
1999-2013 Microchip Technology Inc.
PIC18CXX2
DECFSZ
Decrement f, skip if 0
DCFSNZ
Decrement f, skip if not 0
Syntax:
[ label ] DECFSZ f [,d [,a]]
Syntax:
[label] DCFSNZ f [,d [,a]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) – 1 dest,
skip if result = 0
Operation:
(f) – 1 dest,
skip if result 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0010
11da
ffff
ffff
0100
11da
ffff
ffff
Description:
The contents of register 'f' are
decremented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default).
Description:
The contents of register 'f' are dec-
remented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default).
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded and a NOPis executed
instead, making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (default).
If the result is not 0, the next
instruction, which is already
fetched, is discarded and a NOPis
executed instead, making it a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ’a’ = 1,
then the bank will be selected as
per the BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
Decode
Read
register 'f'
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
DECFSZ
GOTO
CNT, 1, 1
LOOP
HERE
ZERO
NZERO
DCFSNZ TEMP, 1, 0
:
:
Example:
Example:
CONTINUE
Before Instruction
Before Instruction
PC
=
Address (HERE)
TEMP
=
?
After Instruction
After Instruction
CNT
If CNT
PC
If CNT
PC
=
=
=
=
CNT - 1
0;
Address (CONTINUE)
0;
TEMP
If TEMP
PC
If TEMP
PC
=
=
=
=
TEMP - 1,
0;
Address (ZERO)
0;
Address (NZERO)
Address (HERE+2)
1999-2013 Microchip Technology Inc.
DS39026D-page 207
PIC18CXX2
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
[ label ] GOTO k
0 k 1048575
k PC<20:1>
None
Syntax:
[ label ] INCF f [,d [,a]
Operands:
Operation:
Status Affected:
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) + 1 dest
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Status Affected:
Encoding:
C,DC,N,OV,Z
1110
1111
1111
k kkk
kkkk
kkkk
7
0
8
k
kkk kkkk
0010
10da
ffff
ffff
19
Description:
GOTOallows an unconditional
branch anywhere within entire
2 Mbyte memory range. The 20-bit
value ’k’ is loaded into PC<20:1>.
GOTOis always a two-cycle
instruction.
Description:
The contents of register 'f' are
incremented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Words:
Cycles:
1
1
Q2
Q3
Q4
Decode
Read literal
'k'<7:0>,
No
operation
Read literal
’k’<19:8>,
Write to PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
Decode
Read
register 'f'
Process
Data
Write to
destination
GOTO THERE
Example:
INCF
CNT, 1, 0
Example:
After Instruction
Before Instruction
PC
=
Address (THERE)
CNT
Z
=
0xFF
=
=
=
0
?
?
C
DC
After Instruction
CNT
Z
C
=
=
=
=
0x00
1
1
1
DC
DS39026D-page 208
1999-2013 Microchip Technology Inc.
PIC18CXX2
INCFSZ
Increment f, skip if 0
INFSNZ
Increment f, skip if not 0
Syntax:
[ label ] INCFSZ f [,d [,a]
Syntax:
[label] INFSNZ f [,d [,a]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) + 1 dest,
skip if result = 0
Operation:
(f) + 1 dest,
skip if result 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
0011
11da
ffff
ffff
0100
10da
ffff
ffff
Description:
The contents of register 'f' are
incremented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default).
Description:
The contents of register 'f' are
incremented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default).
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded and a NOPis executed
instead, making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (default).
If the result is not 0, the next
instruction, which is already
fetched, is discarded and a NOPis
executed instead, making it a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
Words:
Cycles:
1
1(2)
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
Decode
Read
register 'f'
Process
Data
Write to
destination
If skip:
Q1
If skip:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1, 0
HERE
ZERO
NZERO
INFSNZ REG, 1, 0
Example:
Example:
Before Instruction
Before Instruction
PC
=
Address (HERE)
PC
=
Address (HERE)
After Instruction
After Instruction
CNT
If CNT
PC
If CNT
PC
=
=
=
=
CNT + 1
0;
Address(ZERO)
0;
Address(NZERO)
REG
If REG
PC
If REG
PC
=
=
=
=
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
1999-2013 Microchip Technology Inc.
DS39026D-page 209
PIC18CXX2
IORLW
Inclusive OR literal with WREG
IORWF
Inclusive OR WREG with f
Syntax:
[ label ] IORLW k
0 k 255
Syntax:
[ label ] IORWF f [,d [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 f 255
d [0,1]
a [0,1]
(WREG) .OR. k WREG
N,Z
Operation:
(WREG) .OR. (f) dest
0000
1001
kkkk
kkkk
Status Affected:
Encoding:
N,Z
Description:
The contents of WREG are OR’ed
with the eight-bit literal 'k'. The
result is placed in WREG.
0001
00da
ffff
ffff
Description:
Inclusive OR WREG with register
'f'. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is
placed back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write to
WREG
Words:
Cycles:
1
1
IORLW
0x9A
0x35
Example:
Before Instruction
Q Cycle Activity:
Q1
WREG
=
Q2
Q3
Q4
After Instruction
Decode
Read
register 'f'
Process
Data
Write to
destination
WREG
=
0xBF
IORWF RESULT, 0, 1
Example:
Before Instruction
RESULT
=
0x13
0x91
WREG
=
After Instruction
RESULT
=
0x13
0x93
WREG
=
DS39026D-page 210
1999-2013 Microchip Technology Inc.
PIC18CXX2
LFSR
Load FSR
MOVF
Move f
Syntax:
[ label ] LFSR f,k
Syntax:
[ label ] MOVF f [,d [,a]
Operands:
0 f 2
0 k 4095
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
k FSRf
Operation:
f dest
Status Affected:
Encoding:
None
Status Affected:
Encoding:
N,Z
1110
1111
1110
0000
00ff
k kkk
11
kkkk
k kkk
0101
00da
ffff
ffff
7
Description:
The 12-bit literal 'k' is loaded into
the file select register pointed to
by 'f'.
Description:
The contents of register 'f' are
moved to a destination dependent
upon the status of ’d’. If 'd' is 0, the
result is placed in WREG. If 'd' is 1,
the result is placed back in register
'f' (default). Location 'f' can be any-
where in the 256 byte bank. If ’a’ is
0, the Access Bank will be
Words:
Cycles:
2
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Decode
Read literal
'k' MSB
Process
Data
Write
literal 'k'
MSB to
FSRfH
Decode
Read literal
'k' LSB
Process
Data
Write literal
'k' to FSRfL
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
LFSR 2, 0x3AB
Example:
Q2
Q3
Q4
After Instruction
Decode
Read
register 'f'
Process
Data
Write WREG
FSR2H
FSR2L
=
=
0x03
0xAB
MOVF
REG, 0, 0
Example:
Before Instruction
REG
=
=
0x22
0xFF
WREG
After Instruction
REG
=
=
0x22
0x22
WREG
1999-2013 Microchip Technology Inc.
DS39026D-page 211
PIC18CXX2
MOVFF
Move f to f
MOVLB
Move literal to low nibble in BSR
Syntax:
[label] MOVFF fs,fd
Syntax:
[ label ] MOVLB k
0 k 255
k BSR
Operands:
0 fs 4095
0 fd 4095
Operands:
Operation:
Status Affected:
Encoding:
Operation:
(fs) fd
None
Status Affected:
None
0000
0001
kkkk
kkkk
Encoding:
1st word (source)
2nd word (destin.)
Description:
The 8-bit literal 'k' is loaded into
the Bank Select Register (BSR).
1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Words:
Cycles:
1
1
Description:
The contents of source register 'fs'
are moved to destination register
'fd'. Location of source 'fs' can be
anywhere in the 4096 byte data
space (000h to FFFh), and location
of destination 'fd' can also be any-
where from 000h to FFFh.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
'k'
Process
Data
Write
literal 'k' to
BSR
Either source or destination can be
WREG (a useful special situation).
MOVFFis particularly useful for
transferring a data memory location
to a peripheral register (such as the
transmit buffer or an I/O port).
MOVLB
5
Example:
Before Instruction
BSR register
=
=
0x02
0x05
After Instruction
BSR register
The MOVFFinstruction cannot use
the PCL, TOSU, TOSH or TOSL as
the destination register.
Words:
Cycles:
2
2 (3)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
(src)
Process
Data
No
operation
Decode
No
operation
No
operation
Write
register 'f'
(dest)
No dummy
read
MOVFF
REG1, REG2
Example:
Before Instruction
REG1
REG2
=
=
0x33
0x11
After Instruction
REG1
REG2
=
=
0x33,
0x33
DS39026D-page 212
1999-2013 Microchip Technology Inc.
PIC18CXX2
MOVLW
Move literal to WREG
MOVWF
Move WREG to f
Syntax:
[ label ] MOVLW k
0 k 255
Syntax:
[ label ] MOVWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 f 255
a [0,1]
k WREG
None
Operation:
(WREG) f
Status Affected:
Encoding:
None
0000
1110
kkkk
kkkk
0110
111a
ffff
ffff
Description:
The eight-bit literal 'k' is loaded into
WREG.
Description:
Move data from WREG to register
'f'. Location 'f' can be anywhere in
the 256 byte bank. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write to
WREG
Words:
Cycles:
1
1
MOVLW
0x5A
Example:
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
WREG
=
0x5A
Decode
Read
register 'f'
Process
Data
Write
register 'f'
MOVWF
REG, 0
Example:
Before Instruction
WREG
REG
=
=
0x4F
0xFF
After Instruction
WREG
REG
=
=
0x4F
0x4F
1999-2013 Microchip Technology Inc.
DS39026D-page 213
PIC18CXX2
MULLW
Multiply Literal with WREG
MULWF
Multiply WREG with f
Syntax:
[ label ] MULLW
0 k 255
k
Syntax:
[ label ] MULWF f [,a]
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 f 255
a [0,1]
(WREG) x k PRODH:PRODL
Operation:
(WREG) x (f) PRODH:PRODL
None
Status Affected:
Encoding:
None
0000
1101
kkkk
kkkk
0000
001a
ffff
ffff
Description:
An unsigned multiplication is car-
ried out between the contents of
WREG and the 8-bit literal 'k'.
The 16-bit result is placed in
PRODH:PRODL register pair.
PRODH contains the high byte.
WREG is unchanged.
Description:
An unsigned multiplication is car-
ried out between the contents of
WREG and the register file loca-
tion 'f'. The 16-bit result is stored
in the PRODH:PRODL register
pair. PRODH contains the high
byte.
None of the status flags are
affected.
Both WREG and 'f' are
Note that neither overflow, nor
carry is possible in this opera-
tion. A zero result is possible but
not detected.
unchanged.
None of the status flags are
affected.
Note that neither overflow, nor
carry is possible in this opera-
tion. A zero result is possible but
not detected. If ‘a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ‘a’=
1, then the bank will be selected
as per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write
registers
PRODH:
PRODL
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
MULLW
=
0xC4
Example:
Q2
Q3
Q4
Before Instruction
Decode
Read
register 'f'
Process
Data
Write
WREG
PRODH
PRODL
0xE2
registers
PRODH:
PRODL
=
=
?
?
After Instruction
WREG
PRODH
PRODL
=
=
=
0xE2
0xAD
0x08
MULWF
=
REG, 1
Example:
Before Instruction
WREG
0xC4
REG
PRODH
PRODL
=
=
=
0xB5
?
?
After Instruction
WREG
=
0xC4
REG
PRODH
PRODL
=
=
=
0xB5
0x8A
0x94
DS39026D-page 214
1999-2013 Microchip Technology Inc.
PIC18CXX2
NEGF
Negate f
NOP
No Operation
Syntax:
[label] NEGF f [,a]
Syntax:
[ label ] NOP
None
Operands:
0 f 255
a [0,1]
Operands:
Operation:
Status Affected:
Encoding:
No operation
None
Operation:
( f ) + 1 f
Status Affected:
Encoding:
N,OV, C, DC, Z
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
0110
110a
ffff
ffff
Description:
Words:
No operation.
Description:
Location ‘f’ is negated using two’s
complement. The result is placed in
the data memory location 'f'. If ’a’ is
0, the Access Bank will be
1
1
Cycles:
Q Cycle Activity:
Q1
selected, overriding the BSR value.
If ’a’ = 1, then the bank will be
selected as per the BSR value.
Q2
No
Q3
No
Q4
Decode
No
operation
operation
operation
Words:
Cycles:
1
1
Example:
None.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write
register 'f'
NEGF
REG, 1
Example:
Before Instruction
REG
=
0011 1010 [0x3A]
1100 0110 [0xC6]
After Instruction
REG
=
1999-2013 Microchip Technology Inc.
DS39026D-page 215
PIC18CXX2
POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
Syntax:
[ label ] POP
None
Syntax:
[ label ] PUSH
None
Operands:
Operation:
Status Affected:
Encoding:
Operands:
Operation:
Status Affected:
Encoding:
(TOS) bit bucket
None
(PC+2) TOS
None
0000
0000
0000
0110
0000
0000
0000
0101
Description:
The TOS value is pulled off the
return stack and is discarded. The
TOS value then becomes the previ-
ous value that was pushed onto the
return stack.
This instruction is provided to
enable the user to properly manage
the return stack to incorporate a
software stack.
Description:
The PC+2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows to implement
a software stack by modifying TOS,
and then push it onto the return
stack.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
PUSH PC+2
onto return
stack
No
operation
No
operation
Q2
Q3
Q4
Decode
No
operation
POP TOS
value
No
operation
PUSH
Example:
POP
GOTO
Example:
Before Instruction
NEW
TOS
PC
=
=
00345Ah
000124h
Before Instruction
TOS
= 0031A2h
After Instruction
Stack (1 level down)= 014332h
PC
TOS
=
=
=
000126h
000126h
00345Ah
After Instruction
Stack (1 level down)
TOS
PC
=
=
014332h
NEW
DS39026D-page 216
1999-2013 Microchip Technology Inc.
PIC18CXX2
RCALL
Relative Call
RESET
Reset
Syntax:
[ label ] RCALL
-1024 n 1023
(PC) + 2 TOS,
n
Syntax:
[ label ] RESET
Operands:
Operation:
Operands:
Operation:
None
Reset all registers and flags that
are affected by a MCLR reset.
(PC) + 2 + 2n PC
Status Affected:
Encoding:
None
Status Affected:
Encoding:
All
1101
1nnn
nnnn
nnnn
0000
0000
1111
1111
Description:
Subroutine call with a jump up to
1K from the current location. First,
return address (PC+2) is pushed
onto the stack. Then, add the 2’s
complement number ’2n’ to the PC.
Since the PC will have incremented
to fetch the next instruction, the
new address will be PC+2+2n.
This instruction is a two-cycle
instruction.
Description:
This instruction provides a way to
execute a MCLR Reset in software.
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Start
reset
No
operation
No
operation
Words:
Cycles:
1
2
RESET
Example:
After Instruction
Registers
Flags*
=
=
Reset Value
Reset Value
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
Write to PC
Push PC to
stack
No
No
No
No
operation
operation
operation
operation
HERE
RCALL
Jump
Example:
Before Instruction
PC
=
Address(HERE)
After Instruction
PC
TOS =
=
Address(Jump)
Address (HERE+2)
1999-2013 Microchip Technology Inc.
DS39026D-page 217
PIC18CXX2
RETFIE
Return from Interrupt
RETLW
Return Literal to WREG
Syntax:
[ label ] RETFIE [s]
s [0,1]
Syntax:
[ label ] RETLW k
0 k 255
Operands:
Operation:
Operands:
Operation:
(TOS) PC,
k WREG,
1 GIE/GIEH or PEIE/GIEL,
if s = 1
(TOS) PC,
PCLATU, PCLATH are unchanged
(WS) WREG,
(STATUSS) STATUS,
(BSRS) BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged.
Description:
WREG is loaded with the eight-bit
literal 'k'. The program counter is
loaded from the top of the stack
(the return address). The high
address latch (PCLATH) remains
unchanged.
Status Affected:
Encoding:
GIE/GIEH,PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from Interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit. If ‘s’ = 1, the contents of
the shadow registers WS,
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
STATUSS and BSRS are loaded
into their corresponding registers,
WREG, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
Decode
Read
literal 'k'
Process
Data
pop PC from
stack, Write
to WREG
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
2
Example:
Q Cycle Activity:
Q1
CALL TABLE ; WREG contains table
Q2
Q3
Q4
; offset value
; WREG now has
; table value
:
Decode
No
operation
No
operation
pop PC from
stack
Set GIEH or
GIEL
TABLE
ADDWF PCL
; WREG = offset
; Begin table
;
No
operation
No
operation
No
operation
No
operation
RETLW k0
RETLW k1
:
RETFIE
1
:
Example:
RETLW kn
; End of table
After Interrupt
PC
W
=
=
=
=
TOS
WS
BSRS
STATUSS
1
Before Instruction
BSR
STATUS
GIE/GIEH, PEIE/GIEL=
WREG
=
0x07
After Instruction
WREG
=
value of kn
DS39026D-page 218
1999-2013 Microchip Technology Inc.
PIC18CXX2
RETURN
Return from Subroutine
RLCF
Rotate Left f through Carry
Syntax:
[ label ] RETURN [s]
s [0,1]
Syntax:
[ label ] RLCF f [,d [,a]
Operands:
Operation:
Operands:
0 f 255
d [0,1]
a [0,1]
(TOS) PC,
if s = 1
(WS) WREG,
(STATUSS) STATUS,
(BSRS) BSR,
Operation:
(f<n>) dest<n+1>,
(f<7>) C,
(C) dest<0>
PCLATU, PCLATH are unchanged
Status Affected:
Encoding:
C,N,Z
Status Affected:
Encoding:
None
0011
01da
ffff
ffff
0000
0000
0001
001s
Description:
The contents of register 'f' are
rotated one bit to the left through
the Carry Flag. If 'd' is 0, the result
is placed in WREG. If 'd' is 1, the
result is stored back in register 'f'
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (default).
Description:
Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counter. If ‘s’= 1, the contents of the
shadow registers WS, STATUSS
and BSRS are loaded into their cor-
responding registers, WREG,
STATUS and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
register f
C
Words:
Cycles:
1
2
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q2
Q3
Q4
Decode
No
Process
Data
pop PC from
stack
operation
Decode
Read
Process
Write to
No
No
No
No
register 'f'
Data
destination
operation
operation
operation
operation
RLCF
REG, 0, 0
Example:
Before Instruction
RETURN
Example:
REG
C
=
=
1110 0110
0
After Interrupt
After Instruction
PC = TOS
REG
=
1110 0110
WREG
C
=
=
1100 1100
1
1999-2013 Microchip Technology Inc.
DS39026D-page 219
PIC18CXX2
RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
Syntax:
[ label ] RLNCF f [,d [,a]
Syntax:
[ label ] RRCF f [,d [,a]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f<n>) dest<n+1>,
(f<7>) dest<0>
Operation:
(f<n>) dest<n-1>,
(f<0>) C,
(C) dest<7>
Status Affected:
Encoding:
N,Z
Status Affected:
Encoding:
C,N,Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register 'f' are
rotated one bit to the left. If 'd' is 0,
the result is placed in WREG. If 'd'
is 1, the result is stored back in reg-
ister 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, then
the bank will be selected as per the
BSR value (default).
Description:
The contents of register 'f' are
rotated one bit to the right through
the Carry Flag. If 'd' is 0, the result
is placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, then the
bank will be selected as per the
BSR value (default).
register f
Words:
Cycles:
1
1
register f
C
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register 'f'
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
Process
Write to
register 'f'
Data
destination
RLNCF
REG, 1, 0
Example:
Before Instruction
RRCF
REG, 0, 0
Example:
REG
=
1010 1011
0101 0111
After Instruction
Before Instruction
REG
=
REG
C
=
=
1110 0110
0
After Instruction
REG
=
1110 0110
WREG
C
=
=
0111 0011
0
DS39026D-page 220
1999-2013 Microchip Technology Inc.
PIC18CXX2
RRNCF
Rotate Right f (no carry)
SETF
Set f
Syntax:
[ label ] RRNCF f [,d [,a]
Syntax:
[label] SETF f [,a]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
a [0,1]
Operation:
FFh f
Operation:
(f<n>) dest<n-1>,
(f<0>) dest<7>
Status Affected:
Encoding:
None
0110
100a
ffff
ffff
Status Affected:
Encoding:
N,Z
Description:
The contents of the specified regis-
ter are set to FFh. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, then
the bank will be selected as per the
BSR value (default).
0100
00da
ffff
ffff
Description:
The contents of register 'f' are
rotated one bit to the right. If 'd' is 0,
the result is placed in WREG. If 'd'
is 1, the result is placed back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
register f
Decode
Read
register 'f'
Process
Data
Write
register 'f'
Words:
Cycles:
1
1
SETF
=
REG,1
Example:
Before Instruction
Q Cycle Activity:
Q1
REG
0x5A
0xFF
Q2
Q3
Q4
After Instruction
Decode
Read
register 'f'
Process
Data
Write to
destination
REG
=
RRNCF
REG, 1, 0
Example 1:
Before Instruction
REG
=
1101 0111
1110 1011
RRNCF REG, 0, 0
After Instruction
REG
=
Example 2:
Before Instruction
WREG
REG
=
=
?
1101 0111
After Instruction
WREG
REG
=
=
1110 1011
1101 0111
1999-2013 Microchip Technology Inc.
DS39026D-page 221
PIC18CXX2
SLEEP
Enter SLEEP mode
SUBFWB
Subtract f from WREG with borrow
Syntax:
[ label ] SLEEP
Syntax:
[ label ] SUBFWB f [,d [,a]
Operands:
Operation:
None
Operands:
0 f 255
d [0,1]
a [0,1]
00h WDT,
0 WDT postscaler,
1 TO,
Operation:
(WREG) – (f) – (C) dest
0 PD
Status Affected:
Encoding:
N,OV, C, DC, Z
Status Affected:
Encoding:
TO, PD
0101
01da
ffff
ffff
0000
0000
0000
0011
Description:
Subtract register 'f' and carry flag
(borrow) from WREG (2’s comple-
ment method). If 'd' is 0, the result is
stored in WREG. If 'd' is 1, the result
is stored in register 'f' (default). If ’a’ is
0, the Access Bank will be selected,
overriding the BSR value. If ’a’ is 1,
then the bank will be selected as per
the BSR value (default).
Description:
The power-down status bit (PD) is
cleared. The time-out status bit
(TO) is set. Watchdog Timer and
its postscaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
No
operation
Process
Data
Go to
sleep
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
SLEEP
Example:
SUBFWB
REG, 1, 0
Example 1:
Before Instruction
TO
PD
=
=
?
?
Before Instruction
REG
=
3
After Instruction
WREG
C
=
=
2
1
TO
PD
=
=
1 †
0
After Instruction
† If WDT causes wake-up, this bit is cleared.
REG
=
FF
2
WREG
=
C
Z
N
=
=
=
0
0
1
; result is negative
REG, 0, 0
SUBFWB
Example 2:
Before Instruction
REG
=
2
WREG
C
=
=
5
1
After Instruction
REG
=
2
3
WREG
=
C
Z
N
=
=
=
1
0
0
; result is positive
REG, 1, 0
SUBFWB
Example 3:
Before Instruction
REG
=
1
WREG
C
=
=
2
0
After Instruction
REG
=
0
2
WREG
=
C
Z
N
=
=
=
1
1
0
; result is zero
DS39026D-page 222
1999-2013 Microchip Technology Inc.
PIC18CXX2
SUBLW
Subtract WREG from literal
[ label ]
SUBWF
Syntax:
Subtract WREG from f
Syntax:
[ label ]
SUBLW k
SUBWF f [,d [,a]
Operands:
0 k 255
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
k – (WREG) WREG
N,OV, C, DC, Z
Status Affected:
Encoding:
Operation:
(f) – (WREG) dest
0000
1000
kkkk
kkkk
Status Affected:
Encoding:
N,OV, C, DC, Z
Description:
WREG is subtracted from the
eight-bit literal 'k'. The result is
placed in WREG.
0101
11da
ffff
ffff
Description:
Subtract WREG from register 'f'
(2’s complement method). If 'd' is
0, the result is stored in WREG. If
'd' is 1, the result is stored back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ’a’ is
1, then the bank will be selected
as per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write to
WREG
SUBLW 0x02
Example 1:
Words:
Cycles:
1
1
Before Instruction
WREG
C
=
=
1
?
Q Cycle Activity:
Q1
Q2
Q3
Q4
After Instruction
Decode
Read
register 'f'
Process
Data
Write to
destination
WREG
=
1
C
Z
N
=
=
=
1
0
0
; result is positive
SUBWF
REG, 1, 0
Example 1:
Before Instruction
REG
=
3
SUBLW 0x02
Example 2:
WREG
C
=
=
2
?
Before Instruction
WREG
C
=
=
2
?
After Instruction
REG
=
1
2
After Instruction
WREG
=
C
Z
N
=
=
=
1
0
0
; result is positive
REG, 0, 0
WREG
=
0
C
Z
N
=
=
=
1
1
0
; result is zero
SUBWF
Example 2:
SUBLW 0x02
Example 3:
Before Instruction
REG
=
2
Before Instruction
WREG
C
=
=
2
?
WREG
C
=
=
3
?
After Instruction
After Instruction
REG
=
2
0
WREG
=
FF
; (2’s complement)
; result is negative
WREG
=
C
Z
N
=
=
=
0
0
1
C
Z
N
=
=
=
1
1
0
; result is zero
REG, 1, 0
SUBWF
Example 3:
Before Instruction
REG
=
1
WREG
C
=
=
2
?
After Instruction
REG
=
FFh
2
;(2’s complement)
WREG
=
C
Z
N
=
=
=
0
0
1
; result is negative
1999-2013 Microchip Technology Inc.
DS39026D-page 223
PIC18CXX2
SUBWFB
Subtract WREG from f with Borrow
SWAPF
Swap f
Syntax:
[ label ] SUBWFB f [,d [,a]
Syntax:
[ label ] SWAPF f [,d [,a]
Operands:
0 f 255
d [0,1]
a [0,1]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(f) – (WREG) – (C) dest
Operation:
(f<3:0>) dest<7:4>,
(f<7:4>) dest<3:0>
Status Affected:
Encoding:
N,OV, C, DC, Z
Status Affected:
Encoding:
None
0101
10da
ffff
ffff
0011
10da
ffff
ffff
Description:
Subtract WREG and the carry flag
(borrow) from register 'f' (2’s comple-
ment method). If 'd' is 0, the result is
stored in WREG. If 'd' is 1, the result
is stored back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value. If
’a’ is 1, then the bank will be selected
as per the BSR value (default).
Description:
The upper and lower nibbles of reg-
ister 'f' are exchanged. If 'd' is 0, the
result is placed in WREG. If 'd' is 1,
the result is placed in register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, then the
bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register 'f'
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
SUBWFB REG, 1, 0
Example 1:
Before Instruction
SWAPF
REG, 1, 0
Example:
REG
=
0x19
0x0D
1
(0001 1001)
(0000 1101)
WREG
C
=
=
Before Instruction
REG
=
0x53
0x35
After Instruction
After Instruction
REG
=
0x0C
0x0D
(0000 1011)
(0000 1101)
REG
=
WREG
=
C
Z
N
=
=
=
1
0
0
; result is positive
SUBWFB REG, 0, 0
Example 2:
Before Instruction
REG
=
0x1B
0x1A
0
(0001 1011)
(0001 1010)
WREG
C
=
=
After Instruction
REG
=
0x1B
0x00
(0001 1011)
WREG
=
C
Z
N
=
=
=
1
1
0
; result is zero
SUBWFB REG, 1, 0
Example 3:
Before Instruction
REG
=
0x03
0x0E
1
(0000 0011)
(0000 1101)
WREG
C
=
=
After Instruction
REG
=
0xF5
0x0E
(1111 0100)
; [2’s comp]
(0000 1101)
WREG
=
C
Z
N
=
=
=
0
0
1
; result is negative
DS39026D-page 224
1999-2013 Microchip Technology Inc.
PIC18CXX2
TBLRD
Table Read
TBLRD
Table Read (cont’d)
TBLRD *+ ;
Syntax:
[ label ] TBLRD ( *; *+; *-; +*)
Example 1:
Operands:
Operation:
None
Before Instruction
TABLAT
TBLPTR
MEMORY(0x00A356)
=
=
=
0x55
0x00A356
0x34
if TBLRD *,
(Prog Mem (TBLPTR)) TABLAT;
TBLPTR - No Change;
if TBLRD *+,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) +1 TBLPTR;
if TBLRD *-,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) -1 TBLPTR;
if TBLRD +*,
After Instruction
TABLAT
TBLPTR
=
=
0x34
0x00A357
TBLRD +* ;
Example 2:
Before Instruction
TABLAT
TBLPTR
MEMORY(0x01A357)
MEMORY(0x01A358)
=
=
=
=
0xAA
0x01A357
0x12
0x34
(TBLPTR) +1 TBLPTR;
(Prog Mem (TBLPTR)) TABLAT;
After Instruction
TABLAT
TBLPTR
=
=
0x34
0x01A358
Status Affected: None
0000
0000
0000
10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Encoding:
Description:
This instruction is used to read the
contents of Program Memory (P.M.). To
address the program memory, a
pointer called Table Pointer (TBLPTR)
is used.
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2 Mbyte address range.
TBLPTR[0] = 0:Least Significant
Byte of Program Memory Word
TBLPTR[0] = 1:Most Significant
Byte of Program Memory Word
The TBLRDinstruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
No
No
operation
operation
operation
No
No
No
No
operation
operation
(Read
operation
operation
(Write
Program
Memory)
TABLAT)
1999-2013 Microchip Technology Inc.
DS39026D-page 225
PIC18CXX2
TBLWT
Table Write
TBLWT
Table Write (Continued)
TBLWT *+;
Syntax:
[ label ]
None
TBLWT ( *; *+; *-; +*)
Example 1:
Operands:
Operation:
Before Instruction
TABLAT
TBLPTR
=
=
=
0x55
0x00A356
0xFF
if TBLWT*,
(TABLAT) Prog Mem (TBLPTR)
MEMORY(0x00A356)
or Holding Register;
TBLPTR - No Change;
if TBLWT*+,
After Instructions (table write completion)
TABLAT
TBLPTR
MEMORY(0x00A356)
=
=
=
0x55
0x00A357
0x55
(TABLAT) Prog Mem (TBLPTR)
or Holding Register;
TBLWT +*;
Example 2:
(TBLPTR) +1 TBLPTR;
if TBLWT*-,
Before Instruction
TABLAT
=
=
=
=
0x34
0x01389A
0xFF
TBLPTR
MEMORY(0x01389A)
MEMORY(0x01389B)
(TABLAT) Prog Mem (TBLPTR)
or Holding Register;
(TBLPTR) -1 TBLPTR;
0xFF
After Instruction (table write completion)
if TBLWT+*,
TABLAT
TBLPTR
MEMORY(0x01389A)
MEMORY(0x01389B)
=
=
=
=
0x34
0x01389B
0xFF
(TBLPTR) +1 TBLPTR;
(TABLAT) Prog Mem (TBLPTR)
or Holding Register;
0x34
Status Affected:
Encoding:
None
0000
0000
0000
11nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description:
This instruction is used to program the
contents of Program Memory (P.M.).
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2 Mbyte address
range. The LSb of the TBLPTR
selects which byte of the program
memory location to access.
TBLPTR[0] = 0:Least Significant
Byte of Program Memory Word
TBLPTR[0] = 1:Most Significant
Byte of Program Memory Word
The TBLWTinstruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words:
Cycles:
1
2 (many if long write is to on-chip
EPROM program memory)
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
No
No
operation
operation
operation
No
No
No
No
operation
operation
(Read
TABLAT)
operation
operation
(Write to Holding
Register or Memory)
DS39026D-page 226
1999-2013 Microchip Technology Inc.
PIC18CXX2
TSTFSZ
Test f, skip if 0
XORLW
Exclusive OR literal with WREG
Syntax:
[ label ] TSTFSZ f [,a]
Syntax:
[ label ]
XORLW k
Operands:
0 f 255
a [0,1]
Operands:
0 k 255
Operation:
(WREG) .XOR. k WREG
Operation:
skip if f = 0
None
Status Affected:
Encoding:
N,Z
Status Affected:
Encoding:
0000
1010
kkkk
kkkk
0110
011a
ffff
ffff
Description:
The contents of WREG are
XORed with the 8-bit literal 'k'.
The result is placed in WREG.
Description:
If 'f' = 0, the next instruction,
fetched during the current instruc-
tion execution, is discarded and a
NOPis executed, making this a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1,
then the bank will be selected as
per the BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
Data
Write to
WREG
Words:
Cycles:
1
1(2)
Example:
XORLW0xAF
= 0xB5
Note: 3 cycles if skip and followed
by a 2-word instruction.
Before Instruction
WREG
Q Cycle Activity:
Q1
After Instruction
Q2
Q3
Q4
WREG
=
0x1A
Decode
Read
register 'f'
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NZERO
ZERO
TSTFSZ CNT, 1
:
Example:
:
Before Instruction
PC = Address(HERE)
After Instruction
If CNT
=
=
=
0x00,
Address (ZERO)
0x00,
PC
If CNT
PC
Address (NZERO)
1999-2013 Microchip Technology Inc.
DS39026D-page 227
PIC18CXX2
XORWF
Exclusive OR WREG with f
Syntax:
[ label ] XORWF f [,d [,a]
Operands:
0 f 255
d [0,1]
a [0,1]
Operation:
(WREG) .XOR. (f) dest
Status Affected:
Encoding:
N,Z
0001
10da
ffff
ffff
Description:
Exclusive OR the contents of
WREG with register 'f'. If 'd' is 0, the
result is stored in WREG. If 'd' is 1,
the result is stored back in the reg-
ister 'f' (default). If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, then
the bank will be selected as per the
BSR value (default).
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
XORWF
REG, 1, 0
Example:
Before Instruction
REG
=
0xAF
0xB5
WREG
=
After Instruction
REG
=
0x1A
0xB5
WREG
=
DS39026D-page 228
1999-2013 Microchip Technology Inc.
PIC18CXX2
The MPLAB IDE allows you to:
20.0 DEVELOPMENT SUPPORT
• Edit your source files (either assembly or ‘C’)
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools (auto-
matically updates all project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- absolute listing file
- machine code
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
• Simulators
- MPLAB SIM Software Simulator
• Emulators
20.2 MPASM Assembler
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
The MPASM assembler is a full-featured universal
macro assembler for all PIC MCUs.
- MPLAB ICD for PIC16F87X
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
Programmer
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be used through MPLAB IDE. The MPASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- KEELOQ® Demonstration Board
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
20.1 MPLAB Integrated Development
Environment Software
• Conditional assembly for multi-purpose source
files.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• Directives that allow complete control over the
assembly process.
20.3 MPLAB C17 and MPLAB C18
C Compilers
• An interface to debugging tools
- simulator
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• Customizable toolbar and key mapping
• A status bar
• On-line help
1999-2013 Microchip Technology Inc.
DS39026D-page 229
PIC18CXX2
20.4 MPLINK Object Linker/
MPLIB Object Librarian
20.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC micro-
controllers (MCUs). Software control of the MPLAB ICE
in-circuit emulator is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
building, downloading and source debugging from a
single environment.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PIC microcontrollers.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
• Allows all memory areas to be defined as sections
to provide link-time flexibility.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
20.7 ICEPIC In-Circuit Emulator
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC16C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
20.5 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC-hosted environment by simulating the
PIC series microcontrollers on an instruction level. On
any given instruction, the data areas can be examined
or modified and stimuli can be applied from a file, or
user-defined key press, to any of the pins. The execu-
tion can be performed in single step, execute until
break, or trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multi-
project software development tool.
DS39026D-page 230
1999-2013 Microchip Technology Inc.
PIC18CXX2
20.8 MPLAB ICD In-Circuit Debugger
20.11 PICDEM 1 Low Cost PIC MCU
Demonstration Board
Microchip's In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PIC16F87X and can be used to
develop for this and other PIC microcontrollers from the
PIC16CXXX family. The MPLAB ICD utilizes the in-cir-
cuit debugging capability built into the PIC16F87X. This
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
feature, along with Microchip's
In-Circuit Serial
ProgrammingTM protocol, offers cost-effective in-circuit
FLASH debugging from the graphical user interface of
the MPLAB Integrated Development Environment. This
enables a designer to develop and debug source code
by watching variables, single-stepping and setting
break points. Running at full speed enables testing
hardware in real-time.
20.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In stand-alone mode, the PRO MATE II
device programmer can read, verify, or program PIC
devices. It can also set code protection in this mode.
20.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
serial EEPROM to demonstrate usage of the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
20.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PIC devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
1999-2013 Microchip Technology Inc.
DS39026D-page 231
PIC18CXX2
20.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
20.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstration board supports downloading of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Addition-
ally, a generous prototype area is available for user
hardware.
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Mod-
ule. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of display-
ing time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
20.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
DS39026D-page 232
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 20-1: DEVELOPMENT TOOLS FROM MICROCHIP
0 1 5 2 P M C
X X X C R M F
H C S X X X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X C 8 2 C 1 P I
X 7 X 7 C 1 C I P
X 4 1 7 C I C P
X 9 X 6 C 1 C I P
X 8 X 6 F 1 C I P
X 8 1 6 C I C P
X 7 X 6 C 1 C I P
X 7 1 6 C I C P
X 6 2 1 6 C I F P
X X X C 6 C 1 P I
X 6 1 6 C I C P
X 5 1 6 C I C P
0 0 1 4 C I 0 P
X X X C 2 C 1 P I
s o l T e o r a w f t S o s r o t a u l E m r e g g u b D e s r e m m a o g P r r
s t K l a i E d v n a s d r a B o o m D e
1999-2013 Microchip Technology Inc.
DS39026D-page 233
PIC18CXX2
NOTES:
DS39026D-page 234
1999-2013 Microchip Technology Inc.
PIC18CXX2
21.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ....................................... -0.3 V to (VDD + 0.3 V)
Voltage on VDD with respect to VSS ....................................................................................................... -0.3 V to +7.5 V
Voltage on MCLR with respect to VSS (Note 2) ....................................................................................... 0 V to +13.25 V
Voltage on RA4 with respect to Vss............................................................................................................. 0 V to +8.5 V
Total power dissipation (Note 1) ..............................................................................................................................1.0 W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk byPORTA, PORTB, and PORTE (Note 3) (combined)...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined)..............................................200 mA
Maximum current sunk by PORTC and PORTD (Note 3) (combined)..................................................................200 mA
Maximum current sourced by PORTC and PORTD (Note 3) (combined).............................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL)
2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin, rather
than pulling this pin directly to VSS.
3: PORTD and PORTE not available on the PIC18C2X2 devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1999-2013 Microchip Technology Inc.
DS39026D-page 235
PIC18CXX2
FIGURE 21-1:
PIC18CXX2 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED)
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
PIC18CXXX
4.2V
3.5 V
3.0 V
2.5 V
2.0 V
40 MHz
Frequency
FIGURE 21-2:
PIC18LCXX2 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
PIC18LCXXX
4.2V
3.5 V
3.0 V
2.5 V
2.0 V
40 MHz
6 MHz
Frequency
FMAX = (20.0 MHz/V) (VDDAPPMIN - 2.5 V) + 6 MHz
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
DS39026D-page 236
1999-2013 Microchip Technology Inc.
PIC18CXX2
21.1 DC Characteristics
PIC18LCXX2
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18CXX2
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
(Industrial, Extended)
Param
No.
Symbol
Characteristic
Supply Voltage
Min
Typ Max Units
Conditions
VDD
D001
PIC18LCXX2 2.5
PIC18CXX2 4.2
—
—
—
5.5
5.5
—
V
V
V
HS, XT, RC and LP osc mode
D001
D002
VDR
RAM Data Retention
1.5
Voltage(1)
D003
D004
VPOR
VDD Start Voltage
to ensure internal
Power-on Reset signal
—
—
—
0.7
—
V
See section on Power-on Reset for details
SVDD
VBOR
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
V/ms See section on Power-on Reset for details
Brown-out Reset Voltage
PIC18LCXX2
D005
D005
BORV1:BORV0 = 11 2.5
BORV1:BORV0 = 10 2.7
BORV1:BORV0 = 01 4.2
BORV1:BORV0 = 00 4.5
PIC18CXX2
—
—
—
—
2.66
2.86
4.46
4.78
V
V
V
V
BORV1:BORV0 = 1x N.A.
BORV1:BORV0 = 01 4.2
BORV1:BORV0 = 00 4.5
—
—
—
N.A.
4.46
4.78
V
V
V
Not in operating voltage range of device
Legend: Shading of rows is to assist in readability of the table.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM
data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all fea-
tures that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...).
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
1999-2013 Microchip Technology Inc.
DS39026D-page 237
PIC18CXX2
21.1 DC Characteristics (Continued)
PIC18LCXX2
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18CXX2
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
(Industrial, Extended)
Param
No.
Symbol
Characteristic
Min
Typ Max Units
Conditions
IDD
Supply Current(2,4)
D010
PIC18LCXX2
—
—
—
—
—
—
—
—
—
—
—
—
2
4
mA XT, RC, RCIO osc configurations
FOSC = 4 MHz, VDD = 2.5V
D010
PIC18CXX2
PIC18LCXX2
PIC18CXX2
PIC18LCXX2
PIC18CXX2
PIC18LCXX2
mA XT, RC, RCIO osc configurations
FOSC = 4 MHz, VDD = 4.2V
D010A
D010A
D010C
D010C
D013
55
A LP osc configuration
FOSC = 32 kHz, VDD = 2.5V
250 A LP osc configuration
FOSC = 32 kHz, VDD = 4.2V
38
mA EC, ECIO osc configurations
FOSC = 40 MHz, VDD = 5.5V
38
mA EC, ECIO osc configurations
FOSC = 40 MHz, VDD = 5.5V
HS osc configuration
—
—
—
—
3.5 mA FOSC = 6 MHz, VDD = 2.5V
25
mA FOSC = 25 MHz, VDD = 5.5V
HS + PLL osc configurations
—
—
38
mA FOSC = 10 MHz, VDD = 5.5V
D013
PIC18CXX2
HS osc configuration
—
—
—
—
25
38
mA FOSC = 25 MHz, VDD = 5.5V
HS + PLL osc configurations
mA FOSC = 10 MHz, VDD = 5.5V
D014
D014
PIC18LCXX2
PIC18CXX2
Timer1 osc configuration
A FOSC = 32 kHz, VDD = 2.5V
—
—
55
OSCB osc configuration
—
—
—
—
200 A FOSC = 32 kHz, VDD = 4.2V, -40C to +85C
250 A FOSC = 32 kHz, VDD = 4.2V, -40C to +125C
Legend: Shading of rows is to assist in readability of the table.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM
data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all fea-
tures that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...).
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
DS39026D-page 238
1999-2013 Microchip Technology Inc.
PIC18CXX2
21.1 DC Characteristics (Continued)
PIC18LCXX2
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC18CXX2
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
(Industrial, Extended)
Param
No.
Symbol
Characteristic
Min
Typ Max Units
Conditions
IPD
Power-down Current(3)
D020
—
—
<.5
—
2
4
A VDD = 2.5V, -40C to +85C
A VDD = 5.5V, -40C to +85C
PIC18LCXX2
D020
PIC18CXX2
—
—
—
—
<1
—
—
—
3
4
15
20
A VDD = 4.2V, -40C to +85C
A VDD = 5.5V, -40C to +85C
A VDD = 4.2V, -40C to +125C
A VDD = 5.5V, -40C to +125C
D021B
Module Differential Current
D022
IWDT
IBOR
ILVD
Watchdog Timer
—
—
—
—
1
15
A VDD = 2.5V
A VDD = 5.5V
A VDD = 5.5V, -40C to +85C
A VDD = 5.5V, -40C to +125C
PIC18LCXX2
D022
Watchdog Timer
—
—
—
—
15
20
PIC18CXX2
D022A
D022A
D022B
D022B
D025
Brown-out Reset
—
—
45
A VDD = 2.5V
PIC18LCXX2
Brown-out Reset
—
—
—
—
50
50
A VDD = 5.5V, -40C to +85C
A VDD = 5.5V, -40C to +125
A VDD = 2.5V
PIC18CXX2
Low Voltage Detect
—
—
45
PIC18LCXX2
Low Voltage Detect
—
—
—
—
50
50
A VDD = 4.2V, -40C to +85C
A VDD = 4.2V, -40C to +125C
A VDD = 2.5V
PIC18CXX2
IOSCB
Timer1 Oscillator
—
—
15
PIC18LCXX2
D025
Timer1 Oscillator
—
—
—
—
100 A VDD = 4.2V, -40C to +85C
120 A VDD = 4.2V, -40C to +125C
PIC18CXX2
Legend: Shading of rows is to assist in readability of the table.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM
data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all fea-
tures that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...).
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
1999-2013 Microchip Technology Inc.
DS39026D-page 239
PIC18CXX2
21.2 DC Characteristics: PIC18CXX2 (Industrial, Extended)
PIC18LCXX2 (Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VIL
Input Low Voltage
I/O ports:
with TTL buffer
D030
D030A
D031
Vss
—
0.15VDD
0.8
V
V
VDD < 4.5V
4.5V VDD 5.5V
with Schmitt Trigger buffer
RC3 and RC4
Vss
Vss
0.2VDD
0.3VDD
V
V
D032
MCLR
VSS
VSS
0.2VDD
0.3VDD
V
V
D032A
OSC1 (in XT, HS and LP modes)
and T1OSI
D033
OSC1 (in RC and EC mode)(1)
Input High Voltage
I/O ports:
VSS
0.2VDD
V
VIH
D040
with TTL buffer
0.25VDD +
0.8V
VDD
VDD
V
V
VDD < 4.5V
D040A
2.0
4.5V VDD 5.5V
D041
with Schmitt Trigger buffer
RC3 and RC4
0.8VDD
0.7VDD
VDD
VDD
V
V
D042
MCLR, OSC1 (EC mode)
0.8VDD
0.7VDD
VDD
VDD
V
V
D042A
OSC1 (in XT, HS and LP modes)
and T1OSI
D043
D060
OSC1 (RC mode)(1)
Input Leakage Current(2,3)
I/O ports
0.9VDD
—
VDD
V
IIL
1
A VSS VPIN VDD,
Pin at hi-impedance
D061
D063
MCLR
—
—
5
5
A Vss VPIN VDD
A Vss VPIN VDD
OSC1
IPU
Weak Pull-up Current
PORTB weak pull-up current
D070 IPURB
50
400
A VDD = 5V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC MCU be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
DS39026D-page 240
1999-2013 Microchip Technology Inc.
PIC18CXX2
21.2 DC Characteristics: PIC18CXX2 (Industrial, Extended)
PIC18LCXX2 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
Symbol
No.
Characteristic
Min
Max
Units
Conditions
VOL
Output Low Voltage
I/O ports
D080
—
—
—
—
0.6
0.6
0.6
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40C to +85C
IOL = 7.0 mA, VDD = 4.5V,
-40C to +125C
IOL = 1.6 mA, VDD = 4.5V,
-40C to +85C
IOL = 1.2 mA, VDD = 4.5V,
D080A
D083
OSC2/CLKOUT
(RC mode)
D083A
-40C to +125C
VOH
Output High Voltage(3)
D090
I/O ports
VDD - 0.7
VDD - 0.7
VDD - 0.7
VDD - 0.7
—
—
—
V
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40C to +85C
IOH = -2.5 mA, VDD = 4.5V,
-40C to +125C
IOH = -1.3 mA, VDD = 4.5V,
-40C to +85C
IOH = -1.0 mA, VDD = 4.5V,
-40C to +125C
D090A
D092
OSC2/CLKOUT
(RC mode)
—
D092A
—
D150 VOD
Open Drain High Voltage
8.5
RA4 pin
Capacitive Loading Specs
on Output Pins
D101 CIO
D102 CB
All I/O pins and OSC2
(in RC mode)
—
—
50
pF To meet the AC Timing
Specifications
pF In I2C mode
SCL, SDA
400
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC MCU be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
1999-2013 Microchip Technology Inc.
DS39026D-page 241
PIC18CXX2
FIGURE 21-3:
LOW VOLTAGE DETECT CHARACTERISTICS
VDD
(LVDIF can be
cleared in software)
VLVD
(LVDIF set by hardware)
LVDIF
TABLE 21-1: LOW VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Symbol
Characteristic
LVD Voltage
Min
Max
Units
Conditions
D420
VLVD
LVV<3:0> = 0100
LVV<3:0> = 0101
LVV<3:0> = 0110
LVV<3:0> = 0111
LVV<3:0> = 1000
LVV<3:0> = 1001
LVV<3:0> = 1010
LVV<3:0> = 1011
LVV<3:0> = 1100
LVV<3:0> = 1101
LVV<3:0> = 1110
2.5
2.7
2.8
3.0
3.3
3.5
3.6
3.8
4.0
4.2
4.5
2.66
2.86
2.98
3.2
3.52
3.72
3.84
4.04
4.26
4.46
4.78
V
V
V
V
V
V
V
V
V
V
V
DS39026D-page 242
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 21-2: EPROM PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +40°C
DC CHARACTERISTICS
Param.
Sym
Characteristic
Min
Max Units
Conditions
No.
Internal Program Memory
Programming Specs (Note 1)
Voltage on MCLR/VPP pin
Supply voltage during
programming
D110
D111
VPP
12.75
4.75
13.25
5.25
V
V
(Note 2)
VDDP
D112
D113
IPP
Current into MCLR/VPP pin
Supply current during
programming
—
—
50
30
mA
mA
IDDP
D114
D115
TPROG Programming pulse width
50
1000
s Terminated via internal/external
interrupt or a RESET
TERASE EPROM erase time
Device operation 3V
Device operation 3V
60
30
—
—
min.
min.
Note 1: These specifications are for the programming of the on-chip program memory EPROM through the use of
the table write instructions. The complete programming specifications can be found in the
PIC18CXXX Programming Specifications (Literature Number DS39028).
2: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
1999-2013 Microchip Technology Inc.
DS39026D-page 243
PIC18CXX2
21.3 AC (Timing) Characteristics
21.3.1
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
ck
cs
di
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
Fall
P
R
V
Z
Period
H
High
Rise
I
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
Hold
SU
Setup
ST
DAT
STA
DATA input hold
START condition
STO
STOP condition
DS39026D-page 244
1999-2013 Microchip Technology Inc.
PIC18CXX2
21.3.2
TIMING CONDITIONS
The temperature and voltages specified in Table 21-3
apply to all timing specifications unless otherwise
noted. Figure 21-4 specifies the load conditions for the
timing specifications.
TABLE 21-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
AC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 21.1.
LC parts operate for industrial temperatures only.
FIGURE 21-4:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1 Load condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2/CLKOUT
and including D and E outputs as ports
VSS
1999-2013 Microchip Technology Inc.
DS39026D-page 245
PIC18CXX2
21.3.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 21-5:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
1
3
4
4
3
2
CLKOUT
TABLE 21-4: EXTERNAL CLOCK TIMING REQUIREMENTS
Param. No. Symbol
1A
Characteristic
Min
Max
Units
Conditions
FOSC
External CLKIN
DC
DC
4
DC
DC
4
MHz XT osc
MHz HS osc
MHz HS + PLL osc
kHz LP osc
Frequency(1)
25
10
40
40
MHz EC, ECIO
Oscillator Frequency(1)
DC
0.1
4
4
5
4
4
25
10
200
MHz RC osc
MHz XT osc
MHz HS osc
MHz HS + PLL osc
kHz LP osc mode
1
TOSC
External CLKIN Period(1)
Oscillator Period(1)
250
40
100
25
—
—
250
—
ns
ns
ns
s
ns
XT and RC osc
HS osc
HS + PLL osc
LP osc
25
—
EC, ECIO
250
250
25
100
25
—
10,000
250
250
—
ns
ns
ns
ns
s
RC osc
XT osc
HS osc
HS + PLL osc
LP osc
2
3
TCY
TosL,
TosH
Instruction Cycle Time(1)
External Clock in (OSC1)
High or Low Time
100
30
2.5
10
—
—
—
—
ns
ns
s
ns
ns
ns
ns
TCY = 4/FOSC
XT osc
LP osc
HS osc
XT osc
LP osc
—
4
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
20
50
7.5
—
—
HS osc
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
DS39026D-page 246
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 21-5: PLL CLOCK TIMING SPECIFICATION (VDD = 4.2V - 5.5V)
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
TRC
PLL Start-up Time (Lock Time)
—
-2
2
ms
%
CLK
CLKOUT Stability (Jitter) using PLL
+2
FIGURE 21-6:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
14
12
19
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-6: CLKOUT AND I/O TIMING REQUIREMENTS
Param.
Symbol
Characteristic
Min
Typ
Max
Units Conditions
No.
10
TosH2ckL OSC1 to CLKOUT
TosH2ckH OSC1 to CLKOUT
—
75
75
35
35
—
—
—
50
—
—
200
200
100
100
ns
ns
ns
ns
(1)
(1)
(1)
(1)
(1)
(1)
(1)
11
—
12
13
14
15
16
17
18
18A
TckR
TckF
CLKOUT rise time
CLKOUT fall time
—
—
TckL2ioV CLKOUT to Port out valid
—
0.5TCY + 20 ns
TioV2ckH Port in valid before CLKOUT
TckH2ioI Port in hold after CLKOUT
TosH2ioV OSC1 (Q1 cycle) to Port out valid
TosH2ioI OSC1 (Q2 cycle) to PIC18CXXX
0.25TCY + 25
—
—
ns
ns
ns
ns
ns
0
—
150
—
100
200
Port input invalid
(I/O in hold time)
PIC18LCXXX
—
19
TioV2osH Port input valid to OSC1
0
—
—
ns
(I/O in setup time)
20
TioR
TioF
Port output rise time
Port output fall time
INT pin high or low time
PIC18CXXX
PIC18LCXXX
PIC18CXXX
PIC18LCXXX
—
—
12
—
12
—
—
—
25
50
25
50
—
—
ns
ns
ns
ns
ns
ns
ns
20A
21
—
21A
22††
23††
24††
—
TINP
TCY
TCY
20
TRBP
TRCP
RB7:RB4 change INT high or low time
RC7:RC4 change INT high or low time
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
1999-2013 Microchip Technology Inc.
DS39026D-page 247
PIC18CXX2
FIGURE 21-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 21-4 for load conditions.
FIGURE 21-8:
BROWN-OUT RESET TIMING
BVDD
VDD
35
VBGAP = 1.2V
VIRVST
Enable Internal Reference Voltage
Internal Reference Voltage Stable
36
TABLE 21-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TmcL
TWDT
MCLR Pulse Width (low)
2
7
—
—
s
ms
31
Watchdog Timer Time-out Period
(No Postscaler)
18
33
32
33
34
TOST
TPWRT
TIOZ
Oscillation Start-up Timer Period 1024TOSC
—
72
2
1024TOSC
132
—
ms
s
TOSC = OSC1 period
Power up Timer Period
28
—
I/O Hi-impedance from MCLR
Low or Watchdog Timer Reset
—
35
36
TBOR
Tivrst
Brown-out Reset Pulse Width
200
—
—
—
s
s
VDD BVDD (See D005)
Time for Internal Reference
Voltage to become stable
20
50
DS39026D-page 248
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 21-9:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
40
Tt0H
T0CKI High Pulse Width No Prescaler
With Prescaler
0.5TCY + 20
10
—
—
—
—
—
—
ns
ns
ns
ns
ns
41
42
Tt0L
Tt0P
T0CKI Low Pulse Width No Prescaler
With Prescaler
0.5TCY + 20
10
T0CKI Period
No Prescaler
TCY + 10
With Prescaler
Greater of:
20 nS or TCY + 40
N
ns N = prescale
value
(1, 2, 4,..., 256)
45
46
Tt1H
Tt1L
T1CKI Synchronous, no prescaler
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
High
Time
Synchronous,
with prescaler
PIC18CXXX
10
PIC18LCXXX
25
Asynchronous PIC18CXXX
PIC18LCXXX
30
40
T1CKI Synchronous, no prescaler
0.5TCY + 20
Low
Time
Synchronous,
with prescaler
PIC18CXXX
15
30
30
40
PIC18LCXXX
Asynchronous PIC18CXXX
PIC18LCXXX
47
48
Tt1P
Ft1
T1CKI Synchronous
input
period
Greater of:
20 nS or TCY + 40
N
ns N = prescale
value
(1, 2, 4, 8)
Asynchronous
60
DC
—
50
ns
kHz
—
T1CKI oscillator input frequency range
Tcke2tmrI Delay from external T1CKI clock edge to
timer increment
2TOSC
7TOSC
1999-2013 Microchip Technology Inc.
DS39026D-page 249
PIC18CXX2
FIGURE 21-10:
CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
CCPx
(Capture Mode)
50
51
52
54
CCPx
(Compare or PWM Mode)
53
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-9: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
50
TccL
CCPx input low No Prescaler
0.5TCY + 20
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
time
With
PIC18CXXX
10
Prescaler
PIC18LCXXX
20
0.5TCY + 20
10
51
TccH
CCPx input
high time
No Prescaler
With
PIC18CXXX
Prescaler
PIC18LCXXX
20
52
53
TccP
TccR
CCPx input period
3TCY + 40
N
N = prescale
value (1,4 or 16)
CCPx output fall time
PIC18CXXX
PIC18LCXXX
PIC18CXXX
PIC18LCXXX
—
—
—
—
25
50
25
50
ns
ns
ns
ns
54
TccF
CCPx output fall time
DS39026D-page 250
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 21-11:
PARALLEL SLAVE PORT TIMING (PIC18C4X2)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18C4X2)
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
62
TdtV2wrH Data in valid before WR or CS
20
25
—
—
ns
ns
(setup time)
Extended Temp. Range
63
64
TwrH2dtI WR or CS to data–in invalid PIC18CXXX
20
35
—
—
ns
ns
(hold time)
PIC18LCXXX
TrdL2dtV RD and CS to data–out valid
—
—
80
90
ns
ns
Extended Temp. Range
65
66
TrdH2dtI RD or CS to data–out invalid
10
—
30
ns
TibfINH
Inhibit of the IBF flag bit being cleared from
3TCY
WR or CS
1999-2013 Microchip Technology Inc.
DS39026D-page 251
PIC18CXX2
FIGURE 21-12:
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
BIT6 - - - - - -1
LSb
SDO
SDI
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
Symbol
Characteristic
Min
Max Units Conditions
No.
70
TssL2scH, SS to SCK or SCK input
TCY
—
ns
TssL2scL
71
TscH
TscL
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
ns
ns
ns
ns
71A
72
40
1.25TCY + 30
40
(Note 1)
(Note 1)
SCK input low time
(Slave mode)
72A
73
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
1.5TCY + 40
100
—
—
—
ns
ns
ns
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock edge
of Byte2
(Note 2)
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
75
TdoR
SDO data output rise time
PIC18CXXX
—
—
—
—
—
—
—
—
25
45
25
25
45
25
50
100
ns
ns
ns
ns
ns
ns
ns
ns
PIC18LCXXX
76
78
TdoF
TscR
SDO data output fall time
SCK output rise time
(Master mode)
PIC18CXXX
PIC18LCXXX
79
80
TscF
SCK output fall time (Master mode)
TscH2doV, SDO data output valid after
TscL2doV SCK edge
PIC18CXXX
PIC18LCXXX
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
DS39026D-page 252
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 21-13:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
BIT6 - - - - - -1
BIT6 - - - -1
SDO
SDI
75, 76
MSb IN
74
LSb IN
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
Symbol
TscH
TscL
Characteristic
Min
Max Units Conditions
No.
71
SCK input high time
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
ns
ns
ns
ns
(Slave mode)
71A
72
40
1.25TCY + 30
40
(Note 1)
(Note 1)
SCK input low time
(Slave mode)
72A
73
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
—
—
—
ns
ns
ns
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock edge
of Byte2
1.5TCY + 40
(Note 2)
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
75
TdoR
SDO data output rise time
PIC18CXXX
25
45
25
25
45
25
50
100
ns
ns
ns
ns
ns
ns
ns
ns
PIC18LCXXX
76
78
TdoF
TscR
SDO data output fall time
—
—
SCK output rise time
(Master mode)
PIC18CXXX
PIC18LCXXX
79
80
TscF
SCK output fall time (Master mode)
—
—
TscH2doV, SDO data output valid after
TscL2doV SCK edge
PIC18CXXX
PIC18LCXXX
81
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
TCY
—
ns
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
1999-2013 Microchip Technology Inc.
DS39026D-page 253
PIC18CXX2
FIGURE 21-14:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
LSb
SDO
SDI
BIT6 - - - - - -1
77
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0))
Param.
Symbol
Characteristic
Min
Max Units Conditions
No.
70
TssL2scH, SS to SCK or SCK input
TCY
—
ns
TssL2scL
71
TscH
TscL
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
ns
ns
ns
ns
ns
71A
72
40
1.25TCY + 30
40
(Note 1)
(Note 1)
SCK input low time
(Slave mode)
72A
73
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
73A
74
TB2B
Last clock edge of Byte1 to the first clock edge of Byte2 1.5TCY + 40
—
—
ns
ns
(Note 2)
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
75
TdoR
SDO data output rise time
PIC18CXXX
—
25
45
25
50
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC18LCXXX
76
77
78
TdoF
SDO data output fall time
—
10
—
TssH2doZ SS to SDO output hi-impedance
TscR
SCK output rise time
(Master mode)
PIC18CXXX
PIC18LCXXX
79
80
TscF
SCK output fall time (Master mode)
—
—
TscH2doV, SDO data output valid after SCK
TscL2doV edge
PIC18CXXX
PIC18LCXXX
83
TscH2ssH, SS after SCK edge
1.5TCY + 40
TscL2ssH
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
DS39026D-page 254
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 21-15:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb IN
74
LSb IN
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param.
Symbol
Characteristic
Min
Max Units Conditions
No.
70
TssL2scH, SS to SCK or SCK input
TCY
—
ns
TssL2scL
71
TscH
TscL
TB2B
SCK input high time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
71A
72
40
1.25TCY + 30
40
(Note 1)
SCK input low time
(Slave mode)
72A
73A
74
(Note 1)
(Note 2)
Last clock edge of Byte1 to the first clock edge of Byte2 1.5TCY + 40
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
75
TdoR
SDO data output rise time
PIC18CXXX
25
45
25
50
25
45
25
50
100
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC18LCXXX
76
77
78
TdoF
SDO data output fall time
—
10
—
—
—
—
—
—
—
TssH2doZ SS to SDO output hi-impedance
TscR
SCK output rise time
(Master mode)
PIC18CXXX
PIC18LCXXX
79
80
TscF
SCK output fall time (Master mode)
TscH2doV, SDO data output valid after SCK PIC18CXXX
TscL2doV edge
PIC18LCXXX
TssL2doV SDO data output valid after SS PIC18CXXX
82
83
edge
PIC18LCXXX
TscH2ssH, SS after SCK edge
TscL2ssH
1.5TCY + 40
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
1999-2013 Microchip Technology Inc.
DS39026D-page 255
PIC18CXX2
FIGURE 21-16:
I2C BUS START/STOP BITS TIMING
SCL
SDA
91
93
90
92
STOP
Condition
START
Condition
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-15: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
90
Tsu:sta START condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
ns
Only relevant for Repeated
START condition
91
92
93
Thd:sta START condition
Hold time
4000
600
ns
ns
ns
After this period the first
clock pulse is generated
Tsu:sto STOP condition
Setup time
4700
600
Thd:sto STOP condition
Hold time
4000
600
DS39026D-page 256
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 21-17:
I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
100 kHz mode
Min
Max
Units
Conditions
100
THIGH
Clock high time
4.0
—
s
PIC18CXXX must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
s
PIC18CXXX must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
4.7
—
—
101
TLOW
Clock low time
100 kHz mode
s
s
PIC18CXXX must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
PIC18CXXX must operate at a
minimum of 10 MHz
SSP Module
100 kHz mode
400 kHz mode
1.5TCY
—
—
102
103
TR
TF
SDA and SCL rise
time
1000
300
ns
ns
20 + 0.1CB
CB is specified to be from
10 to 400 pF
SDA and SCL fall time 100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1CB
CB is specified to be from
10 to 400 pF
90
TSU:STA
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TAA
START condition
setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
s
s
s
s
ns
s
ns
ns
s
s
ns
ns
s
s
pF
Only relevant for Repeated
START condition
91
START condition hold
time
—
After this period the first clock
pulse is generated
—
106
107
92
Data input hold time
—
0
0.9
—
Data input setup time
250
100
4.7
0.6
—
(Note 2)
—
STOP condition setup
time
—
—
109
110
D102
Output valid from
clock
3500
—
(Note 1)
—
TBUF
Bus free time
4.7
1.3
—
—
Time the bus must be free before
a new transmission can start
—
CB
Bus capacitive loading
400
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2
2
2: A fast mode I C bus device can be used in a standard mode I C bus system, but the requirement TSU:DAT 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
2
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I C bus specification) before the SCL line is
released.
1999-2013 Microchip Technology Inc.
DS39026D-page 257
PIC18CXX2
FIGURE 21-18:
MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS
SCL
SDA
93
91
90
92
STOP
Condition
START
Condition
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-17: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
90
TSU:STA START condition
Setup time
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
100 kHz mode 2(TOSC)(BRG + 1)
400 kHz mode 2(TOSC)(BRG + 1)
1 MHz mode(1) 2(TOSC)(BRG + 1)
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for
Repeated START
condition
91
92
93
THD:STA START condition
Hold time
ns After this period the
first clock pulse is
generated
TSU:STO STOP condition
Setup time
ns
THD:STO STOP condition
Hold time
ns
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
DS39026D-page 258
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 21-19:
MASTER SSP I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-18: MASTER SSP I2C BUS DATA REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
100
THIGH
Clock high time 100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
ms
ms
1 MHz mode(1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ms
ms
ms
101
102
103
90
TLOW
TR
Clock low time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
—
—
1000
300
ms
ns
ns
SDA and SCL
rise time
CB is specified to be
from 10 to 400 pF
20 + 0.1CB
1 MHz mode(1)
100 kHz mode
400 kHz mode
—
—
300
300
300
ns
ns
ns
TF
SDA and SCL
fall time
CB is specified to be
from 10 to 400 pF
20 + 0.1CB
1 MHz mode(1)
—
100
—
—
ns
TSU:STA
THD:STA
START condition 100 kHz mode
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
ms Only relevant for
ms Repeated START
setup time
400 kHz mode
1 MHz mode(1)
condition
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ms
91
START condition 100 kHz mode
ms After this period the
ms first clock pulse is
hold time
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
2(TOSC)(BRG + 1)
—
—
0.9
generated
ms
ns
ms
106
107
92
THD:DAT Data input
hold time
0
0
1 MHz mode(1)
100 kHz mode
400 kHz mode
TBD
250
100
—
—
—
ns
ns
ns
TSU:DAT
TSU:STO
TAA
Data input
setup time
(Note 2)
1 MHz mode(1)
TBD
2(TOSC)(BRG + 1)
2(TOSC)(BRG + 1)
—
—
—
ns
ms
ms
STOP condition 100 kHz mode
setup time
400 kHz mode
1 MHz mode(1)
2(TOSC)(BRG + 1)
—
3500
1000
ms
ns
ns
109
110
Output valid from 100 kHz mode
—
—
clock
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
—
4.7
1.3
—
—
—
ns
TBUF
Bus free time
ms Time the bus must be
ms free before a new
1 MHz mode(1)
Bus capacitive loading
TBD
—
—
400
ms
pF
transmission can start
D102 CB
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to
the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL
line is released.
1999-2013 Microchip Technology Inc.
DS39026D-page 259
PIC18CXX2
FIGURE 21-20:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note: Refer to Figure 21-4 for load conditions.
122
TABLE 21-19: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units Conditions
No.
120
TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid
PIC18CXXX
PIC18LCXXX
PIC18CXXX
PIC18LCXXX
PIC18CXXX
PIC18LCXXX
—
—
—
—
—
—
40
100
25
ns
ns
ns
ns
ns
ns
121
122
Tckrf
Tdtrf
Clock out rise time and fall time
(Master mode)
50
Data out rise time and fall time
25
50
FIGURE 21-21:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note: Refer to Figure 21-4 for load conditions.
TABLE 21-20: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max
Units
Conditions
No.
125
TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data hold before CK (DT hold time)
Data hold after CK (DT hold time)
10
15
—
—
ns
ns
126
TckL2dtl
DS39026D-page 260
1999-2013 Microchip Technology Inc.
PIC18CXX2
TABLE 21-21: A/D CONVERTER CHARACTERISTICS: PIC18CXX2 (INDUSTRIAL, EXTENDED)
PIC18LCXX2 (INDUSTRIAL)
Param
No.
Symbol
Characteristic
Resolution
Min
Typ
Max
Units
Conditions
A01
NR
—
—
—
—
10
10
bit VREF = VDD 3.0V
bit VREF = VDD 3.0V
A03
A04
A05
A06
EIL
Integral linearity error
Differential linearity error
Full scale error
—
—
—
—
<±1
<±2
LSb VREF = VDD 3.0V
LSb VREF = VDD 3.0V
EDL
EFS
EOFF
—
—
—
—
<±1
<±2
LSb VREF = VDD 3.0V
LSb VREF = VDD 3.0V
—
—
—
—
<±1
<±1
LSb VREF = VDD 3.0V
LSb VREF = VDD 3.0V
Offset error
—
—
—
—
<±1
<±1
LSb VREF = VDD 3.0V
LSb VREF = VDD 3.0V
A10
A20
A20A
A21
A22
—
Monotonicity
guaranteed(3)
—
V
V
V
V
VSS VAIN VREF
VREF
Reference voltage
(VREFH - VREFL)
0V
3V
—
—
—
—
For 10-bit resolution
VREFH Reference voltage High
AVSS
—
—
AVDD + 0.3V
AVDD
VREFL
VAIN
ZAIN
IAD
Reference voltage Low
AVSS -
0.3V
A25
A30
A40
Analog input voltage
AVSS -
0.3V
—
—
VREF + 0.3V
10.0
V
Recommended impedance of
analog voltage source
—
k
A/D conversion PIC18CXXX
current (VDD)
—
—
180
90
—
—
A Average current
consumption when
A/D is on (Note 1).
PIC18LCXXX
A
A50
IREF
VREF input current (Note 2)
10
—
1000
A During VAIN acquisition.
Based on differential of
VHOLD to VAIN. To charge
CHOLD, see Section 16.0.
A During A/D conversion
cycle.
—
—
10
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or AVDD and AVSS pins, whichever is
selected as reference input.
2: VSS VAIN VREF
3: The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes.
1999-2013 Microchip Technology Inc.
DS39026D-page 261
PIC18CXX2
FIGURE 21-22:
A/D CONVERSION TIMING
BSF ADCON0, GO
Note 2
131
130
Q4
132
A/D CLK
. . .
. . .
9
8
7
2
1
0
A/D DATA
ADRES
NEW_DATA
TCY
OLD_DATA
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEPinstruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 21-22: A/D CONVERSION REQUIREMENTS
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
130
TAD
A/D clock period
PIC18CXXX
1.6
20(5)
s TOSC based, VREF 3.0V
PIC18LCXXX
PIC18CXXX
PIC18LCXXX
3.0
2.0
3.0
11
20(5)
6.0
9.0
12
s TOSC based, VREF full range
s A/D RC mode
s A/D RC mode
TAD
131
132
TCNV
TACQ
Conversion time
(not including acquisition time) (Note 1)
Acquisition time (Note 3)
15
10
—
—
s -40C Temp 125C
s
0C Temp 125C
135
136
TSWC
TAMP
Switching Time from convert sample
Amplifier settling time (Note 2)
—
1
(Note 4)
—
s This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from
the last sampled voltage (as
stated on CHOLD).
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 16.0 for minimum conditions, when input voltage has changed more than 1 LSb.
3: The time for the holding capacitor to acquire the “New” input voltage, when the voltage changes full scale
after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is
50 .
4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
DS39026D-page 262
1999-2013 Microchip Technology Inc.
PIC18CXX2
22.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. 'Typical' represents the mean of the distribution at 25C. 'Max' or 'min' represents
(mean + 3) or (mean - 3) respectively, where is standard deviation, over the whole temperature range.
FIGURE 22-1:
TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
16
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
14
12
10
8
5.5V
5.0V
4.5V
4.0V
3.5V
6
3.2V
4
3.0V
2.7V
2
2.5V
0
4
6
8
10
12
14
16
18
20
22
24
26
FOSC (MHz)
FIGURE 22-2:
MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
16
5.5V
Typical: statistical mean @ 25°C
14
12
10
8
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
5.0V
4.5V
4.0V
3.5V
3.2V
6
3.0V
4
2.7V
2
2.5V
0
4
6
8
10
12
14
16
18
20
22
24
26
FOSC (MHz)
1999-2013 Microchip Technology Inc.
DS39026D-page 263
PIC18CXX2
FIGURE 22-3:
TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE)
25
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
20
15
10
5
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
0
4
5
6
7
8
9
10
F
(MHz)
OSC
FIGURE 22-4:
MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE)
25
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
20
15
10
5
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
0
4
5
6
7
8
9
10
F
(MHz)
OSC
DS39026D-page 264
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 22-5:
TYPICAL IDD vs. FOSC OVER VDD (XT MODE)
1.0
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
0.8
0.6
0.4
0.2
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
FIGURE 22-6:
MAXIMUM IDD vs. FOSC OVER VDD (XT MODE)
2.5
5.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
2.0
1.5
1.0
0.5
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
FOSC (MHz)
1999-2013 Microchip Technology Inc.
DS39026D-page 265
PIC18CXX2
FIGURE 22-7:
TYPICAL IDD vs. FOSC OVER VDD (LP MODE)
200
180
160
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
140
120
100
80
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
60
40
20
0
20
30
40
50
60
70
80
90
100
FOSC (kHz)
FIGURE 22-8:
MAXIMUM IDD vs. FOSC OVER VDD (LP MODE)
300
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
250
200
5.5V
5.0V
150
4.5V
4.0V
100
3.5V
3.0V
50
2.5V
0
20
30
40
50
60
(kHz)
70
80
90
100
F
OSC
DS39026D-page 266
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 22-9:
TYPICAL AND MAXIMUM IDD vs. VDD
(TIMER1 AS MAIN OSCILLATOR, 32.768 kHz, C = 47 pF)
300
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
250
200
150
100
50
Max (-40C)
Typ (25C)
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 22-10:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 20 pF, 25C)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
3.3k
5.1k
10k
100k
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
1999-2013 Microchip Technology Inc.
DS39026D-page 267
PIC18CXX2
FIGURE 22-11:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 100 pF, 25C)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
3.3k
5.1k
10k
100k
0.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
DD
FIGURE 22-12:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 300 pF, 25C)
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
3.3k
5.1k
10k
100k
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS39026D-page 268
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 22-13:
IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
100.00
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
Max (125C)
Max (85C)
10.00
1.00
0.10
Typ (25C)
0.01
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 22-14:
IBOR vs. VDD OVER TEMPERATURE (BOR ENABLED, VBOR = 2.50V - 2.66V)
150
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
125
100
75
Maximum RESET current - example only
(Depends on osc mode, osc freq, temp, V
)
DD
Device in SLEEP
Indeterminate State
(May be in RESET or SLEEP
50
25
0
MAX
(-40C to 125C)
I
BOR
Typ IBOR
(25C)
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
1999-2013 Microchip Technology Inc.
DS39026D-page 269
PIC18CXX2
FIGURE 22-15:
TYPICAL AND MAXIMUMITMR1 vs. VDD OVER TEMPERATURE
(-40C TO +125C, TIMER1 WITH OSCILLATOR, XTAL=32 kHZ, C1 AND C2 = 47 pF)
90
80
70
60
50
40
30
20
10
Max (-40C to 125C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
Typ (25C)
0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
DD
FIGURE 22-16:
TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE
(WDT ENABLED)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
Maximum (-40C)
Typical (25C)
0.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
DD
DS39026D-page 270
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 22-17:
TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40C TO +125C)
60
Typical: statistical mean @ 25°C
50
40
30
20
10
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
Max (125C)
Typ (25C)
Min (-40C)
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 22-18:
ILVD vs. VDD OVER TEMPERATURE (LVD ENABLED, VLVD = 3.0V - 3.2V)
50
45
Max
(-40C to 125C)
40
35
30
25
20
15
10
5
Max (-40C to 125C)
Typ (25C)
Typ (25C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
LVDIF is
unknown
LVDIF can
be cleared
by firmware
LVDIF is set
by hardware
0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
DD
1999-2013 Microchip Technology Inc.
DS39026D-page 271
PIC18CXX2
FIGURE 22-19:
ILVD vs. VDD OVER TEMPERATURE (LVD ENABLED, VLVD = 4.5V - 4.78V)
45
40
35
30
25
20
15
10
5
Max (125C)
Typ (25C)
Max (125C)
Typ (25C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
LVDIF is
unknown
LVDIF can
be cleared
by firmware
LVDIF is set
by hardware
0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
DD
FIGURE 22-20:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C)
5.0
4.5
4.0
3.5
3.0
2.5
2.0
Max
(-40C)
Typ
(25C)
Min
(125C)
Typical: statistical mean @ 25°C
1.5
1.0
0.5
0.0
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
0
5
10
15
20
25
IOH (-mA)
DS39026D-page 272
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 22-21:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C)
3.0
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
2.5
2.0
1.5
1.0
0.5
Max (-40C)
Typ (25C)
Min (125C)
0.0
0
5
10
15
20
25
IOH (-mA)
FIGURE 22-22:
TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C)
1.4
1.2
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
1.0
0.8
0.6
0.4
0.2
0.0
Max (-40C to 125C)
Typ (25C)
0
5
10
15
20
25
IOL (mA)
1999-2013 Microchip Technology Inc.
DS39026D-page 273
PIC18CXX2
FIGURE 22-23:
TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C)
2.4
2.2
2.0
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Max (-40C to 125C)
Typ (25C)
0
5
10
15
20
25
I
(mA)
OL
FIGURE 22-24:
MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C)
4.0
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VIH Max (125C)
VIH Min (-40C)
VIL Max (-40C)
VIL Min (125C)
0.0
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
DD
DS39026D-page 274
1999-2013 Microchip Technology Inc.
PIC18CXX2
FIGURE 22-25:
MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40C TO +125C)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
Max VTH (-40C)
Min VTH (125C)
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 22-26:
MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40C TO +125C)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Min VIH (-40C)
Max VIH (125C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
Min VIL (-40C)
Max VIL (125C)
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
1999-2013 Microchip Technology Inc.
DS39026D-page 275
PIC18CXX2
NOTES:
DS39026D-page 276
1999-2013 Microchip Technology Inc.
PIC18CXX2
23.0 PACKAGING INFORMATION
23.1 Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC18C242-I/SP
0117017
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
PIC18C242-E/SO
0110017
YYWWNNN
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
1999-2013 Microchip Technology Inc.
DS39026D-page 277
PIC18CXX2
Package Marking Information (Cont’d)
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
PIC18C442-I/P
0112017
Example
28- and 40-Lead JW (CERDIP)
PIC18C452
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
-I/JW
0115017
44-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18C442
-E/PT
0120017
44-Lead PLCC
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18C452
-I/L
0120017
DS39026D-page 278
1999-2013 Microchip Technology Inc.
PIC18CXX2
23.2 Package Details
The following sections give the technical details of the
packages.
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
D
2
n
1
E
A2
L
A
c
B1
A1
eB
B
p
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.100
.150
.130
2.54
3.81
3.30
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
A2
A1
E
.140
.160
3.56
4.06
.125
.015
.300
.275
1.345
.125
.008
.040
.016
.320
.135
3.18
0.38
7.62
6.99
34.16
3.18
0.20
1.02
3.43
.310
.285
1.365
.130
.012
.053
.019
.350
10
.325
.295
1.385
.135
.015
.065
.022
.430
15
7.87
7.24
8.26
7.49
35.18
3.43
0.38
1.65
0.56
10.92
15
E1
D
34.67
3.30
0.29
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
1.33
Lower Lead Width
0.41
8.13
5
0.48
8.89
10
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
5
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
1999-2013 Microchip Technology Inc.
DS39026D-page 279
PIC18CXX2
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
p
D
B
2
n
1
h
45
c
A2
A
L
A1
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
28
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
1.27
2.50
2.31
0.20
10.34
7.49
17.87
0.50
0.84
4
Overall Height
A
.093
.104
2.36
2.64
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.288
.695
.010
.016
0
.094
.012
.420
.299
.712
.029
.050
8
2.24
0.10
10.01
7.32
17.65
0.25
0.41
0
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
Foot Angle Top
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
DS39026D-page 280
1999-2013 Microchip Technology Inc.
PIC18CXX2
40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
D
2
1
n
E
A2
A
L
c
B1
B
A1
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
40
MAX
n
p
Number of Pins
Pitch
40
.100
.175
.150
2.54
Top to Seating Plane
A
.160
.190
.160
4.06
3.56
4.45
3.81
4.83
4.06
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.140
.015
.595
.530
2.045
.120
.008
.030
.014
.620
5
0.38
15.11
13.46
51.94
3.05
0.20
0.76
0.36
15.75
5
.600
.545
2.058
.130
.012
.050
.018
.650
10
.625
.560
2.065
.135
.015
.070
.022
.680
15
15.24
13.84
52.26
3.30
0.29
1.27
0.46
16.51
10
15.88
14.22
52.45
3.43
0.38
1.78
0.56
17.27
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
§
eB
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
5
10
15
5
10
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
1999-2013 Microchip Technology Inc.
DS39026D-page 281
PIC18CXX2
28-Lead Ceramic Dual In-line with Window (JW) – 600 mil (CERDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
W
D
2
n
1
E
A2
A
L
c
B1
eB
A1
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.100
.210
.160
.038
.600
.520
1.460
.138
.010
.058
.020
.660
.280
2.54
Top to Seating Plane
Ceramic Package Height
Standoff
A
.195
.225
.165
.060
.625
.526
1.490
.150
.012
.065
.023
.710
.290
4.95
3.94
5.33
4.06
5.72
A2
A1
.155
.015
.595
.514
1.430
.125
.008
.050
.016
.610
.270
4.19
1.52
0.38
15.11
13.06
36.32
3.18
0.95
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
E
E1
D
L
15.24
13.21
37.08
3.49
15.88
13.36
37.85
3.81
Tip to Seating Plane
Lead Thickness
c
0.20
0.25
0.30
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Diameter
B1
B
1.27
1.46
1.65
0.41
0.51
0.58
§
eB
W
15.49
6.86
16.76
7.11
18.03
7.37
* Controlling Parameter
§ Significant Characteristic
JEDEC Equivalent: MO-103
Drawing No. C04-013
DS39026D-page 282
1999-2013 Microchip Technology Inc.
PIC18CXX2
40-Lead Ceramic Dual In-line with Window (JW) – 600 mil (CERDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
W
D
2
n
1
E
A2
A
A1
c
B1
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
40
MAX
n
p
Number of Pins
Pitch
40
.100
.205
.160
.045
.600
.520
2.050
.140
.011
.053
.020
.660
.350
2.54
Top to Seating Plane
Ceramic Package Height
Standoff
A
.185
.225
4.70
3.94
5.21
4.06
5.72
4.19
A2
A1
.155
.030
.595
.514
2.040
.135
.008
.050
.016
.610
.340
.165
.060
.625
.526
2.060
.145
.014
.055
.023
.710
.360
0.76
15.11
13.06
51.82
3.43
1.14
1.52
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
E
E1
D
L
15.24
13.21
52.07
3.56
15.88
13.36
52.32
3.68
Tip to Seating Plane
Lead Thickness
c
0.20
0.28
0.36
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Diameter
B1
B
1.27
1.33
1.40
0.41
0.51
0.58
§
eB
W
15.49
8.64
16.76
8.89
18.03
9.14
* Controlling Parameter
§ Significant Characteristic
JEDEC Equivalent: MO-103
Drawing No. C04-014
1999-2013 Microchip Technology Inc.
DS39026D-page 283
PIC18CXX2
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
#leads=n1
p
D1
D
2
1
B
n
CH x 45
A
c
A1
A2
L
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.031
11
0.80
11
Pins per Side
Overall Height
n1
A
.039
.037
.002
.018
.043
.039
.004
.024
.039
3.5
.047
1.00
0.95
1.10
1.00
0.10
0.60
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
.041
.006
.030
1.05
0.15
0.75
§
0.05
0.45
1.00
0
Foot Length
Footprint (Reference)
Foot Angle
0
.463
.463
.390
.390
.004
.012
.025
5
7
.482
.482
.398
.398
.008
.017
.045
15
3.5
12.00
12.00
10.00
10.00
0.15
0.38
0.89
10
7
12.25
12.25
10.10
10.10
0.20
0.44
1.14
15
Overall Width
E
D
.472
.472
.394
.394
.006
.015
.035
10
11.75
11.75
9.90
9.90
0.09
0.30
0.64
5
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
DS39026D-page 284
1999-2013 Microchip Technology Inc.
PIC18CXX2
44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
#leads=n1
D
D1
n 1 2
CH2 x 45
CH1 x 45
A3
A2
A
35
B1
B
c
A1
p
E2
D2
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.050
11
1.27
11
Pins per Side
Overall Height
n1
A
.165
.145
.020
.024
.040
.000
.685
.685
.650
.650
.590
.590
.008
.026
.013
0
.173
.153
.028
.029
.045
.005
.690
.690
.653
.653
.620
.620
.011
.029
.020
5
.180
4.19
3.68
0.51
0.61
1.02
0.00
17.40
17.40
16.51
16.51
14.99
14.99
0.20
0.66
0.33
0
4.39
3.87
0.71
0.74
1.14
0.13
17.53
17.53
16.59
16.59
15.75
15.75
0.27
0.74
0.51
5
4.57
Molded Package Thickness
Standoff
A2
A1
A3
CH1
CH2
E
.160
.035
.034
.050
.010
.695
.695
.656
.656
.630
.630
.013
.032
.021
10
4.06
0.89
0.86
1.27
0.25
17.65
17.65
16.66
16.66
16.00
16.00
0.33
0.81
0.53
10
§
Side 1 Chamfer Height
Corner Chamfer 1
Corner Chamfer (others)
Overall Width
Overall Length
D
Molded Package Width
Molded Package Length
Footprint Width
E1
D1
E2
D2
c
Footprint Length
Lead Thickness
Upper Lead Width
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
B1
B
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
1999-2013 Microchip Technology Inc.
DS39026D-page 285
PIC18CXX2
NOTES:
DS39026D-page 286
1999-2013 Microchip Technology Inc.
PIC18CXX2
APPENDIX A: REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
Revision A (July 1999)
The differences between the devices listed in this data
sheet are shown in Table 1.
Original data sheet for PIC18CXX2 family.
Revision B (March 2001)
Added DC and AC characteristics graphs
(Section 22.0).
Revision C (January 2013)
Added a note to each package outline drawing.
TABLE 1:
DEVICE DIFFERENCES
Feature
PIC18C242
PIC18C252
PIC18C442
PIC18C452
Program Memory (Kbytes)
Data Memory (Bytes)
A/D Channels
16
512
5
32
1536
5
16
512
8
32
1536
8
Parallel Slave Port (PSP)
Package Types
No
No
Yes
Yes
28-pin DIP
28-pin SOIC
28-pin JW
28-pin DIP
28-pin SOIC
28-pin JW
40-pin DIP
44-pin PLCC
44-pin TQFP
40-pin JW
40-pin DIP
44-pin PLCC
44-pin TQFP
40-pin JW
1999-2013 Microchip Technology Inc.
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PIC18CXX2
APPENDIX C: CONVERSION
APPENDIX D: MIGRATION FROM
BASELINE TO
CONSIDERATIONS
ENHANCED DEVICES
This appendix discusses the considerations for con-
verting from previous versions of a device to the ones
listed in this data sheet. Typically, these changes are
due to the differences in the process technology used.
An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
This section discusses how to migrate from a Baseline
device (i.e., PIC16C5X) to an Enhanced MCU device
(i.e., PIC18CXXX).
The following are the list of modifications over the
PIC16C5X microcontroller family:
Not Applicable
Not Currently Available
DS39026D-page 288
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PIC18CXX2
APPENDIX E: MIGRATION FROM
MID-RANGE TO
APPENDIX F: MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
ENHANCED DEVICES
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18CXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442.” The changes discussed, while device
specific, are generally applicable to all mid-range to
enhanced device migrations.
A detailed discussion of the migration pathway and dif-
ferences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18CXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration.” This Application Note is avail-
able as Literature Number DS00726.
This Application Note is available as Literature Number
DS00716.
1999-2013 Microchip Technology Inc.
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PIC18CXX2
NOTES:
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PIC18CXX2
INDEX
PORTB
A
RB3 Pin ............................................................. 81
RB3:RB0 Port Pins ............................................ 81
RB7:RB4 Port Pins ............................................ 80
PORTC (Peripheral Output Override) ........................ 83
PORTD (I/O Mode) .................................................... 85
PORTE (I/O Mode) .................................................... 87
PWM Operation (Simplified) .................................... 112
SSP (SPI Mode) ...................................................... 121
Timer1 ....................................................................... 98
Timer1 (16-bit R/W Mode) ......................................... 98
Timer2 ..................................................................... 102
Timer3 ..................................................................... 104
Timer3 (16-bit R/W Mode) ....................................... 104
USART
A/D ................................................................................... 165
A/D Converter Flag (ADIF Bit) ................................. 167
A/D Converter Interrupt, Configuring ....................... 168
ADCON0 Register .................................................... 165
ADCON1 Register ............................................ 165, 166
ADRES Register .............................................. 165, 167
Analog Port Pins .................................................. 89, 90
Analog Port Pins, Configuring .................................. 170
Associated Registers ............................................... 172
Block Diagram .......................................................... 167
Block Diagram, Analog Input Model ......................... 168
Configuring the Module ............................................ 168
Conversion Clock (TAD) ........................................... 170
Conversion Status (GO/DONE Bit) .......................... 167
Conversions ............................................................. 171
Converter Characteristics ........................................ 261
Equations ................................................................. 169
Sampling Requirements ........................................... 168
Sampling Time ......................................................... 169
Special Event Trigger (CCP) ............................ 110, 171
Timing Diagram ........................................................ 262
Absolute Maximum Ratings ............................................. 235
ACKSTAT ........................................................................ 139
ADCON0 Register ............................................................ 165
GO/DONE Bit ........................................................... 167
ADCON1 Register .................................................... 165, 166
ADDLW ............................................................................ 193
ADDWF ............................................................................ 193
ADDWFC ......................................................................... 194
ADRES Register ...................................................... 165, 167
Analog-to-Digital Converter. See A/D
Asynchronous Receive .................................... 157
Asynchronous Transmit ................................... 155
Watchdog Timer ...................................................... 184
BN .................................................................................... 196
BNC ................................................................................. 197
BNOV .............................................................................. 198
BNZ ................................................................................. 198
BOR. See Brown-out Reset
BOV ................................................................................. 201
BRA ................................................................................. 199
BRG. See Baud Rate Generator
Brown-out Reset (BOR) ............................................. 26, 179
Timing Diagram ....................................................... 248
BSF .................................................................................. 199
BTFSC ............................................................................. 200
BTFSS ............................................................................. 200
BTG ................................................................................. 201
Bus Collision During a Repeated START Condition ........ 147
Bus Collision During a START Condition ........................ 145
Bus Collision During a STOP Condition .......................... 148
BZ .................................................................................... 202
ANDLW ............................................................................ 194
ANDWF ............................................................................ 195
Assembler
MPASM Assembler .................................................. 229
C
B
CALL ................................................................................ 202
Capture (CCP Module) .................................................... 109
Associated Registers ............................................... 111
Block Diagram ......................................................... 109
CCP Pin Configuration ............................................ 109
CCPR1H:CCPR1L Registers .................................. 109
Software Interrupt .................................................... 109
Timer1 Mode Selection ............................................ 109
Capture/Compare/PWM (CCP) ....................................... 107
Capture Mode. See Capture
Baud Rate Generator ....................................................... 136
BC .................................................................................... 195
BCF .................................................................................. 196
BF .................................................................................... 139
Block Diagrams
A/D Converter .......................................................... 167
Analog Input Model .................................................. 168
Baud Rate Generator ............................................... 136
Capture Mode Operation ......................................... 109
Compare Mode Operation ....................................... 110
Low Voltage Detect
CCP1 ....................................................................... 108
CCPR1H Register ........................................... 108
CCPR1L Register ............................................ 108
CCP1CON and CCP2CON Registers ..................... 107
CCP2 ....................................................................... 108
CCPR2H Register ........................................... 108
CCPR2L Register ............................................ 108
Compare Mode. See Compare
External Reference Source .............................. 174
Internal Reference Source ............................... 174
MSSP
2
I C Mode .......................................................... 128
SPI Mode ......................................................... 121
On-Chip Reset Circuit ................................................ 25
Parallel Slave Port (PORTD and PORTE) ................. 90
PORTA
Interaction of Two CCP Modules ............................. 108
PWM Mode. See PWM
RA3:RA0 and RA5 Port Pins ............................. 77
RA4/T0CKI Pin .................................................. 78
RA6 Pin .............................................................. 78
Timer Resources ..................................................... 108
Timing Diagram ....................................................... 250
Clocking Scheme ............................................................... 39
CLRF ............................................................................... 203
CLRWDT ......................................................................... 203
1999-2013 Microchip Technology Inc.
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PIC18CXX2
Code Examples
I
16 x 16 Signed Multiply Routine ................................62
16 x 16 Unsigned Multiply Routine ............................62
8 x 8 Signed Multiply Routine ....................................61
8 x 8 Unsigned Multiply Routine ................................61
Changing Between Capture Prescalers ...................109
Fast Register Stack ....................................................39
Initializing PORTA ......................................................77
Initializing PORTB ......................................................80
Initializing PORTC ......................................................83
Initializing PORTD ......................................................85
Initializing PORTE ......................................................87
Loading the SSPBUF Register ................................122
Saving STATUS, WREG and BSR Registers
I/O Ports ............................................................................. 77
I C (SSP Module) ............................................................ 128
2
ACK Pulse ....................................................... 128, 129
Addressing ............................................................... 129
Block Diagram ......................................................... 128
Read/Write Bit Information (R/W Bit) ....................... 129
Reception ................................................................ 129
Serial Clock (RC3/SCK/SCL) ................................... 129
Slave Mode .............................................................. 128
Timing Diagram, Data .............................................. 257
Timing Diagram, START/STOP Bits ........................ 256
Transmission ........................................................... 129
2
I C Master Mode Reception ............................................ 139
I C Master Mode Repeated START Condition ................ 138
I C Module
in RAM ...............................................................75
Code Protection ....................................................... 179, 186
COMF ...............................................................................204
Compare (CCP Module) ...................................................110
Associated Registers ...............................................111
Block Diagram ..........................................................110
CCP Pin Configuration .............................................110
CCPR1H:CCPR1L Registers ...................................110
Software Interrupt ....................................................110
Special Event Trigger .........................99, 105, 110, 171
Timer1 Mode Selection ............................................110
Configuration Bits .............................................................179
Context Saving During Interrupts .......................................75
Example Code ...........................................................75
Conversion Considerations ..............................................288
CPFSEQ ..........................................................................204
CPFSGT ...........................................................................205
CPFSLT ...........................................................................205
2
2
Acknowledge Sequence Timing .............................. 142
Baud Rate Generator
Block Diagram
Baud Rate Generator ...................................... 136
BRG Reset Due to SDA Collision ............................ 146
BRG Timing ............................................................. 136
Bus Collision
Acknowledge ................................................... 144
Repeated START Condition ............................ 147
Repeated START Condition Timing
(Case 1) ................................................... 147
Repeated START Condition Timing
(Case 2) ................................................... 147
START Condition ............................................. 145
START Condition Timing ......................... 145, 146
STOP Condition ............................................... 148
STOP Condition Timing (Case 1) .................... 148
STOP Condition Timing (Case 2) .................... 148
Transmit Timing ............................................... 144
Bus Collision Timing ................................................ 144
Clock Arbitration ...................................................... 143
Clock Arbitration Timing (Master Transmit) ............. 143
General Call Address Support ................................. 133
Master Mode 7-bit Reception Timing ....................... 141
Master Mode Operation ........................................... 135
Master Mode START Condition ............................... 137
Master Mode Transmission ..................................... 139
Master Mode Transmit Sequence ............................ 135
Multi-Master Mode ................................................... 144
Repeat START Condition Timing ............................ 138
STOP Condition Receive or Transmit Timing .......... 143
STOP Condition Timing ........................................... 142
Waveforms for 7-bit Reception ................................ 130
Waveforms for 7-bit Transmission ........................... 130
ICEPIC In-Circuit Emulator .............................................. 230
ID Locations ............................................................. 179, 186
INCF ................................................................................ 208
INCFSZ ............................................................................ 209
In-Circuit Serial Programming (ICSP) ...................... 179, 186
Indirect Addressing ............................................................ 51
FSR Register ............................................................. 50
INFSNZ ............................................................................ 209
Instruction Cycle ................................................................ 39
Instruction Flow/Pipelining ................................................. 40
Instruction Format ............................................................ 189
D
Data Memory ......................................................................42
General Purpose Registers ........................................42
Special Function Registers ........................................42
DAW .................................................................................206
DC Characteristics ................................................... 237, 240
DECF ...............................................................................206
DECFSNZ ........................................................................207
DECFSZ ...........................................................................207
Device Differences ...........................................................287
Direct Addressing ...............................................................51
E
Electrical Characteristics ..................................................235
Errata ...................................................................................5
F
Firmware Instructions .......................................................187
G
General Call Address Sequence ......................................133
General Call Address Support .........................................133
GOTO ...............................................................................208
DS39026D-page 292
1999-2013 Microchip Technology Inc.
PIC18CXX2
Instruction Set .................................................................. 187
ADDLW .................................................................... 193
ADDWF .................................................................... 193
ADDWFC ................................................................. 194
ANDLW .................................................................... 194
ANDWF .................................................................... 195
BC ............................................................................ 195
BCF .......................................................................... 196
BN ............................................................................ 196
BNC ......................................................................... 197
BNOV ....................................................................... 198
BNZ .......................................................................... 198
BOV ......................................................................... 201
BRA .......................................................................... 199
BSF .......................................................................... 199
BTFSC ..................................................................... 200
BTFSS ..................................................................... 200
BTG .......................................................................... 201
BZ ............................................................................ 202
CALL ........................................................................ 202
CLRF ........................................................................ 203
CLRWDT .................................................................. 203
COMF ...................................................................... 204
CPFSEQ .................................................................. 204
CPFSGT .................................................................. 205
CPFSLT ................................................................... 205
DAW ......................................................................... 206
DECF ....................................................................... 206
DECFSNZ ................................................................ 207
DECFSZ ................................................................... 207
GOTO ...................................................................... 208
INCF ......................................................................... 208
INCFSZ .................................................................... 209
INFSNZ .................................................................... 209
IORLW ..................................................................... 210
IORWF ..................................................................... 210
LFSR ........................................................................ 211
MOVF ....................................................................... 211
MOVFF .................................................................... 212
MOVLB .................................................................... 212
MOVLW ................................................................... 213
MOVWF ................................................................... 213
MULLW .................................................................... 214
MULWF .................................................................... 214
NEGF ....................................................................... 215
NOP ......................................................................... 215
RCALL ..................................................................... 217
RESET ..................................................................... 217
RETFIE .................................................................... 218
RETLW .................................................................... 218
RETURN .................................................................. 219
RLCF ........................................................................ 219
RLNCF ..................................................................... 220
RRCF ....................................................................... 220
RRNCF .................................................................... 221
SETF ........................................................................ 221
SLEEP ..................................................................... 222
SUBFWB .................................................................. 222
SUBLW .................................................................... 223
SUBWF .................................................................... 223
SUBWFB .................................................................. 224
SWAPF .................................................................... 224
TBLRD ..................................................................... 225
TBLWT ..................................................................... 226
TSTFSZ ................................................................... 227
XORLW ................................................................... 227
XORWF ................................................................... 228
Summary Table ....................................................... 190
INT Interrupt (RB0/INT). See Interrupt Sources
INTCON Register
RBIF Bit ..................................................................... 80
INTCON Registers ............................................................. 65
2
Inter-Integrated Circuit. See I C
Internal Program Memory
Read/Writes ............................................................... 57
Interrupt Sources ....................................................... 63, 179
A/D Conversion Complete ....................................... 168
Capture Complete (CCP) ........................................ 109
Compare Complete (CCP) ...................................... 110
INT0 ........................................................................... 75
Interrupt-on-Change (RB7:RB4 ) ............................... 80
PORTB, on Change ................................................... 75
RB0/INT Pin, External ............................................... 75
SSP Receive/Transmit Complete ............................ 115
TMR0 ......................................................................... 75
TMR0 Overflow .......................................................... 95
TMR1 Overflow .................................... 97, 99, 103, 105
TMR2 to PR2 Match ................................................ 102
TMR2 to PR2 Match (PWM) ............................ 101, 112
USART Receive/Transmit Complete ....................... 149
Interrupts, Enable Bits
CCP1 Enable (CCP1IE Bit) ..................................... 109
Interrupts, Flag Bits
A/D Converter Flag (ADIF Bit) ................................. 167
CCP1 Flag (CCP1IF Bit) .................................. 109, 110
Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ....... 80
IORLW ............................................................................. 210
IORWF ............................................................................. 210
IPR Registers ..................................................................... 72
K
KEELOQ Evaluation and Programming Tools ................... 232
L
LFSR ............................................................................... 211
Long Write
and Interrupts ............................................................ 59
Operation ................................................................... 58
Sequence of Events .................................................. 58
Unexpected Termination ........................................... 59
Low Voltage Detect ......................................................... 173
Block Diagrams
External Reference Source ............................. 174
Internal Reference Source ............................... 174
Converter Characteristics ........................................ 242
Effects of a RESET .................................................. 177
Operation ................................................................. 176
Current Consumption ...................................... 177
During SLEEP ................................................. 177
Reference Voltage Set Point ........................... 177
LVD. See Low Voltage Detect.
1999-2013 Microchip Technology Inc.
DS39026D-page 293
PIC18CXX2
PICSTART Plus Entry Level Development System ......... 231
PIE Registers ..................................................................... 70
Pin Functions
M
Master Synchronous Serial Port (MSSP). See SSP.
Memory Organization
MCLR/VPP ........................................................... 10, 13
OSC1/CLKIN ....................................................... 10, 13
OSC2/CLKOUT ................................................... 10, 13
RA0/AN0 .............................................................. 10, 13
RA1/AN1 .............................................................. 10, 13
RA2/AN2 .............................................................. 10, 13
RA3/AN3/VREF ..................................................... 10, 13
RA4/T0CKI .......................................................... 10, 13
RA5/AN4/SS ........................................................ 10, 13
RB0/INT ............................................................... 11, 14
RB1 ...................................................................... 11, 14
RB2 ...................................................................... 11, 14
RB3 ...................................................................... 11, 14
RB4 ...................................................................... 11, 14
RB5 ...................................................................... 11, 14
RB6 ...................................................................... 11, 14
RB7 ...................................................................... 11, 14
RC0/T1OSO/T1CKI ............................................. 12, 15
RC1/T1OSI/CCP2 ................................................ 12, 15
RC2/CCP1 ........................................................... 12, 15
RC3/SCK/SCL ..................................................... 12, 15
RC4/SDI/SDA ...................................................... 12, 15
RC5/SDO ............................................................. 12, 15
RC6/TX/CK .......................................................... 12, 15
RC7/RX/DT .......................................................... 12, 15
RD0/PSP0 ................................................................. 16
RD1/PSP1 ................................................................. 16
RD2/PSP2 ................................................................. 16
RD3/PSP3 ................................................................. 16
RD4/PSP4 ................................................................. 16
RD5/PSP5 ................................................................. 16
RD6/PSP6 ................................................................. 16
RD7/PSP7 ................................................................. 16
RE0/RD/AN5 .............................................................. 16
RE1/WR/AN6 ............................................................. 16
RE2/CS/AN7 .............................................................. 16
VDD ...................................................................... 12, 16
VSS ...................................................................... 12, 16
PIR Registers ..................................................................... 68
Pointer, FSR ...................................................................... 50
POR. See Power-on Reset.
Data Memory .............................................................42
Program Memory .......................................................35
Migration from Baseline to Enhanced Devices ................288
MOVF ...............................................................................211
MOVFF .............................................................................212
MOVLB .............................................................................212
MOVLW ............................................................................213
MOVWF ...........................................................................213
MPLAB C17 and MPLAB C18 C Compilers .....................229
MPLAB ICD In-Circuit Debugger ......................................231
MPLAB ICE High Performance Universal
In-Circuit Emulator with MPLAB IDE ........................230
MPLAB Integrated Development
Environment Software ..............................................229
MPLINK Object Linker/MPLIB Object Librarian ...............230
MULLW ............................................................................214
Multi-Master Mode ...........................................................144
MULWF ............................................................................214
N
NEGF ...............................................................................215
NOP .................................................................................215
O
On-Chip Reset Circuit
Block Diagram ............................................................25
OPCODE Field Descriptions ............................................188
OPTION_REG Register
PS2:PS0 Bits .............................................................95
PSA Bit .......................................................................95
T0CS Bit .....................................................................95
T0SE Bit .....................................................................95
Oscillator Configuration ....................................................179
Oscillator Configurations ....................................................17
HS ..............................................................................17
HS + PLL ....................................................................17
LP ...............................................................................17
RC ........................................................................ 17, 18
RCIO ..........................................................................17
XT ..............................................................................17
Oscillator, Timer1 .........................................97, 99, 103, 105
Oscillator, WDT ................................................................183
PORTA
Associated Registers ................................................. 79
Initialization ................................................................ 77
PORTA Register ........................................................ 77
RA3:RA0 and RA5 Port Pins ..................................... 77
RA4/T0CKI Pin .......................................................... 78
RA6 Pin ..................................................................... 78
TRISA Register .......................................................... 77
PORTB
P
Packaging ........................................................................277
Parallel Slave Port (PSP) .............................................85, 90
Associated Registers .................................................91
Block Diagram ............................................................90
RE0/RD/AN5 Pin .................................................. 89, 90
RE1/WR/AN6 Pin ................................................. 89, 90
RE2/CS/AN7 Pin .................................................. 89, 90
Read Waveforms .......................................................91
Select (PSPMODE Bit) ........................................ 85, 90
Timing Diagram ........................................................251
Write Waveforms .......................................................90
PICDEM 1 Low Cost PIC MCU
Associated Registers ................................................. 82
Initialization ................................................................ 80
PORTB Register ........................................................ 80
RB0/INT Pin, External ................................................ 75
RB3 Pin ..................................................................... 81
RB3:RB0 Port Pins .................................................... 81
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) .......... 80
RB7:RB4 Port Pins .................................................... 80
TRISB Register .......................................................... 80
Demonstration Board ...............................................231
PICDEM 17 Demonstration Board ...................................232
PICDEM 2 Low Cost PIC16CXX
Demonstration Board ...............................................231
PICDEM 3 Low Cost PIC16CXXX
Demonstration Board ...............................................232
DS39026D-page 294
1999-2013 Microchip Technology Inc.
PIC18CXX2
PORTC
Associated Registers ................................................. 84
Q
Q Clock ............................................................................ 112
Block Diagram (Peripheral Output Override) ............. 83
Initialization .......................................................... 83, 85
PORTC Register ........................................................ 83
RC3/SCK/SCL Pin ................................................... 129
RC7/RX/DT Pin ........................................................ 151
TRISC Register .................................................. 83, 149
PORTD .............................................................................. 90
Associated Registers ................................................. 86
Block Diagram (I/O Mode) ......................................... 85
Parallel Slave Port (PSP) Function ............................ 85
PORTD Register ........................................................ 85
TRISD Register .......................................................... 85
PORTE
Analog Port Pins .................................................. 89, 90
Associated Registers ................................................. 89
Block Diagram (I/O Mode) ......................................... 87
Initialization ................................................................ 87
PORTE Register ........................................................ 87
PSP Mode Select (PSPMODE Bit) ...................... 85, 90
RE0/RD/AN5 Pin .................................................. 89, 90
RE1/WR/AN6 Pin ................................................. 89, 90
RE2/CS/AN7 Pin .................................................. 89, 90
TRISE Register .................................................... 87, 88
Postscaler, WDT
R
RAM. See Data Memory.
RCALL ............................................................................. 217
RCON Register ............................................................ 53, 56
RCSTA Register
SPEN Bit .................................................................. 149
Register File ....................................................................... 42
Registers
ADCON0 (A/D Control 0) ......................................... 165
ADCON1 (A/D Control 1) ......................................... 166
CCP1CON and CCP2CON
(Capture/Compare/PWM Control) ................... 107
CONFIG1H (Configuration 1 High) .......................... 180
CONFIG1L (Configuration 1 Low) ........................... 180
CONFIG2H (Configuration 2 High) .......................... 181
CONFIG2L (Configuration 2 Low) ........................... 181
CONFIG3H (Configuration 3 High) .......................... 182
CONFIG4L (Configuration 4 Low) ........................... 182
Flag ...................................................................... 68, 69
INTCON (Interrupt Control) ....................................... 65
INTCON2 (Interrupt Control 2) .................................. 66
INTCON3 (Interrupt Control 3) .................................. 67
IPR1 (Peripheral Interrupt Priority 1) ......................... 72
IPR2 (Peripheral Interrupt Priority 2) ......................... 73
LVDCON (LVD Control) ........................................... 175
PIE2 (Peripheral Interrupt Enable 1) ......................... 70
PIE2 (Peripheral Interrupt Enable 2) ......................... 71
PIR1 (Peripheral Interrupt Request 1) ....................... 68
PIR2 (Peripheral Interrupt Request 2) ....................... 69
RCON (Register Control) ........................................... 74
RCON (RESET Control) ...................................... 53, 56
RCSTA (Receive Status and Control) ..................... 150
SSPCON1 (SSP Control 1) ..................................... 118
SSPCON2 (SSP Control 2) ..................................... 120
SSPSTAT (SSP Status) .......................................... 116
STATUS .................................................................... 52
STKPTR (Stack Pointer) ............................................ 38
Summary ................................................................... 46
T0CON (Timer0 Control) ........................................... 93
T1CON (Timer1 Control) ........................................... 97
T2CON (Timer2 Control) ......................................... 101
T3CON (Timer3 Control) ......................................... 103
TRISE ........................................................................ 88
TXSTA (Transmit Status and Control) ..................... 149
RESET ............................................................... 25, 179, 217
Timing Diagram ....................................................... 248
RETFIE ............................................................................ 218
RETLW ............................................................................ 218
RETURN .......................................................................... 219
Revision History ............................................................... 287
RLCF ............................................................................... 219
RLNCF ............................................................................. 220
RRCF ............................................................................... 220
RRNCF ............................................................................ 221
Assignment (PSA Bit) ................................................ 95
Rate Select (PS2:PS0 Bits) ....................................... 95
Switching Between Timer0 and WDT ........................ 95
Power-down Mode. See SLEEP.
Power-on Reset (POR) .............................................. 26, 179
Oscillator Start-up Timer (OST) ......................... 26, 179
Power-up Timer (PWRT) ................................... 26, 179
Time-out Sequence .................................................... 26
Time-out Sequence on Power-up ........................ 32, 33
Timing Diagram ........................................................ 248
Prescaler, Capture ........................................................... 109
Prescaler, Timer0 ............................................................... 95
Assignment (PSA Bit) ................................................ 95
Rate Select (PS2:PS0 Bits) ....................................... 95
Switching Between Timer0 and WDT ........................ 95
Prescaler, Timer1 ............................................................... 98
Prescaler, Timer2 ............................................................. 112
PRO MATE II Universal Programmer .............................. 231
Product Identification System .......................................... 301
Program Counter
PCL Register .............................................................. 39
PCLATH Register ...................................................... 39
Program Memory ............................................................... 35
Interrupt Vector .......................................................... 35
RESET Vector ............................................................ 35
Program Verification ........................................................ 186
Programming, Device Instructions ................................... 187
PSP.See Parallel Slave Port.
Pulse Width Modulation. See PWM (CCP Module).
PWM (CCP Module) ........................................................ 112
Associated Registers ............................................... 113
Block Diagram .......................................................... 112
CCPR1H:CCPR1L Registers ................................... 112
Duty Cycle ................................................................ 112
Example Frequencies/Resolutions .......................... 113
Output Diagram ........................................................ 112
Period ....................................................................... 112
Setup for PWM Operation ........................................ 113
TMR2 to PR2 Match ........................................ 101, 112
1999-2013 Microchip Technology Inc.
DS39026D-page 295
PIC18CXX2
S
T
SCI. See USART.
TABLAT Register ............................................................... 57
Table Pointer Operations (Table) ...................................... 57
Table Read Operation, Diagram ........................................ 55
Table Write Operation, Diagram ........................................ 55
TBLPTR Register ............................................................... 57
TBLRD ............................................................................. 225
TBLWT ............................................................................. 226
Timer0 ................................................................................ 93
Clock Source Edge Select (T0SE Bit) ....................... 95
Clock Source Select (T0CS Bit) ................................. 95
Overflow Interrupt ...................................................... 95
Prescaler. See Prescaler, Timer0
T0CON Register ........................................................ 93
Timing Diagram ....................................................... 249
Timer1 ................................................................................ 97
Block Diagram ........................................................... 98
Block Diagram (16-bit R/W Mode) ............................. 98
Oscillator .............................................. 97, 99, 103, 105
Overflow Interrupt ................................ 97, 99, 103, 105
Prescaler. .................................................................. 98
Special Event Trigger (CCP) ..................... 99, 105, 110
T1CON Register ........................................................ 97
Timing Diagram ....................................................... 249
TMR1H Register ................................................ 97, 103
TMR1L Register ................................................. 97, 103
Timer2 .............................................................................. 101
Associated Registers ............................................... 102
Block Diagram ......................................................... 102
Postscaler. See Postscaler, Timer2.
SCK ..................................................................................121
SDI ...................................................................................121
SDO .................................................................................121
Serial Clock, SCK .............................................................121
Serial Communication Interface. See USART
Serial Data In, SDI ...........................................................121
Serial Data Out, SDO .......................................................121
Serial Peripheral Interface. See SPI
SETF ................................................................................221
Slave Select Synchronization ...........................................125
Slave Select, SS ..............................................................121
SLEEP ..............................................................179, 185, 222
Software Simulator (MPLAB SIM) ....................................230
Special Event Trigger. See Compare
Special Features of the CPU ............................................179
Configuration Registers ................................... 180–182
Special Function Registers ................................................42
Map ............................................................................45
SPI
Master Mode ............................................................124
Serial Clock ..............................................................121
Serial Data In ...........................................................121
Serial Data Out ........................................................121
Slave Select .............................................................121
SPI Clock .................................................................124
SPI Mode .................................................................121
SPI Master/Slave Connection ..........................................123
SPI Module
Master/Slave Connection .........................................123
Slave Mode ..............................................................125
Slave Select Synchronization ..................................125
Slave Synch Timing .................................................125
Slave Timing with CKE = 0 ......................................126
Slave Timing with CKE = 1 ......................................126
SS ....................................................................................121
SSP ..................................................................................115
Block Diagram (SPI Mode) ......................................121
PR2 Register ................................................... 101, 112
Prescaler. See Prescaler, Timer2.
SSP Clock Shift ............................................... 101, 102
T2CON Register ...................................................... 101
TMR2 Register ......................................................... 101
TMR2 to PR2 Match Interrupt .................. 101, 102, 112
Timer3 .............................................................................. 103
Associated Registers ............................................... 105
Block Diagram ......................................................... 104
Block Diagram (16-bit R/W Mode) ........................... 104
T3CON Register ...................................................... 103
Timing Diagrams
2
2
I C Mode. See I C.
SPI Mode .................................................................121
Associated Registers .......................................127
Block Diagram ..................................................121
SPI Mode. See SPI.
SSPBUF ...................................................................124
SSPCON1 ................................................................118
SSPCON2 Register .................................................120
SSPSR .....................................................................124
SSPSTAT .................................................................116
TMR2 Output for Clock Shift ............................ 101, 102
Acknowledge Sequence Timing .............................. 142
Baud Rate Generator with Clock Arbitration ............ 136
BRG Reset Due to SDA Collision ............................ 146
Bus Collision
START Condition Timing ................................. 145
Bus Collision During a Repeated START
Condition (Case 1) ........................................... 147
Bus Collision During a Repeated START
SSP Module
Condition (Case2) ............................................ 147
Bus Collision During a START Condition
SPI Master Mode .....................................................124
SPI Master./Slave Connection .................................123
SPI Slave Mode .......................................................125
SSPCON1 Register ..........................................................118
SSPOV .............................................................................139
SSPSTAT Register ..........................................................116
R/W Bit .....................................................................129
STATUS Register ...............................................................52
STKPTR Register ...............................................................38
SUBFWB ..........................................................................222
SUBLW ............................................................................223
SUBWF ............................................................................223
SUBWFB ..........................................................................224
SWAPF ............................................................................224
Synchronous Serial Port. See SSP.
(SCL = 0) ......................................................... 146
Bus Collision During a STOP Condition .................. 148
Bus Collision for Transmit and Acknowledge .......... 144
2
I C Bus Data ............................................................ 259
2
I C Master Mode First START Bit Timing ................ 137
2
I C Master Mode Reception Timing ......................... 141
2
I C Master Mode Transmission Timing ................... 140
Master Mode Transmit Clock Arbitration ................. 143
Repeat START Condition ........................................ 138
Slave Synchronization ............................................. 125
SPI Mode Timing (Master Mode) SPI Mode
Master Mode Timing Diagram ......................... 124
SPI Mode Timing (Slave Mode with CKE = 0) ......... 126
SPI Mode Timing (Slave Mode with CKE = 1) ......... 126
DS39026D-page 296
1999-2013 Microchip Technology Inc.
PIC18CXX2
STOP Condition Receive or Transmit ...................... 143
Time-out Sequence on Power-up ........................ 32, 33
USART Asynchronous Master Transmission ........... 156
USART Asynchronous Reception ............................ 158
USART Synchronous Reception .............................. 161
USART Synchronous Transmission ........................ 160
Wake-up from SLEEP via Interrupt .......................... 186
Timing Diagrams and Specifications ................................ 246
A/D Conversion ........................................................ 262
Brown-out Reset (BOR) ........................................... 248
Capture/Compare/PWM (CCP) ................................ 250
CLKOUT and I/O ...................................................... 247
External Clock .......................................................... 246
Baud Rate Generator (BRG) ................................... 151
Associated Registers ....................................... 151
Baud Rate Error, Calculating ........................... 151
Baud Rate Formula ......................................... 151
Baud Rates, Asynchronous Mode
(BRGH = 0) .............................................. 153
Baud Rates, Asynchronous Mode
(BRGH = 1) .............................................. 154
Baud Rates, Synchronous Mode ..................... 152
High Baud Rate Select (BRGH Bit) ................. 151
Sampling ......................................................... 151
RCSTA Register ...................................................... 150
Serial Port Enable (SPEN Bit) ................................. 149
Synchronous Master Mode ...................................... 159
Associated Registers, Reception ..................... 161
Associated Registers, Transmit ....................... 159
Reception ........................................................ 161
Timing Diagram, Synchronous Receive .......... 260
Timing Diagram, Synchronous
Transmission ........................................... 260
Transmission ................................................... 160
Associated Registers ............................... 159
Synchronous Slave Mode ........................................ 162
Associated Registers, Receive ........................ 163
Associated Registers, Transmit ....................... 162
Reception ........................................................ 163
Transmission ................................................... 162
TXSTA Register ....................................................... 149
2
I C Bus Data ............................................................ 257
2
I C Bus START/STOP Bits ...................................... 256
Oscillator Start-up Timer (OST) ............................... 248
Parallel Slave Port (PSP) ......................................... 251
Power-up Timer (PWRT) ......................................... 248
RESET ..................................................................... 248
Timer0 and Timer1 ................................................... 249
USART Synchronous Receive
(Master/Slave) ................................................. 260
USART SynchronousTransmission
(Master/Slave) ................................................. 260
Watchdog Timer (WDT) ........................................... 248
TRISE Register .................................................................. 87
PSPMODE Bit ...................................................... 85, 90
TSTFSZ ........................................................................... 227
Two-Word Instructions
W
Example Cases .......................................................... 41
TXSTA Register
Wake-up from SLEEP .............................................. 179, 185
Timing Diagram ....................................................... 186
Using Interrupts ....................................................... 185
Watchdog Timer (WDT) ........................................... 179, 183
Associated Registers ............................................... 184
Block Diagram ......................................................... 184
Postscaler ................................................................ 184
Programming Considerations .................................. 183
RC Oscillator ........................................................... 183
Time-out Period ....................................................... 183
Timing Diagram ....................................................... 248
Waveform for General Call Address Sequence ............... 133
WCOL .............................................................. 137, 139, 142
WCOL Status Flag ........................................................... 137
WDT ................................................................................ 183
WWW, On-Line Support ...................................................... 5
BRGH Bit ................................................................. 151
U
Universal Synchronous Asynchronous Receiver
Transmitter. See USART.
USART ............................................................................. 149
Asynchronous Mode ................................................ 155
Associated Registers, Receive ........................ 158
Associated Registers, Transmit ....................... 156
Master Transmission ....................................... 156
Receive Block Diagram ................................... 157
Receiver ........................................................... 157
Reception ......................................................... 158
Transmit Block Diagram .................................. 155
Transmitter ....................................................... 155
X
XORLW ........................................................................... 227
XORWF ........................................................................... 228
1999-2013 Microchip Technology Inc.
DS39026D-page 297
PIC18CXX2
NOTES:
DS39026D-page 298
1999-2013 Microchip Technology Inc.
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
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Users of Microchip products can receive assistance
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• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
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Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
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Technical support is available through the web site
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• Business of Microchip – Product selector and
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CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
1999-2013 Microchip Technology Inc.
DS39026D-page 299
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
RE:
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Literature Number: DS39026D
Application (optional):
Would you like a reply?
Y
N
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39026D-page 300
1999-2013 Microchip Technology Inc.
PIC18CXX2
PIC18CXX2 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
/XX
XXX
PART NO.
Device
Examples:
Temperature Package
Range
Pattern
a) PIC18LC452 - I/P 301 = Industrial temp.,
PDIP package, 4 MHz, Extended VDD
limits, QTP pattern #301.
b) PIC18LC242 - I/SO = Industrial temp.,
SOIC package, Extended VDD limits.
c) PIC18C442 - E/P = Extended temp.,
PDIP package, 40MHz, normal VDD
limits.
(1)
(2)
Device
PIC18CXX2 , PIC18CXX2T ;
VDD range 4.2V to 5.5V
(1)
(2)
PIC18LCXX2 , PIC18LCXX2T
VDD range 2.5V to 5.5V
;
Temperature
Range
I
E
=
=
-40C to
-40C to
+85C (Industrial)
+125C (Extended)
(3)
Note 1:
2:
C
= Standard Voltage range
Package
JW
PT
SO
SP
P
=
=
=
=
=
=
Windowed CERDIP
TQFP (Thin Quad Flatpack)
SOIC
Skinny plastic dip
PDIP
LC = Wide Voltage Range
T
= in tape and reel - SOIC,
PLCC, and TQFP
packages only.
L
PLCC
3: JW Devices are UV erasable and can
be programmed to any device configu-
ration. JW Devices meet the electrical
requirement of each oscillator type
(including LC devices).
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Worldwide Site (www.microchip.com)
1999-2013 Microchip Technology Inc.
DS39026D-page 301
PIC18CXX2
DS39026D-page 302
1999-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
32
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 1999-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769676
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
1999-2013 Microchip Technology Inc.
DS39026D-page 303
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11/29/12
DS39026D-page 304
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