PIC24F08KL402_技术文档

PIC24F16KL402 FAMILY

Low-Power, Low-Cost, General Purpose

16-Bit Flash Microcontrollers with nanoWatt XLP Technology

Power Management Modes:

Peripheral Features:

• High-Current Sink/Source (18 mA/18 mA) on All

I/O Pins

• Configurable Open-Drain Outputs on Digital I/O Pins

• Up to Three External Interrupt Sources

• Two 16-Bit Timer/Counters with Selectable Clock

Sources

• Run – CPU, Flash, SRAM and Peripherals on

• Doze – CPU Clock Runs Slower than Peripherals

• Idle – CPU Off, SRAM and Peripherals on

• Sleep – CPU, Flash and Peripherals Off and SRAM on

• Low-Power Consumption:

- Run mode currents under 350 µA/MHz at 1.8V

- Idle mode currents under 80 µA/MHz at 1.8V

- Sleep mode currents as low as 30 nA at 25°C

- Watchdog Timer as low as 210 nA at 25°C

• Up to Two 8-Bit Timers/Counters with Programmable

Prescalers

• Two Capture/Compare/PWM (CCP) modules:

- Modules automatically configure and drive I/O

- 16-bit Capture with max. resolution 40 ns

- 16-bit Compare with max. resolution 83.3 ns

- 1-bit to 10-bit PWM resolution

• Up to One Enhanced CCP module:

- Backward compatible with CCP

- 1, 2 or 4 PWM outputs

High-Performance CPU:

• Modified Harvard Architecture

• Up to 16 MIPS Operation @ 32 MHz

• 8 MHz Internal Oscillator:

- 4x PLL option

- Multiple divide options

• 17-Bit x 17-Bit Single-Cycle Hardware

Fractional/integer Multiplier

• 32-Bit by 16-Bit Hardware Divider

• 16 x 16-Bit Working Register Array

• C Compiler Optimized Instruction Set

Architecture (ISA):

- 76 base instructions

- Flexible addressing modes

• Linear Program Memory Addressing

• Linear Data Memory Addressing

• Two Address Generation Units (AGU) for Separate

Read and Write Addressing of Data Memory

- Programmable dead time

- Auto-shutdown on external event

• Up to Two Master Synchronous Serial Port modules

(MSSPs) with Two Modes of Operation:

- 3-wire SPI (all four modes)

2

- I C™ Master, Multi-Master and Slave modes and

7-Bit/10-Bit Addressing

• Up to Two UART modules:

- Supports RS-485, RS-232 and LIN/J2602

- On-chip hardware encoder/decoder for IrDA^®

- Auto-wake-up on Start bit

- Auto-Baud Detect (ABD)

- Two-byte transmit and receive FIFO buffers

Memory

Peripherals

Flash

Program

(bytes)

Data

EEPROM

(bytes)

Device

Pins

Data

(bytes)

PIC24F16KL402

PIC24F08KL402

PIC24F16KL401

PIC24F08KL401

PIC24F08KL302

PIC24F08KL301

PIC24F08KL201

PIC24F08KL200

PIC24F04KL101

PIC24F04KL100

28

20

28

20

14

20

14

16K

8K

16K

8K

4K

1024

512

256

—

12

—

12

7

2

1

2/2

1/2

2/1

2/0

2

1

2

1

Y

512

—

512

—

512

—

 2011 Microchip Technology Inc.

DS31037B-page 1

PIC24F16KL402 FAMILY

• Fail-Safe Clock Monitor (FSCM) Operation:

- Detects clock failure and switches to on-chip,

low-power RC oscillator

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Flexible Watchdog Timer (WDT):

- Uses its own low-power RC oscillator

- Windowed operating modes

- Programmable period of 2 ms to 131s

• In-Circuit Serial Programming™ (ICSP™) and

In-Circuit Emulation (ICE) via 2 Pins

• Programmable High/Low-Voltage Detect (HLVD)

• Programmable Brown-out Reset (BOR):

- Configurable for software controlled operation and

shutdown in Sleep mode

Analog Features:

• 10-Bit, up to 12-Channel Analog-to-Digital (A/D)

Converter:

- 500 ksps conversion rate

- Conversion available during Sleep and Idle

• Dual Rail-to-Rail Analog Comparators with

Programmable Input/Output Configuration

• On-Chip Voltage Reference

Special Microcontroller Features:

• Operating Voltage Range of 1.8V to 3.6V

• 10,000 Erase/Write Cycle Endurance Flash Program

Memory, Typical

• 100,000 Erase/Write Cycle Endurance Data

EEPROM, Typical

• Flash and Data EEPROM Data Retention:

40 Years Minimum

- Selectable trip points (1.8V, 2.7V and 3.0V)

- Low-power 2.0V POR re-arm

• Self-Programmable under Software Control

• Programmable Reference Clock Output

DS31037B-page 2

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

Pin Diagrams: PIC24FXXKL302/402

28-Pin SPDIP/SSOP/SOIC⁽¹⁾

1

2

3

4

5

6

7

8

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VDD

VSS

MCLR/VPP/RA5

VREF+/CVREF+/AN0/SDA2/CN2/RA0

CVREF-/VREF-/AN1/CN3/RA1

AN9/T3CK/REFO/SS1/CN11/RB15

CVREF/AN10/C1OUT/FLT0/INT1/CN12/RB14

AN11/SDO1/CN13/RB13

AN12/HLVDIN/SS2/CCP2/CN14/RB12

PGEC2/SCK1/P1C/CN15/RB11

PGED2/SDI1/P1B/CN16/RB10

C2OUT/CCP1/P1A/INT2/CN8/RA6

SDI2/CCP3/CN9/RA7

PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/CN4/RB0

PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1

AN4/C1INB/C2IND/T3G/U1RX/CN6/RB2

C1INA/C2INC/SCL2/CN7/RB3

VSS

OSCI/AN13/CLKI/CN30/RA2

9

OSCO/AN14/CLKO/CN29/RA3

SOSCI/AN15/U2RTS/CN1/RB4

SOSCO/SCLKI/U2CTS/CN0/RA4

VDD

10

11

12

13

14

SDA1/T1CK/U1RTS/P1D/CN21/RB9

SCL1/U1CTS/CN22/RB8

U1TX/INT0/CN23/RB7

PGEC3/ASCL1⁽²⁾/SDO2/CN24/RB6

PGED3/ASDA1⁽²⁾/SCK2/CN27/RB5

28-Pin QFN⁽¹⁾

28272625242322

PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/CN4/RB0

PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1

AN4/C1INB/C2IND/T3G/U1RX/CN6/RB2

C1INA/C2INC/SCL2/CN7/RB3

VSS

AN11/SDO1/CN13/RB13

21

1

2

3

4

5

6

7

AN12/HLVDIN/SS2/CCP2/CN14/RB12

20

24FXXKL302⁽²⁾

24FXXKL402

PGEC2/SCK1/P1C/CN15/RB11

19

PGED2/SDI1/P1B/CN16/RB10

18

C2OUT/CCP1/P1A/INT2/CN8/RA6

17

OSCI/AN13/CLKI/CN30/RA2

OSCO/AN14/CLKO/CN29/RA3

SDI2/CCP3/CN9/RA7

SDA1/T1CK/U1RTS/P1D/CN21/RB9

16

15

8

9 1011 12 1314

Contact your Microchip sales team for Chip Scale Package (CSP) availability.

Note 1:

Analog features (indicated in red) are not available on PIC24FXXKL302 devices.

2

2: Alternate location for I C™ functionality of MSSP1, as determined by the I2C1SEL Configuration bit.

 2011 Microchip Technology Inc.

DS31037B-page 3

PIC24F16KL402 FAMILY

Pin Diagrams: PIC24FXXKL301/401

20-Pin SPDIP/SSOP/SOIC⁽¹⁾

1

20

19

18

17

16

15

14

13

12

11

VDD

VSS

MCLR/VPP/RA5

2

3

4

5

6

7

8

PGEC2/VREF+/CVREF+/AN0/SDA2/SDI2/CN2/RA0

PGED2/CVREF-/VREF-/AN1/SDO2/CN3/RA1

PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/P1C/CN4/RB0

PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1

AN4/T3G/U1RX/CN6/RB2

AN9/SCL2/T3CK/REFO/SCK2/CN11/RB15

CVREF/AN10/SDI1/C1OUT/FLT0/INT1/CN12/RB14

AN11/SDO1/P1D/CN13/RB13

AN12/HLVDIN/SCK1/SS2/CCP2/CN14/RB12

C2OUT/CCP1/P1A/INT2/CN8/RA6

SDA1/T1CK/U1RTS/CCP3/CN21/RB9

SCL1/U1CTS/SS1/CN22/RB8

U1TX/INT0/CN23/RB7

OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2

OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3

PGED3/SOSCI/AN15/U2RTS/CN1/RB4

9

10

PGEC3/SOSCO/SCLKI/U2CTS/CN0/RA4

20-Pin QFN⁽¹⁾

20 19 18 17 16

AN9/SCL2/T3CK/REFO/SCK2/CN11/RB15

15

PGED1/AN2/ULPWU/C1IND/C2INB/U2TX/P1C/CN4/RB0

PGEC1/AN3/C1INC/C2INA/U2RX/CN5/RB1

AN4/T3G/U1RX/CN6/RB2

1

2

3

4

5

(2)

CVREF/AN10/SDI1/C1OUT/FLT0/INT1/CN12/RB14

AN11/SDO1/P1D/CN13/RB13

14

13

PIC24FXXKL301

PIC24FXXKL401

12 AN12/HLVDIN/SCK1/SS2/CCP2/CN14/RB12

11 C2OUT/CCP1/P1A/INT2/CN8/RA6

OSCI/AN13/C1INB/C2IND/CLKI/CN30/RA2

OSCO/AN14/C1INA/C2INC/CLKO/CN29/RA3

6

7 8 9 10

Note 1:

Analog features (indicated in red) are not available on PIC24FXXKL301 devices.

DS31037B-page 4

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

Pin Diagrams: PIC24FXXKL10X/20X

20-Pin QFN⁽¹⁾

20 19 18 17 16

AN9/T3CK/REFO/CN11/RB15

CVREF/AN10/SDI1/C1OUT/INT1/CN12/RB14

AN11/SDO1/CN13/RB13

PGED1/AN2/ULPWU/C1IND/CN4/RB0

PGEC1/AN3/C1INC/CN5/RB1

AN4/T3G/U1RX/CN6/RB2

15

₍₂₎14

13

1

2

3

4

5

PIC24FXXKL101

PIC24FXXKL201

12 AN12/HLVDIN/SCK1/CCP2/CN14/RB12

11 CCP1/INT2/CN8/RA6

OSCI/AN13/C1INB/CLKI/CN30/RA2

OSCO/AN14/C1INA/CLKO/CN29/RA3

6

7

8

9 10

20-Pin SPDIP/SSOP/SOIC⁽¹⁾

1

2

3

4

5

6

7

8

20

19

18

17

16

15

14

13

VDD

VSS

MCLR/VPP/RA5

PGEC2/VREF+/CVREF+/AN0/CN2/RA0

PGED2/CVREF-/VREF-/AN1/CN3/RA1

PGED1/AN2/ULPWU/C1IND/CN4/RB0

PGEC1/AN3/C1INC/CN5/RB1

AN9/T3CK/REFO/CN11/RB15

CVREF/AN10/SDI1/C1OUT/INT1/CN12/RB14

AN11/SDO1/CN13/RB13

AN12/HLVDIN/SCK1/CCP2/CN14/RB12

CCP1/INT2/CN8/RA6

SDA1/T1CK/U1RTS/CN21/RB9

SCL1/U1CTS/SS1/CN22/RB8

U1TX/INT0/CN23/RB7

AN4/T3G/U1RX/CN6/RB2

OSCI/AN13/C1INB/CLKI/CN30/RA2

OSCO/AN14/C1INA/CLKO/CN29/RA3

PGED3/SOSCI/AN15/CN1/RB4

9

10

12

11

PGEC3/SOSCO/SCLKI/CN0/RA4

14-Pin PDIP⁽¹⁾

MCLR/VPP/RA5

PGEC2/VREF+/CVREF+/AN0/CN2/RA0

PGED2/CVREF-/VREF-/AN1/ULPWU/CN3/RA1

OSCI/AN13/C1INB/CLKI/CN30/RA2

1

2

3

4

5

6

7

14

13

12

11

10

9

VDD

VSS

AN9/T3CK/REFO/U1RX/SS1/INT0/CN11/RB15

CVREF/AN10/T3G/U1TX/SDI1/C1OUT/INT1/CN12/RB14

CCP1/INT2/CN8/RA6

SDA1/T1CK/U1RTS/SDO1/CCP2/CN21/RB9

SCL1/U1CTS/SCK1/CN22/RB8

OSCO/AN14/C1INA/CLKO/CN29/RA3

PGED3/SOSCI/AN15/HLVDIN/CN1/RB4

PGEC3/SOSCO/SCLKI/CN0/RA4

8

Note 1:

Analog features (indicated in red) are not available on PIC24FXXKL100/101 devices.

 2011 Microchip Technology Inc.

DS31037B-page 5

PIC24F16KL402 FAMILY

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 21

3.0 CPU ........................................................................................................................................................................................... 25

4.0 Memory Organization................................................................................................................................................................. 31

5.0 Flash Program Memory.............................................................................................................................................................. 47

6.0 Data EEPROM Memory ............................................................................................................................................................. 53

7.0 Resets ........................................................................................................................................................................................ 59

8.0 Interrupt Controller ..................................................................................................................................................................... 65

9.0 Oscillator Configuration .............................................................................................................................................................. 95

10.0 Power-Saving Features............................................................................................................................................................ 105

11.0 I/O Ports ................................................................................................................................................................................... 111

12.0 Timer1 ..................................................................................................................................................................................... 115

13.0 Timer2 Module ......................................................................................................................................................................... 117

14.0 Timer3 Module ......................................................................................................................................................................... 119

15.0 Timer4 Module ......................................................................................................................................................................... 123

16.0 Capture/Compare/PWM (CCP) and Enhanced CCP Modules................................................................................................. 125

17.0 Master Synchronous Serial Port (MSSP)................................................................................................................................. 135

18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 149

19.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 157

20.0 Comparator Module.................................................................................................................................................................. 167

21.0 Comparator Voltage Reference................................................................................................................................................ 171

22.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 173

23.0 Special Features ...................................................................................................................................................................... 175

24.0 Development Support............................................................................................................................................................... 187

25.0 Instruction Set Summary.......................................................................................................................................................... 191

26.0 Electrical Characteristics .......................................................................................................................................................... 199

27.0 Packaging Information.............................................................................................................................................................. 225

Appendix A: Revision History............................................................................................................................................................. 249

Index .................................................................................................................................................................................................. 251

The Microchip Web Site..................................................................................................................................................................... 255

Customer Change Notification Service .............................................................................................................................................. 255

Customer Support.............................................................................................................................................................................. 255

Reader Response .............................................................................................................................................................................. 256

Product Identification System............................................................................................................................................................. 257

DS31037B-page 6

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We

welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Web site; http://www.microchip.com

Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

 2011 Microchip Technology Inc.

DS31037B-page 7

PIC24F16KL402 FAMILY

NOTES:

DS31037B-page 8

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

• Doze Mode Operation: When timing-sensitive

applications, such as serial communications,

require the uninterrupted operation of peripherals,

the CPU clock speed can be selectively reduced,

allowing incremental power savings without

missing a beat.

1.0

DEVICE OVERVIEW

This document contains device-specific information for

the following devices:

• PIC24F04KL100

• PIC24F08KL200

• PIC24F08KL301

• PIC24F08KL401

• PIC24F08KL402

• PIC24F04KL101

• PIC24F08KL201

• PIC24F08KL302

• PIC24F16KL401

• PIC24F16KL402

• Instruction-Based Power-Saving Modes: The

microcontroller can suspend all operations, or

selectively shut down its core while leaving its

peripherals active, with a single instruction in

software.

The PIC24F16KL402 family adds an entire range of

economical, low pin count and low-power devices to

Microchip’s portfolio of 16-bit microcontrollers. Aimed

at applications that require low-power consumption but

more computational ability than an 8-bit platform can

provide, these devices offer a range of tailored

peripheral sets that allow the designer to optimize both

price point and features with no sacrifice of

functionality.

1.1.3

OSCILLATOR OPTIONS AND

FEATURES

The PIC24F16KL402 family offers five different

oscillator options, allowing users a range of choices in

developing application hardware. These include:

• Two Crystal modes using crystals or ceramic

resonators.

• Two External Clock modes offering the option of a

divide-by-2 clock output.

1.1

Core Features

• Two Fast Internal Oscillators (FRCs): One with a

nominal 8 MHz output and the other with a

nominal 500 kHz output. These outputs can also

be divided under software control to provide clock

speed as low as 31 kHz or 2 kHz.

• A Phase Locked Loop (PLL) frequency multiplier,

available to the External Oscillator modes and the

8 MHz FRC Oscillator, which allows clock speeds

of up to 32 MHz.

1.1.1

16-BIT ARCHITECTURE

Central to all PIC24F devices is the 16-bit modified

Harvard architecture, first introduced with Microchip’s

dsPIC^®digital signal controllers. The PIC24F CPU core

offers a wide range of enhancements, such as:

• 16-bit data and 24-bit address paths with the

ability to move information between data and

memory spaces

• Linear addressing of up to 12 Mbytes (program

space) and 64 Kbytes (data)

• A 16-element working register array with built-in

software stack support

• A 17 x 17 hardware multiplier with support for

integer math

• Hardware support for 32-bit by 16-bit division

• An instruction set that supports multiple

addressing modes and is optimized for high-level

languages, such as C

• A separate Internal RC Oscillator (LPRC) with a

fixed 31 kHz output, which provides a low-power

option for timing-insensitive applications.

The internal oscillator block also provides a stable

reference source for the Fail-Safe Clock Monitor

(FSCM). This option constantly monitors the main clock

source against a reference signal provided by the

internal oscillator and enables the controller to switch to

the internal oscillator, allowing for continued low-speed

operation or a safe application shutdown.

• Operational performance up to 16 MIPS

1.1.4

EASY MIGRATION

Regardless of the memory size, all the devices share

the same rich set of peripherals, allowing for a smooth

migration path as applications grow and evolve.

1.1.2

POWER-SAVING TECHNOLOGY

All of the devices in the PIC24F16KL402 family

incorporate a range of features that can significantly

reduce power consumption during operation. Key

features include:

The consistent pinout scheme used throughout the

entire family also helps in migrating to the next larger

device. This is true when moving between devices with

the same pin count, or even jumping from 20-pin or

28-pin devices to 44-pin/48-pin devices.

• On-the-Fly Clock Switching: The device clock

can be changed under software control to the

Timer1 source, or the internal, low-power RC

oscillator during operation, allowing the user to

incorporate power-saving ideas into their software

designs.

The PIC24F family is pin compatible with devices in the

dsPIC33 family, and shares some compatibility with the

pinout schema for PIC18 and dsPIC30. This extends

the ability of applications to grow, from the relatively

simple, to the powerful and complex.

 2011 Microchip Technology Inc.

DS31037B-page 9

PIC24F16KL402 FAMILY

1.2

Other Special Features

1.3

Details on Individual Family

Members

• Communications: The PIC24F16KL402 family

incorporates multiple serial communication

peripherals to handle a range of application

requirements. The MSSP module implements

both SPI and I²C™ protocols, and supports both

Master and Slave modes of operation for each.

Devices also include one of two UARTs with

built-in IrDA^®encoders/decoders.

Devices in the PIC24F16KL402 family are available in

14-pin, 20-pin and 28-pin packages. The general block

diagram for all devices is shown in Figure 1-1.

The PIC24F16KL402 family may be thought of as four

different device groups, each offering a slightly different

set of features. These differ from each other in multiple

ways:

• Analog Features: Select members of the

PIC24F16KL402 family include a 10-bit A/D

Converter module. The A/D module incorporates

programmable acquisition time, allowing for a

channel to be selected and a conversion to be

initiated without waiting for a sampling period, as

well as faster sampling speeds.

The comparator modules are configurable for a

wide range of operations and can be used as

either a single or double comparator module.

• The size of the Flash program memory

• The presence and size of data EEPROM

• The presence of an A/D Converter and the

number of external analog channels available

• The number of analog comparators

• The number of general purpose timers

• The number and type of CCP modules

(i.e., CCP vs. ECCP)

• The number of serial communications modules

(both MMSPs and UARTs)

The general differences between the different

sub-families is shown in Table 1-1. The feature sets for

specific devices are summarized in Table 1-2 and

Table 1-3.

A list of the individual pin features available on the

PIC24F16KL402 family devices, sorted by function, is

provided in Table 1-4 (for PIC24FXXKL40X/30X

devices) and Table 1-5 (for PIC24FXXKL20X/10X

devices). Note that this table shows the pin location of

individual peripheral features and not how they are

multiplexed on the same pin. This information is

provided in the pinout diagrams in the beginning of this

data sheet. Multiplexed features are sorted by the

priority given to a feature, with the highest priority

peripheral being listed first.

TABLE 1-1:

FEATURE COMPARISON FOR PIC24F16KL402 FAMILY GROUPS

Program

Memory

(bytes)

Data

EEPROM

(bytes)

Serial

(MSSP/

UART)

Timers

(8/16-bit)

CCP and

ECCP

A/D

(channels)

Device Group

Comparators

PIC24FXXKL10X

PIC24FXXKL20X

PIC24FXXKL30X

4K

8K

—

1/2

2/2

2/0

2/1

1/1

2/2

—

7 or 12

—

1

2

256

512

PIC24FXXKL40X 8K or 16K

12

DS31037B-page 10

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

TABLE 1-2:

DEVICE FEATURES FOR PIC24F16KL40X/30X DEVICES

Features

Operating Frequency

DC – 32 MHz

Program Memory (bytes)

Program Memory (instructions)

Data Memory (bytes)

16K

5632

8K

2816

8K

16K

5632

8K

2816

8K

2816

1024

Data EEPROM Memory (bytes)

512

256

512

256

Interrupt Sources

31 (27/4)

30 (26/4)

31 (27/4)

30 (26/4)

(soft vectors/NMI traps)

I/O Ports

PORTA<7:0>

PORTA<6:0>

PORTB<15:0>

PORTB<15:12,9:7,4,2:0>

Total I/O Pins

24

18

Timers (8/16-bit)

Capture/Compare/PWM modules:

Total

2/2

3

1

3

1

3

1

3

1

3

1

3

1

Enhanced CCP

Input Change Notification Interrupt

Serial Communications:

UART

23

17

2

MSSP

10-Bit Analog-to-Digital Module

(input channels)

12

—

12

—

Analog Comparators

Resets (and delays)

2

POR, BOR, RESETInstruction, MCLR, WDT, Illegal Opcode,

REPEATInstruction, Hardware Traps, Configuration Word Mismatch

(PWRT, OST, PLL Lock)

Instruction Set

Packages

76 Base Instructions, Multiple Addressing Mode Variations

28-Pin PDIP/SSOP/SOIC/QFN

20-Pin SPDIP/SSOP/SOIC/QFN

 2011 Microchip Technology Inc.

DS31037B-page 11

PIC24F16KL402 FAMILY

TABLE 1-3:

DEVICE FEATURES FOR THE PIC24F16KL20X/10X DEVICES

Features

Operating Frequency

DC – 32 MHz

Program Memory (bytes)

Program Memory (instructions)

Data Memory (bytes)

8K

2816

512

4K

1408

512

—

8K

2816

512

4K

1408

512

Data EEPROM Memory (bytes)

—

Interrupt Sources

27 (23/4)

26 (22/4)

27 (23/4)

26 (22/4)

(soft vectors/NMI traps)

I/O Ports

PORTA<6:0>

PORTA<5:0>

PORTB<15:12,9:7,4,2:0>

PORTB<15:14,9:8,4,0>

Total I/O Pins

17

12

Timers (8/16-bit)

Capture/Compare/PWM modules:

Total

1/2

2

0

2

0

2

0

2

0

Enhanced CCP

Input Change Notification Interrupt

Serial Communications:

UART

17

11

1

7

1

MSSP

10-Bit Analog-to-Digital Module

(input channels)

12

—

Analog Comparators

Resets (and delays)

1

POR, BOR, RESETInstruction, MCLR, WDT, Illegal Opcode,

REPEATInstruction, Hardware Traps, Configuration Word Mismatch

(PWRT, OST, PLL Lock)

Instruction Set

Packages

76 Base Instructions, Multiple Addressing Mode Variations

20-Pin SPDIP/SSOP/SOIC/QFN

14-Pin PDIP/TSSOP

DS31037B-page 12

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

FIGURE 1-1:

PIC24F16KL402 FAMILY GENERAL BLOCK DIAGRAM

Data Bus

Interrupt

Controller

16

8

Data Latch

Data RAM

PSV and Table

Data Access

Control Block

PCH

Program Counter

Stack

Control

Logic

PCL

23

Address

Latch

PORTA⁽¹⁾

RA<0:7>

Repeat

Control

Logic

16

23

16

Read AGU

Write AGU

Address Latch

Program Memory

Data EEPROM

Data Latch

16

EA MUX

Address Bus

24

16

Inst Latch

PORTB⁽¹⁾

RB<0:15>

Inst Register

Instruction

Decode and

Control

Divide

Support

Control Signals

16 x 16

W Reg Array

17x17

Multiplier

Power-up

Timer

Timing

Generation

OSCO/CLKO

OSCI/CLKI

Oscillator

FRC/LPRC

Oscillators

Start-up Timer

Power-on

Reset

16-Bit ALU

16

Watchdog

Timer

Precision

Band Gap

Reference

BOR

ULPWU

VDD,

VSS

ULPWU

MCLR

10-Bit

A/D

Timer4

Comparators

Timer1

Timer2

Timer3

UART

1/2⁽¹⁾

CCP1/

ECCP1⁽¹⁾

MSSP

1/2⁽¹⁾

CN1-23⁽¹⁾

HLVD

CCP2

CCP3⁽¹⁾

Note 1: All pins or features are not implemented on all device pinout configurations. See Table 1-4 and Table 1-5 for

I/O port pin descriptions.

 2011 Microchip Technology Inc.

DS31037B-page 13

PIC24F16KL402 FAMILY

TABLE 1-4:

PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS

Pin Number

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

Function

I/O

Buffer

Description

20-Pin

QFN

SPDIP/

SSOP/

SOIC

28-Pin

QFN

AN0

2

3

19

20

1

2

3

27

28

1

I

ANA

A/D Analog Inputs. Not available on PIC24F16KL30X

family devices.

AN1

I

AN2

4

I

AN3

5

2

5

2

I

AN4

6

3

6

3

I

AN5

—

18

17

16

15

7

—

15

14

13

12

4

7

4

I

AN9

26

25

24

23

9

23

22

21

20

6

I

AN10

AN11

AN12

AN13

AN14

AN15

ASCL1

ASDA1

AVDD

AVSS

CCP1

I

8

5

10

11

15

14

28

27

20

7

I

9

6

8

2

—

20

19

14

—

17

16

11

12

11

25

24

17

I/O

I

I C™

Alternate MSSP1 I C Clock Input/Output

2

I C

Alternate MSSP1 I C Data Input/Output

ANA

ST

Positive Supply for Analog modules

Ground Reference for Analog modules

I

I/O

CCP1/ECCP1 Capture Input/Compare and PWM

Output

CCP2

15

13

8

12

10

5

23

19

7

20

16

4

I/O

ST

CCP2 Capture Input/Compare and PWM Output

CCP3 Capture Input/Compare and PWM Output

Comparator 1 Input A (+)

Comparator 1 Input B (-)

Comparator 1 Input C (+)

Comparator 1 Input D (-)

Comparator 1 Output

CCP3

I/O

C1INA

C1INB

C1INC

C1IND

C1OUT

C2INA

C2INB

C2INC

C2IND

C2OUT

CLK I

I

ANA

—

7

4

6

3

5

2

5

2

I

4

1

4

1

I

17

5

14

2

25

5

22

2

O

I

ANA

—

Comparator 2 Input A (+)

Comparator 2 Input B (-)

Comparator 2 Input C (+)

Comparator 2 Input D (-)

Comparator 2 Output

4

1

4

1

I

8

5

7

4

I

7

4

6

3

I

14

7

11

4

20

9

17

6

O

I

ANA

—

Main Clock Input

CLKO

8

5

10

7

O

System Clock Output

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I C = I C™/SMBus input buffer

2

DS31037B-page 14

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

TABLE 1-4:

PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

Function

I/O

Buffer

Description

20-Pin

QFN

SPDIP/

SSOP/

SOIC

28-Pin

QFN

CN0

10

9

7

6

12

11

2

9

I

ST

ANA

ST

Interrupt-on-Change Inputs

CN1

8

CN2

2

19

20

1

27

28

1

CN3

3

CN4

4

CN5

5

2

5

2

CN6

6

3

6

3

CN7

—

14

—

18

17

16

15

—

13

12

11

—

8

—

11

—

15

14

13

12

—

10

9

7

4

CN8

20

19

26

25

24

23

22

21

18

17

16

15

14

10

9

17

16

23

22

21

20

19

18

15

14

13

12

11

7

CN9

CN11

CN12

CN13

CN14

CN15

CN16

CN21

CN22

CN23

CN24

CN27

CN29

CN30

CVREF

CVREF+

CVREF-

8

—

5

7

4

6

17

2

14

19

20

14

12

8

25

2

22

27

28

22

20

13

22

17

26

Comparator Voltage Reference Output

Comparator Reference Positive Input Voltage

Comparator Reference Negative Input Voltage

ECCP1 Enhanced PWM Fault Input

High/Low-Voltage Detect Input

Interrupt 0 Input

3

FLT0

17

15

11

17

14

1

25

23

16

25

20

1

HLVDIN

INT0

INT1

14

11

18

Interrupt 1 Input

INT2

Interrupt 2 Input

MCLR

Master Clear (device Reset) Input. This line is

brought low to cause a Reset.

OSCI

OSCO

P1A

7

8

4

5

9

6

I

ANA

—

Main Oscillator Input

10

20

21

22

18

7

O

Main Oscillator Output

14

5

11

2

17

18

19

15

ECCP1 Output A (Enhanced PWM Mode)

ECCP1 Output B (Enhanced PWM Mode)

ECCP1 Output C (Enhanced PWM Mode)

ECCP1 Output D (Enhanced PWM Mode)

P1B

—

P1C

4

1

—

P1D

16

13

—

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I C = I C™/SMBus input buffer

2

 2011 Microchip Technology Inc.

DS31037B-page 15

PIC24F16KL402 FAMILY

TABLE 1-4:

PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

Function

I/O

Buffer

Description

20-Pin

QFN

SPDIP/

SSOP/

SOIC

28-Pin

QFN

PGEC1

PCED1

PGEC2

PGED2

PGEC3

PGED3

RA0

5

4

2

1

5

2

I/O

I

ST

—

ICSP™ Clock 1

ICSP Data 1

ICSP Clock 2

ICSP Data 2

ICSP Clock 3

ICSP Data 3

PORTA Pins

4

1

2

19

20

7

22

21

15

14

2

19

18

12

11

27

28

6

3

10

9

6

2

19

20

4

RA1

3

RA2

7

9

RA3

8

5

10

12

1

7

RA4

10

1

7

9

RA5

18

11

—

1

26

17

16

1

RA6

14

—

4

20

19

4

I/O

O

RA7

RB0

PORTB Pins

RB1

5

2

5

2

RB2

6

3

6

3

RB3

—

9

—

6

7

4

RB4

11

14

15

16

17

18

21

22

23

24

25

26

22

14

17

7

8

RB5

—

11

12

13

—

15

16

17

18

15

18

12

18

10

13

2

—

8

11

12

13

14

15

18

19

20

21

22

23

19

11

14

4

RB6

RB7

RB8

9

RB9

10

—

12

13

14

15

12

15

9

RB10

RB11

RB12

RB13

RB14

RB15

REFO

SCK1

SCK2

SCL1

SCL2

SCLKI

SDA1

SDA2

SDI1

SDI2

SDO1

SDO2

Reference Clock Output

I/O

I

ST

MSSP1 SPI Serial Input/Output Clock

MSSP2 SPI Serial Input/Output Clock

2

I C

MSSP1 I C Clock Input/Output

2

15

7

I C

MSSP2 I C Clock Input/Output

12

18

2

9

ST

Digital Secondary Clock Input

2

10

19

14

19

13

20

15

27

18

16

21

12

I/O

I

I C

MSSP1 I C Data Input/Output

2

I C

MSSP2 I C Data Input/Output

17

2

21

19

24

15

ST

—

MSSP1 SPI Serial Data Input

MSSP2 SPI Serial Data Input

MSSP1 SPI Serial Data Output

MSSP2 SPI Serial Data Output

I

16

3

O

—

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I C = I C™/SMBus input buffer

2

DS31037B-page 16

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

TABLE 1-4:

PIC24F16KL40X/30X FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

20-Pin

PDIP/

SSOP/

SOIC

28-Pin

Function

I/O

Buffer

Description

20-Pin

QFN

SPDIP/

SSOP/

SOIC

28-Pin

QFN

SOSCI

SOSCO

SS1

9

10

12

15

13

18

6

7

11

12

26

23

18

26

6

8

9

I

O

I

ANA

—

Secondary Oscillator Input

Secondary Oscillator Output

SPI1 Slave Select

9

23

20

15

23

3

SS2

12

10

15

3

—

SPI2 Slave Select

T1CK

T3CK

T3G

ST

—

Timer1 Clock

I

Timer3 Clock

I

Timer3 External Gate Input

UART1 Clear-to-Send Input

UART1 Request-to-Send Output

UART1 Receive

U1CTS

U1RTS

U1RX

U1TX

U2CTS

U2RTS

U2RX

U2TX

ULPWU

VDD

12

13

6

9

17

18

6

14

15

3

I

10

3

O

I

ST

—

11

10

9

8

16

12

11

5

13

9

O

I

UART1 Transmit

7

ST

—

UART2 Clear-to-Send Input

UART2 Request-to-Send Output

UART2 Receive

6

8

O

I

5

2

ST

—

4

1

4

1

O

I

UART2 Transmit

4

1

4

1

ANA

—

Ultra Low-Power Wake-up Input

20

17

13, 28

10, 25

P

Positive Supply for Peripheral Digital Logic and

I/O Pins

VREF+

VREF-

VSS

2

3

19

20

16

2

3

27

28

I

ANA

—

A/D Reference Voltage Input (+)

A/D Reference Voltage Input (-)

19

8, 27

5, 24

P

Ground Reference for Logic and I/O Pins

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I C = I C™/SMBus input buffer

2

 2011 Microchip Technology Inc.

DS31037B-page 17

PIC24F16KL402 FAMILY

TABLE 1-5:

PIC24F16KL20X/10X FAMILY PINOUT DESCRIPTIONS

Pin Number

20-Pin

PDIP/

SSOP/

SOIC

14-Pin

PDIP/

TSSOP

Function

I/O

Buffer

Description

20-Pin

QFN

AN0

2

3

19

20

1

2

3

I

ANA

ST

A/D Analog Inputs. Not available on PIC24F16KL10X

family devices.

AN1

I

AN2

4

—

12

11

—

4

I

AN3

5

2

I

AN4

6

3

I

AN9

18

17

16

15

7

15

14

13

12

4

I

AN10

AN11

AN12

AN13

AN14

AN15

AVDD

AVSS

CCP1

CCP2

C1INA

C1INB

C1INC

C1IND

C1OUT

CLK I

CLKO

CN0

I

8

5

I

9

6

I

20

19

14

15

8

17

16

11

12

5

14

13

10

9

I

Positive Supply for Analog modules

Ground Reference for Analog modules

CCP1 Capture Input/Compare and PWM Output

CCP2 Capture Input/Compare and PWM Output

Comparator 1 Input A (+)

I

I/O

ST

5

I

ANA

—

7

4

Comparator 1 Input B (-)

5

2

—

11

9

I

Comparator 1 Input C (+)

4

1

I

Comparator 1 Input D (-)

17

7

14

4

O

I

Comparator 1 Output

ANA

—

Main Clock Input

8

5

10

7

O

I

System Clock Output

10

9

7

ST

Interrupt-on-Change Inputs

CN1

6

I

ST

CN2

2

19

20

1

2

I

ST

CN3

3

I

ST

CN4

4

–-

10

–-

12

11

–-

9

I

ST

CN5

5

2

I

ST

CN6

6

3

I

ST

CN8

14

–-

18

17

16

15

13

12

11

8

11

–-

15

14

13

12

10

9

I

ST

CN9

I

ST

CN11

CN12

CN13

CN14

CN21

CN22

CN23

CN29

CN30

I

ST

I

ST

I

ST

I

ST

I

ST

8

I

ST

8

–-

5

I

ST

5

I

ST

7

4

I

ST

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I C = I C™/SMBus input buffer

2

DS31037B-page 18

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

TABLE 1-5:

PIC24F16KL20X/10X FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

20-Pin

PDIP/

SSOP/

SOIC

14-Pin

PDIP/

TSSOP

Function

I/O

Buffer

Description

20-Pin

QFN

CVREF

CVREF+

CVREF-

HLVDIN

INT0

17

2

14

19

20

12

8

11

2

I

ANA

ST

Comparator Voltage Reference Output

Comparator Reference Positive Input Voltage

Comparator Reference Negative Input Voltage

High/Low-Voltage Detect Input

Interrupt 0 Input

3

15

11

17

14

1

6

12

11

10

1

ST

INT1

14

11

18

ST

Interrupt 1 Input

INT2

ST

Interrupt 2 Input

MCLR

ST

Master Clear (device Reset) Input. This line is brought

low to cause a Reset.

OSCI

OSCO

PGEC1

PCED1

PGEC2

PGED2

PGEC3

PGED3

RA0

7

8

4

5

4

5

I

ANA

ST

—

Main Oscillator Input

Main Oscillator Output

ICSP™ Clock 1

ICSP Data 1

O

5

2

—

2

I/O

I

4

1

2

19

20

7

ICSP Clock 2

3

ICSP Data 2

10

9

7

ICSP Clock 3

6

ICSP Data 3

2

19

20

4

2

PORTA Pins

RA1

3

RA2

7

4

RA3

8

5

RA4

10

1

7

RA5

18

11

1

RA6

14

4

10

—

6

I/O

O

RB0

PORTB Pins

RB1

5

2

RB2

6

3

RB4

9

6

RB7

11

12

13

15

16

17

18

8

—

8

RB8

9

RB9

10

12

13

14

15

9

RB12

RB13

RB14

RB15

REFO

—

11

12

Reference Clock Output

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I C = I C™/SMBus input buffer

2

 2011 Microchip Technology Inc.

DS31037B-page 19

PIC24F16KL402 FAMILY

TABLE 1-5:

PIC24F16KL20X/10X FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

20-Pin

PDIP/

SSOP/

SOIC

14-Pin

PDIP/

TSSOP

Function

I/O

Buffer

Description

20-Pin

QFN

SCK1

SCL1

SCLKI

SDA1

SDI1

15

12

10

13

17

16

9

12

9

8

I/O

I

ST

MSSP1 SPI Serial Input/Output Clock

2

I C

MSSP1 I C Clock Input/Output

7

12

9

ST

Digital Secondary Clock Input

2

10

14

13

6

I/O

I

I C

MSSP1 I C Data Input/Output

11

9

ST

—

MSSP1 SPI Serial Data Input

MSSP1 SPI Serial Data Output

Secondary Oscillator Input

Secondary Oscillator Output

SPI1 Slave Select

SDO1

SOSCI

SOSCO

SS1

O

I

11

12

9

ANA

—

10

12

13

18

6

7

O

I

9

T1CK

T3CK

T3G

10

15

3

ST

Timer1 Clock

12

11

8

I

ST

Timer3 Clock

I

ST

Timer3 External Gate Input

UART1 Clear-to-Send Input

UART1 Request-to-Send Output

UART1 Receive

U1CTS

U1RTS

U1RX

U1TX

ULPWU

VDD

12

13

6

9

I

ST

10

3

9

O

I

—

12

11

3

ST

11

3

8

O

I

—

UART1 Transmit

1

ANA

—

Ultra Low-Power Wake-up Input

Positive Supply for Peripheral Digital Logic and I/O Pins

A/D Reference Voltage Input (+)

A/D Reference Voltage Input (-)

Ground Reference for Logic and I/O Pins

20

2

17

19

20

16

14

2

P

I

VREF+

VREF-

VSS

ANA

—

3

I

19

13

P

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I C = I C™/SMBus input buffer

2

DS31037B-page 20

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

FIGURE 2-1:

RECOMMENDED

MINIMUM CONNECTIONS

2.0

2.1

GUIDELINES FOR GETTING

STARTED WITH 16-BIT

MICROCONTROLLERS

(1)

C2

VDD

Basic Connection Requirements

Getting started with the PIC24F16KL402 family of

16-bit microcontrollers requires attention to a minimal

set of device pin connections before proceeding with

development.

R1

R2

MCLR

C1

The following pins must always be connected:

PIC24FXXKXX

• All VDD and VSS pins

(see Section 2.2 “Power Supply Pins”)

VDD

VSS

VDD

(1)

C3

C6

• All AVDD and AVSS pins, regardless of whether or

not the analog device features are used

VSS

(see Section 2.2 “Power Supply Pins”)

• MCLR pin

(see Section 2.3 “Master Clear (MCLR) Pin”)

(1)

C4

C5

These pins must also be connected if they are being

used in the end application:

• PGECx/PGEDx pins used for In-Circuit Serial

Programming™ (ICSP™) and debugging purposes

(see Section 2.4 “ICSP Pins”)

Key (all values are recommendations):

C1 through C6: 0.1 F, 20V ceramic

R1: 10 kΩ

• OSCI and OSCO pins when an external oscillator

source is used

R2: 100Ω to 470Ω

(see Section 2.5 “External Oscillator Pins”)

Note 1: The example shown is for a PIC24F device

with five VDD/VSS and AVDD/AVSS pairs.

Other devices may have more or less pairs;

adjust the number of decoupling capacitors

appropriately.

Additionally, the following pins may be required:

• VREF+/VREF- pins are used when external voltage

reference for analog modules is implemented

Note:

The AVDD and AVSS pins must always be

connected, regardless of whether any of

the analog modules are being used.

The minimum mandatory connections are shown in

Figure 2-1.

 2011 Microchip Technology Inc.

DS31037B-page 21

PIC24F16KL402 FAMILY

2.2

Power Supply Pins

2.3

Master Clear (MCLR) Pin

The MCLR pin provides two specific device

functions: Device Reset, and Device Programming

and Debugging. If programming and debugging are

2.2.1

DECOUPLING CAPACITORS

The use of decoupling capacitors on every pair of

power supply pins, such as VDD, VSS, AVDD and

AVSS, is required.

not required in the end application,

a

direct

connection to VDD may be all that is required. The

addition of other components, to help increase the

application’s resistance to spurious Resets from

Consider the following criteria when using decoupling

capacitors:

voltage sags, may be beneficial.

A

typical

• Value and type of capacitor: A 0.1 F (100 nF),

10-20V capacitor is recommended. The capacitor

should be a low-ESR device, with a resonance

frequency in the range of 200 MHz and higher.

Ceramic capacitors are recommended.

configuration is shown in Figure 2-1. Other circuit

designs may be implemented, depending on the

application’s requirements.

During programming and debugging, the resistance

and capacitance that can be added to the pin must

be considered. Device programmers and debuggers

drive the MCLR pin. Consequently, specific voltage

levels (VIH and VIL) and fast signal transitions must

not be adversely affected. Therefore, specific values

of R1 and C1 will need to be adjusted based on the

application and PCB requirements. For example, it is

recommended that the capacitor, C1, be isolated

from the MCLR pin during programming and

debugging operations by using a jumper (Figure 2-2).

The jumper is replaced for normal run-time

operations.

• Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended to

place the capacitors on the same side of the

board as the device. If space is constricted, the

capacitor can be placed on another layer on the

PCB using a via; however, ensure that the trace

length from the pin to the capacitor is no greater

than 0.25 inch (6 mm).

• Handling high-frequency noise: If the board is

experiencing high-frequency noise (upward of

tens of MHz), add a second ceramic type capaci-

tor in parallel to the above described decoupling

capacitor. The value of the second capacitor can

be in the range of 0.01 F to 0.001 F. Place this

second capacitor next to each primary decoupling

capacitor. In high-speed circuit designs, consider

implementing a decade pair of capacitances as

close to the power and ground pins as possible

(e.g., 0.1 F in parallel with 0.001 F).

Any components associated with the MCLR pin

should be placed within 0.25 inch (6 mm) of the pin.

FIGURE 2-2:

EXAMPLE OF MCLR PIN

CONNECTIONS

VDD

• Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a

minimum, thereby reducing PCB trace

R1

R2

MCLR

PIC24FXXKXX

JP

C1

inductance.

Note 1: R1  10 k is recommended. A suggested

starting value is 10 k. Ensure that the

MCLR pin VIH and VIL specifications are met.

2.2.2

TANK CAPACITORS

On boards with power traces running longer than

six inches in length, it is suggested to use a tank capac-

itor for integrated circuits, including microcontrollers, to

supply a local power source. The value of the tank

capacitor should be determined based on the trace

resistance that connects the power supply source to

the device, and the maximum current drawn by the

device in the application. In other words, select the tank

capacitor so that it meets the acceptable voltage sag at

the device. Typical values range from 4.7 F to 47 F.

2: R2  470 will limit any current flowing into

MCLR from the external capacitor, C, in the

event of MCLR pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR pin

VIH and VIL specifications are met.

DS31037B-page 22

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

FIGURE 2-3:

SUGGESTED PLACEMENT

OF THE OSCILLATOR

CIRCUIT

2.4

ICSP Pins

The PGC and PGD pins are used for In-Circuit Serial

Programming™ (ICSP™) and debugging purposes. It

is recommended to keep the trace length between the

ICSP connector and the ICSP pins on the device as

short as possible. If the ICSP connector is expected to

experience an ESD event, a series resistor is recom-

mended, with the value in the range of a few tens of

ohms, not to exceed 100Ω.

Single-Sided and In-Line Layouts:

Copper Pour

(tied to ground)

Primary Oscillator

Crystal

DEVICE PINS

Pull-up resistors, series diodes and capacitors on the

PGC and PGD pins are not recommended as they will

interfere with the programmer/debugger communica-

tions to the device. If such discrete components are an

application requirement, they should be removed from

the circuit during programming and debugging. Alter-

natively, refer to the AC/DC characteristics and timing

requirements information in the respective device

Flash programming specification for information on

capacitive loading limits, and pin input voltage high

(VIH) and input low (VIL) requirements.

Primary

OSC1

OSC2

GND

Oscillator

C1

C2

`

T1OSO

T1OS I

Timer1 Oscillator

Crystal

`

For device emulation, ensure that the “Communication

Channel Select” (i.e., PGCx/PGDx pins), programmed

into the device, matches the physical connections for

the ICSP to the Microchip debugger/emulator tool.

T1 Oscillator: C2

T1 Oscillator: C1

For more information on available Microchip

development tools connection requirements, refer to

Section 24.0 “Development Support”.

Fine-Pitch (Dual-Sided) Layouts:

Top Layer Copper Pour

(tied to ground)

2.5

External Oscillator Pins

Bottom Layer

Copper Pour

(tied to ground)

Many microcontrollers have options for at least two

oscillators: a high-frequency primary oscillator and a

low-frequency

secondary

oscillator

(refer to

OSCO

Section 9.0 “Oscillator Configuration” for details).

The oscillator circuit should be placed on the same

side of the board as the device. Place the oscillator

circuit close to the respective oscillator pins with no

more than 0.5 inch (12 mm) between the circuit

components and the pins. The load capacitors should

be placed next to the oscillator itself, on the same side

of the board.

C2

Oscillator

Crystal

GND

C1

OSCI

Use a grounded copper pour around the oscillator cir-

cuit to isolate it from surrounding circuits. The

grounded copper pour should be routed directly to the

MCU ground. Do not run any signal traces or power

traces inside the ground pour. Also, if using a two-sided

board, avoid any traces on the other side of the board

where the crystal is placed.

DEVICE PINS

In planning the application’s routing and I/O assign-

ments, ensure that adjacent port pins and other

signals, in close proximity to the oscillator, are benign

(i.e., free of high frequencies, short rise and fall times,

and other similar noise).

Layout suggestions are shown in Figure 2-3. In-line

packages may be handled with a single-sided layout

that completely encompasses the oscillator pins. With

fine-pitch packages, it is not always possible to com-

pletely surround the pins and components. A suitable

solution is to tie the broken guard sections to a mirrored

ground layer. In all cases, the guard trace(s) must be

returned to ground.

 2011 Microchip Technology Inc.

DS31037B-page 23

PIC24F16KL402 FAMILY

For additional information and design guidance on

2.6

Unused I/Os

oscillator circuits, please refer to these Microchip

Application Notes, available at the corporate web site

(www.microchip.com):

Unused I/O pins should be configured as outputs and

driven to a logic low state. Alternatively, connect a 1 kΩ

to 10 kΩ resistor to VSS on unused pins and drive the

output to logic low.

• AN826, “Crystal Oscillator Basics and Crystal

Selection for rfPIC™ and PICmicro^®Devices”

• AN849, “Basic PICmicro^®Oscillator Design”

• AN943, “Practical PICmicro^®Oscillator Analysis

and Design”

• AN949, “Making Your Oscillator Work”

DS31037B-page 24

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

For most instructions, the core is capable of executing

a data (or program data) memory read, a working

register (data) read, a data memory write and a

program (instruction) memory read per instruction

cycle. As a result, three parameter instructions can be

supported, allowing trinary operations (i.e., A + B = C)

to be executed in a single cycle.

3.0

CPU

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. For more information on the

CPU, refer to the “PIC24F Family

Reference Manual”, Section 2. “CPU”

(DS39703).

A high-speed, 17-bit by 17-bit multiplier has been

included to significantly enhance the core arithmetic

capability and throughput. The multiplier supports

Signed, Unsigned and Mixed mode, 16-bit by 16-bit or

8-bit by 8-bit integer multiplication. All multiply

instructions execute in a single cycle.

The PIC24F CPU has a 16-bit (data) modified Harvard

architecture with an enhanced instruction set and a

24-bit instruction word with a variable length opcode

field. The Program Counter (PC) is 23 bits wide and

addresses up to 4M instructions of user program

memory space. A single-cycle instruction prefetch

mechanism is used to help maintain throughput and

provides predictable execution. All instructions execute

in a single cycle, with the exception of instructions that

change the program flow, the double-word move

(MOV.D) instruction and the table instructions.

Overhead-free program loop constructs are supported

using the REPEATinstructions, which are interruptible

at any point.

The 16-bit ALU has been enhanced with integer divide

assist hardware that supports an iterative non-restoring

divide algorithm. It operates in conjunction with the

REPEATinstruction looping mechanism and a selection

of iterative divide instructions to support 32-bit (or

16-bit), divided by a 16-bit integer signed and unsigned

division. All divide operations require 19 cycles to

complete, but are interruptible at any cycle boundary.

The PIC24F has a vectored exception scheme, with up

to eight sources of non-maskable traps and up to

118 interrupt sources. Each interrupt source can be

assigned to one of seven priority levels.

PIC24F devices have sixteen, 16-bit working registers

in the programmer’s model. Each of the working

registers can act as a data, address or address offset

register. The 16^thworking register (W15) operates as a

Software Stack Pointer (SSP) for interrupts and calls.

A block diagram of the CPU is illustrated in Figure 3-1.

3.1

Programmer’s Model

The upper 32 Kbytes of the data space memory map

can optionally be mapped into program space at any

16K word boundary of either program memory or data

EEPROM memory, defined by the 8-bit Program Space

Visibility Page Address (PSVPAG) register. The pro-

gram to data space mapping feature lets any instruction

access program space as if it were data space.

Figure 3-2 displays the programmer’s model for the

PIC24F. All registers in the programmer’s model are

memory mapped and can be manipulated directly by

instructions.

Table 3-1 provides a description of each register. All

registers associated with the programmer’s model are

memory mapped.

The Instruction Set Architecture (ISA) has been

significantly enhanced beyond that of the PIC18, but

maintains an acceptable level of backward

compatibility. All PIC18 instructions and addressing

modes are supported, either directly, or through simple

macros. Many of the ISA enhancements have been

driven by compiler efficiency needs.

The core supports Inherent (no operand), Relative,

Literal, Memory Direct and three groups of addressing

modes. All modes support Register Direct and various

Register Indirect modes. Each group offers up to seven

addressing modes. Instructions are associated with

predefined addressing modes depending upon their

functional requirements.

 2011 Microchip Technology Inc.

DS31037B-page 25

PIC24F16KL402 FAMILY

FIGURE 3-1:

PIC24F CPU CORE BLOCK DIAGRAM

PSV and Table

Data Access

Control Block

Data Bus

Interrupt

Controller

16

8

Data Latch

Data RAM

23

16

PCH

PCL

23

Program Counter

Address

Latch

Loop

Control

Logic

Stack

Control

Logic

23

16

RAGU

WAGU

Address Latch

Program Memory

Data EEPROM

Data Latch

EA MUX

16

Address Bus

ROM Latch

24

16

Instruction

Decode and

Control

Instruction Reg

Control Signals

to Various Blocks

Hardware

Multiplier

16 x 16

W Register Array

Divide

16

Support

16-Bit ALU

16

To Peripheral Modules

TABLE 3-1:

CPU CORE REGISTERS

Register(s) Name

Description

W0 through W15

PC

Working Register Array

23-Bit Program Counter

ALU STATUS Register

SR

SPLIM

Stack Pointer Limit Value Register

TBLPAG

PSVPAG

RCOUNT

CORCON

Table Memory Page Address Register

Program Space Visibility Page Address Register

Repeat Loop Counter Register

CPU Control Register

DS31037B-page 26

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

FIGURE 3-2:

PROGRAMMER’S MODEL

15

0

W0 (WREG)

Divider Working Registers

W1

W2

Multiplier Registers

W3

W4

W5

W6

W7

Working/Address

Registers

W8

W9

W10

W11

W12

W13

W14

W15

Frame Pointer

0

Stack Pointer

Stack Pointer Limit

Value Register

SPLIM

22

0

PC

Program Counter

7

0

Table Memory Page

Address Register

TBLPAG

7

Program Space Visibility

Page Address Register

PSVPAG

15

Repeat Loop Counter

Register

RCOUNT

IPL

SRH

SRL

0

— — — — — — —

ALU STATUS Register (SR)

DC

RA N OV Z

C

2 1 0

15

0

— — — — — — — — — — — — IPL3 PSV — —

CPU Control Register (CORCON)

Registers or bits are shadowed for PUSH.Sand POP.Sinstructions.

 2011 Microchip Technology Inc.

DS31037B-page 27

PIC24F16KL402 FAMILY

3.2

CPU Control Registers

REGISTER 3-1:

SR: ALU STATUS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

DC

bit 15

bit 8

R/W-0⁽¹⁾

IPL2⁽²⁾

bit 7

R/W-0⁽¹⁾

IPL1⁽²⁾

R/W-0⁽¹⁾

IPL0⁽²⁾

R-0

RA

R/W-0

N

R/W-0

OV

R/W-0

Z

R/W-0

C

bit 0

Legend:

HSC = Hardware Settable/Clearable bit

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-9

bit 8

Unimplemented: Read as ‘0’

DC: ALU Half Carry/Borrow bit

1= A carry-out from the 4^thlow-order bit (for byte-sized data) or 8^thlow-order bit (for word-sized data)

of the result occurred

0= No carry-out from the 4^thor 8^thlow-order bit of the result has occurred

bit 7-5

IPL<2:0>: CPU Interrupt Priority Level (IPL) Status bits^(1,2)

111= CPU Interrupt Priority Level is 7 (15); user interrupts disabled

110= CPU Interrupt Priority Level is 6 (14)

101= CPU Interrupt Priority Level is 5 (13)

100= CPU Interrupt Priority Level is 4 (12)

011= CPU Interrupt Priority Level is 3 (11)

010= CPU Interrupt Priority Level is 2 (10)

001= CPU Interrupt Priority Level is 1 (9)

000= CPU Interrupt Priority Level is 0 (8)

bit 4

bit 3

bit 2

bit 1

bit 0

RA: REPEATLoop Active bit

1= REPEATloop in progress

0= REPEATloop not in progress

N: ALU Negative bit

1= Result was negative

0= Result was non-negative (zero or positive)

OV: ALU Overflow bit

1= Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation

0= No overflow has occurred

Z: ALU Zero bit

1= An operation, which effects the Z bit, has set it at some time in the past

0= The most recent operation, which effects the Z bit, has cleared it (i.e., a non-zero result)

C: ALU Carry/Borrow bit

1= A carry-out from the Most Significant bit (MSb) of the result occurred

0= No carry-out from the Most Significant bit (MSb) of the result occurred

Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

2: The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority

Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.

DS31037B-page 28

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

REGISTER 3-2:

CORCON: CPU CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

R/C-0

IPL3⁽¹⁾

R/W-0

PSV

U-0

—

U-0

—

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-4

bit 3

Unimplemented: Read as ‘0’

IPL3: CPU Interrupt Priority Level Status bit⁽¹⁾

1= CPU Interrupt Priority Level is greater than 7

0= CPU Interrupt Priority Level is 7 or less

bit 2

PSV: Program Space Visibility in Data Space Enable bit

1= Program space is visible in data space

0= Program space is not visible in data space

bit 1-0

Unimplemented: Read as ‘0’

Note 1: User interrupts are disabled when IPL3 = 1.

The PIC24F CPU incorporates hardware support for

both multiplication and division. This includes a

dedicated hardware multiplier and support hardware

division for a 16-bit divisor.

3.3

Arithmetic Logic Unit (ALU)

The PIC24F ALU is 16 bits wide and is capable of

addition, subtraction, bit shifts and logic operations.

Unless otherwise mentioned, arithmetic operations are

2’s complement in nature. Depending on the operation,

the ALU may affect the values of the Carry (C), Zero

(Z), Negative (N), Overflow (OV) and Digit Carry (DC)

Status bits in the SR register. The C and DC Status bits

operate as Borrow and Digit Borrow bits, respectively,

for subtraction operations.

3.3.1

MULTIPLIER

The ALU contains a high-speed, 17-bit x 17-bit

multiplier. It supports unsigned, signed or mixed sign

operation in several Multiplication modes:

• 16-bit x 16-bit signed

• 16-bit x 16-bit unsigned

The ALU can perform 8-bit or 16-bit operations,

depending on the mode of the instruction that is used.

Data for the ALU operation can come from the W

register array, or data memory, depending on the

addressing mode of the instruction. Likewise, output

data from the ALU can be written to the W register array

or a data memory location.

• 16-bit signed x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit unsigned

• 16-bit unsigned x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit signed

• 8-bit unsigned x 8-bit unsigned

 2011 Microchip Technology Inc.

DS31037B-page 29

PIC24F16KL402 FAMILY

3.3.2

DIVIDER

3.3.3

MULTI-BIT SHIFT SUPPORT

The divide block supports 32-bit/16-bit and 16-bit/16-bit

signed and unsigned integer divide operations with the

following data sizes:

The PIC24F ALU supports both single bit and

single-cycle, multi-bit arithmetic and logic shifts.

Multi-bit shifts are implemented using a shifter block,

capable of performing up to a 15-bit arithmetic right

shift, or up to a 15-bit left shift, in a single cycle. All

multi-bit shift instructions only support Register Direct

Addressing for both the operand source and result

destination.

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0

and the remainder in W1. Sixteen-bit signed and

unsigned DIV instructions can specify any W register

for both the 16-bit divisor (Wn), and any W register

(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.

The divide algorithm takes one cycle per bit of divisor,

so both 32-bit/16-bit and 16-bit/16-bit instructions take

the same number of cycles to execute.

A full summary of instructions that use the shift

operation is provided in Table 3-2.

TABLE 3-2:

Instruction

INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION

Description

ASR

SL

Arithmetic shift right source register by one or more bits.

Shift left source register by one or more bits.

LSR

Logical shift right source register by one or more bits.

DS31037B-page 30

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

User access to the program memory space is restricted

to the lower half of the address range (000000h to

7FFFFFh). The exception is the use of TBLRD/TBLWT

operations, which use TBLPAG<7> to permit access to

the Configuration bits and Device ID sections of the

configuration memory space.

4.0

MEMORY ORGANIZATION

As Harvard architecture devices, the PIC24F

microcontrollers feature separate program and data

memory space and bussing. This architecture also

allows the direct access of program memory from the

data space during code execution.

Memory maps for the PIC24F16KL402 family of

devices are shown in Figure 4-1.

4.1

Program Address Space

The program address memory space of the

PIC24F16KL402 family is 4M instructions. The space is

addressable by a 24-bit value derived from either the

23-bit Program Counter (PC) during program execution,

or from a table operation or data space remapping, as

described in Section 4.3 “Interfacing Program and

Data Memory Spaces”.

FIGURE 4-1:

PROGRAM SPACE MEMORY MAP FOR PIC24F16KL402 FAMILY DEVICES

PIC24F04KLXXX

PIC24F08KL2XX

PIC24F08KL3XX

PIC24F08KL4XX

PIC24F16KLXXX

000000h

000002h

000004h

0000FEh

000100h

000104h

0001FEh

GOTOInstruction

Reset Address

Interrupt Vector Table

Reserved

Alternate Vector Table

GOTOInstruction

Reset Address

Interrupt Vector Table

Reserved

Alternate Vector Table

GOTOInstruction

Reset Address

Interrupt Vector Table

Reserved

Alternate Vector Table

GOTOInstruction

Reset Address

Interrupt Vector Table

Reserved

Alternate Vector Table

GOTOInstruction

Reset Address

Interrupt Vector Table

Reserved

Alternate Vector Table

000200h

Flash

Program Memory

(1408 instructions)

Flash

000AFEh

Program Memory

(2816 instructions)

Flash

Program Memory

(5632 instructions)

0015FEh

002BFEh

Unimplemented

Read ‘0’

Unimplemented

Read ‘0’

Unimplemented

Read ‘

Unimplemented

Read ‘

0

’

Read ‘0’

0

’

7FFE00h

7FFF00h

7FFFFFh

800000h

Data EEPROM

(512 bytes)

Data EEPROM

(512 bytes)

Data EEPROM

(256 bytes)

Reserved

Unique ID

Reserved

Unique ID

Reserved

Unique ID

Reserved

Unique ID

Reserved

Unique ID

800800h

800802h

800808h

80080Ah

Reserved

F80000h

F8000Eh

F80010h

Device Config Registers

Reserved

DEVID (2)

Reserved

DEVID (2)

Reserved

DEVID (2)

Reserved

DEVID (2)

Reserved

DEVID (2)

FEFFFEh

FF0000h

FFFFFFh

Note: Memory areas are not displayed to scale.

DS31037B-page 31

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

4.1.1

PROGRAM MEMORY

ORGANIZATION

4.1.3

DATA EEPROM

In the PIC24F16KL402 family, the data EEPROM is

mapped to the top of the user program memory space,

starting at address, 7FFE00, and expanding up to

address, 7FFFFF.

The program memory space is organized in

word-addressable blocks. Although it is treated as

24 bits wide, it is more appropriate to think of each

address of the program memory as a lower and upper

word, with the upper byte of the upper word being

unimplemented. The lower word always has an even

address, while the upper word has an odd address, as

shown in Figure 4-2.

The data EEPROM is organized as 16-bit wide memory

and 256 words deep. This memory is accessed using

table read and write operations, similar to the user code

memory.

4.1.4

DEVICE CONFIGURATION WORDS

Program memory addresses are always word-aligned

on the lower word, and addresses are incremented or

decremented by two during code execution. This

arrangement also provides compatibility with data

memory space addressing and makes it possible to

access data in the program memory space.

Table 4-1 provides the addresses of the device

Configuration Words for the PIC24F16KL402 family.

Their location in the memory map is shown in

Figure 4-1.

For more information on device Configuration Words,

see Section 23.0 “Special Features”.

4.1.2

HARD MEMORY VECTORS

All PIC24F devices reserve the addresses between

00000h and 000200h for hard-coded program

execution vectors. A hardware Reset vector is provided

to redirect code execution from the default value of the

PC on device Reset to the actual start of code. A GOTO

instruction is programmed by the user at 000000h, with

the actual address for the start of code at 000002h.

TABLE 4-1:

DEVICE CONFIGURATION

WORDS FOR PIC24F16KL402

FAMILY DEVICES

Configuration Word

Configuration Words

Addresses

FBS

F80000

F80004

F80006

F80008

F8000A

F8000C

F8000E

PIC24F devices also have two Interrupt Vector Tables

(IVT), located from 000004h to 0000FFh and 000104h

to 0001FFh. These vector tables allow each of the

many device interrupt sources to be handled by

separate ISRs. A more detailed discussion of the

Interrupt Vector Tables is provided in Section 8.1

“Interrupt Vector Table (IVT)”.

FGS

FOSCSEL

FOSC

FWDT

FPOR

FICD

FIGURE 4-2:

PROGRAM MEMORY ORGANIZATION

least significant word

msw

Address

PC Address

(lsw Address)

most significant word

23

16

8

0

000000h

000002h

000004h

000006h

00000000

000001h

000003h

000005h

000007h

00000000

Program Memory

‘Phantom’ Byte

Instruction Width

(read as ‘0’)

 2011 Microchip Technology Inc.

DS31037B-page 32

PIC24F16KL402 FAMILY

Depending on the particular device, PIC24F16KL402

family devices implement either 512 or 1024 words of

data memory. If an EA points to a location outside of

this area, an all zero word or byte will be returned.

4.2

Data Address Space

The PIC24F core has a separate, 16-bit wide data

memory space, addressable as a single linear range.

The data space is accessed using two Address

Generation Units (AGUs); one each for read and write

operations. The data space memory map is shown in

Figure 4-3.

4.2.1

DATA SPACE WIDTH

The data memory space is organized in

byte-addressable, 16-bit wide blocks. Data is aligned in

data memory and registers as 16-bit words, but all the

data space EAs resolve to bytes. The Least Significant

Bytes (LSBs) of each word have even addresses, while

the Most Significant Bytes (MSBs) have odd

addresses.

All Effective Addresses (EAs) in the data memory space

are 16 bits wide and point to bytes within the data space.

This gives a data space address range of 64 Kbytes or

32K words. The lower half of the data memory space

(that is, when EA<15> = 0) is used for implemented

memory addresses, while the upper half (EA<15> = 1) is

reserved for the Program Space Visibility (PSV) area

(see Section 4.3.3 “Reading Data From Program

Memory Using Program Space Visibility”).

FIGURE 4-3:

DATA SPACE MEMORY MAP FOR PIC24F16KL402 FAMILY DEVICES⁽³⁾

MSB

Address

LSB

Address

MSB

LSB

0000h

07FEh

0800h

0001h

07FFh

0801h

SFR

Space

SFR Space

Data RAM

Near

Data Space

(1)

09FFh

09FEh

Implemented

Data RAM

(2)

0BFFh

0BFEh

1FFEh

1FFFh

Unimplemented

Read as ‘0’

7FFFh

8001h

7FFFh

8000h

Program Space

Visibility Area

FFFFh

FFFEh

Note 1: Upper data memory boundary for PIC24FXXKL10X/20X devices.

2: Upper data memory boundary for PIC24FXXKL30X/40X devices.

3: Data memory areas are not shown to scale.

DS31037B-page 33

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PIC24F16KL402 FAMILY

can clear the MSB of any W register by executing a

Zero-Extend (ZE) instruction on the appropriate

address.

4.2.2

DATA MEMORY ORGANIZATION

AND ALIGNMENT

To maintain backward compatibility with PIC^®devices

and improve data space memory usage efficiency, the

PIC24F instruction set supports both word and byte

operations. As a consequence of byte accessibility, all

Effective Address (EA) calculations are internally

scaled to step through word-aligned memory. For

example, the core recognizes that Post-Modified

Register Indirect Addressing mode [Ws++] will result in

a value of Ws + 1 for byte operations and Ws + 2 for

word operations.

Although most instructions are capable of operating on

word or byte data sizes, it should be noted that some

instructions operate only on words.

4.2.3

NEAR DATA SPACE

The 8-Kbyte area between 0000h and 1FFFh is

referred to as the Near Data Space (NDS). Locations in

this space are directly addressable via a 13-bit abso-

lute address field within all memory direct instructions.

The remainder of the data space is addressable

indirectly. Additionally, the whole data space is

addressable using MOV instructions, which support

Memory Direct Addressing (MDA) with a 16-bit address

field. For PIC24F16KL402 family devices, the entire

implemented data memory lies in Near Data Space.

Data byte reads will read the complete word, which

contains the byte, using the LSB of any EA to

determine which byte to select. The selected byte is

placed onto the LSB of the data path. That is, data

memory and the registers are organized as two

parallel, byte-wide entities with shared (word) address

decode, but separate write lines. Data byte writes only

write to the corresponding side of the array or register,

which matches the byte address.

4.2.4

SFR SPACE

The first 2 Kbytes of the Near Data Space, from 0000h

to 07FFh, are primarily occupied with Special Function

Registers (SFRs). These are used by the PIC24F core

and peripheral modules for controlling the operation of

the device.

All word accesses must be aligned to an even address.

Mis-aligned word data fetches are not supported, so

care must be taken when mixing byte and word

operations, or translating from 8-bit MCU code. If a

mis-aligned read or write is attempted, an address error

trap will be generated. If the error occurred on a read,

the instruction underway is completed; if it occurred on

a write, the instruction will be executed, but the write

will not occur. In either case, a trap is then executed,

allowing the system and/or user to examine the

machine state prior to execution of the address Fault.

SFRs are distributed among the modules that they

control and are generally grouped together by the

module. Much of the SFR space contains unused

addresses; these are read as ‘0’. The SFR space,

where the SFRs are actually implemented, is provided

in Table 4-2. Each implemented area indicates a

32-byte region, where at least one address is

implemented as an SFR. A complete listing of

implemented SFRs, including their addresses, is

provided in Table 4-3 through Table 4-18.

All byte loads into any W register are loaded into the

LSB; the MSB is not modified.

A Sign-Extend (SE) instruction is provided to allow the

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users

TABLE 4-2:

IMPLEMENTED REGIONS OF SFR DATA SPACE

SFR Space Address

xx00

xx20

xx40

xx60

xx80

xxA0

xxC0

xxE0

000h

100h

200h

300h

400h

500h

600h

700h

Core

ICN

Interrupts

—

Timers

MSSP

—

TMR

—

CCP

—

I/O

—

UART

—

A/D

—

ANSEL

—

CMP

—

System

NVM/PMD

Legend: — = No implemented SFRs in this block.

 2011 Microchip Technology Inc.

DS31037B-page 34

PIC24F16KL402 FAMILY

4.2.5

SOFTWARE STACK

4.3

Interfacing Program and Data

Memory Spaces

In addition to its use as a working register, the W15

register in PIC24F devices is also used as a Software

Stack Pointer. The pointer always points to the first

available free word and grows from lower to higher

addresses. It predecrements for stack pops and

post-increments for stack pushes, as shown in

Figure 4-4.

The PIC24F architecture uses a 24-bit wide program

space and 16-bit wide data space. The architecture is

also a modified Harvard scheme, meaning that data

can also be present in the program space. To use this

data successfully, it must be accessed in a way that

preserves the alignment of information in both spaces.

Note that for a PC push during any CALL instruction,

the MSB of the PC is zero-extended before the push,

ensuring that the MSB is always clear.

Apart from the normal execution, the PIC24F

architecture provides two methods by which the

program space can be accessed during operation:

Note:

A PC push during exception processing

will concatenate the SRL register to the

MSB of the PC prior to the push.

• Using table instructions to access individual bytes

or words anywhere in the program space

• Remapping a portion of the program space into

the data space, PSV

The Stack Pointer Limit Value (SPLIM) register,

associated with the Stack Pointer, sets an upper

address boundary for the stack. SPLIM is uninitialized

at Reset. As is the case for the Stack Pointer,

SPLIM<0> is forced to ‘0’ as all stack operations must

be word-aligned. Whenever an EA is generated, using

W15 as a source or destination pointer, the resulting

address is compared with the value in SPLIM. If the

contents of the Stack Pointer (W15) and the SPLIM

register are equal, and a push operation is performed,

a stack error trap will not occur. The stack error trap will

occur on a subsequent push operation.

Table instructions allow an application to read or write

small areas of the program memory. This makes the

method ideal for accessing data tables that need to be

updated from time to time. It also allows access to all

bytes of the program word. The remapping method

allows an application to access a large block of data on

a read-only basis, which is ideal for look-ups from a

large table of static data. It can only access the least

significant word (lsw) of the program word.

4.3.1

ADDRESSING PROGRAM SPACE

Thus, for example, if it is desirable to cause a stack

error trap when the stack grows beyond address,

0DF6, in RAM, initialize the SPLIM with the value,

0DF4.

Since the address ranges for the data and program

spaces are 16 and 24 bits, respectively, a method is

needed to create a 23-bit or 24-bit program address

from 16-bit data registers. The solution depends on the

interface method to be used.

Similarly, a Stack Pointer underflow (stack error) trap is

generated when the Stack Pointer address is found to

be less than 0800h. This prevents the stack from

interfering with the Special Function Register (SFR)

space.

For table operations, the 8-bit Table Memory Page

Address register (TBLPAG) is used to define a 32K word

region within the program space. This is concatenated

with a 16-bit EA to arrive at a full 24-bit program space

address. In this format, the Most Significant bit (MSb) of

TBLPAG is used to determine if the operation occurs in

the user memory (TBLPAG<7> = 0) or the configuration

memory (TBLPAG<7> = 1).

Note:

A write to the SPLIM register should not

be immediately followed by an indirect

read operation using W15.

For remapping operations, the 8-bit Program Space

Visibility Page Address register (PSVPAG) is used to

define a 16K word page in the program space. When

the MSb of the EA is ‘1’, PSVPAG is concatenated with

the lower 15 bits of the EA to form a 23-bit program

space address. Unlike the table operations, this limits

remapping operations strictly to the user memory area.

FIGURE 4-4:

CALLSTACK FRAME

0000h

15

0

Table 4-20 and Figure 4-5 show how the program EA is

created for table operations and remapping accesses

from the data EA. Here, P<23:0> bits refer to a program

space word, whereas the D<15:0> bits refer to a data

space word.

PC<15:0>

000000000

W15 (before CALL)

W15 (after CALL)

PC<22:16>

POP : [--W15]

PUSH: [W15++]

DS31037B-page 43

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

TABLE 4-20: PROGRAM SPACE ADDRESS CONSTRUCTION

Program Space Address

Access

Space

Access Type

<23>

<22:16>

<15>

PC<22:1>

<14:1>

<0>

Instruction Access

(Code Execution)

User

0

0xx xxxx xxxx xxxx xxxx xxx0

TBLRD/TBLWT

(Byte/Word Read/Write)

TBLPAG<7:0>

0xxx xxxx

Data EA<15:0>

xxxx xxxx xxxx xxxx

Data EA<15:0>

Configuration

TBLPAG<7:0>

1xxx xxxx

xxxx xxxx xxxx xxxx

Data EA<14:0>⁽¹⁾

Program Space Visibility User

(Block Remap/Read)

0

PSVPAG<7:0>⁽²⁾

xxxx xxxx

xxx xxxx xxxx xxxx

Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of

the address is PSVPAG<0>.

2: PSVPAG can have only two values (‘00’ to access program memory and FF to access data EEPROM) on

PIC24F16KL402 family devices.

FIGURE 4-5:

DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

Program Counter⁽¹⁾

0

Program Counter

23 Bits

0

1/0

EA

Table Operations⁽²⁾

1/0

TBLPAG

8 Bits

16 bits

24 Bits

Select

1

0

EA

Program Space Visibility⁽¹⁾

(Remapping)

0

PSVPAG

8 bits

15 bits

23 Bits

Byte Select

User/Configuration

Space Select

Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the

program and data spaces.

2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration

memory space.

 2011 Microchip Technology Inc.

DS31037B-page 44

PIC24F16KL402 FAMILY

In Byte mode, either the upper or lower byte of

the lower program word is mapped to the lower

byte of a data address. The upper byte is

selected when the byte select is ‘1’; the lower

byte is selected when it is ‘0’.

4.3.2

DATA ACCESS FROM PROGRAM

MEMORY AND DATA EEPROM

MEMORY USING TABLE

INSTRUCTIONS

The TBLRDL and TBLWTL instructions offer a direct

method of reading or writing the lower word of any

address within the program memory without going

through data space. It also offers a direct method of

reading or writing a word of any address within data

EEPROM memory. The TBLRDH and TBLWTH

instructions are the only method to read or write the

upper 8 bits of a program space word as data.

2. TBLRDH (Table Read High): In Word mode, it

maps the entire upper word of a program address

(P<23:16>) to

a data address. Note that

D<15:8>, the ‘phantom’ byte, will always be ‘0’.

In Byte mode, it maps the upper or lower byte of

the program word to D<7:0> of the data

address, as above. Note that the data will

always be ‘0’ when the upper ‘phantom’ byte is

selected (byte select = 1).

Note:

The TBLRDHand TBLWTHinstructions are

not used while accessing data EEPROM

memory.

In a similar fashion, two table instructions, TBLWTH

and TBLWTL, are used to write individual bytes or

words to a program space address. The details of

their operation are explained in Section 5.0 “Flash

Program Memory”.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two, 16-bit

word-wide address spaces, residing side by side, each

with the same address range. TBLRDL and TBLWTL

access the space which contains the least significant

data word, and TBLRDHand TBLWTHaccess the space

which contains the upper data byte.

For all table operations, the area of program memory

space to be accessed is determined by the Table

Memory Page Address register (TBLPAG). TBLPAG

covers the entire program memory space of the

device, including user and configuration spaces. When

TBLPAG<7> = 0, the table page is located in the user

memory space. When TBLPAG<7> = 1, the page is

located in configuration space.

Two table instructions are provided to move byte or

word-sized (16-bit) data to and from program space.

Both function as either byte or word operations.

Note:

Only table read operations will execute in

the configuration memory space, and only

then, in implemented areas, such as the

Device ID. Table write operations are not

allowed.

1. TBLRDL (Table Read Low): In Word mode, it

maps the lower word of the program space

location (P<15:0>) to a data address (D<15:0>).

FIGURE 4-6:

ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Data EA<15:0>

TBLPAG

Program Space

00

23

16

8

0

000000h

002BFEh

23

15

0

00000000

‘Phantom’ Byte

TBLRDH.B(Wn<0> = 0)

TBLRDL.B(Wn<0> = 1)

TBLRDL.B(Wn<0> = 0)

TBLRDL.W

The address for the table operation is determined by the data EA

within the page defined by the TBLPAG register. Only read

operations are provided; write operations are also valid in the

user memory area.

800000h

DS31037B-page 45

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

24-bit program word are used to contain the data. The

upper 8 bits of any program space location, used as

data, should be programmed with ‘1111 1111’ or ‘0000

0000’ to force a NOP. This prevents possible issues

should the area of code ever be accidentally executed.

4.3.3

READING DATA FROM PROGRAM

MEMORY USING PROGRAM SPACE

VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into a 16K word page of the program space.

This provides transparent access of stored constant

data from the data space without the need to use

special instructions (i.e., TBLRDL/H).

Note:

PSV access is temporarily disabled during

table reads/writes.

For operations that use PSV and are executed outside of

a REPEAT loop, the MOV and MOV.D instructions will

require one instruction cycle, in addition to the specified

execution time. All other instructions will require two

instruction cycles in addition to the specified execution

time.

Program space access through the data space occurs

if the MSb of the data space EA is ‘1’ and PSV is

enabled by setting the PSV bit in the CPU Control

(CORCON<2>) register. The location of the program

memory space to be mapped into the data space is

determined by the Program Space Visibility Page

Address (PSVPAG) register. This 8-bit register defines

any one of 256 possible pages of 16K words in

program space. In effect, PSVPAG functions as the

upper 8 bits of the program memory address, with

15 bits of the EA functioning as the lower bits.

For operations that use PSV, which are executed inside

a REPEAT loop, there will be some instances that

require two instruction cycles, in addition to the

specified execution time of the instruction:

• Execution in the first iteration

• Execution in the last iteration

• Execution prior to exiting the loop due to an

interrupt

• Execution upon re-entering the loop after an

interrupt is serviced

By incrementing the PC by 2 for each program memory

word, the lower 15 bits of data space addresses directly

map to the lower 15 bits in the corresponding program

space addresses.

Data reads from this area add an additional cycle to the

instruction being executed, since two program memory

fetches are required.

Any other iteration of the REPEAT loop will allow the

instruction accessing data, using PSV, to execute in a

single cycle.

Although each data space address, 8000h and higher,

maps directly into a corresponding program memory

address (see Figure 4-7), only the lower 16 bits of the

FIGURE 4-7:

PROGRAM SPACE VISIBILITY OPERATION

When CORCON<2> = 1and EA<15> = 1:

Program Space

Data Space

PSVPAG

23

15

0

000000h

002BFEh

0000h

00

Data EA<14:0>

The data in the page

designated by

PSVPAG is mapped

into the upper half of

the data memory

space....

8000h

PSV Area

...while the lower 15 bits

of the EA specify an exact

address within the PSV

area. This corresponds

exactly to the same lower

15 bits of the actual

FFFFh

program space address.

800000h

 2011 Microchip Technology Inc.

DS31037B-page 46

PIC24F16KL402 FAMILY

Run-Time Self Programming (RTSP) is accomplished

using TBLRD (table read) and TBLWT (table write)

instructions. With RTSP, the user may write program

memory data in blocks of 32 instructions (96 bytes) at

a time, and erase program memory in blocks of 32, 64

and 128 instructions (96,192 and 384 bytes) at a time.

5.0

FLASH PROGRAM MEMORY

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information on Flash Pro-

gramming, refer to the “PIC24F Family

Reference Manual”, Section 4. “Program

Memory” (DS39715).

The NVMOP<1:0> (NVMCON<1:0>) bits decide the

erase block size.

5.1

Table Instructions and Flash

Programming

The PIC24F16KL402 family of devices contains

internal Flash program memory for storing and

executing application code. The memory is readable,

writable and erasable when operating with VDD over

1.8V.

Regardless of the method used, Flash memory

programming is done with the table read and write

instructions. These allow direct read and write access to

the program memory space from the data memory while

the device is in normal operating mode. The 24-bit target

address in the program memory is formed using the

TBLPAG<7:0> bits and the Effective Address (EA) from

a W register, specified in the table instruction, as

depicted in Figure 5-1.

Flash memory can be programmed in three ways:

• In-Circuit Serial Programming™ (ICSP™)

• Run-Time Self Programming (RTSP)

• Enhanced In-Circuit Serial Programming

(Enhanced ICSP)

ICSP allows a PIC24F device to be serially pro-

grammed while in the end application circuit. This is

simply done with two lines for the programming clock

and programming data (which are named PGECx and

PGEDx, respectively), and three other lines for power

(VDD), ground (VSS) and Master Clear/Program mode

Entry Voltage (MCLR/VPP). This allows customers to

manufacture boards with unprogrammed devices and

then program the microcontroller just before shipping

the product. This also allows the most recent firmware

or custom firmware to be programmed.

The TBLRDLand TBLWTLinstructions are used to read

or write to bits<15:0> of program memory. TBLRDLand

TBLWTL can access program memory in both Word

and Byte modes.

The TBLRDHand TBLWTHinstructions are used to read

or write to bits<23:16> of program memory. TBLRDH

and TBLWTHcan also access program memory in Word

or Byte mode.

FIGURE 5-1:

ADDRESSING FOR TABLE REGISTERS

24 Bits

Using

Program

Counter

0

Program Counter

0

Working Reg EA

16 Bits

Using

Table

Instruction

1/0

TBLPAG Reg

8 Bits

User/Configuration

Space Select

Byte

Select

24-Bit EA

 2011 Microchip Technology Inc.

DS31037B-page 47

PIC24F16KL402 FAMILY

5.2

RTSP Operation

5.3

Enhanced In-Circuit Serial

Programming

The PIC24F Flash program memory array is organized

into rows of 32 instructions or 96 bytes. RTSP allows

the user to erase blocks of 1 row, 2 rows and 4 rows

(32, 64 and 128 instructions) at a time, and to program

one row at a time.

Enhanced ICSP uses an on-board bootloader, known

as the program executive, to manage the programming

process. Using an SPI data frame format, the program

executive can erase, program and verify program

memory. For more information on Enhanced ICSP, see

the device programming specification.

The 1-row (96 bytes), 2-row (192 bytes) and 4-row

(384 bytes) erase blocks and single row write block

(96 bytes) are edge-aligned, from the beginning of

program memory.

5.4

Control Registers

When data is written to program memory using TBLWT

instructions, the data is not written directly to memory.

Instead, data written using table writes is stored in holding

latches until the programming sequence is executed.

There are two SFRs used to read and write the

program Flash memory: NVMCON and NVMKEY.

The NVMCON register (Register 5-1) controls the blocks

that need to be erased, which memory type is to be

programmed and when the programming cycle starts.

Any number of TBLWT instructions can be executed

and a write will be successfully performed. However,

32 TBLWTinstructions are required to write the full row

of memory.

NVMKEY is a write-only register that is used for write

protection. To start a programming or erase sequence,

the user must consecutively write 55h and AAh to the

NVMKEY register. For more information, refer to

Section 5.5 “Programming Operations”.

The basic sequence for RTSP programming is to set up

a Table Pointer, then do a series of TBLWTinstructions to

load the buffers. Programming is performed by setting

the control bits in the NVMCON register.

5.5

Programming Operations

Data can be loaded in any order and the holding regis-

ters can be written to multiple times before performing

a write operation. Subsequent writes, however, will

wipe out any previous writes.

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. During a programming or erase operation, the

processor stalls (waits) until the operation is finished.

Setting the WR bit (NVMCON<15>) starts the

operation and the WR bit is automatically cleared when

the operation is finished.

Note:

Writing to a location multiple times without

erasing it is not recommended.

All of the table write operations are single-word writes

(two instruction cycles), because only the buffers are writ-

ten. A programming cycle is required for programming

each row.

DS31037B-page 48

 2011 Microchip Technology Inc.

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REGISTER 5-1:

NVMCON: FLASH MEMORY CONTROL REGISTER

R/SO-0, HC

WR

R/W-0

PGMONLY⁽⁴⁾

U-0

—

U-0

—

U-0

—

U-0

—

WREN

WRERR

bit 15

bit 8

U-0

—

R/W-0

NVMOP5⁽¹⁾

R/W-0

NVMOP4⁽¹⁾

R/W-0

NVMOP1⁽¹⁾

R/W-0

NVMOP0⁽¹⁾

bit 0

ERASE

NVMOP3⁽¹⁾NVMOP2⁽¹⁾

bit 7

Legend:

SO = Settable Only bit

‘1’ = Bit is set

HC = Hardware Clearable bit

R = Readable bit

-n = Value at POR

‘0’ = Bit is cleared

W = Writable bit

x = Bit is unknown

U = Unimplemented bit, read as ‘0’

bit 15

WR: Write Control bit

1= Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once the operation is complete.

0= Program or erase operation is complete and inactive

bit 14

bit 13

WREN: Write Enable bit

1= Enable Flash program/erase operations

0= Inhibit Flash program/erase operations

WRERR: Write Sequence Error Flag bit

1= An improper program or erase sequence attempt, or termination, has occurred (bit is set automatically

on any set attempt of the WR bit)

0= The program or erase operation completed normally

bit 12

bit 11-7

bit 6

PGMONLY: Program Only Enable bit⁽⁴⁾

Unimplemented: Read as ‘0’

ERASE: Erase/Program Enable bit

1= Perform the erase operation specified by NVMOP<5:0> on the next WR command

0= Perform the program operation specified by NVMOP<5:0> on the next WR command

bit 5-0

NVMOP<5:0>: Programming Operation Command Byte bits⁽¹⁾

Erase operations (when ERASE bit is ‘1’):

1010xx= Erase entire boot block (including code-protected boot block)⁽²⁾

1001xx= Erase entire memory (including boot block, configuration block, general block)⁽²⁾

011010= Erase 4 rows of Flash memory⁽³⁾

011001= Erase 2 rows of Flash memory⁽³⁾

011000= Erase 1 row of Flash memory⁽³⁾

0101xx= Erase entire configuration block (except code protection bits)

0100xx= Erase entire data EEPROM⁽⁴⁾

0011xx= Erase entire general memory block programming operations

0001xx= Write 1 row of Flash memory (when ERASE bit is ‘0’)⁽³⁾

Note 1: All other combinations of the NVMOP<5:0> bits are no operation.

2: Available in ICSP™ mode only. Refer to the device programming specification.

3: The address in the Table Pointer decides which rows will be erased.

4: This bit is used only while accessing data EEPROM. It is implemented only in devices with data EEPROM.

 2011 Microchip Technology Inc.

DS31037B-page 49

PIC24F16KL402 FAMILY

4. Write the first 32 instructions from data RAM into

the program memory buffers (see Example 5-1).

5.5.1

PROGRAMMING ALGORITHM FOR

FLASH PROGRAM MEMORY

5. Write the program block to Flash memory:

The user can program one row of Flash program

memory at a time by erasing the programmable row.

The general process is as follows:

a) Set the NVMOP bits to ‘000100’ to

configure for row programming. Clear the

ERASE bit and set the WREN bit.

1. Read a row of program memory (32 instructions)

and store in data RAM.

b) Write 55h to NVMKEY.

c) Write AAh to NVMKEY.

2. Update the program data in RAM with the

desired new data.

d) Set the WR bit. The programming cycle

begins and the CPU stalls for the duration of

the write cycle. When the write to Flash

memory is done, the WR bit is cleared

automatically.

3. Erase a row (see Example 5-1):

a) Set the NVMOP bits (NVMCON<5:0>) to

‘011000’ to configure for row erase. Set the

ERASE (NVMCON<6>) and WREN

(NVMCON<14>) bits.

For protection against accidental operations, the write

initiate sequence for NVMKEY must be used to allow

any erase or program operation to proceed. After the

programming command has been executed, the user

must wait for the programming time until programming

is complete. The two instructions following the start of

the programming sequence should be NOPs, as shown

in Example 5-5.

b) Write the starting address of the block to be

erased into the TBLPAG and W registers.

c) Write 55h to NVMKEY.

d) Write AAh to NVMKEY.

e) Set the WR bit (NVMCON<15>). The erase

cycle begins and the CPU stalls for the

duration of the erase cycle. When the erase is

done, the WR bit is cleared automatically.

EXAMPLE 5-1:

ERASING A PROGRAM MEMORY ROW – ASSEMBLY LANGUAGE CODE

; Set up NVMCON for row erase operation

MOV

#0x4058, W0

W0, NVMCON

;

; Initialize NVMCON

; Init pointer to row to be ERASED

MOV

#tblpage(PROG_ADDR), W0

W0, TBLPAG

#tbloffset(PROG_ADDR), W0

;

; Initialize PM Page Boundary SFR

; Initialize in-page EA[15:0] pointer

; Set base address of erase block

; Block all interrupts

TBLWTL W0, [W0]

DISI

#5

for next 5 instructions

MOV

BSET

NOP

#0x55, W0

W0, NVMKEY

#0xAA, W1

W1, NVMKEY

NVMCON, #WR

; Write the 55 key

;

; Write the AA key

; Start the erase sequence

; Insert two NOPs after the erase

; command is asserted

DS31037B-page 50

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EXAMPLE 5-2:

ERASING A PROGRAM MEMORY ROW – ‘C’ LANGUAGE CODE

// C example using MPLAB C30

int __attribute__ ((space(auto_psv))) progAddr = &progAddr; // Global variable located in Pgm Memory

unsigned int offset;

//Set up pointer to the first memory location to be written

TBLPAG = __builtin_tblpage(&progAddr);

offset = &progAddr & 0xFFFF;

// Initialize PM Page Boundary SFR

// Initialize lower word of address

__builtin_tblwtl(offset, 0x0000);

// Set base address of erase block

// with dummy latch write

NVMCON = 0x4058;

// Initialize NVMCON

asm("DISI #5");

// Block all interrupts for next 5

// instructions

// C30 function to perform unlock

// sequence and set WR

__builtin_write_NVM();

EXAMPLE 5-3:

LOADING THE WRITE BUFFERS – ASSEMBLY LANGUAGE CODE

; Set up NVMCON for row programming operations

MOV

#0x4004, W0

W0, NVMCON

;

; Initialize NVMCON

; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled

MOV

#0x0000, W0

W0, TBLPAG

#0x6000, W0

;

; Initialize PM Page Boundary SFR

; An example program memory address

; Perform the TBLWT instructions to write the latches

; 0th_program_word

MOV

#LOW_WORD_0, W2

#HIGH_BYTE_0, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

; 1st_program_word

MOV

#LOW_WORD_1, W2

#HIGH_BYTE_1, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

; 2nd_program_word

MOV

#LOW_WORD_2, W2

#HIGH_BYTE_2, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

•

; 32nd_program_word

MOV

#LOW_WORD_31, W2

#HIGH_BYTE_31, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0]

; Write PM low word into program latch

; Write PM high byte into program latch

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EXAMPLE 5-4:

LOADING THE WRITE BUFFERS – ‘C’ LANGUAGE CODE

// C example using MPLAB C30

#define NUM_INSTRUCTION_PER_ROW 64

int __attribute__ ((space(auto_psv))) progAddr = &progAddr; // Global variable located in Pgm Memory

unsigned int offset;

unsigned int i;

unsigned int progData[2*NUM_INSTRUCTION_PER_ROW];

// Buffer of data to write

// Initialize NVMCON

//Set up NVMCON for row programming

NVMCON = 0x4004;

//Set up pointer to the first memory location to be written

TBLPAG = __builtin_tblpage(&progAddr);

offset = &progAddr & 0xFFFF;

// Initialize PM Page Boundary SFR

// Initialize lower word of address

//Perform TBLWT instructions to write necessary number of latches

for(i=0; i < 2*NUM_INSTRUCTION_PER_ROW; i++)

{

__builtin_tblwtl(offset, progData[i++]);

__builtin_tblwth(offset, progData[i]);

offset = offset + 2;

// Write to address low word

// Write to upper byte

// Increment address

}

EXAMPLE 5-5:

INITIATING A PROGRAMMING SEQUENCE – ASSEMBLY LANGUAGE CODE

DISI

#5

; Block all interrupts

for next 5 instructions

MOV

BSET

NOP

BTSC

BRA

#0x55, W0

W0, NVMKEY

#0xAA, W1

W1, NVMKEY

NVMCON, #WR

; Write the 55 key

;

; Write the AA key

; Start the erase sequence

; 2 NOPs required after setting WR

;

; Wait for the sequence to be completed

;

NVMCON, #15

$-2

EXAMPLE 5-6:

INITIATING A PROGRAMMING SEQUENCE – ‘C’ LANGUAGE CODE

// C example using MPLAB C30

asm("DISI #5");

// Block all interrupts for next 5 instructions

// Perform unlock sequence and set WR

__builtin_write_NVM();

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6.1

NVMCON Register

6.0

DATA EEPROM MEMORY

The NVMCON register (Register 6-1) is also the primary

control register for data EEPROM program/erase

operations. The upper byte contains the control bits

used to start the program or erase cycle, and the flag bit

to indicate if the operation was successfully performed.

The lower byte of NVMCOM configures the type of NVM

operation that will be performed.

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. For more information on

Data EEPROM, refer to the “PIC24F

Family Reference Manual”, Section 5.

“Data EEPROM” (DS39720).

The data EEPROM memory is a Nonvolatile Memory

(NVM), separate from the program and volatile data

RAM. Data EEPROM memory is based on the same

Flash technology as program memory, and is optimized

for both long retention and a higher number of

erase/write cycles.

6.2

NVMKEY Register

The NVMKEY is a write-only register that is used to

prevent accidental writes or erasures of data EEPROM

locations.

To start any programming or erase sequence, the

following instructions must be executed first, in the

exact order provided:

The data EEPROM is mapped to the top of the user pro-

gram memory space, with the top address at program

memory address, 7FFFFFh. For PIC24FXXKL4XX

devices, the size of the data EEPROM is 256 words

(7FFE00h to 7FFFFFh). For PIC24FXXKL3XX devices,

the size of the data EEPROM is 128 words (7FFF00h to

7FFFFFh). The data EEPROM is not implemented in

PIC24F08KL20X or PIC24F04KL10X devices.

1. Write 55h to NVMKEY.

2. Write AAh to NVMKEY.

After this sequence, a write will be allowed to the

NVMCON register for one instruction cycle. In most

cases, the user will simply need to set the WR bit in the

NVMCON register to start the program or erase cycle.

Interrupts should be disabled during the unlock

sequence.

The MPLAB^®C30 C compiler provides a defined library

procedure (builtin_write_NVM) to perform the

unlock sequence. Example 6-1 illustrates how the

unlock sequence can be performed with in-line

assembly.

The data EEPROM is organized as 16-bit wide

memory. Each word is directly addressable, and is

readable and writable during normal operation over the

entire VDD range.

Unlike the Flash program memory, normal program

execution is not stopped during a data EEPROM

program or erase operation.

The data EEPROM programming operations are

controlled using the three NVM Control registers:

• NVMCON: Nonvolatile Memory Control Register

• NVMKEY: Nonvolatile Memory Key Register

• NVMADR: Nonvolatile Memory Address Register

EXAMPLE 6-1:

DATA EEPROM UNLOCK SEQUENCE

//Disable Interrupts For 5 instructions

asm volatile("disi #5");

//Issue Unlock Sequence

asm volatile("mov #0x55, W0

"mov W0, NVMKEY

\n"

"mov #0xAA, W1

\n"

"mov W1, NVMKEY

\n");

// Perform Write/Erase operations

asm volatile ("bset NVMCON, #WR

"nop

\n"

"nop

\n");

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REGISTER 6-1:

NVMCON: NONVOLATILE MEMORY CONTROL REGISTER

R/S-0, HC

WR

R/W-0

WREN

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

WRERR

PGMONLY

bit 15

bit 8

U-0

—

R/W-0

ERASE

NVMOP5⁽¹⁾NVMOP4⁽¹⁾NVMOP3⁽¹⁾NVMOP2⁽¹⁾NVMOP1⁽¹⁾NVMOP0⁽¹⁾

bit 7

bit 0

Legend:

HC = Hardware Clearable

W = Writable bit

U = Unimplemented bit, read as ‘0’

S = Settable bit

R = Readable bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

bit 14

bit 13

WR: Write Control bit (program or erase)

1= Initiates a data EEPROM erase or write cycle (can be set but not cleared in software)

0= Write cycle is complete (cleared automatically by hardware)

WREN: Write Enable bit (erase or program)

1= Enable an erase or program operation

0= No operation allowed (device clears this bit on completion of the write/erase operation)

WRERR: Flash Error Flag bit

1= A write operation is prematurely terminated (any MCLR or WDT Reset during programming

operation)

0= The write operation completed successfully

bit 12

PGMONLY: Program Only Enable bit

1= Write operation is executed without erasing target address(es) first

0= Automatic erase-before-write. Write operations are preceded automatically by an erase of target

address(es).

bit 11-7

bit 6

Unimplemented: Read as ‘0’

ERASE: Erase Operation Select bit

1= Perform an erase operation when WR is set

0= Perform a write operation when WR is set

bit 5-0

NVMOP<5:0>: Programming Operation Command Byte bits⁽¹⁾

Erase Operations (when ERASE bit is ‘1’):

011010= Erase 8 words

011001= Erase 4 words

011000= Erase 1 word

0100xx= Erase entire data EEPROM

Programming Operations (when ERASE bit is ‘0’):

001xxx= Write 1 word

Note 1: These NVMOP configurations are unimplemented on PIC24F04KL10X and PIC24F08KL20X devices.

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Like program memory operations, the Least Significant

bit (LSb) of NVMADR is restricted to even addresses.

This is because any given address in the data

EEPROM space consists of only the lower word of the

program memory width; the upper word, including the

uppermost “phantom byte”, is unavailable. This means

that the LSb of a data EEPROM address will always be

‘0’.

6.3

NVM Address Register

As with Flash program memory, the NVM Address

Registers, NVMADRU and NVMADR, form the 24-bit

Effective Address (EA) of the selected row or word for

data EEPROM operations. The NVMADRU register is

used to hold the upper 8 bits of the EA, while the

NVMADR register is used to hold the lower 16 bits of

the EA. These registers are not mapped into the

Special Function Register (SFR) space; instead, they

directly capture the EA<23:0> of the last table write

instruction that has been executed and selects the data

EEPROM row to erase. Figure 6-1 depicts the program

memory EA that is formed for programming and erase

operations.

Similarly, the Most Significant bit (MSb) of NVMADRU

is always ‘0’, since all addresses lie in the user program

space.

FIGURE 6-1:

DATA EEPROM ADDRESSING WITH TBLPAG AND NVM ADDRESS REGISTERS

24-Bit PM Address

7Fh

xxxxh

0

TBLPAG

W Register EA

NVMADRU

NVMADR

6.4

Data EEPROM Operations

Note:

Unexpected results will be obtained if the

user attempts to read the EEPROM while

a programming or erase operation is

underway.

The EEPROM block is accessed using table read and

write operations, similar to those used for program

memory. The TBLWTHand TBLRDHinstructions are not

required for data EEPROM operations since the

memory is only 16 bits wide (data on the lower address

is valid only). The following programming operations

can be performed on the data EEPROM:

The C30 C compiler includes library

procedures to automatically perform the

table read and table write operations,

manage the Table Pointer and write

buffers, and unlock and initiate memory

write sequences. This eliminates the need

to create assembler macros or time

critical routines in C for each application.

• Erase one, four or eight words

• Bulk erase the entire data EEPROM

• Write one word

• Read one word

The library procedures are used in the code examples

detailed in the following sections. General descriptions

of each process are provided for users who are not

using the C30 compiler libraries.

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A typical erase sequence is provided in Example 6-2.

This example shows how to do a one-word erase.

Similarly, a four-word erase and an eight-word erase

can be done. This example uses C library procedures to

manage the Table Pointer (builtin_tblpage and

builtin_tbloffset) and the Erase Page Pointer

(builtin_tblwtl). The memory unlock sequence

(builtin_write_NVM) also sets the WR bit to initiate

the operation and returns control when complete.

6.4.1

ERASE DATA EEPROM

The data EEPROM can be fully erased, or can be

partially erased, at three different sizes: one word, four

words or eight words. The bits, NVMOP<1:0>

(NVMCON<1:0>), decide the number of words to be

erased. To erase partially from the data EEPROM, the

following sequence must be followed:

1. Configure NVMCON to erase the required

number of words: one, four or eight.

2. Load TBLPAG and WREG with the EEPROM

address to be erased.

3. Clear NVMIF status bit and enable the NVM

interrupt (optional).

4. Write the key sequence to NVMKEY.

5. Set the WR bit to begin erase cycle.

6. Either poll the WR bit or wait for the NVM

interrupt (NVMIF is set).

EXAMPLE 6-2:

SINGLE-WORD ERASE

int __attribute__ ((space(eedata))) eeData = 0x1234; // Global variable located in EEPROM

unsigned int offset;

// Set up NVMCON to erase one word of data EEPROM

NVMCON = 0x4058;

// Set up a pointer to the EEPROM location to be erased

TBLPAG = __builtin_tblpage(&eeData);

offset = __builtin_tbloffset(&eeData);

__builtin_tblwtl(offset, 0);

// Initialize EE Data page pointer

// Initizlize lower word of address

// Write EEPROM data to write latch

asm volatile ("disi #5");

__builtin_write_NVM();

while(NVMCONbits.WR=1);

// Disable Interrupts For 5 Instructions

// Issue Unlock Sequence & Start Write Cycle

// Optional: Poll WR bit to wait for

// write sequence to complete

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6.4.1.1

Data EEPROM Bulk Erase

6.4.2

SINGLE-WORD WRITE

To erase the entire data EEPROM (bulk erase), the

address registers do not need to be configured

because this operation affects the entire data

EEPROM. The following sequence helps in performing

a bulk erase:

To write a single word in the data EEPROM, the

following sequence must be followed:

1. Erase one data EEPROM word (as mentioned in

Section 6.4.1, Erase Data EEPROM) if

PGMONLY bit (NVMCON<12>) is set to ‘1’.

1. Configure NVMCON to Bulk Erase mode.

2. Write the data word into the data EEPROM

latch.

2. Clear NVMIF status bit and enable NVM

interrupt (optional).

3. Program the data word into the EEPROM:

3. Write the key sequence to NVMKEY.

4. Set the WR bit to begin erase cycle.

- Configure the NVMCON register to program one

EEPROM word (NVMCON<5:0> = 0001xx).

- Clear NVMIF status bit and enable NVM

interrupt (optional).

5. Either poll the WR bit or wait for the NVM

interrupt (NVMIF is set).

- Write the key sequence to NVMKEY.

- Set the WR bit to begin erase cycle.

- Either poll the WR bit or wait for the NVM

interrupt (NVMIF set).

A

typical bulk erase sequence is provided in

Example 6-3.

- To get cleared, wait until NVMIF is set.

A typical single-word write sequence is provided in

Example 6-4.

EXAMPLE 6-3:

DATA EEPROM BULK ERASE

// Set up NVMCON to bulk erase the data EEPROM

NVMCON = 0x4050;

// Disable Interrupts For 5 Instructions

asm volatile ("disi #5");

// Issue Unlock Sequence and Start Erase Cycle

__builtin_write_NVM();

EXAMPLE 6-4:

SINGLE-WORD WRITE TO DATA EEPROM

int __attribute__ ((space(eedata))) eeData = 0x1234; // Global variable located in EEPROM

int newData;

// New data to write to EEPROM

unsigned int offset;

// Set up NVMCON to erase one word of data EEPROM

NVMCON = 0x4004;

// Set up a pointer to the EEPROM location to be erased

TBLPAG = __builtin_tblpage(&eeData);

offset = __builtin_tbloffset(&eeData);

__builtin_tblwtl(offset, newData);

// Initialize EE Data page pointer

// Initizlize lower word of address

// Write EEPROM data to write latch

asm volatile ("disi #5");

__builtin_write_NVM();

while(NVMCONbits.WR=1);

// Disable Interrupts For 5 Instructions

// Issue Unlock Sequence & Start Write Cycle

// Optional: Poll WR bit to wait for

// write sequence to complete

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A

typical read sequence, using the Table

6.4.3

READING THE DATA EEPROM

Pointer management

builtin_tbloffset)

(builtin_tblrdl) procedures from the C30

compiler library, is provided in Example 6-5.

(builtin_tblpage

and table

and

read

To read a word from data EEPROM, the table read

instruction is used. Since the EEPROM array is only

16 bits wide, only the TBLRDL instruction is needed.

The read operation is performed by loading TBLPAG

and WREG with the address of the EEPROM location

followed by a TBLRDLinstruction.

Program Space Visibility (PSV) can also be used to

read locations in the data EEPROM.

EXAMPLE 6-5:

READING THE DATA EEPROM USING THE TBLRDCOMMAND

int __attribute__ ((space(eedata))) eeData = 0x1234;

// Global variable located in EEPROM

// Data read from EEPROM

int data;

unsigned int offset;

// Set up a pointer to the EEPROM location to be erased

TBLPAG = __builtin_tblpage(&eeData);

offset = __builtin_tbloffset(&eeData);

data = __builtin_tblrdl(offset);

// Initialize EE Data page pointer

// Initizlize lower word of address

// Write EEPROM data to write latch

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Any active source of Reset will make the SYSRST

signal active. Many registers associated with the CPU

and peripherals are forced to a known Reset state.

Most registers are unaffected by a Reset; their status is

unknown on Power-on Reset (POR) and unchanged by

all other Resets.

7.0

RESETS

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be

reference source. For more information

on Resets, refer to the “PIC24F Family

Reference Manual”, Section 40. “Reset

with Programmable Brown-out Reset”

(DS39728).

a

comprehensive

Note:

Refer to the specific peripheral or CPU

section of this manual for register Reset

states.

All types of device Reset will set a corresponding status

bit in the RCON register to indicate the type of Reset

(see Register 7-1). A POR will clear all bits except for

the BOR and POR bits (RCON<1:0>) which are set.

The user may set or clear any bit at any time during

code execution. The RCON bits only serve as status

bits. Setting a particular Reset status bit in software will

not cause a device Reset to occur.

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

• POR: Power-on Reset

• MCLR: Pin Reset

• SWR: RESETInstruction

• WDTR: Watchdog Timer Reset

• BOR: Brown-out Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Opcode Reset

• UWR: Uninitialized W Register Reset

The RCON register also has other bits associated with

the Watchdog Timer (WDT) and device power-saving

states. The function of these bits is discussed in other

sections of this manual.

A simplified block diagram of the Reset module is

shown in Figure 7-1.

Note:

The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value, after a

device Reset, will be meaningful.

FIGURE 7-1:

RESET SYSTEM BLOCK DIAGRAM

RESET

Instruction

Glitch Filter

MCLR

WDT

Module

Sleep or Idle

POR

VDD Rise

Detect

SYSRST

VDD

BOREN<1:0>

Brown-out

Reset

00

0

BOR

SBOREN

01

10

SLEEP

11

1

Configuration Mismatch

Trap Conflict

Illegal Opcode

Uninitialized W Register

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REGISTER 7-1:

RCON: RESET CONTROL REGISTER⁽¹⁾

R/W-0

R/W-0⁽³⁾

U-0

—

U-0

—

U-0

—

R/W-0

CM

R/W-0

TRAPR

bit 15

IOPUWR

SBOREN

PMSLP

bit 8

R/W-0

EXTR

R/W-0

SWR

R/W-0

SWDTEN⁽²⁾

R/W-0

WDTO

R/W-0

IDLE

R/W-1

BOR

R/W-1

POR

SLEEP

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

TRAPR: Trap Reset Flag bit

1= A Trap Conflict Reset has occurred

0= A Trap Conflict Reset has not occurred

IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit

1= An illegal opcode detection, an illegal address mode or an uninitialized W register is used as an

Address Pointer and caused a Reset

0= An illegal opcode or uninitialized W Reset has not occurred

bit 13

SBOREN: Software Enable/Disable of BOR bit⁽³⁾

1= BOR is turned on in software

0= BOR is turned off in software

bit 12-10

bit 9

Unimplemented: Read as ‘0’

CM: Configuration Word Mismatch Reset Flag bit

1= A Configuration Word Mismatch Reset has occurred

0= A Configuration Word Mismatch Reset has not occurred

bit 8

PMSLP: Program Memory Power During Sleep bit

1= Program memory bias voltage remains powered during Sleep

0= Program memory bias voltage is powered down during Sleep

EXTR: External Reset (MCLR) Pin bit

bit 7

bit 6

bit 5

bit 4

1= A Master Clear (pin) Reset has occurred

0= A Master Clear (pin) Reset has not occurred

SWR: Software Reset (Instruction) Flag bit

1= A RESETinstruction has been executed

0= A RESETinstruction has not been executed

SWDTEN: Software Enable/Disable of WDT bit⁽²⁾

1= WDT is enabled

0= WDT is disabled

WDTO: Watchdog Timer Time-out Flag bit

1= WDT time-out has occurred

0= WDT time-out has not occurred

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

3: The SBOREN bit is forced to ‘0’ when disabled by the Configuration bits, BOREN<1:0> (FPOR<1:0>).

When the Configuration bits are set to enable SBOREN, the default Reset state will be ‘1’.

DS31037B-page 60

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REGISTER 7-1:

RCON: RESET CONTROL REGISTER⁽¹⁾(CONTINUED)

bit 3

bit 2

bit 1

bit 0

SLEEP: Wake-up from Sleep Flag bit

1= Device has been in Sleep mode

0= Device has not been in Sleep mode

IDLE: Wake-up from Idle Flag bit

1= Device has been in Idle mode

0= Device has not been in Idle mode

BOR: Brown-out Reset Flag bit

1= A Brown-out Reset has occurred (the BOR is also set after a POR)

0= A Brown-out Reset has not occurred

POR: Power-on Reset Flag bit

1= A Power-up Reset has occurred

0= A Power-up Reset has not occurred

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

3: The SBOREN bit is forced to ‘0’ when disabled by the Configuration bits, BOREN<1:0> (FPOR<1:0>).

When the Configuration bits are set to enable SBOREN, the default Reset state will be ‘1’.

TABLE 7-1:

RESET FLAG BIT OPERATION

Setting Event

Flag Bit

Clearing Event

TRAPR (RCON<15>)

IOPUWR (RCON<14>)

CM (RCON<9>)

Trap Conflict Event

POR

Illegal Opcode or Uninitialized W Register Access

Configuration Mismatch Reset

MCLR Reset

POR

EXTR (RCON<7>)

SWR (RCON<6>)

WDTO (RCON<4>)

SLEEP (RCON<3>)

IDLE (RCON<2>)

BOR (RCON<1>)

POR (RCON<0>)

POR

RESETInstruction

POR

WDT Time-out

PWRSAVInstruction, POR

PWRSAV #SLEEPInstruction

PWRSAV #IDLEInstruction

POR, BOR

POR

—

POR

—

Note: All Reset flag bits may be set or cleared by the user software.

TABLE 7-2:

OSCILLATOR SELECTION vs.

TYPE OF RESET (CLOCK

SWITCHING ENABLED)

7.1

Clock Source Selection at Reset

If clock switching is enabled, the system clock source at

device Reset is chosen, as shown in Table 7-2. If clock

switching is disabled, the system clock source is always

selected according to the oscillator Configuration bits.

For more information, see Section 9.0 “Oscillator

Configuration”.

Reset Type

Clock Source Determinant

POR

BOR

FNOSC Configuration bits

(FNOSC<10:8>)

MCLR

WDTO

SWR

COSC Control bits

(OSCCON<14:12>)

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The FSCM delay determines the time at which the

FSCM begins to monitor the system clock source after

the SYSRST signal is released.

7.2

Device Reset Times

The Reset times for various types of device Reset are

summarized in Table 7-3. Note that the system Reset

signal, SYSRST, is released after the POR and PWRT

delay times expire.

The time at which the device actually begins to execute

code will also depend on the system oscillator delays,

which include the Oscillator Start-up Timer (OST) and

the PLL lock time. The OST and PLL lock times occur

in parallel with the applicable SYSRST delay times.

TABLE 7-3:

Reset Type

POR⁽⁶⁾

RESET DELAY TIMES FOR VARIOUS DEVICE RESETS

System Clock

Clock Source

SYSRST Delay

Notes

Delay

EC

TPOR + TPWRT

TPOR+ TPWRT

TPOR + TPWRT

TPWRT

—

1, 2

FRC, FRCDIV

LPRC

TFRC

TLPRC

TLOCK

1, 2, 3

1, 2, 4

ECPLL

FRCPLL

TFRC + TLOCK 1, 2, 3, 4

TOST 1, 2, 5

TOST + TLOCK 1, 2, 4, 5

XT, HS, SOSC

XTPLL, HSPLL

EC

BOR

—

2

FRC, FRCDIV

LPRC

TPWRT

TFRC

TLPRC

TLOCK

2, 3

2, 4

TPWRT

ECPLL

TPWRT

FRCPLL

TPWRT

TFRC + TLOCK 2, 3, 4

TOST 2, 5

TFRC + TLOCK 2, 3, 4

None

XT, HS, SOSC

XTPLL, HSPLL

Any Clock

TPWRT

All Others

—

Note 1: TPOR = Power-on Reset delay.

2: TPWRT = 64 ms nominal if the Power-up Timer is enabled; otherwise, it is zero.

3: TFRC and TLPRC = RC oscillator start-up times.

4: TLOCK = PLL lock time.

5: TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the

oscillator clock to the system.

6: If Two-Speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with

FRC, and in such cases, FRC start-up time is valid.

Note: For detailed operating frequency and timing specifications, see Section 26.0 “Electrical Characteristics”.

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PIC24F16KL402 FAMILY

7.2.1

POR AND LONG OSCILLATOR

START-UP TIMES

7.4

Brown-out Reset (BOR)

PIC24F16KL402 family devices implement a BOR

circuit, which provides the user several configuration

and power-saving options. The BOR is controlled by

the BORV<1:0> and BOREN<1:0> Configuration bits

(FPOR<6:5,1:0>). There are a total of four BOR

configurations, which are provided in Table 7-3.

The oscillator start-up circuitry and its associated delay

timers are not linked to the device Reset delays that

occur at power-up. Some crystal circuits (especially

low-frequency crystals) will have a relatively long

start-up time. Therefore, one or more of the following

conditions is possible after SYSRST is released:

The BOR threshold is set by the BORV<1:0> bits. If

BOR is enabled (any values of BOREN<1:0>, except

‘00’), any drop of VDD below the set threshold point will

reset the device. The chip will remain in BOR until VDD

rises above the threshold.

• The oscillator circuit has not begun to oscillate.

• The Oscillator Start-up Timer (OST) has not

expired (if a crystal oscillator is used).

• The PLL has not achieved a lock (if PLL is used).

If the Power-up Timer is enabled, it will be invoked after

VDD rises above the threshold. Then, it will keep the chip

in Reset for an additional time delay, TPWRT, if VDD

drops below the threshold while the power-up timer is

running. The chip goes back into a BOR and the

Power-up Timer will be initialized. Once VDD rises above

the threshold, the Power-up Timer will execute the

additional time delay.

The device will not begin to execute code until a valid

clock source has been released to the system.

Therefore, the oscillator and PLL start-up delays must

be considered when the Reset delay time must be

known.

7.2.2

FAIL-SAFE CLOCK MONITOR

(FSCM) AND DEVICE RESETS

BOR and the Power-up Timer (PWRT) are indepen-

dently configured. Enabling the BOR Reset does not

automatically enable the PWRT.

If the FSCM is enabled, it will begin to monitor the

system clock source when SYSRST is released. If a

valid clock source is not available at this time, the

device will automatically switch to the FRC oscillator

and the user can switch to the desired crystal oscillator

in the Trap Service Routine (TSR).

7.4.1

SOFTWARE ENABLED BOR

When BOREN<1:0> = 01, the BOR can be enabled or

disabled by the user in software. This is done with the

control bit, SBOREN (RCON<13>). Setting SBOREN

enables the BOR to function, as previously described.

Clearing the SBOREN disables the BOR entirely. The

SBOREN bit only operates in this mode; otherwise, it is

read as ‘0’.

7.3

Special Function Register Reset

States

Most of the Special Function Registers (SFRs)

associated with the PIC24F CPU and peripherals are

reset to a particular value at a device Reset. The SFRs

are grouped by their peripheral or CPU function and their

Reset values are specified in each section of this manual.

Placing BOR under software control gives the user the

additional flexibility of tailoring the application to its

environment without having to reprogram the device to

change the BOR configuration. It also allows the user

to tailor the incremental current that the BOR

consumes. While the BOR current is typically very

small, it may have some impact in low-power

applications.

The Reset value for each SFR does not depend on the

type of Reset, with the exception of four registers. The

Reset value for the Reset Control register, RCON, will

depend on the type of device Reset. The Reset value

for the Oscillator Control register, OSCCON, will

depend on the type of Reset and the programmed

values of the FNOSC bits in the Flash Configuration

Word (FOSCSEL); see Table 7-2. The RCFGCAL and

NVMCON registers are only affected by a POR.

Note:

Even when the BOR is under software

control, the BOR Reset voltage level is still

set by the BORV<1:0> Configuration bits;

it can not be changed in software.

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7.4.2

DETECTING BOR

7.4.3

DISABLING BOR IN SLEEP MODE

When BOR is enabled, the BOR bit (RCON<1>) is

always reset to ‘1’ on any BOR or POR event. This

makes it difficult to determine if a BOR event has

occurred just by reading the state of BOR alone. A

more reliable method is to simultaneously check the

state of both POR and BOR. This assumes that the

POR and BOR bits are reset to ‘0’ in the software,

immediately after any POR event. If the BOR bit is ‘1’

while POR is ‘0’, it can be reliably assumed that a BOR

event has occurred.

When BOREN<1:0> = 10, BOR remains under

hardware control and operates as previously

described. However, whenever the device enters Sleep

mode, BOR is automatically disabled. When the device

returns to any other operating mode, BOR is

automatically re-enabled.

This mode allows for applications to recover from

brown-out situations, while actively executing code

when the device requires BOR protection the most. At

the same time, it saves additional power in Sleep mode

by eliminating the small incremental BOR current.

Note: Even when the device exits from Deep Sleep

mode, both the POR and BOR are set.

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8.1.1

ALTERNATE INTERRUPT VECTOR

TABLE (AIVT)

8.0

INTERRUPT CONTROLLER

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

The Alternate Interrupt Vector Table (AIVT) is located

after the IVT, as shown in Figure 8-1. Access to the

AIVT is provided by the ALTIVT control bit

(INTCON2<15>). If the ALTIVT bit is set, all interrupt

and exception processes will use the alternate vectors

instead of the default vectors. The alternate vectors are

organized in the same manner as the default vectors.

intended to be

a

comprehensive

reference source. For more information

on the Interrupt Controller, refer to the

“PIC24F Family Reference Manual”,

Section 8. “Interrupts” (DS39707).

The PIC24F interrupt controller reduces the numerous

peripheral interrupt request signals to a single interrupt

request signal to the CPU. It has the following features:

The AIVT supports emulation and debugging efforts by

providing a means to switch between an application

and a support environment without requiring the

interrupt vectors to be reprogrammed. This feature also

enables switching between applications for evaluation

of different software algorithms at run time. If the AIVT

is not needed, the AIVT should be programmed with

the same addresses used in the IVT.

• Up to eight processor exceptions and

software traps

• Seven user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• Unique vector for each interrupt or exception

source

• Fixed priority within a specified user priority level

• Alternate Interrupt Vector Table (AIVT) for debug

support

8.2

Reset Sequence

A device Reset is not a true exception, because the

interrupt controller is not involved in the Reset process.

The PIC24F devices clear their registers in response to

a Reset, which forces the Program Counter (PC) to

zero. The microcontroller then begins program

execution at location, 000000h. The user programs a

GOTOinstruction at the Reset address, which redirects

the program execution to the appropriate start-up

routine.

• Fixed interrupt entry and return latencies

8.1

Interrupt Vector Table (IVT)

The IVT is shown in Figure 8-1. The IVT resides in the

program memory, starting at location, 000004h. The

IVT contains 126 vectors, consisting of eight

non-maskable trap vectors, plus up to 118 sources of

interrupt. In general, each interrupt source has its own

vector. Each interrupt vector contains a 24-bit wide

address. The value programmed into each interrupt

vector location is the starting address of the associated

Interrupt Service Routine (ISR).

Note:

Any unimplemented or unused vector

locations in the IVT and AIVT should be

programmed with the address of a default

interrupt handler routine that contains a

RESETinstruction.

Interrupt vectors are prioritized in terms of their natural

priority; this is linked to their position in the vector table.

All other things being equal, lower addresses have a

higher natural priority. For example, the interrupt

associated with vector 0 will take priority over interrupts

at any other vector address.

PIC24F16KL402

family

devices

implement

32 non-maskable traps and unique interrupts; these

are summarized in Table 8-1 and Table 8-2.

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FIGURE 8-1:

PIC24F INTERRUPT VECTOR TABLE

Reset – GOTOInstruction

Reset – GOTOAddress

Reserved

000000h

000002h

000004h

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

Interrupt Vector 0

Interrupt Vector 1

—

000014h

—

(1)

Interrupt Vector Table (IVT)

Interrupt Vector 52

Interrupt Vector 53

Interrupt Vector 54

—

00007Ch

00007Eh

000080h

—

Interrupt Vector 116

Interrupt Vector 117

Reserved

0000FCh

0000FEh

000100h

000102h

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

Interrupt Vector 0

Interrupt Vector 1

—

000114h

(1)

Alternate Interrupt Vector Table (AIVT)

—

Interrupt Vector 52

Interrupt Vector 53

Interrupt Vector 54

—

00017Ch

00017Eh

000180h

—

Interrupt Vector 116

Note 1: See Table 8-2 for the interrupt vector list.

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TABLE 8-1:

TRAP VECTOR DETAILS

IVT Address

Vector Number

AIVT Address

Trap Source

0

1

2

3

4

5

6

7

000004h

000006h

000008h

00000Ah

00000Ch

00000Eh

000010h

000012h

000104h

000106h

000108h

00010Ah

00010Ch

00010Eh

000110h

000112h

Reserved

Oscillator Failure

Address Error

Stack Error

Math Error

Reserved

TABLE 8-2:

IMPLEMENTED INTERRUPT VECTORS

Interrupt Bit Locations

Enable

Vector

Number

Interrupt Source

IVT Address AIVT Address

Flag

Priority

ADC1 Conversion Done

Comparator Event

13

18

0

00002Eh

000038h

000014h

00003Ch

00004Eh

000036h

000034h

000078h

000076h

00003Ah

0000A4h

000032h

000018h

000020h

000046h

00001Ah

000022h

000024h

00004Ah

00005Eh

000096h

00002Ah

00002Ch

000098h

000050h

000052h

0000B4h

00012Eh

IFS0<13>

IEC0<13>

IEC1<2>

IEC0<0>

IEC1<4>

IEC1<13>

IEC1<1>

IEC1<0>

IEC3<2>

IEC3<1>

IEC1<3>

IEC4<8>

IEC0<15>

IEC0<2>

IEC0<6>

IEC1<9>

IEC0<3>

IEC0<7>

IEC0<8>

IEC1<11>

IEC2<5>

IEC4<1>

IEC0<11>

IEC0<12>

IEC4<2>

IEC1<14>

IEC1<15>

IEC5<0>

IPC3<6:4>

IPC4<10:8>

IPC0<2:0>

000138h

000114h

00013Ch

00014Eh

000136h

000134h

000178h

000176h

00013Ah

0001A4h

000132h

000118h

000120h

000146h

00011Ah

000122h

000124h

00014Ah

00015Eh

000196h

00012Ah

00012Ch

000198h

000150h

000152h

0001B4h

IFS1<2>

IFS0<0>

IFS1<4>

IFS1<13>

IFS1<1>

IFS1<0>

IFS3<2>

IFS3<1>

IFS1<3>

IFS4<8>

IFS0<15>

IFS0<2>

IFS0<6>

IFS1<9>

IFS0<3>

IFS0<7>

IFS0<8>

IFS1<11>

IFS2<5>

IFS4<1>

IFS0<11>

IFS0<12>

IFS4<2>

IFS1<14>

IFS1<15>

IFS5<0>

External Interrupt 0

External Interrupt 1

20

29

17

16

50

49

19

72

15

2

IPC5<2:0>

External Interrupt 2

IPC7<6:4>

MSSP1 Bus Collision Event

IPC4<6:4>

2

MSSP1 SPI or I C™ Event

IPC4<2:0>

MSSP2 Bus Collision Event

IPC12<10:8>

IPC12<6:4>

IPC4<14:12>

IPC17<2:0>

IPC3<14:12>

IPC0<10:8>

IPC1<10:8>

IPC6<6:4>

2

MSSP2 SPI or I C Event

Input Change Notification

HLVD (High/Low-Voltage Detect)

NVM (NVM Write Complete)

CCP1/ECCP1

CCP2

6

CCP3

25

3

Timer1

IPC0<14:12>

IPC1<14:12>

IPC2<2:0>

Timer2

7

Timer3

8

Timer4

27

37

65

11

12

66

30

31

80

IPC6<14:12>

IPC9<6:4>

Timer3 Gate External Count

UART1 Error

IPC16<6:4>

IPC2<14:12>

IPC3<2:0>

UART1 Receiver

UART1 Transmitter

UART2 Error

IPC16<10:8>

IPC7<10:8>

IPC7<14:12>

IPC20<2:0>

UART2 Receiver

UART2 Transmitter

ULPW (Ultra Low-Power Wake-up)

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The INTTREG register contains the associated

interrupt vector number and the new CPU Interrupt

Priority Level, which are latched into the Vector

Number (VECNUM<6:0>) and the Interrupt Level

(ILR<3:0>) bit fields in the INTTREG register. The new

Interrupt Priority Level is the priority of the pending

interrupt.

8.3

Interrupt Control and Status

Registers

Depending

on

the

particular

device,

the

PIC24F16KL402 family of devices implements up to

28 registers for the interrupt controller:

• INTCON1

• INTCON2

The interrupt sources are assigned to the IFSx, IECx

and IPCx registers in the same sequence listed in

Table 8-2. For example, the INT0 (External Interrupt 0)

is depicted as having a vector number and a natural

order priority of 0. The INT0IF status bit is found in

IFS0<0>, the INT0IE enable bit in IEC0<0> and the

INT0IP<2:0> priority bits are in the first position of IPC0

(IPC0<2:0>).

• IFS0 through IFS5

• IEC0 through IEC5

• IPC0 through IPC7, ICP9, IPC12, ICP16, ICP18

and IPC20

• INTTREG

Global interrupt control functions are controlled from

INTCON1 and INTCON2. INTCON1 contains the

Interrupt Nesting Disable (NSTDIS) bit, as well as the

control and status flags for the processor trap sources.

The INTCON2 register controls the external interrupt

request signal behavior and the use of the AIV table.

Although they are not specifically part of the interrupt

control hardware, two of the CPU control registers

contain bits that control interrupt functionality. The ALU

STATUS Register (SR) contains the IPL<2:0> bits

(SR<7:5>). These indicate the current CPU Interrupt

Priority Level. The user may change the current CPU

priority level by writing to the IPL bits.

The IFSx registers maintain all of the interrupt request

flags. Each source of interrupt has a status bit, which is

set by the respective peripherals or external signal, and

is cleared via software.

The CORCON register contains the IPL3 bit, which

together with the IPL<2:0> bits, also indicates the cur-

rent CPU priority level. IPL3 is a read-only bit so that

the trap events cannot be masked by the user’s

software.

The IECx registers maintain all of the interrupt enable

bits. These control bits are used to individually enable

interrupts from the peripherals or external signals.

The IPCx registers are used to set the Interrupt Priority

Level for each source of interrupt. Each user interrupt

source can be assigned to one of eight priority levels.

All interrupt registers are described in Register 8-3

through Register 8-30, in the following sections.

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REGISTER 8-1:

SR: ALU STATUS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0

DC⁽¹⁾

bit 15

bit 8

R/W-0

IPL2^(2,3)

bit 7

R/W-0

IPL1^(2,3)

R/W-0

IPL0^(2,3)

R-0

RA⁽¹⁾

R/W-0

N⁽¹⁾

R/W-0

OV⁽¹⁾

R/W-0

Z⁽¹⁾

R/W-0

C⁽¹⁾

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-9

bit 7-5

Unimplemented: Read as ‘0’

IPL<2:0>: CPU Interrupt Priority Level Status bits^(2,3)

111= CPU Interrupt Priority Level is 7 (15); user interrupts disabled

110= CPU Interrupt Priority Level is 6 (14)

101= CPU Interrupt Priority Level is 5 (13)

100= CPU Interrupt Priority Level is 4 (12)

011= CPU Interrupt Priority Level is 3 (11)

010= CPU Interrupt Priority Level is 2 (10)

001= CPU Interrupt Priority Level is 1 (9)

000= CPU Interrupt Priority Level is 0 (8)

Note 1: See Register 3-1 for the description of these bits, which are not dedicated to interrupt control functions.

2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level.

The value in parentheses indicates the Interrupt Priority Level if IPL3 = 1.

3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

Note:

Bit 8 and bits 4 through 0 are described in Section 3.0 “CPU”.

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REGISTER 8-2:

CORCON: CPU CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

R/C-0

IPL3⁽²⁾

R/W-0

PSV⁽¹⁾

U-0

—

U-0

—

bit 7

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-4

bit 3

Unimplemented: Read as ‘0’

IPL3: CPU Interrupt Priority Level Status bit⁽²⁾

1= CPU Interrupt Priority Level is greater than 7

0= CPU Interrupt Priority Level is 7 or less

bit 1-0

Unimplemented: Read as ‘0’

Note 1: See Register 3-2 for the description of this bit, which is not dedicated to interrupt control functions.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

Note:

Bit 2 is described in Section 3.0 “CPU”.

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REGISTER 8-3:

INTCON1: INTERRUPT CONTROL REGISTER 1

R/W-0

NSTDIS

bit 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 8

bit 0

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

MATHERR

ADDRERR

STKERR

OSCFAIL

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

NSTDIS: Interrupt Nesting Disable bit

1= Interrupt nesting is disabled

0= Interrupt nesting is enabled

bit 14-5

bit 4

Unimplemented: Read as ‘0’

MATHERR: Arithmetic Error Trap Status bit

1= Overflow trap has occurred

0= Overflow trap has not occurred

bit 3

bit 2

bit 1

bit 0

ADDRERR: Address Error Trap Status bit

1= Address error trap has occurred

0= Address error trap has not occurred

STKERR: Stack Error Trap Status bit

1= Stack error trap has occurred

0= Stack error trap has not occurred

OSCFAIL: Oscillator Failure Trap Status bit

1= Oscillator failure trap has occurred

0= Oscillator failure trap has not occurred

Unimplemented: Read as ‘0’

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REGISTER 8-4:

INTCON2: INTERRUPT CONTROL REGISTER2

R/W-0

R-0, HSC

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

ALTIVT

DISI

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

INT2EP

INT1EP

INT0EP

bit 7

bit 0

Legend:

HSC = Hardware Settable/Clearable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

ALTIVT: Enable Alternate Interrupt Vector Table bit

1= Use Alternate Interrupt Vector Table

0= Use standard (default) vector table

DISI: DISIInstruction Status bit

1= DISIinstruction is active

0= DISIinstruction is not active

bit 13-3

bit 2

Unimplemented: Read as ‘0’

INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

bit 1

bit 0

INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

DS31037B-page 72

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

REGISTER 8-5:

IFS0: INTERRUPT FLAG STATUS REGISTER 0

R/W-0

NVMIF

bit 15

U-0

—

R/W-0

AD1IF

R/W-0

U-0

—

U-0

—

R/W-0

T3IF

U1TXIF

U1RXIF

bit 8

R/W-0

T2IF

R/W-0

U-0

—

U-0

—

R/W-0

T1IF

R/W-0

U-0

—

R/W-0

INT0IF

CCP2IF

CCP1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

NVMIF: NVM Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 14

bit 13

Unimplemented: Read as ‘0’

AD1IF: A/D Conversion Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 12

bit 11

U1TXIF: UART1 Transmitter Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U1RXIF: UART1 Receiver Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 10-9

bit 8

Unimplemented: Read as ‘0’

T3IF: Timer3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 7

bit 6

T2IF: Timer2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

CCP2IF: Capture/Compare/PWM 2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

Unimplemented: Read as ‘0’

bit 5-4

bit 3

T1IF: Timer1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 2

CCP1IF: Capture/Compare/PWM1 Interrupt Flag Status bit (ECCP1 on PIC24FXXKL40X devices)

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 1

bit 0

Unimplemented: Read as ‘0’

INT0IF: External Interrupt 0 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

 2011 Microchip Technology Inc.

DS31037B-page 73

PIC24F16KL402 FAMILY

REGISTER 8-6:

IFS1: INTERRUPT FLAG STATUS REGISTER 1

R/W-0

U2TXIF⁽¹⁾

R/W-0

U2RXIF⁽¹⁾

R/W-0

INT2IF

U-0

—

R/W-0

T4IF⁽¹⁾

U-0

—

R/W-0

CCP3IF⁽¹⁾

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

INT1IF

R/W-0

CNIF

R/W-0

CMIF

R/W-0

BCL1IF

SSP1IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

U2TXIF: UART2 Transmitter Interrupt Flag Status bit⁽¹⁾

1= Interrupt request has occurred

0= Interrupt request has not occurred

U2RXIF: UART2 Receiver Interrupt Flag Status bit⁽¹⁾

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT2IF: External Interrupt 2 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 12

bit 11

Unimplemented: Read as ‘0’

T4IF: Timer4 Interrupt Flag Status bit⁽¹⁾

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 10

bit 9

Unimplemented: Read as ‘0’

CCP3IF: Capture/Compare/PWM 3 Interrupt Flag Status bit ⁽¹⁾

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8-5

bit 4

Unimplemented: Read as ‘0’

INT1IF: External Interrupt 1 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 3

bit 2

bit 1

bit 0

CNIF: Input Change Notification Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

CMIF: Comparator Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

BCL1IF: MSSP1 I²C Bus Collision Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SSP1IF: MSSP1 SPI/I²C Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices.

DS31037B-page 74

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

REGISTER 8-7:

IFS2: INTERRUPT FLAG STATUS REGISTER 2

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

R/W-0

T3GIF

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-6

bit 5

Unimplemented: Read as ‘0’

T3GIF: Timer3 External Gate Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 4-0

Unimplemented: Read as ‘0’

REGISTER 8-8:

IFS3: INTERRUPT FLAG STATUS REGISTER 3

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

BCL2IF⁽¹⁾

R/W-0

SSP2IF⁽¹⁾

U-0

—

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2

Unimplemented: Read as ‘0’

BCL2IF: MSSP2 I²C Bus Collision Interrupt Flag Status bit⁽¹⁾

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 1

bit 0

SSP2IF: MSSP2 SPI/I²C Event Interrupt Flag Status bit⁽¹⁾

1= Interrupt request has occurred

0= Interrupt request has not occurred

Unimplemented: Read as ‘0’

Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices.

 2011 Microchip Technology Inc.

DS31037B-page 75

PIC24F16KL402 FAMILY

REGISTER 8-9:

IFS4: INTERRUPT FLAG STATUS REGISTER 4

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

HLVDIF

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

U2ERIF⁽¹⁾

R/W-0

U-0

—

U1ERIF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-9

bit 8

Unimplemented: Read as ‘0’

HLVDIF: High/Low-Voltage Detect Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 7-3

bit 2

Unimplemented: Read as ‘0’

U2ERIF: UART2 Error Interrupt Flag Status bit⁽¹⁾

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 1

U1ERIF: UART1 Error Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 0

Unimplemented: Read as ‘0’

Note 1: This bit is unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices.

REGISTER 8-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

ULPWUIF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-1

bit 0

Unimplemented: Read as ‘0’

ULPWUIF: Ultra Low-Power Wake-up Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DS31037B-page 76

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

REGISTER 8-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0

R/W-0

U-0

—

R/W-0

AD1IE

R/W-0

U-0

—

U-0

—

R/W-0

T3IE

NVMIE

U1TXIE

U1RXIE

bit 15

bit 8

R/W-0

T2IE

R/W-0

U-0

—

U-0

—

R/W-0

T1IE

R/W-0

U-0

—

R/W-0

CCP2IE

CCP1IE

INT0IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

NVMIE: NVM Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 14

bit 13

Unimplemented: Read as ‘0’

AD1IE: A/D Conversion Complete Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 12

bit 11

U1TXIE: UART1 Transmitter Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

U1RXIE: UART1 Receiver Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 10-9

bit 8

Unimplemented: Read as ‘0’

T3IE: Timer3 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 7

bit 6

T2IE: Timer2 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

CCP2IE: Capture/Compare/PWM 2 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 5-4

bit 3

Unimplemented: Read as ‘0’

T1IE: Timer1 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 2

CCP1IE: Capture/Compare/PWM 1 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 1

bit 0

IC1IE: Input Capture Channel 1 Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

INT0IE: External Interrupt 0 Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

 2011 Microchip Technology Inc.

DS31037B-page 77

PIC24F16KL402 FAMILY

REGISTER 8-12: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1

R/W-0

U2TXIE⁽¹⁾

R/W-0

U2RXIE⁽¹⁾

R/W-0

U-0

—

R/W-0

T4IE⁽¹⁾

U-0

—

R/W-0

CCP3IE⁽¹⁾

U-0

—

INT2IE

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

CNIE

R/W-0

CMIE

R/W-0

INT1IE

BCL1IE

SSP1IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

U2TXIE: UART2 Transmitter Interrupt Enable bit⁽¹⁾

1= Interrupt request is enabled

0= Interrupt request is not enabled

U2RXIE: UART2 Receiver Interrupt Enable bit⁽¹⁾

1= Interrupt request is enabled

0= Interrupt request is not enabled

INT2IE: External Interrupt 2 Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 12

bit 11

Unimplemented: Read as ‘0’

T4IE: Timer4 Interrupt Enable bit⁽¹⁾

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 10

bit 9

Unimplemented: Read as ‘0’

CCP3IE: Capture/Compare/PWM 3 Interrupt Enable bit⁽¹⁾

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 8-5

bit 4

Unimplemented: Read as ‘0’

INT1IE: External Interrupt 1 Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 3

bit 2

CNIE: Input Change Notification Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

CMIE: Comparator Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 1

bit 0

BCL1IE: MSSP1 I²C Bus Collision Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

SSP1IE: MSSP1 SPI/I²C Event Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices.

DS31037B-page 78

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

REGISTER 8-13: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

R/W-0

T3GIE

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-6

bit 5

Unimplemented: Read as ‘0’

T3GIF: Timer3 External Gate Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 4-2

Unimplemented: Read as ‘0’

REGISTER 8-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

BCL2IE⁽¹⁾

R/W-0

SSP2IE⁽¹⁾

U-0

—

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2

Unimplemented: Read as ‘0’

BCL2IE: MSSP2 I²C Bus Collision Interrupt Enable bit⁽¹⁾

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 1

SSP2IF: MSSP2 SPI/I²C Event Interrupt Enable bit⁽¹⁾

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 0

Unimplemented: Read as ‘0’

Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices.

 2011 Microchip Technology Inc.

DS31037B-page 79

PIC24F16KL402 FAMILY

REGISTER 8-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

HLVDIE

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

U2ERIE⁽¹⁾

R/W-0

U-0

—

U1ERIE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-9

bit 8

Unimplemented: Read as ‘0’

HLVDIE: High/Low-Voltage Detect Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 7-4

bit 2

Unimplemented: Read as ‘0’

U2ERIE: UART2 Error Interrupt Enable bit⁽¹⁾

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 1

U1ERIE: UART1 Error Interrupt Enable bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

bit 0

Unimplemented: Read as ‘0’

Note 1: This bit is unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices.

REGISTER 8-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

ULPWUIE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-1

bit 0

Unimplemented: Read as ‘0’

ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable Bit

1= Interrupt request is enabled

0= Interrupt request is not enabled

DS31037B-page 80

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

REGISTER 8-17: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0

U-0

—

R/W-1

T1IP2

R/W-0

T1IP1

R/W-0

T1IP0

U-0

—

R/W-1

R/W-0

CCP1IP2

CCP1IP1

CCP1IP0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

INT0IP2

INT0IP1

INT0IP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

T1IP<2:0>: Timer1 Interrupt Priority bits

bit 14-12

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

CCP1IP<2:0>: Capture/Compare/PWM 1 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

INT0IP<2:0>: External Interrupt 0 Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

 2011 Microchip Technology Inc.

DS31037B-page 81

PIC24F16KL402 FAMILY

REGISTER 8-18: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1

U-0

—

R/W-1

T2IP2

R/W-0

T2IP1

R/W-0

T2IP0

U-0

—

R/W-1

R/W-0

CCP2IP2

CCP2IP1

CCP2IP0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

T2IP<2:0>: Timer2 Interrupt Priority bits

bit 14-12

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

CCP2IP<2:0>: Capture/Compare/PWM 2 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7-0

Unimplemented: Read as ‘0’

DS31037B-page 82

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

REGISTER 8-19: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U1RXIP2

U1RXIP1

U1RXIP0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

T3IP2

R/W-0

T3IP1

R/W-0

T3IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

bit 14-12

U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11-3

bit 2-0

Unimplemented: Read as ‘0’

T3IP<2:0>: Timer3 Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

 2011 Microchip Technology Inc.

DS31037B-page 83

PIC24F16KL402 FAMILY

REGISTER 8-20: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

NVMIP2

NVMIP1

NVMIP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

AD1IP2

AD1IP1

AD1IP0

U1TXIP2

U1TXIP1

U1TXIP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

NVMIP<2:0>: NVM Interrupt Priority bits

bit 14-12

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11-7

bit 6-4

Unimplemented: Read as ‘0’

AD1IP<2:0>: A/D Conversion Complete Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

DS31037B-page 84

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

REGISTER 8-21: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4

U-0

—

R/W-1

CNIP2

R/W-0

CNIP1

R/W-0

CNIP0

U-0

—

R/W-1

CMIP2

R/W-0

CMIP1

R/W-0

CMIP0

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

BCL1IP2

BCL1IP1

BCL1IP0

SSP1IP2

SSP1IP1

SSP1IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

bit 14-12

CNIP<2:0>: Input Change Notification Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

CMIP<2:0>: Comparator Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

BCL1IP<2:0>: MSSP1 I²C Bus Collision Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

SSP1IP<2:0>: MSSP1 SPI/I²C Event Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

 2011 Microchip Technology Inc.

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REGISTER 8-22: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

INT1IP2

INT1IP1

INT1IP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-0

Unimplemented: Read as ‘0’

INT1IP<2:0>: External Interrupt 1 Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

DS31037B-page 86

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REGISTER 8-23: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6

U-0

—

R/W-1

T4IP2⁽¹⁾

R/W-0

T4IP1⁽¹⁾

R/W-0

T4IP0⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

CCP3IP2⁽¹⁾CCP3IP1⁽¹⁾CCP3IP0⁽¹⁾

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

T4IP<2:0>: Timer4 Interrupt Priority bits⁽¹⁾

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11-7

bit 6-4

Unimplemented: Read as ‘0’

CCP3IP: Capture/Compare/PWM 2 Interrupt Priority bits⁽¹⁾

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices.

 2011 Microchip Technology Inc.

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REGISTER 8-24: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

U2TXIP2⁽¹⁾U2TXIP1⁽¹⁾U2TXIP0⁽¹⁾

U2RXIP2⁽¹⁾U2RXIP1⁽¹⁾U2RXIP0⁽¹⁾

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

INT2IP2

INT2IP1

INT2IP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

Unimplemented: Read as ‘0’

bit 14-12

U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits⁽¹⁾

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits⁽¹⁾

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

INT2IP<2:0>: External Interrupt 2 Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices.

DS31037B-page 88

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REGISTER 8-25: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

T3GIP2

T3GIP1

T3GIP0

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-7

bit 6-4

Unimplemented: Read as ‘0’

T3GIP<2:0>: Timer3 External Gate Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

 2011 Microchip Technology Inc.

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REGISTER 8-26: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

BCL2IP2⁽¹⁾

R/W-0

BCL2IP1⁽¹⁾

R/W-0

BCL2IP0⁽¹⁾

bit 8

bit 15

U-0

—

R/W-1

R/W-0

SSP2IP0⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

SSP2IP2⁽¹⁾SSP2IP1⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

BCL2IP<2:0>: MSSP2 I²C™ Bus Collision Interrupt Priority bits⁽¹⁾

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

SSP2IP<2:0>: MSSP2 SPI/I²C Event Interrupt Priority bits⁽¹⁾

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices.

DS31037B-page 90

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REGISTER 8-27: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

U2ERIP2⁽¹⁾U2ERIP1⁽¹⁾U2ERIP0⁽¹⁾

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U1ERIP2⁽¹⁾U1ERIP1⁽¹⁾U1ERIP0⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

U2ERIP<2:0>: UART2 Error Interrupt Priority bits⁽¹⁾

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

U1ERIP<2:0>: UART1 Error Interrupt Priority bits⁽¹⁾

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices.

 2011 Microchip Technology Inc.

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REGISTER 8-28: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

HLVDIP2

HLVDIP1

HLVDIP0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-0

Unimplemented: Read as ‘0’

HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

REGISTER 8-29: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

ULPWUIP2 ULPWUIP1 ULPWUIP0

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 6-4

Unimplemented: Read as ‘0’

ULPWUIP<2:0>: Ultra Low-Power Wake-up Interrupt Priority bits

111= Interrupt is Priority 7 (highest priority interrupt)

•

001= Interrupt is Priority 1

000= Interrupt source is disabled

DS31037B-page 92

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REGISTER 8-30: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER

R-0

r-0

—

R/W-0

U-0

—

R-0

CPUIRQ

VHOLD

ILR3

ILR2

ILR1

ILR0

bit 15

bit 8

U-0

—

R-0

VECNUM6

VECNUM5 VECNUM4 VECNUM3

VECNUM2

VECNUM1

VECNUM0

bit 0

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

CPUIRQ: Interrupt Request from Interrupt Controller CPU bit

1= An interrupt request has occurred but has not yet been Acknowledged by the CPU (this will

happen when the CPU priority is higher than the interrupt priority)

0= No interrupt request is left unacknowledged

bit 14

bit 13

Reserved: Maintain as ‘0’

VHOLD: Vector Hold bit

Allows vector number capture and changes what Interrupt is stored in the VECNUM bit.

1= VECNUM will contain the value of the highest priority pending interrupt, instead of the current

interrupt

0= VECNUM will contain the value of the last Acknowledged interrupt (last interrupt that has occurred

with higher priority than the CPU, even if other interrupts are pending)

bit 12

Unimplemented: Read as ‘0’

bit 11-8

ILR<3:0>: New CPU Interrupt Priority Level bits

1111= CPU Interrupt Priority Level is 15

•

0001= CPU Interrupt Priority Level is 1

0000= CPU Interrupt Priority Level is 0

bit 7

Unimplemented: Read as ‘0’

bit 6-0

VECNUM<6:0>: Vector Number of Pending Interrupt bits

0111111= Interrupt vector pending is number 135

•

0000001= Interrupt vector pending is Number 9

0000000= Interrupt vector pending is Number 8

 2011 Microchip Technology Inc.

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8.4.3

TRAP SERVICE ROUTINE (TSR)

8.4

Interrupt Setup Procedures

A Trap Service Routine (TSR) is coded like an ISR,

except that the appropriate trap status flag in the

INTCON1 register must be cleared to avoid re-entry

into the TSR.

8.4.1

INITIALIZATION

To configure an interrupt source:

1. Set the NSTDIS Control bit (INTCON1<15>) if

nested interrupts are not desired.

8.4.4

INTERRUPT DISABLE

2. Select the user-assigned priority level for the

interrupt source by writing the control bits in the

appropriate IPCx register. The priority level will

depend on the specific application and the type

of interrupt source. If multiple priority levels are

not desired, the IPCx register control bits, for all

enabled interrupt sources, may be programmed

to the same non-zero value.

All user interrupts can be disabled using the following

procedure:

1. Push the current SR value onto the software

stack using the PUSHinstruction.

2. Force the CPU to Priority Level 7 by inclusive

ORing the value, OEh with SRL.

To enable user interrupts, the POPinstruction may be

used to restore the previous SR value.

Note:

At a device Reset, the IPCx registers are

initialized, such that all user interrupt

sources are assigned to Priority Level 4.

Only user interrupts with a priority level of 7 or less can

be disabled. Trap sources (Level 8-15) cannot be

disabled.

3. Clear the interrupt flag status bit associated with

the peripheral in the associated IFSx register.

The DISI instruction provides a convenient way to

disable interrupts of Priority Levels 1-6 for a fixed

period. Level 7 interrupt sources are not disabled by

the DISIinstruction.

4. Enable the interrupt source by setting the

interrupt enable control bit associated with the

source in the appropriate IECx register.

8.4.2

INTERRUPT SERVICE ROUTINE

The method that is used to declare an ISR and initialize

the IVT with the correct vector address depends on the

programming language (i.e., C or assembler) and the

language development toolsuite that is used to develop

the application. In general, the user must clear the

interrupt flag in the appropriate IFSx register for the

source of the interrupt that the ISR handles. Otherwise,

the ISR will be re-entered immediately after exiting the

routine. If the ISR is coded in assembly language, it

must be terminated using a RETFIE instruction to

unstack the saved PC value, SRL value and old CPU

priority level.

DS31037B-page 94

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• Software-controllable switching between various

clock sources.

9.0

OSCILLATOR

CONFIGURATION

• Software-controllable postscaler for selective

clocking of CPU for system power savings.

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. For more information on

Oscillator Configuration, refer to the

“PIC24F Family Reference Manual”,

Section 38. “Oscillator with 500 kHz

Low-Power FRC” (DS39726).

• System frequency range declaration bits for EC

mode. When using an external clock source, the

current consumption is reduced by setting the

declaration bits to the expected frequency range.

• A Fail-Safe Clock Monitor (FSCM) that detects clock

failure and permits safe application recovery or

shutdown.

A simplified diagram of the oscillator system is shown in

Figure 9-1.

The oscillator system for the PIC24F16KL402 family of

devices has the following features:

• A total of five external and internal oscillator options

as clock sources, providing 11 different clock

modes.

• On-chip 4x Phase Locked Loop (PLL) to boost

internal operating frequency on select internal and

external oscillator sources.

FIGURE 9-1:

PIC24F16KL402 FAMILY CLOCK DIAGRAM

Primary Oscillator

REFOCON<15:8>

XT, HS, EC

OSCO

OSCI

Reference Clock

Generator

XTPLL, HSPLL

ECPLL,FRCPLL

4 x PLL

REFO

8 MHz

4 MHz

8 MHz

FRC

Oscillator

FRCDIV

Peripherals

500 kHz

LPFRC

Oscillator

CLKDIV<10:8>

FRC

CLKO

CPU

LPRC

Oscillator

31 kHz (nominal)

Secondary Oscillator

SOSC

SOSCO

SOSCI

CLKDIV<14:12>

SOSCEN

Enable

Oscillator

Clock Control Logic

Fail-Safe

Clock

Monitor

WDT, PWRT, DSWDT

Clock Source Option

for Other Modules

 2011 Microchip Technology Inc.

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9.1

CPU Clocking Scheme

9.2

Initial Configuration on POR

The system clock source can be provided by one of

four sources:

The oscillator source (and operating mode) that is used

at a device Power-on Reset (POR) event is selected

using Configuration bit settings. The oscillator

Configuration bit settings are located in the

Configuration registers in the program memory (For

more information, see Section 23.1 “Configuration

Bits”). The Primary Oscillator Configuration bits,

POSCMD<1:0> (FOSC<1:0>), and the Initial Oscillator

• Primary Oscillator (POSC) on the OSCI and OSCO

pins

• Secondary Oscillator (SOSC) on the SOSCI and

SOSCO pins

PIC24F16KL402 family devices consist of two

types of secondary oscillators:

Select

Configuration

bits,

FNOSC<2:0>

- High-Power Secondary Oscillator

- Low-Power Secondary Oscillator

(FOSCSEL<2:0>), select the oscillator source that is

used at a POR. The FRC Primary Oscillator with

Postscaler (FRCDIV) is the default (unprogrammed)

selection. The secondary oscillator, or one of the

internal oscillators, may be chosen by programming

these bit locations. The EC mode Frequency Range

Configuration bits, POSCFREQ<1:0> (FOSC<4:3>),

optimize power consumption when running in EC

mode. The default configuration is “frequency range is

greater than 8 MHz”.

These can be selected by using the SOSCSEL

(FOSC<5>) bit.

• Fast Internal RC (FRC) Oscillator

- 8 MHz FRC Oscillator

- 500 kHz Lower Power FRC Oscillator

• Low-Power Internal RC (LPRC) Oscillator with two

modes:

- High-Power/High Accuracy mode

- Low-Power/Low Accuracy mode

The Configuration bits allow users to choose between

the various clock modes, shown in Table 9-1.

The primary oscillator and 8 MHz FRC sources have the

option of using the internal 4x PLL. The frequency of the

FRC clock source can optionally be reduced by the pro-

grammable clock divider. The selected clock source

generates the processor and peripheral clock sources.

9.2.1

CLOCK SWITCHING MODE

CONFIGURATION BITS

The FCKSM Configuration bits (FOSC<7:6>) are used

jointly to configure device clock switching and the

FSCM. Clock switching is enabled only when FCKSM1

is programmed (‘0’). The FSCM is enabled only when

FCKSM<1:0> are both programmed (‘00’).

The processor clock source is divided by two to produce

the internal instruction cycle clock, FCY. In this

document, the instruction cycle clock is also denoted by

FOSC/2. The internal instruction cycle clock, FOSC/2, can

be provided on the OSCO I/O pin for some operating

modes of the primary oscillator.

TABLE 9-1:

CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator Mode Oscillator Source POSCMD<1:0>

FNOSC<2:0>

Notes

1, 2

8 MHz FRC Oscillator with Postscaler

(FRCDIV)

Internal

11

111

500 kHz FRC Oscillator with Postscaler

(LPFRCDIV)

Internal

11

110

1

Low-Power RC Oscillator (LPRC)

Internal

Secondary

Primary

11

00

10

101

100

011

1

Secondary (Timer1) Oscillator (SOSC)

Primary Oscillator (HS) with PLL Module

(HSPLL)

Primary Oscillator (EC) with PLL Module

(ECPLL)

Primary

00

011

Primary Oscillator (HS)

Primary Oscillator (XT)

Primary Oscillator (EC)

Primary

Internal

10

01

00

11

010

001

8 MHz FRC Oscillator with PLL Module

(FRCPLL)

1

8 MHz FRC Oscillator (FRC)

Internal

11

000

Note 1: OSCO pin function is determined by the OSCIOFNC Configuration bit.

2: This is the default oscillator mode for an unprogrammed (erased) device.

DS31037B-page 96

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The Clock Divider register (Register 9-2) controls the

features associated with Doze mode, as well as the

postscaler for the FRC oscillator.

9.3

Control Registers

The operation of the oscillator is controlled by three

Special Function Registers (SFRs):

The FRC Oscillator Tune register (Register 9-3) allows

the user to fine tune the FRC oscillator. OSCTUN

functionality has been provided to help customers com-

pensate for temperature effects on the FRC frequency

over a wide range of temperatures. The tuning step

size is an approximation and is neither characterized

nor tested.

• OSCCON

• CLKDIV

• OSCTUN

The OSCCON register (Register 9-1) is the main

control register for the oscillator. It controls clock

source switching and allows the monitoring of clock

sources.

REGISTER 9-1:

OSCCON: OSCILLATOR CONTROL REGISTER

U-0

—

R-0, HSC

COSC1

R-0, HSC

COSC0

U-0

—

R/W-x⁽¹⁾

NOSC2

R/W-x⁽¹⁾

NOSC1

R/W-x⁽¹⁾

NOSC0

COSC2

bit 15

bit 8

R/SO-0, HSC

CLKLOCK

bit 7

U-0

—

R-0, HSC⁽²⁾

LOCK

U-0

—

R/CO-0, HS

CF

R/W-0⁽³⁾

R/W-0

SOSCDRV

SOSCEN

OSWEN

bit 0

Legend:

HSC = Hardware Settable/Clearable bit

SO = Settable Only bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

HS = Hardware Settable bit CO = Clearable Only bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

bit 15

Unimplemented: Read as ‘0’

bit 14-12

COSC<2:0>: Current Oscillator Selection bits

111= 8 MHz Fast RC Oscillator with Postscaler (FRCDIV)

110= 500 kHz Low-Power Fast RC Oscillator (FRC) with Postscaler (LPFRCDIV)

101= Low-Power RC Oscillator (LPRC)

100= Secondary Oscillator (SOSC)

011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010= Primary Oscillator (XT, HS, EC)

001= 8 MHz FRC Oscillator with Postscaler and PLL module (FRCPLL)

000= 8 MHz FRC Oscillator (FRC)

bit 11

Unimplemented: Read as ‘0’

bit 10-8

NOSC<2:0>: New Oscillator Selection bits⁽¹⁾

111= 8 MHz Fast RC Oscillator with Postscaler (FRCDIV)

110= 500 kHz Low-Power Fast RC Oscillator (FRC) with Postscaler (LPFRCDIV)

101= Low-Power RC Oscillator (LPRC)

100= Secondary Oscillator (SOSC)

011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010= Primary Oscillator (XT, HS, EC)

001= 8 MHz FRC Oscillator with Postscaler and PLL module (FRCPLL)

000= 8 MHz FRC Oscillator (FRC)

Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.

2: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

3: When SOSC is selected to run from a digital clock input, rather than an external crystal (SOSCSRC = 0),

this bit has no effect.

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REGISTER 9-1:

OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)

bit 7

CLKLOCK: Clock Selection Lock Enabled bit

If FSCM is enabled (FCKSM1 = 1):

1= Clock and PLL selections are locked

0= Clock and PLL selections are not locked and may be modified by setting the OSWEN bit

If FSCM is disabled (FCKSM1 = 0):

Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.

bit 6

bit 5

Unimplemented: Read as ‘0’

LOCK: PLL Lock Status bit⁽²⁾

1= PLL module is in lock or the PLL module start-up timer is satisfied

0= PLL module is out of lock, the PLL start-up timer is running or PLL is disabled

bit 4

bit 3

Unimplemented: Read as ‘0’

CF: Clock Fail Detect bit

1= FSCM has detected a clock failure

0= No clock failure has been detected

bit 2

bit 1

SOSCDRV: Secondary Oscillator Drive Strength bit⁽³⁾

1= High-power SOSC circuit is selected

0= Low/high-power select is done via the SOSCSRC Configuration bit

SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit

1= Enable secondary oscillator

0= Disable secondary oscillator

bit 0

OSWEN: Oscillator Switch Enable bit

1= Initiate an oscillator switch to the clock source specified by the NOSC<2:0> bits

0= Oscillator switch is complete

Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.

2: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

3: When SOSC is selected to run from a digital clock input, rather than an external crystal (SOSCSRC = 0),

this bit has no effect.

DS31037B-page 98

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REGISTER 9-2:

CLKDIV: CLOCK DIVIDER REGISTER

R/W-0

ROI

R/W-0

R/W-1

R/W-0

DOZEN⁽¹⁾

R/W-0

R/W-1

DOZE2

DOZE1

DOZE0

RCDIV2

RCDIV1

RCDIV0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

ROI: Recover on Interrupt bit

1= Interrupts clear the DOZEN bit, and reset the CPU and peripheral clock ratio to 1:1

0= Interrupts have no effect on the DOZEN bit

bit 14-12

DOZE<2:0>: CPU-to-Peripheral Clock Ratio Select bits

111= 1:128

110= 1:64

101= 1:32

100= 1:16

011= 1:8

010= 1:4

001= 1:2

000= 1:1

bit 11

DOZEN: DOZE Enable bit⁽¹⁾

1= DOZE<2:0> bits specify the CPU-to-peripheral clock ratio

0= CPU and the peripheral clock ratio are set to 1:1

bit 10-8

RCDIV<2:0>: FRC Postscaler Select bits

When OSCCON (COSC<2:0>) = 111 or 001:

111= 31.25 kHz (divide by 256)

110= 125 kHz (divide by 64)

101= 250 kHz (divide by 32)

100= 500 kHz (divide by 16)

011= 1 MHz (divide by 8)

010= 2 MHz (divide by 4)

001= 4 MHz (divide by 2) (default)

000= 8 MHz (divide by 1)

When OSCCON (COSC<2:0>) = 110:

111= 1.95 kHz (divide by 256)

110= 7.81 kHz (divide by 64)

101= 15.62 kHz (divide by 32)

100= 31.25 kHz (divide by 16)

011= 62.5 kHz (divide by 8)

010= 125 kHz (divide by 4)

001= 250 kHz (divide by 2) (default)

000= 500 kHz (divide by 1)

bit 7-0

Unimplemented: Read as ‘0’

Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.

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DS31037B-page 99

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REGISTER 9-3:

OSCTUN: FRC OSCILLATOR TUNE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

R/W-0

TUN5⁽¹⁾

R/W-0

TUN4⁽¹⁾

R/W-0

TUN3⁽¹⁾

R/W-0

TUN2⁽¹⁾

R/W-0

TUN1⁽¹⁾

R/W-0

TUN0⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-6

bit 5-0

Unimplemented: Read as ‘0’

TUN<5:0>: FRC Oscillator Tuning bits⁽¹⁾

011111= Maximum frequency deviation

011110

•

000001

000000= Center frequency, oscillator is running at factory calibrated frequency

111111

•

100001

100000= Minimum frequency deviation

Note 1: Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC

tuning range and may not be monotonic.

DS31037B-page 100

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Once the basic sequence is completed, the system

clock hardware responds automatically, as follows:

9.4

Clock Switching Operation

With few limitations, applications are free to switch

between any of the four clock sources (POSC, SOSC,

FRC and LPRC) under software control and at any

time. To limit the possible side effects that could result

from this flexibility, PIC24F devices have a safeguard

lock built into the switching process.

1. The clock switching hardware compares the

COSCx bits with the new value of the NOSCx

bits. If they are the same, then the clock switch

is a redundant operation. In this case, the

OSWEN bit is cleared automatically and the

clock switch is aborted.

Note:

The Primary Oscillator mode has three

different submodes (XT, HS and EC),

which are determined by the POSCMDx

Configuration bits. While an application

can switch to and from Primary Oscillator

mode in software, it cannot switch

between the different primary submodes

without reprogramming the device.

2. If a valid clock switch has been initiated, the

LOCK (OSCCON<5>) and CF (OSCCON<3>)

bits are cleared.

3. The new oscillator is turned on by the hardware

if it is not currently running. If a crystal oscillator

must be turned on, the hardware will wait until

the OST expires. If the new source is using the

PLL, then the hardware waits until a PLL lock is

detected (LOCK = 1).

9.4.1

ENABLING CLOCK SWITCHING

4. The hardware waits for 10 clock cycles from the

new clock source and then performs the clock

switch.

To enable clock switching, the FCKSM1 Configuration bit

in the FOSC Configuration register must be programmed

to ‘0’. (Refer to Section 23.0 “Special Features” for

further details.) If the FCKSM1 Configuration bit is

unprogrammed (‘1’), the clock switching function and

FSCM function are disabled; this is the default setting.

5. The hardware clears the OSWEN bit to indicate a

successful clock transition. In addition, the

NOSCx bits value is transferred to the COSCx

bits.

The NOSCx control bits (OSCCON<10:8>) do not

control the clock selection when clock switching is

disabled. However, the COSCx bits (OSCCON<14:12>)

will reflect the clock source selected by the FNOSCx

Configuration bits.

6. The old clock source is turned off at this time,

with the exception of LPRC (if WDT, FSCM or

RTCC with LPRC as a clock source are

enabled) or SOSC (if SOSCEN remains

enabled).

The OSWEN control bit (OSCCON<0>) has no effect

when clock switching is disabled; it is held at ‘0’ at all

times.

Note 1: The processor will continue to execute

code throughout the clock switching

sequence. Timing-sensitive code should

not be executed during this time.

9.4.2

OSCILLATOR SWITCHING

SEQUENCE

2: Direct clock switches between any

Primary Oscillator mode with PLL and

FRCPLL mode are not permitted. This

applies to clock switches in either

direction. In these instances, the

application must switch to FRC mode as

a transition clock source between the two

PLL modes.

At a minimum, performing a clock switch requires this

basic sequence:

1. If

desired,

read

the

COSCx

bits

(OSCCON<14:12>) to determine the current

oscillator source.

2. Perform the unlock sequence to allow a write to

the OSCCON register high byte.

3. Write the appropriate value to the NOSCx bits

(OSCCON<10:8>) for the new oscillator source.

4. Perform the unlock sequence to allow a write to

the OSCCON register low byte.

5. Set the OSWEN bit to initiate the oscillator

switch.

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The following code sequence for a clock switch is

recommended:

9.5

Reference Clock Output

In addition to the CLKO output (FOSC/2) available in

certain oscillator modes, the device clock in the

PIC24F16KL402 family devices can also be configured

to provide a reference clock output signal to a port pin.

This feature is available in all oscillator configurations

and allows the user to select a greater range of clock

submultiples to drive external devices in the

application.

1. Disable interrupts during the OSCCON register

unlock and write sequence.

2. Execute the unlock sequence for the OSCCON

high byte by writing 78h and 9Ah to

OSCCON<15:8>,

instructions.

in

two

back-to-back

3. Write the new oscillator source to the NOSCx

bits in the instruction immediately following the

unlock sequence.

This reference clock output is controlled by the

REFOCON register (Register 9-4). Setting the ROEN

bit (REFOCON<15>) makes the clock signal available

on the REFO pin. The RODIV bits (REFOCON<11:8>)

enable the selection of 16 different clock divider

options.

4. Execute the unlock sequence for the OSCCON

low byte by writing 46h and 57h to

OSCCON<7:0>, in two back-to-back instructions.

5. Set the OSWEN bit in the instruction immediately

following the unlock sequence.

The ROSSLP and ROSEL bits (REFOCON<13:12>)

control the availability of the reference output during

Sleep mode. The ROSEL bit determines if the oscillator

on OSC1 and OSC2, or the current system clock

source, is used for the reference clock output. The

ROSSLP bit determines if the reference source is

available on REFO when the device is in Sleep mode.

6. Continue to execute code that is not

clock-sensitive (optional).

7. Invoke an appropriate amount of software delay

(cycle counting) to allow the selected oscillator

and/or PLL to start and stabilize.

8. Check to see if OSWEN is ‘0’. If it is, the switch

was successful. If OSWEN is still set, then check

the LOCK bit to determine the cause of failure.

To use the reference clock output in Sleep mode, both

the ROSSLP and ROSEL bits must be set. The device

clock must also be configured for one of the primary

modes (EC, HS or XT). Therefore, if the ROSEL bit is

also not set, the oscillator on OSC1 and OSC2 will be

powered down when the device enters Sleep mode.

Clearing the ROSEL bit allows the reference output

frequency to change as the system clock changes

during any clock switches.

The core sequence for unlocking the OSCCON register

and initiating a clock switch is shown in Example 9-1.

EXAMPLE 9-1:

BASIC CODE SEQUENCE

FOR CLOCK SWITCHING

;Place the new oscillator selection in W0

;OSCCONH (high byte) Unlock Sequence

MOV

MOV.b

#OSCCONH, w1

#0x78, w2

#0x9A, w3

w2, [w1]

w3, [w1]

;Set new oscillator selection

MOV.b WREG, OSCCONH

;OSCCONL (low byte) unlock sequence

MOV

MOV.b

#OSCCONL, w1

#0x46, w2

#0x57, w3

w2, [w1]

w3, [w1]

;Start oscillator switch operation

BSET OSCCON,#0

DS31037B-page 102

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REGISTER 9-4:

REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER

R/W-0

ROEN

U-0

—

R/W-0

ROSSLP

ROSEL

RODIV3

RODIV2

RODIV1

RODIV0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

ROEN: Reference Oscillator Output Enable bit

1= Reference oscillator enabled on REFO pin

0= Reference oscillator disabled

bit 14

bit 13

Unimplemented: Read as ‘0’

ROSSLP: Reference Oscillator Output Stop in Sleep bit

1= Reference oscillator continues to run in Sleep

0= Reference oscillator is disabled in Sleep

bit 12

ROSEL: Reference Oscillator Source Select bit

1= Primary oscillator is used as the base clock⁽¹⁾

0= System clock is used as the base clock; the base clock reflects any clock switching of the device

bit 11-8

RODIV<3:0>: Reference Oscillator Divisor Select bits

1111= Base clock value divided by 32,768

1110= Base clock value divided by 16,384

1101= Base clock value divided by 8,192

1100= Base clock value divided by 4,096

1011= Base clock value divided by 2,048

1010= Base clock value divided by 1,024

1001= Base clock value divided by 512

1000= Base clock value divided by 256

0111= Base clock value divided by 128

0110= Base clock value divided by 64

0101= Base clock value divided by 32

0100= Base clock value divided by 16

0011= Base clock value divided by 8

0010= Base clock value divided by 4

0001= Base clock value divided by 2

0000= Base clock value

bit 7-0

Unimplemented: Read as ‘0’

Note 1: The crystal oscillator must be enabled using the FOSC<2:0> bits; the crystal maintains the operation in

Sleep mode.

 2011 Microchip Technology Inc.

DS31037B-page 103

PIC24F16KL402 FAMILY

NOTES:

DS31037B-page 104

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

10.1 Clock Frequency and Clock

Switching

10.0 POWER-SAVING FEATURES

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

PIC24F devices allow for a wide range of clock

frequencies to be selected under application control. If

the system clock configuration is not locked, users can

choose low-power or high-precision oscillators by simply

changing the NOSC bits. The process of changing a

system clock during operation, as well as limitations to

the process, are discussed in more detail in Section 9.0

“Oscillator Configuration”.

intended to be

a

comprehensive

reference source. For more information

on Power-Saving Features, refer to the

“PIC24F Family Reference Manual”,

“Section 39. Power-Saving Features

with Deep Sleep” (DS39727).

The PIC24F16KL402 family of devices provides the

ability to manage power consumption by selectively

managing clocking to the CPU and the peripherals. In

general, a lower clock frequency and a reduction in the

number of circuits being clocked constitutes lower

consumed power. All PIC24F devices manage power

consumption using several strategies:

10.2 Instruction-Based Power-Saving

Modes

PIC24F devices have two special power-saving modes

that are entered through the execution of a special

PWRSAVinstruction. Sleep mode stops clock operation

and halts all code execution; Idle mode halts the CPU

and code execution, but allows peripheral modules to

continue operation.

• Clock frequency

• Instruction-based Idle and Sleep modes

• Hardware-based periodic wake-up from Sleep

• Software Controlled Doze mode

• Selective peripheral control in software

The assembly syntax of the PWRSAV instruction is

shown in Example 10-1.

Note: SLEEP_MODE and IDLE_MODE are

constants, defined in the assembler

include file for the selected device.

Combinations of these methods can be used to

selectively tailor an application’s power consumption,

while still maintaining critical application features, such

as timing-sensitive communications.

Sleep and Idle modes can be exited as a result of an

enabled interrupt, WDT time-out or a device Reset.

When the device exits these modes, it is said to

“wake-up”.

EXAMPLE 10-1:

PWRSAVINSTRUCTION SYNTAX

PWRSAV

#SLEEP_MODE

#IDLE_MODE

; Put the device into SLEEP mode

; Put the device into IDLE mode

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10.2.1

SLEEP MODE

10.2.2

IDLE MODE

Idle mode has these features:

Sleep mode includes these features:

• The CPU will stop executing instructions.

• The WDT is automatically cleared.

• The system clock source is shut down. If an

on-chip oscillator is used, it is turned off.

• The device current consumption will be reduced

to a minimum, provided that no I/O pin is sourcing

current.

• The system clock source remains active. By

default, all peripheral modules continue to operate

normally from the system clock source, but can

also be selectively disabled (see Section 10.5

“Selective Peripheral Module Control”).

• The I/O pin directions and states are frozen.

• The Fail-Safe Clock Monitor does not operate

during Sleep mode since the system clock source

is disabled.

• If the WDT or FSCM is enabled, the LPRC will

also remain active.

• The LPRC clock will continue to run in Sleep

mode if the WDT or RTCC with LPRC as clock

source is enabled.

The device will wake from Idle mode on any of these

events:

• Any interrupt that is individually enabled

• Any device Reset

• The WDT, if enabled, is automatically cleared

prior to entering Sleep mode.

• A WDT time-out

• Some device features, or peripherals, may

continue to operate in Sleep mode. This includes

items, such as the input change notification on the

I/O ports, or peripherals that use an external clock

input. Any peripheral that requires the system

clock source for its operation will be disabled in

Sleep mode.

On wake-up from Idle, the clock is re-applied to the

CPU. Instruction execution begins immediately, start-

ing with the instruction following the PWRSAVinstruction

or the first instruction in the ISR.

10.2.3

INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS

The device will wake-up from Sleep mode on any of

these events:

Any interrupt that coincides with the execution of a

PWRSAVinstruction will be held off until entry into Sleep

or Idle mode has completed. The device will then

wake-up from Sleep or Idle mode.

• On any interrupt source that is individually

enabled

• On any form of device Reset

• On a WDT time-out

On wake-up from Sleep, the processor will restart with

the same clock source that was active when Sleep

mode was entered.

DS31037B-page 106

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See Example 10-2 for initializing the ULPWU module.

10.3 Ultra Low-Power Wake-up

A series resistor, between RB0 and the external

capacitor, provides overcurrent protection for the

RB0/AN0/ULPWU pin and enables software calibration

of the time-out (see Figure 10-1).

The Ultra Low-Power Wake-up (ULPWU) on pin, RB0,

allows a slow falling voltage to generate an interrupt

without excess current consumption. This feature

provides a low-power technique for periodically waking

up the device from Sleep mode.

FIGURE 10-1:

SERIAL RESISTOR

To use this feature:

R

1

1. Charge the capacitor on RB0 by configuring the

RB0

RB0 pin to an output and setting it to ‘1’.

2. Stop charging the capacitor by configuring RB0

as an input.

C

1

3. Discharge the capacitor by setting the ULPEN

and ULPSINK bits in the ULPWCON register.

4. Configure Sleep mode.

5. Enter Sleep mode.

A timer can be used to measure the charge time and

discharge time of the capacitor. The charge time can

then be adjusted to provide the desired delay in Sleep.

This technique compensates for the affects of temper-

ature, voltage and component accuracy. The peripheral

can also be configured as a simple, programmable

Low-Voltage Detect (LVD) or temperature sensor.

The time-out is dependent on the discharge time of the

RC circuit on RB0. When the voltage on RB0 drops

below VIL, the device wakes up and executes the next

instruction.

When the ULPWU module wakes the device from

Sleep mode, the ULPWUIF bit (IFS5<0>) is set. Soft-

ware can check this bit upon wake-up to determine the

wake-up source.

EXAMPLE 10-2:

ULTRA LOW-POWER WAKE-UP INITIALIZATION

//******************************************************************************

// 1. Charge the capacitor on RB0

//******************************************************************************

TRISBbits.TRISB0 = 0;

LATBbits.LATB0 = 1;

for(i = 0; i < 10000; i++) Nop();

//******************************************************************************

//2. Stop Charging the capacitor on RB0

//******************************************************************************

TRISBbits.TRISB0 = 1;

//******************************************************************************

//3. Enable ULPWU Interrupt

//******************************************************************************

IFS5bits.ULPWUIF = 0;

IEC5bits.ULPWUIE = 1;

IPC20bits.ULPWUIP = 0x7;

//******************************************************************************

//4. Enable the Ultra Low Power Wakeup module and allow capacitor discharge

//******************************************************************************

ULPWCONbits.ULPEN = 1;

ULPWCONbits.ULPSINK = 1;

//******************************************************************************

//5. Enter Sleep Mode

//******************************************************************************

Sleep();

//for Sleep, execution will resume here

 2011 Microchip Technology Inc.

DS31037B-page 107

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REGISTER 10-1: ULPWCON: ULPWU CONTROL REGISTER

R/W-0

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

ULPEN

ULPSINK

ULPSIDL

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

ULPEN: ULPWU Module Enable bit

1= Module is enabled

0= Module is disabled

bit 14

bit 13

Unimplemented: Read as ‘0’

ULPSIDL: ULPWU Stop in Idle Select bit

1= Discontinue module operation when the device enters Idle mode

0= Continue module operation in Idle mode

bit 12-9

bit 8

Unimplemented: Read as ‘0’

ULPSINK: ULPWU Current Sink Enable bit

1= Current sink is enabled

0= Current sink is disabled

bit 7-0

Unimplemented: Read as ‘0’

DS31037B-page 108

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10.4 Doze Mode

10.5 Selective Peripheral Module

Control

Generally, changing clock speed and invoking one of

the power-saving modes are the preferred strategies

for reducing power consumption. There may be

circumstances, however, where this is not practical. For

example, it may be necessary for an application to

maintain uninterrupted, synchronous communication,

even while it is doing nothing else. Reducing system

clock speed may introduce communication errors,

Idle and Doze modes allow users to substantially

reduce power consumption by slowing or stopping the

CPU clock. Even so, peripheral modules still remain

clocked and thus, consume power. There may be

cases where the application needs what these modes

do not provide: the allocation of power resources to

CPU processing, with minimal power consumption

from the peripherals.

while using

a

power-saving mode may stop

communications completely.

PIC24F devices address this requirement by allowing

peripheral modules to be selectively disabled, reducing

or eliminating their power consumption. This can be

done with two control bits:

Doze mode is a simple and effective alternative method

to reduce power consumption while the device is still

executing code. In this mode, the system clock

continues to operate from the same source and at the

same speed. Peripheral modules continue to be

clocked at the same speed, while the CPU clock speed

is reduced. Synchronization between the two clock

domains is maintained, allowing the peripherals to

access the SFRs while the CPU executes code at a

slower rate.

• The Peripheral Enable bit, generically named,

“XXXEN”, located in the module’s main control

SFR.

• The Peripheral Module Disable (PMD) bit,

generically named, “XXXMD”, located in one of

the PMD Control registers.

Both bits have similar functions in enabling or disabling

its associated module. Setting the PMD bit for a module

disables all clock sources to that module, reducing its

power consumption to an absolute minimum. In this

state, the control and status registers associated with

the peripheral will also be disabled, so writes to those

registers will have no effect, and read values will be

invalid. Many peripheral modules have a corresponding

PMD bit.

Doze mode is enabled by setting the DOZEN bit

(CLKDIV<11>). The ratio between peripheral and core

clock speed is determined by the DOZE<2:0> bits

(CLKDIV<14:12>).

There

are

eight

possible

configurations, from 1:1 to 1:128, with 1:1 being the

default.

It is also possible to use Doze mode to selectively reduce

power consumption in event driven applications. This

allows clock-sensitive functions, such as synchronous

communications, to continue without interruption. Mean-

while, the CPU Idles, waiting for something to invoke an

interrupt routine. Enabling the automatic return to

full-speed CPU operation on interrupts is enabled by

setting the ROI bit (CLKDIV<15>). By default, interrupt

events have no effect on Doze mode operation.

In contrast, disabling a module by clearing its XXXEN

bit, disables its functionality, but leaves its registers

available to be read and written to. Power consumption

is reduced, but not by as much as when the PMD bits

are used.

To achieve more selective power savings, peripheral

modules can also be selectively disabled when the

device enters Idle mode. This is done through the control

bit of the generic name format, “XXXIDL”. By default, all

modules that can operate during Idle mode will do so.

Using the disable on Idle feature disables the module

while in Idle mode, allowing further reduction of power

consumption during Idle mode. This enhances power

savings for extremely critical power applications.

 2011 Microchip Technology Inc.

DS31037B-page 109

PIC24F16KL402 FAMILY

NOTES:

DS31037B-page 110

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

a general purpose output pin is disabled. The I/O pin

may be read, but the output driver for the parallel port

bit will be disabled. If a peripheral is enabled, but the

peripheral is not actively driving a pin, that pin may be

driven by a port.

11.0 I/O PORTS

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information on the I/O

Ports, refer to the “PIC24F Family

Reference Manual”, Section 12. “I/O

Ports with Peripheral Pin Select (PPS)”

(DS39711). Note that the PIC24F16KL402

family devices do not support Peripheral

Pin Select features.

All port pins have three registers directly associated

with their operation as digital I/O. The Data Direction

register (TRISx) determines whether the pin is an input

or an output. If the data direction bit is a ‘1’, then the pin

is an input. All port pins are defined as inputs after a

Reset. Reads from the Data Latch register (LATx), read

the latch. Writes to the Data Latch, write the latch.

Reads from the port (PORTx), read the port pins, while

writes to the port pins, write the latch.

All of the device pins (except VDD and VSS) are shared

between the peripherals and the parallel I/O ports. All

I/O input ports feature Schmitt Trigger inputs for

improved noise immunity.

Any bit and its associated data and control registers,

that are not valid for a particular device, will be dis-

abled. That means the corresponding LATx and TRISx

registers, and the port pin will read as zeros.

11.1 Parallel I/O (PIO) Ports

A parallel I/O port that shares a pin with a peripheral is,

in general, subservient to the peripheral. The

peripheral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pin. Figure 11-1 illustrates how ports are shared

with other peripherals and the associated I/O pin to

which they are connected.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is nevertheless,

regarded as a dedicated port because there is no

other competing source of outputs.

FIGURE 11-1:

BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Peripheral Module

Output Multiplexers

Peripheral Input Data

Peripheral Module Enable

Peripheral Output Enable

Peripheral Output Data

I/O

1

Output Enable

0

1

PIO Module

Output Data

0

Read TRIS

Data Bus

WR TRIS

D

Q

I/O Pin

CK

TRIS Latch

D

Q

WR LAT +

WR PORT

CK

Data Latch

Read LAT

Input Data

Read PORT

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11.1.1

OPEN-DRAIN CONFIGURATION

11.2 Configuring Analog Port Pins

In addition to the PORT, LAT and TRIS registers for

data control, each port pin can be individually

configured for either digital or open-drain output. This is

controlled by the Open-Drain Control register, ODCx,

associated with each port. Setting any of the bits

configures the corresponding pin to act as an

open-drain output.

The use of the ANS and TRIS registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs must have their

corresponding TRIS bit set (input). If the TRIS bit is

cleared (output), the digital output level (VOH or VOL)

will be converted.

When reading the PORTx register, all pins configured

as analog input channels will read as cleared (a low

level). Analog levels on any pin that is defined as a dig-

ital input (including the ANx pins) may cause the input

buffer to consume current that exceeds the device

specifications.

The maximum open-drain voltage allowed is the same

as the maximum VIH specification.

11.1.2

I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically, this instruction

would be a NOP.

11.2.1

ANALOG SELECTION REGISTER

I/O pins with shared analog functionality, such as A/D

inputs and comparator inputs, must have their digital

inputs shut off when analog functionality is used. Note

that analog functionality includes an analog voltage

being applied to the pin externally.

To allow for analog control, the ANSx registers are

provided. There is one ANS register for each port

(ANSA and ANSB, Register 11-1 and Register 11-2).

Within each ANSx register, there is a bit for each pin

that shares analog functionality with the digital I/O

functionality. If a particular pin does not have an analog

function, that bit is unimplemented.

DS31037B-page 112

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REGISTER 11-1: ANSA: ANALOG SELECTION (PORTA)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

ANSA3

ANSA2

ANSA1

ANSA0

bit 7

bit 0

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

HSC = Hardware Settable/Clearable bit

‘0’ = Bit is cleared x = Bit is unknown

bit 15-4

bit 3-0

Unimplemented: Read as ‘0’

ANSA<3:0>: Analog Select Control bits

1= Digital input buffer is not active (use for analog input)

0= Digital input buffer is active

REGISTER 11-2: ANSB: ANALOG SELECTION (PORTB)

R/W-1

ANSB13⁽¹⁾

R/W-1

ANSB12⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

ANSB15

ANSB14

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-1

ANSB3⁽²⁾

R/W-1

ANSB2⁽¹⁾

R/W-1

ANSB1⁽¹⁾

R/W-1

ANSB0⁽¹⁾

ANSB4

bit 7

bit 0

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

W = Writable bit

‘1’ = Bit is set

HSC = Hardware Settable/Clearable bit

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-12

ANSB<15:12>: Analog Select Control bits⁽¹⁾

1= Digital input buffer is not active (use for analog input)

0= Digital input buffer is active

bit 11-5

bit 4-0

Unimplemented: Read as ‘0’

ANSB<4:0>: Analog Select Control bits⁽²⁾

1= Digital input buffer is not active (use for analog input)

0= Digital input buffer is active

Note 1: ANSB<13:12,2:0> are unimplemented on 14-pin devices.

2: ANSB<3> is unimplemented on 14-pin and 20-pin devices.

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On any pin, only the pull-up resistor or the pull-down

resistor should be enabled, but not both of them. If the

push button or the keypad is connected to VDD, enable

the pull-down, or if they are connected to VSS, enable

the pull-up resistors. The pull-ups are enabled sepa-

rately using the CNPU1 and CNPU2 registers, which

contain the control bits for each of the CN pins.

11.3 Input Change Notification

The input change notification function of the I/O ports

allows the PIC24F16KL402 family of devices to gener-

ate interrupt requests to the processor in response to a

Change-of-State (COS) on selected input pins. This

feature is capable of detecting input Change-of-States,

even in Sleep mode, when the clocks are disabled.

Depending on the device pin count, there are up to

23 external signals that may be selected (enabled) for

generating an interrupt request on a Change-of-State.

Setting any of the control bits enables the weak

pull-ups for the corresponding pins. The pull-downs are

enabled separately, using the CNPD1 and CNPD2

registers, which contain the control bits for each of the

CN pins. Setting any of the control bits enables the

weak pull-downs for the corresponding pins.

There are six control registers associated with the CN

module. The CNEN1 and CNEN2 registers contain the

interrupt enable control bits for each of the CN input

pins. Setting any of these bits enables a CN interrupt

for the corresponding pins.

When the internal pull-up is selected, the pin uses VDD

as the pull-up source voltage. When the internal

pull-down is selected, the pins are pulled down to VSS

by an internal resistor. Make sure that there is no exter-

nal pull-up source/pull-down sink when the internal

pull-ups/pull-downs are enabled.

Each CN pin also has a weak pull-up/pull-down

connected to it. The pull-ups act as a current source

that is connected to the pin. The pull-downs act as a

current sink to eliminate the need for external resistors

when push button or keypad devices are connected.

Note:

Pull-ups and pull-downs on change notifi-

cation pins should always be disabled

whenever the port pin is configured as a

digital output.

EXAMPLE 11-1:

PORT WRITE/READ EXAMPLE (ASSEMBLY LANGUAGE)

MOV

NOP

BTSS

#0xFF00, W0

W0, TRISB

#0x00FF, W0

W0, ANSB

; Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs

; Enable PORTB<15:8> digital input buffers

; Delay 1 cycle

; Next Instruction

PORTB, #13

EXAMPLE 11-2:

PORT WRITE/READ EXAMPLE (C LANGUAGE)

TRISB = 0xFF00;

ANSB = 0x00FF;

NOP();

// Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs

// Enable PORTB<15:8> digital input buffers

// Delay 1 cycle

if(PORTBbits.RB13 == 1)

// execute following code if PORTB pin 13 is set.

{

}

DS31037B-page 114

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Figure 12-1 illustrates a block diagram of the 16-bit

Timer1 module.

12.0 TIMER1

Note:

This data sheet summarizes the features

To configure Timer1 for operation:

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. For more information on

Timers, refer to the “PIC24F Family Refer-

ence Manual”, Section 14. “Timers”

(DS39704).

1. Set the TON bit (= 1).

2. Select the timer prescaler ratio using the

TCKPS<1:0> bits.

3. Set the Clock and Gating modes using the TCS

and TGATE bits.

4. Set or clear the TSYNC bit to configure

synchronous or asynchronous operation.

The Timer1 module is a 16-bit timer which can operate

as a free-running, interval timer/counter, or serve as the

time counter for a software-based Real-Time Clock

(RTC). Timer1 is only reset on initial VDD power-on

events. This allows the timer to continue operating as an

RTC clock source through other types of device Reset.

5. Load the timer period value into the PR1

register.

6. If interrupts are required, set the interrupt enable

bit, T1IE. Use the priority bits, T1IP<2:0>, to set

the interrupt priority.

Timer1 can operate in three modes:

• 16-Bit Timer

• 16-Bit Synchronous Counter

• 16-Bit Asynchronous Counter

Timer1 also supports these features:

• Timer Gate Operation

• Selectable Prescaler Settings

• Timer Operation During CPU Idle and Sleep modes

• Interrupt on 16-Bit Period Register Match or

Falling Edge of External Gate Signal

FIGURE 12-1:

16-BIT TIMER1 MODULE BLOCK DIAGRAM

TCKPS<1:0>

TON

2

SOSCO/

1x

01

00

T1CK

Prescaler

1, 8, 64, 256

Gate

Sync

SOSCEN

SOSCI

TCY

TGATE

TCS

TGATE

1

0

Q

D

Set T1IF

CK

0

Reset

Equal

TMR1

Sync

1

TSYNC

Comparator

PR1

 2011 Microchip Technology Inc.

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REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0

TON

U-0

—

R/W-0

TSIDL

U-0

—

U-0

—

U-0

—

R/W-0

T1ECS1⁽¹⁾

R/W-0

T1ECS0⁽¹⁾

bit 15

bit 8

U-0

—

R/W-0

U-0

—

R/W-0

TCS

U-0

—

TGATE

TCKPS1

TCKPS0

TSYNC

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

TON: Timer1 On bit

1= Starts 16-bit Timer1

0= Stops 16-bit Timer1

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-10

bit 9-8

Unimplemented: Read as ‘0’

T1ECS <1:0>: Timer1 Extended Clock Select bits⁽¹⁾

11= Reserved; do not use

10= Timer1 uses the LPRC as the clock source

01= Timer1 uses the External Clock from T1CK

00= Timer1 uses the Secondary Oscillator (SOSC) as the clock source

bit 7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timer1 Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation is enabled

0= Gated time accumulation is disabled

bit 5-4

TCKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:256

10= 1:64

01= 1:8

00= 1:1

bit 3

bit 2

Unimplemented: Read as ‘0’

TSYNC: Timer1 External Clock Input Synchronization Select bit

When TCS = 1:

1= Synchronize external clock input

0= Do not synchronize external clock input

When TCS = 0:

This bit is ignored.

bit 1

bit 0

TCS: Timer1 Clock Source Select bit

1= Timer1 clock source is selected by T1ECS<1:0>

0= Internal clock (FOSC/2)

Unimplemented: Read as ‘0’

Note 1: The T1ECS bits are valid only when TCS = 1.

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This module is controlled through the T2CON register

(Register 13-1), which enables or disables the timer

and configures the prescaler and postscaler. Timer2

can be shut off by clearing control bit, TMR2ON

(T2CON<2>), to minimize power consumption.

13.0 TIMER2 MODULE

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. For more information on

Timers, refer to the “PIC24F Family Refer-

ence Manual”, Section 14. “Timers”

(DS39704).

The prescaler and postscaler counters are cleared

when any of the following occurs:

• A write to the TMR2 register

• A write to the T2CON register

The Timer2 module incorporates the following features:

• Any device Reset (POR, BOR, MCLR, or

WDT Reset)

• 8-bit Timer and Period registers (TMR2 and PR2,

respectively)

TMR2 is not cleared when T2CON is written.

• Readable and writable (both registers)

A simplified block diagram of the module is shown in

Figure 13-1.

• Software programmable prescaler (1:1, 1:4 and

1:16)

• Software programmable postscaler (1:1 through

1:16)

• Interrupt on TMR2 to PR2 match

• Optional Timer3 gate on TMR2 to PR2 match

• Optional use as the shift clock for the MSSP

modules

FIGURE 13-1:

TIMER2 BLOCK DIAGRAM

4

1:1 to 1:16

T2OUTPS<3:0>

T2CKPS<1:0>

Set T2IF

Postscaler

2

TMR2 Output

(to PWM or MSSPx)

TMR2/PR2

Match

Reset

TMR2

1:1, 1:4, 1:16

Prescaler

Comparator

PR2

FOSC/2

8

Internal Data Bus

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REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

R/W-0

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0

TMR2ON

T2CKPS1

T2CKPS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-7

bit 6-3

Unimplemented: Read as ‘0’

T2OUTPS<3:0>: Timer2 Output Postscale Select bits

1111= 1:16 Postscale

1110= 1:15 Postscale

•

0001= 1:2 Postscale

0000= 1:1 Postscale

bit 2

TMR2ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0

T2CKPS<1:0>: Timer2 Clock Prescale Select bits

10= Prescaler is 16

01= Prescaler is 4

00= Prescaler is 1

DS31037B-page 118

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• Selectable clock source (internal or external) with

device clock, SOSC or LPRC oscillator options

14.0 TIMER3 MODULE

Note:

This data sheet summarizes the features

• Interrupt-on-overflow

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. For more information on

Timers, refer to the “PIC24F Family Refer-

ence Manual”, Section 14. “Timers”

(DS39704).

• Multiple timer gating options, including:

- user-selectable gate sources and polarity

- gate/toggle operation

- Single-pulse (One-Shot) mode

• Module Reset on ECCP Special Event Trigger

The Timer3 module is controlled through the T3CON

register (Register 14-1). A simplified block diagram of

the Timer3 module is shown in Figure 14-1.

The Timer3 timer/counter modules incorporate these

features:

• Software-selectable operation as a 16-bit timer or

counter

The FOSC clock source should not be used with the

ECCP capture/compare features. If the timer will be

used with the capture or compare features, always

select one of the other timer clocking options.

• One 16-bit readable and writable Timer Value

register

FIGURE 14-1:

TIMER3 BLOCK DIAGRAM

SOSC Components

SOSCEN

TMR3CS<1:0>

EN

SOSCO/T1CK

SOSC

1

0

11

10

01

LPRC

SOSCI

Prescaler

1, 2, 4, 8

Gate Sync

Synchronized

FOSC/2

FOSC

T3CK

00

T3OSCEN

2

Clock Input

T3CKPS<1:0>

1

0

T3SYNC

T3GSS<1:0>

T3G

Set T3GIF

00

01

TMR2 Match

C1OUT

Gate

Control

Toggle

Select

One-Shot

Select

10

11

C2OUT/LPRC

T3GSPM

T3GGO

T3GTM

TMR3GE

T3GPOL

Q

D

Set Flag bit,

T3IF, on

TMR3

Overflow

16

Internal Data Bus

 2011 Microchip Technology Inc.

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REGISTER 14-1: T3CON: TIMER3 CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

U-0

—

R/W-0

TMR3CS1

TMR3CS0

T3CKPS1

T3CKPS0

T3OSCEN

T3SYNC

TMR3ON

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-6

Unimplemented: Read as ‘0’

TMR3CS<1:0>: Clock Source Select bits

11= Low-Power RC Oscillator (LPRC)

10= External clock source (selected by T3CON<3>)

01= Instruction clock (FOSC/2)

00= System clock (FOSC)⁽¹⁾

bit 5-4

T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

bit 3

bit 2

T3OSCEN: Timer Oscillator Enable bit

1= SOSC (Secondary Oscillator) is used as a clock source

0= T3CK digital input pin is used as a clock source

T3SYNC: External Clock Input Synchronization Control bit

When TMR3CS<1:0> = 1x:

1= Do not synchronize the external clock input

0= Synchronize the external clock input⁽²⁾

When TMR3CS<1:0> = 0x:

This bit is ignored; Timer3 uses the internal clock.

bit 1

bit 0

Unimplemented: Read as ‘0’

TMR3ON: Timer On bit

1= Enables Timer

0= Stops Timer

Note 1: The FOSC clock source should not be selected if the timer will be used with the ECCP Capture or Compare

features.

2: This option must be selected when the timer will be used with ECCP/CCP.

DS31037B-page 120

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REGISTER 14-2: T3GCON: TIMER3 GATE CONTROL REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

R-x

R/W-0

TMR3GE

T3GPOL

T3GTM

T3GSPM

T3GGO/

T3DONE

T3GVAL

T3GSS1

T3GSS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-8

bit 7

Unimplemented: Read as ‘0’

TMR3GE: Timer Gate Enable bit

If TMR3ON = 0:

This bit is ignored.

If TMR3ON = 1:

1= Timer counting is controlled by the Timer3 gate function

0= Timer counts regardless of the Timer3 gate function

bit 6

bit 5

T3GPOL: Gate Polarity bit

1= Timer gate is active-high (Timer3 counts when the gate is high)

0= Timer gate is active-low (Timer3 counts when the gate is low)

T3GTM: Gate Toggle Mode bit

1= Timer Gate Toggle mode is enabled.

0= Timer Gate Toggle mode is disabled and toggle flip-flop is cleared

Timer3 gate flip-flop toggles on every rising edge.

bit 4

bit 3

T3GSPM: Timer Gate Single Pulse Mode bit

1= Timer Gate Single Pulse mode is enabled and is controlling Timer3 gate

0= Timer Gate Single Pulse mode is disabled

T3GGO/T3DONE: Timer Gate Single Pulse Acquisition Status bit

1= Timer gate single pulse acquisition is ready, waiting for an edge

0= Timer gate single pulse acquisition has completed or has not been started

This bit is automatically cleared when TxGSPM is cleared.

bit 2

T3GVAL: Timer Gate Current State bit

Indicates the current state of the Timer gate that could be provided to the TMR3 register; unaffected by

the state of TMR3GE.

bit 1-0

T3GSS<1:0>: Timer Gate Source Select bits

11= Comparator 2 output

10= Comparator 1 output

01= TMR2 to match PR2 output

00= T3G input pin

Note 1: Initializing T3GCON prior to T3CON is recommended.

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NOTES:

DS31037B-page 122

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The Timer4 module has a control register shown in

Register 15-1. Timer4 can be shut off by clearing

control bit, TMR4ON (T4CON<2>), to minimize power

consumption. The prescaler and postscaler selection of

Timer4 is controlled by this register.

15.0 TIMER4 MODULE

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. For more information on

Timers, refer to the “PIC24F Family Refer-

ence Manual”, Section 14. “Timers”

(DS39704).

The prescaler and postscaler counters are cleared

when any of the following occurs:

• A write to the TMR4 register

• A write to the T4CON register

The

Timer4

module

is

implemented

in

• Any device Reset (POR, BOR, MCLR or WDT

Reset)

PIC24FXXKL30X/40X devices only. It has the following

features:

TMR4 is not cleared when T4CON is written.

• Eight-bit Timer register (TMR4)

Figure 15-1 is a simplified block diagram of the Timer4

module.

• Eight-bit Period register (PR4)

• Readable and writable (all registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMR4 match of PR4

FIGURE 15-1:

TIMER4 BLOCK DIAGRAM

4

1:1 to 1:16

T4OUTPS<3:0>

Set T4IF

Postscaler

2

TMR4 Output

T4CKPS<1:0>

(to PWM)

TMR4/PR4

Match

Reset

8

1:1, 1:4, 1:16

Comparator

PR4

FOSC/2

TMR4

Prescaler

8

Internal Data Bus

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REGISTER 15-1: T4CON: TIMER4 CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

R/W-0

T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0

TMR4ON

T4CKPS1

T4CKPS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-7

bit 6-3

Unimplemented: Read as ‘0’

T4OUTPS<3:0>: Timer4 Output Postscale Select bits

1111= 1:16 Postscale

1110= 1:15 Postscale

•

0001= 1:2 Postscale

0000= 1:1 Postscale

bit 2

TMR4ON: Timer4 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0

T4CKPS<1:0>: Timer4 Clock Prescale Select bits

10= Prescaler is 16

01= Prescaler is 4

00= Prescaler is 1

DS31037B-page 124

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

16.1 Timer Selection

16.0 CAPTURE/COMPARE/PWM

(CCP) AND ENHANCED CCP

MODULES

On all PIC24F16KL402 family devices, the CCP and

ECCP modules use Timer3 as the time base for cap-

ture and compare operations. PWM and Enhanced

PWM operations may use either Timer2 or Timer4.

PWM time base selection is done through the

CCPTMRS0 register (Register 16-6).

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be

a

comprehensive

reference source. For more information

on the Capture/Compare/PWM module,

refer to the “PIC24F Family Reference

Manual”.

16.2 CCP I/O Pins

To configure I/O pins with a CCP function, the proper

mode must be selected by setting the CCPxM<3:0>

bits.

Depending on the particular device, PIC24F16KL402

family devices include up to three CCP and/or ECCP

modules. Key features of all CCP modules include:

Where the Enhanced CCP module is available, it may

have up to four PWM outputs, depending on the

selected operating mode. These outputs are desig-

nated, P1A through P1D. The outputs that are active

depend on the ECCP operating mode selected. To

configure I/O pins for Enhanced PWM operation, the

proper PWM mode must be selected by setting the

PM<1:0> and CCPM<3:0> bits.

• 16-bit input capture for a range of edge events

• 16-bit output compare with multiple output options

• Single-output Pulse Width Modulation (PWM) with

up to 10 bits of resolution

• User-selectable time base from any available

timer

• Special Event Trigger on capture and compare

events to automatically trigger a range of

peripherals

ECCP modules also include these features:

• Operation in Half-Bridge and Full-Bridge (Forward

and Reverse) modes

• Pulse steering control across any or all Enhanced

PWM pins, with user-configurable steering

synchronization

• User-configurable External Fault Detect with

Auto-Shutdown and Auto Restart

PIC24FXXKL40X/30X devices instantiate three CCP

modules, one Enhanced (CCP1) and two standard

(CCP2 and CCP). All other devices instantiate two

standard CCP modules (CCP1 and CCP2).

 2011 Microchip Technology Inc.

DS31037B-page 125

PIC24F16KL402 FAMILY

FIGURE 16-1:

GENERIC CAPTURE MODE BLOCK DIAGRAM

Set CCPxIF

TMR3H

TMR3L

(E)CCPx Pin

Prescaler

 1, 4, 16

and

Edge Detect

CCPRxH

CCPRxL

4

CCPxCON<3:0>

Q1:Q4

4

FIGURE 16-2:

GENERIC COMPARE MODE BLOCK DIAGRAM

Special Event Trigger

(Timer3 Reset)

Set CCPxIF

CCPRxH

CCPRxL

CCPx Pin

S

R

Q

Output

Logic

Compare

Match

Comparator

CCP

Output Enable

4

TMR3H

TMR3L

CCPxCON<3:0>

FIGURE 16-3:

SIMPLIFIED PWM BLOCK DIAGRAM

CCPxCON<5:4>

Duty Cycle Registers

CCPRxL

CCPRxH (Slave)

Comparator

R

S

Q

CCPx

TMR2⁽²⁾

(1)

CCP

Output Enable

Comparator

PR2⁽²⁾

Clear Timer,

CCP1 Pin and

Latch D.C.

Note 1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.

2: Either Timer2 or Timer4 may be used as the PWM time base.

DS31037B-page 126

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

FIGURE 16-4:

SIMPLIFIED BLOCK DIAGRAM OF ENHANCED PWM MODE

DC1B<1:0>

Duty Cycle Registers

PM<1:0>

CCP1M<3:0>

2

4

CCPR1L

ECCP1/P1A

P1B

ECCP1/P1A Output

P1B Output

ECCP Enable

CCPR1H (Slave)

Comparator

Output

Controller

Q

R

S

P1C

P1C Output

TMR2⁽²⁾

(1)

P1D

P1D Output

Comparator

PR2⁽²⁾

Clear Timer,

CCP1 Pin and

Latch D.C.

ECCP1DEL

Note 1: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base.

2: Either Timer2 or Timer4 may be used as the Enhanced PWM time base.

 2011 Microchip Technology Inc.

DS31037B-page 127

PIC24F16KL402 FAMILY

REGISTER 16-1: CCPxCON: CCPx CONTROL REGISTER (STANDARD CCP MODULES)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

R/W-0

CCPxM3⁽¹⁾

R/W-0

CCPxM2⁽¹⁾

R/W-0

CCPxM1⁽¹⁾

R/W-0

CCPxM0⁽¹⁾

bit 0

DCxB1

DCxB0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-6

bit 5-4

Unimplemented: Read as ‘0’

DCxB<1:0>: PWM Duty Cycle Bit 1 and Bit 0 for CCPx Module

Capture and Compare modes:

Unused.

PWM mode:

These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight

Most Significant bits (DCxB<9:2>) of the duty cycle are found in CCPRxL.

bit 3-0

CCPxM<3:0>: CCPx Module Mode Select bits⁽¹⁾

1111= Reserved

1110= Reserved

1101= Reserved

1100= PWM mode

1011= Compare mode: Special Event Trigger; reset timer on CCPx match (CCPxIF bit is set)

1010= Compare mode: Generate software interrupt on compare match (CCPxIF bit is set, CCPx pin

reflects I/O state)

1001= Compare mode: Initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF

bit is set)

1000= Compare mode: Initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is

set)

0111= Capture mode: Every 16th rising edge

0110= Capture mode: Every 4th rising edge

0101= Capture mode: Every rising edge

0100= Capture mode: Every falling edge

0011= Reserved

0010= Compare mode: Toggle output on match (CCPxIF bit is set)

0001= Reserved

0000= Capture/Compare/PWM is disabled (resets CCPx module)

Note 1: CCPxM<3:0> = 1011will only reset the timer and not start the A/D conversion on a CCPx match.

DS31037B-page 128

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

REGISTER 16-2: CCP1CON: ECCP1 CONTROL REGISTER (ECCP MODULES ONLY)⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

PM1

R/W-0

PM0

R/W-0

DC1B1

DC1B0

CCP1M3⁽²⁾CCP1M2⁽²⁾CCP1M1⁽²⁾CCP1M0⁽²⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-8

bit 7-6

Unimplemented: Read as ‘0’

PM<1:0>: Enhanced PWM Output Configuration bits

If CCP1M<3:2> = 00, 01, 10:

xx= P1A is assigned as capture input or compare output; P1B, P1C and P1D are assigned as port pins

If CCP1M<3:2> = 11:

11= Full-bridge output reverse: P1B is modulated; P1C is active; P1A and P1D are inactive

10= Half-bridge output: P1A, P1B are modulated with dead-band control; P1C and P1D are

assigned as port pins

01= Full-bridge output forward: P1D is modulated; P1A is active; P1B, P1C are inactive

00= Single output: P1A, P1B, P1C and P1D are controlled by steering

bit 5-4

bit 3-0

DC1B<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCP1 Module

Capture and Compare modes:

Unused.

PWM mode:

These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight

Most Significant bits (DC1B<9:2>) of the duty cycle are found in CCPR1L.

CCP1M<3:0>: CCP1 Module Mode Select bits⁽²⁾

1111= PWM mode: PA and PC are active-low; PB and PD are active-low

1110= PWM mode: PA and PC are active-low; PB and PD are active-high

1101= PWM mode: PA and PC are active-high; PB and PD are active-low

1100= PWM mode: PA and PC are active-high; PB and PD are active-high

1011= Compare mode: Special Event Trigger; reset timer on CCP1 match (CCPxIF bit is set)

1010= Compare mode: Generate software interrupt on compare match (CCP1IF bit is set, CCP1 pin

reflects I/O state)

1001= Compare mode: Initialize CCP1 pin high; on compare match, force CCP1 pin low (CCP1IF bit is

set)

1000= Compare mode: Initialize CCP1 pin low; on compare match, force CCP1 pin high (CCP1IF

bit is set)

0111= Capture mode: Every 16th rising edge

0110= Capture mode: Every 4th rising edge

0101= Capture mode: Every rising edge

0100= Capture mode: Every falling edge

0011= Reserved

0010= Compare mode: Toggle output on match (CCP1IF bit is set)

0001= Reserved

0000= Capture/Compare/PWM is disabled (resets CCP1 module)

Note 1: This register is implemented only on PIC24FXXKL40X/30X devices. For all other devices, CCP1CON is

configured as Register 16-1.

2: CCP1M<3:0> = 1011will only reset timer and not start A/D conversion on CCP1 match.

 2011 Microchip Technology Inc.

DS31037B-page 129

PIC24F16KL402 FAMILY

REGISTER 16-3: ECCP1AS: ECCP1 AUTO-SHUTDOWN CONTROL REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

ECCPASE

ECCPAS2

ECCPAS1

ECCPAS0

PSSAC1

PSSAC0

PSSBD1

PSSBD0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

ECCPASE: ECCP Auto-Shutdown Event Status bit

1= A shutdown event has occurred; ECCP outputs are in a shutdown state

0= ECCP outputs are operating

bit 6-4

ECCPAS<2:0>: ECCP Auto-Shutdown Source Select bits

111= VIL on FLT0 pin, or either C1OUT or C2OUT is high

110= VIL on FLT0 pin, or C2OUT comparator output is high

101= VIL on FLT0 pin, or C1OUT comparator output is high

100= VIL on FLT0 pin

011= Either C1OUT or C2OUT is high

010= C2OUT comparator output is high

001= C1OUT comparator output is high

000= Auto-shutdown is disabled

bit 3-2

bit 1-0

PSSAC<1:0>: PxA and PxC Pins Shutdown State Control bits

1x= P1A and P1C pins tri-state

01= Drive pins P1A and P1C to ‘1’

00= Drive pins P1A and P1C to ‘0’

PSSBD<1:0>: PxB and PxD Pins Shutdown State Control bits

1x= P1B and P1D pins tri-state

01= Drive pins, P1B and P1D, to ‘1’

00= Drive pins, P1B and P1D, to ‘0’

Note 1: This register is implemented only on PIC24FXXKL40X/30X devices.

Note 1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is

present, the auto-shutdown will persist.

2: Writing to the ECCPASE bit is disabled while an auto-shutdown condition persists.

3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or

auto-restart), the PWM signal will always restart at the beginning of the next PWM period.

DS31037B-page 130

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

REGISTER 16-4: ECCP1DEL: ECCP1 ENHANCED PWM CONTROL REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

PDC6

R/W-0

PDC5

R/W-0

PDC4

R/W-0

PDC3

R/W-0

PDC2

R/W-0

PDC1

R/W-0

PDC0

PRSEN

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

PRSEN: PWM Restart Enable bit

1= Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away;

the PWM restarts automatically

0= Upon auto-shutdown, ECCPASE must be cleared by software to restart the PWM

bit 6-0

PDC<6:0>: PWM Delay Count bits

PDCn = Number of FCY (FOSC/2) cycles between the scheduled time when a PWM signal

should transition active and the actual time it transitions active.

Note 1: This register is implemented only on PIC24FXXKL40X/30X devices.

 2011 Microchip Technology Inc.

DS31037B-page 131

PIC24F16KL402 FAMILY

REGISTER 16-5: PSTR1CON: PULSE STEERING CONTROL REGISTER FOR ECCP1⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

U-0

—

R/W-0

STRD

R/W-0

STRC

R/W-0

STRB

R/W-1

STRA

CMPL1

CMPL0

STRSYNC

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-8

bit 7-6

Unimplemented: Read as ‘0’

CMPL<1:0>: Complementary Mode Output Assignment Steering bits

00= Complementary output assignment is disabled; the STR<D:A> bits are used to determine

Steering mode

01= PxA and PxB are selected as the complementary output pair

10= PxA and PxC are selected as the complementary output pair

11= PxA and PxD are selected as the complementary output pair

bit 5

bit 4

Unimplemented: Read as ‘0’

STRSYNC: Steering Sync bit

1= Output steering update occurs on the next PWM period

0= Output steering update occurs at the beginning of the instruction cycle boundary

bit 3

bit 2

bit 1

bit 0

STRD: Steering Enable D bit

1= P1D pin has the PWM waveform with polarity control from CCP1M<1:0>

0= P1D pin is assigned to port pin

STRC: Steering Enable C bit

1= P1C pin has the PWM waveform with polarity control from CCP1M<1:0>

0= P1C pin is assigned to port pin

STRB: Steering Enable B bit

1= P1B pin has the PWM waveform with polarity control from CCP1M<1:0>

0= P1B pin is assigned to port pin

STRA: Steering Enable A bit

1= P1A pin has the PWM waveform with polarity control from CCP1M<1:0>

0= P1A pin is assigned to port pin

Note 1: This register is only implemented on PIC24FXXKL40X/30X devices. In addition, PWM Steering mode is

available only when CCP1M<3:2> = 11and PM<1:0> = 00.

DS31037B-page 132

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

REGISTER 16-6: CCPTMRS0: CCP TIMER SELECT CONTROL REGISTER 0⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0

C3TSEL0

C2TSEL0

C1TSEL0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-7

bit 6

Unimplemented: Read as ‘0’

C3TSEL0: CCP3 Timer Selection bit

1= CCP3 uses TMR3/TMR4

0= CCP3 uses TMR3/TMR2

bit 5-4

bit 3

Unimplemented: Read as ‘0’

C2TSEL0: CCP2 Timer Selection bit

1= CCP2 uses TMR3/TMR4

0= CCP2 uses TMR3/TMR2

bit 2-1

bit 0

Unimplemented: Read as ‘0’

C1TSEL0: CCP1/ECCP1 Timer Selection bit

1= CCP1/ECCP1 uses TMR3/TMR4

0= CCP1/ECCP1 uses TMR3/TMR2

Note 1: This register is unimplemented on PIC24FXXKL20X/10X devices; maintain as ‘0’.

 2011 Microchip Technology Inc.

DS31037B-page 133

PIC24F16KL402 FAMILY

NOTES:

DS31037B-page 134

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

17.1 I/O Pin Configuration for SPI

17.0 MASTER SYNCHRONOUS

SERIAL PORT (MSSP)

In SPI Master mode, the MSSP module will assert con-

trol over any pins associated with the SDOx and SCKx

outputs. This does not automatically disable other digi-

tal functions associated with the pin, and may result in

the module driving the digital I/O port inputs. To prevent

this, the MSSP module outputs must be disconnected

from their output pins while the module is in SPI Master

mode. While disabling the module temporarily may be

an option, it may not be a practical solution in all

applications.

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be

a

comprehensive

reference source. For more information

on MSSP, refer to the “PIC24F Family

Reference Manual”.

The Master Synchronous Serial Port (MSSP) module is

an 8-bit serial interface, useful for communicating with

other peripheral or microcontroller devices. These

peripheral devices may be serial EEPROMs, Shift reg-

isters, display drivers, A/D Converters, etc. The MSSP

module can operate in one of two modes:

The SDOx and SCKx outputs for the module can be

selectively disabled by using the SDOxDIS and

SCKxDIS bits in the PADCFG1 register (Register 17-10).

Setting the bit disconnects the corresponding output for a

particular module from its assigned pin.

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I²C™)

- Full Master mode

- Slave mode (with general address call)

The SPI interface supports these modes in hardware:

• Master mode

• Slave mode

• Daisy-Chaining Operation in Slave mode

• Synchronized Slave operation

The I²C interface supports the following modes in

hardware:

• Master mode

• Multi-Master mode

• Slave mode with 10-Bit And 7-Bit Addressing and

Address Masking

• Byte NACKing

• Selectable Address and Data Hold and Interrupt

Masking

 2011 Microchip Technology Inc.

DS31037B-page 135

PIC24F16KL402 FAMILY

FIGURE 17-1:

MSSP BLOCK DIAGRAM (SPI MODE)

Internal Data Bus

Write

Read

SSPxBUF

SDIx

SSPxSR

Shift Clock

bit 0

SDOx

SSx

SSx Control Enable

Edge

Select

2

Clock Select

SSPxADD<7:0>

SSPM<3:0>

4

7

SMP:CKE

2

TMR2 Output

(

)

2

SCKx

Baud

Rate

Generator

Edge

Select

TOSC

Prescaler

4, 16, 64

Data to TXx/RXx in SSPxSR

TRIS bit

Note: Refer to the device data sheet for pin multiplexing.

FIGURE 17-2:

SPI MASTER/SLAVE CONNECTION

SPI Master SSPM<3:0> = 00xx

SPI Slave SSPM<3:0> = 010x

SDOx

SDIx

Serial Input Buffer

(SSPxBUF)

Serial Input Buffer

(SSPxBUF)

SDIx

SDOx

SCKx

Shift Register

(SSPxSR)

Shift Register

(SSPxSR)

LSb

MSb

PROCESSOR 1

LSb

PROCESSOR 2

Serial Clock

SCKx

DS31037B-page 136

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

FIGURE 17-3:

MSSP BLOCK DIAGRAM (I²C™ MODE)

Internal Data Bus

Read

Write

SSPxBUF

SCLx

SDAx

Shift

Clock

SSPxSR

MSb

LSb

Address Mask

Match Detect

SSPxADD

Address Match

Start and

Stop bit Detect

Set/Reset S, P bits

Note: Only port I/O names are shown in this diagram. Refer to the text for a full list of multiplexed functions.

2

FIGURE 17-4:

MSSP BLOCK DIAGRAM (I C™ MASTER MODE)

Internal Data Bus

Read

Write

SSPM<3:0>

SSPxADD<6:0>

SSPxBUF

SSPxSR

SDAx

Shift

Clock

Baud

Rate

Generator

SDAx In

MSb

LSb

Start bit, Stop bit,

Acknowledge

Generate

SCLx

Clock Cntl

Start bit Detect

Stop bit Detect

Write Collision Detect

Clock Arbitration

State Counter for

end of XMIT/RCV

RCV Enable

SCLx In

Clock Arbitrate/WCOL Detect

(hold off clock source)

Bus Collision

Set/Reset S, P (SSPxSTAT), WCOL

Set SSPxIF, BCLxIF

Reset ACKSTAT, PEN

 2011 Microchip Technology Inc.

DS31037B-page 137

PIC24F16KL402 FAMILY

REGISTER 17-1: SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

R/W-0

SMP

R/W-0

CKE⁽¹⁾

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-8

bit 7

Unimplemented: Read as ‘0’

SMP: Sample bit

SPI Master mode:

1= Input data is sampled at the end of data output time

0= Input data is sampled at the middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode.

bit 6

CKE: SPI Clock Select bit⁽¹⁾

1= Transmit occurs on transition from active to Idle clock state

0= Transmit occurs on transition from Idle to active clock state

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

D/A: Data/Address bit

Used in I²C™ mode only.

P: Stop bit

Used in I²C mode only. This bit is cleared when the MSSPx module is disabled; SSPEN is cleared.

S: Start bit

Used in I²C mode only.

R/W: Read/Write Information bit

Used in I²C mode only.

UA: Update Address bit

Used in I²C mode only.

BF: Buffer Full Status bit

1= Receive is complete, SSPxBUF is full

0= Receive is not complete, SSPxBUF is empty

Note 1: Polarity of clock state is set by the CKP bit (SSPxCON1<4>).

DS31037B-page 138

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

REGISTER 17-2: SSPxSTAT: MSSPx STATUS REGISTER (I²C™ MODE)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P⁽¹⁾

R-0

S⁽¹⁾

R-0

UA

R-0

BF

R/W

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

SMP: Slew Rate Control bit

In Master or Slave mode:

1 = Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz)

0 = Slew rate control is enabled for High-Speed mode (400 kHz)

bit 6

bit 5

CKE: SMBus Select bit

In Master or Slave mode:

1= Enable SMBus specific inputs

0= Disable SMBus specific inputs

D/A: Data/Address bit

In Master mode:

Reserved.

In Slave mode:

1= Indicates that the last byte received or transmitted was data

0= Indicates that the last byte received or transmitted was address

bit 4

bit 3

bit 2

P: Stop bit⁽¹⁾

1= Indicates that a Stop bit has been detected last

0= Stop bit was not detected last

S: Start bit⁽¹⁾

1= Indicates that a Start bit has been detected last

0= Start bit was not detected last

R/W: Read/Write Information bit

In Slave mode:⁽²⁾

1= Read

0= Write

In Master mode:⁽³⁾

1= Transmit is in progress

0= Transmit is not in progress

bit 1

UA: Update Address bit (10-bit Slave mode only)

1= Indicates that the user needs to update the address in the SSPxADD register

0= Address does not need to be updated

Note 1: This bit is cleared on RESETand when SSPEN is cleared.

2: This bit holds the R/W bit information following the last address match. This bit is only valid from the

address match to the next Start bit, Stop bit or not ACK bit.

3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Active mode.

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REGISTER 17-2: SSPxSTAT: MSSPx STATUS REGISTER (I²C™ MODE) (CONTINUED)

bit 0

BF: Buffer Full Status bit

In Transmit mode:

1= Transmit is in progress, SSPxBUF is full

0= Transmit is complete, SSPxBUF is empty

In Receive mode:

1= SSPxBUF is full (does not include the ACK and Stop bits)

0= SSPxBUF is empty (does not include the ACK and Stop bits)

Note 1: This bit is cleared on RESETand when SSPEN is cleared.

2: This bit holds the R/W bit information following the last address match. This bit is only valid from the

address match to the next Start bit, Stop bit or not ACK bit.

3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Active mode.

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REGISTER 17-3: SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

WCOL

R/W-0

SSPOV⁽¹⁾

R/W-0

SSPEN⁽²⁾

R/W-0

CKP

R/W-0

SSPM3⁽³⁾

R/W-0

SSPM2⁽³⁾

R/W-0

SSPM1⁽³⁾

R/W-0

SSPM0⁽³⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

WCOL: Write Collision Detect bit

1= The SSPxBUF register is written while it is still transmitting the previous word

(must be cleared in software)

0= No collision

bit 6

SSPOV: Receive Overflow Indicator bit⁽¹⁾

SPI Slave mode:

1= A new byte is received while the SSPxBUF register is still holding the previous data. In case of over-

flow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the

SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).

0= No overflow

bit 5

SSPEN: Master Synchronous Serial Port Enable bit⁽²⁾

1= Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins

0= Disables serial port and configures these pins as I/O port pins

bit 4

CKP: Clock Polarity Select bit

1= Idle state for clock is a high level

0= Idle state for clock is a low level

bit 3-0

SSPM<3:0>: Master Synchronous Serial Port Mode Select bits⁽³⁾

1010= SPI Master mode, Clock = FOSC/(2 * ([SSPxADD] + 1))

0101= SPI Slave mode, Clock = SCKx pin; SSx pin control is disabled, SSx can be used as an I/O pin

0100= SPI Slave mode, Clock = SCKx pin; SSx pin control is enabled

0011= SPI Master mode, Clock = TMR2 output/2

0010= SPI Master mode, Clock = FOSC/32

0001= SPI Master mode, Clock = FOSC/8

0000= SPI Master mode, Clock = FOSC/2

Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by

writing to the SSPxBUF register.

2: When enabled, these pins must be properly configured as input or output.

3: Bit combinations not specifically listed here are either reserved or implemented in I²C mode only.

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REGISTER 17-4: SSPxCON1: MSSPx CONTROL REGISTER 1 (I²C™ MODE)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

WCOL

R/W-0

SSPEN⁽¹⁾

R/W-0

CKP

R/W-0

SSPM3⁽²⁾

R/W-0

SSPM2⁽²⁾

R/W-0

SSPM1⁽²⁾

R/W-0

SSPM0⁽²⁾

SSPOV

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-8

bit 7

Unimplemented: Read as ‘0’

WCOL: Write Collision Detect bit

In Master Transmit mode:

1= A write to the SSPxBUF register was attempted while the I²C conditions were not valid for a

transmission to be started (must be cleared in software)

0= No collision

In Slave Transmit mode:

1= The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in

software)

0= No collision

In Receive mode (Master or Slave modes):

This is a “don’t care” bit.

bit 6

SSPOV: Receive Overflow Indicator bit

In Receive mode:

1= A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in

software)

0= No overflow

In Transmit mode:

This is a “don’t care” bit in Transmit mode.

bit 5

bit 4

SSPEN: Master Synchronous Serial Port Enable bit⁽¹⁾

1= Enables the serial port and configures the SDAx and SCLx pins as the serial port pins

0= Disables the serial port and configures these pins as I/O port pins

CKP: SCLx Release Control bit

In Slave mode:

1= Releases clock

0= Holds clock low (clock stretch), used to ensure data setup time

In Master mode:

Unused in this mode.

bit 3-0

SSPM<3:0>: Master Synchronous Serial Port Mode Select bits⁽²⁾

1111= I²C Slave mode, 10-bit address with Start and Stop bit interrupts is enabled

1110= I²C Slave mode, 7-bit address with Start and Stop bit interrupts is enabled

1011= I²C Firmware Controlled Master mode (Slave Idle)

1000= I²C Master mode, clock = FOSC/(2 * ([SSPxADD] + 1))⁽³⁾

0111= I²C Slave mode, 10-bit address

0110= I²C Slave mode, 7-bit address

Note 1: When enabled, the SDAx and SCLx pins must be configured as inputs.

2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.

3: SSPxADD values of 0, 1 or 2 are not supported when the Baud Rate Generator is used with I²C mode.

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REGISTER 17-5: SSPxCON2: MSSPx CONTROL REGISTER 2 (I²C™ MODE)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

GCEN

R/W-0

ACKDT⁽¹⁾

R/W-0

ACKEN⁽²⁾

R/W-0

RCEN⁽²⁾

R/W-0

PEN⁽²⁾

R/W-0

RSEN⁽²⁾

R/W-0

SEN⁽²⁾

ACKSTAT

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

GCEN: General Call Enable bit (Slave mode only)

1= Enables interrupt when a general call address (0000h) is received in the SSPxSR

0= General call address is disabled

bit 6

bit 5

bit 4

ACKSTAT: Acknowledge Status bit (Master Transmit mode only)

1= Acknowledge was not received from slave

0= Acknowledge was received from slave

ACKDT: Acknowledge Data bit (Master Receive mode only)⁽¹⁾

1= No Acknowledge

0= Acknowledge

ACKEN: Acknowledge Sequence Enable bit (Master mode only)⁽²⁾

1= Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit;

automatically cleared by hardware

0= Acknowledge sequence is Idle

bit 3

bit 2

bit 1

bit 0

RCEN: Receive Enable bit (Master Receive mode only)⁽²⁾

1= Enables Receive mode for I²C

0= Receive is Idle

PEN: Stop Condition Enable bit (Master mode only)⁽²⁾

1= Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware

0= Stop condition is Idle

RSEN: Repeated Start Condition Enable bit (Master mode only)⁽²⁾

1= Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware

0= Repeated Start condition is Idle

SEN: Start Condition Enable bit⁽²⁾

Master Mode:

1= Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware

0= Start condition is Idle

Slave Mode:

1= Clock stretching is enabled for both slave transmit and slave receive (stretch is enabled)

0= Clock stretching is disabled

Note 1: The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a

receive.

2: If the I²C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written

(or writes to the SSPxBUF are disabled).

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REGISTER 17-6: SSPxCON3: MSSPx CONTROL REGISTER 3 (SPI MODE)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R-0

R/W-0

PCIE

R/W-0

SCIE

R/W-0

BOEN⁽¹⁾

R/W-0

AHEN

R/W-0

DHEN

ACKTIM

SDAHT

SBCDE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

ACKTIM: Acknowledge Time Status bit (I²C™ mode only)

Unused in SPI mode.

bit 6

bit 5

bit 4

PCIE: Stop Condition Interrupt Enable bit (I²C mode only)

Unused in SPI mode.

SCIE: Start Condition Interrupt Enable bit (I²C mode only)

Unused in SPI mode.

BOEN: Buffer Overwrite Enable bit⁽¹⁾

In SPI Slave mode:

1= SSPxBUF updates every time that a new data byte is shifted in, ignoring the BF bit

0= If a new byte is received with the BF bit of the SSPxSTAT register already set, the SSPxOV bit of

the SSPxCON1 register is set and the buffer is not updated

bit 3

bit 2

SDAHT: SDAx Hold Time Selection bit (I²C mode only)

Unused in SPI mode.

SBCDE: Slave Mode Bus Collision Detect Enable bit (I²C Slave mode only)

Unused in SPI mode.

bit 1

bit 0

AHEN: Address Hold Enable bit (I²C Slave mode only)

Unused in SPI mode.

DHEN: Data Hold Enable bit (Slave mode only)

Unused in SPI mode.

Note 1: For daisy-chained SPI operation: Allows the user to ignore all but the last received byte. SSPxOV is still

set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to

SSPxBUF.

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REGISTER 17-7: SSPxCON3: MSSPx CONTROL REGISTER 3 (I²C™ MODE)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R-0

ACKTIM⁽¹⁾

R/W-0

PCIE

R/W-0

SCIE

R/W-0

BOEN

R/W-0

AHEN

R/W-0

DHEN

SDAHT

SBCDE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

ACKTIM: Acknowledge Time Status bit⁽¹⁾

1= Indicates the I²C bus is in an Acknowledge sequence, set on the 8^thfalling edge of the SCLx clock

0= Not an Acknowledge sequence, cleared on 9^thrising edge of SCLx clock

bit 6

bit 5

bit 4

PCIE: Stop Condition Interrupt Enable bit

1= Enable interrupt on detection of Stop condition

0= Stop detection interrupts are disabled⁽²⁾

SCIE: Start Condition Interrupt Enable bit

1= Enable interrupt on detection of Start or Restart conditions

0= Start detection interrupts are disabled⁽²⁾

BOEN: Buffer Overwrite Enable bit

I.²C Master mode:

This bit is ignored.

I²C Slave mode:

1= SSPxBUF is updated and an ACK is generated for a received address/data byte, ignoring the state

of the SSPxOV bit only if the BF bit = 0

0= SSPxBUF is only updated when SSPxOV is clear

bit 3

bit 2

SDAHT: SDAx Hold Time Selection bit

1= Minimum of 300 ns hold time on SDAx after the falling edge of SCLx

0= Minimum of 100 ns hold time on SDAx after the falling edge of SCLx

SBCDE: Slave Mode Bus Collision Detect Enable bit (Slave mode only)

1= Enables slave bus collision interrupts

0= Slave bus collision interrupts are disabled

bit 1

bit 0

AHEN: Address Hold Enable bit (Slave mode only)

1= Following the 8th falling edge of SCLx for a matching received address byte; CKP bit of the

SSPxCON1 register will be cleared and the SCLx will be held low.

0= Address holding is disabled

DHEN: Data Hold Enable bit (Slave mode only)

1= Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit

of the SSPxCON1 register and SCLx is held low.

0= Data holding is disabled

Note 1: This bit has no effect in Slave modes for which Start and Stop condition detection is explicitly listed as

enabled.

2: The ACKTIM status bit is active only when the AHEN bit or DHEN bit is set.

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REGISTER 17-8: SSPxADD: MSSPx SLAVE ADDRESS/BAUD RATE GENERATOR REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

ADD7

R/W-0

ADD6

R/W-0

ADD5

R/W-0

ADD4

R/W-0

ADD3

R/W-0

ADD2

R/W-0

ADD1

R/W-0

ADD0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

Unimplemented: Read as ‘0’

ADD<7:0>: Slave Address/Baud Rate Generator Value bits

SPI Master and I²C Master modes:

Reload value for Baud Rate Generator. Clock period is (([SPxADD] + 1) *2)/FOSC.

I²C™ Slave modes:

Represents 7 or 8 bits of the slave address, depending on the addressing mode used:

7-Bit mode: Address is ADD<7:1>; ADD<0> is ignored.

10-Bit LSb mode: ADD<7:0> are the Least Significant bits of the address.

10-Bit MSb mode: ADD<2:1> are the two Most Significant bits of the address; ADD<7:3> are always

‘11110’ as a specification requirement; ADD<0> is ignored.

REGISTER 17-9: SSPxMSK: I²C SLAVE ADDRESS MASK REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-1

MSK7

R/W-1

MSK6

R/W-1

MSK5

R/W-1

MSK4

R/W-1

MSK3

R/W-1

MSK2

R/W-1

MSK1

R/W-1

MSK0⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

Unimplemented: Read as ‘0’

MSK<7:0>: Slave Address Mask Select bit⁽¹⁾

1= Masking of corresponding bit of SSPxADD enabled

0= Masking of corresponding bit of SSPxADD disabled

Note 1: MSK0 is not used as a mask bit in 7-bit addressing.

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REGISTER 17-10: PADCFG1: PAD CONFIGURATION CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SDO2DIS⁽¹⁾SCK2DIS⁽¹⁾

SDO1DIS

SCK1DIS

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 11

Unimplemented: Read as ‘0’

SDO2DIS: MSSP2 SDO Pin Disable bit⁽¹⁾

1= The SPI output data (SDO2) of MSSP2 to the pin is disabled

0= The SPI output data (SDO2) of MSSP2 is output to the pin

bit 10

bit 9

SCK2DIS: MSSP2 SCK Pin Disable bit⁽¹⁾

1= The SPI clock (SCK2) of MSSP2 to the pin is disabled

0= The SPI clock (SCK2) of MSSP2 is output to the pin

SDO1DIS: MSSP1 SDO Pin Disable bit

1= The SPI output data (SDO1) of MSSP1 to the pin is disabled

0= The SPI output data (SDO1) of MSSP1 is output to the pin

bit 8

SCK1DIS: MSSP1 SCK Pin Disable bit

1= The SPI clock (SCK1) of MSSP1 to the pin is disabled

0= The SPI clock (SCK1) of MSSP1 is output to the pin

bit 7-0

Unimplemented: Read as ‘0’

Note 1: These bits are implemented only on PIC24FXXKL40X/30X devices.

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NOTES:

DS31037B-page 148

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• Fully Integrated Baud Rate Generator (IBRG) with

16-Bit Prescaler

18.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART)

• Baud Rates Ranging from 1 Mbps to 15 bps at

16 MIPS

• Two-Level Deep, First-In-First-Out (FIFO)

Transmit Data Buffer

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. For more information on the

• Two-Level Deep, FIFO Receive Data Buffer

• Parity, Framing and Buffer Overrun Error

Detection

Universal

Asynchronous

Receiver

Transmitter, refer to the “PIC24F Family

Reference Manual”, Section 21. “UART”

(DS39708).

• Support for 9-Bit mode with Address Detect

(9^thbit = 1)

• Transmit and Receive Interrupts

The Universal Asynchronous Receiver Transmitter

(UART) module is one of the serial I/O modules

available in this PIC24F device family. The UART is a

full-duplex, asynchronous system that can communicate

with peripheral devices, such as personal computers,

LIN/J2602, RS-232 and RS-485 interfaces. This module

also supports a hardware flow control option with the

UxCTS and UxRTS pins, and also includes an IrDA^®

encoder and decoder.

• Loopback mode for Diagnostic Support

• Support for Sync and Break Characters

• Supports Automatic Baud Rate Detection

• IrDA Encoder and Decoder Logic

• 16x Baud Clock Output for IrDA Support

A simplified block diagram of the UART is shown in

Figure 18-1. The UART module consists of these

important hardware elements:

The primary features of the UART module are:

• Baud Rate Generator

• Asynchronous Transmitter

• Asynchronous Receiver

• Full-Duplex, 8-Bit or 9-Bit Data Transmission

Through the UxTX and UxRX Pins

• Even, Odd or No Parity Options (for 8-bit data)

• One or Two Stop bits

• Hardware Flow Control Option with UxCTS and

UxRTS Pins

FIGURE 18-1:

UART SIMPLIFIED BLOCK DIAGRAM

Baud Rate Generator

IrDA^®

UxBCLK

Hardware Flow Control

UARTx Receiver

UxRTS

UxCTS

UxRX

UARTx Transmitter

UxTX

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The maximum baud rate (BRGH = 0) possible is

FCY/16 (for UxBRG = 0) and the minimum baud rate

possible is FCY/(16 * 65536).

18.1 UART Baud Rate Generator (BRG)

The UART module includes a dedicated 16-bit Baud

Rate Generator (BRG). The UxBRG register controls

the period of a free-running, 16-bit timer. Equation 18-1

provides the formula for computation of the baud rate

with BRGH = 0.

Equation 18-2 shows the formula for computation of

the baud rate with BRGH = 1.

EQUATION 18-2: UART BAUD RATE WITH

BRGH = 1⁽¹⁾

EQUATION 18-1: UART BAUD RATE WITH

BRGH = 0⁽¹⁾

FCY

Baud Rate =

4 • (UxBRG + 1)

FCY

Baud Rate =

16 • (UxBRG + 1)

FCY

4 • Baud Rate

– 1

UxBRG =

FCY

16 • Baud Rate

– 1

UxBRG =

Note 1: Based on FCY = FOSC/2; Doze mode

and PLL are disabled.

Note 1: Based on FCY = FOSC/2; Doze mode

and PLL are disabled.

The maximum baud rate (BRGH = 1) possible is FCY/4

(for UxBRG = 0) and the minimum baud rate possible

is FCY/(4 * 65536).

Example 18-1 provides the calculation of the baud rate

error for the following conditions:

Writing a new value to the UxBRG register causes the

BRG timer to be reset (cleared). This ensures the BRG

does not wait for a timer overflow before generating the

new baud rate.

• FCY = 4 MHz

• Desired Baud Rate = 9600

EXAMPLE 18-1:

BAUD RATE ERROR CALCULATION (BRGH = 0)⁽¹⁾

Desired Baud Rate

= FCY/(16 (UxBRG + 1))

Solving for UxBRG value:

UxBRG

= ((FCY/Desired Baud Rate)/16) – 1

= ((4000000/9600)/16) – 1

= 25

Calculated Baud Rate = 4000000/(16 (25 + 1))

= 9615

Error

= (Calculated Baud Rate – Desired Baud Rate)

Desired Baud Rate

= (9615 – 9600)/9600

= 0.16%

Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.

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18.2 Transmitting in 8-Bit Data Mode

18.5 Receiving in 8-Bit or 9-Bit Data

Mode

1. Set up the UART:

a) Write appropriate values for data, parity and

Stop bits.

1. Set up the UART (as described in Section 18.2

“Transmitting in 8-Bit Data Mode”).

b) Write appropriate baud rate value to the

UxBRG register.

2. Enable the UART.

3. A receive interrupt will be generated when one

or more data characters have been received as

per interrupt control bit, URXISELx.

c) Set up transmit and receive interrupt enable

and priority bits.

2. Enable the UART.

4. Read the OERR bit to determine if an overrun

error has occurred. The OERR bit must be reset

in software.

3. Set the UTXEN bit (causes a transmit interrupt,

two cycles after being set).

5. Read UxRXREG.

4. Write data byte to lower byte of UxTXREG word.

The value will be immediately transferred to the

Transmit Shift Register (TSR) and the serial bit

stream will start shifting out with the next rising

edge of the baud clock.

The act of reading the UxRXREG character will move

the next character to the top of the receive FIFO,

including a new set of PERR and FERR values.

5. Alternately, the data byte may be transferred

while UTXEN = 0 and then, the user may set

UTXEN. This will cause the serial bit stream to

begin immediately, because the baud clock will

start from a cleared state.

18.6 Operation of UxCTS and UxRTS

Control Pins

UARTx Clear-to-Send (UxCTS) and Request-to-Send

(UxRTS) are the two hardware-controlled pins that are

associated with the UART module. These two pins

allow the UART to operate in Simplex and Flow Control

modes. They are implemented to control the

transmission and reception between the Data Terminal

Equipment (DTE). The UEN<1:0> bits in the UxMODE

register configure these pins.

6. A transmit interrupt will be generated as per

interrupt control bit, UTXISELx.

18.3 Transmitting in 9-Bit Data Mode

1. Set up the UART (as described in Section 18.2

“Transmitting in 8-Bit Data Mode”).

2. Enable the UART.

18.7 Infrared Support

3. Set the UTXEN bit (causes a transmit interrupt,

two cycles after being set).

The UART module provides two types of infrared UART

support: one is the IrDA clock output to support an

external IrDA encoder and decoder device (legacy

module support), and the other is the full

implementation of the IrDA encoder and decoder.

4. Write UxTXREG as a 16-bit value only.

5. A word write to UxTXREG triggers the transfer

of the 9-bit data to the TSR. The serial bit stream

will start shifting out with the first rising edge of

the baud clock.

As the IrDA modes require a 16x baud clock, they will

only work when the BRGH bit (UxMODE<3>) is ‘0’.

6. A transmit interrupt will be generated as per the

setting of control bit, UTXISELx.

18.7.1

EXTERNAL IrDA SUPPORT – IrDA

CLOCK OUTPUT

18.4 Break and Sync Transmit

Sequence

To support external IrDA encoder and decoder devices,

the UxBCLK pin (same as the UxRTS pin) can be

configured to generate the 16x baud clock. When

UEN<1:0> = 11, the UxBCLK pin will output the 16x

baud clock if the UART module is enabled; it can be

used to support the IrDA codec chip.

The following sequence will send a message frame

header made up of a Break, followed by an auto-baud

Sync byte.

1. Configure the UART for the desired mode.

18.7.2

BUILT-IN IrDA ENCODER AND

DECODER

2. Set UTXEN and UTXBRK – sets up the Break

character.

3. Load the UxTXREG with a dummy character to

initiate transmission (value is ignored).

The UART has full implementation of the IrDA encoder

and decoder as part of the UART module. The built-in

IrDA encoder and decoder functionality is enabled

using the IREN bit (UxMODE<12>). When enabled

(IREN = 1), the receive pin (UxRX) acts as the input

from the infrared receiver. The transmit pin (UxTX) acts

as the output to the infrared transmitter.

4. Write ‘55h’ to UxTXREG – loads the Sync

character into the transmit FIFO.

5. After the Break has been sent, the UTXBRK bit

is reset by hardware. The Sync character now

transmits.

 2011 Microchip Technology Inc.

DS31037B-page 151

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REGISTER 18-1: UxMODE: UARTx MODE REGISTER

R/W-0

U-0

—

R/W-0

USIDL

R/W-0

IREN⁽¹⁾

R/W-0

U-0

—

R/W-0⁽²⁾

UEN1

R/W-0⁽²⁾

UEN0

UARTEN

RTSMD

bit 15

bit 8

R/C-0, HC

WAKE

R/W-0

R/W-0, HC

ABAUD

R/W-0

RXINV

R/W-0

BRGH

R/W-0

LPBACK

PDSEL1

PDSEL0

STSEL

bit 7

bit 0

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

HC = Hardware Clearable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

bit 15

UARTEN: UARTx Enable bit

1= UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>

0= UARTx is disabled; all UARTx pins are controlled by port latches, UARTx power consumption is

minimal

bit 14

bit 13

Unimplemented: Read as ‘0’

USIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12

bit 11

IREN: IrDA^®Encoder and Decoder Enable bit⁽¹⁾

1= IrDA encoder and decoder are enabled

0= IrDA encoder and decoder are disabled

RTSMD: Mode Selection for UxRTS Pin bit

1= UxRTS pin is in Simplex mode

0= UxRTS pin is in Flow Control mode

bit 10

Unimplemented: Read as ‘0’

bit 9-8

UEN<1:0>: UARTx Enable bits⁽²⁾

11= UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by port latches

10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used

01= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches

00= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by

port latches

bit 7

WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit

1= UARTx will continue to sample the UxRX pin; interrupt is generated on the falling edge, bit is

cleared in hardware on the following rising edge

0= No wake-up is enabled

bit 6

bit 5

LPBACK: UARTx Loopback Mode Select bit

1= Enable Loopback mode

0= Loopback mode is disabled

ABAUD: Auto-Baud Enable bit

1= Enable baud rate measurement on the next character – requires reception of a Sync field (55h);

cleared in hardware upon completion

0= Baud rate measurement is disabled or completed

bit 4

RXINV: Receive Polarity Inversion bit

1= UxRX Idle state is ‘0’

0= UxRX Idle state is ‘1’

Note 1: This feature is is only available for the 16x BRG mode (BRGH = 0).

2: Bit availability depends on pin availability.

DS31037B-page 152

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PIC24F16KL402 FAMILY

REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED)

bit 3

BRGH: High Baud Rate Enable bit

1= BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)

0= BRG generates 16 clocks per bit period (16x baud clock, Standard mode)

bit 2-1

PDSEL<1:0>: Parity and Data Selection bits

11= 9-bit data, no parity

10= 8-bit data, odd parity

01= 8-bit data, even parity

00= 8-bit data, no parity

bit 0

STSEL: Stop Bit Selection bit

1= Two Stop bits

0= One Stop bit

Note 1: This feature is is only available for the 16x BRG mode (BRGH = 0).

2: Bit availability depends on pin availability.

 2011 Microchip Technology Inc.

DS31037B-page 153

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REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER

R/W-0

UTXISEL1

bit 15

R/W-0

U-0

—

R/W-0, HC

UTXBRK

R/W-0

R-0, HSC

UTXBF

R-1, HSC

TRMT

UTXINV

UTXISEL0

UTXEN

bit 8

R/W-0

URXISEL1

bit 7

R/W-0

R-1, HSC

RIDLE

R-0, HSC

PERR

R-0, HSC

FERR

R/C-0, HS

OERR

R-0, HSC

URXDA

URXISEL0

ADDEN

bit 0

Legend:

HC = Hardware Clearable bit

HS = Hardware Settable bit C = Clearable bit

HSC = Hardware Settable/Clearable bit

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15,13

UTXISEL<1:0>: Transmission Interrupt Mode Selection bits

11= Reserved; do not use

10= Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the

transmit buffer becomes empty

01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations

are completed

00= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at

least one character open in the transmit buffer)

bit 14

UTXINV: IrDA^®Encoder Transmit Polarity Inversion bit

If IREN = 0:

1= UxTX Idle ‘0’

0= UxTX Idle ‘1’

If IREN = 1:

1= UxTX Idle ‘1’

0= UxTX Idle ‘0’

bit 12

bit 11

Unimplemented: Read as ‘0’

UTXBRK: Transmit Break bit

1= Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits; followed by Stop bit;

cleared by hardware upon completion

0= Sync Break transmission is disabled or completed

bit 10

UTXEN: Transmit Enable bit

1= Transmit is enabled; UxTX pin is controlled by UARTx

0= Transmit is disabled; any pending transmission is aborted and the buffer is reset. UxTX pin is

controlled by the PORT register.

bit 9

bit 8

UTXBF: Transmit Buffer Full Status bit (read-only)

1= Transmit buffer is full

0= Transmit buffer is not full, at least one more character can be written

TRMT: Transmit Shift Register Empty bit (read-only)

1= Transmit Shift Register is empty and the transmit buffer is empty (the last transmission has

completed)

0= Transmit Shift Register is not empty; a transmission is in progress or queued

bit 7-6

URXISEL<1:0>: Receive Interrupt Mode Selection bits

11= Interrupt is set on the RSR transfer, making the receive buffer full (i.e., has 2 data characters)

10= Reserved

01= Reserved

00= Interrupt is set when any character is received and transferred from the RSR to the receive buffer;

receive buffer has one or more characters

DS31037B-page 154

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REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)

bit 5

bit 4

bit 3

bit 2

bit 1

ADDEN: Address Character Detect bit (bit 8 of the received data = 1)

1= Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect

0= Address Detect mode is disabled

RIDLE: Receiver Idle bit (read-only)

1= Receiver is Idle

0= Receiver is active

PERR: Parity Error Status bit (read-only)

1= Parity error has been detected for the current character (character at the top of the receive FIFO)

0= Parity error has not been detected

FERR: Framing Error Status bit (read-only)

1= Framing error has been detected for the current character (character at the top of the receive FIFO)

0= Framing error has not been detected

OERR: Receive Buffer Overrun Error Status bit (clear/read-only)

1= Receive buffer has overflowed

0= Receive buffer has not overflowed (clearing a previously set OERR bit (1 0transition) will reset

the receiver buffer and the RSR to the empty state)

bit 0

URXDA: Receive Buffer Data Available bit (read-only)

1= Receive buffer has data; at least one more character can be read

0= Receive buffer is empty

 2011 Microchip Technology Inc.

DS31037B-page 155

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NOTES:

DS31037B-page 156

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

A block diagram of the A/D Converter is displayed in

Figure 19-1.

19.0 10-BIT HIGH-SPEED A/D

CONVERTER

To perform an A/D conversion:

1. Configure the A/D module:

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

a) Configure port pins as analog inputs and/or

select band gap reference inputs

(ANSA<3:0>, ANSB<15:12, 4:0> and

ANCFG<0>).

intended to be

a

comprehensive

reference source. For more information

on the 10-Bit High-Speed A/D Converter,

refer to the “PIC24F Family Reference

Manual”, Section 17. “10-Bit A/D

Converter” (DS39705).

b) Select the voltage reference source to

match the expected range on analog inputs

(AD1CON2<15:13>).

The 10-bit A/D Converter has the following key

features:

c) Select the analog conversion clock to match

the desired data rate with the processor

clock (AD1CON3<7:0>).

• Successive Approximation (SAR) conversion

• Conversion speeds of up to 500 ksps

• Up to 12 analog input pins

d) Select the appropriate sample/conversion

sequence

(AD1CON1<7:5>

and

AD1CON3<12:8>).

• External voltage reference input pins

• Internal band gap reference input

• Automatic Channel Scan mode

e) Select how conversion results are

presented in the buffer (AD1CON1<9:8>).

f) Select interrupt rate (AD1CON2<5:2>).

g) Turn on A/D module (AD1CON1<15>).

2. Configure A/D interrupt (if required):

a) Clear the AD1IF bit.

• Selectable conversion trigger source

• Two-word conversion result buffer

• Selectable Buffer Fill modes

• Four result alignment options

b) Select A/D interrupt priority.

• Operation during CPU Sleep and Idle modes

Depending on the particular device, PIC24F16KL402

family devices implement up to 12 analog input pins,

designated AN0 through AN4 and AN9 through AN15.

In addition, there are two analog input pins for external

voltage reference connections (VREF+ and VREF-).

These voltage reference inputs may be shared with

other analog input pins.

 2011 Microchip Technology Inc.

DS31037B-page 157

PIC24F16KL402 FAMILY

FIGURE 19-1:

10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM

Internal Data Bus

16

AVDD

AVSS

VR+

VR-

VREF+

VREF-

Comparator

VINH

VINL

VR- VR+

DAC

S/H

10-Bit SAR

Conversion Logic

AN0

AN1

VINH

AN2⁽¹⁾

AN3⁽¹⁾

AN4⁽¹⁾

Data Formatting

AN1

VINL

ADC1BUF0:

ADC1BUF1

AN9

AN10

AN11⁽¹⁾

AN12⁽¹⁾

AD1CON1

AD1CON2

AD1CON3

AD1CHS

VINH

AD1CSSL

AN13

AN14

AN15

VBG

VINL

AN1

Sample Control

Control Logic

Conversion Control

Input MUX Control

Pin Config Control

Note 1: Unimplemented in 14-pin devices.

DS31037B-page 158

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REGISTER 19-1: AD1CON1: A/D CONTROL REGISTER 1

R/W-0

ADON⁽¹⁾

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

ADSIDL

FORM1

FORM0

bit 15

bit 8

R/W-0

U-0

—

U-0

—

R/W-0

ASAM

R/W-0, HSC

SAMP

R

-0, HSC

DONE

bit 0

SSRC2

SSRC1

SSRC0

bit 7

Legend:

HSC = Hardware Settable/Clearable bit

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

ADON: A/D Operating Mode bit⁽¹⁾

1= A/D Converter module is operating

0= A/D Converter is off

bit 14

bit 13

Unimplemented: Read as ‘0’

ADSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-10

bit 9-8

Unimplemented: Read as ‘0’

FORM<1:0>: Data Output Format bits

11= Signed fractional (sddd dddd dd00 0000)

10= Fractional (dddd dddd dd00 0000)

01= Signed integer (ssss sssd dddd dddd)

00= Integer (0000 00dd dddd dddd)

bit 7-5

SSRC<2:0>: Conversion Trigger Source Select bits

111= Internal counter ends sampling and starts conversion (auto-convert)

110= Reserved

101= Reserved

100= Reserved

011= Reserved

010= Timer1 compare ends sampling and starts conversion

001= Active transition on INT0 pin ends sampling and starts conversion

000= Clearing the SAMP bit ends sampling and starts conversion

bit 4-3

bit 2

Unimplemented: Read as ‘0’

ASAM: A/D Sample Auto-Start bit

1= Sampling begins immediately after the last conversion completes; SAMP bit is auto-set

0= Sampling begins when the SAMP bit is set

bit 1

bit 0

SAMP: A/D Sample Enable bit

1= A/D sample/hold amplifier is sampling input

0= A/D sample/hold amplifier is holding

DONE: A/D Conversion Status bit

1= A/D conversion is done

0= A/D conversion is not done

Note 1: Values of ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out the

conversion values from the buffer before disabling the module.

 2011 Microchip Technology Inc.

DS31037B-page 159

PIC24F16KL402 FAMILY

REGISTER 19-2: AD1CON2: A/D CONTROL REGISTER 2

R/W-0

OFFCAL⁽¹⁾

U-0

—

R/W-0

U-0

—

U-0

—

VCFG2

VCFG1

VCFG0

CSCNA

bit 15

bit 8

R-x

—

U-0

—

R/W-0

SMPI3

R/W-0

SMPI2

R/W-0

SMPI1

R/W-0

SMPI0

r-0

—

R/W-0

ALTS

bit 7

bit 0

Legend:

r = Reserved bit

W = Writable bit

‘1’ = Bit is set

HSC = Hardware Settable/Clearable bit

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-13

VCFG<2:0>: Voltage Reference Configuration bits

VCFG<2:0>

VR+

VR-

000

001

010

011

1xx

AVDD

External VREF+ pin

AVDD

AVSS

External VREF- pin

AVSS

External VREF+ pin

AVDD

bit 12

OFFCAL: Offset Calibration bit⁽¹⁾

1= Conversions to get the offset calibration value

0= Conversions to get the actual input value

bit 11

bit 10

Unimplemented: Read as ‘0’

CSCNA: Scan Input Selections for MUX A Input Multiplexer bit

1= Scan inputs

0= Do not scan inputs

bit 9-8

bit 7

Unimplemented: Read as ‘0’

Reserved: Ignore this value

Unimplemented: Read as ‘0’

bit 6

bit 5-2

SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits

1111

.

= Reserved, do not use (may cause conversion data loss)

.

0010

0001= Interrupts at the completion of conversion for each 2^ndsample/convert sequence

0000= Interrupts at the completion of conversion for each sample/convert sequence

bit 1

bit 0

Reserved: Always maintain as ‘0’

ALTS: Alternate Input Sample Mode Select bit

1= Uses MUX A input multiplexer settings for the first sample, then alternates between MUX B and

MUX A input multiplexer settings for all subsequent samples

0= Always uses MUX A input multiplexer settings

Note 1: When the OFFCAL bit is set, inputs are disconnected and tied to AVSS. This sets the inputs of the A/D to

zero. Then, the user can perform a conversion. Use of the Calibration mode is not affected by AD1PCFG

contents nor channel input selection. Any analog input switches are disconnected from the A/D Converter

in this mode. The conversion result is stored by the user software and used to compensate subsequent

conversions. This can be done by adding the two’s complement of the result obtained with the OFFCAL bit

set to all normal A/D conversions.

DS31037B-page 160

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REGISTER 19-3: AD1CON3: A/D CONTROL REGISTER 3

R-0

R/W-0

ADRC

R/W-0

EXTSAM

PUMPEN

SAMC4

SAMC3

SAMC2

SAMC1

SAMC0

bit 15

bit 8

U-0

R/W-0

—

ADCS5

ADCS4

ADCS3

ADCS2

ADCS1

ADCS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

bit 12-8

ADRC: A/D Conversion Clock Source bit

1= A/D internal RC clock

0= Clock derived from system clock

EXTSAM: Extended Sampling Time bit

1= A/D is still sampling after SAMP = 0

0= A/D is finished sampling

PUMPEN: Charge Pump Enable bit

1= Charge pump for switches is enabled

0= Charge pump for switches is disabled

SAMC<4:0>: Auto-Sample Time bits

11111= 31 TAD

·

00001= 1 TAD

00000= 0 TAD (not recommended)

bit 7-6

bit 5-0

Unimplemented: Maintain as ‘0’

ADCS<5:0>: A/D Conversion Clock Select bits

11111= 64 • TCY

11110= 63 • TCY

·

00001= 2 • TCY

00000= TCY

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DS31037B-page 161

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-

REGISTER 19-4: AD1CHS: A/D INPUT SELECT REGISTER

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

CH0NB

CH0SB3

CH0SB2

CH0SB1

CH0SB0

bit 15

bit 8

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

CH0NA

CH0SA3

CH0SA2

CH0SA1

CH0SA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit

1= Channel 0 negative input is AN1

0= Channel 0 negative input is VR-

bit 14-12

bit 11-8

Unimplemented: Read as ‘0’

CH0SB<3:0>: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits

1111= AN15

1110= AN14

1101= AN13

1100= AN12⁽¹⁾

1011= AN11⁽¹⁾

1010= AN10

1001= AN9

1000= Upper guardband rail (0.785 * VDD)

0111= Lower guardband rail (0.215 * VDD)

0110= Internal band gap reference (VBG)

0101= Reserved; do not use

0100= AN4⁽¹⁾

0011= AN3⁽¹⁾

0010= AN2⁽¹⁾

0001= AN1

0000= AN0

bit 7

CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit

1= Channel 0 negative input is AN1

0= Channel 0 negative input is VR-

bit 6-5

bit 4-0

Unimplemented: Read as ‘0’

CH0SA<3:0>: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits

Bit combinations are identical to those for CH0SB<3:0> (above).

Note 1: Unimplemented on 14-pin devices; do not use.

DS31037B-page 162

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REGISTER 19-5: AD1CSSL: A/D INPUT SCAN SELECT REGISTER

R/W-0

CSSL15

CSSL14

CSSL13

CSSL12⁽¹⁾

CSSL11⁽¹⁾

CSSL10

CSSL9

CSSL8

bit 15

bit 8

R/W-0

U-0

—

R/W-0

CSSL4⁽¹⁾

R/W-0

CSSL3⁽¹⁾

R/W-0

CSSL2⁽¹⁾

R/W-0

CSSL7

CSSL6

CSSL1

CSSL0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-6

CSSL<15:6>: A/D Input Pin Scan Selection bits⁽¹⁾

1= Corresponding analog channel selected for input scan

0= Analog channel omitted from input scan

bit 5

Unimplemented: Read as ‘0’

bit 4-0

CSSL<4:0>: A/D Input Pin Scan Selection bits⁽¹⁾

1= Corresponding analog channel selected for input scan

0= Analog channel omitted from input scan

Note 1: These bits are unimplemented on 14-pin devices.

REGISTER 19-6: ANCFG: ANALOG INPUT CONFIGURATION REGISTER

U

-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U

-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

—

VBGEN

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-1

bit 0

Unimplemented: Read as ‘0’

VBGEN: Internal Band Gap Reference Enable bit

1= Internal Band Gap voltage is available as a channel input to the A/D Converter

0= Band gap is not available to the A/D Converter

 2011 Microchip Technology Inc.

DS31037B-page 163

PIC24F16KL402 FAMILY

EQUATION 19-1: A/D CONVERSION CLOCK PERIOD⁽¹⁾

TAD

TCY

ADCS =

– 1

TAD = TCY • (ADCS + 1)

Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.

FIGURE 19-2:

10-BIT A/D CONVERTER ANALOG INPUT MODEL

VDD

RIC  250W

Sampling

RSS  5 k (Typical)

Switch

VT = 0.6V

ANx

RSS

Rs

CHOLD

= DAC capacitance

= 4.4 pF (Typical)

VA

CPIN

6-11 pF

ILEAKAGE

±500 nA

VT = 0.6V

(Typical)

VSS

Legend: CPIN

VT

= Input Capacitance

= Threshold Voltage

ILEAKAGE = Leakage Current at the pin due to

Various Junctions

RIC

= Interconnect Resistance

RSS

= Sampling Switch Resistance

= Sample/Hold Capacitance (from DAC)

CHOLD

Note:

CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs  5 k.

DS31037B-page 164

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

FIGURE 19-3:

A/D TRANSFER FUNCTION

Digital Output Code

Binary (Decimal)

11 1111 1111(1023)

11 1111 1110(1022)

10 0000 0011(515)

10 0000 0010(514)

10 0000 0001(513)

10 0000 0000(512)

01 1111 1111(511)

01 1111 1110(510)

01 1111 1101(509)

00 0000 0001(1)

00 0000 0000(0)

Voltage Level

 2011 Microchip Technology Inc.

DS31037B-page 165

PIC24F16KL402 FAMILY

NOTES:

DS31037B-page 166

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

The comparator outputs may be directly connected to

the CxOUT pins. When the respective COE equals ‘1’,

the I/O pad logic makes the unsynchronized output of

the comparator available on the pin.

20.0 COMPARATOR MODULE

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. For more information on the

Comparator module, refer to the “PIC24F

Family Reference Manual”, Section 19.

“Dual Comparator Module” (DS39710).

A simplified block diagram of the module is displayed in

Figure 20-1. Diagrams of the possible individual

comparator

Figure 20-2.

configurations

are

displayed

in

Each comparator has its own control register,

CMxCON (Register 20-1), for enabling and configuring

its operation. The output and event status of all three

comparators is provided in the CMSTAT register

(Register 20-2).

Depending on the particular device, the comparator

module provides one or two analog comparators. The

inputs to the comparator can be configured to use any

one of up to four external analog inputs, as well as a

voltage reference input from either the internal band

gap reference, divided by 2 (VBG/2), or the comparator

voltage reference generator.

FIGURE 20-1:

COMPARATOR MODULE BLOCK DIAGRAM

CCH<1:0>

CREF

EVPOL<1:0>

CEVT

COUT

Trigger/Interrupt

Logic

CXINB

COE

CPOL

Input

Select

Logic

VIN-

(1)

CXINC

C1

VIN+

(1)

CXIND

C1OUT

VBG/2

(Note 2)

EVPOL<1:0>

CPOL

CEVT

COUT

Trigger/Interrupt

Logic

COE

CXINA

CVREF

VIN-

C2

VIN+

C2OUT

Note 1: These inputs are unavailable on 14-pin (PIC24FXXKL100/200) devices.

2: Comparator 2 is unimplemented on PIC24FXXKL10X/20X devices.

 2011 Microchip Technology Inc.

DS31037B-page 167

PIC24F16KL402 FAMILY

FIGURE 20-2:

INDIVIDUAL COMPARATOR CONFIGURATIONS

Comparator Off

CON = 0, CREF = x, CCH<1:0> = xx

COE

VIN-

-

Cx

VIN+

Off (Read as ‘0’)

CxOUT

(1)

Comparator CxINB > CxINA Compare

Comparator CxINC > CxINA Compare

CON = 1, CREF = 0, CCH<1:0> = 00

CON = 1, CREF = 0, CCH<1:0> = 01

COE

VIN-

-

CXINB

CXINA

CXINC

CXINA

Cx

VIN+

CxOUT

(1)

Comparator VBG > CxINA Compare

Comparator CxIND > CxINA Compare

CON = 1, CREF = 0, CCH<1:0> = 11

CON = 1, CREF = 0, CCH<1:0> = 10

COE

VIN-

-

VBG/2

CXINA

CXIND

Cx

VIN+

CXINA

CxOUT

(1)

Comparator CxINB > CVREF Compare

CON = 1, CREF = 1, CCH<1:0> = 00

Comparator CxINC > CVREF Compare

CON = 1, CREF = 1, CCH<1:0> = 01

COE

VIN-

-

CXINB

CXINC

CVREF

Cx

VIN+

CVREF

CxOUT

(1)

Comparator CxIND > CVREF Compare

CON = 1, CREF = 1, CCH<1:0> = 10

Comparator VBG > CVREF Compare

CON = 1, CREF = 1, CCH<1:0> = 11

COE

VIN-

-

CXIND

CVREF

VBG/2

Cx

VIN+

CVREF

CxOUT

Note 1: This configuration is unavailable on 14-pin (PIC24FXXKL100/200) devices.

DS31037B-page 168

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PIC24F16KL402 FAMILY

REGISTER 20-1: CMxCON: COMPARATOR x CONTROL REGISTERS

R/W-0

CON

R/W-0

COE

R/W-0

CPOL

R/W-0

U-0

—

U-0

—

R/W-0

CEVT

R-0

CLPWR

COUT

bit 15

bit 8

R/W-0

U-0

—

R/W-0

CREF

U-0

—

U-0

—

R/W-0

CCH1

R/W-0

CCH0

EVPOL1

EVPOL0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

bit 13

bit 12

CON: Comparator Enable bit

1= Comparator is enabled

0= Comparator is disabled

COE: Comparator Output Enable bit

1= Comparator output is present on the CxOUT pin

0= Comparator output is internal only

CPOL: Comparator Output Polarity Select bit

1= Comparator output is inverted

0= Comparator output is not inverted

CLPWR: Comparator Low-Power Mode Select bit

1= Comparator operates in Low-Power mode

0= Comparator does not operate in Low-Power mode

bit 11-10

bit 9

Unimplemented: Read as ‘0’

CEVT: Comparator Event bit

1= Comparator event defined by EVPOL<1:0> has occurred; subsequent triggers and interrupts are

disabled until the bit is cleared

0= Comparator event has not occurred

bit 8

COUT: Comparator Output bit

When CPOL = 0:

1= VIN+ > VIN-

0= VIN+ < VIN-

When CPOL = 1:

1= VIN+ < VIN-

0= VIN+ > VIN-

bit 7-6

EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits

11= Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0)

10= Trigger/event/interrupt is generated on transition of the comparator output:

If CPOL = 0 (non-inverted polarity):

High-to-low transition only.

If CPOL = 1 (inverted polarity):

Low-to-high transition only.

01= Trigger/event/interrupt generated on transition of comparator output:

If CPOL = 0 (non-inverted polarity):

Low-to-high transition only.

If CPOL = 1 (inverted polarity):

High-to-low transition only.

00= Trigger/event/interrupt generation is disabled

Unimplemented: Read as ‘0’

bit 5

Note 1: Unimplemented on 14-pin (PIC24FXXKL100/200) devices.

 2011 Microchip Technology Inc.

DS31037B-page 169

PIC24F16KL402 FAMILY

REGISTER 20-1: CMxCON: COMPARATOR x CONTROL REGISTERS (CONTINUED)

bit 4

CREF: Comparator Reference Select bits (non-inverting input)

1= Non-inverting input connects to the internal CVREF voltage

0= Non-inverting input connects to the CxINA pin

bit 3-2

bit 1-0

Unimplemented: Read as ‘0’

CCH<1:0>: Comparator Channel Select bits

11= Inverting input of the comparator connects to VBG/2

10= Inverting input of the comparator connects to CxIND pin⁽¹⁾

01= Inverting input of the comparator connects to CxINC pin⁽¹⁾

00= Inverting input of the comparator connects to CxINB pin

Note 1: Unimplemented on 14-pin (PIC24FXXKL100/200) devices.

REGISTER 20-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0, HSC

C2EVT⁽¹⁾

R-0, HSC

C1EVT

CMIDL

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0, HSC

C2OUT⁽¹⁾

R-0, HSC

C1OUT

bit 7

bit 0

Legend:

HSC = Hardware Settable/Clearable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

CMIDL: Comparator Stop in Idle Mode bit

1= Discontinue operation of all comparators when device enters Idle mode

0= Continue operation of all enabled comparators in Idle mode

bit 14-10

bit 9

Unimplemented: Read as ‘0’

C2EVT: Comparator 2 Event Status bit (read-only)⁽¹⁾

Shows the current event status of Comparator 2 (CM2CON<9>).

C1EVT: Comparator 1 Event Status bit (read-only)

Shows the current event status of Comparator 1 (CM1CON<9>).

Unimplemented: Read as ‘0’

C2OUT: Comparator 2 Output Status bit (read-only)⁽¹⁾

Shows the current output of Comparator 2 (CM2CON<8>).

C1OUT: Comparator 1 Output Status bit (read-only)

Shows the current output of Comparator 1 (CM1CON<8>).

bit 8

bit 7-2

bit 1

bit 0

Note 1: These bits are unimplemented on PIC24FXXKL10X/20X devices.

DS31037B-page 170

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PIC24F16KL402 FAMILY

21.1 Configuring the Comparator

Voltage Reference

21.0 COMPARATOR VOLTAGE

REFERENCE

The comparator voltage reference module is controlled

through the CVRCON register (Register 21-1). The

comparator voltage reference provides a range of

output voltages, with 32 distinct levels.

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information on the

Comparator Voltage Reference, refer to

the “PIC24F Family Reference Manual”,

Section 20. “Comparator Voltage

Reference Module” (DS39709).

The comparator voltage reference supply voltage can

come from either VDD and VSS, or the external VREF+

and VREF-. The voltage source is selected by the

CVRSS bit (CVRCON<5>).

The settling time of the comparator voltage reference

must be considered when changing the CVREF output.

FIGURE 21-1:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

CVRSS = 1

VREF+

AVDD

8R

CVRSS = 0

CVR<3:0>

R

CVREN

R

32 Steps

CVREF

R

8R

CVRSS = 1

VREF-

CVRSS = 0

AVSS

 2011 Microchip Technology Inc.

DS31037B-page 171

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REGISTER 21-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

CVR4

R/W-0

CVR3

R/W-0

CVR2

R/W-0

CVR1

R/W-0

CVR0

CVREN

CVROE

CVRSS

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-8

bit 7

Unimplemented: Read as ‘0’

CVREN: Comparator Voltage Reference Enable bit

1= CVREF circuit is powered on

0= CVREF circuit is powered down

bit 6

CVROE: Comparator VREF Output Enable bit

1= CVREF voltage level is output on the CVREF pin

0= CVREF voltage level is disconnected from the CVREF pin

bit 5

CVRSS: Comparator VREF Source Selection bit

1= Comparator reference source, CVRSRC = VREF+ – VREF-

0= Comparator reference source, CVRSRC = AVDD – AVSS

bit 4-0

CVR<4:0>: Comparator VREF Value Selection 0 ≤ CVR<4:0> ≤ 31 bits

When CVRSS = 1:

CVREF = (VREF-) + (CVR<4:0>/32) • (VREF+ – VREF-)

When CVRSS = 0:

CVREF = (AVSS) + (CVR<4:0>/32) • (AVDD – AVSS)

DS31037B-page 172

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An interrupt flag is set if the device experiences an

excursion past the trip point in the direction of change.

If the interrupt is enabled, the program execution will

branch to the interrupt vector address and the software

can then respond to the interrupt.

22.0 HIGH/LOW-VOLTAGE DETECT

(HLVD)

Note:

This data sheet summarizes the features of

this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information on the

High/Low-Voltage Detect, refer to the

“PIC24F Family Reference Manual”,

Section 36. “High-Level Integration

with Programmable High/Low-Voltage

Detect (HLVD)” (DS39725).

The HLVD Control register (see Register 22-1)

completely controls the operation of the HLVD module.

This allows the circuitry to be “turned off” by the user

under software control, which minimizes the current

consumption for the device.

The High/Low-Voltage Detect module (HLVD) is a

programmable circuit that allows the user to specify

both the device voltage trip point and the direction of

change.

FIGURE 22-1:

HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM

Externally Generated

Trip Point

VDD

HLVDL<3:0>

HLVDIN

VDIR

HLVDEN

Set

HLVDIF

-

Internal Voltage

Reference

1.2V Typical

HLVDEN

 2011 Microchip Technology Inc.

DS31037B-page 173

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REGISTER 22-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER

R/W-0

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

HLVDEN

HLSIDL

bit 15

bit 8

R/W-0

VDIR

R/W-0

IRVST

U-0

—

R/W-0

BGVST

HLVDL3

HLVDL2

HLVDL1

HLVDL0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

HLVDEN: High/Low-Voltage Detect Power Enable bit

1= HLVD is enabled

0= HLVD is disabled

bit 14

bit 13

Unimplemented: Read as ‘0’

HLSIDL: HLVD Stop in Idle Mode bit

1= Discontinue module operation when the device enters Idle mode

0= Continue module operation in Idle mode

bit 12-8

bit 7

Unimplemented: Read as ‘0’

VDIR: Voltage Change Direction Select bit

1= Event occurs when the voltage equals or exceeds the trip point (HLVDL<3:0>)

0= Event occurs when the voltage equals or falls below the trip point (HLVDL<3:0>)

bit 6

bit 5

BGVST: Band Gap Voltage Stable Flag bit

1= Indicates that the band gap voltage is stable

0= Indicates that the band gap voltage is unstable

IRVST: Internal Reference Voltage Stable Flag bit

1= Indicates that the internal reference voltage is stable and the High-Voltage Detect logic generates

the interrupt flag at the specified voltage range

0= Indicates that the internal reference voltage is unstable and the High-Voltage Detect logic will not

generate the interrupt flag at the specified voltage range, and the HLVD interrupt should not be

enabled

bit 4

Unimplemented: Read as ‘0’

bit 3-0

HLVDL<3:0>: High/Low-Voltage Detection Limit bits

1111= External analog input is used (input comes from the HLVDIN pin)

1110= Trip point 14⁽¹⁾

1101= Trip point 13⁽¹⁾

1100= Trip point 12⁽¹⁾

.

0000= Trip point 0⁽¹⁾

Note 1: For the actual trip point, see Section 26.0 “Electrical Characteristics”.

DS31037B-page 174

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PIC24F16KL402 FAMILY

23.1 Configuration Bits

23.0 SPECIAL FEATURES

The Configuration bits can be programmed (read as ‘0’),

or left unprogrammed (read as ‘1’), to select various

device configurations. These bits are mapped starting at

program memory location, F80000h. A complete list is

provided in Table 23-1. A detailed explanation of the

various bit functions is provided in Register 23-1 through

Register 23-7.

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive refer-

ence source. For more information on the

Watchdog Timer, High-Level Device Inte-

gration and Programming Diagnostics,

refer to the individual sections of the

“PIC24F Family Reference Manual”

provided below:

The address, F80000h, is beyond the user program

memory space. In fact, it belongs to the configuration

memory space (800000h-FFFFFFh), which can only be

accessed using table reads and table writes.

• Section 9. “Watchdog Timer (WDT)”

(DS39697)

• Section 36. “High-Level Integration

with Programmable High/Low-

Voltage Detect (HLVD)” (DS39725)

• Section 33. “Programming and

Diagnostics” (DS39716)

TABLE 23-1: CONFIGURATIONREGISTERS

LOCATIONS

Configuration

Address

Register

FBS

F80000

F80004

F80006

F80008

F8000A

F8000C

F8000E

PIC24F16KL402 family devices include several

features intended to maximize application flexibility and

reliability, and minimize cost through elimination of

external components. These are:

FGS

FOSCSEL

FOSC

FWDT

FPOR

FICD

• Flexible Configuration

• Watchdog Timer (WDT)

• Code Protection

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit Emulation

• Factory Programmed Unique ID

 2011 Microchip Technology Inc.

DS31037B-page 175

PIC24F16KL402 FAMILY

REGISTER 23-1: FBS: BOOT SEGMENT CONFIGURATION REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/C-1⁽¹⁾

BSS0

R/C-1⁽¹⁾

BWRP

BSS2

BSS1

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

C = Clearable Only bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-4

bit 3-1

Unimplemented: Read as ‘0’

BSS<2:0>: Boot Segment Program Flash Code Protection bits⁽¹⁾

111= No boot segment; all program memory space is General Segment

110= Standard security boot segment starts at 0200h, ends at 0AFEh

101= Standard security boot segment starts at 0200h, ends at 15FEh⁽²⁾

100= Reserved

011= Reserved

010= High-security boot segment starts at 0200h, ends at 0AFEh

001= High-security boot segment starts at 0200h, ends at 15FEh⁽²⁾

000= Reserved

bit 0

BWRP: Boot Segment Program Flash Write Protection bit⁽¹⁾

1= Boot segment may be written

0= Boot segment is write-protected

Note 1: Code protection bits can only be programmed by clearing them. They can be reset to their default factory

state (‘1’), but only by performing a bulk erase and reprogramming the entire device.

2: This selection is available only on PIC24F16KL40X devices.

REGISTER 23-2: FGS: GENERAL SEGMENT CONFIGURATION REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/C-1⁽¹⁾

GSS0

R/C-1⁽¹⁾

GWRP

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

C = Clearable Only bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-2

bit 1

Unimplemented: Read as ‘0’

GSS0: General Segment Code Flash Code Protection bit⁽¹⁾

1= No protection

0= Standard security is enabled

bit 0

GWRP: General Segment Code Flash Write Protection bit⁽¹⁾

1= General segment may be written

0= General segment is write-protected

Note 1: Code protection bits can only be programmed by clearing them. They can be reset to their default factory

state (‘1’), but only by performing a bulk erase and reprogramming the entire device.

DS31037B-page 176

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PIC24F16KL402 FAMILY

REGISTER 23-3: FOSCSEL: OSCILLATOR SELECTION CONFIGURATION REGISTER

R/P-1

IESO

R/P-1

U-0

—

U-0

—

R/P-0

R/P-1

LPRCSEL

SOSCSRC

FNOSC2

FNOSC1

FNOSC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

IESO: Internal External Switchover bit

1= Internal External Switchover mode is enabled (Two-Speed Start-up is enabled)

0= Internal External Switchover mode is disabled (Two-Speed Start-up is disabled)

LPRCSEL: Internal LPRC Oscillator Power Select bit

1= High-Power/High-Accuracy mode

0= Low-Power/Low-Accuracy mode

SOSCSRC: Secondary Oscillator Clock Source Configuration bit

1= SOSC analog crystal function is available on the SOSCI/SOSCO pins

0= SOSC crystal is disabled; digital SCLKI function is selected on the SOSCO pin

bit 4-3

bit 2-0

Unimplemented: Read as ‘0’

FNOSC<2:0>: Oscillator Selection bits

111= 8 MHz FRC Oscillator with divide-by-N (FRCDIV)

110= 500 kHz Low-Power FRC Oscillator with divide-by-N (LPFRCDIV)

101= Low-Power RC Oscillator (LPRC)

100= Secondary Oscillator (SOSC)

011= Primary Oscillator with PLL module (HS+PLL, EC+PLL)

010= Primary Oscillator (XT, HS, EC)

001= 8 MHz FRC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)

000= 8 MHz FRC Oscillator (FRC)

 2011 Microchip Technology Inc.

DS31037B-page 177

PIC24F16KL402 FAMILY

REGISTER 23-4: FOSC: OSCILLATOR CONFIGURATION REGISTER

R/P-0

R/P-1

R/P-0

R/P-1

POSCMD0

bit 0

FCKSM1

FCKSM0

SOSCSEL POSCFREQ1 POSCFREQ0 OSCIOFNC POSCMD1

bit 7

Legend:

R = Readable bit

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7-6

FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits

1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled

01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled

00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled

bit 5

SOSCSEL: Secondary Oscillator Power Selection Configuration bit

1= Secondary oscillator is configured for high-power operation

0= Secondary oscillator is configured for low-power operation

bit 4-3

POSCFREQ<1:0>: Primary Oscillator Frequency Range Configuration bits

11= Primary oscillator/external clock input frequency is greater than 8 MHz

10= Primary oscillator/external clock input frequency is between 100 kHz and 8 MHz

01= Primary oscillator/external clock input frequency is less than 100 kHz

00= Reserved; do not use

bit 2

OSCIOFNC: CLKO Enable Configuration bit

1= CLKO output signal is active on the OSCO pin; primary oscillator must be disabled or configured

for the External Clock mode (EC) for the CLKO to be active (POSCMD<1:0> = 11or 00)

0= CLKO output is disabled

bit 1-0

POSCMD<1:0>: Primary Oscillator Configuration bits

11= Primary Oscillator mode is disabled

10= HS Oscillator mode is selected

01= XT Oscillator mode is selected

00= External Clock mode is selected

DS31037B-page 178

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REGISTER 23-5: FWDT: WATCHDOG TIMER CONFIGURATION REGISTER

R/P-1

R/P-0

R/P-1

FWDTEN1

WINDIS

FWDTEN0

FWPSA

WDTPS3

WDTPS2

WDTPS1

WDTPS0

bit 7

bit 0

Legend:

R = Readable bit

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7,5

bit 6

FWDTEN<1:0>: Watchdog Timer Enable bit

11= WDT is enabled in hardware

10= WDT is controlled with the SWDTEN bit setting

01= WDT is enabled only while device is active; WDT is disabled in Sleep; SWDTEN bit is disabled

00= WDT is disabled in hardware; SWDTEN bit is disabled

WINDIS: Windowed Watchdog Timer Disable bit

1= Standard WDT is selected; windowed WDT is disabled

0= Windowed WDT is enabled; note that executing a CLRWDTinstruction while the WDT is disabled

in hardware and software (FWDTEN<1:0> = 00 and RCON bit, SWDTEN = 0) will not cause a

device Reset

bit 4

FWPSA: WDT Prescaler bit

1= WDT prescaler ratio of 1:128

0= WDT prescaler ratio of 1:32

bit 3-0

WDTPS<3:0>: Watchdog Timer Postscale Select bits

1111= 1:32,768

1110= 1:16,384

1101= 1:8,192

1100= 1:4,096

1011= 1:2,048

1010= 1:1,024

1001= 1:512

1000= 1:256

0111= 1:128

0110= 1:64

0101= 1:32

0100= 1:16

0011= 1:8

0010= 1:4

0001= 1:2

0000= 1:1

 2011 Microchip Technology Inc.

DS31037B-page 179

PIC24F16KL402 FAMILY

REGISTER 23-6: FPOR: RESET CONFIGURATION REGISTER

R/P-1

MCLRE⁽¹⁾

R/P-1

BORV1⁽²⁾

R/P-1

BORV0⁽²⁾

R/P-1

I2C1SEL⁽³⁾

R/P-1

U-0

—

R/P-1

PWRTEN

BOREN1

BOREN0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

MCLRE: MCLR Pin Enable bit⁽¹⁾

1= MCLR pin is enabled; RA5 input pin is disabled

0= RA5 input pin is enabled; MCLR is disabled

bit 6-5

BORV<1:0>: Brown-out Reset Enable bits⁽²⁾

11= Brown-out Reset is set to the low trip point

10= Brown-out Reset is set to the middle trip point

01= Brown-out Reset is set to the high trip point

00= Downside protection on POR is enabled (Low-Power BOR is selected)

bit 4

bit 3

I2C1SEL: Alternate MSSP1 I²C™ Pin Mapping bit⁽³⁾

1= Default location for SCL1/SDA1 pins (RB8 and RB9)

0= Alternate location for SCL1/SDA1 pins (ASCL1/RB6 and ASDA1/RB5)

PWRTEN: Power-up Timer Enable bit

1= PWRT is enabled

0= PWRT is disabled

bit 2

Unimplemented: Read as ‘0’

bit 1-0

BOREN<1:0>: Brown-out Reset Enable bits

11= BOR is enabled in hardware; SBOREN bit is disabled

10= BOR is enabled only while device is active and disabled in Sleep; SBOREN bit is disabled

01= BOR is controlled with the SBOREN bit setting

00= BOR is disabled in hardware; SBOREN bit is disabled

Note 1: The MCLRE fuse can only be changed when using the VPP-Based ICSP™ mode entry. This prevents a

user from accidentally locking out the device from the low-voltage test entry.

2: Refer to Table 26-5 for BOR trip point voltages.

3: Implemented in 28-pin devices only. This bit position must be programmed (= 1) in all other devices for I²C

functionality to be available.

DS31037B-page 180

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

REGISTER 23-7: FICD: IN-CIRCUIT DEBUGGER CONFIGURATION REGISTER

R/P-1

U-1

—

U-1

—

U-0

—

U-0

—

U-0

—

R/P-1

ICS1

R/P-1

ICS0

DEBUG

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

DEBUG: Background Debugger Enable bit

1= Background debugger is disabled

0= Background debugger functions are enabled

bit 6-5

bit 4-2

bit 1-0

Unimplemented: Read as ‘1’

Unimplemented: Read as ‘0’

ICS<1:0:> ICD Pin Select bits

11= PGEC1/PGED1 are used for programming and debugging the device⁽¹⁾

10= PGEC2/PGED2 are used for programming and debugging the device

01= PGEC3/PGED3 are used for programming and debugging the device

00= Reserved; do not use

Note 1: PGEC1/PGED1 are not available on PIC24F04KL100 (14-pin) devices.

To ensure a globally Unique ID across other Microchip

microcontroller families, the “Unique ID” value should

be further concatenated with the family and Device ID

values stored at address, FF0000h.

23.2 Unique ID

A read-only Unique ID value is stored at addresses,

800802h through 800808h. This factory programmed

value is unique to each microcontroller produced in the

PIC24F16KL402 family. To access this region, use

table read instructions or Program Space Visibility.

 2011 Microchip Technology Inc.

DS31037B-page 181

PIC24F16KL402 FAMILY

REGISTER 23-8: DEVID: DEVICE ID REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 23

bit 16

R

FAMID7

FAMID6

FAMID5

FAMID4

FAMID3

FAMID2

FAMID1

FAMID0

bit 15

bit 8

R

DEV7

DEV6

DEV5

DEV4

DEV3

DEV2

DEV1

DEV0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 23-16

bit 15-8

Unimplemented: Read as ‘0’

FAMID<7:0>: Device Family Identifier bits

01001011= PIC24F16KL402 family

DEV<7:0>: Individual Device Identifier bits

bit 7-0

00000001= PIC24F04KL100

00000010= PIC24F04KL101

00000101= PIC24F08KL200

00000110= PIC24F08KL201

00001010= PIC24F08KL301

00000000= PIC24F08KL302

00001110= PIC24F08KL401

00000100= PIC24F08KL402

00011110= PIC24F16KL401

00010100= PIC24F16KL402

DS31037B-page 182

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

REGISTER 23-9: DEVREV: DEVICE REVISION REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 23

bit 16

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

R

REV3

REV2

REV1

REV0

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 23-4

bit 3-0

Unimplemented: Read as ‘0’

REV<3:0>: Revision Identifier bits

 2011 Microchip Technology Inc.

DS31037B-page 183

PIC24F16KL402 FAMILY

The WDT Flag bit, WDTO (RCON<4>), is not

automatically cleared following a WDT time-out. To

detect subsequent WDT events, the flag must be

cleared in software.

23.3 Watchdog Timer (WDT)

For the PIC24F16KL402 family of devices, the WDT is

driven by the LPRC oscillator. When the WDT is

enabled, the clock source is also enabled.

Note:

The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

The nominal WDT clock source from LPRC is 31 kHz.

This feeds a prescaler that can be configured for either

5-bit (divide-by-32) or 7-bit (divide-by-128) operation.

The prescaler is set by the FWPSA Configuration bit.

With a 31 kHz input, the prescaler yields a nominal

WDT time-out period (TWDT) of 1 ms in 5-bit mode or

4 ms in 7-bit mode.

23.3.1

WINDOWED OPERATION

The Watchdog Timer has an optional Fixed Window

mode of operation. In this Windowed mode, CLRWDT

instructions can only reset the WDT during the last 1/4

of the programmed WDT period. A CLRWDTinstruction,

executed before that window, causes a WDT Reset

similar to a WDT time-out.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the Configuration bits,

WDTPS<3:0> (FWDT<3:0>), which allow the selection

of a total of 16 settings, from 1:1 to 1:32,768. Using the

prescaler and postscaler time-out periods, ranges from

1 ms to 131 seconds can be achieved.

Windowed WDT mode is enabled by programming the

Configuration bit, WINDIS (FWDT<6>), to ‘0’.

23.3.2

CONTROL REGISTER

The WDT, prescaler and postscaler are reset:

The WDT is enabled or disabled by the FWDTEN<1:0>

Configuration bits. When both the FWDTEN<1:0> Con-

figuration bits are set, the WDT is always enabled.

• On any device Reset

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSC bits) or by hardware

(i.e., Fail-Safe Clock Monitor)

• When a PWRSAVinstruction is executed

(i.e., Sleep or Idle mode is entered)

• When the device exits Sleep or Idle mode to

resume normal operation

• By a CLRWDTinstruction during normal execution

The WDT can be optionally controlled in software when

the FWDTEN<1:0> Configuration bits have been pro-

grammed to ‘10’. The WDT is enabled in software by

setting the SWDTEN control bit (RCON<5>). The

SWDTEN control bit is cleared on any device Reset.

The software WDT option allows the user to enable the

WDT for critical code segments, and disable the WDT

during non-critical segments, for maximum power sav-

ings. When the FWTEN<1:0> bits are set to ‘01’, the

WDT is enabled only in Run and Idle modes, and is dis-

abled in Sleep. Software control of the WDT SWDTEN

bit (RCON<5>) is disabled with this setting.

If the WDT is enabled in hardware (FWDTEN<1:0> = 11),

it will continue to run during Sleep or Idle modes. When

the WDT time-out occurs, the device will wake and code

execution will continue from where the PWRSAV

instruction was executed. The corresponding SLEEP or

IDLE bits (RCON<3:2>) will need to be cleared in

software after the device wakes up.

FIGURE 23-1:

WDT BLOCK DIAGRAM

SWDTEN

FWDTEN

LPRC Control

Wake from Sleep

FWPSA

WDTPS<3:0>

Prescaler

(5-Bit/7-Bit)

WDT

Counter

Postscaler

1:1 to 1:32.768

WDT Overflow

Reset

LPRC Input

31 kHz

1 ms/4 ms

All Device Resets

Transition to

New Clock Source

Exit Sleep or

Idle Mode

CLRWDTInstr.

PWRSAVInstr.

Sleep or Idle Mode

DS31037B-page 184

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

23.4 Program Verification and

Code Protection

23.5 In-Circuit Serial Programming

PIC24F16KL402 family microcontrollers can be serially

programmed while in the end application circuit. This is

simply done with two lines for clock (PGECx) and data

(PGEDx), and three other lines for power, ground and

the programming voltage. This allows customers to

manufacture boards with unprogrammed devices and

then program the microcontroller just before shipping

the product. This also allows the most recent firmware

or a custom firmware to be programmed.

For all devices in the PIC24F16KL402 family, code

protection for the boot segment is controlled by the

BSS<2:0> Configuration bits and the general segment

by the Configuration bit, GSS0. These bits inhibit exter-

nal reads and writes to the program memory space

This has no direct effect in normal execution mode.

Write protection is controlled by bit, BWRP, for the boot

segment and bit, GWRP, for the general segment in the

Configuration Word. When these bits are programmed

to ‘0’, internal write and erase operations to program

memory are blocked.

23.6 In-Circuit Debugger

When MPLAB^®ICD 3, MPLAB REAL ICE™ or

PICkit™ 3 is selected as a debugger, the in-circuit

debugging functionality is enabled. This function allows

simple debugging functions when used with

MPLAB IDE. Debugging functionality is controlled

through the PGECx and PGEDx pins.

To use the in-circuit debugger function of the device,

the design must implement ICSP connections to

MCLR, VDD, VSS, PGECx, PGEDx and the pin pair. In

addition, when the feature is enabled, some of the

resources are not available for general use. These

resources include the first 80 bytes of data RAM and

two I/O pins.

 2011 Microchip Technology Inc.

DS31037B-page 185

PIC24F16KL402 FAMILY

NOTES:

DS31037B-page 186

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

24.1 MPLAB Integrated Development

Environment Software

24.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers and dsPIC^®digital signal

controllers are supported with a full range of software

and hardware development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit

microcontroller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• A single graphical interface to all debugging tools

- Simulator

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Various Device

Families

- Programmer (sold separately)

- HI-TECH C^®for Various Device Families

- MPASM^TMAssembler

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- In-Circuit Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Customizable data windows with direct edit of

contents

• Simulators

• High-level source code debugging

• Mouse over variable inspection

- MPLAB SIM Software Simulator

• Emulators

• Drag and drop variables from source to watch

windows

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

• Extensive on-line help

• Integration of select third party tools, such as

IAR C Compilers

- MPLAB ICD 3

- PICkit™ 3 Debug Express

• Device Programmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)

• One-touch compile or assemble, and download to

emulator and simulator tools (automatically

updates all project information)

• Low-Cost Demonstration/Development Boards,

Evaluation Kits, and Starter Kits

• Debug using:

- Source files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

 2011 Microchip Technology Inc.

DS31037B-page 187

PIC24F16KL402 FAMILY

24.2 MPLAB C Compilers for Various

Device Families

24.5 MPLINK Object Linker/

MPLIB Object Librarian

The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the

dsPIC30 and dsPIC33 families of digital signal control-

lers. These compilers provide powerful integration

capabilities, superior code optimization and ease of

use.

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

24.3 HI-TECH C for Various Device

Families

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC

family of microcontrollers and the dsPIC family of digital

signal controllers. These compilers provide powerful

integration capabilities, omniscient code generation

and ease of use.

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

24.6 MPLAB Assembler, Linker and

Librarian for Various Device

Families

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The compilers include a macro assembler, linker, pre-

processor, and one-step driver, and can run on multiple

platforms.

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses

the assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

24.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• MPLAB IDE compatibility

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

source files

• Directives that allow complete control over the

assembly process

DS31037B-page 188

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

24.7 MPLAB SIM Software Simulator

24.9 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

MPLAB ICD 3 In-Circuit Debugger System is Micro-

chip's most cost effective high-speed hardware

debugger/programmer for Microchip Flash Digital Sig-

nal Controller (DSC) and microcontroller (MCU)

devices. It debugs and programs PIC^®Flash microcon-

trollers and dsPIC^®DSCs with the powerful, yet easy-

to-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-

nected to the design engineer's PC using a high-speed

USB 2.0 interface and is connected to the target with a

connector compatible with the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 supports all

MPLAB ICD 2 headers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

24.10 PICkit 3 In-Circuit Debugger/

Programmer and

24.8 MPLAB REAL ICE In-Circuit

Emulator System

PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-

ming of PIC^®and dsPIC^®Flash microcontrollers at a

most affordable price point using the powerful graphical

user interface of the MPLAB Integrated Development

Environment (IDE). The MPLAB PICkit 3 is connected

to the design engineer's PC using a full speed USB

interface and can be connected to the target via an

Microchip debug (RJ-11) connector (compatible with

MPLAB ICD 3 and MPLAB REAL ICE). The connector

uses two device I/O pins and the reset line to imple-

ment in-circuit debugging and In-Circuit Serial Pro-

gramming™.

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC^®Flash MCUs and dsPIC^®Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

The emulator is connected to the design engineer’s PC

using a high-speed USB 2.0 interface and is connected

to the target with either a connector compatible with in-

circuit debugger systems (RJ11) or with the new high-

speed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnection (CAT5).

The PICkit 3 Debug Express include the PICkit 3, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

The emulator is field upgradable through future firmware

downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new

features will be added. MPLAB REAL ICE offers

significant advantages over competitive emulators

including low-cost, full-speed emulation, run-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

 2011 Microchip Technology Inc.

DS31037B-page 189

PIC24F16KL402 FAMILY

24.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

24.13 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

The PICkit™ 2 Development Programmer/Debugger is

a low-cost development tool with an easy to use inter-

face for programming and debugging Microchip’s Flash

families of microcontrollers. The full featured

Windows^®programming interface supports baseline

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

(PIC10F,

PIC12F5xx,

PIC16F5xx),

midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,

dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit

microcontrollers, and many Microchip Serial EEPROM

products. With Microchip’s powerful MPLAB Integrated

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

Development Environment (IDE) the PICkit™

2

enables in-circuit debugging on most PIC^®microcon-

trollers. In-Circuit-Debugging runs, halts and single

steps the program while the PIC microcontroller is

embedded in the application. When halted at a break-

point, the file registers can be examined and modified.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

The PICkit 2 Debug Express include the PICkit 2, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

24.12 MPLAB PM3 Device Programmer

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an MMC card for file

storage and data applications.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

DS31037B-page 190

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

The literal instructions that involve data movement may

use some of the following operands:

25.0 INSTRUCTION SET SUMMARY

Note:

This chapter is a brief summary of the

PIC24F Instruction Set Architecture (ISA)

and is not intended to be a comprehensive

reference source.

• A literal value to be loaded into a W register or file

register (specified by the value of ‘k’)

• The W register or file register where the literal

value is to be loaded (specified by ‘Wb’ or ‘f’)

The PIC24F instruction set adds many enhancements

to the previous PIC^®MCU instruction sets, while

maintaining an easy migration from previous PIC MCU

instruction sets. Most instructions are a single program

memory word. Only three instructions require two

program memory locations.

However, literal instructions that involve arithmetic or

logical operations use some of the following operands:

• The first source operand, which is a register ‘Wb’

without any address modifier

• The second source operand, which is a literal

value

Each single-word instruction is a 24-bit word divided

into an 8-bit opcode, which specifies the instruction

type and one or more operands, which further specify

the operation of the instruction. The instruction set is

highly orthogonal and is grouped into four basic

categories:

• The destination of the result (only if not the same

as the first source operand), which is typically a

register ‘Wd’ with or without an address modifier

The control instructions may use some of the following

operands:

• A program memory address

• Word or byte-oriented operations

• Bit-oriented operations

• Literal operations

• The mode of the table read and table write

instructions

All instructions are a single word, except for certain

double-word instructions, which were made

double-word instructions so that all of the required

information is available in these 48 bits. In the second

word, the 8 MSbs are ‘0’s. If this second word is

executed as an instruction (by itself), it will execute as

a NOP.

• Control operations

Table 25-1 lists the general symbols used in describing

the instructions. The PIC24F instruction set summary

in Table 25-2 lists all the instructions, along with the

status flags affected by each instruction.

Most word or byte-oriented W register instructions

(including barrel shift instructions) have three

operands:

Most single-word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

Program Counter (PC) is changed as a result of the

instruction. In these cases, the execution takes two

instruction cycles, with the additional instruction

cycle(s) executed as a NOP. Notable exceptions are the

BRA (unconditional/computed branch), indirect

CALL/GOTO, all table reads and writes, and

RETURN/RETFIE instructions, which are single-word

instructions but take two or three cycles.

• The first source operand, which is typically a

register ‘Wb’ without any address modifier

• The second source operand, which is typically a

register ‘Ws’ with or without an address modifier

• The destination of the result, which is typically a

register ‘Wd’ with or without an address modifier

However, word or byte-oriented file register instructions

have two operands:

Certain instructions that involve skipping over the

subsequent instruction require either two or three

cycles if the skip is performed, depending on whether

the instruction being skipped is a single-word or

two-word instruction. Moreover, double-word moves

require two cycles. The double-word instructions

execute in two instruction cycles.

• The file register specified by the value, ‘f’

• The destination, which could either be the file

register, ‘f’, or the W0 register, which is denoted

as ‘WREG’

Most bit-oriented instructions (including simple

rotate/shift instructions) have two operands:

• The W register (with or without an address

modifier) or file register (specified by the value of

‘Ws’ or ‘f’)

• The bit in the W register or file register (specified

by a literal value or indirectly by the contents of

register ‘Wb’)

 2011 Microchip Technology Inc.

DS31037B-page 191

PIC24F16KL402 FAMILY

TABLE 25-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field

Description

#text

(text)

[text]

{ }

Means literal defined by “text”

Means “content of text”

Means “the location addressed by text”

Optional field or operation

<n:m>

.b

Register bit field

Byte mode selection

.d

Double-Word mode selection

.S

Shadow register select

.w

Word mode selection (default)

bit4

4-bit bit selection field (used in word addressed instructions) {0...15}

MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero

Absolute address, label or expression (resolved by the linker)

File register address {0000h...1FFFh}

1-bit unsigned literal {0,1}

C, DC, N, OV, Z

Expr

f

lit1

lit4

4-bit unsigned literal {0...15}

lit5

5-bit unsigned literal {0...31}

lit8

8-bit unsigned literal {0...255}

lit10

lit14

lit16

lit23

None

PC

10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode

14-bit unsigned literal {0...16384}

16-bit unsigned literal {0...65535}

23-bit unsigned literal {0...8388608}; LSB must be ‘0’

Field does not require an entry, may be blank

Program Counter

Slit10

Slit16

Slit6

Wb

10-bit signed literal {-512...511}

16-bit signed literal {-32768...32767}

6-bit signed literal {-16...16}

Base W register {W0..W15}

Wd

Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }

Wdo

Destination W register 

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }

Wm,Wn

Wn

Dividend, Divisor working register pair (direct addressing)

One of 16 working registers {W0..W15}

Wnd

Wns

One of 16 destination working registers {W0..W15}

One of 16 source working registers {W0..W15}

WREG

Ws

W0 (working register used in File register instructions)

Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }

Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

Wso

DS31037B-page 192

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

TABLE 25-2: INSTRUCTION SET OVERVIEW

Assembly

# of

Status Flags

Affected

Assembly Syntax

Mnemonic

Description

Words Cycles

ADD

ADDC

AND

ASR

ADD

ADDC

AND

ASR

BCLR

BRA

BSET

BSW.C

BSW.Z

BTG

BTSC

f

f = f + WREG

1

C, DC, N, OV, Z

N, Z

f,WREG

WREG = f + WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

Wd = lit10 + Wd

1

Wd = Wb + Ws

1

Wd = Wb + lit5

1

f = f + WREG + (C)

1

f,WREG

WREG = f + WREG + (C)

Wd = lit10 + Wd + (C)

Wd = Wb + Ws + (C)

Wd = Wb + lit5 + (C)

f = f .AND. WREG

1

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

1

f,WREG

WREG = f .AND. WREG

Wd = lit10 .AND. Wd

Wd = Wb .AND. Ws

1

N, Z

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

1

N, Z

1

N, Z

Wd = Wb .AND. lit5

1

N, Z

f = Arithmetic Right Shift f

WREG = Arithmetic Right Shift f

Wd = Arithmetic Right Shift Ws

Wnd = Arithmetic Right Shift Wb by Wns

Wnd = Arithmetic Right Shift Wb by lit5

Bit Clear f

1

C, N, OV, Z

N, Z

f,WREG

1

Ws,Wd

1

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,#bit4

Ws,#bit4

C,Expr

1

N, Z

BCLR

BRA

1

None

Bit Clear Ws

1

None

Branch if Carry

1 (2)

2

None

GE,Expr

GEU,Expr

GT,Expr

GTU,Expr

LE,Expr

LEU,Expr

LT,Expr

LTU,Expr

N,Expr

Branch if Greater than or Equal

Branch if Unsigned Greater than or Equal

Branch if Greater than

Branch if Unsigned Greater than

Branch if Less than or Equal

Branch if Unsigned Less than or Equal

Branch if Less than

None

Branch if Unsigned Less than

Branch if Negative

None

NC,Expr

NN,Expr

NOV,Expr

NZ,Expr

OV,Expr

Expr

Branch if Not Carry

None

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

None

Branch if Overflow

None

Branch Unconditionally

Branch if Zero

None

Z,Expr

1 (2)

2

None

Wn

Computed Branch

None

BSET

BSW

f,#bit4

Ws,#bit4

Ws,Wb

Bit Set f

1

None

Bit Set Ws

1

None

Write C bit to Ws<Wb>

Write Z bit to Ws<Wb>

Bit Toggle f

1

None

Ws,Wb

1

None

BTG

f,#bit4

Ws,#bit4

f,#bit4

1

None

Bit Toggle Ws

1

None

BTSC

Bit Test f, Skip if Clear

1

None

(2 or 3)

BTSC

Ws,#bit4

Bit Test Ws, Skip if Clear

1

None

(2 or 3)

 2011 Microchip Technology Inc.

DS31037B-page 193

PIC24F16KL402 FAMILY

TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

f,#bit4

Description

Bit Test f, Skip if Set

Words Cycles

BTSS

1

None

(2 or 3)

Ws,#bit4

Bit Test Ws, Skip if Set

1

None

(2 or 3)

BTST

f,#bit4

Ws,#bit4

Ws,Wb

Bit Test f

1

2

1

2

1

Z

BTST.C

BTST.Z

BTST.C

BTST.Z

BTSTS

Bit Test Ws to C

C

Bit Test Ws to Z

Z

Bit Test Ws<Wb> to C

Bit Test Ws<Wb> to Z

Bit Test then Set f

Bit Test Ws to C, then Set

Bit Test Ws to Z, then Set

Call Subroutine

C

Ws,Wb

Z

BTSTS

f,#bit4

Z

BTSTS.C Ws,#bit4

BTSTS.Z Ws,#bit4

C

Z

CALL

CLR

CALL

CLR

lit23

Wn

None

Call Indirect Subroutine

f = 0x0000

None

f

None

CLR

WREG

Ws

WREG = 0x0000

Ws = 0x0000

None

CLR

None

CLRWDT

COM

CLRWDT

Clear Watchdog Timer

WDTO, Sleep

COM

CP

f

f = f

1

N, Z

f,WREG

Ws,Wd

f

WREG = f

N, Z

Wd = Ws

N, Z

CP

Compare f with WREG

Compare Wb with lit5

Compare Wb with Ws (Wb – Ws)

Compare f with 0x0000

Compare Ws with 0x0000

Compare f with WREG, with Borrow

Compare Wb with lit5, with Borrow

C, DC, N, OV, Z

CP

Wb,#lit5

Wb,Ws

f

CP

CP0

CPB

CP0

CPB

Ws

f

Wb,#lit5

Wb,Ws

Compare Wb with Ws, with Borrow

(Wb – Ws – C)

CPSEQ

CPSGT

CPSLT

CPSNE

CPSEQ

CPSGT

CPSLT

CPSNE

Wb,Wn

Compare Wb with Wn, Skip if =

Compare Wb with Wn, Skip if >

Compare Wb with Wn, Skip if <

Compare Wb with Wn, Skip if 

1

None

(2 or 3)

1

(2 or 3)

1

(2 or 3)

1

(2 or 3)

DAW

DEC

DAW.B

DEC

Wn

Wn = Decimal Adjust Wn

f = f –1

1

C

f

C, DC, N, OV, Z

None

DEC

f,WREG

Ws,Wd

f

WREG = f –1

1

DEC

Wd = Ws – 1

1

DEC2

DISI

DIV.SW

DIV.SD

DIV.UW

DIV.UD

EXCH

FF1L

FF1R

f = f – 2

1

f,WREG

Ws,Wd

#lit14

Wm,Wn

Wns,Wnd

Ws,Wnd

WREG = f – 2

1

Wd = Ws – 2

1

DISI

DIV

Disable Interrupts for k Instruction Cycles

Signed 16/16-bit Integer Divide

Signed 32/16-bit Integer Divide

Unsigned 16/16-bit Integer Divide

Unsigned 32/16-bit Integer Divide

Swap Wns with Wnd

1

18

1

N, Z, C, OV

None

EXCH

FF1L

FF1R

Find First One from Left (MSb) Side

Find First One from Right (LSb) Side

1

C

1

C

DS31037B-page 194

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

GOTO

INC

Expr

Go to Address

Go to Indirect

f = f + 1

2

1

2

1

2

1

None

Wn

None

INC

f

C, DC, N, OV, Z

N, Z

INC

f,WREG

WREG = f + 1

Wd = Ws + 1

f = f + 2

INC

Ws,Wd

INC2

IOR

INC2

IOR

f

f,WREG

WREG = f + 2

Wd = Ws + 2

f = f .IOR. WREG

Ws,Wd

f

IOR

f,WREG

WREG = f .IOR. WREG

N, Z

IOR

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

#lit14

Wd = lit10 .IOR. Wd

N, Z

IOR

Wd = Wb .IOR. Ws

N, Z

IOR

Wd = Wb .IOR. lit5

N, Z

LNK

LSR

LNK

Link Frame Pointer

None

LSR

f

f = Logical Right Shift f

C, N, OV, Z

N, Z

LSR

f,WREG

WREG = Logical Right Shift f

Wd = Logical Right Shift Ws

Wnd = Logical Right Shift Wb by Wns

Wnd = Logical Right Shift Wb by lit5

Move f to Wn

LSR

Ws,Wd

LSR

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,Wn

LSR

N, Z

MOV

None

MOV

[Wns+Slit10],Wnd

f

Move [Wns+Slit10] to Wnd

Move f to f

None

MOV

N, Z

MOV

f,WREG

Move f to WREG

None

MOV

#lit16,Wn

#lit8,Wn

Wn,f

Move 16-bit Literal to Wn

Move 8-bit Literal to Wn

None

MOV.b

MOV

None

Move Wn to f

None

MOV

Wns,[Wns+Slit10]

Wso,Wdo

WREG,f

Move Wns to [Wns+Slit10]

Move Ws to Wd

None

MOV

None

MOV

Move WREG to f

None

MOV.D

MUL.SS

MUL.SU

MUL.US

MUL.UU

MUL.SU

MUL.UU

MUL

Wns,Wd

Move Double from W(ns):W(ns+1) to Wd

Move Double from Ws to W(nd+1):W(nd)

{Wnd+1, Wnd} = Signed(Wb) * Signed(Ws)

{Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws)

{Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws)

{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws)

{Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5)

{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5)

W3:W2 = f * WREG

None

Ws,Wnd

None

MUL

Wb,Ws,Wnd

Wb,#lit5,Wnd

f

None

NEG

f

f = f + 1

C, DC, N, OV, Z

NEG

f,WREG

WREG = f + 1

NEG

Ws,Wd

Wd = Ws + 1

1

2

C, DC, N, OV, Z

None

NOP

POP

NOP

No Operation

NOPR

POP

No Operation

None

f

Pop f from Top-of-Stack (TOS)

Pop from Top-of-Stack (TOS) to Wdo

None

POP

Wdo

Wnd

None

POP.D

Pop from Top-of-Stack (TOS) to

W(nd):W(nd+1)

None

POP.S

PUSH

Pop Shadow Registers

1

2

1

All

PUSH

f

Push f to Top-of-Stack (TOS)

Push Wso to Top-of-Stack (TOS)

Push W(ns):W(ns+1) to Top-of-Stack (TOS)

Push Shadow Registers

None

PUSH

Wso

Wns

PUSH.D

PUSH.S

 2011 Microchip Technology Inc.

DS31037B-page 195

PIC24F16KL402 FAMILY

TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

PWRSAV

RCALL

PWRSAV

RCALL

REPEAT

RESET

RETFIE

RETLW

RETURN

RLC

#lit1

Expr

Wn

Go into Sleep or Idle mode

Relative Call

1

2

WDTO, Sleep

None

Computed Call

2

None

REPEAT

#lit14

Wn

Repeat Next Instruction lit14 + 1 times

Repeat Next Instruction (Wn) + 1 times

Software Device Reset

Return from Interrupt

1

None

1

None

RESET

RETFIE

RETLW

RETURN

RLC

1

None

3 (2)

1

None

#lit10,Wn

Return with Literal in Wn

Return from Subroutine

f = Rotate Left through Carry f

WREG = Rotate Left through Carry f

Wd = Rotate Left through Carry Ws

f = Rotate Left (No Carry) f

WREG = Rotate Left (No Carry) f

Wd = Rotate Left (No Carry) Ws

f = Rotate Right through Carry f

WREG = Rotate Right through Carry f

Wd = Rotate Right through Carry Ws

f = Rotate Right (No Carry) f

WREG = Rotate Right (No Carry) f

Wd = Rotate Right (No Carry) Ws

Wnd = Sign-Extended Ws

f = FFFFh

None

f

C, N, Z

RLC

f,WREG

Ws,Wd

f

1

C, N, Z

RLC

1

C, N, Z

RLNC

RRC

RLNC

RRC

1

N, Z

f,WREG

Ws,Wd

f

1

N, Z

1

N, Z

1

C, N, Z

RRC

f,WREG

Ws,Wd

f

1

C, N, Z

RRC

1

C, N, Z

RRNC

SE

1

N, Z

f,WREG

Ws,Wd

Ws,Wnd

f

1

N, Z

1

N, Z

SE

1

C, N, Z

SETM

SL

1

None

WREG

WREG = FFFFh

1

None

Ws

Ws = FFFFh

1

None

SL

f

f = Left Shift f

1

C, N, OV, Z

N, Z

SL

f,WREG

Ws,Wd

Wb,Wns,Wnd

Wb,#lit5,Wnd

f

WREG = Left Shift f

1

SL

Wd = Left Shift Ws

1

SL

Wnd = Left Shift Wb by Wns

Wnd = Left Shift Wb by lit5

f = f – WREG

1

SL

1

N, Z

SUB

1

C, DC, N, OV, Z

SUB

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f – WREG

1

SUB

Wn = Wn – lit10

1

SUB

Wd = Wb – Ws

1

SUB

Wd = Wb – lit5

1

SUBB

f = f – WREG – (C)

1

SUBB

f,WREG

WREG = f – WREG – (C)

Wn = Wn – lit10 – (C)

Wd = Wb – Ws – (C)

1

C, DC, N, OV, Z

#lit10,Wn

Wb,Ws,Wd

SUBB

SUBR

Wb,#lit5,Wd

f

Wd = Wb – lit5 – (C)

f = WREG – f

1

C, DC, N, OV, Z

SUBR

f,WREG

WREG = WREG – f

Wd = Ws – Wb

Wb,Ws,Wd

Wb,#lit5,Wd

Wd = lit5 – Wb

SUBBR

f

f = WREG – f – (C)

1

C, DC, N, OV, Z

SUBBR

SWAP.b

SWAP

f,WREG

Wb,Ws,Wd

Wb,#lit5,Wd

Wn

WREG = WREG – f – (C)

Wd = Ws – Wb – (C)

1

2

C, DC, N, OV, Z

None

Wd = lit5 – Wb – (C)

SWAP

Wn = Nibble Swap Wn

Wn = Byte Swap Wn

Wn

None

TBLRDH

Ws,Wd

Read Prog<23:16> to Wd<7:0>

None

DS31037B-page 196

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

TABLE 25-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

TBLRDL

TBLWTH

TBLWTL

ULNK

TBLRDL

TBLWTH

TBLWTL

ULNK

XOR

Ws,Wd

Read Prog<15:0> to Wd

1

2

1

None

Write Ws<7:0> to Prog<23:16>

Write Ws to Prog<15:0>

Unlink Frame Pointer

f = f .XOR. WREG

None

N, Z

XOR

f

XOR

f,WREG

WREG = f .XOR. WREG

Wd = lit10 .XOR. Wd

Wd = Wb .XOR. Ws

N, Z

XOR

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

Ws,Wnd

N, Z

XOR

N, Z

XOR

Wd = Wb .XOR. lit5

N, Z

ZE

Wnd = Zero-Extend Ws

C, Z, N

 2011 Microchip Technology Inc.

DS31037B-page 197

PIC24F16KL402 FAMILY

NOTES:

DS31037B-page 198

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

26.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of the PIC24F16KL402 family electrical characteristics. Additional information will be

provided in future revisions of this document as it becomes available.

Absolute maximum ratings for the PIC24F16KL402 family are listed below. Exposure to these maximum rating

conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other

conditions above the parameters indicated in the operation listings of this specification, is not implied.

(†)

Absolute Maximum Ratings

Ambient temperature under bias.............................................................................................................-40°C to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.5V

Voltage on any combined analog and digital pin, with respect to VSS ........................................... -0.3V to (VDD + 0.3V)

Voltage on any digital only pin with respect to VSS ....................................................................... -0.3V to (VDD + 0.3V)

Voltage on MCLR/VPP pin with respect to VSS ......................................................................................... -0.3V to +9.0V

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin⁽¹⁾...........................................................................................................................250 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by all ports .......................................................................................................................200 mA

Maximum current sourced by all ports⁽¹⁾...............................................................................................................200 mA

Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 26-1).

†Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions

above those indicated in the operation listings of this specification is not implied. Exposure to maximum

rating conditions for extended periods may affect device reliability.

 2011 Microchip Technology Inc.

DS31037B-page 199

PIC24F16KL402 FAMILY

26.1 DC Characteristics

FIGURE 26-1:

PIC24F16KL402 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)

3.60V

3.00V

3.60V

3.00V

1.80V

8 MHz

32 MHz

Frequency

Note:

For frequencies between 8 MHz and 32 MHz, FMAX = 20 MHz * (VDD – 1.8) + 8 MHz.

TABLE 26-1: THERMAL OPERATING CONDITIONS

Rating

Symbol

Min

Typ

Max

Unit

Operating Junction Temperature Range

Operating Ambient Temperature Range

TJ

TA

-40

—

+125

+85

°C

Power Dissipation:

Internal Chip Power Dissipation:

PINT = VDD x (IDD –  IOH)

PD

PINT + PI/O

W

I/O Pin Power Dissipation:

PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL)

Maximum Allowed Power Dissipation

PDMAX

(TJ – TA)/JA

TABLE 26-2: THERMAL PACKAGING CHARACTERISTICS

Characteristic

Symbol

Typ

Max

Unit

Notes

Package Thermal Resistance, 20-Pin SPDIP

Package Thermal Resistance, 28-Pin SPDIP

Package Thermal Resistance, 20-Pin SSOP

Package Thermal Resistance, 28-Pin SSOP

Package Thermal Resistance, 20-Pin SOIC

Package Thermal Resistance, 28-Pin SOIC

Package Thermal Resistance, 20-Pin QFN

Package Thermal Resistance, 28-Pin QFN

Package Thermal Resistance, 14-Pin SPDIP

Package Thermal Resistance, 14-Pin TSSOP

^JA

JA

^JA

JA

^JA

62.4

60

—

°C/W

1

108

71

75

80.2

43

32

62.4

108

Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.

DS31037B-page 200

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

TABLE 26-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions: 1.8V to 3.6V

DC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

Para

m No.

Symbol

Characteristic

Supply Voltage

Min

Typ⁽¹⁾Max Units

Conditions

DC10 VDD

DC12 VDR

1.8

1.5

—

3.6

—

V

RAM Data Retention

Voltage⁽²⁾

DC16 VPOR

DC17 SVDD

VBG

VDD Start Voltage

to Ensure Internal

Power-on Reset Signal

VSS

0.05

1.14

—

0.7

—

V

VDD Rise Rate

to Ensure Internal

Power-on Reset Signal

V/ms 0-3.3V in 0.1s

0-2.5V in 60 ms

Band Gap Voltage

Reference

1.2

1.26

V

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: This is the limit to which VDD can be lowered without losing RAM data.

 2011 Microchip Technology Inc.

DS31037B-page 201

PIC24F16KL402 FAMILY

TABLE 26-4: HIGH/LOW–VOLTAGE DETECT CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

Param

No.

Symbol

Characteristic

Min

Typ

Max Units

Conditions

DC18 VHLVD

HLVD Voltage on VDD HLVDL<3:0> = 0000

—

1.85

1.90

1.95

2.00

2.05

2.17

2.23

2.36

2.43

2.60

2.78

2.88

3.00

3.12

3.39

1.94

2.00

2.05

2.10

2.15

2.28

2.34

2.48

2.55

2.73

2.92

3.02

3.15

3.28

3.56

V

Transition

HLVDL<3:0> = 0001 1.81

HLVDL<3:0> = 0010 1.85

HLVDL<3:0> = 0011 1.90

HLVDL<3:0> = 0100 1.95

HLVDL<3:0> = 0101 2.06

HLVDL<3:0> = 0110 2.12

HLVDL<3:0> = 0111 2.24

HLVDL<3:0> = 1000 2.31

HLVDL<3:0> = 1001 2.47

HLVDL<3:0> = 1010 2.64

HLVDL<3:0> = 1011 2.74

HLVDL<3:0> = 1100 2.85

HLVDL<3:0> = 1101 2.96

HLVDL<3:0> = 1110 3.22

TABLE 26-5: BOR TRIP POINTS

Standard Operating Conditions: 1.8V to 3.6V

Operating temperature

-40°C  TA  +85°C for Industrial

Param

Symbol

No.

Characteristic

Min

Typ Max Units

Conditions

Note 1

DC19

BOR Voltage on VDD

Transition

BORV = 00

BORV = 01

BORV = 10

BORV = 11

1.85

2.90

2.53

2.0

3.0

2.7

2.15

3.38

3.07

V

1.75 1.85 2.05

Note 1: LPBOR re-arms the POR circuit but does not cause a BOR.

DS31037B-page 202

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

TABLE 26-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)*

Standard Operating Conditions: 1.8V to 3.6V

Operating temperature -40°C  TA  +85°C for Industrial

DC CHARACTERISTICS

Parameter No.

Typical⁽¹⁾

Max

Units

Conditions

IDD Current

DC20

0.154

0.301

0.300

0.585

0.350

0.630

—

mA

1.8V

3.3V

1.8V

3.3V

0.5 MIPS,

FOSC = 1 MHz

DC22

1 MIPS,

FOSC = 2 MHz

—

DC24

DC26

16 MIPS,

FOSC = 32 MHz

7.76

12.0

mA

3.3V

1.44

2.71

4.00

9.00

—

mA

µA

1.8V

3.3V

1.8V

3.3V

FRC (4 MIPS),

FOSC = 8 MHz

DC30

28.0

55.0

LPRC (15.5 KIPS),

FOSC = 31 kHz

µA

Note 1: Data in the Typical column is at 3.3V, 25°C, unless otherwise stated.

*

IDD is measured with all peripherals disabled. All I/Os are configured as outputs and set low; PMDx bits

are set to ‘1’ and WDT, etc., are all disabled.

TABLE 26-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)*

Standard Operating Conditions: 1.8V to 3.6V

Operating temperature -40°C  TA  +85°C for Industrial

DC CHARACTERISTICS

Parameter No.

Typical⁽¹⁾

Max

Units

Conditions

Idle Current (IIDLE)

DC40

0.035

0.077

0.076

0.146

0.080

0.150

—

1.8V

3.3V

1.8V

3.3V

0.5 MIPS,

FOSC = 1 MHz

mA

DC42

1 MIPS,

FOSC = 2 MHz

mA

—

DC44

DC46

16 MIPS,

FOSC = 32 MHz

2.52

3.20

3.3V

0.45

0.76

0.87

1.55

—

mA

µA

1.8V

3.3V

1.8V

3.3V

FRC (4 MIPS),

FOSC = 8 MHz

DC50

18.0

40.0

LPRC (15.5 KIPS),

FOSC = 31 kHz

µA

Note 1: Data in the Typical column is at 3.3V, 25°C, unless otherwise stated.

*

IIDLE is measured with all I/Os configured as outputs and set low; PMDx bits are set to ‘1’ and WDT, etc.,

are all disabled.

 2011 Microchip Technology Inc.

DS31037B-page 203

PIC24F16KL402 FAMILY

TABLE 26-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

Standard Operating Conditions: 1.8V to 3.6V

DC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

Parameter No.

Power-Down Current (IPD)

DC60 0.01

Typical⁽¹⁾

Max

Units

Conditions

0.20

0.87

1.35

0.54

1.68

2.45

µA

-40°C

+25°C

+60°C

+85°C

-40°C

+25°C

+60°C

+85°C

0.03

0.06

0.20

0.01

0.03

0.08

0.25

1.8V

3.3V

( )

Sleep Mode ²

Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.

2: Base IPD is measured with all peripherals and clocks disabled. All I/Os are configured as outputs and set

low; PMDx bits are set to ‘1’ and WDT, etc., are all disabled

TABLE 26-9: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

Standard Operating Conditions: 1.8V to 3.6V

DC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

Parameter No.

Typical⁽¹⁾

Max

Units

Conditions

Module Differential Current (IPD)

DC71

DC72

DC75

0.21

0.45

0.69

1.00

5.24

5.16

4.15

0.03

0.65

0.95

1.50

—

µA

1.8V

3.3V

1.8V

3.3V

1.8V

3.3V

1.8V

3.3V

Watchdog Timer Current

WDT^(2,3)

32 kHz Crystal with Timer1:

(2)

SOSC (SOSCSEL = 0)

HLVD^(2,3)

BOR^(2,3)

LPBOR⁽²⁾

11.00

9.00

0.20

DC76

DC78

Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.

2: The  current is the additional current consumed when the module is enabled. This current should be

added to the base IPD current.

3: This current applies to Sleep only.

DS31037B-page 204

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

TABLE 26-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Standard Operating Conditions: 1.8V to 3.6V

Operating temperature -40°C  TA  +85°C for Industrial

DC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

VIL

Input Low Voltage⁽⁴⁾

I/O Pins

—

V

DI10

VSS

—

0.2 VDD

0.3 VDD

0.8

MCLR

V

DI15

DI16

DI17

DI18

DI19

OSCI (XT mode)

OSCI (HS mode)

I/O Pins with I²C™ Buffer

I/O Pins with SMBus Buffer

Input High Voltage^(4,5)

V

SMBus disabled

V

SMBus enabled

VIH

—

DI20

I/O Pins:

with Analog Functions

Digital Only

0.8 VDD

—

VDD

V

DI25

DI26

DI27

DI28

MCLR

0.8 VDD

0.7 VDD

—

VDD

V

OSCI (XT mode)

OSCI (HS mode)

I/O Pins with I²C Buffer:

with Analog Functions

Digital Only

0.7 VDD

—

VDD

V

DI29

DI30

DI31

I/O Pins with SMBus

2.1

50

—

250

—

VDD

500

30

V

2.5V  VPIN  VDD

VDD = 3.3V, VPIN = VSS

VDD = 2.0V

ICNPU CNx Pull-up Current

A

IPU

Maximum Load Current

for Digital High Detection

w/Internal Pull-up

—

1000

VDD = 3.3V

IIL

Input Leakage

Current^(2,3)

DI50

DI51

I/O Ports

—

0.050

0.300

±0.100

±0.500

A

VSS  VPIN  VDD,

Pin at high-impedance

VREF+, VREF-, AN0, AN1

VSS  VPIN  VDD,

Pin at high-impedance

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: Refer to Table 1-4 and Table 1-5 for I/O pin buffer types.

5: VIH requirements are met when the internal pull-ups are enabled.

 2011 Microchip Technology Inc.

DS31037B-page 205

PIC24F16KL402 FAMILY

TABLE 26-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

Standard Operating Conditions: 1.8V to 3.6V

DC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

—

VOL

Output Low Voltage

DO10

DO16

All I/O Pins

0.4

V

IOL = 4.0 mA

IOL = 3.5 mA

IOL = 1.2 mA

IOL = 0.4 mA

VDD = 3.6V

VDD = 2.0V

VDD = 3.6V

VDD = 2.0V

OSC2/CLKO

VOH

Output High Voltage

DO20

DO26

All I/O Pins

3

—

V

IOH = -3.0 mA

IOH = -1.0 mA

IOH = -0.5 mA

VDD = 3.6V

VDD = 2.0V

VDD = 3.6V

VDD = 2.0V

1.6

3

OSC2/CLKO

1.6

Note 1: Data in “Typ” column is at 25°C unless otherwise stated.

TABLE 26-12: DC CHARACTERISTICS: PROGRAM MEMORY

Standard Operating Conditions: 1.8V to 3.6V

Operating temperature -40°C  TA  +85°C for Industrial

DC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

Program Flash Memory

Cell Endurance

D130

D131

EP

VPR

10,000⁽²⁾

VMIN

—

2

—

3.6

—

E/W

V

VDD for Read

VMIN = Minimum operating voltage

D133A TIW

Self-Timed Write Cycle

Time

ms

D134

D135

TRETD Characteristic Retention

40

—

Year Provided no other specifications

are violated

IDDP

Supply Current During

Programming

10

mA

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: Self-write and block erase.

DS31037B-page 206

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

TABLE 26-13: DC CHARACTERISTICS: DATA EEPROM MEMORY

Standard Operating Conditions: 1.8V to 3.6V

Operating temperature -40°C  TA  +85°C for Industrial

DC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

Data EEPROM Memory

Cell Endurance

D140

D141

EPD

VPRD

100,000

VMIN

—

E/W

V

VDD for Read

3.6

VMIN = Minimum operating

voltage

D143A TIWD

D143B TREF

Self-Timed Write Cycle

Time

—

4

—

ms

Number of Total

Write/Erase Cycles Before

Refresh

10M

E/W

D144

D145

TRETDD Characteristic Retention

40

—

7

—

Year Provided no other specifications

are violated

IDDPD

Supply Current during

Programming

mA

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

TABLE 26-14: DC SPECIFICATIONS: COMPARATOR

Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)

Param

No.

Symbol

Characteristic

Min

Typ

Max

Units

Comments

D300

D301

D302

VIOFF

VICM

Input Offset Voltage

—

0

20

—

40

VDD

—

mV

V

Input Common Mode Voltage

CMRR

Common Mode Rejection

Ratio

55

dB

TABLE 26-15: DC SPECIFICATIONS: COMPARATOR VOLTAGE REFERENCE S

Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated)

Param

No.

Symbol

Characteristic

Min

Typ

Max

Units

Comments

VRD310 CVRES

VRD311 CVRAA

VRD312 CVRUR

Resolution

—

2k

VDD/32

AVDD – 1.5

—

LSb



Absolute Accuracy

Unit Resistor Value (R)

 2011 Microchip Technology Inc.

DS31037B-page 207

PIC24F16KL402 FAMILY

26.2 AC Characteristics and Timing Parameters

The information contained in this section defines the PIC24F16KL402 Family AC characteristics and timing parameters.

TABLE 26-16: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

Standard Operating Conditions: 1.8V to 3.6V

AC CHARACTERISTICS

Operating temperature-40°C  TA  +85°C for Industrial

Operating voltage VDD range as described in Section 26.1 “DC Characteristics”.

FIGURE 26-2:

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 – for all pins except OSCO

VDD/2

Load Condition 2 – for OSCO

CL

RL

VSS

CL

RL = 464

CL = 50 pF for all pins except OSCO

15 pF for OSCO output

V^SS

TABLE 26-17: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

Param

Symbol

Characteristic

Min

Typ⁽¹⁾Max Units

Conditions

No.

DO50 COSC2

OSCO/CLKO Pin

—

15

pF In XT and HS modes when

external clock is used to drive

OSCI

DO56 CIO

DO58 CB

All I/O Pins and OSCO

SCLx, SDAx

—

50

pF EC mode

pF In I²C™ mode

400

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

DS31037B-page 208

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

FIGURE 26-3:

EXTERNAL CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

OSCI

OS20

OS25

OS30 OS30

OS31 OS31

CLKO

OS40

OS41

TABLE 26-18: EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 1.8V to 3.6V

Operating temperature -40°C  TA  +85°C for Industrial

AC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

OS10 FOSC External CLKI Frequency

(External clocks allowed

DC

4

—

32

8

MHz EC

MHz ECPLL

only in EC mode)

Oscillator Frequency

0.2

4

—

4

25

8

MHz XT

MHz HS

MHz XTPLL

kHz SOSC

31

33

OS20 TOSC TOSC = 1/FOSC

—

See Parameter #OS10 for FOSC

value

OS25 TCY

Instruction Cycle Time⁽²⁾

62.5

—

DC

—

ns

OS30 TosL, External Clock in (OSCI)

TosH High or Low Time

0.45 x TOSC

EC

OS31 TosR, External Clock in (OSCI)

TosF Rise or Fall Time

—

20

ns

OS40 TckR CLKO Rise Time⁽³⁾

OS41 TckF CLKO Fall Time⁽³⁾

—

6

10

ns

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with

the device executing code. Exceeding these specified limits may result in an unstable oscillator operation

and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an

external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time

limit is “DC” (no clock) for all devices.

3: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the

Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).

 2011 Microchip Technology Inc.

DS31037B-page 209

PIC24F16KL402 FAMILY

TABLE 26-19: PLL CLOCK TIMING SPECIFICATIONS

Standard Operating Conditions: 1.8V to 3.6V

Operating temperature -40°C  TA  +85°C for Industrial

AC CHARACTERISTICS

Param

No.

Sym

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

OS50 FPLLI PLL Input Frequency

Range

4

—

8

32

2

MHz ECPLL, HSPLL modes,

-40°C  TA  +85°C

OS51 FSYS PLL Output Frequency

Range

16

—

-2

—

1

MHz -40°C  TA  +85°C

OS52 TLOCK PLL Start-up Time

(Lock Time)

ms

OS53 DCLK CLKO Stability (Jitter)

1

2

%

Measured over 100 ms period

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

TABLE 26-20: INTERNAL RC OSCILLATOR ACCURACY

Standard Operating Conditions: 1.8V to 3.6V

AC CHARACTERISTICS

Operating temperature

-40°C  TA  +85°C for Industrial

Param

No.

Characteristic

Min

Typ

Max Units

Conditions

F20

FRC @ 8 MHz⁽¹⁾

-2

-5

—

+2

+5

%

+25°C

3.0V  VDD  3.6V

1.8V  VDD  3.6V

-40°C  TA +85°C

F21

LPRC @ 31 kHz⁽²⁾

-15

+15

Note 1: The frequency is calibrated at 25°C and 3.3V. The OSCTUN bits can be used to compensate for

temperature drift.

2: The change of LPRC frequency as VDD changes.

TABLE 26-21: INTERNAL RC OSCILLATOR SPECIFICATIONS

Standard Operating Conditions: 1.8V to 3.6V

AC CHARACTERISTICS

Operating temperature -40°C  TA  +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

No.

Sym

Characteristic

Min

Typ

Max

Units

Conditions

—

TFRC FRC Start-up Time

TLPRC LPRC Start-up Time

5

s

70

DS31037B-page 210

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

FIGURE 26-4:

CLKO AND I/O TIMING CHARACTERISTICS

I/O Pin

(Input)

DI35

DI40

I/O Pin

(Output)

New Value

Old Value

DO31

DO32

Note:

Refer to Figure 26-2 for load conditions.

TABLE 26-22: CLKO AND I/O TIMING REQUIREMENTS

Standard Operating Conditions: 1.8V to 3.6V

Operating temperature -40°C  TA  +85°C for Industrial

AC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

DO31 TIOR Port Output Rise Time

DO32 TIOF Port Output Fall Time

—

20

10

—

25

—

ns

DI35

TINP

INTx pin High or Low

Time (output)

DI40

TRBP CNx High or Low Time

(input)

2

—

TCY

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

 2011 Microchip Technology Inc.

DS31037B-page 211

PIC24F16KL402 FAMILY

TABLE 26-23: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT RESET TIMING REQUIREMENTS

Standard Operating Conditions: 1.8V to 3.6V

AC CHARACTERISTICS

Operating temperature

-40°C



TA



+85°C for Industrial

Param

No.

Symbol

Characteristic

Min. Typ⁽¹⁾

Max.

Units

Conditions

SY10 TmcL

MCLR Pulse Width (low)

Power-up Timer Period

Power-on Reset Delay

2

50

1

—

64

5

—

90

s

ms

s

ns

SY11

SY12

SY13

TPWRT

TPOR

TIOZ

10

—

100

I/O High-Impedance from

MCLR Low or Watchdog

Timer Reset

SY20

SY25

TWDT

TBOR

Watchdog Timer Time-out

Period

0.85

3.4

1

1.0

4.0

—

1.15

4.6

—

ms

s

1.32 prescaler

1:128 prescaler

Brown-out Reset Pulse

Width

SY45

SY55

SY65

SY71

TRST

TLOCK

TOST

TPM

Internal State Reset Time

PLL Start-up Time

—

5

100

1024

1

—

s

Oscillator Start-up Time

TOSC

s

Program Memory Wake-up

Time

Sleep wake-up with

PMSLP = 0

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

TABLE 26-24: COMPARATOR TIMINGS

Param

Symbol

Characteristic

Min

Typ

Max

Units

Comments

No.

300

301

TRESP

Response Time^*(1)

—

150

—

400

10

ns

TMC2OV Comparator Mode Change to

Output Valid^*

s

*

Parameters are characterized but not tested.

Note 1: Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions

from VSS to VDD.

TABLE 26-25: COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS

Param

Symbol

Characteristic

Min

Typ

Max

Units

Comments

No.

VR310 TSET

Settling Time⁽¹⁾

—

10

s

Note 1: Settling time is measured while CVRSS = 1and CVR<3:0> bits transition from ‘0000’ to ‘1111’.

DS31037B-page 212

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

FIGURE 26-5:

CAPTURE/COMPARE/PWM TIMINGS (ECCP1, ECCP2 MODULES)

CCPx

(Capture Mode)

50

51

52

54

CCPx

(Compare or PWM Mode)

53

Note:

Refer to Figure 26-2 for load conditions.

TABLE 26-26: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP1, ECCP2 MODULES)

Param

Symbol

Characteristic

Min

Max

Units

Conditions

No.

50

TCCL

CCPx Input Low No prescaler

0.5 TCY + 20

—

ns

Time

With prescaler

20

0.5 TCY + 20

20

51

52

TCCH

TCCP

CCPx Input

High Time

No prescaler

With prescaler

CCPx Input Period

greater of:

40, or

N = prescale

value (1, 4 or 16)

2 TCY + 40

N

53

54

TCCR

TCCF

CCPx Output Fall Time

—

25

ns

 2011 Microchip Technology Inc.

DS31037B-page 213

PIC24F16KL402 FAMILY

FIGURE 26-6:

EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

SCKx

(CKP = 0)

78

79

78

SCKx

(CKP = 1)

MSb

bit 6 - - - - - - 1

LSb

SDOx

SDIx

75, 76

MSb In

74

bit 6 - - - - 1

LSb In

73

Note: Refer to Figure 26-2 for load conditions.

TABLE 26-27: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

Param

No.

Symbol

Characteristic

Min

Max

Units

Conditions

73

TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge

TDIV2SCL

20

—

ns

74

TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge

TSCL2DIL

40

—

ns

75

76

78

79

TDOR

TDOF

TSCR

TSCF

FSCK

SDOx Data Output Rise Time

SDOx Data Output Fall Time

SCKx Output Rise Time (Master mode)

SCKx Output Fall Time (Master mode)

SCKx Frequency

—

25

10

ns

MHz

DS31037B-page 214

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

FIGURE 26-7:

EXAMPLE SPI MASTER MODE TIMING (CKE = 1)

81

SCKx

(CKP = 0)

79

78

73

SCKx

(CKP = 1)

LSb

MSb

bit 6 - - - - - - 1

SDOx

SDIx

75, 76

MSb In

74

bit 6 - - - - 1

LSb In

Note: Refer to Figure 26-2 for load conditions.

TABLE 26-28: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

Param.

No.

Symbol

Characteristic

Min

Max

Units

Conditions

73

TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge

TDIV2SCL

35

—

ns

74

TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge

TSCL2DIL

40

—

ns

75

76

78

79

81

TDOR

TDOF

TSCR

TSCF

SDOx Data Output Rise Time

—

25

—

ns

SDOx Data Output Fall Time

SCKx Output Rise Time (Master mode)

SCKx Output Fall Time (Master mode)

—

TDOV2SCH, SDOx Data Output Setup to SCKx Edge

TDOV2SCL

TCY

FSCK

SCKx Frequency

—

10

MHz

 2011 Microchip Technology Inc.

DS31037B-page 215

PIC24F16KL402 FAMILY

FIGURE 26-8:

EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

SSx

70

SCKx

(CKP = 0)

83

71

72

SCKx

(CKP = 1)

80

MSb

LSb

SDOx

SDIx

bit 6 - - - - - - 1

bit 6 - - - - 1

75, 76

77

MSb In

74

LSb In

73

Note:

Refer to Figure 26-2 for load conditions.

TABLE 26-29: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)

Param

No.

Symbol

Characteristic

Min

Max Units Conditions

70

TSSL2SCH, SSx  to SCKx  or SCKx  Input

3 TCY

—

ns

TSSL2SCL

70A

71

TSSL2WB SSx to write to SSPxBUF

3 TCY

—

ns

TSCH

SCKx Input High Time

(Slave mode)

Continuous

Single Byte

Continuous

Single Byte

1.25 TCY + 30

ns

71A

72

40

ns (Note 1)

TSCL

SCKx Input Low Time

(Slave mode)

1.25 TCY + 30

ns

72A

73

40

20

ns (Note 1)

TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge

TDIV2SCL

ns

73A

74

TB2B

Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40

—

ns (Note 2)

TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge

TSCL2DIL

40

ns

75

76

77

80

TDOR

TDOF

SDOx Data Output Rise Time

SDOx Data Output Fall Time

—

10

—

25

50

ns

TSSH2DOZ SSx  to SDOx Output High-Impedance

TSCH2DOV, SDOx Data Output Valid after SCKx Edge

TSCL2DOV

83

TSCH2SSH, SSx  after SCKx Edge

TSCL2SSH

1.5 TCY + 40

—

ns

FSCK

SCKx Frequency

10 MHz

Note 1: Requires the use of Parameter #73A.

2: Only if Parameter #71A and #72A are used.

DS31037B-page 216

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

FIGURE 26-9:

EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)

82

SSx

70

SCKx

83

(CKP = 0)

71

72

73

SCKx

(CKP = 1)

80

MSb

bit 6 - - - - - - 1

LSb

SDOx

SDIx

75, 76

77

MSb In

74

bit 6 - - - - 1

LSb In

Note: Refer to Figure 26-2 for load conditions.

TABLE 26-30: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Param

No.

Symbol

Characteristic

Min

Max Units Conditions

70

TSSL2SCH, SSx  to SCKx  or SCKx  Input

3 TCY

—

ns

TSSL2SCL

70A

71

TSSL2WB SSx to Write to SSPxBUF

3 TCY

1.25 TCY + 30

40

—

ns

TSCH

TSCL

TB2B

SCKx Input High Time

(Slave mode)

Continuous

Single Byte

Continuous

Single Byte

ns

71A

72

ns (Note 1)

ns

SCKx Input Low Time

(Slave mode)

1.25 TCY + 30

40

72A

73A

74

ns (Note 1)

ns (Note 2)

ns

Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40

TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge

TSCL2DIL

40

75

76

77

80

TDOR

TDOF

SDOx Data Output Rise Time

SDOx Data Output Fall Time

—

10

—

25

50

ns

TSSH2DOZ SSx  to SDOx Output High-Impedance

TSCH2DOV, SDOx Data Output Valid After SCKx Edge

TSCL2DOV

82

83

TSSL2DOV SDOx Data Output Valid After SSx  Edge

—

50

—

ns

TSCH2SSH, SSx  After SCKx Edge

1.5 TCY + 40

TSCL2SSH

FSCK

SCKx Frequency

—

10 MHz

Note 1: Requires the use of Parameter #73A.

2: Only if Parameter #71A and #72A are used.

 2011 Microchip Technology Inc.

DS31037B-page 217

PIC24F16KL402 FAMILY

FIGURE 26-10:

I²C™ BUS START/STOP BITS TIMING

SCLx

91

93

90

92

SDAx

Stop

Condition

Start

Condition

Note: Refer to Figure 26-2 for load conditions.

TABLE 26-31: I²C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)

Param.

Symbol

Characteristic

Min

Max

Units

Conditions

No.

90

TSU:STA Start Condition

Setup Time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

4700

600

—

ns

Only relevant for Repeated

Start condition

91

92

93

THD:STA Start Condition

Hold Time

4000

600

ns

After this period, the first

clock pulse is generated

TSU:STO Stop Condition

Setup Time

4700

600

THD:STO Stop Condition

Hold Time

4000

600

FIGURE 26-11:

I²C™ BUS DATA TIMING

103

102

100

101

SCLx

90

106

107

91

92

SDAx

In

110

109

SDAx

Out

Note: Refer to Figure 26-2 for load conditions.

DS31037B-page 218

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

TABLE 26-32: I²C™ BUS DATA REQUIREMENTS (SLAVE MODE)

Param.

No.

Symbol

Characteristic

100 kHz mode

Min

Max

Units

Conditions

100

THIGH

Clock High Time

4.0

—

s

Must operate at a minium of

1.5 MHz

400 kHz mode

0.6

—

s

Must operate at a minium of

10 MHz

MSSP module

100 kHz mode

1.5 TCY

4.7

—

101

TLOW

Clock Low Time

s

Must operate at a minium of

1.5 MHz

400 kHz mode

MSSP module

1.3

—

Must operate at a minium of

10 MHz

1.5 TCY

—

102

103

TR

SDAx and SCLx Rise Time 100 kHz mode

400 kHz mode

1000

300

ns

20 + 0.1 CB

CB is specified to be from

10 to 400 pF

TF

SDAx and SCLx Fall Time 100 kHz mode

400 kHz mode

—

300

ns

20 + 0.1 CB

CB is specified to be from

10 to 400 pF

90

TSU:STA

Start Condition Setup Time 100 kHz mode

400 kHz mode

4.7

0.6

4.0

0.6

0

—

s

ns

s

ns

s

ns

s

pF

Only relevant for Repeated

Start condition

91

THD:STA Start Condition Hold Time 100 kHz mode

400 kHz mode

—

After this period, the first clock

pulse is generated

—

106

107

92

THD:DAT Data Input Hold Time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

—

0

0.9

—

TSU:DAT Data Input Setup Time

250

100

4.7

0.6

—

(Note 2)

—

TSU:STO Stop Condition Setup Time 100 kHz mode

400 kHz mode

—

109

110

D102

TAA

TBUF

CB

Output Valid from Clock

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

3500

—

(Note 1)

—

Bus Free Time

4.7

1.3

—

Time the bus must be free before

a new transmission can start

—

Bus Capacitive Loading

400

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of

the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.

2

2: A Fast mode I C™ bus device can be used in a Standard mode I C bus system, but the requirement, TSU:DAT  250 ns,

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If

such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line,

2

TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification), before the SCLx line

is released.

 2011 Microchip Technology Inc.

DS31037B-page 219

PIC24F16KL402 FAMILY

FIGURE 26-12:

MSSP I²C™ BUS START/STOP BITS TIMING WAVEFORMS

SCLx

93

91

90

92

SDAx

Stop

Condition

Start

Condition

Note: Refer to Figure 26-2 for load conditions.

TABLE 26-33: I²C™ BUS START/STOP BITS REQUIREMENTS (MASTER MODE)

Param.

Symbol

Characteristic

Min

Max Units

Conditions

No.

90

TSU:STA Start Condition

Setup Time

100 kHz mode

400 kHz mode

2(TOSC)(BRG + 1)

—

ns Only relevant for

Repeated Start

condition

91

THD:STA Start Condition

Hold Time

100 kHz mode

400 kHz mode

2(TOSC)(BRG + 1)

—

ns After this period, the

first clock pulse is

generated

92

93

TSU:STO Stop Condition

Setup Time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

2(TOSC)(BRG + 1)

—

ns

THD:STO Stop Condition

Hold Time

—

ns

DS31037B-page 220

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

FIGURE 26-13:

MSSP I²C™ BUS DATA TIMING

103

102

100

101

SCLx

90

106

91

92

107

SDAx

In

110

109

SDAx

Out

Note: Refer to Figure 26-2 for load conditions.

TABLE 26-34: I²C™ BUS DATA REQUIREMENTS (MASTER MODE)

Param.

Symbol

Characteristic

Min

Max Units

Conditions

No.

100

THIGH

Clock High Time 100 kHz mode 2(TOSC)(BRG + 1)

400 kHz mode 2(TOSC)(BRG + 1)

—

ns

—

ns

s

ns

—

ns

s

101

102

103

90

TLOW

TR

Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1)

400 kHz mode 2(TOSC)(BRG + 1)

—

SDAx and SCLx 100 kHz mode

—

1000

300

—

CB is specified to be from

10 to 400 pF

Rise Time

400 kHz mode

20 + 0.1 CB

—

TF

SDAx and SCLx 100 kHz mode

CB is specified to be from

10 to 400 pF

Fall Time

400 kHz mode

20 + 0.1 CB

TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1)

Only relevant for Repeated

Start condition

Setup Time

400 kHz mode 2(TOSC)(BRG + 1)

—

91

THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1)

—

After this period, the first

clock pulse is generated

Hold Time

400 kHz mode 2(TOSC)(BRG + 1)

—

106

107

92

THD:DAT Data Input

Hold Time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

0

—

0

0.9

—

TSU:DAT Data Input

Setup Time

250

100

(Note 1)

—

TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1)

—

Setup Time

400 kHz mode 2(TOSC)(BRG + 1)

—

109

110

TAA

Output Valid

from Clock

100 kHz mode

400 kHz mode

—

3500

1000

—

TBUF

Bus Free Time 100 kHz mode

400 kHz mode

4.7

1.3

Time the bus must be free

before a new transmission

can start

—

D102

CB

Bus Capacitive Loading

—

400

pF

Note 1: A Fast mode I²C bus device can be used in a Standard mode I²C bus system, but Parameter  250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the

SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data

bit to the SDAx line, Parameter + Parameter = 1000 + 250 = 1250 ns (for 100 kHz mode), before the SCLx

line is released.

 2011 Microchip Technology Inc.

DS31037B-page 221

PIC24F16KL402 FAMILY

TABLE 26-35: A/D MODULE SPECIFICATIONS

Standard Operating Conditions: 1.8V to 3.6V (unless otherwise

stated)

Operating temperature -40°C  TA  +85°C for Industrial

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min.

Typ

Max.

Units

Conditions

Device Supply

AD01 AVDD

AD02 AVSS

Module VDD Supply

Module VSS Supply

Greater of

VDD – 0.3

or 1.8

—

Lesser of

VDD + 0.3

or 3.6

V

VSS – 0.3

VSS + 0.3

Reference Inputs

AD05 VREFH

AD06 VREFL

AD07 VREF

Reference Voltage High

Reference Voltage Low

AVSS + 1.7

AVSS

—

AVDD

V

AVDD – 1.7

AVDD + 0.3

Absolute Reference

Voltage

AVSS – 0.3

Analog Input

AD10 VINH-VINL Full-Scale Input Span

VREFL

—

VREFH

AVDD + 0.3

AVDD/2

V

(Note 1)

AD11 VIN

AD12 VINL

Absolute Input Voltage

AVSS – 0.3

Absolute VINL Input

Voltage

AD17 RIN

Recommended

—

2.5K



10-bit

Impedance of Analog

Voltage Source

A/D Accuracy

AD20b NR

AD21b INL

Resolution

—

10

±1

—

±2

bits

Integral Nonlinearity

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

AD22b DNL

AD23b GERR

AD24b EOFF

AD25b

Differential Nonlinearity

Gain Error

—

±1

—

±1.5

±3

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

Offset Error

±2

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3V

Monotonicity

—

(Note 2)

Note 1: Measurements are taken with external VREF+ and VREF- used as the A/D voltage reference.

2: The A/D conversion result never decreases with an increase in the input voltage.

DS31037B-page 222

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

TABLE 26-36: A/D CONVERSION TIMING REQUIREMENTS⁽¹⁾

Standard Operating Conditions: 1.8V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  TA  +85°C for Industrial

Param

Symbol

No.

Characteristic

Min.

Typ

Max.

Units

Conditions

Clock Parameters

AD50

AD51

TAD

TRC

A/D Clock Period

75

—

ns

TCY = 75 ns, AD1CON3

in default state

A/D Internal RC Oscillator Period

—

250

Conversion Rate

AD55

AD56

AD57

AD58

AD59

TCONV

FCNV

TSAMP

TACQ

Conversion Time

Throughput Rate

Sample Time

—

12

—

1

—

500

TAD

ksps AVDD  2.7V

—

TAD

Acquisition Time

750

—

ns

(Note 2)

TSWC

Switching Time from Convert to

Sample

—

(Note 3)

AD60

AD61

TDIS

Discharge Time

0.5

—

3

TAD

Clock Parameters

Sample Start Delay from setting

Sample bit (SAMP)

TPSS

2

—

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

2: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale

after the conversion (VDD to VSS or VSS to VDD).

3: On the following cycle of the device clock.

 2011 Microchip Technology Inc.

DS31037B-page 223

PIC24F16KL402 FAMILY

NOTES:

DS31037B-page 224

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

27.0 PACKAGING INFORMATION

27.1 Package Marking Information

14-Lead PDIP (300 mil)

Example

PIC24F04KL100

e

3

-I/P

1116012

20-Lead PDIP (300 mil)

Example

PIC24F08KL201

XXXXXXXXXXXXXXXXX

e

3

-I/P

YYWWNNN

1116012

28-Lead SPDIP (.300”)

Example

PIC24F16KL302

e

3

-I/SP

1116012

Legend: XX...X Product-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

e

3

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note:

In the event the full Microchip part number cannot be marked on one line, it

will be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2011 Microchip Technology Inc.

DS31037B-page 225

PIC24F16KL402 FAMILY

20-Lead SOIC (7.50 mm)

Example

XXXXXXXXXXXX

PIC24F08KL301

-I/SO

e

3

1116012

YYWWNNN

28-Lead SOIC (7.50 mm)

Example

PIC24F08KL302

XXXXXXXXXXXXXXXXXXXX

e

3

-I/SO

1116012

YYWWNNN

14-Lead TSSOP (4.4 mm)

Example

24F08KL1

1116

XXXXXXXX

YYWW

012

NNN

20-Lead SSOP (5.30 mm)

Example

PIC24F08KL

401-I/SS

e

3

1116012

DS31037B-page 226

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

28-Lead SSOP (5.30 mm)

Example

PIC24F08KL

e

3

402-I/SS

1116012

20-Lead QFN (5x5x0.9 mm)

Example

PIN 1

PIC24F08

KL301

e

3

-I/MQ

1116012

28-Lead QFN (5x5x0.9 mm)

Example

PIN 1

PIC24F08

KL302

e

3

-I/ML

1116012

28-Lead QFN (6x6 mm)

Example

PIN 1

PIC24F08KL

XXXXXXXX

YYWWNNN

e

3

301-I/ML

1116012

 2011 Microchip Technology Inc.

DS31037B-page 227

PIC24F16KL402 FAMILY

27.2 Package Details

The following sections give the technical details of the packages.

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N

NOTE 1

E1

3

1

2

D

E

A2

A

L

c

A1

b1

b

e

eB

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ꢌ

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ꢩꢉꢇꢌꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ

ꢛꢘꢕꢈꢊꢋꢌꢐꢅꢏꢕꢅꢛꢘꢕꢈꢊꢋꢌꢐꢅꢸꢃꢋꢏꢘ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢸꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ

ꢫꢃꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ

ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢯꢡꢡꢌꢐꢅꢳꢌꢉꢋꢅꢸꢃꢋꢏꢘ

ꢦꢙ

ꢦꢀ

ꢠ

ꢠꢀ

ꢟ

ꢳ

ꢖ

ꢔꢀ

ꢔ

ꢌꢩ

ꢁꢀꢀꢨ

ꢁꢣꢀꢨ

ꢁꢙꢷꢣ

ꢁꢙꢥꢣ

ꢁꢺꢞꢨ

ꢁꢀꢀꢨ

ꢁꢣꢣꢹ

ꢁꢣꢥꢨ

ꢁꢣꢀꢥ

ꢶ

ꢁꢀꢞꢣ

ꢶ

ꢁꢞꢀꢣ

ꢁꢙꢨꢣ

ꢁꢺꢨꢣ

ꢁꢀꢞꢣ

ꢁꢣꢀꢣ

ꢁꢣꢻꢣ

ꢁꢣꢀꢹ

ꢶ

ꢁꢞꢙꢨ

ꢁꢙꢹꢣ

ꢁꢺꢺꢨ

ꢁꢀꢨꢣ

ꢁꢣꢀꢨ

ꢁꢣꢺꢣ

ꢁꢣꢙꢙ

ꢁꢥꢞꢣ

ꢳꢕꢗꢌꢐꢅꢳꢌꢉꢋꢅꢸꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢼꢕꢗꢅꢛꢡꢉꢖꢃꢄꢜꢅꢅꢚ

ꢝꢙꢋꢄꢊꢞ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢚꢅꢛꢃꢜꢄꢃꢎꢃꢖꢉꢄꢏꢅꢝꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ

ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢁꢣꢀꢣꢤꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ

ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ

ꢩꢛꢝꢪꢅꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢣꢨꢩ

DS31037B-page 228

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

ꢟꢖꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢅꢉꢇꢐꢑꢂꢃꢌꢑꢄꢇꢒꢈꢓꢇꢔꢇꢕꢖꢖꢇꢗꢌꢉꢇꢘꢙꢆꢚꢇꢛꢈꢎꢐꢈꢜ

ꢝꢙꢋꢄꢞ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ

ꢅ

N

E1

NOTE 1

1

2

3

D

E

A2

A

L

c

A1

b1

eB

e

b

ꢯꢄꢃꢏꢇꢰꢱꢝꢲꢠꢛ

ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ

ꢙꢣ

ꢢꢰꢱ

ꢱꢴꢢ

ꢢꢦꢵ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇꢱ

ꢂꢃꢏꢖꢘ

ꢫꢕꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢩꢉꢇꢌꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ

ꢛꢘꢕꢈꢊꢋꢌꢐꢅꢏꢕꢅꢛꢘꢕꢈꢊꢋꢌꢐꢅꢸꢃꢋꢏꢘ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢸꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ

ꢫꢃꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ

ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢯꢡꢡꢌꢐꢅꢳꢌꢉꢋꢅꢸꢃꢋꢏꢘ

ꢳꢕꢗꢌꢐꢅꢳꢌꢉꢋꢅꢸꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢼꢕꢗꢅꢛꢡꢉꢖꢃꢄꢜꢅꢅꢚ

ꢌ

ꢦ

ꢦꢙ

ꢦꢀ

ꢠ

ꢠꢀ

ꢟ

ꢳ

ꢁꢀꢣꢣꢅꢩꢛꢝ

ꢶ

ꢁꢀꢞꢣ

ꢶ

ꢁꢞꢀꢣ

ꢁꢙꢨꢣ

ꢀꢁꢣꢞꢣ

ꢁꢀꢞꢣ

ꢁꢣꢀꢣ

ꢁꢣꢻꢣ

ꢁꢣꢀꢹ

ꢶ

ꢁꢙꢀꢣ

ꢁꢀꢷꢨ

ꢶ

ꢁꢀꢀꢨ

ꢁꢣꢀꢨ

ꢁꢞꢣꢣ

ꢁꢙꢥꢣ

ꢁꢷꢹꢣ

ꢁꢀꢀꢨ

ꢁꢣꢣꢹ

ꢁꢣꢥꢨ

ꢁꢣꢀꢥ

ꢶ

ꢁꢞꢙꢨ

ꢁꢙꢹꢣ

ꢀꢁꢣꢻꢣ

ꢁꢀꢨꢣ

ꢁꢣꢀꢨ

ꢁꢣꢺꢣ

ꢁꢣꢙꢙ

ꢁꢥꢞꢣ

ꢖ

ꢔꢀ

ꢔ

ꢌꢩ

ꢝꢙꢋꢄꢊꢞ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢚꢅꢛꢃꢜꢄꢃꢎꢃꢖꢉꢄꢏꢅꢝꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ

ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢁꢣꢀꢣꢤꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ

ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ

ꢩꢛꢝꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢀꢷꢩ

 2011 Microchip Technology Inc.

DS31037B-page 229

PIC24F16KL402 FAMILY

ꢟꢠꢂꢃꢄꢅꢆꢇꢡꢢꢌꢑꢑꢚꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢅꢉꢇꢐꢑꢂꢃꢌꢑꢄꢇꢒꢡꢈꢓꢇꢔꢇꢕꢖꢖꢇꢗꢌꢉꢇꢘꢙꢆꢚꢇꢛꢡꢈꢎꢐꢈꢜ

ꢝꢙꢋꢄꢞ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ

N

NOTE 1

E1

1

2 3

D

E

A2

A

L

c

b1

A1

b

e

eB

ꢯꢄꢃꢏꢇꢰꢱꢝꢲꢠꢛ

ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ

ꢙꢹ

ꢢꢰꢱ

ꢱꢴꢢ

ꢢꢦꢵ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇꢱ

ꢂꢃꢏꢖꢘ

ꢫꢕꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢩꢉꢇꢌꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ

ꢛꢘꢕꢈꢊꢋꢌꢐꢅꢏꢕꢅꢛꢘꢕꢈꢊꢋꢌꢐꢅꢸꢃꢋꢏꢘ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢸꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ

ꢫꢃꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ

ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢯꢡꢡꢌꢐꢅꢳꢌꢉꢋꢅꢸꢃꢋꢏꢘ

ꢳꢕꢗꢌꢐꢅꢳꢌꢉꢋꢅꢸꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢼꢕꢗꢅꢛꢡꢉꢖꢃꢄꢜꢅꢅꢚ

ꢌ

ꢦ

ꢦꢙ

ꢦꢀ

ꢠ

ꢠꢀ

ꢟ

ꢳ

ꢁꢀꢣꢣꢅꢩꢛꢝ

ꢶ

ꢁꢀꢞꢨ

ꢶ

ꢁꢞꢀꢣ

ꢁꢙꢹꢨ

ꢀꢁꢞꢻꢨ

ꢁꢀꢞꢣ

ꢁꢣꢀꢣ

ꢁꢣꢨꢣ

ꢁꢣꢀꢹ

ꢶ

ꢁꢙꢣꢣ

ꢁꢀꢨꢣ

ꢶ

ꢁꢀꢙꢣ

ꢁꢣꢀꢨ

ꢁꢙꢷꢣ

ꢁꢙꢥꢣ

ꢀꢁꢞꢥꢨ

ꢁꢀꢀꢣ

ꢁꢣꢣꢹ

ꢁꢣꢥꢣ

ꢁꢣꢀꢥ

ꢶ

ꢁꢞꢞꢨ

ꢁꢙꢷꢨ

ꢀꢁꢥꢣꢣ

ꢁꢀꢨꢣ

ꢁꢣꢀꢨ

ꢁꢣꢺꢣ

ꢁꢣꢙꢙ

ꢁꢥꢞꢣ

ꢖ

ꢔꢀ

ꢔ

ꢌꢩ

ꢝꢙꢋꢄꢊꢞ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢚꢅꢛꢃꢜꢄꢃꢎꢃꢖꢉꢄꢏꢅꢝꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ

ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢁꢣꢀꢣꢤꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ

ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ

ꢩꢛꢝꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢺꢣꢩ

DS31037B-page 230

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

ꢟꢖꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢡꢗꢅꢉꢉꢇꢣꢏꢋꢉꢌꢑꢄꢇꢒꢡꢣꢓꢇꢔ ꢤꢌꢆꢄꢥꢇꢦꢧꢨꢖꢇꢗꢗꢇꢘꢙꢆꢚꢇꢛꢡꢣꢐꢩꢜ

ꢝꢙꢋꢄꢞ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ

D

N

E

E1

NOTE 1

1

2

3

b

e

α

h

c

φ

A2

A

L

β

A1

L1

ꢯꢄꢃꢏꢇꢢꢰꢳꢳꢰꢢꢠꢫꢠꢼꢛ

ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ

ꢢꢰꢱ

ꢱꢴꢢ

ꢢꢦꢵ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇꢱ

ꢂꢃꢏꢖꢘ

ꢙꢣ

ꢌ

ꢀꢁꢙꢺꢅꢩꢛꢝ

ꢴꢆꢌꢐꢉꢊꢊꢅꢲꢌꢃꢜꢘꢏ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢛꢏꢉꢄꢋꢕꢎꢎꢅꢅꢚ

ꢦ

ꢶ

ꢙꢁꢣꢨ

ꢣꢁꢀꢣ

ꢶ

ꢙꢁꢻꢨ

ꢶ

ꢣꢁꢞꢣ

ꢦꢙ

ꢦꢀ

ꢠ

ꢴꢆꢌꢐꢉꢊꢊꢅꢸꢃꢋꢏꢘ

ꢀꢣꢁꢞꢣꢅꢩꢛꢝ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢸꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ

ꢝꢘꢉꢑꢎꢌꢐꢅꢾꢕꢡꢏꢃꢕꢄꢉꢊꢿ

ꢬꢕꢕꢏꢅꢳꢌꢄꢜꢏꢘ

ꢠꢀ

ꢟ

ꢘ

ꢺꢁꢨꢣꢅꢩꢛꢝ

ꢀꢙꢁꢹꢣꢅꢩꢛꢝ

ꢣꢁꢙꢨ

ꢣꢁꢥꢣ

ꢶ

ꢣꢁꢺꢨ

ꢀꢁꢙꢺ

ꢳ

ꢬꢕꢕꢏꢡꢐꢃꢄꢏ

ꢬꢕꢕꢏꢅꢦꢄꢜꢊꢌ

ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢳꢌꢉꢋꢅꢸꢃꢋꢏꢘ

ꢢꢕꢊꢋꢅꢟꢐꢉꢎꢏꢅꢦꢄꢜꢊꢌꢅꢫꢕꢡ

ꢢꢕꢊꢋꢅꢟꢐꢉꢎꢏꢅꢦꢄꢜꢊꢌꢅꢩꢕꢏꢏꢕꢑ

ꢳꢀ

ꢀ

ꢀꢁꢥꢣꢅꢼꢠꢬ

ꢣꣀ

ꢣꢁꢙꢣ

ꢣꢁꢞꢀ

ꢨꣀ

ꢶ

ꢹꣀ

ꢖ

ꢔ

ꢁ

ꢣꢁꢞꢞ

ꢣꢁꢨꢀ

ꢀꢨꣀ

ꢂ

ꢨꣀ

ꢀꢨꣀ

ꢝꢙꢋꢄꢊꢞ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢚꢅꢛꢃꢜꢄꢃꢎꢃꢖꢉꢄꢏꢅꢝꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ

ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢣꢁꢀꢨꢅꢑꢑꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ

ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ

ꢩꢛꢝꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢼꢠꢬꢪ ꢼꢌꢎꢌꢐꢌꢄꢖꢌꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢡꢈꢐꢡꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ

ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢷꢥꢩ

 2011 Microchip Technology Inc.

DS31037B-page 231

PIC24F16KL402 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS31037B-page 232

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

ꢟꢠꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢡꢗꢅꢉꢉꢇꢣꢏꢋꢉꢌꢑꢄꢇꢒꢡꢣꢓꢇꢔꢇꢤꢌꢆꢄꢥꢇꢦꢧꢨꢖꢇꢗꢗꢇꢘꢙꢆꢚꢇꢛꢡꢣꢐꢩꢜ

ꢝꢙꢋꢄꢞ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ

D

N

E

E1

NOTE 1

1

2

3

e

b

h

α

h

c

φ

A2

A

L

A1

L1

β

ꢯꢄꢃꢏꢇꢢꢰꢳꢳꢰꢢꢠꢫꢠꢼꢛ

ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ

ꢢꢰꢱ

ꢱꢴꢢ

ꢢꢦꢵ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇꢱ

ꢂꢃꢏꢖꢘ

ꢙꢹ

ꢌ

ꢀꢁꢙꢺꢅꢩꢛꢝ

ꢴꢆꢌꢐꢉꢊꢊꢅꢲꢌꢃꢜꢘꢏ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢛꢏꢉꢄꢋꢕꢎꢎꢅꢅꢚ

ꢦ

ꢶ

ꢙꢁꢣꢨ

ꢣꢁꢀꢣ

ꢶ

ꢙꢁꢻꢨ

ꢶ

ꢣꢁꢞꢣ

ꢦꢙ

ꢦꢀ

ꢠ

ꢴꢆꢌꢐꢉꢊꢊꢅꢸꢃꢋꢏꢘ

ꢀꢣꢁꢞꢣꢅꢩꢛꢝ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢸꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ

ꢝꢘꢉꢑꢎꢌꢐꢅꢾꢕꢡꢏꢃꢕꢄꢉꢊꢿ

ꢬꢕꢕꢏꢅꢳꢌꢄꢜꢏꢘ

ꢠꢀ

ꢟ

ꢘ

ꢺꢁꢨꢣꢅꢩꢛꢝ

ꢀꢺꢁꢷꢣꢅꢩꢛꢝ

ꢣꢁꢙꢨ

ꢣꢁꢥꢣ

ꢶ

ꢣꢁꢺꢨ

ꢀꢁꢙꢺ

ꢳ

ꢬꢕꢕꢏꢡꢐꢃꢄꢏ

ꢳꢀ

ꢀ

ꢀꢁꢥꢣꢅꢼꢠꢬ

ꢬꢕꢕꢏꢅꢦꢄꢜꢊꢌꢅꢫꢕꢡ

ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢳꢌꢉꢋꢅꢸꢃꢋꢏꢘ

ꢢꢕꢊꢋꢅꢟꢐꢉꢎꢏꢅꢦꢄꢜꢊꢌꢅꢫꢕꢡ

ꢢꢕꢊꢋꢅꢟꢐꢉꢎꢏꢅꢦꢄꢜꢊꢌꢅꢩꢕꢏꢏꢕꢑ

ꢣꣀ

ꢣꢁꢀꢹ

ꢣꢁꢞꢀ

ꢨꣀ

ꢶ

ꢹꣀ

ꢖ

ꢔ

ꢁ

ꢣꢁꢞꢞ

ꢣꢁꢨꢀ

ꢀꢨꣀ

ꢂ

ꢨꣀ

ꢀꢨꣀ

ꢝꢙꢋꢄꢊꢞ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢚꢅꢛꢃꢜꢄꢃꢎꢃꢖꢉꢄꢏꢅꢝꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ

ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢣꢁꢀꢨꢅꢑꢑꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ

ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ

ꢩꢛꢝꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢼꢠꢬꢪ ꢼꢌꢎꢌꢐꢌꢄꢖꢌꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢡꢈꢐꢡꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ

ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢨꢙꢩ

 2011 Microchip Technology Inc.

DS31037B-page 233

PIC24F16KL402 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS31037B-page 234

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2011 Microchip Technology Inc.

DS31037B-page 235

PIC24F16KL402 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS31037B-page 236

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2011 Microchip Technology Inc.

DS31037B-page 237

PIC24F16KL402 FAMILY

ꢟꢖꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢡꢪꢫꢌꢑꢢꢇꢡꢗꢅꢉꢉꢇꢣꢏꢋꢉꢌꢑꢄꢇꢒꢡꢡꢓꢇꢔꢇꢨꢧꢕꢖꢇꢗꢗꢇꢘꢙꢆꢚꢇꢛꢡꢡꢣꢈꢜꢇ

ꢝꢙꢋꢄꢞ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ

D

N

E

E1

NOTE 1

1

2

e

b

c

A2

A

φ

A1

L1

ꢯꢄꢃꢏꢇꢢꢰꢳꢳꢰꢢꢠꢫꢠꢼꢛ

L

ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ

ꢢꢰꢱ

ꢱꢴꢢ

ꢢꢦꢵ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇꢱ

ꢂꢃꢏꢖꢘ

ꢙꢣ

ꢌ

ꢣꢁꢻꢨꢅꢩꢛꢝ

ꢴꢆꢌꢐꢉꢊꢊꢅꢲꢌꢃꢜꢘꢏ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢛꢏꢉꢄꢋꢕꢎꢎꢅ

ꢴꢆꢌꢐꢉꢊꢊꢅꢸꢃꢋꢏꢘ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢸꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ

ꢬꢕꢕꢏꢅꢳꢌꢄꢜꢏꢘ

ꢬꢕꢕꢏꢡꢐꢃꢄꢏ

ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢬꢕꢕꢏꢅꢦꢄꢜꢊꢌ

ꢦ

ꢶ

ꢀꢁꢺꢨ

ꢶ

ꢺꢁꢹꢣ

ꢨꢁꢞꢣ

ꢺꢁꢙꢣ

ꢣꢁꢺꢨ

ꢀꢁꢙꢨꢅꢼꢠꢬ

ꢶ

ꢙꢁꢣꢣ

ꢀꢁꢹꢨ

ꢶ

ꢹꢁꢙꢣ

ꢨꢁꢻꢣ

ꢺꢁꢨꢣ

ꢣꢁꢷꢨ

ꢦꢙ

ꢦꢀ

ꢠ

ꢠꢀ

ꢟ

ꢳ

ꢳꢀ

ꢖ

ꢀꢁꢻꢨ

ꢣꢁꢣꢨ

ꢺꢁꢥꢣ

ꢨꢁꢣꢣ

ꢻꢁꢷꢣ

ꢣꢁꢨꢨ

ꢣꢁꢣꢷ

ꢣꣀ

ꢣꢁꢙꢨ

ꢹꣀ

ꢀ

ꢥꣀ

ꢳꢌꢉꢋꢅꢸꢃꢋꢏꢘ

ꢔ

ꢣꢁꢙꢙ

ꢶ

ꢣꢁꢞꢹ

ꢝꢙꢋꢄꢊꢞ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢣꢁꢙꢣꢅꢑꢑꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ

ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ

ꢩꢛꢝꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢼꢠꢬꢪ ꢼꢌꢎꢌꢐꢌꢄꢖꢌꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢡꢈꢐꢡꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ

ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢺꢙꢩ

DS31037B-page 238

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2011 Microchip Technology Inc.

DS31037B-page 239

PIC24F16KL402 FAMILY

ꢟꢠꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢡꢪꢫꢌꢑꢢꢇꢡꢗꢅꢉꢉꢇꢣꢏꢋꢉꢌꢑꢄꢇꢒꢡꢡꢓꢇꢔꢇꢨꢧꢕꢖꢇꢗꢗꢇꢘꢙꢆꢚꢇꢛꢡꢡꢣꢈꢜ

ꢝꢙꢋꢄꢞ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ

D

N

E

E1

1

2

b

NOTE 1

e

c

A2

A

φ

A1

L

L1

ꢯꢄꢃꢏꢇꢢꢰꢳꢳꢰꢢꢠꢫꢠꢼꢛ

ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ

ꢢꢰꢱ

ꢱꢴꢢ

ꢢꢦꢵ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇꢱ

ꢂꢃꢏꢖꢘ

ꢙꢹ

ꢌ

ꢣꢁꢻꢨꢅꢩꢛꢝ

ꢴꢆꢌꢐꢉꢊꢊꢅꢲꢌꢃꢜꢘꢏ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢛꢏꢉꢄꢋꢕꢎꢎꢅ

ꢴꢆꢌꢐꢉꢊꢊꢅꢸꢃꢋꢏꢘ

ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢸꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ

ꢬꢕꢕꢏꢅꢳꢌꢄꢜꢏꢘ

ꢬꢕꢕꢏꢡꢐꢃꢄꢏ

ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

ꢬꢕꢕꢏꢅꢦꢄꢜꢊꢌ

ꢦ

ꢶ

ꢀꢁꢺꢨ

ꢶ

ꢺꢁꢹꢣ

ꢨꢁꢞꢣ

ꢀꢣꢁꢙꢣ

ꢣꢁꢺꢨ

ꢀꢁꢙꢨꢅꢼꢠꢬ

ꢶ

ꢙꢁꢣꢣ

ꢀꢁꢹꢨ

ꢶ

ꢹꢁꢙꢣ

ꢨꢁꢻꢣ

ꢀꢣꢁꢨꢣ

ꢣꢁꢷꢨ

ꢦꢙ

ꢦꢀ

ꢠ

ꢠꢀ

ꢟ

ꢳ

ꢳꢀ

ꢖ

ꢀꢁꢻꢨ

ꢣꢁꢣꢨ

ꢺꢁꢥꢣ

ꢨꢁꢣꢣ

ꢷꢁꢷꢣ

ꢣꢁꢨꢨ

ꢣꢁꢣꢷ

ꢣꣀ

ꢣꢁꢙꢨ

ꢹꣀ

ꢀ

ꢥꣀ

ꢳꢌꢉꢋꢅꢸꢃꢋꢏꢘ

ꢔ

ꢣꢁꢙꢙ

ꢶ

ꢣꢁꢞꢹ

ꢝꢙꢋꢄꢊꢞ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ

ꢙꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢣꢁꢙꢣꢅꢑꢑꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ

ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ

ꢩꢛꢝꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ

ꢼꢠꢬꢪ ꢼꢌꢎꢌꢐꢌꢄꢖꢌꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢡꢈꢐꢡꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ

ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢺꢞꢩ

DS31037B-page 240

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2011 Microchip Technology Inc.

DS31037B-page 241

PIC24F16KL402 FAMILY

20-Lead Plastic Quad Flat, No Lead Package (MQ) 5x5x0.9 mm Body [QFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Microchip Technology Drawing C04-120A

DS31037B-page 242

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2011 Microchip Technology Inc.

DS31037B-page 243

PIC24F16KL402 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS31037B-page 244

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2011 Microchip Technology Inc.

DS31037B-page 245

PIC24F16KL402 FAMILY

28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5 mm Body [QFN] Land Pattern

With 0.55 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Microchip Technology Drawing C04-2140A

DS31037B-page 246

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

ꢟꢠꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢬꢏꢅꢆꢇꢭꢉꢅꢋꢥꢇꢝꢙꢇꢃꢄꢅꢆꢇꢈꢅꢍꢢꢅꢮꢄꢇꢒꢯꢃꢓꢇꢔꢇꢰꢱꢰꢇꢗꢗꢇꢘꢙꢆꢚꢇꢛꢬꢭꢝꢜ

ꢲꢌꢋꢪꢇꢖꢧꢨꢨꢇꢗꢗꢇꢩꢙꢑꢋꢅꢍꢋꢇꢃꢄꢑꢮꢋꢪ

ꢝꢙꢋꢄꢞ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ

D

D2

EXPOSED

PAD

e

E

b

E2

2

1

2

1

K

N

NOTE 1

L

BOTTOM VIEW

TOP VIEW

A

A3

A1

ꢯꢄꢃꢏꢇꢢꢰꢳꢳꢰꢢꢠꢫꢠꢼꢛ

ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ

ꢢꢰꢱ

ꢱꢴꢢ

ꢢꢦꢵ

ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇꢱ

ꢂꢃꢏꢖꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢲꢌꢃꢜꢘꢏ

ꢛꢏꢉꢄꢋꢕꢎꢎꢅ

ꢝꢕꢄꢏꢉꢖꢏꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ

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 2011 Microchip Technology Inc.

DS31037B-page 247

PIC24F16KL402 FAMILY

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DS31037B-page 248

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

APPENDIX A: REVISION HISTORY

Revision A (September 2011)

APPENDIX B: MIGRATING FROM

PIC18/PIC24 TO

PIC24F16KL402

Original data sheet for the PIC24F16KL402 family of

devices.

The PIC24F16KL402 family combines traditional

PIC18 peripherals with a faster PIC24 core to provide

a low-cost, high-performance microcontroller with

low-power consumption.

Revision B (November 2011)

Code written for PIC18 devices can be migrated to the

PIC24F16KL402 by using a C compiler that generates

PIC24 machine level instructions. Assembly language

code will need to be rewritten using PIC24 instructions.

The PIC24 instruction set shares similarities to the

PIC18 instruction set, which should ease porting of

assembly code. Application code will require changes

to support certain PIC24 peripherals.

Updates DC Specifications in Tables 26-6 through 26-9

(all Typical and Maximum values).

Updates AC Specifications in Tables 26-7 through

26-30 (SPI Timing Requirements) with the addition of

the FSCK specification.

Other minor typographic corrections throughout.

Code written for PIC24 devices can be migrated to the

PIC24F16KL402 without many code changes. Certain

peripherals, however, will require application changes

to support modules that were traditionally available

only on PIC18 devices.

Refer to Table B-1 for a list of peripheral modules on

the PIC24F16KL402 and where they originated from.

TABLE B-1:

TABLE B-1: PIC24F16KL402

PERIPHERAL MODULE

ORIGINATING

ARCHITECTURE

Peripheral Module

PIC18

PIC24

ECCP/CCP

X

—

X

MSSP (I²C™/SPI)

Timer2/4 (8-bit)

Timer3 (16-bit)

Timer1 (16-bit)

10-Bit A/D Converter

Comparator

X

—

X

Comparator Voltage

Reference

X

UART

HLVD

—

X

 2011 Microchip Technology Inc.

DS31037B-page 249

PIC24F16KL402 FAMILY

NOTES:

DS31037B-page 250

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

INDEX

Code Examples

A

Data EEPROM Bulk Erase......................................... 59

Data EEPROM Unlock Sequence .............................. 55

Erasing a Program Memory Row,

‘C’ Language Code............................................. 53

Erasing a Program Memory Row,

Assembly Language Code ................................. 52

I/O Port Write/Read .................................................. 116

Initiating a Programming Sequence,

‘C’ Language Code............................................. 54

Initiating a Programming Sequence,

Assembly Language Code ................................. 54

Loading the Write Buffers, ‘C’ Language Code .......... 54

Loading the Write Buffers, Assembly

Language Code.................................................. 53

PWRSAV Instruction Syntax .................................... 107

Reading the Data EEPROM Using the

A/D

10-Bit High-Speed A/D Converter............................. 159

Conversion Timing Requirements............................. 225

Module Specifications............................................... 224

A/D Converter

Analog Input Model................................................... 166

Transfer Function...................................................... 167

AC Characteristics

Capacitive Loading Requirements on

Output Pins....................................................... 210

Internal RC Accuracy................................................ 212

Internal RC Oscillator Specifications......................... 212

Load Conditions and Requirements.......................... 210

Temperature and Voltage Specifications.................. 210

Assembler

MPASM Assembler................................................... 190

TBLRD Command .............................................. 60

Sequence for Clock Switching.................................. 104

Single-Word Erase ..................................................... 58

Single-Word Write to Data EEPROM ......................... 59

Ultra Low-Power Wake-up Initialization.................... 109

Code Protection................................................................ 187

Comparator....................................................................... 169

Comparator Voltage Reference........................................ 173

Configuring ............................................................... 173

Configuration Bits ............................................................. 177

Core Features..................................................................... 11

CPU

ALU............................................................................. 31

Control Registers........................................................ 30

Core Registers............................................................ 28

Programmer’s Model .................................................. 27

Customer Change Notification Service............................. 257

Customer Notification Service .......................................... 257

Customer Support............................................................. 257

B

Block Diagrams

10-Bit High-Speed A/D Converter............................. 160

16-Bit Timer1 ............................................................ 117

Accessing Program Memory with

Table Instructions ............................................... 47

CALL Stack Frame...................................................... 45

Capture Mode Operation .......................................... 128

Comparator Module .................................................. 169

Comparator Voltage Reference ................................ 173

Compare Mode Operation ........................................ 128

CPU Programmer’s Model.......................................... 29

Data Access From Program Space

Address Generation............................................ 46

Data EEPROM Addressing with TBLPAG

and NVM Registers............................................. 57

Enhanced PWM Mode.............................................. 129

High/Low-Voltage Detect (HLVD) ............................. 175

Individual Comparator Configurations....................... 170

D

2

MSSP (I C Master Mode) ......................................... 139

Data EEPROM Memory...................................................... 55

Erasing ....................................................................... 58

Operations.................................................................. 57

Programming

2

MSSP (I C Mode) ..................................................... 139

MSSP (SPI Mode)..................................................... 138

PIC24F CPU Core ...................................................... 28

PIC24F16KL402 Family (General).............................. 15

PSV Operation............................................................ 48

PWM Operation (Simplified) ..................................... 128

Reset System.............................................................. 61

Serial Resistor........................................................... 109

Shared I/O Port Structure ......................................... 113

Simplified UART........................................................ 151

SPI Master/Slave Connection................................... 138

System Clock.............................................................. 97

Table Register Addressing.......................................... 49

Timer2....................................................................... 119

Timer3....................................................................... 121

Timer4....................................................................... 125

Watchdog Timer (WDT)............................................ 186

Bulk Erase .......................................................... 59

Reading Data EEPROM..................................... 60

Single-Word Write .............................................. 59

Programming Control Registers

NVMADR(U)....................................................... 57

NVMCON............................................................ 55

NVMKEY ............................................................ 55

Data Memory

Address Space ........................................................... 35

Memory Map............................................................... 35

Near Data Space........................................................ 36

Organization ............................................................... 36

SFR Space ................................................................. 36

Software Stack ........................................................... 45

Space Width ............................................................... 35

C

C Compilers

MPLAB C18 .............................................................. 190

Capture/Compare/PWM (CCP)......................................... 127

CCP/ECCP

CCP I/O Pins............................................................. 127

Timer Selection......................................................... 127

 2011 Microchip Technology Inc.

DS31037B-page 251

PIC24F16KL402 FAMILY

DC Characteristics

Interrupt Sources

TMR3 Overflow......................................................... 121

TMR4 to PR4 Match (PWM)..................................... 125

Interrupts

BOR Trip Points........................................................204

Comparator ...............................................................209

Comparator Voltage Reference ................................209

Data EEPROM Memory............................................209

High/Low-Voltage Detect ..........................................204

I/O Pin Input Specifications.......................................207

I/O Pin Output Specifications....................................208

Idle Current (IIDLE) ....................................................205

Operating Current (IDD).............................................205

Power-Down Current (IPD) ........................................206

Program Memory ......................................................208

Temperature and Voltage Specifications..................203

Alternate Interrupt Vector Table (AIVT) ...................... 67

Control and Status Registers...................................... 70

Implemented Vectors.................................................. 69

Interrupt Vector Table (IVT)........................................ 67

Reset Sequence ......................................................... 67

Setup Procedures....................................................... 96

Trap Vectors............................................................... 69

Vector Table ............................................................... 68

M

Development Support .......................................................189

Device Features for PIC24F16KL20X/10X

Family (Summary).......................................................14

Device Features for PIC24F16KL40X/30X

Master Synchronous Serial Port (MSSP) ......................... 137

Microchip Internet Web Site.............................................. 257

MPLAB ASM30 Assembler, Linker, Librarian................... 190

MPLAB Integrated Development

Family (Summary).......................................................13

Environment Software .............................................. 189

MPLAB PM3 Device Programmer .................................... 192

MPLAB REAL ICE In-Circuit Emulator System ................ 191

MPLINK Object Linker/MPLIB Object Librarian................ 190

E

Electrical Characteristics

Absolute Maximum Ratings ......................................201

Thermal Operating Conditions..................................202

Thermal Packaging Characteristics ..........................202

V/F Graphs................................................................202

Enhanced CCP .................................................................127

Equations

A/D Conversion Clock Period ...................................166

UART Baud Rate with BRGH = 0 .............................152

UART Baud Rate with BRGH = 1 .............................152

Errata ....................................................................................9

Examples

N

Near Data Space ................................................................ 36

O

Oscillator Configuration

Clock Switching ........................................................ 103

Sequence ......................................................... 103

Configuration Bit Values for Clock Selection .............. 98

CPU Clocking Scheme ............................................... 98

Initial Configuration on POR ....................................... 98

Reference Clock Output ........................................... 104

Oscillator, Timer3.............................................................. 121

Baud Rate Error Calculation (BRGH = 0) .................152

F

Flash Program Memory

P

Control Registers ........................................................50

Enhanced ICSP Operation..........................................50

Programming Algorithm ..............................................52

Programming Operations............................................50

RTSP Operation..........................................................50

Table Instructions........................................................49

Packaging

Details....................................................................... 230

Marking..................................................................... 227

Pinout Descriptions for PIC24F16KL20X/10X Family......... 20

Pinout Descriptions for PIC24F16KL40X/30X Family......... 16

Power-Saving ................................................................... 111

Power-Saving Features .................................................... 107

Clock Frequency, Clock Switching ........................... 107

Coincident Interrupts................................................. 108

Instruction-Based Modes.......................................... 107

Idle.................................................................... 108

Sleep ................................................................ 108

Selective Peripheral Control ..................................... 111

Ultra Low-Power Wake-up (ULPWU) ....................... 109

Product Identification System ........................................... 259

Program and Data Memory

G

Getting Started Guidelines for 16-Bit MCUs .......................23

H

High/Low-Voltage Detect (HLVD) .....................................175

I

I/O Ports

Analog Port Configuration.........................................114

Analog Selection Registers.......................................114

Input Change Notification..........................................116

Open-Drain Configuration .........................................114

Parallel (PIO) ............................................................113

In-Circuit Debugger...........................................................187

In-Circuit Serial Programming (ICSP) ...............................187

Instruction Set

Access Using Table Instructions................................. 47

Program Space Visibility............................................. 48

Program and Data Memory Spaces

Addressing.................................................................. 45

Interfacing................................................................... 45

Program Memory

Opcode Symbols.......................................................194

Overview ...................................................................195

Summary...................................................................193

Address Space ........................................................... 33

Device Configuration Words....................................... 34

Hard Memory Vectors................................................. 34

Memory Map............................................................... 33

Organization ............................................................... 34

2

Inter-Integrated Circuit. See I C.

Internet Address................................................................257

DS31037B-page 252

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

Program Verification ......................................................... 187

PWM (CCP Module)

IFS3 (Interrupt Flag Status 3)..................................... 77

IFS4 (Interrupt Flag Status 4)..................................... 78

IFS5 (Interrupt Flag Status 5)..................................... 78

INTCON 2 (Interrupt Control 2) .................................. 74

INTCON1 (Interrupt Control 1) ................................... 73

INTTREG (Interrupt Control and Status) .................... 95

IPC0 (Interrupt Priority Control 0)............................... 83

IPC1 (Interrupt Priority Control 1)............................... 84

IPC12 (Interrupt Priority Control 12)........................... 92

IPC16 (Interrupt Priority Control 16)........................... 93

IPC18 (Interrupt Priority Control 18)........................... 94

IPC2 (Interrupt Priority Control 2)............................... 85

IPC20 (Interrupt Priority Control 20)........................... 94

IPC3 (Interrupt Priority Control 3)............................... 86

IPC4 (Interrupt Priority Control 4)............................... 87

IPC5 (Interrupt Priority Control 5)............................... 88

IPC6 (Interrupt Priority Control 6)............................... 89

IPC7 (Interrupt Priority Control 7)............................... 90

IPC9 (Interrupt Priority Control 9)............................... 91

NVMCON (Flash Memory Control)............................. 51

NVMCON (Nonvolatile Memory Control).................... 56

OSCCON (Oscillator Control)..................................... 99

OSCTUN (FRC Oscillator Tune) .............................. 102

PADCFG1 (Pad Configuration Control).................... 149

PSTR1CON (ECCP Pulse Steering) ........................ 134

RCON (Reset Control)................................................ 62

REFOCON (Reference Oscillator Control)............... 105

SR (ALU STATUS)............................................... 30, 71

SSPxADD (MSSPx Slave Address/Baud

TMR4 to PR4 Match ................................................. 125

R

Reader Response............................................................. 258

Register Maps

A/D Converter ............................................................. 43

Analog Select.............................................................. 43

CCP/ECCP ................................................................. 40

Comparator................................................................. 43

CPU Core.................................................................... 37

ICN.............................................................................. 38

Interrupt Controller...................................................... 39

MSSP.......................................................................... 41

NVM............................................................................ 44

Pad Configuration ....................................................... 42

PMD............................................................................ 44

PORTA........................................................................ 42

PORTB........................................................................ 42

System, Clock Control ................................................ 44

Timer........................................................................... 40

UART .......................................................................... 41

Ultra Low-Power Wake-up.......................................... 44

Registers

AD1CHS (A/D Input Select)...................................... 164

AD1CON1 (A/D Control 1)........................................ 161

AD1CON2 (A/D Control 2)........................................ 162

AD1CON3 (A/D Control 3)........................................ 163

AD1CSSL (A/D Input Scan Select, Low) .................. 165

ANCFG (Analog Input Configuration) ....................... 165

ANSA (Analog Selection, PORTA) ........................... 115

ANSB (Analog Selection, PORTB) ........................... 115

CCP1CON

Enhanced (ECCP1) .......................................... 131

CCPTMRS0 (CCP Timer Select).............................. 135

CCPxCON

Standard CCP................................................... 130

CLKDIV (Clock Divider) ............................................ 101

CMSTAT (Comparator Status).................................. 172

CMxCON (Comparator x Control)............................. 171

CORCON (CPU Control) ............................................ 31

CORCON (CPU Core Control).................................... 72

CVRCON (Comparator Voltage

Reference Control) ........................................... 174

DEVID (Device ID).................................................... 184

DEVREV (Device Revision)...................................... 185

ECCP1AS (ECCP1 Auto-Shutdown Control)............ 132

ECCP1DEL (ECCP1 Enhanced PWM Control)........ 133

FBS (Boot Segment Configuration) .......................... 178

FGS (General Segment Configuration)..................... 178

FICD (In-Circuit Debugger Configuration)................. 183

FOSC (Oscillator Configuration) ............................... 180

FOSCSEL (Oscillator Selection Configuration)......... 179

FPOR (Reset Configuration)..................................... 182

FWDT (Watchdog Timer Configuration) ................... 181

HLVDCON (High/Low-Voltage Detect Control)......... 176

IEC0 (Interrupt Enable Control 0) ............................... 79

IEC1 (Interrupt Enable Control 1) ............................... 80

IEC2 (Interrupt Enable Control 2) ............................... 81

IEC3 (Interrupt Enable Control 3) ............................... 81

IEC4 (Interrupt Enable Control 4) ............................... 82

IEC5 (Interrupt Enable Control 5) ............................... 82

IFS0 (Interrupt Flag Status 0) ..................................... 75

IFS1 (Interrupt Flag Status 1) ..................................... 76

IFS2 (Interrupt Flag Status 2) ..................................... 77

Rate Generator)................................................ 148

SSPxCON1 (MSSPx Control 1)

2

I C mode .......................................................... 144

SPI mode.......................................................... 143

SSPxCON2 (MSSPx Control 2)................................ 145

SSPxCON3 (MSSPx Control 3)

2

I C mode .......................................................... 147

SPI mode.......................................................... 146

2

SSPxMSK (I C Slave Address Mask) ...................... 148

SSPxSTAT (MSSPx Status)

2

I C Mode .......................................................... 141

SPI mode.......................................................... 140

T1CON (Timer1 Control) .......................................... 118

T2CON (Timer2 Control) .......................................... 120

T3GCON (Timer3 Gate Control)............................... 123

T4CON (Timer4 Control) .......................................... 126

ULPWCON (ULPWU Control) .................................. 110

UxMODE (UARTx Mode) ......................................... 154

UxSTA (UARTx Status and Control) ........................ 156

Resets

Brown-out Reset (BOR).............................................. 65

Clock Source Selection .............................................. 63

Delay Times................................................................ 64

Device Times.............................................................. 64

RCON Flag Operation ................................................ 63

SFR States ................................................................. 65

Revision History................................................................ 251

S

Serial Peripheral Interface. See SPI Mode.

SFR Space ......................................................................... 36

Software Simulator (MPLAB SIM) .................................... 191

Software Stack ................................................................... 45

 2011 Microchip Technology Inc.

DS31037B-page 253

PIC24F16KL402 FAMILY

T

U

Timer1...............................................................................117

Timer2...............................................................................119

Timer3...............................................................................121

Oscillator...................................................................121

Overflow Interrupt .....................................................121

Timer4...............................................................................125

PR4 Register.............................................................125

TMR4 Register..........................................................125

TMR4 to PR4 Match Interrupt ...................................125

Timing Diagrams

UART................................................................................ 151

Baud Rate Generator (BRG) .................................... 152

Break and Sync Transmit Sequence ........................ 153

IrDA Support............................................................. 153

Operation of UxCTS and UxRTS Control Pins ......... 153

Receiving in 8-Bit or 9-Bit Data Mode....................... 153

Transmitting in 8-Bit Data Mode ............................... 153

Transmitting in 9-Bit Data Mode ............................... 153

W

Watchdog Timer (WDT).................................................... 186

Windowed Operation ................................................ 186

WWW Address ................................................................. 257

WWW, On-Line Support ....................................................... 9

Capture/Compare/PWM (ECCP1, ECCP2) ..............215

CLKO and I/O Timing................................................213

Example SPI Master Mode (CKE = 0) ......................216

Example SPI Master Mode (CKE = 1) ......................217

Example SPI Slave Mode (CKE = 0) ........................218

Example SPI Slave Mode (CKE = 1) ........................219

External Clock...........................................................211

2

I C Bus Data.............................................................220

2

I C Bus Start/Stop Bits..............................................220

2

MSSP I C Bus Data..................................................222

2

MSSP I C Bus Start/Stop Bits ..................................222

Timing Requirements

Capture/Compare/PWM (ECCP1, ECCP2) ..............215

CLKO and I/O ...........................................................213

Comparator ...............................................................214

Comparator Voltage Reference Settling Time ..........214

External Clock...........................................................211

2

I C Bus Data (Slave Mode).......................................221

2

I C Bus Data Requirements (Master Mode) .............223

2

I C Bus Start/Stop Bits (Master Mode) .....................222

2

I C Bus Start/Stop Bits (Slave Mode) .......................220

PLL Clock Specifications ..........................................212

SPI Mode (Master Mode, CKE = 0) ..........................216

SPI Mode (Master Mode, CKE = 1) ..........................217

SPI Slave Mode (CKE = 1) .......................................219

Timing Requirements SPI Mode

(Slave Mode, CKE = 0) .............................................218

DS31037B-page 254

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://microchip.com/support

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the

registration instructions.

 2011 Microchip Technology Inc.

DS31037B-page 255

PIC24F16KL402 FAMILY

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip

product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our

documentation can better serve you, please FAX your comments to the Technical Publications Manager at

(480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

TO:

RE:

Technical Publications Manager

Reader Response

Total Pages Sent ________

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Literature Number: DS31037B

Application (optional):

Would you like a reply?

Y

N

Device: PIC24F16KL402 Family

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS31037B-page 256

 2011 Microchip Technology Inc.

PIC24F16KL402 FAMILY

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PIC 24 F 16 KL4 02 T - I / PT - XXX

a)

b)

PIC24F16KL402-I/ML: General Purpose,

16-Kbyte program memory, 28-pin, Industrial

temp, QFN package

Microchip Trademark

Architecture

PIC24F04KL101T-I/SS: General Purpose,

4-Kbyte program memory, 20-pin, Industrial

temp, SSOP package, tape-and-reel

Flash Memory Family

Program Memory Size (KB)

Product Group

Pin Count

Tape and Reel Flag (if applicable)

Temperature Range

Package

Pattern

Architecture

24 = 16-bit modified Harvard without DSP

Flash Memory Family

Product Group

F

= Standard voltage range Flash program memory

KL4 = General purpose microcontrollers

KL3

KL2

KL1

Pin Count

00 = 14-pin

01 = 20-pin

02 = 28-pin

Temperature Range

Package

I

= -40C to +85C (Industrial)

SP

SO

SS

ST

ML, MQ

P

=

SPDIP

SOIC

SSOP

TSSOP

QFN

PDIP

Pattern

Three-digit QTP, SQTP, Code or Special Requirements

(blank otherwise)

ES = Engineering Sample

 2011 Microchip Technology Inc.

DS31037B-page 257

PIC24F16KL402 FAMILY

NOTES:

DS31037B-page 258

 2011 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-811-6

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

 2011 Microchip Technology Inc.

DS31037B-page 259

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hangzhou

Tel: 86-571-2819-3187

Fax: 86-571-2819-3189

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-330-9305

Los Angeles

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Toronto

Mississauga, Ontario,

Canada

China - Xiamen

Tel: 905-673-0699

Fax: 905-673-6509

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

08/02/11

DS31037B-page 260

 2011 Microchip Technology Inc.


型号：	PIC24F08KL402
厂家：	MICROCHIP
描述：	Low-Power, Low-Cost, General Purpose 16-Bit Flash Microcontrollers with nanoWatt XLP Technology 低功耗，低成本，通用16位闪存微控制器采用nanoWatt XLP技术闪存微控制器
文件：	总260页 (文件大小：3191K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC24F08KL402 [MICROCHIP]

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PIC24F08KL402-I/SS

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PIC24F16KA101-E/P

PIC24F16KA101-E/SS

PIC24F16KA101-I/ML

PIC24F16KA101-I/MQ

PIC24F16KA101-I/P

PIC24F16KA101-I/SO

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