PIC24FJ128_技术文档

PIC24FJ128GA Family

Data Sheet

General Purpose,

16-Bit Flash Microcontrollers

Preliminary

DS39747C

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

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•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

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dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC and SmartShunt are

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Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi,

MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM,

PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,

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Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,

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Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

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Company’s quality system processes and procedures are for its

PICmicro^®8-bit MCUs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS39747C-page ii

Preliminary

PIC24FJ128GA FAMILY

General Purpose, 16-bit Flash Microcontrollers

High-Performance CPU:

Analog Features:

• Modified Harvard Architecture

• Up to 16 MIPS operation @ 32 MHz

• 8 MHz internal oscillator:

• 10-bit, up to 16-channel Analog-to-Digital Converter

(A/D):

- 500 ksps conversion rate

- 4x PLL option

- Multiple divide options

• 17-bit x 17-bit Single-Cycle Hardware

Fractional/Integer Multiplier

- Conversion available during Sleep and Idle

• Dual Analog Comparators with Programmable

Input/Output Configuration

• 32-bit by 16-bit Hardware Divider

• 16 x 16-bit Working Register Array

• C compiler Optimized Instruction Set Architecture:

- 76 base instructions

Peripheral Features:

• Two 3-wire/4-wire SPI modules, supporting 4 Frame

modes with 4-level FIFO Buffer

2

• Two I C™ modules support Multi-Master/Slave

- Flexible addressing modes

mode and 7-bit/10-bit Addressing

• Two UART modules:

- Supports RS-232, RS-485 and LIN 1.2

- Supports IrDA^®with on-chip hardware endec

- Auto-Wake-up on Start bit

• Linear Program Memory Addressing up to 12 Mbytes

• Linear Data Memory Addressing up to 64 Kbytes

• Two Address Generation Units for separate Read

and Write Addressing of Data Memory

- Auto-Baud Detect

- 4-level FIFO buffer

Special Microcontroller Features:

• Operating Voltage Range of 2.0V to 3.6V

• Flash Program Memory:

• Parallel Master Slave Port (PMP/PSP):

- Supports 8-bit or 16-bit data

- 1000 erase/write cycles, typical

- Supports 16 address lines

- Flash retention 20 years, typical

• Hardware Real-Time Clock/Calendar (RTCC):

- Provides clock, calendar and alarm functions

• Five 16-bit Timers/Counters with Programmable

prescaler

• Self-Reprogrammable under Software Control

• Selectable Power Management modes:

- Sleep, Idle and Alternate Clock modes

• Fail-Safe Clock Monitor operation:

- Detects clock failure and switches to on-chip,

low-power RC oscillator

• Five 16-bit Capture Inputs

• Five 16-bit Compare/PWM Outputs

• High-Current Sink/Source on select I/O pins:

18 mA/18 mA

• On-Chip LDO Regulator

• JTAG Boundary Scan and Programming Support

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Configurable Open-Drain Output on Digital I/O pins

• Up to 5 External Interrupt Sources

• Flexible Watchdog Timer (WDT) with On-Chip,

Low-Power RC Oscillator for reliable operation

• In-Circuit Serial Programming™ (ICSP™) and

In-Circuit Emulation (ICE) via 2 pins

Program

Pins Memory

(Bytes)

SRAM

(Bytes)

Timers

16-bit

10-bit

A/D (ch)

Device

SPI

I²C™

PIC24FJ64GA006

PIC24FJ96GA006

PIC24FJ128GA006

PIC24FJ64GA008

PIC24FJ96GA008

PIC24FJ128GA008

PIC24FJ64GA010

PIC24FJ96GA010

PIC24FJ128GA010

64

64K

96K

8K

5

2

16

2

Y

64

128K

64K

80

96K

80

128K

64K

100

96K

128K

Preliminary

DS39747C-page 1

PIC24FJ128GA FAMILY

Pin Diagrams

64-Pin TQFP

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

SOSCO/T1CK/CN0/RC14

SOSCI/CN1/RC13

OC1/RD0

1

PMD5/RE5

PMD6/RE6

2

PMD7/RE7

3

IC4/PMCS1/INT4/RD11

IC3/PMCS2/INT3/RD10

IC2/U1CTS//INT2/RD9

IC1/RTCC/INT1/RD8

Vss

PMA5/SCK2/CN8/RG6

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

4

5

6

MCLR

PMA2/SS2/CN11/RG9

VSS

7

PIC24FJXXGA006

PIC24FJXXXGA006

8

OSC2/CLKO/RC15

OSC1/CLKI/RC12

VDD

9

VDD

10

11

12

13

14

15

16

C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/RB4

SCL1/RG2

C2IN+/AN3/CN5/RB3

SDA1/RG3

U1RTS/BCLK1/SCK1/INT0/RF6

U1RX/SDI1/RF2

U1TX/SDO1/RF3

C2IN-/AN2/SS1/CN4/RB2

PGC1/EMUC1/VREF-/AN1/CN3/RB1

PGD1/EMUD1/PMA6/VREF+/AN0/CN2/RB0

DS39747C-page 2

Preliminary

PIC24FJ128GA FAMILY

Pin Diagrams (Continued)

80-Pin TQFP

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

SOSCO/T1CK/CN0/RC14

SOSCI/CN1/RC13

OC1/RD0

1

PMD5/RE5

PMD6/RE6

2

PMD7/RE7

3

IC4/PMCS1/RD11

IC3/PMCS2/RD10

IC2/RD9

T2CK/RC1

4

T4CK/RC3

5

PMA5/SCK2/CN8/RG6

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

MCLR

6

IC1/RTCC/RD8

SDA2/INT4/RA15

SCL2/INT3/RA14

7

8

9

VSS

PMA2/SS2/CN11/RG9

VSS

10

11

12

13

14

15

16

17

18

19

20

PIC24FJXXGA008

PIC24FJXXXGA008

OSC2/CLKO/RC15

OSC1/CLKI/RC12

VDD

TMS/INT1/RE8

TDO/INT2/RE9

SCL1/RG2

SDA1/RG3

SCK1/INT0/RF6

SDI1/RF7

C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/RB4

C2IN+/AN3/CN5/RB3

C2IN-/AN2/SS1/CN4/RB2

PGC1/EMUC1/AN1/CN3/RB1

PGD1/EMUD1/AN0/CN2/RB0

SDO1/RF8

U1RX/RF2

U1TX/RF3

Preliminary

DS39747C-page 3

PIC24FJ128GA FAMILY

Pin Diagrams (Continued))

100-Pin TQFP

VSS

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

1

RG15

VDD

PMD5/RE5

SOSCO/T1CK/CN0/RC14

SOSCI/CN1/RC13

OC1/RD0

IC4/PMCS1/RD11

IC3/PMCS2/RD10

IC2/RD9

IC1/RTCC/RD8

INT4/RA15

INT3/RA14

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

PMD6/RE6

PMD7/RE7

T2CK/RC1

T3CK/RC2

T4CK/RC3

T5CK/RC4

PMA5/SCK2/CN8/RG6

PMA4/SDI2/CN9/RG7

PMA3/SDO2/CN10/RG8

MCLR

PMA2/SS2/CN11/RG9

VSS

OSC2/CLKO/RC15

OSC1/CLKI/RC12

VDD

PIC24FJXXGA010

PIC24FJXXXGA010

TDO/RA5

VDD

TMS/RA0

INT1/RE8

INT2/RE9

TDI/RA4

SDA2/RA3

SCL2/RA2

SCL1/RG2

SDA1/RG3

SCK1/INT0/RF6

C1IN+/AN5/CN7/RB5

C1IN-/AN4/CN6/RB4

C2IN+/AN3/CN5/RB3

C2IN-/AN2/SS1/CN4/RB2

PGC1/EMUC1/AN1/CN3/RB1

PGD1/EMUD1/AN0/CN2/RB0

SDI1/RF7

SDO1/RF8

U1RX/RF2

U1TX/RF3

DS39747C-page 4

Preliminary

PIC24FJ128GA FAMILY

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 CPU............................................................................................................................................................................................ 19

3.0 Memory Organization................................................................................................................................................................. 25

4.0 Flash Program Memory.............................................................................................................................................................. 45

5.0 Resets ........................................................................................................................................................................................ 51

6.0 Interrupt Controller ..................................................................................................................................................................... 57

7.0 Oscillator Configuration.............................................................................................................................................................. 91

8.0 Power-Saving Features.............................................................................................................................................................. 97

9.0 I/O Ports ..................................................................................................................................................................................... 99

10.0 Timer1 ...................................................................................................................................................................................... 101

11.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 103

12.0 Input Capture............................................................................................................................................................................ 109

13.0 Output Compare....................................................................................................................................................................... 111

14.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 115

15.0 Inter-Integrated Circuit (I²C™) ................................................................................................................................................. 123

16.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 131

17.0 Parallel Master Port.................................................................................................................................................................. 139

18.0 Real-Time Clock and Calendar ................................................................................................................................................ 149

19.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 161

20.0 10-bit High-Speed A/D Converter............................................................................................................................................. 165

21.0 Comparator Module.................................................................................................................................................................. 173

22.0 Comparator Voltage Reference................................................................................................................................................ 177

23.0 Special Features ...................................................................................................................................................................... 179

24.0 Instruction Set Summary.......................................................................................................................................................... 189

25.0 Development Support............................................................................................................................................................... 197

26.0 Electrical Characteristics.......................................................................................................................................................... 201

27.0 Packaging Information.............................................................................................................................................................. 213

Appendix A: Revision History............................................................................................................................................................. 219

Index ................................................................................................................................................................................................. 221

The Microchip Web Site..................................................................................................................................................................... 225

Customer Change Notification Service.............................................................................................................................................. 225

Customer Support.............................................................................................................................................................................. 225

Reader Response.............................................................................................................................................................................. 226

Product Identification System ............................................................................................................................................................ 227

Preliminary

DS39747C-page 5

PIC24FJ128GA FAMILY

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We

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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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DS39747C-page 6

Preliminary

PIC24FJ128GA FAMILY

1.1.2

POWER-SAVING TECHNOLOGY

1.0

DEVICE OVERVIEW

All of the devices in the PIC24FJ128GA family incorpo-

rate a range of features that can significantly reduce

power consumption during operation. Key items

include:

This document contains device specific information for

the following devices:

• PIC24FJ64GA006

• PIC24FJ64GA008

• PIC24FJ64GA010

• PIC24FJ96GA006

• PIC24FJ96GA008

• PIC24FJ96GA010

• PIC24FJ128GA006

• PIC24FJ128GA008

• PIC24FJ128GA010

• On-the-Fly Clock Switching: The device clock

can be changed under software control to the

Timer1 source or the internal low-power RC

oscillator during operation, allowing the user to

incorporate power-saving ideas into their software

designs.

• Doze Mode Operation: When timing-sensitive

applications, such as serial communications,

require the uninterrupted operation of peripherals,

the CPU clock speed can be selectively reduced,

allowing incremental power savings without

missing a beat.

This family introduces a new line of Microchip devices:

a 16-bit RISC microcontroller family with a broad

peripheral feature set and enhanced computational

performance. The PIC24FJ128GA family offers a new

migration option for those high-performance applica-

tions which may be outgrowing their 8-bit platforms, but

don’t require the numerical processing power of a

digital signal processor.

• Instruction-Based Power-Saving Modes: The

microcontroller can suspend all operations, or

selectively shut down its core while leaving its

peripherals active, with a single instruction in

software.

1.1.3

OSCILLATOR OPTIONS AND

FEATURES

1.1

Core Features

1.1.1

16-BIT ARCHITECTURE

All of the devices in the PIC24FJ128GA family offer five

different oscillator options, allowing users a range of

choices in developing application hardware. These

include:

Central to all PIC24 devices is the 16-bit modified

Harvard architecture, first introduced with Microchip’s

dsPIC^®digital signal controllers. The PIC24 CPU core

offers a wide range of enhancements, such as:

• Two Crystal modes, using crystals or ceramic

resonators.

• 16-bit data and 24-bit address paths, with the

ability to move information between data and

memory spaces

• Two External Clock modes, offering the option of

a divide-by-2 clock output.

• Linear addressing of up to 8 Mbytes (program

space) and 64 Kbytes (data)

• A Fast Internal Oscillator (FRC) with a nominal

8 MHz output, which can also be divided under

software control to provide clock speeds as low as

31 kHz.

• A 16-element working register array with built-in

software stack support

• A 17 x 17 hardware multiplier with support for

integer math

• A Phase Lock Loop (PLL) frequency multiplier,

available to the external oscillator modes and the

FRC oscillator, which allows clock speeds of up to

32 MHz.

• Hardware support for 32 by 16-bit division

• An instruction set that supports multiple

addressing modes and is optimized for high-level

languages such as ‘C’

• A separate internal RC oscillator (LPRC) with a

fixed 31 kHz output, which provides a low-power

option for timing-insensitive applications.

• Operational performance up to 16 MIPS

The internal oscillator block also provides a stable ref-

erence source for the Fail-Safe Clock Monitor. This

option constantly monitors the main clock source

against a reference signal provided by the internal

oscillator and enables the controller to switch to the

internal oscillator, allowing for continued low-speed

operation or a safe application shutdown.

Preliminary

DS39747C-page 7

PIC24FJ128GA FAMILY

1.1.4

EASY MIGRATION

1.3

Details on Individual Family

Members

Regardless of the memory size, all devices share the

same rich set of peripherals, allowing for a smooth

migration path as applications grow and evolve.

Devices in the PIC24FJ128GA family are available in

64-pin, 80-pin and 100-pin packages. The general

block diagram for all devices is shown in Figure 1-1.

The consistent pinout scheme used throughout the

entire family also aids in migrating to the next larger

device. This is true when moving between devices with

the same pin count, or even jumping from 64-pin to

80-pin to 100-pin devices.

The devices are differentiated from each other in two

ways:

1. Flash program memory (64 Kbytes for

PIC24FJ64GA devices, 96 Kbytes for

PIC24FJ96GA devices and 128 Kbytes for

PIC24FJ128GA devices).

The PIC24 family is pin-compatible with devices in the

dsPIC33 family, and shares some compatibility with the

pinout schema for PIC18 and dsPIC30. This extends

the ability of applications to grow from the relatively

simple to the powerful and complex, yet still select a

Microchip device.

2. Available I/O pins and ports (53 pins on 6 ports

for 64-pin devices, 69 pins on 7 ports for 80-pin

devices and 84 pins on 7 ports for 100-pin

devices).

All other features for devices in this family are identical.

These are summarized in Table 1-1.

1.2

Other Special Features

• Communications: The PIC24FJ128GA family

incorporates a range of serial communication

peripherals to handle a range of application

requirements. All devices are equipped with two

independent UARTs with built-in IrDA

encoder/decoders. There are also two indepen-

dent SPI modules, and two independent I²C

modules that support both Master and Slave

modes of operation.

A

list of the pin features available on the

PIC24FJ128GA family devices, sorted by function, is

shown in Table 1-2. Note that this table shows the pin

location of individual peripheral features and not how

they are multiplexed on the same pin. This information

is provided in the pinout diagrams in the beginning of

the data sheet. Multiplexed features are sorted by the

priority given to a feature, with the highest priority

peripheral being listed first.

• Parallel Master/Enhanced Parallel Slave Port:

One of the general purpose I/O ports can be

reconfigured for enhanced parallel data communi-

cations. In this mode, the port can be configured

for both master and slave operations, and

supports 8-bit and 16-bit data transfers with up to

16 external address lines in Master modes.

• Real-Time Clock/Calendar: This module

implements a full-featured clock and calendar with

alarm functions in hardware, freeing up timer

resources and program memory space for use of

the core application.

• 10-Bit A/D Converter: This module incorporates

programmable acquisition time, allowing for a

channel to be selected and a conversion to be

initiated without waiting for a sampling period, as

well as faster sampling speeds.

DS39747C-page 8

Preliminary

PIC24FJ128GA FAMILY

TABLE 1-1:

DEVICE FEATURES FOR THE PIC24FJ128GA FAMILY

Features

Operating Frequency

DC – 32 MHz

96K

Program Memory (Bytes)

64K

96K

128K

64K

128K

64K

96K

128K

Program Memory (Instructions) 22,016 32,768 44,032 22,016 32,768 44,032 22,016 32,768 44,032

Data Memory (Bytes)

8192

Interrupt Sources

43

(Soft Vectors/NMI Traps)

(39/4)

I/O Ports

Ports B, C, D, E, F, G

53

Ports A, B, C, D, E, F, G

69

Ports A, B, C, D, E, F, G

84

Total I/O Pins

Timers:

Total number (16-bit)

32-bit (from paired 16-bit timers)

Input Capture Channels

5

2

5

Output Compare/PWM Chan-

nels

Input Change Notification

Interrupt

19

22

Serial Communications:

Enhanced UART

SPI (3-wire/4-wire)

I²C™

2

Parallel Communications

(PMP/PSP)

Yes

JTAG Boundary Scan

Yes

16

10-bit Analog-to-Digital Module

(input channels)

Analog Comparators

Resets (and Delays)

2

POR, BOR, RESETInstruction, MCLR, WDT; Illegal Opcode,

Repeat Hardware Traps, (PWRT, OST, PLL Lock)

Instruction Set

Packages

76 Base Instructions, Multiple Addressing Mode Variations

64-pin TQFP

80-pin TQFP

100-pin TQFP

Preliminary

DS39747C-page 9

PIC24FJ128GA FAMILY

FIGURE 1-1:

PIC24FJ128GA FAMILY GENERAL BLOCK DIAGRAM

Data Bus

Interrupt

(1)

Controller

PORTA

RA0:RA7,

RA9:RA10,

RA14:15

16

8

Data Latch

Data RAM

PSV & Table

Data Access

Control Block

PCU PCH PCL

Program Counter

PORTB

23

Address

Latch

Repeat

Control

Logic

Stack

Control

Logic

RB0:RB15

16

23

16

(1)

Read AGU

Write AGU

Address Latch

Program Memory

Data Latch

PORTC

RC1:RC4,

RC12:RC15

EA MUX

(1)

Address Bus

24

PORTD

16

RD0:RD15

Inst Latch

Inst Register

(1)

PORTE

Instruction

RE0:RE9

Decode &

Control

Divide

Support

Control Signals

16 x 16

W Reg Array

17x17

Multiplier

(1)

Power-up

Timer

PORTF

Timing

OSC2/CLKO

OSC1/CLKI

Generation

RF0:RF8,

RF12:RF13

Oscillator

Start-up Timer

FRC/LPRC

Oscillators

16-bit ALU

16

Power-on

Reset

Precision

Band Gap

Reference

(1)

Watchdog

Timer

PORTG

ENVREG

Brown-out

Reset

RG0:RG9,

RG12:RG15

Voltage

Regulator

(2)

VDDCORE/VCAP

Timer1

VDD,VSS

MCLR

10-bit

ADC

Timer2/3

Comparators

Timer4/5

RTCC

SPI1/2

PMP/PSP

PWM/

OC1-5

(1)

IC1-5

I2C1/2

CN1-22

UART1/2

Note 1: Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions.

2: BOR functionality is provided when the on-board voltage regulator is enabled.

DS39747C-page 10

Preliminary

PIC24FJ128GA FAMILY

TABLE 1-2:

PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS

Pin Number

Input

Buffer

Function

I/O

Description

64-pin

80-pin

100-pin

AN0

AN1

16

15

14

13

12

11

17

18

21

22

23

24

27

28

29

30

19

20

35

29

12

11

21

14

13

22

39

40

48

47

16

15

14

13

12

11

4

20

19

18

17

16

15

21

22

27

28

29

30

33

34

35

36

25

26

38

35

16

15

27

18

17

28

49

50

60

59

20

19

18

17

16

15

6

25

24

23

22

21

20

26

27

32

33

34

35

41

42

43

44

30

31

48

39

21

20

32

23

22

33

63

64

74

73

25

24

23

22

21

20

10

11

12

14

44

81

82

83

84

49

I

ANA

—

A/D Analog Inputs.

AN2

I

AN3

I

AN4

I

AN5

I

AN6

I

AN7

I

AN8

I

AN9

I

AN10

AN11

AN12

AN13

AN14

AN15

AVDD

AVSS

BCLK1

BCLK2

C1IN-

C1IN+

C1OUT

C2IN-

C2IN+

C2OUT

CLKI

CLKO

CN0

I

P

O

I

Positive Supply for Analog Modules.

Ground Reference for Analog Modules.

UART1 IrDA^®Baud Clock.

UART2 IrDA^®Baud Clock.

Comparator 1 Negative Input.

Comparator 1 Positive Input.

Comparator 1 Output.

—

ANA

—

I

O

I

ANA

—

Comparator 2 Negative Input.

Comparator 2 Positive Input.

Comparator 2 Output.

I

O

I

ANA

—

Main Clock Input Connection.

System Clock Output.

O

I

ST

Interrupt-on-Change Inputs.

CN1

I

ST

CN2

I

ST

CN3

I

ST

CN4

I

ST

CN5

I

ST

CN6

I

ST

CN7

I

ST

CN8

I

ST

CN9

5

7

I

ST

CN10

CN11

CN12

CN13

CN14

CN15

CN16

CN17

6

8

I

ST

8

10

36

66

67

68

69

39

I

ST

30

52

53

54

55

31

I

ST

I

ST

I

ST

I

ST

I

ST

I

ST

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I²C™ = I²C/SMBus input buffer

Preliminary

DS39747C-page 11

PIC24FJ128GA FAMILY

TABLE 1-2:

PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

Function

I/O

Description

Interrupt-on-Change Inputs.

64-pin

80-pin

100-pin

CN18

CN19

CN20

CN21

CVREF

EMUC1

EMUD1

EMUC2

EMUD2

ENVREG

IC1

32

—

23

15

16

17

18

57

42

43

44

45

52

35

42

43

44

45

7

40

65

37

38

29

19

20

21

22

71

54

55

56

57

64

45

13

14

52

53

9

50

80

47

48

34

24

25

26

27

86

68

69

70

71

79

55

18

19

66

67

13

I

ST

ANA

ST

I

O

Comparator Voltage Reference Output.

In-Circuit Emulator Clock Input/Output.

In-Circuit Emulator Data Input/Output.

In-Circuit Emulator Clock Input/Output.

In-Circuit Emulator Data Input/Output.

Enable for On-Chip Voltage Regulator.

Input Capture Inputs.

I/O

I

IC2

IC3

IC4

IC5

INT0

External Interrupt Inputs.

INT1

INT2

INT3

INT4

MCLR

Master Clear (Device Reset) Input. This line is brought

low to cause a Reset.

OC1

OC2

46

49

50

51

52

17

30

39

40

15

16

17

18

58

61

62

63

66

21

36

49

50

19

20

21

22

72

76

77

78

81

26

44

63

64

24

25

26

27

O

—

Output Compare/PWM Outputs.

OC3

O

—

OC4

O

—

OC5

O

—

OCFA

OCFB

OSC1

OSC2

PGC1

PGD1

PGC2

PGD2

I

ST

ANA

ST

Output Compare Fault A Input.

I

Output Compare Fault B Input.

I

Main Oscillator Input Connection.

O

Main Oscillator Output Connection.

I/O

In-Circuit Debugger and ICSP™ Programming Clock

In-Circuit Debugger and ICSP Programming Data.

In-Circuit Debugger and ICSP™ Programming Clock.

In-Circuit Debugger and ICSP Programming Data.

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I²C™ = I²C/SMBus input buffer

DS39747C-page 12

Preliminary

PIC24FJ128GA FAMILY

TABLE 1-2:

PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

80-pin

36

Input

Buffer

Function

I/O

Description

64-pin

100-pin

PMA0

PMA1

30

44

I/O

ST

Parallel Master Port Address Bit 0 Input (Buffered Slave

modes) and Output (Master modes).

29

35

43

Parallel Master Port Address Bit 1 Input (Buffered Slave

modes) and Output (Master modes).

PMA2

PMA3

PMA4

PMA5

PMA6

PMA7

PMA8

PMA9

PMA10

PMA11

PMA12

PMA13

PMBE

PMCS1

PMCS2

PMD0

PMD1

PMD2

PMD3

PMD4

PMD5

PMD6

PMD7

PMRD

PMWR

8

10

8

14

12

11

10

29

28

50

49

42

41

35

34

78

71

70

93

94

98

99

100

3

O

—

ST

—

Parallel Master Port Address (Demultiplexed Master

modes).

6

5

7

O

4

6

O

16

22

32

31

28

27

24

23

51

45

44

60

61

62

63

64

1

24

23

40

39

34

33

30

29

63

57

56

76

77

78

79

80

1

O

Parallel Master Port Byte Enable Strobe.

O

Parallel Master Port Chip Select 1 Strobe/Address bit 14.

Parallel Master Port Chip Select 2 Strobe/Address bit 15.

O

I/O

O

Parallel Master Port Data (Demultiplexed Master mode)

or Address/Data (Multiplexed Master modes).

2

4

3

5

53

52

67

66

82

81

Parallel Master Port Read Strobe.

Parallel Master Port Write Strobe.

O

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I²C™ = I²C/SMBus input buffer

Preliminary

DS39747C-page 13

PIC24FJ128GA FAMILY

TABLE 1-2:

PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

Function

I/O

Description

64-pin

80-pin

100-pin

RA0

RA1

—

16

15

14

13

12

11

17

18

21

22

23

24

27

28

29

30

—

39

47

48

40

—

23

24

52

53

20

19

18

17

16

15

21

22

27

28

29

30

33

34

35

36

4

17

38

58

59

60

61

91

92

28

29

66

67

25

24

23

22

21

20

26

27

32

33

34

35

41

42

43

44

6

I/O

ST

PORTA Digital I/O.

RA2

RA3

RA4

RA5

RA6

RA7

RA9

RA10

RA14

RA15

RB0

PORTB Digital I/O.

RB1

RB2

RB3

RB4

RB5

RB6

RB7

RB8

RB9

RB10

RB11

RB12

RB13

RB14

RB15

RC1

RC2

RC3

RC4

RC12

RC13

RC14

RC15

PORTC Digital I/O.

—

5

7

8

—

49

59

60

50

9

63

73

74

64

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I²C™ = I²C/SMBus input buffer

DS39747C-page 14

Preliminary

PIC24FJ128GA FAMILY

TABLE 1-2:

PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

Function

I/O

Description

64-pin

80-pin

100-pin

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

RD8

RD9

RD10

RD11

RD12

RD13

RD14

RD15

RE0

RE1

RE2

RE3

RE4

RE5

RE6

RE7

RE8

RE9

RF0

RF1

RF2

RF3

RF4

RF5

RF6

RF7

RF8

RF12

RF13

46

49

50

51

52

53

54

55

42

43

44

45

—

60

61

62

63

64

1

58

61

62

63

66

67

68

69

54

55

56

57

64

65

37

38

76

77

78

79

80

1

72

76

77

78

81

82

83

84

68

69

70

71

79

80

47

48

93

94

98

99

100

3

I/O

ST

PORTD Digital I/O.

PORTE Digital I/O.

2

4

3

5

—

58

59

34

33

31

32

35

—

13

14

72

73

42

41

39

40

45

44

43

—

18

19

87

88

52

51

49

50

55

54

53

40

39

PORTF Digital I/O.

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I²C™ = I²C/SMBus input buffer

Preliminary

DS39747C-page 15

PIC24FJ128GA FAMILY

TABLE 1-2:

PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

Function

I/O

Description

64-pin

80-pin

100-pin

RG0

RG1

—

37

36

4

75

74

47

46

6

90

89

57

56

10

11

12

14

96

97

95

1

I/O

O

ST

—

PORTG Digital I/O.

RG2

RG3

RG6

RG7

5

7

RG8

6

8

RG9

8

10

—

54

45

6

RG12

RG13

RG14

RG15

RTCC

SCK1

SCK2

SCL1

SCL2

SDA1

SDA2

SDI1

SDI2

SDO1

SDO2

SOSCI

SOSCO

SS1

—

42

35

4

68

55

10

57

58

56

59

54

11

53

12

73

74

23

14

74

6

Real-Time Clock Alarm Output.

SPI1 Serial Clock Output.

O

—

I/O

I

ST

I²C

ST

—

SPI2 Serial Clock Output.

37

32

36

31

34

5

47

52

46

53

44

7

I2C1 Synchronous Serial Clock Input/Output.

I2C2 Synchronous Serial Clock Input/Output.

I2C1 Data Input/Output.

I2C2 Data Input/Output.

SPI1 Serial Data Input.

I

SPI2 Serial Data Input.

33

6

43

8

O

SPI1 Serial Data Output.

O

—

SPI2 Serial Data Output.

47

48

14

8

59

60

18

10

60

4

I

ANA

ST

—

Secondary Oscillator/Timer1 Clock Input.

Secondary Oscillator/Timer1 Clock Output.

Slave Select Input/Frame Select Output (SPI1).

Slave Select Input/Frame Select Output (SPI2).

Timer1 Clock.

O

I/O

I

SS2

T1CK

T2CK

T3CK

T4CK

T5CK

TCK

48

—

27

28

24

23

I

Timer2 External Clock Input.

—

5

7

I

Timer3 External Clock Input.

8

I

Timer4 External Clock Input.

—

33

34

14

13

9

I

Timer5 External Clock Input.

38

60

61

17

I

JTAG Test Clock/Programming Clock Input.

JTAG Test Data/Programming Data Input.

JTAG Test Data Output.

TDI

I

TDO

O

TMS

I

ST

JTAG Test Mode Select Input.

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I²C™ = I²C/SMBus input buffer

DS39747C-page 16

Preliminary

PIC24FJ128GA FAMILY

TABLE 1-2:

PIC24FJ128GA FAMILY PINOUT DESCRIPTIONS (CONTINUED)

Pin Number

Input

Buffer

Function

I/O

Description

64-pin

80-pin

100-pin

U1CTS

U1RTS

U1RX

U1TX

43

35

34

33

21

29

31

32

37

38

42

41

27

35

39

40

47

48

52

51

40

39

49

50

I

O

I

ST

—

UART1 Clear to Send Input.

UART1 Request to Send Output.

UART1 Receive.

ST

DIG

ST

—

O

I

UART1 Transmit Output.

U2CTS

U2RTS

U2RX

U2TX

VDD

UART2 Clear to Send Input.

UART2 Request to Send Output.

UART 2 Receive Input.

O

I

ST

—

O

P

UART2 Transmit Output.

10, 26, 38 12, 32, 48 2, 16, 37,

46, 62

—

Positive Supply for Peripheral Digital Logic and I/O pins.

VDDCAP

56

70

85

External Filter Capacitor Connection (regulator enabled).

P

—

VDDCORE

Positive Supply for Microcontroller Core Logic (regulator

disabled).

VREF-

VREF+

VSS

15

16

23

24

28

29

I

ANA

—

A/D and Comparator Reference Voltage (Low) Input.

A/D and Comparator Reference Voltage (High) Input.

Ground Reference for Logic and I/O pins.

9, 25, 41

11, 31, 51 15, 36, 45,

65, 75

P

Legend:

TTL = TTL input buffer

ANA = Analog level input/output

ST = Schmitt Trigger input buffer

I²C™ = I²C/SMBus input buffer

Preliminary

DS39747C-page 17

PIC24FJ128GA FAMILY

NOTES:

DS39747C-page 18

Preliminary

PIC24FJ128GA FAMILY

For most instructions, the core is capable of executing

a data (or program data) memory read, a working reg-

ister (data) read, a data memory write and a program

(instruction) memory read per instruction cycle. As a

result, three-parameter instructions can be supported,

allowing trinary operations (that is, A + B = C) to be

executed in a single cycle.

2.0

CPU

The PIC24 CPU has a 16-bit (data) modified Harvard

architecture with an enhanced instruction set, and a

23-bit instruction word with a variable length opcode

field. The Program Counter (PC) is 24 bits wide and

addresses up to 4M instructions of user program

memory space. A single-cycle instruction prefetch

mechanism is used to help maintain throughput and

provides predictable execution. All instructions execute

in a single cycle, with the exception of instructions that

change the program flow, the double-word move

(MOV.D) instruction and the table instructions. Over-

head-free program loop constructs are supported using

the REPEATinstructions, which are interruptible at any

point.

A high-speed 17-bit by 17-bit multiplier has been

included to significantly enhance the core arithmetic

capability and throughput. The multiplier supports

signed, unsigned and mixed mode 16-bit by 16-bit or

8-bit by 8-bit integer multiplication. All multiply

instructions execute in a single cycle.

The 16-bit ALU has been enhanced with integer divide

assist hardware that supports an iterative

non-restoring divide algorithm. It operates in conjunc-

tion with the REPEAT instruction looping mechanism,

and a selection of iterative divide instructions, to

support 32-bit (or 16-bit) divided by 16-bit integer

signed and unsigned division. All divide operations

require 19 cycles to complete but are interruptible at

any cycle boundary.

PIC24 devices have sixteen 16-bit working registers in

the programmer’s model. Each of the working

registers can act as a data, address or address offset

register. The 16th working register (W15) operates as

a software Stack Pointer for interrupts and calls.

The upper 32 Kbytes of the data space memory map

can optionally be mapped into program space at any

16K word boundary defined by the 8-bit Program

Space Visibility Page (PSVPAG) register. The program

to data space mapping feature lets any instruction

access program space as if it were data space.

The PIC24 has a vectored exception scheme with up

to 8 sources of non-maskable traps and up to 118

interrupt sources. Each interrupt source can be

assigned to one of seven priority levels.

A block diagram of the CPU is shown in Figure 2-1.

The Instruction Set Architecture (ISA) has been signifi-

cantly enhanced beyond that of the PIC18, but main-

tains an acceptable level of backward compatibility. All

PIC18 instructions and addressing modes are

supported either directly or through simple macros.

Many of the ISA enhancements have been driven by

compiler efficiency needs.

2.1

Programmer’s Model

The programmer’s model for the PIC24 is shown in

Figure 2-2. All registers in the programmer’s model are

memory mapped and can be manipulated directly by

instructions. A description of each register is provided

in Table 2-1. All registers associated with the

programmer’s model are memory mapped.

The core supports Inherent (no operand), Relative,

Literal, Memory Direct and three groups of addressing

modes. All modes support Register Direct and various

Register Indirect modes. Each group offers up to 7

addressing modes. Instructions are associated with

predefined addressing modes depending upon their

functional requirements.

Preliminary

DS39747C-page 19

PIC24FJ128GA FAMILY

FIGURE 2-1:

PIC24 CPU CORE BLOCK DIAGRAM

PSV & Table

Data Access

Control Block

Data Bus

Interrupt

Controller

16

8

Data Latch

Data RAM

23

16

PCH PCL

Program Counter

PCU

23

Address

Latch

Loop

Control

Logic

Stack

Control

Logic

23

16

RAGU

WAGU

Address Latch

Program Memory

Data Latch

EA MUX

16

Address Bus

ROM Latch

24

16

Instruction

Decode &

Control

Instruction Reg

Control Signals

to Various Blocks

Hardware

Multiplier

16 x 16

W Register Array

Divide

16

Support

16-Bit ALU

16

To Peripheral Modules

DS39747C-page 20

Preliminary

PIC24FJ128GA FAMILY

TABLE 2-1:

CPU CORE REGISTERS

Register(s) Name

Description

W0 through W15

PC

Working register array

23-bit Program Counter

SR

ALU STATUS register

SPLIM

Stack Pointer Limit Value register

Table Memory Page Address register

Program Space Visibility Page Address register

Repeat Loop Counter register

CPU Control Register

TBLPAG

PSVPAG

RCOUNT

CORCON

FIGURE 2-2:

PROGRAMMER’S MODEL

15

0

W0 (WREG)

Divider Working Registers

Multiplier Registers

W1

W2

W3

W4

W5

W6

W7

Working/Address

Registers

W8

W9

W10

W11

W12

W13

W14

W15

Frame Pointer

Stack Pointer

0

Stack Pointer Limit

Program Counter

0

SPLIM

22

0

PC

7

0

TBLPAG

Data Table Page Address

7

Program Space Visibility

Page Address

PSVPAG

15

RCOUNT

IPL

REPEAT Loop Counter

SRL

0

C

SRH

STATUS Register (SR)

— — — — — — —

DC

RA N OV Z

2 1 0

15

0

— — — — — — — — — — — — IPL3 PSV — —

Core Control Register (CORCON)

Registers or bits shadowed for PUSH.Sand POP.Sinstructions.

Preliminary

DS39747C-page 21

PIC24FJ128GA FAMILY

2.2

CPU Control Registers

REGISTER 2-1:

Upper Byte:

SR: CPU STATUS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U -0

—

R/W-0

DC

—

bit 15

bit 8

Lower Byte:

R/W-0⁽¹⁾

IPL2⁽²⁾

R/W-0⁽¹⁾

IPL1⁽²⁾

R/W-0⁽¹⁾

IPL0⁽²⁾

R-0

RA

R/W-0

N

R/W-0

OV

R/W-0

C

Z

bit 7

bit 0

bit 15-9 Unimplemented: Read as ‘0’

bit 8

DC: ALU Half Carry/Borrow bit

1= A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data)

of the result occurred

0= No carry-out from the 4th or 8th low-order bit of the result has occurred

bit 7-5

IPL2:IPL0: CPU Interrupt Priority Level Status bits⁽²⁾

111= CPU interrupt priority level is 7 (15). User interrupts disabled.

110= CPU interrupt priority level is 6 (14)

101= CPU Interrupt Priority Level is 5 (13)

100= CPU interrupt priority level is 4 (12)

011= CPU interrupt priority level is 3 (11)

010= CPU interrupt priority level is 2 (10)

001= CPU interrupt priority level is 1 (9)

000= CPU interrupt priority level is 0 (8)

Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority

level. The value in parentheses indicates the IPL when IPL3 = 1.

bit 4

bit 3

bit 2

bit 1

bit 0

RA: REPEATLoop Active bit

1= REPEATloop in progress

0= REPEATloop not in progress

N: ALU Negative bit

1= Result was negative

0= Result was non-negative (zero or positive)

OV: ALU Overflow bit

1= Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation

0= No overflow has occurred

Z: ALU Zero bit

1= An operation which effects the Z bit has set it at some time in the past

0= The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result)

C: ALU Carry/Borrow bit

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 22

Preliminary

PIC24FJ128GA FAMILY

REGISTER 2-2:

Upper Byte:

CORCON: CORE CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

U-0

—

U-0

—

U-0

—

R/C-0

IPL3

R/W-0

PSV

U-0

—

bit 7

bit 0

bit 15-4 Unimplemented: Read as ‘0’

bit 3

IPL3: CPU Interrupt Priority Level Status bit

1= CPU interrupt priority level is greater than 7

0= CPU interrupt priority level is 7 or less

Note: User interrupts are disabled when IPL3 = 1.

bit 2

PSV: Program Space Visibility in Data Space Enable bit

1= Program space visible in data space

0= Program space not visible in data space

bit 1-0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

The PIC24 CPU incorporates hardware support for

both multiplication and division. This includes a dedi-

cated hardware multiplier and support hardware for

16-bit divisor division.

2.3

Arithmetic Logic Unit (ALU)

The PIC24 ALU is 16 bits wide and is capable of addi-

tion, subtraction, bit shifts and logic operations. Unless

otherwise mentioned, arithmetic operations are 2’s

complement in nature. Depending on the operation, the

ALU may affect the values of the Carry (C), Zero (Z),

Negative (N), Overflow (OV) and Digit Carry (DC)

Status bits in the SR register. The C and DC Status bits

operate as Borrow and Digit Borrow bits, respectively,

for subtraction operations.

2.3.1

MULTIPLIER

The ALU contains a high-speed 17-bit x 17-bit

multiplier. It supports unsigned, signed or mixed sign

operation in several multiplication modes:

1. 16-bit x 16-bit signed

2. 16-bit x 16-bit unsigned

The ALU can perform 8-bit or 16-bit operations,

depending on the mode of the instruction that is used.

Data for the ALU operation can come from the W

register array, or data memory, depending on the

addressing mode of the instruction. Likewise, output

data from the ALU can be written to the W register array

or a data memory location.

3. 16-bit signed x 5-bit (literal) unsigned

4. 16-bit unsigned x 16-bit unsigned

5. 16-bit unsigned x 5-bit (literal) unsigned

6. 16-bit unsigned x 16-bit signed

7. 8-bit unsigned x 8-bit unsigned

Preliminary

DS39747C-page 23

PIC24FJ128GA FAMILY

2.3.2

DIVIDER

2.3.3

MULTI-BIT SHIFT SUPPORT

The divide block supports 32-bit/16-bit and 16-bit/16-bit

signed and unsigned integer divide operation with the

following data sizes:

The PIC24 ALU supports both single-bit and

single-cycle, multi-bit arithmetic and logic shifts.

Multi-bit shifts are implemented using a shifter block,

capable of performing up to a 15-bit arithmetic right

shift, or up to a 15-bit left shift, in a single cycle. All

multi-bit shift instructions only support register direct

addressing for both the operand source and result

destination.

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0

and the remainder in W1. 16-bit signed and unsigned

DIVinstructions can specify any W register for both the

16-bit divisor (Wn) and any W register (aligned) pair

(W(m+1):Wm) for the 32-bit dividend. The divide algo-

rithm takes one cycle per bit of divisor, so both

32-bit/16-bit and 16-bit/16-bit instructions take the

same number of cycles to execute.

A full summary of instructions that use the shift

operation is provided below in Table 2-2.

TABLE 2-2:

Instruction

INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION

Description

ASR

ASRF

ASRW

Arithmetic shift right source register by one bit.

Arithmetic shift right the content of the register by one bit.

Arithmetic shift right source register by up to 15 bits, value held in the W register referenced

within instruction.

ASRK

SL

Arithmetic shift right source register up to 15 bits. Shift value is literal.

Shift left source register by one bit.

SLF

SLW

SLK

LSR

LSRF

LSRW

Shift left the content of the file register by one bit.

Shift left source register by up to 15 bits, value held in the W register referenced instruction.

Shift left source register up to 15 bits. Shift value is literal.

Logical shift right source register by one bit.

Logical shift right the content of the register by one bit.

Logical shift right source register by up to 15 bits, value held in the W register referenced

within instruction.

LSRK

Logical shift right source register up to 15 bits. Shift value is literal.

DS39747C-page 24

Preliminary

PIC24FJ128GA FAMILY

either the 23-bit Program Counter (PC) during program

execution, or from table operation or data space

remapping, as described in Section 3.3 “Interfacing

Program and Data Memory Spaces”.

3.0

MEMORY ORGANIZATION

As Harvard architecture devices, PIC24 micro-

controllers feature separate program and data memory

spaces and busses. This architecture also allows the

direct access of program memory from the data space

during code execution.

User access to the program memory space is restricted

to the lower half of the address range (000000h to

7FFFFFh). The exception is the use of TBLRD/TBLWT

operations, which use TBLPAG<7> to permit access to

the Configuration bits and Device ID sections of the

configuration memory space.

3.1

Program Address Space

The

program

address

memory

space

of

PIC24FJ128GA family devices is 4M instructions. The

space is addressable by a 24-bit value derived from

Memory maps for the PIC24FJ128GA family of devices

are shown in Figure 3-1.

FIGURE 3-1:

PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GA FAMILY DEVICES

PIC24FJ64GA

PIC24FJ96GA

PIC24FJ128GA

000000h

000002h

000004h

GOTOInstruction

Reset Address

GOTOInstruction

Reset Address

GOTOInstruction

Reset Address

Interrupt Vector Table

Reserved

Interrupt Vector Table

Reserved

Interrupt Vector Table

Reserved

0000FEh

000100h

000104h

0001FEh

000200h

Alternate Vector Table

User Flash

Program Memory

(22K instructions)

User Flash

Program Memory

(32K instructions)

User Flash

Program Memory

(44K instructions)

Flash Config Words

00ABFEh

00AC00h

00FFFEh

010000h

Flash Config Words

0157FEh

015800h

Unimplemented

(Read ‘0’s)

Unimplemented

(Read ‘0’s)

7FFFFEh

800000h

Reserved

F7FFFEh

F80000h

Device Configuration

Registers

Device Configuration

Registers

Device Configuration

Registers

F8000Eh

F80010h

Reserved

DEVID (2)

Reserved

DEVID (2)

Reserved

FEFFFEh

FF0000h

DEVID (2)

FFFFFEh

Note:

Memory areas are not shown to scale.

Preliminary

DS39747C-page 25

PIC24FJ128GA FAMILY

3.1.1

PROGRAM MEMORY

ORGANIZATION

3.1.3

FLASH CONFIGURATION WORDS

In PIC24FJ128GA family devices, the top two words of

on-chip program memory are reserved for configura-

tion information. On device Reset, the configuration

information is copied into the appropriate Configuration

registers. The addresses of the Flash Configuration

Word for devices in the PIC24FJ128GA family are

shown in Table 3-1. Their location in the memory map

is shown with the other memory vectors in Figure 3-1.

The program memory space is organized in word

addressable blocks. Although it is treated as 24 bits

wide, it is more appropriate to think of each address of

the program memory as a lower and upper word, with

the upper byte of the upper word being unimplemented.

The lower word always has an even address, while the

upper word has an odd address (Figure 3-2).

The Configuration Words in program memory are a

compact format. The actual Configuration bits are

mapped in several different registers in the configura-

tion memory space. Their order in the Flash Configura-

tion Words do not reflect a corresponding arrangement

in the configuration space. Additional details on the

device Configuration Words are provided in

Section 23.1 “Configuration Bits”.

Program memory addresses are always word-aligned

on the lower word, and addresses are incremented or

decremented by two during code execution. This

arrangement also provides compatibility with data

memory space addressing and makes it possible to

access data in the program memory space.

3.1.2

HARD MEMORY VECTORS

All PIC24 devices reserve the addresses between

00000h and 000200h for hard coded program execu-

tion vectors. A hardware Reset vector is provided to

redirect code execution from the default value of the

PC on device Reset to the actual start of code. A GOTO

instruction is programmed by the user at 000000h, with

the actual address for the start of code at 000002h.

TABLE 3-1:

FLASH CONFIGURATION

WORDS FOR PIC24FJ128GA

FAMILY DEVICES

Program

Memory

Configuration

Word

Device

(K words)

Addresses

PIC24 devices also have two interrupt vector tables,

located from 000004h to 0000FFh and 000100h to

0001FFh. These vector tables allow each of the many

device interrupt sources to be handled by separate

ISRs. A more detailed discussion of the interrupt vector

tables is provided in Section 6.1 “Interrupt Vector

Table”.

PIC24FJ64GA

PIC24FJ96GA

PIC24FJ128GA

22

32

44

00ABFCh:

00ABFEh

00FFFCh:

00FFFEh

0157FCh:

0157FEh

FIGURE 3-2:

PROGRAM MEMORY ORGANIZATION

least significant word

8

msw

Address

PC Address

(lsw Address)

most significant word

23

16

0

000000h

000002h

000004h

000006h

00000000

000001h

000003h

000005h

000007h

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

Instruction Width

DS39747C-page 26

Preliminary

PIC24FJ128GA FAMILY

PIC24FJ128GA family devices implement a total of

8 Kbytes of data memory. Should an EA point to a loca-

tion outside of this area, an all zero word or byte will be

returned.

3.2

Data Address Space

The PIC24 core has a separate 16-bit wide data mem-

ory space, addressable as a single linear range. The

data space is accessed using two Address Generation

Units (AGUs), one each for read and write operations.

The data space memory map is shown in Figure 3-3.

3.2.1

DATA SPACE WIDTH

The data memory space is organized in byte address-

able, 16-bit wide blocks. Data is aligned in data

memory and registers as 16-bit words, but all data

space EAs resolve to bytes. The Least Significant

Bytes of each word have even addresses, while the

Most Significant Bytes have odd addresses.

All Effective Addresses (EAs) in the data memory

space are 16 bits wide, and point to bytes within the

data space. This gives a data space address range of

64 Kbytes, or 32K words. The lower half of the data

memory space (that is, when EA<15> = 0) is used for

implemented memory addresses, while the upper half

(EA<15> = 1) is reserved for the Program Space Visi-

bility area (see Section 3.3.3 “Reading Data from

Program Memory Using Program Space Visibility”).

FIGURE 3-3:

DATA SPACE MEMORY MAP FOR PIC24FJ128GA FAMILY DEVICES

MSB

Address

LSB

Address

MSB

LSB

0000h

SFR

0001h

SFR Space

Data RAM

Space

07FFh

0801h

07FEh

0800h

Near

Data Space

Implemented

Data RAM

1FFFh

2001h

27FFh

2801h

1FFEh

2000h

07FEh

0800h

Unimplemented

Read as ‘0’

7FFFh

8001h

7FFFh

8000h

Program Space

Visibility Area

FFFFh

FFFEh

Note:

Data memory areas are not shown to scale.

Preliminary

DS39747C-page 27

PIC24FJ128GA FAMILY

A sign-extend instruction (SE) is provided to allow

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users

can clear the MSB of any W register by executing a

zero-extend (ZE) instruction on the appropriate

address.

3.2.2

DATA MEMORY ORGANIZATION

AND ALIGNMENT

To maintain backward compatibility with PICmicro^®

devices and improve data space memory usage effi-

ciency, the PIC24 instruction set supports both word

and byte operations. As a consequence of byte acces-

sibility, all effective address calculations are internally

scaled to step through word-aligned memory. For

example, the core recognizes that Post-Modified

Register Indirect Addressing mode [Ws++] will result in

a value of Ws + 1 for byte operations and Ws + 2 for

word operations.

Although most instructions are capable of operating on

word or byte data sizes, it should be noted that some

instructions operate only on words.

3.2.3

NEAR DATA SPACE

The 8-Kbyte area between 0000h and 1FFFh is

referred to as the near data space. Locations in this

space are directly addressable via a 13-bit absolute

address field within all memory direct instructions. The

remainder of the data space is addressable indirectly.

Additionally, the whole data space is addressable using

MOV instructions, which support Memory Direct

Addressing with a 16-bit address field.

Data byte reads will read the complete word which con-

tains the byte, using the LSb of any EA to determine

which byte to select. The selected byte is placed onto

the LSB of the data path. That is, data memory and reg-

isters are organized as two parallel byte-wide entities

with shared (word) address decode but separate write

lines. Data byte writes only write to the corresponding

side of the array or register which matches the byte

address.

3.2.4

SFR SPACE

The first 2 Kbytes of the near data space, from 0000h

to 07FFh, are primarily occupied with Special Function

Registers (SFRs). These are used by the PIC24 core

and peripheral modules for controlling the operation of

the device.

All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported, so

care must be taken when mixing byte and word opera-

tions, or translating from 8-bit MCU code. If a

misaligned read or write is attempted, an address error

trap will be generated. If the error occurred on a read,

the instruction underway is completed; if it occurred on

a write, the instruction will be executed but the write will

not occur. In either case, a trap is then executed, allow-

ing the system and/or user to examine the machine

state prior to execution of the address Fault.

SFRs are distributed among the modules that they con-

trol, and are generally grouped together by module.

Much of the SFR space contains unused addresses;

these are read as ‘0’. A diagram of the SFR space,

showing where SFRs are actually implemented, is

shown in Table 3-2. Each implemented area indicates

a 32-byte region where at least one address is imple-

mented as an SFR. A complete listing of implemented

SFRs, including their addresses, is shown in Tables 3-3

through 3-30.

All byte loads into any W register are loaded into the

Least Significant Byte. The Most Significant Byte is not

modified.

TABLE 3-2:

IMPLEMENTED REGIONS OF SFR DATA SPACE

SFR Space Address

xx00

xx20

xx40

xx60

xx80

xxA0

xxC0

xxE0

000h

100h

200h

300h

400h

500h

600h

700h

Core

ICN

—

Interrupts

—

Timers

A/D

Capture

Compare

—

I²C™

UART

SPI

—

I/O

—

PMP

—

RTC/Comp

—

CRC

System

I/O

NVM/PMD

—

Legend: — = No implemented SFRs in this block

DS39747C-page 28

Preliminary

PIC24FJ128GA FAMILY

3.2.5

SOFTWARE STACK

3.3

Interfacing Program and Data

Memory Spaces

In addition to its use as a working register, the W15 reg-

ister in PIC24 devices is also used as a software Stack

Pointer. The pointer always points to the first available

free word and grows from lower to higher addresses. It

pre-decrements for stack pops and post-increments for

stack pushes, as shown in Figure 3-4. Note that for a

PC push during any CALLinstruction, the MSB of the

PC is zero-extended before the push, ensuring that the

MSB is always clear.

The PIC24 architecture uses a 24-bit wide program

space and 16-bit wide data space. The architecture is

also a modified Harvard scheme, meaning that data

can also be present in the program space. To use this

data successfully, it must be accessed in a way that

preserves the alignment of information in both spaces.

Aside from normal execution, the PIC24 architecture

provides two methods by which program space can be

accessed during operation:

Note:

A PC push during exception processing

will concatenate the SRL register to the

MSB of the PC prior to the push.

• Using table instructions to access individual bytes

or words anywhere in the program space

The Stack Pointer Limit register (SPLIM) associated

with the Stack Pointer sets an upper address boundary

for the stack. SPLIM is uninitialized at Reset. As is the

case for the Stack Pointer, SPLIM<0> is forced to ‘0’

because all stack operations must be word-aligned.

Whenever an EA is generated using W15 as a source

or destination pointer, the resulting address is com-

pared with the value in SPLIM. If the contents of the

Stack Pointer (W15) and the SPLIM register are equal

and a push operation is performed, a stack error trap

will not occur. The stack error trap will occur on a

subsequent push operation. Thus, for example, if it is

desirable to cause a stack error trap when the stack

grows beyond address 2000h in RAM, initialize the

SPLIM with the value, 1FFEh.

• Remapping a portion of the program space into

the data space (Program Space Visibility)

Table instructions allow an application to read or write

to small areas of the program memory. This makes the

method ideal for accessing data tables that need to be

updated from time to time. It also allows access to all

bytes of the program word. The remapping method

allows an application to access a large block of data on

a read-only basis, which is ideal for look ups from a

large table of static data. It can only access the least

significant word of the program word.

3.3.1

ADDRESSING PROGRAM SPACE

Since the address ranges for the data and program

spaces are 16 and 24 bits respectively, a method is

needed to create a 23-bit or 24-bit program address

from 16-bit data registers. The solution depends on the

interface method to be used.

Similarly, a Stack Pointer underflow (stack error) trap is

generated when the Stack Pointer address is found to

be less than 0800h. This prevents the stack from

interfering with the Special Function Register (SFR)

space.

For table operations, the 8-bit Table Page register

(TBLPAG) is used to define a 32K word region within

the program space. This is concatenated with a 16-bit

EA to arrive at a full 24-bit program space address. In

this format, the Most Significant bit of TBLPAG is used

to determine if the operation occurs in the user memory

(TBLPAG<7> = 0) or the configuration memory

(TBLPAG<7> = 1).

A write to the SPLIM register should not be immediately

followed by an indirect read operation using W15.

FIGURE 3-4:

CALL STACK FRAME

0000h

15

0

For remapping operations, the 8-bit Program Space

Visibility register (PSVPAG) is used to define a

16K word page in the program space. When the Most

Significant bit of the EA is ‘1’, PSVPAG is concatenated

with the lower 15 bits of the EA to form a 23-bit program

space address. Unlike table operations, this limits

remapping operations strictly to the user memory area.

PC<15:0>

000000000

W15 (before CALL)

PC<22:16>

W15 (after CALL)

Table 3-31 and Figure 3-5 show how the program EA is

created for table operations and remapping accesses

from the data EA. Here, P<23:0> refers to a program

space word, whereas D<15:0> refers to a data space

word.

POP : [--W15]

PUSH: [W15++]

DS39747C-page 40

Preliminary

PIC24FJ128GA FAMILY

TABLE 3-31: PROGRAM SPACE ADDRESS CONSTRUCTION

Program Space Address

Access

Space

Access Type

<23>

<22:16>

<15>

PC<22:1>

<14:1>

<0>

Instruction Access

(Code Execution)

User

0

0xx xxxx xxxx xxxx xxxx xxx0

TBLRD/TBLWT

(Byte/Word Read/Write)

TBLPAG<7:0>

0xxx xxxx

Data EA<15:0>

xxxx xxxx xxxx xxxx

Data EA<15:0>

Configuration

TBLPAG<7:0>

1xxx xxxx

xxxx xxxx xxxx xxxx

Data EA<14:0>⁽¹⁾

Program Space Visibility User

(Block Remap/Read)

0

PSVPAG<7:0>

xxxx xxxx

xxx xxxx xxxx xxxx

Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of

the address is PSVPAG<0>.

FIGURE 3-5:

DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

Program Counter⁽¹⁾

Program Counter

23 bits

0

1/0

EA

Table Operations⁽²⁾

1/0

TBLPAG

8 bits

16 bits

24 bits

Select

0

1

EA

Program Space Visibility⁽¹⁾

(Remapping)

0

PSVPAG

8 bits

15 bits

23 bits

Byte Select

User/Configuration

Space Select

Note 1: The LSb of program space addresses is always fixed as ‘0’, in order to maintain word alignment of

data in the program and data spaces.

2: Table operations are not required to be word-aligned. Table read operations are permitted in the

configuration memory space.

Preliminary

DS39747C-page 41

PIC24FJ128GA FAMILY

2. TBLRDH (Table Read High): In Word mode, it

3.3.2

DATA ACCESS FROM PROGRAM

MEMORY USING TABLE

INSTRUCTIONS

maps the entire upper word of a program address

(P<23:16>) to

a data address. Note that

D<15:8>, the “phantom byte”, will always be ‘0’.

The TBLRDL and TBLWTL instructions offer a direct

method of reading or writing the lower word of any

address within the program space, without going

through data space. The TBLRDHand TBLWTHinstruc-

tions are the only method to read or write the upper 8 bits

of a program space word as data.

In Byte mode, it maps the upper or lower byte of

the program word to D<7:0> of the data

address, as above. Note that the data will

always be ‘0’ when the upper “phantom” byte is

selected (byte select = 1).

In a similar fashion, two table instructions, TBLWTH

and TBLWTL, are used to write individual bytes or

words to a program space address. The details of

their operation are explained in Section 4.0 “Flash

Program Memory”.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two 16-bit

word wide address spaces, residing side by side, each

with the same address range. TBLRDL and TBLWTL

access the space which contains the least significant

data word, and TBLRDHand TBLWTHaccess the space

which contains the upper data byte.

For all table operations, the area of program memory

space to be accessed is determined by the Table Page

register (TBLPAG). TBLPAG covers the entire program

memory space of the device, including user and config-

uration spaces. When TBLPAG<7> = 0, the Table Page

is located in the user memory space. When

TBLPAG<7> = 1, the page is located in configuration

space.

Two table instructions are provided to move byte or

word sized (16-bit) data to and from program space.

Both function as either byte or word operations.

1. TBLRDL (Table Read Low): In Word mode, it

maps the lower word of the program space

location (P<15:0>) to a data address (D<15:0>).

Note:

Only table read operations will execute in

the configuration memory space and only

then, in implemented areas such as the

Device ID. Table write operations are not

allowed.

In Byte mode, either the upper or lower byte of

the lower program word is mapped to the lower

byte of a data address. The upper byte is

selected when byte select is ‘1’; the lower byte

is selected when it is ‘0’.

FIGURE 3-6:

ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Program Space

TBLPAG

02

Data EA<15:0>

23

15

0

000000h

23

16

8

0

00000000

020000h

030000h

‘Phantom’ Byte

TBLRDH.B(Wn<0> = 0)

TBLRDL.B(Wn<0> = 1)

TBLRDL.B(Wn<0> = 0)

TBLRDL.W

The address for the table operation is determined by the data EA

within the page defined by the TBLPAG register.

Only read operations are shown; write operations are also valid in

the user memory area.

800000h

DS39747C-page 42

Preliminary

PIC24FJ128GA FAMILY

24-bit program word are used to contain the data. The

upper 8 bits of any program space locations used as

data should be programmed with ‘1111 1111’ or

‘0000 0000’ to force a NOP. This prevents possible

issues should the area of code ever be accidentally

executed.

3.3.3

READING DATA FROM PROGRAM

MEMORY USING PROGRAM

SPACE VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word page of the program space.

This provides transparent access of stored constant

data from the data space without the need to use

special instructions (i.e., TBLRDL/H).

Note:

PSV access is temporarily disabled during

table reads/writes.

Program space access through the data space occurs

if the Most Significant bit of the data space EA is ‘1’ and

program space visibility is enabled by setting the PSV

bit in the Core Control register (CORCON<2>). The

location of the program memory space to be mapped

into the data space is determined by the Program

Space Visibility Page register (PSVPAG). This 8-bit

register defines any one of 256 possible pages of

16K words in program space. In effect, PSVPAG func-

tions as the upper 8 bits of the program memory

address, with the 15 bits of the EA functioning as the

lower bits. Note that by incrementing the PC by 2 for

each program memory word, the lower 15 bits of data

space addresses directly map to the lower 15 bits in the

corresponding program space addresses.

For operations that use PSV and are executed outside

a REPEATloop, the MOV and MOV.Dinstructions will

require one instruction cycle in addition to the specified

execution time. All other instructions will require two

instruction cycles in addition to the specified execution

time.

For operations that use PSV which are executed inside

a REPEAT loop, there will be some instances that

require two instruction cycles in addition to the

specified execution time of the instruction:

• Execution in the first iteration

• Execution in the last iteration

• Execution prior to exiting the loop due to an

interrupt

• Execution upon re-entering the loop after an

interrupt is serviced

Data reads to this area add an additional cycle to the

instruction being executed, since two program memory

fetches are required.

Any other iteration of the REPEAT loop will allow the

instruction accessing data, using PSV, to execute in a

single cycle.

Although each data space address, 8000h and higher,

maps directly into a corresponding program memory

address (see Figure 3-7), only the lower 16 bits of the

FIGURE 3-7:

PROGRAM SPACE VISIBILITY OPERATION

When CORCON<2> = 1and EA<15> = 1:

Program Space

Data Space

PSVPAG

02

23

15

0

000000h

0000h

Data EA<14:0>

010000h

018000h

The data in the page

designated by

PSVPAG is mapped

into the upper half of

the data memory

space....

8000h

PSV Area

...while the lower 15

bits of the EA specify

an exact address

within the PSV area.

This corresponds

exactly to the same

lower 15 bits of the

actual program space

address.

FFFFh

800000h

Preliminary

DS39747C-page 43

PIC24FJ128GA FAMILY

NOTES:

DS39747C-page 44

Preliminary

PIC24FJ128GA FAMILY

RTSP is accomplished using TBLRD (table read) and

TBLWT (table write) instructions. With RTSP, the user

may write program memory data in blocks of 64 instruc-

tions (192 bytes) at a time, and erase program memory

in blocks of 512 instructions (1536 bytes) at a time.

4.0

FLASH PROGRAM MEMORY

Note:

This data sheet summarizes the features

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

4.1

Table Instructions and Flash

Programming

The PIC24FJ128GA family of devices contains internal

Flash program memory for storing and executing appli-

cation code. The memory is readable, writable and

erasable during normal operation over the entire VDD

range.

Regardless of the method used, all programming of

Flash memory is done with the table read and table

write instructions. These allow direct read and write

access to the program memory space from the data

memory while the device is in normal operating mode.

The 24-bit target address in the program memory is

formed using bits<7:0> of the TBLPAG register and the

Effective Address (EA) from a W register specified in

the table instruction, as shown in Figure 4-1.

Flash memory can be programmed in two ways:

1. In-Circuit Serial Programming (ICSP)

2. Run-Time Self-Programming (RTSP)

ICSP allows a PIC24FJ128GA family device to be seri-

ally programmed while in the end application circuit.

This is simply done with two lines for Programming

Clock and Programming Data (which are named PGCx

and PGDx, respectively), and three other lines for

power (VDD), ground (VSS) and Master Clear (MCLR).

This allows customers to manufacture boards with

unprogrammed devices and then program the micro-

controller just before shipping the product. This also

allows the most recent firmware or a custom firmware

to be programmed.

The TBLRDLand the TBLWTLinstructions are used to

read or write to bits<15:0> of program memory.

TBLRDLand TBLWTLcan access program memory in

both Word and Byte modes.

The TBLRDHand TBLWTHinstructions are used to read

or write to bits<23:16> of program memory. TBLRDH

and TBLWTHcan also access program memory in Word

or Byte mode.

FIGURE 4-1:

ADDRESSING FOR TABLE REGISTERS

24 bits

Program Counter

Using

Program

Counter

0

Working Reg EA

Using

Table

Instruction

1/0

TBLPAG Reg

8 bits

16 bits

User/Configuration

Space Select

Byte

Select

24-bit EA

Preliminary

DS39747C-page 45

PIC24FJ128GA FAMILY

4.2

RTSP Operation

4.3

Control Registers

The PIC24 Flash program memory array is organized

into rows of 64 instructions or 192 bytes. RTSP allows

the user to erase blocks of eight rows (512 instructions)

at a time, and to program one row at a time. The 8-row

erase blocks and single-row write blocks are edge-

aligned, from the beginning of program memory, on

boundaries of 1536 bytes and 192 bytes, respectively.

There are two SFRs used to read and write the

program Flash memory: NVMCON and NVMKEY.

The NVMCON register (Register 4-1) controls which

blocks are to be erased, which memory type is to be

programmed and the start of the programming cycle.

NVMKEY is a write-only register that is used for write

protection. To start a programming or erase sequence,

the user must consecutively write 55h and AAh to the

NVMKEY register. Refer to Section 4.4 “Programming

Operations” for further details.

The program memory implements holding buffers that

can contain 64 instructions of programming data. Prior

to the actual programming operation, the write data

must be loaded into the buffers in sequential order. The

instructions words loaded must always be from a group

of 64 boundaries.

4.4

Programming Operations

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. A programming operation is nominally 4 ms in

duration and the processor stalls (waits) until the oper-

ation is finished. Setting the WR bit (NVMCON<15>)

starts the operation, and the WR bit is automatically

cleared when the operation is finished.

The basic sequence for RTSP programming is to set up

a Table Pointer, then do a series of TBLWTinstructions

to load the buffers. Programming is performed by set-

ting the control bits in the NVMCON register. A total of

64 TBLWTL and TBLWTH instructions are required to

load the instructions.

All of the table write operations are single-word writes

(2 instruction cycles), because only the buffers are writ-

ten. A programming cycle is required for programming

each row.

DS39747C-page 46

Preliminary

PIC24FJ128GA FAMILY

REGISTER 4-1:

NVMCOM: FLASH MEMORY CONTROL REGISTER

Upper Byte:

R/SO-0⁽¹⁾R/W-0⁽¹⁾

R/W-0⁽¹⁾

WRERR

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

WR

bit 15

WREN

bit 8

Lower Byte:

U-0

—

R/W-0⁽¹⁾

U-0

R/W-0⁽¹⁾

ERASE

—

NVMOP3⁽²⁾NVMOP2⁽²⁾NVMOP1⁽²⁾NVMOP0⁽²⁾

bit 7

bit 0

bit 15

WR: Write Control bit

1= Initiates a Flash memory program or erase operation

The operation is self-timed and the bit is cleared by hardware once operation is complete.

0= Program or erase operation is complete and inactive

bit 14

bit 13

WREN: Write Enable bit

1= Enable Flash program/erase operations

0= Inhibit Flash program/erase operations

WRERR: Write Sequence Error Flag bit

1= An improper program or erase sequence attempt or termination has occurred (bit is set automatically

on any set attempt of the WR bit)

0= The program or erase operation completed normally

bit 12-7 Unimplemented: Read as ‘0’

bit 6

ERASE: Erase/Program Enable bit

1= Perform the erase operation specified by NVMOP3:NVMOP0 on the next WR command

0= Perform the program operation specified by NVMOP3:NVMOP0 on the next WR command

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

NVMOP3:NVMOP0: NVM Operation Select bits⁽²⁾

1111= Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)

0010= Memory row erase operation (ERASE = 1) or no operation (ERASE = 0)

0001= Memory row program operation (ERASE = 0) or no operation (ERASE = 1)

Note 1: These bits can only be reset on POR.

2: All other combinations of NVMOP3:NVMOP0 are unimplemented.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

SO = Settable-Only bit

‘0’ = Bit is cleared

U = Unimplemented bit

x = Bit is unknown

-n = Value at Reset

Preliminary

DS39747C-page 47

PIC24FJ128GA FAMILY

4. Write the first 64 instructions from data RAM into

the program memory buffers (see Example 4-2).

4.4.1

PROGRAMMING ALGORITHM FOR

FLASH PROGRAM MEMORY

5. Write the program block to Flash memory:

The user can program one row of program Flash memory

at a time. To do this, it is necessary to erase the 8-row

erase block containing the desired row. The general

process is:

a) Set the NVMOP bits to ‘0001’ to configure

for row programming. Clear the ERASE bit

and set the WREN bit.

b) Write 55h to NVMKEY.

c) Write AAh to NVMKEY.

1. Read eight rows of program memory

(512 instructions) and store in data RAM.

d) Set the WR bit. The programming cycle

begins and the CPU stalls for the duration of

the write cycle. When the write to Flash mem-

ory is done, the WR bit is cleared automati-

cally.

2. Update the program data in RAM with the

desired new data.

3. Erase the block (see Example 4-1):

a) Set the NVMOP bits (NVMCOM<3:0>) to

‘0010’ to configure for block erase. Set the

ERASE (NVMCOM<6>) and WREN

(NVMCOM<14>) bits.

6. Repeat steps 4 and 5, using the next available

64 instructions from the block in data RAM by

incrementing the value in TBLPAG, until all

512 instructions are written back to Flash

memory.

b) Write the starting address of the block to be

erased into the TBLPAG and W registers.

c) Write 55h to NVMKEY.

d) Write AAh to NVMKEY.

For protection against accidental operations, the write

initiate sequence for NVMKEY must be used to allow

any erase or program operation to proceed. After the

programming command has been executed, the user

must wait for the programming time until programming

is complete. The two instructions following the start of

the programming sequence should be NOPs, as shown

in Example 4-3.

e) Set the WR bit (NVMCOM<15>). The erase

cycle begins and the CPU stalls for the dura-

tion of the erase cycle. When the erase is

done, the WR bit is cleared automatically.

EXAMPLE 4-1:

ERASING A PROGRAM MEMORY BLOCK

; Set up NVMCON for block erase operation

MOV

#0x4042, W0

W0, NVMCON

;

; Initialize NVMCON

; Init pointer to row to be ERASED

MOV

#tblpage(PROG_ADDR), W0

W0, TBLPAG

#tbloffset(PROG_ADDR), W0

;

; Initialize PM Page Boundary SFR

; Initialize in-page EA[15:0] pointer

; Set base address of erase block

; Block all interrupts with priority <7

; for next 5 instructions

TBLWTL W0, [W0]

DISI

#5

MOV

BSET

NOP

#0x55, W0

W0, NVMKEY

#0xAA, W1

W1, NVMKEY

NVMCON, #WR

; Write the 55 key

;

; Write the AA key

; Start the erase sequence

; Insert two NOPs after the erase

; command is asserted

DS39747C-page 48

Preliminary

PIC24FJ128GA FAMILY

EXAMPLE 4-2:

LOADING THE WRITE BUFFERS

; Set up NVMCON for row programming operations

MOV

#0x4001, W0

W0, NVMCON

;

; Initialize NVMCON

; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled

MOV

#0x0000, W0

W0, TBLPAG

#0x6000, W0

;

; Initialize PM Page Boundary SFR

; An example program memory address

; Perform the TBLWT instructions to write the latches

; 0th_program_word

MOV

TBLWTL

#LOW_WORD_0, W2

#HIGH_BYTE_0, W3

W2, [W0]

;

; Write PM low word into program latch

; Write PM high byte into program latch

TBLWTH

W3, [W0++]

; 1st_program_word

MOV

#LOW_WORD_1, W2

#HIGH_BYTE_1, W3

W2, [W0]

;

MOV

TBLWTL

; Write PM low word into program latch

; Write PM high byte into program latch

TBLWTH

W3, [W0++]

;

2nd_program_word

MOV

TBLWTL

#LOW_WORD_2, W2

#HIGH_BYTE_2, W3

W2, [W0]

;

; Write PM low word into program latch

; Write PM high byte into program latch

TBLWTH

W3, [W0++]

•

; 63rd_program_word

MOV

#LOW_WORD_31, W2

;

MOV

TBLWTL

TBLWTH

#HIGH_BYTE_31, W3

W2, [W0]

W3, [W0++]

;

; Write PM low word into program latch

; Write PM high byte into program latch

EXAMPLE 4-3:

INITIATING A PROGRAMMING SEQUENCE

DISI

#5

; Block all interrupts with priority <7

; for next 5 instructions

MOV

BSET

NOP

#0x55, W0

W0, NVMKEY

#0xAA, W1

W1, NVMKEY

NVMCON, #WR

; Write the 55 key

;

; Write the AA key

; Start the erase sequence

; Insert two NOPs after the

; erase command is asserted

Preliminary

DS39747C-page 49

PIC24FJ128GA FAMILY

NOTES:

DS39747C-page 50

Preliminary

PIC24FJ128GA FAMILY

5.0

RESETS

Note:

Refer to the specific peripheral or CPU

section of this manual for register Reset

states.

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

All types of device Reset will set a corresponding status

bit in the RCON register to indicate the type of Reset

(see Register 5-1). A POR will clear all bits except for

the BOR and POR bits (RCON<1:0>), which are set.

The user may set or clear any bit at any time during

code execution. The RCON bits only serve as status

bits. Setting a particular Reset status bit in software will

not cause a device Reset to occur.

• POR: Power-on Reset

• MCLR: Pin Reset

• SWR: RESETInstruction

• WDT: Watchdog Timer Reset

• BOR: Brown-out Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Opcode Reset

• UWR: Uninitialized W Register Reset

The RCON register also has other bits associated with

the Watchdog Timer and device power-saving states.

The function of these bits is discussed in other sections

of this manual.

A simplified block diagram of the Reset module is

shown in Figure 5-1.

Note:

The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset will be meaningful.

Any active source of Reset will make the SYSRST sig-

nal active. Many registers associated with the CPU and

peripherals are forced to a known Reset state. Most

registers are unaffected by a Reset; their status is

unknown on POR and unchanged by all other Resets.

FIGURE 5-1:

RESET SYSTEM BLOCK DIAGRAM

RESET

Instruction

Glitch Filter

MCLR

WDT

Module

Sleep or Idle

POR

VDD Rise

Detect

SYSRST

VDD

Brown-out

Reset

BOR

Enable Voltage Regulator

Trap Conflict

Illegal Opcode

Uninitialized W Register

Preliminary

DS39747C-page 51

PIC24FJ128GA FAMILY

REGISTER 5-1:

Upper Byte:

RCON: RESET CONTROL REGISTER

R/W-0

IOPUWR

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CM

R/W-0

TRAPR

VREGS

bit 15

bit 8

Lower Byte:

R/W-0

EXTR

R/W-0

SWR

R/W-0

SWDTEN

R/W-0

WDTO

R/W-0

IDLE

R/W-1

BOR

R/W-1

POR

SLEEP

bit 7

bit 0

bit 15

bit 14

TRAPR: Trap Reset Flag bit

1= A Trap Conflict Reset has occurred

0= A Trap Conflict Reset has not occurred

IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit

1= An illegal opcode detection, an illegal address mode, or uninitialized W register used as an Address

Pointer caused a Reset

0= An illegal opcode or uninitialized W Reset has not occurred

bit 13-10 Unimplemented: Read as ‘0’

bit 9

bit 8

bit 7

bit 6

bit 5

CM: Configuration Word Mismatch Reset Flag bit

1= A Configuration Word Mismatch Reset has occurred

0= A Configuration Word Mismatch Reset has not occurred

VREGS: Voltage Regulator Standby Enable bit

1= Regulator remains active during Sleep

0= Regulator goes to standby during Sleep

EXTR: External Reset (MCLR) Pin bit

1= A Master Clear (pin) Reset has occurred

0= A Master Clear (pin) Reset has not occurred

SWR: Software Reset (Instruction) Flag bit

1= A RESETinstruction has been executed

0= A RESETinstruction has not been executed

SWDTEN: Software Enable/Disable of WDT bit

1= WDT is enabled

0= WDT is disabled

Note: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless

of the SWDTEN bit setting.

bit 4

bit 3

bit 2

WDTO: Watchdog Timer Time-out Flag bit

1= WDT time-out has occurred

0= WDT time-out has not occurred

SLEEP: Wake From Sleep Flag bit

1= Device has been in Sleep mode

0= Device has not been in Sleep mode

IDLE: Wake-up From Idle Flag bit

1= Device was in Idle mode

0= Device was not in Idle mode

bit 1

bit 0

BOR: Brown-out Reset Flag bit

1= A Brown-out Reset has occurred. Note that BOR is also set after Power-on Reset.

0= A Brown-out Reset has not occurred

POR: Power-on Reset Flag bit

1= A Power-up Reset has occurred

0= A Power-up Reset has not occurred

Note:

All of the Reset status bits may be set or cleared in software. Setting one of these bits in software

does not cause a device Reset.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 52

Preliminary

PIC24FJ128GA FAMILY

TABLE 5-1:

RESET FLAG BIT OPERATION

Setting Event

Flag Bit

Clearing Event

TRAPR (RCON<15>)

IOPR (RCON<14>)

EXTR (RCON<7>)

SWR (RCON<6>)

WDTO (RCON<4>)

SLEEP (RCON<3>)

IDLE (RCON<2>)

BOR (RCON<1>)

POR (RCON<0>)

Trap conflict event

POR

Illegal opcode or uninitialized W register access

MCLR Reset

RESETinstruction

WDT time-out

PWRSAVinstruction, POR

PWRSAV #SLEEPinstruction

PWRSAV #IDLEinstruction

POR, BOR

POR

—

POR

—

Note: All Reset flag bits may be set or cleared by the user software.

5.1

Clock Source Selection at Reset

5.2

Device Reset Times

If clock switching is enabled, the system clock source

at device Reset is chosen as shown in Table 5-2. If

clock switching is disabled, the system clock source is

always selected according to the oscillator Configura-

tion bits. Refer to 7.0 “Oscillator Configuration” for

further details.

The Reset times for various types of device Reset are

summarized in Table 5-3. Note that the system Reset

signal, SYSRST, is released after the POR and PWRT

delay times expire.

The time that the device actually begins to execute

code will also depend on the system oscillator delays,

which include the Oscillator Start-up Timer (OST) and

the PLL lock time. The OST and PLL lock times occur

in parallel with the applicable SYSRST delay times.

TABLE 5-2:

OSCILLATOR SELECTION vs.

TYPE OF RESET (CLOCK

SWITCHING ENABLED)

The FSCM delay determines the time at which the

FSCM begins to monitor the system clock source after

the SYSRST signal is released.

Reset Type

Clock Source Determinant

POR

BOR

Oscillator Configuration Bits

(FNOSC2:FNOSC0)

MCLR

WDTR

SWR

COSC Control bits

(OSCCON<14:12>)

Preliminary

DS39747C-page 53

PIC24FJ128GA FAMILY

TABLE 5-3:

Reset Type

POR

RESET DELAY TIMES FOR VARIOUS DEVICE RESETS

System Clock

Delay

FSCM

Delay

Clock Source

SYSRST Delay

Notes

1, 2, 3

EC, FRC, FRCDIV, LPRC TPOR + TSTARTUP + TRST

—

TFSCM

—

ECPLL, FRCPLL

XT, HS, SOSC

XTPLL, HSPLL

EC, FRC, FRCDIV, LPRC

ECPLL, FRCPLL

XT, HS, SOSC

XTPLL, HSPLL

Any Clock

TPOR + TSTARTUP + TRST

TLOCK

TOST

1, 2, 3, 5, 6

1, 2, 3, 4, 6

TPOR + TSTARTUP + TRST TOST + TLOCK

1, 2, 3, 4, 5, 6

BOR

TSTARTUP + TRST

TRST

—

2, 3

TLOCK

TFSCM

—

2, 3, 5, 6

TOST

2, 3, 4, 6

TOST + TLOCK

2, 3, 4, 5, 6

MCLR

WDT

—

3

Any Clock

TRST

—

Software

Any clock

TRST

—

Illegal Opcode Any Clock

Uninitialized W Any Clock

TRST

—

TRST

—

Trap Conflict

Any Clock

TRST

—

Note 1: TPOR = Power-on Reset delay (10 μs nominal).

2: TSTARTUP = TVREG (10 μs nominal) if on-chip regulator enabled or TPWRT (64 ms nominal) if on-chip

regulator disabled.

3: TRST = Internal state Reset time (20 μs nominal).

4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the

oscillator clock to the system.

5: TLOCK = PLL lock time (20 μs nominal).

6: TFSCM = Fail-Safe Clock Monitor delay (100 μs nominal).

5.2.1

POR AND LONG OSCILLATOR

START-UP TIMES

5.2.2

FAIL-SAFE CLOCK MONITOR

(FSCM) AND DEVICE RESETS

The oscillator start-up circuitry and its associated delay

timers are not linked to the device Reset delays that

occur at power-up. Some crystal circuits (especially

low-frequency crystals) will have a relatively long

start-up time. Therefore, one or more of the following

conditions is possible after SYSRST is released:

If the FSCM is enabled, it will begin to monitor the sys-

tem clock source when SYSRST is released. If a valid

clock source is not available at this time, the device will

automatically switch to the FRC oscillator and the user

can switch to the desired crystal oscillator in the Trap

Service Routine.

• The oscillator circuit has not begun to oscillate.

• The Oscillator Start-up Timer has NOT expired (if

a crystal oscillator is used).

• The PLL has not achieved a LOCK (if PLL is used).

The device will not begin to execute code until a valid

clock source has been released to the system. There-

fore, the oscillator and PLL start-up delays must be

considered when the Reset delay time must be known.

DS39747C-page 54

Preliminary

PIC24FJ128GA FAMILY

5.2.2.1

FSCM Delay for Crystal and PLL

Clock Sources

5.3

Special Function Register Reset

States

When the system clock source is provided by a crystal

oscillator and/or the PLL, a small delay, TFSCM, will

automatically be inserted after the POR and PWRT

delay times. The FSCM will not begin to monitor the

system clock source until this delay expires. The FSCM

delay time is nominally 100 μs and provides additional

time for the oscillator and/or PLL to stabilize. In most

cases, the FSCM delay will prevent an oscillator failure

trap at a device Reset when the PWRT is disabled.

Most of the Special Function Registers (SFRs) associ-

ated with the PIC24 CPU and peripherals are reset to a

particular value at a device Reset. The SFRs are

grouped by their peripheral or CPU function and their

Reset values are specified in each section of this manual.

The Reset value for each SFR does not depend on the

type of Reset, with the exception of four registers. The

Reset value for the Reset Control register, RCON, will

depend on the type of device Reset. The Reset value

for the Oscillator Control register, OSCCON, will

depend on the type of Reset and the programmed val-

ues of the oscillator Configuration bits in the FOSC

Device Configuration register (see Table 5-2). The

RCFGCAL and EECON1 registers are only affected by

a POR.

Preliminary

DS39747C-page 55

PIC24FJ128GA FAMILY

NOTES:

DS39747C-page 56

Preliminary

PIC24FJ128GA FAMILY

6.1.1

ALTERNATE INTERRUPT VECTOR

TABLE

6.0

INTERRUPT CONTROLLER

The PIC24 interrupt controller reduces the numerous

peripheral interrupt request signals to a single interrupt

request signal to the PIC24 CPU. It has the following

features:

The Alternate Interrupt Vector Table (AIVT) is located

after the IVT as shown in Figure 6-1. Access to the

AIVT is provided by the ALTIVT control bit

(INTCON2<15>). If the ALTIVT bit is set, all interrupt

and exception processes will use the alternate vectors

instead of the default vectors. The alternate vectors are

organized in the same manner as the default vectors.

• Up to 8 processor exceptions and software traps

• 7 user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• A unique vector for each interrupt or exception

source

The AIVT supports emulation and debugging efforts by

providing a means to switch between an application

and a support environment without requiring the inter-

rupt vectors to be reprogrammed. This feature also

enables switching between applications for evaluation

of different software algorithms at run time. If the AIVT

is not needed, the AIVT should be programmed with

the same addresses used in the IVT.

• Fixed priority within a specified user priority level

• Alternate Interrupt Vector Table (AIVT) for debug

support

• Fixed interrupt entry and return latencies

6.1

Interrupt Vector Table

The Interrupt Vector Table (IVT) is shown in Figure 6-1.

The IVT resides in program memory, starting at location

000004h. The IVT contains 126 vectors, consisting of 8

non-maskable trap vectors, plus up to 118 sources of

interrupt. In general, each interrupt source has its own

vector. Each interrupt vector contains a 24-bit wide

address. The value programmed into each interrupt

vector location is the starting address of the associated

Interrupt Service Routine (ISR).

6.2

Reset Sequence

A device Reset is not a true exception because the

interrupt controller is not involved in the Reset process.

The PIC24 device clears its registers in response to a

Reset which forces the PC to zero. The microcontroller

then begins program execution at location 000000h.

The user programs a GOTO instruction at the Reset

address, which redirects program execution to the

appropriate start-up routine.

Interrupt vectors are prioritized in terms of their natural

priority; this is linked to their position in the vector table.

All other things being equal, lower addresses have a

higher natural priority. For example, the interrupt asso-

ciated with vector 0 will take priority over interrupts at

any other vector address.

Note: Any unimplemented or unused vector

locations in the IVT and AIVT should be

programmed with the address of a default

interrupt handler routine that contains a

RESETinstruction.

PIC24FJ128GA family devices implement non-

maskable traps and unique interrupts. These are

summarized in Table 6-1 and Table 6-2.

Preliminary

DS39747C-page 57

PIC24FJ128GA FAMILY

FIGURE 6-1:

PIC24 INTERRUPT VECTOR TABLE

Reset – GOTOInstruction

Reset – GOTOAddress

Reserved

000000h

000002h

000004h

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

Interrupt Vector 0

Interrupt Vector 1

—

000014h

—

Interrupt Vector 52

Interrupt Vector 53

Interrupt Vector 54

—

00007Ch

00007Eh

000080h

Interrupt Vector Table (IVT)⁽¹⁾

—

Interrupt Vector 116

Interrupt Vector 117

Reserved

0000FCh

0000FEh

000100h

000102h

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

Interrupt Vector 0

Interrupt Vector 1

—

000114h

—

Alternate Interrupt Vector Table (AIVT)⁽¹⁾

Interrupt Vector 52

Interrupt Vector 53

Interrupt Vector 54

—

00017Ch

00017Eh

000180h

—

Interrupt Vector 116

Interrupt Vector 117

Start of Code

0001FEh

000200h

Note 1: See Table 6-2 for the Interrupt Vector list.

TABLE 6-1:

TRAP VECTOR DETAILS

IVT Address

Vector Number

AIVT Address

Trap Source

0

1

2

3

4

5

6

7

000004h

000006h

000008h

00000Ah

00000Ch

00000Eh

000010h

000012h

000104h

000106h

000108h

00010Ah

00010Ch

00010Eh

000110h

0001172h

Reserved

Oscillator Failure

Address Error

Stack Error

Math Error

Reserved

DS39747C-page 58

Preliminary

PIC24FJ128GA FAMILY

TABLE 6-2:

IMPLEMENTED INTERRUPT VECTORS

Interrupt Bit Locations

Enable

Vector

Number

AIVT

Address

Interrupt Source

IVT Address

Flag

Priority

ADC1 Conversion Done

Comparator Event

CRC Generator

External Interrupt 0

External Interrupt 1

External Interrupt 2

External Interrupt 3

External Interrupt 4

I2C1 Master Event

I2C1 Slave Event

I2C2 Master Event

I2C2 Slave Event

Input Capture 1

Input Capture 2

Input Capture 3

Input Capture 4

Input Capture 5

Input Change Notification

Output Compare 1

Output Compare 2

Output Compare 3

Output Compare 4

Output Compare 5

Parallel Master Port

Real-Time Clock/Calendar

SPI1 Error

13

18

67

0

00002Eh

000038h

00009Ah

000014h

00003Ch

00004Eh

00007Eh

000080h

000036h

000034h

000078h

000076h

000016h

00001Eh

00005Eh

000060h

000062h

00003Ah

000018h

000020h

000046h

000048h

000066h

00006Eh

000090h

000026h

000028h

000054h

000056h

00001Ah

000022h

000024h

00004Ah

00004Ch

000096h

00002Ah

00002Ch

000098h

000050h

000052h

00012Eh

000138h

00019Ah

000114h

00013Ch

00014Eh

00017Eh

000180h

000136h

000034h

000178h

000176h

000116h

00011Eh

00015Eh

000160h

000162h

00013Ah

000118h

000120h

000146h

000148h

000166h

00016Eh

000190h

000126h

000128h

000154h

000156h

00011Ah

000122h

000124h

00014Ah

00014Ch

000196h

00012Ah

00012Ch

000198h

000150h

000152h

IFS0<13>

IFS1<2>

IFS4<3>

IFS0<0>

IFS1<4>

IFS1<13>

IFS3<5>

IFS3<6>

IFS1<1>

IFS1<0>

IFS3<2>

IFS3<1>

IFS0<1>

IFS0<5>

IFS2<5>

IFS2<6>

IFS2<7>

IFS1<3>

IFS0<2>

IFS0<6>

IFS1<9>

IFS1<10>

IFS2<9>

IFS2<13>

IFS3<14>

IFS0<9>

IFS0<10>

IFS2<0>

IFS2<1>

IFS0<3>

IFS0<7>

IFS0<8>

IFS1<11>

IFS1<12>

IFS4<1>

IFS0<11>

IFS0<12>

IFS4<2>

IFS1<14>

IFS1<15>

IEC0<13>

IEC1<2>

IEC4<3>

IEC0<0>

IEC1<4>

IEC1<13>

IEC3<5>

IEC3<6>

IEC1<1>

IEC1<0>

IEC3<2>

IEC3<1>

IEC0<1>

IEC0<5>

IEC2<5>

IEC2<6>

IEC2<7>

IEC1<3>

IEC0<2>

IEC0<6>

IEC1<9>

IEC1<10>

IEC2<9>

IEC2<13>

IEC3<13>

IEC0<9>

IEC0<10>

IEC0<0>

IEC2<1>

IEC0<3>

IEC0<7>

IEC0<8>

IEC1<11>

IEC1<12>

IEC4<1>

IEC0<11>

IEC0<12>

IEC4<2>

IEC1<14>

IEC1<15>

IPC3<6:4>

IPC4<10:8>

IPC16<14:12>

IPC0<2:0>

20

29

53

54

17

16

50

49

1

IPC5<2:0>

IPC7<6:4>

IPC13<6:4>

IPC13<10:8>

IPC4<6:4>

IPC4<2:0>

IPC12<10:8>

IPC12<6:4>

IPC0<6:4>

5

IPC1<6:4>

37

38

39

19

2

IPC9<6:4>

IPC9<10:8>

IPC9<14:12>

IPC4<14:12>

IPC0<10:8>

IPC1<10:8>

IPC6<6:4>

6

25

26

41

45

62

9

IPC6<10:8>

IPC10<6:4>

IPC11<6:4>

IPC15<10:8>

IPC2<6:4>

SPI1 Event

10

32

33

3

IPC2<10:8>

IPC8<2:0>

SPI2 Error

SPI2 Event

IPC8<6:4>

Timer1

IPC0<14:12>

IPC1<14:12>

IPC2<2:0>

Timer2

7

Timer3

8

Timer4

27

28

65

11

12

66

30

31

IPC6<14:12>

IPC7<2:0>

Timer5

UART1 Error

IPC16<6:4>

IPC2<14:12>

IPC3<2:0>

UART1 Receiver

UART1 Transmitter

UART2 Error

IPC16<10:8>

IPC7<10:8>

IPC7<14:12>

UART2 Receiver

UART2 Transmitter

Preliminary

DS39747C-page 59

PIC24FJ128GA FAMILY

The interrupt sources are assigned to the IFSx, IECx

and IPCx registers in the same sequence that they are

listed in Table 6-2. For example, the INT0 (External

Interrupt 0) is shown as having a vector number and a

natural order priority of 0. Thus, the INT0IF status bit is

found in IFS0<0>, the enable bit in IEC0<0> and the

priority bits in the first position of IPC0 (IPC0<2:0>).

6.3

Interrupt Control and Status

Registers

The PIC24FJ128GA family devices implement a total

of 28 registers for the interrupt controller:

• INTCON1

• INTCON2

Although they are not specifically part of the interrupt

control hardware, two of the CPU control registers con-

tain bits that control interrupt functionality. The CPU

STATUS register (SR) contains the IPL2:IPL0 bits

(SR<7:5>). These indicate the current CPU interrupt

priority level. The user may change the current CPU

priority level by writing to the IPL bits.

• IFS0 through IFS4

• IEC0 through IEC4

• IPC0 through IPC14, and IPC16

Global interrupt control functions are controlled from

INTCON1 and INTCON2. INTCON1 contains the Inter-

rupt Nesting Disable (NSTDIS) bit, as well as the

control and status flags for the processor trap sources.

The INTCON2 register controls the external interrupt

request signal behavior and the use of the Alternate

Interrupt Vector Table.

The CORCON register contains the IPL3 bit, which

together with IPL2:IPL0, also indicates the current CPU

priority level. IPL3 is a read-only bit so that trap events

cannot be masked by the user software.

The IFS registers maintain all of the interrupt request

flags. Each source of interrupt has a status bit which is

set by the respective peripherals, or external signal,

and is cleared via software.

All interrupt registers are described in Register 6-1

through Register 6-30, in the following pages.

The IEC registers maintain all of the interrupt enable

bits. These control bits are used to individually enable

interrupts from the peripherals or external signals.

The IPC registers are used to set the interrupt priority

level for each source of interrupt. Each user interrupt

source can be assigned to one of eight priority levels.

DS39747C-page 60

Preliminary

PIC24FJ128GA FAMILY

REGISTER 6-1:

Upper Byte:

SR: STATUS REGISTER (IN CPU)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0

DC

—

bit 15

bit 8

Lower Byte:

R/W-0

IPL2^(1,2)

R/W-0

IPL1^(1,2)

R/W-0

IPL0^(1,2)

R-0

RA

R/W-0

N

R/W-0

OV

R/W-0

C

Z

bit 7

bit 0

bit 7-5

IPL2:IPL0: CPU Interrupt Priority Level Status bits^(1,2)

111= CPU interrupt priority level is 7 (15). User interrupts disabled.

110= CPU interrupt priority level is 6 (14)

101= CPU interrupt priority level is 5 (13)

100= CPU interrupt priority level is 4 (12)

011= CPU interrupt priority level is 3 (11)

010= CPU interrupt priority level is 2 (10)

001= CPU interrupt priority level is 1 (9)

000= CPU interrupt priority level is 0 (8)

Note 1: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority

level. The value in parentheses indicates the IPL if IPL3 = 1.

2: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

REGISTER 6-2:

Upper Byte:

CORCON: CORE CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

U-0

—

U-0

—

U-0

—

R/C-0

IPL3⁽¹⁾

R/W-0

PSV

U-0

—

bit 7

bit 0

bit 3

IPL3: CPU Interrupt Priority Level Status bit⁽¹⁾

1= CPU interrupt priority level is greater than 7; peripheral interrupts are disabled

0= CPU interrupt priority level is 7 or less

Note 1: The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority

level.

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 61

PIC24FJ128GA FAMILY

REGISTER 6-3:

Upper Byte:

INTCON1: INTERRUPT CONTROL REGISTER 1

R/W-0

NSTDIS

bit 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 8

Lower Byte:

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

MATHERR ADDRERR STKERR OSCFAIL

bit 7

bit 0

bit 15

NSTDIS: Interrupt Nesting Disable bit

1= Interrupt nesting is disabled

0= Interrupt nesting is enabled

bit 14-5 Unimplemented: Read as ‘0’

bit 4

bit 3

bit 2

bit 1

bit 0

MATHERR: Arithmetic Error Trap Status bit

1= Overflow trap has occurred

0= Overflow trap has not occurred

ADDRERR: Address Error Trap Status bit

1= Address error trap has occurred

0= Address error trap has not occurred

STKERR: Stack Error Trap Status bit

1= Stack error trap has occurred

0= Stack error trap has not occurred

OSCFAIL: Oscillator Failure Trap Status bit

1= Oscillator failure trap has occurred

0= Oscillator failure trap has not occurred

Unimplemented: Read as ‘0’

.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

DS39747C-page 62

Preliminary

PIC24FJ128GA FAMILY

REGISTER 6-4:

Upper Byte:

INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-0

R-0

DISI

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

ALTIVT

bit 15

bit 8

Lower Byte:

U-0

—

U-0

—

U-0

—

R/W-0

INT1EP

R/W-0

INT4EP

INT3EP

INT2EP

INT0EP

bit 7

bit 0

bit 15

bit 14

ALTIVT: Enable Alternate Interrupt Vector Table bit

1= Use alternate vector table

0= Use standard (default) vector table

DISI: DISIInstruction Status bit

1= DISIinstruction is active

0= DISIis not active

bit 13-5 Unimplemented: Read as ‘0’

bit 4

bit 3

bit 2

bit 1

bit 0

INT4EP: External Interrupt 4 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

INT3EP: External Interrupt 3 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 63

PIC24FJ128GA FAMILY

REGISTER 6-5:

Upper Byte:

IFS0: INTERRUPT FLAG STATUS REGISTER 0

U-0

—

U-0

R/W-0

AD1IF

R/W-0

SPI1IF

R/W-0

T3IF

—

U1TXIF

U1RXIF

SPF1IF

bit 15

bit 8

Lower Byte:

R/W-0

T2IF

R/W-0

OC2IF

R/W-0

IC2IF

U-0

—

R/W-0

T1IF

R/W-0

OC1IF

R/W-0

IC1IF

R/W-0

INT0IF

bit 7

bit 0

bit 15,14 Unimplemented: Read as ‘0’

bit 13

bit 12

bit 11

bit 10

bit 9

AD1IF: A/D Conversion Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U1TXIF: UART1 Transmitter Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U1RXIF: UART1 Receiver Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPI1IF: SPI1 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPF1IF: SPI1 Fault Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8

T3IF: Timer3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 7

T2IF: Timer2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 6

OC2IF: Output Compare Channel 2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 5

IC2IF: Input Capture Channel 2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 4

bit 3

Unimplemented: Read as ‘0’

T1IF: Timer1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 2

bit 1

bit 0

OC1IF: Output Compare Channel 1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

IC1IF: Input Capture Channel 1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT0IF: External Interrupt 0 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 64

Preliminary

PIC24FJ128GA FAMILY

REGISTER 6-6:

Upper Byte:

IFS1: INTERRUPT FLAG STATUS REGISTER 1

R/W-0

U2RXIF

R/W-0

INT2IF

R/W-0

T5IF

R/W-0

T4IF

R/W-0

OC4IF

R/W-0

OC3IF

U-0

—

U2TXIF

bit 15

bit 8

Lower Byte:

U-0

—

U-0

—

U-0

—

R/W-0

INT1IF

R/W-0

CNIF

R/W-0

CMIF

R/W-0

MI2C1IF

R/W-0

SI2C1IF

bit 7

bit 0

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

U2TXIF: UART2 Transmitter Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U2RXIF: UART2 Receiver Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT2IF: External Interrupt 2 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T5IF: Timer5 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T4IF: Timer4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

OC4IF: Output Compare Channel 4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

OC3IF: Output Compare Channel 3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8-5

bit 4

Unimplemented: Read as ‘0’

INT1IF: External Interrupt 1 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 3

bit 2

bit 1

bit 0

CNIF: Input Change Notification Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

CMIF: Comparator Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

MI2C1IF: Master I2C1 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 65

PIC24FJ128GA FAMILY

REGISTER 6-7:

Upper Byte:

IFS2: INTERRUPT FLAG STATUS REGISTER 2

U-0

—

U-0

R/W-0

PMPIF

U-0

—

U-0

—

U-0

—

R/W-0

OC5IF

U-0

—

bit 15

bit 8

Lower Byte:

R/W-0

IC5IF

R/W-0

IC4IF

R/W-0

IC3IF

U-0

—

U-0

—

U-0

—

R/W-0

SPI2IF

R/W-0

SPF2IF

bit 7

bit 0

bit 15-14 Unimplemented: Read as ‘0’

bit 13

PMPIF: Parallel Master Port Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 12-10 Unimplemented: Read as ‘0’

bit 9

OC5IF: Output Compare Channel 5 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8

bit 7

Unimplemented: Read as ‘0’

IC5IF: Input Capture Channel 5 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 6

bit 5

IC4IF: Input Capture Channel 4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

IC3IF: Input Capture Channel 3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 4-2

bit 1

Unimplemented: Read as ‘0’

SPI2IF: SPI2 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 0

SPI2IF: SPI2 Fault Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 66

Preliminary

PIC24FJ128GA FAMILY

REGISTER 6-8:

Upper Byte:

IFS3: INTERRUPT FLAG STATUS REGISTER 3

U-0

—

R/W-0

RTCIF

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

R/W-0

INT4IF

R/W-0

INT3IF

U-0

—

U-0

—

R/W-0

MI2C2IF

R/W-0

SI2C2IF

U-0

—

bit 7

bit 0

bit 15

bit 14

Unimplemented: Read as ‘0’

RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 13-7 Unimplemented: Read as ‘0’

bit 6

INT4IF: External Interrupt 4 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 5

INT3IF: External Interrupt 3 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 4-3

bit 2

Unimplemented: Read as ‘0’

MI2C2IF: Master I2C2 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 1

SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 0

Unimplemented: Read as ‘0’

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 67

PIC24FJ128GA FAMILY

REGISTER 6-9:

Upper Byte:

IFS4: INTERRUPT FLAG STATUS REGISTER 4

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CRCIF

R/W-0

U2ERIF

R/W-0

U1ERIF

U-0

—

bit 7

bit 0

bit 15-4 Unimplemented: Read as ‘0’

bit 3

bit 2

bit 1

bit 0

CRCIF: CRC Generator Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U2ERIF: UART2 Error Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U1ERIF: UART1 Error Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

Unimplemented: Read as ‘0’

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 68

Preliminary

PIC24FJ128GA FAMILY

REGISTER 6-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0

Upper Byte:

U-0

—

U-0

—

R/W-0

AD1IE

R/W-0

T3IE

U1TXIE

U1RXIE

SPI1IE

SPF1IE

bit 15

bit 8

Lower Byte:

R/W-0

T2IE

R/W-0

OC2IE

R/W-0

IC2IE

U-0

—

R/W-0

T1IE

R/W-0

OC1IE

R/W-0

IC1IE

R/W-0

INT0IE

bit 7

bit 0

bit 15-14 Unimplemented: Read as ‘0’

bit 13

bit 12

bit 11

bit 10

bit 9

AD1IE: A/D Conversion Complete Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

U1TXIE: UART1 Transmitter Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

U1RXIE: UART1 Receiver Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

SPI1IE: SPI1 Transfer Complete Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

SPF1IE: SPI1 Fault Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 8

T3IE: Timer3 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 7

T2IE: Timer2 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 6

OC2IE: Output Compare Channel 2 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 5

IC2IE: Input Capture Channel 2 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 4

bit 3

Unimplemented: Read as ‘0’

T1IE: Timer1 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 2

bit 1

bit 0

OC1IE: Output Compare Channel 1 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

IC1IE: Input Capture Channel 1 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

INT0IE: External Interrupt 0 Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 69

PIC24FJ128GA FAMILY

REGISTER 6-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1

Upper Byte:

R/W-0

T5IE

R/W-0

T4IE

R/W-0

OC4IE

R/W-0

OC3IE

U-0

—

U2TXIE

U2RXIE

INT2IE

bit 15

bit 8

Lower Byte:

U-0

—

U-0

—

U-0

—

R/W-0

INT1IE

R/W-0

CNIE

R/W-0

CMIE

R/W-0

MI2C1IE

R/W-0

SI2C1IE

bit 7

bit 0

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

U2TXIE: UART2 Transmitter Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

U2RXIE: UART2 Receiver Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

INT2IE: External Interrupt 2 Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

T5IE: Timer5 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

T4IE: Timer4 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

OC4IE: Output Compare Channel 4 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

OC3IE: Output Compare Channel 3 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 8-5

bit 4

Unimplemented: Read as ‘0’

INT1IE: External Interrupt 1 Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 3

bit 2

bit 1

bit 0

CNIE: Input Change Notification Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

CMIE: Comparator Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

MI2C1IE: Master I2C1 Event Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

SI2C1IE: Slave I2C1 Event Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 70

Preliminary

PIC24FJ128GA FAMILY

REGISTER 6-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2

Upper Byte:

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

OC5IE

U-0

—

PMPIE

bit 15

bit 8

Lower Byte:

R/W-0

IC5IE

R/W-0

IC4IE

R/W-0

IC3IE

U-0

—

U-0

—

U-0

—

R/W-0

SPI2IE

R/W-0

SPF2IE

bit 7

bit 0

bit 15-14 Unimplemented: Read as ‘0’

bit 13

PMPIE: Parallel Master Port Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 12-10 Unimplemented: Read as ‘0’

bit 9

OC5IE: Output Compare Channel 5 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 8

bit 7

Unimplemented: Read as ‘0’

IC5IE: Input Capture Channel 5 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 6

bit 5

IC4IE: Input Capture Channel 4 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

IC3IE: Input Capture Channel 3 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 4-2

bit 1

Unimplemented: Read as ‘0’

SPI2IE: SPI2 Event Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 0

SPF2IE: SPI2 Fault Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 71

PIC24FJ128GA FAMILY

REGISTER 6-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3

Upper Byte:

U-0

—

R/W-0

RTCIE

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0

MI2C2IE

R/W-0

SI2C2IE

U-0

—

INT4IE

INT3IE

bit 7

bit 0

bit 15

bit 14

Unimplemented: Read as ‘0’

RTCIE: Real-Time Clock/Calendar Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 13-7 Unimplemented: Read as ‘0’

bit 6

INT4IE: External Interrupt 4 Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 5

INT3IE: External Interrupt 3 Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 4-3

bit 2

Unimplemented: Read as ‘0’

MI2C2IE: Master I2C2 Event Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 1

SI2C2IE: Slave I2C2 Event Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 0

Unimplemented: Read as ‘0’

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 72

Preliminary

PIC24FJ128GA FAMILY

REGISTER 6-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4

Upper Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

U2ERIE

R/W-0

U1ERIE

U-0

—

CRCIE

bit 7

bit 0

bit 15-4 Unimplemented: Read as ‘0’

bit 3

bit 2

CRCIE: CRC Generator Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

U2ERIE: UART2 Error Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 1

bit 0

U1ERIE: UART1 Error Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 73

PIC24FJ128GA FAMILY

REGISTER 6-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0

Upper Byte:

U-0

—

R/W-1

T1IP2

R/W-0

T1IP1

R/W-0

T1IP0

U-0

—

R/W-1

R/W-0

OC1IP2

OC1IP1

OC1IP0

bit 15

bit 8

Lower Byte:

U-0

—

R/W-1

IC1IP2

R/W-0

IC1IP1

R/W-0

IC1IP0

U-0

—

R/W-1

INT0IP2

R/W-0

INT0IP1

R/W-0

INT0IP0

bit 7

bit 0

bit 15

Unimplemented: Read as ‘0’

bit 14-12 T1IP2:T1IP0: Timer1 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8 OC1IP2:OC1IP0: Output Compare Channel 1 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC1IP2:IC1IP0: Input Capture Channel 1 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

INT0IP2:INT0IP0: External Interrupt 0 Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 74

Preliminary

PIC24FJ128GA FAMILY

REGISTER 6-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1

Upper Byte:

U-0

—

R/W-1

T2IP2

R/W-0

T2IP1

R/W-0

T2IP0

U-0

—

R/W-1

R/W-0

OC2IP2

OC2IP1

OC2IP0

bit 15

bit 8

Lower Byte:

U-0

—

R/W-1

IC2IP2

R/W-0

IC2IP1

R/W-0

IC2IP0

U-0

—

U-0

—

U-0

—

bit 7

bit 0

bit 15

Unimplemented: Read as ‘0’

bit 14-12 T2IP2:T2IP0: Timer2 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8 OC2IP2:OC2IP0: Output Compare Channel 2 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC2IP2:IC2IP0: Input Capture Channel 2 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 75

PIC24FJ128GA FAMILY

REGISTER 6-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2

Upper Byte:

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

U1RXIP2 U1RXIP1 U1RXIP0

SPI1IP2

SPI1IP1

SPI1IP0

bit 15

bit 8

Lower Byte:

U-0

—

R/W-1

R/W-0

SPF1IP0

U-0

—

R/W-1

T3IP2

R/W-0

T3IP1

R/W-0

T3IP0

SPF1IP2

SPF1IP1

bit 7

bit 0

bit 15

Unimplemented: Read as ‘0’

bit 14-12 U1RXIP2:U1RXIP0: UART1 Receiver Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8 SPI1IP2:SPI1IP0: SPI1 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

SPF1IP2:SPF1IP0: SPI1 Fault Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

T3IP2:T3IP0: Timer3 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 76

Preliminary

PIC24FJ128GA FAMILY

REGISTER 6-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3

Upper Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

U1TXIP2

R/W-0

U1TXIP1

R/W-0

U1TXIP0

bit 0

AD1IP2

AD1IP1

AD1IP0

bit 7

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4

AD1IP2:AD1IP0: A/D Conversion Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

U1TXIP2:U1TXIP0: UART1 Transmitter Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 77

PIC24FJ128GA FAMILY

REGISTER 6-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4

Upper Byte:

U-0

—

R/W-1

CNIP2

R/W-0

CNIP1

R/W-0

CNIP0

U-0

—

R/W-1

CMIP2

R/W-0

CMIP1

R/W-0

CMIP0

bit 15

bit 8

Lower Byte:

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

SI2C1P2

R/W-0

SI2C1P1

R/W-0

SI2C1P0

bit 0

MI2C1P2 MI2C1P1 MI2C1P0

bit 7

bit 15

Unimplemented: Read as ‘0’

bit 14-12 CNIP2:CNIP0: Input Change Notification Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8 CMIP2:CMIP0: Comparator Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

MI2C1P2:MI2C1P0: Master I2C1 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

SI2C1P2:SI2C1P0: Slave I2C1 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 78

Preliminary

PIC24FJ128GA FAMILY

REGISTER 6-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5

Upper Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

INT1IP2

R/W-0

INT1IP1

R/W-0

INT1IP0

bit 7

bit 0

bit 15-3 Unimplemented: Read as ‘0’

bit 2-0

INT1IP2:INT1IP0: External Interrupt 1 Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 79

PIC24FJ128GA FAMILY

REGISTER 6-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6

Upper Byte:

U-0

—

R/W-1

T4IP2

R/W-0

T4IP1

R/W-0

T4IP0

U-0

—

R/W-1

R/W-0

OC4IP2

OC4IP1

OC4IP0

bit 15

bit 8

Lower Byte:

U-0

—

R/W-1

OC3IP2

R/W-0

OC3IP0

U-0

—

U-0

—

U-0

—

OC3IP1

—

bit 7

bit 0

bit 15

Unimplemented: Read as ‘0’

bit 14-12 T4IP2:T4IP0: Timer4 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8 OC4IP2:OC4IP0: Output Compare Channel 4 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

OC3IP2:OC3IP0: Output Compare Channel 3 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 80

Preliminary

PIC24FJ128GA FAMILY

REGISTER 6-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7

Upper Byte:

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

U2TXIP2 U2TXIP1 U2TXIP0

U2RXIP2 U2RXIP1 U2RXIP0

bit 8

bit 15

Lower Byte:

U-0

—

R/W-1

R/W-0

INT2IP0

U-0

—

R/W-1

T5IP2

R/W-0

T5IP1

R/W-0

T51P0

INT2IP2

INT2IP1

bit 7

bit 0

bit 15

Unimplemented: Read as ‘0’

bit 14-12 U2TXIP2:U2TXIP0: UART2 Transmitter Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8 U2RXIP2:U2RXIP0: UART2 Receiver Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

INT2IP2:INT2IP0: External Interrupt 2 Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

T5IP2:T5IP0: Timer5 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 81

PIC24FJ128GA FAMILY

REGISTER 6-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8

Upper Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

R/W-1

R/W-0

SPI2IP1

R/W-0

SPI2IP0

U-0

—

R/W-1

SPF2IP2

R/W-0

SPF2IP1

R/W-0

SPF2IP0

bit 0

SPI2IP2

bit 7

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4

SPI2IP2:SPI2IP0: SPI2 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

SPF2IP2:SPF2IP0: SPI2 Fault Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 82

Preliminary

PIC24FJ128GA FAMILY

REGISTER 6-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9

Upper Byte:

U-0

—

R/W-1

IC5IP2

R/W-0

IC5IP1

R/W-0

IC5IP0

U-0

—

R/W-1

IC4IP2

R/W-0

IC4IP1

R/W-0

IC4IP0

bit 15

bit 8

Lower Byte:

U-0

—

R/W-1

IC3IP2

R/W-0

IC3IP1

R/W-0

IC3IP0

U-0

—

U-0

—

U-0

—

bit 7

bit 0

bit 15

Unimplemented: Read as ‘0’

bit 14-12 IC5IP2:IC5IP0: Input Capture Channel 5 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8 IC4IP2:IC4IP0: Input Capture Channel 4 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC3IP2:IC3IP0: Input Capture Channel 3 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 83

PIC24FJ128GA FAMILY

REGISTER 6-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10

Upper Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

R/W-1

R/W-0

OC5IP1

R/W-0

OC5IP0

U-0

—

U-0

—

U-0

—

OC5IP2

—

bit 7

bit 0

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4

OC5IP2:OC5IP0: Output Compare Channel 5 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

REGISTER 6-26: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11

Upper Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

R/W-1

R/W-0

PMPIP1

R/W-0

PMPIP0

U-0

—

U-0

—

U-0

—

PMPIP2

—

bit 7

bit 0

bit 15-7 Unimplemented: Read as ‘0’

bit 6-4

PMPIP2:PMPIP0: Parallel Master Port Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 84

Preliminary

PIC24FJ128GA FAMILY

REGISTER 6-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12

Upper Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

MI2C2P2 MI2C2P1 MI2C2P0

bit 8

bit 15

Lower Byte:

U-0

—

R/W-1

R/W-0

SI2C2P1

R/W-0

SI2C2P0

U-0

—

U-0

—

U-0

—

U-0

—

SI2C2P2

bit 7

bit 0

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 MI2C2P2:MI2C2P0: Master I2C2 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

SI2C2P2:SI2C2P0: Slave I2C2 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 85

PIC24FJ128GA FAMILY

REGISTER 6-28: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13

Upper Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

INT4IP2

INT4IP1

INT4IP0

bit 15

bit 8

Lower Byte:

U-0

—

R/W-1

R/W-0

INT3IP1

R/W-0

INT3IP0

U-0

—

U-0

—

INT3IP2

—

bit 7

bit 0

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 INT4IP2:INT4IP0: External Interrupt 4 Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

INT3IP2:INT3IP0: External Interrupt 3 Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 86

Preliminary

PIC24FJ128GA FAMILY

REGISTER 6-29: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15

Upper Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

RTCIP2

RTCIP1

RTCIP0

bit 15

bit 8

Lower Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 RTCIP2:RTCIP0: Real-Time Clock/Calendar Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7-0

Unimplemented: Read as ‘0’

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 87

PIC24FJ128GA FAMILY

REGISTER 6-30: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16

Upper Byte:

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

CRCIP2

CRCIP1

CRCIP0

U2ERIP2 U2ERIP1 U2ERIP0

bit 8

bit 15

Lower Byte:

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U1ERIP2 U1ERIP1 U1ERIP0

bit 7

bit 0

bit 15

Unimplemented: Read as ‘0’

bit 14-12 CRCIP2:CRCIP0: CRC Generator Error Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8 U2ERIP2:U2ERIP0: UART2 Error Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

U1ERIP2:U1ERIP0: UART1 Error Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 88

Preliminary

PIC24FJ128GA FAMILY

6.4.3

TRAP SERVICE ROUTINE

6.4

Interrupt Setup Procedures

A Trap Service Routine (TSR) is coded like an ISR,

except that the appropriate trap status flag in the

INTCON1 register must be cleared to avoid re-entry

into the TSR.

6.4.1

INITIALIZATION

To configure an interrupt source:

1. Set the NSTDIS Control bit (INTCON1<15>) if

nested interrupts are not desired.

6.4.4

INTERRUPT DISABLE

2. Select the user-assigned priority level for the

interrupt source by writing the control bits in the

appropriate IPCx Control register. The priority

level will depend on the specific application and

type of interrupt source. If multiple priority levels

are not desired, the IPCx register control bits for

all enabled interrupt sources may be

programmed to the same non-zero value.

All user interrupts can be disabled using the following

procedure:

1. Push the current SR value onto the software

stack using the PUSHinstruction.

2. Force the CPU to priority level 7 by inclusive

ORing the value OEh with SRL.

To enable user interrupts, the POPinstruction may be

Note: At a device Reset, the IPC registers are

initialized, such that all user interrupt

sources are assigned to priority level 4.

used to restore the previous SR value.

Note that only user interrupts with a priority level of 7 or

less can be disabled. Trap sources (level 8-15) cannot

be disabled.

3. Clear the interrupt flag status bit associated with

the peripheral in the associated IFSx Status

register.

The DISIinstruction provides a convenient way to dis-

able interrupts of priority levels 1-6 for a fixed period of

time. Level 7 interrupt sources are not disabled by the

DISI instruction.

4. Enable the interrupt source by setting the inter-

rupt enable control bit associated with the

source in the appropriate IECx Control register.

6.4.2

INTERRUPT SERVICE ROUTINE

The method that is used to declare an ISR and initialize

the IVT with the correct vector address will depend on

the programming language (i.e., ‘C’ or assembler) and

the language development toolsuite that is used to

develop the application. In general, the user must clear

the interrupt flag in the appropriate IFSx register for the

source of interrupt that the ISR handles. Otherwise, the

ISR will be re-entered immediately after exiting the rou-

tine. If the ISR is coded in assembly language, it must

be terminated using a RETFIE instruction to unstack

the saved PC value, SRL value and old CPU priority

level.

Preliminary

DS39747C-page 89

PIC24FJ128GA FAMILY

NOTES:

DS39747C-page 90

Preliminary

PIC24FJ128GA FAMILY

• On-chip 4x PLL to boost internal operating frequency

on select internal and external oscillator sources

7.0

OSCILLATOR

CONFIGURATION

• Software-controllable switching between various

clock sources

Note:

This data sheet summarizes the features

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

• Software-controllable postscaler for selective

clocking of CPU for system power savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and permits safe application recovery

or shutdown

The oscillator system for PIC24FJ128GA family

devices has the following features:

A simplified diagram of the oscillator system is shown

in Figure 7-1.

• A total of four external and internal oscillator options

as clock sources, providing 11 different clock modes

FIGURE 7-1:

PIC24FJ128GA FAMILY CLOCK DIAGRAM

PIC24FJ128GA Family

Primary Oscillator

CLKO

XT, HS, EC

CLKDIV<14:12>

OSC1

OSC2

XTPLL, HSPLL,

ECPLL, FRCPLL

CPU

8 MHz

4 MHz

4 x PLL

FRC

Oscillator

FRCDIV

Peripherals

8 MHz

(Nominal)

CLKDIV<10:8>

FRC

LPRC

Oscillator

31 kHz (Nominal)

Secondary Oscillator

SOSC

SOSCO

SOSCI

SOSCEN

Enable

Oscillator

Clock Control Logic

Fail-Safe

Clock

Monitor

WDT, PWRT

Clock Source Option

for other Modules

The primary oscillator and FRC sources have the

option of using the internal 4x PLL. The frequency of

the FRC clock source can optionally be reduced by the

programmable clock divider. The selected clock source

generates the processor and peripheral clock sources.

7.1

CPU Clocking Scheme

The system clock source can be provided by one of

four sources:

• Primary Oscillator (POSC) on the OSC1 and

OSC2 pins

The processor clock source is divided by two to pro-

duce the internal instruction cycle clock, FCY. In this

document, the instruction cycle clock is also denoted

by FOSC/2. The internal instruction cycle clock, FOSC/2,

can be provided on the OSC2 I/O pin for some

operating modes of the primary oscillator.

• Secondary Oscillator (SOSC) on the SOSCI and

SOSCO pins

• Fast Internal RC (FRC) Oscillator

• Low-Power Internal RC (LPRC) Oscillator

Preliminary

DS39747C-page 91

PIC24FJ128GA FAMILY

The secondary oscillator, or one of the internal

oscillators, may be chosen by programming these bit

locations.

7.2

Oscillator Configuration

The oscillator source (and operating mode) that is

used at a device Power-on Reset event is selected

using Configuration bit settings. The oscillator Config-

uration bit settings are located in the Configuration

registers in the program memory (refer to

Section 23.1 “Configuration Bits” for further

details.) The Primary Oscillator Configuration bits,

POSCMD1:POSCMD0 (Configuration Word 2<1:0>),

and the Initial Oscillator Select Configuration bits,

The Configuration bits allow users to choose between

the various clock modes, shown in Table 7-1.

7.2.1

CLOCK SWITCHING MODE

CONFIGURATION BITS

The FCKSM Configuration bits (Configuration Word 2<7:6>)

are used to jointly configure device clock switching and

the Fail-Safe Clock Monitor (FSCM). Clock switching is

enabled only when FCKSM1 is programmed (‘0’). The

FSCM is enabled only when FCKSM1:FCKSM0 are

both programmed (‘00’).

FNOSC2:FNOSC0

(Configuration Word 2<10:8>),

select the oscillator source that is used at a Power-on

Reset. The FRC primary oscillator with postscaler

(FRCDIV) is the default (unprogrammed) selection.

TABLE 7-1:

CONFIGURATION BIT VALUES FOR CLOCK SELECTION

POSCMD1:

POSCMD0

FNOSC2:

FNOSC0

Oscillator Mode

Oscillator Source

Note

1, 2

Fast RC Oscillator with Postscaler

(FRCDIV)

Internal

00

111

(Reserved)

Internal

00

110

101

100

1

Low-Power RC Oscillator (LPRC)

Secondary (Timer1) Oscillator

(SOSC)

Secondary

Primary Oscillator (HS) with PLL

Module (HSPLL)

Primary

10

01

00

011

Primary Oscillator (XT) with PLL

Module (ECPLL)

Primary Oscillator (EC) with PLL

Module (XTPLL)

Primary Oscillator (HS)

Primary Oscillator (XT)

Primary Oscillator (EC)

Primary

Internal

10

01

00

010

001

Fast RC Oscillator with PLL Module

(FRCPLL)

1

Fast RC Oscillator (FRC)

Internal

00

000

Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.

2: This is the default oscillator mode for an unprogrammed (erased) device.

The Clock Divider register (Register 7-2) controls the

features associated with Doze mode, as well as the

postscaler for the FRC oscillator.

7.3

Control Registers

The operation of the oscillator is controlled by three

Special Function Registers:

The FRC Oscillator Tune register (Register 7-3) allows

the user to fine tune the FRC oscillator over a range of

approximately ±12%. Each bit increment or decrement

changes the factory calibrated frequency of the FRC

oscillator by a fixed amount.

• OSCCON

• CLKDIV

• OSCTUN

The OSCCON register (Register 7-1) is the main con-

trol register for the oscillator. It controls clock source

switching, and allows the monitoring of clock sources.

DS39747C-page 92

Preliminary

PIC24FJ128GA FAMILY

REGISTER 7-1:

Upper Byte:

OSCCON: OSCILLATOR CONTROL REGISTER

U-0

—

R-0

COSC2

R-0

U-0

—

R/W-x⁽¹⁾

NOSC2

R/W-x⁽¹⁾

NOSC1

R/W-x⁽¹⁾

NOSC0

COSC1

COSC0

bit 15

bit 8

Lower Byte:

R/SO-0

CLKLOCK

bit 7

U-0

—

R-0⁽²⁾

LOCK

U-0

—

R/CO-0

CF

U-0

—

R/W-0

SOSCEN

R/W-0

OSWEN

bit 0

bit 15

Unimplemented: Read as ‘0’

bit 14-12 COSC2:COSC0: Current Oscillator Selection bits

111= Fast RC Oscillator with Postscaler (FRCDIV)

110= Reserved

101= Low-Power RC Oscillator (LPRC)

100= Secondary Oscillator (SOSC)

011= Primary Oscillator with PLL module (HSPLL, ECPLL)

010= Primary Oscillator (XT, HS, EC)

001= Fast RC Oscillator with postscaler and PLL module (FRCPLL)

000= Fast RC Oscillator (FRC)

bit 11

Unimplemented: Read as ‘0’

bit 10-8 NOSC2:NOSC0: New Oscillator Selection bits

111= Fast RC Oscillator with Postscaler (FRCDIV)

110= Reserved

101= Low-Power RC Oscillator (LPRC)

100= Secondary Oscillator (SOSC)

011= Primary Oscillator with PLL module (HSPLL, ECPLL)

010= Primary Oscillator (XT, HS, EC)

001= Fast RC Oscillator with postscaler and PLL module (FRCPLL)

000= Fast RC Oscillator (FRC)

bit 7

CLKLOCK: Clock Selection Lock Enabled bit

If FSCM is enabled (FCKSM1 = 1):

1= Clock and PLL selections are locked

0= Clock and PLL selections are not locked and may be modified by setting the OSWEN bit

If FSCM is disabled (FCKSM1 = 0):

Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.

bit 6

bit 5

Unimplemented: Read as ‘0’

LOCK: PLL Lock Status bit

1= PLL module is in lock or PLL module start-up timer is satisfied

0= PLL module is out of lock, PLL start-up timer is running or PLL is disabled

bit 4

bit 3

Unimplemented: Read as ‘0’

CF: Clock Fail Detect bit

1= FSCM has detected a clock failure

0= No clock failure has been detected

bit 2

bit 1

Unimplemented: Read as ‘0’

SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit

1= Enable secondary oscillator

0= Disable secondary oscillator

bit 0

OSWEN: Oscillator Switch Enable bit

1= Initiate an oscillator switch to clock source specified by NOSC2:NOSC0 bits

0= Oscillator switch is complete

Note 1: Reset values for these bits are determined by the FNOSC Configuration bits.

2: Also resets to ‘0’ during any valid clock switch, or whenever a non-PLL Clock mode is selected.

Legend: U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

CO = Clear-Only bit

‘0’ = Bit is cleared

SO = Set-Only bit

x = Bit is unknown

Preliminary

DS39747C-page 93

PIC24FJ128GA FAMILY

REGISTER 7-2:

Upper Byte:

CLKDIV: CLOCK DIVIDER REGISTER

R/W-0

ROI

R/W-0

DOZE2

R/W-0

R/W-1

DOZE1

DOZE0

DOZEN⁽¹⁾RCDIV2

RCDIV1

RCDIV0

bit 15

bit 8

Lower Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

bit 15

ROI: Recover on Interrupt bit

1= Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1

0= Interrupts have no effect on the DOZEN bit

bit 14-12 DOZE2:DOZE0: CPU Peripheral Clock Ratio Select bits

111= 1:128

110= 1:64

101= 1:32

100= 1:16

011= 1:8

010= 1:4

001= 1:2

000= 1:1

bit 11

DOZEN: DOZE Enable bit⁽¹⁾

1= DOZE2:DOZE0 bits specify the CPU peripheral clock ratio

0= CPU peripheral clock ratio set to 1:1

Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.

bit 10-8 RCDIV2:RCDIV0: FRC Postscaler Select bits

111= 31.25 kHz (divide by 256)

110= 125 kHz (divide by 64)

101= 250 kHz (divide by 32)

100= 500 kHz (divide by 16)

011= 1 MHz (divide by 8)

010= 2 MHz (divide by 4)

001= 4 MHz (divide by 2)

000= 8 MHz (divide by 1)

bit 7-0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 94

Preliminary

PIC24FJ128GA FAMILY

REGISTER 7-3:

Upper Byte:

OSCTUN: FRC OSCILLATOR TUNE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

U-0

—

R/W-0

TUN5

R/W-0

TUN4

R/W-0

TUN3

R/W-0

TUN2

R/W-0

TUN1

R/W-0

TUN0

bit 7

bit 0

bit 15-6 Unimplemented: Read as ‘0’

bit 5-0

TUN5:TUN0: FRC Oscillator Tuning bits

011111= Maximum frequency deviation

011110=

•

000001=

000000= Center frequency, oscillator is running at factory calibrated frequency

111111=

•

100001=

100000= Minimum frequency deviation

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

7.4.1

ENABLING CLOCK SWITCHING

7.4

Clock Switching Operation

To enable clock switching, the FCKSM1 Configuration

bit in the Configuration register must be programmed to

‘0’. (Refer to Section 23.1 “Configuration Bits” for

further details.) If the FCKSM1 Configuration bit is

unprogrammed (‘1’), the clock switching function and

Fail-Safe Clock Monitor function are disabled. This is

the default setting.

With few limitations, applications are free to switch

between any of the four clock sources (POSC, SOSC,

FRC and LPRC) under software control and at any

time. To limit the possible side effects that could result

from this flexibility, PIC24 devices have a safeguard

lock built into the switching process.

The NOSC control bits (OSCCON<10:8>) do not

control the clock selection when clock switching is dis-

abled. However, the COSC bits (OSCCON<14:12>)

will reflect the clock source selected by the FNOSC

Configuration bits.

Note:

Primary Oscillator mode has three

different submodes (XT, HS and EC)

which are determined by the POSCMD

Configuration bits. While an application

can switch to and from Primary Oscillator

mode in software, it cannot switch

between the different primary submodes

without reprogramming the device.

The OSWEN control bit (OSCCON<0>) has no effect

when clock switching is disabled. It is held at ‘0’ at all

times.

Preliminary

DS39747C-page 95

PIC24FJ128GA FAMILY

A recommended code sequence for a clock switch

includes the following:

7.4.2

OSCILLATOR SWITCHING

SEQUENCE

1. Disable interrupts during the OSCCON register

unlock and write sequence.

At a minimum, performing a clock switch requires this

basic sequence:

2. Execute the unlock sequence for the OSCCON

high byte, by writing 78h and 9Ah to

1. If

desired,

read

the

COSC

bits

(OSCCON<14:12>), to determine the current

oscillator source.

OSCCON<15:8>

instructions.

in

two

back-to-back

2. Perform the unlock sequence to allow a write to

the OSCCON register high byte.

3. Write new oscillator source to the NOSC control

bits in the instruction immediately following the

unlock sequence.

3. Write the appropriate value to the NOSC control

bits (OSCCON<10:8>) for the new oscillator

source.

4. Execute the unlock sequence for the OSCCON

low byte by writing 46h and 57h to

OSCCON<7:0> in two back-to-back instructions.

4. Perform the unlock sequence to allow a write to

the OSCCON register low byte.

5. Set the OSWEN bit in the instruction immediately

following the unlock sequence.

5. Set the OSWEN bit to initiate the oscillator

switch.

6. Continue to execute code that is not clock

sensitive (optional).

Once the basic sequence is completed, the system

clock hardware responds automatically as follows:

7. Invoke an appropriate amount of software delay

(cycle counting) to allow the selected oscillator

and/or PLL to start and stabilize.

1. The clock switching hardware compares the

COSC status bits with the new value of the

NOSC control bits. If they are the same, then the

clock switch is a redundant operation. In this

case, the OSWEN bit is cleared automatically

and the clock switch is aborted.

8. Check to see if OSWEN is ‘0’. If it is, the switch

was successful. If OSWEN is still set, then

check the LOCK bit to determine cause of

failure.

2. If a valid clock switch has been initiated, the

LOCK (OSCCON<5>) and CF (OSCCON<3>)

status bits are cleared.

The core sequence for unlocking the OSCCON register

and initiating a clock switch is shown in Example 7-1.

3. The new oscillator is turned on by the hardware

if it is not currently running. If a crystal oscillator

must be turned on, the hardware will wait until

the OST expires. If the new source is using the

PLL, then the hardware waits until a PLL lock is

detected (LOCK = 1).

EXAMPLE 7-1:

BASIC CODE SEQUENCE

FOR CLOCK SWITCHING

;Place the new oscillator selection in W0

;OSCCONH (high byte) Unlock Sequence

MOV

MOV.b

#OSCCONH, w1

#0x78, w2

#0x9A, w3

w2, [w1]

4. The hardware waits for 10 clock cycles from the

new clock source and then performs the clock

switch.

w3, [w1]

;Set new oscillator selection

MOV.b WREG, OSCCONH

;OSCCONL (low byte) unlock sequence

5. The hardware clears the OSWEN bit to indicate a

successful clock transition. In addition, the NOSC

bit values are transferred to the COSC status bits.

MOV

MOV.b

MOV

MOV.b

#OSCCONL, w1

#0x01, w0

#0x46, w2

#0x57, w3

w2, [w1]

6. The old clock source is turned off at this time,

with the exception of LPRC (if WDT or FSCM

are enabled) or SOSC (if SOSCEN remains

set).

w3, [w1]

Note 1: The processor will continue to execute

code throughout the clock switching

sequence. Timing sensitive code should

not be executed during this time.

;Start oscillator switch operation

MOV.b w0, [w1]

2: Direct clock switches between any

Primary Oscillator mode with PLL and

FRCPLL mode are not permitted. This

applies to clock switches in either direc-

tion. In these instances, the application

must switch to FRC mode as a transition

clock source between the two PLL

modes.

DS39747C-page 96

Preliminary

PIC24FJ128GA FAMILY

8.0

POWER-SAVING FEATURES

Note: SLEEP_MODE and IDLE_MODE are con-

stants defined in the assembler include

file for the selected device.

Note:

This data sheet summarizes the features

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

Sleep and Idle modes can be exited as a result of an

enabled interrupt, WDT time-out or a device Reset.

When the device exits these modes, it is said to

“wake-up”.

The PIC24FJ128GA family of devices provide the ability

to manage power consumption by selectively managing

clocking to the CPU and the peripherals. In general, a

lower clock frequency and a reduction in the number of

circuits being clocked constitutes lower consumed

power. All PIC24F devices manage power consumption

in four different ways:

8.2.1

SLEEP MODE

Sleep mode has these features:

• The system clock source is shut down. If an

on-chip oscillator is used, it is turned off.

• The device current consumption will be reduced

to a minimum provided that no I/O pin is sourcing

current.

• Clock frequency

• Instruction-based Sleep and Idle modes

• Software-controlled Doze mode

• Selective peripheral control in software

• The Fail-Safe Clock Monitor does not operate

during Sleep mode since the system clock source

is disabled.

Combinations of these methods can be used to selec-

tively tailor an application’s power consumption, while

still maintaining critical application features, such as

timing sensitive communications.

• The LPRC clock will continue to run in Sleep

mode if the WDT is enabled.

• The WDT, if enabled, is automatically cleared

prior to entering Sleep mode.

8.1

Clock Frequency and Clock

Switching

• Some device features or peripherals may

continue to operate in Sleep mode. This includes

items such as the input change notification on the

I/O ports, or peripherals that use an external clock

input. Any peripheral that requires the system

clock source for its operation will be disabled in

Sleep mode.

PIC24F devices allow for a wide range of clock

frequencies to be selected under application control. If

the system clock configuration is not locked, users can

choose low-power or high-precision oscillators by simply

changing the NOSC Configuration bits. The process of

changing a system clock during operation, as well as

limitations to the process, are discussed in more detail in

Section 7.0 “Oscillator Configuration”.

The device will wake-up from Sleep mode on any of the

these events:

• On any interrupt source that is individually

enabled

8.2

Instruction-Based Power-Saving

Modes

• On any form of device Reset

• On a WDT time-out

On wake-up from Sleep, the processor will restart with

the same clock source that was active when Sleep

mode was entered.

PIC24F devices have two special power-saving modes

that are entered through the execution of a special

PWRSAVinstruction. Sleep mode stops clock operation

and halts all code execution; Idle mode halts the CPU

and code execution, but allows peripheral modules to

continue operation. The assembly syntax of the

PWRSAVinstruction is shown in Example 8-1.

EXAMPLE 8-1:

PWRSAV INSTRUCTION SYNTAX

PWRSAV

#SLEEP_MODE

#IDLE_MODE

; Put the device into SLEEP mode

; Put the device into IDLE mode

Preliminary

DS39747C-page 97

PIC24FJ128GA FAMILY

It is also possible to use Doze mode to selectively

reduce power consumption in event driven applica-

tions. This allows clock sensitive functions, such as

synchronous communications, to continue without

interruption while the CPU idles, waiting for something

to invoke an interrupt routine. Enabling the automatic

return to full-speed CPU operation on interrupts is

enabled by setting the ROI bit (CLKDIV<15>). By

default, interrupt events have no effect on Doze mode

operation.

8.2.2

IDLE MODE

Idle mode has these features:

• The CPU will stop executing instructions.

• The WDT is automatically cleared.

• The system clock source remains active. By

default, all peripheral modules continue to operate

normally from the system clock source, but can

also be selectively disabled (see Section 8.4

“Selective Peripheral Module Control”).

• If the WDT or FSCM is enabled, the LPRC will

also remain active.

8.4

Selective Peripheral Module

Control

The device will wake from Idle mode on any of these

events:

Idle and Doze modes allow users to substantially

reduce power consumption by slowing or stopping the

CPU clock. Even so, peripheral modules still remain

clocked and thus consume power. There may be cases

where the application needs what these modes do not

provide: the allocation of power resources to CPU

processing with minimal power consumption from the

peripherals.

• Any interrupt that is individually enabled.

• Any device Reset.

• A WDT time-out.

On wake-up from Idle, the clock is re-applied to the

CPU and instruction execution begins immediately,

starting with the instruction following the PWRSAV

instruction, or the first instruction in the ISR.

PIC24F devices address this requirement by allowing

peripheral modules to be selectively disabled, reducing

or eliminating their power consumption. This can be

done with two control bits:

8.2.3

INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS

Any interrupt that coincides with the execution of a

PWRSAVinstruction will be held off until entry into Sleep

or Idle mode has completed. The device will then

wake-up from Sleep or Idle mode.

• The Peripheral Enable bit, generically named

“XXXEN”, located in the module’s main control

SFR.

• The Peripheral Module Disable (PMD) bit, generi-

cally named “XXXMD”, located in one of the PMD

control registers.

8.3

Doze Mode

Generally, changing clock speed and invoking one of

the power-saving modes are the preferred strategies

for reducing power consumption. There may be cir-

cumstances, however, where this is not practical. For

example, it may be necessary for an application to

maintain uninterrupted synchronous communication,

even while it is doing nothing else. Reducing system

clock speed may introduce communication errors,

Both bits have similar functions in enabling or disabling

its associated module. Setting the PMD bit for a module

disables all clock sources to that module, reducing its

power consumption to an absolute minimum. In this

state, the control and status registers associated with the

peripheral will also be disabled, so writes to those regis-

ters will have no effect and read values will be invalid.

Many peripheral modules have a corresponding PMD

bit.

while using

a

power-saving mode may stop

communications completely.

In contrast, disabling a module by clearing its XXXEN

bit disables its functionality, but leaves its registers

available to be read and written to. Power consumption

is reduced, but not by as much as the PMD bit does.

Most peripheral modules have an enable bit;

exceptions include Capture, Compare and RTCC.

Doze mode is a simple and effective alternative method

to reduce power consumption while the device is still

executing code. In this mode, the system clock contin-

ues to operate from the same source and at the same

speed. Peripheral modules continue to be clocked at the

same speed, while the CPU clock speed is reduced.

Synchronization between the two clock domains is

maintained, allowing the peripherals to access the SFRs

while the CPU executes code at a slower rate.

To achieve more selective power savings, peripheral

modules can also be selectively disabled when the

device enters Idle mode. This is done through the

control bit of the generic name format “XXXIDL”. By

default, all modules that can operate during Idle mode

will do so. Using the disable on Idle feature allows fur-

ther reduction of power consumption during Idle mode,

enhancing power savings for extremely critical power

applications.

Doze mode is enabled by setting the DOZEN bit

(CLKDIV<11>). The ratio between peripheral and core

clock speed is determined by the DOZE2:DOZE0 bits

(CLKDIV<14:12>). There are eight possible

configurations, from 1:1 to 1:256, with 1:1 being the

default.

DS39747C-page 98

Preliminary

PIC24FJ128GA FAMILY

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

a general purpose output pin is disabled. The I/O pin

may be read, but the output driver for the parallel port

bit will be disabled. If a peripheral is enabled, but the

peripheral is not actively driving a pin, that pin may be

driven by a port.

9.0

I/O PORTS

Note:

This data sheet summarizes the features

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

All of the device pins (except VDD, VSS, MCLR and

OSC1/CLKI) are shared between the peripherals and

the parallel I/O ports. All I/O input ports feature Schmitt

Trigger inputs for improved noise immunity.

All port pins have three registers directly associated

with their operation as digital I/O. The data direction

register (TRISx) determines whether the pin is an input

or an output. If the data direction bit is a ‘1’, then the pin

is an input. All port pins are defined as inputs after a

Reset. Reads from the latch (LATx), read the latch.

Writes to the latch, write the latch. Reads from the port

(PORTx), read the port pins, while writes to the port

pins, write the latch.

9.1

Parallel I/O (PIO) Ports

A parallel I/O port that shares a pin with a peripheral is,

in general, subservient to the peripheral. The periph-

eral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pin. The logic also prevents “loop through”, in

which a port’s digital output can drive the input of a

peripheral that shares the same pin. Figure 9-1 shows

how ports are shared with other peripherals and the

associated I/O pin to which they are connected.

Any bit and its associated data and control registers

that are not valid for a particular device will be

disabled. That means the corresponding LATx and

TRISx registers and the port pin will read as zeros.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is nevertheless

regarded as a dedicated port because there is no

other competing source of outputs. An example is the

INT4 pin.

FIGURE 9-1:

BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Peripheral Module

Output Multiplexers

Peripheral Input Data

Peripheral Module Enable

I/O

Peripheral Output Enable

Peripheral Output Data

1

Output Enable

0

1

PIO Module

Output Data

0

Read TRIS

Data Bus

WR TRIS

D

Q

I/O Pin

CK

TRIS Latch

D

Q

WR LAT +

WR Port

CK

Data Latch

Read LAT

Read Port

Input Data

Preliminary

DS39747C-page 99

PIC24FJ128GA FAMILY

9.1.1

OPEN-DRAIN CONFIGURATION

9.3

Input Change Notification

In addition to the PORT, LAT and TRIS registers for

data control, each port pin can also be individually con-

figured for either digital or open-drain output. This is

controlled by the Open-Drain Control register, ODCx,

associated with each port. Setting any of the bits con-

figures the corresponding pin to act as an open-drain

output.

The input change notification function of the I/O ports

allows the PIC24FJ128GA family of devices to gener-

ate interrupt requests to the processor in response to a

change-of-state on selected input pins. This feature is

capable of detecting input change-of-states even in

Sleep mode, when the clocks are disabled. Depending

on the device pin count, there are up to 22 external sig-

nals (CN0 through CN21) that may be selected

(enabled) for generating an interrupt request on a

change-of-state.

The open-drain feature allows the generation of

outputs higher than VDD (e.g., 5V) on any desired digi-

tal-only pins by using external pull-up resistors. The

maximum open-drain voltage allowed is the same as

the maximum VIH specification.

There are four control registers associated with the CN

module. The CNEN1 and CNEN2 registers contain the

interrupt enable control bits for each of the CN input

pins. Setting any of these bits enables a CN interrupt

for the corresponding pins.

9.2

Configuring Analog Port Pins

The use of the AD1PCFG and TRIS registers control

the operation of the A/D port pins. The port pins that are

desired as analog inputs must have their correspond-

ing TRIS bit set (input). If the TRIS bit is cleared (out-

put), the digital output level (VOH or VOL) will be

converted.

Each CN pin also has a weak pull-up connected to it.

The pull-ups act as a current source that is connected

to the pin, and eliminate the need for external resistors

when push button or keypad devices are connected.

The pull-ups are enabled separately using the CNPU1

and CNPU2 registers, which contain the control bits for

each of the CN pins. Setting any of the control bits

enables the weak pull-ups for the corresponding pins.

When reading the PORT register, all pins configured as

analog input channels will read as cleared (a low level).

Pins configured as digital inputs will not convert an

analog input. Analog levels on any pin that is defined as

a digital input (including the ANx pins) may cause the

input buffer to consume current that exceeds the

device specifications.

Note:

Pull-ups on change notification pins

should always be disabled whenever the

port pin is configured as a digital output.

9.2.1

I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically this instruction

would be a NOP.

EXAMPLE 9-1:

PORT WRITE/READ EXAMPLE

MOV

NOP

0xFF00, W0

W0, TRISBB

; Configure PORTB<15:8> as inputs

; and PORTB<7:0> as outputs

; Delay 1 cycle

btss PORTB, #13

; Next Instruction

DS39747C-page 100

Preliminary

PIC24FJ128GA FAMILY

Figure 10-1 presents a block diagram of the 16-bit

timer module.

10.0 TIMER1

Note:

This data sheet summarizes the features

To configure Timer1 for operation:

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

1. Set the TON bit (= 1).

2. Select the timer prescaler ratio using the

TCKPS1:TCKPS0 bits.

The Timer1 module is a 16-bit timer which can serve as

the time counter for the Real-Time Clock, or operate as

a free-running interval timer/counter. Timer1 can

operate in three modes:

3. Set the Clock and Gating modes using the TCS

and TGATE bits.

4. Set or clear the TSYNC bit to configure

synchronous or asynchronous operation.

• 16-bit Timer

5. Load the timer period value into the PR1

register.

• 16-bit Synchronous Counter

• 16-bit Asynchronous Counter

6. If interrupts are required, set the interrupt enable

bit, T1IE. Use the priority bits, T1IP2:T1IP0, to

set the interrupt priority.

Timer1 also supports these features:

• Timer gate operation

• Selectable prescaler settings

• Timer operation during CPU Idle and Sleep

modes

• Interrupt on 16-bit period register match or falling

edge of external gate signal

FIGURE 10-1:

16-BIT TIMER1 MODULE BLOCK DIAGRAM

TCKPS1:TCKPS0

TON

2

SOSCO/

1x

01

00

T1CK

Prescaler

1, 8, 64, 256

Gate

Sync

SOSCEN

SOSCI

TCY

TGATE

TCS

TGATE

1

0

Q

D

Set T1IF

CK

0

Reset

Equal

TMR1

Sync

1

TSYNC

Comparator

PR1

Preliminary

DS39747C-page 101

PIC24FJ128GA FAMILY

REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER

Upper Byte:

R/W-0

TON

U-0

—

R/W-0

TSIDL

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

R/W-0

TCKPS1

R/W-0

TCKPS0

U-0

—

R/W-0

TSYNC

R/W-0

TCS

U-0

—

TGATE

bit 7

bit 0

bit 15

TON: Timer1 On bit

1= Starts 16-bit Timer1

0= Stops 16-bit Timer1

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6

TGATE: Timer1 Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation enabled

0= Gated time accumulation disabled

bit 5-4

TCKPS1:TCKPS0: Timer1 Input Clock Prescale Select bits

11= 1:256

10= 1:64

01= 1:8

00= 1:1

bit 3

bit 2

Unimplemented: Read as ‘0’

TSYNC: Timer1 External Clock Input Synchronization Select bit

When TCS = 1:

1= Synchronize external clock input

0= Do not synchronize external clock input

When TCS = 0:

This bit is ignored.

bit 1

bit 0

TCS: Timer1 Clock Source Select bit

1= External clock from pin T1CK (on the rising edge)

0= Internal clock (FOSC/2)

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 102

Preliminary

PIC24FJ128GA FAMILY

To configure Timer2/3 or Timer4/5 for 32-bit operation:

11.0 TIMER2/3 AND TIMER4/5

1. Set the T32 bit (T2CON<3> or T4CON<3> = 1).

Note:

This data sheet summarizes the features

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

2. Select the prescaler ratio for Timer2 or Timer4

using the TCKPS1:TCKPS0 bits.

3. Set the Clock and Gating modes using the TCS

and TGATE bits.

The Timer2/3 and Timer4/5 modules are 32-bit timers,

which can also be configured as four independent 16-bit

timers with selectable operating modes.

4. Load the timer period value. PR3 (or PR5) will

contain the most significant word of the value,

while PR2 (or PR4) contains the least significant

word.

As a 32-bit timer, Timer2/3 and Timer4/5 operate in

three modes:

5. If interrupts are required, set the interrupt enable

bit T3IE or T5IE; use the priority bits,

T3IP2:T3IP0 or T5IP2:T5IP0, to set the interrupt

priority. Note that while Timer2 or Timer4 con-

trols the timer, the interrupt appears as a Timer3

or Timer5 interrupt.

• Two independent 16-bit timers (Timer2 and

Timer3) with all 16-bit operating modes (except

Asynchronous Counter mode)

• Single 32-bit Timer

• Single 32-bit Synchronous Counter

6. Set the TON bit (= 1).

They also support these features:

The timer value at any point is stored in the register

pair, TMR3:TMR2 (or TMR5:TMR4). TMR3 (TMR5)

always contains the most significant word of the count,

while TMR2 (TMR4) contains the least significant word.

• Timer gate operation

• Selectable prescaler settings

• Timer operation during Idle and Sleep modes

• Interrupt on a 32-bit period register match

• ADC Event Trigger (Timer4/5 only)

To configure any of the timers for individual 16-bit

operation:

1. Clear the T32 bit corresponding to that timer

(T2CON<3> for Timer2 and Timer3 or

T4CON<3> for Timer4 and Timer5).

Individually, all four of the 16-bit timers can function as

synchronous timers or counters. They also offer the

features listed above, except for the ADC Event

Trigger; this is implemented only with Timer5. The

operating modes and enabled features are determined

by setting the appropriate bit(s) in the T2CON, T3CON,

T4CON and T5CON registers. T2CON and T4CON are

shown in generic form in Register 11-1; T3CON and

T5CON are shown in Register 11-2.

2. Select the timer prescaler ratio using the

TCKPS1:TCKPS0 bits.

3. Set the Clock and Gating modes using the TCS

and TGATE bits.

4. Load the timer period value into the PRx register.

5. If interrupts are required, set the interrupt enable

bit, TxIE; use the priority bits, TxIP2:TxIP0, to

set the interrupt priority.

For 32-bit timer/counter operation, Timer2 and Timer4

are the least significant word; Timer3 and Timer4 are

the most significant word of the 32-bit timers.

6. Set the TON bit (TxCON<15> = 1).

Note:

For 32-bit operation, T3CON and T5CON

control bits are ignored. Only T2CON and

T4CON control bits are used for setup and

control. Timer2 and Timer4 clock and gate

inputs are utilized for the 32-bit timer

modules, but an interrupt is generated with

the Timer3 or Timer5 interrupt flags.

Preliminary

DS39747C-page 103

PIC24FJ128GA FAMILY

FIGURE 11-1:

TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM

TCKPS1:TCKPS0

2

TON

T2CK

(T4CK)

1x

01

00

Prescaler

1, 8, 64, 256

Gate

Sync

TCY

TGATE

TCS

1

0

Q

D

Set T3IF (T5IF)

Q

CK

PR3

PR2

(PR5)

(PR4)

ADC Event Trigger*

Equal

MSB

Comparator

LSB

TMR2

(TMR4)

TMR3

(TMR5)

Sync

Reset

16

Read TMR2 (TMR4)

Write TMR2 (TMR4)

16

TMR3HLD

(TMR5HLD)

Data Bus<15:0>

Note: The 32-bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are

respective to the T2CON and T4CON registers.

*

The ADC Event Trigger is available only on Timer4/5.

DS39747C-page 104

Preliminary

PIC24FJ128GA FAMILY

FIGURE 11-2:

TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM

TCKPS1:TCKPS0

2

TON

T2CK

(T4CK)

1x

Prescaler

1, 8, 64, 256

Gate

Sync

01

00

TGATE

TCS

TGATE

TCY

Q

D

1

0

Set T2IF (T4IF)

Q

CK

Reset

Equal

TMR2 (TMR4)

Sync

Comparator

PR2 (PR4)

FIGURE 11-3:

TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM

TCKPS1:TCKPS0

2

TON

T3CK

(T5CK)

1x

01

00

Sync

Prescaler

1, 8, 64, 256

TGATE

TCS

TGATE

TCY

Q

D

1

0

Set T3IF (T5IF)

CK

Reset

Equal

TMR3 (TMR5)

ADC Event Trigger*

Comparator

PR3 (PR5)

*

The ADC Event Trigger is available only on Timer4/5.

Preliminary

DS39747C-page 105

PIC24FJ128GA FAMILY

REGISTER 11-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER

Upper Byte:

R/W-0

TON

U-0

—

R/W-0

TSIDL

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

R/W-0

TCKPS1

R/W-0

TCKPS0

R/W-0

T32

U-0

—

R/W-0

U-0

—

TGATE

TCS

bit 7

bit 0

bit 15

TON: Timerx On bit

When TxCON<3> = 1:

1= Starts 32-bit Timerx/y

0= Stops 32-bit Timerx/y

When TxCON<3> = 0:

1= Starts 16-bit Timerx

0= Stops 16-bit Timerx

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6

TGATE: Timerx Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation enabled

0= Gated time accumulation disabled

bit 5-4

bit 3

TCKPS1:TCKPS0: Timer2 Input Clock Prescale Select bits

11= 1:256

10= 1:64

01= 1:8

00= 1:1

T32: 32-bit Timer Mode Select bit

1= Timerx and Timery form a single 32-bit timer

0= Timerx and Timery act as two 16-bit timers

Note:

In 32-bit mode, T3CON control bits do not affect 32-bit timer operation.

bit 2

bit 1

Unimplemented: Read as ‘0’

TCS: Timerx Clock Source Select bit

1= External clock from pin TxCK (on the rising edge)

0= Internal clock (FOSC/2)

bit 0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

DS39747C-page 106

Preliminary

PIC24FJ128GA FAMILY

REGISTER 11-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER

Upper Byte:

R/W-0

TON⁽¹⁾

U-0

—

R/W-0

TSIDL⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0

TCS⁽¹⁾

U-0

—

TGATE⁽¹⁾TCKPS1⁽¹⁾TCKPS0⁽¹⁾

bit 7

bit 0

bit 15

TON: Timery On bit⁽¹⁾

1= Starts 16-bit Timery

0= Stops 16-bit Timery

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit⁽¹⁾

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6

TGATE: Timery Gated Time Accumulation Enable bit⁽¹⁾

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation enabled

0= Gated time accumulation disabled

bit 5-4

TCKPS1:TCKPS0: Timery Input Clock Prescale Select bits⁽¹⁾

11= 1:256

10= 1:64

01= 1:8

00= 1:1

bit 3-2

bit 1

Unimplemented: Read as ‘0’

TCS: Timery Clock Source Select bit⁽¹⁾

1= External clock from pin TyCK (on the rising edge)

0= Internal clock (FOSC/2)

bit 0

Unimplemented: Read as ‘0’

Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery

operation; all timer functions are set through T2CON.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 107

PIC24FJ128GA FAMILY

NOTES:

DS39747C-page 108

Preliminary

PIC24FJ128GA FAMILY

12.0 INPUT CAPTURE

Note:

This data sheet summarizes the features

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

FIGURE 12-1:

INPUT CAPTURE BLOCK DIAGRAM

From 16-bit Timers

TMRx

TMRy

16

ICTMR

(ICxCON<7>)

1

0

Prescaler

Counter

(1, 4, 16)

FIFO

R/W

Logic

Edge Detection Logic

and

Clock Synchronizer

ICx pin

ICM<2:0>(ICxCON<2:0>)

3

Mode Select

ICOV, ICBNE(ICxCON<4:3>)

ICxBUF

ICI<1:0>

Interrupt

Logic

ICxCON

System Bus

Set Flag ICxIF

(in IFSn Register)

Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.

Preliminary

DS39747C-page 109

PIC24FJ128GA FAMILY

12.1 Input Capture Registers

REGISTER 12-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER

Upper Byte:

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

ICSIDL

bit 15

bit 8

Lower Byte:

R/W-0

ICI1

R/W-0

ICI0

R-0, HC

ICOV

R-0, HC

ICBNE

R/W-0

ICM2

R/W-0

ICM1

R/W-0

ICM0

ICTMR

bit 7

bit 0

bit 15-14 Unimplemented: Read as ‘0’

bit 13

ICSIDL: Input Capture x Module Stop in Idle Control bit

1= Input capture module will halt in CPU Idle mode

0= Input capture module will continue to operate in CPU Idle mode

bit 12-8 Unimplemented: Read as ‘0’

bit 7

ICTMR: Input Capture x Timer Select bit

1= TMR2 contents are captured on capture event

0= TMR3 contents are captured on capture event

Note:

Timer selections may vary. Refer to the device data sheet for details.

bit 6-5

ICI1:ICI0: Select Number of Captures per Interrupt bits

11= Interrupt on every fourth capture event

10= Interrupt on every third capture event

01= Interrupt on every second capture event

00= Interrupt on every capture event

bit 4

ICOV: Input Capture x Overflow Status Flag (Read-Only) bit

1= Input capture overflow occurred

0= No input capture overflow occurred

bit 3

ICBNE: Input Capture x Buffer Empty Status (Read-Only) bit

1= Input capture buffer is not empty, at least one more capture value can be read

0= Input capture buffer is empty

bit 2-0

ICM2:ICM0: Input Capture x Mode Select bits

111= Input capture functions as interrupt pin only when device is in Sleep or Idle mode

(rising edge detect only, all other control bits are not applicable)

110= Unused (module disabled)

101= Capture mode, every 16th rising edge

100= Capture mode, every 4th rising edge

011= Capture mode, every rising edge

010= Capture mode, every falling edge

001= Capture mode, every edge (rising and falling) – ICI<1:0> does not control interrupt generation

for this mode

000= Input capture module turned off

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

HS = Set in Hardware

‘0’ = Bit is cleared

HC = Cleared in Hardware

x = Bit is unknown

DS39747C-page 110

Preliminary

PIC24FJ128GA FAMILY

The output compare module does not have to be dis-

abled after the falling edge of the output pulse. Another

pulse can be initiated by rewriting the value of the

OCxCON register.

13.0 OUTPUT COMPARE

Note:

This data sheet summarizes the features

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

13.2 Setup for Continuous Output

Pulse Generation

13.1 Setup for Single Output Pulse

Generation

When the OCM control bits (OCxCON<2:0>) are set to

‘101’, the selected output compare channel initializes

the OCx pin to the low state and generates output

pulses on each and every compare match event.

When the OCM control bits (OCxCON<2:0>) are set to

‘100’, the selected output compare channel initializes

the OCx pin to the low state and generates a single out-

put pulse.

For the user to configure the module for the generation

of a continuous stream of output pulses, the following

steps are required (these steps assume the timer

source is initially turned off, but this is not a requirement

for the module operation):

To generate a single output pulse, the following steps

are required (these steps assume the timer source is

initially turned off, but this is not a requirement for the

module operation):

1. Determine the instruction clock cycle time. Take

into account the frequency of the external clock

to the timer source (if one is used) and the timer

prescaler settings.

1. Determine the instruction clock cycle time. Take

into account the frequency of the external clock

to the timer source (if one is used) and the timer

prescaler settings.

2. Calculate time to the rising edge of the output

pulse relative to the TMRy start value (0000h).

2. Calculate time to the rising edge of the output

pulse relative to the TMRy start value (0000h).

3. Calculate the time to the falling edge of the pulse,

based on the desired pulse width and the time to

the rising edge of the pulse.

3. Calculate the time to the falling edge of the pulse

based on the desired pulse width and the time to

the rising edge of the pulse.

4. Write the values computed in step 2 and 3

above into the Compare register, OCxR, and the

4. Write the values computed in steps 2 and 3

above into the Compare register, OCxR, and the

Secondary

Compare

register,

OCxRS,

Secondary

Compare

register,

OCxRS,

respectively.

5. Set Timer Period register, PRy, to value equal to

or greater than value in OCxRS, the Secondary

Compare register.

5. Set Timer Period register, PRy, to value equal to

or greater than value in OCxRS, the Secondary

Compare register.

6. Set the OCM bits to ‘101’ and the OCTSEL bit to

the desired timer source. The OCx pin state will

now be driven low.

6. Set the OCM bits to ‘100’ and the OCTSEL

(OCxCON<3>) bit to the desired timer source.

The OCx pin state will now be driven low.

7. Enable the compare time base by setting the TON

7. Set the TON (TyCON<15>) bit to ‘1’, which

(TyCON<15>) bit to ‘1’.

enables the compare time base to count.

8. Upon the first match between TMRy and OCxR,

the OCx pin will be driven high.

8. Upon the first match between TMRy and OCxR,

the OCx pin will be driven high.

9. When the compare time base, TMRy, matches

the Secondary Compare register, OCxRS, the

second and trailing edge (high-to-low) of the pulse

is driven onto the OCx pin.

9. When the incrementing timer, TMRy, matches the

Secondary Compare register, OCxRS, the

second and trailing edge (high-to-low) of the pulse

is driven onto the OCx pin. No additional pulses

are driven onto the OCx pin and it remains at low.

As a result of the second compare match event,

the OCxIF interrupt flag bit is set, which will

result in an interrupt if it is enabled, by setting

the OCxIE bit. For further information on periph-

eral interrupts, refer to Section 6.0 “Interrupt

Controller”.

10. As a result of the second compare match event,

the OCxIF interrupt flag bit set.

11. When the compare time base and the value in its

respective Period register match, the TMRy

register resets to 0x0000and resumes counting.

12. Steps 8 through 11 are repeated and a continuous

stream of pulses is generated, indefinitely. The

OCxIF flag is set on each OCxRS-TMRy compare

match event.

10. To initiate another single pulse output, change the

Timer and Compare register settings, if needed,

and then issue a write to set the OCM bits to ‘100’.

Disabling and re-enabling of the timer and clear-

ing the TMRy register are not required, but may

be advantageous for defining a pulse from a

known event time boundary.

Preliminary

DS39747C-page 111

PIC24FJ128GA FAMILY

EQUATION 13-1: CALCULATING THE PWM

13.3 Pulse-Width Modulation Mode

(1)

PERIOD

The following steps should be taken when configuring

the output compare module for PWM operation:

PWM Period = [(PRy) + 1] • TCY • (Timer Prescale Value)

where:

PWM Frequency = 1/[PWM Period]

1. Set the PWM period by writing to the selected

Timer Period register (PRy).

2. Set the PWM duty cycle by writing to the OCxRS

register.

Note 1: Based on TCY = FOSC/2, Doze mode and

PLL are disabled.

3. Write the OCxR register with the initial duty

cycle.

Note: A PRy value of N will produce a PWM

period of N + 1 time base count cycles. For

example, a value of 7 written into the PRy

register will yield a period consisting of

8 time base cycles.

4. Enable interrupts, if required, for the timer and

output compare modules. The output compare

interrupt is required for PWM Fault pin utiliza-

tion.

5. Configure the output compare module for one of

two PWM operation modes by writing to the Out-

13.3.2

PWM DUTY CYCLE

put

Compare

mode

bits

OCM<2:0>

The PWM duty cycle is specified by writing to the

OCxRS register. The OCxRS register can be written to

at any time, but the duty cycle value is not latched into

OCxR until a match between PRy and TMRy occurs

(i.e., the period is complete). This provides a double

buffer for the PWM duty cycle and is essential for glitch-

less PWM operation. In the PWM mode, OCxR is a

read-only register.

(OCxCON<2:0>).

6. Set the TMRy prescale value and enable the

time base by setting TON (TxCON<15>) = 1.

Note: The OCxR register should be initialized

before the output compare module is first

enabled. The OCxR register becomes a

Read-Only Duty Cycle register when the

module is operated in the PWM modes.

The value held in OCxR will become the

PWM duty cycle for the first PWM period.

The contents of the Duty Cycle Buffer

register, OCxRS, will not be transferred

into OCxR until a time base period match

occurs.

Some important boundary parameters of the PWM duty

cycle include:

• If the Duty Cycle register, OCxR, is loaded with

0000h, the OCx pin will remain low (0% duty cycle).

• If OCxR is greater than PRy (Timer Period register),

the pin will remain high (100% duty cycle).

• If OCxR is equal to PRy, the OCx pin will be low

for one time base count value and high for all

other count values.

13.3.1

PWM PERIOD

The PWM period is specified by writing to PRy, the

Timer Period register. The PWM period can be

calculated using Equation 13-1.

See Example 13-1 for PWM mode timing details.

Table 13-1 shows example PWM frequencies and

resolutions for a device operating at 10 MIPS.

(1)

EQUATION 13-2: CALCULATION FOR MAXIMUM PWM RESOLUTION

FCY

log₁₀

(

)

FPWM • (Timer Prescale Value)

bits

Maximum PWM Resolution (bits) =

log₁₀(2)

Note 1: Based on TCY = FOSC/2, Doze mode and PLL are disabled.

DS39747C-page 112

Preliminary

PIC24FJ128GA FAMILY

(1)

EXAMPLE 13-1:

PWM PERIOD AND DUTY CYCLE CALCULATIONS

1. Find the Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device

clock rate) and a Timer2 prescaler setting of 1:1.

TCY = 2/FOSC = 62.5 ns

PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 μs

PWM Period = (PR2 + 1) • TCY • (Timer 2 Prescale Value)

19.2 μs

PR2

= (PR2 + 1) • 62.5 ns • 1

= 306

2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:

PWM Resolution = log₁₀(FCY/FPWM)/log₁₀2) bits

= (log₁₀(16 MHz/52.08 kHz)/log₁₀2) bits

= 8.3 bits

Note 1: Based on TCY = FOSC/2, Doze mode and PLL are disabled.

(1)

TABLE 13-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)

PWM Frequency

7.6 Hz

61 Hz

122 Hz

977 Hz

3.9 kHz

31.3 kHz

125 kHz

Timer Prescaler Ratio

Period Register Value

Resolution (bits)

8

FFFFh

16

1

FFFFh

16

1

7FFFh

15

1

0FFFh

12

1

007Fh

7

1

001Fh

5

03FFh

10

Note 1: Based on TCY = FOSC/2, Doze mode and PLL are disabled.

(1)

TABLE 13-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)

PWM Frequency

30.5 Hz

244 Hz

488 Hz

3.9 kHz

15.6 kHz

125 kHz

500 kHz

Timer Prescaler Ratio

Period Register Value

Resolution (bits)

8

FFFFh

16

1

FFFFh

16

1

7FFFh

15

1

0FFFh

12

1

007Fh

7

1

001Fh

5

03FFh

10

Note 1: Based on TCY = FOSC/2, Doze mode and PLL are disabled.

FIGURE 13-1:

OUTPUT COMPARE MODULE BLOCK DIAGRAM

Set Flag bit

OCxIF⁽¹⁾

OCxRS⁽¹⁾

Output

Logic

OCxR⁽¹⁾

OCx⁽¹⁾

S

R

Q

Output Enable

3

OCM2:OCM0

Mode Select

OCFA or OCFB⁽²⁾

Comparator

0

OCTSEL

1

0

1

16

Period match signals

from time bases

(see Note 3).

TMR register inputs

from time bases

(see Note 3).

Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through 8.

2: OCFA pin controls OC1-OC4 channels. OCFB pin controls OC5-OC8 channels.

3: Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the time

bases associated with the module.

Preliminary

DS39747C-page 113

PIC24FJ128GA FAMILY

13.4 Output Compare Register

REGISTER 13-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER

Upper Byte:

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

OCSIDL

bit 15

bit 8

Lower Byte:

U-0

—

U-0

—

U-0

R-0 HC

OCFLT

R/W-0

OCM2

R/W-0

OCM1

R/W-0

OCM0

—

OCTSEL

bit 7

bit 0

bit 15-14 Unimplemented: Read as ‘0’

bit 13

OCSIDL: Stop Output Compare x in Idle Mode Control bit

1= Output Compare x will halt in CPU Idle mode

0= Output Compare x will continue to operate in CPU Idle mode

bit 12-5 Unimplemented: Read as ‘0’

bit 4

bit 3

OCFLT: PWM Fault Condition Status bit

1= PWM Fault condition has occurred (cleared in HW only)

0= No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111)

OCTSEL: Output Compare x Timer Select bit

1= Timer3 is the clock source for Output Compare x

0= Timer2 is the clock source for Output Compare x

Note: Refer to the device data sheet for specific time bases available to the output compare module.

bit 2-0

OCM2:OCM0: Output Compare x Mode Select bits

111= PWM mode on OCx, Fault pin enabled

110= PWM mode on OCx, Fault pin disabled

101= Initialize OCx pin low, generate continuous output pulses on OCx pin

100= Initialize OCx pin low, generate single output pulse on OCx pin

011= Compare event toggles OCx pin

010= Initialize OCx pin high, compare event forces OCx pin low

001= Initialize OCx pin low, compare event forces OCx pin high

000= Output compare channel is disabled

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

HS = Set in Hardware

‘0’ = Bit is cleared

HC = Cleared in Hardware

x = Bit is unknown

DS39747C-page 114

Preliminary

PIC24FJ128GA FAMILY

To set up the SPI module for the Standard Master mode

of operation:

14.0 SERIAL PERIPHERAL

INTERFACE (SPI)

1. If using interrupts:

Note:

This data sheet summarizes the features

a) Clear the SPIxIF bit in the respective IFSn

register.

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

b) Set the SPIxIE bit in the respective IECn

register.

The Serial Peripheral Interface (SPI) module is a syn-

chronous serial interface useful for communicating with

other peripheral or microcontroller devices. These

peripheral devices may be serial EEPROMs, shift reg-

isters, display drivers, A/D converters, etc. The SPI

module is compatible with Motorola’s SPI and SIOP

interfaces.

c) Write the SPIxIP bits in the respective IPCn

register to set the interrupt priority.

2. Write the desired settings to the SPIxCON

register with MSTEN (SPIxCON1<5>) = 1.

3. Clear the SPIROV bit (SPIxSTAT<6>).

4. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

The module supports operation in two buffer modes. In

Standard mode, data is shifted through a single serial

buffer. In Enhanced Buffer mode, data is shifted

through an 8-level FIFO buffer.

5. Write the data to be transmitted to the SPIxBUF

register. Transmission (and reception) will start

as soon as data is written to the SPIxBUF

register.

Note:

Do not perform read-modify-write opera-

tions (such as bit-oriented instructions) on

the SPIxBUF register, in either Standard or

Enhanced Buffer mode.

To set up the SPI module for the Standard Slave mode

of operation:

1. Clear the SPIxBUF register.

2. If using interrupts:

The module also supports a basic framed SPI protocol

while operating in either Master or Slave modes. A total

of four framed SPI configurations are supported.

a) Clear the SPIxIF bit in the respective IFSn

register.

b) Set the SPIxIE bit in the respective IECn

register.

The SPI serial interface consists of four pins:

• SDIx: Serial Data Input

c) Write the SPIxIP bits in the respective IPCn

register to set the interrupt priority.

• SDOx: Serial Data Output

• SCKx: Shift Clock Input or Output

3. Write the desired settings to the SPIxCON1 and

SPIxCON2

(SPIxCON1<5>) = 0.

registers

with

MSTEN

• SSx: Active-Low Slave Select or Frame

Synchronization I/O Pulse

4. Clear the SMP bit.

The SPI module can be configured to operate using 2,

3 or 4 pins. In the 3-pin mode, SSx is not used. In the

2-pin mode, both SDOx and SSx are not used.

5. If the CKE bit is set, then the SSEN bit

(SPIxCON1<7>) must be set to enable the SSx

pin.

A block diagram of the module is shown in Figure 14-1.

6. Clear the SPIROV bit (SPIxSTAT<6>).

Depending on the pin count, devices of the

PIC24FJ128GA family offer one or two SPI modules on

a single device.

7. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

Note: In this section, the SPI modules are

referred to together as SPIx or separately

as SPI1 and SPI2. Special Function Reg-

isters will follow a similar notation. For

example, SPIxCON refers to the control

register for the SPI1 or SPI2 module.

Preliminary

DS39747C-page 115

PIC24FJ128GA FAMILY

To set up the SPI module for the Enhanced Buffer

Master mode of operation:

To set up the SPI module for the Enhanced Buffer

Slave mode of operation:

1. If using interrupts:

1. Clear the SPIxBUF register.

2. If using interrupts:

a) Clear the SPIxIF bit in the respective IFSn

register.

• Clear the SPIxIF bit in the respective IFSn

register.

b) Set the SPIxIE bit in the respective IECn

register.

• Set the SPIxIE bit in the respective IECn

register.

c) Write the SPIxIP bits in the respective IPCn

register.

• Write the SPIxIP bits in the respective IPCn

register to set the interrupt priority.

2. Write the desired settings to the SPIxCON1 and

SPIxCON2

(SPIxCON1<5>) = 1.

3. Clear the SPIROV bit (SPIxSTAT<6>).

registers

with

MSTEN

3. Write the desired settings to the SPIxCON1 and

SPIxCON2

registers

with

MSTEN

(SPIxCON1<5>) = 0.

4. Select Enhanced Buffer mode by setting the

SPIBEN bit (SPIxCON2<0>).

4. Clear the SMP bit.

5. If the CKE bit is set, then the SSEN bit must be

set, thus enabling the SSx pin.

5. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

6. Clear the SPIROV bit (SPIxSTAT<6>).

6. Write the data to be transmitted to the SPIxBUF

register. Transmission (and reception) will start

as soon as data is written to the SPIxBUF

register.

7. Select Enhanced Buffer mode by setting the

SPIBEN bit (SPIxCON2<0>).

8. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

FIGURE 14-1:

SPI MODULE BLOCK DIAGRAM

SCKx

1:1/4/16/64

Primary

Prescaler

1:1 to 1:8

Secondary

Prescaler

FCY

SSx

Sync

Control

Select

Edge

Control

Clock

SPIxCON1<1:0>

SPIxCON1<4:2>

Control

Shift

SDOx

SDIx

Enable

Master Clock

bit0

SPIxSR

Transfer

8-Level FIFO Buffer

(Enhanced Modes)

SPIxBUF⁽¹⁾

Write SPIxBUF

Read SPIxBUF

16

Internal Data Bus

Note 1: In Standard modes, data is transferred directly between SPIxSR and SPIxBUF.

DS39747C-page 116

Preliminary

PIC24FJ128GA FAMILY

REGISTER 14-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER

Upper Byte:

R/W-0

U-0

—

R/W-0

U-0

—

U-0

—

R-0

SPIEN

SPISIDL

SPIBEC2 SPIBEC1 SPIBEC0

bit 8

bit 15

Lower Byte:

U-0

—

R/C-0

U-0

—

U-0

—

U-0

—

U-0

—

R-0

SPIROV

SPITBF

SPIRBF

bit 7

bit 0

bit 15

SPIEN: SPIx Enable bit

1= Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins

0= Disables module

bit 14

bit 13

Unimplemented: Read as ‘0’

SPISIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-11 Unimplemented: Read as ‘0’

bit 10-8 SPIBEC2:SPIBEC0: SPIx Buffer Element Count bits

Master mode:

Number of SPI transfers pending.

Slave mode:

Number of SPI transfers unread.

bit 7

bit 6

Unimplemented: Read as ‘0’

SPIROV: Receive Overflow Flag bit

1= A new byte/word is completely received and discarded. The user software has not read the previous

data in the SPIxBUF register.

0= No overflow has occurred

bit 5-2

bit 1

Unimplemented: Read as ‘0’

SPITBF: SPIx Transmit Buffer Full Status bit

1= Transmit not yet started, SPIxTXB is full

0= Transmit started, SPIxTXB is empty

In Standard Buffer mode:

Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB.

Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.

In Enhanced Buffer mode:

Automatically set in hardware when CPU writes SPIxBUF location, loading the last available buffer location.

Automatically cleared in hardware when a buffer location is available for a CPU write.

SPIRBF: SPIx Receive Buffer Full Status bit

bit 0

1= Receive complete, SPIxRXB is full

0= Receive is not complete, SPIxRXB is empty

In Standard Buffer mode:

Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.

Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.

In Enhanced Buffer mode:

Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread buffer

location.

Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR.

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

S = Settable bit

‘0’ = Bit is cleared

C = Clearable bit

x = Bit is unknown

Preliminary

DS39747C-page 117

PIC24FJ128GA FAMILY

REGISTER 14-2: SPIXCON1: SPIx CONTROL REGISTER 1

Upper Byte:

U-0

—

U-0

—

U-0

—

R/W-0

SMP

R/W-0

CKE

DISSCK

DISSDO

MODE16

bit 15

bit 8

Lower Byte:

R/W-0

SSEN

R/W-0

CKP

R/W-0

MSTEN

R/W-0

SPRE2

R/W-0

SPRE0

R/W-0

PPRE1

R/W-0

SPRE1

PPRE0

bit 7

bit 0

bit 15-13 Unimplemented: Read as ‘0’

bit 12

bit 11

bit 10

bit 9

DISSCK: Disable SCKx pin bit (SPI Master modes only)

1= Internal SPI clock is disabled, pin functions as I/O

0= Internal SPI clock is enabled

DISSDO: Disable SDOx pin bit

1= SDOx pin is not used by module; pin functions as I/O

0= SDOx pin is controlled by the module

MODE16: Word/Byte Communication Select bit

1= Communication is word-wide (16 bits)

0= Communication is byte-wide (8 bits)

SMP: SPIx Data Input Sample Phase bit

Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

Slave mode:

SMP must be cleared when SPIx is used in Slave mode.

bit 8

CKE: SPIx Clock Edge Select bit

1= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)

0= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)

Note:

The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the

Framed SPI modes (FRMEN = 1).

bit 7

SSEN: Slave Select Enable (Slave mode) bit

1= SSx pin used for Slave mode

0= SSx pin not used by module. Pin controlled by port function.

bit 6

CKP: Clock Polarity Select bit

1= Idle state for clock is a high level; active state is a low level

0= Idle state for clock is a low level; active state is a high level

bit 5

MSTEN: Master Mode Enable bit

1= Master mode

0= Slave mode

bit 4-2

SPRE2:SPRE0: Secondary Prescale (Master mode) bits

111= Secondary prescale 1:1

110= Secondary prescale 2:1

...

000= Secondary prescale 8:1

bit 1-0

PPRE1:PPRE0: Primary Prescale (Master mode) bits

11= Primary prescale 1:1

10= Primary prescale 4:1

01= Primary prescale 16:1

00= Primary prescale 64:1

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 118

Preliminary

PIC24FJ128GA FAMILY

REGISTER 14-3: SPIxCON2: SPIx CONTROL REGISTER 2

Upper Byte:

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

FRMEN

bit 15

SPIFSD

SPIFPOL

bit 8

Lower Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SPIFE

R/W-0

SPIBEN

bit 7

bit 0

bit 15

bit 14

bit 13

FRMEN: Framed SPIx Support bit

1= Framed SPIx support enabled

0= Framed SPIx support disabled

SPIFSD: Frame Sync Pulse Direction Control on SSx pin bit

1= Frame sync pulse input (slave)

0= Frame sync pulse output (master)

SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only)

1= Frame sync pulse is active-high

0= Frame sync pulse is active-low

bit 12-2 Unimplemented: Read as ‘0’

bit 1

SPIFE: Frame Sync Pulse Edge Select bit

1= Frame sync pulse coincides with first bit clock

0= Frame sync pulse precedes first bit clock

SPIBEN: Enhanced Buffer Enable bit

bit 0

1= Enhanced Buffer enabled

0= Enhanced Buffer disabled (legacy mode)

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 119

PIC24FJ128GA FAMILY

FIGURE 14-2:

SPI MASTER/SLAVE CONNECTION (STANDARD MODE)

PROCESSOR 1 (SPI Master)

PROCESSOR 2 (SPI Slave)

SDOx

SDIx

Serial Receive Buffer

(SPIxRXB)

Serial Receive Buffer

(SPIxRXB)

SDIx

SDOx

Shift Register

(SPIxSR)

Shift Register

(SPIxSR)

LSb

MSb

LSb

Serial Transmit Buffer

(SPIxTXB)

Serial Clock

SCKx

SSx

SCKx

SPIx Buffer

(SPIxBUF)

SPIx Buffer

(SPIxBUF)

(SSEN (SPIxCON1<7>) = 1and MSTEN (SPIxCON1<5>) = 0)

(MSTEN (SPIxCON1<5> = 1))

Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory

mapped to SPIxBUF.

FIGURE 14-3:

SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)

PROCESSOR 1 (SPI Enhanced Buffer Master)

PROCESSOR 2 (SPI Enhanced Buffer Slave)

SDOx

SDIx

SDOx

Shift Register

(SPIxSR)

Shift Register

(SPIxSR)

LSb

MSb

LSb

8-Level FIFO Buffer

8-level FIFO Buffer

Serial Clock

SPIx Buffer

(SPIxBUF)

SPIx Buffer

(SPIxBUF)

SCKx

SSx

SCKx

SSx

MSTEN (SPIxCON1<5> = 1and

SPIBEN (SPIxCON2<0>) = 1

SSEN (SPIxCON1<7>) = 1and

MSTEN (SPIxCON1<5>) = 0and

SPIBEN (SPIxCON2<0>) = 1

Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory

mapped to SPIxBUF.

DS39747C-page 120

Preliminary

PIC24FJ128GA FAMILY

FIGURE 14-4:

FIGURE 14-5:

FIGURE 14-6:

FIGURE 14-7:

SPI MASTER, FRAME MASTER CONNECTION DIAGRAM

PIC24

PROCESSOR 2

(SPI Slave, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync

Pulse

SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM

PIC24

PROCESSOR 2

SPI Master, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync

Pulse

SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM

PIC24

PROCESSOR 2

(SPI Slave, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync.

Pulse

SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM

PIC24

PROCESSOR 2

(SPI Master, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync

Pulse

Preliminary

DS39747C-page 121

PIC24FJ128GA FAMILY

(1)

EQUATION 14-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED

FCY

FSCK =

Primary Prescaler * Secondary Prescaler

Note 1: Based on TCY = FOSC/2, Doze mode and PLL are disabled.

(1,2)

TABLE 14-1: SAMPLE SCK FREQUENCIES

Secondary Prescaler Settings

FCY = 16 MHz

1:1

2:1

4:1

6:1

8:1

Primary Prescaler Settings

1:1

4:1

16000

4000

1000

250

8000

2000

500

4000

1000

250

63

2667

667

167

42

2000

500

125

31

16:1

64:1

125

FCY = 5 MHz

Primary Prescaler Settings

1:1

4:1

5000

1250

313

78

2500

625

156

39

1250

313

78

833

208

52

625

156

39

16:1

64:1

20

13

10

Note 1: Based on TCY = FOSC/2, Doze mode and PLL are disabled.

2: SCKx frequencies shown in kHz.

DS39747C-page 122

Preliminary

PIC24FJ128GA FAMILY

15.1 Communicating as a Master in a

Single Master Environment

15.0 INTER-INTEGRATED CIRCUIT

2

(I C™)

The details of sending a message in Master mode

depends on the communications protocol for the device

being communicated with. Typically, the sequence of

events is as follows:

Note:

This data sheet summarizes the features

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

1. Assert a Start condition on SDAx and SCLx.

2. Send the I²C device address byte to the slave

with a write indication.

The Inter-Integrated Circuit (I²C) module is a serial

interface useful for communicating with other periph-

eral or microcontroller devices. These peripheral

devices may be serial EEPROMs, display drivers, A/D

converters, etc.

3. Wait for and verify an Acknowledge from the

slave.

4. Send the first data byte (sometimes known as

the command) to the slave.

The I²C module supports these features:

• Independent master and slave logic

• 7-bit and 10-bit device addresses

5. Wait for and verify an Acknowledge from the

slave.

2

• General call address, as defined in the I C protocol

6. Send the serial memory address low byte to the

slave.

• Clock stretching to provide delays for the

processor to respond to a slave data request

7. Repeat steps 4 and 5 until all data bytes are

sent.

• Both 100 kHz and 400 kHz bus specifications.

• Configurable address masking

8. Assert a Repeated Start condition on SDAx and

SCLx.

• Multi-Master modes to prevent loss of messages

in arbitration

9. Send the device address byte to the slave with

a read indication.

• Bus Repeater mode, allowing the acceptance of

all messages as a slave regardless of the address

10. Wait for and verify an Acknowledge from the

slave.

• Automatic SCL

11. Enable master reception to receive serial

memory data.

A block diagram of the module is shown in Figure 15-1.

12. Generate an ACK or NACK condition at the end

of a received byte of data.

13. Generate a Stop condition on SDAx and SCLx.

Preliminary

DS39747C-page 123

PIC24FJ128GA FAMILY

2

FIGURE 15-1:

I C™ BLOCK DIAGRAM

Internal

Data Bus

I2CxRCV

Read

Shift

Clock

SCLx

SDAx

I2CxRSR

LSB

Address Match

Write

Read

Match Detect

I2CxMSK

Write

Read

I2CxADD

Start and Stop

Bit Detect

Write

Start and Stop

Bit Generation

I2CxSTAT

I2CxCON

Read

Write

Collision

Detect

Acknowledge

Generation

Read

Clock

Stretching

Write

Read

I2CxTRN

LSB

Shift Clock

Reload

Control

Write

Read

BRG Down Counter

TCY/2

I2CxBRG

DS39747C-page 124

Preliminary

PIC24FJ128GA FAMILY

15.2 Setting Baud Rate When

Operating as a Bus Master

15.3 Slave Address Masking

The I2CxMSK register (Register 15-3) designates

address bit positions as “don’t care” for both 7-bit and

10-bit Address modes. Setting a particular bit location

(= 1) in the I2CxMSK register causes the slave module

to respond whether the corresponding address bit

value is a ‘0’ or ‘1’. For example, when I2CxMSK is set

to ‘00100000’, the slave module will detect both

addresses ‘0000000’ and ‘00100000’.

To compute the Baud Rate Generator reload value, use

the following equation:

(1)

EQUATION 15-1:

FCY

FSCL = ---------------------------------------------

2 ⋅ (I2CxBRG + 1)

or

To enable address masking, the IPMI (Intelligent

Peripheral Management Interface) must be disabled by

clearing the IPMIEN bit (I2CxCON<11>).

FCY

⎛

⎝

⎞

– 1

-------------------

I2CxBRG =

⎠

2 ⋅ FSCL

Note 1: Based on TCY = FOSC/2, Doze mode and

PLL are disabled.

2

(1)

TABLE 15-1: I C™ CLOCK RATES

Required

System

FSCL

I2CxBRG Value

Actual

FCY

FSCL

(Decimal)

(Hexadecimal)

100 kHz

400 kHz

1 MHz

16 MHz

8 MHz

4 MHz

16 MHz

8 MHz

4 MHz

2 MHz

16 MHz

8 MHz

4 MHz

79

39

19

9

4F

27

13

9

100 kHz

400 kHz

333 kHz⁽²⁾

1 MHz

4

2

7

1 MHz

3

1 MHz⁽³⁾

1 MHz⁽⁴⁾

1 MHz

1

Legend: Shaded rows represent invalid reload values for a given FSCL and FCY.

Note 1: Based on TCY = FOSC/2, Doze mode and PLL are disabled.

2: This is closest value to 400 kHz for this value of FCY.

3: FCY = 2 MHz is the minimum input clock frequency to have FSCL = 1 MHz.

4: I2CxBRG cannot have a value of less than 2.

Preliminary

DS39747C-page 125

PIC24FJ128GA FAMILY

REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER

Upper Byte:

R/W-0

I2CEN

U-0

—

R/W-0

R/W-1 HC

SCLREL

R/W-0

A10M

R/W-0

SMEN

I2CSIDL

IPMIEN

DISSLW

bit 15

bit 8

Lower Byte:

R/W-0

GCEN

R/W-0

STREN

R/W-0

R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC

ACKEN RCEN PEN RSEN SEN

bit 0

ACKDT

bit 7

bit 15

I2CEN: I2Cx Enable bit

1= Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins

0= Disables I2Cx module. All I²C pins are controlled by port functions.

bit 14

bit 13

Unimplemented: Read as ‘0’

I2CSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters an Idle mode

0= Continue module operation in Idle mode

bit 12

SCLREL: SCLx Release Control bit (when operating as I²C Slave)

1= Release SCLx clock

0= Hold SCLx clock low (clock stretch)

If STREN = 1:

Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock).

Hardware clear at beginning of slave transmission.

Hardware clear at end of slave reception.

If STREN = 0:

Bit is R/S (i.e., software may only write ‘1’ to release clock).

Hardware clear at beginning of slave transmission.

bit 11

bit 10

bit 9

IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit

1= IPMI Support mode is enabled; all addresses Acknowledged

0= IPMI mode disabled

A10M: 10-bit Slave Address bit

1= I2CxADD is a 10-bit slave address

0= I2CxADD is a 7-bit slave address

DISSLW: Disable Slew Rate Control bit

1= Slew rate control disabled

0= Slew rate control enabled

bit 8

SMEN: SMBus Input Levels bit

1= Enable I/O pin thresholds compliant with SMBus specification

0= Disable SMBus input thresholds

bit 7

GCEN: General Call Enable bit (when operating as I²C slave)

1= Enable interrupt when a general call address is received in the I2CRSR

(module is enabled for reception)

0= General call address disabled

.

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

HS = Set in Hardware

‘0’ = Bit is cleared

HC = Cleared in Hardware

x = Bit is unknown

DS39747C-page 126

Preliminary

PIC24FJ128GA FAMILY

REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)

Upper Byte:

R/W-0

U-0

—

R/W-0

R/W-1 HC

SCLREL

R/W-0

A10M

R/W-0

SMEN

I2CEN

I2CSIDL

IPMIEN

DISSLW

bit 15

bit 8

Lower Byte:

R/W-0

GCEN

R/W-0

STREN

R/W-0

R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC R/W-0 HC

ACKEN RCEN PEN RSEN SEN

bit 0

ACKDT

bit 7

bit 6

bit 5

bit 4

STREN: SCLx Clock Stretch Enable bit (when operating as I²C slave)

Used in conjunction with SCLREL bit.

1= Enable software or receive clock stretching

0= Disable software or receive clock stretching

ACKDT: Acknowledge Data bit (When operating as I²C master. Applicable during master receive.)

Value that will be transmitted when the software initiates an Acknowledge sequence.

1= Send NACK during Acknowledge

0= Send ACK during Acknowledge

ACKEN: Acknowledge Sequence Enable bit

(When operating as I²C master. Applicable during master receive.)

1= Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit

Hardware clear at end of master Acknowledge sequence.

0= Acknowledge sequence not in progress

bit 3

bit 2

bit 1

bit 0

.

RCEN: Receive Enable bit (when operating as I²C master)

1= Enables Receive mode for I²C

Hardware clear at end of eighth bit of master receive data byte.

0= Receive sequence not in progress

PEN: Stop Condition Enable bit (when operating as I²C master)

1= Initiate Stop condition on SDAx and SCLx pins

Hardware clear at end of master Stop sequence.

0= Stop condition not in progress

RSEN: Repeated Start Condition Enabled bit (when operating as I²C master)

1= Initiate Repeated Start condition on SDAx and SCLx pins

Hardware clear at end of master Repeated Start sequence.

0= Repeated Start condition not in progress

SEN: Start Condition Enabled bit (when operating as I²C master)

1= Initiate Start condition on SDA and SCL pins

Hardware clear at end of master Start sequence.

0= Start condition not in progress

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

HS = Set in Hardware

‘0’ = Bit is cleared

HC = Cleared in Hardware

x = Bit is unknown

Preliminary

DS39747C-page 127

PIC24FJ128GA FAMILY

REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER

Upper Byte:

R-0 HSC

U-0

—

U-0

—

U-0

—

R/C-0 HS R-0 HSC

BCL GCSTAT

R-0 HSC

ADD10

bit 8

ACKSTAT TRSTAT

bit 15

Lower Byte:

R/C-0 HS R/C-0 HS R-0 HSC R/C-0 HSC R/C-0 HSC R-0 HSC

IWCOL I2COV D/A R/W

bit 7

R-0 HSC

RBF

R-0 HSC

TBF

P

S

bit 0

bit 15

bit 14

ACKSTAT: Acknowledge Status bit

(When operating as I²C master. Applicable to master transmit operation.)

1= NACK received from slave

0= ACK received from slave

Hardware set or clear at end of slave Acknowledge.

TRSTAT: Transmit Status bit

(When operating as I²C master. Applicable to master transmit operation.)

1= Master transmit is in progress (8 bits + ACK)

0= Master transmit is not in progress

Hardware set at beginning of master transmission.

Hardware clear at end of slave Acknowledge.

bit 13-11 Unimplemented: Read as ‘0’

bit 10

BCL: Master Bus Collision Detect bit

1= A bus collision has been detected during a master operation

0= No collision

Hardware set at detection of bus collision.

bit 9

GCSTAT: General Call Status bit

1= General call address was received

0= General call address was not received

Hardware set when address matches general call address.

Hardware clear at Stop detection.

bit 8

ADD10: 10-bit Address Status bit

1= 10-bit address was matched

0= 10-bit address was not matched

Hardware set at match of 2nd byte of matched 10-bit address.

Hardware clear at Stop detection.

bit 7

bit 6

.

IWCOL: Write Collision Detect bit

1= An attempt to write the I2CxTRN register failed because the I²C module is busy

0= No collision

Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).

I2COV: Receive Overflow Flag bit

1= A byte was received while the I2CxRCV register is still holding the previous byte

0= No overflow

Hardware set at attempt to transfer I2CRSR to I2CxRCV (cleared by software).

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

C = Clearable bit

‘1’ = Bit is set

HS = Set in Hardware

‘0’ = Bit is cleared

HSC = Hardware Set/Cleared

x = Bit is unknown

DS39747C-page 128

Preliminary

PIC24FJ128GA FAMILY

REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)

Upper Byte:

R-0 HSC

U-0

—

U-0

—

U-0

—

R/C-0 HS R-0 HSC

BCL GCSTAT

R-0 HSC

ADD10

bit 8

ACKSTAT TRSTAT

bit 15

Lower Byte:

R/C-0 HS R/C-0 HS R-0 HSC R/C-0 HSC R/C-0 HSC R-0 HSC

IWCOL I2COV D/A R/W

bit 7

R-0 HSC

RBF

R-0 HSC

TBF

P

S

bit 0

bit 5

D/A: Data/Address bit (when operating as I²C slave)

1= Indicates that the last byte received was data

0= Indicates that the last byte received was device address

Hardware clear at device address match.

Hardware set by write to I2CxTRN or by reception of slave byte.

bit 4

bit 3

bit 2

bit 1

P: Stop bit

1= Indicates that a Stop bit has been detected last

0= Stop bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop detected.

S: Start bit

1= Indicates that a Start (or Repeated Start) bit has been detected last

0= Start bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop detected.

R/W: Read/Write bit Information (when operating as I²C slave)

1= Read – indicates data transfer is output from slave

0= Write – indicates data transfer is input to slave

Hardware set or clear after reception of I²C device address byte.

RBF: Receive Buffer Full Status bit

1= Receive complete, I2CxRCV is full

0= Receive not complete, I2CxRCV is empty

Hardware set when I2CxRCV written with received byte.

Hardware clear when software reads I2CxRCV.

bit 0

TBF: Transmit Buffer Full Status bit

1= Transmit in progress, I2CxTRN is full

0= Transmit complete, I2CxTRN is empty

Hardware set when software writes I2CxTRN.

Hardware clear at completion of data transmission.

.

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

C = Clearable bit

‘1’ = Bit is set

HS = Set in Hardware

‘0’ = Bit is cleared

HSC = Hardware Set/Cleared

x = Bit is unknown

Preliminary

DS39747C-page 129

PIC24FJ128GA FAMILY

REGISTER 15-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER

Upper Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

AMSK9

AMSK8

bit 15

bit 8

Lower Byte:

R/W-0

AMSK3

R/W-0

AMSK2

R/W-0

AMSK7

bit 7

AMSK6

AMSK5

AMSK4

AMSK1

AMSK0

bit 0

bit 15-10 Unimplemented: Read as ‘0’

bit 9-0 AMSKx: Mask for Address Bit x Select bit

1= Enable masking for bit x of incoming message address; bit match not required in this position

0= Disable masking for bit x; bit match required in this position

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS39747C-page 130

Preliminary

PIC24FJ128GA FAMILY

• Fully Integrated Baud Rate Generator with 16-bit

Prescaler

16.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART)

• Baud Rates Ranging from 1 Mbps to 15 bps at

16 MIPS

• 4-Deep First-In-First-Out (FIFO) Transmit Data

Buffer

Note:

This data sheet summarizes the features

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

• 4-Deep FIFO Receive Data Buffer

• Parity, Framing and Buffer Overrun Error Detection

• Support for 9-bit mode with Address Detect

(9th bit = 1)

The Universal Asynchronous Receiver Transmitter

(UART) module is one of the serial I/O modules

available in the PIC24 device family. The UART is a full-

duplex asynchronous system that can communicate

with peripheral devices, such as personal computers,

LIN, RS-232 and RS-485 interfaces. The module also

supports a hardware flow control option with the

UxCTS and UxRTS pins and also includes an IrDA

encoder and decoder.

• Transmit and Receive Interrupts

• Loopback mode for Diagnostic Support

• Support for Sync and Break Characters

• Supports Automatic Baud Rate Detection

• IrDA Encoder and Decoder Logic

• 16x Baud Clock Output for IrDA Support

A simplified block diagram of the UART is shown in

Figure 16-1. The UART module consists of these key

important hardware elements:

The primary features of the UART module are:

• Full-Duplex 8 or 9-bit Data Transmission through

the UxTX and UxRX pins

• Baud Rate Generator

• Even, Odd or No Parity Options (for 8-bit data)

• One or Two Stop bits

• Asynchronous Transmitter

• Asynchronous Receiver

• Hardware Flow Control Option with UxCTS and

UxRTS pins

FIGURE 16-1:

UART SIMPLIFIED BLOCK DIAGRAM

Baud Rate Generator

IrDA^®

BCLKx

UxRTS

UxCTS

Hardware Flow Control

UARTx Receiver

UxRX

UxTX

UARTx Transmitter

Preliminary

DS39747C-page 131

PIC24FJ128GA FAMILY

The maximum baud rate (BRGH = 0) possible is

FCY/16 (for BRGx = 0), and the minimum baud rate

possible is FCY/(16 * 65536).

16.1 UART Baud Rate Generator (BRG)

The UART module includes a dedicated 16-bit Baud

Rate Generator. The BRGx register controls the period

of a free-running 16-bit timer. Equation 16-1 shows the

formula for computation of the baud rate with

BRGH = 0.

Equation 16-2 shows the formula for computation of

the baud rate with BRGH = 1.

EQUATION 16-2: UART BAUD RATE WITH

(1,2)

BRGH = 1

EQUATION 16-1: UART BAUD RATE WITH

(1,2)

BRGH = 0

FCY

Baud Rate =

4 • (BRGx + 1)

FCY

Baud Rate =

16 • (BRGx + 1)

FCY

4 • Baud Rate

– 1

BRGx =

FCY

16 • Baud Rate

– 1

BRGx =

Note 1: FCY denotes the instruction cycle clock

frequency.

Note 1: FCY denotes the instruction cycle clock

frequency (FOSC/2).

2: Based on TCY = FOSC/2, Doze mode

and PLL are disabled.

2: Based on TCY = FOSC/2, Doze mode

and PLL are disabled.

The maximum baud rate (BRGH = 1) possible is FCY/4

(for BRGx = 0) and the minimum baud rate possible is

FCY/(4 * 65536).

Example 16-1 shows the calculation of the baud rate

error for the following conditions:

Writing a new value to the BRGx register causes the

BRG timer to be reset (cleared). This ensures the BRG

does not wait for a timer overflow before generating the

new baud rate.

• FCY = 4 MHz

• Desired Baud Rate = 9600

(1)

EXAMPLE 16-1:

BAUD RATE ERROR CALCULATION (BRGH = 0)

Desired Baud Rate

=

FCY/(16 (BRGx + 1))

Solving for BRGx value:

BRGx

=

((FCY/Desired Baud Rate)/16) – 1

((4000000/9600)/16) – 1

25

Calculated Baud Rate

=

4000000/(16 (25 + 1))

9615

Error

=

(Calculated Baud Rate – Desired Baud Rate)

Desired Baud Rate

=

(9615 – 9600)/9600

0.16%

Note 1: Based on TCY = FOSC/2, Doze mode and PLL are disabled.

DS39747C-page 132

Preliminary

PIC24FJ128GA FAMILY

16.2 Transmitting in 8-Bit Data Mode

16.5 Receiving in 8-Bit or 9-Bit Data

Mode

1. Set up the UART:

a) Write appropriate values for data, parity and

Stop bits.

1. Set up the UART (as described in Section 16.2

“Transmitting in 8-Bit Data Mode”).

b) Write appropriate baud rate value to the

BRGx register.

2. Enable the UART.

3. A receive interrupt will be generated when one

or more data characters have been received as

per interrupt control bit, URXISELx.

c) Set up transmit and receive interrupt enable

and priority bits.

2. Enable the UART.

4. Read the OERR bit to determine if an overrun

error has occurred. The OERR bit must be reset

in software.

3. Set the UTXEN bit (causes a transmit interrupt).

4. Write data byte to lower byte of TXxREG word.

The value will be immediately transferred to the

Transmit Shift Register (TSR), and the serial bit

stream will start shifting out with next rising edge

of the baud clock.

5. Read RXxREG.

The act of reading the RXxREG character will move the

next character to the top of the receive FIFO, including

a new set of PERR and FERR values.

5. Alternately, the data byte may be transferred

while UTXEN = 0, and then the user may set

UTXEN. This will cause the serial bit stream to

begin immediately because the baud clock will

start from a cleared state.

16.6 Operation of UxCTS and UxRTS

Control Pins

UARTx Clear to Send (UxCTS) and Request to Send

(UxRTS) are the two hardware controlled pins that are

associated with the UART module. These two pins

allow the UART to operate in Simplex and Flow Control

mode. They are implemented to control the transmis-

sion and reception between the Data Terminal

Equipment (DTE). The UEN<1:0> bits in the UxMODE

register configure these pins.

6. A transmit interrupt will be generated as per

interrupt control bit, UTXISELx.

16.3 Transmitting in 9-Bit Data Mode

1. Set up the UART (as described in Section 16.2

“Transmitting in 8-Bit Data Mode”).

2. Enable the UART.

16.7 Infrared Support

3. Set the UTXEN bit (causes a transmit interrupt).

4. Write TXxREG as a 16-bit value only.

The UART module provides two types of infrared UART

support: one is the IrDA clock output to support exter-

nal IrDA encoder and decoder device (legacy module

support) and the other is the full implementation of the

IrDA encoder and decoder.

5. A word write to TXxREG triggers the transfer of

the 9-bit data to the TSR. Serial bit stream will

start shifting out with the first rising edge of the

baud clock.

6. A transmit interrupt will be generated as per the

setting of control bit, UTXISELx.

16.8 External IrDA Support – IrDA

Clock Output

16.4 Break and Sync Transmit

Sequence

To support external IrDA encoder and decoder devices,

the BCLKx pin (same as the UxRTS pin) can be

configured to generate the 16x baud clock. With

UEN<1:0> = 11, the BCLKx pin will output the 16x

baud clock if the UART module is enabled. It can be

used to support the IrDA codec chip.

The following sequence will send a message frame

header made up of a Break, followed by an auto-baud

Sync byte.

1. Configure the UART for the desired mode.

2. Set UTXEN and UTXBRK – sets up the Break

character,

16.9 Built-in IrDA Encoder and Decoder

3. Load the TXxREG with a dummy character to

initiate transmission (value is ignored).

The UART has full implementation of the IrDA encoder

and decoder as part of the UART module. The built-in

IrDA encoder and decoder functionality is enabled

using the IREN bit UxMODE<12>. When enabled

(IREN = 1), the receive pin (UxRX) acts as the input

from the infrared receiver. The transmit pin (UxTX) acts

as the output to the infrared transmitter.

4. Write ‘55h’ to TXxREG – loads Sync character

into the transmit FIFO.

5. After the Break has been sent, the UTXBRK bit

is reset by hardware. The Sync character now

transmits.

Preliminary

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REGISTER 16-1: UxMODE: UARTx MODE REGISTER

Upper Byte:

R/W-0

UARTEN

bit 15

U-0

—

R/W-0

USIDL

R/W-0

IREN

R/W-0

U-0

—

R/W-0⁽¹⁾

UEN1

R/W-0⁽¹⁾

UEN0

RTSMD

bit 8

Lower Byte:

R/W-0 HC

WAKE

bit 7

R/W-0

LPBACK

R/W-0 HC

ABAUD

R/W-0

RXINV

R/W-0

BRGH

R/W-0

PDSEL1

PDSEL0

STSEL

bit 0

bit 15

UARTEN: UARTx Enable bit

1= UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>

0= UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption minimal

bit 14

bit 13

Unimplemented: Read as ‘0’

USIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12

bit 11

IREN: IrDA Encoder and Decoder Enable bit

1= IrDA encoder and decoder enabled

0= IrDA encoder and decoder disabled

Note: This feature is only available for the 16x BRG mode (BRGH = 0).

RTSMD: Mode Selection for UxRTS Pin bit

1= UxRTS pin in Simplex mode

0= UxRTS pin in Flow Control mode

bit 10

Unimplemented: Read as ‘0’

bit 9-8

UEN1:UEN0: UARTx Enable bits

11= UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by PORT latches

10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used

01= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by PORT latches

00= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by PORT latches

Note 1: Bit availability depends on pin availability.

bit 7

WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit

1= UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit cleared in

hardware on following rising edge

0= No wake-up enabled

bit 6

bit 5

LPBACK: UARTx Loopback Mode Select bit

1= Enable Loopback mode

0= Loopback mode is disabled

ABAUD: Auto-Baud Enable bit

1= Enable baud rate measurement on the next character – requires reception of a Sync field (55h); cleared

in hardware upon completion

0= Baud rate measurement disabled or completed

bit 4

RXINV: Receive Polarity Inversion bit

1= UxRX Idle state is ‘0’

0= UxRX Idle state is ‘1’

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at Reset

W = Writable bit

‘1’ = Bit is set

HC = Hardware Cleared

‘0’ = Bit is cleared

HS = Hardware Set

x = Bit is unknown

DS39747C-page 134

Preliminary

PIC24FJ128GA FAMILY

REGISTER 16-1: UxMODE: UARTx MODE REGISTER (CONTINUED)

Upper Byte:

R/W-0

U-0

—

R/W-0

USIDL

R/W-0

IREN

R/W-0

U-0

—

R/W-0⁽¹⁾

UEN1

R/W-0⁽¹⁾

UEN0

UARTEN

bit 15

RTSMD

bit 8

Lower Byte:

R/W-0 HC

WAKE

bit 7

R/W-0

LPBACK

R/W-0 HC

ABAUD

R/W-0

RXINV

R/W-0

BRGH

R/W-0

PDSEL1

PDSEL0

STSEL

bit 0

bit 3

BRGH: High Baud Rate Enable bit

1= BRG generates 4 clocks per bit period (4x Baud Clock, High-Speed mode)

0= BRG generates 16 clocks per bit period (16x Baud Clock, Standard mode)

bit 2-1

PDSEL1:PDSEL0: Parity and Data Selection bits

11= 9-bit data, no parity

10= 8-bit data, odd parity

01= 8-bit data, even parity

00= 8-bit data, no parity

bit 0

STSEL: Stop Bit Selection bit

1= Two Stop bits

0= One Stop bit

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at Reset

W = Writable bit

‘1’ = Bit is set

HC = Hardware Cleared

‘0’ = Bit is cleared

HS = Hardware Set

x = Bit is unknown

Preliminary

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REGISTER 16-2: UxSTA: UARTx STATUS AND CONTROL REGISTER

Upper Byte:

R/W-0

U-0

—

R/W-0 HC

UTXBRK

R/W-0

R-0

R-1

UTXISEL1 UTXINV⁽¹⁾UTXISEL0

UTXEN

UTXBF

TRMT

bit 15

bit 8

Lower Byte:

R/W-0

R-1

R-0

PERR

R-0

FERR

R/C-0

OERR

R-0

URXISEL1 URXISEL0 ADDEN

bit 7

RIDLE

URXDA

bit 0

bit 15,13 UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits

11= Reserved; do not use

10= Interrupt when a character is transferred to the Transmit Shift Register and as a result, the transmit

buffer becomes empty

01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations

are completed

00= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at

least one character open in the transmit buffer)

bit 14

UTXINV: IrDA Encoder Transmit Polarity Inversion bit⁽¹⁾

1= IrDA encoded UxTX idle state is ‘1’

0= IrDA encoded UxTX idle state is ‘0’

Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled

(IREN = 1).

bit 12

bit 11

Unimplemented: Read as ‘0’

UTXBRK: Transmit Break bit

1= Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;

cleared by hardware upon completion

0= Sync Break transmission disabled or completed

bit 10

bit 9

UTXEN: Transmit Enable bit

1= Transmit enabled, UxTX pin controlled by UARTx

0= Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by PORT.

UTXBF: Transmit Buffer Full Status bit (Read-Only)

1= Transmit buffer is full

0= Transmit buffer is not full, at least one more character can be written

bit 8

TRMT: Transmit Shift Register Empty bit (Read-Only)

1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)

0= Transmit Shift Register is not empty, a transmission is in progress or queued

bit 7-6

URXISEL1:URXISEL0: Receive Interrupt Mode Selection bits

11= Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)

10= Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)

0x= Interrupt is set when any character is received and transferred from the RSR to the receive buffer.

Receive buffer has one or more characters.

bit 5

ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1= Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.

0 = Address Detect mode disabled

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at Reset

W = Writable bit

‘1’ = Bit is set

HS = Hardware Set

‘0’ = Bit is cleared

HC = Hardware Cleared

x = Bit is unknown

DS39747C-page 136

Preliminary

PIC24FJ128GA FAMILY

REGISTER 16-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)

Upper Byte:

R/W-0

U-0

—

R/W-0 HC

UTXBRK

R/W-0

R-0

R-1

UTXISEL1 UTXINV⁽¹⁾UTXISEL0

UTXEN

UTXBF

TRMT

bit 15

bit 8

Lower Byte:

R/W-0

R-1

R-0

PERR

R-0

FERR

R/C-0

OERR

R-0

URXISEL1 URXISEL0 ADDEN

bit 7

RIDLE

URXDA

bit 0

bit 4

bit 3

bit 2

bit 1

RIDLE: Receiver Idle bit (Read-Only)

1= Receiver is Idle

0= Receiver is active

PERR: Parity Error Status bit (Read-Only)

1= Parity error has been detected for the current character (character at the top of the receive FIFO)

0= Parity error has not been detected

FERR: Framing Error Status bit (Read-Only)

1= Framing error has been detected for the current character (character at the top of the receive FIFO)

0= Framing error has not been detected

OERR: Receive Buffer Overrun Error Status bit (Read/Clear-Only)

1= Receive buffer has overflowed

0= Receive buffer has not overflowed (clearing a previously set OERR bit (1→ 0transition) will reset the

receiver buffer and the RSR to the empty state)

bit 0

URXDA: Receive Buffer Data Available bit (Read-Only)

1= Receive buffer has data, at least one more character can be read

0= Receive buffer is empty

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at Reset

W = Writable bit

‘1’ = Bit is set

HS = Hardware Set

‘0’ = Bit is cleared

HC = Hardware Cleared

x = Bit is unknown

Preliminary

DS39747C-page 137

PIC24FJ128GA FAMILY

NOTES:

DS39747C-page 138

Preliminary

PIC24FJ128GA FAMILY

Key features of the PMP module include:

17.0 PARALLEL MASTER PORT

• Up to 16 Programmable Address Lines

• Up to Two Chip Select Lines

Note:

This data sheet summarizes the features

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

• Programmable Strobe Options

- Individual Read and Write Strobes or;

- Read/Write Strobe with Enable Strobe

• Address Auto-Increment/Auto-Decrement

• Programmable Address/Data Multiplexing

• Programmable Polarity on Control Signals

• Legacy Parallel Slave Port Support

• Enhanced Parallel Slave Support

- Address Support

The Parallel Master Port module (PMP) is a parallel

8-bit I/O module, specifically designed to communicate

with a wide variety of parallel devices, such as commu-

nications peripherals, LCDs, external memory devices

and microcontrollers. Because the interface to parallel

peripherals varies significantly, the PMP is highly

configurable.

- 4-byte Deep Auto-Incrementing Buffer

• Programmable Wait States

• Selectable Input Voltage Levels

FIGURE 17-1:

PMP MODULE OVERVIEW

Address Bus

Data Bus

Control Lines

PMA<0>

PMALL

PIC24F

Parallel Master Port

PMA<1>

PMALH

Up to 16-bit Address

EEPROM

PMA<13:2>

PMA<14>

PMCS1

PMA<15>

PMCS2

PMBE

FIFO

Buffer

Microcontroller

LCD

PMRD

PMRD/PMWR

PMWR

PMENB

PMD<7:0>

PMA<7:0>

PMA<15:8>

8-bit Data

Preliminary

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PIC24FJ128GA FAMILY

REGISTER 17-1: PMCON: PARALLEL PORT CONTROL REGISTER

Upper Byte:

R/W-0

U-0

—

R/W-0

PSIDL

R/W-0

PMPEN

ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN

bit 8

bit 15

Lower Byte:

R/W-0

CSF1

R/W-0

CSF0

R/W-0⁽¹⁾

ALP

R/W-0⁽¹⁾

CS2P

R/W-0⁽¹⁾

CS1P

R/W-0

BEP

R/W-0

WRSP

R/W-0

RDSP

bit 7

bit 0

bit 15

PMPEN: Parallel Master Port Enable bit

1= PMP enabled

0= PMP disabled, no off-chip access performed

bit 14

bit 13

Unimplemented: Read as ‘0’

PSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-11 ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits

11= Reserved

10= All 16 bits of address are multiplexed on PMD<7:0> pins

01= Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 8 bits are on PMA<15:8>

00= Address and data appear on separate pins

bit 10

bit 9

PTBEEN: Byte Enable Port Enable bit (16-bit Master mode)

1= PMBE port enabled

0= PMBE port disabled

PTWREN: Write Enable Strobe Port Enable bit

1= PMWR/PMENB port enabled

0= PMWR/PMENB port disabled

bit 8

PTRDEN: Read/Write Strobe Port Enable bit

1= PMRD/PMWR port enabled

0= PMRD/PMWR port disabled

bit 7-6

CSF1:CSF0: Chip Select Function bits

11= Reserved

10= PMCS1 and PMCS2 function as chip select

01= PMCS2 functions as chip select, PMCS1 functions as address bit 14

00= PMCS1 and PMCS2 function as address bits 15 and 14

bit 5

ALP: Address Latch Polarity bit⁽¹⁾

1= Active-high (PMALL and PMALH)

0= Active-low (PMALL and PMALH)

Note 1: These bits have no effect when their corresponding pins are used as address lines.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = bit is unknown

-n = Value at Reset

DS39747C-page 140

Preliminary

PIC24FJ128GA FAMILY

REGISTER 17-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)

Upper Byte:

R/W-0

U-0

—

R/W-0

PSIDL

R/W-0

PMPEN

bit 15

ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN

bit 8

Lower Byte:

R/W-0

CSF1

R/W-0

CSF0

R/W-0⁽¹⁾

ALP

R/W-0⁽¹⁾

CS2P

R/W-0⁽¹⁾

CS1P

R/W-0

BEP

R/W-0

WRSP

R/W-0

RDSP

bit 7

bit 0

bit 4

bit 3

bit 2

bit 1

CS2P: Chip Select 2 Polarity bit⁽¹⁾

1= Active-high (PMCS2)

0= Active-low (PMCS2)

CS1P: Chip Select 1 Polarity bit⁽¹⁾

1= Active-high (PMCS1/PMCS)

0= Active-low (PMCS1/PMCS)

BEP: Byte Enable Polarity bit

1= Byte enable active-high (PMBE)

0= Byte enable active-low (PMBE)

WRSP: Write Strobe Polarity bit

For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10):

1= Write strobe active-high (PMWR)

0= Write strobe active-low (PMWR)

For Master mode 1 (PMMODE<9:8> = 11):

1= Enable strobe active-high (PMENB)

0= Enable strobe active-low (PMENB)

bit 0

RDSP: Read Strobe Polarity bit

For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10):

1= Read strobe active-high (PMRD)

0= Read strobe active-low (PMRD)

For Master mode 1 (PMMODE<9:8> = 11):

1= Read/write strobe active-high (PMRD/PMWR)

0= Read/write strobe active-low (PMRD/PMWR)

Note 1: These bits have no effect when their corresponding pins are used as address lines.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = bit is unknown

-n = Value at Reset

Preliminary

DS39747C-page 141

PIC24FJ128GA FAMILY

REGISTER 17-2: PMMODE: PARALLEL PORT MODE REGISTER

Upper Byte:

R-0

R/W-0

BUSY

IRQM1

IRQM0

INCM1

INCM0

MODE16

MODE1

MODE0

bit 15

bit 8

Lower Byte:

R/W-0

WAITM2

R/W-0

WAITM1

R/W-0

WAITB1⁽¹⁾WAITB0⁽¹⁾WAITM3

WAITM0 WAITE1⁽¹⁾WAITE0⁽¹⁾

bit 7

bit 0

bit 15

BUSY: Busy bit (Master mode only)

1= Port is busy (not useful when the processor stall is active)

0= Port is not busy

bit 14-13 IRQM1:IRQM0: Interrupt Request Mode bits

11= Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)

or on a read or write operation when PMA<1:0> = 11(Addressable PSP mode only)

10= No interrupt generated, processor stall activated

01= Interrupt generated at the end of the read/write cycle

00= No interrupt generated

bit 12-11 INCM1:INCM0: Increment Mode bits

11= PSP read and write buffers auto-increment (Legacy PSP mode only)

10= Decrement ADDR<15,13:0> by 1 every read/write cycle

01= Increment ADDR<15,13:0> by 1 every read/write cycle

00= No increment or decrement of address

bit 10

MODE16: 8/16-bit Mode bit

1= 16-bit mode: data register is 16 bits, a read or write to the data register invokes two 8-bit transfers

0= 8-bit mode: data register is 8 bits, a read or write to the data register invokes one 8-bit transfer

bit 9-8

MODE1:MODE0: Parallel Port Mode Select bits

11= Master mode 1 (PMCSx, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)

10= Master mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)

01= Enhanced PSP, control signals (PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0>)

00= Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>)

bit 7-6

bit 5-2

bit 1-0

WAITB1:WAITB0: Data Setup to Read/Write Wait State Configuration bits⁽¹⁾

11= Data wait of 4 TCY; multiplexed address phase of 4 TCY

10= Data wait of 3 TCY; multiplexed address phase of 3 TCY

01= Data wait of 2 TCY; multiplexed address phase of 2 TCY

00= Data wait of 1 TCY; multiplexed address phase of 1 TCY

WAITM3:WAITM0: Read to Byte Enable Strobe Wait State Configuration bits

1111= Wait of additional 15 TCY

...

0001= Wait of additional 1 TCY

0000= No additional wait cycles (operation forced into one TCY)

WAITE1:WAITE0: Data Hold After Strobe Wait State Configuration bits⁽¹⁾

11= Wait of 4 TCY

10= Wait of 3 TCY

01= Wait of 2 TCY

00= Wait of 1 TCY

Note 1: WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at Reset

DS39747C-page 142

Preliminary

PIC24FJ128GA FAMILY

REGISTER 17-3: PMADDR: PARALLEL PORT ADDRESS REGISTER

Upper Byte:

R/W-0

CS1

R/W-0

bit 8

CS2

ADDR<13:8>

bit 15

Lower Byte:

R/W-0

bit 0

ADDR<7:0>

bit 7

bit 15

bit 14

CS2: Chip Select 2 bit

1= Chip select 2 is active

0= Chip select 2 is inactive (pin functions as PMA<15>)

CS1: Chip Select 1 bit

1= Chip select 1 is active

0= Chip select 1 is inactive (pin functions as PMA<14>)

bit 13-0 ADDR13:ADDR0: Parallel Port Destination Address bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at Reset

REGISTER 17-4: PMPEN: PARALLEL PORT ENABLE REGISTER

Upper Byte:

R/W-0

PTEN15

bit 15

R/W-0

PTEN14

PTEN13

PTEN12

PTEN11

PTEN10

PTEN9

PTEN8

bit 8

Lower Byte:

R/W-0

PTEN6

R/W-0

PTEN5

R/W-0

PTEN4

R/W-0

PTEN2

R/W-0

PTEN7

PTEN3

PTEN1

PTEN0

bit 7

bit 0

bit 15-14 PTEN15:PTEN14: PMCSx Strobe Enable bits

1= PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1

0= PMA15 and PMA14 function as port I/O

bit 13-2 PTEN13:PTEN2: PMP Address Port Enable bits

1= PMA<13:2> function as PMP address lines

0= PMA<13:2> function as port I/O

bit 1-0

PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits

1= PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL

0= PMA1 and PMA0 pads functions as port I/O

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at Reset

Preliminary

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REGISTER 17-5: PMSTAT: PARALLEL PORT STATUS REGISTER

Upper Byte:

R-0

IBF

R/W-0 HS

IBOV

U-0

—

U-0

—

R-0

IB3F

IB2F

IB1F

IB0F

bit 15

bit 8

Lower Byte:

R-1

R/W-0 HS

OBUF

U-0

—

U-0

—

R-1

OB1E

R-1

OBE

OB3E

OB2E

OB0E

bit 7

bit 0

bit 15

bit 14

IBF: Input Buffer Full Status bit

1= All writable input buffer registers are full

0= Some or all of the writable input buffer registers are empty

IBOV: Input Buffer Overflow Status bit

1= A write attempt to a full input byte register occurred (must be cleared in software)

0= No overflow occurred

bit 13-12 Unimplemented: Read as ‘0’

bit 11-8 IBnF: Input Buffer n Status Full bit

1= Input buffer contains data that has not been read (reading buffer will clear this bit)

0= Input buffer does not contain any unread data

bit 7

bit 6

OBE: Output buffer Empty Status bit

1= All readable output buffer registers are empty

0= Some or all of the readable output buffer registers are full

OBUF: Output Buffer Underflow Status bit

1= A read occurred from an empty output byte register (must be cleared in software)

0= No underflow occurred

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

OBnE: Output Buffer n Status Empty bit

1= Output buffer is empty (writing data to the buffer will clear this bit)

0= Output buffer contains data that has not been transmitted

Legend:

HS = Hardware Set

W = Writable bit

‘1’ = Bit is set

HC = Hardware Cleared

R = Readable bit

-n = Value at Reset

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

DS39747C-page 144

Preliminary

PIC24FJ128GA FAMILY

REGISTER 17-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER

Upper Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

RTSECSEL PMPTTL

bit 0

bit 7

bit 15-2 Unimplemented: Read as ‘0’

bit 1

bit 0

RTSECSEL: RTCC Seconds Clock Output Select bit

1= RTCC Seconds Clock is selected for the RTCC pin

0= RTCC Alarm Pulse is selected for the RTCC pin

Note:

To enable the actual RTCC output, the RTCCFG (RTCOE) bit needs to be set.

PMPTTL: PMP Module TTL Input Buffer Select bit

1= PMP module uses TTL input buffers

0= PMP module uses Schmitt input buffers

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at Reset

Preliminary

DS39747C-page 145

PIC24FJ128GA FAMILY

FIGURE 17-2:

LEGACY PARALLEL SLAVE PORT EXAMPLE

Address Bus

Data Bus

Master

PMD<7:0>

PIC24F Slave

PMD<7:0>

Control Lines

PMCS

PMRD

PMWR

PMCS

PMRD

PMWR

FIGURE 17-3:

ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE

PIC24F Slave

Master

PMA<1:0>

Write

Address

Decode

Read

Address

Decode

PMD<7:0>

PMDOUT1L (0)

PMDIN1L (0)

PMDIN1H (1)

PMDIN2L (2)

PMDIN2H (3)

PMCS

PMRD

PMWR

PMDOUT1H (1)

PMDOUT2L (2)

PMDOUT2H (3)

PMRD

PMWR

Address Bus

Data Bus

Control Lines

TABLE 17-1: SLAVE MODE ADDRESS RESOLUTION

PMA<1:0>

Output Register (Buffer)

Input Register (Buffer)

00

01

10

11

PMDOUT1<7:0> (0)

PMDOUT1<15:8> (1)

PMDOUT2<7:0> (2)

PMDOUT2<15:8> (3)

PMDIN1<7:0> (0)

PMDIN1<15:8> (1)

PMDIN2<7:0> (2)

PMDIN2<15:8> (3)

FIGURE 17-4:

MASTER MODE, DEMULTIPLEXED ADDRESSING (SEPARATE READ AND

WRITE STROBES, TWO CHIP SELECTS)

PIC24F

PMA<13:0>

PMD<7:0>

PMCS1

PMCS2

PMRD

Address Bus

Data Bus

Control Lines

PMWR

DS39747C-page 146

Preliminary

PIC24FJ128GA FAMILY

FIGURE 17-5:

MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ

AND WRITE STROBES, TWO CHIP SELECTS)

PIC24F

PMA<13:8>

PMD<7:0>

PMA<7:0>

PMCS1

PMCS2

PMALL

PMRD

Address Bus

Multiplexed

Data and

Address Bus

Control Lines

PMWR

FIGURE 17-6:

MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND

WRITE STROBES, TWO CHIP SELECTS)

PMD<7:0>

PMA<13:8>

PIC24F

PMCS1

PMCS2

PMALL

PMALH

PMRD

PMWR

Multiplexed

Data and

Address Bus

Control Lines

FIGURE 17-7:

EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION

PIC24F

A<7:0>

PMD<7:0>

PMALL

373

A<15:0>

D<7:0>

CE

A<15:8>

373

OE

WR

PMALH

PMCS

PMRD

PMWR

Address Bus

Data Bus

Control Lines

FIGURE 17-8:

EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION

PIC24F

A<7:0>

373

PMD<7:0>

PMALL

A<14:0>

D<7:0>

CE

A<14:8>

PMA<14:7>

OE

WR

Address Bus

Data Bus

PMCS

PMRD

PMWR

Control Lines

Preliminary

DS39747C-page 147

PIC24FJ128GA FAMILY

FIGURE 17-9:

EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION

PIC24F

PMD<7:0>

Parallel Peripheral

AD<7:0>

PMALL

PMCS

PMRD

PMWR

ALE

CS

Address Bus

Data Bus

RD

WR

Control Lines

FIGURE 17-10:

PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA)

PIC24F

Parallel EEPROM

PMA<n:0>

A<n:0>

PMD<7:0>

D<7:0>

PMCS

PMRD

PMWR

CE

OE

WR

Address Bus

Data Bus

Control Lines

FIGURE 17-11:

PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA)

PIC24F

Parallel EEPROM

A<n:1>

D<7:0>

PMA<n:0>

PMD<7:0>

PMBE

PMCS

PMRD

PMWR

A0

CE

OE

WR

Address Bus

Data Bus

Control Lines

FIGURE 17-12:

LCD CONTROL EXAMPLE (BYTE MODE OPERATION)

PIC24F

LCD Controller

PM<7:0>

PMA0

D<7:0>

RS

PMRD/PMWR

PMCS

R/W

E

Address Bus

Data Bus

Control Lines

DS39747C-page 148

Preliminary

PIC24FJ128GA FAMILY

18.0 REAL-TIME CLOCK AND

CALENDAR

Note:

This data sheet summarizes the features

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

FIGURE 18-1:

RTCC BLOCK DIAGRAM

CPU Clock Domain

RTCC Clock Domain

32.768 kHz Input

from SOSC Oscillator

RCFGCAL

RTCC Prescalers

0.5s

ALCFGRPT

YEAR

MTHDAY

RTCVAL

RTCC Timer

Alarm

WKDYHR

MINSEC

Event

Comparator

ALMTHDY

Compare Registers

with Masks

ALRMVAL

ALWDHR

ALMINSEC

Repeat Counter

RTCC Interrupt

RTCC Interrupt Logic

Alarm Pulse

RTCC Pin

RTCOE

Preliminary

DS39747C-page 149

PIC24FJ128GA FAMILY

The Alarm Value register window (ALRMVALH and

ALRMVALL) uses the ALRMPTR bits

(ALCFGRPT<9:8>) to select the desired alarm register

pair (see Table 18-2).

18.1 RTCC Module Registers

The RTCC module registers are organized into three

categories:

• RTCC Control Registers

• RTCC Value Registers

• Alarm Value Registers

By writing the ALRMVALH byte, the alarm pointer value

ALRMPTR<1:0> decrements by one until it reaches

‘00’. Once it reaches ‘00’, the ALRMMIN and

ALRMSEC value will be accessible through

ALRMVALH and ALRMVALL until the pointer value is

manually changed.

18.1.1

REGISTER MAPPING

To limit the register interface, the RTCC Timer and

Alarm Time registers are accessed through corre-

sponding register pointers. The RTCC Value register

window (RTCVALH and RTCVALL) uses the RTCPTR

bits (RCFGCAL<9:8>) to select the desired timer

register pair (see Table 18-1).

TABLE 18-2: ALRMVAL REGISTER

MAPPING

Alarm Value Register Window

ALRMPTR

<1:0>

ALRMVAL<15:8> ALRMVAL<7:0>

By writing the RTCVALH byte, the RTCC pointer value

RTCPTR<1:0> decrements by one until it reaches ‘00’.

Once it reaches ‘00’, the MINUTES and SECONDS

value will be accessible through RTCVALH and

RTCVALL until the pointer value is manually changed.

00

01

10

11

ALRMMIN

ALRMWD

ALRMMNTH

—

ALRMSEC

ALRMHR

ALRMDAY

—

TABLE 18-1: RTCVAL REGISTER MAPPING

Considering that the 16-bit core does not distinguish

between 8-bit and 16-bit read operations, the user must

be aware that when reading either the ALRMVALH or

ALRMVALL bytes will decrement the ALRMPTR<1:0>

value. The same applies to the RTCVALH or RTCVALL

bytes with the RTCPTR<1:0> being decremented.

RTCC Value Register Window

RTCPTR

<1:0>

RTCVAL<15:8> RTCVAL<7:0>

00

01

10

11

MINUTES

WEEKDAY

MONTH

—

SECONDS

HOURS

DAY

Note:

This only applies to read operations and

not write operations.

YEAR

DS39747C-page 150

Preliminary

PIC24FJ128GA FAMILY

18.1.2

RTCC CONTROL REGISTERS

(1)

REGISTER 18-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER

Upper Byte:

R/W-0

RTCEN⁽²⁾

bit 15

U-0

—

R/W-0

R-0

R/W-0

RTCWREN RTCSYNC HALFSEC RTCOE

RTCPTR1 RTCPTR0

bit 8

Lower Byte:

R/W-0

CAL7

R/W-0

CAL6

R/W-0

CAL5

R/W-0

CAL4

R/W-0

CAL3

R/W-0

CAL2

R/W-0

CAL1

R/W-0

CAL0

bit 7

bit 0

bit 15

RTCEN: RTCC Enable bit⁽²⁾

1= RTCC module is enabled

0= RTCC module is disabled

bit 14

bit 13

Unimplemented: Read as ‘0’

RTCWREN: RTCC Value Registers Write Enable bit

1= RTCVALH and RTCVALL registers can be written to by the user

0= RTCVALH and RTCVALL registers are locked out from being written to by the user

bit 12

RTCSYNC: RTCC Value Registers Read Synchronization bit

1= RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple

resulting in an invalid data read. If the register is read twice and results in the same data, the data can

be assumed to be valid.

0= RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple

bit 11

bit 10

HALFSEC: Half-Second Status bit

1= Second half period of a second

0= First half period of a second

Note:

This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.

RTCOE: RTCC Output Enable bit

1= RTCC output enabled

0= RTCC output disabled

Note 1: The RCFGCAL register is only affected by a POR.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 151

PIC24FJ128GA FAMILY

(1)

REGISTER 18-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER

(CONTINUED)

Upper Byte:

R/W-0

RTCEN⁽²⁾

bit 15

U-0

—

R/W-0

R-0

R/W-0

RTCWREN RTCSYNC HALFSEC RTCOE

RTCPTR1 RTCPTR0

bit 8

Lower Byte:

R/W-0

CAL7

R/W-0

CAL6

R/W-0

CAL5

R/W-0

CAL4

R/W-0

CAL3

R/W-0

CAL2

R/W-0

CAL1

R/W-0

CAL0

bit 7

bit 0

RTCPTR1:RTCPTR0: RTCC Value Register Window Pointer bits

bit 9-8

Points to the corresponding RTCC Value registers when reading RTCVALH and RTCVALL registers; the

RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.

RTCVAL<15:8>:

00= MINUTES

01= WEEKDAY

10= MONTH

11= Reserved

RTCVAL<7:0>:

00= SECONDS

01= HOURS

10= DAY

11= YEAR

bit 7-0

CAL7:CAL0: RTC Drift Calibration bits

01111111= Maximum positive adjustment; adds 508 RTC clock pulses every one minute

...

01111111= Minimum positive adjustment; adds 4 RTC clock pulses every one minute

00000000= No adjustment

11111111= Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute

...

10000000= Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute

Note 1: The RCFGCAL register is only affected by a POR.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 152

Preliminary

PIC24FJ128GA FAMILY

REGISTER 18-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER

Upper Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

RTSECSEL PMPTTL

bit 0

bit 7

bit 15-2 Unimplemented: Read as ‘0’

bit 1

bit 0

RTSECSEL: RTCC Seconds Clock Output Select bit

1= RTCC seconds clock is selected for the RTCC pin

0= RTCC alarm pulse is selected for the RTCC pin

Note:

To enable the actual RTCC output, the RTCCFG (RTCOE) bit needs to be set.

PMPTTL: PMP Module TTL Input Buffer Select bit

1= PMP module uses TTL input buffers

0= PMP module uses Schmitt input buffers

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at Reset

Preliminary

DS39747C-page 153

PIC24FJ128GA FAMILY

REGISTER 18-3: ALCFGRPT: ALARM CONFIGURATION REGISTER

Upper Byte:

R/W-0

ALRMEN

bit 15

R/W-0

CHIME

AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0

bit 8

Lower Byte:

R/W-0

ARPT7

ARPT6

ARPT5

ARPT4

ARPT3

ARPT2

ARPT1

ARPT0

bit 7

bit 0

bit 15

bit 14

ALRMEN: Alarm Enable bit

1= Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00 and

CHIME = 0)

0= Alarm is disabled

CHIME: Chime Enable bit

1= Chime is enabled; ARPT<7:0> is allowed to roll over from 00h to FFh

0= Chime is disabled; ARPT<7:0> stops once it reaches 00h

bit 13-10 AMASK3:AMASK0: Alarm Mask Configuration bits

0000= Every half second

0001= Every second

0010= Every 10 seconds

0011= Every minute

0100= Every 10 minutes

0101= Every hour

0110= Once a day

0111= Once a week

1000= Once a month

1001= Once a year (except when configured for February 29th, once every 4 years)

101x= Reserved – do not use

11xx= Reserved – do not use

bit 9-8

ALRMPTR1:ALRMPTR0: Alarm Value Register Window Pointer bits

Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers; the

ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’.

ALRMVAL<15:8>:

00= ALRMMIN

01= ALRMWD

10= ALRMMNTH

11= Unimplemented

ALRMVAL<7:0>:

00= ALRMSEC

01= ALRMHR

10= ALRMDAY

11= Unimplemented

bit 7-0

ARPT7:ARPT0: Alarm Repeat Counter Value bits

11111111= Alarm will repeat 255 more times

...

00000000= Alarm will not repeat

The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh

unless CHIME = 1.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 154

Preliminary

PIC24FJ128GA FAMILY

18.1.3

RTCVAL REGISTER MAPPINGS

(1)

REGISTER 18-4: YEAR: YEAR VALUE REGISTER

Upper Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

R/W-x

YRTEN3

bit 7

R/W-x

YRTEN1

R/W-x

YRTEN2

YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0

bit 0

bit 15-8 Unimplemented: Read as ‘0’

bit 7-4

bit 3-0

YRTEN3:YRTEN0: Binary Coded Decimal Value of Year’s Tens Digit; Contains a value from 0 to 9

YRONE3:YRONE0: Binary Coded Decimal Value of Year’s Ones Digit; Contains a value from 0 to 9

Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

(1)

REGISTER 18-5: MTHDY: MONTH AND DAY VALUE REGISTER

Upper Byte:

U-0

—

U-0

—

U-0

—

R-x

MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0

bit 8

bit 15

Lower Byte:

U-0

—

U-0

—

R/W-x

DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0

bit 0

bit 7

bit 15-13 Unimplemented: Read as ‘0’

bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; Contains a value of 0 or 1

bit 11-8 MTHONE3:MTHONE0: Binary Coded Decimal Value of Month’s Ones Digit; Contains a value from 0 to 9

bit 7-6

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

DAYTEN1:DAYTEN0: Binary Coded Decimal Value of Day’s Tens Digit; Contains a value from 0 to 3

DAYONE3:DAYONE0: Binary Coded Decimal Value of Day’s Ones Digit; Contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 155

PIC24FJ128GA FAMILY

(1)

REGISTER 18-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER

Upper Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-x

WDAY2

WDAY1

WDAY0

bit 15

bit 8

Lower Byte:

U-0

—

U-0

—

R/W-x

HRTEN1

R/W-x

HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0

bit 0

bit 7

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 WDAY2:WDAY0: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6

bit 7-6

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

HRTEN1:HRTEN0: Binary Coded Decimal Value of Hour’s Tens Digit; Contains a value from 0 to 2

HRONE3:HRONE0: Binary Coded Decimal Value of Hour’s Ones Digit; Contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

REGISTER 18-7: MINSEC: MINUTES AND SECONDS VALUE REGISTER

Upper Byte:

U-0

—

R/W-x

MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0

bit 8

bit 15

Lower Byte:

U-0

—

R/W-x

SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0

bit 0

bit 7

bit 15

Unimplemented: Read as ‘0’

bit 14-12 MINTEN2:MINTEN0: Binary Coded Decimal Value of Minute’s Tens Digit; Contains a value from 0 to 5

bit 11-8 MINONE3:MINONE0: Binary Coded Decimal Value of Minute’s Ones Digit; Contains a value from 0 to 9

bit 7

Unimplemented: Read as ‘0’

bit 6-4

bit 3-0

SECTEN2:SECTEN0: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from 0 to 5

SECONE3:SECONE0: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from 0 to 9

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 156

Preliminary

PIC24FJ128GA FAMILY

18.1.4

ALRMVAL REGISTER MAPPINGS

(1)

REGISTER 18-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER

Upper Byte:

U-0

—

U-0

—

U-0

—

R/W-x

MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0

bit 8

bit 15

Lower Byte:

U-0

—

U-0

—

R/W-x

DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0

bit 0

bit 7

bit 15-13 Unimplemented: Read as ‘0’

bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; Contains a value of 0 or 1

bit 11-8 MTHONE3:MTHONE0: Binary Coded Decimal Value of Month’s Ones Digit; Contains a value from 0 to 9

bit 7-6

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

DAYTEN1:DAYTEN0: Binary Coded Decimal Value of Day’s Tens Digit; Contains a value from 0 to 3

DAYONE3:DAYONE0: Binary Coded Decimal Value of Day’s Ones Digit; Contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

(1)

REGISTER 18-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER

Upper Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-x

WDAY0

bit 8

WDAY2

WDAY1

bit 15

Lower Byte:

U-0

—

U-0

—

R/W-x

HRTEN1

R/W-x

HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0

bit 0

bit 7

bit 15-11 Unimplemented: Read as ‘0’

bit 10-8 WDAY2:WDAY0: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6

bit 7-6

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

HRTEN1:HRTEN0: Binary Coded Decimal Value of Hour’s Tens Digit; Contains a value from 0 to 2

HRONE3:HRONE0: Binary Coded Decimal Value of Hour’s Ones Digit; Contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 157

PIC24FJ128GA FAMILY

REGISTER 18-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER

Upper Byte:

U-0

—

R/W-x

MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0

bit 8

bit 15

Lower Byte:

U-0

—

R/W-x

SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0

bit 0

bit 7

bit 15

Unimplemented: Read as ‘0’

bit 14-12 MINTEN2:MINTEN0: Binary Coded Decimal Value of Minute’s Tens Digit; Contains a value from 0 to 5

bit 11-8 MINONE3:MINONE0: Binary Coded Decimal Value of Minute’s Ones Digit; Contains a value from 0 to 9

bit 7

Unimplemented: Read as ‘0’

bit 6-4

bit 3-0

SECTEN2:SECTEN0: Binary Coded Decimal Value of Second’s Tens Digit; Contains a value from 0 to 5

SECONE3:SECONE0: Binary Coded Decimal Value of Second’s Ones Digit; Contains a value from 0 to 9

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

3. a) If the oscillator is faster then ideal (negative

result form step 2), the RCFGCAL register value

needs to be negative. This causes the specified

number of clock pulses to be subtracted from

the timer counter once every minute.

18.2 Calibration

The real-time crystal input can be calibrated using the

periodic auto-adjust feature. When properly calibrated,

the RTCC can provide an error of less than 3 seconds

per month. This is accomplished by finding the number

of error clock pulses and storing the value into the

lower half of the RCFGCAL register. The 8-bit signed

value loaded into the lower half of RCFGCAL is multi-

plied by four and will be either added or subtracted from

the RTCC timer, once every minute. Refer to the steps

below for RTCC calibration:

b) If the oscillator is slower then ideal (positive

result from step 2) the RCFGCAL register value

needs to be positive. This causes the specified

number of clock pulses to be subtracted from

the timer counter once every minute.

4. Load the RCFGCAL register with the correct

value.

1. Using another timer resource on the device, the

user must find the error of the 32.768 kHz

crystal.

Writes to the lower half of the RCFGCAL register

should only occur when the timer is turned off, or

immediately after the rising edge of the seconds pulse.

2. Once the error is known, it must be converted to

the number of error clock pulses per minute.

Note:

It is up to the user to include in the error

value the initial error of the crystal, drift

due to temperature and drift due to crystal

aging.

Formula box:

(Ideal frequency (32,768) – measured frequency)

* 60 = clocks per minute

DS39747C-page 158

Preliminary

PIC24FJ128GA FAMILY

After each alarm is issued, the ALCFGRPT register is

decremented by one. Once the register has reached

‘00’, the alarm will be issued one last time, after which

the ALRMEN bit will be cleared automatically and the

alarm will turn off. Indefinite repetition of the alarm can

occur if the CHIME bit = 1. Instead of the alarm being

disabled when the ALCFGRPT register reaches ‘00’, it

will roll over to FF and continue counting indefinitely

when CHIME = 1.

18.3 Alarm

• Configurable from half second to one year

• Enabled using the ALRMEN bit (ALCFGRPT<7>,

Register 18-3)

• One-time alarm and repeat alarm options

available

18.3.1

CONFIGURING THE ALARM

The alarm feature is enabled using the ALRMEN bit.

This bit is cleared when an alarm is issued. Writes to

ALRMVALH:ALRMVALL should only take place when

ALRMEN = 0.

18.3.2

ALARM INTERRUPT

At every alarm event an interrupt is generated. In addi-

tion, an alarm pulse output is provided that operates at

half the frequency of the alarm. This output is

completely synchronous to the RTCC clock and can be

used as a trigger clock to other peripherals.

As shown in Figure 18-2, the interval selection of the

alarm is configured through the AMASK bits

(ALCFGRPT<13:10>). These bits determine which and

how many digits of the alarm must match the clock

value for the alarm to occur. The alarm can also be con-

figured to repeat based on a preconfigured interval.

The amount of times this occurs once the alarm is

enabled is stored in the lower half of the ALCFGRPT

register.

Note:

Changing any of the registers, other then

the RCFGCAL and ALCFGRPT registers

and the CHIME bit while the alarm is

enabled (ALRMEN = 1), can result in a

false alarm event leading to a false alarm

interrupt. To avoid a false alarm event, the

timer and alarm values should only be

changed while the alarm is disabled

(ALRMEN = 0). It is recommended that the

ALCFGRPT register and CHIME bit be

changed when RTCSYNC = 0.

When ALCFGRPT

= 00 and CHIME bit = 0

(ALCFGRPT<14>), the repeat function is disabled and

only a single alarm will occur. The alarm can be

repeated up to 255 times by loading the lower half of

the ALCFGRPT register with FFh.

FIGURE 18-2:

ALARM MASK SETTINGS

Day of

the

Week

Alarm Mask Setting

(AMASK3:AMASK0)

Month

Day

Hours

Minutes

Seconds

0000– Every half second

0001– Every second

0010– Every 10 seconds

0011– Every minute

0100– Every 10 minutes

0101– Every hour

s

m

0110– Every day

h

0111– Every week

1000– Every month

1001– Every year⁽¹⁾

d

m

d

Note 1: Annually, except when configured for February 29.

Preliminary

DS39747C-page 159

PIC24FJ128GA FAMILY

NOTES:

DS39747C-page 160

Preliminary

PIC24FJ128GA FAMILY

19.1 Registers

19.0 PROGRAMMABLE CYCLIC

REDUNDANCY CHECK (CRC)

GENERATOR

There are four registers used to control programmable

CRC operation:

• CRCCON

• CRCXOR

• CRCDAT

• CRCWDAT

The programmable CRC generator offers the following

features:

• User-programmable polynomial CRC equation

• Interrupt output

• Data FIFO

REGISTER 19-1: CRCCON: CRC CONTROL REGISTER

Upper Byte:

U-0

—

U-0

—

R/W-0

CSIDL

R-0

VWORD4 VWORD3 VWORD2 VWORD1 VWORD0

bit 8

bit 15

Lower Byte:

R-0

R-1

U-0

—

R/W-0

CRCFUL CRCMPT

bit 7

CRCGO

PLEN3

PLEN2

PLEN1

PLEN0

bit 0

bit 15-14 Unimplemented: Read as ‘0’

bit 13 CSIDL: CRC Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-8 VWORD4:VWORD0: Pointer Value bits

Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN3:PLEN0 > 7,

or 16 when PLEN3:PLEN0 ≤ 7.

bit 7

bit 6

CRCFUL: FIFO Full bit

1= FIFO is full

0= FIFO is not full

CRCMPT: FIFO Empty Bit

1= FIFO is empty

0= FIFO is not empty

bit 5

bit 4

Unimplemented: Read as ‘0’

CRCGO: Start CRC bit

1= Start CRC serial shifter

0= CRC serial shifter turned off

bit 3-0

PLEN3:PLEN0: Polynomial Length bits

Denotes the length of the polynomial to be generated minus 1.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 161

PIC24FJ128GA FAMILY

TABLE 19-1: EXAMPLE CRC SETUP

19.2 Overview

Bit Name

Bit Value

The module implements a software configurable CRC

generator. The terms of the polynomial and its length

can be programmed using the CRCXOR (X<15:1>) bits

and the CRCCON (PLEN3:PLEN0) bits, respectively.

PLEN3:PLEN0

X<15:1>

1111

000100000010000

Note that for the value of X<15:1>, the 12th bit and the

5th bit are set to ‘1’, as required by the equation. The

0th bit required by the equation is always XORed. For

a 16-bit polynomial, the 16th bit is also always

assumed to be XORed; therefore, the X<15:1> bits do

not have the 0th bit or the 16th bit.

Consider the CRC equation:

x

¹⁶+ x¹²+ x⁵+ 1

To program this polynomial into the CRC generator,

the CRC register bits should be set as shown in

Table 19-1.

The topology of a standard CRC generator is shown in

Figure 19-2.

FIGURE 19-1:

CRC SHIFTER DETAILS

PLEN<3:0>

0

1

2

15

CRC Shift Register

Hold

X2

Hold

X1

X3

X15

0

XOR

OUT

IN

BIT 0

IN

BIT 1

IN

BIT 2

IN

BIT 15

DOUT

1

p_clk

CRC Read Bus

CRC Write Bus

DS39747C-page 162

Preliminary

PIC24FJ128GA FAMILY

16

12

5

FIGURE 19-2:

CRC GENERATOR RECONFIGURED FOR x + x + x + 1

XOR

D

Q

D

Q

D

Q

D

Q

D

Q

SDOx

BIT 0

BIT 4

BIT 5

BIT 12

BIT 15

p_clk

CRC Read Bus

CRC Write Bus

To empty words already written into a FIFO, the

CRCGO bit must be set to ‘1’ and the CRC shifter

allowed to run until the CRCMPT bit is set.

19.3 User Interface

19.3.1

DATA INTERFACE

Also, to get the correct CRC reading, it will be

necessary to wait for the CRCMPT bit to go high before

reading the CRCWDAT register.

To start serial shifting, a ‘1’ must be written to the

CRCGO bit.

The module incorporates a FIFO that is 8 deep when

PLEN (PLEN<3:0>) > 7, and 16 deep otherwise. The

data for which the CRC is to be calculated must first be

written into the FIFO. The smallest data element that

can be written into the FIFO is one byte. For example,

if PLEN = 5, then the size of the data is PLEN + 1 = 6.

The data must be written as follows:

If a word is written when the CRCFUL bit is set, the

VWORD pointer will roll over to 0. The hardware will

then behave as if the FIFO is empty. However, the con-

dition to generate an interrupt will not be met; therefore,

no interrupt will be generated (See Section 19.3.2

“Interrupt Operation”).

At least one instruction cycle must pass after a write to

CRCWDAT before a read of the VWORD bits is done.

data[5:0] = crc_input[5:0]

data[7:6] = ‘bxx

Once data is written into the CRCWDAT MSb (as

defined by PLEN), the value of VWORD

(VWORD<4:0>) increments by one. The serial shifter

starts shifting data into the CRC engine when

CRCGO = 1 and VWORD > 0. When the MSb is

shifted out, VWORD decrements by one. The serial

shifter continues shifting until the VWORD reaches 0.

Therefore, for a given value of PLEN, it will take

(PLEN + 1) * VWORD number of clock cycles to

complete the CRC calculations.

19.3.2

INTERRUPT OPERATION

When VWORD4:VWORD0 makes a transition from a

value of ‘1’ to ‘0’, an interrupt will be generated.

19.4 Operation in Power Save Modes

19.4.1

SLEEP MODE

If Sleep mode is entered while the module is operating,

the module will be suspended in its current state until

clock execution resumes.

When VWORD reaches 8 (or 16), the CRCFUL bit will

be set. When VWORD reaches 0, the CRCMPT bit will

be set.

19.4.2

IDLE MODE

To continue full module operation in Idle mode, the

CSIDL bit must be cleared prior to entry into the mode.

To continually feed data into the CRC engine, the rec-

ommended mode of operation is to initially “prime” the

FIFO with a sufficient number of words so no interrupt

is generated before the next word can be written. Once

that is done, start the CRC by setting the CRCGO bit to

‘1’. From that point onward, the VWORD bits should be

polled. If they read less than 8 or 16, another word can

be written into the FIFO.

If CSIDL = 1, the module will behave the same way as

it does in Sleep mode; pending interrupt events will be

passed on, even though the module clocks are not

available.

Preliminary

DS39747C-page 163

PIC24FJ128GA FAMILY

NOTES:

DS39747C-page 164

Preliminary

PIC24FJ128GA FAMILY

To perform an A/D conversion:

1. Configure the A/D module:

20.0 10-BIT HIGH-SPEED A/D

CONVERTER

a) Select port pins as analog inputs

(AD1PCFG<15:0>).

Note:

This data sheet summarizes the features

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

b) Select voltage reference source to match

expected range on analog inputs

(AD1CON2<15:13>).

The 10-bit A/D converter has the following key

features:

c) Select the analog conversion clock to

match desired data rate with processor

clock (AD1CON3<7:0>).

• Successive Approximation (SAR) conversion

• Conversion speeds of up to 500 ksps

• Up to 16 analog input pins

d) Select the appropriate sample/conversion

sequence

(AD1CON1<7:0>

and

AD1CON3<12:8>).

• External voltage reference input pins

• Automatic Channel Scan mode

e) Select how conversion results are

presented in the buffer (AD1CON1<9:8>).

• Selectable conversion trigger source

• 16-word conversion result buffer

• Selectable Buffer Fill modes

f) Select interrupt rate (AD1CON2<5:2>).

g) Turn on A/D module (AD1CON1<15>).

2. Configure A/D interrupt (if required):

a) Clear the AD1IF bit.

• Four result alignment options

• Operation during CPU Sleep and Idle modes

b) Select A/D interrupt priority.

Depending on the particular device pinout, the 10-bit

A/D converter can have up to 16 analog input pins, des-

ignated AN0 through AN15. In addition, there are two

analog input pins for external voltage reference con-

nections. These voltage reference inputs may be

shared with other analog input pins. The actual number

of analog input pins and external voltage reference

input configuration will depend on the specific device.

Refer to the device data sheet for further details.

A block diagram of the A/D converter is shown in

Figure 20-1.

Preliminary

DS39747C-page 165

PIC24FJ128GA FAMILY

Figure 20-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM

Internal Data Bus

16

AVDD

VR+

AVSS

VREF+

VR-

Comparator

VREF-

VINH

VR- VR+

S/H

DAC

VINL

AN0

AN1

VINH

10-Bit SAR

Conversion Logic

AN2

AN3

Data Formatting

AN4

AN5

VINL

AN6

ADC1BUF0:

ADC1BUFF

AN7

AN8

AD1CON1

AD1CON2

AD1CON3

AD1CHS

AN9

VINH

AN10

AN11

AN12

AN13

AN14

AN15

AD1PCFG

AD1CSSL

VINL

Sample Control

Control Logic

Conversion Control

Input MUX Control

Pin Config. Control

DS39747C-page 166

Preliminary

PIC24FJ128GA FAMILY

REGISTER 20-1: AD1CON1: A/D CONTROL REGISTER 1

Upper Byte:

R/W-0

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

ADON

ADSIDL

FORM1

FORM0

bit 15

bit 8

Lower Byte:

R/W-0

U-0

—

U-0

—

R/W-0

ASAM

R/W-0 HCS R/C-0 HCS

SAMP DONE

bit 0

SSRC2

SSRC1

SSRC0

bit 7

bit 15

ADON: A/D Operating Mode bit

1= A/D converter module is operating

0= A/D converter is off

bit 14

bit 13

Unimplemented: Read as ‘0’

ADSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-10 Unimplemented: Read as ‘0’

bit 9-8

FORM1:FORM0: Data Output Format bits

11= Signed fractional (sddd dddd dd00 0000)

10= Fractional (dddd dddd dd00 0000)

01= Signed integer (ssss sssd dddd dddd)

00= Integer (0000 00dd dddd dddd)

bit 7-5

SSRC2:SSRC0: Conversion Trigger Source Select bits

111= Internal counter ends sampling and starts conversion (auto-convert)

110= Reserved

10x= Reserved

011= Reserved

010= Timer3 compare ends sampling and starts conversion

001= Active transition on INT0 pin ends sampling and starts conversion

000= Clearing SAMP bit ends sampling and starts conversion

bit 4-3

bit 2

Unimplemented: Read as ‘0’

ASAM: A/D Sample Auto-Start bit

1= Sampling begins immediately after last conversion completes. SAMP bit is auto-set.

0= Sampling begins when SAMP bit is set

bit 1

bit 0

SAMP: A/D Sample Enable bit

1= A/D sample/hold amplifier is sampling input

0= A/D sample/hold amplifier is holding

DONE: A/D Conversion Status bit

1= A/D conversion is done

0= A/D conversion is NOT done

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

C = Clear-Only bit

‘0’ = Bit is cleared

HCS = Hardware Cleared/Set

x = Bit is unknown

Preliminary

DS39747C-page 167

PIC24FJ128GA FAMILY

REGISTER 20-2: AD1CON2: A/D CONTROL REGISTER 2

Upper Byte:

R/W-0

U-0

r

U-0

—

R/W-0

U-0

—

U-0

—

VCFG2

VCFG1

VCFG0

CSCNA

bit 15

bit 8

Lower Byte:

R-0

U-0

—

R/W-0

SMPI3

R/W-0

SMPI2

R/W-0

SMPI1

R/W-0

SMPI0

R/W-0

BUFM

R/W-0

ALTS

BUFS

bit 7

bit 0

bit 15-13 VCFG2:VCFG0: Voltage Reference Configuration bits:

VCFG2:VCFG0

VR+

VR-

000

001

010

011

1xx

AVDD

External VREF+ pin

AVDD

AVSS

External VREF- pin

AVSS

External VREF+ pin

AVDD

bit 12

bit 11

bit 10

Reserved: User should write ‘0’ to this location

Unimplemented: Read as ‘0’

CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit

1= Scan inputs

0= Do not scan inputs

bit 9-8

bit 7

Unimplemented: Read as ‘0’

BUFS: Buffer Fill Status bit (Valid only when BUFM = 1)

1= A/D is currently filling buffer 08-0F, user should access data in 00-07

0= A/D is currently filling buffer 00-07, user should access data in 08-0F

bit 6

Unimplemented: Read as ‘0’

bit 5-2

SMPI3:SMPI0: Sample/Convert Sequences Per Interrupt Selection bits

1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence

1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence

.....

0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence

0000 = Interrupts at the completion of conversion for each sample/convert sequence

bit 1

bit 0

BUFM: Buffer Mode Select bit

1 = Buffer configured as two 8-word buffers (ADC1BUFn<15:8> and ADC1BUFn<7:0>)

0 = Buffer configured as one 16-word buffer (ADC1BUFn<15:0>)

ALTS: Alternate Input Sample Mode Select bit

1= Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A

input multiplexer settings for all subsequent samples

0= Always use MUX A input multiplexer settings

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 168

Preliminary

PIC24FJ128GA FAMILY

REGISTER 20-3: AD1CON3: A/D CONTROL REGISTER 3

Upper Byte:

R/W-0

U-0

—

U-0

—

R/W-0

ADRC

SAMC4

SAMC3

SAMC2

SAMC1

SAMC0

bit 15

bit 8

Lower Byte:

R/W-0

ADCS6

R/W-0

ADCS5

R/W-0

ADCS4

R/W-0

ADCS3

R/W-0

ADCS1

R/W-0

ADCS7

ADCS2

ADCS0

bit 7

bit 0

bit 15

ADRC: A/D Conversion Clock Source bit

1= A/D internal RC clock

0= Clock derived from system clock

bit 14-13 Unimplemented: Read as ‘0’

bit 12-8 SAMC4:SAMC0: Auto-Sample Time bits

11111= 31 TAD

·····

00001= 1 TAD

00000= 0 TAD (not recommended)

bit 7-0

ADCS7:ADCS0: A/D Conversion Clock Select bits

11111111= 128 • TCY

······

00000001= TCY

00000000= TCY/2

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 169

PIC24FJ128GA FAMILY

REGISTER 20-4: AD1CHS: A/D INPUT SELECT REGISTER

Upper Byte:

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

CH0NB

CH0SB3

CH0SB2

CH0SB1

CH0SB0

bit 15

bit 8

Lower Byte:

R/W-0

U-0

—

U-0

—

U-0

R/W-0

CH0SA3

R/W-0

CH0NA

—

CH0SA2

CH0SA1

CH0SA0

bit 7

bit 0

bit 15

CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit

1= Channel 0 negative input is AN1

0= Channel 0 negative input is VR-

bit 14-12 Unimplemented: Read as ‘0’

bit 11-8 CH0SB3:CH0SB0: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits

1111= Channel 0 positive input is AN15

1110= Channel 0 positive input is AN14

·····

0001= Channel 0 positive input is AN1

0000= Channel 0 positive input is AN0

bit 7

CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit

1= Channel 0 negative input is AN1

0= Channel 0 negative input is VR-

bit 6-4

bit 3-0

Unimplemented: Read as ‘0’

CH0SA3:CH0SA0: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits

1111= Channel 0 positive input is AN15

1110= Channel 0 positive input is AN14

·····

0001= Channel 0 positive input is AN1

0000= Channel 0 positive input is AN0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 170

Preliminary

PIC24FJ128GA FAMILY

REGISTER 20-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER

Upper Byte:

R/W-0

PCFG15

bit 15

PCFG14

PCFG13

PCFG12

PCFG11

PCFG10

PCFG9

PCFG8

bit 8

Lower Byte:

R/W-0

PCFG6

R/W-0

PCFG5

R/W-0

PCFG4

R/W-0

PCFG3

R/W-0

PCFG1

R/W-0

PCFG7

PCFG2

PCFG0

bit 7

bit 0

bit 15-0 PCFG15:PCFG0: Analog Input Pin Configuration Control bits

1= Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled

0= Pin configured in Analog mode; I/O port read disabled, A/D samples pin voltage

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

REGISTER 20-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER

Upper Byte:

R/W-0

CSSL15

bit 15

R/W-0

CSSL14

CSSL13

CSSL12

CSS1L1

CSSL10

CSSL9

CSSL8

bit 8

Lower Byte:

R/W-0

CSSL6

R/W-0

CSSL5

R/W-0

CSSL4

R/W-0

CSSL3

R/W-0

CSSL1

R/W-0

CSSL7

CSSL2

CSSL0

bit 7

bit 0

bit 15-0 CSSL15:CSSL0: A/D Input Pin Scan Selection bits

1= Corresponding analog channel selected for input scan

0= Analog channel omitted from input scan

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

(1)

EQUATION 20-1: A/D CONVERSION CLOCK PERIOD

TAD = TCY(ADCS + 1)

TAD

– 1

ADCS =

TCY

Note 1: Based on TCY = FOSC/2, Doze mode and PLL are disabled.

Preliminary

DS39747C-page 171

PIC24FJ128GA FAMILY

FIGURE 20-2:

10-BIT A/D CONVERTER ANALOG INPUT MODEL

VDD

RIC ≤ 250Ω

RSS ≤ 5 kΩ (Typical)

Sampling

Switch

VT = 0.6V

ANx

RSS

Rs

CHOLD

= DAC capacitance

= 4.4 pF (Typical)

VA

CPIN

ILEAKAGE

±500 nA

6-11 pF

(Typical)

VSS

Legend: CPIN

VT

= Input Capacitance

= Threshold Voltage

ILEAKAGE = Leakage Current at the pin due to

various junctions

RIC

= Interconnect Resistance

RSS

= Sampling Switch Resistance

= Sample/Hold Capacitance (from DAC)

CHOLD

Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ.

FIGURE 20-3:

A/D TRANSFER FUNCTION

Output Code

(Binary (Decimal))

11 1111 1111(1023)

11 1111 1110(1022)

10 0000 0011(515)

10 0000 0010(514)

10 0000 0001(513)

10 0000 0000(512)

01 1111 1111(511)

01 1111 1110(510)

01 1111 1101(509)

00 0000 0001(1)

00 0000 0000(0)

Voltage Level

DS39747C-page 172

Preliminary

PIC24FJ128GA FAMILY

21.0 COMPARATOR MODULE

Note:

This data sheet summarizes the features

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

FIGURE 21-1:

COMPARATOR I/O OPERATING MODES

C1NEG

CMCON<6>

C1EN

C1

C1INV

C1IN+

C1IN-

VIN-

VIN+

C1OUT

C1POS

C1IN+

CVREF

C1OUTEN

C2NEG

C2POS

CMCON<7>

C2EN

C2

C2INV

C2IN+

C2IN-

VIN-

VIN+

C2OUT

C2IN+

CVREF

C2OUTEN

Preliminary

DS39747C-page 173

PIC24FJ128GA FAMILY

REGISTER 21-1: CMCON: COMPARATOR CONTROL REGISTER

Upper Byte:

R/W-0

U-0

—

R/C-0

R/W-0

C2EN

R/W-0

C1EN

R/W-0

CMIDL

C2EVT

C1EVT

C2OUTEN C1OUTEN

bit 8

bit 15

Lower Byte:

R-0

C1OUT

R/W-0

C2INV

R/W-0

C1INV

R/W-0

C2NEG

R/W-0

C1NEG

R/W-0

C2OUT

C2POS

C1POS

bit 7

bit 0

bit 15

CMIDL: Stop in Idle Mode

1= When device enters Idle mode, module does not generate interrupts. Module is still enabled.

0= Continue normal module operation in Idle mode

bit 14

bit 13

Unimplemented: Read as ‘0’

C2EVT: Comparator 2 Event

1= Comparator output changed states

0= Comparator output did not change states

bit 12

bit 11

bit 10

bit 9

C1EVT: Comparator 1 Event

1= Comparator output changed states

0= Comparator output did not change states

C2EN: Comparator 2 Enable

1= Comparator is enabled

0= Comparator is disabled

C1EN: Comparator 1 Enable

1= Comparator is enabled

0= Comparator is disabled

C2OUTEN: Comparator 2 Output Enable

1= Comparator output is driven on the output pad

0= Comparator output is not driven on the output pad

bit 8

C1OUTEN: Comparator 1 Output Enable

1= Comparator output is driven on the output pad

0= Comparator output is not driven on the output pad

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 174

Preliminary

PIC24FJ128GA FAMILY

REGISTER 21-1: CMCON: COMPARATOR CONTROL REGISTER (CONTINUED)

Upper Byte:

R/W-0

U-0

—

R/C-0

R/W-0

C2EN

R/W-0

C1EN

R/W-0

CMIDL

C2EVT

C1EVT

C2OUTEN C1OUTEN

bit 8

bit 15

Lower Byte:

R-0

C1OUT

R/W-0

C2INV

R/W-0

C1INV

R/W-0

C2NEG

R/W-0

C1NEG

R/W-0

C2OUT

C2POS

C1POS

bit 7

bit 0

bit 7

C2OUT: Comparator 2 Output bit

When C2INV = 0:

1= C2 VIN+ > C2 VIN-

0= C2 VIN+ < C2 VIN-

When C2INV = 1:

0= C2 VIN+ > C2 VIN-

1= C2 VIN+ < C2 VIN-

bit 6

C1OUT: Comparator 1 Output bit

When C1INV = 0:

1= C1 VIN+ > C1 VIN-

0= C1 VIN+ < C1 VIN-

When C1INV = 1:

0= C1 VIN+ > C1 VIN-

1= C1 VIN+ < C1 VIN-

bit 5

bit 4

bit 3

C2INV: Comparator 2 Output Inversion bit

1= C2 output inverted

0= C2 output not inverted

C1INV: Comparator 1 Output Inversion bit

1= C1 output inverted

0= C1 output not inverted

C2NEG: Comparator 2 Negative Input Configure bit

1= Input is connected to VIN+

0= Input is connected to VIN-

See Figure 21-1 for the comparator modes.

bit 2

bit 1

bit 0

C2POS: Comparator 2 Positive Input Configure bit

1= Input is connected to VIN+

0= Input is connected to CVREF

See Figure 21-1 for the comparator modes.

C1NEG: Comparator 1 Negative Input Configure bit

1= Input is connected to VIN+

0= Input is connected to VIN-

See Figure 21-1 for the comparator modes.

C1POS: Comparator 1 Positive Input Configure bit

1= Input is connected to VIN+

0= Input is connected to CVREF

See Figure 21-1 for the comparator modes.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS39747C-page 175

PIC24FJ128GA FAMILY

NOTES:

DS39747C-page 176

Preliminary

PIC24FJ128GA FAMILY

voltage, each with 16 distinct levels. The range to be

used is selected by the CVRR bit (CVRCON<5>). The

primary difference between the ranges is the size of the

steps selected by the CVREF Selection bits

(CVR3:CVR0), with one range offering finer resolution.

22.0 COMPARATOR VOLTAGE

REFERENCE

Note:

This data sheet summarizes the features

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

The comparator reference supply voltage can come

from either VDD and VSS, or the external VREF+ and

VREF-. The voltage source is selected by the CVRSS

bit (CVRCON<4>).

22.1 Configuring the Comparator

Voltage Reference

The settling time of the comparator voltage reference

must be considered when changing the CVREF

output.

The voltage reference module is controlled through the

CVRCON register (Register 22-1). The comparator

voltage reference provides two ranges of output

FIGURE 22-1:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

CVRSS = 1

CVRSS = 0

VREF+

AVDD

8R

CVR3:CVR0

R

CVREN

R

16 Steps

CVREF

R

CVRR

VREF-

8R

CVRSS = 1

CVRSS = 0

AVSS

Preliminary

DS39747C-page 177

PIC24FJ128GA FAMILY

REGISTER 22-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER

Upper Byte:

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

Lower Byte:

R/W-0

CVRR

R/W-0

CVRSS

R/W-0

CVR3

R/W-0

CVR2

R/W-0

CVR1

R/W-0

CVR0

CVREN

CVROE

bit 7

bit 0

bit 15-8 Unimplemented: Read as ‘0’

bit 7

bit 6

bit 5

bit 4

bit 3-0

CVREN: Comparator Voltage Reference Enable bit

1= CVREF circuit powered on

0= CVREF circuit powered down

CVROE: Comparator VREF Output Enable bit

1= CVREF voltage level is output on CVREF pin

0= CVREF voltage level is disconnected from CVREF pin

CVRR: Comparator VREF Range Selection bit

1= 0 to 0.67 CVRSRC, with CVRSRC/24 step size

0= 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size

CVRSS: Comparator VREF Source Selection bit

1= Comparator reference source CVRSRC = VREF+ – VREF-

0= Comparator reference source CVRSRC = AVDD – AVSS

CVR3:CVR0: Comparator VREF Value Selection 0 ≤ CVR3:CVR0 ≤ 15 bits

When CVRR = 1:

CVREF = (CVR<3:0>/ 24) • (CVRSRC)

When CVRR = 0:

CVREF = 1/4 • (CVRSRC) + (CVR<3:0>/32) • (CVRSRC)

Legend:

R = Readable bit

W = Writable bit

‘1’ = bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = bit is cleared x = bit is unknown

-n = Value at Reset

DS39747C-page 178

Preliminary

PIC24FJ128GA FAMILY

TABLE 23-1: FLASH CONFIGURATION

WORDS LOCATIONS FOR

PIC24FJ128GA FAMILY

DEVICES

23.0 SPECIAL FEATURES

Note:

This data sheet summarizes the features

of this group of PIC24FJ devices. It is not

intended to be a comprehensive reference

source.

Configuration Word

Addresses

Device

PIC24FJ128GA family devices include several

features intended to maximize application flexibility and

reliability, and minimize cost through elimination of

external components. These are:

1

2

PIC24FJ64GA

PIC24FJ96GA

PIC24FJ128GA

00ABFEh

00FFFEh

0157FEh

00ABFCh

00FFFCh

0157FCh

• Flexible Configuration

• Watchdog Timer (WDT)

• Code Protection

When creating applications for these devices, users

should always specifically allocate the location of the

Flash Configuration Word for configuration data. This is

to make certain that program code is not stored in this

address when the code is compiled.

• JTAG Boundary Scan Interface

• In-Circuit Serial Programming

• In-Circuit Emulation

The volatile memory cells used for the Configuration

bits always reset to ‘1’ on Power-on Resets. For all

other type of Reset events, the previously programmed

values are maintained and used without reloading from

program memory.

23.1 Configuration Bits

The Configuration bits can be programmed (read as

‘0’), or left unprogrammed (read as ‘1’), to select vari-

ous device configurations. These bits are mapped

starting at program memory location F80000h. A com-

plete list is shown in Table 23-1. A detailed explanation

of the various bit functions is provided in Register 23-1

through Register 23-4.

The upper byte of both Flash Configuration Words in

program memory should always be ‘1111 1111’. This

makes them appear to be NOP instructions in the

remote event that their locations are ever executed by

accident. Since Configuration bits are not implemented

in the corresponding locations, writing ‘1’s to these

locations has no effect on device operation.

Note that address F80000h is beyond the user program

memory space. In fact, it belongs to the configuration

memory space (800000h-FFFFFFh) which can only be

accessed using table reads and table writes.

To prevent inadvertent configuration changes during

code execution, all programmable Configuration bits

are write-once. After a bit is initially programmed during

a power cycle, it cannot be written to again. Changing

a device configuration requires that power to the device

be cycled.

23.1.1

CONSIDERATIONS FOR

CONFIGURING PIC24FJ128GA

FAMILY DEVICES

In PIC24FJ128GA family devices, the configuration

bytes are implemented as volatile memory. This means

that configuration data must be programmed each time

the device is powered up. Configuration data is stored

in the two words at the top of the on-chip program

memory space, known as the Flash Configuration

Words. Their specific locations are shown in

Table 23-1. These are packed representations of the

actual device Configuration bits, whose actual

locations are distributed among five locations in config-

uration space. The configuration data is automatically

loaded from the Flash Configuration Words to the

proper Configuration registers during device Resets.

Preliminary

DS39747C-page 179

PIC24FJ128GA FAMILY

REGISTER 23-1: FLASH CONFIGURATION WORD 1

Upper Third:

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

bit 23

bit 16

Middle Third:

r-0

R/PO-1

GCP

R/PO-1

GWRP

R/PO-1

DEBUG

R/PO-1

COE

U-1

—

R/PO-1

ICS

bit 8

r

JTAGEN

bit 15

Lower Third:

R/PO-1

WINDIS

U-1

R/PO-1

FWPSA

R/PO-1

WDTPS3

R/PO-1

WDTPS2

R/PO-1

WDTPS1

R/PO-1

FWDTEN

bit 7

—

WDTPS0

bit 0

bit 23-16 Unimplemented: Read as ‘0’

bit 15

bit 14

Reserved: Maintain as ‘1’

JTAGEN: JTAG Port Enable bit

1= JTAG port is enabled

0= JTAG port is disabled

bit 13

bit 12

bit 11

bit 10

GCP: General Segment Program Memory Code Protection bit

1= Code protection is disabled

0= Code protection is enabled for the entire program memory space

GWRP: General Segment Code Flash Write Protection bit

1= Writes to program memory are allowed

0= Writes to program memory are disabled

DEBUG: Background Debugger Enable bit

1= Device resets into Operational mode

0= Device resets into Debug mode

COE: Set Clip On Emulation bit

1= Device resets into Operational mode

0= Device resets into Clip On Emulation mode

bit 9

bit 8

Unimplemented: Read as ‘1’

ICS: ICD Pin Placement Select bit

1= ICD uses EMUC2/EMUD2

0= ICD uses EMUC1/EMUD1

bit 7

bit 6

bit 5

FWDTEN: Watchdog Timer Enable bit

1= Watchdog Timer is enabled

0= Watchdog Timer is disabled

WINDIS: Windowed Watchdog Timer Disable bit

1= Standard Watchdog Timer enabled

0= Windowed Watchdog Timer enabled; FWDTEN must be ‘1’

Unimplemented: Read as ‘1’

Legend:

R = Readable bit

PO = Program-Once bit

‘1’ = Bit is set

U = Unimplemented, read as ‘1’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value when unprogrammed

DS39747C-page 180

Preliminary

PIC24FJ128GA FAMILY

REGISTER 23-1: FLASH CONFIGURATION WORD 1 (CONTINUED)

Upper Third:

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

bit 23

bit 16

Middle Third:

r-0

R/PO-1

GCP

R/PO-1

GWRP

R/PO-1

DEBUG

R/PO-1

COE

U-1

—

R/PO-1

ICS

bit 8

r

JTAGEN

bit 15

Lower Third:

R/PO-1

WINDIS

U-1

R/PO-1

FWPSA

R/PO-1

WDTPS3

R/PO-1

WDTPS2

R/PO-1

WDTPS1

R/PO-1

FWDTEN

bit 7

—

WDTPS0

bit 0

bit 4

FWPSA: WDT Prescaler Ratio Select bit

1= Prescaler ratio of 1:128

0= Prescaler ratio of 1:32

bit 3-0

WDTPS3:WDTPS0: Watchdog Timer Postscaler Select bits

1111= 1:32,768

1110= 1:16,384

1101= 1:8,192

1100= 1:4,096

1011= 1:2,048

1010= 1:1,024

1001= 1:512

1000= 1:256

0111= 1:128

0110= 1:64

0101= 1:32

0100= 1:16

0011= 1:8

0010= 1:4

0001= 1:2

0000= 1:1

Legend:

R = Readable bit

PO = Program-Once bit

‘1’ = Bit is set

U = Unimplemented, read as ‘1’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value when unprogrammed

Preliminary

DS39747C-page 181

PIC24FJ128GA FAMILY

REGISTER 23-2: FLASH CONFIGURATION WORD 2

Upper Third:

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

bit 23

bit 16

Middle Third:

R/PO-1

IESO

U-1

—

U-1

—

U-1

—

U-1

—

R/PO-1

FNOSC2 FNOSC1 FNOSC0

bit 8

bit 15

Lower Third:

R/PO-1

U-1

—

U-1

—

U-1

—

R/PO-1

FCKSM1 FCKSM0 OSCIOFCN

bit 7

POSCMD1 POSCMD0

bit 0

bit 23-16 Unimplemented: Read as ‘1’

bit 15 IESO: Internal External Switchover bit

1= IESO mode (Two-Speed Start-up) enabled

0= IESO mode (Two-Speed Start-up) disabled

bit 14-11 Unimplemented: Read as ‘1’

bit 10-8 FNOSC2:FNOSC0: Initial Oscillator Select bits

111= Fast RC Oscillator with Postscaler (FRCDIV)

110= Reserved

101= Low-Power RC Oscillator (LPRC)

100= Secondary Oscillator (SOSC)

011= Primary Oscillator with PLL module (HSPLL, ECPLL)

010= Primary Oscillator (XT, HS, EC)

001= Fast RC Oscillator with postscaler and PLL module (FRCPLL)

000= Fast RC Oscillator (FRC)

bit 7-6

bit 5

FCKSM1:FCKSM0: Clock Switching and Fail-Safe Clock Monitor Configuration bits

1x= Clock switching and Fail-Safe Clock Monitor are disabled

01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled

00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled

OSCIOFCN: OSC2 Pin Configuration bit

If POSCMD1:POSCMD0 = 11 or 00:

1= OSC2/CLKO/RC15 functions as CLKO (FOSC/2)

0= OSC2/CLKO/RC15 functions as port I/O (RC15)

If POSCMD1:POSCMD0 = 10 or 01:

OSCIOFCN has no effect on OSC2/CLKO/RC15.

bit 4-2

bit 1-0

Unimplemented: Read as ‘1’

POSCMD1:POSCMD0: Primary Oscillator Configuration bits

11= Primary oscillator disabled

10= HS Oscillator mode selected

01= XT Oscillator mode selected

00= EC Oscillator mode selected

.

Legend:

R = Readable bit

PO = Program-Once bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘1’

-n = Value when unprogrammed

‘0’ = Bit is cleared x = Bit is unknown

DS39747C-page 182

Preliminary

PIC24FJ128GA FAMILY

REGISTER 23-3: DEVID: DEVICE ID REGISTER

Upper Third:

U

—

bit 23

bit 16

Middle Third:

U

—

U

R

—

FAMID7

FAMID6

FAMID5

FAMID4

FAMID3

FAMID2

bit 15

bit 8

Lower Third:

R

FAMID1

bit 7

R

FAMID0

DEV5

DEV4

DEV3

DEV2

DEV1

DEV0

bit 0

bit 23-14 Unimplemented: Read as ‘0’

bit 13-6 FAMID7:FAMID0: Device Family Identifier bits

00010000= PIC24FJ128GA family

bit 5-0

DEV5:DEV0: Individual Device Identifier bits

000101= PIC24FJ64GA006

000110= PIC24FJ96GA006

000111= PIC24FJ128GA006

001000= PIC24FJ64GA008

001001= PIC24FJ96GA008

001010= PIC24FJ128GA008

001011= PIC24FJ64GA010

001100= PIC24FJ96GA010

001101= PIC24FJ128GA010

Legend:

R = Readable bit

U = Unimplemented bit, read as ‘0’

Preliminary

DS39747C-page 183

PIC24FJ128GA FAMILY

REGISTER 23-4: DEVREV: DEVICE REVISION REGISTER

Upper Third:

U

—

bit 23

bit 16

Middle Third:

R

r

R

r

R

r

R

r

U

R

—

MAJRV2

bit 15

bit 8

Lower Third:

R

U

R

MAJRV1

bit 7

MAJRV0

—

DOT2

DOT1

DOT0

bit 0

bit 23-16 Unimplemented: Read as ‘0’

bit 15-12 Reserved: For factory use only

bit 11-9 Unimplemented: Read as ‘0’

bit 8-6

bit 5-3

bit 2-0

MAJRV2:MAJRV0: Major Revision Identifier bits

Unimplemented: Read as ‘0’

DOT2:DOT0: Minor Revision Identifier bits

Legend:

R = Readable bit

r = Reserved bit

U = Unimplemented bit, read as ‘0’

DS39747C-page 184

Preliminary

PIC24FJ128GA FAMILY

FIGURE 23-1:

CONNECTIONS FOR THE

ON-CHIP REGULATOR

23.2 On-Chip Voltage Regulator

All of the PIC24FJ128GA family devices power their

core digital logic at a nominal 2.5V. This may create an

issue for designs that are required to operate at a

higher typical voltage, such as 3.3V. To simplify system

design, all devices in the PIC24FJ128GA family incor-

porate an on-chip regulator that allows the device to

run its core logic from VDD.

Regulator Enabled (ENVREG tied to VDD):

3.3V

PIC24FJ128GA

VDD

ENVREG

The regulator is controlled by the ENVREG pin. Tying

VDD to the pin enables the regulator, which in turn, pro-

vides power to the core from the other VDD pins. When

the regulator is enabled, a low ESR capacitor (such as

tantalum) must be connected to the VDDCORE/VCAP pin

(Figure 23-1). This helps to maintain the stability of the

regulator. The recommended value for the filer capacitor

is provided in Section 26.1 “DC Characteristics”.

VDDCORE/VCAP

VSS

CEFC

(10 μF typ)

Regulator Disabled (ENVREG tied to ground):

2.5V⁽¹⁾

If ENVREG is tied to VSS, the regulator is disabled. In

this case, separate power for the core logic at a nomi-

nal 2.5V must be supplied to the device on the

VDDCORE/VCAP pin to run the I/O pins at higher voltage

levels, typically 3.3V. Alternatively, the VDDCORE/VCAP

and VDD pins can be tied together to operate at a lower

nominal voltage. Refer to Figure 23-1 for possible

configurations.

3.3V⁽¹⁾

PIC24FJ128GA

VDD

ENVREG

VDDCORE/VCAP

VSS

23.2.1

ON-CHIP REGULATOR AND POR

When the voltage regulator is enabled, it takes approxi-

mately 20 μs for it to generate output. During this time,

designated as TSTARTUP, code execution is disabled.

TSTARTUP is applied every time the device resumes

operation after any power-down, including Sleep mode.

Regulator Disabled (VDD tied to VDDCORE):

2.5V⁽¹⁾

PIC24FJ128GA

VDD

If the regulator is disabled, a separate Power-up Timer

(PWRT) is automatically enabled. The PWRT adds a

fixed delay of 64 ms nominal delay at device start-up.

ENVREG

VDDCORE/VCAP

VSS

23.2.2

When

ON-CHIP REGULATOR AND BOR

the on-chip regulator is enabled,

PIC24FJ128GA family devices also have a simple

brown-out capability. If the voltage supplied to the reg-

ulator is inadequate to maintain a regulated level, the

regulator Reset circuitry will generate a Brown-out

Reset. This event is captured by the BOR flag bit

(RCON<0>). The brown-out voltage levels are specific

in Section 26.1 “DC Characteristics”.

Note 1: These are typical operating voltages. Refer

to Section 26.1 “DC Characteristics” for

the full operating ranges of VDD and

VDDCORE.

23.2.3

POWER-UP REQUIREMENTS

The on-chip regulator is designed to meet the power-up

requirements for the device. If the application does not

use the regulator, then strict power-up conditions must

be adhered to. While powering up, VDDCORE must

never exceed VDD by 0.3 volts.

Preliminary

DS39747C-page 185

PIC24FJ128GA FAMILY

If the WDT is enabled, it will continue to run during

Sleep or Idle modes. When the WDT time-out occurs,

the device will wake the device and code execution will

continue from where the PWRSAVinstruction was exe-

cuted. The corresponding SLEEP or IDLE bits

(RCON<3:2>) will need to be cleared in software after

the device wakes up.

23.3 Watchdog Timer (WDT)

For PIC24FJ128GA family devices, the WDT is driven

by the LPRC oscillator. When the WDT is enabled, the

clock source is also enabled.

The nominal WDT clock source from LPRC is 32 kHz.

This feeds a prescaler that can be configured for either

5-bit (divide-by-32) or 7-bit (divide-by-128) operation.

The prescaler is set by the FWPSA Configuration bit.

With a 32 kHz input, the prescaler yields a nominal

WDT time-out period (TWDT) of 1 ms in 5-bit mode, or

4 ms in 7-bit mode.

The WDT Flag bit, WDTO (RCON<4>), is not auto-

matically cleared following a WDT time-out. To detect

subsequent WDT events, the flag must be cleared in

software.

Note:

The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the WDTPS3:WDTPS0

Configuration bits (Flash Configuration Word 1<3:0>),

which allow the selection of a total of 16 settings, from

1:1 to 1:32,768. Using the prescaler and postscaler,

time-out periods ranging from 1 ms to 131 seconds can

be achieved.

23.3.1

CONTROL REGISTER

The WDT is enabled or disabled by the FWDTEN

device Configuration bit. When the FWDTEN

Configuration bit is set, the WDT is always enabled.

The WDT, prescaler and postscaler are reset:

• On any device Reset

The WDT can be optionally controlled in software when

the FWDTEN Configuration bit has been programmed

to ‘0’. The WDT is enabled in software by setting the

SWDTEN control bit (RCON<5>). The SWDTEN con-

trol bit is cleared on any device Reset. The software

WDT option allows the user to enable the WDT for crit-

ical code segments and disable the WDT during

non-critical segments for maximum power savings.

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSC bits), or by hardware

(i.e., Fail-Safe Clock Monitor)

• When a PWRSAVinstruction is executed (i.e.,

Sleep or Idle mode is entered)

• When the device exits Sleep or Idle mode to

resume normal operation

• By a CLRWDTinstruction during normal execution

FIGURE 23-2:

WDT BLOCK DIAGRAM

SWDTEN

FWDTEN

LPRC Control

Wake from Sleep

FWPSA

WDTPS3:WDTPS0

Prescaler

(5-bit/7-bit)

WDT

Counter

Postscaler

WDT Overflow

1:1 to 1:32.768

LPRC Input

Reset

32 kHz

1 ms/4 ms

All Device Resets

Transition to

New Clock Source

Exit Sleep or

Idle Mode

CLRWDTInstr.

PWRSAVInstr.

Sleep or Idle Mode

DS39747C-page 186

Preliminary

PIC24FJ128GA FAMILY

23.4 JTAG Interface

23.6

In-Circuit Serial Programming

PIC24FJ128GA family devices implement a JTAG

interface, which supports boundary scan device testing

as well as in-circuit programming.

PIC24FJ128GA family microcontrollers can be serially

programmed while in the end application circuit. This is

simply done with two lines for clock (PGCx) and data

(PGDx) and three other lines for power, ground and the

programming voltage. This allows customers to manu-

facture boards with unprogrammed devices and then

program the microcontroller just before shipping the

product. This also allows the most recent firmware or a

custom firmware to be programmed.

23.5 Program Verification and

Code Protection

For all devices in the PIC24FJ128GA family of devices,

the on-chip program memory space is treated as a

single block. Code protection for this block is controlled

by one Configuration bit, GCP. This bit inhibits external

reads and writes to the program memory space. It has

no direct effect in normal execution mode.

23.7 In-Circuit Debugger

When MPLAB^®ICD 2 is selected as a debugger, the

In-Circuit Debugging functionality is enabled. This

function allows simple debugging functions when used

with MPLAB IDE. Debugging functionality is controlled

through the EMUCx (Emulation/Debug Clock) and

EMUDx (Emulation/Debug Data) pins.

23.5.1

CONFIGURATION REGISTER

PROTECTION

The Configuration registers are protected against inad-

vertent or unwanted changes or reads in two ways. The

primary protection is the write-once feature of the

Configuration bits which prevents reconfiguration once

the bit has been programmed during a power cycle. To

safeguard against unpredictable events, Configuration

bit changes resulting from individual cell level disrup-

tions (such as ESD events) will cause a parity error and

trigger a device Reset.

To use the In-Circuit Debugger function of the device,

the design must implement ICSP connections to

MCLR, VDD, VSS, PGCx, PGDx and the

EMUDx/EMUCx pin pair. In addition, when the feature

is enabled, some of the resources are not available for

general use. These resources include the first 80 bytes

of data RAM and two I/O pins.

The data for the Configuration registers is derived from

the Flash Configuration Words in program memory.

When the GCP bit is set, the source data for device

configuration is also protected as a consequence.

Preliminary

DS39747C-page 187

PIC24FJ128GA FAMILY

NOTES:

DS39747C-page 188

Preliminary

PIC24FJ128GA FAMILY

The literal instructions that involve data movement may

use some of the following operands:

24.0 INSTRUCTION SET SUMMARY

Note:

This chapter is a brief summary of the

PIC24 instruction set architecture, and is

not intended to be a comprehensive refer-

ence source. For detailed information on

programming

• A literal value to be loaded into a W register or file

register (specified by the value of ‘k’)

• The W register or file register where the literal

value is to be loaded (specified by ‘Wb’ or ‘f’)

However, literal instructions that involve arithmetic or

logical operations use some of the following operands:

The PIC24 instruction set adds many enhancements to

the previous PICmicro^®MCU instruction sets, while

maintaining an easy migration from previous PICmicro

MCU instruction sets. Most instructions are a single

program memory word. Only three instructions require

two program memory locations.

• The first source operand which is a register ‘Wb’

without any address modifier

• The second source operand which is a literal

value

• The destination of the result (only if not the same

as the first source operand) which is typically a

register ‘Wd’ with or without an address modifier

Each single-word instruction is a 24-bit word divided

into an 8-bit opcode, which specifies the instruction

type and one or more operands, which further specify

the operation of the instruction. The instruction set is

highly orthogonal and is grouped into four basic

categories:

The control instructions may use some of the following

operands:

• A program memory address

• Word or byte-oriented operations

• Bit-oriented operations

• Literal operations

• The mode of the table read and table write

instructions

All instructions are a single word, except for certain

double-word instructions, which were made double-

word instructions so that all the required information is

available in these 48 bits. In the second word, the

8 MSbs are ‘0’s. If this second word is executed as an

instruction (by itself), it will execute as a NOP.

• Control operations

Table 24-1 shows the general symbols used in

describing the instructions. The PIC24 instruction set

summary in Table 24-2 lists all the instructions, along

with the status flags affected by each instruction.

Most single-word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles, with the additional instruction cycle(s) executed

as a NOP. Notable exceptions are the BRA (uncondi-

tional/computed branch), indirect CALL/GOTO, all table

reads and writes, and RETURN/RETFIE instructions,

which are single-word instructions but take two or three

cycles.

Most word or byte-oriented W register instructions

(including barrel shift instructions) have three

operands:

• The first source operand which is typically a

register ‘Wb’ without any address modifier

• The second source operand which is typically a

register ‘Ws’ with or without an address modifier

• The destination of the result which is typically a

register ‘Wd’ with or without an address modifier

However, word or byte-oriented file register instructions

have two operands:

Certain instructions that involve skipping over the sub-

sequent instruction require either two or three cycles if

the skip is performed, depending on whether the

instruction being skipped is a single-word or two-word

instruction. Moreover, double-word moves require two

cycles. The double-word instructions execute in two

instruction cycles.

• The file register specified by the value ‘f’

• The destination, which could either be the file

register ‘f’ or the W0 register, which is denoted as

‘WREG’

Most bit-oriented instructions (including simple rotate/

shift instructions) have two operands:

• The W register (with or without an address

modifier) or file register (specified by the value of

‘Ws’ or ‘f’)

• The bit in the W register or file register

(specified by a literal value or indirectly by the

contents of register ‘Wb’)

Preliminary

DS39747C-page 189

PIC24FJ128GA FAMILY

TABLE 24-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field

Description

#text

(text)

[text]

{ }

Means literal defined by “text”

Means “content of text”

Means “the location addressed by text”

Optional field or operation

<n:m>

.b

Register bit field

Byte mode selection

.d

Double-Word mode selection

.S

Shadow register select

.w

Word mode selection (default)

bit4

4-bit bit selection field (used in word addressed instructions) ∈ {0...15}

MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero

Absolute address, label or expression (resolved by the linker)

File register address ∈ {0000h...1FFFh}

1-bit unsigned literal ∈ {0,1}

C, DC, N, OV, Z

Expr

f

lit1

lit4

4-bit unsigned literal ∈ {0...15}

lit5

5-bit unsigned literal ∈ {0...31}

lit8

8-bit unsigned literal ∈ {0...255}

lit10

lit14

lit16

lit23

None

PC

10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode

14-bit unsigned literal ∈ {0...16384}

16-bit unsigned literal ∈ {0...65535}

23-bit unsigned literal ∈ {0...8388608}; LSB must be ‘0’

Field does not require an entry, may be blank

Program Counter

Slit10

Slit16

Slit6

Wb

10-bit signed literal ∈ {-512...511}

16-bit signed literal ∈ {-32768...32767}

6-bit signed literal ∈ {-16...16}

Base W register ∈ {W0..W15}

Wd

Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }

Wdo

Destination W register ∈

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }

Wm,Wn

Wn

Dividend, Divisor working register pair (direct addressing)

One of 16 working registers ∈ {W0..W15}

Wnd

Wns

One of 16 destination working registers ∈ {W0..W15}

One of 16 source working registers ∈ {W0..W15}

W0 (working register used in file register instructions)

Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }

WREG

Ws

Wso

Source W register ∈

{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

DS39747C-page 190

Preliminary

PIC24FJ128GA FAMILY

TABLE 24-2: INSTRUCTION SET OVERVIEW

Assembly

# of

Status Flags

Affected

Assembly Syntax

Mnemonic

Description

Words Cycles

ADD

ADDC

AND

ASR

ADD

ADDC

AND

ASR

f

f = f + WREG

1

C, DC, N, OV, Z

N, Z

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f + WREG

1

Wd = lit10 + Wd

Wd = Wb + Ws

1

Wd = Wb + lit5

1

f = f + WREG + (C)

1

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f + WREG + (C)

Wd = lit10 + Wd + (C)

Wd = Wb + Ws + (C)

Wd = Wb + lit5 + (C)

f = f .AND. WREG

1

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f .AND. WREG

Wd = lit10 .AND. Wd

Wd = Wb .AND. Ws

1

N, Z

1

N, Z

1

N, Z

Wd = Wb .AND. lit5

1

N, Z

f = Arithmetic Right Shift f

WREG = Arithmetic Right Shift f

Wd = Arithmetic Right Shift Ws

Wnd = Arithmetic Right Shift Wb by Wns

Wnd = Arithmetic Right Shift Wb by lit5

Bit Clear f

1

C, N, OV, Z

N, Z

ASR

f,WREG

Ws,Wd

1

ASR

BCLR

BRA

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,#bit4

1

N, Z

BCLR

BRA

1

None

Ws,#bit4

C,Expr

Bit Clear Ws

1

None

Branch if Carry

1 (2)

2

None

GE,Expr

GEU,Expr

GT,Expr

GTU,Expr

LE,Expr

LEU,Expr

LT,Expr

LTU,Expr

N,Expr

Branch if Greater than or Equal

Branch if Unsigned Greater than or Equal

Branch if Greater than

Branch if Unsigned Greater than

Branch if Less than or Equal

Branch if Unsigned Less than or Equal

Branch if Less than

None

Branch if Unsigned Less than

Branch if Negative

None

NC,Expr

NN,Expr

NOV,Expr

NZ,Expr

OV,Expr

Expr

Branch if Not Carry

None

BRA

BSET

BSW.C

BSW.Z

BTG

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

None

Branch if Overflow

None

Branch Unconditionally

Branch if Zero

None

Z,Expr

1 (2)

2

None

Wn

Computed Branch

None

BSET

BSW

BTG

f,#bit4

Bit Set f

1

None

Ws,#bit4

Ws,Wb

Bit Set Ws

1

None

Write C bit to Ws<Wb>

Write Z bit to Ws<Wb>

Bit Toggle f

1

None

Ws,Wb

1

None

f,#bit4

1

None

Ws,#bit4

f,#bit4

Bit Toggle Ws

1

None

BTSC

Bit Test f, Skip if Clear

1

None

(2 or 3)

BTSC

Ws,#bit4

Bit Test Ws, Skip if Clear

1

None

(2 or 3)

Preliminary

DS39747C-page 191

PIC24FJ128GA FAMILY

TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

f,#bit4

Description

Bit Test f, Skip if Set

Words Cycles

BTSS

1

None

(2 or 3)

Ws,#bit4

Bit Test Ws, Skip if Set

1

None

(2 or 3)

BTST

f,#bit4

Bit Test f

1

2

1

2

1

Z

BTST.C

BTST.Z

BTST.C

BTST.Z

BTSTS

Ws,#bit4

Ws,Wb

f,#bit4

Bit Test Ws to C

C

Bit Test Ws to Z

Z

Bit Test Ws<Wb> to C

Bit Test Ws<Wb> to Z

Bit Test then Set f

C

Z

BTSTS

Z

BTSTS.C Ws,#bit4

Bit Test Ws to C, then Set

Bit Test Ws to Z, then Set

Call Subroutine

C

BTSTS.Z

CALL

CLR

Ws,#bit4

lit23

Wn

Z

CALL

CLR

None

Call Indirect Subroutine

f = 0x0000

None

f

None

CLR

WREG

Ws

WREG = 0x0000

None

CLR

Ws = 0x0000

None

CLRWDT

COM

CLRWDT

COM

CP

Clear Watchdog Timer

f = f

WDTO, Sleep

N, Z

f

f,WREG

WREG = f

N, Z

Ws,Wd

Wd = Ws

N, Z

CP

f

Compare f with WREG

Compare Wb with lit5

Compare Wb with Ws (Wb – Ws)

Compare f with 0x0000

Compare Ws with 0x0000

Compare f with 0xFFFF

Compare Ws with 0xFFFF

Compare f with WREG, with Borrow

Compare Wb with lit5, with Borrow

C, DC, N, OV, Z

CP

Wb,#lit5

CP

Wb,Ws

CP0

CP1

CPB

CP0

f

CP0

Ws

CP1

f

CP1

Ws

CPB

f

Wb,#lit5

Wb,Ws

Compare Wb with Ws, with Borrow

(Wb – Ws – C)

CPSEQ

CPSGT

CPSLT

CPSNE

CPSEQ

CPSGT

CPSLT

CPSNE

Wb,Wn

Compare Wb with Wn, Skip if =

Compare Wb with Wn, Skip if >

Compare Wb with Wn, Skip if <

Compare Wb with Wn, Skip if ≠

1

None

(2 or 3)

1

(2 or 3)

1

(2 or 3)

1

(2 or 3)

DAW

DEC

DAW

Wn

Wn = Decimal Adjust Wn

f = f –1

1

C

DEC

f

C, DC, N, OV, Z

None

DEC

f,WREG

Ws,Wd

f

WREG = f –1

1

DEC

Wd = Ws – 1

1

DEC2

DISI

f = f – 2

1

f,WREG

Ws,Wd

#lit14

WREG = f – 2

1

Wd = Ws – 2

1

DISI

DIV

Disable Interrupts for k Instruction Cycles

Signed 16/16-bit Integer Divide

Signed 32/16-bit Integer Divide

Unsigned 16/16-bit Integer Divide

Unsigned 32/16-bit Integer Divide

Swap Wns with Wnd

1

DIV.SW

DIV.SD

DIV.UW

DIV.UD

EXCH

Wm,Wn

Wns,Wnd

18

1

N, Z, C, OV

None

EXCH

DS39747C-page 192

Preliminary

PIC24FJ128GA FAMILY

TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

FF1L

FF1R

GOTO

INC

Ws,Wnd

Expr

Find First One from Left (MSb) Side

Find First One from Right (LSb) Side

Go to Address

1

2

1

2

1

2

1

2

1

C

FF1R

GOTO

None

Wn

Go to Indirect

None

INC

f

f = f + 1

C, DC, N, OV, Z

N, Z

INC

f,WREG

Ws,Wd

WREG = f + 1

INC

Wd = Ws + 1

INC2

IOR

INC2

IOR

f

f = f + 2

f,WREG

Ws,Wd

WREG = f + 2

Wd = Ws + 2

f

f = f .IOR. WREG

IOR

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

#lit14

WREG = f .IOR. WREG

Wd = lit10 .IOR. Wd

N, Z

IOR

N, Z

IOR

Wd = Wb .IOR. Ws

N, Z

IOR

Wd = Wb .IOR. lit5

N, Z

LNK

LSR

LNK

Link Frame Pointer

None

LSR

f

f = Logical Right Shift f

WREG = Logical Right Shift f

Wd = Logical Right Shift Ws

Wnd = Logical Right Shift Wb by Wns

Wnd = Logical Right Shift Wb by lit5

Move f to Wn

C, N, OV, Z

N, Z

LSR

f,WREG

Ws,Wd

LSR

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,Wn

LSR

N, Z

MOV

MOV.b

MOV

MOV.D

MUL.SS

MUL.SU

MUL.US

MUL.UU

MUL.SU

MUL.UU

MUL

None

[Wns+Slit10],Wnd

f

Move [Wns+Slit10] to Wnd

Move f to f

None

N, Z

f,WREG

#lit16,Wn

#lit8,Wn

Wn,f

Move f to WREG

N, Z

Move 16-bit Literal to Wn

Move 8-bit Literal to Wn

Move Wn to f

None

Wns,[Wns+Slit10]

Wso,Wdo

WREG,f

Wns,Wd

Ws,Wnd

Wb,Ws,Wnd

Wb,#lit5,Wnd

f

Move Wns to [Wns+Slit10]

Move Ws to Wd

None

Move WREG to f

N, Z

Move Double from W(ns):W(ns+1) to Wd

Move Double from Ws to W(nd+1):W(nd)

{Wnd+1, Wnd} = Signed(Wb) * Signed(Ws)

{Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws)

{Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws)

{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws)

{Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5)

{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5)

W3:W2 = f * WREG

None

MUL

None

NEG

f

f = f + 1

C, DC, N, OV, Z

None

NEG

f,WREG

Ws,Wd

WREG = f + 1

NEG

Wd = Ws + 1

NOP

POP

NOP

No Operation

NOPR

POP

No Operation

None

f

Pop f from Top-of-Stack (TOS)

Pop from Top-of-Stack (TOS) to Wdo

Pop from Top-of-Stack (TOS) to W(nd):W(nd+1)

Pop Shadow Registers

None

POP

Wdo

Wnd

None

POP.D

POP.S

None

All

Preliminary

DS39747C-page 193

PIC24FJ128GA FAMILY

TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

PUSH

f

Push f to Top-of-Stack (TOS)

Push Wso to Top-of-Stack (TOS)

Push W(ns):W(ns+1) to Top-of-Stack (TOS)

Push Shadow Registers

Go into Sleep or Idle mode

Relative Call

1

None

PUSH

Wso

Wns

None

PUSH.D

PUSH.S

2

None

1

None

PWRSAV

RCALL

PWRSAV #lit1

1

WDTO, Sleep

None

RCALL

REPEAT

RESET

RETFIE

RETLW

RETURN

RLC

Expr

Wn

2

Computed Call

2

None

REPEAT

#lit14

Wn

Repeat Next Instruction lit14 + 1 times

Repeat Next Instruction (Wn) + 1 times

Software Device Reset

Return from Interrupt

1

None

1

None

RESET

RETFIE

RETLW

RETURN

RLC

1

None

3 (2)

1

None

#lit10,Wn

Return with Literal in Wn

Return from Subroutine

f = Rotate Left through Carry f

WREG = Rotate Left through Carry f

Wd = Rotate Left through Carry Ws

f = Rotate Left (No Carry) f

WREG = Rotate Left (No Carry) f

Wd = Rotate Left (No Carry) Ws

f = Rotate Right through Carry f

WREG = Rotate Right through Carry f

Wd = Rotate Right through Carry Ws

f = Rotate Right (No Carry) f

WREG = Rotate Right (No Carry) f

Wd = Rotate Right (No Carry) Ws

Wnd = Sign-Extended Ws

f = FFFFh

None

f

C, N, Z

RLC

f,WREG

Ws,Wd

f

1

C, N, Z

RLC

1

C, N, Z

RLNC

RRC

RLNC

RRC

1

N, Z

f,WREG

Ws,Wd

f

1

N, Z

1

N, Z

1

C, N, Z

RRC

f,WREG

Ws,Wd

f

1

C, N, Z

RRC

1

C, N, Z

RRNC

SE

1

N, Z

f,WREG

Ws,Wd

Ws,Wnd

f

1

N, Z

1

N, Z

SE

1

C, N, Z

SETM

SL

1

None

WREG

Ws

WREG = FFFFh

1

None

Ws = FFFFh

1

None

SL

f

f = Left Shift f

1

C, N, OV, Z

N, Z

SL

f,WREG

Ws,Wd

Wb,Wns,Wnd

Wb,#lit5,Wnd

f

WREG = Left Shift f

1

SL

Wd = Left Shift Ws

1

SL

Wnd = Left Shift Wb by Wns

Wnd = Left Shift Wb by lit5

f = f – WREG

1

SL

1

N, Z

SUB

1

C, DC, N, OV, Z

SUB

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f – WREG

1

SUB

Wn = Wn – lit10

1

SUB

Wd = Wb – Ws

1

SUB

Wd = Wb – lit5

1

SUBB

SUBR

f = f – WREG – (C)

1

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f – WREG – (C)

Wn = Wn – lit10 – (C)

1

Wd = Wb – Ws – (C)

1

Wd = Wb – lit5 – (C)

1

SUBR

f = WREG – f

1

f,WREG

Wb,Ws,Wd

Wb,#lit5,Wd

WREG = WREG – f

1

Wd = Ws – Wb

1

Wd = lit5 – Wb

1

DS39747C-page 194

Preliminary

PIC24FJ128GA FAMILY

TABLE 24-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

SUBBR

SWAP.b

SWAP

TBLRDH

TBLRDL

TBLWTH

TBLWTL

ULNK

f

f = WREG – f – (C)

1

2

1

C, DC, N, OV, Z

None

f,WREG

Wb,Ws,Wd

Wb,#lit5,Wd

Wn

WREG = WREG – f – (C)

Wd = Ws – Wb – (C)

Wd = lit5 – Wb – (C)

SWAP

Wn = Nibble Swap Wn

Wn = Byte Swap Wn

Wn

None

TBLRDH

TBLRDL

TBLWTH

TBLWTL

ULNK

Ws,Wd

Read Prog<23:16> to Wd<7:0>

Read Prog<15:0> to Wd

Write Ws<7:0> to Prog<23:16>

Write Ws to Prog<15:0>

Unlink Frame Pointer

f = f .XOR. WREG

None

XOR

f

N, Z

XOR

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

Ws,Wnd

WREG = f .XOR. WREG

Wd = lit10 .XOR. Wd

N, Z

XOR

N, Z

XOR

Wd = Wb .XOR. Ws

N, Z

XOR

Wd = Wb .XOR. lit5

N, Z

ZE

Wnd = Zero-Extend Ws

C, Z, N

Preliminary

DS39747C-page 195

PIC24FJ128GA FAMILY

NOTES:

DS39747C-page 196

Preliminary

PIC24FJ128GA FAMILY

25.1 MPLAB Integrated Development

Environment Software

25.0 DEVELOPMENT SUPPORT

The PICmicro^®microcontrollers are supported with a

full range of hardware and software development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

• A single graphical interface to all debugging tools

- Simulator

- MPLAB C18 and MPLAB C30 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- Programmer (sold separately)

- Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

• Emulators

• Customizable data windows with direct edit of

contents

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB ICE 4000 In-Circuit Emulator

• In-Circuit Debugger

• High-level source code debugging

• Visual device initializer for easy register

initialization

- MPLAB ICD 2

• Mouse over variable inspection

• Device Programmers

• Drag and drop variables from source to watch

windows

- PICSTART^®Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Extensive on-line help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

• One touch assemble (or compile) and download

to PICmicro MCU emulator and simulator tools

(automatically updates all project information)

• Debug using:

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

Preliminary

DS39747C-page 197

PIC24FJ128GA FAMILY

25.2 MPASM Assembler

25.5 MPLAB ASM30 Assembler, Linker

and Librarian

The MPASM Assembler is a full-featured, universal

macro assembler for all PICmicro MCUs.

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• User-defined macros to streamline

assembly code

• Rich directive set

• Conditional assembly for multi-purpose

source files

• Flexible macro language

• MPLAB IDE compatibility

• Directives that allow complete control over the

assembly process

25.6 MPLAB SIM Software Simulator

25.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PICmicro MCUs and dsPIC^®DSCs on an

instruction level. On any given instruction, the data

areas can be examined or modified and stimuli can be

applied from a comprehensive stimulus controller.

Registers can be logged to files for further run-time

analysis. The trace buffer and logic analyzer display

extend the power of the simulator to record and track

program execution, actions on I/O, most peripherals

and internal registers.

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI

C

compilers for

Microchip’s PIC18 family of microcontrollers and the

dsPIC30, dsPIC33 and PIC24 family of digital signal

controllers. These compilers provide powerful integra-

tion capabilities, superior code optimization and ease

of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

25.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

DS39747C-page 198

Preliminary

PIC24FJ128GA FAMILY

25.7 MPLAB ICE 2000

High-Performance

25.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PICmicro

MCUs and can be used to develop for these and other

PICmicro MCUs and dsPIC DSCs. The MPLAB ICD 2

utilizes the in-circuit debugging capability built into

the Flash devices. This feature, along with Microchip’s

In-Circuit Serial Programming^TM(ICSP^TM) protocol,

offers cost-effective, in-circuit Flash debugging from the

graphical user interface of the MPLAB Integrated

Development Environment. This enables a designer to

develop and debug source code by setting breakpoints,

single stepping and watching variables, and CPU

status and peripheral registers. Running at full speed

enables testing hardware and applications in real

time. MPLAB ICD 2 also serves as a development

programmer for selected PICmicro devices.

In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PICmicro

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing features. Interchangeable processor modules allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PICmicro microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft^®Windows^®32-bit operating system were

chosen to best make these features available in a

simple, unified application.

25.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PICmicro devices without a PC connection. It can also

set code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an SD/MMC card for

file storage and secure data applications.

25.8 MPLAB ICE 4000

High-Performance

In-Circuit Emulator

The MPLAB ICE 4000 In-Circuit Emulator is intended to

provide the product development engineer with a

complete microcontroller design tool set for high-end

PICmicro MCUs and dsPIC DSCs. Software control of

the MPLAB ICE 4000 In-Circuit Emulator is provided by

the MPLAB Integrated Development Environment,

which allows editing, building, downloading and source

debugging from a single environment.

The MPLAB ICE 4000 is a premium emulator system,

providing the features of MPLAB ICE 2000, but with

increased emulation memory and high-speed perfor-

mance for dsPIC30F and PIC18XXXX devices. Its

advanced emulator features include complex triggering

and timing, and up to 2 Mb of emulation memory.

The MPLAB ICE 4000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

Preliminary

DS39747C-page 199

PIC24FJ128GA FAMILY

25.11 PICSTART Plus Development

Programmer

25.13 Demonstration, Development and

Evaluation Boards

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PICmicro devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

A wide variety of demonstration, development and

evaluation boards for various PICmicro MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

25.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer with an easy-to-use interface for pro-

gramming many of Microchip’s baseline, mid-range

and PIC18F families of Flash memory microcontrollers.

The PICkit 2 Starter Kit includes a prototyping develop-

ment board, twelve sequential lessons, software and

HI-TECH’s PICC Lite C compiler, and is designed to

help get up to speed quickly using PIC^®micro-

controllers. The kit provides everything needed to

program, evaluate and develop applications using

Microchip’s powerful, mid-range Flash memory family

of microcontrollers.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart^®battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

DS39747C-page 200

Preliminary

PIC24FJ128GA FAMILY

26.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of the PIC24FJ128GA family electrical characteristics. Additional information will be

provided in future revisions of this document as it becomes available.

Absolute maximum ratings for the PIC24FJ128GA family are listed below. Exposure to these maximum rating conditions

for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions

above the parameters indicated in the operation listings of this specification, is not implied.

Absolute Maximum Ratings^(†)

Ambient temperature under bias...............................................................................................................-40°C to +85°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V

Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)

Voltage on any digital-only pin with respect to VSS .................................................................................. -0.3V to +6.0V

Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +2.8V

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin (Note 1)................................................................................................................250 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by all ports .......................................................................................................................200 mA

Maximum current sourced by all ports (Note 1)....................................................................................................200 mA

Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 26-2).

†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Preliminary

DS39747C-page 201

PIC24FJ128GA FAMILY

26.1 DC Characteristics

TABLE 26-1: OPERATING MIPS VS. VOLTAGE

Max MIPS

PIC24FJ128GA

16

VDD Range

(in Volts)

Temp Range

(in °C)

2.0-3.6V

-40°C to +85°C

TABLE 26-2: THERMAL OPERATING CONDITIONS

Rating

Symbol

Min

Typ

Max

Unit

PIC24FJ128GA:

Operating Junction Temperature Range

Operating Ambient Temperature Range

TJ

TA

-40

—

+125

+85

°C

Power Dissipation:

Internal Chip Power Dissipation:

PINT = VDD x (IDD – Σ IOH)

PD

PINT + PI/O

W

I/O Pin Power Dissipation:

PI/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL)

Maximum Allowed Power Dissipation

PDMAX

(TJ – TA)/θJA

TABLE 26-3: THERMAL PACKAGING CHARACTERISTICS

Characteristic

Symbol

Typ

Max

Unit

Notes

Package Thermal Resistance, 14x14x1 mm TQFP

Package Thermal Resistance, 12x12x1 mm TQFP

Package Thermal Resistance, 10x10x1 mm TQFP

θJA

50

—

°C/W (Note 1)

69.4

76.6

Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.

TABLE 26-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for Industrial

Param

No.

Symbol

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

Operating Voltage

DC10 Supply Voltage

VDD

2.7

VDDCORE

2.0

—

3.6

2.75

—

V

Regulator enabled

Regulator disabled

VDD

VDDCORE

DC12 VDR

RAM Data Retention

Voltage⁽²⁾

1.5

DC16 VPOR

VDD Start Voltage

to ensure internal

Power-on Reset signal

—

VSS

—

V

DC17 SVDD

VDD Rise Rate

to ensure internal

Power-on Reset signal

0.05

V/ms 0-3.3V in 0.1s

0-2.5V in 60 ms

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: This is the limit to which VDD can be lowered without losing RAM data.

DS39747C-page 202

Preliminary

PIC24FJ128GA FAMILY

TABLE 26-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

Parameter

Typical⁽¹⁾

No.

Max

Units

Conditions

Operating Current (IDD)⁽²⁾

DC20

1.6

6.0

20

4.0

12

mA

μA

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

DC20a

DC20b

DC20d

DC20e

DC20f

DC23

2.5V⁽³⁾

3.6V⁽⁴⁾

2.5V⁽³⁾

3.6V⁽⁴⁾

2.5V⁽³⁾

3.6V⁽⁴⁾

2.5V⁽³⁾

3.6V⁽⁴⁾

1 MIPS

DC23a

DC23b

DC23d

DC23e

DC23f

DC24

12

4 MIPS

12

32

DC24a

DC24b

DC24d

DC24e

DC24f

DC31

20

32

20

32

16 MIPS

20

32

20

32

20

32

70

150

200

400

150

200

400

DC31a

DC31b

DC31d

DC31e

DC31f

100

200

70

μA

LPRC (31 kHz)

μA

100

200

μA

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1

driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD.

MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are

operational. No peripheral modules are operating.

3: On-chip voltage regulator disabled (ENVREG tied to VSS).

4: On-chip voltage regulator enabled (ENVREG tied to VDD).

Preliminary

DS39747C-page 203

PIC24FJ128GA FAMILY

TABLE 26-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

Parameter

Typical⁽¹⁾

No.

Max

Units

Conditions

Idle Current (IIDLE): Core Off, Clock On Base Current⁽²⁾

DC40

0.7

2.1

6.8

150

2

mA

μA

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

DC40a

DC40b

DC40d

DC40e

DC40f

DC43

2.5V⁽³⁾

3.6V⁽⁴⁾

2.5V⁽³⁾

3.6V⁽⁴⁾

2.5V⁽³⁾

3.6V⁽⁴⁾

2.5V⁽³⁾

3.6V⁽⁴⁾

2

1 MIPS

2

4

DC43a

DC43b

DC43d

DC43e

DC43f

DC47

4

4 MIPS

4

8

DC47a

DC47b

DC47c

DC47d

DC47e

DC51

8

16 MIPS

8

500

DC51a

DC51b

DC51d

DC51e

DC51f

μA

LPRC (31 kHz)

μA

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: Base IIDLE current is measured with core off, clock on and all modules turned off.

3: On-chip voltage regulator disabled (ENVREG tied to VSS).

4: On-chip voltage regulator enabled (ENVREG tied to VDD).

DS39747C-page 204

Preliminary

PIC24FJ128GA FAMILY

TABLE 26-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

Parameter

Typical⁽¹⁾

No.

Max

Units

Conditions

Power-Down Current (IPD)⁽²⁾

DC60

3

25

45

μA

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

DC60a

DC60b

DC60f

DC60g

DC60h

2.0V⁽³⁾

3.6V⁽⁴⁾

100

20

27

120

600

40

Base Power-Down Current⁽⁵⁾

60

600

Module Differential Current

DC61

10

8

25

15

μA

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

-40°C

+25°C

+85°C

DC61a

DC61b

DC61f

DC61g

DC61h

DC62

2.0V⁽³⁾

3.6V⁽⁴⁾

2.0V⁽³⁾

3.6V⁽⁴⁾

(5)

Watchdog Timer Current: ΔIWDT

DC62a

DC62b

DC62f

DC62g

DC62h

8

RTCC + Timer1 w/32 kHz Crystal:

(5)

ΔIRTCC

8

Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and

pulled high. WDT, etc., are all switched off.

3: On-chip voltage regulator disabled (ENVREG tied to VSS).

4: On-chip voltage regulator enabled (ENVREG tied to VDD).

5: The Δ current is the additional current consumed when the module is enabled. This current should be

added to the base IPD current.

Preliminary

DS39747C-page 205

PIC24FJ128GA FAMILY

TABLE 26-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

VIL

Input Low Voltage

I/O pins

DI10

VSS

—

0.2 VDD

0.15 VDD

0.2 VDD

0.3 VDD

0.8

V

DI11

DI15

DI16

DI17

DI18

DI19

PMP pins

PMPTTL = 1

MCLR

OSC1 (XT mode)

OSC1 (HS mode)

SDAx, SCLx

Input High Voltage

SMBus disabled

SMBus enabled

VIH

DI20

I/O pins:

With Analog Functions

Digital-Only

0.8 VDD

—

VDD

5.5

V

DI21

DI25

DI26

DI27

DI28

DI29

PMP pins

0.25 VDD + 0.8

0.8 VDD

0.7 VDD

2.1

—

VDD

V

PMPTTL = 1

MCLR

OSC1 (XT mode)

OSC1 (HS mode)

SDAx, SCLx

SMBus disabled

SMBus enabled,

2.5V ≤ VPIN ≤ VDD

DI30

ICNPU CNxx Pull-up Current

50

250

400

μA

VDD = 3.3V, VPIN = VSS

IIL

Input Leakage Current^(2,3)

DI50

DI51

I/O Ports

—

+1

μA

VSS ≤ VPIN ≤ VDD,

Pin at high-impedance

Analog Input pins

VSS ≤ VPIN ≤ VDD,

Pin at high-impedance

DI55

DI56

MCLR

OSC1

—

+1

μA

VSS ≤ VPIN ≤ VDD

VSS ≤ VPIN ≤ VDD,

XT and HS modes

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

DS39747C-page 206

Preliminary

PIC24FJ128GA FAMILY

TABLE 26-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾Max

Units

Conditions

VOL

Output Low Voltage

DO10

DO16

I/O Ports

—

0.4

V

IOL = 8.5 mA, VDD = 3.6V

IOL = 6.0 mA, VDD = 2.0V

IOL = 8.5 mA, VDD = 3.6V

IOL = 6.0 mA, VDD = 2.0V

OSC2/CLKO

VOH

Output High Voltage

DO20

DO26

I/O Ports

2.4

1.4

2.4

1.4

—

V

IOH = -6.0 mA, VDD = 3.6V

IOH = -3.0 mA, VDD = 2.0V

IOH = -6.0 mA, VDD = 3.6V

IOH = -3.0 mA, VDD = 2.0V

OSC2/CLKO

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

TABLE 26-10: DC CHARACTERISTICS: PROGRAM MEMORY

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

Program Flash Memory

Cell Endurance

D130

D131

EP

VPR

100

1K

—

E/W -40°C to +85°C

VDD for Read

VMIN

3.6

V

VMIN = Minimum operating

voltage

D132B VPEW VDD for Self-Timed Write

VMIN

—

3

3.6

—

V

VMIN = Minimum operating

voltage

D133A TIW

Self-Timed Write Cycle

Time

ms

D134

D135

TRETD Characteristic Retention

20

—

10

Year Provided no other specifications are

violated

IDDP

Supply Current during

Programming

—

mA

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

TABLE 26-11: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)

Param

No.

Symbol

Characteristics

Min

Typ

Max

Units

Comments

VRGOUT Regulator Output Voltage

—

2.5

10

—

V

CEFC

External Filter Capacitor

Value

4.7

μF

Capacitor must be low

series resistance

TVREG

TPWRT

—

10

64

—

μs

ENVREG = 1

ENVREG = 0

ms

Preliminary

DS39747C-page 207

PIC24FJ128GA FAMILY

26.2 AC Characteristics and Timing Parameters

The information contained in this section defines the PIC24FJ128GA family AC characteristics and timing parameters.

TABLE 26-12: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Operating voltage VDD range as described in Section 26.1 “DC Characteristics”.

FIGURE 26-1:

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 – for all pins except OSC2

VDD/2

Load Condition 2 – for OSC2

CL

RL

VSS

CL

RL = 464Ω

CL = 50 pF for all pins except OSC2

15 pF for OSC2 output

VSS

TABLE 26-13: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

Param

Symbol

Characteristic

Min

Typ⁽¹⁾Max Units

Conditions

No.

DO50 COSC2

OSC2/CLKO pin

—

15

pF In XT and HS modes when

external clock is used to drive

OSC1.

DO56 CIO

DO58 CB

All I/O pins and OSC2

SCLx, SDAx

—

50

pF EC mode

pF In I²C™ mode

400

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

DS39747C-page 208

Preliminary

PIC24FJ128GA FAMILY

FIGURE 26-2:

EXTERNAL CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

OSC1

CLKO

OS20

OS25

OS30 OS30

OS31 OS31

OS40

OS41

TABLE 26-14: EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

OS10 FOSC External CLKI Frequency

(External clocks allowed

DC

3

—

32

8

MHz EC

MHz ECPLL

only in EC mode)

Oscillator Frequency

3

10

31

—

10

8

32

33

MHz XT

MHz XTPLL

MHz HS

kHz

SOSC

OS20 TOSC TOSC = 1/FOSC

—

See parameter OS10

for FOSC value

OS25 TCY

Instruction Cycle Time⁽²⁾

33

—

DC

—

ns

OS30 TosL, External Clock in (OSC1)

TosH High or Low Time

0.45 x TOSC

EC

OS31 TosR, External Clock in (OSC1)

TosF Rise or Fall Time

—

20

ns

OS40 TckR CLKO Rise Time⁽³⁾

OS41 TckF CLKO Fall Time⁽³⁾

—

6

10

ns

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with

the device executing code. Exceeding these specified limits may result in an unstable oscillator operation

and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an

external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “Max.” cycle time

limit is “DC” (no clock) for all devices.

3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. CLKO is low for the

Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).

Preliminary

DS39747C-page 209

PIC24FJ128GA FAMILY

TABLE 26-15: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V)

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

Param

No.

Sym

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

OS50 FPLLI PLL Input Frequency

Range⁽²⁾

2

—

8

32

2

MHz ECPLL, HSPLL, XTPLL

modes

OS51 FSYS On-Chip VCO System

Frequency

8

—

1

MHz

ms

%

OS52 TLOC PLL Start-up Time

(Lock Time)

—

OS53 DCLK CLKO Stability (Jitter)

-2

+2

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

TABLE 26-16: AC CHARACTERISTICS: INTERNAL RC ACCURACY

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

AC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for Industrial

Param

No.

Characteristic

Min

Typ

Max

Units

Conditions

Internal FRC Accuracy @ 8 MHz⁽¹⁾

F20

FRC

-2

-5

—

+2

+5

%

+25°C

VDD = 3.0-3.6V

-40°C ≤ TA ≤ +85°C

Legend: TBD = To Be Determined

Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift.

TABLE 26-17: INTERNAL RC ACCURACY

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

Param

No.

Characteristic

Min

Typ

Max

Units

Conditions

LPRC @ 31 kHz⁽¹⁾

F21

-15

—

+15

%

-40°C ≤ TA ≤ +85°C

VDD = 3.0-3.6V

Note 1: Change of LPRC frequency as VDD changes.

DS39747C-page 210

Preliminary

PIC24FJ128GA FAMILY

FIGURE 26-3:

CLKO AND I/O TIMING CHARACTERISTICS

I/O Pin

(Input)

DI35

DI40

I/O Pin

(Output)

New Value

Old Value

DO31

DO32

Note: Refer to Figure 26-1 for load conditions.

TABLE 26-18: CLKO AND I/O TIMING REQUIREMENTS

Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

DO31 TIOR Port Output Rise Time

DO32 TIOF Port Output Fall Time

—

20

10

—

25

—

ns

DI35

TINP

INTx pin High or Low

Time (output)

DI40

TRBP CNx High or Low Time

(input)

2

—

TCY

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

Preliminary

DS39747C-page 211

PIC24FJ128GA FAMILY

NOTES:

DS39747C-page 212

Preliminary

PIC24FJ128GA FAMILY

27.0 PACKAGING INFORMATION

27.1 Package Marking Information

64-Lead TQFP (10x10x1 mm)

Example

XXXXXXXXXX

YYWWNNN

PIC24FJ128

GA006-I/

PT

e

3

0510017

80-Lead TQFP (12x12x1 mm)

Example

XXXXXXXXXXXX

YYWWNNN

PIC24FJ128GA

008-I/PT

0510017

e

3

100-Lead TQFP (12x12x1 mm)

Example

XXXXXXXXXXXX

YYWWNNN

PIC24FJ128GA

010-I/PT

0510017

e

3

100-Lead TQFP (14x14x1 mm)

Example

XXXXXXXXXXXX

YYWWNNN

PIC24FJ128GA

010-I/PF

0510017

e

3

Legend: XX...X Customer-specific information

Y

YY

e

WW

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

3

NNN

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Preliminary

DS39747C-page 213

PIC24FJ128GA FAMILY

27.2 Package Details

The following sections give the technical details of the packages.

64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

E

E1

#leads=n1

p

D1

D

2

1

B

n

CH x 45°

α

A

c

L

A2

φ

A1

β

(F)

Units

Dimension Limits

INCHES

NOM

64

MILLIMETERS*

NOM

64

MIN

MAX

MIN

MAX

n

p

Number of Pins

Pitch

.020

0.50

16

Pins per Side

n1

A

16

.043

.039

.006

.024

.039

3.5

Overall Height

.039

.047

1.00

1.10

1.00

0.15

0.60

1.00

3.5

1.20

Molded Package Thickness

Standoff

A2

A1

L

.037

.002

.018

.041

.010

.030

0.95

0.05

0.45

1.05

0.25

0.75

Foot Length

(F)

φ

E

D

Footprint (Reference)

Foot Angle

0

.463

.390

.005

.007

.025

5

7

.482

.398

.009

.011

.045

15

0

11.75

9.90

0.13

0.17

0.64

5

7

12.25

10.10

0.23

0.27

1.14

15

Overall Width

.472

.394

.007

.009

.035

10

12.00

10.00

0.18

0.22

0.89

10

Overall Length

Molded Package Width

Molded Package Length

Lead Thickness

Lead Width

E1

D1

c

B

CH

α

Pin 1 Corner Chamfer

Mold Draft Angle Top

Mold Draft Angle Bottom

*Controlling Parameter

Notes:

β

5

10

15

5

10

15

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions

shall not exceed .010" (0.254mm) per side.

JEDEC Equivalent: MS-026

Drawing No. C04-085

DS39747C-page 214

Preliminary

PIC24FJ128GA FAMILY

80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

E

E1

#leads=n1

p

D1

D

2

1

B

n

CH x 45°

A

α

c

A2

φ

β

L

A1

(F)

Units

Dimension Limits

INCHES

NOM

80

MILLIMETERS*

NOM

80

MIN

MAX

MIN

MAX

n

p

Number of Pins

Pitch

.020

0.50

20

Pins per Side

n1

A

20

.043

.039

.004

.024

.039

3.5

Overall Height

.039

.037

.002

.018

.047

1.00

1.10

1.00

0.10

0.60

1.00

3.5

1.20

Molded Package Thickness

Standoff

A2

A1

L

.041

.006

.030

0.95

0.05

0.45

1.05

0.15

0.75

Foot Length

(F)

Footprint (Reference)

Foot Angle

φ

E

0

.541

.463

.004

.007

.025

5

7

.561

.482

.008

.011

.045

15

0

13.75

11.75

0.09

0.17

0.64

5

7

14.25

12.25

0.20

0.27

1.14

15

Overall Width

.551

.472

.006

.009

.035

10

14.00

12.00

0.15

0.22

0.89

10

Overall Length

D

Molded Package Width

Molded Package Length

Lead Thickness

Lead Width

E1

D1

c

B

CH

α

Pin 1 Corner Chamfer

Mold Draft Angle Top

Mold Draft Angle Bottom

*Controlling Parameter

Notes:

β

5

10

15

5

10

15

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions

shall not exceed .010" (0.254mm) per side.

JEDEC Equivalent: MS-026

Drawing No. C04-092

Preliminary

DS39747C-page 215

PIC24FJ128GA FAMILY

100-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

E

E1

#leads = n1

p

D1

D

2

1

B

c

n

CH x 45

α

A

A1

φ

β

A2

L

F

Units

Dimension Limits

INCHES

NOM

MILLIMETERS

NOM

100

0.40 BSC

25

*

MIN

MAX

MIN

MAX

n

p

Number of Pins

Pitch

100

.016 BSC

25

Pins per Side

n1

A

Overall Height

.039

.043

.047

1.00

1.10

1.00

0.10

0.60

1.20

Molded Package Thickness

Standoff

A2

A1

L

.037

.002

.018

.039

.041

.006

.030

0.95

0.05

0.45

1.05

0.15

0.75

.004

Foot Length

.024

Footprint (Reference)

Foot Angle

F

φ

.039 REF.

3.5°

1.00 REF.

3.5°

14.00 BSC

0°

7°

0°

7°

Overall Width

E

D

.551 BSC

.472 BSC

.006

Overall Length

14.00 BSC

12.00 BSC

Molded Package Width

Molded Package Length

Lead Thickness

Lead Width

E1

D1

c

.004

.005

.008

.009

15°

0.09

0.13

0.15

0.20

0.23

15°

B

α

β

.007

0.18

10°

Mold Draft Angle Top

Mold Draft Angle Bottom

5°

10°

5°

10°

15°

*

Controlling Parameter

Notes:

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.10" (0.254 mm) per side.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

See ASME Y14.5M

REF: Reference Dimension, usually without tolerance, for information purposes only.

See ASME Y14.5M

JEDEC Equivalent: MS-026

Revised 07-22-05

Drawing No. C04-100

DS39747C-page 216

Preliminary

PIC24FJ128GA FAMILY

100-Lead Plastic Thin Quad Flatpack (PF) 14x14x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

E

E1

#leads=n1

p

D

D1

B

2

1

n

A

α

c

A2

φ

β

L

A1

(F)

Units

Dimension Limits

INCHES

NOM

MILLIMETERS*

MIN

MAX

MIN

NOM

100

0.50

25

MAX

n

p

Number of Pins

Pitch

100

.020

Pins per Side

n1

A

25

Overall Height

Molded Package Thickness

.047

.041

.006

.030

1.20

A2

A1

L

.037

.039

0.95

0.05

0.45

1.00

1.05

0.15

0.75

Standoff

§

.002

.018

Foot Length

.024

.039

0.60

1.00

(F)

φ

Footprint (Reference)

Foot Angle

0

3.5

7

0

3.5

7

Overall Width

E

D

.630 BSC

.551 BSC

16.00 BSC

14.00 BSC

Overall Length

Molded Package Width

Molded Package Length

Lead Thickness

E1

D1

c

.004

.007

11

.008

.011

13

0.09

0.17

11

0.20

0.27

13

Lead Width

B

.009

12

0.22

12

α

Mold Draft Angle Top

Mold Draft Angle Bottom

β

11

12

13

11

12

13

*Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-026

Drawing No. C04-110

Preliminary

DS39747C-page 217

PIC24FJ128GA FAMILY

NOTES:

DS39747C-page 218

Preliminary

PIC24FJ128GA FAMILY

APPENDIX A: REVISION HISTORY

Revision A (September 2005)

Original data sheet for PIC24FJ128GA family devices.

Revision B (March 2006)

Update of electrical specifications.

Revision C (June 2006)

Update of electrical specifications.

Preliminary

DS39747C-page 219

PIC24FJ128GA FAMILY

NOTES:

DS39747C-page 220

Preliminary

PIC24FJ128GA FAMILY

INDEX

A

C

A/D Converter ................................................................... 165

AC

C Compilers

MPLAB C18.............................................................. 198

MPLAB C30.............................................................. 198

Clock Switching

and Clock Frequency.................................................. 97

Enabling...................................................................... 95

Operation.................................................................... 95

Oscillator Sequence ................................................... 96

Code Examples

Characteristics .......................................................... 208

Internal RC Accuracy........................................ 210

Load Conditions........................................................ 208

Temperature and Voltage Specifications.................. 208

Alternate Interrupt Vector Table (AIVT) .............................. 57

Arithmetic Logic Unit (ALU)................................................. 23

Assembler

MPASM Assembler................................................... 198

Basic Code Sequence for

Clock Switching .................................................. 96

Erasing a Program Memory Block.............................. 48

Initiating a Programming Sequence ........................... 49

Loading Write Buffers................................................. 49

Port Write/Read........................................................ 100

PWRSAV Instruction Syntax ...................................... 97

Comparator Module.......................................................... 173

Comparator Voltage Reference........................................ 177

Configuring ............................................................... 177

Configuration Bits ............................................................. 179

Configuration Register Protection..................................... 187

Configuring Analog Port Pins............................................ 100

Core Features....................................................................... 7

16-bit Architecture ........................................................ 7

Easy Migration.............................................................. 8

Oscillator Options, Features......................................... 7

Power-Saving Technology............................................ 7

CPU.................................................................................... 19

Control Registers........................................................ 22

Programmer’s Model .................................................. 21

CRC

B

Baud Rate Error Calculation (BRGH = 0) ......................... 132

Block Diagrams

10-bit High-Speed A/D Converter ............................. 166

16-bit Timer1 Module................................................ 101

8-bit Multiplexed Address and

Data Application................................................ 148

Accessing Program Memory with

Table Instructions ............................................... 42

Addressable Parallel Slave Port ............................... 146

Comparator I/O Operating Modes............................. 173

Comparator Voltage Reference ................................ 177

Connections for On-Chip Voltage Regulator............. 185

Device Clock............................................................... 91

I²C............................................................................. 124

Input Capture ............................................................ 109

LCD Control .............................................................. 148

Legacy Parallel Slave Port........................................ 146

Master Mode, Demultiplexed Addressing ................. 146

Master Mode, Fully Multiplexed Addressing ............. 147

Master Mode, Partially Multiplexed Addressing........ 147

Multiplexed Addressing Application .......................... 147

Output Compare Module........................................... 113

Parallel EEPROM (Up to 15-bit Address,

Example Setup ......................................................... 162

Operation in Power Save Modes.............................. 163

Overview................................................................... 162

Registers .................................................................. 161

User Interface........................................................... 163

Customer Change Notification Service............................. 225

Customer Notification Service .......................................... 225

Customer Support............................................................. 225

16-bit Data)....................................................... 148

Parallel EEPROM (Up to 15-bit Address,

8-bit Data)......................................................... 148

Partially Multiplexed Addressing Application ............ 147

PIC24 CPU Core......................................................... 20

PIC24FJ128GA Family (General)............................... 10

PMP Module ............................................................. 139

Program Space Visibility Operation ............................ 43

Reset System.............................................................. 51

RTCC........................................................................ 149

Shared Port Structure ................................................. 99

SPI ............................................................................ 116

SPI Master, Frame Master Connection..................... 121

SPI Master, Frame Slave Connection....................... 121

SPI Master/Slave Connection

D

Data Memory

Address Space ........................................................... 27

Width .................................................................. 27

Memory Map for PIC24F128GA

Family Devices ................................................... 27

Near Data Space........................................................ 28

Organization and Alignment ....................................... 28

SFR Space ................................................................. 28

Software Stack ........................................................... 40

DC Characteristics............................................................ 202

I/O Pin Input Specifications ...................................... 206

I/O Pin Output Specifications.................................... 207

Idle Current (IIDLE).................................................... 204

Operating Current (IDD) ............................................ 203

Power-Down Current (IPD)........................................ 205

Program Memory...................................................... 207

Temperature and Voltage Specifications.................. 202

Development Support....................................................... 197

(Enhanced Buffer Modes)................................. 120

SPI Master/Slave Connection

(Standard Mode)............................................... 120

SPI Slave, Frame Master Connection....................... 121

SPI Slave, Frame Slave Connection......................... 121

Timer2 and Timer4 (16-bit Synchronous) ................. 105

Timer2/3 and Timer4/5 (32-bit) ................................. 104

Timer3 and Timer5 (16-bit Asynchronous) ............... 105

UART ........................................................................ 131

Watchdog Timer (WDT)............................................ 186

Brown-out Reset (BOR)

and On-Chip Voltage Regulator................................ 185

Preliminary

DS39747C-page 221

PIC24FJ128GA FAMILY

E

M

Electrical Characteristics...................................................201

Absolute Maximum Ratings ......................................201

ENVREG pin .....................................................................185

Equations

Memory Organization ......................................................... 25

Microchip Internet Web Site.............................................. 225

MPLAB ASM30 Assembler, Linker, Librarian................... 198

MPLAB ICD 2 In-Circuit Debugger ................................... 199

MPLAB ICE 2000 High-Performance

Universal In-Circuit Emulator.................................... 199

MPLAB ICE 4000 High-Performance

Universal In-Circuit Emulator.................................... 199

MPLAB Integrated Development

A/D Conversion Clock Period ...................................171

Calculating the PWM Period.....................................112

Calculation for Maximum PWM Resolution...............112

Relationship Between Device and

SPI Clock Speed...............................................122

UART Baud Rate with BRGH = 0 .............................132

UART Baud Rate with BRGH = 1 .............................132

Errata ....................................................................................6

Environment Software .............................................. 197

MPLAB PM3 Device Programmer .................................... 199

MPLINK Object Linker/MPLIB Object Librarian................ 198

F

O

Flash Configuration Words..........................................26, 179

Flash Program Memory.......................................................45

Control Registers ........................................................46

Operations ..................................................................46

Programming Algorithm ..............................................48

RTSP Operation..........................................................46

Table Instructions........................................................45

FSCM

Open-Drain Configuration................................................. 100

Oscillator Configuration ...................................................... 91

Clock Switching Mode Configuration Bits................... 92

Control Registers........................................................ 92

CLKDIV............................................................... 92

OSCCON............................................................ 92

OSCTUN ............................................................ 92

Output Compare ............................................................... 111

Registers .................................................................. 114

and Device Resets......................................................54

Delay for Crystal and PLL Clock Sources...................55

P

I

Packaging......................................................................... 213

Details....................................................................... 214

Marking..................................................................... 213

Pad Configuration Map....................................................... 37

Parallel Master Port (PMP)............................................... 139

PICSTART Plus Development Programmer..................... 200

Pinout Descriptions

I/O Ports..............................................................................99

Parallel I/O (PIO).........................................................99

Write/Read Timing ....................................................100

I²C

Clock Rates...............................................................125

Communicating as Master in a

Single Master Environment...............................123

Setting Baud Rate When Operating

PIC24FJ128GA Family............................................... 11

POR and Long Oscillator Start-up Times ........................... 54

Power-on Reset (POR)

and On-Chip Voltage Regulator................................ 185

Power-Saving Features ...................................................... 97

Power-Saving Modes

Doze ........................................................................... 98

Instruction-Based........................................................ 97

Idle...................................................................... 98

Sleep .................................................................. 97

Program Address Space..................................................... 25

Memory Map for PIC24FJ128GA

as Bus Master...................................................125

Slave Address Masking ............................................125

Implemented Interrupt Vectors (table).................................59

In-Circuit Debugger...........................................................187

In-Circuit Serial Programming (ICSP) ...............................187

Input Capture ....................................................................109

Registers...................................................................110

Input Change Notification..................................................100

Instruction Set

Overview...................................................................191

Summary...................................................................189

Inter-Integrated Circuit (I2C) .............................................123

Internal RC Oscillator

Use with WDT...........................................................186

Internet Address................................................................225

Interrupt Control and Status Registers................................60

IECx ............................................................................60

IFSx.............................................................................60

INTCON1, INTCON2 ..................................................60

IPCx ............................................................................60

Interrupt Controller ..............................................................57

Interrupt Setup Procedures.................................................89

Initialization .................................................................89

Interrupt Disable..........................................................89

Interrupt Service Routine (ISR)...................................89

Trap Service Routine (TSR)........................................89

Interrupt Vector Table (IVT) ................................................57

Interrupts Coincident with

Family Devices ................................................... 25

Program and Data Memory Spaces

Interfacing................................................................... 40

Program Memory

Data Access Using Table Instructions........................ 42

Hard Memory Vectors................................................. 26

Interrupt Vector........................................................... 26

Organization ............................................................... 26

Reading Data Using Program Space Visibility............ 43

Reset Vector............................................................... 26

Table Instructions

TBLRDH ............................................................. 42

TBLRDL.............................................................. 42

Program Space

Address Construction ................................................. 41

Addressing.................................................................. 40

Data Access from, Address Generation ..................... 41

Program Verification and Code Protection ....................... 187

Programmer’s Model .......................................................... 19

Power Save Instructions .............................................98

DS39747C-page 222

Preliminary

PIC24FJ128GA FAMILY

Pulse-Width Modulation Mode.......................................... 112

Duty Cycle................................................................. 112

Period........................................................................ 112

IEC0 (Interrupt Enable Control 0)............................... 69

IEC1 (Interrupt Enable Control 1)............................... 70

IEC2 (Interrupt Enable Control 2)............................... 71

IEC3 (Interrupt Enable Control 3)............................... 72

IEC4 (Interrupt Enable Control 4)............................... 73

IFS0 (Interrupt Flag Status 0)..................................... 64

IFS1 (Interrupt Flag Status 1)..................................... 65

IFS2 (Interrupt Flag Status 2)..................................... 66

IFS3 (Interrupt Flag Status 3)..................................... 67

IFS4 (Interrupt Flag Status 4)..................................... 68

INTCON1 (Interrupt Control 1) ................................... 62

INTCON2 (Interrupt Control 2) ................................... 63

IPC0 (Interrupt Priority Control 0)............................... 74

IPC1 (Interrupt Priority Control 1)............................... 75

IPC10 (Interrupt Priority Control 10)........................... 84

IPC11 (Interrupt Priority Control 11)........................... 84

IPC12 (Interrupt Priority Control 12)........................... 85

IPC13 (Interrupt Priority Control 13)........................... 86

IPC15 (Interrupt Priority Control 15)........................... 87

IPC16 (Interrupt Priority Control 16)........................... 88

IPC2 (Interrupt Priority Control 2)............................... 76

IPC3 (Interrupt Priority Control 3)............................... 77

IPC4 (Interrupt Priority Control 4)............................... 78

IPC5 (Interrupt Priority Control 5)............................... 79

IPC6 (Interrupt Priority Control 6)............................... 80

IPC7 (Interrupt Priority Control 7)............................... 81

IPC8 (Interrupt Priority Control 8)............................... 82

IPC9 (Interrupt Priority Control 9)............................... 83

MINSEC (Minutes and Seconds Value) ................... 156

MTHDY (Month and Day Value)............................... 155

NVMCON (Flash Memory Control)............................. 47

OCxCON (Output Compare x Control)..................... 114

OSCCON (Oscillator Control)..................................... 93

OSCTUN (FRC Oscillator Tune) ................................ 95

PADCFG1 (Pad Configuration Control)............ 145, 153

PMADDR (Parallel Port Address)............................. 143

PMCON (Parallel Port Control)................................. 140

PMMODE (Parallel Port Mode) ................................ 142

PMPEN (Parallel Port Enable).................................. 143

PMSTAT (Parallel Port Status)................................. 144

RCFGCAL (RTCC Calibration

R

Reader Response............................................................. 226

Register Map

ADC ............................................................................ 35

CPU Core.................................................................... 29

CRC ............................................................................ 39

Dual Comparator......................................................... 38

I2C1 ............................................................................ 33

I2C2 ............................................................................ 33

ICN.............................................................................. 31

Input Capture .............................................................. 32

Interrupt Controller...................................................... 30

NVM............................................................................ 39

Output Compare ......................................................... 32

Parallel Master/Slave Port .......................................... 38

PMD............................................................................ 39

PORTA........................................................................ 35

PORTB........................................................................ 36

PORTC ....................................................................... 36

PORTD ....................................................................... 36

PORTE........................................................................ 37

PORTF........................................................................ 37

PORTG ....................................................................... 37

Real-Time Clock and Calendar................................... 38

SPI1 ............................................................................ 34

SPI2 ............................................................................ 34

System........................................................................ 39

Timers......................................................................... 31

UART1 ........................................................................ 34

UART2 ........................................................................ 34

Registers

AD1CHS (A/D Input Select)...................................... 170

AD1CON1 (A/D Control 1)........................................ 167

AD1CON2 (A/D Control 2)........................................ 168

AD1CON3 (A/D Control 3)........................................ 169

AD1CSSL (A/D Input Scan Select)........................... 171

AD1PCFG (A/D Port Configuration).......................... 171

ALCFGRPT (Alarm Configuration)............................ 154

ALMINSEC (Alarm Minutes and

Seconds Value) ................................................ 158

ALMTHDY (Alarm Month and Day Value) ................ 157

ALWDHR (Alarm Weekday and

Hours Value)..................................................... 157

CLKDIV (Clock Divider) .............................................. 94

CMCON (Comparator Control) ................................. 174

CORCON (Core Control) ...................................... 23, 61

CRCCON (CRC Control) .......................................... 161

CVRCON (Comparator Voltage

Reference Control) ........................................... 178

DEVID (Device ID).................................................... 183

DEVREV (Device Revision)...................................... 184

Flash Configuration Word 1 ...................................... 180

Flash Configuration Word 2 ...................................... 182

I2CxCON (I²Cx Control)............................................ 126

I2CxMSK (I²Cx Slave Mode

Address Mask).................................................. 130

I2CxSTAT (I²Cx Status)............................................ 128

ICxCON (Input Capture x Control)............................ 110

and Configuration)............................................ 151

RCON (Reset Control)................................................ 52

SPIxCON1 (SPIx Control 1) ..................................... 118

SPIxCON2 (SPIx Control 2) ..................................... 119

SPIxSTAT (SPIx Status and Control)....................... 117

SR (CPU STATUS) .................................................... 22

SR (STATUS in CPU)................................................. 61

T1CON (Timer1 Control) .......................................... 102

Timer3/5 Control)...................................................... 107

TxCON (Timer2/4 Control) ....................................... 106

UxMODE (UARTx Mode) ......................................... 134

UxSTA (UARTx Status and Control) ........................ 136

WKDYHR (Weekday and Hours Value) ................... 156

YEAR (Year Value)................................................... 155

Reset Sequence................................................................. 57

Resets ................................................................................ 51

Clock Source Selection .............................................. 53

Device Times.............................................................. 53

Revision History................................................................ 219

Preliminary

DS39747C-page 223

PIC24FJ128GA FAMILY

RTCC

U

Alarm.........................................................................159

Configuring........................................................159

Interrupt.............................................................159

ALRMVAL Register Mappings ..................................157

Calibration.................................................................158

Control Registers ......................................................151

Module Registers......................................................150

Mapping ............................................................150

RTCVAL Register Mapping.......................................155

UART

Baud Rate Generator (BRG) .................................... 132

Infrared Support........................................................ 133

IrDA

Built-in Encoder and Decoder........................... 133

External Support, Clock Output........................ 133

Operation of UxCTS and UxRTS

Control Pins...................................................... 133

Receiving

8-bit or 9-bit Data Mode.................................... 133

Transmitting

8-bit Data Mode................................................ 133

9-bit Data Mode................................................ 133

Break and Sync Sequence............................... 133

Universal Asynchronous Receiver

S

Selective Peripheral Module Control...................................98

Serial Peripheral Interface (SPI) .......................................115

Setup for Continuous Output Pulse Generation................111

Setup for Single Output Pulse Generation........................111

Software Simulator (MPLAB SIM).....................................198

Software Stack Pointer, Frame Pointer

Transmitter (UART) .................................................. 131

CALL Stack Frame......................................................40

Special Features ...............................................................179

Code Protection ........................................................179

Flexible Configuration ...............................................179

In-Circuit Emulation...................................................179

In-Circuit Serial Programming (ICSP).......................179

JTAG Boundary Scan Interface ................................179

Watchdog Timer (WDT)............................................179

Special Function Register Reset States..............................55

Symbols Used in Opcode Descriptions.............................190

V

VDDCORE/VCAP Pin ........................................................... 185

Voltage Regulator (On-Chip) ............................................ 185

W

Watchdog Timer (WDT).................................................... 186

Control Register........................................................ 186

Programming Considerations ................................... 186

WWW Address ................................................................. 225

WWW, On-Line Support ....................................................... 6

T

Timer1 Module ..................................................................101

Timer2/3 Module ...............................................................103

Timer4/5 Module ...............................................................103

Timing Diagrams

CLKO and I/O ...........................................................211

External Clock...........................................................209

Timing Requirements

Capacitive Loading on Output Pin ............................208

CLKO and I/O ...........................................................211

External Clock...........................................................209

Timing Specifications

PLL Clock..................................................................210

DS39747C-page 224

Preliminary

PIC24FJ128GA FAMILY

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

Preliminary

DS39747C-page 225

PIC24FJ128GA FAMILY

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

Device: PIC24FJ128GA Family

Questions:

Literature Number: DS39747C

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS39747C-page 226

Preliminary

PIC24FJ128GA FAMILY

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PIC 24 FJ 128 GA0 10 T - I / PT - XXX

a)

b)

PIC24FJ128GA008-I/PT 301:

General purpose PIC24, 96 KB program

memory, 80-pin, Industrial temp.,

TQFP package, QTP pattern #301.

Microchip Trademark

Architecture

PIC24FJ128GA010-I/PT:

Flash Memory Family

General purpose PIC24, 128 KB program

memory, 100-pin, Industrial temp.,

TQFP package.

Program Memory Size (KB)

Product Group

Pin Count

Tape and Reel Flag (if applicable)

Temperature Range

Package

Pattern

Architecture

24 = 16-bit modified Harvard without DSP

Flash Memory Family FJ = Flash program memory

Product Group

Pin Count

GA0 = General purpose microcontrollers

06 = 64-pin

08 = 80-pin

10 = 100-pin

Temperature Range

Package

I

= -40°C to +85°C (Industrial)

PT = 64-Lead, 80-Lead, 100-Lead (12x12x1 mm)

TQFP (Thin Quad Flatpack)

PF = 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack)

Pattern

Three-digit QTP, SQTP, Code or Special Requirements

(blank otherwise)

ES = Engineering Sample

Preliminary

DS39747C-page 227

PIC24FJ128GA FAMILY

DS39747C-page 228

Preliminary

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-3910

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-5160-8631

Fax: 91-11-5160-8632

China - Chengdu

Tel: 86-28-8676-6200

Fax: 86-28-8676-6599

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

Hong Kong

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Tel: 852-2401-1200

Fax: 852-2401-3431

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Atlanta

Korea - Seoul

Alpharetta, GA

Tel: 770-640-0034

Fax: 770-640-0307

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Boston

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Singapore

Tel: 65-6334-8870

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Fax: 65-6334-8850

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Detroit

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

San Jose

Mountain View, CA

Tel: 650-215-1444

Fax: 650-961-0286

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

06/08/06

DS39747C-page 228

Preliminary

DSTEMP