PIC24FJ64GL302 [MICROCHIP]
16-Bit eXtreme Low-Power Microcontrollers with LCD Controller in Low Pin Count Packages;
| 型号： | PIC24FJ64GL302 |
| 厂家： | 
MICROCHIP |
| 描述： | 16-Bit eXtreme Low-Power Microcontrollers with LCD Controller in Low Pin Count Packages CD 微控制器 |
| 文件： | 总424页 (文件大小：4867K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC24FJ128GL306 FAMILY
16-Bit eXtreme Low-Power Microcontrollers with
LCD Controller in Low Pin Count Packages
High-Performance CPU
Functional Safety and Security Peripherals
• Modified Harvard Architecture
• 128 Kbytes Flash Memory
• 8 Kbytes SRAM
• Fail-Safe Clock Monitor Operation:
- Detects clock failure and switches to on-chip,
low-power RC oscillator
• Power-on Reset (POR), Brown-out Reset (BOR)
• Up to 16 MIPS Operation @ 32 MHz
• 17-Bit x 17-Bit Single-Cycle Hardware
Fractional/Integer Multiplier
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• 32-Bit by 16-Bit Hardware Divider
• Programmable High/Low-Voltage Detect (HLVD)
• 16-Bit x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture
• Flexible Watchdog Timer (WDT) with
RC Oscillator for Reliable Operation
• Two Address Generation Units (AGUs) for Separate
Read and Write Addressing of Data Memory
• Deadman Timer (DMT) for Monitoring Health
of Software
• Programmable 32-Bit Cyclic Redundancy Check
(CRC) Generator
LCD Display Controller
• 32x8 with Up to 256 Pixels
• LCD Charge Pump
• Flash OTP by ICSP™ Write Inhibit
• CodeGuard™ Security
• Core-Independent LCD Animation
• Operation in Sleep mode
• ECC Flash Memory (128 Kbytes) with Fault
Injection:
-
-
Single Error Correction (SEC)
Double Error Detection (DED)
Analog Features
• Up to 17-Channel, Software-Selectable, 10/12-Bit
Analog-to-Digital Converter:
• Customer OTP Memory
• Unique Device Identifier (UDID)
- 12-bit, 350K samples/second conversion rate
(single Sample-and-Hold)
Special Microcontroller Features
- 10-bit, 400K samples/second conversion rate
(single Sample-and-Hold)
• Supply Voltage Range of 2.0V to 3.6V
• Operating Ambient Temperature Range of
-40°C to +125°C
- Sleep mode operation
- Low-voltage boost for input
- Band gap reference input feature
• On-Chip Voltage Regulators (1.8V) for
Low-Power Operation
- Core-independent windowed threshold
compare feature
• Flash Memory:
- 10,000 erase/write cycle endurance, typical
- Data retention: 20 years minimum
- Self-programmable under software control
- Flash OTP emulation
- Auto-scan feature
• Three Analog Comparators with Input Multiplexing:
- Programmable reference voltage for comparators
eXtreme Low-Power Features
• 8 MHz Fast RC Internal Oscillator:
-
-
Multiple clock divide options
Fast start-up
• Sleep and Idle modes Selectively Shut Down
Peripherals and/or Core for Substantial Power
Reduction and Fast Wake-up
• 96 MHz PLL Option
• Doze mode Allows CPU to Run at a Lower Clock
Speed than Peripherals
• Programmable Reference Clock Output
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Emulation (ICE) via Two Pins
• Alternate Clock modes Allow On-the-Fly
Switching to a Lower Clock Speed for Selective
Power Reduction
• JTAG Boundary Scan Support
• Retention Sleep with On-Chip Ultra Low-Power
Retention Regulator
2019-2020 Microchip Technology Inc.
DS30010198B-page 1
PIC24FJ128GL306 FAMILY
• Four UART modules:
Peripheral Features
- LIN/J2602 bus support (auto-wake-up,
Auto-Baud Detect, Break character support)
• Independent, Low-Power 32 kHz Timer Oscillator
• Six-Channel DMA Controller:
- RS-232 and RS-485 support
- IrDA® mode (hardware encoder/decoder
functions)
- Minimizes CPU overhead and increases data
throughput
• Timer1: 16-Bit Timer/Counter with External Crystal
Oscillator; Timer1 can Provide an A/D Trigger
• Five External Interrupt Pins
• Hardware Real-Time Clock and Calendar (RTCC)
• Timer2,3,4,5: 16-Bit Timer/Counter can Create
32-Bit Timer; Timer3 and Timer5 can Provide an
A/D Trigger
• Peripheral Pin Select (PPS) allows Independent
I/O Mapping of Many Peripherals
• Configurable Interrupt-on-Change on All I/O Pins:
• Five MCCP modules, Each with a Dedicated
16/32-Bit Timer:
- Each pin is independently configurable for
rising edge or falling edge change detection
- One 6-output MCCP module
- Four 2-output MCCP modules
• Reference Clock Output with Programmable
Divider
• Two Variable Width, Serial Peripheral Interface (SPI)
Ports on All Devices; Three Operation modes:
• Four Configurable Logic Cell (CLC) Blocks:
- Two inputs and one output, all mappable to
peripherals or I/O pins
- 3-wire SPI (supports all four SPI modes)
- Up to 32-byte deep FIFO buffer
- I2S mode
- AND/OR/XOR logic and D/JK flip-flop
functions
- Speed up to 25 MHz
• Two I2C Master and Slave w/Address Masking,
PMBus™ and IPMI Support
Qualification
• AEC-Q100 REVG (Grade 1: -40°C to +125°C)
Compliant
TABLE 1:
PIC24FJ128GL306 FAMILY DEVICES
Memory
Peripherals
Device
PIC24FJ128GL306
PIC24FJ128GL305
PIC24FJ128GL303
PIC24FJ128GL302
PIC24FJ64GL306
PIC24FJ64GL305
PIC24FJ64GL303
PIC24FJ64GL302
128K
128K
128K
128K
64K
8K
8K
8K
8K
8K
8K
8K
8K
64 54 32/33
48 39 24/25
36 29 15/16
28 21 13/14
64 54 32/33
48 39 24/25
36 29 15/16
28 21 13/14
6
6
6
6
6
6
6
6
17
12
11
9
3
3
3
3
3
3
3
3
Yes 1/4
Yes 1/4
Yes 1/4
Yes 1/4
Yes 1/4
Yes 1/4
Yes 1/4
Yes 1/4
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Yes Yes 256
Yes Yes 152
Yes Yes
Yes Yes
80
42
17
12
11
9
Yes Yes 256
Yes Yes 152
64K
64K
Yes Yes
Yes Yes
80
42
64K
DS30010198B-page 2
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Pin Diagrams
28-Pin QFN/UQFN
28 27 26 25 24 23 22
RG7
RG8
MCLR
RB5
1
2
3
4
5
6
7
RC14
RC13
VSS
21
20
19
18
17
16
15
(4)
RC15
RC12
VDD
PIC24FJXXXGL302
RB4
RB1
RG3
RB0
8
9 10 11 12 13 14
Note 1: See Table 2 for a complete description of pin functions.
2: Shaded pins are up to 5.5 VDC tolerant.
3: There is an internal pull-up resistor connected to the TMS pin during POR and programming.
4: RC15/OSCO will toggle during programming or debugging time.
TABLE 2:
28-PIN QFN/UQFN COMPLETE PIN FUNCTION DESCRIPTIONS
Pin
Function
Pin
Function
1
2
3
4
5
6
7
8
9
VLCAP1/C1INC/C2INC/C3INC/RP26/RG7
VLCAP2/C2IND/RP19/RG8
15 TDO/SEG47/RP31/SDA1/OCM1F/INT0/RG3
16 VDD
MCLR
17 OSCI/CLKI/RC12
18 OSCO/CLKO/RC15
19 VSS
PGC3/SEG2/AN5/C1INA/RP18/ASCL1(1)/OCM1A/RB5
PGD3/SEG3/AN4/C1INB/RP28/ASDA1(1)/OCM1B/RB4
PGC1/SEG6/CVREF-/AN1/AN1-/C2INA/RP1/RB1
PGD1/SEG7/VREF+/CVREF+/AN0/C2INB/RP0/RB0
PGC2/LCDBIAS3/AN6/RP6/RB6
20 SOSCI/RC13
21 SOSCO/SCLKI/RPI37/PWRLCLK/RC14
22 VCAP
PGD2/AN7/RP7/T1CK/RB7
23 VSS
10 AVDD/VDD
24 COM4/SEG48/RP2/SCL1/OCM1E/RF1
25 COM3/RE0
11 AVSS/VSS
12 TMS/COM5/SEG29/CVREF/AN10/RP15/RB10
13 TCK/SEG8/AN14/RP14/SDA2/OCM1C/RB14
14 TDI/SEG9/AN15/RP29/SCL2/OCM1D/RB15
26 COM2/C3INA/RE1
27 COM1/C3IND/RE2
28 COM0/HLVDIN/RE3
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
Note 1: Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit.
2019-2020 Microchip Technology Inc.
DS30010198B-page 3
PIC24FJ128GL306 FAMILY
Pin Diagrams (Continued)
28-Pin SOIC/SSOP
RF1
RE0
RE1
RE2
RE3
RG7
RG8
MCLR
RB5
RB4
RB1
RB0
RB6
RB7
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
VCAP
RC14
RC13
VSS
(4)
RC15
RC12
VDD
RG3
RB15
RB14
RB10
9
10
11
12
13
14
(3)
AVSS/VSS
AVDD/VDD
Note 1: See Table 3 for a complete description of pin functions.
2: Shaded pins are up to 5.5 VDC tolerant.
3: There is an internal pull-up resistor connected to the TMS pin during POR and programming.
4: RC15/OSCO will toggle during programming or debugging time.
TABLE 3:
28-PIN SOIC/SSOP COMPLETE PIN FUNCTION DESCRIPTIONS
Pin
Function
Pin
Function
1
2
3
4
5
6
7
8
9
COM4/SEG48/RP2/SCL1/OCM1E/RF1
COM3/RE0
15 AVDD/VDD
16 AVSS/VSS
COM2/C3INA/RE1
17 TMS/COM5/SEG29/CVREF/AN10/RP15/RB10
18 TCK/SEG8/AN14/RP14/SDA2/OCM1C/RB14
19 TDI/SEG9/AN15/RP29/SCL2/OCM1D/RB15
20 TDO/SEG47/RP31/SDA1/OCM1F/INT0/RG3
COM1/C3IND/RE2
COM0/HLVDIN/RE3
VLCAP1/C1INC/C2INC/C3INC/RP26/RG7
VLCAP2/C2IND/RP19/RG8
MCLR
21
VDD
22 OSCI/CLKI/RC12
23 OSCO/CLKO/RC15
PGC3/SEG2/AN5/C1INA/RP18/ASCL1(1)/OCM1A/RB5
10 PGD3/SEG3/AN4/C1INB/RP28/ASDA1(1)/OCM1B/RB4
11 PGC1/SEG6/CVREF-/AN1/AN1-/C2INA/RP1/RB1
12 PGD1/SEG7/VREF+/CVREF+/AN0/C2INB/RP0/RB0
13 PGC2/LCDBIAS3/AN6/RP6/RB6
24
VSS
25 SOSCI/RC13
26 SOSCO/SCLKI/RPI37/PWRLCLK/RC14
27
28
VCAP
VSS
14 PGD2/AN7/RP7/T1CK/RB7
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
Note 1: Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit.
DS30010198B-page 4
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Pin Diagrams (Continued)
36-Pin UQFN
RE5
RE6
1
2
3
4
5
6
7
8
9
RC14
RC13
Vss
RC15(4)
RC12
VDD
27
26
25
24
23
22
21
20
19
RE7
RG7
RG8
MCLR
RB5
PIC24FJXXXGL303
RG2
RB4
RG3
RB1
RB15
Note 1: See Table 4 for a complete description of pin functions.
2: Shaded pins are up to 5.5 VDC tolerant.
3: There is an internal pull-up resistor connected to the TMS pin during POR and programming.
4: RC15/OSCO will toggle during programming or debugging time.
2019-2020 Microchip Technology Inc.
DS30010198B-page 5
PIC24FJ128GL306 FAMILY
TABLE 4:
36-PIN UQFN COMPLETE PIN FUNCTION DESCRIPTIONS
Pin
Function
Pin
Function
1
2
3
4
5
6
7
8
9
LCDBIAS2/RE5
19 TDI/SEG9/AN15/RP29/SCL2/OCM1D/RB15
20 TDO/SEG47/RP31/SDA1/OCM1F/INT0/RG3
21 SEG28/SCL1/RG2
22 VDD
LCDBIAS1/RE6
LCDBIAS0/RE7
VLCAP1/C1INC/C2INC/C3INC/RP26/RG7
VLCAP2/C2IND/RP19/RG8
23 OSCI/CLKI/RC12
24 OSCO/CLKO/RC15
25 VSS
MCLR
PGC3/SEG2/AN5/C1INA/RP18/ASCL1(1)/OCM1A/RB5
PGD3/SEG3/AN4/C1INB/RP28/ASDA1(1)/OCM1B/RB4
PGC1/SEG6/CVREF-/AN1/AN1-/C2INA/RP1/RB1
26 SOSCI/RC13
27 SOSCO/SCLKI/RPI37/PWRLCLK/RC14
28 SEG25/C3INB/RD6
29 SEG26/C3INA/RD7
30 VCAP
10 PGD1/SEG7/VREF+//CVREF+/AN0/C2INB/RP0/RB0
11 PGC2/LCDBIAS3/AN6/RP6/RB6
12 PGD2/AN7/RP7/T1CK/RB7
13 AVDD/VDD
31 VSS
14 AVSS/VSS
32 COM4/SEG48/RP2/OCM1E/RF1
33 COM3/RE0
15 COM7/SEG31/AN8/RP8/RB8
16 COM6/SEG30/AN9/RP9/RB9
17 TMS/COM5/SEG29/CVREF/AN10/RP15/RB10
18 TCK/SEG8/AN14/RP14/SDA2/OCM1C/RB14
34 COM2/RE1
35 COM1/C3IND/RE2
36 COM0/HLVDIN/RE3
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
Note 1: Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit.
DS30010198B-page 6
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Pin Diagrams (Continued)
48-Pin TQFP/UQFN
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
RE5
RE6
RE7
RG7
RG8
MCLR
VSS
1
RC14
RC13
RD0
2
3
RD11
RD10
4
5
VSS
6
PIC24FJXXXGL305
(4)
RC15
7
RC12
VDD
VDD
8
RB5
RB4
RB1
RB0
9
RG2
RG3
RF3
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
Note 1: See Table 5 for a complete description of pin functions.
2: Shaded pins are up to 5.5 VDC tolerant.
3: There is an internal pull-up resistor connected to the TMS pin during POR and programming.
4: RC15/OSCO will toggle during programming or debugging time.
2019-2020 Microchip Technology Inc.
DS30010198B-page 7
PIC24FJ128GL306 FAMILY
TABLE 5:
48-PIN TQFP/UQFN COMPLETE PIN FUNCTION DESCRIPTIONS
Pin
Function
Pin
Function
1
2
3
4
5
6
7
8
9
LCDBIAS2/RE5
25 SEG12/RP16/RF3
LCDBIAS1/RE6
26 SEG47/RP31/SDA1/OCM1F/INT0/RG3
27 SEG28/SCL1/RG2
28 VDD
LCDBIAS0/RE7
VLCAP1/C1INC/C2INC/C3INC(2)/RP26/RG7
VLCAP2/AN19/C2IND/RP19/RG8
29 OSCI/CLKI/RC12
30 OSCO/CLKO/RC15
31 VSS
MCLR
VSS
VDD
32 SEG15/C3IND/RP3/RD10
33 SEG16/C3INC/RP12/RD11
34 SEG17/RP11/RD0
35 SOSCI/RC13
PGC3/SEG2/AN5/C1INA/RP18/SCL1(1)/OCM1A/RB5
10 PGD3/SEG3/AN4/C1INB/RP28/SDA1(1)/OCM1B/RB4
11 PGC1/SEG6/CVREF-/AN1/AN1-/C2INA/RP1/RB1
12 PGD1/SEG7/VREF+/CVREF+/AN0/C2INB/RP0/RB0
13 PGC2/LCDBIAS3/AN6/C1IND/RP6/RB6
14 PGD2/AN7/RP7/T1CK/RB7
36 SOSCO/SCLKI/RPI37/PWRLCLK/RC14
37 SEG22/RP22/RD3
38 SEG23/RP25/RD4
39 SEG24/RP20/RD5
40 SEG25/C3INB/RD6
41 SEG26/C3INA/RD7
42 VCAP
15 AVDD
16 AVSS
17 COM7/SEG31/AN8/RP8/RB8
18 COM6/SEG30/AN9/RP9/RB9
19 TMS/COM5/SEG29/CVREF/AN10/RP15/RB10
20 TDO/AN11/RB11
43 VSS
44 COM4/SEG48/RP2/OCM1E/RF1
45 COM3/RE0
21 TCK/SEG8/AN14/RP14/OCM1C/RB14
22 TDI/SEG9/AN15/RP29/OCM1D/RB15
23 SEG10/RP10/SDA2/RF4
46 COM2/RE1
47 COM1/RE2
24 SEG11/RP17/SCL2/RF5
48 COM0/HLVDIN/RE3
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
Note 1: Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit.
2: Alternate pin assignments for C3INC as determined by the ALTCMPI Configuration bit.
DS30010198B-page 8
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Pin Diagrams (Continued)
64-Pin TQFP/QFN
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RC14
RC13
RD0
RE5
RE6
RE7
RG6
RG7
RG8
MCLR
RG9
VSS
1
2
3
4
5
6
7
8
RD11
RD10
RD9
RD8
VSS
PIC24FJXXXGL306
RC15(4)
9
RC12
VDD
VDD
10
11
12
13
14
15
16
RB5
RB4
RB3
RB2
RB1
RB0
RG2
RG3
RF6
RF2
RF3
Note 1: See Table 6 for a complete description of pin functions.
2: Shaded pins are up to 5.5 VDC tolerant.
3: There is an internal pull-up resistor connected to the TMS pin during POR and programming.
4: RC15/OSCO will toggle during programming or debugging time.
2019-2020 Microchip Technology Inc.
DS30010198B-page 9
PIC24FJ128GL306 FAMILY
TABLE 6:
64-PIN TQFP/QFN COMPLETE PIN FUNCTION DESCRIPTIONS
Pin
Function
Pin
Function
1
2
3
4
5
6
7
8
9
LCDBIAS2/RE5
33 SEG12/RP16/RF3
34 SEG40/RP30/RF2
35 RP5/INT0/RF6
LCDBIAS1/RE6
LCDBIAS0/RE7
SEG0/C1IND/RP21/RG6
VLCAP1/C1INC/C2INC(2)/C3INC(2)/RP26/RG7
36 SEG47/RP31/SDA1/OCM1F/RG3
37 SEG28/SCL1/RG2
38 VDD
VLCAP2/C2IND/RP19/RG8
MCLR
39 OSCI/CLKI/RC12
40 OSCO/CLKO/RC15
41 VSS
SEG1/C2INC/RP27/RG9
VSS
10 VDD
42 SEG13/RP2/RD8
43 SEG14/RP4/RD9
44 SEG15/C3IND/RP3/RD10
45 SEG16/C3INC/RP12/RD11
46 SEG17/RP11/RD0
47 SOSCI/RC13
11 PGC3/SEG2/AN5/C1INA/RP18/ASCL1(1)/OCM1A/RB5
12 PGD3/SEG3/AN4/C1INB/RP28/ASDA1(1)/OCM1B/RB4
13 SEG4/AN3/C2INA/RB3
14 SEG5/AN2/C2INB/RP13/RB2
15 PGC1/SEG6/CVREF-/AN1/AN1-/RP1/RB1
16 PGD1/SEG7/VREF+/CVREF+/AN0/RP0/RB0
17 PGC2/LCDBIAS3/AN6/RP6/RB6
18 PGD2/AN7/RP7/T1CK/RB7
19 AVDD
48 SOSCO/SCLKI/RPI37/PWRLCLK/RC14
49 SEG20/RP24/RD1
50 SEG21/RP23/RD2
51 SEG22/RP22/RD3
52 SEG23/RP25/RD4
53 SEG24/RP20/RD5
54 SEG25/C3INB/RD6
55 SEG26/C3INA/RD7
56 VCAP
20 AVSS
21 COM7/SEG31/AN8/RP8/RB8
22 COM6/SEG30/AN9/RP9/RB9
23 TMS/COM5/SEG29/CVREF/AN10/RP15/RB10
24 TDO/AN11/RB11
25 VSS
57 AN16/RA0
26 VDD
58 SEG27/RF0
27 TCK/SEG18/AN12/RB12
28 TDI/SEG19/AN13/RB13
29 SEG8/AN14/RP14/OCM1C/RB14
30 SEG9/AN15/RP29/OCM1D/RB15
31 SEG10/RP10/SDA2/RF4
32 SEG11/RP17/SCL2/RF5
59 COM4/SEG48/OCM1E/RF1
60 COM3/RE0
61 COM2/RE1
62 COM1/RE2
63 COM0/RE3
64 SEG63/HLVDIN/RE4
Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions.
Note 1: Alternate pin assignments for I2C1 as determined by the ALTI2C1 Configuration bit.
2: Alternate pin assignments for C2INC and C3INC as determined by the ALTCMPI Configuration bit.
DS30010198B-page 10
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 15
2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 21
3.0 CPU............................................................................................................................................................................................ 27
4.0 Memory Organization................................................................................................................................................................. 33
5.0 Direct Memory Access Controller (DMA) ................................................................................................................................... 53
6.0 Flash Program Memory.............................................................................................................................................................. 61
7.0 Resets ........................................................................................................................................................................................ 75
8.0 Interrupt Controller ..................................................................................................................................................................... 81
9.0 Oscillator Configuration.............................................................................................................................................................. 95
10.0 Power-Saving Features............................................................................................................................................................ 113
11.0 I/O Ports ................................................................................................................................................................................... 125
12.0 Timer1 ...................................................................................................................................................................................... 157
13.0 Timer2/3 and Timer4/5............................................................................................................................................................. 159
14.0 Capture/Compare/PWM/Timer Modules (MCCP) .................................................................................................................... 165
15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 181
2
16.0 Inter-Integrated Circuit (I C)..................................................................................................................................................... 201
17.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 209
18.0 Liquid Crystal Display (LCD) Controller.................................................................................................................................... 219
19.0 Real-Time Clock and Calendar (RTCC) with Timestamp......................................................................................................... 235
20.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator........................................................................................ 255
21.0 Configurable Logic Cell (CLC).................................................................................................................................................. 261
22.0 12-Bit A/D Converter with Threshold Detect ............................................................................................................................ 271
23.0 Triple Comparator Module........................................................................................................................................................ 289
24.0 Comparator Voltage Reference................................................................................................................................................ 295
25.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 297
26.0 Deadman Timer (DMT) ............................................................................................................................................................ 299
27.0 Special Features ...................................................................................................................................................................... 307
28.0 Instruction Set Summary.......................................................................................................................................................... 329
29.0 Development Support............................................................................................................................................................... 337
30.0 Electrical Characteristics.......................................................................................................................................................... 339
31.0 Packaging Information.............................................................................................................................................................. 381
Appendix A: Revision History............................................................................................................................................................. 411
Index ................................................................................................................................................................................................. 413
The Microchip Website ...................................................................................................................................................................... 419
Customer Change Notification Service .............................................................................................................................................. 419
Customer Support.............................................................................................................................................................................. 419
Product Identification System ............................................................................................................................................................ 421
2019-2020 Microchip Technology Inc.
DS30010198B-page 11
PIC24FJ128GL306 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS30010198B-page 12
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33/PIC24 Family
Reference Manual”. These documents should be
considered as the general reference for the operation
of a particular module or device feature.
Note 1: To access the documents listed below,
browse to the documentation section of the
PIC24FJ128GL306 product page of the
Microchip website (www.microchip.com) or
select a family reference manual section
from the following list.
In addition to parameters, features and
other documentation, the resulting page
provides links to the related family
reference manual sections.
• “CPU with Extended Data Space (EDS)” (www.microchip.com/DS39732)
• “Direct Memory Access Controller (DMA)” (www.microchip.com/DS30009742)
• “PIC24F Flash Program Memory” (www.microchip.com/DS30009715)
• “Data Memory with Extended Data Space (EDS)” (www.microchip.com/DS39733)
• “Reset” (www.microchip.com/DS39712)
• “Interrupts” (www.microchip.com/DS70000600)
• “Oscillator” (www.microchip.com/DS39700)
• “Power-Saving Features with Deep Sleep” (www.microchip.com/DS39727)
• “I/O Ports with Peripheral Pin Select (PPS)” (www.microchip.com/DS30009711)
• “Timers” (www.microchip.com/DS39704)
• “Capture/Compare/PWM/Timer (MCCP and SCCP)” (www.microchip.com/DS30003035)
• “Serial Peripheral Interface (SPI) with Audio Codec Support” (www.microchip.com/DS70005136)
• “Inter-Integrated Circuit (I2C)” (www.microchip.com/DS70000195)
• “Universal Asynchronous Receiver Transmitter (UART)” (www.microchip.com/DS70000582)
• “RTCC with Timestamp” (www.microchip.com/DS70005193)
• “32-Bit Programmable Cyclic Redundancy Check (CRC)” (www.microchip.com/DS30009729)
• “Configurable Logic Cell (CLC)” (www.microchip.com/DS70005298)
• “12-Bit A/D Converter with Threshold Detect” (www.microchip.com/DS39739)
• “Scalable Comparator Module” (www.microchip.com/DS39734)
• “Dual Comparator Module” (www.microchip.com/DS39710)
• “High-Level Integration with Programmable High/Low-Voltage Detect (HLVD)” (www.microchip.com/DS39725)
• “Watchdog Timer (WDT)” (www.microchip.com/DS39697)
• “CodeGuard™ Intermediate Security” (www.microchip.com/DS70005182)
• “High-Level Device Integration” (www.microchip.com/DS39719)
• “Programming and Diagnostics” (www.microchip.com/DS39716)
• “Comparator Voltage Reference Module” (www.microchip.com/DS39709)
• “Deadman Timer” (www.microchip.com/DS70005155)
• “Liquid Crystal Display (LCD)” (www.microchip.com/DS30009740)
2019-2020 Microchip Technology Inc.
DS30010198B-page 13
PIC24FJ128GL306 FAMILY
NOTES:
DS30010198B-page 14
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
This new low-power mode also supports the continuous
operation of the low-power, on-chip Real-Time Clock/
Calendar (RTCC), making it possible for an application
to keep time while the device is otherwise asleep.
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC24FJ128GL306
• PIC24FJ128GL305
• PIC24FJ128GL303
• PIC24FJ128GL302
• PIC24FJ64GL306
• PIC24FJ64GL305
• PIC24FJ64GL303
• PIC24FJ64GL302
Aside from this new feature, PIC24FJ128GL306 family
devices also include all of the legacy power-saving
features of previous PIC24F microcontrollers, such as:
• On-the-Fly Clock Switching, allowing the selection
of a lower power clock during run time
The PIC24FJ128GL306 family introduces eXtreme
low-power microcontrollers with LCD controller in low pin
count packages. This is a 16-bit microcontroller family
with a broad peripheral feature set and enhanced
computational performance. This family also offers a
new migration option for those high-performance
applications which may be outgrowing their 8-bit
platforms, but do not require the numerical processing
power of a Digital Signal Processor (DSP).
• Doze Mode Operation, for maintaining peripheral
clock speed while slowing the CPU clock
• Instruction-Based Power-Saving Modes, for quick
invocation of the Idle and Sleep modes
1.1.3
OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC24FJ128GL306 family offer
six different oscillator options, allowing users a range of
choices in developing application hardware. These
include:
Table 1-1 lists the functions of the various pins shown
in the pinout diagrams.
• Two Crystal modes
1.1
Core Features
• External Clock (EC) mode
• A Phase-Locked Loop (PLL) frequency multiplier,
which allows processor speeds up to 32 MHz
1.1.1
16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® Digital Signal Controllers (DSCs). The PIC24F
CPU core offers a wide range of enhancements,
such as:
• An internal Fast RC Oscillator (FRC), a nominal
8 MHz output with multiple frequency divider options
• A separate internal Low-Power RC Oscillator
(LPRC), 32 kHz nominal for low-power,
timing-insensitive applications.
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor (FSCM).
This option constantly monitors the main clock source
against a reference signal provided by the internal oscil-
lator and enables the controller to switch to the internal
oscillator, allowing for continued low-speed operation
or a safe application shutdown.
• Linear addressing of up to 12 Mbytes
(program space) and 32 Kbytes (data)
• A 16-element Working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
1.1.4
EASY MIGRATION
• Hardware support for 32 by 16-bit division
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve. The
consistent pinout scheme used throughout the entire
family also aids in migrating from one device to the next
larger device.
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as ‘C’
• Operational performance up to 16 MIPS
1.1.2
POWER-SAVING TECHNOLOGY
The PIC24FJ128GL306 family of devices includes
Retention Sleep, a low-power mode with essential
circuits being powered from a separate low-voltage
regulator.
2020 Microchip Technology Inc.
DS30010198B-page 15
PIC24FJ128GL306 FAMILY
• Communications: The PIC24FJ128GL306 family
incorporates a range of serial communication
peripherals to handle a range of application
requirements. There are two independent I2C
modules that support both Master and Slave
modes of operation. Devices also have, through
the PPS feature, four independent UARTs with
built-in IrDA® encoders/decoders, LIN support and
two SPI modules.
1.2
DMA Controller
PIC24FJ128GL306 family devices have a Direct Memory
Access (DMA) Controller. This module acts in concert
with the CPU, allowing data to move between data
memory and peripherals without the intervention of the
CPU, increasing data throughput and decreasing execu-
tion time overhead. Six independently programmable
channels make it possible to service multiple peripherals
at virtually the same time, with each channel peripheral
performing a different operation. Many types of data
transfer operations are supported.
• Analog Features: All members of the
PIC24FJ128GL306 family include a 12-bit A/D
Converter (A/D) module and a triple comparator
module. The A/D module incorporates a range of
new features that allow the converter to assess
and make decisions on incoming data, reducing
CPU overhead for routine A/D conversions. The
comparator module includes three analog
comparators that are configurable for a wide
range of operations.
1.3
LCD Controller
The versatile on-chip LCD controller includes many
features that make the integration of displays in low-
power applications easier. These include an integrated
voltage regulator with charge pump and an integrated
internal resistor ladder that allows contrast control in
software, and display operation above the device VDD.
• Real-Time Clock and Calendar (RTCC): This
module implements a full-featured clock and
calendar with alarm functions in hardware, freeing
up timer resources and program memory space
for use of the core application.
Core-independent automatic display features:
• Dual display memory
• Blink mode of individual pixels or the complete
pixels
• Deadman Timer (DMT): This module is provided
to interrupt the processor in the event of a
software malfunction.
• Blank of individual pixels or the complete pixels
• Timing schedule can be changed without core
intervention, based on user configurations
1.5
Details of Individual Family
Members
1.4
Other Special Features
Devices in the PIC24FJ128GL306 family are available
in 28-pin, 36-pin, 48-pin and 64-pin packages. The
general block diagram for all devices is shown in
Figure 1-1.
• Peripheral Pin Select: The Peripheral Pin Select
(PPS) feature allows most digital peripherals to be
mapped over a fixed set of digital I/O pins. Users
may independently map the input and/or output of
any one of the many digital peripherals to any one
of the I/O pins.
A
list of the pin features available on the
PIC24FJ128GL306 family devices, sorted by function,
is shown in Table 1-1. Note that this table shows the pin
location of individual peripheral features and not how
they are multiplexed on the same pin. This information
is provided in the “Pin Diagrams” section in the begin-
ning of this data sheet. Multiplexed features are sorted
by the priority given to a feature, with the highest
priority peripheral being listed first.
• Configurable Logic Cell: The Configurable
Logic Cell (CLC) module allows the user to
specify combinations of signals as inputs to a
logic function and to use the logic output to control
other peripherals or I/O pins.
• Timing Modules: The PIC24FJ128GL306 family
provides five independent, general purpose, 16-bit
timers (four of which can be combined
into two 32-bit timers). The devices also include
five multiple output advanced
Capture/Compare/PWM/Timer peripherals.
DS30010198B-page 16
2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
FIGURE 1-1:
PIC24FJ128GL306 FAMILY GENERAL BLOCK DIAGRAM
Data Bus
Interrupt
Controller
PORTA(1)
(1 I/O)
16
16
16
8
Data Latch
Data RAM
EDS and
Table Data
Access Control
PORTB(1)
(16 I/Os)
DMA
Controller
PCH
PCL
23
Program Counter
Address
Latch
Stack
Control
Logic
Repeat
Control
Logic
PORTC(1)
(4 I/Os)
16
23
16
16
Read AGU
Write AGU
Address Latch
PORTD(1)
(12 I/Os)
Program Memory/
Extended Data
Space
Data Latch
PORTE(1)
(8 I/Os)
Address Bus
24
EA MUX
16
16
Inst Latch
PORTF(1)
(7 I/Os)
Literal
Data
Inst Register
DMA
Data Bus
PORTG(1)
(6 I/Os)
Instruction
Decode and
Control
Control Signals
OSCO/CLKO
16
OSCI/CLKI
SOSCO/SOSCI
REFO
Divide
Power-up
Timer
Support
Timing
16 x 16
W Reg Array
Generation
17x17
Multiplier
Oscillator
Start-up Timer
FRC/LPRC
Oscillators
Power-on
Reset
Precision
Band Gap
Reference
16-Bit ALU
Watchdog
Timer
16
HLVD and
BOR(2)
Voltage
Regulators
VCAP
VDD, VSS
MCLR
Timer2/3(3)
and 4/5
12-Bit
A/D
MCCP
1/4
Comparators(3)
CLC1-4(1)
Timer1
RTCC
SPI
1-2(3)
UART
1-4(3)
IOCs(1)
DMT
I2C1-2
LCD
Note 1: Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-1 for specific implementations by pin count.
2: Some peripheral I/Os are only accessible through remappable pins.
3: These peripheral I/Os are only accessible through remappable pins.
2020 Microchip Technology Inc.
DS30010198B-page 17
PIC24FJ128GL306 FAMILY
TABLE 1-1:
Pin Name
PIC24FJ128GL306 FAMILY PINOUT DESCRIPTION
Pin
Buffer Type
PPS
Description
Type
AN0-AN16
AVDD
I
Analog
—
No A/D Analog Inputs
P
P
No Positive Supply for Analog Modules
No Ground Reference for Analog Modules
AVSS
—
C1INA-C1IND
C1OUT
I
O
Analog
DIG
No Comparator 1 Inputs A through D
Yes Comparator 1 Output
C2INA-C2IND
C2OUT
I
O
Analog
DIG
No Comparator 2 Inputs A through D
Yes Comparator 2 Output
C3INA-C3IND
C3OUT
I
O
Analog
DIG
No Comparator 3 Inputs A through D
Yes Comparator 3 Output
CLKI
CLKO
—
O
—
DIG
No Main Clock Input Connection
No System Clock Output
COM0-COM7
LCDBIAS0-LCDBIAS3
VLCAP1
VLCAP2
SEG0-SEG31
SEG40
SEG47
SEG48
SEG63
O
O
O
O
O
O
O
O
O
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
No LCD Driver Common Outputs 0 through 7
No Bias Inputs 0 through 3 for LCD Driver Charge Pump
No LCD Drive Charge Pump Capacitor Input 1
No LCD Drive Charge Pump Capacitor Input 2
No LCD Driver Segment Outputs 0 through 31
No LCD Driver Segment Output 40
No LCD Driver Segment Output 47
No LCD Driver Segment Output 48
No LCD Driver Segment Output 63
CVREF
O
I
Analog
Analog
Analog
No Comparator Voltage Reference Output
No Comparator Voltage Reference (high) Input
No Comparator Voltage Reference (low) Input
CVREF+
CVREF-
I
INT0
INT1-INT4
I
I
ST
ST
No External Interrupt Input 0
Yes External Interrupt Inputs 1 through 4
HLVDIN
MCLR
I
I
Analog
ST
No High/Low-Voltage Detect Input
No Master Clear (device Reset) Input
This line is brought low to cause a Reset.
ICM1-ICM5
TCKIA-TCKIB
OCFA-OCFB
OCM1A-OCM1F
OCM2A-OCM2B
OCM3A-OCM3B
OCM4A-OCM4B
OCM5A-OCM5B
I
I
I
O
O
O
O
O
ST
ST
ST
DIG
DIG
DIG
DIG
DIG
Yes MCCP Capture Inputs 1 through 5
Yes MCCP Timer Clock Inputs A through B
Yes MCCP Fault Inputs A through B
No MCCP1 Outputs A through F
Yes MCCP2 Outputs A through B
Yes MCCP3 Outputs A through B
Yes MCCP4 Outputs A through B
Yes MCCP5 Outputs A through B
CLCINA-CLCIND
CLC1OUT-CLC4OUT
I
O
ST
DIG
Yes CLC Inputs A through D
Yes CLC Outputs 1 through 4
OSCI
OSCO
I
O
Analog/ST
No Main Oscillator Input Connection
Main Oscillator Output Connection
REFO
REFI
O
I
—
ST
Yes Reference Clock Output
Yes Reference Clock Input
Legend: TTL = TTL input buffer
I2C = I2C/SMBus input buffer
ST = Schmitt Trigger input buffer
Analog = Analog level input/output
DIG = Digital input/output
SMB3 = SMBus Version 3
DS30010198B-page 18
2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 1-1:
Pin Name
PIC24FJ128GL306 FAMILY PINOUT DESCRIPTION (CONTINUED)
Pin
Buffer Type
PPS
Description
Type
PGC1
PGD1
PGC2
PGD2
PGC3
PGD3
I
ST
DIG/ST
ST
DIG/ST
ST
No ICSP™ Programming Clock 1
No ICSP Programming Data 1
No ICSP Programming Clock 2
No ICSP Programming Data 2
No ICSP Programming Clock 3
No ICSP Programming Data 3
I/O
I
I/O
I
I/O
DIG/ST
PWRLCLK
TMPRN
PWRGT
RTCC
I
I
O
O
ST
ST
DIG
DIG
No Real-Time Clock 50/60 Hz Clock Input
Yes Tamper Detect
Yes RTCC Power Control
Yes RTCC Clock Output
RA0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
DIG/ST
DIG/ST
DIG/ST
DIG/ST
DIG/ST
DIG/ST
DIG/ST
DIG/ST
ST
No PORTA Digital I/O
RB0-RB15
RC12-RC15
RD0-RD11
RE0-RE7
No PORTB Digital I/Os
No PORTC Digital I/Os
No PORTD Digital I/Os
No PORTE Digital I/Os
RF0-RF6
No PORTF Digital I/Os
RG2-RG3, RG6-RG9
RP0-RP31
RPI37
No PORTG Digital I/Os
No Remappable Peripherals (input or output)
No Remappable Peripheral (input only)
SCK1
SDI1
SDO1
SS1
I/O
I
O
ST
ST
DIG
ST
Yes Synchronous Serial Clock Input/Output for SPI1
Yes SPI1 Data In
Yes SPI1 Data Out
I/O
Yes SPI1 Slave Synchronization or Frame Pulse I/O
SCK2
SDI2
SDO2
SS2
I/O
I
O
ST
ST
DIG
ST
Yes Synchronous Serial Clock Input/Output for SPI2
Yes SPI2 Data In
Yes SPI2 Data Out
I/O
Yes SPI2 Slave Synchronization or Frame Pulse I/O
SCL1
SDA1
I/O
DIG/I2C/SMB3
No I2C1 Synchronous Serial Clock Input/Output
I2C1 Data Input/Output
ASCL1
ASDA1
Alternate I2C1 Synchronous Serial Clock Input/Output
Alternate I2C1 Data Input/Output
SCL2
SDA2
I/O
DIG/I2C/SMB3
No I2C2 Synchronous Serial Clock Input/Output
I2C2 Data Input/Output
U1CTS
U1RTS
U1RX
I
O
I
ST
DIG
ST
Yes UART1 Clear-to-Send
Yes UART1 Request-to-Send
Yes UART1 Receive
U1TX
O
DIG
Yes UART1 Transmit
U2CTS
U2RTS
U2RX
I
O
I
ST
DIG
ST
Yes UART2 Clear-to-Send
Yes UART2 Request-to-Send
Yes UART2 Receive
U2TX
O
DIG
Yes UART2 Transmit
U3CTS
U3RTS
U3RX
I
O
I
ST
DIG
ST
Yes UART3 Clear-to-Send
Yes UART3 Request-to-Send
Yes UART3 Receive
U3TX
O
DIG
Yes UART3 Transmit
Legend: TTL = TTL input buffer
I2C = I2C/SMBus input buffer
ST = Schmitt Trigger input buffer
Analog = Analog level input/output
DIG = Digital input/output
SMB3 = SMBus Version 3
2020 Microchip Technology Inc.
DS30010198B-page 19
PIC24FJ128GL306 FAMILY
TABLE 1-1:
Pin Name
PIC24FJ128GL306 FAMILY PINOUT DESCRIPTION (CONTINUED)
Pin
Buffer Type
PPS
Description
Type
U4CTS
U4RTS
U4RX
I
O
I
ST
DIG
ST
Yes UART4 Clear-to-Send
Yes UART4 Request-to-Send
Yes UART4 Receive
U4TX
O
DIG
Yes UART4 Transmit
SOSCI
SOSCO
SCLKI
—
—
I
—
—
ST
—
Secondary Oscillator/Timer1 Clock Input
No Secondary Oscillator/Timer1 Clock Output
No Secondary Clock Digital Input
T1CK
T2CK-T5CK
TxCK
I
I
I
ST
ST
ST
No Timer1 Clock
Yes Timer2 through Timer5 Clock
Yes Timer External Clock
TCK
TDI
TDO
TMS
I
I
O
I
ST
ST
DIG
ST
No JTAG Test Clock/Programming Clock Input
No JTAG Test Data/Programming Data Input
No JTAG Test Data Output
No JTAG Test Mode Select Input
VCAP
VDD
P
P
I
—
—
No External Filter Capacitor Connection (regulator enabled)
No Positive Supply for Peripheral Digital Logic and I/O Pins
No Comparator and A/D Reference Voltage (high) Input
No Ground Reference for Peripheral Digital Logic and I/O Pins
VREF+
VSS
Analog
—
P
Legend: TTL = TTL input buffer
I2C = I2C/SMBus input buffer
ST = Schmitt Trigger input buffer
Analog = Analog level input/output
DIG = Digital input/output
SMB3 = SMBus Version 3
DS30010198B-page 20
2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTIONS
2.0
2.1
GUIDELINES FOR GETTING
STARTED WITH
16-BIT MICROCONTROLLERS
(2)
C2
VDD
Basic Connection Requirements
Getting started with the PIC24FJ128GL306 family of
16-bit microcontrollers requires attention to a minimal
set of device pin connections before proceeding with
development.
R1
R2
(1)
MCLR
VCAP
C1
The following pins must always be connected:
C7
PIC24FJXXX
• All VDD and VSS pins
(see Section 2.2 “Power Supply Pins”)
VDD
VSS
VDD
(2)
(2)
C3
C6
• All AVDD and AVSS pins, regardless of whether or
not the analog device features are used
VSS
(see Section 2.2 “Power Supply Pins”)
• MCLR pin
(see Section 2.3 “Master Clear (MCLR) Pin”)
(2)
(2)
C4
C5
• VCAP pin
(see Section 2.4 “Voltage Regulator Pin (VCAP)”)
These pins must also be connected if they are being
used in the end application:
Key (all values are recommendations):
C1 through C6: 0.1 µF, 50V ceramic
C7: 10 µF, 16V or greater, ceramic
R1: 10 kΩ
• PGCx/PGDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.4.2 “ICSP Pins”)
R2: 100Ω to 470Ω
• OSCI and OSCO pins when an external oscillator
source is used
(see Section 2.5 “External Oscillator Pins”)
Note 1: See Section 2.4 “Voltage Regulator Pin
(VCAP)” for an explanation of voltage
regulator pin connections.
2: The example shown is for a PIC24F device
with five VDD/VSS and AVDD/AVSS pairs.
Other devices may have more or less pairs;
adjust the number of decoupling capacitors
appropriately.
Additionally, the following pins may be required:
• VREF+ pin used when external voltage reference
for analog modules is implemented
Note:
The AVDD and AVSS pins must always be
connected, regardless of whether any of
the analog modules are being used.
The minimum mandatory connections are shown in
Figure 2-1.
2019-2020 Microchip Technology Inc.
DS30010198B-page 21
PIC24FJ128GL306 FAMILY
2.2
Power Supply Pins
2.3
Master Clear (MCLR) Pin
The MCLR pin provides two specific device functions:
device Reset, and device programming and debug-
ging. If programming and debugging are not required
in the end application, a direct connection to VDD
may be all that is required. The addition of other
components, to help increase the application’s
resistance to spurious Resets from voltage sags, may
be beneficial. A typical configuration is shown in
Figure 2-1. Other circuit designs may be implemented
depending on the application’s requirements.
2.2.1
DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A 0.1 µF (100 nF),
25V-50V capacitor is recommended. The capacitor
should be a low-ESR device with a self-resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
During programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R1 and C1 will need to be adjusted based on the
application and PCB requirements. For example, it is
recommended that the capacitor, C1, be isolated
from the MCLR pin during programming and debug-
ging operations by using a jumper (Figure 2-2). The
jumper is replaced for normal run-time operations.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
• Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic-type capaci-
tor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1 µF in parallel with 0.001 µF).
Any components associated with the MCLR pin
should be placed within 0.25 inch (6 mm) of the pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R1
R2
MCLR
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
PIC24FJXXX
JP
C1
Note 1: R1 10 k is recommended. A suggested
starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
inductance.
2.2.2
BULK CAPACITORS
2: R2 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of a MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
On boards with power traces running longer than six
inches in length, it is suggested to use a bulk
capacitance of 10 µF or greater located near the MCU.
The value of the capacitor should be determined based
on the trace resistance that connects the power supply
source to the device, and the maximum current drawn
by the device in the application. Typical values range
from 10 µF to 47 µF. The capacitor should be ceramic
and have a voltage rating of 25V or more to reduce DC
bias effects (see Section 2.4.1 “Considerations for
Ceramic Capacitors”).
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FIGURE 2-3:
FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
2.4
Voltage Regulator Pin (VCAP)
Note:
This section applies only to PIC24FJ
devices with an on-chip voltage regulator.
10
1
Refer to Section 27.3 “On-Chip Voltage Regulator”
for details on connecting and using the on-chip
regulator.
A low-ESR (< 5Ω) capacitor is required on the VCAP pin
to stabilize the voltage regulator output voltage. The
VCAP pin must not be connected to VDD and must use a
capacitor of 10 µF connected to ground. The type can be
ceramic or tantalum. Suitable examples of capacitors
are shown in Table 2-1. Capacitors with equivalent
specifications can be used.
0.1
0.01
0.001
0.01
0.1
1
10
100
1000 10,000
Frequency (MHz)
Designers may use Figure 2-3 to evaluate the ESR
equivalence of candidate devices.
Note: Typical data measurement at +25°C, 0V DC bias.
The placement of this capacitor should be close to VCAP.
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to Section 30.0 “Electrical
Characteristics” for additional information.
.
TABLE 2-1:
Make
SUITABLE CAPACITOR EQUIVALENTS (0805 CASE SIZE)
Nominal
Part #
Base Tolerance
Rated Voltage
Capacitance
TDK
TDK
C2012X5R1E106K085AC
C2012X5R1C106K085AC
C0805C106M4PACTU
GRM21BR61E106KA3L
GRM21BR61C106KE15
10 µF
10 µF
10 µF
10 µF
10 µF
±10%
±10%
±10%
±10%
±10%
25V
16V
16V
25V
16V
Kemet
Murata
Murata
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2.4.1
CONSIDERATIONS FOR CERAMIC
CAPACITORS
FIGURE 2-4:
DC BIAS VOLTAGE vs.
CAPACITANCE
CHARACTERISTICS
In recent years, large value, low-voltage, surface-mount
ceramic capacitors have become very cost effective in
sizes up to a few tens of microfarad. The low-ESR, small
physical size and other properties make ceramic
capacitors very attractive in many types of applications.
10
0
-10
-20
-30
-40
-50
-60
-70
16V Capacitor
10V Capacitor
Ceramic capacitors are suitable for use with the inter-
nal voltage regulator of this microcontroller. However,
some care is needed in selecting the capacitor to
ensure that it maintains sufficient capacitance over the
intended operating range of the application.
6.3V Capacitor
-80
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14 15
16 17
DC Bias Voltage (VDC)
Typical low-cost, 10 µF ceramic capacitors are available
in X5R, X7R and Y5V dielectric ratings (other types are
also available, but are less common). The initial tolerance
specifications for these types of capacitors are
often specified as ±10% to ±20% (X5R and X7R) or
-20%/+80% (Y5V). However, the effective capacitance
that these capacitors provide in an application circuit
will also vary based on additional factors, such as the
applied DC bias voltage and the temperature. The total
in-circuit tolerance is, therefore, much wider than the
initial tolerance specification.
When selecting a ceramic capacitor to be used with the
internal voltage regulator, it is suggested to select a
high-voltage rating so that the operating voltage is a
small percentage of the maximum rated capacitor volt-
age. For example, choose a ceramic capacitor rated at
a minimum of 16V for the 1.8V core voltage. Suggested
capacitors are shown in Table 2-1.
2.4.2
ICSP PINS
The PGCx and PGDx pins are used for In-Circuit Serial
Programming (ICSP) and debugging purposes. It is
recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom-
mended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
The X5R and X7R capacitors typically exhibit satisfac-
tory temperature stability (ex: ±15% over a wide
temperature range, but consult the manufacturer’s data
sheets for exact specifications). However, Y5V capaci-
tors typically have extreme temperature tolerance
specifications of +22%/-82%. Due to the extreme
temperature tolerance, a 10 µF nominal rated Y5V type
capacitor may not deliver enough total capacitance to
meet minimum internal voltage regulator stability and
transient response requirements. Therefore, Y5V
capacitors are not recommended for use with the
internal regulator if the application must operate over a
wide temperature range.
Pull-up resistors, series diodes and capacitors on the
PGCx and PGDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits, and pin Voltage Input High
(VIH) and Voltage Input Low (VIL) requirements.
In addition to temperature tolerance, the effective
capacitance of large value ceramic capacitors can vary
substantially, based on the amount of DC voltage
applied to the capacitor. This effect can be very signifi-
cant, but is often overlooked or is not always
documented.
For device emulation, ensure that the “Communication
Channel Select” pins (i.e., PGCx/PGDx) programmed
into the device match the physical connections for the
ICSP to the Microchip debugger/emulator tool.
A typical DC bias voltage vs. capacitance graph for
X7R type capacitors is shown in Figure 2-4.
For more information on available Microchip
development tools connection requirements, refer to
Section 29.0 “Development Support”.
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FIGURE 2-5:
SUGGESTED
2.5
External Oscillator Pins
PLACEMENT OF THE
OSCILLATOR CIRCUIT
Many microcontrollers have options for at least two
oscillators: a high-frequency Primary Oscillator and
a
low-frequency Secondary Oscillator (refer to
Single-Sided and In-Line Layouts:
Section 9.0 “Oscillator Configuration” for details).
Copper Pour
(tied to ground)
Primary Oscillator
Crystal
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins with no
more than 0.5 inch (12 mm) between the circuit com-
ponents and the pins. The load capacitors should be
placed next to the oscillator itself, on the same side of
the board.
DEVICE PINS
Primary
OSCI
OSCO
GND
Oscillator
C1
C2
`
`
Use a grounded copper pour around the oscillator
circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
traces inside the ground pour. Also, if using a two-sided
board, avoid any traces on the other side of the board
where the crystal is placed.
SOSCO
SOSCI
Secondary
Oscillator
Crystal
`
Layout suggestions are shown in Figure 2-5. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to com-
pletely surround the pins and components. A suitable
solution is to tie the broken guard sections to a mirrored
ground layer. In all cases, the guard trace(s) must be
returned to ground.
Sec Oscillator: C2
Sec Oscillator: C1
Fine-Pitch (Dual-Sided) Layouts:
Top Layer Copper Pour
(tied to ground)
In planning the application’s routing and I/O assign-
ments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times,
and other similar noise).
Bottom Layer
Copper Pour
(tied to ground)
OSCO
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate website
(www.microchip.com):
C2
Oscillator
Crystal
GND
• AN943, “Practical PICmicro® Oscillator Analysis
and Design”
C1
OSCI
• AN949, “Making Your Oscillator Work”
• AN1798, “Crystal Selection for Low-Power
Secondary Oscillator”
DEVICE PINS
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When a Microchip debugger/emulator is used as a pro-
grammer, the user application firmware must correctly
configure the ANSELx registers. Automatic initializa-
tion of these registers is only done during debugger
operation. Failure to correctly configure the register(s)
will result in all A/D pins being recognized as analog
input pins, resulting in the port value being read as a
logic ‘0’, which may affect user application functionality.
2.6
Configuration of Analog and
Digital Pins During ICSP
Operations
If an ICSP compliant emulator is selected as a debugger,
it automatically initializes all of the A/D input pins (ANx)
as “digital” pins. This is done by clearing all bits in the
ANSELx registers. Refer to Section 11.2 “Configur-
ing Analog Port Pins (ANSELx)” for more specific
information.
2.7
Unused I/Os
The bits in these registers that correspond to the A/D
pins that initialized the emulator must not be changed
by the user application firmware; otherwise, commu-
nication errors will result between the debugger and the
device.
Unused I/O pins should be configured as outputs and
driven to a logic low state. Alternatively, connect a 1 kΩ
to 10 kΩ resistor to VSS on unused pins and drive the
output to logic low.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must modify the appropriate bits during
initialization of the A/D module, as follows:
• Set the bits corresponding to the pin(s) to be
configured as analog. Do not change any other
bits, particularly those corresponding to the
PGCx/PGDx pair, at any time.
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The core supports Inherent (no operand), Relative,
Literal, Memory Direct Addressing modes along with
three groups of addressing modes. All modes support
Register Direct and various Register Indirect modes.
Each group offers up to seven addressing modes.
Instructions are associated with predefined addressing
modes depending upon their functional requirements.
3.0
CPU
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to “CPU with Extended Data
Space (EDS)” (www.microchip.com/
DS39732) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in
this data sheet supersedes the information
in the FRM.
For most instructions, the core is capable of executing
a data (or program data) memory read, a Working reg-
ister (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, three parameter instructions can be supported,
allowing trinary operations (for example, A + B = C) to
be executed in a single cycle.
The PIC24F CPU has a 16-bit (data) modified Harvard
architecture with an enhanced instruction set and a
24-bit instruction word with a variable length opcode
field. The Program Counter (PC) is 23 bits wide and
addresses up to 4M instructions of user program
memory space. A single-cycle instruction prefetch
mechanism is used to help maintain throughput and
provides predictable execution. All instructions execute
in a single cycle, with the exception of instructions that
change the program flow, the double-word move
(MOV.D) instruction and the table instructions.
Overhead-free program loop constructs are supported
using the REPEATinstructions, which are interruptible
at any point.
A high-speed, 17-bit x 17-bit multiplier has been included
to significantly enhance the core arithmetic capability and
throughput. The multiplier supports Signed, Unsigned
and Mixed mode, 16-bit x 16-bit or 8-bit x 8-bit, integer
multiplication. All multiply instructions execute in a single
cycle.
The 16-bit ALU has been enhanced with integer divide
assist hardware that supports an iterative non-restoring
divide algorithm. It operates in conjunction with the
REPEATinstruction looping mechanism and a selection
of iterative divide instructions to support 32-bit (or 16-bit),
divided by 16-bit, integer signed and unsigned division.
All divide operations require 19 cycles to complete but
are interruptible at any cycle boundary.
PIC24F devices have sixteen, 16-bit Working registers
in the programmer’s model. Each of the Working
registers can act as a Data, Address or Address Offset
register. The 16th Working register (W15) operates as
a Software Stack Pointer (SSP) for interrupts and calls.
The PIC24F has a vectored exception scheme with up
to eight sources of non-maskable traps and up to
118 interrupt sources. Each interrupt source can be
assigned to one of seven priority levels.
The lower 32 Kbytes of the Data Space (DS) can be
accessed linearly. The upper 32 Kbytes of the Data
Space are referred to as Extended Data Space (EDS),
to which the extended data RAM, EPMP memory
space or program memory can be mapped.
A block diagram of the CPU is shown in Figure 3-1.
3.1
Programmer’s Model
The programmer’s model for the PIC24F is shown in
Figure 3-2. All registers in the programmer’s model are
memory-mapped and can be manipulated directly by
instructions.
The Instruction Set Architecture (ISA) has been
significantly enhanced beyond that of the PIC18, but
maintains an acceptable level of backward compatibility.
All PIC18 instructions and addressing modes are
supported, either directly, or through simple macros.
Many of the ISA enhancements have been driven by
compiler efficiency needs.
A description of each register is provided in Table 3-1.
All registers associated with the programmer’s model
are memory-mapped.
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FIGURE 3-1:
PIC24F CPU CORE BLOCK DIAGRAM
EDS and Table
Data Access
Control Block
Data Bus
Interrupt
Controller
16
16
16
8
Data Latch
23
Data RAM
Up to 0x7FFF
16
PCH
Program Counter
PCL
23
Address
Latch
Stack
Control
Logic
Loop
Control
Logic
23
16
RAGU
WAGU
Address Latch
Program Memory/
Extended Data
Space
EA MUX
Address Bus
24
Data Latch
ROM Latch
16
16
Instruction
Decode and
Control
Instruction Reg
Control Signals
to Various Blocks
Hardware
Multiplier
16 x 16
W Register Array
Divide
Support
16
16-Bit ALU
16
To Peripheral Modules
TABLE 3-1:
CPU CORE REGISTERS
Register(s) Name
Description
W0 through W15
PC
Working Register Array
23-Bit Program Counter
ALU STATUS Register
SR
SPLIM
Stack Pointer Limit Value Register
Table Memory Page Address Register
REPEATLoop Counter Register
CPU Control Register
TBLPAG
RCOUNT
CORCON
DISICNT
DSRPAG
DSWPAG
Disable Interrupt Count Register
Data Space Read Page Register
Data Space Write Page Register
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FIGURE 3-2:
PROGRAMMER’S MODEL
15
0
W0 (WREG)
Divider Working Registers
W1
W2
Multiplier Registers
W3
W4
W5
W6
W7
Working/Address
Registers
W8
W9
W10
W11
W12
W13
W14
W15
Frame Pointer
Stack Pointer
0
0
Stack Pointer Limit
Value Register
SPLIM
22
0
PC
Program Counter
0
7
0
Table Memory Page
Address Register
TBLPAG
DSRPAG
9
0
Data Space Read Page Register
Data Space Write Page Register
8
0
0
0
DSWPAG
15
15
REPEATLoop Counter
Register
RCOUNT
SRH
SRL
IPL
— — — — — ——
DC
RA N OV Z C
1 0
ALU STATUS Register (SR)
2
15
0
— — — — — — — — — — — —
— — —
IPL3
CPU Control Register (CORCON)
Disable Interrupt Count Register
13
0
DISICNT
Registers or bits are shadowed for PUSH.Sand POP.Sinstructions.
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3.2
CPU Control Registers
REGISTER 3-1:
SR: ALU STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
DC
bit 15
bit 8
R/W-0(1)
IPL2(2)
bit 7
R/W-0(1)
IPL1(2)
R/W-0(1)
IPL0(2)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-9
bit 8
Unimplemented: Read as ‘0’
DC: ALU Half Carry/Borrow bit
1= A carry out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0= No carry out from the 4th or 8th low-order bit of the result has occurred
bit 7-5
IPL[2:0]: CPU Interrupt Priority Level Status bits(1,2)
111= CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
bit 4
bit 3
bit 2
bit 1
bit 0
RA: REPEATLoop Active bit
1= REPEATloop is in progress
0= REPEATloop is not in progress
N: ALU Negative bit
1= Result was negative
0= Result was not negative (zero or positive)
OV: ALU Overflow bit
1= Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation
0= No overflow has occurred
Z: ALU Zero bit
1= An operation, which affects the Z bit, has set it at some time in the past
0= The most recent operation, which affects the Z bit, has cleared it (i.e., a non-zero result)
C: ALU Carry/Borrow bit
1= A carry out from the Most Significant bit (MSb) of the result occurred
0= No carry out from the Most Significant bit of the result occurred
Note 1: The IPLx Status bits are read-only when NSTDIS (INTCON1[15]) = 1.
2: The IPLx Status bits are concatenated with the IPL3 Status bit (CORCON[3]) to form the CPU Interrupt
Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
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REGISTER 3-2:
CORCON: CPU CORE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
R/C-0
IPL3(1)
R/W-1
PSV(2)
U-0
—
U-0
—
bit 7
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 3
Unimplemented: Read as ‘0’
IPL3: CPU Interrupt Priority Level Status bit(1)
1= CPU Interrupt Priority Level is greater than 7
0= CPU Interrupt Priority Level is 7 or less
bit 2
PSV: Program Space Visibility (PSV) in Data Space Enable bit(2)
1= Program space is visible in Data Space
0= Program space is not visible in Data Space
bit 1-0
Unimplemented: Read as ‘0’
Note 1: The IPL3 bit is concatenated with the IPL[2:0] bits (SR[7:5]) to form the CPU Interrupt Priority Level; see
Register 3-1 for bit description.
2: If PSV = 0, any reads from data memory at 0x8000 and above will cause an address trap error instead of
reading from the PSV section of program memory. This bit is not individually addressable.
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3.3.2
DIVIDER
3.3
Arithmetic Logic Unit (ALU)
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
The PIC24F ALU is 16 bits wide and is capable of addi-
tion, subtraction, bit shifts and logic operations. Unless
otherwise mentioned, arithmetic operations are 2’s
complement in nature. Depending on the operation, the
ALU may affect the values of the Carry (C), Zero (Z),
Negative (N), Overflow (OV) and Digit Carry (DC)
Status bits in the SR register. The C and DC Status bits
operate as Borrow and Digit Borrow bits, respectively,
for subtraction operations.
• 32-bit signed/16-bit signed divide
• 32-bit unsigned/16-bit unsigned divide
• 16-bit signed/16-bit signed divide
• 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. The 16-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn), and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array, or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from theALU can be written to the W register array
or a data memory location.
The PIC24F CPU incorporates hardware support for
both multiplication and division. This includes a
dedicated hardware multiplier and support hardware
for 16-bit divisor division.
3.3.3
MULTIBIT SHIFT SUPPORT
The PIC24F ALU supports both single-bit and single-
cycle, multibit arithmetic and logic shifts. Multibit shifts
are implemented using a shifter block, capable of
performing up to a 15-bit arithmetic right shift, or up to
a 15-bit left shift, in a single cycle. All multibit shift
instructions only support Register Direct Addressing for
both the operand source and result destination.
3.3.1
MULTIPLIER
The ALU contains a high-speed, 17-bit x 17-bit
multiplier. It supports unsigned, signed or mixed sign
operation in several multiplication modes:
A full summary of instructions that use the shift
operation is provided in Table 3-2.
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
TABLE 3-2:
Instruction
INSTRUCTIONS THAT USE THE SINGLE-BIT AND MULTIBIT SHIFT OPERATION
Description
ASR
SL
Arithmetic Shift Right Source register by one or more bits.
Shift Left Source register by one or more bits.
LSR
Logical Shift Right Source register by one or more bits.
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4.1
Program Memory Space
4.0
MEMORY ORGANIZATION
The program address memory space of the
PIC24FJ128GL306 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
from either the 23-bit Program Counter (PC) during pro-
gram execution, or from table operation or Data Space
remapping, as described in Section 4.3 “Interfacing
Program and Data Memory Spaces”.
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive ref-
erence source. For more information, refer
to “PIC24F Flash Program Memory”
(www.microchip.com/DS30009715) in the
“dsPIC33/PIC24
Family
Reference
Manual”. The information in this data sheet
supersedes the information in the FRM.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG[7] to permit access to
the Configuration bits and customer OTP sections of
the configuration memory space.
As Harvard architecture devices, PIC24F micro-
controllers feature separate program and data memory
spaces and buses. This architecture also allows direct
access of program memory from the Data Space (DS)
during code execution.
The memory map for the PIC24FJ128GL306 family of
devices is shown in Figure 4-1.
2019-2020 Microchip Technology Inc.
DS30010198B-page 33
PIC24FJ128GL306 FAMILY
FIGURE 4-1:
PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GL306 DEVICES
PIC24FJ64GL30X
PIC24FJ128GL30X
GOTOInstruction
Reset Address
GOTOInstruction
Reset Address
000000h
000002h
000004h
0000FEh
000100h
Interrupt Vector Table
Interrupt Vector Table
User Flash Program Memory
(22K Instructions)
User Flash Program Memory
(44K Instructions)
Flash Config Words
00AFFEh
00B000h
Flash Config Words
015FFEh
016000h
Unimplemented
Read ‘0’
Unimplemented
Read ‘0’
7FFFFFh
800000h
Reserved
Executive Code Memory
Reserved
Reserved
Executive Code Memory
Reserved
800100h
800FFEh
801000h
8016FEh
801700h
8017FEh
801800h
OTP Memory
OTP Memory
Reserved
Reserved
F9FFFEh
FA0000h
FA00FEh
FA0100h
Flash Write Latches
Reserved
Flash Write Latches
Reserved
FEFFFEh
FF0000h
FF0004h
DEVID (2)
Reserved
DEVID (2)
Reserved
FFFFFFh
Legend: Memory areas are not shown to scale.
Note:
Exact boundary addresses are determined by the size of the implemented program memory (Table 4-1).
TABLE 4-1:
PROGRAM MEMORY SIZES AND BOUNDARIES(2)
Program Memory
Device
Upper Boundary
Write Blocks(1)
Erase Blocks(1)
(Instruction Words)
PIC24FJ128GL30X
PIC24FJ64GL30X
015FFEh (45,056 x 24)
00AFFEh (22,528 x 24)
352
176
44
22
Note 1: One Write Block = 128 Instruction Words; One Erase Block (Page) = 1024 Instruction Words.
2: To maintain integer page sizes, the memory sizes are not exactly half of each other.
DS30010198B-page 34
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.3
CONFIGURATION BITS OVERVIEW
The Configuration bits are stored in the last page loca-
tion of implemented program memory. These bits can be
set or cleared to select various device configurations.
There are two types of Configuration bits: system oper-
ation bits and code-protect bits. The system operation
bits determine the power-on settings for system-level
components, such as the oscillator and the Watchdog
Timer. The code-protect bits prevent program memory
from being read and written.
The program memory space is organized in word-
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-2).
Program memory addresses are always word-aligned
on the lower word and addresses are incremented or
decremented by two during code execution. This
arrangement also provides compatibility with data
memory space addressing and makes it possible to
access data in the program memory space.
Refer to Section 27.0 “Special Features” for the full
Configuration register description for each specific
device.
4.1.4
CODE-PROTECT CONFIGURATION
BITS
4.1.2
HARD MEMORY VECTORS
The device implements intermediate security features
defined by the FSEC register. The Boot Segment (BS)
is the higher privileged segment and the General Seg-
ment (GS) is the lower privileged segment. The total
user code memory can be split into BS or GS. The size
of the segments is determined by the BSLIM[12:0] bits.
The relative location of the segments within user space
does not change, such that BS (if present) occupies the
memory area just after the Interrupt Vector Table (IVT)
and the GS occupies the space just after the BS (or if
the Alternate IVT is enabled, just after it).
All PIC24F devices reserve the addresses between
000000h and 000200h for hard-coded program execu-
tion vectors. A hardware Reset vector is provided to
redirect code execution from the default value of the PC
on a device Reset to the actual start of code. A GOTO
instruction is programmed by the user at 000000h, with
the actual address for the start of code at 000002h.
The PIC24FJ128GL306 devices can have up to two
Interrupt Vector Tables (IVT). The first is located from
addresses, 000004h to 0000FFh. The Alternate Inter-
rupt Vector Table (AIVT) can be enabled by the AIVTDIS
Configuration bit if the Boot Segment (BS) is present. If
the user has configured a Boot Segment, the AIVT will
be located at the address: (BSLIM[12:0] – 1) x 0x800.
These vector tables allow each of the many device
interrupt sources to be handled by separate ISRs. A
more detailed discussion of the Interrupt Vector Tables is
provided in Section 8.1 “Interrupt Vector Table”.
The Configuration Segment (CS) is a small segment
(less than a page, typically just one row) within user
Flash address space. It contains all user configuration
data that are loaded by the NVM Controller during the
Reset sequence.
2019-2020 Microchip Technology Inc.
DS30010198B-page 35
PIC24FJ128GL306 FAMILY
The 16-bit wide data addresses in the data memory
space point to bytes within the Data Space (DS). This
gives a DS address range of 64 Kbytes or 32K words.
The lower half (0000h to 7FFFh) is used for
implemented (on-chip) memory addresses.
4.2
Data Memory Space
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information, refer
to “Data Memory with Extended Data
Space (EDS)” (www.microchip.com/
DS39733) in the “dsPIC33/PIC24 Family
Reference Manual”, . The information in
this data sheet supersedes the information
in the FRM.
The upper half of data memory address space (8000h to
FFFFh) is used as a window into the Extended Data
Space (EDS). This allows the microcontroller to directly
access a greater range of data beyond the standard
16-bit address range. EDS is discussed in detail in
Section 4.2.5 “Extended Data Space (EDS)”.
4.2.1
DATA SPACE WIDTH
The PIC24F core has a 16-bit wide data memory space,
addressable as a single linear range. The Data Space is
accessed using two Address Generation Units (AGUs),
one each for read and write operations. The Data Space
memory map is shown in Figure 4-2.
The data memory space is organized in byte-
addressable, 16-bit wide blocks. Data are aligned in
data memory and registers as 16-bit words, but all Data
Space EAs resolve to bytes. The Least Significant Bytes
(LSBs) of each word have even addresses, while the
Most Significant Bytes (MSBs) have odd addresses.
FIGURE 4-2:
DATA SPACE MEMORY MAP FOR PIC24FJ128GL306 DEVICES
MSB
Address
LSB
Address
MSB
LSB
0001h
0000h
SFR
Space
SFR Space
07FFh
0801h
07FEh
0800h
Near
Data Space
1FFFh
2001h
1FFEh
2000h
8 Kbytes Data RAM
Unimplemented
27FFh
2801h
27FEh
2800h
Lower 32 Kbytes
Data Space
7FFFh
8001h
7FFEh
8000h
EDS Window
Upper 32 Kbytes
Data Space
FFFFh
FFFEh
Note: Memory areas are not shown to scale.
DS30010198B-page 36
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
A Sign-Extend (SE) instruction is provided to allow users
to translate 8-bit signed data to 16-bit signed values.
Alternatively, for 16-bit unsigned data, users can clear
the MSB of any W register by executing a Zero-Extend
(ZE) instruction on the appropriate address.
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCUs and
improve Data Space memory usage efficiency, the
PIC24F instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
EA calculations are internally scaled to step through
word-aligned memory. For example, the core recognizes
that Post-Modified Register Indirect Addressing mode,
[Ws++], will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions operate only on words.
4.2.3
NEAR DATA SPACE
The 8-Kbyte area between 0000h and 1FFFh is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions. The
remainder of the Data Space is addressable indirectly.
Additionally, the whole Data Space is addressable
using MOV instructions, which support Memory Direct
Addressing with a 16-bit address field.
Data byte reads will read the complete word, which
contains the byte, using the LSB of any EA to deter-
mine which byte to select. The selected byte is placed
onto the LSB of the data path. That is, data memory
and registers are organized as two parallel, byte-wide
entities with shared (word) address decode, but
separate write lines. Data byte writes only write to the
corresponding side of the array or register which
matches the byte address.
4.2.4
SPECIAL FUNCTION REGISTER
(SFR) SPACE
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed; if it occurred on
a write, the instruction will be executed but the write will
not occur. In either case, a trap is then executed, allow-
ing the system and/or user to examine the machine
state prior to execution of the address Fault.
The first 2 Kbytes of the Near Data Space, from 0000h
to 07FFh, are primarily occupied with Special Function
Registers (SFRs). These are used by the PIC24F core
and peripheral modules for controlling the operation of
the device.
SFRs are distributed among the modules that they
control and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. Each implemented area indicates
a 32-byte region where at least one address is
implemented as an SFR. A complete list of imple-
mented SFRs, including their addresses, is shown in
Table 4-2 through Table 4-9. These tables contain all
registers applicable to the PIC24FJ128GL306 family.
Not all registers are present on all device variants. Refer
to Table 1 for peripheral availability. Refer to Table 11-3
through Table 11-9 for detailed port availability for the
different package options.
All byte loads into any W register are loaded into the
LSB. The Most Significant Byte (MSB) is not modified.
2019-2020 Microchip Technology Inc.
DS30010198B-page 37
PIC24FJ128GL306 FAMILY
TABLE 4-2:
SFR MAP: 0000h BLOCK
(1)
(2)
(1)
(2)
Register
Address
All Resets
Register
Address
All Resets
CPU Core
WREG0
Interrupt Controller (Continued)
0000h
0002h
0004h
0006h
0008h
000Ah
000Ch
000Eh
0010h
0012h
0014h
0016h
0018h
001Ah
001Ch
001Eh
0020h
002Eh
0030h
0032h
0034h
0036h
0042h
0044h
0052h
0054h
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000100000000000
xxxxxxxxxxxxxxxx
0000000000000000
--------00000000
------0000000000
-------000000000
xxxxxxxxxxxxxxxx
-------000000000
------------01--
--xxxxxxxxxxxxxx
--------00000000
IFS3
008Eh
0090h
0092h
0094h
0096h
0098h
009Ah
009Ch
009Eh
00A0h
00A2h
00A4h
00A6h
00A8h
00AAh
00ACh
00AEh
00B0h
00B2h
00B4h
00B6h
00B8h
00BAh
00BCh
00BEh
00C0h
00C2h
00C4h
00C6h
00C8h
00CAh
00CCh
00CEh
00D0h
00D2h
00D4h
00D6h
00D8h
00DAh
00DCh
00DEh
00E0h
00E2h
00E4h
000-00---00--00-
-------0----0000
00----000-00000-
-0-000----000000
----------0-----
000000000--00000
00000--0-0-00000
00-00------0--00
000-00---00--00-
-------0----0000
00----000-00000-
-0-000----000000
----------0-----
-100-100-100-100
-100---------100
-100-100-100-100
-100-100-100-100
-100-100-100-100
------100----100
-100---------100
-100-100-100-100
---------100-100
-------------100
-100------------
-100-100-----100
-----100-100----
-----100-100----
-100-100--------
-100-100-100----
-100-100-100-100
----------------
-------------100
----------------
-100-100-100----
-100-----100-100
---------100-100
-100-100--------
-100-100-100-100
---------100-100
-100-100--------
-----100-----100
----------------
---------100----
0-0-000000000000
WREG1
IFS4
WREG2
IFS5
WREG3
IFS6
WREG4
IFS7
WREG5
IEC0
WREG6
IEC1
WREG7
IEC2
WREG8
IEC3
WREG9
IEC4
WREG10
WREG11
WREG12
WREG13
WREG14
WREG15
SPLIM
IEC5
IEC6
IEC7
IPC0
IPC1
IPC2
IPC3
PCL
IPC4
PCH
IPC5
DSRPAG
DSWPAG
RCOUNT
SR
IPC6
IPC7
IPC8
IPC9
CORCON
DISICNT
TBLPAG
IPC10
IPC11
IPC12
IPC13
IPC14
IPC15
IPC16
IPC17
IPC18
IPC19
IPC20
IPC21
IPC22
IPC23
IPC24
IPC25
IPC26
IPC27
IPC28
IPC29
INTTREG
Deadman Timer
DMTCON
DMTPRECLR
DMTCLR
DMTSTAT
DMTCNTL
DMTCNTH
DMTHOLDREG
DMTPSCNTL
DMTPSCNTH
DMTPSINTVL
DMTPSINTVH
Interrupt Controller
INTCON1
INTCON2
INTCON3
INTCON4
IFS0
005Ch
0060h
0064h
0068h
006Ch
006Eh
0070h
0074h
0076h
0078h
007Ah
0000000000000000
00000000--------
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0080h
0082h
0084h
0086h
0088h
008Ah
008Ch
0----------0000-
100----0---00000
0000000000000000
--------------00
000000000--00000
00000--0-0-00000
00-00------0--00
IFS1
IFS2
Legend: x= unknown or indeterminate value; -= unimplemented bits.
Note 1: Address values are in hexadecimal.
2: Reset values are in binary.
DS30010198B-page 38
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 4-3:
SFR MAP: 0100h BLOCK
(1)
(2)
(1)
(2)
Register
Address
All Resets
Register
Address
All Resets
Oscillator and Reset
Timers (Continued)
TMR2
OSCCON
CLKDIV
OSCTUN
OSCDIV
OSCFDIV
RCON
0100h
-qqq-qqq00q00000
0011000000q-----
0000000000000000
-000000000000001
000000000-------
0010--0000000011
0196h
0198h
019Ah
019Ch
019Eh
01A0h
01A2h
01A4h
01A6h
01A8h
01AAh
01ACh
01AEh
01B0h
0000000000000000
0000000000000000
0000000000000000
1111111111111111
1111111111111111
0-0---xx-0000-0-
0-0---xx-000--0-
0000000000000000
0000000000000000
0000000000000000
1111111111111111
1111111111111111
0-0---xx-0000-0-
0-0---xx-000--0-
0102h
0106h
010Ch
010Eh
0110h
TMR3HLD
TMR3
PR2
PR3
T2CON
T3CON
TMR4
HLVD
HLVDCON
CRC
0114h
0-0-xxxx----0000
TMR5HLD
TMR5
CRCCON1
CRCCON2
CRCXORL
CRCXORH
CRCDATL
CRCDATH
CRCWDATL
CRCWDATH
REFO
0158h
015Ah
015Ch
015Eh
0160h
0162h
0164h
0166h
0-00000001x00---
---00000---00000
000000000000000-
0000000000000000
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
PR4
PR5
T4CON
T5CON
Real-Time Clock and Calendar (RTCC)
RTCCON1L
RTCCON1H
RTCCON2L
RTCCON2H
RTCCON3L
RTCSTATL
TIMEL
01CCh
01CEh
01D0h
01D2h
01D4h
01D8h
01DCh
01DEh
01E0h
01E2h
01E4h
01E6h
01E8h
01EAh
01ECh
01EEh
01F0h
01F2h
0---00000000---0
00--000000000000
10000---0000--00
0011111111111111
0000000000000000
----------0-0000
-0000000--------
--000000-0000000
--000001-----110
00000000---00001
-0000000--------
--000000-0000000
--000001-----110
00000000---00001
-0000000--------
--000000-0000000
--000000-----000
00000000---00000
REFOCONL
REFOCONH
PMD
0168h
016Ah
0-000-00----0000
-000000000000000
PMD1
0178h
017Ah
017Ch
017Eh
0180h
0182h
0184h
0186h
00000---00000--0
----------------
-----00-0---0-0-
------------000-
-----------xxxxx
---------------0
----------00----
------------00--
PMD2
TIMEH
PMD3
DATEL
PMD4
DATEH
PMD5
ALMTIMEL
ALMTIMEH
ALMDATEL
ALMDATEH
TSATIMEL
TSATIMEH
TSADATEL
TSADATEH
PMD6
PMD7
PMD8
Timers
TMR1
0190h
0192h
0194h
0000000000000000
1111111111111111
0-0---00-000-00-
PR1
T1CON
Legend: x= unknown or indeterminate value; -= unimplemented bits; q= value set by Configuration bits.
Note 1: Address values are in hexadecimal.
2: Reset values are in binary.
2019-2020 Microchip Technology Inc.
DS30010198B-page 39
PIC24FJ128GL306 FAMILY
TABLE 4-4:
SFR MAP: 0200h BLOCK
(1)
(2)
(1)
(2)
Register
Address
All Resets
Register
Address
All Resets
Multiple Output Capture/Compare/PWM
Multiple Output Capture/Compare/PWM (Continued)
CCP1CON1L
CCP1CON1H
CCP1CON2L
CCP1CON2H
CCP1CON3L
CCP1CON3H
CCP1STATL
CCP1TMRL
CCP1TMRH
CCP1PRL
026Ch
026Eh
0270h
0272h
0274h
0276h
0278h
027Ch
027Eh
0280h
0282h
0284h
0288h
028Ch
028Eh
0290h
0292h
0294h
0296h
0298h
029Ah
029Ch
02A0h
02A2h
02A4h
02A6h
02A8h
0000000000000000
0000000000000000
0000000000000000
0000000100000000
----------000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
1111111111111111
1111111111111111
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000100000000
----------000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
CCP2RBL
02ACh
02B0h
02B2h
02B4h
02B6h
02B8h
02BAh
02BCh
02BEh
02C0h
02C4h
02C6h
02C8h
02CAh
02CCh
02D0h
02D4h
02D6h
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000100000000
----------000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
CCP2BUFL
CCP2BUFH
CCP3CON1L
CCP3CON1H
CCP3CON2L
CCP3CON2H
CCP3CON3L
CCP3CON3H
CCP3STATL
CCP3TMRL
CCP3TMRH
CCP3PRL
CCP1PRH
CCP1RAL
CCP1RBL
CCP1BUFL
CCP1BUFH
CCP2CON1L
CCP2CON1H
CCP2CON2L
CCP2CON2H
CCP2CON3L
CCP2CON3H
CCP2STATL
CCP2TMRL
CCP2TMRH
CCP2PRL
CCP3PRH
CCP3RAL
CCP3RBL
CCP3BUFL
CCP3BUFH
Comparator
CMSTAT
02E6h
02E8h
02EAh
02ECh
02EEh
02F4h
0----000-----000
-----00000000000
000---0000-0--00
000---0000-0--00
000---0000-0--00
-------------000
CVRCON
CM1CON
CM2CON
CM3CON
ANCFG
CCP2PRH
CCP2RAL
Legend: x= unknown or indeterminate value; -= unimplemented bits.
Note 1: Address values are in hexadecimal.
2: Reset values are in binary.
DS30010198B-page 40
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 4-5:
SFR MAP: 0300h BLOCK
(1)
(2)
(1)
(2)
Register
Address
All Resets
Register
UART
Address
All Resets
Multiple Output Capture/Compare/PWM
CCP4CON1L
CCP4CON1H
CCP4CON2L
CCP4CON2H
CCP4CON3L
CCP4CON3H
CCP4STATL
CCP4TMRL
CCP4TMRH
CCP4PRL
0300h
0302h
0304h
0306h
0308h
030Ah
030Ch
0310h
0312h
0314h
0316h
0318h
031Ch
0320h
0322h
0324h
0326h
0328h
032Ah
032Ch
032Eh
0330h
0334h
0336h
0338h
033Ah
033Ch
0340h
0344h
0346h
0000000000000000
0000000000000000
0000000000000000
0000000100000000
----------000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000100000000
----------000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
U1MODE
U1STA
0398h
039Ah
039Ch
039Eh
03A0h
03A2h
03AEh
03B0h
03B2h
03B4h
03B6h
03B8h
03C4h
03C6h
03C8h
03CAh
03CCh
03CEh
03D0h
03D2h
03D4h
03D6h
03D8h
03DAh
0-000-0000000000
0000000100010000
x------xxxxxxxxx
-------000000000
0000000000000000
0000000000000000
0-000-0000000000
0000000100010000
x------xxxxxxxxx
-------000000000
0000000000000000
0000000000000000
0-000-0000000000
0000000100010000
x------xxxxxxxxx
-------000000000
0000000000000000
0000000000000000
0-000-0000000000
0000000100010000
x------xxxxxxxxx
-------000000000
0000000000000000
0000000000000000
U1TXREG
U1RXREG
U1BRG
U1ADMD
U2MODE
U2STA
U2TXREG
U2RXREG
U2BRG
CCP4PRH
CCP4RAL
U2ADMD
U3MODE
U3STA
CCP4RBL
CCP4BUFL
CCP4BUFH
CCP5CON1L
CCP5CON1H
CCP5CON2L
CCP5CON2H
CCP5CON3L
CCP5CON3H
CCP5STATL
CCP5TMRL
CCP5TMRH
CCP5PRL
U3TXREG
U3RXREG
U3BRG
U3ADMD
U4MODE
U4STA
U4TXREG
U4RXREG
U4BRG
U4ADMD
SPI
CCP5PRH
SPI1CON1L
SPI1CON1H
SPI1CON2L
SPI1STATL
SPI1STATH
03F4h
03F6h
03F8h
03FCh
03FEh
0-00000000000000
0000000000000000
-----------00000
---00--0001-1-00
--000000--000000
CCP5RAL
CCP5RBL
CCP5BUFL
CCP5BUFH
Legend: x= unknown or indeterminate value; -= unimplemented bits.
Note 1: Address values are in hexadecimal.
2: Reset values are in binary.
2019-2020 Microchip Technology Inc.
DS30010198B-page 41
PIC24FJ128GL306 FAMILY
TABLE 4-6:
SFR MAP: 0400h BLOCK
(1)
(2)
(1)
(2)
Register
Address
All Resets
Register
Address
All Resets
2
SPI (Continued)
SPI1BUFL
I C (Continued)
I2C1CONL
I2C1CONH
I2C1STAT
I2C1ADD
I2C1MSK
I2C2RCV
I2C2TRN
I2C2BRG
I2C2CONL
I2C2CONH
I2C2STAT
I2C2ADD
I2C2MSK
DMA
0400h
0402h
0404h
0408h
040Ah
040Ch
040Eh
0410h
0412h
0414h
0418h
041Ah
041Ch
041Eh
0420h
0424h
0426h
0428h
042Ah
0000000000000000
0000000000000000
---xxxxxxxxxxxxx
---00--0000-0-00
0-0000000-000000
0000000000000000
0000000000000000
0-00000000000000
0000000000000000
-----------00000
---00--0001-1-00
--000000--000000
0000000000000000
0000000000000000
---xxxxxxxxxxxxx
---00--0000-0-00
0-0000000-000000
0000000000000000
0000000000000000
049Ah
049Ch
049Eh
04A0h
04A2h
04A4h
04A6h
04A8h
04AAh
04ACh
04AEh
04B0h
04B2h
0-01000000000000
---------0000000
000--00000000000
------0000000000
------0000000000
--------00000000
--------11111111
0000000000000000
0-01000000000000
---------0000000
000--00000000000
------0000000000
------0000000000
SPI1BUFH
SPI1BRGL
SPI1IMSKL
SPI1IMSKH
SPI1URDTL
SPI1URDTH
SPI2CON1L
SPI2CON1H
SPI2CON2L
SPI2STATL
SPI2STATH
SPI2BUFL
SPI2BUFH
SPI2BRGL
SPI2IMSKL
SPI2IMSKH
SPI2URDTL
SPI2URDTH
DMACON
DMABUF
DMAL
04C4h
04C6h
04C8h
04CAh
04CCh
04CEh
04D0h
04D2h
04D4h
04D6h
04D8h
04DAh
04DCh
04DEh
04E0h
04E2h
04E4h
04E6h
04E8h
04EAh
04ECh
04EEh
04F0h
04F2h
04F4h
04F6h
04F8h
04FAh
04FCh
04FEh
0--------------0
0000000000000000
0000000000000000
0000000000000000
---0-00000000000
0000000000000--0
0000000000000000
0000000000000000
0000000000000001
---0-00000000000
0000000000000--0
0000000000000000
0000000000000000
0000000000000001
---0-00000000000
0000000000000--0
0000000000000000
0000000000000000
0000000000000001
---0-00000000000
0000000000000--0
0000000000000000
0000000000000000
0000000000000001
---0-00000000000
0000000000000--0
0000000000000000
0000000000000000
0000000000000001
---0-00000000000
DMAH
DMACH0
DMAINT0
DMASRC0
DMADST0
DMACNT0
DMACH1
DMAINT1
DMASRC1
DMADST1
DMACNT1
DMACH2
DMAINT2
DMASRC2
DMADST2
DMACNT2
DMACH3
DMAINT3
DMASRC3
DMADST3
DMACNT3
DMACH4
DMAINT4
DMASRC4
DMADST4
DMACNT4
DMACH5
Configurable Logic Cell (CLC)
CLC1CONL
CLC1CONH
CLC1SEL
0464h
0466h
0468h
046Ch
046Eh
0470h
0472h
0474h
0478h
047Ah
047Ch
047Eh
0480h
0484h
0486h
0488h
048Ah
048Ch
0490h
0492h
0---00--000--000
------------0000
-000-000-000-000
0000000000000000
0000000000000000
0---00--000--000
------------0000
-000-000-000-000
0000000000000000
0000000000000000
0---00--000--000
------------0000
-000-000-000-000
0000000000000000
0000000000000000
0---00--000--000
------------0000
-000-000-000-000
0000000000000000
0000000000000000
CLC1GLSL
CLC1GLSH
CLC2CONL
CLC2CONH
CLC2SELL
CLC2GLSL
CLC2GLSH
CLC3CONL
CLC3CONH
CLC3SELL
CLC3GLSL
CLC3GLSH
CLC4CONL
CLC4CONH
CLC4SELL
CLC4GLSL
CLC4GLSH
2
I C
I2C1RCV
I2C1TRN
I2C1BRG
0494h
0496h
0498h
--------00000000
--------11111111
0000000000000000
Legend: x= unknown or indeterminate value; -= unimplemented bits.
Note 1: Address values are in hexadecimal.
2: Reset values are in binary.
DS30010198B-page 42
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 4-7:
SFR MAP: 0500h BLOCK
(1)
(2)
(1)
(2)
Register
Address
All Resets
Register
Address
All Resets
DMA (Continued)
DMAINT5
LCD (Continued)
LCDSE2
0500h
0502h
0504h
0506h
0000000000000--0
0000000000000000
0000000000000000
0000000000000001
058Ah
058Ch
058Eh
0590h
0592h
0594h
0596h
0598h
059Ah
059Ch
059Eh
05A0h
05A2h
05A4h
05A6h
05A8h
05AAh
05ACh
05AEh
05B0h
05B2h
05B4h
05B6h
05B8h
05BAh
05BCh
05BEh
05C0h
05C2h
05C4h
05C6h
05C8h
05CAh
05CCh
05CEh
05D0h
05D2h
05D4h
05D6h
05D8h
05DAh
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
0-------------00
0000000000000000
0000000000000000
0000000000000001
0000000000000001
0000000000000001
0000000000000001
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
DMASRC5
DMADST5
DMACNT5
LCD
LCDSE3
LCDREG
LCDACTRL
LCDASTAT
LCDCON
0540h
0542h
0544h
0546h
0548h
054Ah
054Ch
054Eh
0550h
0552h
0554h
0556h
0558h
055Ah
055Ch
055Eh
0560h
0562h
0564h
0566h
0568h
056Ah
056Ch
056Eh
0570h
0572h
0574h
0576h
0578h
057Ah
057Ch
057Eh
0580h
0582h
0584h
0586h
0588h
0000000000000000
0000000000000000
0000000000000000
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
LCDFC0
LCDREF
LCDFC1
LCDPS
LCDFC2
LCDDATA0
LCDDATA1
LCDDATA2
LCDDATA3
LCDDATA4
LCDDATA5
LCDDATA6
LCDDATA7
LCDDATA8
LCDDATA9
LCDDATA10
LCDDATA11
LCDDATA12
LCDDATA13
LCDDATA14
LCDDATA15
LCDDATA16
LCDDATA17
LCDDATA18
LCDDATA19
LCDDATA20
LCDDATA21
LCDDATA22
LCDDATA23
LCDDATA24
LCDDATA25
LCDDATA26
LCDDATA27
LCDDATA28
LCDDATA29
LCDDATA30
LCDDATA31
LCDSE0
LCDTEVNT
LCDSDATA0
LCDSDATA1
LCDSDATA2
LCDSDATA3
LCDSDATA4
LCDSDATA5
LCDSDATA6
LCDSDATA7
LCDSDATA8
LCDSDATA9
LCDSDATA10
LCDSDATA11
LCDSDATA12
LCDSDATA13
LCDSDATA14
LCDSDATA15
LCDSDATA16
LCDSDATA17
LCDSDATA18
LCDSDATA19
LCDSDATA20
LCDSDATA21
LCDSDATA22
LCDSDATA23
LCDSDATA24
LCDSDATA25
LCDSDATA26
LCDSDATA27
LCDSDATA28
LCDSDATA29
LCDSDATA30
LCDSDATA31
LCDSE1
Legend: x= unknown or indeterminate value; -= unimplemented bits.
Note 1: Address values are in hexadecimal.
2: Reset values are in binary.
2019-2020 Microchip Technology Inc.
DS30010198B-page 43
PIC24FJ128GL306 FAMILY
TABLE 4-8:
SFR MAP: 0600h BLOCK
(1)
(2)
(1)
(2)
Register
Address
All Resets
Register
ODCD
Address
All Resets
I/O
06A2h
06A4h
06A6h
06A8h
06AAh
06ACh
06AEh
----000000000000
----11--11------
----000000000000
----000000000000
----000000000000
----000000000000
----000000000000
PADCON
IOCSTAT
PORTA
TRISA
065Ch
065Eh
0---------------
----------000000
ANSELD
IOCPD
IOCND
IOCFD
IOCPUD
IOCPDD
PORTE
TRISE
0660h
0662h
0664h
0666h
0668h
066Ah
066Ch
066Eh
0670h
0672h
---------------1
---------------0
---------------0
---------------0
---------------1
---------------0
---------------0
---------------0
---------------0
---------------0
PORTA
LATA
ODCA
ANSELA
IOCPA
IOCNA
IOCFA
IOCPUA
IOCPDA
PORTB
TRISB
06B0h
06B2h
06B4h
06B6h
06B8h
06BAh
06BCh
06BEh
06C0h
06C2h
--------11111111
--------00000000
--------00000000
--------00000000
-----------1111-
--------00000000
--------00000000
--------00000000
--------00000000
--------00000000
PORTE
LATE
ODCE
ANSELE
IOCPE
IOCNE
IOCFE
IOCPUE
IOCPDE
PORTF
TRISF
0674h
0676h
0678h
067Ah
067Ch
067Eh
0680h
0682h
0684h
0686h
1111111111111111
0000000000000000
0000000000000000
0000000000000000
1111111111111111
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
PORTB
LATB
ODCB
ANSELB
IOCPB
IOCNB
IOCFB
IOCPUB
IOCPDB
PORTC
TRISC
PORTC
LATC
06C4h
06C6h
06C8h
06CAh
---------1111111
---------0000000
---------0000000
---------0000000
----------------
---------0000000
---------0000000
---------0000000
---------0000000
---------0000000
PORTF
LATF
ODCF
ANSELF
IOCPF
IOCNF
IOCFF
06CCH
06CEh
06D0h
06D2h
06D4h
06D6h
0688h
068Ah
068Ch
068Eh
0690h
0692h
0694h
0696h
0698h
069Ah
1111------------
0000------------
0000------------
0000------------
1111------------
0000------------
0000------------
0000------------
0000------------
0000------------
IOCPUF
IOCPDF
PORTG
TRISG
PORTG
LATG
ODCC
ANSELC
IOCPC
IOCNC
IOCFC
IOCPUC
IOCPDC
PORTD
TRISD
PORTD
LATD
06D8h
06DAh
06DCh
06DEh
06E0h
06E2h
06E4h
06E6h
06E8h
06EAh
------1111--11--
------0000--00--
------0000--00--
------0000--00--
------1111------
------0000--00--
------0000--00--
------0000--00--
------0000--00--
------0000--00--
ODCG
ANSELG
IOCPG
IOCNG
IOCFG
IOCPUF
IOCPDG
069Ch
069Eh
06A0h
----111111111111
----000000000000
----000000000000
Legend: x= unknown or indeterminate value; -= unimplemented bits.
Note 1: Address values are in hexadecimal.
2: Reset values are in binary.
DS30010198B-page 44
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 4-9:
SFR MAP: 0700h BLOCK
(1)
(2)
(1)
(2)
Register
Address
All Resets
Register
Peripheral Pin Select (PPS)
0790h
Address
All Resets
ADC
ADC1BUF0
ADC1BUF1
ADC1BUF2
ADC1BUF3
ADC1BUF4
ADC1BUF5
ADC1BUF6
ADC1BUF7
ADC1BUF8
ADC1BUF9
ADC1BUF10
ADC1BUF11
ADC1BUF12
ADC1BUF13
ADC1BUF14
ADC1BUF15
ADC1BUF16
AD1CON1
AD1CON2
AD1CON3
AD1CHS
0700h
0702h
0704h
0706h
0708h
070Ah
070Ch
070Eh
0710h
0712h
0714h
0716h
0718h
071Ah
071Ch
071Eh
0720h
0734h
0736h
0738h
073Ah
073Ch
073Eh
0740h
0742h
0744h
0746h
074Ch
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
0-0000000000-000
000000--00000000
0000000000000000
0000000000000000
-000------------
0000000000000000
-------------000
0000--00----0000
0000000000000000
0000000000000000
xxxxxxxxxxxxxxxx
RPINR0
RPINR1
RPINR2
RPINR3
RPINR4
RPINR5
RPINR6
RPINR11
RPINR12
RPINR13
RPINR14
RPINR17
RPINR18
RPINR19
RPINR20
RPINR21
RPINR22
RPINR23
RPINR25
RPINR26
RPINR27
RPOR0
--111111--------
--111111--111111
----------111111
--xxxxxx--111111
--111111--111111
--111111--111111
--111111--111111
--111111--111111
--111111--111111
--111111--111111
----------111111
--111111--------
--111111--111111
--111111--111111
--111111--111111
--111111--111111
--111111--111111
--111111--111111
--111111--111111
--111111--111111
--111111--111111
-0000000-0000000
-0000000-0000000
-0000000-0000000
-0000000-0000000
-0000000-0000000
-0000000-0000000
-0000000-0000000
-0000000-0000000
-0000000-0000000
-0000000-0000000
-0000000-0000000
-0000000-0000000
-0000000-0000000
-0000000-0000000
-0000000-0000000
-0000000-0000000
0792h
0794h
0796h
0798h
079Ah
079Ch
07A6h
07A8h
07AAh
07ACh
07B2h
07B4h
07B6h
07B8h
07BAh
07BCh
07BEh
07C2h
07C4h
07C6h
07D4h
07D6h
07D8h
07DAh
07DCh
07DEh
07E0h
07E2h
07E4h
07E6h
07E8h
07EAh
07ECh
07EEh
07F0h
07F2h
AD1CSSH
AD1CSSL
AD1CON4
AD1CON5
AD1CHITH
AD1CHITL
AD1RESDMA
NVM
RPOR1
RPOR2
RPOR3
RPOR4
RPOR5
RPOR6
RPOR7
NVMCON
0760h
0762h
0764h
0766h
000000------0000
0000000000000000
--------00000000
--------00000000
RPOR8
NVMADR
RPOR9
NVMADRU
NVMKEY
RPOR10
RPOR11
RPOR12
RPOR13
RPOR14
RPOR15
ECC
ECCCONL
ECCCONH
ECCADDRL
ECCADDRH
ECCSTATL
ECCSTATH
076Ch
076Eh
0770h
0772h
0774h
0776h
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
Legend: x= unknown or indeterminate value; -= unimplemented bits.
Note 1: Address values are in hexadecimal.
2: Reset values are in binary.
2019-2020 Microchip Technology Inc.
DS30010198B-page 45
PIC24FJ128GL306 FAMILY
particular EDS page is selected through the Data
Space Read Page register (DSRPAG) or the Data
Space Write Page register (DSWPAG). For PSV, only
the DSRPAG register is used. The combination of the
DSRPAG register value and the 16-bit wide data
address forms a 24-bit Effective Address (EA).
4.2.5
EXTENDED DATA SPACE (EDS)
The Extended Data Space (EDS) allows PIC24F
devices to address a much larger range of data than
would otherwise be possible with a 16-bit address
range.
EDS allows read access to the program memory
space. This feature is called Program Space Visibility
(PSV) and is discussed in detail in Section 4.3.3
“Reading Data from Program Memory Using EDS”.
Note:
Accessing Page 0 in the EDS window will
generate an address error trap as Page 0
is the base data memory (data locations,
0800h to 7FFFh, in the lower Data Space).
Figure 4-3 displays the entire EDS space. The EDS is
organized as pages, called EDS pages, with one page
equal to the size of the EDS window (32 Kbytes). A
FIGURE 4-3:
EXTENDED DATA SPACE
0000h
Special
Function
Registers
0800h
Internal
Data
Memory
Space
047FEh
04800h
Unimplemented
EDS Pages
8000h
000000h
7F8000h
000001h
7F8001h
32-Kbyte
EDS
Window
Program
Space
Access
(Lower
Word)
Program
Space
Access
(Lower
Word)
Program
Space
Access
(Upper
Word)
Program
Space
Access
(Upper
Word)
007FFEh
FFFEh
7FFFFEh
007FFFh
7FFFFFh
DSRPAG
= 200h
DSRPAG
= 2FFh
DSRPAG
= 300h
DSRPAG
= 3FFh
Program Memory
DS30010198B-page 46
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
4.2.6
SOFTWARE STACK
4.3
Interfacing Program and Data
Memory Spaces
Apart from its use as a Working register, the W15
register in PIC24F devices is also used as a Software
Stack Pointer (SSP). The pointer always points to the
first available free word and grows from lower to higher
addresses. It pre-decrements for stack pops and post-
increments for stack pushes, as shown in Figure 4-4.
Note that for a PC push during any CALL instruction,
the MSB of the PC is zero-extended before the push,
ensuring that the MSB is always clear.
The PIC24F architecture uses a 24-bit wide program
space and 16-bit wide Data Space. The architecture is
also a modified Harvard scheme, meaning that data
can also be present in the program space. To use these
data successfully, they must be accessed in a way that
preserves the alignment of information in both spaces.
Aside from normal execution, the PIC24F architecture
provides two methods by which program space can be
accessed during operation:
Note:
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
• Using table instructions to access individual bytes
or words anywhere in the program space
The Stack Pointer Limit Value register (SPLIM), associ-
ated with the Stack Pointer, sets an upper address
boundary for the stack. SPLIM is uninitialized at Reset.
As is the case for the Stack Pointer, SPLIM[0] is forced
to ‘0’ as all stack operations must be word-aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is com-
pared with the value in SPLIM. If the contents of the
Stack Pointer (W15) and the SPLIM register are equal,
and a push operation is performed, a stack error trap
will not occur. The stack error trap will occur on a
subsequent push operation. Thus, for example, if it is
desirable to cause a stack error trap when the stack
grows beyond address 2000h in RAM, initialize the
SPLIM with the value, 1FFEh.
• Remapping a portion of the program space into
the Data Space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This makes the
method ideal for accessing data tables that need to be
updated from time to time. It also allows access to all
bytes of the program word. The remapping method
allows an application to access a large block of data on
a read-only basis, which is ideal for look-ups from a
large table of static data. It can only access the least
significant word of the program word.
4.3.1
ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0800h. This prevents the stack from
interfering with the SFR space.
For table operations, the 8-bit Table Memory Page
Address register (TBLPAG) is used to define a 32K word
region within the program space. This is concatenated
with a 16-bit EA to arrive at a full 24-bit program space
address. In this format, the MSBs of TBLPAG are
used to determine if the operation occurs in the user
memory (TBLPAG[7] = 0) or the configuration memory
(TBLPAG[7] = 1).
Awrite to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-4:
CALLSTACK FRAME
0000h
15
0
For remapping operations, the 10-bit Extended Data
Space Read register (DSRPAG) is used to define a
16K word page in the program space. When the Most
Significant bit (MSb) of the EA is ‘1’, and the MSb (bit 9)
of DSRPAG is ‘1’, the lower 8 bits of DSRPAG are
concatenated with the lower 15 bits of the EA to form a
23-bit program space address. The DSRPAG[8] bit
decides whether the lower word (when the bit is ‘0’) or
the higher word (when the bit is ‘1’) of program memory
is mapped. Unlike table operations, this strictly limits
remapping operations to the user memory area.
PC[15:0]
000000000
W15 (before CALL)
PC[22:16]
[Free Word]
W15 (after CALL)
POP : [--W15]
PUSH: [W15++]
Table 4-10 and Figure 4-5 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P[23:0] refers to a program
space word, whereas D[15:0] refers to a Data Space
word.
2019-2020 Microchip Technology Inc.
DS30010198B-page 47
PIC24FJ128GL306 FAMILY
TABLE 4-10: PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
[23]
[22:16]
[15]
[14:1]
[0]
Instruction Access
(Code Execution)
User
User
0
PC[22:1]
0
0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT
(Byte/Word Read/Write)
TBLPAG[7:0]
Data EA[15:0]
xxxx xxxx xxxx xxxx
Data EA[15:0]
0xxx xxxx
TBLPAG[7:0]
1xxx xxxx
Configuration
xxxx xxxx xxxx xxxx
Program Space Visibility User
(Block Remap/Read)
0
0
DSRPAG[7:0](2)
Data EA[14:0](1)
xxxx xxxx
xxx xxxx xxxx xxxx
Note 1: Data EA[15] is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is DSRPAG[0].
2: DSRPAG[9] is always ‘1’ in this case. DSRPAG[8] decides whether the lower word or higher word of
program memory is read. When DSRPAG[8] is ‘0’, the lower word is read, and when it is ‘1’, the higher
word is read.
FIGURE 4-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter
0
Program Counter
23 Bits
0
EA
1/0
(2)
1/0
TBLPAG
8 Bits
Table Operations
16 Bits
24 Bits
Select
1
1/0
EA
(1)
Program Space Visibility
(Remapping)
0
DSRPAG[7:0]
8 Bits
1-Bit
15 Bits
23 Bits
User/Configuration
Space Select
Byte Select
Note 1: DSRPAG[8] acts as word select. DSRPAG[9] should always be ‘1’ to map program memory to data memory.
2: The instructions, TBLRDH/TBLWTH/TBLRDL/TBLWTL, decide if the higher or lower word of program memory is
accessed. TBLRDH/TBLWTHinstructions access the higher word and TBLRDL/TBLWTLinstructions access the
lower word. Table Read operations are permitted in the configuration memory space.
DS30010198B-page 48
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
2. TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
(P[23:16]) to a data address. Note that D[15:8],
the ‘phantom’ byte, will always be ‘0’.
4.3.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going through
Data Space. The TBLRDHand TBLWTHinstructions are
the only method to read or write the upper eight bits of a
program space word as data.
In Byte mode, it maps the upper or lower byte of
the program word to D[7:0] of the data address,
as above. Note that the data will always be ‘0’
when the upper ‘phantom’ byte is selected (byte
select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are described in Section 6.0 “Flash
Program Memory”.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to Data Space addresses.
Program memory can thus be regarded as two, 16-bit
word-wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word, and TBLRDHand TBLWTHaccess the space
which contains the upper data byte.
For all table operations, the area of program memory
space to be accessed is determined by the Table
Memory Page Address (TBLPAG) register. TBLPAG
covers the entire program memory space of the
device, including user and configuration spaces. When
TBLPAG[7] = 0, the table page is located in the user
memory space. When TBLPAG[7] = 1, the page is
located in configuration space.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
1. TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space
location (P[15:0]) to a data address (D[15:0]).
Note:
Only Table Read operations will execute
in the configuration memory space where
Device IDs are located. Table Write
operations are not allowed.
In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when byte select is ‘1’; the lower byte
is selected when it is ‘0’.
FIGURE 4-6:
ACCESS PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
Data EA[15:0]
23
15
0
000000h
23
16
8
0
00000000
00000000
00000000
00000000
020000h
030000h
‘Phantom’ Byte
TBLRDH.B (Wn[0] = 0)
TBLRDL.B (Wn[0] = 1)
TBLRDL.B (Wn[0] = 0)
TBLRDL.W
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
800000h
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Table 4-11 provides the corresponding 23-bit EDS
address for program memory with EDS page and
source addresses.
4.3.3
READING DATA FROM PROGRAM
MEMORY USING EDS
The upper 32 Kbytes of Data Space may optionally be
mapped into any 16K word page of the program space.
This provides transparent access of stored constant
data from the Data Space without the need to use
special instructions (i.e., TBLRDL/H).
For operations that use PSV and are executed outside a
REPEATloop, the MOVand MOV.Dinstructions will require
one instruction cycle in addition to the specified execution
time. All other instructions will require two instruction
cycles in addition to the specified execution time.
Program space access through the Data Space occurs
when the MSb of EA is ‘1’ and the DSRPAG[9] bit is
also ‘1’. The lower eight bits of DSRPAG are concate-
nated to the Wn[14:0] bits to form a 23-bit EA to access
program memory. The DSRPAG[8] decides which word
should be addressed; when the bit is ‘0’, the lower
word, and when ‘1’, the upper word of the program
memory is accessed.
For operations that use PSV, which are executed inside
a REPEAT loop, there will be some instances that
require two instruction cycles in addition to the
specified execution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
The entire program memory is divided into 512 EDS
pages, from 200h to 3FFh, each consisting of 16K words
of data. Pages, 200h to 2FFh, correspond to the lower
words of the program memory, while 300h to 3FFh
correspond to the upper words of the program memory.
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction accessing data, using PSV, to execute in a
single cycle.
Using this EDS technique, the entire program memory
can be accessed. Previously, the access to the upper
word of the program memory was not supported.
TABLE 4-11: EDS PROGRAM ADDRESS WITH DIFFERENT PAGES AND ADDRESSES
DSRPAG
(Data Space Read Register)
Source Address while
Indirect Addressing
23-Bit EA Pointing
to EDS
Comment
200h
000000h to 007FFEh Lower words of 4M program
•
•
•
•
•
•
instructions (8 Mbytes) for
read operations only.
2FFh
7F8000h to 7FFFFEh
300h
8000h to FFFFh
000001h to 007FFFh Upper words of 4M program
•
•
•
•
•
•
instructions (4 Mbytes remaining;
4 Mbytes are phantom bytes) for
read operations only.
3FFh
7F8001h to 7FFFFFh
000h
Invalid Address
Address error trap.(1)
Note 1: When the source/destination address is above 8000h and DSRPAG/DSWPAG is ‘0’, an address error trap
will occur.
EXAMPLE 4-1:
EDS READ CODE FROM PROGRAM MEMORY IN ASSEMBLY
; Set the EDS page from where the data to be read
mov
mov
mov
bset
#0x0202, w0
w0, DSRPAG
#0x000A, w1
w1, #15
;page 0x202, consisting lower words, is selected for read
;select the location (0x0A) to be read
;set the MSB of the base address, enable EDS mode
;Read a byte from the selected location
mov.b
mov.b
[w1++], w2
[w1++], w3
;read Low byte
;read High byte
;Read a word from the selected location
mov
[w1], w2
;
;Read Double - word from the selected location
mov.d [w1], w2 ;two word read, stored in w2 and w3
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FIGURE 4-7:
PROGRAM SPACE VISIBILITY OPERATION TO ACCESS LOWER WORD
When DSRPAG[9:8] = 10and EA[15] = 1:
Program Space
Data Space
DSRPAG
202h
23
15
0
000000h
0000h
8000h
FFFFh
Data EA[14:0]
010000h
017FFEh
The data in the page
designatedbyDSRPAG
are mapped into the
upper half of the data
memory space....
EDS Window
... while the lower
15 bits of the EA
specify an exact
address within the
EDS area. This corre-
sponds exactly to the
same lower 15 bits of
the actual program
space address.
7FFFFEh
FIGURE 4-8:
PROGRAM SPACE VISIBILITY OPERATION TO ACCESS UPPER WORD
When DSRPAG[9:8] = 11and EA[15] = 1:
Program Space
Data Space
DSRPAG
302h
23
15
0
000000h
0000h
Data EA[14:0]
010001h
017FFFh
The data in the page
designated by DSRPAG
are mapped into the
upper half of the data
memory space....
8000h
EDS Window
... while the lower
15 bits of the EA
specify an exact
address within the
EDS area. This corre-
sponds exactly to the
same lower 15 bits of
the actual program
space address.
FFFFh
7FFFFEh
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NOTES:
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The controller also monitors CPU instruction process-
ing directly, allowing it to be aware of when the CPU
requires access to peripherals on the DMA bus and
automatically relinquishing control to the CPU as
needed. This increases the effective bandwidth for
handling data without DMA operations causing a
processor Stall. This makes the controller essentially
transparent to the user.
5.0
DIRECT MEMORY ACCESS
CONTROLLER (DMA)
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. To complement the infor-
mation in this data sheet, refer to “Direct
Memory Access Controller (DMA)”
(www.microchip.com/DS30009742) in the
“dsPIC33/PIC24 Family Reference Man-
ual”. The information in this data sheet
supersedes the information in the FRM.
The DMA Controller has these features:
• Six Independent and Independently
Programmable Channels
• Concurrent Operation with the CPU (no DMA
caused Wait states)
The Direct Memory Access (DMA) Controller is designed
to service high throughput data peripherals operating on
the SFR bus, allowing them to access data memory
directly and alleviating the need for CPU-intensive man-
agement. By allowing these data-intensive peripherals to
share their own data path, the main data bus is also
deloaded, resulting in additional power savings.
• DMA Bus Arbitration
• Five Programmable Address modes
• Four Programmable Transfer modes
• Four Flexible Internal Data Transfer modes
• Byte or Word Support for Data Transfer
• 16-Bit Source and Destination Address Register
for Each Channel, Dynamically Updated and
Reloadable
The DMA Controller functions both as a peripheral and a
direct extension of the CPU. It is located on the micro-
controller data bus, between the CPU and DMA-enabled
peripherals, with direct access to SRAM. This partitions
the SFR bus into two buses, allowing the DMA Controller
access to the DMA-capable peripherals located on the
new DMA SFR bus. The controller serves as a Master
device on the DMA SFR bus, controlling data flow from
DMA-capable peripherals.
• 16-Bit Transaction Count Register, Dynamically
Updated and Reloadable
• Upper and Lower Address Limit Registers
• Counter Half-Full Level Interrupt
• Software Triggered Transfer
• Null Write mode for Symmetric Buffer Operations
A simplified block diagram of the DMA Controller is
shown in Figure 5-1.
FIGURE 5-1:
DMA FUNCTIONAL BLOCK DIAGRAM
CPU Execution Monitoring
To DMA-Enabled
Peripherals
To I/O Ports
and Peripherals
DMACON
DMAH
Control
Logic
DMAL
DMABUF
Data
Bus
DMACH0
DMAINT0
DMASRC0
DMADST0
DMACNT0
DMACH1
DMAINT1
DMASRC1
DMADST1
DMACNT1
DMACH4
DMACH5
DMAINT5
DMASRC5
DMADST5
DMACNT5
DMAINT4
DMASRC4
DMADST4
DMACNT4
Channel 0
Channel 1
Channel 4
Channel 5
Data RAM
Data RAM
Address Generation
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5.1.4
TRANSFER MODE
5.1
Summary of DMA Operations
The DMA Controller supports four types of data
transfers, based on the volume of data to be moved for
each trigger.
The DMA Controller is capable of moving data between
addresses according to a number of different parameters.
Each of these parameters can be independently
configured for any transaction; in addition, any or all of
the DMA channels can independently perform a differ-
ent transaction at the same time. Transactions are
classified by these parameters:
• One-Shot: A single transaction occurs for each
trigger.
• Continuous: A series of back-to-back transactions
occur for each trigger; the number of transactions
is determined by the DMACNTn transaction
counter.
• Source and destination (SFRs and data RAM)
• Data size (byte or word)
• Repeated One-Shot: A single transaction is
performed repeatedly, once per trigger, until the
DMA channel is disabled.
• Trigger source
• Transfer mode (One-Shot, Repeated or
Continuous)
• Repeated Continuous: A series of transactions
are performed repeatedly, one cycle per trigger,
until the DMA channel is disabled.
• Addressing modes (Fixed Address or Address
Blocks, with or without Address Increment/
Decrement)
All transfer modes allow the option to have the source
and destination addresses, and counter value, auto-
matically reloaded after the completion of a transaction.
Repeated mode transfers do this automatically.
In addition, the DMA Controller provides channel priority
arbitration for all channels.
5.1.1
SOURCE AND DESTINATION
Using the DMA Controller, data may be moved between
any two addresses in the Data Space. The SFR space
(0000h to 07FFh), or the data RAM space (0800h to
FFFFh), can serve as either the source or the destina-
tion. Data can be moved between these areas in either
direction or between addresses in either area. The four
different combinations are shown in Figure 5-2.
5.1.5
ADDRESSING MODES
The DMA Controller also supports transfers between
single addresses or address ranges. The four basic
options are:
• Fixed-to-Fixed: Between two constant addresses
• Fixed-to-Block: From a constant source address
to a range of destination addresses
If it is necessary to protect areas of data RAM, the DMA
Controller allows the user to set upper and lower address
boundaries for operations in the Data Space above the
SFR space. The boundaries are set by the DMAH and
DMAL Limit registers. If a DMA channel attempts an
operation outside of the address boundaries, the
transaction is terminated and an interrupt is generated.
• Block-to-Fixed: From a range of source addresses
to a single, constant destination address
• Block-to-Block: From a range of source
addresses to a range of destination addresses
The option to select auto-increment or auto-decrement
of source and/or destination addresses is available for
Block Addressing modes.
5.1.2
DATA SIZE
In addition to the four basic modes, the DMA Controller
also supports Peripheral Indirect Addressing (PIA)
mode, where the source or destination address is gen-
erated jointly by the DMA Controller and a PIA-capable
peripheral. When enabled, the DMA channel provides
a base source and/or destination address, while the
peripheral provides a fixed range offset address.
The DMA Controller can handle both 8-bit and 16-bit
transactions. Size is user-selectable using the SIZE bit
(DMACHn[1]). By default, each channel is configured
for word-sized transactions. When byte-sized transac-
tions are chosen, the LSb of the source and/or
destination address determines if the data represent
the upper or lower byte of the data RAM location.
For PIC24FJ128GL306 family devices, the 12-bit A/D
Converter module is the only PIA-capable peripheral.
Details for its use in PIA mode are provided in
Section 22.0 “12-Bit A/D Converter with Threshold
Detect”.
5.1.3
TRIGGER SOURCE
The DMA Controller can use any one of the device’s
interrupt sources to initiate a transaction. The DMA
trigger sources are listed in reverse order of their
natural interrupt priority and are shown in Table 5-1.
Since the source and destination addresses for any
transaction can be programmed independently of the
trigger source, the DMA Controller can use any trigger
to perform an operation on any peripheral. This also
allows DMA channels to be cascaded to perform more
complex transfer operations.
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FIGURE 5-2:
TYPES OF DMA DATA TRANSFERS
Peripheral to Memory
SFR Area
Memory to Peripheral
SFR Area
DMASRCn
DMADSTn
07FFh
0800h
07FFh
0800h
Data RAM
Data RAM
DMAL
DMAL
DMA RAM Area
DMA RAM Area
DMADSTn
DMAH
DMASRCn
DMAH
Peripheral to Peripheral
SFR Area
Memory to Memory
SFR Area
DMASRCn
DMADSTn
07FFh
0800h
07FFh
0800h
Data RAM
Data RAM
DMAL
DMAL
DMAH
DMA RAM Area
DMA RAM Area
DMASRCn
DMADSTn
DMAH
Note: Relative sizes of memory areas are not shown to scale.
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5.1.6
CHANNEL PRIORITY
5.3
Peripheral Module Disable
Each DMA channel functions independently of the
others, but also competes with the others for access to
the data and DMA buses. When access collisions
occur, the DMA Controller arbitrates between the
channels using a user-selectable priority scheme. Two
schemes are available:
Unlike other peripheral modules, the channels of the
DMA Controller cannot be individually powered down
using the Peripheral Module Disable (PMD) registers.
Instead, the channels are controlled as two groups. The
DMA0MD bit (PMD7[4]) selectively controls DMACH0
through DMACH3. The DMA1MD bit (PMD7[5])
controls DMACH4 and DMACH5. Setting both bits
effectively disables the DMA Controller.
• Round-Robin: When two or more channels
collide, the lower numbered channel receives
priority on the first collision. On subsequent colli-
sions, the higher numbered channels each
receive priority, based on their channel number.
5.4
DMA Registers
The DMA Controller uses a number of registers to con-
trol its operation. The number of registers depends on
the number of channels implemented for a particular
device.
• Fixed: When two or more channels collide, the
lowest numbered channel always receives
priority, regardless of past history; however, any
channel being actively processed is not available
for an immediate retrigger. If a higher priority
channel is continually requesting service, it will be
scheduled for service after the next lower priority
channel with a pending request.
There are always four module-level registers (one
control and three buffer/address):
• DMACON: DMA Engine Control Register
(Register 5-1)
• DMAH and DMAL: DMA High and Low Address
Limit Registers
5.2
Typical Setup
• DMABUF: DMA Data Buffer
To set up a DMA channel for a basic data transfer:
Each of the DMA channels implements five registers
(two control and three buffer/address):
1. Enable the DMA Controller (DMAEN = 1) and
select an appropriate channel priority scheme
by setting or clearing PRSSEL.
• DMACHn: DMA Channel n Control Register
(Register 5-2)
2. Program DMAH and DMAL with the appropriate
upper and lower address boundaries for data
RAM operations.
• DMAINTn: DMA Channel n Interrupt Register
(Register 5-3)
3. Select the DMA channel to be used and disable
• DMASRCn: DMA Data Source Address Pointer
for Channel n
its operation (CHEN = 0).
4. Program the appropriate source and destination
addresses for the transaction into the channel’s
DMASRCn and DMADSTn registers. For PIA
mode addressing, use the base address value.
• DMADSTn: DMAData Destination Address Pointer
for Channel n
• DMACNTn: DMA Transaction Counter for
Channel n
5. Program the DMACNTn register for the number
of triggers per transfer (One-Shot or Continuous
modes) or the number of words (bytes) to be
transferred (Repeated modes).
For PIC24FJ128GL306 family devices, there are a total
of 34 registers.
6. Set or clear the SIZE bit to select the data size.
7. Program the TRMODE[1:0] bits to select the
Data Transfer mode.
8. Program the SAMODE[1:0] and DAMODE[1:0]
bits to select the addressing mode.
9. Enable the DMA channel by setting CHEN.
10. Enable the trigger source interrupt.
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REGISTER 5-1:
DMACON: DMA ENGINE CONTROL REGISTER
R/W-0
DMAEN
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PRSSEL
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
DMAEN: DMA Module Enable bit
1= Enables module
0= Disables module and terminates all active DMA operation(s)
bit 14-1
bit 0
Unimplemented: Read as ‘0’
PRSSEL: Channel Priority Scheme Selection bit
1= Round-robin scheme
0= Fixed priority scheme
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REGISTER 5-2:
DMACHn: DMA CHANNEL n CONTROL REGISTER
U-0
—
U-0
—
U-0
—
r-0
—
U-0
—
R/W-0
R/W-0
RELOAD(1)
R/W-0
CHREQ(3)
NULLW
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SIZE
R/W-0
CHEN
SAMODE1
bit 7
SAMODE0
DAMODE1
DAMODE0
TRMODE1
TRMODE0
bit 0
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
NULLW: Null Write Mode bit
bit 11
bit 10
1= A dummy write is initiated to DMASRCn for every write to DMADSTn
0= No dummy write is initiated
bit 9
RELOAD: Address and Count Reload bit(1)
1= DMASRCn, DMADSTn and DMACNTn registers are reloaded to their previous values upon the
start of the next operation
0= DMASRCn, DMADSTn and DMACNTn are not reloaded on the start of the next operation(2)
bit 8
CHREQ: DMA Channel Software Request bit(3)
1= A DMA request is initiated by software; automatically cleared upon completion of a DMA transfer
0= No DMA request is pending
bit 7-6
SAMODE[1:0]: Source Address Mode Selection bits
11= DMASRCn is used in Peripheral Indirect Addressing and remains unchanged
10= DMASRCn is decremented based on the SIZE bit after a transfer completion
01= DMASRCn is incremented based on the SIZE bit after a transfer completion
00= DMASRCn remains unchanged after a transfer completion
bit 5-4
bit 3-2
DAMODE[1:0]: Destination Address Mode Selection bits
11= DMADSTn is used in Peripheral Indirect Addressing and remains unchanged
10= DMADSTn is decremented based on the SIZE bit after a transfer completion
01= DMADSTn is incremented based on the SIZE bit after a transfer completion
00= DMADSTn remains unchanged after a transfer completion
TRMODE[1:0]: Transfer Mode Selection bits
11= Repeated Continuous mode
10= Continuous mode
01= Repeated One-Shot mode
00= One-Shot mode
bit 1
bit 0
SIZE: Data Size Selection bit
1= Byte (8-bit)
0= Word (16-bit)
CHEN: DMA Channel Enable bit
1= The corresponding channel is enabled
0= The corresponding channel is disabled
Note 1: Only the original DMACNTn is required to be stored to recover the original DMASRCn and DMADSTn.
2: DMASRCn, DMADSTn and DMACNTn are always reloaded in Repeated mode transfers
(DMACHn[2] = 1), regardless of the state of the RELOAD bit.
3: The number of transfers executed while CHREQ is set depends on the configuration of TRMODE[1:0].
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REGISTER 5-3:
DMAINTn: DMA CHANNEL n INTERRUPT REGISTER
R-0
DBUFWF(1)
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHSEL6
CHSEL5
CHSEL4
CHSEL3
CHSEL2
CHSEL1
CHSEL0
bit 8
R/W-0
HIGHIF(1,2)
R/W-0
LOWIF(1,2)
R/W-0
DONEIF(1)
R/W-0
HALFIF(1)
R/W-0
OVRUNIF(1)
U-0
—
U-0
—
R/W-0
HALFEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
DBUFWF: DMA Buffered Data Write Flag bit(1)
1= The content of the DMA buffer has not been written to the location specified in DMADSTn or
DMASRCn in Null Write mode
0= The content of the DMA buffer has been written to the location specified in DMADSTn or DMASRCn
in Null Write mode
bit 14-8
bit 7
CHSEL[6:0]: DMA Channel Trigger Selection bits
See Table 5-1 for a complete list.
HIGHIF: DMA High Address Limit Interrupt Flag bit(1,2)
1= The DMA channel has attempted to access an address higher than DMAH or the upper limit of the
data RAM space
0= The DMA channel has not invoked the high address limit interrupt
bit 6
bit 5
LOWIF: DMA Low Address Limit Interrupt Flag bit(1,2)
1= The DMA channel has attempted to access the DMA SFR address lower than DMAL, but above
the SFR range (07FFh)
0= The DMA channel has not invoked the low address limit interrupt
DONEIF: DMA Complete Operation Interrupt Flag bit(1)
If CHEN = 1:
1= The previous DMA session has ended with completion
0= The current DMA session has not yet completed
If CHEN = 0:
1= The previous DMA session has ended with completion
0= The previous DMA session has ended without completion
bit 4
bit 3
HALFIF: DMA 50% Watermark Level Interrupt Flag bit(1)
1= DMACNTn has reached the halfway point to 0000h
0= DMACNTn has not reached the halfway point
OVRUNIF: DMA Channel Overrun Flag bit(1)
1= The DMA channel is triggered while it is still completing the operation based on the previous trigger
0= The overrun condition has not occurred
bit 2-1
bit 0
Unimplemented: Read as ‘0’
HALFEN: Halfway Completion Watermark bit
1= Interrupts are invoked when DMACNTn has reached its halfway point and at completion
0= An interrupt is invoked only at the completion of the transfer
Note 1: Setting these flags in software does not generate an interrupt.
2: Testing for address limit violations (DMASRCn or DMADSTn is either greater than DMAH or less than
DMAL) is NOT done before the actual access.
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TABLE 5-1:
DMA TRIGGER SOURCES
CHSEL[6:0]
Trigger (Interrupt)
CHSEL[6:0]
1000101
Trigger (Interrupt)
45h UART1 RX Interrupt
0000000
0000001
...
0h
1h
Off
1000110
1000111
...
46h UART1 Error Interrupt
47h
...
6h
Reserved
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
...
...
Reserved
7h
MCCP5 IC/OC Interrupt
MCCP5 Timer Interrupt
MCCP4 IC/OC Interrupt
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
...
4Ah
8h
4Bh DMACHA5 Interrupt
4Ch DMACHA4 Interrupt
4Dh DMACHA3 Interrupt
4Eh DMACHA2 Interrupt
4Fh DMACHA1 Interrupt
50h DMACHA0 Interrupt
51h ADC Interrupt
9h
Ah MCCP4 Timer Interrupt
Bh MCCP3 IC/OC Interrupt
Ch MCCP3 Timer Interrupt
Dh MCCP2 IC/OC Interrupt
Eh MCCP2 Timer Interrupt
Fh
MCCP1 IC/OC Interrupt
52h
10h MCCP1 Timer Interrupt
11h
...
Reserved
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
...
53h
...
Reserved
54h HLVD Interrupt
55h CRC Interrupt
56h LCD Interrupt
57h LCD Automation Interrupt
58h Reserved
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
...
22h
23h SPI2 Receive Interrupt
24h SPI2 Transmit Interrupt
25h SPI2 General Interrupt
26h SPI1 Receive Interrupt
27h SPI1 Transmit Interrupt
28h SPI1 General Interrupt
29h
59h CLC4 Out
5Ah CLC3 Out
5Bh CLC2 Out
5Ch CLC1 Out
...
Reserved
5Dh Reserved
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
...
2Eh
5Eh RTCC Alarm Interrupt
5Fh TMR5 Interrupt
60h TMR4 Interrupt
61h TMR3 Interrupt
62h TMR2 Interrupt
63h TMR1 Interrupt
64h
2Fh I2C2 Slave Interrupt
30h I2C2 Master Interrupt
31h I2C2 Collision Interrupt
32h I2C1 Slave Interrupt
33h I2C1 Master Interrupt
34h I2C1 Collision Interrupt
35h
...
Reserved
...
Reserved
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
...
66h
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
3Ah
67h Comparator Interrupt
68h INT4 Interrupt
69h INT3 Interrupt
6Ah INT2 Interrupt
6Bh INT1 Interrupt
6Ch INT0 Interrupt
6Dh Interrupt-on-Change (IOC) Interrupt
6Eh
3Bh UART4 TX Interrupt
3Ch UART4 RX Interrupt
3Dh UART4 Error Interrupt
3Eh UART3 TX Interrupt
3Fh UART3 RX Interrupt
40h UART3 Error Interrupt
41h UART2 TX Interrupt
42h UART2 RX Interrupt
43h UART2 Error Interrupt
44h UART1 TX Interrupt
...
Reserved
1111111
7Fh
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2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
RTSP is accomplished using TBLRD(Table Read) and
TBLWT(Table Write) instructions. With RTSP, the user
may write program memory data in blocks of
128 instructions (384 bytes) at a time and erase
program memory in blocks of 1024 instructions
(3072 bytes) at a time.
6.0
FLASH PROGRAM MEMORY
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive refer-
ence source. For more information, refer
to “PIC24F Flash Program Memory”
(www.microchip.com/DS30009715) in the
The device implements a 7-bit Error Correcting Code
(ECC). The NVM block contains a logic to write and
read ECC bits to and from the Flash memory. The
Flash is programmed at the same time as the
corresponding ECC parity bits. The ECC provides
improved resistance to Flash errors. ECC single-bit
errors can be transparently corrected; ECC double-bit
errors generate an interrupt.
“dsPIC33/PIC24
Family
Reference
Manual”. The information in this data
sheet supersedes the information in the
FRM.
The PIC24FJ128GL306 family of devices contains
internal Flash program memory for storing and execut-
ing application code. The program memory is readable,
writable and erasable. The Flash memory can be
programmed in four ways:
6.1
Table Instructions and Flash
Programming
• In-Circuit Serial Programming™ (ICSP™)
• Run-Time Self-Programming (RTSP)
• JTAG
Regardless of the method used, all programming of
Flash memory is done with the Table Read and Table
Write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using the TBLPAG[7:0] bits and the Effective
Address (EA) from a W register, specified in the table
instruction, as shown in Figure 6-1.
• Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
ICSP allows a PIC24FJ128GL306 family device to be
serially programmed while in the end application circuit.
This is simply done with two lines for the programming
clock and programming data (named PGCx and PGDx,
respectively), and three other lines for power (VDD),
ground (VSS) and Master Clear (MCLR). This allows
customers to manufacture boards with unprogrammed
devices and then program the microcontroller just
before shipping the product. This also allows the most
The TBLRDLand the TBLWTLinstructions are used to
read or write to bits[15:0] of program memory. TBLRDL
and TBLWTL can access program memory in both
Word and Byte modes.
The TBLRDHand TBLWTHinstructions are used to read
or write to bits[23:16] of program memory. TBLRDHand
TBLWTHcan also access program memory in Word or
Byte mode.
recent firmware or
programmed.
a
custom firmware to be
FIGURE 6-1:
ADDRESSING FOR TABLE REGISTERS
24 Bits
Program Counter
Using
Program
Counter
0
0
Working Reg EA
Using
Table
Instruction
1/0
TBLPAG Reg
8 Bits
16 Bits
User/Configuration
Space Select
Byte
Select
24-Bit EA
2019-2020 Microchip Technology Inc.
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6.2.2
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
6.2
RTSP Operation
The PIC24F Flash program memory array is organized
into rows of 128 instructions or 384 bytes. RTSP allows
the user to erase blocks of eight rows (1024 instruc-
tions) at a time and to program one row at a time. It is
also possible to program two instruction word blocks.
The user can program one row of Flash program memory
at a time. To do this, it is necessary to erase the 8-row
erase block containing the desired row. The general
process is:
1. Read eight rows of program memory
(1024 instructions) and store in data RAM.
The 8-row erase blocks and single row write blocks are
edge-aligned, from the beginning of program memory, on
boundaries of 3072 bytes and 384 bytes, respectively.
2. Update the program data in RAM with the
desired new data.
When data are written to program memory using
TBLWTinstructions, the data are not written directly to
memory. Instead, data written using Table Writes are
stored in holding latches until the programming
sequence is executed.
3. Erase the block (see Example 6-1):
a) Set the NVMOP[3:0] bits (NVMCON[3:0]) to
‘0011’ to configure for block erase. Set the
WREN (NVMCON[14]) bit.
b) Write the starting address of the block to
be erased into the NVMADRU/NVMADR
registers.
Any number of TBLWT instructions can be executed
and a write will be successfully performed. However,
128 TBLWTinstructions are required to write the full row
of memory.
c) Write 55h to NVMKEY.
d) Write AAh to NVMKEY.
To ensure that no data are corrupted during a write, any
unused address should be programmed with
FFFFFFh. This is because the holding latches reset to
an unknown state, so if the addresses are left in the
Reset state, they may overwrite the locations on rows
which were not rewritten.
e) Set the WR bit (NVMCON[15]). The erase
cycle begins and the CPU stalls for the
duration of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
4. Update the TBLPAG register to point to the
programming latches on the device. Update the
NVMADRU/NVMADR registers to point to the
destination in the program memory.
The basic sequence for RTSP programming is to set
the Table Pointer to point to the programming latches,
do a series of TBLWT instructions to load the buffers
and set the NVMADRU/NVMADR registers to point to
the destination. Programming is performed by setting
the control bits in the NVMCON register.
5. Write the first 128 instructions from data RAM into
the program memory buffers (see Table 6-1).
6. Write the program block to Flash memory:
Data can be loaded in any order and the holding
registers can be written to multiple times before perform-
ing a write operation. Subsequent writes, however, will
wipe out any previous writes.
a) Set the NVMOPx bits to ‘0010’ to configure
for row programming. Set the WREN bit.
b) Write 55h to NVMKEY.
c) Write AAh to NVMKEY.
Note:
Writing to a location multiple times without
erasing is not recommended.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration
of the write cycle. When the write to Flash
memory is done, the WR bit is cleared
automatically.
All of the Table Write operations are single-word writes
(two instruction cycles), because only the buffers
are written. A programming cycle is required for
programming each row.
7. Repeat Steps 4 through 6, using the next
available 128 instructions from the block in data
RAM, by incrementing the value in NVMADRU/
NVMADR until all 1024 instructions are written
back to Flash memory.
6.2.1
PROGRAMMING OPERATIONS
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. During a programming or erase operation, the
processor stalls (waits) until the operation is finished.
Setting the WR bit (NVMCON[15]) starts the operation
and the WR bit is automatically cleared when the
operation is finished.
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 6-2.
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TABLE 6-1:
EXAMPLE PAGE ERASE
Step 1: Set the NVMCON register to erase a page.
MOV
MOV
#0x4003, W0
W0, NVMCON
Step 2: Load the address of the page to be erased into the NVMADRU/NVMADR register pair.
MOV
MOV
MOV
MOV
#PAGE_ADDR_LO, W0
W0, NVMADR
#PAGE_ADDR_HI, W0
W0, NVMADRU
Step 3: Set the WR bit.
MOV
MOV
MOV
MOV
BSET
NOP
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W0
W0, NVMKEY
NVMCON, #WR
EXAMPLE 6-1:
ERASING A PROGRAM MEMORY BLOCK (‘C’ LANGUAGE CODE)
// C example using MPLAB XC16
unsigned
unsigned
long progAddr = 0xXXXXXX;
int offset;
// Address of row to write
//Set up pointer to the first memory location to be written
NVMADRU = progAddr>>16;
NVMADR = progAddr & 0xFFFF;
NVMCON = 0x4003;
// Initialize PM Page Boundary SFR
// Initialize lower word of address
// Initialize NVMCON
asm("DISI #5");
// Block all interrupts with priority <7
// for next 5 instructions
__builtin_write_NVM();
// check function to perform unlock
// sequence and set WR
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TABLE 6-2:
CODE MEMORY PROGRAMMING EXAMPLE: ROW WRITES
Step 1: Set the NVMCON register to program 128 instruction words.
MOV
MOV
#0x4002, W0
W0, NVMCON
Step 2: Initialize the TBLPAG register for writing to the latches.
MOV
MOV
#0xFA, W12
W12, TBLPAG
Step 3: Load W0:W5 with the next four instruction words to program.
MOV
MOV
MOV
MOV
MOV
MOV
#<LSW0>, W0
#<MSB1:MSB0>, W1
#<LSW1>, W2
#<LSW2>, W3
#<MSB3:MSB2>, W4
#<LSW3>, W5
Step 4: Set the Read Pointer (W6) and load the (next set of) write latches.
CLR
CLR
W6
W7
TBLWTL
[W6++], [W7]
TBLWTH.B [W6++], [W7++]
TBLWTH.B [W6++], [++W7]
TBLWTL
TBLWTL
[W6++], [W7++]
[W6++], [W7]
TBLWTH.B [W6++], [W7++]
TBLWTH.B [W6++], [++W7]
TBLWTL
[W6++], [W7++]
Step 5: Repeat Steps 4 and 5, for a total of 32 times, to load the write latches with 128 instructions.
Step 6: Set the NVMADRU/NVMADR register pair to point to the correct address.
MOV
MOV
MOV
MOV
#DestinationAddress[15:0], W3
#DestinationAddress[23:16], W4
W3, NVMADR
W4, NVMADRU
Step 7: Execute the WR bit unlock sequence and initiate the write cycle.
MOV
MOV
MOV
MOV
BSET
NOP
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W0
W0, NVMKEY
NVMCON, #WR
EXAMPLE 6-2:
ROW PROGRAMMING (‘C’ LANGUAGE CODE)
int varWord1L[128];
int varWord1H[128];
int targetWriteAddressL;
int targetWriteAddressH;
int i;
// bits<15:0>
// bits<22:16>
NVMCON = 0x4002;
TBLPAG = 0xFA;
NVMADRL = targetWriteAddressL;
NVMADRH = targetWriteAddressH;
// Set WREN and row program mode
// set target write address
for(i=0; i<128; i++)
{
// load write latches with data
// to be written
__builtin_tblwtl( (i*2), varWord1L[i]);
__builtin_tblwth( (i*2), varWord1H[i]);
}
__builtin_disi(5);
__builtin_write_NVM();
//Disable interrupts for NVM unlock sequence
// initiate write
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PIC24FJ128GL306 FAMILY
words to be programmed. The TBLWTL and TBLWTH
instructions write the desired data into the write latches.
To configure the NVMCON register for a two-word write,
set the NVMOPx bits (NVMCON[3:0]) to ‘0001’. The
write is performed by executing the unlock sequence
and setting the WR bit. An equivalent procedure in ‘C’,
using the MPLAB® XC16 compiler and built-in hardware
functions, is shown in Example 6-3.
6.2.3
PROGRAMMING A DOUBLE WORD
OF FLASH PROGRAM MEMORY
If a Flash location has been erased, it can be
programmed using Table Write instructions to write two
instruction words (2 x 24-bit) into the write latch. The
TBLPAG register is loaded with the address of the write
latches and the NVMADRU/NVMADR registers are
loaded with the address of the first of the two instruction
TABLE 6-3:
PROGRAMMING A DOUBLE WORD OF FLASH PROGRAM MEMORY
Step 1: Initialize the TBLPAG register for writing to the latches.
MOV
MOV
#0xFA, W12
W12, TBLPAG
Step 2: Load W0:W2 with the next two packed instruction words to program.
MOV
MOV
MOV
#<LSW0>, W0
#<MSB1:MSB0>, W1
#<LSW1>, W2
Step 3: Set the Read Pointer (W6) and Write Pointer (W7), and load the (next set of) write latches.
CLR
W6
CLR
W7
TBLWTL
[W6++], [W7]
TBLWTH.B [W6++], [W7++]
TBLWTH.B [W6++], [++W7]
TBLWTL.W [W6++], [W7++]
Step 4: Set the NVMADRU/NVMADR register pair to point to the correct address.
MOV
MOV
MOV
MOV
#DestinationAddress[15:0], W3
#DestinationAddress[23:16], W4
W3, NVMADR
W4, NVMADRU
Step 5: Set the NVMCON register to program two instruction words.
MOV
MOV
NOP
#0x4001, W10
W10, NVMCON
Step 6: Initiate the write cycle.
MOV
MOV
MOV
MOV
BSET
NOP
NOP
NOP
#0x55, W1
W1, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
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EXAMPLE 6-3:
PROGRAMMING A DOUBLE WORD OF FLASH PROGRAM MEMORY
(‘C’ LANGUAGE CODE)
// C example using MPLAB XC16
unsigned
unsigned
unsigned
unsigned
unsigned
long progAddr = 0xXXXXXX;
// Address of word to program
int progData1L = 0xXXXX;
char progData1H = 0xXX;
int progData2L = 0xXXXX;
char progData2H = 0xXX;
// Data to program lower word of word 1
// Data to program upper byte of word 1
// Data to program lower word of word 2
// Data to program upper byte of word 2
//Set up NVMCON for word programming
NVMCON = 0x4001;
// Initialize NVMCON
TBLPAG = 0xFA;
// Point TBLPAG to the write latches
//Set up pointer to the first memory location to be written
NVMADRU = progAddr>>16;
// Initialize PM Page Boundary SFR
NVMADR = progAddr & 0xFFFF;
// Initialize lower word of address
//Perform TBLWT instructions to write latches
__builtin_tblwtl(0, progData1L);
__builtin_tblwth(0, progData2H);
__builtin_tblwtl(1, progData2L);
__builtin_tblwth(1, progData2H);
asm(“DISI #5”);
// Write word 1 to address low word
// Write word 1 to upper byte
// Write word 2 to address low word
// Write word 2 to upper byte
// Block interrupts with priority <7 for next 5
// instructions
__builtin_write_NVM();
// XC16 function to perform unlock sequence and set WR
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NVMKEY (Register 6-4) is a write-only register that is
used for write protection. To start a programming or erase
sequence, the user must consecutively write 55h and
AAh to the NVMKEY register. Refer to Section 6.2.1
“Programming Operations” for further details.
6.3
Control Registers
There are four SFRs used to read and write the Program
Flash Memory (PFM): NVMCON, NVMADRU, NVMADR
and NVMKEY.
The NVMCON register (Register 6-1) controls which
blocks are to be erased, which memory type is to be
programmed and when the programming cycle starts.
The NVMADRU/NVMADR registers contain the upper
byte and lower word of the destination of the NVM write or
erase operation. Some operations (chip erase) operate
on fixed locations and do not require an address value.
REGISTER 6-1:
NVMCON: NONVOLATILE FLASH MEMORY CONTROL REGISTER
HC/R/S-0(1,3)
WR
R/W-0(1)
WREN
HSC/R-0(1)
WRERR
R/W-0
r-0
—
r-0
—
U-0
—
U-0
—
NVMSIDL
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0(1)
NVMOP3(2)
R/W-0(1)
R/W-0(1)
R/W-0(1)
NVMOP2(2) NVMOP1(2) NVMOP0(2)
bit 7
bit 0
Legend:
S = Settable bit
W = Writable bit
‘1’ = Bit is set
HC = Hardware Clearable bit
‘0’ = Bit is cleared
r = Reserved bit
R = Readable bit
-n = Value at POR
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
HSC = Hardware Settable/Clearable bit
bit 15
WR: Write Control bit(1,3)
1= Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once the operation is complete
0= Program or erase operation is complete and inactive
bit 14
bit 13
WREN: Write Enable bit(1)
1= Enables Flash program/erase operations
0= Inhibits Flash program/erase operations
WRERR: Write Sequence Error Flag bit(1)
1= An improper program or erase sequence attempt, or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0= The program or erase operation completed normally
bit 12
NVMSIDL: NVM Stop in Idle bit
1= Removes power from the program memory when device enters Idle mode
0= Powers program memory in Standby mode when the device enters Idle mode
bit 11-10
bit 9-4
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
bit 3-0
NVMOP[3:0]: NVM Operation Select bits(1,2)
1110= Chip erases user memory (does not erase Device ID, customer OTP or executive memory)
0100= Unused
0011= Erases a page of program or executive memory
0010= Row programming operation
0001= Double-word programming operation
Note 1: These bits can only be reset on a Power-on Reset.
2: All other combinations of NVMOP[3:0] are unimplemented.
3: Unlock sequence must be executed before writing to this bit.
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REGISTER 6-2:
NVMADR: NONVOLATILE MEMORY LOWER ADDRESS REGISTER
R/W-x R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 8
R/W-x
NVMADR[15:8]
bit 15
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
NVMADR[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
NVMADR[15:0]: Nonvolatile Memory Lower Write Address bits
Selects the lower 16 bits of the location to program or erase in Program Flash Memory. This register may
be read or written to by the user application.
REGISTER 6-3:
NVMADRU: NONVOLATILE MEMORY UPPER ADDRESS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-x
bit 7
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 0
NVMADRU[23:16]
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
NVMADRU[23:16]: Nonvolatile Memory Upper Write Address bits
Selects the upper eight bits of the location to program or erase in Program Flash Memory. This register
may be read or written to by the user application.
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Register 6-4:
NVMKEY: NONVOLATILE MEMORY KEY REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
W-0
bit 7
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY[7:0]
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
NVMKEY[7:0]: NVM Key Register bits (write-only)
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Double-bit error occurrences generate a generic hard
trap and set the ECCDBE (INTCON4[1]) bit. If no Inter-
rupt Service Routine is implemented for the hard trap, a
device Reset will also occur. The ECCSTATH register
contains double-bit error status information. The
DEDOUT bit is the expected calculated Dual Bit Error
Detection (DED) parity and DEDIN is the actual value
from a Flash read operation. When no error is present,
DEDIN equals DEDOUT.
6.4
Error Correcting Code (ECC)
In order to improve program memory performance and
durability, these devices include Error Correcting Code
(ECC) functionality as an integral part of the Flash
memory controller. ECC can determine the presence of
single-bit errors in program data, including which bit is
in error, and correct the data automatically without user
intervention. ECC cannot be disabled.
When data are written to program memory, ECC
generates a 7-bit Hamming code parity value for every
two (24-bit) instruction words. The data are stored in
blocks of 48 data bits and seven parity bits; parity data
are not memory-mapped and are inaccessible. When
the data are read back, the ECC calculates the parity
on them and compares it to the previously stored parity
value. If a parity mismatch occurs, there are two
possible outcomes:
6.4.1
ECC FAULT INJECTION
To test Fault handling, an ECC error can be generated.
Both single and double-bit errors can be generated in
both the read and write data paths. Read path Fault
injection first reads the Flash data and then modifies
them prior to entering the ECC logic. Write path Fault
injection modifies the actual data prior to them being
written into the target Flash and will cause an ECC error
on a subsequent Flash read. The following procedure is
used to inject a Fault:
• Single-bit error has occurred and has been
automatically corrected on read-back
• Double-bit error has occurred and the read data
are not changed
1. Load the Flash target address into the
ECCADDR register.
2. Select 1st Fault bit determined by the
FLT1PTRx (ECCCONH[7:0]) bits. The target bit
is inverted to create the Fault.
Single-bit error occurrence can be identified by the
state of the ECCSBEIF (IFS6[12]) bit. An interrupt can
be generated when the corresponding interrupt enable
bit is set, ECCSBEIE (IEC6[12]). The ECCSTATL
register contains the parity information for single-bit
errors. The SECOUT[7:0] bits field contains the
expected calculated SEC parity and the SECIN[7:0]
bits contain the actual value from a Flash read opera-
tion. The SECSYNDx bits (ECCSTATH[7:0]) indicate
the bit position of the single-bit error within the 48-bit
pair of instruction words. When no error is present,
SECINx equals SECOUTx and SECSYNDx is zero.
3. If a double Fault is desired, select the 2nd Fault bit
determined by the FLT2PTRx (ECCCONH[15:8])
bits; otherwise, set to all ‘1’s.
4. Write the NVMKEY unlock sequence (see
Section 6.3 “Control Registers”).
5. Enable the ECC Fault injection logic by setting
the FLTINJ bit (ECCCONL[0]).
6. Perform a read or write to the Flash target
address.
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6.4.2
ECC CONTROL REGISTERS
REGISTER 6-5:
ECCCONL: ECC FAULT INJECTION CONFIGURATION REGISTER LOW
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
FLTINJ
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-1
bit 0
Unimplemented: Read as ‘0’
FLTINJ: Fault Injection Sequence Enable bit
1= Enabled
0= Disabled
REGISTER 6-6:
ECCCONH: ECC FAULT INJECTION CONFIGURATION REGISTER HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT2PTR[7:0]
bit 15
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT1PTR[7:0]
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
FLT2PTR[7:0]: ECC Fault Injection Bit Pointer 2 bits
11111111-00111000= No Fault injection occurs
00110111= Fault injection (bit inversion) occurs on bit 55 of ECC bit order
•
•
•
00000001= Fault injection (bit inversion) occurs on bit 1 of ECC bit order
00000000= Fault injection (bit inversion) occurs on bit 0 of ECC bit order
bit 7-0
FLT1PTR[7:0]: ECC Fault Injection Bit Pointer 1 bits
11111111-00111000= No Fault injection occurs
00110111 = Fault injection occurs on bit 55 of ECC bit order
•
•
•
00000001= Fault injection occurs on bit 1 of ECC bit order
00000000= Fault injection occurs on bit 0 of ECC bit order
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REGISTER 6-7:
ECCADDRL: ECC FAULT INJECT ADDRESS COMPARE REGISTER LOW
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
ECCADDR[15:8]
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ECCADDR[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
ECCADDR[15:0]: ECC Fault Injection NVM Address Match Compare bits
REGISTER 6-8:
ECCADDRH: ECC FAULT INJECT ADDRESS COMPARE REGISTER HIGH
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
ECCADDR[23:16]
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
ECCADDR[23:16]: ECC Fault Injection NVM Address Match Compare bits
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REGISTER 6-9:
ECCSTATL: ECC SYSTEM STATUS DISPLAY REGISTER LOW
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
SECOUT[7:0]
bit 15
R-0
bit 8
bit 0
R-0
R-0
R-0
R-0
R-0
SECIN[7:0]
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-0
SECOUT[7:0]: Calculated Single Error Correction Parity Value bits
SECIN[7:0]: Read Single Error Correction Parity Value bits
SECIN[7:0] bits are the actual parity value of a Flash read operation.
REGISTER 6-10: ECCSTATH: ECC SYSTEM STATUS DISPLAY REGISTER HIGH
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
DEDOUT
DEDIN
bit 8
bit 15
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
SECSYND[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-10
bit 9
Unimplemented: Read as ‘0’
DEDOUT: Calculated Dual Bit Error Detection Parity bit
DEDIN: Read Dual Bit Error Detection Parity bit
bit 8
DEDIN is the actual parity value of a Flash read operation.
SECSYND[7:0]: Calculated ECC Syndrome Value bits
Indicates the bit location that contains the error.
bit 7-0
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Only the lower 16 data bits stored at the activation
addresses are evaluated; the upper eight bits and
second 24-bit word, written by the double-word pro-
gramming (NVMOP[3:0]), should be written as ‘0’s. The
addresses can be programmed in any order and also
during separate ICSP/Enhanced ICSP/RTSP sessions,
but any attempt to program an incorrect 16-bit value or
use a row programming operation to program the values
will be aborted without altering the existing data.
6.5
Flash OTP by ICSP™ Write Inhibit
ICSP Write Inhibit is an access restriction feature, that
when activated, restricts all of Flash memory. Once acti-
vated, ICSP Write Inhibit permanently prevents ICSP
Flash programming and erase operations, and cannot
be deactivated. This feature is intended to prevent alter-
ation of Flash memory contents, with behavior similar to
One-Time-Programmable (OTP) devices.
RTSP, including erase and programming operations, is
not restricted when ICSP Write Inhibit is activated;
however, code to perform these actions must be pro-
grammed into the device before ICSP Write Inhibit is
activated. This allows for a bootloader-type application
to alter Flash contents with ICSP Write Inhibit activated.
TABLE 6-4:
ICSP™ WRITE INHIBIT
ACTIVATION ADDRESSES
AND DATA
ICSP Write
Configuration
Inhibit
Memory Address
Activation Value
Entry into ICSP and Enhanced ICSP modes is not
affected by ICSP Write Inhibit. In these modes, it will con-
tinue to be possible to read configuration memory space
and any user memory space regions which are not code
protected. With ICSP writes inhibited, an attempt to set
WR (NVMCON[15]) = 1 will maintain WR = 0, and
instead, set WRERR (NVMCON[13]) = 1. All Enhanced
ICSP erase and programming commands will have no
effect with self-checked programming commands return-
ing a FAIL response opcode (PASS if the destination
already exactly matched the requested programming
data).
Write Lock 1
Write Lock 2
0x801024
0x801028
0x006D63
0x006870
6.6
JTAG Operation
The PIC24F family supports JTAG boundary scan.
Boundary scan can improve the manufacturing
process by verifying pin to PCB connectivity.
6.7
Enhanced In-Circuit Serial
Programming
Once ICSP Write Inhibit is activated, it is not possible for
a device executing in Debug mode to erase/write Flash,
nor can a debug tool switch the device to Production
mode. ICSP Write Inhibit should therefore, only be
activated on devices programmed for production.
Enhanced In-Circuit Serial Programming uses an on-
board bootloader, known as the Program Executive (PE),
to manage the programming process. Using an SPI data
frame format, the Program Executive can erase, program
and verify program memory. For more information on
Enhanced ICSP, refer to the “PIC24FJ128GL306 Family
Flash Programming Specification” (www.microchip.com/
DS30010189).
6.5.1
Note:
ACTIVATING FLASH OTP BY ICSP
WRITE INHIBIT
It is not possible to deactivate ICSP Write
Inhibit.
ICSP Write Inhibit is activated by executing a pair of
NVMCON double-word programming commands to
save two 16-bit activation values in the configuration
memory space. The target NVM addresses and values
required for activation are shown in Table 6-4. Once
both addresses contain their activation values, ICSP
Write Inhibit will take permanent effect on the next
device Reset.
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Any active source of Reset will make the SYSRST
signal active. Many registers associated with the CPU
and peripherals are forced to a known Reset state.
Most registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
7.0
RESETS
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to “Reset” (www.microchip.com/
DS39712) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in this
data sheet supersedes the information in
the FRM.
Note:
Refer to the specific peripheral or CPU
section of this data sheet for register
Reset states.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 7-1). A POR will clear all bits, except for
the BOR and POR (RCON[1:0]) bits, which are set. The
user may set or clear any bit at any time during code
execution. The RCON bits only serve as status bits.
Setting a particular Reset status bit in software will not
cause a device Reset to occur.
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• MCLR: Master Clear Pin Reset
• SWR: RESETInstruction
The RCON register also has other bits associated with
the Watchdog Timer and device Power-Saving states.
The function of these bits is discussed in other sections
of this data sheet.
• WDT: Watchdog Timer Reset
• BOR: Brown-out Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode Reset
• UWR: Uninitialized W Register Reset
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register values after a
device Reset will be meaningful.
A simplified block diagram of the Reset module is
shown in Figure 7-1.
FIGURE 7-1:
RESET SYSTEM BLOCK DIAGRAM
RESET
Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
POR
VDD Rise
Detect
SYSRST
VDD
Brown-out
Reset
BOR
Enable Voltage Regulator
Trap Conflict
Illegal Opcode
Configuration Mismatch
Uninitialized W Register
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REGISTER 7-1:
RCON: RESET CONTROL REGISTER(6)
R/W-0
TRAPR(1)
R/W-0
R/W-1
R/W-0
RETEN(2)
U-0
—
U-0
—
R/W-0
CM(1)
R/W-0
VREGS(3)
IOPUWR(1) SBOREN(5)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
EXTR(1)
SWR(1)
SWDTEN(4)
WDTO(1)
SLEEP(1)
IDLE(1)
BOR(1)
POR(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
TRAPR: Trap Reset Flag bit(1)
1= A Trap Conflict Reset has occurred
0= A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Register Access Reset Flag bit(1)
1= An illegal opcode detection, an illegal address mode or Uninitialized W register is used as an
Address Pointer and caused a Reset
0= An illegal opcode or Uninitialized W register Reset has not occurred
bit 13
bit 12
SBOREN: Software Control Over the BOR Function bit(5)
1= BOR is enabled
0= BOR is disabled
RETEN: Retention Mode Enable bit(2)
1= Retention mode is enabled while device is in Sleep mode (1.2V regulator supplies to the core)
0= Retention mode is disabled; normal voltage levels are present
bit 11-10
bit 9
Unimplemented: Read as ‘0’
CM: Configuration Word Mismatch Reset Flag bit(1)
1= A Configuration Word Mismatch Reset has occurred
0= A Configuration Word Mismatch Reset has not occurred
bit 8
bit 7
bit 6
VREGS: Fast Wake-up from Sleep bit(3)
1= Regulator Standby mode is disabled (fast wake-up, uses more power)
0= Regulator Standby mode is enabled (slow wake-up, uses less power)
EXTR: External Reset (MCLR) Pin bit(1)
1= A Master Clear (pin) Reset has occurred
0= A Master Clear (pin) Reset has not occurred
SWR: Software RESET(Instruction) Flag bit(1)
1= A RESETinstruction has been executed
0= A RESETinstruction has not been executed
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the LPCFG Configuration bit is ‘1’ (unprogrammed), the retention regulator is disabled and the RETEN
bit has no effect.
3: Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from Sleep.
Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring.
4: If the FWDTEN[1:0] Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless of
the SWDTEN bit setting.
5: The BOREN[1:0] (FPOR[1:0]) Configuration bits must be set to ‘01’ in order for SBOREN to have an effect.
6: On wake-up from Retention Sleep, RCON will have same value as a POR event.
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REGISTER 7-1:
RCON: RESET CONTROL REGISTER(6) (CONTINUED)
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SWDTEN: Software Enable/Disable of WDT bit(4)
1= WDT is enabled
0= WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit(1)
1= WDT time-out has occurred
0= WDT time-out has not occurred
SLEEP: Wake from Sleep Flag bit(1)
1= Device has been in Sleep mode
0= Device has not been in Sleep mode
IDLE: Wake-up from Idle Flag bit(1)
1= Device has been in Idle mode
0= Device has not been in Idle mode
BOR: Brown-out Reset Flag bit(1)
1= A Brown-out Reset has occurred (also set after a Power-on Reset)
0= A Brown-out Reset has not occurred
POR: Power-on Reset Flag bit(1)
1= A Power-on Reset has occurred
0= A Power-on Reset has not occurred
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the LPCFG Configuration bit is ‘1’ (unprogrammed), the retention regulator is disabled and the RETEN
bit has no effect.
3: Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from Sleep.
Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring.
4: If the FWDTEN[1:0] Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless of
the SWDTEN bit setting.
5: The BOREN[1:0] (FPOR[1:0]) Configuration bits must be set to ‘01’ in order for SBOREN to have an effect.
6: On wake-up from Retention Sleep, RCON will have same value as a POR event.
TABLE 7-1:
Flag Bit
RESET FLAG BIT OPERATION
Setting Event
Trap Conflict Event
Clearing Event
TRAPR (RCON[15])
IOPUWR (RCON[14])
CM (RCON[9])
POR
Illegal Opcode or Uninitialized W Register Access
Configuration Mismatch Reset
MCLR Reset
POR
POR
EXTR (RCON[7])
SWR (RCON[6])
WDTO (RCON[4])
SLEEP (RCON[3])
IDLE (RCON[2])
BOR (RCON[1])
POR (RCON[0])
POR
RESETInstruction
POR
WDT Time-out
CLRWDT, PWRSAVInstruction, POR
PWRSAV #0Instruction
PWRSAV #1Instruction
POR, BOR
POR
POR
—
POR
—
Note:
All Reset flag bits may be set or cleared by the user software.
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7.1
Special Function Register Reset
States
7.4
Low-Power BOR (LPBOR)
Low-Power BOR is implemented to provide downside
protection when BOR is disabled.
Most of the Special Function Registers (SFRs) associated
with the PIC24F CPU and peripherals are reset to a par-
ticular value at a device Reset. The SFRs are grouped by
their peripheral or CPU function and their Reset values
are specified in each section of this data sheet.
• LPBOR re-arms the POR to ensure that the
device will reset if VDD drops below the POR
threshold. The LPBOR trip point is around 2.0V.
• LPBOR is selected in the configuration through
the DNVPEN bit in the FPOR Configuration
register.
The Reset value for each SFR does not depend on the
type of Reset, with the exception of four registers. The
Reset value for the Reset Control register, RCON, will
depend on the type of device Reset. The Reset value for
the Oscillator Control register, OSCCON, will depend on
the type of Reset and the programmed values of the
FNOSC[2:0] bits in the FOSCSEL Configuration register
(see Table 7-2). The NVMCON register is only affected
by a POR.
Because it is designed for very low-current
consumption, accuracy may vary slightly.
7.5
Clock Source Selection at Reset
If clock switching is enabled, the system clock source
at device Reset is chosen, as shown in Table 7-2. If
clock switching is disabled, the system clock source is
always selected according to the Oscillator Configura-
tion bits. For more information, refer to “Oscillator”
(www.microchip.com/DS39700) in the “dsPIC33/PIC24
Family Reference Manual”.
7.2
Device Reset Times
The Reset times for various types of device Reset are
summarized in Table 7-3. Note that the Master Reset
Signal, SYSRST, is released after the POR delay time
expires.
TABLE 7-2:
OSCILLATOR SELECTION vs.
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
The time at which the device actually begins to execute
code will also depend on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
Reset Type
Clock Source Determinant
POR
FNOSC[2:0] Configuration bits
(FOSCSEL[2:0])
The Fail-Safe Clock Monitor (FSCM) delay determines
the time at which the FSCM begins to monitor the system
clock source after the SYSRST signal is released.
BOR
MCLR
WDTO
SWR
COSC[2:0] Control bits
(OSCCON[14:12])
7.3
Brown-out Reset (BOR)
PIC24FJ128GL306 family devices implement a BOR
circuit that provides the user with several configuration
and power-saving options. The BOR is controlled by the
BOREN[1:0] (FPOR[1:0]) Configuration bits.
When BOR is enabled, any drop of VDD below the BOR
threshold results in a device BOR. Threshold levels are
described in Section 30.1 “DC Characteristics”.
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TABLE 7-3:
Reset Type
POR
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
System Clock
Delay
Clock Source
SYSRST Delay
Notes
1, 2, 3
EC
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TPOR + TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TSTARTUP + TRST
TRST
—
ECPLL
TLOCK
1, 2, 3, 5
1, 2, 3, 4
1, 2, 3, 4, 5
1, 2, 3, 6, 7
1, 2, 3, 5, 6
1, 2, 3, 6
2, 3
XT, HS, SOSC
XTPLL, HSPLL
FRC, OSCFDIV
FRCPLL
TOST
TOST + TLOCK
TFRC
TFRC + TLOCK
LPRC
TLPRC
BOR
EC
—
ECPLL
TLOCK
2, 3, 5
2, 3, 4
2, 3, 4, 5
2, 3, 6, 7
2, 3, 5, 6
2, 3, 6
3
XT, HS, SOSC
XTPLL, HSPLL
FRC, OSCFDIV
FRCPLL
TOST
TOST + TLOCK
TFRC
TFRC + TLOCK
LPRC
TLPRC
—
MCLR
WDT
Any Clock
Any Clock
Any clock
TRST
—
3
Software
TRST
—
3
Illegal Opcode Any Clock
Uninitialized W Any Clock
TRST
—
3
TRST
—
3
Trap Conflict
Any Clock
TRST
—
3
Note 1: TPOR = Power-on Reset delay (10 µs nominal).
2: TSTARTUP = TVREG.
3: TRST = Internal State Reset Time (2 µs nominal).
4: TOST = Oscillator Start-up Timer (OST). A 10-bit counter counts 1024 oscillator periods before releasing
the oscillator clock to the system.
5: TLOCK = PLL Lock Time.
6: TFRC and TLPRC = RC Oscillator Start-up Times.
7: If Two-Speed Start-up is enabled, regardless of the Primary Oscillator selected, the device starts with FRC
so the system clock delay is just TFRC, and in such cases, FRC start-up time is valid; it switches to the
Primary Oscillator after its respective clock delay.
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The device will not begin to execute code until a valid
clock source has been released to the system. There-
fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
7.5.1
POR AND LONG OSCILLATOR
START-UP TIMES
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially low-
frequency crystals) will have a relatively long start-up
time. Therefore, one or more of the following conditions
is possible after SYSRST is released:
7.5.2
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
If the FSCM is enabled, it will begin to monitor the
system clock source when SYSRST is released. If a
valid clock source is not available at this time, the
device will automatically switch to the FRC Oscillator
and the user can switch to the desired crystal oscillator
in the Trap Service Routine (TSR).
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
crystal oscillator is used).
• The PLL has not achieved a lock (if PLL is used).
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8.1.1
ALTERNATE INTERRUPT VECTOR
TABLE
8.0
INTERRUPT CONTROLLER
Note 1: This data sheet summarizes the features
of the PIC24FJ128GL306 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this
data sheet, refer to “Interrupts”
(www.microchip.com/DS70000600) in
the “dsPIC33/PIC24 Family Reference
Manual”. The information in this data
sheet supersedes the information in the
FRM.
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 8-1. The AIVTEN
(INTCON2[8]) control bit provides access to the AIVT.
If the AIVTEN bit is set, all interrupt and exception
processes will use the alternate vectors instead of the
default vectors. The alternate vectors are organized in
the same manner as the default vectors.
The AIVT is available only if the Boot Segment has
been defined and the AIVT has been enabled. To
enable the AIVT, both the Configuration bit, AIVTDIS
(FSEC[15]), and the AIVTEN bit (INTCON2[8] in the
SFR), have to be set. When the AIVT is enabled, all
interrupts and exception processes use the alternate
vectors instead of the default vectors. The AIVT begins
at the start of the last page of the Boot Segment (BS)
defined by the BSLIM[12:0] bits. The AIVT address is:
(BSLIM[12:0] – 1) x 0x800.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The PIC24FJ128GL306 family interrupt controller
reduces the numerous peripheral interrupt request
signals to a single interrupt request signal to the
PIC24FJ128GL306 family CPU.
8.2
Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The PIC24FJ128GL306 family devices clear their
registers in response to a Reset, which forces the PC
to zero. The device then begins program execution at
location, 0x000000. A GOTO instruction at the Reset
address can redirect program execution to the
appropriate start-up routine.
The interrupt controller has the following features:
• Up to Eight Processor Exceptions and
Software Traps
• Seven User-Selectable Priority Levels
• Interrupt Vector Table (IVT) with a Unique Vector
for Each Interrupt or Exception Source
Note: Any unimplemented or unused vector
locations in the IVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESETinstruction.
• Fixed Priority within a Specified User Priority Level
• Fixed Interrupt Entry and Return Latencies
8.1
Interrupt Vector Table
The PIC24FJ128GL306 family IVT, shown in Figure 8-1,
resides in program memory starting at location,
000004h. The IVT contains six non-maskable trap
vectors and up to 118 sources of interrupt. In general,
each interrupt source has its own vector. Each interrupt
vector contains a 24-bit wide address. The value
programmed into each interrupt vector location is the
starting address of the associated Interrupt Service
Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with Vector 0 takes priority over interrupts at any other
vector address.
2019-2020 Microchip Technology Inc.
DS30010198B-page 81
PIC24FJ128GL306 FAMILY
FIGURE 8-1:
PIC24F INTERRUPT VECTOR TABLES
(1)
(1,2)
Interrupt Vector Table (IVT)
Alternate Interrupt Vector Table (AIVT)
Reset – GOTOInstruction
Reset – GOTOAddress
Oscillator Fail Trap Vector
Address Error Trap Vector
General Hard Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
000000h
000002h
000004h
Reserved
Reserved
BOA+00h
BOA+02h
BOA+04h
Oscillator Fail Trap Vector
Address Error Trap Vector
General Hard Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
General Soft Trap Vector
Reserved
General Soft Trap Vector
Reserved
Interrupt Vector 0
Interrupt Vector 1
—
000014h
Interrupt Vector 0
Interrupt Vector 1
—
BOA+14h
—
—
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
—
00007Ch
00007Eh
000080h
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
—
BOA+7Ch
BOA+7Eh
BOA+80h
—
—
Interrupt Vector 116
Interrupt Vector 117
0000FCh
0000FEh
Interrupt Vector 116
Interrupt Vector 117
(Start of Code)
BOA+FEh
(BOA+100h)
Legend: BOA: Base Offset Address for AIVT, which is the starting address of the last page of the Boot Segment.
All addresses are in hexadecimal.
Note 1: See Table 8-2 for the interrupt vector list.
2: AIVT is only available when a Boot Segment is implemented.
TABLE 8-1:
TRAP VECTOR DETAILS
MPLAB® XC16
ISR Name
Vector Number
IVT Address
AIVT Address
Trap Source
0
1
2
3
4
5
6
7
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
BOA+04h
BOA+06h
BOA+08h
BOA+0Ah
BOA+0Ch
BOA+0Eh
BOA+10h
BOA+12h
Oscillator Failure
Address Error
_Oscillator Fail
_AddressError
General Hardware Error _NVMError
Stack Error
_StackError
_MathError
Reserved
Math Error
Reserved
General Software Error
Reserved
_GeneralError
Reserved
Legend: BOA = Base Offset Address for AIVT segment, which is the starting address of the last page of the
Boot Segment.
DS30010198B-page 82
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 8-2:
INTERRUPT VECTOR DETAILS
Interrupt Bit Location
®
MPLAB XC16
ISR Name
Vector
#
IRQ
#
Interrupt Description
IVT Address
Flag
Enable
Priority
Highest Natural Order Priority
External Interrupt 0
Capture/Compare/Timer1
Capture/Compare/Timer2
Timer1
_INT0Interrupt
_CCT1Interrupt
_CCT2Interrupt
_T1Interrupt
8
9
0
1
000014h
000016h
IFS0[0]
IFS0[1]
IFS0[2]
IFS0[3]
IFS0[4]
—
IEC0[0]
IEC0[1]
IEC0[2]
IEC0[3]
IEC0[4]
—
IPC0[2:0]
IPC0[6:4]
IPC0[10:8]
IPC0[14:12]
IPC1[2:0]
—
10
2
000018h
11
3
00001Ah
Direct Memory Access 0
Reserved
_DMA0Interrupt
Reserved
12
4
00001Ch
13-14
15
5-6
7
00001Eh-000020h
000022h
Timer2
_T2Interrupt
IFS0[7]
IFS0[8]
IFS0[9]
IEC0[7]
IEC0[8]
IEC0[9]
IPC1[14:12]
IPC2[2:0]
IPC2[6:4]
IPC2[10:8]
IPC2[14:12]
IPC3[2:0]
IPC3[6:4]
IPC3[10:8]
IPC3[14:12]
IPC4[2:0]
IPC4[6:4]
IPC4[10:8]
IPC4[14:12]
IPC5[2:0]
—
Timer3
_T3Interrupt
16
8
000024h
SPI1 General
_SPI1Interrupt
_SPI1TXInterrupt
_U1RXInterrupt
_U1TXInterrupt
_ADC1Interrupt
_DMA1Interrupt
17
9
000026h
SPI1 Transfer Done
UART1 Receiver
UART1 Transmitter
A/D Converter 1
Direct Memory Access 1
18
10
11
000028h
IFS0[10] IEC0[10]
IFS0[11] IEC0[11]
IFS0[12] IEC0[12]
IFS0[13] IEC0[13]
IFS0[14] IEC0[14]
IFS0[15] IEC0[15]
19
00002Ah
20
12
13
14
15
16
17
18
19
20
21
22
23
24
25-26
27
28
29
30
31
32
33
34-35
36
37-42
43
44
45
46
47
48
49
50
51-52
00002Ch
21
00002Eh
22
000030h
NVM Program/Erase Complete _NVMInterrupt
23
000032h
I2C1 Slave Events
I2C1 Master Events
Comparator
_SI2C1Interrupt
_MI2C1Interrupt
_CompInterrupt
_IOCInterrupt
_INT1Interrupt
Reserved
24
000034h
IFS1[0]
IFS1[1]
IFS1[2]
IFS1[3]
IFS1[4]
—
IEC1[0]
IEC1[1]
IEC1[2]
IEC1[3]
IEC1[4]
—
25
000036h
26
000038h
Interrupt-on-Change Interrupt
External Interrupt 1
Reserved
27
00003Ah
28
00003Ch
29
00003Eh
Capture/Compare 5
Reserved
_CCP5Interrupt
Reserved
30
000040h
IFS1[6]
—
IEC1[6]
—
IPC5[10:8]
—
31
000042h
Direct Memory Access 2
Reserved
_DMA2Interrupt
Reserved
32
000044h
IFS1[8]
—
IEC1[8]
—
IPC6[2:0]
—
33-34
35
000046h-000048h
00004Ah
Timer4
_T4Interrupt
IFS1[11] IEC1[11]
IFS1[12] IEC1[12]
IFS1[13] IEC1[13]
IFS1[14] IEC1[14]
IFS1[15] IEC1[15]
IPC6[14:12]
IPC7[4:2]
IPC7[6:4]
IPC7[10:8]
IPC7[14:12]
IPC8[2:0]
IPC8[6:4]
—
Timer5
_T5Interrupt
36
00004Ch
External Interrupt 2
UART2 Receiver
UART2 Transmitter
SPI2 General
_INT2Interrupt
_U2RXInterrupt
_U2TXInterrupt
_SPI2Interrupt
_SPI2TXInterrupt
Reserved
37
00004Eh
38
000050h
39
000052h
40
000054h
IFS2[0]
IFS2[1]
—
IEC2[0]
IEC2[1]
—
SPI2 Transfer Done
Reserved
41
000056h
42-43
44
000058h-00005Ah
00005Ch
Direct Memory Access 3
Reserved
_DMA3Interrupt
Reserved
IFS2[4]
—
IEC2[4]
—
IPC9[2:0]
—
45-50
51
00005Eh-000068h
00006Ah
Capture/Compare/Timer3
Capture/Compare/Timer4
Reserved
_CCT3Interrupt
_CCT4Interrupt
Reserved
IFS2[11] IEC2[11] IPC10[14:12]
52
00006Ch
IFS2[12] IEC2[12]
IPC11[2:0]
—
53
00006Eh
—
—
Direct Memory Access 4
Capture/Compare/Timer5
Reserved
_DMA4Interrupt
_CCT5Interrupt
Reserved
54
000070h
IFS2[14] IEC2[14]
IPC11[10:8]
55
000072h
IFS2[15] IEC2[15] IPC11[14:12]
56
000074h
—
—
—
I2C2 Slave Events
I2C2 Master Events
Reserved
_SI2C2Interrupt
_MI2C2Interrupt
Reserved
57
000076h
IFS3[1]
IFS3[2]
—
IEC3[1]
IEC3[2]
—
IPC12[6:4]
IPC12[10:8]
—
58
000078h
59-60
00007Ah-00007Ch
2019-2020 Microchip Technology Inc.
DS30010198B-page 83
PIC24FJ128GL306 FAMILY
TABLE 8-2:
INTERRUPT VECTOR DETAILS (CONTINUED)
Interrupt Bit Location
®
MPLAB XC16
Vector
#
IRQ
#
Interrupt Description
IVT Address
ISR Name
Flag
Enable
Priority
External Interrupt 3
External Interrupt 4
Reserved
_INT3Interrupt
_INT4Interrupt
Reserved
61
62
53
54
00007Eh
000080h
IFS3[5]
IFS3[6]
—
IEC3[5]
IEC3[6]
—
IPC13[6:4]
IPC13[10:8]
—
63-65
66
55-57
58
000082h-000086h
000088h
SPI1 Receive Done
SPI2 Receive Done
Reserved
_SPI1RXInterrupt
_SPI2RXInterrupt
Reserved
IFS3[10] IEC3[10]
IPC14[10:8]
67
59
00008Ah
IFS3[11] IEC3[11] IPC14[14:12]
68
60
00008Ch
—
—
—
Direct Memory Access 5
_DMA5Interrupt
69
61
00008Eh
IFS3[13] IEC3[13]
IFS3[14] IEC3[14]
IPC15[6:4]
IPC15[10:8]
Real-Time Clock and Calendar _RTCCInterrupt
70
62
000090h
Capture/Compare 1
Capture/Compare 2
UART1 Error
_CCP1Interrupt
_CCP2Interrupt
_U1EInterrupt
_U2EInterrupt
_CRCInterrupt
Reserved
71
63
000092h
IFS3[15] IEC3[15] IPC15[14:12]
72
64
000094h
IFS4[0]
IFS4[1]
IFS4[2]
IFS4[3]
—
IEC4[0]
IEC4[1]
IEC4[2]
IEC4[3]
—
IPC16[2:0]
IPC16[6:4]
IPC16[10:8]
IPC16[14:12]
—
73
65
000096h
UART2 Error
74
66
000098h
Cyclic Redundancy Check
Reserved
75
67
00009Ah
76-79
80
68-71
72
00009Ch-0000A2h
0000A4h
High/Low-Voltage Detect
Reserved
_HLVDInterrupt
Reserved
IFS4[8]
—
IEC4[8]
—
IPC18[2:0]
—
81-88
89
73-80
81
0000A6h-0000B4h
0000B6h
UART3 Error
_U3EInterrupt
_U3RXInterrupt
_U3TXInterrupt
_I2C1BCInterrupt
_I2C2BCInterrupt
Reserved
IFS5[1]
IFS5[2]
IFS5[3]
IFS5[4]
IFS5[5]
—
IEC5[1]
IEC5[2]
IEC5[3]
IEC5[4]
IEC5[5]
—
IPC20[6:4]
IPC20[10:8]
IPC20[14:12]
IPC21[2:0]
IPC21[6:4]
—
UART3 Receiver
UART3 Transmitter
I2C1 Bus Collision
I2C2 Bus Collision
Reserved
90
82
0000B8h
91
83
0000BAh
92
84
0000BCh
93
85
0000BEh
94
86
0000C0h
UART4 Error
_U4EInterrupt
_U4RXInterrupt
_U4TXInterrupt
Reserved
95
87
0000C2h
IFS5[7]
IFS5[8]
IFS5[9]
—
IEC5[7]
IEC5[8]
IEC5[9]
—
IPC21[14:12]
IPC22[2:0]
IPC20[6:4]
—
UART4 Receiver
UART4 Transmitter
Reserved
96
88
0000C4h
97
89
0000C6h
98-101
102
103
104
105
106
107
108
109
90-93 0000C8h-0000CEh
Capture/Compare 3
Capture/Compare 4
Configurable Logic Cell 1
Configurable Logic Cell 2
Configurable Logic Cell 3
Configurable Logic Cell 4
LCD – Liquid Crystal Display
LCD Automation Timer
Reserved
_CCP3Interrupt
_CCP4Interrupt
_CLC1Interrupt
_CLC2Interrupt
_CLC3Interrupt
_CLC4Interrupt
_LCDInterrupt
_LCDATInterrupt
Reserved
94
95
0000D0h
0000D2h
0000D4h
0000D6h
0000D8h
0000DAh
0000DCh
0000DEh
IFS5[14] IEC5[14]
IPC23[10:8]
IFS5[15] IEC5[15] IPC23[14:12]
96
IFS6[0]
IFS6[1]
IFS6[2]
IFS6[3]
IFS6[4]
IFS6[5]
—
IEC6[0]
IEC6[1]
IEC6[2]
IEC6[3]
IEC6[4]
IEC6[5]
—
IPC24[2:0]
IPC24[6:4]
IPC24[10:8]
IPC24[14:12]
IPC25[2:0]
IPC25[6:4]
—
97
98
99
100
101
110-113 102-105 0000E0h-0000E6h
FRC Self-Tuning Interrupt
Reserved
_FSTInterrupt
Reserved
114
115
116
117
118
106
107
108
109
110
0000E8h
0000EAh
0000ECh
0000EEh
0000F0h
IFS6[10] IEC6[10]
IPC26[10:8]
—
—
—
ECC Single-Bit Error
Reserved
_ECCSBEInterrupt
Reserved
IFS6[12] IEC6[12]
IPC27[2:0]
—
—
—
Real-Time Clock Timestamp
Reserved
_RTCCTSInterrupt
Reserved
IFS6[14] IEC6[14]
IPC27[10:8]
—
119-124 111-116 0000F2h-0000FCh
125 117 0000FEh
—
—
JTAG
_JTAGInterrupt
IFS7[5]
IEC7[5]
IPC29[6:4]
DS30010198B-page 84
2019-2020 Microchip Technology Inc.
TABLE 8-3:
INTERRUPT FLAG REGISTERS
Register Address Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IFS0
IFS1
IFS2
IFS3
IFS4
IFS5
IFS6
IFS7
0088h
NVMIF
DMA1IF
U2RXIF
DMA4IF
RTCIF
—
AD1IF
INT2IF
—
U1TXIF
U1RXIF
T4IF
SPI1TXIF SPI1IF
T3IF
DMA2IF
—
T2IF
—
—
CCP5IF
—
—
—
DMA0IF
INT1IF
DMA3IF
—
T1IF
IOCIF
—
CCT2IF
CMIF
—
CCT1IF
MI2C1IF
SPI2TXIF
INT0IF
SI2C1IF
SPI2IF
—
008Ah U2TXIF
008Ch CCT5IF
008Eh CCP1IF
T5IF
—
—
—
—
CCT4IF
CCT3IF
—
—
DMA5IF
—
—
SPI2RXIF SPI1RXIF
—
—
—
INT4IF
—
INT3IF
—
—
MI2C2IF SI2C2IF
0090h
—
—
—
—
—
—
—
—
—
HLVDIF
U4RXIF
—
—
—
CRCIF
U2ERIF
U3RXIF
CLC3IF
—
U1ERIF
U3ERIF
CLC2IF
—
CCP2IF
—
0092h CCP4IF
CCP3IF
RTCCTSIF
—
—
—
ECCSBEIF
—
U4TXIF
—
U4ERIF
—
—
I2C2BCIF I2C1BCIF U3TXIF
0094h
0096h
—
—
—
FSTIF
—
—
LCDATIF
JTAGIF
LCDIF
—
CLC4IF
—
CLC1IF
—
—
—
—
—
—
TABLE 8-4:
INTERRUPT ENABLE REGISTERS
Register Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IEC0
IEC1
IEC2
IEC3
IEC4
IEC5
IEC6
IEC7
0098h
009Ah
009Ch
009Eh
00A0h
00A2h
00A4h
00A6h
NVMIE
U2TXIE
CCT5IE
CCP1IE
—
DMA1IE
U2RXIE
DMA4IE
RTCIE
—
AD1IE
INT2IE
—
U1TXIE
U1RXIE
T4IE
SPI1TXIE SPI1IE
T3IE
DMA2IE
—
T2IE
—
—
CCP5IE
—
—
—
DMA0IE
INT1IE
DMA3IE
—
T1IE
IOCIE
—
CCT2IE
CMIE
CCT1IE
MI2C1IE
SPI2TXIE
SI2C2IE
U1ERIE
U3ERIE
CLC2IE
—
INT0IE
SI2C1IE
SPI2IE
—
T5IE
—
—
—
—
—
—
CCT4IE
CCT3IE
—
—
—
DMA5IE
—
—
SPI2RXIE SPI1RXIE
—
—
INT4IE
—
INT3IE
—
—
MI2C2IE
—
—
—
—
—
—
—
HLVDIE
—
—
CRCIE U2ERIE
CCP2IE
—
CCP4IE
—
CCP3IE
RTCCTSIE
—
—
—
ECCSBEIE
—
U4TXIE U4RXIE U4ERIE
—
I2C2BCIE I2C1BCIE U3TXIE U3RXIE
—
FSTIE
—
—
—
—
—
—
—
—
LCDATIE
JTAGIE
LCDIE
—
CLC4IE CLC3IE
CLC1IE
—
—
—
—
—
—
TABLE 8-5:
INTERRUPT PRIORITY REGISTERS
Register Address Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IPC0
00A8h
00AAh
00ACh
00AEh
00B0h
00B2h
00B4h
00B6h
00B8h
00BAh
00BCh
00BEh
00C0h
00C2h
00C4h
00C6h
00C8h
00CAh
00CCh
00CEh
00D0h
00D2h
00D4h
00D6h
00D8h
00DAh
00DCh
00DEh
00E0h
00E2h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T1IP[2:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCT2IP[2:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCT1IP[2:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT0IP[2:0]
DMA0IP[2:0]
T3IP[2:0]
U1TXIP[2:0]
SI2C1IP[2:0]
INT1IP[2:0]
DMA2IP[2:0]
T5IP[2:0]
SPI2IP[2:0]
DMA3IP[2:0]
—
IPC1
T2IP[2:0]
—
—
—
—
—
IPC2
U1RXIP[2:0]
SPI1TXIP[2:0]
DMA1IP[2:0]
CMIP[2:0]
CCP5IP[2:0]
—
SPI1IP[2:0]
IPC3
NVMIP[2:0]
AD1IP[2:0]
IPC4
IOCIP[2:0]
MI2C1IP[2:0]
IPC5
—
—
—
—
—
—
—
—
IPC6
T4IP[2:0]
—
—
—
IPC7
U2TXIP[2:0]
U2RXIP[2:0]
—
INT2IP[2:0]
IPC8
—
—
—
—
—
—
—
—
—
—
—
SPI2TXIP[2:0]
IPC9
—
—
—
—
—
—
—
—
—
IPC10
IPC11
IPC12
IPC13
IPC14
IPC15
IPC16
IPC17
IPC18
IPC19
IPC20
IPC21
IPC22
IPC23
IPC24
IPC25
IPC26
IPC27
IPC28
IPC29
CCT3IP[2:0]
—
—
—
—
CCT5IP[2:0]
DMA4IP[2:0]
MI2C2IP[2:0]
INT4IP[2:0]
SPI1RXIP[2:0]
RTCIP[2:0]
U2ERIP[2:0]
—
—
SI2C2IP[2:0]
INT3IP[2:0]
—
CCT4IP[2:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SPI2RXIP[2:0]
—
—
—
CCP1IP[2:0]
DMA5IP[2:0]
U1ERIP[2:0]
—
—
CRCIP[2:0]
CCP2IP[2:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
HLVDIP[2:0]
—
—
—
—
—
—
—
—
U3TXIP[2:0]
U3RXIP[2:0]
—
U3ERIP[2:0]
I2C2BCIP[2:0]
U4TXIP[2:0]
—
—
U4TXIP[2:0]
—
—
—
—
I2C1BCIP[2:0]
U4RXIP[2:0]
—
—
—
—
—
CCP4IP[2:0]
CCP3IP[2:0]
CLC3IP[2:0]
—
—
—
—
—
—
—
CLC4IP[2:0]
CLC2IP[2:0]
LCDATIP[2:0]
—
CLC1IP[2:0]
LCDIP[2:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FSTIP[2:0]
RTCCTSIP[2:0]
—
—
—
—
—
—
—
—
ECCSBEIP[2:0]
—
—
—
—
—
—
—
—
—
—
—
JTAGIP[2:0]
—
PIC24FJ128GL306 FAMILY
8.4.3
IECx
8.3
Interrupt Resources
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
Many useful resources are provided on the main
product page of the Microchip website for the devices
listed in this data sheet.
8.4.4
IPCx
8.3.1
KEY RESOURCES
The IPCx registers are used to set the Interrupt Priority
Level (IPL) for each source of interrupt. Each user
interrupt source can be assigned to one of eight priority
levels.
• “Interrupts” (www.microchip.com/DS70000600)
in the “dsPIC33/PIC24 Family Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
8.4.5
INTTREG
The INTTREG register contains the associated
interrupt vector number and the new CPU Interrupt Pri-
ority Level, which are latched into the Vector Number
bits (VECNUM[7:0]) and Interrupt Priority Level bits
(ILR[3:0]) fields in the INTTREG register. The new
Interrupt Priority Level is the priority of the pending
interrupt.
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
8.4
Interrupt Control and Status
Registers
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence as they are
listed in Table 8-2. For example, the INT0 (External
Interrupt 0) is shown as having Vector Number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0[0], the INT0IE bit in IEC0[0] and the INT0IPx
bits in the first position of IPC0 (IPC0[2:0]).
PIC24FJ128GL306 family devices implement the
following registers for the interrupt controller:
• INTCON1
• INTCON2
• INTCON4
• IFS0 through IFS7
• IEC0 through IEC7
• IPC0 through ICP29
• INTTREG
8.4.6
STATUS/CONTROL REGISTERS
Although these registers are not specifically part of the
interrupt control hardware, two of the CPU Control
registers contain bits that control interrupt functionality.
For more information on these registers, refer to
“CPU with Extended Data Space (EDS)”
(www.microchip.com/DS39732) in the “dsPIC33/PIC24
Family Reference Manual”.
8.4.1
INTCON1-INTCON4
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit, as well as the
control and status flags for the processor trap sources.
• The CPU STATUS Register, SR, contains the
IPL[2:0] bits (SR[7:5]). These bits indicate the
current CPU Interrupt Priority Level. The user
software can change the current CPU Interrupt
Priority Level by writing to the IPLx bits.
The INTCON2 register controls global interrupt gener-
ation, the external interrupt request signal behavior and
the use of the Alternate Interrupt Vector Table (AIVT).
The INTCON3 register contains the Deadman Timer
(DMT) trap bit. The INTCON4 register contains the
Software Generated Hard Trap (SGHT) bit and the
ECC Double-Bit Error (ECCDBE) trap bit.
• The CORCON register contains the IPL3 bit,
which together with the IPL[2:0] bits, also indi-
cates the current CPU Interrupt Priority Level.
IPL3 is a read-only bit so that trap events cannot
be masked by the user software.
8.4.2
IFSx
All Interrupt registers are described in Register 8-3
through Register 8-7 in the following pages.
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal, and
is cleared via software.
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REGISTER 8-1:
SR: ALU STATUS REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
DC
bit 15
bit 8
R/W-0(3)
IPL2(2)
bit 7
R/W-0(3)
IPL1(2)
R/W-0(3)
IPL0(2)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’= Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
IPL[2:0]: CPU Interrupt Priority Level Status bits(2,3)
111= CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
Note 1: For complete register details, see Register 3-1.
2: The IPL[2:0] Status bits are concatenated with the IPL3 Status bit (CORCON[3]) to form the CPU Interrupt
Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. User interrupts are
disabled when IPL3 = 1.
3: The IPL[2:0] Status bits are read-only when the NSTDIS bit (INTCON1[15]) = 1.
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REGISTER 8-2:
CORCON: CPU CORE CONTROL REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
R/C-0
IPL3(2)
R/W-1
PSV
U-0
—
U-0
—
bit 7
Legend:
C = Clearable bit
W = Writable bit
‘1’= Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 3
Unimplemented: Read as ‘0’
IPL3: CPU Interrupt Priority Level Status bit(2)
1= CPU Interrupt Priority Level is greater than 7
0= CPU Interrupt Priority Level is 7 or less
bit 2
PSV: Not used as part of the interrupt module
Unimplemented: Read as ‘0’
bit 1-0
Note 1: For complete register details, see Register 3-2.
2: The IPL[2:0] Status bits are concatenated with the IPL3 Status bit (CORCON[3]) to form the CPU Interrupt
Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. User interrupts are
disabled when IPL3 = 1.
2019-2020 Microchip Technology Inc.
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REGISTER 8-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
NSTDIS
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 8
bit 0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
MATHERR
ADDRERR
STKERR
OSCFAIL
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
NSTDIS: Interrupt Nesting Disable bit
1= Interrupt nesting is disabled
0= Interrupt nesting is enabled
bit 14-5
bit 4
Unimplemented: Read as ‘0’
MATHERR: Math Error Status bit
1= Math error trap has occurred
0= Math error trap has not occurred
bit 3
bit 2
bit 1
bit 0
ADDRERR: Address Error Trap Status bit
1= Address error trap has occurred
0= Address error trap has not occurred
STKERR: Stack Error Trap Status bit
1= Stack error trap has occurred
0= Stack error trap has not occurred
OSCFAIL: Oscillator Failure Trap Status bit
1= Oscillator failure trap has occurred
0= Oscillator failure trap has not occurred
Unimplemented: Read as ‘0’
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REGISTER 8-4:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
GIE
R-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
DISI
SWTRAP
AIVTEN
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
GIE: Global Interrupt Enable bit
1= Interrupts and associated interrupt enable bits are enabled
0= Interrupts are disabled, but traps are still enabled
DISI: DISIInstruction Status bit
1= DISIinstruction is active
0= DISIinstruction is not active
SWTRAP: Software Trap Status bit
1= Software trap is enabled
0= Software trap is disabled
bit 12-9
bit 8
Unimplemented: Read as ‘0’
AIVTEN: Alternate Interrupt Vector Table Enable bit
1= Uses Alternate Interrupt Vector Table (if enabled in Configuration bits)
0= Uses standard Interrupt Vector Table (default)
bit 7-5
bit 4
Unimplemented: Read as ‘0’
INT4EP: External Interrupt 4 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
bit 3
bit 2
bit 1
bit 0
INT3EP: External Interrupt 3 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
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REGISTER 8-5:
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-0
DMT
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
DMT: Deadman Timer (soft) Trap Status bit
1= Deadman Timer trap has occurred
0= Trap has not occurred
bit 14-0
Unimplemented: Read as ‘0’
REGISTER 8-6:
INTCON4: INTERRUPT CONTROL REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/C-0
R/C-0
SGHT
ECCDBE
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-2
bit 1
Unimplemented: Read as ‘0’
ECCDBE: ECC Double-Bit Error Trap bit
1= ECC double-bit error trap has occurred
0= ECC double-bit error trap has not occurred
bit 0
SGHT: Software Generated Hard Trap Status bit
1= Software generated hard trap has occurred
0= Software generated hard trap has not occurred
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REGISTER 8-7:
INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
R-0
CPUIRQ
bit 15
U-0
—
R/W-0
U-0
—
R-0
R-0
R-0
R-0
VHOLD
ILR3
ILR2
ILR1
ILR0
bit 8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
VECNUM[7:0]
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CPUIRQ: Interrupt Request from Interrupt Controller to CPU bit
1= An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens
when the CPU priority is higher than the interrupt priority
0= No interrupt request is unacknowledged
bit 14
bit 13
Unimplemented: Read as ‘0’
VHOLD: Vector Number Capture Configuration bit
1= The VECNUMx bits contain the value of the highest priority pending interrupt
0= The VECNUMx bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt
that has occurred with higher priority than the CPU, even if other interrupts are pending)
bit 12
Unimplemented: Read as ‘0’
bit 11-8
ILR[3:0]: New CPU Interrupt Priority Level bits
1111= CPU Interrupt Priority Level is 15
•
•
•
0001= CPU Interrupt Priority Level is 1
0000= CPU Interrupt Priority Level is 0
bit 7-0
VECNUM[7:0]: Vector Number of Pending Interrupt bits
11111111= 255, Reserved; do not use
•
•
•
00001001= 9, CCT1, MCCP1 timer
00001000= 8, INT0 – External Interrupt 0
00000111= 7, Reserved; do not use
00000110= 6, Generic soft error trap
00000101= 5, Reserved; do not use
00000100= 4, Math error trap
00000011= 3, Stack error trap
00000010= 2, Generic hard trap
00000001= 1, Address error trap
00000000= 0, Oscillator fail trap
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NOTES:
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• Software-Controllable Switching between Various
Clock Sources
9.0
OSCILLATOR CONFIGURATION
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices.
It is not intended to be a comprehensive
reference source. For more information,
refer to “Oscillator” (www.microchip.com/
DS39700) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in this
data sheet supersedes the information in
the FRM.
• Software-Controllable Postscaler for Selective
Clocking of CPU for System Power Savings
• A Fail-Safe Clock Monitor (FSCM) that Detects
Clock Failure and Permits Safe Application
Recovery or Shutdown
• ASeparate and Independently Configurable System
Clock Output for Synchronizing External Hardware
A simplified diagram of the oscillator system is shown
in Figure 9-1.
The oscillator system for the PIC24FJ128GL306 family
devices have the following features:
• An On-Chip PLL Block to Provide a Range of
Frequency Options for the System Clock
FIGURE 9-1:
PIC24FJ128GL306 FAMILY CLOCK DIAGRAM
PIC24FJ128GL306 Family
Primary Oscillator
XT, HS, EC
OSCO
OSCI
PLL
Peripheral Clock
FOSC to MCCPs
XTPLL, HSPLL
ECPLL,FRCPLL
PLL and
DIV
PLLMODE[3:0]
CPDIV[1:0]
OSCFDIV
÷2
÷ n
FP to Peripherals
FCY
RCDIV[2:0] DIV[14:0]
FCY
to CPU
Secondary Oscillator
SOSC
LPRC
FRC
SOSCO
SOSCI
SOSCEN
Enable
Oscillator
DOZE[14:12]
32 kHz
LPRC
Oscillator
Clock Control Logic
FSCM
8 kHz
31.25 kHz
Divider
FRC
Timer, CCP, RTCC, CLC, WDT, PWRT
WDT, RTCC, CLC
FRC
Self-Tune
Control
WDT, Other Modules
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9.1
CPU Clocking Scheme
9.2
Initial Configuration on POR
The system clock source can be provided by one of
four sources:
The oscillator source (and operating mode) that is used
at a device Power-on Reset event is selected using
Configuration bit settings. The Oscillator Configuration
bit settings are located in the Configuration registers in
the program memory (refer to Section 27.1 “Configu-
ration Bits” for further details). The Primary Oscillator
Configuration bits, POSCMD[1:0] (FOSC[1:0]), and the
Oscillator Select Configuration bits, FNOSC[2:0]
(FOSCSEL[2:0]), select the oscillator source that is
used at a Power-on Reset. The OSCFDIV clock source
is the default (unprogrammed) selection; the default
input source to the OSCFDIV divider is the FRC
clock source. Other oscillators may be chosen by
programming these bit locations.
• Primary Oscillator (POSC) on the OSCI and
OSCO pins
• Secondary Oscillator (SOSC) on the SOSCI and
SOSCO pins
• Fast Internal RC (FRC) Oscillator
• Low-Power Internal RC (LPRC) Oscillator
The Primary Oscillator and FRC sources have the
option of using the internal PLL block, which can
generate a 4x, 6x or 8x PLL clock. If the PLL is used,
the PLL clocks can then be postscaled, if necessary,
and used as the system clock. Refer to Section 9.7
“Oscillator Modes” for additional information. The
internal FRC provides an 8 MHz clock source.
The Configuration bits allow users to choose between
the various Clock modes shown in Table 9-1.
Each clock source (XTPLL, ECPLL, FRCPLL, HS, XT,
EC, FRC, LPRC and SOSC) can be used as an input
to an additional divider, which can then be used to
produce a divided clock source for use as a system
clock (OSCFDIV).
9.2.1
CLOCK SWITCHING MODE
CONFIGURATION BITS
The FCKSM[1:0] Configuration bits (FOSC[7:6]) are
used to jointly configure device clock switching and the
Fail-Safe Clock Monitor (FSCM). Clock switching is
enabled only when FCKSM1 is programmed (‘0’). The
FSCM is enabled only when FCKSM[1:0] are both
programmed (‘00’).
The selected clock source generates the processor
and peripheral clock sources. The processor clock
source is divided by two to produce the internal instruc-
tion cycle clock, FCY. In this document, the instruction
cycle clock is also denoted by FOSC/2. The internal
instruction cycle clock, FOSC/2, can be provided on the
OSCO I/O pin for some operating modes of the Primary
Oscillator.
TABLE 9-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator Source
POSCMD[1:0]
FNOSC[2:0]
Notes
1, 2, 3
Oscillator with Frequency Division
(OSCFDIV)
Internal/External
11
111
Low-Power RC Oscillator (LPRC)
Internal
11
11
101
100
3
3
Secondary (Timer1) Oscillator
(SOSC)
Secondary
Primary Oscillator (XT) with PLL
Module (XTPLL)
Primary
Primary
01
00
011
011
Primary Oscillator (EC) with PLL
Module (ECPLL)
Primary Oscillator (HS)
Primary Oscillator (XT)
Primary Oscillator (EC)
Primary
Primary
Primary
Internal
10
01
00
11
010
010
010
001
Fast RC Oscillator with PLL Module
(FRCPLL)
3
3
Fast RC Oscillator (FRC)
Internal
11
000
Note 1: The input oscillator to the OSCFDIV Clock mode is determined by the RCDIV[2:0] (CLKDIV[10:8) bits. At
POR, the default value selects the FRC module.
2: This is the default Oscillator mode for an unprogrammed (erased) device.
3: OSCO pin function is determined by the OSCIOFNC Configuration bit.
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The CLKDIV register (Register 9-2) controls the
features associated with Doze mode, as well as the
postscalers for the OSCFDIV Clock mode and the PLL
module.
9.3
Control Registers
The operation of the oscillator is controlled by five
Special Function Registers:
• OSCCON
• CLKDIV
The OSCTUN register (Register 9-3) allows the user to
fine-tune the FRC Oscillator over
approximately ±1.5%.
a range of
• OSCTUN
• OSCDIV
• OSCFDIV
The OSCDIV and OSCFDIV registers provide control
for the system oscillator frequency divider.
The OSCCON register (Register 9-1) is the main control
register for the oscillator. It controls clock source
switching and allows the monitoring of clock sources.
OSCCON is protected by a write lock to prevent
inadvertent clock switches. See Section 9.4 “Clock
Switching Operation” for more information.
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REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER(1)
U-0
—
R-x(2)
R-x(2)
R-x(2)
U-0
—
R/W-x(2)
NOSC2
R/W-x(2)
NOSC1
R/W-x(2)
NOSC0
COSC2
COSC1
COSC0
bit 15
bit 8
R/W-0
R/W-0
R-0(4)
LOCK
U-0
—
R/CO-0
CF
R/W-0
R/W-0
R/W-0
CLKLOCK(5) IOLOCK(3)
POSCEN
SOSCEN
OSWEN
bit 7
bit 0
Legend:
CO = Clearable Only bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC[2:0]: Current Oscillator Selection bits(2)
111= Oscillator with Frequency Divider (OSCFDIV)
110= Reserved
101= Low-Power RC Oscillator (LPRC)
100= Secondary Oscillator (SOSC)
011= Primary Oscillator with PLL module (XTPLL, ECPLL)
010= Primary Oscillator (XT, HS, EC)
001= Fast RC Oscillator with PLL module (FRCPLL)
000= Fast RC Oscillator (FRC)
bit 11
Unimplemented: Read as ‘0’
bit 10-8
NOSC[2:0]: New Oscillator Selection bits(2)
111= Oscillator with Frequency Divider (OSCFDIV)
110= Reserved
101= Low-Power RC Oscillator (LPRC)
100= Secondary Oscillator (SOSC)
011= Primary Oscillator with PLL module (XTPLL, ECPLL)
010= Primary Oscillator (XT, HS, EC)
001= Fast RC Oscillator with PLL module (FRCPLL)
000= Fast RC Oscillator (FRC)
bit 7
bit 6
CLKLOCK: Clock Selection Lock Enable bit(5)
If FSCM is Enabled (FCKSM[1:0] = 00):
1= Clock and PLL selections are locked
0= Clock and PLL selections are not locked and may be modified by setting the OSWEN bit
If FSCM is Disabled (FCKSM[1:0] = 1x):
Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
IOLOCK: I/O Lock Enable bit(3)
1= I/O lock is active
0= I/O lock is not active
Note 1: OSCCON is protected by a write lock to prevent inadvertent clock switches. See Section 9.4 “Clock
Switching Operation” for more information.
2: Reset values for these bits are determined by the FNOSCx Configuration bits.
3: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared.
4: This bit also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.
5: When CLKLOCK is set, the NOSC[2:0], OSWEN, CPDIV[1:0] and PLLEN bits cannot be modified.
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REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED)
bit 5
LOCK: PLL Lock Status bit(4)
1= PLL module is in lock or PLL module start-up timer is satisfied
0= PLL module is out of lock, PLL start-up timer is running or PLL is disabled
bit 4
bit 3
Unimplemented: Read as ‘0’
CF: Clock Fail Detect bit
1= FSCM has detected a clock failure
0= No clock failure has been detected
bit 2
bit 1
bit 0
POSCEN: Primary Oscillator Sleep Enable bit
1= Primary Oscillator continues to operate during Sleep mode
0= Primary Oscillator is disabled during Sleep mode
SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit
1= Enables Secondary Oscillator
0= Disables Secondary Oscillator
OSWEN: Oscillator Switch Enable bit
1= Initiates an oscillator switch to a clock source specified by the NOSC[2:0] bits
0= Oscillator switch is complete
Note 1: OSCCON is protected by a write lock to prevent inadvertent clock switches. See Section 9.4 “Clock
Switching Operation” for more information.
2: Reset values for these bits are determined by the FNOSCx Configuration bits.
3: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In
addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared.
4: This bit also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.
5: When CLKLOCK is set, the NOSC[2:0], OSWEN, CPDIV[1:0] and PLLEN bits cannot be modified.
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REGISTER 9-2:
CLKDIV: CLOCK DIVIDER REGISTER
R/W-0
ROI
R/W-0
R/W-1
R/W-1
R/W-0
DOZEN(1)
R/W-0
R/W-0
R/W-0
DOZE2
DOZE1
DOZE0
RCDIV2
RCDIV1
RCDIV0
bit 15
bit 8
R/W-0
CPDIV1
bit 7
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
CPDIV0
PLLEN
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
ROI: Recover on Interrupt bit
1= Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1
0= Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE[2:0]: CPU Peripheral Clock Ratio Select bits
111= 1:128
110= 1:64
101= 1:32
100= 1:16
011= 1:8 (default)
010= 1:4
001= 1:2
000= 1:1
bit 11
DOZEN: Doze Enable bit(1)
1= DOZE[2:0] bits specify the CPU peripheral clock ratio
0= CPU peripheral clock ratio is set to 1:1
bit 10-8
RCDIV[2:0]: System Frequency Divider Clock Source Select bits
111= Reserved; do not use
110= Reserved
101= Low-Power RC Oscillator (LPRC)
100= Secondary Oscillator (SOSC)
011= Primary Oscillator (XT, HS, EC) with PLL module (XTPLL, HSPLL, ECPLL)
010= Primary Oscillator (XT, HS, EC)
001= Fast RC Oscillator (FRC) with PLL module (FRCPLL)
000= Fast RC Oscillator (FRC)
bit 7-6
CPDIV[1:0]: System Clock Select bits (postscaler select from PLL, 32 MHz clock branch)
11= 4 MHz (divide-by-8)
10= 8 MHz (divide-by-4)
01= 16 MHz (divide-by-2)
00= 32 MHz (divide-by-1)
bit 5
PLLEN: PLL Enable bit
1= PLL is always active
0= PLL is only active when a PLL Oscillator mode is selected (OSCCON[14:12] = 011or 001)
bit 4-0
Unimplemented: Read as ‘0’
Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
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REGISTER 9-3:
OSCTUN: FRC OSCILLATOR TUNE REGISTER
R/W-0
STEN
U-0
—
R/W-0
R/W-0
STSRC(1)
R/W-0
R/W-0
R/W-0
STOR
R/W-0
STSIDL
STLOCK
STLPOL
STORPOL
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN[5:0](2)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
STEN: FRC Self-Tune Enable bit
1= FRC self-tuning is enabled; TUNx bits are controlled by hardware
0= FRC self-tuning is disabled; application may optionally control the TUNx bits
bit 14
bit 13
Unimplemented: Read as ‘0’
STSIDL: FRC Self-Tune Stop in Idle bit
1= Self-tuning stops during Idle mode
0= Self-tuning continues during Idle mode
bit 12
bit 11
bit 10
bit 9
STSRC: FRC Self-Tune Reference Clock Source bit(1)
1= Reserved
0= FRC is an approximate match to the 32.768 kHz SOSC tolerance
STLOCK: FRC Self-Tune Lock Status bit
1= FRC accuracy is currently within ±0.2% of the STSRC reference accuracy
0= FRC accuracy may not be within ±0.2% of the STSRC reference accuracy
STLPOL: FRC Self-Tune Lock Interrupt Polarity bit
1= A self-tune lock interrupt is generated when STLOCK is ‘0’
0= A self-tune lock interrupt is generated when STLOCK is ‘1’
STOR: FRC Self-Tune Out of Range Status bit
1= STSRC reference clock error is beyond the range of TUN[5:0]; no tuning is performed
0= STSRC reference clock is within the tunable range; tuning is performed
bit 8
STORPOL: FRC Self-Tune Out of Range Interrupt Polarity bit
1= A self-tune out of range interrupt is generated when STOR is ‘0’
0= A self-tune out of range interrupt is generated when STOR is ‘1’
bit 7-6
Unimplemented: Read as ‘0’
Note 1: Use of either clock tuning reference source has specific application requirements. See Section 9.6 “FRC
Active Clock Tuning” for details.
2: These bits are read-only when STEN = 1.
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REGISTER 9-3:
OSCTUN: FRC OSCILLATOR TUNE REGISTER (CONTINUED)
bit 5-0
TUN[5:0]: FRC Oscillator Tuning bits(2)
011111= Maximum frequency deviation
011110=
•
•
•
000001=
000000= Center frequency oscillator is running at factory calibrated frequency
111111=
•
•
•
100001=
100000= Minimum frequency deviation
Note 1: Use of either clock tuning reference source has specific application requirements. See Section 9.6 “FRC
Active Clock Tuning” for details.
2: These bits are read-only when STEN = 1.
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REGISTER 9-4:
OSCDIV: OSCILLATOR DIVISOR REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-1
DIV[14:8]
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
DIV[7:0]
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
DIV[14:0]: Reference Clock Divider bits
bit 14-0
Specifies the 1/2 period of the reference clock in the source clocks
(ex: Period of ref_clk_output = [Reference Source * 2] * DIV[14:0]).
111111111111111= Oscillator frequency divided by 65,534 (32,767 * 2)
111111111111110= Oscillator frequency divided by 65,532 (32,766 * 2)
•
•
•
000000000000011= Oscillator frequency divided by 6 (3 * 2)
000000000000010= Oscillator frequency divided by 4 (2 * 2)
000000000000001= Oscillator frequency divided by 2 (1 * 2) (default)
000000000000000= Oscillator frequency is unchanged (no divider)
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REGISTER 9-5:
OSCFDIV: OSCILLATOR FRACTIONAL DIVISOR REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
TRIM[0:7]
bit 15
R/W-0
TRIM8
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
TRIM[0:8] Trim bits
Provides fractional additive to the DIV[14:0] bits value for the 1/2 period of the oscillator clock.
0000_0000_0= 0/512 (0.0) divisor added to DIVx value
0000_0000_1= 1/512 (0.001953125) divisor added to DIVx value
0000_0001_0= 2/512 (0.00390625) divisor added to DIVx value
•
•
•
100000000 = 256/512 (0.5000) divisor added to DIVx value
•
•
•
1111_1111_0= 510/512 (0.99609375) divisor added to DIVx value
1111_1111_1= 511/512 (0.998046875) divisor added to DIVx value
bit 6-0
Unimplemented: Read as ‘0’
Note 1: TRIMx values greater than zero are ONLY valid when DIVx values are greater than zero.
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Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
9.4
Clock Switching Operation
With few limitations, applications are free to switch
between any of the four clock sources (POSC, SOSC,
FRC and LPRC) under software control and at any
time. To limit the possible side effects that could result
from this flexibility, PIC24F devices have a safeguard
lock built into the switching process.
1. The clock switching hardware compares the
COSCx bits with the new value of the NOSCx
bits. If they are the same, then the clock switch
is a redundant operation. In this case, the
OSWEN bit is cleared automatically and the
clock switch is aborted.
Note:
The Primary Oscillator mode has three
different submodes (XT, HS and EC),
which are determined by the POSCMDx
Configuration bits. While an application
can switch to and from Primary Oscillator
mode in software, it cannot switch
between the different primary submodes
without reprogramming the device.
2. If a valid clock switch has been initiated, the
LOCK (OSCCON[5]) and CF (OSCCON[3]) bits
are cleared.
3. The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware will wait until
the OST expires. If the new source is using the
PLL, then the hardware waits until a PLL lock is
detected (LOCK = 1).
9.4.1
ENABLING CLOCK SWITCHING
4. The hardware waits for ten clock cycles from the
new clock source and then performs the clock
switch.
To enable clock switching, the FCKSM1 Configuration
bit in FOSC must be programmed to ‘0’. (Refer to
Section 27.1 “Configuration Bits” for further details.)
If the FCKSM1 Configuration bit is unprogrammed (‘1’),
the clock switching function and Fail-Safe Clock
Monitor function are disabled; this is the default setting.
5. The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the NOSCx
bits value is transferred to the COSCx bits.
6. The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM is
enabled) or SOSC (if SOSCEN remains set).
The NOSCx control bits (OSCCON[10:8]) do not control
the clock selection when clock switching is disabled.
However, the COSC[2:0] bits (OSCCON[14:12]) will
reflect the clock source selected by the FNOSCx
Configuration bits.
Note 1: The processor will continue to execute
code throughout the clock switching
sequence. Timing-sensitive code should
not be executed during this time.
The OSWEN control bit (OSCCON[0]) has no effect
when clock switching is disabled; it is held at ‘0’ at all
times.
2: Direct clock switches between any
Primary Oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transitional
clock source between the two PLL modes.
9.4.2
OSCILLATOR SWITCHING
SEQUENCE
At a minimum, performing a clock switch requires this
basic sequence:
1. If
desired,
read
the
COSCx
bits
(OSCCON[14:12]) to determine the current
oscillator source.
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte.
3. Write the appropriate value to the NOSCx bits
(OSCCON[10:8]) for the new oscillator source.
4. Perform the unlock sequence to allow a write to
the OSCCON register low byte.
5. Set the OSWEN bit to initiate the oscillator
switch.
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A recommended code sequence for a clock switch
includes the following:
9.5
Fail-Safe Clock Monitoring
The Fail-Safe Clock Monitor (FSCM) detects clock
failures. In case of a clock problem, the Fail-Safe Clock
Monitor switches the clock to the on-chip Low-Power
RC (LPRC) Oscillator and generates the oscillator trap.
1. Disable interrupts during the OSCCON register
unlock and write sequence.
2. Execute the unlock sequence for the OSCCON
high byte by writing 78h and 9Ah to
OSCCON[15:8] in two back-to-back instructions.
To enable clock switching, the FCKSM[1:0]
Configuration bits in the FOSC register must be
programmed to ‘00’.
3. Write the new oscillator source to the NOSCx
bits in the instruction immediately following the
unlock sequence.
9.6
FRC Active Clock Tuning
4. Execute the unlock sequence for the OSCCON
low byte by writing 46h and 57h to OSCCON[7:0]
in two back-to-back instructions.
PIC24FJ128GL306 family devices include an auto-
matic mechanism to calibrate the FRC during run time.
This system uses active clock tuning from a source of
known accuracy to maintain the FRC within a very
narrow margin of its nominal 8 MHz frequency.
5. Set the OSWEN bit in the instruction immediately
following the unlock sequence.
6. Continue to execute code that is not clock-sensitive
(optional).
The self-tune system is controlled by the bits in the
upper half of the OSCTUN register. Setting the STEN
bit (OSCTUN[15]) enables the self-tuning feature,
allowing the hardware to calibrate to a source selected
by the STSRC bit (OSCTUN[12]).
7. Invoke an appropriate amount of software delay
(cycle counting) to allow the selected oscillator
and/or PLL to start and stabilize.
8. Check to see if OSWEN is ‘0’. If it is, the switch
was successful. If OSWEN is still set, then
check the LOCK bit to determine the cause of
the failure.
When STSRC = 0, the system uses the crystal-
controlled SOSC for its calibration source. Regardless
of the source, the system uses the TUN[5:0] bits
(OSCTUN[5:0]) to change the FRC Oscillator’s
frequency. Frequency monitoring and adjustment are
dynamic, occurring continuously during run time. While
the system is active, the TUNx bits cannot be written to
by software.
The core sequence for unlocking the OSCCON register
and initiating a clock switch is shown in Example 9-1.
EXAMPLE 9-1:
BASIC CODE SEQUENCE
FOR CLOCK SWITCHING
The self-tune system can generate a hardware inter-
rupt, FSTIF. The interrupt can result from a drift of the
FRC, from the reference, by greater than 0.2% in either
direction, or whenever the frequency deviation is
beyond the ability of the TUN[5:0] bits to correct (i.e.,
greater than 1.5%). The STLOCK and STOR status bits
(OSCTUN[11,9]) are used to indicate these conditions.
;Place the new oscillator selection in W0
;OSCCONH (high byte) Unlock Sequence
MOV
MOV
MOV
MOV.b
MOV.b
#OSCCONH, w1
#0x78, w2
#0x9A, w3
w2, [w1]
w3, [w1]
;Set new oscillator selection
MOV.b WREG, OSCCONH
;OSCCONL (low byte) unlock sequence
The STLPOL and STORPOL bits (OSCTUN[10,8])
configure the FSTIF interrupt to occur in the presence
or the absence of the conditions. It is the user’s respon-
sibility to monitor both the STLOCK and STOR bits to
determine the exact cause of the interrupt.
MOV
MOV
MOV
MOV.b
MOV.b
#OSCCONL, w1
#0x46, w2
#0x57, w3
w2, [w1]
Note:
The STLPOL and STORPOL bits should
be ignored when the self-tune system is
disabled (STEN = 0).
w3, [w1]
;Start oscillator switch operation
BSET OSCCON, #0
// or use XC16 built-in macro:
// Initiate Clock Switch to Primary
//Oscillator with PLL (NOSC=0b011)
__builtin_write_OSCCONH(0x03);
__builtin_write_OSCCONL(OSCCON | 0x01);
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TABLE 9-3:
VALID PRIMARY OSCILLATOR
CONFIGURATIONS
9.7
Oscillator Modes
The PLL block is shown in Figure 9-2. In this system,
the input from the Primary Oscillator is divided down by
a PLL prescaler to generate a 4 MHz output. This is
used to drive an on-chip, 96 MHz PLL frequency multi-
plier to drive the fixed, divide-by-3 frequency divider
and configurable PLL prescaler/divider to generate a
range of system clock frequencies. The CPDIV[1:0] bits
select the system clock speed. Available clock options
are listed in Table 9-2.
Input Oscillator
Frequency
PLL Mode
Clock Mode
(PLLMODE[3:0])
48 MHz
32 MHz
24 MHz
20 MHz
16 MHz
12 MHz
8 MHz
ECPLL
12 (0111)
8 (0110)
6 (0101)
5 (0100)
4 (0011)
3 (0010)
2 (0001)
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
HSPLL, ECPLL
The user must manually configure the PLL divider to
generate the required 4 MHz output using the
PLLMODE[3:0] Configuration bits. This limits the
choices for Primary Oscillator frequency to a total of
eight possibilities, as shown in Table 9-3.
ECPLL, XTPLL,
FRCPLL
4 MHz
ECPLL, XTPLL,
FRCPLL
1 (0000)
TABLE 9-2:
SYSTEM CLOCK OPTIONS
MCU Clock Division
(CPDIV[1:0])
Microcontroller
Clock Frequency
None (00)
2 (01)
4 (10)
8 (11)
32 MHz
16 MHz
8 MHz
4 MHz
FIGURE 9-2:
PLL BLOCK
PLLMODE[3:0]
(Note 1)
12
0111
0110
0101
0100
0011
0010
0001
0000
8
6
5
4
3
2
1
Input from
POSC
8
4
2
1
11
PLL Output
4 MHz
32 MHz
10 for System Clock
01
00
96 MHz
PLL
Input from
FRC
3
CPDIV[1:0]
1100
1101
1110
x4
x6
x8
Note 1: This MUX is controlled by the COSC[2:0] bits when running from the PLL or the NOSC[2:0] bits when
preparing to switch to the PLL.
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clock signal is needed. The SOSC, however, has a long
start-up time (as long as one second). To avoid delays
for peripheral start-up, the SOSC can be manually
started using the SOSCEN bit.
9.8
Primary Oscillator (PRI or POSC)
The PIC24FJ128GL306 family devices feature a
Primary Oscillator (POSC), which is available on the
OSCI and OSCO pins. This connection enables an
external crystal (or ceramic resonator) to provide the
clock to the device. The Primary Oscillator provides
three modes of operation:
To use the Secondary Oscillator, the SOSCSEL bit
(FOSC[3]) must be set to ‘1’. Programming the
SOSCSEL bit to ‘0’ configures the SOSC pins for Digital
mode, enabling digital I/O functionality on the pins.
• Medium Speed Oscillator (XT Mode): The XT
mode is a Medium Gain, Medium Frequency
mode used to work with crystal frequencies of
3.5 MHz to 10 MHz.
9.10.2
CRYSTAL SELECTION
The 32.768 kHz crystal used for the SOSC must have
the following specifications in order to properly start up
and run at the correct frequency when the SOSC is in
High-Power mode (default):
• High-Speed Oscillator (HS Mode): The HS mode is
a High-Gain, High-Frequency mode used to work
with crystal frequencies of 10 MHz to 32 MHz.
• 12.5 pF loading capacitance
• 1.0 pF shunt capacitance
• A typical ESR of 35k-50k; 70k maximum
• External Clock Source Operation (EC Mode): If the
crystal driver is disabled, the EC mode allows the
internal oscillator to be bypassed. The device
clocks are generated from an external source
(0 MHz to up to 64 MHz) and input on the CLKI pin.
In addition, the two external crystal loading capacitors
should be in the range of 18 pF-22 pF, which will be
based on the PC board layout. The capacitors should
be C0G, 5% tolerance and rated 25V or greater.
9.9
Low-Power RC (LPRC) Oscillator
The accuracy and duty cycle of the SOSC can be
measured on the REFO pin, and is recommended to be
in the range of 40-60% and accurate to ±0.65 Hz.
The PIC24FJ128GL306 family devices contain one
instance of the Low-Power RC (LPRC) Oscillator, which
provides a nominal clock frequency of 32 kHz. The
LPRC Oscillator is the clock source for the Power-up
Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe
Clock Monitor (FSCM) circuits in the clock subsystem.
The LPRC Oscillator is enabled at power-on. The LPRC
Oscillator remains enabled under these conditions:
9.10.3
LOW-POWER SOSC OPERATION
The Secondary Oscillator can operate in two distinct lev-
els of power consumption based on device configuration.
In Low-Power mode, the oscillator operates in a low drive
strength, low-power state. By default, the oscillator uses
a higher drive strength, and therefore, requires more
power. Low-Power mode is selected by Configuration bit,
SOSCHP (FDEVOPT1[3]). The lower drive strength of
this mode makes the SOSC more sensitive to noise and
requires a longer start-up time. This mode can be used
with lower load capacitance crystals (6-9 pF) to reduce
Sleep current in the RTCC. When Low-Power mode is
used, care must be taken in the design and layout of the
SOSC circuit to ensure that the oscillator starts up and
oscillates properly. PC board layout issues, stray capaci-
tance and other factors will need to be carefully controlled
in order for the crystal to operate.
• The FSCM is enabled
• The WDT is enabled
• The LPRC Oscillator is selected as the system clock
If none of these conditions is true, the LPRC Oscillator
shuts off after the PWRT expires.
9.10 Secondary Oscillator (SOSC)
9.10.1
BASIC SOSC OPERATION
PIC24FJ128GL306 family devices do not have to set the
SOSCEN bit to use the Secondary Oscillator. Any
module requiring the SOSC (such as the RTCC or
Timer1) will automatically turn on the SOSC when the
FIGURE 9-3:
REFERENCE CLOCK GENERATOR
1000
0110
0101
0100
0011
0010
0001
0000
REFI Pin
PLL (4/6/8x or 96 MHz)
SOSC
ROOUT
REFO
LPRC
FRC
POSC
Peripheral Clock
Oscillator Clock
Divider
RODIV[14:0]
To SPI, CCP, CLC
ROSEL[3:0]
Note 1: In Retention mode, the maximum peripheral output frequency to an I/O pin must be limited to 33 kHz or less.
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To use the reference clock output in Sleep mode, both
the ROSLP bit must be set and the clock selected by
the ROSELx bits must be enabled for operation, during
Sleep mode, if possible. Clearing the ROSELx bits
allows the reference output frequency to change as the
system clock changes during any clock switches. The
ROOUT bit enables/disables the reference clock
output on the REFO pin.
9.11 Reference Clock Output
In addition to the CLKO output (FOSC/2) available in
certain Oscillator modes, the device clock in the
PIC24FJ128GL306 family devices can also be config-
ured to provide a reference clock output signal to a port
pin. This feature is available in all oscillator configura-
tions and allows the user to select a greater range of
clock submultiples to drive external devices in the
application. CLKO is enabled by Configuration bit,
OSCIOFNC, and is independent of the REFO refer-
ence clock. REFO is mappable to any I/O pin that has
mapped output capability. Refer to Table 11-10 for
more information.
The ROACTIVE bit (REFOCONL[8]) indicates that the
module is active; it can be cleared by disabling the
module (setting ROEN to ‘0’). The user must not
change the reference clock source or adjust the divider
when the ROACTIVE bit indicates that the module is
active. To avoid glitches, the user should not disable
the module until the ROACTIVE bit is ‘1’.
This reference clock output is controlled by the
REFOCONL and REFOCONH registers. Setting the
ROEN bit (REFOCONL[15]) makes the clock signal
available on the REFO pin. The RODIV[14:0] bits
(REFOCONH[14:0]) enable the selection of different
clock divide options. The ROSWEN bit (REFOCONL[9])
indicates that the clock divider has successfully switched.
In order to change the divider, the user should wait until
this bit has been cleared. Write the updated values to
RODIVx, set the ROSWEN bit and then wait until it is
cleared before assuming that the REFO clock is valid.
The PLLSS Configuration bit (FOSC[4]), when cleared,
can be used to generate a REFO clock with the PLL
that is independent of the system clock. The PLL can-
not be used in the primary clock chain. For example, if
the system clock is using FRC at 8 MHz, the PLL can
use the FRC as the input and generate 32 MHz (PLL4x
mode) out of REFO.
The ROSEL[3:0] bits (REFOCONL[3:0]) determine
which clock source is used for the reference clock out-
put. The ROSLP bit (REFOCONL[11]) determines if the
reference source is available on REFO when the
device is in Sleep mode.
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REGISTER 9-6:
REFOCONL: REFERENCE OSCILLATOR CONTROL REGISTER LOW
R/W-0
ROEN
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R-0
ROACTIVE
bit 8
ROSIDL
ROOUT
ROSLP
ROSWEN
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
ROSEL[3:0]
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ROEN: Reference Oscillator Output Enable bit
1= Reference Oscillator module is enabled
0= Reference Oscillator is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
ROSIDL: REFO Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12
bit 11
ROOUT: Reference Clock Output Enable bit
1= Reference clock is driven out on the REFO pin
0= Reference clock is not driven out on the REFO pin
ROSLP: Reference Oscillator Output Stop in Sleep bit
1= Reference Oscillator continues to run in Sleep
0= Reference Oscillator is disabled in Sleep
bit 10
bit 9
Unimplemented: Read as ‘0’
ROSWEN: Reference Clock RODIVx Switch Enable bit
1= Switch clock divider; clock divider switching is currently in progress
0= Clock divider switch has been completed
bit 8
ROACTIVE: Reference Clock Request Status bit
1= Reference clock is active (user should not change the REFO settings)
0= Reference clock is inactive (user can update the REFO settings)
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
ROSEL[3:0]: Reference Clock Source Select bits
1111-1001= Reserved
1000= REFI pin
0111= Reserved
0110= PLL
0101= SOSC
0100= LPRC
0011= FRC
0010= POSC
0001= System clock (FOSC/2)
0000= FOSC
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PIC24FJ128GL306 FAMILY
REGISTER 9-7:
REFOCONH: REFERENCE OSCILLATOR CONTROL REGISTER HIGH
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
RODIV[14:8]
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RODIV[7:0]
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
RODIV[14:0]: Reference Clock Divider bits
Specifies 1/2 period of the reference clock in the source clocks
bit 14-0
(ex: Period of Output = [Reference Source * 2] * RODIV[14:0]; this equation does not apply to
RODIV[14:0] = 0).
111111111111111= REFO clock is the base clock frequency divided by 65,534 (32,767 * 2)
111111111111110= REFO clock is the base clock frequency divided by 65,532 (32,766 * 2)
•
•
•
000000000000011= REFO clock is the base clock frequency divided by 6 (3 * 2)
000000000000010= REFO clock is the base clock frequency divided by 4 (2 * 2)
000000000000001= REFO clock is the base clock frequency divided by 2 (1 * 2)
000000000000000= REFO clock is the same frequency as the base clock (no divider)
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NOTES:
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The MPLAB® XC16 C compiler offers “built-in” functions
for the power-saving modes as follows:
10.0 POWER-SAVING FEATURES
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive ref-
erence source. For more information, refer
to “Power-Saving Features with Deep
Sleep” (www.microchip.com/DS39727) in
the “dsPIC33/PIC24 Family Reference
Manual”. The information in this data
sheet supersedes the information in the
FRM.
Idle();
Sleep();
// places part in Idle
// places part in Sleep
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to “wake-up”.
10.2.1
SLEEP MODE
Sleep mode has these features:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
The PIC24FJ128GL306 family of eXtreme low-power
devices provides the ability to manage power con-
sumption by selectively managing clocking to the CPU
and the peripherals. In general, a lower clock frequency
and a reduction in the number of circuits being clocked
constitutes lower consumed power. All PIC24F devices
manage power consumption in four different ways:
• The device current consumption will be reduced
to a minimum provided that no I/O pin is sourcing
current.
• The Fail-Safe Clock Monitor does not operate
during Sleep mode since the system clock source
is disabled.
• The LPRC clock will continue to run in Sleep
mode if the WDT is enabled.
• Clock Frequency
• Instruction-Based Sleep and Idle modes
• Software Controlled Doze mode
• Selective Peripheral Control in Software
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Some device features or peripherals may
continue to operate in Sleep mode. Refer to
Table 10-2 for peripherals active in Sleep. This
includes items, such as the Input Change Notifi-
cation (ICN) on the I/O ports or peripherals that
use an External Clock input. Any peripheral that
requires the system clock source for its operation
will be disabled in Sleep mode.
Combinations of these methods can be used to
selectively tailor an application’s power consumption,
while still maintaining critical application features, such
as timing-sensitive communications.
10.1 Clock Frequency and Clock
Switching
The device will wake-up from Sleep mode on any of the
these events:
PIC24F devices allow for a wide range of clock
frequencies to be selected under application control. If
the system clock configuration is not locked, users can
choose low-power or high-precision oscillators by simply
changing the NOSC[2:0] bits. The process of changing
a system clock during operation, as well as limitations to
the process, are discussed in more detail in Section 9.0
“Oscillator Configuration”.
• On any interrupt source that is individually
enabled.
• On any form of device Reset.
• On a WDT time-out.
On wake-up from Sleep, the processor will restart with
the same clock source that was active when Sleep
mode was entered.
10.2 Instruction-Based Power-Saving
Modes
PIC24F devices have two special power-saving modes
that are entered through the execution of a special
PWRSAVinstruction. Sleep mode stops clock operation
and halts all code execution; Idle mode halts the CPU
and code execution, but allows peripheral modules to
continue operation. The assembly syntax of the
PWRSAVinstruction is shown in Example 10-1.
EXAMPLE 10-1:
PWRSAVINSTRUCTION SYNTAX
PWRSAV
PWRSAV
#0
#1
; Put the device into SLEEP mode
; Put the device into IDLE mode
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The low-voltage retention regulator is only available
when Sleep mode is invoked. It is controlled by the
LPCFG Configuration bit (FPOR[2]) and in firmware by
the RETEN bit (RCON[12]). LPCFG must be
programmed (= 0) and the RETEN bit must be set (= 1)
for the regulator to be enabled.
10.2.2
IDLE MODE
Idle mode has these features:
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.4
“Selective Peripheral Module Control”).
Note 1: In Retention mode, the maximum periph-
eral output frequency to an I/O pin must
be limited to 33 kHz or less.
• If the WDT or FSCM is enabled, the LPRC will
also remain active.
10.2.5
EXITING FROM LOW-VOLTAGE
RETENTION SLEEP
The device will wake from Idle mode on any of these
events:
All of the methods for exiting from standard Sleep also
apply to Retention Sleep (MCLR, INT0, etc.). However,
in order to allow the regulator to switch from 1.8V (oper-
ating) to Retention mode (1.2V), there is a hardware
‘lockout timer’ from the execution of Retention Sleep
until Retention Sleep can be exited.
• Any interrupt that is individually enabled.
• Any device Reset.
• A WDT time-out.
On wake-up from Idle, the clock is reapplied to the CPU
and instruction execution begins immediately, starting
with the instruction following the PWRSAVinstruction or
the first instruction in the ISR.
During the ‘lockout time’, the only method to exit Reten-
tion Sleep is a POR or MCLR. Interrupts that are
asserted (such as INT0) during the ‘lockout time’ are
masked. The lockout timer then sets a minimum interval
from when the part enters Retention Sleep until it can exit
from Retention Sleep. Interrupts are not ‘held pending’
during lockout; they are masked, and in order to exit after
the lockout expires, the exiting source must assert after
the lockout time.
10.2.3
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
Any interrupt that coincides with the execution of a
PWRSAV instruction will be held off until entry into
Sleep or Idle mode has completed. The device will
then wake-up from Sleep or Idle mode.
The lockout timer is derived from the LPRC clock,
which has a wide (untrimmed) frequency tolerance.
10.2.4
LOW-VOLTAGE RETENTION
REGULATOR
The lockout time will be one of the following two cases:
• If the LPRC was not running at the time of
Retention Sleep, the lockout time is
two LPRC periods + LPRC wake-up time
PIC24FJ128GL306 family devices incorporate a second
on-chip voltage regulator, designed to provide power to
select microcontroller features at 1.2V nominal. This
regulator allows features, such as data RAM and the
WDT, to be maintained in power-saving modes where
they would otherwise be inactive, or maintain them at a
lower power than would otherwise be the case.
• If the LPRC was running at the time of Retention
Sleep, the lockout time is one LPRC period
Refer to Table 30-20 and Table 30-21 in the AC Electrical
Specifications for the LPRC timing.
Retention Sleep uses less power than standard Sleep
mode, but takes more time to recover and begin execu-
tion. An additional 10-15 µs (typical) is required to
charge VCAP from 1.2V to 1.8V and start to execute
instructions when exiting Retention Sleep.
10.2.6
SUMMARY OF LOW-POWER SLEEP
MODES
The RETEN bit and the VREGS bit (RCON[12,8]) allow
for four different Sleep modes, which will vary by wake-
up time and power consumption. Refer to Table 10-1
for a summary of these modes. Specific information
about the current consumption and wake times can be
found in Section 30.0 “Electrical Characteristics”.
The VREGS bit allows control of speed to exit from the
Sleep modes (regular and Retention) at the cost of
more power. The regulator band gaps are enabled,
which increases the current but reduces time to recover
from Sleep by ~10 µs.
TABLE 10-1: LOW-POWER SLEEP MODES
RETEN VREGS
MODE
Relative Power
0
0
1
0
1
0
Standby Sleep
Sleep
A Few μA Range
100 μA Range
Less than 1 μA
Low-Voltage
Standby Sleep
1
1
Low-Voltage Sleep A Few μA Range
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Synchronization between the two clock domains is
maintained, allowing the peripherals to access the
SFRs while the CPU executes code at a slower rate.
10.3 Doze Mode
Generally, changing clock speed and invoking one of
the power-saving modes are the preferred strategies
for reducing power consumption. There may be
circumstances, however, where this is not practical. For
example, it may be necessary for an application to
maintain uninterrupted synchronous communication,
even while it is doing nothing else. Reducing system
clock speed may introduce communication errors,
Doze mode is enabled by setting the DOZEN bit
(CLKDIV[11]). The ratio between peripheral and core
clock speed is determined by the DOZE[2:0] bits
(CLKDIV[14:12]). There are eight possible configurations,
from 1:1 to 1:256, with 1:1 being the default.
It is also possible to use Doze mode to selectively
reduce power consumption in event-driven applica-
tions. This allows clock-sensitive functions, such as
synchronous communications, to continue without
interruption while the CPU Idles, waiting for something
to invoke an interrupt routine. Enabling the automatic
return to full-speed CPU operation on interrupts is
enabled by setting the ROI bit (CLKDIV[15]). By
default, interrupt events have no effect on Doze mode
operation.
while using
a
power-saving mode may stop
communications completely.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock contin-
ues to operate from the same source and at the same
speed. Peripheral modules continue to be clocked at
the same speed while the CPU clock speed is reduced.
TABLE 10-2: POWER-SAVING OPERATING MODES
Operating Mode
Active Clocks
Active Peripherals
Wake-up Sources
Low-Voltage/
Retention Sleep
Refer to the respective Timer, REFO, MCCP,
• Interrupt source that is individually enabled
• Any form of device Reset
• WDT time-out
Peripheral for active
clock source
LCD, BOR, WDT,
HLVD, RTCC, CMP,
CVREF, CLC, UART,
SPI, I2C
Sleep
Refer to the respective Timer, REFO, MCCP,
• Interrupt source that is individually enabled
• Any form of device Reset
• WDT time-out
Peripheral for active
clock source
LCD, BOR, WDT,
HLVD, ADC, RTCC,
CMP, CVREF, CLC,
UART, SPI, I2C
Idle
All clocks
All clocks
All peripherals
• Interrupt source that is individually enabled
• Any form of device Reset
• WDT time-out
Doze
All peripherals
• Interrupt source that is individually enabled
(ROI bit (CLKDIV[15]) should be enabled)
• Any form of device Reset
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In contrast, disabling a module by clearing its XXXEN
bit disables its functionality, but leaves its registers
available to be read and written to. This reduces power
consumption, but not by as much as setting the PMD
bit does. Most peripheral modules have an enable bit;
exceptions include input capture, output compare and
RTCC.
10.4 Selective Peripheral Module Control
Idle and Doze modes allow users to substantially
reduce power consumption by slowing or stopping the
CPU clock. Even so, peripheral modules still remain
clocked, and thus, consume power. There may be
cases where the application needs what these modes
do not provide: the allocation of power resources to
CPU processing with minimal power consumption from
the peripherals.
To achieve more selective power savings, peripheral
modules can also be selectively disabled when the
device enters Idle mode. This is done through the
control bit of the generic name format, “XXXIDL”. By
default, all modules that can operate during Idle mode
will do so. Using the disable on Idle feature allows
further reduction of power consumption during Idle
mode, enhancing power savings for extremely critical
power applications.
PIC24F devices address this requirement by allowing
peripheral modules to be selectively disabled, reducing
or eliminating their power consumption. This can be
done with two control bits:
• The Peripheral Enable bit, generically named,
“XXXEN”, located in the module’s main control
SFR.
• The Peripheral Module Disable (PMD) bit,
generically named, “XXXMD”, located in one of
the PMD Control registers.
Both bits have similar functions in enabling or disabling
their associated module. Setting the PMD bit for a
module disables all clock sources to that module,
reducing its power consumption to an absolute mini-
mum. In this state, the control and status registers
associated with the peripheral will also be disabled, so
writes to those registers will have no effect and read
values will be invalid. Many peripheral modules have a
corresponding PMD bit.
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TABLE 10-3: PERIPHERAL MODULE DISABLE REGISTER SUMMARY
All
Resets
Register
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
PMD7
PMD8
T5MD
—
T4MD
—
T3MD
—
T2MD
—
T1MD
—
—
—
—
—
—
—
I2C1MD
U2MD
—
U1MD
—
SPI2MD SPI1MD
—
—
—
—
—
ADCMD
0000
0000
0000
0000
0000
0000
0000
0000
—
CRCMD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CMPMD RTCCMD
—
—
—
U3MD
I2C2MD
HLVDMD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U4MD
—
REFOMD
—
—
—
—
—
—
—
—
CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD
—
—
—
—
—
—
—
LCDMD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMA1MD DMA0MD
—
—
—
—
—
DMTMD
—
—
CLC4MD CLC3MD CLC2MD CLC1MD
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC24FJ128GL306 FAMILY
REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1
R/W-0
T5MD
R/W-0
T4MD
R/W-0
T3MD
R/W-0
T2MD
R/W-0
T1MD
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
U2MD
R/W-0
U1MD
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
I2C1MD
SPI2MD
SPI1MD
ADC1MD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
T5MD: Timer5 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
T4MD: Timer4 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
T3MD: Timer3 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
T2MD: Timer2 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
T1MD: Timer1 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 10-8
bit 7
Unimplemented: Read as ‘0’
I2C1MD: I2C1 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 6
bit 5
bit 4
bit 3
U2MD: UART2 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
U1MD: UART1 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
SPI2MD: SPI2 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
SPI1MD: SPI1 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 2-1
bit 0
Unimplemented: Read as ‘0’
ADC1MD: A/D Converter Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
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REGISTER 10-2: PMD3: PERIPHERAL MODULE DISABLE REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
CMPMD
RTCCMD
bit 15
bit 8
bit 0
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
U3MD
U-0
—
R/W-0
U-0
—
CRCMD
I2C2MD
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10
Unimplemented: Read as ‘0’
CMPMD: Triple Comparator Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 9
RTCCMD: RTCC Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 8
bit 7
Unimplemented: Read as ‘0’
CRCMD: CRC Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 6-4
bit 3
Unimplemented: Read as ‘0’
U3MD: UART3 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 2
bit 1
Unimplemented: Read as ‘0’
I2C2MD: I2C2 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 0
Unimplemented: Read as ‘0’
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REGISTER 10-3: PMD4: PERIPHERAL MODULE DISABLE REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
R/W-0
U4MD
U-0
—
R/W-0
U-0
—
R/W-0
U-0
—
REFOMD
HLVDMD
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5
Unimplemented: Read as ‘0’
U4MD: UART4 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 4
bit 3
Unimplemented: Read as ‘0’
REFOMD: Reference Clock Output Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 2
bit 1
Unimplemented: Read as ‘0’
HLVDMD: High/Low-Voltage Detect Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 0
Unimplemented: Read as ‘0’
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REGISTER 10-4: PMD5: PERIPHERAL MODULE DISABLE REGISTER 5
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCP5MD
CCP4MD
CCP3MD
CCP2MD
CCP1MD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4
Unimplemented: Read as ‘0’
CCP5MD: MCCP5 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 3
bit 2
bit 1
bit 0
CCP4MD: MCCP4 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
CCP3MD: MCCP3 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
CCP2MD: MCCP2 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
CCP1MD: MCCP1 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
2019-2020 Microchip Technology Inc.
DS30010198B-page 121
PIC24FJ128GL306 FAMILY
REGISTER 10-5: PMD6: PERIPHERAL MODULE DISABLE REGISTER 6
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
LCDMD
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-7
bit 6
Unimplemented: Read as ‘0’
LCDMD: LCD Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 5-0
Unimplemented: Read as ‘0’
REGISTER 10-6: PMD7: PERIPHERAL MODULE DISABLE REGISTER 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
DMA1MD
DMA0MD
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5
Unimplemented: Read as ‘0’
DMA1MD: DMA1 Controller (Channels 4 through 7) Disable bit
1= Controller is disabled
0= Controller power and clock sources are enabled
bit 4
DMA0MD: DMA0 Controller (Channels 0 through 3) Disable bit
1= Controller is disabled
0= Controller power and clock sources are enabled
bit 3-0
Unimplemented: Read as ‘0’
DS30010198B-page 122
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
REGISTER 10-7: PMD8: PERIPHERAL MODULE DISABLE REGISTER 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
DMTMD
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
CLC4MD
CLC3MD
CLC2MD
CLC1MD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-9
bit 8
Unimplemented: Read as ‘0’
DMTMD: DMT Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 7-6
bit 5
Unimplemented: Read as ‘0’
CLC4MD: CLC4 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 4
CLC3MD: CLC3 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 3
CLC2MD: CLC2 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 2
CLC1MD: CLC1 Module Disable bit
1= Module is disabled
0= Module power and clock sources are enabled
bit 1-0
Unimplemented: Read as ‘0’
2019-2020 Microchip Technology Inc.
DS30010198B-page 123
PIC24FJ128GL306 FAMILY
NOTES:
DS30010198B-page 124
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as a
general purpose output pin is disabled. The I/O pin may
be read, but the output driver for the parallel port bit will be
disabled. If a peripheral is enabled, but the peripheral is
not actively driving a pin, that pin may be driven by a port.
11.0 I/O PORTS
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive refer-
ence source. For more information, refer to
“I/O Ports with Peripheral Pin Select
(PPS)” (www.microchip.com/DS30009711)
in the “dsPIC33/PIC24 Family Refer-
ence Manual”. The information in this data
sheet supersedes the information in the
FRM.
All port pins have three registers directly associated
with their operation as digital I/Os and one register
associated with their operation as analog inputs. The
Data Direction register (TRISx) determines whether the
pin is an input or an output. If the data direction bit is a
‘1’, then the pin is an input. All port pins are defined as
inputs after a Reset. Reads from the Output Latch
register (LATx), read the latch; writes to the latch, write
the latch. Reads from the PORTx register, read the port
pins; writes to the port pins, write the latch.
All of the device pins (except VDD, VSS, MCLR and
OSCI/CLKI) are shared between the peripherals and the
Parallel I/O (PIO) ports. All I/O input ports feature
Schmitt Trigger (ST) inputs for improved noise immunity.
Any bit and its associated data and control registers that
are not valid for a particular device will be disabled. That
means the corresponding LATx and TRISx registers,
and the port pin, will read as zeros. Table 11-3 through
Table 11-9 show ANSELx bits and port availability for
device variants. When a pin is shared with another
peripheral or function that is defined as an input only, it
is regarded as a dedicated port because there is no
other competing source of inputs.
11.1 Parallel I/O (PIO) Ports
A Parallel I/O port that shares a pin with a peripheral is,
in general, subservient to the peripheral. The periph-
eral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 11-1 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
FIGURE 11-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module
Output Multiplexers
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
I/O
1
0
Output Enable
Output Data
1
0
PIO Module
Read TRISx
Data Bus
D
Q
I/O Pin
WR TRISx
CK
TRIS Latch
D
Q
WR LATx +
WR PORTx
CK
Data Latch
Read LATx
Input Data
Read PORTx
2019-2020 Microchip Technology Inc.
DS30010198B-page 125
PIC24FJ128GL306 FAMILY
11.1.1
I/O PORT WRITE/READ TIMING
11.2 Configuring Analog Port Pins
(ANSELx)
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.
The ANSELx and TRISx registers control the operation
of the pins with analog function. Each port pin with
analog function is associated with one of the ANSELx
bits, which decide if the pin function should be analog
or digital. Refer to Table 11-1 for detailed behavior of
the pin for different ANSELx and TRISx bit settings.
11.1.2
OPEN-DRAIN CONFIGURATION
In addition to the PORTx, LATx and TRISx registers for
data control, each port pin can also be individually
configured for either a digital or open-drain output. This
is controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits con-
figures the corresponding pin to act as an open-drain
output.
When reading the PORTx register, all pins configured as
analog input channels will read as cleared (a low level).
11.2.1
ANALOG INPUT PINS AND
VOLTAGE CONSIDERATIONS
The voltage tolerance of pins used as device inputs is
dependent on the pin’s input function. Most input pins
are able to handle DC voltages of up to 5.5V, a level
typical for digital logic circuits. However, several pins can
only tolerate voltages up to VDD. Voltage excursions
beyond VDD on these pins should always be avoided.
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any desired
digital only pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
Table 11-2 summarizes the different voltage toler-
ances. For more information, refer to Section 30.0
“Electrical Characteristics” for more details.
TABLE 11-1: CONFIGURING ANALOG/DIGITAL FUNCTION OF AN I/O PIN
Pin Function
ANSELx Setting
TRISx Setting
Comments
Analog Input
Analog Output
Digital Input
1
1
0
1
1
1
It is recommended to keep ANSELx = 1.
It is recommended to keep ANSELx = 1.
Firmware must wait at least one instruction cycle
after configuring a pin as a digital input before a valid
input value can be read.
Digital Output
0
0
Make sure to disable the analog output function on
the pin if any is present.
TABLE 11-2: INPUT VOLTAGE LEVELS FOR PORT OR PIN TOLERATED DESCRIPTION INPUT
Port or Pin
PORTB[15:7,5:2]
Tolerated Input
Description
PORTD[11:0]
PORTE[4:0]
PORTF[6:0]
PORTG[9,6,3:2]
PORTA[0]
Tolerates input levels above VDD; useful
for most standard logic.
5.5V
PORTB[6,1:0]
PORTC[15:12]
PORTE[7:5]
PORTG[8:7]
VDD
Only VDD input levels are tolerated.
DS30010198B-page 126
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 11-3: PORTA PIN AND ANSELA AVAILABILITY
PORTA I/O Pins
Device
RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
PIC24FJXXXGL306
PIC24FJXXXGL305
PIC24FJXXXGL303
PIC24FJXXXGL302
ANSELA Bit Present
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x
—
—
—
x
TABLE 11-4: PORTB PIN AND ANSELB AVAILABILITY
PORTB I/O Pins
RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
Device
PIC24FJXXXGL306
PIC24FJXXXGL305
PIC24FJXXXGL303
PIC24FJXXXGL302
ANSELB Bit Present
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
—
—
—
x
—
—
—
x
—
—
—
x
—
—
—
x
—
—
x
x
x
—
x
—
x
TABLE 11-5: PORTC PIN AND ANSELC AVAILABILITY
PORTC I/O Pins
RC15 RC14 RC13 RC12 RC11 RC10 RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
Device
PIC24FJXXXGL306
PIC24FJXXXGL305
PIC24FJXXXGL303
PIC24FJXXXGL302
ANSELC Bit Present
x
x
x
x
x
x
x
x
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x
x
x
x
x
x
x
x
—
—
—
—
TABLE 11-6: PORTD PIN AND ANSELD AVAILABILITY
PORTD I/O Pins
RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
Device
PIC24FJXXXGL306
PIC24FJXXXGL305
PIC24FJXXXGL303
PIC24FJXXXGL302
ANSELD Bit Present
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
—
—
—
—
—
—
—
—
x
x
x
—
—
—
—
—
—
—
—
x
—
—
x
—
—
x
x
x
—
—
—
—
—
—
—
—
—
—
—
—
—
x
—
x
2019-2020 Microchip Technology Inc.
DS30010198B-page 127
PIC24FJ128GL306 FAMILY
TABLE 11-7: PORTE PIN AND ANSELE AVAILABILITY
PORTE I/O Pins
Device
RE15 RE14 RE13 RE12 RE11 RE10 RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0
PIC24FJXXXGL306
PIC24FJXXXGL305
PIC24FJXXXGL303
PIC24FJXXXGL302
ANSELE Bit Present
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
—
—
—
x
x
x
x
x
—
—
—
—
—
—
x
—
TABLE 11-8: PORTF PIN AND ANSELF AVAILABILITY
PORTF I/O Pins
Device
RF15 RF14 RF13 RF12 RF11 RF10 RF9 RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0
PIC24FJXXXGL306
PIC24FJXXXGL305
PIC24FJXXXGL303
PIC24FJXXXGL302
ANSELF Bit Present
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x
x
x
x
x
x
x
x
—
—
—
—
x
x
x
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x
x
—
TABLE 11-9: PORTG PIN AND ANSELG AVAILABILITY
PORTG I/O Pins
RG15 RG14 RG13 RG12 RG11 RG10 RG9 RG8 RG7 RG6 RG5 RG4 RG3 RG2 RG1 RG0
Device
PIC24FJXXXGL306
PIC24FJXXXGL305
PIC24FJXXXGL303
PIC24FJXXXGL302
ANSELG Bit Present
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x
x
x
x
x
x
x
x
x
x
x
x
—
—
—
—
—
—
—
—
—
—
x
x
x
x
—
—
—
—
—
—
—
—
—
—
—
—
—
x
—
—
—
x
x
x
x
—
—
—
DS30010198B-page 128
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
The user should use the instruction sequence (or
equivalent) shown in Example 11-1 to clear the
Interrupt-on-Change Status registers.
11.3 Interrupt-on-Change (IOC)
The interrupt-on-change function of the I/O ports allows
the PIC24FJ128GL306 family of devices to generate
interrupt requests to the processor in response to a
Change-of-State (COS) on selected input pins. This
feature is capable of detecting input Change-of-States,
even in Sleep mode, when the clocks are disabled.
At the end of this sequence, the W0 register will contain
a zero for each bit for which the port pin had a change
detected. In this way, any indication of a pin changing
will not be lost.
Due to the asynchronous and real-time nature of the
interrupt-on-change, the value read on the port pins
may not indicate the state of the port when the change
was detected, as a second change can occur during
the interval between clearing the flag and reading the
port. It is up to the user code to handle this case if it is
a possibility in their application. To keep this interval to
a minimum, it is recommended that any code modifying
the IOCFx registers be run either in the interrupt
handler or with interrupts disabled.
Interrupt-on-change functionality is enabled on a pin by
setting the IOCPx and/or IOCNx register bit for that pin.
For example, PORTC has register names, IOCPC and
IOCNC, for these functions. Setting a value of ‘1’ in the
IOCPx register enables interrupts for low-to-high tran-
sitions, while setting a value of ‘1’ in the IOCNx register
enables interrupts for high-to-low transitions. Setting a
value of ‘1’ in both register bits will enable interrupts for
either case (e.g., a pulse on the pin will generate two
interrupts). In order for any IOC to be detected, the
global IOC Interrupt Enable bit (IEC1[3]) must be set,
the IOCON (PADCON[15]) bit set and the associated
ISFx flag cleared.
Each Interrupt-on-Change (IOC) pin has both a weak
pull-up and a weak pull-down connected to it. The pull-
ups act as a current source connected to the pin, while
the pull-downs act as a current sink connected to the
pin. These eliminate the need for external resistors
when push button or keypad devices are connected.
When an interrupt request is generated for a pin, the
corresponding status flag (IOCFx register bit) will be
set, indicating that a Change-of-State occurred on that
pin. The IOCFx register bit will remain set until cleared
by writing a zero to it. When any IOCFx flag bit in a
given port is set, the corresponding IOCPxF bit in the
IOCSTAT register will be set. This flag indicates that a
change was detected on one of the bits on the given
port. The IOCPxF flag will be cleared when all
IOCFx[15:0] bits are cleared.
The pull-ups and pull-downs are separately enabled
using the IOCPUx registers (for pull-ups) and the
IOCPDx registers (for pull-downs). Each IOC pin has
individual control bits for its pull-up and pull-down. Set-
ting a control bit enables the weak pull-up or pull-down
for the corresponding pin.
Note:
Pull-ups and pull-downs on pins should
always be disabled whenever the pin is
configured as a digital output.
Multiple individual status flags can be cleared by writing
a zero to one or more bits using a Read-Modify-Write
(RMW) operation. If another edge is detected on a pin
whose status bit is being cleared during the Read-
Modify-Write sequence, the associated change flag will
still be set at the end of the Read-Modify-Write
sequence.
EXAMPLE 11-1:
IOC STATUS READ/CLEAR IN ASSEMBLY
MOV
XOR
AND
0xFFFF, W0
IOCFx, W0
IOCFx
; Initial mask value 0xFFFF -> W0
; W0 has '1' for each bit set in IOCFx
; IOCFx & W0 ->IOCFx
EXAMPLE 11-2:
PORT READ/WRITE IN ASSEMBLY
MOV
MOV
NOP
0xFF00, W0
W0, TRISB
; Configure PORTB[15:8] as inputs
; and PORTB[7:0] as outputs
; Delay 1 cycle
BTSS PORTB, #13
; Next Instruction
EXAMPLE 11-3:
PORT READ/WRITE IN ‘C’
TRISB = 0xFF00;
Nop();
// Configure PORTB[15:8] as inputs and PORTB[7:0] as outputs
// Delay 1 cycle
If (PORTBbits.RB13){ };
// Next Instruction
2019-2020 Microchip Technology Inc.
DS30010198B-page 129
PIC24FJ128GL306 FAMILY
11.4 I/O Port Control Registers
REGISTER 11-1: PADCON: PORT CONFIGURATION REGISTER
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
IOCON
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
IOCON: Interrupt-on-Change Enable bit
1= Interrupt-on-change functionality is enabled
0= Interrupt-on-change functionality is disabled
bit 14-0
Unimplemented: Read as ‘0’
DS30010198B-page 130
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
REGISTER 11-2: IOCSTAT: INTERRUPT-ON-CHANGE STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
R/HS/HC-0
IOCPGF
R/HS/HC-0
IOCPFF
R/HS/HC-0
IOCPEF
R/HS/HC-0 R/HS/HC-0
IOCPDF IOCPCF
R/HS/HC-0 R/HS/HC-0
IOCPBF IOCPAF
bit 0
bit 7
Legend:
HS = Hardware Settable bit
W = Writable bit
HC = Hardware Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
bit 15-7
bit 6
Unimplemented: Read as ‘0’
IOCPGF: Interrupt-on-Change PORTG Flag bit
1= A change was detected on an IOC-enabled pin on PORTG
0= No change was detected or the user has cleared all detected changes
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IOCPFF: Interrupt-on-Change PORTF Flag bit
1= A change was detected on an IOC-enabled pin on PORTF
0= No change was detected or the user has cleared all detected changes
IOCPEF: Interrupt-on-Change PORTE Flag bit
1= A change was detected on an IOC-enabled pin on PORTE
0= No change was detected or the user has cleared all detected changes
IOCPDF: Interrupt-on-Change PORTD Flag bit
1= A change was detected on an IOC-enabled pin on PORTD
0= No change was detected or the user has cleared all detected changes
IOCPCF: Interrupt-on-Change PORTC Flag bit
1= A change was detected on an IOC-enabled pin on PORTC
0= No change was detected or the user has cleared all detected changes
IOCPBF: Interrupt-on-Change PORTB Flag bit
1= A change was detected on an IOC-enabled pin on PORTB
0= No change was detected or the user has cleared all detected changes
IOCPAF: Interrupt-on-Change PORTA Flag bit
1= A change was detected on an IOC-enabled pin on PORTA
0= No change was detected, or the user has cleared all detected change
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REGISTER 11-3: TRISx: OUTPUT ENABLE FOR PORTx REGISTER(1)
R/W-1
bit 15
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
TRISx[15:8]
R/W-1
R/W-1
R/W-1
TRISx[7:0]
R/W-1
R/W-1
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
TRISx[15:0]: Output Enable for PORTx bits
1= LATx[n] is not driven on the PORTx[n] pin
0= LATx[n] is driven on the PORTx[n] pin
Note 1: See Table 11-3 through Table 11-9 for individual bit availability in this register.
REGISTER 11-4: PORTx: INPUT DATA FOR PORTx REGISTER(1)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PORTx[15:8]
bit 15
R/W-1
bit 7
bit 8
R/W-1
bit 0
R/W-1
R/W-1
R/W-1
PORTx[7:0]
R/W-1
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PORTx[15:0]: PORTx Data Input Value bits
Note 1: See Table 11-3 through Table 11-9 for individual bit availability in this register.
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REGISTER 11-5: LATx: OUTPUT DATA FOR PORTx REGISTER(1)
R/W-x
bit 15
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 8
R/W-x
LATx[15:8]
R/W-x
R/W-x
R/W-x
LATx[7:0]
R/W-x
R/W-x
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
LATx[15:0]: PORTx Data Output Value bits
Note 1: See Table 11-3 through Table 11-9 for individual bit availability in this register.
REGISTER 11-6: ODCx: OPEN-DRAIN ENABLE FOR PORTx REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ODCx[15:8]
bit 15
R/W-0
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
ODCx[7:0]
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
ODCx[15:0]: PORTx Open-Drain Enable bits
1= Open-drain is enabled on the PORTx pin
0= Open-drain is disabled on the PORTx pin
Note 1: See Table 11-3 through Table 11-9 for individual bit availability in this register.
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REGISTER 11-7: ANSELx: ANALOG SELECT FOR PORTx REGISTER(1)
R/W-1
bit 15
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
ANSELx[15:8]
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANSELx[7:0]
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
ANSELx[15:0]: Analog Select for PORTx bits
1 = Analog input is enabled and digital input is disabled on the PORTx[n] pin
0 = Analog input is disabled and digital input is enabled on the PORTx[n] pin
Note 1: See Table 11-3 through Table 11-9 for individual bit availability in this register.
REGISTER 11-8: IOCPx: INTERRUPT-ON-CHANGE POSITIVE EDGE x REGISTER(1,2,3)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
IOCPx[15:8]
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
IOCPx[7:0]
R/W-0
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
IOCPx[15:0]: Interrupt-on-Change Positive Edge x Enable bits
1= Interrupt-on-change is enabled on the IOCx pin for a positive going edge; the associated status bit
and interrupt flag will be set upon detecting an edge
0= Interrupt-on-change is disabled on the IOCx pin for a positive going edge
Note 1: Setting both IOCPx and IOCNx will enable the IOCx pin for both edges, while clearing both registers will
disable the functionality.
2: Changing the value of this register while the module is enabled (IOCON = 1) may cause a spurious IOC
event. The corresponding interrupt must be ignored, cleared (using IOCFx) or masked (within the interrupt
controller), or this module must be enabled (IOCON = 0) when changing this register.
3: See Table 11-3 through Table 11-9 for individual bit availability in this register.
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REGISTER 11-9: IOCNx: INTERRUPT-ON-CHANGE NEGATIVE EDGE x REGISTER(1,2,3)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
IOCNx[15:8]
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
IOCNx[7:0]
R/W-0
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
IOCNx[15:0]: Interrupt-on-Change Negative Edge x Enable bits
1= Interrupt-on-change is enabled on the IOCx pin for a negative going edge; the associated status bit
and interrupt flag will be set upon detecting an edge
0= Interrupt-on-change is disabled on the IOCx pin for a negative going edge
Note 1: Setting both IOCPx and IOCNx will enable the IOCx pin for both edges, while clearing both registers will
disable the functionality.
2: Changing the value of this register while the module is enabled (IOCON = 1) may cause a spurious IOC
event. The corresponding interrupt must be ignored, cleared (using IOCFx) or masked (within the interrupt
controller), or this module must be enabled (IOCON = 0) when changing this register.
3: See Table 11-3 through Table 11-9 for individual bit availability in this register.
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REGISTER 11-10: IOCFx: INTERRUPT-ON-CHANGE FLAG x REGISTER(1,2)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
IOCFx[15:8]
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
IOCFx[7:0]
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
IOCFx[15:0]: Interrupt-on-Change Flag x bits
1= An enabled change was detected on the associated pin; set when IOCPx = 1and a positive edge was
detected on the IOCx pin, or when IOCNx = 1and a negative edge was detected on the IOCx pin
0= No change was detected or the user cleared the detected change
Note 1: It is not possible to set the IOCFx register bits with software writes (as this would require the addition of
significant logic). To test IOC interrupts, it is recommended to enable the IOC functionality on one or more
GPIO pins and then use the corresponding LATx register bit(s) to trigger an IOC interrupt.
2: See Table 11-3 through Table 11-9 for individual bit availability in this register.
REGISTER 11-11: IOCPUx: INTERRUPT-ON-CHANGE PULL-UP ENABLE x REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
IOCPUx[15:8]
bit 15
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
IOCPUx[7:0]
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
IOCPUx[15:0]: Interrupt-on-Change Pull-up Enable x bits
1= Pull-up is enabled
0= Pull-up is disabled
Note 1: See Table 11-3 through Table 11-9 for individual bit availability in this register.
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REGISTER 11-12: IOCPDx: INTERRUPT-ON-CHANGE PULL-DOWN ENABLE x REGISTER(1)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
IOCPDx[15:8]
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IOCPDx[7:0]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
IOCPDx[15:0]: Interrupt-on-Change Pull-Down Enable x bits
1= Pull-down is enabled
0= Pull-down is disabled
Note 1: See Table 11-3 through Table 11-9 for individual bit availability in this register.
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PPS is not available for these peripherals:
11.5 Peripheral Pin Select (PPS)
• I2C (input and output)
• Input Change Notifications
• Analog (inputs and outputs)
• INT0
Amajor challenge in general purpose devices is provid-
ing the largest possible set of peripheral features while
minimizing the conflict of features on I/O pins. In an
application that needs to use more than one peripheral
multiplexed on a single pin, inconvenient work arounds
in application code, or a complete redesign, may be the
only option.
A key difference between pin select and non-pin select
peripherals is that pin select peripherals are not asso-
ciated with a default I/O pin. The peripheral must
always be assigned to a specific I/O pin before it can be
used. In contrast, non-pin select peripherals are always
available on a default pin, assuming that the peripheral
is active and not conflicting with another peripheral.
The Peripheral Pin Select (PPS) feature provides an
alternative to these choices by enabling the user’s
peripheral set selection and its placement on a wide
range of I/O pins. By increasing the pinout options
available on a particular device, users can better tailor
the microcontroller to their entire application, rather
than trimming the application to fit the device.
11.5.2.1
Peripheral Pin Select Function
Priority
The Peripheral Pin Select feature operates over a fixed
subset of digital I/O pins. Users may independently
map the input and/or output of any one of many digital
peripherals to any one of these I/O pins. PPS is per-
formed in software and generally does not require the
device to be reprogrammed. Hardware safeguards are
included that prevent accidental or spurious changes to
the peripheral mapping once it has been established.
Pin-selectable peripheral outputs (e.g., output com-
pare, UART transmit) will take priority over general
purpose digital functions on a pin, such as port I/O.
Specialized digital outputs will take priority over PPS
outputs on the same pin. The pin diagrams list
peripheral outputs in the order of priority. Refer to them
for priority concerns on a particular pin.
Unlike PIC24F devices with fixed peripherals, pin-
selectable peripheral inputs will never take ownership
of a pin. The pin’s output buffer will be controlled by the
TRISx setting or by a fixed peripheral on the pin. If the
pin is configured in Digital mode, then the PPS input will
operate correctly. If an analog function is enabled on
the pin, the PPS input will be disabled.
11.5.1
AVAILABLE PINS
The number of available pins is dependent on the par-
ticular device and its pin count. Pins that support the
Peripheral Pin Select feature include the designation,
“RPn” or “RPIn”, in their full pin designation, where “n”
is the remappable pin number. “RP” is used to desig-
nate pins that support both remappable input and
output functions, while “RPI” indicates pins that support
remappable input functions only.
11.5.3
CONTROLLING PERIPHERAL PIN
SELECT
PPS features are controlled through two sets of Special
Function Registers (SFRs): one to map peripheral
inputs and one to map outputs. Because they are
separately controlled, a particular peripheral’s input
and output (if the peripheral has both) can be placed on
any selectable function pin without constraint.
PIC24FJ128GL306 family devices support a larger
number of remappable input/output pins than remap-
pable input only pins. In this device family, there are up
to 33 remappable input/output pins, depending on the
pin count of the particular device selected. These pins
are numbered, RP0 through RP31 and RPI37.
The association of a peripheral to a peripheral-selectable
pin is handled in two different ways, depending on if an
input or an output is being mapped.
See Table 1-1 for a summary of pinout options in each
package offering.
11.5.2
AVAILABLE PERIPHERALS
The peripherals managed by the PPS are all digital
only peripherals. These include general serial commu-
nications (UART and SPI), general purpose timer clock
inputs, timer related peripherals (input capture and
output compare) and external interrupt inputs. Also
included are the outputs of the comparator module,
since these are discrete digital signals.
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Each register contains one or two sets of 6-bit fields,
with each set associated with one of the pin-selectable
peripherals. Programming a given peripheral’s bit field
with an appropriate 6-bit value maps the RPn/RPIn pin
with that value to that peripheral. For any given device,
the valid range of values for any of the bit fields corre-
sponds to the maximum number of Peripheral Pin
Selections supported by the device.
11.5.3.1
Input Mapping
The inputs of the Peripheral Pin Select options are
mapped on the basis of the peripheral; that is, a control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 11-13
through Register 11-33).
TABLE 11-10: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1)
Function Mapping
Bits
Input Name
Function Name
Register
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
Timer2 External Clock
Timer3 External Clock
Timer4 External Clock
Timer5 External Clock
CCP Capture 1
INT1
INT2
RPINR0[13:8]
RPINR1[5:0]
INT1R[5:0]
INT2R[5:0]
INT3
RPINR1[13:8]
RPINR2[5:0]
INT3R[5:0]
INT4
INT4R[5:0]
T2CK
RPINR3[5:0]
T2CKR[5:0]
T3CKR[5:0]
T4CKR[5:0]
T5CKR[5:0]
ICM1R[5:0]
ICM2R[5:0]
ICM3R[5:0]
ICM4R[5:0]
OCFAR[5:0]
OCFBR[5:0]
TCKIAR[5:0]
TCKIBR[5:0]
REFIR[5:0]
TMPRNR[5:0]
ICM5R[5:0]
U3RXR[5:0]
U1RXR[5:0]
U1CTSR[5:0]
U2RXR[5:0]
U2CTSR[5:0]
SDI1R[5:0]
T3CK
RPINR3[13:8]
RPINR4[5:0]
T4CK
T5CK
RPINR4[13:8]
RPINR5[5:0]
ICM1
CCP Capture 2
ICM2
RPINR5[13:8]
RPINR6[5:0]
CCP Capture 3
ICM3
CCP Capture 4
ICM4
RPINR6[13:8]
RPINR11[5:0]
RPINR11[13:8]
RPINR12[5:0]
RPINR12[13:8]
RPINR13[5:0]
RPINR13[13:8]
RPINR14[5:0]
RPINR17[13:8]
RPINR18[5:0]
RPINR18[13:8]
RPINR19[5:0]
RPINR19[13:8]
RPINR20[5:0]
RPINR20[13:8]
RPINR21[5:0]
RPINR21[13:8]
RPINR22[5:0]
RPINR22[13:8]
RPINR23[5:0]
RPINR23[13:8]
RPINR25[5:0]
RPINR25[13:8]
RPINR26[5:0]
RPINR26[13:8]
RPINR27[5:0]
RPINR27[13:8]
Output Compare Fault A
Output Compare Fault B
CCP Clock Input A
CCP Clock Input B
Reference Clock Input
Tamper Detect
OCFA
OCFB
TCKIA
TCKIB
REFI
TMPRN
ICM5
CCP Capture 5
UART3 Receive
U3RX
U1RX
U1CTS
U2RX
U2CTS
SDI1
UART1 Receive
UART1 Clear-to-Send
UART2 Receive
UART2 Clear-to-Send
SPI1 Data Input
SPI1 Clock Input
SCK1IN
SS1IN
U3CTS
SDI2
SCK1R[5:0]
SS1R[5:0]
SPI1 Slave Select Input
UART3 Clear-to-Send
SPI2 Data Input
U3CTSR[5:0]
SDI2R[5:0]
SPI2 Clock Input
SCK2IN
SS2IN
TxCK
SCK2R[5:0]
SS2R[5:0]
SPI2 Slave Select Input
Generic Timer External Clock
CLC Input A
TXCKR[5:0]
CLCINAR[5:0]
CLCINBR[5:0]
CLCINCR[5:0]
CLCINDR[5:0]
U4RXR[5:0]
U4CTSR[5:0]
CLCINA
CLCINB
CLCINC
CLCIND
U4RX
U4CTS
CLC Input B
CLC Input C
CLC Input D
UART4 Receive
UART4 Clear-to-Send
Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger (ST) input buffers.
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value of the bit field corresponds to one of the peripher-
als and that peripheral’s output is mapped to the pin (see
Table 11-11).
11.5.3.2
Output Mapping
In contrast to inputs, the outputs of the Peripheral Pin
Select options are mapped on the basis of the pin. In this
case, a control register associated with a particular pin
dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Each register contains two 6-bit fields, with each field
being associated with either one RPa pin or one RPb pin
(see Register 11-34, Table 11-13 and Table 11-14). The
Because of the mapping technique, the list of peripherals
for output mapping also includes a null value of ‘000000’.
This permits any given pin to remain disconnected from
the output of any of the pin-selectable peripherals.
TABLE 11-11: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT)
Output Function Number
Function
Output Name
0
None (Pin Disabled)
C1OUT
C2OUT
U1TX
—
1
Comparator 1 Output
2
Comparator 2 Output
UART1 Transmit
3
4
U1RTS
UART1 Request-to-Send
UART2 Transmit
5
U2TX
6
U2RTS
UART2 Request-to-Send
SPI1 Data Output
7
SDO1
8
SCK1OUT
SS1OUT
SDO2
SPI1 Clock Output
9
SPI1 Slave Select Output
SPI2 Data Output
10
11
12
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
SCK2OUT
SS2OUT
OCM2A
OCM2B
OCM3A
OCM3B
OCM4A
OCM4B
U3TX
SPI2 Clock Output
SPI2 Slave Select Output
CCP2A Output Compare
CCP2B Output Compare
CCP3A Output Compare
CCP3B Output Compare
CCP4A Output Compare
CCP4B Output Compare
UART3 Transmit
U3RTS
UART3 Request-to-Send
UART4 Transmit
U4TX
U4RTS
UART4 Request-to-Send
Comparator 3 Output
RTCC Power Control
Reference Clock Output
CLC1 Output
C3OUT
PWRGT
REFO
CLC1OUT
CLC2OUT
CLC3OUT
CLC4OUT
RTCC
CLC2 Output
CLC3 Output
CLC4 Output
RTCC Clock Output
CCP5B Output Compare
CCP5A Output Compare
OCM5B
OCM5A
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11.5.3.3
Mapping Limitations
11.5.4.1
Control Register Lock
The control schema of the Peripheral Pin Select is
extremely flexible. Other than systematic blocks that
prevent signal contention, caused by two physical pins
being configured as the same functional input or two
functional outputs configured as the same pin, there
are no hardware enforced lockouts. The flexibility
extends to the point of allowing a single input to drive
multiple peripherals or a single functional output to
drive multiple output pins.
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes will
appear to execute normally, but the contents of the
registers will remain unchanged. To change these reg-
isters, they must be unlocked in hardware. The register
lock is controlled by the IOLOCK bit (OSCCON[6]).
Setting IOLOCK prevents writes to the control
registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
11.5.3.4
Mapping Exceptions for Family
Devices
1. Write 46h to OSCCON[7:0].
2. Write 57h to OSCCON[7:0].
3. Clear (or set) IOLOCK as a single operation.
The differences in available remappable pins are
summarized in Table 11-12.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the Peripheral Pin Selects to be configured
with a single unlock sequence, followed by an update
to all control registers, then locked with a second lock
sequence.
When developing applications that use remappable
pins, users should also keep these things in mind:
• For the RPINRx registers, bit combinations corre-
sponding to an unimplemented pin for a particular
device are treated as invalid; the corresponding
module will not have an input mapped to it.
11.5.4.2
Continuous State Monitoring
• For RPORx registers, the bit fields corresponding
to an unimplemented pin will also be
unimplemented; writing to these fields will have
no effect.
In addition to being protected from direct writes, the con-
tents of the RPINRx and RPORx registers are constantly
monitored in hardware by shadow registers. If an unex-
pected change in any of the registers occurs (such as cell
disturbances caused by ESD or other external events), a
Configuration Mismatch Reset will be triggered.
11.5.4
CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC24F devices include three features to
prevent alterations to the peripheral map:
11.5.4.3
Configuration Bit Pin Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to the
RPINRx and RPORx registers. The IOL1WAY (FOSC[5])
Configuration bit blocks the IOLOCK bit from being
cleared after it has been set once. If IOLOCK remains
set, the register unlock procedure will not execute and
the Peripheral Pin Select Control registers cannot be
written to. The only way to clear the bit and re-enable
peripheral remapping is to perform a device Reset.
• Control register lock sequence
• Continuous state monitoring
• Configuration bit remapping lock
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows users unlimited access (with the
proper use of the unlock sequence) to the Peripheral
Pin Select registers.
TABLE 11-12: REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ128GL306 FAMILY DEVICES
RPn Pins (I/O)
Unimplemented
RPIn Pins
Unimplemented
Device
Total
Total
PIC24FJXXXGL306
PIC24FJXXXGL305
PIC24FJXXXGL303
PIC24FJXXXGL302
32
24
15
13
—
—
—
—
1
1
1
1
—
—
—
—
2019-2020 Microchip Technology Inc.
DS30010198B-page 141
PIC24FJ128GL306 FAMILY
A final consideration is that Peripheral Pin Select func-
tions neither override analog inputs nor reconfigure
pins with analog functions for digital I/Os. If a pin is
configured as an analog input on a device Reset, it
must be explicitly reconfigured as a digital I/O when
used with a Peripheral Pin Select.
11.5.5
CONSIDERATIONS FOR
PERIPHERAL PIN SELECTION
The ability to control Peripheral Pin Selection intro-
duces several considerations into application design
that could be overlooked. This is particularly true for
several common peripherals that are available only as
remappable peripherals.
Example 11-4 shows a configuration for bidirectional
communication with flow control using UART1. The
following input and output functions are used:
The main consideration is that the Peripheral Pin
Selects are not available on default pins in the device’s
default (Reset) state. Since all RPINRx registers reset
to ‘111111’ and all RPORx registers reset to ‘000000’,
all Peripheral Pin Select inputs are tied to VSS, and all
Peripheral Pin Select outputs are disconnected.
• Input Functions: U1RX, U1CTS
• Output Functions: U1TX, U1RTS
EXAMPLE 11-4:
CONFIGURING UART1
INPUT AND OUTPUT
FUNCTIONS
This situation requires the user to initialize the device
with the proper peripheral configuration before any
other application code is executed. Since the IOLOCK
bit resets in the unlocked state, it is not necessary to
execute the unlock sequence after the device has
come out of Reset. For application safety, however, it is
best to set IOLOCK and lock the configuration after
writing to the control registers.
// Unlock Registers
asm volatile
("MOV
"MOV
"MOV
"MOV.b w2, [w1]
"MOV.b w3, [w1]
#OSCCON, w1 \n"
#0x46, w2
#0x57, w3
\n"
\n"
\n"
\n"
;
"BCLR
OSCCON, #6")
Because the unlock sequence is timing-critical, it must
be executed as an assembly language routine in the
same manner as changes to the oscillator configura-
tion. If the bulk of the application is written in ‘C’, or
another high-level language, the unlock sequence
should be performed by writing in-line assembly.
// or use XC16 built-in macro:
// __builtin_write_OSCCONL(OSCCON & 0xbf);
// Configure Input Functions (Table 11-10)
// Assign U1RX To Pin RP0
RPINR18bits.U1RXR = 0;
Choosing the configuration requires the review of all
Peripheral Pin Selects and their pin assignments,
especially those that will not be used in the application.
In all cases, unused pin-selectable peripherals should
be disabled completely. Unused peripherals should
have their inputs assigned to an unused RPn/RPIn pin
function. I/O pins with unused RPn functions should be
configured with the null peripheral output.
// Assign U1CTS To Pin RP1
RPINR18bits.U1CTSR = 1;
// Configure Output Functions (Table 11-11)
// Assign U1TX To Pin RP2
RPOR1bits.RP2R = 3;
// Assign U1RTS To Pin RP3
RPOR1bits.RP3R = 4;
The assignment of a peripheral to a particular pin does
not automatically perform any other configuration of the
pin’s I/O circuitry. In theory, this means adding a pin-
selectable output to a pin may mean inadvertently
driving an existing peripheral input when the output is
driven. Users must be familiar with the behavior of
other fixed peripherals that share a remappable pin and
know when to enable or disable them. To be safe, fixed
digital peripherals that share the same pin should be
disabled when not in use.
// Lock Registers
asm volatile
("MOV
"MOV
"MOV
#OSCCON, w1
#0x46, w2
#0x57, w3
\n"
\n"
\n"
\n"
\n"
;
"MOV.b w2, [w1]
"MOV.b w3, [w1]
"BSET
OSCCON, #6")
// or use XC16 built-in macro:
// __builtin_write_OSCCONL(OSCCON | 0x40);
Along these lines, configuring a remappable pin for a
specific peripheral does not automatically turn that
feature on. The peripheral must be specifically config-
ured for operation and enabled as if it were tied to a
fixed pin. Where this happens in the application code
(immediately following a device Reset and peripheral
configuration or inside the main application routine)
depends on the peripheral and its use in the
application.
DS30010198B-page 142
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
11.5.6
PERIPHERAL PIN SELECT
REGISTERS
Note:
Input and Output register values can only
be changed if IOLOCK (OSCCON[6]) = 0.
See Section 11.5.4.1 “Control Register
Lock” for a specific command sequence.
The PIC24FJ128GL306 family of devices implements a
total of 36 registers for remappable peripheral
configuration:
• Input Remappable Peripheral Registers (21)
• Output Remappable Peripheral Registers (15)
REGISTER 11-13: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INT1R5
INT1R4
INT1R3
INT1R2
INT1R1
INT1R0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-0
Unimplemented: Read as ‘0’
INT1R[5:0]: Assign External Interrupt 1 (INT1) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
REGISTER 11-14: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INT3R5
INT3R4
INT3R3
INT3R2
INT3R1
INT3R0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INT2R5
INT2R4
INT2R3
INT2R2
INT2R1
INT2R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
INT3R[5:0]: Assign External Interrupt 3 (INT3) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
INT2R[5:0]: Assign External Interrupt 2 (INT2) to the Corresponding RPn or RPIn Pin bits
2019-2020 Microchip Technology Inc.
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REGISTER 11-15: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INT4R5
INT4R4
INT4R3
INT4R2
INT4R1
INT4R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
INT4R[5:0]: Assign External Interrupt 4 (INT4) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-16: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
T3CKR5
T3CKR4
T3CKR3
T3CKR2
T3CKR1
T3CKR0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
T2CKR5
T2CKR4
T2CKR3
T2CKR2
T2CKR1
T2CKR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
T3CKR[5:0]: Assign Timer3 Clock (T3CK) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
T2CKR[5:0]: Assign Timer2 Clock to (T2CK) the Corresponding RPn or RPIn Pin bits
DS30010198B-page 144
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
REGISTER 11-17: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
T5CKR5
T5CKR4
T5CKR3
T5CKR2
T5CKR1
T5CKR0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
T4CKR5
T4CKR4
T4CKR3
T4CKR2
T4CKR1
T4CKR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
T5CKR[5:0]: Assign Timer5 Clock (T5CK) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
T4CKR[5:0]: Assign Timer4 Clock (T4CK) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-18: RPINR5: PERIPHERAL PIN SELECT INPUT REGISTER 5
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ICM2R5
ICM2R4
ICM2R3
ICM2R2
ICM2R1
ICM2R0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ICM1R5
ICM1R4
ICM1R3
ICM1R2
ICM1R1
ICM1R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
ICM2R[5:0]: Assign CCP2 Capture Mode (ICM2) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
ICM1R[5:0]: Assign CCP1 Capture Mode (ICM1) to the Corresponding RPn or RPIn Pin bits
2019-2020 Microchip Technology Inc.
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REGISTER 11-19: RPINR6: PERIPHERAL PIN SELECT INPUT REGISTER 6
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ICM4R5
ICM4R4
ICM4R3
ICM4R2
ICM4R1
ICM4R0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ICM3R5
ICM3R4
ICM3R3
ICM3R2
ICM3R1
ICM3R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
ICM4R[5:0]: Assign CCP4 Capture Mode (ICM4) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
ICM3R[5:0]: Assign CCP3 Capture Mode (ICM3) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-20: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
OCFBR0
bit 8
OCFBR5
OCFBR4
OCFBR3
OCFBR2
OCFBR1
bit 15
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
OCFAR5
OCFAR4
OCFAR3
OCFAR2
OCFAR1
OCFAR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
OCFBR[5:0]: Assign Output Compare Fault B (OCFB) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
OCFAR[5:0]: Assign Output Compare Fault A (OCFA) to the Corresponding RPn or RPIn Pin bits
DS30010198B-page 146
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PIC24FJ128GL306 FAMILY
REGISTER 11-21: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TCKIBR5
TCKIBR4
TCKIBR3
TCKIBR2
TCKIBR1
TCKIBR0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TCKIAR5
TCKIAR4
TCKIAR3
TCKIAR2
TCKIAR1
TCKIAR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
TCKIBR[5:0]: Assign MCCP Clock Input B (TCKIB) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
TCKIAR[5:0]: Assign MCCP Clock Input A (TCKIA) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-22: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TMPRNR0
bit 8
TMPRNR5
TMPRNR4
TMPRNR3
TMPRNR2
TMPRNR1
bit 15
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
REFIR5
REFIR4
REFIR3
REFIR2
REFIR1
REFIR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
TMPRNR[5:0]: Assign Tamper Detect (TMPRN) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
REFIR[5:0]: Assign Reference Clock Input (REFI) to the Corresponding RPn or RPIn Pin bits
2019-2020 Microchip Technology Inc.
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REGISTER 11-23: RPINR14: PERIPHERAL PIN SELECT INPUT REGISTER 14
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ICM5R5
ICM5R4
ICM5R3
ICM5R2
ICM5R1
ICM5R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
ICM5R[5:0]: Assign CCP5 Capture Mode (ICM5) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-24: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U3RXR0
bit 8
U3RXR5
U3RXR4
U3RXR3
U3RXR2
U3RXR1
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-0
Unimplemented: Read as ‘0’
U3RXR[5:0]: Assign UART3 Receive (U3RX) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
DS30010198B-page 148
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PIC24FJ128GL306 FAMILY
REGISTER 11-25: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U1CTSR5
U1CTSR4
U1CTSR3
U1CTSR2
U1CTSR1
U1CTSR0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U1RXR5
U1RXR4
U1RXR3
U1RXR2
U1RXR1
U1RXR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
U1CTSR[5:0]: Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
U1RXR[5:0]: Assign UART1 Receive (U1RX) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-26: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U2CTSR0
bit 8
U2CTSR5
U2CTSR4
U2CTSR3
U2CTSR2
U2CTSR1
bit 15
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U2RXR5
U2RXR4
U2RXR3
U2RXR2
U2RXR1
U2RXR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
U2CTSR[5:0]: Assign UART2 Clear-to-Send (U2CTS) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
U2RXR[5:0]: Assign UART2 Receive (U2RX) to the Corresponding RPn or RPIn Pin bits
2019-2020 Microchip Technology Inc.
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REGISTER 11-27: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SCK1R5
SCK1R4
SCK1R3
SCK1R2
SCK1R1
SCK1R0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SDI1R5
SDI1R4
SDI1R3
SDI1R2
SDI1R1
SDI1R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
SCK1R[5:0]: Assign SPI1 Clock Input (SCK1IN) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
SDI1R[5:0]: Assign SPI1 Data Input (SDI1) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-28: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U3CTSR0
bit 8
U3CTSR5
U3CTSR4
U3CTSR3
U3CTSR2
U3CTSR1
bit 15
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SS1R5
SS1R4
SS1R3
SS1R2
SS1R1
SS1R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit
Unimplemented: Read as ‘0’
U3CTSR[5:0]: Assign UART3 Receive (U3CTS) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
SS1R[5:0]: Assign SPI1 Slave Select Input (SS1IN) to the Corresponding RPn or RPIn Pin bits
DS30010198B-page 150
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
REGISTER 11-29: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SCK2R5
SCK2R4
SCK2R3
SCK2R2
SCK2R1
SCK2R0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SDI2R5
SDI2R4
SDI2R3
SDI2R2
SDI2R1
SDI2R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
SCK2R[5:0]: Assign SPI2 Clock Input (SCK2IN) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
SDI2R[5:0]: Assign SPI2 Data Input (SDI2) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-30: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TXCKR0
bit 8
TXCKR5
TXCKR4
TXCKR3
TXCKR2
TXCKR1
bit 15
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SS2R5
SS2R4
SS2R3
SS2R2
SS2R1
SS2R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
TXCKR[5:0]: Assign Generic Timer External Clock (TxCK) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
SS2R[5:0]: Assign SPI2 Slave Select Input (SS2IN) to the Corresponding RPn or RPIn Pin bits
2019-2020 Microchip Technology Inc.
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PIC24FJ128GL306 FAMILY
REGISTER 11-31: RPINR25: PERIPHERAL PIN SELECT INPUT REGISTER 25
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CLCINBR0
bit 8
CLCINBR5
CLCINBR4
CLCINBR3
CLCINBR2
CLCINBR1
bit 15
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CLCINAR0
bit 0
CLCINAR5
CLCINAR4
CLCINAR3
CLCINAR2
CLCINAR1
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
CLCINBR[5:0]: Assign CLC Input B (CLCINB) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
CLCINAR[5:0]: Assign CLC Input A (CLCINA) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-32: RPINR26: PERIPHERAL PIN SELECT INPUT REGISTER 26
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CLCINDR0
bit 8
CLCINDR5
CLCINDR4
CLCINDR3
CLCINDR2
CLCINDR1
bit 15
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
CLCINCR0
bit 0
CLCINCR5
CLCINCR4
CLCINCR3
CLCINCR2
CLCINCR1
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
CLCINDR[5:0]: Assign CLC Input D (CLCIND) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
CLCINCR[5:0]: Assign CLC Input C (CLCINC) to the Corresponding RPn or RPIn Pin bits
DS30010198B-page 152
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
REGISTER 11-33: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U4CTSR5
U4CTSR4
U4CTSR3
U4CTSR2
U4CTSR1
U4CTSR0
bit 15
bit 8
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U4RXR5
U4RXR4
U4RXR3
U4RXR2
U4RXR1
U4RXR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
U4CTSR[5:0]: Assign UART4 Clear-to-Send (U4CTS) to the Corresponding RPn or RPIn Pin bits
Unimplemented: Read as ‘0’
bit 5-0
U4RXR[5:0]: Assign UART4 Receive (U4RX) to the Corresponding RPn or RPIn Pin bits
REGISTER 11-34: RPORx: PERIPHERAL PIN SELECT OUTPUT REGISTER x
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RPaR0
bit 8
RPaR5
RPaR4
RPaR3
RPaR2
RPaR1
bit 15
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RPbR5
RPbR4
RPbR3
RPbR2
RPbR1
RPbR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
RPaR[5:0]: RPa Output Pin Mapping bits
Peripheral Output Number y is assigned to pin, RPa (see Table 11-11 for peripheral function numbers).
Unimplemented: Read as ‘0’
bit 7-6
bit 5-0
RPbR[5:0]: RPb Output Pin Mapping bits
Peripheral Output Number y is assigned to pin, RPb (see Table 11-11 for peripheral function numbers).
2019-2020 Microchip Technology Inc.
DS30010198B-page 153
TABLE 11-13: PPS INPUT CONTROL FOR RPINR REGISTERS
Register
Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RPINR0
RPINR1
RPINR2
RPINR3
RPINR4
RPINR5
RPINR6
RPINR7
RPINR8
RPINR9
RPINR10
RPINR11
RPINR12
RPINR13
RPINR14
RPINR15
RPINR16
RPINR17
RPINR18
RPINR19
RPINR20
RPINR21
RPINR22
RPINR23
RPINR24
RPINR25
RPINR26
RPINR27
790h
792h
794h
796h
798h
79Ah
79Ch
79Eh
7A0h
7A2h
7A4h
7A6h
7A8h
7AAh
7ACh
7AEh
7B0h
7B2h
7B4h
7B6h
7B8h
7BAh
7BCh
7BEh
7C0h
7C2h
7C4h
7C6h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1R[5:0]
INT3R[5:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT2R[5:0]
—
—
—
—
—
—
INT4R[5:0]
T2CKR[5:0]
T4CKR[5:0]
ICM1R[5:0]
ICM3R[5:0]
T3CKR[5:0]
T5CKR[5:0]
ICM2R[5:0]
ICM4R[5:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OCFBR[5:0]
TCKIBR[5:0]
TMPRNR[5:0]
OCFAR[5:0]
TCKIAR[5:0]
REFI1R[5:0]
ICM5R[5:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U3RXR[5:0]
U1CTSR[5:0]
U2CTSR[5:0]
SCK1R[5:0]
U3CTSR[5:0]
SCK2R[5:0]
TXCKR[5:0]
U1RXR[5:0]
U2RXR[5:0]
SDI1R[5:0]
SS1R[5:0]
SDI2R[5:0]
SS2R[5:0]
—
—
—
—
CLCINBR[5:0]
CLCINDR[5:0]
U4CTSR[5:0]
—
—
—
—
—
—
—
—
CLCINAR[5:0]
CLCINCR[5:0]
U4RXR[5:0]
TABLE 11-14: PPS OUTPUT CONTROL FOR RPOR REGISTERS
Register
Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RPOR0
RPOR1
RPOR2
RPOR3
RPOR4
RPOR5
RPOR6
RPOR7
RPOR8
RPOR9
RPOR10
RPOR11
RPOR12
RPOR13
RPOR14
RPOR15
7D4h
7D6h
7D8h
7DAh
7DCh
7DEh
7E0h
7E2h
7E4h
7E6h
7E8h
7EAh
7ECh
7EEh
7F0h
7F2h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RP1R[5:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RP0R[5:0]
RP3R[5:0]
RP5R[5:0]
RP7R[5:0]
RP9R[5:0]
RP11R[5:0]
RP13R[5:0]
RP15R[5:0]
RP17R[5:0]
RP19R[5:0]
RP21R[5:0]
RP23R[5:0]
RP25R[5:0]
RP27R[5:0]
RP29R[5:0]
RP31R[5:0]
RP2R[5:0]
RP4R[5:0]
RP6R[5:0]
RP8R[5:0]
RP10R[5:0]
RP12R[5:0]
RP14R[5:0]
RP16R[5:0]
RP18R[5:0]
RP20R[5:0]
RP22R[5:0]
RP24R[5:0]
RP26R[5:0]
RP28R[5:0]
RP30R[5:0]
PIC24FJ128GL306 FAMILY
NOTES:
DS30010198B-page 156
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Figure 12-1 presents a block diagram of the 16-bit
timer module.
12.0 TIMER1
Note:
This data sheet summarizes the features of
To configure Timer1 for operation:
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive ref-
erence source. For more information,
refer to “Timers” (www.microchip.com/
DS39704) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in
this data sheet supersedes the
information in the FRM.
1. Set the TON bit (= 1).
2. Select the timer prescaler ratio using the
TCKPS[1:0] bits.
3. Set the Clock and Gating modes using the TCS,
TECS[1:0] and TGATE bits.
4. Set or clear the TSYNC bit to configure
synchronous or asynchronous operation.
5. Load the timer period value into the PR1
register.
The Timer1 module is a 16-bit timer, which can serve
as the time counter for the Real-Time Clock (RTC) or
operate as a free-running, interval timer/counter.
Timer1 can operate in three modes:
6. If interrupts are required, set the interrupt enable
bit, T1IE. Use the priority bits, T1IP[2:0], to set
the interrupt priority.
• 16-Bit Timer
• 16-Bit Synchronous Counter
• 16-Bit Asynchronous Counter
Timer1 also supports these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during CPU Idle and Sleep modes
• Interrupt on 16-Bit Period Register Match or
Falling Edge of External Gate Signal
FIGURE 12-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
TGATE
LPRC
Clock
Input Select
1
0
D
Q
Q
SOSCO
Set T1IF
CK
Reset
Equal
TMR1
SOSCI
Comparator
PR1
SOSCSEL
SOSCEN
Clock Input Select Detail
TECS[1:0]
Gate
Output
2
SOSC
Input
TCKPS[1:0]
TON
2
T1CK Input
LPRC Input
TxCK Input
Prescaler
1, 8, 64, 256
Gate
Sync
0
Clock
Output
to TMR1
1
Sync
TCY
TSYNC
TGATE
TCS
2019-2020 Microchip Technology Inc.
DS30010198B-page 157
PIC24FJ128GL306 FAMILY
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER(1)
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
TECS1
TECS0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
TCS
U-0
—
TGATE
TCKPS1
TCKPS0
TSYNC
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timer1 On bit
1= Starts 16-bit Timer1
0= Stops 16-bit Timer1
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Timer1 Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-10
bit 9-8
Unimplemented: Read as ‘0’
TECS[1:0]: Timer1 Extended Clock Source Select bits (selected when TCS = 1)
11= Generic timer (TxCK) external input
10= LPRC Oscillator
01= T1CK External Clock input
00= SOSC
bit 7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation is enabled
0= Gated time accumulation is disabled
bit 5-4
TCKPS[1:0]: Timer1 Input Clock Prescale Select bits
11= 1:256
10= 1:64
01= 1:8
00= 1:1
bit 3
bit 2
Unimplemented: Read as ‘0’
TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1= Synchronizes the External Clock input
0= Does not synchronize the External Clock input
When TCS = 0:
This bit is ignored.
bit 1
bit 0
TCS: Timer1 Clock Source Select bit
1= Extended clock is selected by the timer
0= Internal clock (FOSC/2)
Unimplemented: Read as ‘0’
Note 1: Changing the value of T1CON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
DS30010198B-page 158
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
To configure Timer2/3 or Timer4/5 for 32-bit operation:
13.0 TIMER2/3 AND TIMER4/5
1. Set the T32 bit (T2CON[3] = 1 or
T4CON[3] = 1).
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive refer-
ence source. For more information, refer to
“Timers” (www.microchip.com/DS39704)
in the “dsPIC33/PIC24 Family Reference
Manual”. The information in this data sheet
supersedes the information in the FRM.
2. Select the prescaler ratio for Timer2 or Timer4
using the TCKPS[1:0] bits.
3. Set the Clock and Gating modes using the TCS
and TGATE bits. If TCS is set to an External
Clock, RPINRx (TyCK) must be configured to
an available RPn/RPIn pin. For more informa-
tion, see Section 11.5 “Peripheral Pin Select
(PPS)”.
The Timer2/3 and Timer4/5 modules are 32-bit timers,
which can also be configured as independent, 16-bit
timers with selectable operating modes.
4. Load the timer period value. PR3 or PR5 will
contain the most significant word (msw) of the
value, while PR2 or PR4 contains the least
significant word (lsw).
As a 32-bit timer, Timer2/3 or Timer4/5 can operate in
three modes:
5. If interrupts are required, set the interrupt enable
bit, T3IE or T5IE. Use the priority bits, T3IP[2:0] or
T5IP[2:0], to set the interrupt priority. Note that
while Timer2 or Timer4 controls the timer, the
interrupt appears as a Timer3 or Timer5 interrupt.
• Two Independent 16-Bit Timers with All 16-Bit
Operating modes (except Asynchronous Counter
mode)
• Single 32-Bit Timer
• Single 32-Bit Synchronous Counter
6. Set the TON bit (= 1).
They also support these features:
The timer value, at any point, is stored in the register
pair, TMR[3:2] (or TMR[5:4]). TMR3 (or TMR5) always
contains the most significant word of the count, while
TMR2 (or TMR4) contains the least significant word.
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during Idle and Sleep modes
• Interrupt on a 32-Bit Period Register Match
To configure any of the timers for individual 16-bit
operation:
• A/D Event Trigger (on Timer4/5 in 32-bit mode
and Timer5 in 16-bit mode)
1. Clear the T32 bit (T2CON[3] for Timer2 and
Timer3 or T4CON[3] for Timer4 and Timer5).
Individually, all of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed above, except for the A/D event trigger.
This trigger is implemented only on Timer4/5 in 32-bit
mode and Timer5 in 16-bit mode. The operating modes
and enabled features are determined by setting the
appropriate bit(s) in the T2CON, T3CON, T4CON and
T5CON registers. T2CON and T4CON are shown in
generic form in Register 13-1; T3CON and T5CON are
shown in Register 13-2.
2. Select the timer prescaler ratio using the
TCKPS[1:0] bits.
3. Set the Clock and Gating modes using the TCS
and TGATE bits. See Section 11.5 “Peripheral
Pin Select (PPS)” for more information.
4. Load the timer period value into the PRx register.
5. If interrupts are required, set the interrupt enable
bit, TxIE. Use the priority bits, TxIP[2:0], to set
the interrupt priority.
For 32-bit timer/counter operation, Timer2 and Timer4
are the least significant word; Timer3 and Timer5 are
the most significant word of the 32-bit timer.
6. Set the TON bit (TxCON[15] = 1).
Note:
For 32-bit operation, T3CON and T5CON
control bits are ignored. Only T2CON and
T4CON control bits are used for setup and
control. Timer2 and Timer4 clocks, and
gate inputs are utilized for the 32-bit timer
modules, but an interrupt is generated
with the Timer3 and Timer5 interrupt flags.
2019-2020 Microchip Technology Inc.
DS30010198B-page 159
PIC24FJ128GL306 FAMILY
FIGURE 13-1:
TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM
TCY
T2CK (T4CLK)
TxCK
TCKPS[1:0]
2
SOSC Input
LPRC Input
Prescaler
1, 8, 64, 256
Gate
Sync
TECS[1:0]
(2)
(2)
TGATE
TGATE
TCS
1
Q
Q
D
Set T3IF (T5IF)
0
CK
PR3
PR2
(PR5)
(PR4)
Equal
Reset
Comparator
(3)
A/D Event Trigger
MSB
LSB
TMR2
(TMR4)
TMR3
(TMR5)
Sync
16
(1)
(1)
Read TMR2 (TMR4)
Write TMR2 (TMR4)
16
16
TMR3HLD
(TMR5HLD)
Data Bus[15:0]
Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are
respective to the T2CON and T4CON registers.
2: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.5 “Peripheral
Pin Select (PPS)” for more information.
3: The A/D event trigger is available only on Timer4/5 in 32-bit mode and Timer4 in 16-bit mode.
DS30010198B-page 160
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
FIGURE 13-2:
TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TCY
T2CK (T4CLK)
TCKPS[1:0]
2
TxCK
SOSC Input
LPRC Input
TON
Prescaler
1, 8, 64, 256
Gate
Sync
TECS[1:0]
(1)
(1)
TGATE
TGATE
TCS
1
0
Q
D
Set T2IF (T4IF)
Q
CK
Reset
Equal
Sync
TMR2 (TMR4)
Comparator
PR2 (PR4)
Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.5 “Peripheral
Pin Select (PPS)” for more information.
FIGURE 13-3:
TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM
TCY
T3CK (T5CLK)
TxCK
TCKPS[1:0]
2
TON
SOSC Input
LPRC Input
Prescaler
1, 8, 64, 256
Gate
Sync
TECS[1:0]
(1)
(1)
TGATE
TGATE
TCS
1
0
Q
Q
D
Set T3IF (T5IF)
CK
Reset
Equal
TMR3 (TMR5)
Comparator
PR3 (PR5)
(2)
A/D Event Trigger
Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.5 “Peripheral
Pin Select (PPS)” for more information.
2: The A/D event trigger is available only on Timer5.
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REGISTER 13-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(1)
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
R/W-0
TECS1(2)
R/W-0
TECS0(2)
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
T32(3)
U-0
—
R/W-0
TCS(2)
U-0
—
TGATE
TCKPS1
TCKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
TON: Timerx On bit
When TxCON[3] = 1:
1= Starts 32-bit Timerx/y
0= Stops 32-bit Timerx/y
When TxCON[3] = 0:
1= Starts 16-bit Timerx
0= Stops 16-bit Timerx
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Timerx Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-10
bit 9-8
Unimplemented: Read as ‘0’
TECS[1:0]: Timerx Extended Clock Source Select bits (selected when TCS = 1)(2)
When TCS = 1:
11= Generic timer (TxCK) external input
10= LPRC Oscillator
01= TyCK External Clock input
00= SOSC
When TCS = 0:
These bits are ignored; the timer is clocked from the internal system clock (FOSC/2).
bit 7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation is enabled
0= Gated time accumulation is disabled
bit 5-4
TCKPS[1:0]: Timerx Input Clock Prescale Select bits
11= 1:256
10= 1:64
01= 1:8
00= 1:1
Note 1: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
2: If TCS = 1and TECS[1:0] = x1, the selected external timer input (TxCK or TyCK) must be configured to an
available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
3: In 32-bit mode, the T3CON and T5CON control bits do not affect 32-bit timer operation.
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REGISTER 13-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(1) (CONTINUED)
bit 3
T32: 32-Bit Timer Mode Select bit(3)
1= Timerx and Timery form a single 32-bit timer
0= Timerx and Timery act as two 16-bit timers
bit 2
bit 1
Unimplemented: Read as ‘0’
TCS: Timerx Clock Source Select bit(2)
1= Timer source is selected by TECS[1:0]
0= Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
2: If TCS = 1and TECS[1:0] = x1, the selected external timer input (TxCK or TyCK) must be configured to an
available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
3: In 32-bit mode, the T3CON and T5CON control bits do not affect 32-bit timer operation.
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REGISTER 13-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(1)
R/W-0
TON(2)
U-0
—
R/W-0
TSIDL(2)
U-0
—
U-0
—
U-0
—
R/W-0
TECS1(2,3)
R/W-0
TECS0(2,3)
bit 15
bit 8
U-0
—
R/W-0
TGATE(2)
R/W-0
TCKPS1(2)
R/W-0
TCKPS0(2)
U-0
—
U-0
—
R/W-0
TCS(2,3)
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
TON: Timery On bit(2)
1= Starts 16-bit Timery
0= Stops 16-bit Timery
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Timery Stop in Idle Mode bit(2)
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-10
bit 9-8
Unimplemented: Read as ‘0’
TECS[1:0]: Timery Extended Clock Source Select bits (selected when TCS = 1)(2,3)
11= Generic timer (TxCK) external input
10= LPRC Oscillator
01= TyCK External Clock input
00= SOSC
bit 7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timery Gated Time Accumulation Enable bit(2)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation is enabled
0= Gated time accumulation is disabled
bit 5-4
TCKPS[1:0]: Timery Input Clock Prescale Select bits(2)
11= 1:256
10= 1:64
01= 1:8
00= 1:1
bit 3-2
bit 1
Unimplemented: Read as ‘0’
TCS: Timery Clock Source Select bit(2,3)
1= External clock from pin, TyCK (on the rising edge)
0= Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to
reset and is not recommended.
2: When 32-bit operation is enabled (T2CON[3] = 1or T4CON[3] = 1), this bit has no effect on Timery
operation; all timer functions are set through T2CON and T4CON.
3: If TCS = 1and TECS[1:0] = x1, the selected external timer input (TyCK) must be configured to an
available RPn/RPIn pin. For more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
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A conceptual block diagram for the module is shown in
Figure 14-1. All three modules share a time base gener-
ator and a common Timer register pair (CCPxTMRH/L);
other shared hardware components are added as a
particular mode requires.
14.0 CAPTURE/COMPARE/PWM/
TIMER MODULES (MCCP)
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to “Capture/Compare/PWM/Timer
(MCCP and SCCP)” (www.microchip.com/
DS30003035) in the “dsPIC33/PIC24 Fam-
ily Reference Manual”. The information in
this data sheet supersedes the information
in the FRM.
Each module has a total of eight control and status
registers:
• CCPxCON1L (Register 14-1)
• CCPxCON1H (Register 14-2)
• CCPxCON2L (Register 14-3)
• CCPxCON2H (Register 14-4)
• CCPxCON3L (Register 14-5)
• CCPxCON3H (Register 14-6)
• CCPxSTATL (Register 14-7)
PIC24FJ128GL306 family devices include several
Capture/Compare/PWM/Timer base modules, which
provide the functionality of three different peripherals of
earlier PIC24F devices. The module can operate in one
of three major modes:
Each module also includes eight buffer/counter
registers that serve as Timer Value registers or data
holding buffers:
• General Purpose Timer
• Input Capture
• Output Compare/PWM
• CCPxTMRH/CCPxTMRL (CCPx Timer High/Low
Counters)
• CCPxPRH/CCPxPRL (CCPx Timer Period High/
Low)
This family of devices features five instances of the
MCCP module. MCCP1 provides up to six outputs and
an extended range of power control features, whereas
MCCP2-MCCP5 support two outputs.
• CCPxRAH/CCPxRAL (CCPx Primary Output
Compare Data High/Low Buffers)
• CCPxRBH/CCPxRBL (CCPx Secondary Output
Compare Data High/Low Buffers)
The MCCPx modules can be operated only in one of
the three major modes at any time. The other modes
are not available unless the module is reconfigured for
the new mode.
• CCPxBUFH/CCPxBUFL (CCPx Input Capture
High/Low Buffers)
FIGURE 14-1:
MCCPx CONCEPTUAL BLOCK DIAGRAM
CCPxIF
CCTxIF
External
Input Capture
CCPxTMRH/L
Sync/Trigger Out
Capture Input
Special Trigger (to A/D)
Time Base
Generator
Clock
Sources
T32
CCSEL
Compare/PWM
Output(s)
MOD[3:0]
Output
16/32-Bit
Timer
Compare/PWM
Sync and
Gating
OCFA/OCFB
Sources
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There are eight inputs available to the clock generator,
which are selected using the CLKSEL[2:0] bits
(CCPxCON1L[10:8]). Available sources include the FRC
and LPRC, the Secondary Oscillator and the TCLKI
External Clock inputs. The system clock is the default
source (CLKSEL[2:0] = 000). On PIC24FJ128GL306
family devices, clock sources to the MCCPx modules
must be synchronized with the system clock. As a result,
when clock sources are selected, clock input timing
restrictions or module operating restrictions may exist.
14.1 Time Base Generator
The Timer Clock Generator (TCG) generates a clock
for the module’s internal time base using one of the
clock signals already available on the microcontroller.
This is used as the time reference for the module in its
three major modes. The internal time base is shown in
Figure 14-2.
FIGURE 14-2:
TIMER CLOCK GENERATOR
TMRPS[1:0]
TMRSYNC
SSDG
Clock
Sources
To Rest
of Module
Clock
Synchronizer
(1)
Prescaler
Gate
CLKSEL[2:0]
Note 1: Gating is available in Timer modes only.
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by one. This mode provides a simple timer function
when it is important to track long time periods. Note that
the T32 bit (CCPxCON1L[5]) should be set before the
CCPxTMRL or CCPxPRH registers are written to
initialize the 32-bit timer.
14.2 General Purpose Timer
Timer mode is selected when CCSEL = 0 and
MOD[3:0] = 0000. The timer can function as a 32-bit
timer or a dual 16-bit timer, depending on the setting of
the T32 bit (Table 14-1).
14.2.1
SYNC AND TRIGGER OPERATION
TABLE 14-1: TIMER OPERATION MODE
In both 16-bit and 32-bit modes, the timer can also
function in either Synchronization (“Sync”) or Trigger
mode operation. Both use the SYNC[4:0] bits
(CCPxCON1H[4:0]) to determine the input signal source.
The difference is how that signal affects the timer.
T32
Operating Mode
(CCPxCON1L[5])
0
1
Dual Timer Mode (16-bit)
Timer Mode (32-bit)
In Sync operation, the Timer Reset or clear occurs when
the input selected by SYNC[4:0] is asserted. The timer
immediately begins to count again from zero unless it is
held for some other reason. Sync operation is used when-
ever the TRIGEN bit (CCPxCON1H[7]) is cleared. The
SYNC[4:0] bits can have any value except ‘11111’.
Dual 16-Bit Timer mode provides a simple timer function
with two independent 16-bit timer/counters. The primary
timer uses the CCPxTMRL and CCPxPRL registers.
Only the primary timer can interact with other modules
on the device. It generates the MCCPx Sync out signals
for use by other MCCPx modules. It can also use the
SYNC[4:0] bits’ signal generated by other modules.
In Trigger mode operation, the timer is held in Reset
until the input selected by SYNC[4:0] is asserted; when
it occurs, the timer starts counting. Trigger operation is
used whenever the TRIGEN bit is set. In Trigger mode,
the timer will continue running after a trigger event as
long as the CCPTRIG bit (CCPxSTATL[7]) is set. To
clear CCPTRIG, the TRCLR bit (CCPxSTATL[5]) must
be set to clear the trigger event, reset the timer and
hold it at zero until another trigger event occurs. On
PIC24FJ128GL306 family devices, Trigger mode
operation can only be used when the system clock is
the time base source (CLKSEL[2:0] = 000).
The secondary timer uses the CCPxTMRH and
CCPxPRH registers. It is intended to be used only as a
periodic interrupt source for scheduling CPU events. It
does not generate an output Sync/trigger signal like the
primary time base. In Dual Timer mode, the CCPx Timer
Period High register, CCPxPRH, generates the MCCPx
compare event (CCPxIF) used by many other modules
on the device.
The 32-Bit Timer mode uses the CCPxTMRL and
CCPxTMRH registers, together, as a single 32-bit timer.
When CCPxTMRL overflows, CCPxTMRH increments
FIGURE 14-3:
DUAL 16-BIT TIMER MODE
CCPxPRL
Comparator
Set CCTxIF
Sync/
Trigger
Control
SYNC[4:0]
CCPxTMRL
Comparator
Special Event Trigger
Time Base
Generator
Clock
Sources
CCPxRB
CCPxTMRH
Comparator
CCPxPRH
Set CCPxIF
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FIGURE 14-4:
32-BIT TIMER MODE
Sync/
Trigger
Control
SYNC[4:0]
Time Base
Generator
Clock
Sources
CCPxTMRH
CCPxTMRL
CCPxPRL
Comparator
Set CCTxIF
CCPxPRH
output pulses. Like most PIC® MCU peripherals, the
Output Compare x module can also generate interrupts
on a compare match event.
14.3 Output Compare Mode
Output Compare mode compares the Timer register
value with the value of one or two Compare registers,
depending on its mode of operation. The Output
Compare x module, on compare match events, has the
ability to generate a single output transition or a train of
Table 14-2 shows the various modes available in
Output Compare modes.
TABLE 14-2: OUTPUT COMPARE/PWM MODES
MOD[3:0]
T32
Operating Mode
(CCPxCON1L[3:0]) (CCPxCON1L[5])
0001
0001
0010
0010
0011
0011
0100
0101
0110
0111
1111
0
1
0
1
0
1
0
0
0
0
0
Output High on Compare (16-bit)
Output High on Compare (32-bit)
Output Low on Compare (16-bit)
Output Low on Compare (32-bit)
Output Toggle on Compare (16-bit)
Output Toggle on Compare (32-bit)
Dual Edge Compare (16-bit)
Single Edge Mode
Dual Edge Mode
PWM Mode
Dual Edge Compare (16-bit buffered)
Center-Aligned Pulse (16-bit buffered)(1)
Variable Frequency Pulse (16-bit)(1)
External Input Source Mode (16-bit)
Center PWM Mode
Note 1: Available only on the MCCP1 module.
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FIGURE 14-5:
OUTPUT COMPARE x BLOCK DIAGRAM
CCPxCON1H/L
CCPxCON2H/L
CCPxCON3H/L
CCPxPRL
Comparator
CCPxRAH/L
Rollover/Reset
CCPxRA Buffer
Comparator
OCx Output,
Auto-Shutdown
and Polarity
Control
CCPx Pin(s)
OCFA/OCFB
Match
Event
Time Base
Generator
OCx Clock
Sources
Edge
Detect
Increment
Reset
CCPxTMRH/L
Comparator
Rollover
Match
Event
Match Event
Trigger and
Sync Logic
Fault Logic
Trigger and
Sync Sources
CCPxRB Buffer
Rollover/Reset
CCPxRBH/L
Output Compare
Interrupt
Reset
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Input Capture mode uses a dedicated 16/32-bit, synchro-
nous, up counting timer for the capture function. The timer
value is written to the FIFO when a capture event occurs.
The internal value may be read (with a synchronization
delay) using the CCPxTMRH/L registers.
14.4 Input Capture Mode
Input Capture mode is used to capture a timer value
from an independent timer base upon an event on an
input pin or other internal Trigger source. The input
capture features are useful in applications requiring
frequency (time period) and pulse measurement.
Figure 14-6 depicts a simplified block diagram of the
Input Capture mode.
To use Input Capture mode, the CCSEL bit
(CCPxCON1L[4]) must be set. The T32 and MOD[3:0]
bits are used to select the proper Capture mode, as
shown in Table 14-3.
TABLE 14-3: INPUT CAPTURE MODES
MOD[3:0]
(CCPxCON1L[3:0])
T32
Operating Mode
(CCPxCON1L[5])
0000
0000
0001
0001
0010
0010
0011
0011
0100
0100
0101
0101
0
1
0
1
0
1
0
1
0
1
0
1
Edge Detect (16-bit capture)
Edge Detect (32-bit capture)
Every Rising (16-bit capture)
Every Rising (32-bit capture)
Every Falling (16-bit capture)
Every Falling (32-bit capture)
Every Rise/Fall (16-bit capture)
Every Rise/Fall (32-bit capture)
Every 4th Rising (16-bit capture)
Every 4th Rising (32-bit capture)
Every 16th Rising (16-bit capture)
Every 16th Rising (32-bit capture)
FIGURE 14-6:
INPUT CAPTURE x BLOCK DIAGRAM
ICS[2:0]
MOD[3:0]
OPS[3:0]
Event and
Interrupt
Logic
Set CCPxIF
Edge Detect Logic
Clock
ICx Clock
Sources
and
Select
Clock Synchronizer
Increment
Reset
16
Trigger and
Sync Logic
Trigger and
Sync Sources
4-Level FIFO Buffer
CCPxTMRH/L
T32
16
16
CCPxBUFx
System Bus
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The type of output signal is selected using the
AUXOUT[1:0] control bits (CCPxCON2H[4:3]). The
type of output signal is also dependent on the module
operating mode.
14.5 Auxiliary Output
The MCCPx modules have an auxiliary (secondary)
output that provides other peripherals access to inter-
nal module signals. The auxiliary output is intended to
connect to other MCCPx modules, or other digital
peripherals, to provide these types of functions:
• Time Base Synchronization
• Peripheral Trigger and Clock Inputs
• Signal Gating
TABLE 14-4: AUXILIARY OUTPUT
AUXOUT[1:0]
CCSEL
MOD[3:0]
Comments
Signal Description
No Output
00
01
10
11
01
10
11
01
10
11
x
0
xxxx
0000
Auxiliary Output Disabled
Time Base Modes
Time Base Period Reset or Rollover
Special Event Trigger Output
No Output
0
1
0001
through
1111
Output Compare Modes
Input Capture Modes
Time Base Period Reset or Rollover
Output Compare Event Signal
Output Compare Signal
xxxx
Time Base Period Reset or Rollover
Reflects the Value of the ICDIS bit
Input Capture Event Signal
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REGISTER 14-1: CCPxCON1L: CCPx CONTROL 1 LOW REGISTERS
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCPON
CCPSIDL
CCPSLP
TMRSYNC
CLKSEL2
CLKSEL1
CLKSEL0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
T32
R/W-0
R/W-0
MOD3
R/W-0
MOD2
R/W-0
MOD1
R/W-0
MOD0
TMRPS1
TMRPS0
CCSEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
CCPON: CCPx Module Enable bit
1= Module is enabled with an operating mode specified by the MOD[3:0] control bits
0= Module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
CCPSIDL: CCPx Stop in Idle Mode Bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12
CCPSLP: CCPx Sleep Mode Enable bit
1= Module continues to operate in Sleep modes
0= Module does not operate in Sleep modes
bit 11
TMRSYNC: Time Base Clock Synchronization bit
1= Module time base clock is synchronized to the internal system clocks; timing restrictions apply
0= Module time base clock is not synchronized to the internal system clocks
bit 10-8
CLKSEL[2:0]: CCPx Time Base Clock Select bits
111= TCKIA pin
110= TCKIB pin
101= PLL clock
100= 2x system clock
010= SOSC clock
001= Reference clock output
000= System clock
For MCCP1 and MCCP5:
011= CLC1 output
For MCCP2:
011= CLC2 output
For MCCP3:
011= CLC3 output
For MCCP4:
011= CLC4 output
bit 7-6
TMRPS[1:0]: Time Base Prescale Select bits
11= 1:64 Prescaler
10= 1:16 Prescaler
01= 1:4 Prescaler
00= 1:1 Prescaler
Note 1: Available only on the MCCP1 module.
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REGISTER 14-1: CCPxCON1L: CCPx CONTROL 1 LOW REGISTERS (CONTINUED)
bit 5
T32: 32-Bit Time Base Select bit
1= Uses 32-bit time base for timer, single edge output compare or input capture function
0= Uses 16-bit time base for timer, single edge output compare or input capture function
bit 4
CCSEL: Capture/Compare Mode Select bit
1= Input capture peripheral
0= Output compare/PWM/timer peripheral (exact function is selected by the MOD[3:0] bits)
bit 3-0
MOD[3:0]: CCPx Mode Select bits
For CCSEL = 1(Input Capture modes):
1xxx= Reserved
011x= Reserved
0101= Capture every 16th rising edge
0100= Capture every 4th rising edge
0011= Capture every rising and falling edge
0010= Capture every falling edge
0001= Capture every rising edge
0000= Capture every rising and falling edge (Edge Detect mode)
For CCSEL = 0(Output Compare/Timer modes):
1111= External Input mode: Pulse generator is disabled, source is selected by ICS[2:0]
1110= Reserved
110x= Reserved
10xx= Reserved
0111= Variable Frequency Pulse mode(1)
0110= Center-Aligned Pulse Compare mode, buffered(1)
0101= Dual Edge Compare mode, buffered
0100= Dual Edge Compare mode
0011= 16-Bit/32-Bit Single Edge mode, toggles output on compare match
0010= 16-Bit/32-Bit Single Edge mode, drives output low on compare match
0001= 16-Bit/32-Bit Single Edge mode, drives output high on compare match
0000= 16-Bit/32-Bit Timer mode, output functions are disabled
Note 1: Available only on the MCCP1 module.
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REGISTER 14-2: CCPxCON1H: CCPx CONTROL 1 HIGH REGISTERS
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
OPS3(3)
R/W-0
OPS2(3)
R/W-0
OPS1(3)
R/W-0
OPS0(3)
OPSSRC(1) RTRGEN(2)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRIGEN
ONESHOT
ALTSYNC
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
OPSSRC: Output Postscaler Source Select bit(1)
1= Output postscaler scales module trigger output events
0= Output postscaler scales time base interrupt events
RTRGEN: Retrigger Enable bit(2)
1= Time base can be retriggered when the TRIGEN bit = 1
0= Time base may not be retriggered when the TRIGEN bit = 1
bit 13-12
bit 11-8
Unimplemented: Read as ‘0’
OPS3[3:0]: CCPx Interrupt Output Postscale Select bits(3)
1111= Interrupt every 16th time base period match
1110= Interrupt every 15th time base period match
...
0100= Interrupt every 5th time base period match
0011= Interrupt every 4th time base period match or 4th input capture event
0010= Interrupt every 3rd time base period match or 3rd input capture event
0001= Interrupt every 2nd time base period match or 2nd input capture event
0000= Interrupt after each time base period match or input capture event
bit 7
TRIGEN: CCPx Trigger Enable bit
1= Trigger operation of time base is enabled
0= Trigger operation of time base is disabled
bit 6
ONESHOT: One-Shot Mode Enable bit
1= One-Shot Trigger mode is enabled; Trigger mode duration is set by the OSCNT[2:0] bits
0= One-Shot Trigger mode is disabled
bit 5
ALTSYNC: CCPx Clock Select bit
1= An alternate signal is used as the module synchronization output signal
0= The module synchronization output signal is the Time Base Reset/rollover event
bit 4-0
SYNC[4:0]: CCPx Synchronization Source Select bits
See Table 14-5 for the definition of inputs.
Note 1: This control bit has no function in Input Capture modes.
2: This control bit has no function when TRIGEN = 0.
3: Output postscale settings, from 1:5 to 1:16 (0100-1111), will result in a FIFO buffer overflow for
Input Capture modes.
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TABLE 14-5: SYNCHRONIZATION SOURCES
SYNC[4:0]
Synchronization Source
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
None; Timer with Rollover on CCPxPR Match or FFFFh
Reserved
Reserved
Reserved
A/D Start Conversion
CMP3 Trigger
CMP2 Trigger
CMP1 Trigger
Reserved
Reserved
Reserved
Reserved
CLC4 Out
CLC3 Out
CLC2 Out
CLC1 Out
Reserved
Reserved
Reserved
Reserved
INT2 Pad
INT1 Pad
INT0 Pad
Reserved
Reserved
MCCP5 Sync Out
MCCP4 Sync Out
MCCP3 Sync Out
MCCP2 Sync Out
MCCP1 Sync Out
MCCPx Sync Out(1)
MCCPx Timer Sync Out(1)
Note 1: CCP1 when connected to CCP1, CCP2 when connected to CCP2, etc.
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REGISTER 14-3: CCPxCON2L: CCPx CONTROL 2 LOW REGISTERS
R/W-0
PWMRSEN
bit 15
R/W-0
U-0
—
R/W-0
SSDG
U-0
—
U-0
—
U-0
—
U-0
—
ASDGM
bit 8
R/W-0
ASDG7
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ASDG6
ASDG5
ASDG4
ASDG3
ASDG2
ASDG1
ASDG0
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
PWMRSEN: CCPx PWM Restart Enable bit
1= ASEVT bit clears automatically at the beginning of the next PWM period, after the shutdown input
has ended
0= ASEVT bit must be cleared in software to resume PWM activity on output pins
ASDGM: CCPx Auto-Shutdown Gate Mode Enable bit
1= Waits until the next Time Base Reset or rollover for shutdown to occur
0= Shutdown event occurs immediately
bit 13
bit 12
Unimplemented: Read as ‘0’
SSDG: CCPx Software Shutdown/Gate Control bit
1= Manually forces auto-shutdown, timer clock gate or input capture signal gate event (setting of
ASDGM bit still applies)
0= Normal module operation
bit 11-8
bit 7-0
Unimplemented: Read as ‘0’
ASDG[7:0]: CCPx Auto-Shutdown/Gating Source Enable bits
1= ASDGx Source n is enabled (see Table 14-6 for auto-shutdown/gating sources)
0= ASDGx Source n is disabled
TABLE 14-6: AUTO-SHUTDOWN SOURCES
ASDG[7:0]
Auto-Shutdown Source
MCCP3
MCCP1
MCCP2
MCCP4
MCCP5
1xxx xxxx
OCFB
OCFA
x1xx xxxx
xx1x xxxx CLC1
CLC2
CLC3
CLC4
CLC1
xxx1 xxxx MCCP2 OCM Out MCCP1 OCM Out MCCP1 OCM Out MCCP1 OCM Out MCCP1 OCM Out
xxxx 1xxx MCCP3 OCM Out MCCP3 OCM Out MCCP4 OCM Out MCCP5 OCM Out MCCP2 OCM Out
xxxx x1xx
xxxx xx1x
xxxx xxx1
CMP3 Out
CMP2 Out
CMP1 Out
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REGISTER 14-4: CCPxCON2H: CCPx CONTROL 2 HIGH REGISTERS
R/W-0
OENSYNC
bit 15
U-0
—
R/W-0(1)
OCFEN
R/W-0(1)
OCEEN
R/W-0(1)
OCDEN
R/W-0(1)
OCCEN
R/W-0
R/W-1
OCBEN
OCAEN
bit 8
R/W-0
ICGSM1
bit 7
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
ICS2
R/W-0
ICS1
R/W-0
ICS0
ICGSM0
AUXOUT1
AUXOUT0
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
OENSYNC: Output Enable Synchronization bit
1= Update by output enable bits occurs on the next Time Base Reset or rollover
0= Update by output enable bits occurs immediately
bit 14
Unimplemented: Read as ‘0’
bit 13-8
OC[F:A]EN: Output Enable/Steering Control bits(1)
1= OCMnx pin is controlled by the CCPx module and produces an output compare or PWM signal
0= OCMnx pin is not controlled by the CCPx module; the pin is available to the port logic or another
peripheral multiplexed on the pin
bit 7-6
ICGSM[1:0]: Input Capture Gating Source Mode Control bits
11= Reserved
10= One-Shot mode: Falling edge from gating source disables future capture events (ICDIS = 1)
01= One-Shot mode: Rising edge from gating source enables future capture events (ICDIS = 0)
00= Level-Sensitive mode: A high level from gating source will enable future capture events; a low
level will disable future capture events
bit 5
Unimplemented: Read as ‘0’
bit 4-3
AUXOUT[1:0]: Auxiliary Output Signal on Event Selection bits
11= Input capture or output compare event; no signal in Timer mode
10= Signal output is defined by module operating mode (see Table 14-4)
01= Time base rollover event (all modes)
00= Disabled
bit 2-0
ICS[2:0]: Input Capture Source Select bits
111= CLC4 output
110= CLC3 output
101= CLC2 output
100= CLC1 output
011= Comparator 3 output
010= Comparator 2 output
001= Comparator 1 output
000= Input Capture x (ICMx) I/O pin
Note 1: The OC[F:C]EN bits are available only on the MCCP1 module.
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REGISTER 14-5: CCPxCON3L: CCPx CONTROL 3 LOW REGISTERS
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DT[5:0]
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
DT[5:0]: CCPx Dead-Time Select bits
111111= Inserts 63 dead-time delay periods between complementary output signals
111110= Inserts 62 dead-time delay periods between complementary output signals
...
000010= Inserts 2 dead-time delay periods between complementary output signals
000001= Inserts 1 dead-time delay period between complementary output signals
000000= Dead-time logic is disabled
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REGISTER 14-6: CCPxCON3H: CCPx CONTROL 3 HIGH REGISTERS
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
OETRIG
OSCNT2
OSCNT1
OSCNT0
OUTM2
OUTM1
OUTM0
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POLACE
POLBDF
PSSACE1
PSSACE0
PSSBDF1
PSSBDF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
OETRIG: CCPx Dead-Time Select bit
1= For Triggered mode (TRIGEN = 1): Module does not drive enabled output pins until triggered
0= Normal output pin operation
bit 14-12
OSCNT[2:0]: One-Shot Event Count bits
111= Extends one-shot event by 7 time base periods (8 time base periods total)
110= Extends one-shot event by 6 time base periods (7 time base periods total)
101= Extends one-shot event by 5 time base periods (6 time base periods total)
100= Extends one-shot event by 4 time base periods (5 time base periods total)
011= Extends one-shot event by 3 time base periods (4 time base periods total)
010= Extends one-shot event by 2 time base periods (3 time base periods total)
001= Extends one-shot event by 1 time base period (2 time base periods total)
000= Does not extend one-shot trigger event
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OUTM[2:0]: PWMx Output Mode Control bits
111= Reserved
110= Output Scan mode
101= Brush DC Output mode, forward
100= Brush DC Output mode, reverse
011= Reserved
010= Half-Bridge Output mode
001= Push-Pull Output mode
000= Steerable Single Output mode
bit 7-6
bit 5
Unimplemented: Read as ‘0’
POLACE: CCPx Output Pins, OCMxA, OCMxC and OCMxE, Polarity Control bit
1= Output pin polarity is active-low
0= Output pin polarity is active-high
bit 4
POLBDF: CCPx Output Pins, OCMxB, OCMxD and OCMxF, Polarity Control bit
1= Output pin polarity is active-low
0= Output pin polarity is active-high
bit 3-2
PSSACE[1:0]: PWMx Output Pins, OCMxA, OCMxC and OCMxE, Shutdown State Control bits
11= Pins are driven active when a shutdown event occurs
10= Pins are driven inactive when a shutdown event occurs
0x= Pins are tri-stated when a shutdown event occurs
bit 1-0
PSSBDF[1:0]: PWMx Output Pins, OCMxB, OCMxD, and OCMxF, Shutdown State Control bits
11= Pins are driven active when a shutdown event occurs
10= Pins are driven inactive when a shutdown event occurs
0x= Pins are in a high-impedance state when a shutdown event occurs
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REGISTER 14-7: CCPxSTATL: CCPx STATUS REGISTER LOW
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
W-0
U-0
—
U-0
—
ICGARM
bit 15
bit 8
R-0
W1-0
W1-0
R/C-0
R/C-0
R/C-0
ICDIS
R/C-0
ICOV
R/C-0
CCPTRIG
TRSET
TRCLR
ASEVT
SCEVT
ICBNE
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
R = Readable bit
W1 = Write ‘1’ Only bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-11
bit 10
Unimplemented: Read as ‘0’
ICGARM: Input Capture Gate Arm bit
A write of ‘1’ to this location will arm the Input Capture x module for a one-shot gating event when
ICGSM[1:0] = 01or 10; read as ‘0’.
bit 9-8
bit 7
Unimplemented: Read as ‘0’
CCPTRIG: CCPx Trigger Status bit
1= Timer has been triggered and is running
0= Timer has not been triggered and is held in Reset
bit 6
bit 5
bit 4
TRSET: CCPx Trigger Set Request bit
Writes ‘1’ to this location to trigger the timer when TRIGEN = 1(location always reads as ‘0’).
TRCLR: CCPx Trigger Clear Request bit
Writes ‘1’ to this location to cancel the timer trigger when TRIGEN = 1(location always reads as ‘0’).
ASEVT: CCPx Auto-Shutdown Event Status/Control bit
1= A shutdown event is in progress; CCPx outputs are in the Shutdown state
0= CCPx outputs operate normally
bit 3
bit 2
bit 1
bit 0
SCEVT: Single Edge Compare Event Status bit
1= A single edge compare event has occurred
0= A single edge compare event has not occurred
ICDIS: Input Capture x Disable bit
1= Event on Input Capture x pin (ICMx) does not generate a capture event
0= Event on Input Capture x pin will generate a capture event
ICOV: Input Capture x Buffer Overflow Status bit
1= The Input Capture x FIFO buffer has overflowed
0= The Input Capture x FIFO buffer has not overflowed
ICBNE: Input Capture x Buffer Status bit
1= Input Capture x buffer has data available
0= Input Capture x buffer is empty
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The SPI serial interface consists of four pins:
15.0 SERIAL PERIPHERAL
INTERFACE (SPI)
• SDIx: Serial Data Input
• SDOx: Serial Data Output
• SCKx: Shift Clock Input or Output
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. To complement the infor-
mation in this data sheet, refer to “Serial
Peripheral Interface (SPI) with Audio
Codec Support” (www.microchip.com/
DS70005136) in the “dsPIC33/PIC24
Family Reference Manual”. The informa-
tion in this data sheet supersedes the
information in the FRM.
• SSx: Active-Low Slave Select or Frame
Synchronization I/O Pulse
The SPI module can be configured to operate using
two, three or four pins. In the 3-pin mode, SSx is not
used. In the 2-pin mode, both SDOx and SSx are not
used.
The SPI module has the ability to generate three inter-
rupts reflecting the events that occur during the data
communication. The following types of interrupts can
be generated:
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices may be serial EEPROMs, shift
registers, display drivers, A/D Converters, etc. The SPI
module is compatible with the Motorola® SPI and SIOP
interfaces. All devices in the PIC24FJ128GL306 family
include two SPI modules.
1. Receive interrupts are signalled by SPIxRXIF.
This event occurs when:
- RX watermark interrupt
- SPIROV = 1
- SPIRBF = 1
- SPIRBE = 1
provided the respective mask bits are enabled in
SPIxIMSKL/H.
The module supports operation in two buffer modes. In
Standard Buffer mode, datum is shifted through a
single serial buffer. In Enhanced Buffer mode, data are
shifted through a FIFO buffer. The FIFO level depends
on the configured mode.
2. Transmit interrupts are signalled by SPIxTXIF.
This event occurs when:
- TX watermark interrupt
- SPITUR = 1
Note:
FIFO depth for this device is 32 (in 8-Bit
Data mode).
- SPITBF = 1
- SPITBE = 1
Variable length data can be transmitted and received
from 2 to 32 bits.
provided the respective mask bits are enabled in
SPIxIMSKL/H.
Note:
Do not perform Read-Modify-Write opera-
tions (such as bit-oriented instructions) on
the SPIxBUF register in either Standard or
Enhanced Buffer mode.
3. General interrupts are signalled by SPIxIF. This
event occurs when
- FRMERR = 1
- SPIBUSY = 1
- SRMT = 1
The module also supports a basic framed SPI protocol
while operating in either Master or Slave mode. A total
of four framed SPI configurations are supported.
provided the respective mask bits are enabled in
SPIxIMSKL/H.
The module also supports Audio modes. Four different
Audio modes are available.
• I2S mode
A block diagram of the module in Enhanced Buffer mode
is shown in Figure 15-1.
• Left Justified mode
• Right Justified mode
• PCM/DSP mode
Note:
In this section, the SPI modules are
referred to together as SPIx, or separately
as SPI1 or SPI2. Special Function Regis-
ters will follow a similar notation. For
example, SPIxCON1 and SPIxCON2
refer to the control registers for either of
the two SPI modules.
In each of these modes, the serial clock is free-running
and audio data are always transferred.
If an audio protocol data transfer takes place between
two devices, then usually one device is the Master and
the other is the Slave. However, audio data can be
transferred between two Slaves. Because the audio
protocols require free-running clocks, the Master can
be a third party controller. In either case, the Master
generates two free-running clocks: SCKx and LRC
(Left, Right Channel Clock/SSx/FSYNC).
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6. Clear the SPIROV bit (SPIxSTATL[6]).
15.1 Master Mode Operation
7. Write the desired settings to the SPIxCON1L
Perform the following steps to set up the SPIx module
for Master mode operation:
register with MSTEN (SPIxCON1L[5]) = 0.
8. Enable SPI operation by setting the SPIEN bit
(SPIxCON1L[15]).
1. Disable the SPIx interrupts in the respective
IECx register.
9. Transmission (and reception) will start as soon
as the Master provides the serial clock.
2. Stop and reset the SPIx module by clearing the
SPIEN bit.
The following additional features are provided in
Slave mode:
3. Clear the receive buffer.
4. Clear the ENHBUF bit (SPIxCON1L[0]) if using
Standard Buffer mode or set the bit if using
Enhanced Buffer mode.
• Slave Select Synchronization:
The SSx pin allows a Synchronous Slave mode. If
the SSEN bit (SPIxCON1L[7]) is set, transmission
and reception are enabled in Slave mode only if
the SSx pin is driven to a low state. The port out-
put or other peripheral outputs must not be driven
in order to allow the SSx pin to function as an
input. If the SSEN bit is set and the SSx pin is
driven high, the SDOx pin is no longer driven and
will tri-state, even if the module is in the middle of
a transmission. An aborted transmission will be
tried again the next time the SSx pin is driven low
using the data held in the SPIxTXB register. If the
SSEN bit is not set, the SSx pin does not affect
the module operation in Slave mode.
5. If SPIx interrupts are not going to be used, skip
this step. Otherwise, the following additional
steps are performed:
a) Clear the SPIx interrupt flags/events in the
respective IFSx register.
b) Write the SPIx interrupt priority and
sub-priority bits in the respective IPCx
register.
c) Set the SPIx interrupt enable bits in the
respective IECx register.
6. Write the Baud Rate register, SPIxBRGL.
7. Clear the SPIROV bit (SPIxSTATL[6]).
• SPITBE Status Flag Operation:
8. Write the desired settings to the SPIxCON1L
The SPITBE bit (SPIxSTATL[3]) has a different
function in the Slave mode of operation. The
following describes the function of SPITBE for
various settings of the Slave mode of operation:
register with MSTEN (SPIxCON1L[5]) = 1.
9. Enable SPI operation by setting the SPIEN bit
(SPIxCON1L[15]).
10. Write the data to be transmitted to the
SPIxBUFL and SPIxBUFH registers. Transmis-
sion (and reception) will start as soon as data
are written to the SPIxBUFL/H registers.
- If SSEN (SPIxCON1L[7]) is cleared, the
SPITBE bit is cleared when SPIxBUF is
loaded by the user code. It is set when the
module transfers SPIxTXB to SPIxTXSR.
This is similar to the SPITBE bit function in
Master mode.
15.2 Slave Mode Operation
- If SSEN is set, SPITBE is cleared when
SPIxBUF is loaded by the user code. How-
ever, it is set only when the SPIx module
completes data transmission. A transmission
will be aborted when the SSx pin goes high
and may be retried at a later time. So, each
data word is held in SPIxTXB until all bits are
transmitted to the receiver.
The following steps are used to set up the SPIx module
for the Slave mode of operation:
1. If using interrupts, disable the SPIx interrupts in
the respective IECx register.
2. Stop and reset the SPIx module by clearing the
SPIEN bit.
3. Clear the receive buffer.
4. Clear the ENHBUF bit (SPIxCON1L[0]) if using
Standard Buffer mode or set the bit if using
Enhanced Buffer mode.
5. If using interrupts, the following additional steps
are performed:
a) Clear the SPIx interrupt flags/events in the
respective IFSx register.
b) Write the SPIx interrupt priority and
sub-priority bits in the respective IPCx
register.
c) Set the SPIx interrupt enable bits in the
respective IECx register.
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FIGURE 15-1:
SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
Internal
Data Bus
Write
Read
SPIxRXB
SPIxTXB
SPIxURDT
MSB
Transmit
Receive
SPIxRXSR
SPIxTXSR
MSB
SDIx
0
1
Shift
Control
SDOx
TXELM[5:0] = 6’b0
URDTEN
SSx and
FSYNC Control
Clock
Control
Edge
Select
MCLKEN
SSx/FSYNC
SCKx
REFO
Baud Rate
Generator
Peripheral Clock
Edge
Select
Clock
Control
Enable Master Clock
In Slave+Audio mode:
15.3 Audio Mode Operation
• This mode enables the device to receive SCKx
and LRC pulses as long as the SPIEN bit
(SPIxCON1L[15]) = 1.
To initialize the SPIx module for Audio mode, follow the
steps to initialize it for Master/Slave mode, but also set the
AUDEN bit (SPIxCON1H[15]). In Master+Audio mode:
• The SPIx module drives zeros out of SDOx, but
does not shift data out or in (SDIx) until the
module receives the LRC (i.e., the edge that
precedes the left channel).
• This mode enables the device to generate SCKx
and LRC pulses as long as the SPIEN bit
(SPIxCON1L[15]) = 1.
• The SPIx module generates LRC and SCKx
continuously, in all cases, regardless of the
transmit data while in Master mode.
• Once the module receives the leading edge
of LRC, it starts receiving data if
DISSDI (SPIxCON1L[4]) = 0and the serial data
shift out continuously, even when the TX FIFO is
empty.
• The SPIx module drives the leading edge of LRC
and SCKx within one SCKx period, and the serial
data shift in and out continuously, even when the
TX FIFO is empty.
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15.4 SPI Control Registers
REGISTER 15-1: SPIxCON1L: SPIx CONTROL REGISTER 1 LOW
R/W-0
SPIEN
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SMP
R/W-0
CKE(1)
SPISIDL
DISSDO
MODE32(1,4) MODE16(1,4)
bit 15
bit 8
R/W-0
SSEN(2)
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
MCLKEN(3)
R/W-0
SPIFE
R/W-0
MSTEN
DISSDI
DISSCK
ENHBUF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
SPIEN: SPIx On bit
1= Enables module
0= Turns off and resets module, disables clocks, disables interrupt event generation, allows SFR
modifications
bit 14
bit 13
Unimplemented: Read as ‘0’
SPISIDL: SPIx Stop in Idle Mode bit
1= Halts in CPU Idle mode
0= Continues to operate in CPU Idle mode
bit 12
DISSDO: Disable SDOx Output Port bit
1= SDOx pin is not used by the module; pin is controlled by the port function
0= SDOx pin is controlled by the module
bit 11-10
MODE[32,16]: Serial Word Length bits(1,4)
AUDEN = 0:
MODE32 MODE16
COMMUNICATION FIFO DEPTH
1
0
0
x
1
0
32-Bit
16-Bit
8-Bit
8
16
32
AUDEN = 1:
MODE32 MODE16
COMMUNICATION
1
1
0
0
1
0
1
0
24-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
32-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
16-Bit Data, 16-Bit FIFO, 32-Bit Channel/64-Bit Frame
16-Bit Data, 16-Bit FIFO, 16-Bit Channel/32-Bit Frame
bit 9
SMP: SPIx Data Input Sample Phase bit
Master Mode:
1= Input datum is sampled at the end of data output time
0= Input datum is sampled at the middle of data output time
Slave Mode:
Input datum is always sampled at the middle of data output time, regardless of the SMP setting.
Note 1: When AUDEN = 1, this module functions as if CKE = 0, regardless of its actual value.
2: When FRMEN = 1, SSEN is not used.
3: MCLKEN can only be written when the SPIEN bit = 0.
4: This channel is not meaningful for DSP/PCM mode as LRC follows the FRMSYPW bit.
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REGISTER 15-1: SPIxCON1L: SPIx CONTROL REGISTER 1 LOW (CONTINUED)
CKE: SPIx Clock Edge Select bit(1)
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1= Transmit happens on transition from active clock state to Idle clock state
0= Transmit happens on transition from Idle clock state to active clock state
SSEN: Slave Select Enable bit (Slave mode)(2)
1= SSx pin is used by the macro in Slave mode; SSx pin is used as the Slave select input
0= SSx pin is not used by the macro (SSx pin will be controlled by the port I/O)
CKP: SPIx Clock Polarity Select bit
1= Idle state for clock is a high level; active state is a low level
0= Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1= Master mode
0= Slave mode
DISSDI: Disable SDIx Input Port bit
1= SDIx pin is not used by the module; pin is controlled by the port function
0= SDIx pin is controlled by the module
DISSCK: Disable SCKx Output Port bit
1= SCKx pin is not used by the module; pin is controlled by the port function
0= SCKx pin is controlled by the module
MCLKEN: Master Clock Enable bit(3)
1= REFO is used by the BRG
0= Peripheral clock is used by the BRG
SPIFE: Frame Sync Pulse Edge Select bit
1= Frame Sync pulse (Idle-to-active edge) coincides with the first bit clock
0= Frame Sync pulse (Idle-to-active edge) precedes the first bit clock
ENHBUF: Enhanced Buffer Mode Enable bit
1= Enhanced Buffer mode is enabled
0= Enhanced Buffer mode is disabled
Note 1: When AUDEN = 1, this module functions as if CKE = 0, regardless of its actual value.
2: When FRMEN = 1, SSEN is not used.
3: MCLKEN can only be written when the SPIEN bit = 0.
4: This channel is not meaningful for DSP/PCM mode as LRC follows the FRMSYPW bit.
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REGISTER 15-2: SPIxCON1H: SPIx CONTROL REGISTER 1 HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AUDEN(1) SPISGNEXT
IGNROV
IGNTUR
AUDMONO(2) URDTEN(3) AUDMOD1(4) AUDMOD0(4)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMEN
FRMSYNC
FRMPOL
MSSEN
FRMSYPW
FRMCNT2
FRMCNT1
FRMCNT0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
AUDEN: Audio Codec Support Enable bit(1)
1= Audio protocol is enabled; MSTEN controls the direction of both the SCKx and frame (a.k.a. LRC),
and this module functions as if FRMEN = 1, FRMSYNC = MSTEN, FRMCNT[2:0] = 001 and
SMP = 0, regardless of their actual values
0= Audio protocol is disabled
bit 14
bit 13
SPISGNEXT: SPIx Sign-Extend RX FIFO Read Data Enable bit
1= Data from RX FIFO are sign-extended
0= Data from RX FIFO are not sign-extended
IGNROV: Ignore Receive Overflow bit
1= A Receive Overflow (ROV) is NOT a critical error; during ROV, data in the FIFO are not overwritten
by the receive data
0= A ROV is a critical error that stops SPI operation
bit 12
IGNTUR: Ignore Transmit Underrun bit
1= A Transmit Underrun (TUR) is NOT a critical error and data indicated by URDTEN are transmitted
until the SPIxTXB is not empty
0= A TUR is a critical error that stops SPI operation
bit 11
bit 10
bit 9-8
AUDMONO: Audio Data Format Transmit bit(2)
1= Audio data are mono (i.e., each data word is transmitted on both left and right channels)
0= Audio data are stereo
URDTEN: Transmit Underrun Data Enable bit(3)
1= Transmits data out of the SPIxURDTL/H registers during Transmit Underrun conditions
0= Transmits the last received data during Transmit Underrun conditions
AUDMOD[1:0]: Audio Protocol Mode Selection bits(4)
11= PCM/DSP mode
10= Right Justified mode: This module functions as if SPIFE = 1, regardless of its actual value
01= Left Justified mode: This module functions as if SPIFE = 1, regardless of its actual value
00= I2S mode: This module functions as if SPIFE = 0, regardless of its actual value
bit 7
FRMEN: Framed SPIx Support bit
1= Framed SPIx support is enabled (SSx pin is used as the FSYNC input/output)
0= Framed SPIx support is disabled
Note 1: AUDEN can only be written when the SPIEN bit = 0.
2: AUDMONO can only be written when the SPIEN bit = 0and is only valid for AUDEN = 1.
3: URDTEN is only valid when IGNTUR = 1.
4: AUDMOD[1:0] bits can only be written when the SPIEN bit = 0and are only valid when AUDEN = 1. When
NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.
DS30010198B-page 186
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REGISTER 15-2: SPIxCON1H: SPIx CONTROL REGISTER 1 HIGH (CONTINUED)
bit 6
bit 5
bit 4
FRMSYNC: Frame Sync Pulse Direction Control bit
1= Frame Sync pulse input (Slave)
0= Frame Sync pulse output (Master)
FRMPOL: Frame Sync/Slave Select Polarity bit
1= Frame Sync pulse/Slave select is active-high
0= Frame Sync pulse/Slave select is active-low
MSSEN: Master Mode Slave Select Enable bit
1= SPIx Slave select support is enabled with polarity determined by FRMPOL (SSx pin is automatically
driven during transmission in Master mode)
0= SPIx Slave select support is disabled (SSx pin will be controlled by port I/O)
bit 3
FRMSYPW: Frame Sync Pulse-Width bit
1= Frame Sync pulse is one serial word length wide (as defined by MODE[32,16]/WLENGTH[4:0])
0= Frame Sync pulse is one clock (SCKx) wide
bit 2-0
FRMCNT[2:0]: Frame Sync Pulse Counter bits
Controls the number of serial words transmitted per Sync pulse.
111= Reserved
110= Reserved
101= Generates a Frame Sync pulse on every 32 serial words
100= Generates a Frame Sync pulse on every 16 serial words
011= Generates a Frame Sync pulse on every 8 serial words
010= Generates a Frame Sync pulse on every 4 serial words
001= Generates a Frame Sync pulse on every 2 serial words (value used by audio protocols)
000= Generates a Frame Sync pulse on each serial word
Note 1: AUDEN can only be written when the SPIEN bit = 0.
2: AUDMONO can only be written when the SPIEN bit = 0and is only valid for AUDEN = 1.
3: URDTEN is only valid when IGNTUR = 1.
4: AUDMOD[1:0] bits can only be written when the SPIEN bit = 0and are only valid when AUDEN = 1. When
NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.
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REGISTER 15-3: SPIxCON2L: SPIx CONTROL REGISTER 2 LOW
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
WLENGTH[4:0](1,2)
R/W-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
WLENGTH[4:0]: Variable Word Length bits(1,2)
11111= 32-bit data
11110= 31-bit data
11101= 30-bit data
11100= 29-bit data
11011= 28-bit data
11010= 27-bit data
11001= 26-bit data
11000= 25-bit data
10111= 24-bit data
10110= 23-bit data
10101= 22-bit data
10100= 21-bit data
10011= 20-bit data
10010= 19-bit data
10001= 18-bit data
10000= 17-bit data
01111= 16-bit data
01110= 15-bit data
01101= 14-bit data
01100= 13-bit data
01011= 12-bit data
01010= 11-bit data
01001= 10-bit data
01000= 9-bit data
00111= 8-bit data
00110= 7-bit data
00101= 6-bit data
00100= 5-bit data
00011= 4-bit data
00010= 3-bit data
00001= 2-bit data
00000= See MODE[32,16] bits in SPIxCON1L[11:10]
Note 1: These bits are effective when AUDEN = 0only.
2: Varying the length by changing these bits does not affect the depth of the TX/RX FIFO.
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REGISTER 15-4: SPIxSTATL: SPIx STATUS REGISTER LOW
U-0
—
U-0
—
U-0
—
HS/R/C-0
FRMERR
HSC/R-0
SPIBUSY
U-0
—
U-0
—
HSC/R-0
SPITUR(1)
bit 15
bit 8
HSC/R-0
SRMT
HS/R/C-0
SPIROV
HSC/R-1
SPIRBE
U-0
—
HSC/R-1
SPITBE
U-0
—
HSC/R-0
SPITBF
HSC/R-0
SPIRBF
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit x = Bit is unknown
‘0’ = Bit is cleared HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
bit 15-13
bit 12
Unimplemented: Read as ‘0’
FRMERR: SPIx Frame Error Status bit
1= Frame error is detected
0= No frame error is detected
bit 11
SPIBUSY: SPIx Activity Status bit
1= Module is currently busy with some transactions
0= No ongoing transactions (at time of read)
bit 10-9
bit 8
Unimplemented: Read as ‘0’
SPITUR: SPIx Transmit Underrun Status bit(1)
1= Transmit buffer has encountered a Transmit Underrun (TUR) condition
0= Transmit buffer does not have a Transmit Underrun condition
bit 7
bit 6
bit 5
SRMT: Shift Register Empty Status bit
1= No current or pending transactions (i.e., neither SPIxTXB or SPIxTXSR contains data to transmit)
0= Current or pending transactions
SPIROV: SPIx Receive Overflow Status bit
1= A new byte/half-word/word has been completely received when the SPIxRXB is full
0= No overflow
SPIRBE: SPIx RX Buffer Empty Status bit
1= RX buffer is empty
0= RX buffer is not empty
Standard Buffer Mode:
Automatically set in hardware when SPIxBUF is read from, reading SPIxRXB. Automatically cleared in
hardware when SPIx transfers data from SPIxRXSR to SPIxRXB.
Enhanced Buffer Mode:
Indicates RXELM[5:0] = 6’b000000.
bit 4
bit 3
Unimplemented: Read as ‘0’
SPITBE: SPIx Transmit Buffer Empty Status bit
1= SPIxTXB is empty
0= SPIxTXB is not empty
Standard Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxTXB to SPIxTXSR. Automatically
cleared in hardware when SPIxBUF is written, loading SPIxTXB.
Enhanced Buffer Mode:
Indicates TXELM[5:0] = 6’b000000.
Note 1: SPITUR is cleared when SPIEN = 0. When IGNTUR = 1, SPITUR provides dynamic status of the Transmit
Underrun condition, but does not stop RX/TX operation and does not need to be cleared by software.
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REGISTER 15-4: SPIxSTATL: SPIx STATUS REGISTER LOW (CONTINUED)
bit 2
Unimplemented: Read as ‘0’
bit 1
SPITBF: SPIx Transmit Buffer Full Status bit
1= SPIxTXB is full
0= SPIxTXB not full
Standard Buffer Mode:
Automatically set in hardware when SPIxBUF is written, loading SPIxTXB. Automatically cleared in
hardware when SPIx transfers data from SPIxTXB to SPIxTXSR.
Enhanced Buffer Mode:
Indicates TXELM[5:0] = 6’b111111.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1= SPIxRXB is full
0= SPIxRXB is not full
Standard Buffer Mode:
Automatically set in hardware when SPIx transfers data from SPIxRXSR to SPIxRXB. Automatically
cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer Mode:
Indicates RXELM[5:0] = 6’b111111.
Note 1: SPITUR is cleared when SPIEN = 0. When IGNTUR = 1, SPITUR provides dynamic status of the Transmit
Underrun condition, but does not stop RX/TX operation and does not need to be cleared by software.
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REGISTER 15-5: SPIxSTATH: SPIx STATUS REGISTER HIGH(4)
U-0
—
U-0
—
HSC/R-0
RXELM5(3)
HSC/R-0
RXELM4(2)
HSC/R-0
RXELM3(1)
HSC/R-0
RXELM2
HSC/R-0
RXELM1
HSC/R-0
RXELM0
bit 15
bit 8
U-0
—
U-0
—
HSC/R-0
TXELM5(3)
HSC/R-0
TXELM4(2)
HSC/R-0
TXELM3(1)
HSC/R-0
TXELM2
HSC/R-0
TXELM1
HSC/R-0
TXELM0
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
RXELM[5:0]: Receive Buffer Element Count bits (valid in Enhanced Buffer mode)(1,2,3)
Unimplemented: Read as ‘0’
bit 5-0
TXELM[5:0]: Transmit Buffer Element Count bits (valid in Enhanced Buffer mode)(1,2,3)
Note 1: RXELM3 and TXELM3 bits are only present when FIFODEPTH = 8 or higher.
2: RXELM4 and TXELM4 bits are only present when FIFODEPTH = 16 or higher.
3: RXELM5 and TXELM5 bits are only present when FIFODEPTH = 32.
4: See the MODE32/16 bits in the SPIxCON1L register.
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REGISTER 15-6: SPIxBUFL: SPIx BUFFER REGISTER LOW
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATA[15:8]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATA[7:0]
bit 7
Legend:
bit 0
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
DATA[15:0]: SPIx FIFO Data bits
When the MODE[32,16] or WLENGTH[4:0] bits select 16 to 9-bit data, the SPIx only uses DATA[15:0].
When the MODE[32,16] or WLENGTH[4:0] bits select 8 to 2-bit data, the SPIx only uses DATA[7:0].
REGISTER 15-7: SPIxBUFH: SPIx BUFFER REGISTER HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DATA[31:24]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 15
R/W-0
bit 7
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0 R/W-0
DATA[23:16]
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
DATA[31:16]: SPIx FIFO Data bits
When the MODE[32,16] or WLENGTH[4:0] bits select 32 to 25-bit data, the SPIx uses DATA[31:16].
When the MODE[32,16] or WLENGTH[4:0] bits select 24 to 17-bit data, the SPIx only uses DATA[23:16].
DS30010198B-page 192
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REGISTER 15-8: SPIxBRGL: SPIx BAUD RATE GENERATOR REGISTER LOW
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
BRG[12:8](1)
R/W-0
R/W-0
bit 8
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BRG[7:0](1)
bit 7
Legend:
bit 0
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-0
Unimplemented: Read as ‘0’
BRG[12:0]: SPIx Baud Rate Generator Divisor bits(1)
Note 1: Changing the BRG value when SPIEN = 1causes undefined behavior.
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REGISTER 15-9: SPIxIMSKL: SPIx INTERRUPT MASK REGISTER LOW
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
SPITUREN
bit 8
FRMERREN
BUSYEN
bit 15
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
U-0
—
R/W-0
R/W-0
SRMTEN
SPIROVEN
SPIRBEN
SPITBEN
SPITBFEN SPIRBFEN
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
FRMERREN: Enable Interrupt Events via FRMERR bit
1= Frame error generates an interrupt event
0= Frame error does not generate an interrupt event
bit 11
BUSYEN: Enable Interrupt Events via SPIBUSY bit
1= SPIBUSY generates an interrupt event
0= SPIBUSY does not generate an interrupt event
bit 10-9
bit 8
Unimplemented: Read as ‘0’
SPITUREN: Enable Interrupt Events via SPITUR bit
1= Transmit Underrun (TUR) generates an interrupt event
0= Transmit Underrun does not generate an interrupt event
bit 7
bit 6
bit 5
SRMTEN: Enable Interrupt Events via SRMT bit
1= Shift Register Empty (SRMT) generates interrupt events
0= Shift Register Empty does not generate interrupt events
SPIROVEN: Enable Interrupt Events via SPIROV bit
1= SPIx Receive Overflow (ROV) generates an interrupt event
0= SPIx Receive Overflow does not generate an interrupt event
SPIRBEN: Enable Interrupt Events via SPIRBE bit
1= SPIx receive buffer empty generates an interrupt event
0= SPIx receive buffer empty does not generate an interrupt event
bit 4
bit 3
Unimplemented: Read as ‘0’
SPITBEN: Enable Interrupt Events via SPITBE bit
1= SPIx transmit buffer empty generates an interrupt event
0= SPIx transmit buffer empty does not generate an interrupt event
bit 2
bit 1
Unimplemented: Read as ‘0’
SPITBFEN: Enable Interrupt Events via SPITBF bit
1= SPIx transmit buffer full generates an interrupt event
0= SPIx transmit buffer full does not generate an interrupt event
bit 0
SPIRBFEN: Enable Interrupt Events via SPIRBF bit
1= SPIx receive buffer full generates an interrupt event
0= SPIx receive buffer full does not generate an interrupt event
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REGISTER 15-10: SPIxIMSKH: SPIx INTERRUPT MASK REGISTER HIGH
R/W-0
RXWIEN
bit 15
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RXMSK5(1) RXMSK4(1,4) RXMSK3(1,3)
RXMSK2(1,2) RXMSK1(1) RXMSK0(1)
bit 8
R/W-0
TXWIEN
bit 7
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
TXMSK2(1,2)
R/W-0
R/W-0
TXMSK5(1) TXMSK4(1,4) TXMSK3(1,3)
TXMSK1(1) TXMSK0(1)
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
RXWIEN: Receive Watermark Interrupt Enable bit
1= Triggers receive buffer element watermark interrupt when RXMSK[5:0] RXELM[5:0]
0= Disables receive buffer element watermark interrupt
bit 14
Unimplemented: Read as ‘0’
bit 13-8
RXMSK[5:0]: RX Buffer Mask bits(1,2,3,4)
RX mask bits; used in conjunction with the RXWIEN bit.
TXWIEN: Transmit Watermark Interrupt Enable bit
bit 7
1= Triggers transmit buffer element watermark interrupt when TXMSK[5:0] = TXELM[5:0]
0= Disables transmit buffer element watermark interrupt
bit 6
Unimplemented: Read as ‘0’
bit 5-0
TXMSK[5:0]: TX Buffer Mask bits(1,2,3,4)
TX mask bits; used in conjunction with the TXWIEN bit.
Note 1: Mask values higher than FIFODEPTH are not valid. The module will not trigger a match for any value in
this case.
2: RXMSK2 and TXMSK2 bits are only present when FIFODEPTH = 8 or higher.
3: RXMSK3 and TXMSK3 bits are only present when FIFODEPTH = 16 or higher.
4: RXMSK4 and TXMSK4 bits are only present when FIFODEPTH = 32.
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REGISTER 15-11: SPIxURDTL: SPIx UNDERRUN DATA REGISTER LOW
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
URDATA[15:8]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
URDATA[7:0]
bit 7
Legend:
bit 0
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
URDATA[15:0]: SPIx Underrun Data bits
These bits are only used when URDTEN = 1. This register holds the data to transmit when a Transmit
Underrun condition occurs.
When the MODE[32,16] or WLENGTH[4:0] bits select 16 to 9-bit data, the SPIx only uses URDATA[15:0].
When the MODE[32,16] or WLENGTH[4:0] bits select 8 to 2-bit data, the SPIx only uses URDATA[7:0].
REGISTER 15-12: SPIxURDTH: SPIx UNDERRUN DATA REGISTER HIGH
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
URDATA[31:24]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
URDATA[23:16]
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
URDATA[31:16]: SPIx Underrun Data bits
These bits are only used when URDTEN = 1. This register holds the data to transmit when a Transmit
Underrun condition occurs.
When the MODE[32,16] or WLENGTH[4:0] bits select 32 to 25-bit data, the SPIx only uses
URDATA[31:16]. When the MODE[32,16] or WLENGTH[4:0] bits select 24 to 17-bit data, the SPIx only
uses URDATA[23:16].
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FIGURE 15-2:
SPIx MASTER/SLAVE CONNECTION (STANDARD MODE)
Processor 1 (SPIx Master)
Processor 2 (SPIx Slave)
SDOx
SDIx
Serial Receive Buffer
Serial Transmit Buffer
(2)
(2)
(SPIxRXB)
(SPIxTXB)
SDIx
SDOx
SDIx
Shift Register
(SPIxRXSR)
Shift Register
(SPIxTXSR)
LSb
LSb
MSb
MSb
MSb
MSb
LSb
LSb
SDOx
Shift Register
(SPIxRXSR)
Shift Register
(SPIxTXSR)
Serial Clock
Serial Transmit Buffer
SCKx
SCKx
Serial Receive Buffer
(2)
(2)
(SPIxTXB)
(SPIxRXB)
(1)
SSx
SPIx Buffer
(SPIxBUF)
SPIx Buffer
(SPIxBUF)
MSTEN (SPIxCON1L[5]) = 1
MSSEN (SPIxCON1H[4]) =
1and MSTEN (SPIxCON1L[5]) = 0
Note 1: Using the SSx pin in Slave mode of operation is optional.
2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers
are memory-mapped to SPIxBUF.
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FIGURE 15-3:
SPIx MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)
Processor 1 (SPIx Master)
Processor 2 (SPIx Slave)
SDOx
SDIx
Serial Transmit FIFO
Serial Receive FIFO
(2)
(2)
(SPIxRXB)
(SPIxTXB)
SDIx
SDOx
SDIx
Shift Register
(SPIxRXSR)
Shift Register
(SPIxTXSR)
LSb
LSb
MSb
MSb
MSb
MSb
LSb
LSb
SDOx
Shift Register
(SPIxRXSR)
Shift Register
(SPIxTXSR)
Serial Clock
SCKx
Serial Transmit FIFO
SCKx
Serial Receive FIFO
(2)
(2)
(SPIxTXB)
(SPIxRXB)
(1)
SSx
SPIx Buffer
(SPIxBUF)
SPIx Buffer
(SPIxBUF)
MSTEN (SPIxCON1L[5]) = 1
MSSEN (SPIxCON1H[4]) =
1and MSTEN (SPIxCON1L[5]) = 0
Note 1: Using the SSx pin in Slave mode of operation is optional.
2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers
are memory-mapped to SPIxBUF.
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FIGURE 15-4:
SPIx MASTER, FRAME MASTER CONNECTION DIAGRAM
Processor 2
(SPIx Slave, Frame Slave)
PIC24FJ128GL306
(SPIx Master, Frame Master)
Serial Receive Buffer
Serial Receive Buffer
(3)
(3)
(SPIxTXB)
(SPIxRXB)
SDIx
SDOx
SDIx
Shift Register
(SPIxRXSR)
Shift Register
(SPIxRXSR)
MSb
MSb
LSb
LSb
MSb
MSb
LSb
LSb
SDOx
Shift Register
(SPIxTXSR)
Shift Register
(SPIxTXSR)
Serial Clock
Frame Sync
Serial Transmit Buffer
Serial Transmit Buffer
SCKx
SSx
SCKx
(3)
(3)
(SPIxTXB)
(SPIxTXB)
(1,2)
Pulse
(1)
SSx
SPI Buffer
(SPIxBUF)
SPI Buffer
(SPIxBUF)
Note 1: In Framed SPI modes, the SSx pin is used to transmit/receive the Frame Synchronization pulse.
2: Framed SPI modes require the use of all four pins (i.e., using the SSx pin is not optional).
3: The SPIxTXB and SPIxRXB registers are memory-mapped to the SPIxBUF register.
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FIGURE 15-5:
FIGURE 15-6:
FIGURE 15-7:
SPIx MASTER, FRAME SLAVE CONNECTION DIAGRAM
PIC24F
Processor 2
SPIx Master, Frame Slave)
SDOx
SDIx
SDOx
SCKx
SSx
SDIx
SCKx
SSx
Serial Clock
Frame Sync
Pulse
SPIx SLAVE, FRAME MASTER CONNECTION DIAGRAM
PIC24F
(SPIx Slave, Frame Master)
Processor 2
SDOx
SDIx
SDIx
SDOx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync.
Pulse
SPIx SLAVE, FRAME SLAVE CONNECTION DIAGRAM
PIC24F
(SPIx Slave, Frame Slave)
Processor 2
SDOx
SDIx
SDIx
SDOx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync
Pulse
EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPIx CLOCK SPEED
FPB
Baud Rate =
(2 * (SPIxBRG + 1))
Where:
FPB is the Peripheral Bus Clock Frequency.
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16.1 Communicating as a Master in a
Single Master Environment
16.0 INTER-INTEGRATED CIRCUIT
2
(I C)
The details of sending a message in Master mode
depends on the communications protocol for the device
being communicated with. Typically, the sequence of
events is as follows:
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive ref-
erence source. For more information, refer
to “Inter-Integrated Circuit (I2C)”
(www.microchip.com/DS70000195) in the
“dsPIC33/PIC24 Family Reference Man-
ual”. The information in this data sheet
supersedes the information in the FRM.
1. Assert a Start condition on SDAx and SCLx.
2. Send the I2C device address byte to the Slave
with a write indication.
3. Wait for and verify an Acknowledge from the
Slave.
The Inter-Integrated Circuit (I2C) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be serial EEPROMs, display drivers, A/D
Converters, etc.
4. Send the first data byte (sometimes known as
the command) to the Slave.
5. Wait for and verify an Acknowledge from the
Slave.
6. Send the serial memory address low byte to the
Slave.
The I2C module supports these features:
7. Repeat Steps 4 and 5 until all data bytes are
sent.
• Independent Master and Slave Logic
• 7-Bit and 10-Bit Device Addresses
8. Assert a Repeated Start condition on SDAx and
SCLx.
• General Call Address as Defined in the
I2C Protocol
9. Send the device address byte to the Slave with
a read indication.
• Clock Stretching to Provide Delays for the
Processor to Respond to a Slave Data Request
10. Wait for and verify an Acknowledge from the
Slave.
• Both 100 kHz, 400 kHz and 1 MHz Bus
Specifications
11. Enable Master reception to receive serial
memory data.
• Configurable Address Masking
• Multi-Master modes to Prevent Loss of Messages
in Arbitration
12. Generate an ACK or NACK condition at the end
of a received byte of data.
• Bus Repeater mode, Allowing the Acceptance of All
Messages as a Slave, regardless of the Address
13. Generate a Stop condition on SDAx and SCLx.
• Automatic SCL
• PMBus™ Support
A block diagram of the module is shown in Figure 16-1.
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FIGURE 16-1:
I2Cx BLOCK DIAGRAM
Internal
Data Bus
I2CxRCV
Read
Shift
Clock
SCLx
SDAx
I2CxRSR
LSb
Address Match
Write
Read
Match Detect
I2CxMSK
Write
Read
I2CxADD
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
I2CxSTAT
I2CxCON
Read
Write
Collision
Detect
Acknowledge
Generation
Read
Clock
Stretching
Write
Read
I2CxTRN
LSb
Shift Clock
Reload
Control
Write
Read
BRG Down Counter
TCY/2
I2CxBRG
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16.2 Setting Baud Rate When Operating
as a Bus Master
16.3 Slave Address Masking
The I2CxMSK register (Register 16-4) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit
location (= 1) in the I2CxMSK register causes the Slave
module to respond, whether the corresponding address
bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK is
set to ‘0010000000’, the Slave module will detect both
addresses, ‘0000000000’ and ‘0010000000’.
To compute the Baud Rate Generator reload value, use
Equation 16-1.
EQUATION 16-1: COMPUTING BAUD RATE
RELOAD VALUE(1,2,3)
FCY
FSCL =
(I2CxBRG + 2) * 2
To enable address masking, the Intelligent Peripheral
Management Interface (IPMI) must be disabled by
clearing the STRICT bit (I2CxCONL[11]).
or:
FCY
(FSCL * 2)
I2CxBRG =
– 2
[
]
Note:
As a result of changes in the I2C protocol,
the addresses in Table 16-2 are reserved
and will not be Acknowledged in Slave
mode. This includes any address mask
settings that include any of these
addresses.
Note 1: Based on FCY = FOSC/2; Doze mode and
PLL are disabled.
2: These clock rate values are for guidance
only. The actual clock rate can be
affected by various system-level para-
meters. The actual clock rate should be
measured in its intended application.
3: I2CxBRG values of 0 to 3 are forbidden.
TABLE 16-1: I2Cx CLOCK RATES(1,2)
I2CxBRG Value
Required System FSCL
FCY
Actual FSCL
(Decimal)
(Hexadecimal)
4E
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
1 MHz
16 MHz
8 MHz
4 MHz
16 MHz
8 MHz
4 MHz
16 MHz
78
38
18
18
8
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
1 MHz
26
12
12
8
3
3
6
6
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
2: These clock rate values are for guidance only. The actual clock rate can be affected by various
system-level parameters. The actual clock rate should be measured in its intended application.
TABLE 16-2: I2Cx RESERVED ADDRESSES(1)
Slave Address R/W Bit
Description
0000 000
0000 000
0000 001
0000 01x
0000 1xx
1111 0xx
1111 1xx
0
1
x
x
x
x
x
General Call Address(2)
Start Byte
C-Bus Address
Reserved
HS Mode Master Code
10-Bit Slave Upper Byte(3)
Reserved
Note 1: The address bits listed here will never cause an address match independent of address mask settings.
2: This address will be Acknowledged only if GCEN = 1.
3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.
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REGISTER 16-1: I2CxCONL: I2Cx CONTROL REGISTER LOW
R/W-0
I2CEN
U-0
—
HC/R/W-0
I2CSIDL
R/W-1
SCLREL(1)
R/W-0
R/W-0
A10M
R/W-0
R/W-0
SMEN
STRICT
DISSLW
bit 15
bit 8
R/W-0
GCEN
R/W-0
R/W-0
HC/R/W-0
ACKEN
HC/R/W-0
RCEN
HC/R/W-0
PEN
HC/R/W-0
RSEN
HC/R/W-0
SEN
STREN
ACKDT
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
W = Writable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
bit 15
I2CEN: I2Cx Enable bit (writable from software only)
1= Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0= Disables the I2Cx module; all I2C pins are controlled by port functions
bit 14
bit 13
Unimplemented: Read as ‘0’
I2CSIDL: I2Cx Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (I2C Slave mode only)(1)
Module resets and (I2CEN = 0) sets SCLREL = 1.
If STREN = 0:(2)
1= Releases clock
0= Forces clock low (clock stretch)
If STREN = 1:
1= Releases clock
0= Holds clock low (clock stretch); user may program this bit to ‘0’, clock stretch at next SCLx low
bit 11
STRICT: I2Cx Strict Reserved Address Rule Enable bit
1= Strict reserved addressing is enforced (for reserved addresses, refer to Table 16-2)
In Slave Mode: The device does not respond to reserved address space and addresses falling in
that category are NACKed.
In Master Mode: The device is allowed to generate addresses with reserved address space.
0= Reserved addressing would be Acknowledged
In Slave Mode: The device will respond to an address falling in the reserved address space. When
there is a match with any of the reserved addresses, the device will generate an ACK.
In Master Mode: Reserved.
bit 10
bit 9
A10M: 10-Bit Slave Address Flag bit
1= I2CxADD is a 10-bit Slave address
0= I2CxADD is a 7-bit Slave address
DISSLW: Slew Rate Control Disable bit
1= Slew rate control is disabled for Standard Speed mode (100 kHz, also disabled for 1 MHz mode)
0= Slew rate control is enabled for High-Speed mode (400 kHz)
Note 1: Automatically cleared to ‘0’ at the beginning of Slave transmission; automatically cleared to ‘0’ at the end
of Slave reception. The user software must provide a delay between writing to the transmit buffer and set-
ting the SCLREL bit. This delay must be greater than the minimum setup time for Slave transmissions, as
specified in Section 30.0 “Electrical Characteristics”.
2: Automatically cleared to ‘0’ at the beginning of Slave transmission.
3: SMBus 3.0 specification input level can be selected by the SMB3EN Configuration bit (FDEVOPT1[10]).
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REGISTER 16-1: I2CxCONL: I2Cx CONTROL REGISTER LOW (CONTINUED)
bit 8
bit 7
bit 6
SMEN: SMBus Input Levels Enable bit(3)
1= Enables input logic so thresholds are compliant with the SMBus specification
0= Disables SMBus-specific inputs
GCEN: General Call Enable bit (I2C Slave mode only)
1= Enables interrupt when a general call address is received in I2CxRSR; module is enabled for reception
0= General call address is disabled
STREN: SCLx Clock Stretch Enable bit
In I2C Slave mode only; used in conjunction with the SCLREL bit.
1= Enables clock stretching
0= Disables clock stretching
bit 5
ACKDT: Acknowledge Data bit
In I2C Master mode during Master Receive mode. The value that will be transmitted when the user
initiates an Acknowledge sequence at the end of a receive.
In I2C Slave mode when AHEN = 1or DHEN = 1. The value that the Slave will transmit when it initiates
an Acknowledge sequence at the end of an address or data reception.
1= NACK is sent
0= ACK is sent
bit 4
bit 3
ACKEN: Acknowledge Sequence Enable bit
In I2C Master mode only; applicable during Master Receive mode.
1= Initiates Acknowledge sequence on SDAx and SCLx pins, and transmits the ACKDT data bit
0= Acknowledge sequence is Idle
RCEN: Receive Enable bit (I2C Master mode only)
1= Enables Receive mode for I2C; automatically cleared by hardware at the end of the 8-bit receive
data byte
0= Receive sequence is not in progress
bit 2
bit 1
bit 0
PEN: Stop Condition Enable bit (I2C Master mode only)
1= Initiates Stop condition on the SDAx and SCLx pins
0= Stop condition is Idle
RSEN: Restart Condition Enable bit (I2C Master mode only)
1= Initiates Restart condition on the SDAx and SCLx pins
0= Restart condition is Idle
SEN: Start Condition Enable bit (I2C Master mode only)
1= Initiates Start condition on the SDAx and SCLx pins
0= Start condition is Idle
Note 1: Automatically cleared to ‘0’ at the beginning of Slave transmission; automatically cleared to ‘0’ at the end
of Slave reception. The user software must provide a delay between writing to the transmit buffer and set-
ting the SCLREL bit. This delay must be greater than the minimum setup time for Slave transmissions, as
specified in Section 30.0 “Electrical Characteristics”.
2: Automatically cleared to ‘0’ at the beginning of Slave transmission.
3: SMBus 3.0 specification input level can be selected by the SMB3EN Configuration bit (FDEVOPT1[10]).
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REGISTER 16-2: I2CxCONH: I2Cx CONTROL REGISTER HIGH
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
R/W-0
PCIE
R/W-0
SCIE
R/W-0
BOEN
R/W-0
SDAHT(1)
R/W-0
R/W-0
AHEN
R/W-0
DHEN
SBCDE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6
Unimplemented: Read as ‘0’
PCIE: Stop Condition Interrupt Enable bit (I2C Slave mode only)
1= Enables interrupt on detection of Stop condition
0= Stop detection interrupts are disabled
bit 5
bit 4
SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only)
1= Enables interrupt on detection of Start or Restart conditions
0= Start detection interrupts are disabled
BOEN: Buffer Overwrite Enable bit (I2C Slave mode only)
1= I2CxRCV is updated and an ACK is generated for a received address/data byte, ignoring the state
of the I2COV bit only if the RBF bit = 0
0= I2CxRCV is only updated when I2COV is clear
bit 3
bit 2
SDAHT: SDAx Hold Time Selection bit(1)
1= Minimum of 300 ns hold time on SDAx after the falling edge of SCLx
0= Minimum of 100 ns hold time on SDAx after the falling edge of SCLx
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If, on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the
BCL bit is set and the bus goes Idle. This Detection mode is only valid during data and ACK transmit
sequences.
1= Enables Slave bus collision interrupts
0= Slave bus collision interrupts are disabled
bit 1
bit 0
AHEN: Address Hold Enable bit (I2C Slave mode only)
1= Following the 8th falling edge of SCLx for a matching received address byte; the SCLREL bit
(I2CxCONL[12]) will be cleared and SCLx will be held low
0= Address holding is disabled
DHEN: Data Hold Enable bit (I2C Slave mode only)
1= Following the 8th falling edge of SCLx for a received data byte; Slave hardware clears the SCLREL
bit (I2CxCONL[12]) and SCLx is held low
0= Data holding is disabled
Note 1: This bit must be set to ‘0’ for 1 MHz operation.
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REGISTER 16-3: I2CxSTAT: I2Cx STATUS REGISTER
HSC/R-0
HSC/R-0
TRSTAT
HSC/R-0
ACKTIM
U-0
—
U-0
—
HSC/R/C-0
BCL
HSC/R-0
GCSTAT
HSC/R-0
ADD10
ACKSTAT
bit 15
bit 8
HS/R/C-0
IWCOL
HS/R/C-0
I2COV
HSC/R-0
D/A
HSC/R-0
P
HSC/R-0
S
HSC/R-0
R/W
HSC/R-0
RBF
HSC/R-0
TBF
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
‘0’ = Bit is cleared
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
HSC = Hardware Settable/Clearable bit
bit 15
bit 14
bit 13
ACKSTAT: Acknowledge Status bit (updated in all Master and Slave modes)
1= Acknowledge was not received from Slave
0= Acknowledge was received from Slave
TRSTAT: Transmit Status bit (when operating as I2C Master; applicable to Master transmit operation)
1= Master transmit is in progress (8 bits + ACK)
0= Master transmit is not in progress
ACKTIM: Acknowledge Time Status bit (valid in I2C Slave mode only)
1= Indicates I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCLx clock
0= Not an Acknowledge sequence, cleared on 9th rising edge of SCLx clock
bit 12-11
bit 10
Unimplemented: Read as ‘0’
BCL: Bus Collision Detect bit (Master/Slave mode; cleared when I2C module is disabled, I2CEN = 0)
1= A bus collision has been detected during a Master or Slave transmit operation
0= No bus collision has been detected
bit 9
bit 8
bit 7
GCSTAT: General Call Status bit (cleared after Stop detection)
1= General call address was received
0= General call address was not received
ADD10: 10-Bit Address Status bit (cleared after Stop detection)
1= 10-bit address was matched
0= 10-bit address was not matched
IWCOL: I2Cx Write Collision Detect bit
1= An attempt to write to the I2CxTRN register failed because the I2C module is busy; must be cleared
in software
0= No collision
bit 6
I2COV: I2Cx Receive Overflow Flag bit
1= A byte was received while the I2CxRCV register is still holding the previous byte; I2COV is a “don’t
care” in Transmit mode, must be cleared in software
0= No overflow
bit 5
bit 4
D/A: Data/Address bit (when operating as I2C Slave)
1= Indicates that the last byte received was data
0= Indicates that the last byte received or transmitted was an address
P: I2Cx Stop bit
Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
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REGISTER 16-3: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 3
S: I2Cx Start bit
Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0.
1= Indicates that a Start (or Repeated Start) bit has been detected last
0= Start (or Repeated Start) bit was not detected last
bit 2
bit 1
bit 0
R/W: Read/Write Information bit (when operating as I2C Slave)
1= Read: Indicates the data transfer is output from the Slave
0= Write: Indicates the data transfer is input to the Slave
RBF: Receive Buffer Full Status bit
1= Receive is complete, I2CxRCV is full
0= Receive is not complete, I2CxRCV is empty
TBF: Transmit Buffer Full Status bit
1= Transmit is in progress, I2CxTRN is full (8 bits of data)
0= Transmit is complete, I2CxTRN is empty
REGISTER 16-4: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
bit 8
MSK[9:8]
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
MSK[7:0]
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
MSK[9:0]: I2Cx Mask for Address Bit x Select bits
1= Enables masking for bit x of the incoming message address; bit match is not required in this position
0= Disables masking for bit x; bit match is required in this position
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A simplified block diagram of the UARTx module is
shown in Figure 17-1. The UARTx module consists of
these key important hardware elements:
17.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to “Universal Asynchronous
Note:
Throughout this section, references to
register and bit names that may be asso-
ciated with a specific UART module are
referred to generically by the use of ‘x’ in
place of the specific module number.
Thus, “UxSTA” might refer to the Status
register for either UART1, UART2, UART3
or UART4.
Receiver
Transmitter
(UART)”
(www.microchip.com/DS70000582) in the
“dsPIC33/PIC24 Family Reference Man-
ual”. The information in this data sheet
supersedes the information in the FRM.
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules available
in the PIC24F device family. The UART is a full-duplex,
asynchronous system that can communicate with
peripheral devices, such as personal computers,
LIN/J2602, RS-232 and RS-485 interfaces. The module
also supports a hardware flow control option with the
UxCTS and UxRTS pins. The UART module includes
an IrDA® encoder/decoder unit.
The PIC24FJ128GL306 family devices are equipped
with four UART modules, referred to as UART1,
UART2, UART3 and UART4.
The primary features of the UARTx modules are:
• Full-Duplex, 8 or 9-Bit Data Transmission through
the UxTX and UxRX Pins
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Control Option with the UxCTS
and UxRTS Pins
• Fully Integrated Baud Rate Generator with
16-Bit Prescaler
• Baud Rates Range from Up to 1 Mbps and Down to
15 Hz at 16 MIPS in 16x mode
• Baud Rates Range from Up to 4 Mbps and Down to
61 Hz at 16 MIPS in 4x mode
• 4-Deep, First-In-First-Out (FIFO) Transmit Data
Buffer
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-Bit mode with Address Detect
(9th bit = 1)
• Separate Transmit and Receive Interrupts
• Loopback mode for Diagnostic Support
• Polarity Control for Transmit and Receive Lines
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA® Encoder and Decoder Logic
• Includes DMA Support
• 16x Baud Clock Output for IrDA Support
2019-2020 Microchip Technology Inc.
DS30010198B-page 209
PIC24FJ128GL306 FAMILY
FIGURE 17-1:
UARTx SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
®
IrDA
(1)
Hardware Flow Control
UARTx Receiver
UxRTS/BCLKx
(1)
UxCTS
(1)
UxRX
(1)
UARTx Transmitter
UxTX
Note 1: The UART1, UART2, UART3 and UART4 inputs and outputs must all be assigned to available RPn/RPIn pins
before use. See Section 11.5 “Peripheral Pin Select (PPS)” for more information.
DS30010198B-page 210
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Equation 17-2 shows the formula for computation of
the baud rate when BRGH = 1.
17.1 UARTx Baud Rate Generator (BRG)
The UARTx module includes a dedicated, 16-bit Baud
Rate Generator. The UxBRG register controls the
period of a free-running, 16-bit timer. Equation 17-1
shows the formula for computation of the baud rate
when BRGH = 0.
EQUATION 17-2: UARTx BAUD RATE WITH
BRGH = 1(1,2)
FCY
Baud Rate =
4 • (UxBRG + 1)
EQUATION 17-1: UARTx BAUD RATE WITH
FCY
4 • Baud Rate
BRGH = 0(1,2)
UxBRG =
– 1
FCY
Baud Rate =
16 • (UxBRG + 1)
Note 1: FCY denotes the instruction cycle
clock frequency.
FCY
UxBRG =
– 1
16 • Baud Rate
2: Based on FCY = FOSC/2; Doze mode
and PLL are disabled.
Note 1: FCY denotes the instruction cycle
clock frequency (FOSC/2).
The maximum baud rate (BRGH = 1) possible is FCY/4
(for UxBRG = 0) and the minimum baud rate possible
is FCY/(4 * 65536).
2: Based on FCY = FOSC/2; Doze mode
and PLL are disabled.
Writing a new value to the UxBRG register causes the
BRG timer to be reset (cleared). This ensures the BRG
does not wait for a timer overflow before generating the
new baud rate.
Example 17-1 shows the calculation of the baud rate
error for the following conditions:
• FCY = 4 MHz
• Desired Baud Rate = 9600
The maximum baud rate (BRGH = 0) possible is
FCY/16 (for UxBRG = 0) and the minimum baud rate
possible is FCY/(16 * 65536).
EXAMPLE 17-1:
BAUD RATE ERROR CALCULATION (BRGH = 0)(1)
Desired Baud Rate = FCY/(16 (UxBRG + 1))
Solving for UxBRG Value:
UxBRG
UxBRG
UxBRG
= ((FCY/Desired Baud Rate)/16) – 1
= ((4000000/9600)/16) – 1
= 25
Calculated Baud Rate = 4000000/(16 (25 + 1))
= 9615
Error
= (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600
= 0.16%
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
2019-2020 Microchip Technology Inc.
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17.2 Transmitting in 8-Bit Data Mode
17.5 Receiving in 8-Bit or 9-Bit Data
Mode
1. Set up the UARTx:
a) Write appropriate values for data, parity and
Stop bits.
1. Set up the UARTx (as described in Section 17.2
“Transmitting in 8-Bit Data Mode”).
b) Write appropriate baud rate value to the
UxBRG register.
2. Enable the UARTx by setting the URXEN bit
(UxSTA[12]).
c) Set up transmit and receive interrupt enable
and priority bits.
3. A receive interrupt will be generated when one
or more data characters have been received as
per interrupt control bits, URXISEL[1:0].
2. Enable the UARTx.
4. Read the OERR bit to determine if an overrun
error has occurred. The OERR bit must be reset
in software.
3. Set the UTXEN bit (causes a transmit interrupt,
two cycles after being set).
4. Write a data byte to the lower byte of the
UxTXREG word. The value will be immediately
transferred to the Transmit Shift Register (TSR)
and the serial bit stream will start shifting out
with the next rising edge of the baud clock.
5. Read UxRXREG.
The act of reading the UxRXREG character will move
the next character to the top of the receive FIFO,
including a new set of PERR and FERR values.
5. Alternatively, the data byte may be transferred
while UTXEN = 0 and then the user may set
UTXEN. This will cause the serial bit stream to
begin immediately because the baud clock will
start from a cleared state.
17.6 Operation of UxCTS and UxRTS
Control Pins
UARTx Clear-to-Send (UxCTS) and Request-to-Send
(UxRTS) are the two hardware controlled pins that are
associated with the UARTx modules. These two pins
allow the UARTx to operate in Simplex and Flow
Control mode. They are implemented to control the
transmission and reception between the Data Terminal
Equipment (DTE). The UEN[1:0] bits in the UxMODE
register configure these pins.
6. A transmit interrupt will be generated as per
interrupt control bits, UTXISEL[1:0].
17.3 Transmitting in 9-Bit Data Mode
1. Set up the UARTx (as described in Section 17.2
“Transmitting in 8-Bit Data Mode”).
2. Enable the UARTx.
17.7 Infrared Support
3. Set the UTXEN bit (causes a transmit interrupt).
4. Write UxTXREG as a 16-bit value only.
The UARTx module provides two types of infrared
UART support: one is the IrDA clock output to support
an external IrDA encoder and decoder device (legacy
module support), and the other is the full implementa-
tion of the IrDA encoder and decoder. Note that
because the IrDAmodes require a 16x baud clock, they
will only work when the BRGH bit (UxMODE[3]) is ‘0’.
5. A word write to UxTXREG triggers the transfer
of the 9-bit data to the TSR. The serial bit stream
will start shifting out with the first rising edge of
the baud clock.
6. A transmit interrupt will be generated as per the
setting of control bits, UTXISELx.
17.7.1
IrDA CLOCK OUTPUT FOR
EXTERNAL IrDA SUPPORT
17.4 Break and Sync Transmit
Sequence
To support external IrDAencoder and decoder devices,
the BCLKx pin (same as the UxRTS pin) can be
configured to generate the 16x baud clock. When
UEN[1:0] = 11, the BCLKx pin will output the 16x baud
clock if the UARTx module is enabled; it can be used to
support the IrDA codec chip.
The following sequence will send a message frame
header, made up of a Break, followed by an auto-baud
Sync byte.
1. Configure the UARTx for the desired mode.
2. Set UTXEN and UTXBRK to set up the Break
character.
17.7.2
BUILT-IN IrDA ENCODER AND
DECODER
3. Load the UxTXREG with a dummy character to
initiate transmission (value is ignored).
The UARTx has full implementation of the IrDA
encoder and decoder as part of the UARTx module.
The built-in IrDA encoder and decoder functionality is
enabled using the IREN bit (UxMODE[12]). When
enabled (IREN = 1), the receive pin (UxRX) acts as the
input from the infrared receiver. The transmit pin
(UxTX) acts as the output to the infrared transmitter.
4. Write ‘55h’ to UxTXREG; this loads the Sync
character into the transmit FIFO.
5. After the Break has been sent, the UTXBRK bit
is reset by hardware. The Sync character now
transmits.
DS30010198B-page 212
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REGISTER 17-1: UxMODE: UARTx MODE REGISTER
R/W-0
UARTEN(1)
bit 15
U-0
—
R/W-0
USIDL
R/W-0
IREN(2)
R/W-0
U-0
—
R/W-0
UEN1
R/W-0
UEN0
RTSMD
bit 8
HC/R/W-0
WAKE
R/W-0
HC/R/W-0
ABAUD
R/W-0
R/W-0
BRGH
R/W-0
R/W-0
R/W-0
LPBACK
URXINV
PDSEL1
PDSEL0
STSEL
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
UARTEN: UARTx Enable bit(1)
1= UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN[1:0]
0= UARTx is disabled; all UARTx pins are controlled by port latches, UARTx power consumption is minimal
bit 14
bit 13
Unimplemented: Read as ‘0’
USIDL: UARTx Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12
bit 11
IREN: IrDA® Encoder and Decoder Enable bit(2)
1= IrDA encoder and decoder are enabled
0= IrDA encoder and decoder are disabled
RTSMD: Mode Selection for UxRTS Pin bit
1= UxRTS pin is in Simplex mode
0= UxRTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
UEN[1:0]: UARTx Enable bits
bit 9-8
11= UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by port latches
10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches
00= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by
port latches
bit 7
WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit
1= UARTx continues to sample the UxRX pin; interrupt is generated on the falling edge, bit is cleared
in hardware on the following rising edge
0= No wake-up is enabled
bit 6
bit 5
LPBACK: UARTx Loopback Mode Select bit
1= Enables Loopback mode
0= Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1= Enables baud rate measurement on the next character – requires reception of a Sync field (55h);
cleared in hardware upon completion
0= Baud rate measurement is disabled or completed
bit 4
URXINV: UARTx Receive Polarity Inversion bit
1= UxRX Idle state is ‘0’
0= UxRX Idle state is ‘1’
Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For
more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
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REGISTER 17-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 3
BRGH: High Baud Rate Enable bit
1= High-Speed mode (4 BRG clock cycles per bit)
0= Standard Speed mode (16 BRG clock cycles per bit)
bit 2-1
PDSEL[1:0]: Parity and Data Selection bits
11= 9-bit data, no parity
10= 8-bit data, odd parity
01= 8-bit data, even parity
00= 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit
1= Two Stop bits
0= One Stop bit
Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For
more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
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REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
UTXISEL1
bit 15
R/W-0
UTXINV(1)
R/W-0
U-0
—
HC/R/W-0
UTXBRK
R/W-0
UTXEN(2)
HSC/R-0
UTXBF
HSC/R-1
TRMT
UTXISEL0
bit 8
R/W-0
URXISEL1
bit 7
R/W-0
R/W-0
HSC/R-1
RIDLE
HSC/R-0
PERR
HSC/R-0
FERR
HS/R/C-0
OERR
HSC/R-0
URXDA
URXISEL0
ADDEN
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
‘0’ = Bit is cleared
x = Bit is unknown
HS = Hardware Settable bit HC = Hardware Clearable bit
bit 15,13
UTXISEL[1:0]: UARTx Transmission Interrupt Mode Selection bits
11= Reserved; do not use
10= Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the
transmit buffer becomes empty
01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least
one character open in the transmit buffer)
bit 14
UTXINV: UARTx IrDA® Encoder Transmit Polarity Inversion bit(1)
IREN = 0:
1= UxTX Idle state is ‘0’
0= UxTX Idle state is ‘1’
IREN = 1:
1= UxTX Idle state is ‘1’
0= UxTX Idle state is ‘0’
bit 12
bit 11
Unimplemented: Read as ‘0’
UTXBRK: UARTx Transmit Break bit
1= Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0= Sync Break transmission is disabled or completed
bit 10
UTXEN: UARTx Transmit Enable bit(2)
1= Transmit is enabled, UxTX pin is controlled by UARTx
0= Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is
controlled by the port
bit 9
bit 8
UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1= Transmit buffer is full
0= Transmit buffer is not full, at least one more character can be written
TRMT: Transmit Shift Register Empty bit (read-only)
1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0= Transmit Shift Register is not empty, a transmission is in progress or queued
Note 1: The value of this bit only affects the transmit properties of the module when the IrDA® encoder is enabled
(IREN = 1).
2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For
more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
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DS30010198B-page 215
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REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 7-6
URXISEL[1:0]: UARTx Receive Interrupt Mode Selection bits
11= Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has four data characters)
10= Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has three data characters)
0x= Interrupt is set when any character is received and transferred from the RSR to the receive buffer;
receive buffer has one or more characters
bit 5
bit 4
bit 3
bit 2
bit 1
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1= Address Detect mode is enabled (if 9-bit mode is not selected, this does not take effect)
0= Address Detect mode is disabled
RIDLE: Receiver Idle bit (read-only)
1= Receiver is Idle
0= Receiver is active
PERR: Parity Error Status bit (read-only)
1= Parity error has been detected for the current character (the character at the top of the receive FIFO)
0= Parity error has not been detected
FERR: Framing Error Status bit (read-only)
1= Framing error has been detected for the current character (the character at the top of the receive FIFO)
0= Framing error has not been detected
OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1= Receive buffer has overflowed
0= Receive buffer has not overflowed (clearing a previously set OERR bit (‘1’ to ‘0’ transition) will reset
the receive buffer and the RSR to the empty state)
bit 0
URXDA: UARTx Receive Buffer Data Available bit (read-only)
1= Receive buffer has data, at least one more character can be read
0= Receive buffer is empty
Note 1: The value of this bit only affects the transmit properties of the module when the IrDA® encoder is enabled
(IREN = 1).
2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For
more information, see Section 11.5 “Peripheral Pin Select (PPS)”.
DS30010198B-page 216
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REGISTER 17-3: UxRXREG: UARTx RECEIVE REGISTER (NORMALLY READ-ONLY)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0
UxRXREG8
bit 15
bit 8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
UxRXREG[7:0]
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-9
bit 8-0
Unimplemented: Read as ‘0’
UxRXREG[8:0]: Data of the Received Character bits
REGISTER 17-4: UxTXREG: UARTx TRANSMIT REGISTER (NORMALLY WRITE-ONLY)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
W-x
UxTXREG8
bit 8
bit 15
W-x
W-x
W-x
W-x
W-x
W-x
W-x
W-x
bit 0
UxTXREG[7:0]
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-9
bit 8-0
Unimplemented: Read as ‘0’
UxTXREG[8:0]: Data of the Transmitted Character bits
2019-2020 Microchip Technology Inc.
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REGISTER 17-5: UxBRG: UARTx BAUD RATE GENERATOR REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BRG[15:8]
bit 15
R/W-0
bit 7
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
BRG[7:0]
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
BRG[15:0]: Baud Rate Divisor bits
REGISTER 17-6: UxADMD: UARTx ADDRESS DETECT AND MATCH REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADMMASK7 ADMMASK6 ADMMASK5 ADMMASK4 ADMMASK3 ADMMASK2 ADMMASK1 ADMMASK0
bit 15 bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADMADDR7 ADMADDR6 ADMADDR5 ADMADDR4 ADMADDR3 ADMADDR2 ADMADDR1 ADMADDR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
ADMMASK[7:0]: ADMADDR[7:0] (UxADMD[7:0]) Masking bits
For ADMMASKx:
1= ADMADDRx is used to detect the address match
0= ADMADDRx is not used to detect the address match
bit 7-0
ADMADDR[7:0]: Address Detect Task Off-Load bits
Used with the ADMMASK[7:0] bits (UxADMD[15:8]) to offload the task of detecting the address
character from the processor during Address Detect mode.
DS30010198B-page 218
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• Up to Eight Commons:
- Static (one common)
- 1/2 multiplex (two commons)
18.0 LIQUID CRYSTAL DISPLAY
(LCD) CONTROLLER
Note:
This data sheet summarizes the features
of the PIC24FJ128GL306 family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
“Liquid Crystal Display (LCD)”
(www.microchip.com/DS30009740) in
the “dsPIC33/PIC24 Family Reference
Manual”.
- 1/3 multiplex (three commons)
- 1/4 multiplex (four commons)
- 1/5 multiplex (five commons)
- 1/6 multiplex (six commons)
- 1/7 multiplex (seven commons)
- 1/8 multiplex (eight commons)
• Ability to Drive Up to 9 (in 28-pin devices) or Up to
36 (in 64-pin devices) Segments, Depending on
the Multiplexing Mode Selected; Table 18-1
shows the segment availability
The Liquid Crystal Display (LCD) controller generates
the data and timing control required to directly drive a
static or multiplexed LCD panel. The module can drive
up to eight commons signals on all devices, and from
9 to 36 segments, depending on the specific device.
• Static, 1/2 or 1/3 LCD Bias
• On-Chip Bias Generator with Dedicated Charge Pump
to Support a Range of Fixed and Bias Options
• Internal Resistors for Bias Voltage Generation
• Software Contrast Control for LCD Using
Internal Biasing
• Core-Independent Automatic Display Features:
- Dual display memory used to display two
different content displays
Note: To be driven by the LCD controller, pins must
be set as analog inputs. For the port corre-
sponding to the desired common or segment
pin, set TRISx = 1and ANSELx = 1.
The LCD controller includes these features:
- Blink mode of individual pixels or the
complete pixels
- Blanking of individual pixels or the complete pixels
- Timing schedule can be changed without core
intervention based on user configurations
• Direct Driving of LCD Panel
• Three LCD Clock Sources with Selectable
Prescaler
A simplified block diagram of the module is shown in
Figure 18-1.
TABLE 18-1: LCD SEGMENT AVAILABILITY
Segments
Device
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PIC24FJXXXGL306
PIC24FJXXXGL305
PIC24FJXXXGL303
PIC24FJXXXGL302
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
—
—
—
—
—
—
x
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Segments
SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG
Device
63
48
47
40
31
30
29
28
27
26
25
24
23
22
21
20
19
18
PIC24FJXXXGL306
PIC24FJXXXGL305
PIC24FJXXXGL303
PIC24FJXXXGL302
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
x
x
x
x
x
—
—
—
—
—
—
—
—
—
—
—
2019-2020 Microchip Technology Inc.
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FIGURE 18-1:
LCD CONTROLLER MODULE BLOCK DIAGRAM
Data Bus
LCD DATA
32 x 18 (= 8 x 64)
LCDDATA31
LCDDATA30
512
to
64
64
.
.
.
SEG[62:0]
MUX
LCDDATA1
LCDDATA0
16
Bias
Voltage
To I/O Pins
Timing Control
8
LCDCON
LCDPS
LCDSEx
COMx[7:0]
LCD BIAS Generation
LCDREG
LCDREF
Resistor Ladder
FRC Oscillator
LCD Clock
Source Select
LCD
Charge Pump
LPRC Oscillator
SOSC
(Secondary Oscillator)
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18.1 LCD Control Registers
REGISTER 18-1: LCDCON: LCD CONTROL REGISTER
R/W-0
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
LCDEN
LCDSIDL
bit 15
bit 8
U-0
—
R/W-0
R/C-0
R/W-0
CS1
R/W-0
CS0
R/W-0
R/W-0
R/W-0
SLPEN
WERR
LMUX2
LMUX1
LMUX0
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
LCDEN: LCD Driver Enable bit
1= LCD driver module is enabled
0= LCD driver module is not enabled
bit 14
bit 13
Unimplemented: Read as ‘0’
LCDSIDL: Stop LCD Drive in CPU Idle Mode Control bit
1= LCD driver halts in CPU Idle mode
0= LCD driver continues to operate in CPU Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
SLPEN: LCD Driver Enable in Sleep Mode bit
1= LCD driver module is disabled in Sleep mode
0= LCD driver module is enabled in Sleep mode
bit 5
WERR: LCD Write Failed Error bit
1= LCDDATAx register is written while WA (LCDPS[4]) = 0(must be cleared in software)
0= No LCD write error
bit 4-3
CS[1:0]: Clock Source Select bits
1x= SOSC
01= LPRC
00= FRC
bit 2-0
LMUX[2:0]: LCD Commons Select bits
LMUX[2:0]
Multiplex
Bias
111
110
101
100
011
010
001
000
1/8 MUX (COM[7:0])
1/7 MUX (COM[6:0])
1/6 MUX (COM[5:0])
1/5 MUX (COM[4:0])
1/4 MUX (COM[3:0])
1/3 MUX (COM[2:0])
1/2 MUX (COM[1:0])
Static (COM0)
1/3
1/3
1/3
1/3
1/3
1/2 or 1/3
1/2 or 1/3
Static
2019-2020 Microchip Technology Inc.
DS30010198B-page 221
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REGISTER 18-2: LCDREG: LCD CHARGE PUMP CONTROL REGISTER
RW-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
CPEN
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
RW-0
RW-0
CKSEL1
CKSEL0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CPEN: 3.6V Charge Pump Enable bit
1= The regulator generates the highest (3.6V) voltage
0= Highest voltage in the system is supplied externally (AVDD)
bit 14-2
bit 1-0
Unimplemented: Read as ‘0’
CLKSEL[1:0]: Regulator Clock Select Control bits
11= SOSC
10= 8 MHz FRC
01= 32 kHz LPRC
00= Disables regulator and floats regulator voltage output
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REGISTER 18-3: LCDPS: LCD PHASE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
WFT
R/W-0
R-0
R-0
WA
R/W-0
LP3
R/W-0
LP2
R/W-0
LP1
R/W-0
LP0
BIASMD
LCDA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7
Unimplemented: Read as ‘0’
WFT: Waveform Type Select bit
1= Type-B waveform (phase changes on each frame boundary)
0= Type-A waveform (phase changes within each common type)
bit 6
BIASMD: Bias Mode Select bit
When LMUX[2:0] = 000or 011through 111:
0= Static Bias mode (do not set this bit to ‘1’)
When LMUX[2:0] = 001or 010:
1= 1/2 Bias mode
0= 1/3 Bias mode
bit 5
LCDA: LCD Active Status bit
1= LCD driver module is active
0= LCD driver module is inactive
bit 4
WA: LCD Write Allow Status bit
1= Write into the LCDDATAx registers is allowed
0= Write into the LCDDATAx registers is not allowed
bit 3-0
LP[3:0]: LCD Prescaler Select bits
1111= 1:16
1110= 1:15
1101= 1:14
1100= 1:13
1011= 1:12
1010= 1:11
1001= 1:10
1000= 1:9
0111= 1:8
0110= 1:7
0101= 1:6
0100= 1:5
0011= 1:4
0010= 1:3
0001= 1:2
0000= 1:1
\
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REGISTER 18-4: LCDSEx: LCD SEGMENT x ENABLE REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SE(n+15)
SE(n+14)
SE(n+13)
SE(n+12)
SE(n+11)
SE(n+10)
SE(n+9)
SE(n+8)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SE(n)
SE(n+7)
SE(n+6)
SE(n+5)
SE(n+4)
SE(n+3)
SE(n+2)
SE(n+1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
SE(n+15):SE(n): Segment Enable bits
For LCDSE0: n = 0
For LCDSE1: n = 16
For LCDSE2: n = 32
For LCDSE3: n = 48
1= Segment function of the pin is enabled, digital I/O is disabled
0= Segment function of the pin is disabled, digital I/O is enabled
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REGISTER 18-5: LCDDATAx: LCD DATA x REGISTER(1)
R/W-0
S(n+15)Cy
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
S(n+14)Cy
S(n+13)Cy
S(n+12)Cy
S(n+11)Cy
S(n+10)Cy
S(n+9)Cy
S(n+8)Cy
bit 8
R/W-0
S(n+7)Cy
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
S(n)Cy
S(n+6)Cy
S(n+5)Cy
S(n+4)Cy
S(n+3)Cy
S(n+2)Cy
S(n+1)Cy
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
S(n+15)Cy:S(n)Cy: Pixel On bits
For Registers, LCDDATA0 through LCDDATA3: n = (16x), y = 0
For Registers, LCDDATA4 through LCDDATA7: n = (16(x – 4)), y = 1
For Registers, LCDDATA8 through LCDDATA11: n = (16(x – 8)), y = 2
For Registers, LCDDATA12 through LCDDATA15: n = (16(x – 12)), y = 3
For Registers, LCDDATA16 through LCDDATA19: n = (16(x – 16)), y = 4
For Registers, LCDDATA20 through LCDDATA23: n = (16(x – 20)), y = 5
For Registers, LCDDATA24 through LCDDATA27: n = (16(x – 24)), y = 6
For Registers, LCDDATA28 through LCDDATA31: n = (16(x – 28)), y = 7
1= Pixel is on
0= Pixel is off
Note 1: Table 18-2 shows the correlation of each bit in the LCDDATAx registers to the respective common and
segment signals.
TABLE 18-2: LCD DATA REGISTERS AND BITS FOR SEGMENT AND COM COMBINATIONS
Segments
COM Lines
0 to 15
16 to 31
32 to 47
48 to 64
LCDDATA0
S00C0:S15C0
LCDDATA4
LCDDATA1
S16C0:S31C0
LCDDATA5
LCDDATA2
S32C0:S47C0
LCDDATA6
LCDDATA3
S48C0:S63C0
LCDDATA7
0
1
2
3
4
5
6
7
S00C1:S15C1
LCDDATA8
S16C1:S31C1
LCDDATA9
S32C1:S47C1
LCDDATA10
S32C2:S47C2
LCDDATA14
S32C3:S47C3
LCDDATA18
S32C4:S47C4
LCDDATA22
S32C5:S47C5
LCDDATA26
S32C6:S47C6
LCDDATA30
S32C7:S47C7
S48C1:S63C1
LCDDATA11
S48C2:S63C2
LCDDATA15
S48C3:S63C3
LCDDATA19
S48C4:S63C4
LCDDATA23
S48C5:S63C5
LCDDATA27
S48C6:S63C6
LCDDATA31
S48C7:S63C7
S00C2:S15C2
LCDDATA12
S00C3:S15C3
LCDDATA16
S00C4:S15C4
LCDDATA20
S00C5:S15C5
LCDDATA24
S00C6:S15C6
LCDDATA28
S00C7:S15C7
S16C2:S31C2
LCDDATA13
S16C3:S31C3
LCDDATA17
S16C4:S31C4
LCDDATA21
S16C5:S31C5
LCDDATA25
S16C6:S31C6
LCDDATA29
S16C7:S31C7
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REGISTER 18-6: LCDREF: LCD REFERENCE LADDER CONTROL REGISTER
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LCDIRE
LCDCST2
LCDCST1
LCDCST0
VLCD3PE
VLCD2PE
VLCD1PE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
LRLAP1
LRLAP0
LRLBP1
LRLBP0
LRLAT2
LRLAT1
LRLAT0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
LCDIRE: LCD Internal Reference Enable bit
1= Internal LCD reference is enabled and connected to the internal contrast control circuit
0= Internal LCD reference is disabled
bit 14
Unimplemented: Read as ‘0’
bit 13-11
LCDCST[2:0]: LCD Contrast Control bits
Selects the Resistance of the LCD Contrast Control Resistor Ladder:
111= Resistor ladder is at maximum resistance (minimum contrast)
110= Resistor ladder is at 6/7th of maximum resistance
101= Resistor ladder is at 5/7th of maximum resistance
100= Resistor ladder is at 4/7th of maximum resistance
011= Resistor ladder is at 3/7th of maximum resistance
010= Resistor ladder is at 2/7th of maximum resistance
001= Resistor ladder is at 1/7th of maximum resistance
000= Minimum resistance (maximum contrast); resistor ladder is shorted
bit 10
bit 9
VLCD3PE: LCD Bias 3 Pin Enable bit
1= Bias 3 level is connected to the external pin, LCDBIAS3
0= Bias 3 level is internal (internal resistor ladder)
VLCD2PE: LCD Bias 2 Pin Enable bit
1= Bias 2 level is connected to the external pin, LCDBIAS2
0= Bias 2 level is internal (internal resistor ladder)
bit 8
VLCD1PE: LCD Bias 1 Pin Enable bit
1= Bias 1 level is connected to the external pin, LCDBIAS1
0= Bias 1 level is internal (internal resistor ladder)
bit 7-6
LRLAP[1:0]: LCD Reference Ladder A Time Power Control bits
During Time Interval A:
11= Internal LCD reference ladder is powered in High-Power mode
10= Internal LCD reference ladder is powered in Medium Power mode
01= Internal LCD reference ladder is powered in Low-Power mode
00= Internal LCD reference ladder is powered down and unconnected
bit 5-4
LRLBP[1:0]: LCD Reference Ladder B Time Power Control bits
During Time Interval B:
11= Internal LCD reference ladder is powered in High-Power mode
10= Internal LCD reference ladder is powered in Medium Power mode
01= Internal LCD reference ladder is powered in Low-Power mode
00= Internal LCD reference ladder is powered down and unconnected
bit 3
Unimplemented: Read as ‘0’
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REGISTER 18-6: LCDREF: LCD REFERENCE LADDER CONTROL REGISTER (CONTINUED)
bit 2-0
LRLAT[2:0]: LCD Reference Ladder A Time Interval Control bits
Sets the number of 32 clock counts when the A Time Interval Power mode is active.
For Type-A Waveforms (WFT = 0):
111= Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 9 clocks
110= Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 10 clocks
101= Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 11 clocks
100= Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 12 clocks
011= Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 13 clocks
010= Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 14 clocks
001= Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 15 clocks
000= Internal LCD reference ladder is always in B Power mode
For Type-B Waveforms (WFT = 1):
111= Internal LCD reference ladder is in A Power mode for 7 clocks and B Power mode for 25 clocks
110= Internal LCD reference ladder is in A Power mode for 6 clocks and B Power mode for 26 clocks
101= Internal LCD reference ladder is in A Power mode for 5 clocks and B Power mode for 27 clocks
100= Internal LCD reference ladder is in A Power mode for 4 clocks and B Power mode for 28 clocks
011= Internal LCD reference ladder is in A Power mode for 3 clocks and B Power mode for 29 clocks
010= Internal LCD reference ladder is in A Power mode for 2 clocks and B Power mode for 30 clocks
001= Internal LCD reference ladder is in A Power mode for 1 clock and B Power mode for 31 clocks
000= Internal LCD reference ladder is always in B Power mode
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REGISTER 18-7: LCDACTRL: LCD AUTOMATIC CONTROL REGISTER
R/W-0
R/W-0
SMFCS[2:0](1,2,3,4,5)
R/W-0
R/W-0
R/W-0
BLINKFCS[2:0](4,5,6,7)
R/W-0
R/W-0
BLINKMODE[1:0](8,9)
bit 8
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0 R/W-0
FCCS[1:0]
R/W-0
ELCDEN
bit 0
BLANKFCS[2:0](3,5,6,7,10,11)
BLANKMODE[1:0]
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
SMFCS[2:0]: Frame Counter Selection for Data Memory Selection bits(1,2,3,4,5)
When DMSEL[1:0] = 10(one-time switchover from current display memory to another memory):
000= Reserved
001= Selects Frame Counter 0 (FC0)
When DMSEL[1:0] = 11(continues to switch over from one memory to another memory):
000= Reserved
001= Selects Frame Counter 0 (FC0)
010= Selects Frame Counter 0 (FC0), then continues with Frame Counter 1 (FC1) at the frequency
given by the time event
011= Reserved
When DMSEL[1:0] = 11(continues to switch over from one memory to another with a repeated pattern):
100= Alternates between FC0 and FC1 at the frequency given by the time event
101= Reserved
110= Reserved
111= Reserved
Note 1: Secondary memory is selected for pixel enable to Blink or Blank when
BLINKMODE[1:0] = 01| BLANKMODE[1:0] = 01.
2: Secondary memory is used to store data to display or selects the pixel to Blink or Blank.
3: FC1 is used when Blink mode is not selected (i.e., BLINKMODE[1:0] = 00| 11).
4: FC2 is used when Blank mode is not selected (i.e., BLANKMODE[1:0] = 00| 11).
5: Frame counter selection switchover based on time event.
6: Pixel will alternate between ON and OFF state at the frequency given by the selected frame counter.
7: FC0 is used when secondary memory is not selected with switchover function
(i.e., DMSEL[1:0] = 00or 01).
8: Blink mode ON state is effective to the pixel when Blank mode is off.
9: Blink mode OFF state drives ‘0’ to the pixel.
10: One-time Blank continues to Blank until a user changes the Blank mode to enable or disable the
enhanced LCD feature (clears ELCDEN) or SBLANK is clear.
11: In One-Time Blank Configuration mode, the pixel continues to Blink (to alternate between on and off) until
the timer event happens.
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REGISTER 18-7: LCDACTRL: LCD AUTOMATIC CONTROL REGISTER (CONTINUED)
bit 12-10
BLINKFCS[2:0]: Frame Counter Selection for Blink Selection bits (BLINKMODE = 01or 10)(4,5,6,7)
000= Reserved
001= Selects Frame Counter 1 (FC1)
010= Selects Frame Counter 0 (FC0), then continues with Frame Counter 1 (FC1) at the frequency
given by the time event
011= Reserved
100= Alternates between FC0 and FC1 at the frequency given by the time event (repeated pattern)
101= Reserved
110= Reserved
111= Reserved
bit 9-8
bit 7-5
BLINKMODE[1:0]: Blink Mode bits(8,9)
00= Blink mode is disabled
01= Blink mode is enabled with selected pixels (when DMSEL[1:0] = 00)
10= Blink mode is enabled with all pixels
11= Reserved
BLANKFCS[2:0]: Blank Operation Selection from Frame Counter Selection bits(3,5,6,7,10,11)
(when BLANKMODE[1:0] = 01or 10)
000= Reserved
001= Selects Frame Counter 2 (FC2)
010= Selects Frame Counter 0 (FC0), then continues with Frame Counter 1 (FC1) at the frequency
given by the time event
011= Reserved
100= Alternates between FC0 and FC1 at the frequency given by the time event (repeated pattern)
101= Reserved
110= One-time Blank selects Frame Counter 2 (FC2) by the time event(10,11)
111= Reserved
bit 4-3
bit 2-1
bit 0
BLANKMODE[1:0]: Blank Mode bits
00= Blank mode is disabled
01= Blank mode is enabled with selected pixels (when DMSEL[1:0] = 00)
10= Blank mode is enabled with all pixels
11= Reserved
FCCS[1:0]: Clock Source bits
00= LCD clock
01= RTCC
10= CLC1
11= CLC2
ELCDEN: Enhancement LCD Enable bit
1= Enhancement function is enabled
0= Enhancement function is disabled
Note 1: Secondary memory is selected for pixel enable to Blink or Blank when
BLINKMODE[1:0] = 01| BLANKMODE[1:0] = 01.
2: Secondary memory is used to store data to display or selects the pixel to Blink or Blank.
3: FC1 is used when Blink mode is not selected (i.e., BLINKMODE[1:0] = 00| 11).
4: FC2 is used when Blank mode is not selected (i.e., BLANKMODE[1:0] = 00| 11).
5: Frame counter selection switchover based on time event.
6: Pixel will alternate between ON and OFF state at the frequency given by the selected frame counter.
7: FC0 is used when secondary memory is not selected with switchover function
(i.e., DMSEL[1:0] = 00or 01).
8: Blink mode ON state is effective to the pixel when Blank mode is off.
9: Blink mode OFF state drives ‘0’ to the pixel.
10: One-time Blank continues to Blank until a user changes the Blank mode to enable or disable the
enhanced LCD feature (clears ELCDEN) or SBLANK is clear.
11: In One-Time Blank Configuration mode, the pixel continues to Blink (to alternate between on and off) until
the timer event happens.
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REGISTER 18-8: LCDASTAT: LCD AUTOMATIC STATUS REGISTER
U-0
—
R/C-0
R-0
R-0
R/C-0
R/C-0
FC2O
R/C-0
FC1O
R/C-0
FC0O
SBLANK(1,2,3,4) SMEMACT
PMEMACT
TEVENTO
bit 15
bit 8
R/W-0
SMLOCK(7)
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SMCLEAR
PMLOCK(5,6) PMCLEAR
SMEMEN
PMEMDIS
DMSEL1
DMSEL0
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
Unimplemented: Read as ‘0’
SBLANK: Blank Status bit(1,2,3,4)
1= Pixels are in continuous Blank
0= Pixels are not in continuous Blank
bit 13
bit 12
bit 11
bit 10
bit 9
SMEMACT: Secondary Memory Active bit
1= Data display is from secondary memory
0= Data display is not from secondary memory
PMEMACT: Primary Memory Active bit
1= Data display is from primary memory
0= Data display is not from primary memory
TEVENTO: Time Event Overflow bit
1= This flag is set when the time event overflows
0= Timer event does not overflow
FC2O: Frame Counter 2 Overflow bit
1= This flag is set when Frame Counter 2 overflows
0= Frame Counter 2 does not overflow
FC1O: Frame Counter 1 Overflow bit
1= This flag is set when Frame Counter 1 overflows
0= Frame Counter 1 does not overflow
bit 8
FC0O: Frame Counter 0 Overflow bit
1= This flag is set when Frame Counter 0 overflows
0= Frame Counter 0 does not overflow
Note 1: Reflects BLANKFCS[2:0] = 110status.
2: It is the user’s responsibility to clear the bit to make LCD active.
3: This bit is cleared by hardware when the user changes Blank mode = 0or clears the ELCDEN bit.
4: This flag bit is used to generate an enhanced feature interrupt.
5: This bit is effective when SMEMEN = 1; otherwise, the write follows the Write Allow bit, WA (LCDPS[4]).
6: When the PMLOCK bit is set, it does not allow the user to write to the primary memory.
7: When the SMLOCK bit is set, it does not allow the user to write to the secondary memory.
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REGISTER 18-8: LCDASTAT: LCD AUTOMATIC STATUS REGISTER (CONTINUED)
SMLOCK: Secondary Memory Lock Enable bit(7)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
1= Secondary memory is locked
0= Secondary memory is unlocked
SMCLEAR: Secondary Memory Clear Enable bit
1= Secondary memory is cleared immediately
0= Secondary memory is not cleared
PMLOCK: Primary Memory Lock Enable bit(5,6)
1= Primary memory is locked
0= Primary memory is unlocked
PMCLEAR: Primary Memory Clear Enable bit
1= Primary memory is cleared immediately
0= Primary memory is not cleared
SMEMEN: Secondary Memory Enable bit
1= Secondary memory is enabled
0= Secondary memory is disabled
PMEMDIS: Primary Memory Disable bit
1= Primary memory is disabled
0= Primary memory is enabled
DMSEL[1:0]: Data Memory Selection bits
11= Continues alternating selection between primary and secondary memories based on SMFCS[2:0]
10= Alternates selection between primary and secondary memories on SMFCS[2:0]
01= Selects secondary memory as display memory
00= Selects primary memory as display memory
Note 1: Reflects BLANKFCS[2:0] = 110status.
2: It is the user’s responsibility to clear the bit to make LCD active.
3: This bit is cleared by hardware when the user changes Blank mode = 0or clears the ELCDEN bit.
4: This flag bit is used to generate an enhanced feature interrupt.
5: This bit is effective when SMEMEN = 1; otherwise, the write follows the Write Allow bit, WA (LCDPS[4]).
6: When the PMLOCK bit is set, it does not allow the user to write to the primary memory.
7: When the SMLOCK bit is set, it does not allow the user to write to the secondary memory.
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REGISTER 18-9: LCDFC0: LCD FRAME COUNTER 0 REGISTER
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
FC0[15:8](1,2,3)
R/W-0
R/W-0
R/W-0
R/W-0
FC0[7:0](1,2,3)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
FC0[15:0]: Time Base Value bits(1,2,3)
These bits define the overflow value.
Note 1: It is recommended to make the FC0x values to be multiples of the frame frequency.
2: FC0x value must be greater than two.
3: FC0x should not be written when ELCDEN = 1.
REGISTER 18-10: LCDFC1: LCD FRAME COUNTER 1 REGISTER
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
FC1[15:8](1,2,3)
R/W-0
R/W-0
R/W-0
R/W-0
FC1[7:0](1,2,3)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
FC1[15:0]: Time Base Value bits(1,2,3)
These bits define the overflow value.
Note 1: It is recommended to make the FC1x values to be multiples of the frame frequency.
2: FC1x value must be greater than two.
3: FC1x should not be written when ELCDEN = 1.
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REGISTER 18-11: LCDFC2: LCD FRAME COUNTER 2 REGISTER
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
FC2[15:8](1,2,3)
R/W-0
R/W-0
R/W-0
R/W-0
FC2[7:0](1,2,3)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
FC2[15:0]: Time Base Value bits(1,2,3)
These bits define the overflow value.
Note 1: It is recommended to make the FC2x values to be multiples of the frame frequency.
2: FC2x value must be greater than two.
3: FC2x should not be written when ELCDEN = 1.
REGISTER 18-12: LCDEVENT: LCD TIME EVENT SELECTION REGISTER
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
TEVENT[15:8](1,2,3)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TEVENT[7:0](1,2,3)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15:0
TEVENT[15:0]: Time Base Event Value bits(1,2,3)
These bits define the time event value.
Note 1: The TEVENTx value should be multiples of the frame frequency.
2: The TEVENTx value should be greater than the FCx value.
3: The overflow is (TEVENTx * 16 ±1); the TEVENTx overflow gets ±1 based on the TEVENTx ratio with the
FCx value.
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REGISTER 18-13: LCDSDATAx: LCD SDATA x REGISTER
R/W-0
S(n+15)Cy
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
S(n+14)Cy
S(n+13)Cy
S(n+12)Cy
S(n+11)Cy
S(n+10)Cy
S(n+9)Cy
S(n+8)Cy
bit 8
R/W-0
S(n+7)Cy
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
S(n)Cy
S(n+6)Cy
S(n+5)Cy
S(n+4)Cy
S(n+3)Cy
S(n+2)Cy
S(n+1)Cy
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15:0
S(n+15)Cy:S(n)Cy: Pixel Blink/Blank Enable bits (Segment x and Common y)
If BLINKMODE[1:0] = 01or BLANKMODE[1:0] = 01:
1= Pixel is selected for Blink or Blank
0= Pixel is not selected for Blink or Blank
Else:
SEGxCOMy: Pixel Data bits (Segment x and Common y)
1= Pixel on (dark)
0= Pixel off (clear)
TABLE 18-3: LCD SDATA REGISTERS AND BITS FOR SEGMENT AND COM COMBINATIONS
Segments
COM Lines
0 to 15
16 to 31
32 to 47
48 to 64
LCDSDATA0
S00C0:S15C0
LCDSDATA4
S00C1:S15C1
LCDSDATA8
S00C2:S15C2
LCDSDATA12
S00C3:S15C3
LCDSDATA16
S00C4:S15C4
LCDSDATA20
S00C5:S15C5
LCDSDATA24
S00C6:S15C6
LCDSDATA28
S00C7:S15C7
LCDSDATA1
S16C0:S31C0
LCDSDATA5
S16C1:S31C1
LCDSDATA9
S16C2:S31C2
LCDSDATA13
S16C3:S31C3
LCDSDATA17
S16C4:S31C4
LCDSDATA21
S16C5:S31C5
LCDSDATA25
S16C6:S31C6
LCDSDATA29
S16C7:S31C7
LCDSDATA2
S32C0:S47C0
LCDSDATA6
S32C1:S47C1
LCDSDATA10
S32C2:S47C2
LCDSDATA14
S32C3:S47C3
LCDSDATA18
S32C4:S47C4
LCDSDATA22
S32C5:S47C5
LCDSDATA26
S32C6:S47C6
LCDSDATA30
S32C7:S47C7
LCDSDATA3
S48C0:S63C0
LCDSDATA7
S48C1:S63C1
LCDSDATA11
S48C2:S63C2
LCDSDATA15
S48C3:S63C3
LCDSDATA19
S48C4:S63C4
LCDSDATA23
S48C5:S63C5
LCDSDATA27
S48C6:S63C6
LCDSDATA31
S48C7:S63C7
0
1
2
3
4
5
6
7
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19.1 RTCC Source Clock
19.0 REAL-TIME CLOCK AND
CALENDAR (RTCC) WITH
TIMESTAMP
The RTCC clock divider block converts the incoming
oscillator source into accurate 1/2 and 1 second clocks
for the RTCC. The clock divider is optimized to work
with three different oscillator sources:
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to “RTCC with Timestamp”
(www.microchip.com/DS70005193) in the
“dsPIC33/PIC24 Family Reference Man-
ual”. The information in this data sheet
supersedes the information in the FRM.
• 32.768 kHz Crystal Oscillator
• 32 kHz Low-Power RC Oscillator (LPRC)
• External 50 Hz or 60 Hz Powerline Frequency
An asynchronous prescaler, PS[1:0] (RTCCON2L[5:4]), is
provided that allows the RTCC to work with higher
speed clock sources, such as the system clock. Divide
ratios of 1:16, 1:64 or 1:256 may be selected, allowing
sources up to 32 MHz to clock the RTCC.
The RTCC provides the user with a Real-Time Clock
and Calendar (RTCC) function that can be calibrated.
19.1.1
COARSE FREQUENCY DIVISION
Key features of the RTCC module are:
• Selectable Clock Source
The clock divider block has a 16-bit counter used to
divide the input clock frequency. The divide ratio is set
by the DIV[15:0] register bits (RTCCON2H[15:0]). The
DIV[15:0] bits should be programmed with a value to
produce a nominal 1/2 second clock divider count
period.
• Provides Hours, Minutes and Seconds Using
24-Hour Format
• Visibility of One Half Second Period
• Provides Calendar – Weekday, Date, Month
and Year
19.1.2
FINE FREQUENCY DIVISION
• Alarm-Configurable for Half a Second, 1 Second,
10 Seconds, 1 Minute, 10 Minutes, 1 Hour, 1 Day,
1 Week, 1 Month or 1 Year
The fine frequency division is set using the FDIV[4:0]
(RTCCON2L[15:11]) bits. Increasing the FDIVx value
will lengthen the overall clock divider period.
• Alarm Repeat with Decrementing Counter
• Alarm with Indefinite Repeat Chime
If FDIV[4:0] = 00000, the fine frequency division circuit
is effectively disabled. Otherwise, it will optionally
remove a clock pulse from the input of the clock divider
every 1/2 second. This functionality will allow the user to
remove up to 31 pulses over a fixed period of
16 seconds, depending on the value of FDIVx.
• Year 2000 to 2099 Leap Year Correction
• BCD Format for Smaller Software Overhead
• Optimized for Long-Term Battery Operation
• User Calibration of the 32.768 kHz Clock
Crystal/32 kHz INTRC Frequency with Periodic
Auto-Adjust
The value for DIV[15:0] is calculated as shown in
Equation 19-1. The fractional remainder of the DIV[15:0]
calculation result can be used to calculate the value for
FDIV[4:0].
• Fractional Second Synchronization
• Calibration to within ±2.64 Seconds Error
per Month
EQUATION 19-1: RTCC CLOCK DIVIDER
OUTPUT FREQUENCY
• Calibrates Up to 260 ppm of Crystal Error
• Ability to Periodically Wake-up External Devices
without CPU Intervention (external power control)
F
IN
FOUT =
FDIV[4:0]
2 • (PS[1:0] Prescaler) • (DIV[15:0] + 1) +
• Power Control Output for External Circuit Control
• Calibration takes Effect Every 15 Seconds
• Timestamp Capture Register for Time and Date
32
The DIV[15:0] value is the integer part of this calculation:
• Programmable Prescaler and Clock Divider
Circuit allows Operation with Any Clock Source
Up to 32 MHz, Including 32.768 kHz Crystal,
50/60 Hz Powerline Clock, External Real-Time
Clock (RTC) or 32 kHz LPRC Clock
F
IN
DIV[15:0] =
– 1
2 • (PS[1:0] Prescaler
)
The FDIV[4:0] value is the fractional part of the DIV[15:0]
calculation, multiplied by 32.
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FIGURE 19-1:
RTCC BLOCK DIAGRAM
PWCPS[1:0]
Alarm Registers
Comparators
Power
Control
Repeat
Control
RTCOE
PS[1:0]
1/2
Second
RTCC
PPS
Clock
Divider
Time/Date
Registers
CLKSEL[1:0]
Timestamp Time/
Date Registers
OUTSEL[2:0]
Note 1: In Retention mode, the maximum peripheral output frequency to an I/O pin must be limited to 33 kHz or less.
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Clearing the WRLOCK bit requires an unlock sequence
after it has been written to a ‘1’, writing two bytes con-
secutively to the NVMKEY register. A sample assembly
sequence is shown in Example 19-1. If WRLOCK is
already cleared, it can be set to ‘1’ without using the
unlock sequence.
19.2 RTCC Module Registers
The RTCC module registers are organized into four
categories:
• RTCC Control Registers
• RTCC Value Registers
• Alarm Value Registers
• Timestamp Registers
Note:
To avoid accidental writes to the timer, it is
recommended that the WRLOCK bit
(RTCCON1L[11]) is kept clear at any
other time. For the WRLOCK bit to be set,
there is only one instruction cycle time
window allowed between the 55h/AA
sequence and the setting of WRLOCK;
therefore, it is recommended that code
follow the procedure in Example 19-1.
19.2.1
REGISTER MAPPING
Previous RTCC implementations used a Register
Pointer to access the RTCC Time and Date registers,
as well as the Alarm Time and Date registers. These
registers are now mapped to memory and are
individually addressable.
19.2.2
WRITE LOCK
19.2.3
SELECTING RTCC CLOCK SOURCE
To prevent spurious changes to the Time Control or Time
Value registers, the WRLOCK bit (RTCCON1L[11]) must
be cleared (‘0’). The POR default state is when the
WRLOCK bit is ‘0’ and is cleared on any device Reset
(POR, BOR, MCLR). It is recommended that the
WRLOCK bit be set to ‘1’ after the Date and Time
registers are properly initialized, and after the RTCEN bit
(RTCCON1L[15]) has been set.
The clock source for the RTCC module can be selected
using the CLKSEL[1:0] bits in the RTCCON2L register.
When the bits are set to ‘00’, the Secondary Oscillator
(SOSC) is used as the reference clock and when the
bits are ‘01’, LPRC is used as the reference clock.
When CLKSEL[1:0] = 10, the external powerline (50 Hz
and 60 Hz) is used as the clock source. When
CLKSEL[1:0] = 11, the system clock is used as the
clock source.
Any attempt to write to the RTCEN bit, the RTCCON2L/H
registers, or the Date or Time registers, will be ignored
as long as WRLOCK is ‘1’. The Alarm, Power Control
and Timestamp registers can be changed when
WRLOCK is ‘1’.
EXAMPLE 19-1:
SETTING THE WRLOCK BIT
DISI
MOV
MOV
MOV
MOV
MOV
BCLR
#6
;disable interrupts for 6 instructions
#NVKEY, W1
#0x55, W2
W2, [W1]
#0xAA, W3
W3, [W1]
; first unlock code
; write first unlock code
; second unlock sequence
; write second unlock sequence
; clear the WRLOCK bit
RTCCON1L, #WRLOCK
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19.3 RTCC Registers
19.3.1
RTCC CONTROL REGISTERS
REGISTER 19-1: RTCCON1L: RTCC CONTROL REGISTER 1 LOW
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RTCEN
WRLOCK
PWCEN
PWCPOL
PWCPOE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
RTCOE
OUTSEL2
OUTSEL1
OUTSEL0
TSAEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
RTCEN: RTCC Enable bit
1= RTCC is enabled and counts from selected clock source
0= RTCC is not enabled
bit 14-12
bit 11
Unimplemented: Read as ‘0’
WRLOCK: RTCC Register Write Lock bit
1= RTCC registers are locked
0= RTCC registers may be written to by user
bit 10
bit 9
PWCEN: Power Control Enable bit
1= Power control is enabled
0= Power control is disabled
PWCPOL: Power Control Polarity bit
1= Power control output is active-high
0= Power control output is active-low
bit 8
PWCPOE: Power Control Output Enable bit
1= Power control output pin is enabled
0= Power control output pin is disabled
bit 7
RTCOE: RTCC Output Enable bit
1= RTCC output is enabled
0= RTCC output is disabled
bit 6-4
OUTSEL[2:0]: RTCC Output Signal Selection bits
111= Unused
110= Unused
101= Unused
100= Timestamp A event
011= Power control
010= RTCC input clock
001= Second clock
000= Alarm event
bit 3-1
bit 0
Unimplemented: Read as ‘0’
TSAEN: Timestamp A Enable bit
1= Timestamp event will occur when a low pulse is detected on the TMPRN pin
0= Timestamp is disabled
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REGISTER 19-2: RTCCON1H: RTCC CONTROL REGISTER 1 HIGH
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
ALRMEN
CHIME
AMASK3
AMASK2
AMASK1
AMASK0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALMRPT7
ALMRPT6
ALMRPT5
ALMRPT4
ALMRPT3
ALMRPT2
ALMRPT1
ALMRPT0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ALRMEN: Alarm Enable bit
1= Alarm is enabled (cleared automatically after an alarm event whenever ALMRPT[7:0] = 00h and
CHIME = 0)
0= Alarm is disabled
bit 14
CHIME: Chime Enable bit
1= Chime is enabled; ALMRPT[7:0] bits roll over from 00h to FFh
0= Chime is disabled; ALMRPT[7:0] bits stop once they reach 00h
bit 13-12
bit 11-8
Unimplemented: Read as ‘0’
AMASK[3:0]: Alarm Mask Configuration bits
0000= Every half second
0001= Every second
0010= Every ten seconds
0011= Every minute
0100= Every ten minutes
0101= Every hour
0110= Once a day
0111= Once a week
1000= Once a month
1001= Once a year (except when configured for February 29th, once every four years)
101x= Reserved – do not use
11xx= Reserved – do not use
bit 7-0
ALMRPT[7:0]: Alarm Repeat Counter Value bits
11111111= Alarm will repeat 255 more times
•
•
•
00000000= Alarm will repeat 0 more times
The counter decrements on any alarm event. The counter is prevented from rolling over from ‘00’ to ‘FF’
unless CHIME = 1.
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REGISTER 19-3: RTCCON2L: RTCC CONTROL REGISTER 2 LOW
R/W-0
FDIV4
R/W-0
FDIV3
R/W-0
FDIV2
R/W-0
FDIV1
R/W-0
FDIV0
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
PS1
R/W-0
PS0
U-0
—
U-0
—
R/W-0
R/W-0
PWCPS1
PWCPS0
CLKSEL1
CLKSEL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-11
FDIV[4:0]: Fractional Clock Divide bits
00000= No fractional clock division
00001= Increase period by 1 RTCC input clock cycle every 16 seconds
00010= Increase period by 2 RTCC input clock cycles every 16 seconds
•
•
•
11101= Increase period by 30 RTCC input clock cycles every 16 seconds
11111= Increase period by 31 RTCC input clock cycles every 16 seconds
bit 10-8
bit 7-6
Unimplemented: Read as ‘0’
PWCPS[1:0]: Power Control Prescale Select bits
00= 1:1
01= 1:16
10= 1:64
11= 1:256
bit 5-4
PS[1:0]: Prescale Select bits
00= 1:1
01= 1:16
10= 1:64
11= 1:256
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
CLKSEL[1:0]: Clock Select bits
00= SOSC
01= LPRC
10= PWRLCLK pin
11= System clock
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19.3.2
RTCVAL REGISTER MAPPINGS
REGISTER 19-4: RTCCON2H: RTCC CONTROL REGISTER 2 HIGH(1)
R/W-0
bit 15
R/W-1
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
DIV[15:8]
R/W-1
DIV[7:0]
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
DIV[15:0]: Clock Divide bits
Sets the period of the clock divider counter; value should cause a nominal 1/2 second underflow.
Note 1: A write to this register is only allowed when WRLOCK = 1.
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REGISTER 19-5: RTCCON3L: RTCC CONTROL REGISTER 3 LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PWCSAMP[7:0]
bit 15
R/W-0
bit 7
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
PWCSTAB[7:0](1)
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
PWCSAMP[7:0]: Power Control Sample Window Timer bits
11111111= Sample window is always enabled, even when PWCEN = 0
11111110= Sample window is 254 TPWCCLK clock periods
•
•
•
00000001= Sample window is 1 TPWCCLK clock period
00000000= No sample window
bit 7-0
PWCSTAB[7:0]: Power Control Stability Window Timer bits(1)
11111111= Stability window is 255 TPWCCLK clock periods
11111110= Stability window is 254 TPWCCLK clock periods
•
•
•
00000001= Stability window is 1 TPWCCLK clock period
00000000= No stability window; sample window starts when the alarm event triggers
Note 1: The sample window always starts when the stability window timer expires, except when its initial value is 00h.
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REGISTER 19-6: RTCSTATL: RTCC STATUS REGISTER LOW
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/C-0
U-0
—
R/C-0
TSAEVT(1)
R-0
R-0
R-0
ALMEVT
SYNC
ALMSYNC HALFSEC(2)
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5
Unimplemented: Read as ‘0’
ALMEVT: Alarm Event bit
1= An alarm event has occurred
0= An alarm event has not occurred
bit 4
bit 3
Unimplemented: Read as ‘0’
TSAEVT: Timestamp A Event bit(1)
1= A timestamp event has occurred
0= A timestamp event has not occurred
bit 2
bit 1
SYNC: Synchronization Status bit
1= TIMEL/H registers may change during software read
0= TIMEL/H registers may be read safely
ALMSYNC: Alarm Synchronization Status bit
1= Alarm registers (ALMTIMEL/H and ALMDATEL/H) and Alarm Mask Configuration bits
(AMASK[3:0]) should not be modified, and Alarm control bits (ALRMEN, ALMRPT[7:0]) may
change during software read
0= Alarm registers and Alarm control bits may be written/modified safely
bit 0
HALFSEC: Half Second Status bit(2)
1= Second half period of a second
0= First half period of a second
Note 1: User software may write a ‘1’ to this location to initiate a Timestamp A event; timestamp capture is not
valid until TSAEVT reads as ‘1’.
2: This bit is read-only; it is cleared to ‘0’ on a write to the SECONE[3:0] bits.
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19.3.3
RTCC VALUE REGISTERS
REGISTER 19-7: TIMEL: RTCC TIME REGISTER LOW
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
SECTEN[2:0]: Binary Coded Decimal Value of Seconds ‘10’ Digit bits
Contains a value from 0 to 5.
bit 11-8
bit 7-0
SECONE[3:0]: Binary Coded Decimal Value of Seconds ‘1’ Digit bits
Contains a value from 0 to 9.
Unimplemented: Read as ‘0’
REGISTER 19-8: TIMEH: RTCC TIME REGISTER HIGH
U-0
—
U-0
—
R/W-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-12
Unimplemented: Read as ‘0’
HRTEN[1:0]: Binary Coded Decimal Value of Hours ‘10’ Digit bits
Contains a value from 0 to 2.
bit 11-8
HRONE[3:0]: Binary Coded Decimal Value of Hours ‘1’ Digit bits
Contains a value from 0 to 9.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN[2:0]: Binary Coded Decimal Value of Minutes ‘10’ Digit bits
Contains a value from 0 to 5.
bit 3-0
MINONE[3:0]: Binary Coded Decimal Value of Minutes ‘1’ Digit bits
Contains a value from 0 to 9.
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REGISTER 19-9: DATEL: RTCC DATE REGISTER LOW
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
WDAY2
WDAY1
WDAY0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-12
Unimplemented: Read as ‘0’
DAYTEN[1:0]: Binary Coded Decimal Value of Days ‘10’ Digit bits
Contains a value from 0 to 3.
bit 11-8
DAYONE[3:0]: Binary Coded Decimal Value of Days ‘1’ Digit bits
Contains a value from 0 to 9.
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
WDAY[2:0]: Binary Coded Decimal Value of Weekdays ‘1’ Digit bits
Contains a value from 0 to 6.
REGISTER 19-10: DATEH: RTCC DATE REGISTER HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
R/W-x
R/W-x
R/W-x
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MTHTEN
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-12
bit 11-8
bit 7-5
bit 4
YRTEN[3:0]: Binary Coded Decimal Value of Years ‘10’ Digit bits
YRONE[3:0]: Binary Coded Decimal Value of Years ‘1’ Digit bits
Unimplemented: Read as ‘0’
MTHTEN: Binary Coded Decimal Value of Months ‘10’ Digit bit
Contains a value either 0 or 1.
bit 3-0
MTHONE[3:0]: Binary Coded Decimal Value of Months ‘1’ Digit bits
Contains a value from 0 to 9.
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19.3.4
ALARM VALUE REGISTERS
REGISTER 19-11: ALMTIMEL: RTCC ALARM TIME REGISTER LOW
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
SECTEN[2:0]: Binary Coded Decimal Value of Seconds ‘10’ Digit bits
Contains a value from 0 to 5.
bit 11-8
bit 7-0
SECONE[3:0]: Binary Coded Decimal Value of Seconds ‘1’ Digit bits
Contains a value from 0 to 9.
Unimplemented: Read as ‘0’
REGISTER 19-12: ALMTIMEH: RTCC ALARM TIME REGISTER HIGH
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-12
Unimplemented: Read as ‘0’
HRTEN[1:0]: Binary Coded Decimal Value of Hours ‘10’ Digit bits
Contains a value from 0 to 2.
bit 11-8
HRONE[3:0]: Binary Coded Decimal Value of Hours ‘1’ Digit bits
Contains a value from 0 to 9.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN[2:0]: Binary Coded Decimal Value of Minutes ‘10’ Digit bits
Contains a value from 0 to 5.
bit 3-0
MINONE[3:0]: Binary Coded Decimal Value of Minutes ‘1’ Digit bits
Contains a value from 0 to 9.
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REGISTER 19-13: ALMDATEL: RTCC ALARM DATE REGISTER LOW
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
WDAY2
WDAY1
WDAY0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-12
Unimplemented: Read as ‘0’
DAYTEN[1:0]: Binary Coded Decimal Value of Days ‘10’ Digit bits
Contains a value from 0 to 3.
bit 11-8
DAYONE[3:0]: Binary Coded Decimal Value of Days ‘1’ Digit bits
Contains a value from 0 to 9.
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
WDAY[2:0]: Binary Coded Decimal Value of Weekdays ‘1’ Digit bits
Contains a value from 0 to 6.
REGISTER 19-14: ALMDATEH: RTCC ALARM DATE REGISTER HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MTHTEN
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-12
bit 11-8
bit 7-5
bit 4
YRTEN[3:0]: Binary Coded Decimal Value of Years ‘10’ Digit bits
YRONE[3:0]: Binary Coded Decimal Value of Years ‘1’ Digit bits
Unimplemented: Read as ‘0’
MTHTEN: Binary Coded Decimal Value of Months ‘10’ Digit bit
Contains a value either 0 or 1.
bit 3-0
MTHONE[3:0]: Binary Coded Decimal Value of Months ‘1’ Digit bits
Contains a value from 0 to 9.
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19.3.5
TIMESTAMP REGISTERS
REGISTER 19-15: TSATIMEL: RTCC TIMESTAMP A TIME REGISTER LOW(1)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
SECTEN[2:0]: Binary Coded Decimal Value of Seconds ‘10’ Digit bits
Contains a value from 0 to 5.
bit 11-8
bit 7-0
SECONE[3:0]: Binary Coded Decimal Value of Seconds ‘1’ Digit bits
Contains a value from 0 to 9.
Unimplemented: Read as ‘0’
Note 1: If TSAEN = 0, bits[15:0] can be used for persistent storage throughout a non-Power-on Reset (MCLR,
WDT, etc.).
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REGISTER 19-16: TSATIMEH: RTCC TIMESTAMP A TIME REGISTER HIGH(1)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-12
Unimplemented: Read as ‘0’
HRTEN[1:0]: Binary Coded Decimal Value of Hours ‘10’ Digit bits
Contains a value from 0 to 2.
bit 11-8
HRONE[3:0]: Binary Coded Decimal Value of Hours ‘1’ Digit bits
Contains a value from 0 to 9.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN[2:0]: Binary Coded Decimal Value of Minutes ‘10’ Digit bits
Contains a value from 0 to 5.
bit 3-0
MINONE[3:0]: Binary Coded Decimal Value of Minutes ‘1’ Digit bits
Contains a value from 0 to 9.
Note 1: If TSAEN = 0, bits[15:0] can be used for persistence storage throughout a non-Power-on Reset (MCLR,
WDT, etc.).
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REGISTER 19-17: TSADATEL: RTCC TIMESTAMP A DATE REGISTER LOW(1)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DAYTEN1
DAYTEN0
DAYONE3
DAYONE2
DAYONE1
DAYONE0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
WDAY2
WDAY1
WDAY0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-12
Unimplemented: Read as ‘0’
DAYTEN[1:0]: Binary Coded Decimal Value of Days ‘10’ Digit bits
Contains a value from 0 to 3.
bit 11-8
DAYONE[3:0]: Binary Coded Decimal Value of Days ‘1’ Digit bits
Contains a value from 0 to 9.
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
WDAY[2:0]: Binary Coded Decimal Value of Weekdays ‘1’ Digit bits
Contains a value from 0 to 6.
Note 1: If TSAEN = 0, bits[15:0] can be used for persistence storage throughout a non-Power-on Reset (MCLR,
WDT, etc.).
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REGISTER 19-18: TSADATEH: RTCC TIMESTAMP A DATE REGISTER HIGH(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
MTHTEN
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-12
bit 11-8
bit 7-5
bit 4
YRTEN[3:0]: Binary Coded Decimal Value of Years ‘10’ Digit bits
YRONE[3:0]: Binary Coded Decimal Value of Years ‘1’ Digit bits
Unimplemented: Read as ‘0’
MTHTEN: Binary Coded Decimal Value of Months ‘10’ Digit bit
Contains a value either 0 or 1.
bit 3-0
MTHONE[2:0]: Binary Coded Decimal Value of Months ‘1’ Digit bits
Contains a value from 0 to 9.
Note 1: If TSAEN = 0, bits[15:0] can be used for persistence storage throughout a non-Power-on Reset (MCLR,
WDT, etc.).
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19.5.1
CONFIGURING THE ALARM
19.4 Calibration
The alarm feature is enabled using the ALRMEN bit.
This bit is cleared when an alarm is issued. Writes to
the Alarm Value registers should only take place when
ALRMEN = 0.
19.4.1
CLOCK SOURCE CALIBRATION
A crystal oscillator that is connected to the RTCC may
be calibrated to provide an accurate 1-second clock in
two ways. First, coarse frequency adjustment is per-
formed by adjusting the value written to the DIV[15:0]
bits. Secondly, a 5-bit value can be written to the
FDIV[4:0] control bits to perform a fine clock division.
As shown in Figure 19-2, the interval selection of the
alarm is configured through the AMASK[3:0] bits
(RTCCON1H[11:8]). These bits determine which and
how many digits of the alarm must match the clock
value for the alarm to occur.
The DIVx and FDIVx values can be concatenated and
considered as a 21-bit prescaler value. If the oscillator
source is slightly faster than ideal, the FDIV[4:0] value
can be increased to make a small decrease in the RTC
frequency. The value of DIV[15:0] should be increased
to make larger decreases in the RTC frequency. If the
oscillator source is slower than ideal, FDIV[4:0] may be
decreased for small calibration changes and DIV[15:0]
may need to be decreased to make larger calibration
changes.
The alarm can also be configured to repeat based on a
preconfigured interval. The amount of times this
occurs, once the alarm is enabled, is stored in the
ALMRPT[7:0] bits (RTCCON1H[7:0]). When the value
of the ALMRPTx bits equals 00h and the CHIME bit
(RTCCON1H[14]) is cleared, the repeat function is dis-
abled and only a single alarm will occur. The alarm can
be repeated, up to 255 times, by loading ALMRPT[7:0]
with FFh.
Before calibration, the user must determine the error of
the crystal. This should be done using another timer
resource on the device or an external timing reference.
It is up to the user to include in the error value, the initial
error of the crystal, drift due to temperature and drift
due to crystal aging.
After each alarm is issued, the value of the ALMRPTx
bits is decremented by one. Once the value has reached
00h, the alarm will be issued one last time, after which,
the ALRMEN bit will be cleared automatically and the
alarm will turn off.
Indefinite repetition of the alarm can occur if the
CHIME bit = 1. Instead of the alarm being disabled
when the value of the ALMRPTx bits reaches 00h, it
rolls over to FFh and continues counting indefinitely
while CHIME is set.
19.5 Alarm
• Configurable from half second to one year
• Enabled using the ALRMEN bit (RTCCON1H[15])
• One-time alarm and repeat alarm options are
available
19.5.2
ALARM INTERRUPT
At every alarm event, an interrupt is generated. This
output is completely synchronous to the RTCC clock
and can be used as a trigger clock to the other
peripherals.
Note:
Changing any of the register bits, other
than the RTCOE bit (RTCCON1L[7]), the
ALMRPT[7:0] bits (RTCCON1H[7:0] and
the CHIME bit, while the alarm is enabled
(ALRMEN = 1), can result in a false alarm
event leading to a false alarm interrupt. To
avoid a false alarm event, the timer and
alarm values should only be changed
while the alarm is disabled (ALRMEN = 0).
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FIGURE 19-2:
ALARM MASK SETTINGS
Day of
the
Week
Alarm Mask Setting
(AMASK[3:0])
Month
Day
Hours
Minutes
Seconds
0000- Every half second
0001- Every second
0010- Every 10 seconds
0011- Every minute
0100- Every 10 minutes
0101- Every hour
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
m
m
m
m
m
m
m
m
m
m
m
0110- Every day
h
h
h
h
h
h
h
h
0111- Every week
1000- Every month
d
d
d
d
(1)
1001- Every year
m
m
d
Note 1: Annually, except when configured for February 29.
Once the RTCC and PWC are enabled and running, the
PWC logic will generate a control output and a sample
gate output. The control output is driven out on the
RTCC pin (when RTCOE = 1and OUTSEL[2:0] = 011)
and is used to power up or down the device, as
described above.
19.6 Power Control
The RTCC includes a power control feature that allows
the device to periodically wake-up an external device,
wait for the device to be stable before sampling wake-up
events from that device and then shut down the external
device. This can be done completely autonomously by
the RTCC, without the need to wake-up from the current
lower power mode.
Once the control output is asserted, the stability window
begins, in which the external device is given enough
time to power up and provide a stable output.
To use this feature:
Once the output is stable, the RTCC provides a sample
gate during the sample window. The use of this sample
gate depends on the external device being used, but
typically, it is used to mask out one or more wake-up
signals from the external device.
1. Enable the RTCC (RTCEN = 1).
2. Set the PWCEN bit (RTCCON1L[10]).
3. Configure the RTCC pin to drive the PWC control
signal (RTCOE = 1and OUTSEL[2:0] = 011).
The polarity of the PWC control signal may be chosen
using the PWCPOL bit (RTCCON1L[9]). An active-low
or active-high signal may be used with the appropriate
external switch to turn on or off the power to one or
more external devices. The active-low setting may also
be used in conjunction with an open-drain setting on
the RTCC pin, in order to drive the ground pin(s) of the
external device directly (with the appropriate external
VDD pull-up device), without the need for external
switches. Finally, the CHIME bit should be set to enable
the PWC periodicity.
Finally, both the stability and the sample windows close
after the expiration of the sample window and the
external device is powered down.
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19.6.1
POWER CONTROL CLOCK SOURCE
19.7.1
TIMESTAMP OPERATION
The stability and sample windows are controlled by the
PWCSAMPx and PWCSTABx bit fields in the
RTCCON3L register (RTCCON3L[15:8] and [7:0],
respectively). As both the stability and sample windows
are defined in terms of the RTCC clock, their
absolute values vary by the value of the PWC clock
base period (TPWCCLK). For example, using a
32.768 kHz SOSC input clock would produce a
TPWCCLK of 1/32768 = 30.518 µs. The 8-bit magnitude
of PWCSTABx and PWCSAMPx allows for a window
size of 0 to 255 TPWCCLK. The period of the PWC clock
can also be adjusted with a 1:1, 1:16, 1:64 or
1:256 prescaler, determined by the PWCPS[1:0] bits
(RTCCON2L[7:6]).
The event input is enabled for timestamping using the
TSAEN bit (RTCCON1L[0]). When the timestamp event
occurs, the present time and date values will be stored in
the TSATIMEL/H and TSADATEL/H registers, the
TSAEVT status bit (RTCSTATL[3]) will be set and an
RTCC interrupt will occur. A new timestamp capture event
cannot occur until the user clears the TSAEVT status bit.
Note 1: The TSATIMEL/H and TSADATEL/H regis-
ter pairs can be used for data storage when
TSAEN = 0. The values of TSATIMEL/H
and TSADATEL/H will be maintained
throughout all types of non-Power-on
Resets (MCLR, WDT, etc).
In addition, certain values for the PWCSTABx and
PWCSAMPx fields have specific control meanings in
determining power control operations. If either bit field is
00h, the corresponding window is inactive. In addition, if
the PWCSTABx field is FFh, the stability window
remains active continuously, even if power control is
disabled.
19.7.2
MANUAL TIMESTAMP OPERATION
The current time and date may be captured in the
TSATIMEL/H and TSADATEL/H registers by writing a
‘1’ to the TSAEVT bit location while the timestamp func-
tionality is enabled (TSAEN = 1). This write will not set
the TSAEVT bit, but it will initiate a timestamp capture.
The TSAEVT bit will be set when the capture operation
is complete. The user must poll the TSAEVT bit to
determine when the capture operation is complete.
19.7 Event Timestamping
The RTCC includes a set of Timestamp registers that
may be used for the capture of Time and Date register
values when an external input signal is received. The
RTCC will trigger a timestamp event when a low pulse
occurs on the TMPRN pin.
After the Timestamp registers have been read, the
TSAEVT bit should be cleared to allow further
hardware or software timestamp capture events.
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The 32-bit programmable CRC generator provides a
hardware implemented method of quickly generating
checksums for various networking and security
applications. It offers the following features:
20.0 32-BIT PROGRAMMABLE
CYCLIC REDUNDANCY CHECK
(CRC) GENERATOR
• User-Programmable CRC Polynomial Equation,
Up to 32 Bits
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to “32-Bit Programmable Cyclic
• Programmable Shift Direction (little or big-endian)
• Independent Data and Polynomial Lengths
• Configurable Interrupt Output
Redundancy
(www.microchip.com/DS30009729) in the
“dsPIC33/PIC24 Family Reference
Check
(CRC)”
• Data FIFO
Figure 20-1 displays a simplified block diagram of the
CRC generator. A simple version of the CRC shift
engine is displayed in Figure 20-2.
Manual”. The information in this data
sheet supersedes the information in the
FRM.
FIGURE 20-1:
CRC BLOCK DIAGRAM
CRCDATH
CRCDATL
FIFO Empty
Variable FIFO
(4x32, 8x16 or 16x8)
Event
CRCISEL
1
0
CRCWDATH
CRCWDATL
CRC
Interrupt
LENDIAN
Shift Buffer
1
0
CRC Shift Engine
Shift
Complete
Event
Shifter Clock
2 * FCY
FIGURE 20-2:
CRC SHIFT ENGINE DETAIL
CRC Shift Engine
CRCWDATH
CRCWDATL
Read/Write Bus
X1
(1)
X0
Xn
Shift Buffer
Data
(1)
Bit 0
Bit 1
Bit n
Note 1: n = PLEN[4:1] + 1.
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20.1.2
DATA INTERFACE
20.1 User Interface
The module incorporates a FIFO that works with a
variable datum width. Input datum width can be config-
ured to any value, between 1 and 32 bits, using the
DWIDTH[4:0] bits (CRCCON2[12:8]). When the datum
width is greater than 15, the FIFO is 4 words deep.
When the DWIDTHx bits are between 15 and 8, the
FIFO is 8 words deep. When the DWIDTHx bits are
less than 8, the FIFO is 16 words deep.
20.1.1
POLYNOMIAL INTERFACE
The CRC module can be programmed for CRC
polynomials of up to the 32nd order, using up to 32 bits.
Polynomial length, which reflects the highest exponent
in the equation, is selected by the PLEN[4:0] bits
(CRCCON2[4:0]).
The CRCXORL and CRCXORH registers control which
exponent terms are included in the equation. Setting a
particular bit includes that exponent term in the equa-
tion. Functionally, this includes an XOR operation on
the corresponding bit in the CRC engine. Clearing the
bit disables the XOR.
The data for which the CRC is to be calculated must
first be written into the FIFO. Even if the datum width is
less than 8, the smallest data element that can be
written into the FIFO is 1 byte. For example, if the
DWIDTHx bits are 5, then the size of the data is
DWIDTH[4:0] + 1 or 6. The data are written as a whole
byte; the two unused upper bits are ignored by the
module.
For example, consider two CRC polynomials, one a
16-bit and the other a 32-bit equation.
Once datum is written into the MSb of the CRCDAT reg-
isters (that is, the MSb as defined by the datum width),
the value of the VWORD[4:0] bits (CRCCON1[12:8])
increments by one. For example, if the DWIDTHx bits
are 24, the VWORDx bits will increment when bit 7 of
CRCDATH is written. Therefore, CRCDATL must always
be written to before CRCDATH.
EQUATION 20-1: 16-BIT, 32-BIT CRC
POLYNOMIALS
X16 + X12 + X5 + 1
and
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +
X8 + X7 + X5 + X4 + X2 + X + 1
The CRC engine starts shifting data when the CRCGO
bit (CRCCON1[4]) is set and the value of the VWORDx
bits is greater than zero.
To program these polynomials into the CRC generator,
set the register bits, as shown in Table 20-1.
Each word is copied out of the FIFO into a buffer
register, which decrements the VWORDx bits. The data
are then shifted out of the buffer. The CRC engine
continues shifting at a rate of two bits per instruction
cycle, until the VWORDx bits reach zero. This means
that for a given data width, it takes half that number of
instructions for each word to complete the calculation.
For example, it takes 16 cycles to calculate the CRC for
a single word of 32-bit data.
Note that the appropriate positions are set to ‘1’ to indi-
cate that they are used in the equation (for example,
X26 and X23). The ‘0’ bit required by the equation is
always XORed; thus, X0 is a don’t care. For a poly-
nomial of length 32, it is assumed that the 32nd bit will
be used. Therefore, the X[31:1] bits do not have the
32nd bit.
When the VWORDx bits reach the maximum value for
the configured value of the DWIDTHx bits (4, 8 or 16),
the CRCFUL bit (CRCCON1[7]) becomes set. When
the VWORDx bits reach zero, the CRCMPT bit
(CRCCON1[6]) becomes set. The FIFO is emptied and
the VWORD[4:0] bits are set to ‘00000’ whenever
CRCEN is ‘0’.
At least one instruction cycle must pass after a write to
CRCWDAT before a read of the VWORDx bits is done.
TABLE 20-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALS
Bit Values
CRC Control Bits
16-Bit Polynomial
32-Bit Polynomial
PLEN[4:0]
X[31:16]
X[15:1]
01111
11111
0000 0000 0000 0001
0001 0000 0010 000
0000 0100 1100 0001
0001 1101 1011 011
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Or, if the data width (DWIDTH[4:0] bits) is less than the
polynomial length (PLEN[4:0] bits):
20.1.3
DATA SHIFT DIRECTION
The LENDIAN bit (CRCCON1[3]) is used to control the
shift direction. By default, the CRC will shift data
through the engine, MSb first. Setting LENDIAN (= 1)
causes the CRC to shift data, LSb first. This setting
allows better integration with various communication
schemes and removes the overhead of reversing the
bit order in software. Note that this only changes the
direction that the data are shifted into the engine. The
result of the CRC calculation will still be a normal CRC
result, not a reverse CRC result.
1. Clear the CRC Interrupt Selection bit
(CRCISEL = 0) to get the interrupt when all
shifts are done. Clear the CRC interrupt flag.
Write dummy data in the CRCDAT registers and
wait until the CRC interrupt flag is set.
2. Read the final CRC result from the CRCWDAT
registers.
3. Restore the data width (DWIDTH[4:0] bits) for
further calculations (optional). If the data width
(DWIDTH[4:0] bits) is equal to, or less than, the
polynomial length (PLEN[4:0] bits):
20.1.4
INTERRUPT OPERATION
The module generates an interrupt that is configurable
by the user for either of two conditions.
a) Clear the CRC Interrupt Selection bit
(CRCISEL = 0) to get the interrupt when all
shifts are done.
If CRCISEL is ‘0’, an interrupt is generated when the
VWORD[4:0] bits make a transition from a value of ‘1’
to ‘0’. If CRCISEL is ‘1’, an interrupt will be generated
after the CRC operation finishes and the module sets
the CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’
will not generate an interrupt. Note that when an
interrupt occurs, the CRC calculation would not yet be
complete. The module will still need (PLENx + 1)/2
clock cycles after the interrupt is generated until the
CRC calculation is finished.
b) Suspend the calculation by setting
CRCGO = 0.
c) Clear the CRC interrupt flag.
d) Write the dummy data with the total data
length equal to the polynomial length in the
CRCDAT registers.
e) Resume the calculation by setting
CRCGO = 1.
f) Wait until the CRC interrupt flag is set.
20.1.5
TYPICAL OPERATION
g) Read the final CRC result from the
CRCWDAT registers.
To use the module for a typical CRC calculation:
There are eight registers used to control programmable
CRC operation:
1. Set the CRCEN bit to enable the module.
2. Configure the module for desired operation:
• CRCCON1
• CRCCON2
• CRCXORL
• CRCXORH
• CRCDATL
• CRCDATH
• CRCWDATL
• CRCWDATH
a) Program the desired polynomial using the
CRCXOR registers and PLEN[4:0] bits.
b) Configure the data width and shift direction
using the DWIDTH[4:0] and LENDIAN bits.
3. Set the CRCGO bit to start the calculations.
4. Set the desired CRC non-direct initial value by
writing to the CRCWDAT registers.
5. Load all data into the FIFO by writing to the
CRCDAT registers as space becomes available
(the CRCFUL bit must be zero before the next
data loading).
The CRCCON1 and CRCCON2 registers (Register 20-1
and Register 20-2) control the operation of the module
and configure the various settings.
6. Wait until the data FIFO is empty (CRCMPT bit
is set).
The CRCXOR registers (Register 20-3 and
Register 20-4) select the polynomial terms to be used
in the CRC equation. The CRCDAT and CRCWDAT
registers are each register pairs that serve as buffers
for the double-word input data, and CRC processed
output, respectively.
7. Read the result:
If the data width (DWIDTH[4:0] bits) is more than
the polynomial length (PLEN[4:0] bits):
a) Wait (DWIDTH[4:0] + 1)/2 instruction cycles
to make sure that shifts from the shift buffer
are finished.
b) Change the data width to the polynomial
length (DWIDTH[4:0] = PLEN[4:0]).
c) Write one dummy data word to the CRCDAT
registers.
d) Wait two instruction cycles to move the data
from the FIFO to the shift buffer and
(PLEN[4:0] + 1)/2 instruction cycles to shift
out the result.
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REGISTER 20-1: CRCCON1: CRC CONTROL 1 REGISTER
R/W-0
U-0
—
R/W-0
CSIDL
HSC/R-0
VWORD4
HSC/R-0
VWORD3
HSC/R-0
VWORD2
HSC/R-0
VWORD1
HSC/R-0
VWORD0
CRCEN
bit 15
bit 8
HSC/R-0
CRCFUL
HSC/R-1
CRCMPT
R/W-0
HC/R/W-0
CRCGO
R/W-0
U-0
—
U-0
—
U-0
—
CRCISEL
LENDIAN
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CRCEN: CRC Enable bit
1= Enables module
0= Disables module; all state machines, pointers and CRCWDAT/CRCDAT registers reset; other SFRs
are NOT reset
bit 14
bit 13
Unimplemented: Read as ‘0’
CSIDL: CRC Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-8
bit 7
VWORD[4:0]: CRC Pointer Value bits
Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN[4:0] 7 or 16
when PLEN[4:0] 7.
CRCFUL: CRC FIFO Full bit
1= FIFO is full
0= FIFO is not full
bit 6
CRCMPT: CRC FIFO Empty bit
1= FIFO is empty
0= FIFO is not empty
bit 5
CRCISEL: CRC Interrupt Selection bit
1= Interrupt on FIFO is empty; the final word of datum is still shifting through the CRC
0= Interrupt on shift is complete and results are ready
bit 4
CRCGO: Start CRC bit
1= Starts CRC serial shifter
0= CRC serial shifter is turned off
bit 3
LENDIAN: Data Shift Direction Select bit
1= Data word is shifted into the CRC, starting with the LSb (little endian)
0= Data word is shifted into the CRC, starting with the MSb (big endian)
bit 2-0
Unimplemented: Read as ‘0’
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REGISTER 20-2: CRCCON2: CRC CONTROL 2 REGISTER
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DWIDTH4
DWIDTH3
DWIDTH2
DWIDTH1
DWIDTH0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PLEN4
PLEN3
PLEN2
PLEN1
PLEN0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
DWIDTH[4:0]: CRC Data Word Width Configuration bits
Configures the width of the data word (Data Word Width – 1).
Unimplemented: Read as ‘0’
bit 7-5
bit 4-0
PLEN[4:0]: Polynomial Length Configuration bits
Configures the length of the polynomial (Polynomial Length – 1).
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REGISTER 20-3: CRCXORL: CRC XOR POLYNOMIAL REGISTER LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
X[15:8]
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
X[7:1]
R/W-0
R/W-0
U-0
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-1
bit 0
X[15:1]: XOR of Polynomial Term Xn Enable bits
Unimplemented: Read as ‘0’
REGISTER 20-4: CRCXORH: CRC XOR POLYNOMIAL REGISTER HIGH
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
X[31:24]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
X[23:16]
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
X[31:16]: XOR of Polynomial Term Xn Enable bits
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The Configurable Logic Cell (CLC) module allows the
user to specify combinations of signals as inputs to a
logic function and to use the logic output to control
other peripherals or I/O pins. This provides greater
flexibility and potential in embedded designs, since the
CLC module can operate outside the limitations of
software execution and supports a vast amount of
output designs.
21.0 CONFIGURABLE LOGIC CELL
(CLC)
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive refer-
ence source. For more information, refer
to “Configurable Logic Cell (CLC)”
(www.microchip.com/DS70005298) in the
There are four input gates to the selected logic func-
tion. These four input gates select from a pool of up to
32 signals that are selected using four data source
selection multiplexers. Figure 21-1 shows an overview
of the module. Figure 21-3 shows the details of the data
source multiplexers and logic input gate connections.
“dsPIC33/PIC24
Family
Reference
Manual”. The information in this data sheet
supersedes the information in the FRM.
FIGURE 21-1:
CLCx MODULE
CLCIN[0]
CLCIN[1]
CLCIN[2]
CLCIN[3]
CLCIN[4]
CLCIN[5]
CLCIN[6]
CLCIN[7]
CLCIN[8]
CLCIN[9]
CLCIN[10]
CLCIN[11]
CLCIN[12]
CLCIN[13]
CLCIN[14]
CLCIN[15]
CLCIN[16]
CLCIN[17]
CLCIN[18]
CLCIN[19]
CLCIN[20]
CLCIN[21]
CLCIN[22]
CLCIN[23]
CLCIN[24]
CLCIN[25]
CLCIN[26]
CLCIN[27]
CLCIN[28]
CLCIN[29]
CLCIN[30]
CLCIN[31]
See Figure 21-2
LCOE
LCEN
Gate 1
Gate 2
Gate 3
Gate 4
TRISx Control
CLCx
Logic
Output
CLCx
Logic
Output
Function
LCPOL
Interrupt
det
MODE[2:0]
INTP
INTN
Sets
CLCxIF
Flag
Interrupt
det
See Figure 21-3
Note: All register bits shown in this figure can be found in the CLCxCONL register.
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FIGURE 21-2:
CLCx LOGIC FUNCTION COMBINATORIAL OPTIONS
AND – OR
OR – XOR
Gate 1
Gate 2
Gate 3
Gate 4
Gate 1
Gate 2
Gate 3
Gate 4
Logic Output
Logic Output
MODE[2:0] = 000
MODE[2:0] = 001
4-Input AND
S-R Latch
Gate 1
Gate 1
Gate 2
Gate 3
Gate 4
Logic Output
S
R
Q
Gate 2
Gate 3
Gate 4
Logic Output
MODE[2:0] = 011
MODE[2:0] = 010
1-Input D Flip-Flop with S and R
2-Input D Flip-Flop with R
Gate 4
Gate 4
Gate 2
D
Q
Logic Output
S
R
Logic Output
Gate 2
Gate 1
Gate 3
D
Q
Gate 1
Gate 3
R
MODE[2:0] = 101
MODE[2:0] = 100
J-K Flip-Flop with R
1-Input Transparent Latch with S and R
Gate 4
Gate 2
Gate 1
Gate 4
Gate 3
J
Q
Logic Output
S
Gate 2
Gate 1
Gate 3
D
Q
Logic Output
K
R
LE
R
MODE[2:0] = 110
MODE[2:0] = 111
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FIGURE 21-3:
CLCx INPUT SOURCE SELECTION DIAGRAM
Data Selection
000
CLCIN[0]
CLCIN[1]
CLCIN[2]
CLCIN[3]
CLCIN[4]
CLCIN[5]
CLCIN[6]
CLCIN[7]
Data Gate 1
Data 1 Noninverted
G1D1T
G1D1N
G1D2T
Data 1
Inverted
111
000
DS1x (CLCxSEL[2:0])
G1D2N
G1D3T
G1D3N
G1D4T
Gate 1
CLCIN[8]
CLCIN[9]
G1POL
(CLCxCONH[0])
CLCIN[10]
CLCIN[11]
CLCIN[12]
CLCIN[13]
CLCIN[14]
CLCIN[15]
Data 2 Noninverted
Data 2
Inverted
111
000
G1D4N
DS2x (CLCxSEL[6:4])
CLCIN[16]
CLCIN[17]
CLCIN[18]
CLCIN[19]
CLCIN[20]
CLCIN[21]
CLCIN[22]
CLCIN[23]
Data Gate 2
Gate 2
Data 3 Noninverted
(Same as Data Gate 1)
Data Gate 3
Data 3
Inverted
111
000
Gate 3
Gate 4
DS3x (CLCxSEL[10:8])
(Same as Data Gate 1)
Data Gate 4
CLCIN[24]
CLCIN[25]
CLCIN[26]
CLCIN[27]
CLCIN[28]
CLCIN[29]
CLCIN[30]
CLCIN[31]
(Same as Data Gate 1)
Data 4 Noninverted
Data 4
Inverted
111
DS4x (CLCxSEL[14:12])
Note: All controls are undefined at power-up.
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The CLCx Input MUX Select register (CLCxSEL)
allows the user to select up to four data input sources
using the four data input selection multiplexers. Each
multiplexer has a list of eight data sources available.
21.1 Control Registers
The CLCx module is controlled by the following registers:
• CLCxCONL
• CLCxCONH
• CLCxSEL
The CLCx Gate Logic Input Select registers (CLCxGLSL
and CLCxGLSH) allow the user to select which outputs
from each of the selection MUXes are used as inputs to
the input gates of the logic cell. Each data source MUX
outputs both a true and a negated version of its output.
All of these eight signals are enabled, ORed together by
the logic cell input gates. If no gate inputs are selected,
the output will be zero or one, depending on the GxPOL
bits.
• CLCxGLSL
• CLCxGLSH
The CLCx Control registers (CLCxCONL and
CLCxCONH) are used to enable the module and inter-
rupts, control the output enable bit, select output polarity
and select the logic function. The CLCx Control registers
also allow the user to control the logic polarity of not only
the cell output, but also some intermediate variables.
REGISTER 21-1: CLCxCONL: CLCx CONTROL REGISTER LOW
R/W-0
LCEN
U-0
—
U-0
—
U-0
—
R/W-0
INTP
R/W-0
INTN
U-0
—
U-0
—
bit 15
bit 8
R/W-0
LCOE
R-0
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
LCOUT
LCPOL
MODE2
MODE1
MODE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
LCEN: CLCx Enable bit
1= CLCx is enabled and mixing input signals
0= CLCx is disabled and has logic zero outputs
bit 14-12
bit 11
Unimplemented: Read as ‘0’
INTP: CLCx Positive Edge Interrupt Enable bit
1= Interrupt will be generated when a rising edge occurs on LCOUT
0= Interrupt will not be generated
bit 10
INTN: CLCx Negative Edge Interrupt Enable bit
1= Interrupt will be generated when a falling edge occurs on LCOUT
0= Interrupt will not be generated
bit 9-8
bit 7
Unimplemented: Read as ‘0’
LCOE: CLCx Port Enable bit
1= CLCx port pin output is enabled
0= CLCx port pin output is disabled
bit 6
LCOUT: CLCx Data Output Status bit
1= CLCx output high
0= CLCx output low
bit 5
LCPOL: CLCx Output Polarity Control bit
1= The output of the module is inverted
0= The output of the module is not inverted
bit 4-3
Unimplemented: Read as ‘0’
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REGISTER 21-1: CLCxCONL: CLCx CONTROL REGISTER LOW (CONTINUED)
bit 2-0 MODE[2:0]: CLCx Mode bits
111= Cell is a 1-input transparent latch with S and R
110= Cell is a JK flip-flop with R
101= Cell is a 2-input D flip-flop with R
100= Cell is a 1-input D flip-flop with S and R
011= Cell is an SR latch
010= Cell is a 4-input AND
001= Cell is an OR-XOR
000= Cell is an AND-OR
REGISTER 21-2: CLCxCONH: CLCx CONTROL REGISTER (HIGH)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
G4POL
G3POL
G2POL
G1POL
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 3
Unimplemented: Read as ‘0’
G4POL: Gate 4 Polarity Control bit
1= The output of Channel 4 logic is inverted when applied to the logic cell
0= The output of Channel 4 logic is not inverted
bit 2
bit 1
bit 0
G3POL: Gate 3 Polarity Control bit
1= The output of Channel 3 logic is inverted when applied to the logic cell
0= The output of Channel 3 logic is not inverted
G2POL: Gate 2 Polarity Control bit
1= The output of Channel 2 logic is inverted when applied to the logic cell
0= The output of Channel 2 logic is not inverted
G1POL: Gate 1 Polarity Control bit
1= The output of Channel 1 logic is inverted when applied to the logic cell
0= The output of Channel 1 logic is not inverted
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REGISTER 21-3: CLCxSEL: CLCx INPUT MUX SELECT REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
DS4[2:0]
DS3[2:0]
bit 15
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
DS2[2:0]
DS1[2:0]
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
DS4[2:0]: Data Selection MUX 4 Signal Selection bits
111= MCCP3 OC out
110= MCCP1 OC out
101= Unimplemented
100= LCD automation timer interrupt
011= SPIx Input (SDIx) corresponding to the CLCx module(1)
010= Comparator 3 output
001= Module-specific CLCx output(1)
000= CLCIND I/O pin
bit 11
Unimplemented: Read as ‘0’
bit 10-8
DS3[2:0]: Data Selection MUX 3 Signal Selection bits
111= MCCP3 OC out
110= MCCP2 OC out
101= DMA Channel 1 interrupt
100= UARTx RX output corresponding to the CLCx module(1)
011= SPIx Output (SDOx) corresponding to the CLCx module(1)
010= Comparator 2 output
001= CLCx output(1)
000= CLCINC I/O pin
bit 7
Unimplemented: Read as ‘0’
bit 6-4
DS2[2:0]: Data Selection MUX 2 Signal Selection bits
111= MCCP2 OC out
110= MCCP1 OC out
101= DMA Channel 0 interrupt
100= A/D conversion done interrupt
011= UARTx TX input corresponding to the CLCx module(1)
010= Comparator 1 output
001= CLCx output(1)
000= CLCINB I/O pin
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DS1[2:0]: Data Selection MUX 1 Signal Selection bits
111= Timer3 match event
110= Timer2 match event
101= Unimplemented
100= REFO output
011= INTRC/LPRC clock source
010= SOSC clock source
001= System clock (TCY)
000= CLCINA I/O pin
Note 1: For more information, see Table 21-1.
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TABLE 21-1: MODULE-SPECIFIC INPUT DATA SOURCES
Input Source
Bit Field Value
CLC1
CLC2
CLC3
CLC4
011
SDI1
CLC2 Output
U1RX
SDI2
SDI1
CLC4 Output
U3RX
SDI2
CLC3 Output
U4RX
DS4[2:0]
DS3[2:0]
DS2[2:0]
001
100
011
001
011
001
CLC1 Output
U2RX
SDO1
SDO2
SDO1
SDO2
CLC1 Output
U1TX
CLC2 Output
U2TX
CLC1 Output
U3TX
CLC2 Output
U4TX
CLC2 Output
CLC1 Output
CLC2 Output
CLC1 Output
REGISTER 21-4: CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
G2D4T
G2D4N
G2D3T
G2D3N
G2D2T
G2D2N
G2D1T
G2D1N
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
G1D4T
G1D4N
G1D3T
G1D3N
G1D2T
G1D2N
G1D1T
G1D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
G2D4T: Gate 2 Data Source 4 True Enable bit
1= The Data Source 4 signal is enabled for Gate 2
0= The Data Source 4 signal is disabled for Gate 2
G2D4N: Gate 2 Data Source 4 Negated Enable bit
1= The Data Source 4 inverted signal is enabled for Gate 2
0= The Data Source 4 inverted signal is disabled for Gate 2
G2D3T: Gate 2 Data Source 3 True Enable bit
1= The Data Source 3 signal is enabled for Gate 2
0= The Data Source 3 signal is disabled for Gate 2
G2D3N: Gate 2 Data Source 3 Negated Enable bit
1= The Data Source 3 inverted signal is enabled for Gate 2
0= The Data Source 3 inverted signal is disabled for Gate 2
G2D2T: Gate 2 Data Source 2 True Enable bit
1= The Data Source 2 signal is enabled for Gate 2
0= The Data Source 2 signal is disabled for Gate 2
G2D2N: Gate 2 Data Source 2 Negated Enable bit
1= The Data Source 2 inverted signal is enabled for Gate 2
0= The Data Source 2 inverted signal is disabled for Gate 2
G2D1T: Gate 2 Data Source 1 True Enable bit
1= The Data Source 1 signal is enabled for Gate 2
0= The Data Source 1 signal is disabled for Gate 2
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REGISTER 21-4: CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER (CONTINUED)
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
G2D1N: Gate 2 Data Source 1 Negated Enable bit
1= The Data Source 1 inverted signal is enabled for Gate 2
0= The Data Source 1 inverted signal is disabled for Gate 2
G1D4T: Gate 1 Data Source 4 True Enable bit
1= The Data Source 4 signal is enabled for Gate 1
0= The Data Source 4 signal is disabled for Gate 1
G1D4N: Gate 1 Data Source 4 Negated Enable bit
1= The Data Source 4 inverted signal is enabled for Gate 1
0= The Data Source 4 inverted signal is disabled for Gate 1
G1D3T: Gate 1 Data Source 3 True Enable bit
1= The Data Source 3 signal is enabled for Gate 1
0= The Data Source 3 signal is disabled for Gate 1
G1D3N: Gate 1 Data Source 3 Negated Enable bit
1= The Data Source 3 inverted signal is enabled for Gate 1
0= The Data Source 3 inverted signal is disabled for Gate 1
G1D2T: Gate 1 Data Source 2 True Enable bit
1= The Data Source 2 signal is enabled for Gate 1
0= The Data Source 2 signal is disabled for Gate 1
G1D2N: Gate 1 Data Source 2 Negated Enable bit
1= The Data Source 2 inverted signal is enabled for Gate 1
0= The Data Source 2 inverted signal is disabled for Gate 1
G1D1T: Gate 1 Data Source 1 True Enable bit
1= The Data Source 1 signal is enabled for Gate 1
0= The Data Source 1 signal is disabled for Gate 1
G1D1N: Gate 1 Data Source 1 Negated Enable bit
1= The Data Source 1 inverted signal is enabled for Gate 1
0= The Data Source 1 inverted signal is disabled for Gate 1
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REGISTER 21-5: CLCxGLSH: CLCx GATE LOGIC INPUT SELECT HIGH REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
G4D4T
G4D4N
G4D3T
G4D3N
G4D2T
G4D2N
G4D1T
G4D1N
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
G3D4T
G3D4N
G3D3T
G3D3N
G3D2T
G3D2N
G3D1T
G3D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
G4D4T: Gate 4 Data Source 4 True Enable bit
1= The Data Source 4 signal is enabled for Gate 4
0= The Data Source 4 signal is disabled for Gate 4
G4D4N: Gate 4 Data Source 4 Negated Enable bit
1= The Data Source 4 inverted signal is enabled for Gate 4
0= The Data Source 4 inverted signal is disabled for Gate 4
G4D3T: Gate 4 Data Source 3 True Enable bit
1= The Data Source 3 signal is enabled for Gate 4
0= The Data Source 3 signal is disabled for Gate 4
G4D3N: Gate 4 Data Source 3 Negated Enable bit
1= The Data Source 3 inverted signal is enabled for Gate 4
0= The Data Source 3 inverted signal is disabled for Gate 4
G4D2T: Gate 4 Data Source 2 True Enable bit
1= The Data Source 2 signal is enabled for Gate 4
0= The Data Source 2 signal is disabled for Gate 4
G4D2N: Gate 4 Data Source 2 Negated Enable bit
1= The Data Source 2 inverted signal is enabled for Gate 4
0= The Data Source 2 inverted signal is disabled for Gate 4
G4D1T: Gate 4 Data Source 1 True Enable bit
1= The Data Source 1 signal is enabled for Gate 4
0= The Data Source 1 signal is disabled for Gate 4
bit 8
G4D1N: Gate 4 Data Source 1 Negated Enable bit
1= The Data Source 1 inverted signal is enabled for Gate 4
0= The Data Source 1 inverted signal is disabled for Gate 4
bit 7
G3D4T: Gate 3 Data Source 4 True Enable bit
1= The Data Source 4 signal is enabled for Gate 3
0= The Data Source 4 signal is disabled for Gate 3
bit 6
G3D4N: Gate 3 Data Source 4 Negated Enable bit
1= The Data Source 4 inverted signal is enabled for Gate 3
0= The Data Source 4 inverted signal is disabled for Gate 3
bit 5
G3D3T: Gate 3 Data Source 3 True Enable bit
1= The Data Source 3 signal is enabled for Gate 3
0= The Data Source 3 signal is disabled for Gate 3
bit 4
G3D3N: Gate 3 Data Source 3 Negated Enable bit
1= The Data Source 3 inverted signal is enabled for Gate 3
0= The Data Source 3 inverted signal is disabled for Gate 3
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REGISTER 21-5: CLCxGLSH: CLCx GATE LOGIC INPUT SELECT HIGH REGISTER (CONTINUED)
bit 3
bit 2
bit 1
bit 0
G3D2T: Gate 3 Data Source 2 True Enable bit
1= The Data Source 2 signal is enabled for Gate 3
0= The Data Source 2 signal is disabled for Gate 3
G3D2N: Gate 3 Data Source 2 Negated Enable bit
1= The Data Source 2 inverted signal is enabled for Gate 3
0= The Data Source 2 inverted signal is disabled for Gate 3
G3D1T: Gate 3 Data Source 1 True Enable bit
1= The Data Source 1 signal is enabled for Gate 3
0= The Data Source 1 signal is disabled for Gate 3
G3D1N: Gate 3 Data Source 1 Negated Enable bit
1= The Data Source 1 inverted signal is enabled for Gate 3
0= The Data Source 1 inverted signal is disabled for Gate 3
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22.1 Basic Operation
22.0 12-BIT A/D CONVERTER WITH
THRESHOLD DETECT
To perform a standard A/D conversion:
1. Configure the module:
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to “12-Bit A/D Converter with
Threshold Detect” (www.microchip.com/
DS39739) in the “dsPIC33/PIC24 Family
Reference Manual”. The information in
this data sheet supersedes the
information in the FRM.
a) Configure port pins as analog inputs by
setting the appropriate bits in the ANSELx
registers (see Section 11.2 “Configuring
Analog Port Pins (ANSELx)” for more
information).
b) Select the voltage reference source to
match the expected range on analog inputs
(AD1CON2[15:13]).
c) Select the positive and negative multiplexer
inputs for each channel (AD1CHS[15:0]).
The A/D Converter has the following key features:
d) Select the analog conversion clock to match
the desired data rate with the processor
clock (AD1CON3[7:0]).
• Successive Approximation Register (SAR)
Conversion
• Selectable 10-Bit or 12-Bit (default) Conversion
Resolution
e) Select the appropriate sample/conversion
sequence
(AD1CON1[7:4]
and
• Conversion Speeds of Up to 350 ksps (12-bit) and
400 ksps (10-bit)
AD1CON3[12:8]).
f) For Channel A scanning operations, select
the positive channels to be included
(AD1CSSH and AD1CSSL registers).
• Up to 20 Analog Input Channels (internal and
external)
• Multiple Internal Reference Input Channels
• External Voltage Reference Input Pins
g) Select how conversion results are
presented in the buffer (AD1CON1[9:8] and
AD1CON5 register).
• Unipolar Differential Sample-and-Hold (S/H)
Amplifier
h) Select the interrupt rate (AD1CON2[5:2]).
i) Turn on A/D module (AD1CON1[15]).
2. Configure the A/D interrupt (if required):
a) Clear the AD1IF bit (IFS0[13]).
• Automated Threshold Scan and Compare
Operation to Pre-Evaluate Conversion Results
• Selectable Conversion Trigger Source
• Fixed Length (one word per channel),
Configurable Conversion Result Buffer
b) Enable the AD1IE interrupt (IEC0[13]).
c) Select the A/D interrupt priority (IPC3[6:4]).
• Four Options for Results Alignment
• Configurable Interrupt Generation
3. If the module is configured for manual sampling,
set the SAMP bit (AD1CON1[1]) to begin
sampling.
• Enhanced DMA Operations with Indirect Address
Generation
• Operation During CPU Sleep and Idle modes
The 12-bit A/D Converter module is an enhanced
version of the 10-bit module offered in earlier PIC24
devices. It is a Successive Approximation Register
(SAR) Converter, enhanced with 12-bit resolution, a
wide range of automatic sampling options, tighter inte-
gration with other analog modules and a configurable
results buffer.
It also includes a unique Threshold Detect feature that
allows the module itself to make simple decisions
based on the conversion results, and enhanced opera-
tion with the DMAController through Peripheral Indirect
Addressing (PIA).
A simplified block diagram for the module is shown in
Figure 22-1.
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FIGURE 22-1:
12-BIT A/D CONVERTER BLOCK DIAGRAM (PIC24FJ128GL306 FAMILY)
Internal Data Bus
16
VR+
VR-
AVDD
AVSS
VREF+
VR- VR+
VINH
VINL
SAR
AN0
AN1
AN2
VINH
Data Formatting
Extended DMA Data
(1)
AN12
VINL
ADC1BUF0:
ADC1BUF15
(1)
AN13
(1)
AD1CON1
AD1CON2
AD1CON3
AD1CON4
AD1CON5
AD1CHS
AN14
(1)
AN15
(1)
AN16
VINH
VBG
AVDD
AVSS
AD1CHITL
AD1CSSL
AD1CSSH
AD1RESDMA
VINL
Sample Control
Input MUX Control
Control Logic
Conversion Control
16
DMA Data Bus
Note 1: Available ANx pins are package-dependent.
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In PIA mode, the buffer space is created as a series of
contiguous smaller buffers, one per analog channel.
The size of the channel buffer determines how many
analog channels can be accommodated. The size of
the buffer is selected by the DMABL[2:0] bits
(AD1CON4[2:0]). The size options range from a single
word per buffer to 128 words. Each channel is allocated
a buffer of this size, regardless of whether or not the
channel will actually have conversion data.
22.2 Extended DMA Operations
In addition to the standard features available on all 12-bit
A/D Converters, PIC24FJ128GL306 family devices
implement a limited extension of DMA functionality.
This extension adds features that work with the
device’s DMA Controller to expand the A/D module’s
data storage abilities beyond the module’s built-in
buffer.
The Extended DMA functionality is controlled by the
DMAEN bit (AD1CON1[11]); setting this bit enables
the functionality. The DMABM bit (AD1CON1[12])
configures how the DMA feature operates.
The IA is created by combining the base address within
a channel buffer with three to five bits (depending on
the buffer size) to identify the channel. The base
address ranges from zero to seven bits wide, depend-
ing on the buffer size. The address is right-padded with
a ‘0’ in order to maintain address alignment in the Data
Space. The concatenated channel and base address
bits are then left-padded with zeros, as necessary, to
complete the 11-bit IA.
22.2.1
EXTENDED BUFFER MODE
Extended Buffer mode (DMABM = 1) maps the A/D
Data Buffer registers and data from all channels above
13 into a user-specified area of data RAM. This allows
users to read the conversion results of channels above
13, which do not have their own memory-mapped A/D
buffer locations, from data memory.
The IA is configured to auto-increment which channel
is written in each analog input’s sub-buffer during write
operations by using the SMPIx bits (AD1CON2[6:2]).
To accomplish this, the DMA destination address must
be configured in Peripheral Indirect Addressing mode,
the DMA destination address must point to the begin-
ning of the buffer, the DMA source address must be
configured in “Remains Unchanged” mode and the
source address should be pointing to the AD1RESDMA
register. The DMA count must be set to generate an
interrupt after the desired number of conversions.
As with PIA operations for any DMA-enabled module,
the base destination address in the DMADSTn register
must be masked properly to accommodate the IA.
Table 22-1 shows how complete addresses are
formed. Note that the address masking varies for each
buffer size option. Because of masking requirements,
some address ranges may not be available for certain
buffer sizes. Users should verify that the DMA base
address is compatible with the buffer size selected.
In Extended Buffer mode, the A/D control bits will function
similarly to non-DMAmodes. The BUFREGEN bit will still
select between FIFO mode and Channel-Aligned mode,
but the number of words in the destination FIFO will be
determined by the SMPI[4:0] bits in DMA mode. In FIFO
mode, the BUFM bit will still split the output FIFO into two
sets of 13 results (the SMPIx bits should be set accord-
ingly) and the BUFS bit will still indicate which set of
results is being written to and which can be read.
Figure 22-2 shows how the parts of the address define
the buffer locations in data memory. In this case, the
module “allocates” 256 bytes of data RAM (1000h to
1100h) for 32 buffers of four words each. However, this
is not a hard allocation and nothing prevents these
locations from being used for other purposes. For
example, in the current case, if Analog Channels 1, 3
and 8 are being sampled and converted, conversion
data will only be written to the channel buffers, starting
at 1008h, 1018h and 1040h. The holes in the PIA buffer
space can be used for any other purpose. It is the
user’s responsibility to keep track of buffer locations
and prevent data overwrites.
22.2.2
PIA MODE
When DMABM = 0, the A/D module is configured to
function with the DMA Controller for Peripheral Indirect
Addressing (PIA) mode operations. In this mode, the
A/D module generates an 11-bit Indirect Address (IA).
This is ORed with the destination address in the DMA
Controller to define where the A/D conversion data will
be stored.
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TABLE 22-1: INDIRECT ADDRESS GENERATION IN PIA MODE
Available
Input
Channels
Buffer Size per
Channel (words)
Generated Offset
Address (lower 11 bits)
Allowable DMADSTn
Addresses
DMABL[2:0]
000
001
010
011
100
101
110
111
1
2
000 00cc ccc0
000 0ccc ccn0
000 cccc cnn0
00c cccc nnn0
0cc cccn nnn0
ccc ccnn nnn0
ccc cnnn nnn0
ccc nnnn nnn0
32
32
32
32
32
32
16
8
xxxx xxxx xx00 0000
xxxx xxxx x000 0000
xxxx xxxx 0000 0000
xxxx xxx0 0000 0000
xxxx xx00 0000 0000
xxxx x000 0000 0000
xxxx x000 0000 0000
xxxx x000 0000 0000
4
8
16
32
64
128
Legend: ccc= Channel number (three to five bits), n= Base buffer address (zero to seven bits),
x= User-definable range of DMADSTn for base address, 0= Masked bits of DMADSTn for IA
FIGURE 22-2:
EXAMPLE OF BUFFER ADDRESS GENERATION IN PIA MODE
(4-WORD BUFFERS PER CHANNEL)
DMABL[2:0] = 010
(4 Words Per Input)
A/D Module
(PIA Mode)
Data RAM
BBA Channel
1000h
Ch 0 Buffer (4 Words)
Ch 1 Buffer (4 Words) 1008h
ccccc(0-31)
000 cccc cnn0(IA)
Ch 2 Buffer (4 Words)
Ch 3 Buffer (4 Words)
1010h
1018h
nn(0-3)
(Buffer Base Address)
Destination
Range
1038h
1040h
Ch 7 Buffer (4 Words)
Ch 8 Buffer (4 Words)
1000h (DMA Base Address)
10F0h
10F8h
Ch 27 Buffer (4 Words)
Ch 29 Buffer (4 Words)
Ch 31 Buffer (4 Words)
DMADSTn
1100h
DMA Channel
Buffer Address
Channel Address
Address Mask
DMA Base Address
1000h
1002h
1004h
1006h
1008h
0001 0000 0000 0000
0001 0000 0000 0010
0001 0000 0000 0100
0001 0000 0000 0110
0001 0000 0000 1000
Ch 0, Word 0
Ch 0, Word 1
Ch 0, Word 2
Ch 0, Word 3
Ch 1, Word 0
Ch 1, Word 1
Ch 1, Word 2
Ch 1, Word 3
100Ah 0001 0000 0000 1010
100Ch 0001 0000 0000 1100
100Eh 0001 0000 0000 1110
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• ANCFG (Register 22-7)
22.3 Registers
• AD1CHITH and AD1CHITL (Register 22-8 and
Register 22-9)
The 12-bit A/D Converter is controlled through a total of
12 registers:
• AD1CSSH and AD1CSSL (Register 22-10 and
Register 22-11)
• AD1CON1 through AD1CON5 (Register 22-1
through Register 22-5)
• AD1RESDMA (not shown) – The 16-bit conversion
buffer for Extended Buffer mode
• AD1CHS (Register 22-6)
REGISTER 22-1: AD1CON1: A/D CONTROL REGISTER 1
R/W-0
ADON
U-0
—
R/W-0
R/W-0
DMABM(1)
R/W-0
R/W-0
R/W-0
R/W-0
ADSIDL
DMAEN
MODE12
FORM1
FORM0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
ASAM
HSC/R/W-0 HSC/R/C-0
SAMP DONE
bit 0
SSRC3
SSRC2
SSRC1
SSRC0
bit 7
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
R = Readable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ADON: A/D Operating Mode bit
1= A/D Converter is operating
0= A/D Converter is off
bit 14
bit 13
Unimplemented: Read as ‘0’
ADSIDL: A/D Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12
bit 11
bit 10
bit 9-8
DMABM: Extended DMA Buffer Mode Select bit(1)
1= Extended Buffer mode: Buffer address is defined by the DMADSTn register
0= PIA mode: Buffer addresses are defined by the DMA Controller and AD1CON4[2:0]
DMAEN: Extended DMA/Buffer Enable bit
1= Extended DMA and buffer features are enabled
0= Extended features are disabled
MODE12: A/D 12-Bit Operation Mode bit
1= 12-bit A/D operation
0= 10-bit A/D operation
FORM[1:0]: Data Output Format bits (see formats following)
11= Fractional result, signed, left justified
10= Absolute fractional result, unsigned, left justified
01= Decimal result, signed, right justified
00= Absolute decimal result, unsigned, right justified
bit 7-4
SSRC[3:0]: Sample Clock Source Select bits
0000= SAMP is cleared by software
0001= INT0
0010= Timer3
0011= Timer5
0101= Timer1 (will not trigger during Sleep mode)
0110= Timer1 (may trigger during Sleep mode)
0111= Auto-Convert mode
Note 1: This bit is only available when Extended DMA and buffer features are available (DMAEN = 1).
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REGISTER 22-1: AD1CON1: A/D CONTROL REGISTER 1 (CONTINUED)
bit 3
bit 2
Unimplemented: Read as ‘0’
ASAM: A/D Sample Auto-Start bit
1= Sampling begins immediately after last conversion; SAMP bit is auto-set
0= Sampling begins when SAMP bit is manually set
bit 1
bit 0
SAMP: A/D Sample Enable bit
1= A/D Sample-and-Hold amplifiers are sampling
0= A/D Sample-and-Hold amplifiers are holding
DONE: A/D Conversion Status bit
1= A/D conversion cycle has completed
0= A/D conversion cycle has not started or is in progress
Note 1: This bit is only available when Extended DMA and buffer features are available (DMAEN = 1).
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REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
r-0
—
R/W-0
R/W-0
U-0
—
U-0
—
PVCFG1
PVCFG0
NVCFG0
BUFREGEN
CSCNA
bit 15
bit 8
R-0
R/W-0
SMPI4
R/W-0
SMPI3
R/W-0
SMPI2
R/W-0
SMPI1
R/W-0
SMPI0
R/W-0
BUFM
R/W-0
ALTS
BUFS
bit 7
bit 0
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-14
bit 13
PVCFG[1:0]: A/D Converter Positive Voltage Reference Configuration bits
1x= Unimplemented, do not use
01= External VREF+
00= AVDD
NVCFG0: A/D Converter Negative Voltage Reference Configuration bit
1= AVSS
0= AVSS
bit 12
bit 11
Reserved: Maintain as ‘0’
BUFREGEN: A/D Buffer Register Enable bit
1= Conversion result is loaded into the buffer location determined by the converted channel
0= A/D result buffer is treated as a FIFO
bit 10
CSCNA: Scan Input Selections for CH0+ During Sample A bit
1= Scans inputs
0= Does not scan inputs
bit 9-8
bit 7
Unimplemented: Read as ‘0’
BUFS: Buffer Fill Status bit
When DMAEN = 1and DMABM = 1:
1= A/D is currently filling the destination buffer from [buffer start + (buffer size/2)] to
[buffer start + (buffer size – 1)]. User should access data located from [buffer start] to
[buffer start + (buffer size/2) – 1].
0= A/D is currently filling the destination buffer from [buffer start] to [buffer start + (buffer size/2) – 1].
User should access data located from [buffer start + (buffer size/2)] to [buffer start + (buffer size – 1)].
When DMAEN = 0:
1= A/D is currently filling ADC1BUF13-ADC1BUF25, user should access data in
ADC1BUF0-ADC1BUF12
0= A/D is currently filling ADC1BUF0-ADC1BUF12, user should access data in
ADC1BUF13-ADC1BUF25
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REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2 (CONTINUED)
bit 6-2
SMPI[4:0]: Interrupt Sample/DMA Increment Rate Select bits
When DMAEN = 1 and DMABM = 0:
11111= Increments the DMA address after completion of the 32nd sample/conversion operation
11110= Increments the DMA address after completion of the 31st sample/conversion operation
•
•
•
00001= Increments the DMA address after completion of the 2nd sample/conversion operation
00000= Increments the DMA address after completion of each sample/conversion operation
When DMAEN = 1and DMABM = 1:
11111= Resets the DMA offset after completion of the 32nd sample/conversion operation
11110= Resets the DMA offset after completion of the 31nd sample/conversion operation
•
•
•
00001= Resets the DMA offset after completion of the 2nd sample/conversion operation
00000= Resets the DMA offset after completion of every sample/conversion operation
When DMAEN = 0:
11111= Interrupts at the completion of the conversion for each 32nd sample
11110= Interrupts at the completion of the conversion for each 31st sample
•
•
•
00001= Interrupts at the completion of the conversion for every other sample
00000= Interrupts at the completion of the conversion for each sample
bit 1
bit 0
BUFM: Buffer Fill Mode Select bit
1= Starts buffer filling at ADC1BUF0 on first interrupt and ADC1BUF13 on next interrupt
0= Always starts filling buffer at ADC1BUF0
ALTS: Alternate Input Sample Mode Select bit
1= Uses channel input selects for Sample A on first sample and Sample B on next sample
0= Always uses channel input selects for Sample A
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REGISTER 22-3: AD1CON3: A/D CONTROL REGISTER 3
R/W-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADRC(1)
EXTSAM
PUMPEN(2)
SAMC4
SAMC3
SAMC2
SAMC1
SAMC0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCS7
ADCS6
ADCS5
ADCS4
ADCS3
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-8
ADRC: A/D Conversion Clock Source bit(1)
1= Dedicated ADC RC clock generator (4 MHz nominal)
0= Clock derived from system clock
EXTSAM: Extended Sampling Time bit
1= A/D is still sampling after SAMP = 0
0= A/D is finished sampling
PUMPEN: Charge Pump Enable bit(2)
1= Charge pump for switches is enabled
0= Charge pump for switches is disabled
SAMC[4:0]: Auto-Sample Time Select bits
11111= 31 TAD
•
•
•
00001= 1 TAD
00000= 0 TAD
bit 7-0
ADCS[7:0]: A/D Conversion Clock Select bits
11111111= 256 • TCY = TAD
•
•
•
00000001= 2 •TCY = TAD
00000000= TCY = TAD
Note 1: Selecting the internal ADC RC clock requires that ADCSx be one or greater. Setting ADCSx = 0when
ADRC = 1will violate the TAD (minimum) specification.
2: The user should enable the charge pump if AVDD is < 2.7V. Longer sample times are required due to the
increase of the internal resistance of the MUX if the charge pump is disabled.
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REGISTER 22-4: AD1CON4: A/D CONTROL REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
DMABL[2:0](1)
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
DMABL[2:0]: DMA Buffer Size Select bits(1)
111= Allocates 128 words of buffer to each analog input
110= Allocates 64 words of buffer to each analog input
101= Allocates 32 words of buffer to each analog input
100= Allocates 16 words of buffer to each analog input
011= Allocates 8 words of buffer to each analog input
010= Allocates 4 words of buffer to each analog input
001= Allocates 2 words of buffer to each analog input
000= Allocates 1 word of buffer to each analog input
Note 1: The DMABL[2:0] bits are only used when AD1CON1[11] = 1and AD1CON1[12] = 0; otherwise, their value
is ignored.
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REGISTER 22-5: AD1CON5: A/D CONTROL REGISTER 5
R/W-0
ASEN
R/W-0
LPEN
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
BGREQ
ASINT1
ASINT0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
WM1
R/W-0
WM0
R/W-0
CM1
R/W-0
CM0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
ASEN: Auto-Scan Enable bit
1= Auto-scan is enabled
0= Auto-scan is disabled
LPEN: Low-Power Enable bit
1= Low power is enabled after scan
0= Full power is enabled after scan
bit 13
bit 12
Unimplemented: Read as ‘0’
BGREQ: Band Gap Request bit
1= Band gap is enabled when the A/D is enabled and active
0= Band gap is not enabled by the A/D
bit 11-10
bit 9-8
Unimplemented: Read as ‘0’
ASINT[1:0]: Auto-Scan (Threshold Detect) Interrupt Mode bits
11= Interrupt after Threshold Detect sequence has completed and a valid compare has occurred
10= Interrupt after a valid compare has occurred
01= Interrupt after Threshold Detect sequence has completed
00= No interrupt
bit 7-4
bit 3-2
Unimplemented: Read as ‘0’
WM[1:0]: Write Mode bits
11= Reserved
10= Auto-compare only (conversion results are not saved, but interrupts are generated when a valid
match occurs, as defined by the CMx and ASINTx bits)
01= Convert and save (conversion results are saved to locations as determined by the register bits
when a match occurs, as defined by the CMx bits)
00= Legacy operation (conversion data are saved to a location determined by the buffer register bits)
bit 1-0
CM[1:0]: Compare Mode bits
11= Outside Window mode: Valid match occurs if the conversion result is outside of the window
defined by the corresponding buffer pair
10= Inside Window mode: Valid match occurs if the conversion result is inside the window defined by
the corresponding buffer pair
01= Greater Than mode: Valid match occurs if the result is greater than the value in the corresponding
buffer register
00= Less Than mode: Valid match occurs if the result is less than the value in the corresponding buffer
register
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REGISTER 22-6: AD1CHS: A/D SAMPLE SELECT REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0NB2
CH0NB1
CH0NB0
CH0SB4
CH0SB3
CH0SB2
CH0SB1
CH0SB0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0NA2
CH0NA1
CH0NA0
CH0SA4
CH0SA3
CH0SA2
CH0SA1
CH0SA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-13
CH0NB[2:0]: Sample B Channel 0 Negative Input Select bits
1xx= Unimplemented
011= Unimplemented
010= AN1-
001= Unimplemented
000= AVSS
bit 12-8
CH0SB[4:0]: Sample B Channel 0 Positive Input Select bits
11111= Reserved
(1)
11110= AVDD
(1)
11101= AVSS
11100= Band Gap Reference (VBG)(1)
10001-11011= Reserved
10000= AN16
01111= AN15
01110= AN14
01101= AN13
01100= AN12
01011= AN11
01010= AN10
01001= AN9
01000= AN8
00111= AN7
00110= AN6
00101= AN5
00100= AN4
00011= AN3
00010= AN2
00001= AN1
00000= AN0
bit 7-5
bit 4-0
CH0NA[2:0]: Sample A Channel 0 Negative Input Select bits
Same definitions as for CHONB[2:0].
CH0SA[4:0]: Sample A Channel 0 Positive Input Select bits
Same definitions as for CHOSB[4:0].
Note 1: These input channels do not have corresponding memory-mapped result buffers.
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REGISTER 22-7: ANCFG: A/D BAND GAP REFERENCE CONFIGURATION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
VBGEN3(1) VBGEN2(1) VBGEN1(1)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2
Unimplemented: Read as ‘0’
VBGEN3: A/D Band Gap Reference Enable bit(1)
1= Band gap reference is enabled
0= Band gap reference is disabled
bit 1
bit 0
VBGEN2: Comparator Band Gap Reference Enable bit(1)
1= Band gap reference is enabled
0= Band gap reference is disabled
VBGEN1: VREG, BOR, HLVD, FRC, NVM and A/D Boost Band Gap Reference Enable bit(1)
1= Band gap reference is enabled
0= Band gap reference is disabled
Note 1: When a module requests a band gap reference voltage, that reference will be enabled automatically after
a brief start-up time. The user can manually enable the band gap references using the ANCFG register,
before enabling the module requesting the band gap reference, to avoid this start-up time (~1 ms).
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REGISTER 22-8: AD1CHITH: A/D SCAN COMPARE HIT REGISTER HIGH
U/0
—
U/0
—
U/0
—
U/0
—
U/0
—
U/0
—
U/0
—
U/0
—
bit 15
bit 8
U/0
—
U/0
—
U/0
—
U/0
—
U/0
—
U/0
—
U/0
—
R/W-0
CHH16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-1
bit 0
Unimplemented: Read as ‘0’
CHH16: A/D Compare Hit bit
If CM[1:0] = 11:
1
0
=
=
A/D Result Buffer n has been written with data or a match has occurred
A/D Result Buffer n has not been written with data
For All Other Values of CM[1:0]:
1
0
= A match has occurred on A/D Result Channel n
No match has occurred on A/D Result Channel n
=
REGISTER 22-9: AD1CHITL: A/D SCAN COMPARE HIT REGISTER LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
CHH[15:8]
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
CHH[7:0]
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
CHH[15:0]: A/D Compare Hit bits
If CM[1:0] = 11:
1
0
=
=
A/D Result Buffer n has been written with data or a match has occurred
A/D Result Buffer n has not been written with data
For All Other Values of CM[1:0]:
1
0
= A match has occurred on A/D Result Channel n
No match has occurred on A/D Result Channel n
=
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REGISTER 22-10: AD1CSSH: A/D INPUT SCAN SELECT REGISTER HIGH
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
CSS[30:28]
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CSS16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
CSS[30:28]: A/D Input Scan Selection bits
bit 14-12
1= Includes corresponding channel for input scan
0= Skips channel for input scan
bit 11-1
bit 0
Unimplemented: Read as ‘0’
CSS16: A/D Input Scan Selection bit
1= Includes corresponding channel for input scan
0= Skips channel for input scan
REGISTER 22-11: AD1CSSL: A/D INPUT SCAN SELECT REGISTER LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
CSS[15:8]
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
CSS[7:0]
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
CSS[15:0]: A/D Input Scan Selection bits
1= Includes corresponding channel for input scan
0= Skips channel for input scan
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FIGURE 22-3:
12-BIT A/D CONVERTER ANALOG INPUT MODEL
AVDD
VT = 0.6V
Sampling
Switch
ANx
SS
RSS
RIC 250
Rs
CHOLD
= S/H Input Capacitance
= 40 pF
VA
ILEAKAGE
500 nA
CPIN
VT = 0.6V
AVSS
Legend: CPIN
= Input Capacitance
= Threshold Voltage
Sampling
Switch
(RSS 3 k)
RMAX
VT
ILEAKAGE = Leakage Current at the Pin due to
Various Junctions
RIC
RSS
CHOLD
= Interconnect Resistance
= Sampling Switch Resistance
= Sample/Hold Capacitance
RMIN
AVDD (V)
AVDDMAX
AVDDMIN
Note: The CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs 2.5 k.
EQUATION 22-1: A/D CONVERSION CLOCK PERIOD
TAD = TCY (ADCS + 1)
TAD
TCY
ADCS =
– 1
Note: Based on TCY = 2/FOSC; Doze mode and PLL are disabled.
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FIGURE 22-4:
12-BIT A/D TRANSFER FUNCTION
Output Code
(Binary (Decimal))
1111 1111 1111(4095)
1111 1111 1110(4094)
0010 0000 0011(2051)
0010 0000 0010(2050)
0010 0000 0001(2049)
0010 0000 0000(2048)
0001 1111 1111(2047)
0001 1111 1110(2046)
0001 1111 1101(2045)
0000 0000 0001(1)
0000 0000 0000(0)
Voltage Level
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FIGURE 22-5:
10-BIT A/D TRANSFER FUNCTION
Output Code
(Binary (Decimal))
11 1111 1111(1023)
11 1111 1110(1022)
10 0000 0011(515)
10 0000 0010(514)
10 0000 0001(513)
10 0000 0000(512)
01 1111 1111(511)
01 1111 1110(510)
01 1111 1101(509)
00 0000 0001(1)
00 0000 0000(0)
Voltage Level
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voltage reference input from one of the internal band
gap references or the comparator voltage reference
generator (VBG and CVREF).
23.0 TRIPLE COMPARATOR
MODULE
Note:
This data sheet summarizes the features of
The comparator outputs may be directly connected to
the CxOUT pins. When the respective COE bit equals
‘1’, the I/O pad logic makes the unsynchronized output
of the comparator available on the pin.
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive ref-
erence source. For more information, refer
to “Scalable Comparator Module”
(www.microchip.com/DS39734) in the
“dsPIC33/PIC24 Family Reference Man-
ual”. The information in this data sheet
supersedes the information in the FRM.
A simplified block diagram of the module in shown in
Figure 23-1. Diagrams of the possible individual
comparator configurations are shown in Figure 23-2
through Figure 23-4.
Each comparator has its own control register,
CMxCON (Register 23-1), for enabling and configuring
its operation. The output and event status of all three
comparators is provided in the CMSTAT register
(Register 23-2).
The triple comparator module provides three dual input
comparators. The inputs to the comparator can be
configured to use any one of five external analog inputs
(CxINA, CxINB, CxINC, CxIND and CVREF+) and a
FIGURE 23-1:
TRIPLE COMPARATOR MODULE BLOCK DIAGRAM
EVPOL[1:0]
CCH[1:0]
CEVT
Trigger/Interrupt
Logic
Input
Select
Logic
COE
CPOL
VIN-
C1
00
01
10
11
VIN+
CxINB
CxINC
CxIND
C1OUT
Pin
COUT
–
EVPOL[1:0]
CPOL
00
VBG
CEVT
Trigger/Interrupt
Logic
11
CVREF+
COE
VIN-
(1)
C2
CVREFM[1:0]
VIN+
C2OUT
Pin
COUT
0
1
EVPOL[1:0]
CPOL
CxINA
+
0
1
Trigger/Interrupt
Logic
CEVT
Comparator Voltage
Reference
COE
VIN-
CVREF+
C3
VIN+
(1)
CVREFP
C3OUT
Pin
COUT
CREF
Note 1: Refer to the CVRCON register (Register 24-1) for bit details.
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FIGURE 23-2:
INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 0
Comparator Off
CEN = 0, CREF = x, CCH[1:0] = xx
COE
VIN-
Cx
VIN+
Off (Read as ‘0’)
CxOUT
Pin
Comparator CxINB > CxINA Compare
Comparator CxINC > CxINA Compare
CEN = 1, CCH[1:0] = 00, CVREFM[1:0] = xx
CEN = 1, CCH[1:0] = 01, CVREFM[1:0] = xx
COE
COE
VIN-
VIN-
CxINB
CxINC
Cx
Cx
VIN+
VIN+
CxINA
CxINA
CxOUT
Pin
CxOUT
Pin
Comparator VBG > CxINA Compare
CEN = 1, CCH[1:0] = 11, CVREFM[1:0] = 00
Comparator CxIND > CxINA Compare
CEN = 1, CCH[1:0] = 10, CVREFM[1:0] = xx
COE
COE
VIN-
VIN-
VBG
CxIND
Cx
Cx
VIN+
VIN+
CxINA
CxINA
CxOUT
Pin
CxOUT
Pin
Comparator CVREF+ > CxINA Compare
CEN = 1, CCH[1:0] = 11, CVREFM[1:0] = 11
COE
VIN-
CVREF+
Cx
VIN+
CxINA
CxOUT
Pin
FIGURE 23-3:
INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1AND CVREFP = 0
Comparator CxINC > CVREF Compare
Comparator CxINB > CVREF Compare
CEN = 1, CCH[1:0] = 00, CVREFM[1:0] = xx
CEN = 1, CCH[1:0] = 01, CVREFM[1:0] = xx
COE
COE
VIN-
VIN-
CxINC
CxINB
Cx
Cx
VIN+
VIN+
CVREF
CVREF
CxOUT
Pin
CxOUT
Pin
Comparator VBG > CVREF Compare
CEN = 1, CCH[1:0] = 11, CVREFM[1:0] = 00
Comparator CxIND > CVREF Compare
CEN = 1, CCH[1:0] = 10, CVREFM[1:0] = xx
COE
COE
VIN-
VIN-
VBG
CxIND
Cx
Cx
VIN+
VIN+
CVREF
CVREF
CxOUT
Pin
CxOUT
Pin
Comparator CVREF+ > CVREF Compare
CEN = 1, CCH[1:0] = 11, CVREFM[1:0] = 11
COE
VIN-
CVREF+
Cx
VIN+
CVREF
CxOUT
Pin
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FIGURE 23-4:
INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1AND CVREFP = 1
Comparator CxINC > CVREF Compare
CEN = 1, CCH[1:0] = 01, CVREFM[1:0] = xx
Comparator CxINB > CVREF Compare
CEN = 1, CCH[1:0] = 00, CVREFM[1:0] = xx
COE
COE
VIN-
VIN-
CxINC
CxINB
Cx
Cx
VIN+
VIN+
CVREF+
CVREF+
CxOUT
Pin
CxOUT
Pin
Comparator VBG > CVREF Compare
CEN = 1, CCH[1:0] = 11, CVREFM[1:0] = 00
Comparator CxIND > CVREF Compare
CEN = 1, CCH[1:] = 10, CVREFM[1:0] = xx
COE
COE
VIN-
VIN-
VBG
CxIND
Cx
Cx
VIN+
VIN+
CVREF+
CVREF+
CxOUT
Pin
CxOUT
Pin
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REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS
(COMPARATORS 1 THROUGH 3)
R/W-0
CEN
R/W-0
COE
R/W-0
CPOL
U-0
—
U-0
—
U-0
—
HS/R/W-0
CEVT
HSC/R-0
COUT
bit 15
bit 8
R/W-0
R/W-0
U-0
—
R/W-0
CREF
U-0
—
U-0
—
R/W-0
CCH1
R/W-0
CCH0
EVPOL1
EVPOL0
bit 7
bit 0
Legend:
HS = Hardware Settable bit
W = Writable bit
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
CEN: Comparator Enable bit
1= Comparator is enabled
0= Comparator is disabled
COE: Comparator Output Enable bit
1= Comparator output is present on the CxOUT pin
0= Comparator output is internal only
CPOL: Comparator Output Polarity Select bit
1= Comparator output is inverted
0= Comparator output is not inverted
bit 12-10
bit 9
Unimplemented: Read as ‘0’
CEVT: Comparator Event bit
1= Comparator event that is defined by EVPOL[1:0] has occurred; subsequent triggers and interrupts
are disabled until the bit is cleared
0= Comparator event has not occurred
bit 8
COUT: Comparator Output bit
When CPOL = 0:
1= VIN+ > VIN-
0= VIN+ < VIN-
When CPOL = 1:
1= VIN+ < VIN-
0= VIN+ > VIN-
bit 7-6
EVPOL[1:0]: Trigger/Event/Interrupt Polarity Select bits
11= Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0)
10= Trigger/event/interrupt is generated on transition of the comparator output:
If CPOL = 0(noninverted polarity):
High-to-low transition only.
If CPOL = 1(inverted polarity):
Low-to-high transition only.
01= Trigger/event/interrupt is generated on transition of comparator output:
If CPOL = 0(noninverted polarity):
Low-to-high transition only.
If CPOL = 1(inverted polarity):
High-to-low transition only.
00= Trigger/event/interrupt generation is disabled
Unimplemented: Read as ‘0’
bit 5
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REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS
(COMPARATORS 1 THROUGH 3) (CONTINUED)
bit 4
CREF: Comparator Reference Select bits (noninverting input)
1= Noninverting input connects to the internal CVREF voltage
0= Noninverting input connects to the CxINA pin
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
CCH[1:0]: Comparator Channel Select bits
11= Inverting input of the comparator connects to the internal selectable reference voltage specified
by the CVREFM[1:0] bits in the CVRCON register
10= Inverting input of the comparator connects to the CxIND pin
01= Inverting input of the comparator connects to the CxINC pin
00= Inverting input of the comparator connects to the CxINB pin
REGISTER 23-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
HSC/R-0
C3EVT
HSC/R-0
C2EVT
HSC/R-0
C1EVT
CMIDL
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
HSC/R-0
C3OUT
HSC/R-0
C2OUT
HSC/R-0
C1OUT
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CMIDL: Comparator Stop in Idle Mode bit
1= Discontinues operation of all comparators when device enters Idle mode
0= Continues operation of all enabled comparators in Idle mode
bit 14-11
bit 10
Unimplemented: Read as ‘0’
C3EVT: Comparator 3 Event Status bit (read-only)
Shows the current event status of Comparator 3 (CM3CON[9]).
C2EVT: Comparator 2 Event Status bit (read-only)
Shows the current event status of Comparator 2 (CM2CON[9]).
C1EVT: Comparator 1 Event Status bit (read-only)
Shows the current event status of Comparator 1 (CM1CON[9]).
Unimplemented: Read as ‘0’
bit 9
bit 8
bit 7-3
bit 2
C3OUT: Comparator 3 Output Status bit (read-only)
Shows the current output of Comparator 3 (CM3CON[8]).
C2OUT: Comparator 2 Output Status bit (read-only)
Shows the current output of Comparator 2 (CM2CON[8]).
C1OUT: Comparator 1 Output Status bit (read-only)
Shows the current output of Comparator 1 (CM1CON[8]).
bit 1
bit 0
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NOTES:
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24.1 Configuring the Comparator
Voltage Reference
24.0 COMPARATOR VOLTAGE
REFERENCE
The voltage reference module is controlled through the
CVRCON register (Register 24-1). The comparator
voltage reference provides two ranges of output
voltage, each with 16 distinct levels. The primary differ-
ence between the ranges is the size of the steps
selected by the CVREF Value Selection bits (CVR[4:0]),
with one range offering finer resolution.
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to “Dual Comparator Module”
(www.microchip.com/DS39710) in the
“dsPIC33/PIC24 Family Reference Man-
ual”. The information in this data sheet
supersedes the information in the FRM.
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
VREF-. The voltage source is selected by the CVRSS
bit (CVRCON[5]).
The settling time of the comparator voltage reference
must be considered when changing the CVREF output.
FIGURE 24-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
CVREF+
AVDD
CVRSS = 0
CVR[4:0]
R
CVREN
R
R
R
CVREF
CVROE
32 Steps
R
R
R
CVREF
Pin
CVRSS = 1
CVREF-
CVRSS = 0
AVSS
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REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CVREFP
CVREFM1
CVREFM0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
CVR4
R/W-0
CVR3
R/W-0
CVR2
R/W-0
CVR1
R/W-0
CVR0
CVREN
CVROE
CVRSS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-11
bit 10
Unimplemented: Read as ‘0’
CVREFP: Comparator Voltage Reference Select bit (valid only when CREF is ‘1’)
1= CVREF+ is used as a reference voltage to the comparators
0= The CVR[4:0] bits (5-bit DAC) within this module provide the reference voltage to the comparators
bit 9-8
CVREFM[1:0]: Comparator Band Gap Reference Source Select bits (valid only when CCH[1:0] = 11)
00= Band gap voltage is provided as an input to the comparators
01= Reserved
10= Reserved
11= CVREF+ is provided as an input to the comparators
bit 7
CVREN: Comparator Voltage Reference Enable bit
1= CVREF circuit is powered on
0= CVREF circuit is powered down
bit 6
CVROE: Comparator VREF Output Enable bit
1= CVREF voltage level is output on the CVREF pin
0= CVREF voltage level is disconnected from the CVREF pin
bit 5
CVRSS: Comparator VREF Source Selection bit
1= Comparator reference source, CVRSRC = CVREF+ – CVREF-
0= Comparator reference source, CVRSRC = AVDD – AVSS
bit 4-0
CVR[4:0]: Comparator VREF Value Selection bits (0 CVR[4:0] 31)
When CVRSS = 1:
CVREF = (CVREF-) + (CVR[4:0]/32) (CVREF+ – CVREF-)
When CVRSS = 0:
CVREF = (AVSS) + (CVR[4:0]/32) (AVDD – AVSS)
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An interrupt flag is set if the device experiences an
excursion past the trip point in the direction of change.
If the interrupt is enabled, the program execution will
branch to the interrupt vector address and the software
can then respond to the interrupt. The HLVDIF flag may
be set during a POR or BOR event. The firmware
should clear the flag before the application uses it for
the first time, even if the interrupt was disabled.
25.0 HIGH/LOW-VOLTAGE DETECT
(HLVD)
Note:
This data sheet summarizes the features
of the PIC24FJ128GL306 family of
devices. It is not intended to be a
comprehensive reference source. For
more information, refer to “High-Level
Integration
High/Low-Voltage Detect (HLVD)”
(www.microchip.com/DS39725) in the
“dsPIC33/PIC24
Manual”. The information in this data
sheet supersedes the information in the
FRM.
with
Programmable
The HLVD Control register (see Register 25-1)
completely controls the operation of the HLVD module.
This allows the circuitry to be “turned off” by the user
under software control, which minimizes the current
consumption for the device.
Family
Reference
The High/Low-Voltage Detect (HLVD) module is a
programmable circuit that allows the user to specify
both the device voltage trip point and the direction of
change.
FIGURE 25-1:
HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM
Externally Generated
Trip Point
VDD
VDD
HLVDL[3:0]
HLVDIN
CMPEN
VDIR
Set
HLVDIF
Band Gap
1.2V Typical
HLVDEN
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REGISTER 25-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER
R/W-0
U-0
—
R/W-0
LSIDL
U-0
—
R/W-0
VDIR
HS/HC/R-0 HS/HC/R-0 HS/HC/R-0
HLVDEN
BGVST
IRVST
HLVDEVT(2)
bit 15
bit 8
R/S-0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
HLVDL0
bit 0
CMPEN(3)
HLVDL3
HLVDL2
HLVDL1
bit 7
Legend:
HS = Hardware Settable bit
W = Writable bit
HC = Hardware Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared S = Settable bit
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
bit 15
HLVDEN: High/Low-Voltage Detect Power Enable bit
1= HLVD is enabled
0= HLVD is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
LSIDL: HLVD Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12
bit 11
Unimplemented: Read as ‘0’
VDIR: Voltage Change Direction Select bit
1= Event occurs when voltage equals or exceeds trip point (HLVDL[3:0])
0= Event occurs when voltage equals or falls below trip point (HLVDL[3:0])
bit 10
bit 9
BGVST: Band Gap Voltage Stable Flag bit
1= Indicates that the band gap voltage is stable
0= Indicates that the band gap voltage is unstable
IRVST: Internal Reference Voltage Stable Flag bit
1= Internal reference voltage is stable; the High-Voltage Detect logic generates the interrupt flag at the
specified voltage range
0= Internal reference voltage is unstable; the High-Voltage Detect logic will not generate the interrupt
flag at the specified voltage range and the HLVD interrupt should not be enabled
bit 8
bit 7
HLVDEVT: High/Low-Voltage Detect Event Status bit(2)
1= HLVD event is true during current instruction cycle
0= HLVD event is not true during current instruction cycle
CMPEN: High/Low-Voltage Detect Comparator Enable bit(3)
1= HLVD comparator is enabled
0= HLVD comparator is disabled
bit 6-4
bit 3-0
Unimplemented: Read as ‘0’
HLVDL[3:0]: High/Low-Voltage Detection Limit bits
1111= External analog input is used (input comes from the HLVDIN pin)
1110= Trip Point 1(1)
1101= Trip Point 2(1)
1100= Trip Point 3(1)
•
•
•
0100= Trip Point 11(1)
00xx= Unused
Note 1: For the actual trip point, see Section 30.0 “Electrical Characteristics”.
2: The HLVDIF flag cannot be cleared by software unless HLVDEVT = 0. The voltage must be monitored so
that the HLVD condition (as set by VDIR and HLVDL[3:0]) is not asserted.
3: CMPEN can only be written when the HLVDEN bit = 1.
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clocked whenever an instruction fetch occurs until a
count match occurs. Instructions are not fetched when
the processor is in Sleep mode.
26.0 DEADMAN TIMER (DMT)
Note:
This data sheet summarizes the features
of the PIC24FJ128GL306 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Deadman Timer (DMT)”
(www.microchip.com/DS70005155) in the
“dsPIC33/PIC24 Family Reference Man-
ual”. The information in this data sheet
supersedes the information in the FRM.
The DMT can be enabled in the Configuration fuse or
by software in the DMTCON register by setting the ON
bit. The DMT consists of a 32-bit counter with a
time-out count match value, as specified by the two
16-bit Configuration Fuse registers: FDMTCNTL and
FDMTCNTH.
A DMT is typically used in mission-critical and safety-
critical applications, where any single failure of
software functionality and sequencing must be
detected.
The primary function of the Deadman Timer (DMT) is to
interrupt the processor in the event of a software mal-
function. The DMT, which works on the system clock, is
a free-running instruction fetch timer. The DMT is
Figure 26-1 shows a block diagram of the Deadman
Timer module.
FIGURE 26-1:
DEADMAN TIMER BLOCK DIAGRAM
BAD1
Improper Sequence
BAD2
Flag
DMT Enable
(Counter) = DMT Max. Count(1)
DMT Event
Instruction Fetched Strobe(2)
System Clock
32-Bit Counter
Note 1: DMT Max. Count is controlled by the initial value of the FDMTCNTL and FDMTCNTH Configuration registers.
2: DMT window interval is controlled by the value of the FDMTIVTL and FDMTIVTH Configuration registers.
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26.1 Deadman Timer Control Registers
REGISTER 26-1: DMTCON: DEADMAN TIMER CONTROL REGISTER
R/W-0
ON(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ON: DMT Module Enable bit(1)
1= Deadman Timer module is enabled
0= Deadman Timer module is not enabled
bit 14-0
Unimplemented: Read as ‘0’
Note 1: This bit has control only when DMTDIS = 0in the FDMT register.
REGISTER 26-2: DMTPRECLR: DEADMAN TIMER PRECLEAR REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STEP1[7:0]
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
STEP1[7:0]: DMT Preclear Enable bits
01000000=
Enables the Deadman Timer preclear (STEP1)
All Other
Write Patterns = Sets the BAD1 flag; these bits are cleared when a DMT Reset event occurs.
STEP1[7:0] bits are also cleared if the STEP2[7:0] bits are loaded with the correct
value in the correct sequence.
Unimplemented: Read as ‘0’
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REGISTER 26-3: DMTCLR: DEADMAN TIMER CLEAR REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STEP2[7:0]
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
STEP2[7:0]: DMT Clear Timer bits
00001000=
Clears STEP1[7:0], STEP2[7:0] and the Deadman Timer if preceded by the correct load-
ing of the STEP1[7:0] bits in the correct sequence. The write to these bits may be verified
by reading the DMTCNTL/H register pair and observing the counter being reset.
All Other
Write Patterns = Sets the BAD2 bit; the value of STEP1[7:0] will remain unchanged and the new value
being written to STEP2[7:0] will be captured. These bits are cleared when a DMT
Reset event occurs.
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REGISTER 26-4: DMTSTAT: DEADMAN TIMER STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
HC/R-0
BAD1
HC/R-0
BAD2
HC/R-0
U-0
—
U-0
—
U-0
—
U-0
—
R-0
DMTEVENT
WINOPN
bit 0
bit 7
Legend:
HC = Hardware Clearable bit
W = Writable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
bit 15-8
bit 7
Unimplemented: Read as ‘0’
BAD1: Deadman Timer Bad STEP1[7:0] Value Detect bit
1= Incorrect STEP1[7:0] value was detected
0= Incorrect STEP1[7:0] value was not detected
bit 6
bit 5
BAD2: Deadman Timer Bad STEP2[7:0] Value Detect bit
1= Incorrect STEP2[7:0] value was detected
0= Incorrect STEP2[7:0] value was not detected
DMTEVENT: Deadman Timer Event bit
1= Deadman Timer event was detected (counter expired, or bad STEP1[7:0] or STEP2[7:0] value was
entered prior to counter increment)
0= Deadman Timer event was not detected
bit 4-1
bit 0
Unimplemented: Read as ‘0’
WINOPN: Deadman Timer Clear Window bit
1= Deadman Timer clear window is open
0= Deadman Timer clear window is not open
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REGISTER 26-5: DMTCNTL: DEADMAN TIMER COUNT REGISTER LOW
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
COUNTER[15:8]
bit 15
R-0
bit 8
bit 0
R-0
R-0
R-0
R-0
R-0
COUNTER[7:0]
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
COUNTER[15:0]: Read Current Contents of Lower DMT Counter bits
REGISTER 26-6: DMTCNTH: DEADMAN TIMER COUNT REGISTER HIGH
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
COUNTER[31:24]
bit 15
bit 8
bit 0
R-0
R-0
R-0
R-0
R-0
R-0
COUNTER[23:16]
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
COUNTER[31:16]: Read Current Contents of Higher DMT Counter bits
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REGISTER 26-7: DMTPSCNTL: DMT POST-CONFIGURE COUNT STATUS REGISTER LOW
R-y
R-y
R-y
R-y
R-y
R-y
R-y
R-y
R-y
PSCNT[15:8]
bit 15
R-y
bit 8
bit 0
R-y
R-y
R-y
PSCNT[7:0]
R-y
R-y
R-y
bit 7
Legend:
y = Value from Configuration bit on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PSCNT[15:0]: Lower DMT Instruction Count Value Configuration Status bits
This is always the value of the FDMTCNTL Configuration register.
REGISTER 26-8: DMTPSCNTH: DMT POST-CONFIGURE COUNT STATUS REGISTER HIGH
R-y
bit 15
R-y
R-y
R-y
R-y
R-y
R-y
R-y
R-y
R-y
PSCNT[31:24]
bit 8
bit 0
R-y
R-y
R-y
R-y
R-y
R-y
PSCNT[23:16]
bit 7
Legend:
y = Value from Configuration bit on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PSCNT[31:16]: Higher DMT Instruction Count Value Configuration Status bits
This is always the value of the FDMTCNTH Configuration register.
DS30010198B-page 304
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PIC24FJ128GL306 FAMILY
REGISTER 26-9: DMTPSINTVL: DMT POST-CONFIGURE INTERVAL STATUS REGISTER LOW
R-y
bit 15
R-y
R-y
R-y
R-y
R-y
R-y
R-y
R-y
PSINTV[15:8]
bit 8
bit 0
R-y
R-y
R-y
PSINTV[7:0]
R-y
R-y
R-y
R-y
bit 7
Legend:
y = Value from Configuration bit on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PSINTV[15:0]: Lower DMT Window Interval Configuration Status bits
This is always the value of the FDMTIVTL Configuration register.
REGISTER 26-10: DMTPSINTVH: DMT POST-CONFIGURE INTERVAL STATUS REGISTER HIGH
R-y
R-y
R-y
R-y
R-y
R-y
R-y
R-y
PSINTV[31:24]
bit 15
bit 8
bit 0
R-y
R-y
R-y
R-y
R-y
R-y
R-y
R-y
PSINTV[23:16]
bit 7
Legend:
y = Value from Configuration bit on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PSINTV[15:0]: Higher DMT Window Interval Configuration Status bits
This is always the value of the FDMTIVTH Configuration register.
2019-2020 Microchip Technology Inc.
DS30010198B-page 305
PIC24FJ128GL306 FAMILY
REGISTER 26-11: DMTHOLDREG: DMT HOLD REGISTER(1)
R-0
bit 15
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
UPRCNT[15:8]
bit 8
bit 0
R-0
R-0
R-0
R-0
UPRCNT[7:0]
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
UPRCNT[15:0]: DMTCNTH Register Value When DMTCNTL/DMTCNTH were Last Read bits
Note 1: The DMTHOLDREG register is initialized to ‘0’ on Reset, and is only loaded when the DMTCNTL and
DMTCNTH registers are read.
DS30010198B-page 306
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PIC24FJ128GL306 FAMILY
27.1 Configuration Bits
27.0 SPECIAL FEATURES
The Configuration bits are stored in the last page loca-
tion of implemented program memory. These bits can be
set or cleared to select various device configurations.
There are two types of Configuration bits: system oper-
ation bits and code-protect bits. The system operation
bits determine the power-on settings for system-level
components, such as the oscillator and the Watchdog
Timer. The code-protect bits prevent program memory
from being read and written.
Note:
This data sheet summarizes the features of
the PIC24FJ128GL306 family of devices. It
is not intended to be a comprehensive
reference source. For more information,
refer to the following sections of the
“dsPIC33/PIC24 Family Reference Man-
ual”. The information in this data sheet
supersedes the information in the FRM.
•
“Watchdog Timer (WDT)”
(www.microchip.com/DS39697)
27.1.1
CONSIDERATIONS FOR
CONFIGURING PIC24FJ128GL306
FAMILY DEVICES
• “High-Level Device Integration”
(www.microchip.com/DS39719)
• “Programming and Diagnostics”
In PIC24FJ128GL306 family devices, the Configuration
bytes are implemented as volatile memory. This means
that configuration data must be programmed each time
the device is powered up. Configuration data are stored
in the three words at the top of the on-chip program
memory space, known as the Flash Configuration
Words. Their specific locations are shown in Table 27-1.
The configuration data are automatically loaded from the
Flash Configuration Words to the proper Configuration
registers during device Resets.
(www.microchip.com/DS39716)
PIC24FJ128GL306 family devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
Note:
Configuration data are reloaded on all
types of device Resets.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
The upper byte of all Flash Configuration Words in
program memory should always be ‘00000000’. This
makes them appear to be NOP instructions in the
remote event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘0’s to these
locations has no effect on device operation.
2019-2020 Microchip Technology Inc.
DS30010198B-page 307
PIC24FJ128GL306 FAMILY
TABLE 27-1: CONFIGURATION WORD ADDRESSES
Configuration Register
PIC24FJ128GL30X
PIC24FJ64GL30X
FSEC
0x015F00
0x015F10
0x015F14
0x015F18
0x015F1C
0x015F20
0x015F24
0x015F28
0x015F2C
0x015F30
0x015F34
0x015F38
0x015F3C
0x015F40
0x00AF00
0x00AF10
0x00AF14
0x00AF18
0x00AF1C
0x00AF20
0x00AF24
0x00AF28
0x00AF2C
0x00AF30
0x00AF34
0x00AF38
0x00AF3C
0x00AF40
FBSLIM
FSIGN
FOSCSEL
FOSC
FWDT
FPOR
FICD
FDMTIVTL
FDMTIVTH
FDMTCNTL
FDMTCNTH
FDMT
FDEVOPT1
DS30010198B-page 308
2019-2020 Microchip Technology Inc.
TABLE 27-2: CONFIGURATION REGISTER MAP
Register
Name
Bits
23-16
Bit 15
Bit 14 Bit 13 Bit 12 Bit 11
Bit 10 Bit 9 Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FSEC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AIVTDIS
—
—
—
—
—
—
—
—
—
—
—
—
CSS[2:0]
CWRP
GSS[1:0]
GWRP
—
BSEN
BSS[1:0]
BWRP
FBSLIM
FSIGN
BSLIM[12:0]
—
(2)
r
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(2)
(2)
FOSCSEL
FOSC
—
—
—
—
—
—
r
r
IESO
PLLMODE[3:0]
FNOSC[2:0]
—
WDTCMX
—
—
—
FCKSM[1:0]
FWDTEN[1:0]
IOL1WAY PLLSS SOSCSEL OSCIOFNC
POSCMD[1:0]
WDTPS[3:0]
FWDT
WDTCLK[1:0]
WDTWIN[1:0] WINDIS
FWPSA
—
FPOR
—
—
—
—
—
—
—
—
—
(1)
—
—
—
DNVPEN
—
LPCFG
—
BOREN[1:0]
ICS[1:0]
FICD
—
r
JTAGEN
—
FDMTIVTL
FDMTIVTH
FDMTCNTL
FDMTCNTH
FDMT
DMTIVT[15:0]
DMTIVT[31:16]
DMTCNT[15:0]
DMTCNT[31:16]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMTDIS
FDEVOPT1
SMB3EN
ALTI2C1 SOSCHP TMPRPIN ALTCMPI
—
Legend: — = unimplemented, read as ‘1’.
Note 1: Bit is reserved, maintain as ‘1’.
2: Bit is reserved, maintain as ‘0’.
PIC24FJ128GL306 FAMILY
REGISTER 27-1: FSEC CONFIGURATION REGISTER
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
R/PO-1
U-1
—
U-1
—
U-1
—
R/PO-1
CSS2
R/PO-1
CSS1
R/PO-1
CSS0
R/PO-1
CWRP
AIVTDIS
bit 15
bit 8
R/PO-1
GSS1
R/PO-1
GSS0
R/PO-1
GWRP
U-1
—
R/PO-1
BSEN
R/PO-1
BSS1
R/PO-1
BSS0
R/PO-1
BWRP
bit 7
bit 0
Legend:
PO = Program Once bit
W = Writable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
bit 23-16
bit 15
Unimplemented: Read as ‘1’
AIVTDIS: Alternate Interrupt Vector Table Disable bit
1= Disables AIVT; AIVTEN bit (INTCON2[8]) is not available
0= Enables AIVT; AIVTEN bit (INTCON2[8]) is available
bit 14-12
bit 11-9
Unimplemented: Read as ‘1’
CSS[2:0]: Configuration Segment (CS) Code Protection Level bits
111= No protection (other than CWRP)
110= Standard security
10x= Enhanced security
0xx= High security
bit 8
CWRP: Configuration Segment Program Write Protection bit
1= Configuration Segment is not write-protected
0= Configuration Segment is write-protected
bit 7-6
GSS[1:0]: General Segment (GS) Code Protection Level bits
11= No protection (other than GWRP)
10= Standard security
0x= High security
bit 5
GWRP: General Segment Program Write Protection bit
1= General Segment is not write-protected
0= General Segment is write-protected
bit 4
bit 3
Unimplemented: Read as ‘1’
BSEN: Boot Segment (BS) Control bit
1= No Boot Segment is enabled
0= Boot Segment size is determined by BSLIM[12:0]
bit 2-1
bit 0
BSS[1:0]: Boot Segment Code Protection Level bits
11= No protection (other than BWRP)
10= Standard security
0x= High security
BWRP: Boot Segment Program Write Protection bit
1= Boot Segment can be written
0= Boot Segment is write-protected
DS30010198B-page 310
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PIC24FJ128GL306 FAMILY
REGISTER 27-2: FBSLIM CONFIGURATION REGISTER
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
U-1
—
U-1
—
U-1
—
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
BSLIM[12:8]
bit 15
R/PO-1
bit 7
bit 8
R/PO-1
bit 0
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
BSLIM[7:0]
Legend:
PO = Program Once bit
W = Writable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
bit 23-13
bit 12-0
Unimplemented: Read as ‘1’
BSLIM[12:0]: Active Boot Segment Code Flash Page Address Limit (inverted) bits
This bit field contains the last active Boot Segment Page + 1 (i.e., first page address of GS). The value
is stored as an inverted page address, such that programming additional ‘0’s can only increase the size
of BS. If the BSLIM[12:0] bits are set to all ‘1’s (unprogrammed default), the active Boot Segment size
is zero.
2019-2020 Microchip Technology Inc.
DS30010198B-page 311
PIC24FJ128GL306 FAMILY
REGISTER 27-3: FSIGN CONFIGURATION REGISTER
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
r-0
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 15
bit 8
bit 0
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 7
Legend:
PO = Program Once bit
W = Writable bit
r = Reserved bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 23-16
bit 15
Unimplemented: Read as ‘1’
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘1’
bit 14-0
\
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PIC24FJ128GL306 FAMILY
REGISTER 27-4: FOSCSEL CONFIGURATION REGISTER
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
r-0
—
r-0
—
bit 15
bit 8
R/PO-1
IESO
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
PLLMODE3 PLLMODE2 PLLMODE1 PLLMODE0
FNOSC2
FNOSC1
FNOSC0
bit 7
bit 0
Legend:
PO = Program Once bit
W = Writable bit
r = Reserved bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
bit 23-10
bit 9-8
bit 7
Unimplemented: Read as ‘1’
Reserved: Maintain as ‘0’
IESO: Two-Speed Oscillator Start-up Enable bit
1= Starts up the device with FRC, then automatically switches to the user-selected oscillator when ready
0= Starts up the device with the user-selected oscillator source
bit 6-3
PLLMODE[3:0]: Frequency Multiplier Select bits
1111= No PLL is used (PLLEN bit is unavailable)
1110= 8x PLL is selected
1101= 6x PLL is selected
1100= 4x PLL is selected
0111= 96 MHz PLL is selected (Input Frequency = 48 MHz)
0110= 96 MHz PLL is selected (Input Frequency = 32 MHz)
0101= 96 MHz PLL is selected (Input Frequency = 24 MHz)
0100= 96 MHz PLL is selected (Input Frequency = 20 MHz)
0011= 96 MHz PLL is selected (Input Frequency = 16 MHz)
0010= 96 MHz PLL is selected (Input Frequency = 12 MHz)
0001= 96 MHz PLL is selected (Input Frequency = 8 MHz)
0000= 96 MHz PLL is selected (Input Frequency = 4 MHz)
bit 2-0
FNOSC[2:0]: Oscillator Selection bits
111= Oscillator with Frequency Divider (OSCFDIV)
110= Reserved
101= Low-Power RC Oscillator (LPRC)
100= Secondary Oscillator (SOSC)
011= Primary Oscillator with PLL (XTPLL, HSPLL, ECPLL)
010= Primary Oscillator (XT, HS, EC)
001= Fast RC Oscillator with PLL (FRCPLL)
000= Fast RC Oscillator (FRC)
2019-2020 Microchip Technology Inc.
DS30010198B-page 313
PIC24FJ128GL306 FAMILY
REGISTER 27-5: FOSC CONFIGURATION REGISTER
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 15
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
PLLSS
R/PO-1
R/PO-1
R/PO-1
R/PO-1
POSCMD0
bit 0
FCKSM1
FCKSM0
IOL1WAY
SOSCSEL
OSCIOFNC POSCMD1
bit 7
Legend:
PO = Program Once bit
W = Writable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
bit 23-8
bit 7-6
Unimplemented: Read as ‘1’
FCKSM[1:0]: Clock Switching and Monitor Selection bits
1x= Clock switching and the Fail-Safe Clock Monitor are disabled
01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00= Clock switching and the Fail-Safe Clock Monitor are enabled
bit 5
bit 4
IOL1WAY: Peripheral Pin Select Configuration bit
1= The IOLOCK bit can be set only once (with unlock sequence).
0= The IOLOCK bit can be set and cleared as needed (with unlock sequence)
PLLSS: PLL Secondary Selection Configuration bit
This Configuration bit only takes effect when the PLL is NOT being used by the system (i.e., not
selected as part of the system clock source). Used to generate an independent clock out of REFO.
1= PLL is fed by the Primary Oscillator
0= PLL is fed by the on-chip Fast RC (FRC) Oscillator
bit 3
bit 2
SOSCSEL: SOSC Selection Configuration bit
1= Crystal (SOSCI/SOSCO) mode
0= Digital (SCLKI) Externally Supplied Clock mode
OSCIOFNC: CLKO Enable Configuration bit
1= CLKO output signal is active on the OSCO pin (when the Primary Oscillator is disabled or configured
for EC mode)
0= CLKO output is disabled
bit 1-0
POSCMD[1:0]: Primary Oscillator Configuration bits
11= Primary Oscillator mode is disabled
10= HS Oscillator mode is selected (10 MHz-32 MHz)
01= XT Oscillator mode is selected (1.5 MHz-10 MHz)
00= External Clock mode is selected
DS30010198B-page 314
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PIC24FJ128GL306 FAMILY
REGISTER 27-6: FWDT CONFIGURATION REGISTER
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
U-1
—
R/PO-1
R/PO-1
U-1
—
R/PO-1
U-1
—
R/PO-1
R/PO-1
WDTCLK1
WDTCLK0
WDTCMX
WDTWIN1
WDTWIN0
bit 15
bit 8
R/PO-1
WINDIS
R/PO-1
R/PO-1
R/PO-1
FWPSA
R/PO-1
R/PO-1
R/PO-1
R/PO-1
FWDTEN1
FWDTEN0
WDTPS3
WDTPS2
WDTPS1
WDTPS0
bit 7
bit 0
Legend:
PO = Program Once bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 23-15
bit 14-13
Unimplemented: Read as ‘1’
WDTCLK[1:0]: Watchdog Timer Clock Select bits (when WDTCMX = 1)
11= Always uses LPRC
10= Uses FRC when WINDIS = 0, system clock is not LPRC and device is not in Sleep; otherwise,
uses LPRC
01= Always uses SOSC
00= Uses peripheral clock when system clock is not LPRC and device is not in Sleep; otherwise, uses
LPRC
bit 12
bit 11
Unimplemented: Read as ‘1’
WDTCMX: WDT Clock MUX Control bit
1= Enables WDT clock MUX, WDT clock is selected by WDTCLK[1:0]
0= WDT clock is LPRC
bit 10
Unimplemented: Read as ‘1’
bit 9-8
WDTWIN[1:0]: Watchdog Timer Window Width bits
11= WDT window is 25% of the WDT period
10= WDT window is 37.5% of the WDT period
01= WDT window is 50% of the WDT period
00= WDT window is 75% of the WDT period
bit 7
WINDIS: Windowed Watchdog Timer Disable bit
1= Windowed WDT is disabled
0= Windowed WDT is enabled
bit 6-5
FWDTEN[1:0]: Watchdog Timer Enable bits
11= WDT is enabled
10= WDT is disabled (control is placed on the SWDTEN bit)
01= WDT is enabled only while device is active and disabled in Sleep; SWDTEN bit is disabled
00= WDT and SWDTEN are disabled
bit 4
FWPSA: Watchdog Timer Prescaler bit
1= WDT prescaler ratio of 1:128
0= WDT prescaler ratio of 1:32
2019-2020 Microchip Technology Inc.
DS30010198B-page 315
PIC24FJ128GL306 FAMILY
REGISTER 27-6: FWDT CONFIGURATION REGISTER (CONTINUED)
bit 3-0
WDTPS[3:0]: Watchdog Timer Postscale Select bits
1111= 1:32,768
1110= 1:16,384
1101= 1:8,192
1100= 1:4,096
1011= 1:2,048
1010= 1:1,024
1001= 1:512
1000= 1:256
0111= 1:128
0110= 1:64
0101= 1:32
0100= 1:16
0011= 1:8
0010= 1:4
0001= 1:2
0000= 1:1
DS30010198B-page 316
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PIC24FJ128GL306 FAMILY
REGISTER 27-7: FPOR CONFIGURATION REGISTER
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 15
bit 8
U-1
—
U-1
—
U-1
—
U-1
—
R/PO-1
R/PO-1
LPCFG
R/PO-1
R/PO-1
DNVPEN
BOREN1
BOREN0
bit 7
bit 0
Legend:
PO = Program Once bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 23-4
bit 3
Unimplemented: Read as ‘1’
DNVPEN: Downside Voltage Protection Enable bit
1= Downside protection is enabled when BOR is inactive
0= Downside protection is disabled when BOR is inactive
bit 2
LPCFG: Low-Power Regulator Control bit
1= Retention feature is not available
0= Retention feature is available and controlled by RETEN during Sleep
bit 1-0
BOREN[1:0]: Brown-out Reset Enable bits
11= Brown-out Reset is enabled in hardware; SBOREN bit is disabled
10= Brown-out Reset is enabled only while device is active and is disabled in Sleep; SBOREN bit is
disabled
01= Brown-out Reset is controlled with the SBOREN bit setting
00= Brown-out Reset is disabled in hardware; SBOREN bit is disabled
2019-2020 Microchip Technology Inc.
DS30010198B-page 317
PIC24FJ128GL306 FAMILY
REGISTER 27-8: FICD CONFIGURATION REGISTER
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 15
bit 8
r-1
—
U-1
—
R/PO-0
U-1
—
U-1
—
U-1
—
R/PO-1
ICS1
R/PO-1
ICS0
JTAGEN
bit 7
bit 0
Legend:
PO = Program Once bit
W = Writable bit
r = Reserved bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 23-8
bit 7
Unimplemented: Read as ‘1’
Reserved: Maintain as ‘1’
bit 6
Unimplemented: Read as ‘1’
JTAGEN: JTAG Port Enable bit
bit 5
1= JTAG port is enabled
0= JTAG port is disabled
bit 4-2
bit 1-0
Unimplemented: Read as ‘1’
ICS[1:0]: ICD Communication Channel Select bits
11= Communicates on PGC1/PGD1
10= Communicates on PGC2/PGD2
01= Communicates on PGC3/PGD3
00= Reserved; do not use
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REGISTER 27-9: FDMTIVTL CONFIGURATION REGISTER
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
DMTIVT[15:8]
bit 15
R/PO-1
bit 7
bit 8
R/PO-1
bit 0
R/PO-1
R/PO-1
DMTIVT[7:0]
Legend:
PO = Program Once bit
W = Writable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
bit 23-16
bit 15-0
Unimplemented: Read as ‘1’
DMTIVT[15:0]: DMT Window Interval Lower 16 bits
REGISTER 27-10: FDMTIVTH CONFIGURATION REGISTER
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
R/PO-1
bit 15
bit 16
R/PO-1
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
DMTIVT[31:24]
R/PO-1
bit 7
R/PO-1
R/PO-1
R/PO-1
bit 0
DMTIVT[23:16]
Legend:
PO = Program Once bit
W = Writable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
bit 23-16
bit 15-0
Unimplemented: Read as ‘1’
DMTIVT[31:16]: DMT Window Interval Higher 16 bits
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REGISTER 27-11: FDMTCNTL CONFIGURATION REGISTER
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
DMTCNT[15:8]
bit 15
R/PO-1
bit 7
bit 8
R/PO-1
bit 0
R/PO-1
R/PO-1
DMTCNT[7:0]
Legend:
PO = Program Once bit
W = Writable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
bit 23-16
bit 15-0
Unimplemented: Read as ‘1’
DMTCNT[15:0]: DMT Instruction Count Time-out Value Lower 16 bits
REGISTER 27-12: FDMTCNTH CONFIGURATION REGISTER
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
R/PO-1
bit 15
bit 16
R/PO-1
bit 8
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
DMTCNT[31:24]
R/PO-1
bit 7
R/PO-1
R/PO-1
R/PO-1
bit 0
DMTCNT[23:16]
Legend:
PO = Program Once bit
W = Writable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
bit 23-16
bit 15-0
Unimplemented: Read as ‘1’
DMTIVT[31:16]: DMT Instruction Count Time-out Value Higher 16 bits
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REGISTER 27-13: FDMT CONFIGURATION REGISTER
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 15
bit 8
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
R/PO-1
DMTDIS
bit 7
bit 0
Legend:
PO = Program Once bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 23-1
bit 0
Unimplemented: Read as ‘1’
DMTDIS: DMT Disable bit
1= DMT is disabled
0= DMT is enabled
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REGISTER 27-14: FDEVOPT1 CONFIGURATION REGISTER
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
bit 23
bit 16
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
R/PO-1
SMB3EN(2)
U-1
—
U-1
—
bit 15
bit 8
bit 0
U-1
—
U-1
—
U-1
—
R/PO-1
R/PO-1
R/PO-1
R/PO-1
U-1
—
ALTI2C1
SOSCHP
TMPRPIN
ALTCMPI
bit 7
Legend:
PO = Program Once bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 23-11
bit 10
Unimplemented: Read as ‘1’
SMB3EN: SMBus 3.0 Levels Enable bit(2)
1= SMBus 3.0 input levels
0= Normal I2C input levels
bit 9-5
bit 4
Unimplemented: Read as ‘1’
ALTI2C1: Alternate I2C1 bit
1= SDA1 and SCL1 on RG2 and RG3
0= ASDA1 and ASCL1 on RB5 and RB4
bit 3
SOSCHP: SOSC High-Power Enable bit (valid only when SOSCSEL = 1)
1= SOSC High-Power mode is enabled
0= SOSC Low-Power mode is enabled (see Section 9.10.3 “Low-Power SOSC Operation” for more
information)
bit 2
bit 1
bit 0
TMPRPIN: Tamper Pin Enable bit
1= TMPRN pin function is disabled
0= TMPRN pin function is enabled
ALTCMPI: Alternate Comparator Input Enable bit
1= C2INC and C3INC are on their standard pin locations
0= C2INC and C3INC are on RG7(1)
Unimplemented: Read as ‘1’
Note 1: RG7 is used for multiple functions, but only one use case is allowable.
2: SMBus mode is enabled by the SMEN bit (I2CxCONL[8]).
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TABLE 27-3: PIC24FJ CORE DEVICE ID REGISTERS
Bit
Address
Name
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
FF0000h
FF0002h
DEVID
DEVREV
FAMID[7:0]
DEV[7:0]
—
REV[3:0]
TABLE 27-4: DEVICE ID BIT FIELD
DESCRIPTIONS
27.2 Unique Device Identifier (UDID)
All PIC24FJ128GL306 family devices are individually
encoded during final manufacturing with a Unique
Device Identifier, or UDID. The UDID cannot be erased
by a bulk erase command or any other user-accessible
means. This feature allows for manufacturing
traceability of Microchip Technology devices in applica-
tions where this is a requirement. It may also be used
by the application manufacturer for any number of
things that may require unique identification, such as:
Bit Field
Register
Description
FAMID[7:0] DEVID
Encodes the family ID of
the device; FAMID = 0x22.
DEV[7:0]
REV[3:0]
DEVID
Encodes the individual ID
of the device.
DEVREV Encodes the sequential
(numerical) revision
identifier of the device.
• Tracking the device
• Unique serial number
• Unique security key
TABLE 27-5: PIC24FJ128GL306 FAMILY
DEVICE IDs
The UDID comprises five 24-bit program words. When
taken together, these fields form a unique 120-bit
identifier.
Device
DEVID
PIC24FJ128GL306
PIC24FJ64GL306
PIC24FJ128GL305
PIC24FJ64GL305
PIC24FJ128GL303
PIC24FJ64GL303
PIC24FJ128GL302
PIC24FJ64GL302
0x220E
0x2206
0x220C
0x2204
0x220A
0x2202
0x2208
0x2200
The UDID is stored in five read-only locations, located
between 0x801600 and 0x801608 in the device config-
uration space. Table 27-6 lists the addresses of the
Identifier Words and shows their contents.
TABLE 27-6: UDID ADDRESSES
UDID
Address
Description
UDID1
UDID2
UDID3
UDID4
UDID5
0x801600
0x801602
0x801604
0x801606
0x801608
UDID Word 1
UDID Word 2
UDID Word 3
UDID Word 4
UDID Word 5
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27.3.1
ON-CHIP REGULATOR AND POR
27.3
On-Chip Voltage Regulator
The voltage regulator takes approximately 10 µs for it
to generate output. During this time, designated as
TVREG, code execution is disabled. TVREG is applied
every time the device resumes operation after any
power-down, including Sleep mode. TVREG is deter-
mined by the status of the VREGS bit (RCON[8]) and
the WDTWIN[1:0] Configuration bits (FWDT[9:8]).
Refer to Section 30.0 “Electrical Characteristics” for
more information on TVREG.
All PIC24FJ128GL306 family devices power their core
digital logic at a nominal 1.8V. This may create an issue
for designs that are required to operate at a higher
typical voltage, such as 3.3V. To simplify system
design, all devices in the PIC24FJ128GL306 family
incorporate an on-chip regulator that allows the device
to run its core logic from VDD.
This regulator is always enabled. It provides a constant
voltage (1.8V nominal) to the digital core logic, from a
VDD of about 2.1V, all the way up to the device’s
VDDMAX. It does not have the capability to boost VDD
levels. In order to prevent brown-out conditions when
the voltage drops too low for the regulator, the Brown-
out Reset occurs. Then, the regulator output follows
VDD with a typical voltage drop of 300 mV.
Note:
For more information, see Section 30.0
“Electrical Characteristics”. The infor-
mation in this data sheet supersedes the
information in the FRM.
27.3.2
VOLTAGE REGULATOR STANDBY
MODE
A low-ESR capacitor (such as ceramic) must be
connected to the VCAP pin (Figure 27-1). This helps to
maintain the stability of the regulator. The recommended
value for the filter capacitor (CEFC) is provided in
Section 30.1 “DC Characteristics”.
The on-chip regulator always consumes a small incre-
mental amount of current over IDD/IPD, including when
the device is in Sleep mode, even though the core
digital logic does not require power. To provide addi-
tional savings in applications where power resources
are critical, the regulator can be made to enter Standby
mode, on its own, whenever the device goes into Sleep
mode. This feature is controlled by the VREGS bit
(RCON[8]). Clearing the VREGS bit enables the
Standby mode. When waking up from Standby mode,
the regulator needs to wait for TVREG to expire before
wake-up.
FIGURE 27-1:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
3.3V(1)
PIC24FJXXXGL30X
VDD
27.3.3
LOW-VOLTAGE RETENTION
REGULATOR
VCAP
VSS
CEFC
(10 F typ.)
When in Sleep mode, PIC24FJ128GL306 family
devices may use a separate low-power, low-voltage
retention regulator to power critical circuits. This regu-
lator, which operates at 1.2V nominal, maintains power
to data RAM and the RTCC, while all other core digital
logic is powered down. The low-voltage retention regu-
lator is described in more detail in Section 10.2.4
“Low-Voltage Retention Regulator”.
Note 1: This is a typical operating voltage. Refer to
Section 30.0 “Electrical Characteristics”
for the full operating ranges of VDD.
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The WDT Time-out Flag bit, WDTO (RCON[4]), is not
automatically cleared following a WDT time-out. To
detect subsequent WDT events, the flag must be
cleared in software.
27.4 Watchdog Timer (WDT)
For PIC24FJ128GL306 family devices, the WDT is driven
by the LPRC Oscillator, the Secondary Oscillator (SOSC)
or the system timer. When the device is in Sleep mode,
the LPRC Oscillator will be used. When the WDT is
enabled, the clock source is also enabled.
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 32 kHz input, the prescaler yields a nominal
WDT Time-out (TWDT) period of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
27.4.1
WINDOWED OPERATION
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDTinstruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPS[3:0] Config-
uration bits (FWDT[3:0]), which allow the selection of a
total of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler time-out periods, ranges from
1 ms to 131 seconds can be achieved.
Windowed WDT mode is enabled by programming the
WINDIS Configuration bit (FWDT[7]) to ‘0’.
27.4.2
CONTROL REGISTER
The WDT is enabled or disabled by the FWDTEN[1:0]
Configuration bits (FWDT[6:5]). When the Configuration
bits, FWDTEN[1:0] = 11, the WDT is always enabled.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSCx bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
The WDT can be optionally controlled in software when
the Configuration bits, FWDTEN[1:0] = 10. When
FWDTEN[1:0] = 00, the Watchdog Timer is always dis-
abled. The WDT is enabled in software by setting the
SWDTEN control bit (RCON[5]). The SWDTEN control
bit is cleared on any device Reset. The software WDT
option allows the user to enable the WDT for critical
code segments and disable the WDT during non-critical
code segments for maximum power savings.
• When a PWRSAVinstruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDTinstruction during normal execution
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The corresponding SLEEP or IDLE
(RCON[3:2]) bits will need to be cleared in software
after the device wakes up.
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FIGURE 27-2:
WDT BLOCK DIAGRAM
Wake from
Sleep
SWDTEN
LPRC Control
FWPSA
FWDTEN[1:0]
WDTCLK[1:0]
WDTPS[3:0]
WDT Overflow
Reset
Prescaler
WDT
Counter
Postscaler
1:1 to 1:32.768
(5-bit/7-bit)
32 kHz
SOSC
1 ms/4 ms
FRC
Peripheral Clock
All Device Resets
Transition to New
Clock Source
LPRC
Exit Sleep or
Idle Mode
WINDIS
CLRWDTInstr.
PWRSAVInstr.
System Clock (LRPC)
Sleep or Idle Mode
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27.5 Program Verification and
Code Protection
27.8 Customer OTP Memory
PIC24FJ128GL306 family devices provide 256 bytes of
One-Time-Programmable (OTP) memory, located at
addresses, 801700h through 8017FEh. This memory
can be used for persistent storage of application-specific
information that will not be erased by reprogramming the
device. This includes many types of information, such as
(but not limited to):
PIC24FJ128GL306 family devices offer basic
implementation of CodeGuard™ Security that supports
General Segment (GS) security and Boot Segment
(BS) security. This feature helps protect individual
intellectual property.
Note:
For more information on usage, con-
figuration and operation, refer to
“CodeGuard™ Intermediate Security”
(www.microchip.com/DS70005182) in the
• Application checksums
• Code revision information
• Product information
“dsPIC33/PIC24
Manual”.
Family
Reference
• Serial numbers
• System manufacturing dates
• Manufacturing lot numbers
27.6 JTAG Interface
Customer OTP memory may be programmed in any
mode, including user RTSP mode, but it cannot be
erased. Data are not cleared by a chip erase.
PIC24FJ128GL306 family devices implement a JTAG
interface, which supports boundary scan device
testing.
Note:
Do not write the OTP memory more than
once. Writing to the OTP memory more
than once may result in an ECC Double-Bit
Error (ECCDBE).
27.7
In-Circuit Serial Programming™
PIC24FJ128GL306 family microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock (PGCx) and
data (PGDx), and three other lines for power (VDD),
ground (VSS) and MCLR. This allows customers to man-
ufacture boards with unprogrammed devices and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
27.9 In-Circuit Debugger
This function allows simple debugging functions when
used with MPLAB® X IDE. Debugging functionality is
controlled through the PGCx (Emulation/Debug Clock)
and PGDx (Emulation/Debug Data) pins.
To use the in-circuit debugger function of the device,
the design must implement ICSP™ connections to
MCLR, VDD, VSS and the PGCx/PGDx pin pair, desig-
nated by the ICS[1:0] Configuration bits. In addition,
when the feature is enabled, some of the resources are
not available for general use. These resources include
the first 80 bytes of data RAM and two I/O pins.
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NOTES:
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The literal instructions that involve data movement may
use some of the following operands:
28.0 INSTRUCTION SET SUMMARY
Note:
This chapter is a brief summary of the
PIC24F Instruction Set Architecture (ISA)
and is not intended to be a comprehensive
reference source.
• A literal value to be loaded into a W register or file
register (specified by the value of ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
The PIC24F instruction set adds many enhancements
to the previous PIC® MCU instruction sets, while main-
taining an easy migration from previous PIC MCU
instruction sets. Most instructions are a single program
memory word. Only three instructions require two
program memory locations.
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register, ‘Wb’,
without any address modifier
• The second source operand, which is a literal
value
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction. The instruction set is
highly orthogonal and is grouped into four basic
categories:
• The destination of the result (only if not the same
as the first source operand), which is typically a
register, ‘Wd’, with or without an address modifier
The control instructions may use some of the following
operands:
• A program memory address
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
• The mode of the Table Read and Table Write
instructions
All instructions are a single word, except for certain
double-word instructions, which were made double-
word instructions so that all the required information is
available in these 48 bits. In the second word, the
8 MSbs are ‘0’s. If this second word is executed as an
instruction (by itself), it will execute as a NOP.
• Control operations
Table 28-1 shows the general symbols used in
describing the instructions. The PIC24F instruction set
summary in Table 28-2 lists all the instructions, along
with the status flags affected by each instruction.
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Program Counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (uncondi-
tional/computed branch), indirect CALL/GOTO, all
Table Reads and Table Writes, and RETURN/RETFIE
instructions, which are single-word instructions but take
two or three cycles.
• The first source operand, which is typically a
register, ‘Wb’, without any address modifier
• The second source operand, which is typically a
register, ‘Ws’, with or without an address modifier
• The destination of the result, which is typically a
register, ‘Wd’, with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
Certain instructions that involve skipping over the sub-
sequent instruction require either two or three cycles if
the skip is performed, depending on whether the
instruction being skipped is a single-word or two-word
instruction. Moreover, double-word moves require two
cycles. The double-word instructions execute in two
instruction cycles.
• The file register specified by the value, ‘f’
• The destination, which could either be the file
register, ‘f’, or the W0 register, which is denoted
as ‘WREG’
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register
(specified by a literal value or indirectly by the
contents of register, ‘Wb’)
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TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
(text)
[text]
{ }
Means literal defined by “text”
Means “content of text”
Means “the location addressed by text”
Optional field or operation
[n:m]
.b
Register bit field
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
bit4
4-bit Bit Selection field (used in word addressed instructions) {0...15}
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Absolute address, label or expression (resolved by the linker)
File register address {0000h...1FFFh}
1-bit unsigned literal {0,1}
C, DC, N, OV, Z
Expr
f
lit1
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
lit14
lit16
lit23
None
PC
10-bit unsigned literal {0...255} for Byte mode, {0...1023} for Word mode
14-bit unsigned literal {0...16383}
16-bit unsigned literal {0...65535}
23-bit unsigned literal {0...8388607}; LSb must be ‘0’
Field does not require an entry, may be blank
Program Counter
Slit10
Slit16
Slit6
Wb
10-bit signed literal {-512...511}
16-bit signed literal {-32768...32767}
6-bit signed literal {-16...16}
Base W register {W0..W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Wn
Dividend, Divisor Working register pair (direct addressing)
One of 16 Working registers {W0..W15}
Wnd
Wns
One of 16 destination Working registers {W0..W15}
One of 16 source Working registers {W0..W15}
WREG
Ws
W0 (Working register used in file register instructions)
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wso
DS30010198B-page 330
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 28-2: INSTRUCTION SET OVERVIEW
Assembly
# of
# of
Status Flags
Affected
Assembly Syntax
Mnemonic
Description
Words Cycles
ADD
ADDC
AND
ASR
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
ADDC
AND
AND
AND
AND
AND
ASR
ASR
ASR
ASR
ASR
BCLR
BCLR
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BSET
BSET
BSW.C
BSW.Z
BTG
BTG
BTSC
f
f = f + WREG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
N, Z
f,WREG
WREG = f + WREG
1
1
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
Wd = lit10 + Wd
Wd = Wb + Ws
1
Wd = Wb + lit5
1
f = f + WREG + (C)
1
f,WREG
WREG = f + WREG + (C)
Wd = lit10 + Wd + (C)
Wd = Wb + Ws + (C)
Wd = Wb + lit5 + (C)
f = f .AND. WREG
1
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
1
1
1
f,WREG
WREG = f .AND. WREG
Wd = lit10 .AND. Wd
Wd = Wb .AND. Ws
1
N, Z
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
N, Z
1
N, Z
Wd = Wb .AND. lit5
1
N, Z
f = Arithmetic Right Shift f
WREG = Arithmetic Right Shift f
Wd = Arithmetic Right Shift Ws
Wnd = Arithmetic Right Shift Wb by Wns
Wnd = Arithmetic Right Shift Wb by lit5
Bit Clear f
1
C, N, OV, Z
C, N, OV, Z
C, N, OV, Z
N, Z
f,WREG
1
Ws,Wd
1
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,#bit4
Ws,#bit4
C,Expr
1
1
N, Z
BCLR
BRA
1
None
Bit Clear Ws
1
None
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
None
GE,Expr
GEU,Expr
GT,Expr
GTU,Expr
LE,Expr
LEU,Expr
LT,Expr
LTU,Expr
N,Expr
Branch if Greater Than or Equal
Branch if Unsigned Greater Than or Equal
Branch if Greater Than
Branch if Unsigned Greater Than
Branch if Less Than or Equal
Branch if Unsigned Less Than or Equal
Branch if Less Than
Branch if Unsigned Less Than
Branch if Negative
None
None
None
None
None
None
None
None
None
NC,Expr
NN,Expr
NOV,Expr
NZ,Expr
OV,Expr
Expr
Branch if Not Carry
None
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
None
None
None
Branch if Overflow
None
Branch Unconditionally
Branch if Zero
None
Z,Expr
1 (2)
2
None
Wn
Computed Branch
None
BSET
BSW
f,#bit4
Ws,#bit4
Ws,Wb
Bit Set f
1
None
Bit Set Ws
1
None
Write C bit to Ws[Wb]
Write Z bit to Ws[Wb]
Bit Toggle f
1
None
Ws,Wb
1
None
BTG
f,#bit4
Ws,#bit4
f,#bit4
1
None
Bit Toggle Ws
1
None
BTSC
Bit Test f, Skip if Clear
1
None
(2 or 3)
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
None
(2 or 3)
2019-2020 Microchip Technology Inc.
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TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Bit Test f, Skip if Set
Words Cycles
BTSS
BTSS
BTSS
f,#bit4
1
1
1
None
(2 or 3)
Ws,#bit4
Bit Test Ws, Skip if Set
1
None
(2 or 3)
BTST
BTST
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wb
Bit Test f
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
Z
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
Bit Test Ws to C
Bit Test Ws to Z
Bit Test Ws[Wb] to C
Bit Test Ws[Wb] to Z
Bit Test then Set f
Bit Test Ws to C, then Set
Bit Test Ws to Z, then Set
Call Subroutine
Call Indirect Subroutine
f = 0x0000
C
Z
C
Ws,Wb
Z
BTSTS
f,#bit4
Z
BTSTS.C Ws,#bit4
BTSTS.Z Ws,#bit4
C
Z
CALL
CLR
CALL
CALL
CLR
lit23
Wn
None
None
None
None
None
WDTO, Sleep
N, Z
f
CLR
WREG
Ws
WREG = 0x0000
Ws = 0x0000
CLR
CLRWDT
COM
CLRWDT
COM
Clear Watchdog Timer
f = f
f
COM
f,WREG
WREG = f
N, Z
COM
CP
Ws,Wd
Wd = Ws
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N, Z
CP
f
Compare f with WREG
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
CP
Wb,#lit5
Compare Wb with lit5
CP
Wb,Ws
Compare Wb with Ws (Wb – Ws)
Compare f with 0x0000
CP0
CPB
CP0
CP0
CPB
CPB
CPB
f
Ws
Compare Ws with 0x0000
Compare f with WREG, with Borrow
Compare Wb with lit5, with Borrow
f
Wb,#lit5
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
CPSEQ
CPSGT
CPSLT
CPSNE
CPSEQ
CPSGT
CPSLT
CPSNE
Wb,Wn
Wb,Wn
Wb,Wn
Wb,Wn
Compare Wb with Wn, Skip if =
Compare Wb with Wn, Skip if >
Compare Wb with Wn, Skip if <
Compare Wb with Wn, Skip if
1
1
1
1
1
None
None
None
None
(2 or 3)
1
(2 or 3)
1
(2 or 3)
1
(2 or 3)
DAW
DEC
DAW.B
DEC
Wn
Wn = Decimal Adjust Wn
f = f –1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
f
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
None
DEC
f,WREG
Ws,Wd
f
WREG = f –1
1
DEC
Wd = Ws – 1
1
DEC2
DEC2
f = f – 2
1
DEC2
f,WREG
Ws,Wd
#lit14
Wm,Wn
Wm,Wn
Wm,Wn
Wm,Wn
Wns,Wnd
Ws,Wnd
Ws,Wnd
WREG = f – 2
1
DEC2
Wd = Ws – 2
1
DISI
DIV
DISI
Disable Interrupts for k Instruction Cycles
Signed 16/16-bit Integer Divide
Signed 32/16-bit Integer Divide
Unsigned 16/16-bit Integer Divide
Unsigned 32/16-bit Integer Divide
Swap Wns with Wnd
1
DIV.SW
DIV.SD
DIV.UW
DIV.UD
EXCH
18
18
18
18
1
N, Z, C, OV
N, Z, C, OV
N, Z, C, OV
N, Z, C, OV
None
EXCH
FF1L
FF1R
FF1L
Find First One from Left (MSb) Side
Find First One from Right (LSb) Side
1
C
FF1R
1
C
DS30010198B-page 332
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
GOTO
GOTO
GOTO
INC
Expr
Go to Address
Go to Indirect
f = f + 1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
None
Wn
None
INC
f
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
N, Z
INC
f,WREG
WREG = f + 1
Wd = Ws + 1
f = f + 2
INC
Ws,Wd
INC2
IOR
INC2
INC2
INC2
IOR
f
f,WREG
WREG = f + 2
Wd = Ws + 2
f = f .IOR. WREG
Ws,Wd
f
IOR
f,WREG
WREG = f .IOR. WREG
N, Z
IOR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
#lit14
Wd = lit10 .IOR. Wd
N, Z
IOR
Wd = Wb .IOR. Ws
N, Z
IOR
Wd = Wb .IOR. lit5
N, Z
LNK
LSR
LNK
Link Frame Pointer
None
LSR
f
f = Logical Right Shift f
C, N, OV, Z
C, N, OV, Z
C, N, OV, Z
N, Z
LSR
f,WREG
WREG = Logical Right Shift f
Wd = Logical Right Shift Ws
Wnd = Logical Right Shift Wb by Wns
Wnd = Logical Right Shift Wb by lit5
Move f to Wn
LSR
Ws,Wd
LSR
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,Wn
LSR
N, Z
MOV
MOV
None
MOV
[Wns+Slit10],Wnd
f
Move [Wns+Slit10] to Wnd
Move f to f
None
MOV
N, Z
MOV
f,WREG
Move f to WREG
N, Z
MOV
#lit16,Wn
#lit8,Wn
Wn,f
Move 16-bit Literal to Wn
Move 8-bit Literal to Wn
None
MOV.b
MOV
None
Move Wn to f
None
MOV
Wns,[Wns+Slit10]
Wso,Wdo
WREG,f
Move Wns to [Wns+Slit10]
Move Ws to Wd
None
MOV
None
MOV
Move WREG to f
N, Z
MOV.D
MOV.D
MUL.SS
MUL.SU
MUL.US
MUL.UU
MUL.SU
MUL.UU
MUL
Wns,Wd
Move Double from W(ns):W(ns+1) to Wd
Move Double from Ws to W(nd+1):W(nd)
{Wnd+1, Wnd} = Signed(Wb) * Signed(Ws)
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws)
{Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws)
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws)
{Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5)
{Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5)
W3:W2 = f * WREG
None
Ws,Wnd
None
MUL
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,#lit5,Wnd
Wb,#lit5,Wnd
f
None
None
None
None
None
None
None
NEG
NEG
f
f = f + 1
C, DC, N, OV, Z
NEG
f,WREG
Ws,Wd
WREG = f + 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
1
C, DC, N, OV, Z
C, DC, N, OV, Z
None
NEG
Wd = Ws + 1
NOP
POP
NOP
No Operation
NOPR
POP
No Operation
None
f
Pop f from Top-of-Stack (TOS)
Pop from Top-of-Stack (TOS) to Wdo
Pop from Top-of-Stack (TOS) to W(nd):W(nd+1)
Pop Shadow Registers
None
POP
Wdo
Wnd
None
POP.D
POP.S
PUSH
PUSH
PUSH.D
PUSH.S
None
All
PUSH
f
Push f to Top-of-Stack (TOS)
Push Wso to Top-of-Stack (TOS)
Push W(ns):W(ns+1) to Top-of-Stack (TOS)
Push Shadow Registers
None
Wso
Wns
None
None
None
2019-2020 Microchip Technology Inc.
DS30010198B-page 333
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TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
PWRSAV
RCALL
PWRSAV
RCALL
RCALL
REPEAT
REPEAT
RESET
RETFIE
RETLW
RETURN
RLC
#lit1
Expr
Wn
Go into Sleep or Idle mode
Relative Call
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
WDTO, Sleep
None
Computed Call
2
None
REPEAT
#lit14
Wn
Repeat Next Instruction lit14 + 1 Times
Repeat Next Instruction (Wn) + 1 Times
Software Device Reset
Return from Interrupt
1
None
1
None
RESET
RETFIE
RETLW
RETURN
RLC
1
None
3 (2)
3 (2)
3 (2)
1
None
#lit10,Wn
Return with Literal in Wn
Return from Subroutine
f = Rotate Left through Carry f
WREG = Rotate Left through Carry f
Wd = Rotate Left through Carry Ws
f = Rotate Left (No Carry) f
WREG = Rotate Left (No Carry) f
Wd = Rotate Left (No Carry) Ws
f = Rotate Right through Carry f
WREG = Rotate Right through Carry f
Wd = Rotate Right through Carry Ws
f = Rotate Right (No Carry) f
WREG = Rotate Right (No Carry) f
Wd = Rotate Right (No Carry) Ws
Wnd = Sign-Extended Ws
f = FFFFh
None
None
f
C, N, Z
C, N, Z
C, N, Z
N, Z
RLC
f,WREG
Ws,Wd
f
1
RLC
1
RLNC
RRC
RLNC
RLNC
RLNC
RRC
1
f,WREG
Ws,Wd
f
1
N, Z
1
N, Z
1
C, N, Z
C, N, Z
C, N, Z
N, Z
RRC
f,WREG
Ws,Wd
f
1
RRC
1
RRNC
RRNC
RRNC
RRNC
SE
1
f,WREG
Ws,Wd
Ws,Wnd
f
1
N, Z
1
N, Z
SE
1
C, N, Z
None
SETM
SETM
SETM
SETM
SL
1
WREG
WREG = FFFFh
1
None
Ws
Ws = FFFFh
1
None
SL
f
f = Left Shift f
1
C, N, OV, Z
C, N, OV, Z
C, N, OV, Z
N, Z
SL
f,WREG
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
f
WREG = Left Shift f
1
SL
Wd = Left Shift Ws
1
SL
Wnd = Left Shift Wb by Wns
Wnd = Left Shift Wb by lit5
f = f – WREG
1
SL
1
N, Z
SUB
SUB
1
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
SUB
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
WREG = f – WREG
1
SUB
Wn = Wn – lit10
1
SUB
Wd = Wb – Ws
1
SUB
Wd = Wb – lit5
1
SUBB
SUBB
SUBB
SUBB
f
f = f – WREG – (C)
1
1
1
1
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
f,WREG
#lit10,Wn
WREG = f – WREG – (C)
Wn = Wn – lit10 – (C)
SUBB
SUBB
SUBR
SUBR
SUBR
SUBR
SUBBR
Wb,Ws,Wd
Wb,#lit5,Wd
f
Wd = Wb – Ws – (C)
Wd = Wb – lit5 – (C)
f = WREG – f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
SUBR
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = WREG – f
Wd = Ws – Wb
Wd = lit5 – Wb
SUBBR
f = WREG – f – (C)
SUBBR
SUBBR
SUBBR
SWAP.b
SWAP
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
Wn
WREG = WREG – f – (C)
Wd = Ws – Wb – (C)
Wd = lit5 – Wb – (C)
Wn = Nibble Swap Wn
Wn = Byte Swap Wn
1
1
1
1
1
1
1
1
1
1
C, DC, N, OV, Z
C, DC, N, OV, Z
C, DC, N, OV, Z
None
SWAP
Wn
None
DS30010198B-page 334
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
TBLRDH
TBLRDL
TBLWTH
TBLWTL
ULNK
TBLRDH
TBLRDL
TBLWTH
TBLWTL
ULNK
XOR
Ws,Wd
Ws,Wd
Ws,Wd
Ws,Wd
Read Prog[23:16] to Wd[7:0]
Read Prog[15:0] to Wd
Write Ws[7:0] to Prog[23:16]
Write Ws to Prog[15:0]
Unlink Frame Pointer
f = f .XOR. WREG
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
1
1
1
1
1
1
1
None
None
None
None
None
N, Z
XOR
f
XOR
f,WREG
WREG = f .XOR. WREG
Wd = lit10 .XOR. Wd
Wd = Wb .XOR. Ws
N, Z
XOR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Ws,Wnd
N, Z
XOR
N, Z
XOR
Wd = Wb .XOR. lit5
N, Z
ZE
ZE
Wnd = Zero-Extend Ws
C, Z, N
2019-2020 Microchip Technology Inc.
DS30010198B-page 335
PIC24FJ128GL306 FAMILY
NOTES:
DS30010198B-page 336
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
29.0 DEVELOPMENT SUPPORT
Move a design from concept to production in record time with Microchip’s award-winning development tools. Microchip
tools work together to provide state of the art debugging for any project with easy-to-use Graphical User Interfaces (GUIs)
in our free MPLAB® X and Atmel Studio Integrated Development Environments (IDEs), and our code generation tools.
Providing the ultimate ease-of-use experience, Microchip’s line of programmers, debuggers and emulators work
seamlessly with our software tools. Microchip development boards help evaluate the best silicon device for an application,
while our line of third party tools round out our comprehensive development tool solutions.
Microchip’s MPLAB X and Atmel Studio ecosystems provide a variety of embedded design tools to consider, which sup-
port multiple devices, such as PIC® MCUs, AVR® MCUs, SAM MCUs and dsPIC® DSCs. MPLAB X tools are compatible
with Windows®, Linux® and Mac® operating systems while Atmel Studio tools are compatible with Windows.
Go to the following website for more information and details:
https://www.microchip.com/development-tools/
2019-2020 Microchip Technology Inc.
DS30010198B-page 337
PIC24FJ128GL306 FAMILY
NOTES:
DS30010198B-page 338
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
30.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC24FJ128GL306 family electrical characteristics. Additional information
will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC24FJ128GL306 family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other
conditions above the parameters indicated in the operation listings of this specification, is not implied.
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any general purpose digital or analog pin (not 5.5V tolerant) with respect to VSS....... -0.3V to (VDD + 0.3V)
Voltage on any general purpose digital or analog pin (5.5V tolerant, including MCLR) with respect to VSS:
When VDD = 0V: .......................................................................................................................... -0.3V to +4.0V
When VDD 2.0V: ....................................................................................................................... -0.3V to +6.0V
Voltage on AVDD with respect to VSS ...................................................(VDD – 0.3V) to (lesser of: 4.0V or (VDD + 0.3V))
Voltage on AVSS with respect to VSS ........................................................................................................ -0.3V to +0.3V
Maximum current out of VSS pin:
+85°C......................................................................................................................................................300 mA
+125°C....................................................................................................................................................100 mA
Maximum current into VDD pin (Note 1):
+85°C......................................................................................................................................................300 mA
+125°C....................................................................................................................................................100 mA
Maximum output current sunk by any I/O pin:
RB15, RC15 .............................................................................................................................................50 mA
All other I/Os.............................................................................................................................................25 mA
Maximum output current sourced by any I/O pin:
RB15, RC15 .............................................................................................................................................50 mA
All other I/Os.............................................................................................................................................25 mA
Maximum current sunk by group of I/Os between two VSS Pins (Note 2):
+85°C......................................................................................................................................................300 mA
+125°C......................................................................................................................................................75 mA
Maximum current sourced by group of I/Os between two VDD pins (Note 2):
+85°C......................................................................................................................................................300 mA
+125°C......................................................................................................................................................75 mA
Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 30-1).
2: Only on the 28-lead and 36-lead packages can AVDD/AVSS be considered for grouping of I/Os.
†
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
2019-2020 Microchip Technology Inc.
DS30010198B-page 339
PIC24FJ128GL306 FAMILY
30.1 DC Characteristics
FIGURE 30-1:
PIC24FJ128GL306 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
3.6V
3.6V
PIC24FJ128GL306
(Note 1)
(Note 1)
32 MHz
Frequency
Note 1: Lower operating boundary is 2.0V or VBOR (when BOR is enabled), whichever is lower. For best
analog performance, operate above 2.2V.
TABLE 30-1: THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
PIC24FJ128GL306:
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
-40
-40
—
—
+135
+125
°C
°C
TA
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH)
PD
PINT + PI/O
W
W
I/O Pin Power Dissipation:
PI/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
PDMAX
(TJ – TA)/JA
TABLE 30-2: THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Notes
Package Thermal Resistance, 6x6 mm 28-Pin QFN
Package Thermal Resistance, 4x4x0.6 mm 28-Pin UQFN
Package Thermal Resistance, 7.50 mm 28-Pin SOIC
Package Thermal Resistance, 5.30 mm 28-Pin SSOP
Package Thermal Resistance, 5x5 mm 36-Pin UQFN
Package Thermal Resistance, 6x6x0.5 mm 48-Pin UQFN
Package Thermal Resistance, 7x7x1 mm 48-Pin TQFP
Package Thermal Resistance, 9x9x0.9 mm 64-Pin QFN
Package Thermal Resistance, 10x10x1 mm 64-Pin TQFP
JA
JA
JA
JA
JA
JA
JA
JA
JA
38.4
38.7
79.0
67.1
35.4
28.3
71.0
23.0
68.9
—
—
—
—
—
—
—
—
—
°C/W (Note 1)
°C/W (Note 1)
°C/W (Note 1)
°C/W (Note 1)
°C/W (Note 1)
°C/W (Note 1)
°C/W (Note 1)
°C/W (Note 1)
°C/W (Note 1)
Note 1: Junction to ambient thermal resistance; Theta-JA (JA) numbers are achieved by package simulations.
DS30010198B-page 340
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 30-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS
Operating Conditions:
2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
Operating Voltage
DC10 VDD
Supply Voltage
2.0
VBOR
VSS
—
—
—
3.6
3.6
—
V
V
V
BOR is disabled
BOR is enabled
DC16 VPOR
VDD Start Voltage
to Ensure Internal
(Note 1)
Power-on Reset Signal
DC17A SVDD
DC17B VBOR
Recommended
VDD Rise Rate
to Ensure Internal
Power-on Reset Signal
1V/20 ms
1.95
—
1V/10 µS sec (Notes 1 and 3)
Brown-out Reset
Voltage on VDD
2.1
2.2
V
(Note 2)
Transition, High-to-Low
Note 1: If the VPOR or SVDD parameters are not met, or the application experiences slow power-down VDD ramp
rates, it is recommended to enable and use BOR.
2: On a rising VDD power-up sequence, application firmware execution begins at the higher of the VPORREL or
VBOR level (when BOREN = 1).
3: VDD rise times outside this window may not internally reset the processor and are not parametrically
tested.
2019-2020 Microchip Technology Inc.
DS30010198B-page 341
PIC24FJ128GL306 FAMILY
TABLE 30-4: OPERATING CURRENT (IDD)
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
Typical(1)
No.
Operating
Temperature
Max(2)
Units
VDD
Conditions
Operating Current (IDD)(3)
DC19
DC20
DC23
DC24
DC31
208.8
215.4
362.3
366.4
1.3
350
350
550
550
1.6
µA
µA
µA
µA
mA
mA
mA
mA
µA
µA
µA
µA
mA
mA
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
0.5 MIPS,
FOSC = 1 MHz
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +125°C
1 MIPS,
FOSC = 2 MHz
4 MIPS,
FOSC = 8 MHz
1.35
5
1.6
6.2
16 MIPS,
FOSC = 32 MHz
5.1
6.2
41.5
47.4
55.5
61.9
1.34
1.35
130
130
310
310
1.7
LPRC (16 KIPS),
FOSC = 32 kHz
DC32
FRC (4 MIPS),
FOSC = 8 MHz
1.7
Note 1: Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Typical parameters are for design
guidance only and are not tested.
2: Data in “Max” column are production tested.
3: Base IDD current is measured with:
• Oscillator is configured in EC mode without PLL (FNOSC[2:0] (FOSCSEL[2:0]) = 010,
PLLMODE[3:0] (FOSCSEL[6:3]) = 1111and POSCMOD[1:0] (FOSC[1:0]) = 00)
• OSCI pin is driven with external square wave, with levels from 0.3V to VDD – 0.3V
• OSCO is configured as an I/O in the Configuration Words (OSCIOFCN (FOSC[2]) = 0)
• FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 11)
• Secondary Oscillator circuit is disabled (SOSCSEL (FOSC[3]) = 0)
• Main and low-power BOR circuits are disabled (BOREN[1:0] (FPOR[1:0]) = 00and
LPBOREN (FPOR[3]) = 0)
• Watchdog Timer is disabled (FWDTEN[1:0] (FWDT[6:5]) = 00)
• All I/O pins (except OSCI) are configured as outputs and driving low
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• JTAG is disabled (JTAGEN (FICD[5]) = 0)
• NOPinstructions are executed
DS30010198B-page 342
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
TABLE 30-5: IDLE CURRENT (IIDLE)
Operating Conditions:
2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
Operating
Temperature
Typical(1)
Max(2)
Units
VDD
Conditions
No.
Idle Current (IIDLE)(3)
DC40
DC43
DC47
DC50
DC51
110
121.3
130.2
130.2
329.7
357.5
350
250
250
325
325
500
500
600
600
1.8
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
1 MIPS,
FOSC = 2 MHz
4 MIPS,
FOSC = 8 MHz
370.9
1.2
1.3
1.8
16 MIPS,
FOSC = 32 MHz
1.22
1.9
1.31
1.9
369.6
375.1
382.9
388.9
37.5
550
550
650
650
110
110
300
300
FRC (4 MIPS),
FOSC = 8 MHz
43.3
LPRC (16 KIPS),
FOSC = 32 kHz
50.8
57.1
Note 1: Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design
guidance only and are not tested.
2: Data in “Max” column are production tested.
3: Base IIDLE current is measured with:
• Oscillator is configured in EC mode without PLL (FNOSC[2:0] (FOSCSEL[2:0]) = 010,
PLLMODE[3:0] (FOSCSEL[6:3]) = 1111and POSCMOD[1:0] (FOSC[1:0]) = 00)
• OSCI pin is driven with external square wave, with levels from 0.3V to VDD – 0.3V
• OSCO is configured as an I/O in Configuration Words (OSCIOFCN (FOSC[2]) = 0)
• FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 11)
• Secondary Oscillator circuit is disabled (SOSCSEL (FOSC[3]) = 0)
• Main and low-power BOR circuits are disabled (BOREN[1:0] (FPOR[1:0]) = 00and
LPBOREN (FPOR[3]) = 0)
• Watchdog Timer is disabled (FWDTEN[1:0] (FWDT[6:5]) = 00)
• All I/O pins (except OSCI) are configured as outputs and driving low
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• JTAG is disabled (JTAGEN (FICD[5]) = 0)
• pwrsav #1 (IDLE)instruction is executed
2019-2020 Microchip Technology Inc.
DS30010198B-page 343
PIC24FJ128GL306 FAMILY
TABLE 30-6: POWER-DOWN CURRENT (IPD)
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
Typical(1)
No.
Operating
Temperature
Max(2)
Units
VDD
Conditions
Power-Down Current(5,6)
DC60
3.47
4.31
9.93
38.79
3.72
4.6
10
10
µA
µA
µA
µA
µA
µA
µA
µA
nA
nA
µA
µA
nA
nA
µA
µA
-40°C
+25°C
+85°C
+125°C
-40°C
2.0V
3.3V
2.0V
3.3V
20
150
Sleep(3)
10
10
+25°C
+85°C
+125°C
-40°C
10.27
39.45
272.7
450
20
150
DC61
Note 7
Note 7
Note 7
Note 7
Note 7
Note 7
Note 7
Note 7
+25°C
+85°C
+125°C
-40°C
4.5
28.7
336
Low-Voltage Retention Sleep(4)
460
+25°C
+85°C
+125°C
4.5
29
Note 1: Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design
guidance only and are not tested.
2: Data in “Max” column are production tested.
3: The retention low-voltage regulator is disabled; RETEN (RCON[12]) = 0, LPCFG (FPOR[2]) = 1.
4: The retention low-voltage regulator is enabled; RETEN (RCON[12]) = 1, LPCFG (FPOR[2]) = 0.
5: Base IPD current is measured with:
• Oscillator is configured in FRC mode without PLL (FNOSC[2:0] (FOSCSEL[2:0]) = 000,
PLLMODE[3:0] (FOSCSEL[6:3]) = 1111and POSCMOD[1:0] (FOSC[1:0]) = 11)
• OSCO is configured as an I/O in Configuration Words (OSCIOFCN (FOSC[2]) = 0)
• FSCM is disabled (FCKSM[1:0] (FOSC[7:6]) = 11)
• Secondary Oscillator circuit is disabled (SOSCSEL (FOSC[3]) = 0)
• Main and low-power BOR circuits are disabled (BOREN[1:0] (FPOR[1:0]) = 00and
LPBOREN (FPOR[3]) = 0)
• Watchdog Timer is disabled (FWDTEN[1:0] (FWDT[6:5]) = 00)
• All I/O pins are configured as outputs and driving low
• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)
• JTAG is disabled (JTAGEN (FICD[5]) = 0)
• pwrsav #0 (SLEEP)instruction is executed
6: These currents are measured on the device containing the most memory in this family.
7: For design guidance, please refer to Figure 30-2 and Figure 30-3.
DS30010198B-page 344
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
FIGURE 30-2:
IPD VS. TEMPERATURE GRAPHS (PAGE 1 OF 2)(1,2)
Base I (Extended, V =ꢀ3.3V)
PD
ꢁꢁꢀ
150
140
130
120
110
100
90
80
70
Typical
Max
60
50
40
30
20
10
0
-40ꢀ -35ꢀ -30ꢀ -25ꢀ -20ꢀ -15ꢀ -10ꢀ -5ꢀ 0ꢀ 5ꢀ 10ꢀ 15ꢀ 20ꢀ 25ꢀ 30ꢀ 35ꢀ 40ꢀ 45ꢀ 50ꢀ 55ꢀ 60ꢀ 65ꢀ 70ꢀ 75ꢀ 80ꢀ 85ꢀ 90ꢀ 95ꢀ 100ꢀ105ꢀ110ꢀ115ꢀ120ꢀ125
Temperature (ºC)
I
PD
Retention (Extended, V =ꢀ3.3V)
ꢁꢁꢀ
120
110
100
90
80
70
60
50
40
30
20
10
0
Typical
Max
-40ꢀ -35ꢀ -30ꢀ -25ꢀ -20ꢀ -15ꢀ -10ꢀ -5ꢀ 0ꢀ 5ꢀ 10ꢀ 15ꢀ 20ꢀ 25ꢀ 30ꢀ 35ꢀ 40ꢀ 45ꢀ 50ꢀ 55ꢀ 60ꢀ 65ꢀ 70ꢀ 75ꢀ 80ꢀ 85ꢀ 90ꢀ 95ꢀ 100ꢀ105ꢀ110ꢀ115ꢀ120ꢀ125
Temperature (ºC)
Note 1: For base IPD, temperature points of -40°C, +25°C and +125°C are production tested only.
2: For IPD retention, data provided are characterized but not production tested.
2019-2020 Microchip Technology Inc.
DS30010198B-page 345
PIC24FJ128GL306 FAMILY
FIGURE 30-3:
IPD VS. TEMPERATURE GRAPHS (PAGE 2 OF 2)(1,2)
Base I (Industrial, V =ꢀ3.3V)
PD
ꢁꢁꢀ
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Typical
Max
8
7
6
5
4
3
2
1
0
-40ꢀ -35ꢀ -30ꢀ -25ꢀ -20ꢀ -15ꢀ -10ꢀ -5ꢀ 0ꢀ
5ꢀ 10ꢀ 15ꢀ 20ꢀ 25ꢀ 30ꢀ 35ꢀ 40ꢀ 45ꢀ 50ꢀ 55ꢀ 60ꢀ 65ꢀ 70ꢀ 75ꢀ 80ꢀ 85
Temperature (ºC)
I
PD
Retention (Industrial, V =ꢀ3.3V)
ꢁꢁꢀ
15
14
13
12
11
10
9
8
7
Typical
Max
6
5
4
3
2
1
0
-40ꢀ -35ꢀ -30ꢀ -25ꢀ -20ꢀ -15ꢀ -10ꢀ -5ꢀ 0ꢀ
5ꢀ 10ꢀ 15ꢀ 20ꢀ 25ꢀ 30ꢀ 35ꢀ 40ꢀ 45ꢀ 50ꢀ 55ꢀ 60ꢀ 65ꢀ 70ꢀ 75ꢀ 80ꢀ 85
Temperature (ºC)
Note 1: For base IPD, temperature points of -40°C, +25°C and +125°C are production tested only.
2: For IPD retention, data provided are characterized but not production tested.
DS30010198B-page 346
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PIC24FJ128GL306 FAMILY
TABLE 30-7: CURRENT (BOR, WDT, HLVD, ADC, LCD, DMT, RTCC)(3)
Operating Conditions:
2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
Operating
Temperature
Typical(1)
Max
Units
VDD
Conditions
No.
Incremental Current Brown-out Reset (BOR)(2)
DC70
1.3
2
5
5
µA
µA
µA
µA
2.0V
3.3V
2.0V
3.3V
-40°C to +85°C
-40°C to +125°C
BOR(2)
WDT(2)
HLVD(2)
1.5
10
2.1
10
Incremental Current Watchdog Timer (WDT)(2)
DC71
0.27
0.35
0.55
0.6
1
1
5
5
µA
µA
µA
µA
2.0V
3.3V
2.0V
3.3V
-40°C to +85°C
-40°C to +125°C
Incremental Current High/Low-Voltage Detect (HLVD)(2)
DC72
1.9
2.6
2.6
3.3
5
5
µA
µA
µA
µA
2.0V
3.3V
2.0V
3.3V
-40°C to +85°C
-40°C to +125°C
10
10
Incremental Current ADC (ADC)(2)
DC73
379.6
522.7
398.6
522
700
700
750
750
µA
µA
µA
µA
2.0V
3.3V
2.0V
3.3V
-40°C to +85°C
-40°C to +125°C
ADC(2) with internal RC clock
Incremental Current LCD (LCD)(2)
DC74
DC75
DC76
DC77
DC78
DC79
1.3
1.7
12
12
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
-40°C to +85°C
LCD (low-power resistor ladder)
7.8
25
LCD (medium power resistor
ladder)
12.2
64.3
105.1
10.2
10.2
11.5
13.8
40.1
39.2
25
140
140
25(4)
25(4)
45(4)
45(4)
70(4)
70(4)
LCD (high-power resistor ladder)
LCD + Charge Pump (low-power
resistor ladder)
LCD + Charge Pump (low-power
resistor ladder)
LCD + Charge Pump (medium
power resistor ladder)
Note 1: Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design
guidance only and are not tested.
2: Incremental current while the module is enabled and running.
3: The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current. The current includes the selected clock source enabled for WDT
and RTCC.
4: These parameters are characterized but not tested in manufacturing.
2019-2020 Microchip Technology Inc.
DS30010198B-page 347
PIC24FJ128GL306 FAMILY
TABLE 30-7: CURRENT (BOR, WDT, HLVD, ADC, LCD, DMT, RTCC)(3) (CONTINUED)
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Parameter
Operating
Temperature
Typical(1)
Max
Units
VDD
Conditions
No.
DC80
43.1
42
85(4)
85(4)
420(4)
420(4)
420(4)
420(4)
µA
µA
µA
µA
µA
µA
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
LCD + Charge Pump (medium
power resistor ladder)
-40°C to +125°C
DC81
DC82
299.2
252.8
295.5
237.6
LCD + Charge Pump
(high-power resistor ladder)
-40°C to +85°C
-40°C to +125°C
LCD + Charge Pump
(high-power resistor ladder)
Incremental Current DMT (DMT)(2)
DC83
177.2
234.1
575
1000
1000
1500
1500
nA
nA
nA
nA
2.0V
3.3V
2.0V
3.3V
-40°C to +85°C
-40°C to +125°C
DMT(2)
750
Incremental Current Real-Time Clock and Calendar (RTCC)(2)
DC84
786.4
894.6
500
—
nA
nA
nA
nA
nA
nA
2.0V
3.3V
2.0V
3.3V
2.0V
3.3V
RTCC (with SOSC enabled in
-40°C to +125°C
-40°C to +85°C
-40°C to +125°C
Low-Power mode)(2)
—
DC85
1000
1000
1300
1300
RTCC (with LPRC enabled)(2)
550
570
600
Note 1: Data in the “Typical” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design
guidance only and are not tested.
2: Incremental current while the module is enabled and running.
3: The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current. The current includes the selected clock source enabled for WDT
and RTCC.
4: These parameters are characterized but not tested in manufacturing.
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TABLE 30-8:
I/O PIN INPUT SPECIFICATIONS
Operating Conditions:
2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
VIL
Input Low Voltage(3)
I/O Pins with ST Buffer
I/O Pins with TTL Buffer
MCLR
DI10
DI11
DI15
DI16
DI18
DI19
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
0.2 VDD
0.15 VDD
0.2 VDD
0.2 VDD
0.3 VDD
0.8
V
V
V
V
V
V
OSCI (EC mode)
I/O Pins with I2C Buffer
I/O Pins with SMBus Buffer
Input High Voltage(3)
SMBus is enabled
VIH
DI20
DI21
I/O Pins with ST Buffer:
with Analog Functions,
Digital Only
0.8 VDD
0.8 VDD
—
—
VDD
5.5
V
V
I/O Pins with TTL Buffer:
with Analog Functions,
Digital Only
0.25 VDD + 0.8
0.25 VDD + 0.8
—
—
VDD
5.5
V
V
DI25
DI26
DI28
MCLR
0.8 VDD
0.7 VDD
—
—
VDD
VDD
V
V
OSCI (EC mode)
I/O Pins with I2C Buffer:
with Analog Functions,
Digital Only
0.7 VDD
0.7 VDD
—
—
VDD
5.5
V
V
DI29
DI30
I/O Pins with SMBus Buffer:
with Analog Functions,
Digital Only
1.35
1.35
—
—
VDD
5.5
V
V
ICNPU
CNx Pull-up Current
CNx Pull-Down Current
Input Leakage Current(2)
I/O Ports
100
150
—
—
450
550
µA
µA
VDD = 3.3V, VPIN = VSS
VDD = 3.3V, VPIN = VDD
DI30A ICNPD
IIL
DI50
—
—
—
—
±1
±1
µA
µA
VSS VPIN VDD,
pin at high-impedance
DI51
Analog Input Pins
VSS VPIN VDD,
pin at high-impedance
DI55
DI56
MCLR
—
—
—
—
±1
±1
µA
µA
VSS VPIN VDD
OSCI/CLKI
VSS VPIN VDD,
EC, XT and HS modes
Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: Negative current is defined as current sourced by the pin.
3: Refer to Table 1-1 for I/O pin buffer types.
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TABLE 30-9:
I/O PIN OUTPUT SPECIFICATIONS
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
VOL
Output Low Voltage
DO10
DO16
DO20
I/O Ports
—
—
—
—
—
—
—
—
—
—
0.35
0.7
V
V
V
V
V
IOL = 6 mA, VDD = 3.6V
IOL = 18 mA, VDD = 3.6V
IOL = 5.0 mA, VDD = 2V
IOL = 9 mA, VDD = 3.6V
IOL = 6 mA, VDD = 2V
0.4
RB15, RC15
0.35
0.35
VOH
Output High Voltage
I/O Ports
3.2
2.7
—
—
—
—
—
—
—
—
—
—
—
—
V
V
V
V
V
V
IOH = -6.0 mA, VDD = 3.6V
IOH = -18 mA, VDD = 3.6V
IOH = -1.0 mA, VDD = 2V
IOH = -10 mA, VDD = 2V
IOH = -6.0 mA, VDD = 3.6V
IOH = -1.0 mA, VDD = 2V
1.75
0.9
DO26
RB15, RC15
3.25
1.75
Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
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FIGURE 30-4:
I/O VOL VS. IOL CHARACTER GRAPHS(1)
I/O VOL Versus IOL (VDD = 3.6V)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-40C Typical
25C Typical
85C Typical
125C Typical
Max
6
8
10
12
14
16
18
IOL (mA)
I/O VOL Versus IOL (VDD = 2.0V)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-40C Typical
25C Typical
85C Typical
125C Typical
Max
5
6
7
8
9
10
11
IOL (mA)
Note 1: Production test conditions are given in Table 30-9.
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FIGURE 30-5:
I/O VOH VS. IOL CHARACTER GRAPHS(1)
I/O VOH Versus IOL (VDD = 3.6V)
3.6
3.5
3.4
3.3
3.2
3.1
3
-40C Typical
25C Typical
85C Typical
125C Typical
Min
2.9
2.8
2.7
-18
-16
-14
-12
-10
-8
-6
IOL (mA)
I/O VOH Versus IOL (VDD = 2.0V)
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
-40C Typical
25C Typical
85C Typical
125C Typical
Min
0.9
-9
-8
-7
-6
-5
-4
IOL (mA)
Note 1: Production test conditions are given in Table 30-9.
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FIGURE 30-6:
RC15, RB15 VOL VS. IOL CHARACTER GRAPHS(1)
RC15 & RB15 VOL Versus IOL (VDD = 3.6V)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
-40C Typical
25C Typical
85C Typical
125C Typical
Max
0
9
14
19
24
29
34
IOL (mA)
RC15 & RB15 VOL Versus IOL (VDD = 2.0V)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
-40C Typical
25C Typical
85C Typical
125C Typical
Max
0
6
8
10
12
14
16
18
20
IOL (mA)
Note 1: Production test conditions are given in Table 30-9.
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FIGURE 30-7:
RC15, RB15 VOH VS. IOL CHARACTER GRAPHS(1)
RC15 & RB15 VOH Versus IOL (VDD = 3.6V)
3.6
3.5
3.4
3.3
3.2
3.1
3
-40C Typical
25C Typical
85C Typical
125C Typical
Min
2.9
2.8
2.7
-26
-22
-18
-14
-10
-6
IOL (mA)
RC15 & RB15 VOH Versus IOL (VDD = 2.0V)
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
-40C Typical
25C Typical
85C Typical
125C Typical
Min
0.9
-14
-13
-12
-11
-10
IOL (mA)
-9
-8
-7
-6
-5
Note 1: Production test conditions are given in Table 30-9.
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TABLE 30-10: PROGRAM MEMORY
Operating Conditions:
2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristic
Min Typ(1) Max Units
Conditions
Program Flash Memory
Cell Endurance
D130
D131
D132B
EP
10000
2.0
—
—
—
20
—
3.6
3.6
—
E/W -40C to +125C
VPR
VDD for Read
V
V
VDD for Self-Timed Write
2.0
D133A TIW
Self-Timed Word Write
Cycle Time
—
µs
Self-Timed Row Write
Cycle Time
—
20
20
1.5
—
—
40
—
ms
D133B TIE
Self-Timed Page Erase
Time
ms
D134
TRETD
Characteristic Retention
—
Year If no other specifications are violated
Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated.
TABLE 30-11: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristics
Min
Typ Max Units
Comments
DVR
TVREG
Voltage Regulator Start-up Time
—
10
—
µs
VREGS = 0with any POR or
BOR
DVR10
DVR11
VBG
TBG
Internal Band Gap Reference
1.14
—
1.2 1.26
V
Band Gap Reference
Start-up Time
1
—
ms
DVR20 VRGOUT Regulator Output Voltage
1.6
10
1.8
—
2.0
—
V
VDD > 1.9V
DVR21
CEFC
External Filter Capacitor Value
µF Series resistance < 3
recommended; < 5 required
DVR30
VLVR
Low-Voltage Regulator
Output Voltage
0.9
—
1.2
V
RETEN = 1, LPCFG = 0
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TABLE 30-12: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS
Operating Conditions: -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min
Typ
Max Units
Conditions
DC18 VHLVD
HLVD Voltage on VDD HLVDL[3:0] = 0100(1) 3.39
—
—
—
V
V
V
V
V
V
V
V
V
V
V
V
Transition
HLVDL[3:0] = 0101
HLVDL[3:0] = 0110
HLVDL[3:0] = 0111
HLVDL[3:0] = 1000
HLVDL[3:0] = 1001
HLVDL[3:0] = 1010
HLVDL[3:0] = 1011
HLVDL[3:0] = 1100
HLVDL[3:0] = 1101
HLVDL[3:0] = 1110
HLVDL[3:0] = 1111
3.24
2.93
2.73
2.62
2.39
2.29
2.18
2.08
1.98
1.88
—
—
—
3.39
3.17
3.06
2.8
—
—
—
—
2.68
2.56
2.45
2.34
2.23
—
—
—
—
—
DC101 VTHL
HLVD Voltage on
1.20
HLVDIN Pin Transition
DC105 TONLVD HLVD Module Enable Time
—
5
—
µs
From POR or
HLVDEN = 1
Note 1: Trip points for values of HLVD[3:0], from ‘0000’ to ‘0011’, are not implemented.
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TABLE 30-13: COMPARATOR DC SPECIFICATIONS
Operating Conditions: -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min
Typ
Max Units
Comments
D300
D301
D302
D306
D307
D308
D309
VIOFF
VICM
Input Offset Voltage
Input Common-Mode Voltage
—
0
12
—
50
VDD
—
mV (Note 1)
V
(Note 1)
CMRR Common-Mode Rejection Ratio
55
—
—
—
—
—
dB
µA
ns
µs
µA
(Note 1)
IQCMP
TRESP
AVDD Quiescent Current per Comparator
Response Time
27
300
—
—
Comparator is enabled
(Note 2)
—
TMC2OV Comparator Mode Change to Valid Output
Operating Supply Current
10
—
IDD
30
AVDD = 3.3V
Note 1: Parameters are characterized but not tested.
2: Measured with one input at VDD/2 and the other transitioning from VSS to VDD, 40 mV step, 15 mV overdrive.
TABLE 30-14: COMPARATOR VOLTAGE REFERENCE DC SPECIFICATIONS
Operating Conditions: -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Settling Time
Min
Typ
Max
Units
Comments
(Note 1)
VR310
TSET
—
-20
—
—
—
10
+80
—
µs
mV
k
VRD311 CVRAA
VRD312 CVRUR
Absolute Accuracy
Unit Resistor Value (R)
4.5
Note 1: Measures the interval while CVR[4:0] transitions from ‘11111’ to ‘00000’.
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30.2 AC Characteristics and Timing Parameters
The information contained in this section defines the PIC24FJ128GL306 family AC characteristics and timing
parameters.
TABLE 30-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Operating voltage VDD range as described in Section 30.1 “DC Characteristics”.
FIGURE 30-8:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSCO
VDD/2
Load Condition 2 – for OSCO
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSCO
15 pF for OSCO output
VSS
TABLE 30-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
Characteristic
Min
Typ(1) Max Units
Conditions
No.
DO50 COSCO
OSCO/CLKO Pin
—
—
15
pF In XT and HS modes when the
External Clock is used to drive
OSCI
DO56 CIO
DO58 CB
All I/O Pins and OSCO
SCLx, SDAx
—
—
—
—
50
pF EC mode
pF In I2C mode
400
Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
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FIGURE 30-9:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
OSCI
OS20
OS30
OS30
OS31 OS31
OS25
CLKO
OS40
OS41
TABLE 30-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
OS10 FOSC
External CLKI Frequency
(External clocks allowed
only in EC mode)
DC
4
—
—
32
48
MHz EC
MHz ECPLL (Note 2)
Oscillator Frequency
3.5
4
10
12
31
—
—
—
—
—
10
8
32
24
33
MHz XT
MHz XTPLL
MHz HS
MHz HSPLL
kHz
SOSC
OS20 TOSC
OS25 TCY
TOSC = 1/FOSC
—
—
—
—
See Parameter OS10 for
FOSC value
Instruction Cycle Time(3)
62.5
—
—
DC
—
ns
ns
OS30 TosL,
TosH
External Clock in (OSCI) 0.45 x TOSC
High or Low Time
EC
EC
OS31 TosR, External Clock in (OSCI)
—
—
20
ns
TosF
OS40 TckR
OS41 TckF
Rise or Fall Time
CLKO Rise Time(4)
CLKO Fall Time(4)
—
—
15
15
30
30
ns
ns
Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: Represents input to the system clock prescaler. PLL dividers and postscalers must still be configured so
that the system clock frequency does not exceed the maximum frequency shown in Figure 30-1.
3: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type, under standard operating conditions, with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an
External Clock applied to the OSCI/CLKI pin. When an External Clock input is used, the “Max.” cycle time
limit is “DC” (no clock) for all devices.
4: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the
Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
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TABLE 30-18: AC SPECIFICATIONS FOR PHASE-LOCKED LOOP (PLL) MODE
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Sym
Characteristic
Input Frequency Range
Min
Typ
Max Units
Conditions
FIN
2
—
—
24
16
MHz
FMIN Minimum Output Frequency from
the Frequency Multiplier
—
MHz 4 MHz FIN with 4x feedback ratio,
2 MHz FIN with 8x feedback ratio
FMAX Maximum Output Frequency from
the Frequency Multiplier
96
-4
—
—
—
MHz 4 MHz FIN with 24x net multiplication ratio,
24 MHz FIN with 4x net multiplication ratio
FSLEW Maximum Step Function of FIN at
which the PLL will be Ensured to
Maintain Lock
+4
%
Full input range of FIN
TLOCK Lock Time for VCO
—
—
—
—
24
µs With the specified minimum, TREF, and a
lock timer count of one cycle, this is the
maximum VCO lock time supported
JFM8 Cumulative Jitter of Frequency
Multiplier Over Voltage and
±0.12
%
4 MHz FIN with 4x feedback ratio
Temperature during Any Eight
Consecutive Cycles of the PLL Output
TABLE 30-19: INTERNAL RC ACCURACY
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
F20
FRC Accuracy @ 8 MHz
-1.5
+0.15
1.5
%
2.0V VDD 3.6V, -20°C TA +85°C
(Note 2)
-2
-2
—
—
2
2
%
%
2.0V VDD 3.6V, -40°C TA -20°C
2.0V VDD 3.6V, +85°C TA +125°C
(Note 2)
-0.20 +0.05 -0.20
%
-20°C TA +85°C
F20A
FRC Accuracy @ 8 MHz with
Enabled Self-Tune
Feature
F21
F22
F23
LPRC @ 32 kHz
-20
—
—
0.1
5
20
—
8
%
%/bit
ms
VCAP Output Voltage = 1.8V
OSCTUN Step-Size
TLOCK FRC Self-Tune Lock
Time(3)
—
Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
2: To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB)
must be kept to a minimum.
3: Time from reference clock stable, and in range, to FRC tuned within range specified by F20
(with self-tune).
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(1)
FIGURE 30-10:
FRC ACCURACY OVER TEMPERATURE AND VDD
VDD (V)
Note 1: Temperature points of -40°C, +25°C and +85°C are production tested only.
TABLE 30-20: RC OSCILLATOR START-UP TIME
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
FR0
TFRC
FRC Oscillator Start-up
Time
—
2
—
µs
FR1
TLPRC
Low-Power RC Oscillator
Start-up Time
—
50
—
µs
Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
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FIGURE 30-11:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
Old Value
New Value
DO31
DO32
Note:
Refer to Figure 30-8 for Load conditions.
TABLE 30-21: CLKO AND I/O TIMING REQUIREMENTS
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
DO31 TIOR
DO32 TIOF
Port Output Rise Time
Port Output Fall Time
—
—
1
10
10
—
25
25
—
ns
ns
DI35
TINP
INTx Pin High or Low
Time (input)
TCY
DI40
TRBP
CNx High or Low Time
(input)
1
—
—
TCY
Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated.
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TABLE 30-22: RESET AND BROWN-OUT RESET REQUIREMENTS
Operating Conditions:
2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
SY10 TMCL
SY12 TPOR
SY13 TIOZ
MCLR Pulse Width (Low)
Power-on Reset Delay
2
—
2
—
—
µs
µs
µs
—
I/O High-Impedance from
MCLR Low or Watchdog
Timer Reset
Lesser of:
(3 TCY + 2)
or 700
—
(3 TCY + 2)
SY25 TBOR
SY45 TRST
Brown-out Reset Pulse
Width
1
—
—
µs
VDD VBOR
Internal State Reset Time
—
—
50
7
—
—
µs
µs
SY71 TWAKEUP Wake-up Time from Sleep
Mode
VREGS (RCON[8]) = 1,
RETEN (RCON[12]) = 0,
LPCFG (FPOR[2]) = 1
—
—
—
35
—
—
—
µs
µs
µs
VREGS (RCON[8]) = 0,
RETEN (RCON[12]) = 0,
LPCFG (FPOR[2]) = 1
210
325
VREGS (RCON[8]) = 1,
RETEN (RCON[12]) = 1,
LPCFG (FPOR[2]) = 0
VREGS (RCON[8]) = 0,
RETEN (RCON[12]) = 1,
LPCFG (FPOR[2]) = 0
Note 1: Data in the “Typ” column are at 3.3V, +25°C unless otherwise stated.
2019-2020 Microchip Technology Inc.
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FIGURE 30-12:
TIMER1 EXTERNAL CLOCK TIMING CHARACTERISTICS
T1CK
TA11
TA10
TA15
TA20
TMR1
TABLE 30-23: TIMER1 EXTERNAL CLOCK TIMING CHARACTERISTICS
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
Symbol
No.
Characteristics(1)
Min
Max
Units
Conditions
TA10
TA11
TA15
TA20
TCKH
TCKL
TCKP
T1CK High Time Synchronous
Asynchronous
1
10
1
—
—
—
—
—
—
3
TCY
ns
Must also meet Parameter TA15
Must also meet Parameter TA15
T1CK Low Time Synchronous
Asynchronous
TCY
ns
10
2
T1CK Input
Period
Synchronous
Asynchronous
TCY
ns
20
—
TCKEXTMRL Delay from External T1CK Clock
Edge to Timer Increment
TCY
Synchronous mode
Note 1: These parameters are characterized but not tested in manufacturing.
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FIGURE 30-13:
MCCP TIMER MODE EXTERNAL CLOCK TIMING CHARACTERISTICS
TCKIx
TMR10
TMR11
TMR15
TMR20
CCPxTMR
TABLE 30-24: MCCP TIMER MODE TIMING REQUIREMENTS
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
Symbol
No.
Characteristics(1)
Min
Max
Units
Conditions
TMR10
TCKH
TCKL
TCKP
TCKIx High Time Synchronous
1
—
TCY
Must also meet
Parameter TMR15
Asynchronous
10
1
—
—
ns
TMR11
TCKIx Low Time Synchronous
TCY
Must also meet
Parameter TMR15
Asynchronous
TCKIx Input Period Synchronous
Asynchronous
10
2
—
—
—
1
ns
TCY
ns
TMR15
TMR20
20
—
TCKEXTMRL Delay from External TCKIx Clock Edge
to Timer Increment
TCY
Note 1: These parameters are characterized but not tested in manufacturing.
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DS30010198B-page 365
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FIGURE 30-14:
MCCP INPUT CAPTURE x MODE TIMING CHARACTERISTICS
ICMx
IC10
IC11
IC15
TABLE 30-25: MCCP INPUT CAPTURE x MODE TIMING REQUIREMENTS
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
Symbol
No.
Characteristics(1)
Min
Max
Units
Conditions
IC10
IC11
IC15
TICL
TICH
TICP
ICMx Input Low Time
ICMx Input High Time
ICMx Input Period
25
25
50
—
—
—
ns
ns
ns
Must also meet Parameter IC15
Must also meet Parameter IC15
Note 1: These parameters are characterized but not tested in manufacturing.
FIGURE 30-15:
MCCP PWM MODE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OCMnx
OC15
OCMnx is Tri-Stated
TABLE 30-26: MCCP PWM MODE TIMING REQUIREMENTS
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
Characteristics(1)
Min
Max
Units
No.
OC15
OC20
TFD
Fault Input to PWM I/O Change
Fault Input Pulse Width
—
30
—
ns
ns
TFLT
10
Note 1: These parameters are characterized but not tested in manufacturing.
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PIC24FJ128GL306 FAMILY
TABLE 30-27: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY
Operating Conditions:
2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Maximum Data
Rate Typ.(1)
Mode
CKE
CKP
SMP
Master Transmit Only (Half-Duplex)
Master Transmit/Receive (Full-Duplex)
0,1
0,1
0,1
0,1
0,1
0,1
0,1
0
25 MHz
11 MHz
21 MHz
11 MHz
1
Slave Transmit/Receive (Full-Duplex)
0,1
Note 1: These parameters are characterized but not tested in manufacturing.
FIGURE 30-16:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP35
SP10
SCKx
(CKP = 1)
SDOx
SDIx
MSb
LSb
MSb In
SP40 SP41
LSb In
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FIGURE 30-17:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP10
SCKx
(CKP = 1)
SP35
SDOx
SDIx
MSb
LSb
MSb In
SP41
LSb In
SP40
DS30010198B-page 368
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PIC24FJ128GL306 FAMILY
TABLE 30-28: SPIx MODULE MASTER MODE TIMING REQUIREMENTS
Operating Conditions:
2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.
No.
Symbol
Characteristics(1)
Min
Max
Units
SP10
TSCL, TSCH
SCKx Output Low or High Time
20
—
—
7
ns
ns
SP35
SP36
SP40
SP41
TSCH2DOV,
TSCL2DOV
SDOx Data Output Valid After SCKx Edge
TDOV2SC,
TDOV2SCL
SDOx Data Output Setup to First SCKx Edge
Setup Time of SDIx Data Input to SCKx Edge
Hold Time of SDIx Data Input to SCKx Edge
7
7
7
—
—
—
ns
ns
ns
TDIV2SCH,
TDIV2SCL
TSCH2DIL,
TSCL2DIL
Note 1: These parameters are characterized but not tested in manufacturing.
FIGURE 30-18:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP70
SCKx
(CKP = 1)
SP35
SDOx
SDIx
MSb
LSb
SP51
MSb In
SP41
LSb In
SP40
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FIGURE 30-19:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP70
SCKx
(CKP = 1)
SP35
MSb
LSb
SDOx
SDIx
SP51
MSb In
SP41
LSb In
SP40
TABLE 30-29: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param.No.
Symbol
Characteristics(1)
Min
Max
Units
SP70
SP35
TSCL, TSCH
SCKx Input Low Time or High Time
45
—
—
ns
ns
TSCH2DOV,
TSCL2DOV
SDOx Data Output Valid After SCKx Edge
10
SP40
SP41
SP50
TDIV2SCH,
TDIV2SCL
Setup Time of SDIx Data Input to SCKx Edge
Hold Time of SDIx Data Input to SCKx Edge
SSx to SCKx or SCKx Input
0
7
—
—
—
ns
ns
ns
TSCH2DIL,
TSCL2DIL
TSSL2SCH,
TSSL2SCL
40
SP51
SP52
TSSH2DOZ
SSx to SDOx Output High-Impedance
SSx After SCKx Edge
2.5
10
12
—
ns
ns
TSCH2SSH,
TSCL2SSH
SP60
TSSL2DOV
SDOx Data Output Valid After SSx Edge
—
12.5
ns
Note 1: These parameters are characterized but not tested in manufacturing.
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FIGURE 30-20:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Start Condition
Note: Refer to Figure 30-8 for load conditions.
Stop Condition
FIGURE 30-21:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM33
IM10
IM25
SDAx
In
IM45
IM40
IM40
SDAx
Out
Note: Refer to Figure 30-8 for load conditions.
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TABLE 30-30: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristics
Min.(1)
Max.
Units
Conditions
IM10 TLO:SCL Clock Low Time 100 kHz mode TCY * (BRG + 2)
400 kHz mode TCY * (BRG + 2)
—
—
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
µs
µs
µs
pF
pF
pF
ns
1 MHz mode
TCY * (BRG + 2)
—
IM11 THI:SCL ClockHighTime 100 kHz mode TCY * (BRG + 2)
400 kHz mode TCY * (BRG + 2)
—
—
1 MHz mode
TCY * (BRG + 2)
—
IM20 TF:SCL SDAx and SCLx 100 kHz mode
—
300
300
100
1000
300
300
—
Fall Time
400 kHz mode
20 + 0.1 CB
1 MHz mode
—
IM21 TR:SCL SDAx and SCLx 100 kHz mode
—
Rise Time
400 kHz mode
20 + 0.1 CB
1 MHz mode
—
250
100
100
0
IM25 TSU:DAT Data Input
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
—
—
IM26 THD:DAT Data Input
Hold Time
—
0
0.9
0.3
—
0
IM30 TSU:STA Start Condition 100 kHz mode TCY * (BRG + 2)
Only relevant for Repeated
Start condition
Setup Time
400 kHz mode TCY * (BRG + 2)
—
1 MHz mode
TCY * (BRG + 2)
—
IM31 THD:STA Start Condition 100 kHz mode TCY * (BRG + 2)
—
After this period, the first clock
pulse is generated
Hold Time
400 kHz mode TCY * (BRG + 2)
—
1 MHz mode
TCY * (BRG + 2)
—
IM33 TSU:STO Stop Condition 100 kHz mode TCY * (BRG + 2)
—
Setup Time
400 kHz mode TCY * (BRG + 2)
—
1 MHz mode
TCY * (BRG + 2)
—
IM34 THD:STO Stop Condition 100 kHz mode TCY * (BRG + 2)
—
Hold Time
400 kHz mode TCY * (BRG + 2)
—
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
TCY * (BRG + 2)
—
IM40 TAA:SCL Output Valid
from Clock
—
—
3500
1000
350
—
—
IM45 TBF:SDA Bus Free Time 100 kHz mode
4.7
1.3
0.5
—
The amount of time the bus
must be free before a new
transmission can start
400 kHz mode
1 MHz mode
—
—
IM50 CB
Bus Capacitive 100 kHz mode
400
400
10
Loading
400 kHz mode
—
1 MHz mode
—
IM51 TPGD
Pulse Gobbler Delay
52
312
Note 1: BRG is the value of the I2C Baud Rate Generator.
DS30010198B-page 372
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PIC24FJ128GL306 FAMILY
FIGURE 30-22:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Start
Condition
Stop
Condition
Note: Refer to Figure 30-8 for load conditions.
FIGURE 30-23:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS33
IS25
SDAx
In
IS45
IS40
IS40
SDAx
Out
Note: Refer to Figure 30-8 for load conditions.
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PIC24FJ128GL306 FAMILY
TABLE 30-31: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristics
Min.
Max.
Units
Conditions
IS10
IS11
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
T
T
T
T
T
T
T
T
T
T
T
T
LO
:
SCL Clock Low Time 100 kHz mode
4.7
1.3
0.5
4.0
0.6
0.5
—
—
—
µs CPU clock must be minimum 800 kHz
400 kHz mode
µs CPU clock must be minimum 3.2 MHz
1 MHz mode
—
µs
HI:SCL Clock High Time 100 kHz mode
—
µs CPU clock must be minimum 800 kHz
400 kHz mode
—
µs CPU clock must be minimum 3.2 MHz
1 MHz mode
—
µs
F:SCL
SDAx and SCLx 100 kHz mode
Fall Time
300
300
100
1000
300
300
—
ns
400 kHz mode 20 + 0.1 C
B
ns
1 MHz mode
—
—
ns
R:SCL
SDAx and SCLx 100 kHz mode
Rise Time
ns
400 kHz mode 20 + 0.1 C
B
ns
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
—
250
100
100
0
ns
SU
:
DAT Data Input
ns
Setup Time
—
ns
—
ns
HD
:
DAT Data Input
—
ns
Hold Time
0
0.9
0.3
—
µs
0
µs
SU
:
STA Start Condition 100 kHz mode
4700
600
250
4000
600
250
4000
600
600
4000
600
250
0
ns Only relevant for Repeated Start
Setup Time
condition
400 kHz mode
—
ns
1 MHz mode
—
ns
HD
:
STA Start Condition 100 kHz mode
—
ns After this period, the first clock pulse is
Hold Time
generated
400 kHz mode
—
ns
1 MHz mode
—
ns
SU
:
STO Stop Condition
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
100 kHz mode
400 kHz mode
1 MHz mode
—
ns
Setup Time
—
ns
—
ns
HD
:
STO Stop Condition
—
ns
Hold Time
—
ns
—
ns
AA:
SCL Output Valid
3500
1000
350
—
ns
from Clock
0
ns
0
ns
BF
:
SDA Bus Free Time 100 kHz mode
4.7
1.3
0.5
—
µs The amount of time the bus must be
free before a new transmission can
start
µs
400 kHz mode
—
µs
1 MHz mode
—
C
B
Bus Capacitive 100 kHz mode
400
400
10
pF
pF
pF
Loading
400 kHz mode
—
1 MHz mode
—
DS30010198B-page 374
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TABLE 30-32: A/D MODULE SPECIFICATIONS
Operating Conditions:
2.0V to 3.6V (unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01 AVDD
AD02 AVSS
Module VDD Supply
Module VSS Supply
Greater of:
VDD – 0.3
or 2.2
—
—
Lesser of:
VDD + 0.3
or 3.6
V
V
VSS – 0.3
VSS + 0.3
Reference Inputs
AD05 VREFH
AD06 VREFL
AD07 VREF
Reference Voltage High AVSS + 1.7
—
—
—
AVDD
V
V
V
Reference Voltage Low
AVSS
AVDD – 1.7
AVDD + 0.3
Absolute Reference
Voltage
AVSS – 0.3
Analog Inputs
AD10 VINH-VINL Full-Scale Input Span
VREFL
—
—
—
VREFH
AVDD + 0.3
AVDD/3
V
V
V
(Note 2)
AD11 VIN
AD12 VINL
Absolute Input Voltage
AVSS – 0.3
AVSS – 0.3
Absolute VINL Input
Voltage
AD13
Leakage Current
—
—
±1.0
—
±610
2.5k
nA
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3V,
Source Impedance = 2.5 k
AD17 RIN
Recommended
10-bit
Impedance of Analog
Voltage Source
A/D Accuracy
AD20B Nr
Resolution
—
—
12
±1
—
bits
AD21B INL
Integral Nonlinearity
< ±2
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V,
Conversion Rate = 125 ksps
AD22B DNL
AD23B GERR
AD24B EOFF
AD25B
Differential Nonlinearity
Gain Error
—
—
—
—
±0.5
±0.6
±0.5
—
< ±1(3)
-2 to +5
-2 to +4
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V,
Conversion Rate = 125 ksps
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V,
Conversion Rate = 125 ksps
Offset Error
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V,
Conversion Rate = 125 ksps
Monotonicity(1)
—
Guaranteed
Note 1: The A/D conversion result never decreases with an increase in the input voltage.
2: Measurements are taken with the external VREF+ and VREF- used as the A/D voltage reference.
3: Code 2047 can have a DNL error of 1 LSb to <1.5 LSb and code 3071 can have a DNL error of 1 LSb
to <2.5 LSb.
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DS30010198B-page 375
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TABLE 30-33: A/D CONVERSION TIMING REQUIREMENTS(1)
Operating Conditions:
Operating temperature
2.0V to 3.6V (unless otherwise stated)
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristic
Min.
Typ
Max.
Units
Conditions
Clock Parameters
AD50
AD51
TAD
tRC
A/D Clock Period
178
—
—
—
—
ns
ns
A/D Internal RC Oscillator
Period
269.18
Conversion Rate
AD55
AD55A
AD56
tCONV
FCNV
SAR Conversion Time,
12-Bit Mode
—
16
—
—
TAD
TAD
SAR Conversion Time,
10-Bit Mode
—
14
Throughput Rate
—
—
—
—
400
350
ksps
ksps
AVDD > 2.7V, 10-bit mode
AVDD > 2.7V, 12-bit mode
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
DS30010198B-page 376
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FIGURE 30-24:
10-BIT AND 12-BIT ENOB
10-ꢂit Mode (ENOB)
9.94
9.93
9.92
9.91
9.9
-40C
25C
9.89
9.88
9.87
9.86
9.85
9.84
85C
125C
100
150
200
250
300
350
400
Conversion Rate (ŬƐƉƐ)
12-ꢂit Mode (ENOB)
11.8
11.75
11.7
11.65
11.6
-40C
25C
11.55
11.5
85C
125C
11.45
11.4
100
150
200ꢀ
250ꢀ
300
350
Conversion Rate (ŬƐƉƐ)
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DS30010198B-page 377
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FIGURE 30-25:
12-BIT INL DNL PLOTS
DNL, 12-bit Mode, 100KSPS, Vdd=3.3V
INL, 12-bit Mode, 100KSPS, Vdd=3.3V
0.4
0.3
0.8
0.6
0.4
0.2
0
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.2
-0.4
-0.6
0
0
0
500
500
500
1000
1500
2000
2500
3000
3500
3500
3500
4000
4000
4000
0
500
1000
1500
2000
2500
3000
3500
4000
INL, 12-bit Mode, 250KSPS, Vdd=3.3V
DNL, 12-bit Mode, 250KSPS, Vdd=3.3V
1
0.8
0.6
0.4
0.2
0
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.2
-0.4
-0.6
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
3500
4000
DNL, 12-bit Mode, 350KSPS, Vdd=3.3V
INL, 12-bit Mode, 350KSPS, Vdd=3.3V
1
0.8
0.6
0.4
0.2
0
2
1.5
1
0.5
0
-0.2
-0.4
-0.6
-0.8
-1
-0.5
-1
0
500
1000
1500
2000
2500
3000
3500
4000
1000
1500
2000
2500
3000
-1.2
DS30010198B-page 378
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FIGURE 30-26:
10-BIT INL DNL PLOTS
DNL, 10-bit Mode, 100KSPS, Vdd=3.3V
INL, 10-bit Mode, 100KSPS, Vdd=3.3V
0.1
0.05
0
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.05
-0.1
-0.15
0
200
400
600
800
1000
0
200
400
600
800
1000
DNL, 10-bit Mode, 250KSPS, Vdd=3.3V
INL, 10-bit Mode, 250KSPS, Vdd=3.3V
0.15
0.1
0.2
0.15
0.1
0.05
0
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.05
-0.1
-0.15
0
200
400
600
800
1000
0
200
400
600
800
1000
DNL, 10-bit Mode, 400KSPS, Vdd=3.3V
INL, 10-bit Mode, 400KSPS, Vdd=3.3V
0.25
0.2
0.3
0.2
0.1
0
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.1
-0.2
-0.3
0
200
400
600
800
1000
0
200
400
600
800
1000
2019-2020 Microchip Technology Inc.
DS30010198B-page 379
FIGURE 30-27:
GAIN AND OFFSET VOLTAGES
10-Bit Mode (Oīset)
12-Bit Mode (Oīset)
0.4
0.7
0.6
0.5
0.4
0.3
0.2
0.1
і
ChgPp Ebld
ї
і
ChgPp Ebld
ї
0.35
0.3
-40C
25C
-40C
25C
0.25
0.2
85C
85C
125C
125C
0.15
0.1
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
VDD (V)
3
3.1 3.2 3.3 3.4 3.5 3.6
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
VDD (V)
3
3.1 3.2 3.3 3.4 3.5 3.6
10-Bit Mode (Gain)
12-Bit Mode (Gain)
1.4
1.2
1
1.6
1.4
1.2
1
і
rgd
ї
і
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ї
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
-40C
25C
-40C
25C
85C
85C
125C
125C
2
21 22 23 24 25 26 27 2.8 2.9
3
3.1 3.2 3.3 3.4 3.5 3.6
7 2.8 2.9
VDD (V)
3
3.1 3.2 3.3 3.4 3.5 3.6
-0.2
-0.4
-0.2
-0.4
VDD (V)
PIC24FJ128GL306 FAMILY
31.0 PACKAGING INFORMATION
31.1 Package Marking Information
28-Lead QFN (6x6 mm)
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
24FJ128
GL302
1910017
28-Lead UQFN (4x4x0.6 mm)
Example
XXXXX
XXXXXX
PIC24
FJ128
GL302
1910017
XXXXXX
YYWWNNN
28-Lead SOIC (7.50 mm)
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
PIC24FJ128GL302
1910017
YYWWNNN
28-Lead SSOP (5.30 mm)
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC24FJ128
GL302
YYWWNNN
1910017
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2019-2020 Microchip Technology Inc.
DS30010198B-page 381
PIC24FJ128GL306 FAMILY
31.1 Package Marking Information (Continued)
36-Lead UQFN (5x5 mm)
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
24FJ128
GL303
1910017
48-Lead UQFN (6x6 mm)
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
24FJ128
GL305
1910017
Example
48-Lead TQFP (7x7x1.0 mm)
FJ128GL
3051910
017
XXXXXXX
XXXYYWW
NNN
64-Lead QFN (9x9x0.9 mm)
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
24FJ128
GL306
1910017
64-Lead TQFP (10x10x1 mm)
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC24FJ128
GL306
1920017
DS30010198B-page 382
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
31.2 Package Details
The following sections give the technical details of the packages.
2019-2020 Microchip Technology Inc.
DS30010198B-page 383
PIC24FJ128GL306 FAMILY
DS30010198B-page 384
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
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2019-2020 Microchip Technology Inc.
DS30010198B-page 385
PIC24FJ128GL306 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS30010198B-page 386
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019-2020 Microchip Technology Inc.
DS30010198B-page 387
PIC24FJ128GL306 FAMILY
DS30010198B-page 388
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019-2020 Microchip Technology Inc.
DS30010198B-page 389
PIC24FJ128GL306 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS30010198B-page 390
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019-2020 Microchip Technology Inc.
DS30010198B-page 391
PIC24FJ128GL306 FAMILY
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DS30010198B-page 392
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
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2019-2020 Microchip Technology Inc.
DS30010198B-page 393
PIC24FJ128GL306 FAMILY
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DS30010198B-page 394
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
36-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M5) - 5x5 mm Body [UQFN]
With Corner Anchors
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
SEE
DETAIL A
B
E
NOTE 1
N
1
2
(DATUM B)
(DATUM A)
2X
0.10 C
2X
A
0.10 C
0.10 C
TOP VIEW
36X
0.08 C
0.10
C A B
SEATING
PLANE
C
D2
SIDE VIEW
0.10
C A B
E2
K
2
1
NOTE 1
N
L
16X b
0..07
0.05
C A B
C
e
BOTTOM VIEW
Microchip Technology Drawing C04-436–M5 Rev B Sheet 1 of 2
2019-2020 Microchip Technology Inc.
DS30010198B-page 395
PIC24FJ128GL306 FAMILY
36-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M5) - 5x5 mm Body [UQFN]
With Corner Anchors
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(A3)
A
C
SEATING
PLANE
A1
DETAIL A
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Terminal Width
Terminal Length
N
36
0.40 BSC
0.55
e
A
A1
A3
D
D2
E
E2
b
L
0.50
0.00
0.60
0.05
0.02
0.152 REF
5.00 BSC
3.70
5.00 BSC
3.70
3.60
3.80
3.60
0.15
0.30
3.80
0.25
0.50
0.20
0.40
Terminal-to-Exposed-Pad
K
0.25 REF
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-436–M5 Rev B Sheet 2 of 2
DS30010198B-page 396
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
36-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M5) - 5x5 mm Body [UQFN]
With Corner Anchors
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
36
Y3
1
2
ØV
Y2
C2
EV
G
Y1
R
X3
X1
E
SILK SCREEN
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Contact Pitch
E
0.40 BSC
Center Pad Width
Center Pad Length
X2
Y2
C1
C2
X1
Y1
X3
Y3
R
3.80
3.80
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width (X36)
Contact Pad Length (X36
Corner Pad Width (X4)
Corner Pad Length (X4)
Corner Pad Radius
5.00
5.00
0.20
0.80
0.85
0.85
0.10
Contact Pad to Center Pad (X36)
Thermal Via Diameter
Thermal Via Pitch
G
V
EV
0.20
0.30
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2436–M5 Rev B
2019-2020 Microchip Technology Inc.
DS30010198B-page 397
PIC24FJ128GL306 FAMILY
48-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M4) - 6x6 mm Body [UQFN]
With Corner Anchors and 4.6x4.6 mm Exposed Pad
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
A1
52X
0.08 C
0.10 C
D
A
B
E
NOTE 1
N
1
2
(DATUM B)
(DATUM A)
2X
0.10 C
2X
0.10 C
(A3)
TOP VIEW
A
SEATING
PLANE
8X (b1)
C
0.10
C A B
D2
SIDE VIEW
0.10
C A B
8X (b2)
E2
e
2
2
1
NOTE 1
N
(K)
L
48X b
0.07
0.05
C A B
C
e
BOTTOM VIEW
Microchip Technology Drawing C04-442A-M4 Sheet 1 of 2
DS30010198B-page 398
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
48-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M4) - 6x6 mm Body [UQFN]
With Corner Anchors and 4.6x4.6 mm Exposed Pad
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Terminal Width
Corner Anchor Pad
N
48
0.40 BSC
0.55
e
A
A1
A3
D
D2
E
E2
b
b1
0.50
0.00
0.60
0.05
0.02
0.15 REF
6.00 BSC
4.60
6.00 BSC
4.60
4.50
4.70
4.50
0.15
4.70
0.25
0.20
0.45 REF
0.23 REF
0.40
Corner Anchor Pad, Metal-free Zone
Terminal Length
b2
L
0.35
0.45
Terminal-to-Exposed-Pad
K
0.30 REF
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-442A-M4 Sheet 2 of 2
2019-2020 Microchip Technology Inc.
DS30010198B-page 399
PIC24FJ128GL306 FAMILY
48-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M4) - 6x6 mm Body [UQFN]
With Corner Anchors and 4.6x4.6 mm Exposed Pad
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
R
48
Y3
1
2
ØV
G2
Y2
EV
C2
G1
Y1
SILK SCREEN
X1
X3
E
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Contact Pitch
E
0.40 BSC
Center Pad Width
X2
Y2
C1
C2
X1
Y1
X3
Y3
R
4.70
4.70
Center Pad Length
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width (X48)
Contact Pad Length (X48)
Corner Anchor Pad Width (X4)
Corner Anchor Pad Length (X4)
Pad Corner Radius (X 20)
Contact Pad to Center Pad (X48)
Contact Pad to Contact Pad
Thermal Via Diameter
6.00
6.00
0.20
0.80
0.90
0.90
0.10
G1
G2
V
0.25
0.20
0.33
1.20
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2442A-M4
DS30010198B-page 400
2019-2020 Microchip Technology Inc.
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48-Lead Plastic Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1
2
D
2
D
E1
2
A
B
E
E1
A
A
NOTE 1
E
2
N
N/4 TIPS
0.20 C A-B D
1
2
3
e
2
0.20 C A-B D 4X
e
TOP VIEW
C
A2
A1
A
SEATING
PLANE
48X
0.08 C
48X b
0.08
C A-B D
SIDE VIEW
Microchip Technology Drawing C04-300-PT Rev D Sheet 1 of 2
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48-Lead Plastic Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
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ࣄ
2 ࣄ
1 R2
R1
H
c
ࣄ
2 ࣄ
L
(L1)
SECTION A-A
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Terminals
Pitch
N
e
48
0.50 BSC
Overall Height
Standoff
Molded Package Thickness
Overall Length
Molded Package Length
Overall Width
A
A1
A2
D
D1
E
-
-
-
1.20
0.15
1.05
0.05
0.95
1.00
9.00 BSC
7.00 BSC
9.00 BSC
Molded Package Width
Terminal Width
Terminal Thickness
Terminal Length
Footprint
Lead Bend Radius
Lead Bend Radius
Foot Angle
E1
b
7.00 BSC
0.22
0.17
0.09
0.45
0.27
0.16
0.75
c
-
L
0.60
1.00 REF
L1
R1
R2
ࣄ
ࣄ
1 ࣄ
2 0.08
0.08
0°
0°
11°
-
-
-
0.20
7°
3.5°
-
12°
Lead Angle
Mold Draft Angle
-
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-300-PT Rev D Sheet 2 of 2
DS30010198B-page 402
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48-Lead Plastic Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
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C1
G
C2
SILK SCREEN
48
Y1
1 2
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
E
0.50 BSC
8.40
8.40
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width (X48)
C1
C2
X1
0.30
1.50
Contact Pad Length (X48)
Distance Between Pads
Y1
G
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2300-PT Rev D
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DS30010198B-page 403
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DS30010198B-page 404
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DS30010198B-page 406
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64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1/2
D
NOTE 2
E1/2
A
B
E1
E
A
A
SEE DETAIL 1
4X N/4 TIPS
N
1
3
0.20 C A-B D
2
4X
NOTE 1
0.20 H A-B D
TOP VIEW
A2
A
0.05
C
SEATING
PLANE
A1
C A-B D
64 X b
0.08
0.08 C
e
SIDE VIEW
Microchip Technology Drawing C04-085C Sheet 1 of 2
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64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
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H
c
E
T
L
(L1)
X=A—B OR D
X
SECTION A-A
e/2
DETAIL 1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
64
0.50 BSC
-
1.00
-
MAX
Number of Leads
Lead Pitch
Overall Height
N
e
A
-
1.20
1.05
0.15
0.75
Molded Package Thickness
Standoff
A2
A1
L
0.95
0.05
0.45
Foot Length
0.60
Footprint
Foot Angle
L1
I
1.00 REF
3.5°
0°
7°
Overall Width
Overall Length
E
D
E1
D1
c
b
D
E
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
-
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
0.09
0.17
11°
0.20
0.27
13°
0.22
12°
12°
11°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085C Sheet 2 of 2
DS30010198B-page 408
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64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
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C1
E
C2
G
Y1
X1
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
0.50 BSC
11.40
MIN
0.20
MAX
Contact Pitch
E
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width (X28)
Contact Pad Length (X28)
Distance Between Pads
C1
C2
X1
Y1
G
11.40
0.30
1.50
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2085B Sheet 1 of 1
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DS30010198B-page 409
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NOTES:
DS30010198B-page 410
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APPENDIX A: REVISION HISTORY
Revision A (March 2019)
Original data sheet for the PIC24FJ128GL306 family of
devices.
Revision B (July 2020)
This revision incorporates the following updates:
• Registers:
- Updates Register 7-1, Register 18-8,
Register 18-9, Register 18-10,
Register 18-11, Register 25-1 and
Register 27-8.
• Tables:
- Updates Table 8-2, Table 8-3, Table 8-4,
Table 8-5, Table 10-1, Table 30-4, Table 30-
8, Table 30-12, Table 30-17, Table 30-18,
Table 30-19, Table 30-32 and Table 30-33.
- Adds Table 30-27.
• Figures:
- Updates Figure 9-1, Figure 18-1 and
Figure 25-1.
- Adds Figure 30-2, Figure 30-24,
Figure 30-25, Figure 30-26 and Figure 30-27.
• Sections:
- Updates Analog Features, Peripheral
Features, Section 6.4 “Error Correcting
Code (ECC)” and Section 29.0
“Development Support”.
- Adds Section 7.4 “Low-Power BOR
(LPBOR)”, Section 9.5 “Fail-Safe Clock
Monitoring”, Section 9.8 “Primary
Oscillator (PRI or POSC)” and Section 9.9
“Low-Power RC (LPRC) Oscillator”.
- Adds -40ºC to +125ºC Extended temperature
information to Section 30.0 “Electrical
Characteristics”.
2019-2020 Microchip Technology Inc.
DS30010198B-page 411
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NOTES:
DS30010198B-page 412
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INDEX
Individual Comparator Configurations,
CREF = 1, CVREFP = 0................................... 290
Individual Comparator Configurations,
A
A/D
Control Registers ...................................................... 275
CREF = 1, CVREFP = 1................................... 291
Input Capture x Module ............................................ 170
LCD Controller Module............................................. 220
MCLR Pin Connection Example................................. 22
On-Chip Regulator Connections............................... 324
Oscillator Circuit Placement ....................................... 25
Output Compare x Module ....................................... 169
PIC24F CPU Core...................................................... 28
PIC24FJ128GL306 Family (General)......................... 17
PLL Module .............................................................. 107
PSV Operation (Lower Word)..................................... 51
PSV Operation (Upper Word)..................................... 51
Recommended Minimum Connections....................... 21
Reference Clock Generator...................................... 108
Reset System ............................................................. 75
RTCC Module........................................................... 236
Shared I/O Port Structure......................................... 125
SPIx Master, Frame Master Connection .................. 199
SPIx Master, Frame Slave Connection .................... 200
SPIx Master/Slave Connection
(Enhanced Buffer Modes)................................. 198
SPIx Master/Slave Connection (Standard Mode)..... 197
SPIx Module (Enhanced Mode)................................ 183
SPIx Slave, Frame Master Connection .................... 200
SPIx Slave, Frame Slave Connection ...................... 200
System Clock.............................................................. 95
Timer Clock Generator ............................................. 166
Timer2/3 and Timer4/5 (32-Bit) ................................ 160
Triple Comparator Module........................................ 289
UARTx (Simplified)................................................... 210
Watchdog Timer (WDT)............................................ 326
Extended DMA Operations ....................................... 273
Operation .................................................................. 271
Transfer Functions
10-Bit ................................................................ 288
12-Bit ................................................................ 287
AC Characteristics
A/D Conversion Timing Requirements...................... 376
A/D Specifications..................................................... 375
and Timing Parameters............................................. 358
Capacitive Loading on Output Pins........................... 358
CLKO and I/O Timing Requirements ........................ 362
External Clock Timing Requirements........................ 359
I2Cx Bus Data Requirements (Master Mode)........... 372
I2Cx Bus Data Requirements (Slave Mode)............. 374
Internal RC Accuracy................................................ 360
Load Conditions for Device Timing........................... 358
MCCP Input Capture x Mode Requirements ............ 366
MCCP PWM Mode Requirements ............................ 366
MCCP Timer Mode Requirements............................ 365
Phase-Locked Loop Mode Specifications................. 360
RC Oscillator Start-up Time...................................... 361
Reset and Brown-out Reset Requirements .............. 363
SPIx Master Mode Requirements............................. 369
SPIx Maximum Data/Clock Rate Summary .............. 367
SPIx Module Slave Mode Timing Requirements ...... 370
Timer1 External Clock Timing................................... 364
Analog/Digital Pins Configuration During ICSP .................. 26
B
Block Diagrams
12-Bit A/D Converter................................................. 272
12-Bit A/D Converter Analog Input Model................. 286
16-Bit Asynchronous Timer3/Timer5 ........................ 161
16-Bit Synchronous Timer2/Timer4 .......................... 161
16-Bit Timer1 Module................................................ 157
32-Bit Timer Mode .................................................... 168
Access Program Memory Using
Table Instructions ............................................... 49
Addressing for Table Registers................................... 61
Buffer Address Generation in PIA Mode................... 274
CALL Stack Frame...................................................... 47
CLCx Input Source Selection.................................... 263
CLCx Logic Function Combinatorial Options............ 262
CLCx Module ............................................................ 261
Comparator Voltage Reference ................................ 295
Conceptual MCCPx Module...................................... 165
CPU Programmer’s Model.......................................... 29
CRC Module ............................................................. 255
CRC Shift Engine Detail............................................ 255
Data Access from Program Space Address
C
Capture/Compare/PWM/Timer
Auxiliary Output ........................................................ 171
General Purpose Timer ............................................ 167
Input Capture Mode.................................................. 170
Output Compare Mode............................................. 168
Synchronization Sources.......................................... 175
Time Base Generator ............................................... 166
Capture/Compare/PWM/Timer (MCCP) ........................... 165
Character Graphs
10-Bit and 12-Bit ENOB............................................ 377
10-Bit INL DNL Plots ................................................ 379
12-Bit INL DNL Plots ................................................ 378
FRC Accuracy Over Temperature and VDD ............. 361
Gain and Offset Voltages ......................................... 380
I/O VOH vs. IOL.......................................................... 352
I/O VOL vs. IOL .......................................................... 351
IPD vs. Temperature, Page 1.................................... 345
IPD vs. Temperature, Page 2.................................... 346
RC15, RB15 VOH vs. IOL .......................................... 354
RC15, RB15 VOL vs. IOL........................................... 353
CLC
Generation .......................................................... 48
Deadman Timer ........................................................ 299
DMA Module ............................................................... 53
Dual 16-Bit Timer Mode............................................ 167
High/Low-Voltage Detect (HLVD) ............................. 297
I2Cx Module.............................................................. 202
Individual Comparator Configurations,
Control Registers...................................................... 264
Module-Specific Input Sources................................. 267
CREF = 0.......................................................... 290
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Code Examples
High/Low-Voltage Detect.......................................... 356
I/O Pin Input Specifications....................................... 349
I/O Pin Output Specifications.................................... 350
Idle Current (IIDLE) .................................................... 343
Internal Voltage Regulator Specifications................. 355
Operating Current (IDD) ............................................ 342
Power-Down Current (IPD)........................................ 344
Program Memory...................................................... 355
Temperature and Voltage Specifications.................. 341
Thermal Operating Conditions.................................. 340
Thermal Packaging................................................... 340
Basic Clock Switching...............................................106
Configuring UART1 Input/Output Functions .............142
Double-Word Flash Programming (C Language) .......66
EDS Read from Program Memory in Assembly..........50
Erasing a Program Memory Block (C Language) .......63
IOC Status Read/Clear in Assembly.........................129
Port Read/Write in Assembly....................................129
Port Read/Write in C .................................................129
PWRSAV Instruction Syntax.....................................113
Row Programming (C Language) ...............................64
Setting the WRLOCK Bit...........................................237
Code Memory Programming Example
Double-Word Programming ........................................65
Page Erase .................................................................63
Row Writes..................................................................64
Code Protection ................................................................327
Comparator Voltage Reference ........................................295
Configuring................................................................295
Configurable Logic Cell (CLC) ..........................................261
Configurable Logic Cell. See CLC.
Configuration Bits..............................................................307
Core Features .....................................................................15
CPU.....................................................................................27
Arithmetic Logic Unit (ALU).........................................32
Clocking Scheme ........................................................96
Control Registers ........................................................30
Core Registers............................................................28
Programmer’s Model...................................................27
CRC
Deadman Timer
Control Registers...................................................... 300
Deadman Timer (DMT)..................................................... 299
Development Support....................................................... 337
Direct Memory Access Controller. See DMA.
DMA
Channel Trigger Sources............................................ 60
Control Registers........................................................ 56
Peripheral Module Disable (PMD) Registers.............. 56
Summary of Operations.............................................. 54
Types of Data Transfers ............................................. 55
Typical Setup.............................................................. 56
DMA Controller ................................................................... 16
E
Electrical Characteristics .................................................. 339
Absolute Maximum Ratings...................................... 339
V/F Graph (Industrial) ............................................... 340
Equations
16-Bit, 32-Bit CRC Polynomials................................ 256
A/D Conversion Clock Period ................................... 286
Baud Rate Reload Calculation.................................. 203
Relationship Between Device and
Data Shift Direction ...................................................257
Interrupt Operation....................................................257
Polynomials...............................................................256
Setup Examples for 16 and 32-Bit Polynomials........256
Typical Operation......................................................257
User Interface ...........................................................256
Customer Change Notification Service .............................419
Customer Notification Service...........................................419
Customer OTP Memory ....................................................327
Customer Support.............................................................419
Cyclic Redundancy Check. See CRC.
SPIx Clock Speed............................................. 200
UARTx Baud Rate with BRGH = 0 ........................... 211
UARTx Baud Rate with BRGH = 1 ........................... 211
Errata.................................................................................. 12
Error Correcting Code (ECC).............................................. 70
Control Registers........................................................ 71
Fault Injection ............................................................. 70
External Oscillator Pins....................................................... 25
D
F
Data Memory Space ...........................................................36
Extended Data Space (EDS) ......................................46
Memory Map ...............................................................36
Near Data Space ........................................................37
Organization, Alignment..............................................37
SFR Space..................................................................37
Map, 0000h Block ...............................................38
Map, 0100h Block ...............................................39
Map, 0200h Block ...............................................40
Map, 0300h Block ...............................................41
Map, 0400h Block ...............................................42
Map, 0500h Block ...............................................43
Map, 0600h Block ...............................................44
Map, 0700h Block ...............................................45
Software Stack............................................................47
DC Characteristics
Flash OTP by ICSP Write Inhibit ........................................ 74
Flash Program Memory ...................................................... 61
and Table Instructions ................................................ 61
Control Registers........................................................ 67
Double-Word Programming........................................ 65
Enhanced ICSP Operation ......................................... 74
JTAG Operation.......................................................... 74
RTSP Operation ......................................................... 62
Programming...................................................... 62
Programming Algorithm...................................... 62
G
Guidelines for Getting Started with 16-Bit MCUs................ 21
H
High/Low-Voltage Detect (HLVD)..................................... 297
Comparator Specifications........................................357
Comparator Voltage Reference Specifications .........357
Current (BOR, WDT, HLVD, ADC, LCD,
DMT, RTCC).....................................................347
DS30010198B-page 414
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I
M
I/O Ports............................................................................ 125
Analog Port Pins Configuration (ANSELx)................ 126
Configuring Analog/Digital Function of I/O Pins........ 126
Control Registers ...................................................... 130
Open-Drain Configuration......................................... 126
Parallel (PIO) ............................................................ 125
Peripheral Pin Select ................................................ 138
Write/Read Timing .................................................... 126
Memory Organization ......................................................... 33
Program Memory Space............................................. 33
Microchip Internet Website ............................................... 419
N
Near Data Space ................................................................ 37
O
2
On-Chip Voltage Regulator............................................... 324
POR.......................................................................... 324
Standby Mode .......................................................... 324
Oscillator Configuration ...................................................... 95
Clock Switching ........................................................ 105
Sequence ......................................................... 105
Configuration Bit Values for Clock Selection.............. 96
Control Registers........................................................ 97
Initial Configuration on POR....................................... 96
Low-Power RC (LPRC) Oscillator ............................ 108
Modes....................................................................... 107
Primary Oscillator (PRI or POSC) ............................ 108
Reference Clock Output ........................................... 109
Secondary Oscillator Operation................................ 108
Other Special Features....................................................... 16
I C
Clock Rates............................................................... 203
Communicating as Master in Single
Master Environment.......................................... 201
Reserved Addresses................................................. 203
Setting Baud Rate as Bus Master............................. 203
Slave Address Masking ............................................ 203
ICSP Pins............................................................................ 24
ICSP Write Inhibit
Activating .................................................................... 74
In-Circuit Debugger........................................................... 327
Instruction Set
Overview................................................................... 331
Summary................................................................... 329
Symbols Used in Opcode Descriptions..................... 330
Interfacing Program and Data Memory Spaces.................. 47
P
2
Inter-Integrated Circuit. See I C.
Packaging
Internet Address................................................................ 419
Interrupt Controller .............................................................. 81
Alternate Interrupt Vector Table (AIVT) ...................... 81
Control and Status Registers...................................... 87
IEC0-IEC7........................................................... 87
IFS0-IFS7 ........................................................... 87
INTCON1 ............................................................ 87
INTCON2 ............................................................ 87
INTCON4 ............................................................ 87
INTTREG ............................................................ 87
IPC0-IPC29......................................................... 87
Interrupt Vector Details ............................................... 83
Interrupt Vector Table (IVT) ........................................ 81
Reset Sequence ......................................................... 81
Resources................................................................... 87
Interrupt-on-Change (IOC)................................................ 129
Interrupts
Details....................................................................... 383
Marking..................................................................... 381
Peripheral Disable Bits ..................................................... 116
Peripheral Enable Bits...................................................... 116
Peripheral Pin Select (PPS).............................................. 138
Available Peripherals and Pins................................. 138
Configuration Control................................................ 141
Considerations for Selection..................................... 142
Control Registers...................................................... 143
Input Mapping........................................................... 139
Mapping Exceptions ................................................. 141
Output Mapping........................................................ 140
Peripheral Priority..................................................... 138
Selectable Input Sources.......................................... 139
Selectable Output Sources....................................... 140
Pin Descriptions
28-Pin QFN/UQFN Devices.......................................... 3
28-Pin SOIC/SSOP Devices......................................... 4
36-Pin UQFN Devices .................................................. 6
48-Pin TQFN/UQFN Devices ....................................... 8
64-Pin TQFN/QFN Devices........................................ 10
Pin Diagrams ........................................................................ 3
Pinout Description............................................................... 18
Power-Saving Features.................................................... 113
Clock Frequency, Clock Switching ........................... 113
Doze Mode ............................................................... 115
Instruction-Based Modes.......................................... 113
Idle.................................................................... 114
Sleep ................................................................ 113
Low-Voltage Retention Regulator............................. 114
Selective Peripheral Module Control ........................ 116
Product Identification System ........................................... 421
Trap Vectors ............................................................... 82
Vector Tables.............................................................. 82
J
JTAG Interface.................................................................. 327
K
Key Features..................................................................... 307
L
LCD
Control Registers ...................................................... 221
Data Registers/Bits for Segment and COM
Combinations.................................................... 225
Liquid Crystal Display Controller............................... 219
SDATA Registers/Bits for Segment and COM
Combinations.................................................... 234
Segment Availability.................................................. 219
LCD Controller .................................................................... 16
Low-Voltage Retention Regulator..................................... 324
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DS30010198B-page 415
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Program Memory Space
DATEH (RTCC Date High) ....................................... 245
DATEL (RTCC Date Low)......................................... 245
DMACHn (DMA Channel n Control) ........................... 58
DMACON (DMA Engine Control)................................ 57
DMAINTn (DMA Channel n Interrupt)......................... 59
DMTCLR (Deadman Timer Clear)............................ 301
DMTCNTH (Deadman Timer Count High)................ 303
DMTCNTL (Deadman Timer Count Low) ................. 303
DMTCON (Deadman Timer Control) ........................ 300
DMTHOLDREG (DMT Hold)..................................... 306
DMTPRECLR (Deadman Timer Preclear)................ 300
DMTPSCNTH (DMT Post-Configure Count
Access Using Table Instructions.................................49
Addressing ..................................................................47
Configuration Bits
Code-Protect.......................................................35
Overview.............................................................35
Hard Memory Vectors .................................................35
Memory Map ...............................................................34
Organization................................................................35
Reading Data Using EDS ...........................................50
Sizes and Boundaries.................................................34
Program Verification..........................................................327
Status High)...................................................... 304
DMTPSCNTL (DMT Post-Configure Count
R
Real-Time Clock and Calendar (RTCC)............................235
Referenced Sources ...........................................................13
Register Maps
Status Low)....................................................... 304
DMTPSINTVH (DMT Post-Configure Interval
Status High)...................................................... 305
DMTPSINTVL (DMT Post-Configure Interval
Status Low)....................................................... 305
DMTSTAT (Deadman Timer Status) ........................ 302
ECCADDRH (ECC Fault Inject Address
Compare High) ................................................... 72
ECCADDRL (ECC Fault Inject Address
Configuration Registers ............................................309
Interrupt Enable Registers ..........................................85
Interrupt Flag Registers ..............................................85
Interrupt Priority Registers ..........................................86
Peripheral Module Disable (PMD) ............................117
PPS Input Control for RPINR Registers....................154
PPS Output Control for RPOR Registers..................155
Registers
Compare Low).................................................... 72
ECCCONH (ECC Fault Injection
AD1CHITH (A/D Scan Compare Hit High)................284
AD1CHITL (A/D Scan Compare Hit Low) .................284
AD1CHS (A/D Sample Select)..................................282
AD1CON1 (A/D Control 1)........................................275
AD1CON2 (A/D Control 2)........................................277
AD1CON3 (A/D Control 3)........................................279
AD1CON4 (A/D Control 4)........................................280
AD1CON5 (A/D Control 5)........................................281
AD1CSSH (A/D Input Scan Select High)..................285
AD1CSSL (A/D Input Scan Select Low) ...................285
ALMDATEH (RTCC Alarm Date High)......................247
ALMDATEL (RTCC Alarm Date Low) .......................247
ALMTIMEH (RTCC Alarm Time High) ......................246
ALMTIMEL (RTCC Alarm Time Low)........................246
ANCFG (A/D Band Gap Reference
Configuration) ...................................................283
ANSELx (Analog Select for PORTx).........................134
CCPxCON1H (CCPx Control 1 High) .......................174
CCPxCON1L (CCPx Control 1 Low).........................172
CCPxCON2H (CCPx Control 2 High) .......................177
CCPxCON2L (CCPx Control 2 Low).........................176
CCPxCON3H (CCPx Control 3 High) .......................179
CCPxCON3L (CCPx Control 3 Low).........................178
CCPxSTATL (CCPx Status Low)..............................180
CLCxCONH (CLCx Control High).............................265
CLCxCONL (CLCx Control Low) ..............................264
CLCxGLSH (CLCx Gate Logic Input
Select High) ......................................................269
CLCxGLSL (CLCx Gate Logic Input Select Low) .....267
CLCxSEL (CLCx Input MUX Select).........................266
CLKDIV (Clock Divider) ............................................100
CMSTAT (Comparator Module Status).....................293
CMxCON (Comparator x Control,
Comparators 1 Through 3)................................292
CORCON (CPU Core Control).............................. 31, 89
CRCCON1 (CRC Control 1) .....................................258
CRCCON2 (CRC Control 2) .....................................259
CRCXORH (CRC XOR Polynomial High).................260
CRCXORL (CRC XOR Polynomial Low) ..................260
CVRCON (Comparator Voltage
Configuration High)............................................. 71
ECCCONL (ECC Fault Injection
Configuration Low) ............................................. 71
ECCSTATH (ECC System Status Display High)........ 73
ECCSTATL (ECC System Status Display Low) ......... 73
FBSLIM Configuration .............................................. 311
FDEVOPT1 Configuration ........................................ 322
FDMT Configuration ................................................. 321
FDMTCNTH Configuration ....................................... 320
FDMTCNTL Configuration........................................ 320
FDMTIVTH Configuration ......................................... 319
FDMTIVTL Configuration.......................................... 319
FICD Configuration................................................... 318
FOSC Configuration ................................................. 314
FOSCSEL Configuration........................................... 313
FPOR Configuration ................................................. 317
FSEC Configuration.................................................. 310
FSIGN Configuration ................................................ 312
FWDT Configuration................................................. 315
HLVDCON (High/Low-Voltage Detect Control) ........ 298
I2CxCONH (I2Cx Control High)................................ 206
I2CxCONL (I2Cx Control Low) ................................. 204
I2CxMSK (I2Cx Slave Mode Address Mask)............ 208
I2CxSTAT (I2Cx Status) ........................................... 207
INTCON1 (Interrupt Control 1).................................... 90
INTCON2 (Interrupt Control 2).................................... 91
INTCON3 (Interrupt Control 3).................................... 92
INTCON4 (Interrupt Control 4).................................... 92
INTTREG (Interrupt Control and Status) .................... 93
IOCFx (Interrupt-on-Change Flag x)......................... 136
IOCNx (Interrupt-on-Change Negative Edge x)........ 135
IOCPDx (Interrupt-on-Change
Pull-Down Enable x)......................................... 137
IOCPUx (Interrupt-on-Change Pull-up Enable x)...... 136
IOCPx (Interrupt-on-Change Positive Edge x).......... 134
IOCSTAT (Interrupt-on-Change Status)................... 131
LATx (Output Data for PORTx)................................. 133
LCDACTRL (LCD Automatic Control)....................... 228
LCDASTAT (LCD Automatic Status) ........................ 230
LCDCON (LCD Control) ........................................... 221
Reference Control)............................................296
DS30010198B-page 416
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
LCDDATAx (LCD Data x) ......................................... 225
LCDEVENT (LCD Time Event Selection) ................. 233
LCDFC0 (LCD Frame Counter 0) ............................. 232
LCDFC1 (LCD Frame Counter 1) ............................. 232
LCDFC2 (LCD Frame Counter 2) ............................. 233
LCDPS (LCD Phase) ................................................ 223
LCDREF (LCD Reference Ladder Control)............... 226
LCDREG (LCD Charge Pump Control)..................... 222
LCDSDATAx (LCD SDATA x)................................... 234
LCDSEx (LCD Segment x Enable) ........................... 224
NVMADR (Nonvolatile Memory Lower Address) ........ 68
NVMADRU (Nonvolatile Memory Upper Address)...... 68
NVMCON (Nonvolatile Flash Memory Control) .......... 67
NVMKEY (Nonvolatile Memory Key) .......................... 69
ODCx (Open-Drain Enable for PORTx).................... 133
OSCCON (Oscillator Control) ..................................... 98
OSCDIV (Oscillator Divisor)...................................... 103
OSCFDIV (Oscillator Fractional Divisor)................... 104
OSCTUN (FRC Oscillator Tune)............................... 101
PADCON (Port Configuration) .................................. 130
PMD1 (Peripheral Module Disable 1) ....................... 118
PMD3 (Peripheral Module Disable 3) ....................... 119
PMD4 (Peripheral Module Disable 4) ....................... 120
PMD5 (Peripheral Module Disable 5) ....................... 121
PMD6 (Peripheral Module Disable 6) ....................... 122
PMD7 (Peripheral Module Disable 7) ....................... 122
PMD8 (Peripheral Module Disable 8) ....................... 123
PORTx (Input Data for PORTx) ................................ 132
RCON (Reset Control)................................................ 76
REFOCONH (Reference Oscillator Control High) .... 111
REFOCONL (Reference Oscillator Control Low)...... 110
RPINR0 (Peripheral Pin Select Input 0).................... 143
RPINR1 (Peripheral Pin Select Input 1).................... 143
RPINR11 (Peripheral Pin Select Input 11)................ 146
RPINR12 (Peripheral Pin Select Input 12)................ 147
RPINR13 (Peripheral Pin Select Input 13)................ 147
RPINR14 (Peripheral Pin Select Input 14)................ 148
RPINR17 (Peripheral Pin Select Input 17)................ 148
RPINR18 (Peripheral Pin Select Input 18)................ 149
RPINR19 (Peripheral Pin Select Input 19)................ 149
RPINR2 (Peripheral Pin Select Input 2).................... 144
RPINR20 (Peripheral Pin Select Input 20)................ 150
RPINR21 (Peripheral Pin Select Input 21)................ 150
RPINR22 (Peripheral Pin Select Input 22)................ 151
RPINR23 (Peripheral Pin Select Input 23)................ 151
RPINR25 (Peripheral Pin Select Input 25)................ 152
RPINR26 (Peripheral Pin Select Input 26)................ 152
RPINR27 (Peripheral Pin Select Input 27)................ 153
RPINR3 (Peripheral Pin Select Input 3).................... 144
RPINR4 (Peripheral Pin Select Input 4).................... 145
RPINR5 (Peripheral Pin Select Input 5).................... 145
RPINR6 (Peripheral Pin Select Input 6).................... 146
RPORx (Peripheral Pin Select Output x) .................. 153
RTCCON1H (RTCC Control 1 High)......................... 239
RTCCON1L (RTCC Control 1 Low).......................... 238
RTCCON2H (RTCC Control 2 High)......................... 241
RTCCON2L (RTCC Control 2 Low).......................... 240
RTCCON3L (RTCC Control 3 Low).......................... 242
RTCSTATL (RTCC Status Low) ............................... 243
SPIxBRGL (SPIx Baud Rate Generator Low)........... 193
SPIxBUFH (SPIx Buffer High)................................... 192
SPIxBUFL (SPIx Buffer Low).................................... 192
SPIxCON1H (SPIx Control 1 High)........................... 186
SPIxCON1L (SPIx Control 1 Low) ............................ 184
SPIxCON2L (SPIx Control 2 Low) ............................ 188
SPIxIMSKH (SPIx Interrupt Mask High) ................... 195
SPIxIMSKL (SPIx Interrupt Mask Low)..................... 194
SPIxSTATH (SPIx Status High)................................ 191
SPIxSTATL (SPIx Status Low)................................. 189
SPIxURDTH (SPIx Underrun Data High) ................. 196
SPIxURDTL (SPIx Underrun Data Low)................... 196
SR (ALU STATUS)............................................... 30, 88
T1CON (Timer1 Control) .......................................... 158
TIMEH (RTCC Time High)........................................ 244
TIMEL (RTCC Time Low)......................................... 244
TRISx (Output Enable for PORTx) ........................... 132
TSADATEH (RTCC Timestamp A Date High).......... 251
TSADATEL (RTCC Timestamp A Date Low) ........... 250
TSATIMEH (RTCC Timestamp A Time High) .......... 249
TSATIMEL (RTCC Timestamp A Time Low)............ 248
TxCON (Timer2 and Timer4 Control) ....................... 162
TyCON (Timer3 and Timer5 Control) ....................... 164
UxADMD (UARTx Address Detect and Match) ........ 218
UxBRG (UARTx Baud Rate Generator) ................... 218
UxMODE (UARTx Mode) ......................................... 213
UxRXREG (UARTx Receive,
Normally Read-Only)........................................ 217
UxSTA (UARTx Status and Control) ........................ 215
UxTXREG (UARTx Transmit,
Normally Write-Only) ........................................ 217
Resets
BOR (Brown-out Reset).............................................. 75
Brown-out Reset (BOR).............................................. 78
Clock Source Selection .............................................. 78
CM (Configuration Mismatch Reset) .......................... 75
Delay Times................................................................ 79
Device Times.............................................................. 78
IOPUWR (Illegal Opcode Reset)................................ 75
Low-Power BOR (LPBOR) ......................................... 78
MCLR (Master Clear Pin Reset)................................. 75
POR (Power-on Reset)............................................... 75
RCON Flags, Operation ............................................. 77
SFR States ................................................................. 78
SWR (RESETInstruction) ........................................... 75
TRAPR (Trap Conflict Reset) ..................................... 75
UWR (Uninitialized W Register Reset)....................... 75
WDT (Watchdog Timer Reset) ................................... 75
Revision History................................................................ 411
RTCC
Alarm Configuration.................................................. 252
Alarm Mask Settings (Figure)................................... 253
Alarm Value Registers.............................................. 246
Calibration ................................................................ 252
Clock Source Selection ............................................ 237
Control Registers...................................................... 238
Event Timestamping................................................. 254
Module Registers...................................................... 237
Power Control........................................................... 253
Register Mapping ..................................................... 237
RTCVAL Register Mappings .................................... 241
Source Clock ............................................................ 235
Timestamp Registers................................................ 248
Value Registers ........................................................ 244
Write Lock................................................................. 237
2019-2020 Microchip Technology Inc.
DS30010198B-page 417
PIC24FJ128GL306 FAMILY
S
U
Serial Peripheral Interface (SPI) .......................................181
Serial Peripheral Interface. See SPI.
Software Stack....................................................................47
Special Features ...............................................................307
SPI
UART................................................................................ 209
Baud Rate Generator (BRG) .................................... 211
Infrared Support........................................................ 212
Operation of UxCTS and UxRTS Pins...................... 212
Receiving
Audio Mode Operation ..............................................183
Control Registers ......................................................184
Master Mode Operation ............................................182
Slave Mode Operation ..............................................182
Summary of Low-Power Sleep Modes..............................114
8-Bit or 9-Bit Data Mode................................... 212
Transmitting
8-Bit Data Mode................................................ 212
9-Bit Data Mode................................................ 212
Break and Sync Sequence............................... 212
Unique Device Identifier (UDID) ....................................... 323
Universal Asynchronous Receiver Transmitter. See UART.
Unused I/Os........................................................................ 26
T
Timer1...............................................................................157
Timer2/3 and Timer4/5......................................................159
Timing Diagrams
V
CLKO and I/O Characteristics...................................362
External Clock...........................................................359
I2Cx Bus Data (Master Mode) ..................................371
I2Cx Bus Data (Slave Mode) ....................................373
I2Cx Bus Start/Stop Bits (Master Mode)...................371
I2Cx Bus Start/Stop Bits (Slave Mode).....................373
MCCP Input Capture x Mode....................................366
MCCP PWM Mode Characteristics...........................366
MCCP Timer Mode External Clock...........................365
SPIx Master Mode (CKE = 0)....................................367
SPIx Master Mode (CKE = 1)....................................368
SPIx Slave Mode (CKE = 0)......................................369
SPIx Slave Mode (CKE = 1)......................................370
Timer1 External Clock Characteristics......................364
Triple Comparator .............................................................289
Triple Comparator Module ................................................289
Voltage Regulator Pin (VCAP) ............................................. 23
W
Watchdog Timer (WDT).................................................... 325
Control Register........................................................ 325
Windowed Operation ................................................ 325
WWW Address ................................................................. 419
WWW, On-Line Support ..................................................... 12
DS30010198B-page 418
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the website
at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2019-2020 Microchip Technology Inc.
DS30010198B-page 419
PIC24FJ128GL306 FAMILY
NOTES:
DS30010198B-page 420
2019-2020 Microchip Technology Inc.
PIC24FJ128GL306 FAMILY
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PIC 24 FJ 128 GL3 06 T - I / PT - XXX
a)
b)
PIC24FJ128GL306-I/PT:
PIC24F General Purpose Device, 64-Pin,
Industrial Temp., TQFP Package.
Microchip Trademark
Architecture
PIC24FJ128GL302-I/ML:
PIC24F General Purpose Device, 28-Pin,
Industrial Temp., QFN Package
Flash Memory Family
Program Memory Size (Kbytes)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture
24 = 16-Bit Modified Harvard without DSP
Flash Memory Family FJ = Flash Program Memory
Pin Count
02 = 28-pin (QFN, UQFN, SOIC, SSOP)
03 = 36-pin (UQFN)
05 = 48-pin (UQFN, TQFP)
06 = 64-pin (QFN, TQFP)
Temperature Range
Package
I
E
=
-40C to +85C (Industrial)
= -40C to +125C (Extended)
ML = 28-Lead (6x6 mm) QFN (Plastic Quad Flat)
MV = 28-Lead (4x4x.5 mm) UQFN (Plastic Ultra Thin Quad Flat)
SO = 28-Lead (7.50 mm) SOIC (Plastic Small Outline)
SS = 28-Lead (5.30 mm) SSOP (Plastic Shrink Small Outline)
M5 = 36-Lead (5x5 mm) UQFN (Ultra Thin Plastic Quad Flat)
M4 = 48-Lead (6x6 mm) UQFN (Ultra Thin Plastic Quad Flat)
PT = 48-Lead (7x7x1 mm) TQFP (Thin Quad Flatpack)
MR = 64-Lead (9x9x.9 mm) QFN (Plastic Quad Flat)
PT = 64-Lead (10x10x1 mm) TQFP (Plastic Thin Quad Flatpack
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
ES = Engineering Sample
2019-2020 Microchip Technology Inc.
DS30010198B-page 421
PIC24FJ128GL306 FAMILY
NOTES:
DS30010198B-page 422
2019-2020 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019-2020, Microchip Technology Incorporated, All Rights
Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
ISBN: 978-1-5224-6339-9
2019-2020 Microchip Technology Inc.
DS30010198B-page 423
Worldwide Sales and Service
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DS30010198B-page 424
2019-2020 Microchip Technology Inc.
02/28/20
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SI9137DB
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