PIC24HJ128GP804-H/ML

PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04

Data Sheet

High-Performance,

16-bit Microcontrollers

DS70293F

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC³²logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, chipKIT,

chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,

FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,

Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,

MPLINK, mTouch, Omniscient Code Generation, PICC,

PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,

rfLAB, Select Mode, Total Endurance, TSHARC,

UniWinDriver, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-457-6

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS70293F-page 2

PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 AND

PIC24HJ128GPX02/X04

High-Performance, 16-bit Microcontrollers

Operating Range:

Timers/Capture/Compare/PWM:

• Up to 40 MIPS operation (at 3.0-3.6V):

- Industrial temperature range (-40°C to +85°C)

- Extended temperature range (-40°C to +125°C)

• Up to 20 MIPS operation (at 3.0-3.6V):

- High temperature range (-40°C to +150°C)

• Timer/Counters, up to five 16-bit timers:

- Can pair up to make two 32-bit timers

- One timer runs as a Real-Time Clock with an

external 32.768 kHz oscillator

- Programmable prescaler

• Input Capture (up to four channels):

- Capture on up, down or both edges

- 16-bit capture input functions

High-Performance CPU:

• Modified Harvard architecture

• C compiler optimized instruction set

• 16-bit wide data path

- 4-deep FIFO on each capture

• Output Compare (up to four channels):

- Single or Dual 16-bit Compare mode

- 16-bit Glitchless PWM mode

• 24-bit wide instructions

• Linear program memory addressing up to 4M

instruction words

• Hardware Real-Time Clock and Calendar

(RTCC):

• Linear data memory addressing up to 64 Kbytes

• 71 base instructions: mostly 1 word/1 cycle

• Flexible and powerful addressing modes

• Software stack

- Provides clock, calendar and alarm functions

Interrupt Controller:

• 5-cycle latency

• 16 x 16 multiply operations

• Up to 45 available interrupt sources

• Up to three external interrupts

• Seven programmable priority levels

• Five processor exceptions

• 32/16 and 16/16 divide operations

• Up to ±16-bit shifts for up to 40-bit data

Direct Memory Access (DMA):

• 8-channel hardware DMA

Digital I/O:

• Up to 2 Kbytes dual ported DMA buffer area (DMA

RAM) to store data transferred via DMA:

• Peripheral pin Select functionality

- Allows data transfer between RAM and a

peripheral while CPU is executing code (no

cycle stealing)

• Up to 35 programmable digital I/O pins

• Wake-up/Interrupt-on-Change for up to 31 pins

• Output pins can drive from 3.0V to 3.6V

• Most peripherals support DMA

• Up to 5.5V output with open drain configuration on

5V tolerant pins with external pull-up

On-Chip Flash and SRAM:

• 4 mA sink on all I/O pins

• Flash program memory (up to 128 Kbytes)

• Data SRAM (up to 8 Kbytes)

• Boot, Secure and General Security for program

Flash

DS70293F-page 3

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

Communication Modules:

System Management:

• 4-wire SPI (up to two modules):

• Flexible clock options:

- Framing supports I/O interface to simple

codecs

- External, crystal, resonator and internal RC

- Fully integrated Phase-Locked Loop (PLL)

- Extremely low jitter PLL

- Supports 8-bit and 16-bit data

- Supports all serial clock formats and

sampling modes

• I²C™:

• Power-Up Timer

• Oscillator Start-up Timer/Stabilizer

• Watchdog Timer with its own RC oscillator

• Fail-Safe Clock Monitor

- Full Multi-Master Slave mode support

- 7-bit and 10-bit addressing

• Reset by multiple sources

- Bus collision detection and arbitration

- Integrated signal conditioning

- Slave address masking

Power Management:

• On-chip 2.5V voltage regulator

• UART (up to two modules):

• Switch between clock sources in real time

• Idle, Sleep and Doze modes with fast wake-up

- Interrupt on address bit detect

- Interrupt on UART error

- Wake-up on Start bit from Sleep mode

- 4-character TX and RX FIFO buffers

- LIN 2.0 bus support

Analog-to-Digital Converters (ADCs):

• 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:

- Two and four simultaneous samples (10-bit ADC)

- Up to 13 input channels with auto-scanning

- IrDA^®encoding and decoding in hardware

- High-Speed Baud mode

- Conversion start can be manual or

synchronized with one of four trigger sources

- Hardware Flow Control with CTS and RTS

• Enhanced CAN (ECAN™ module) 2.0B active:

- Conversion possible in Sleep mode

- ±2 LSb max integral nonlinearity

- ±1 LSb max differential nonlinearity

- Up to eight transmit and up to 32 receive

buffers

- 16 receive filters and three masks

- Loopback, Listen Only and Listen All

Comparator Module:

- Messages modes for diagnostics and bus

monitoring

• Two analog comparators with programmable

input/output configuration

- Wake-up on CAN message

- Automatic processing of Remote

Transmission Requests

CMOS Flash Technology:

- FIFO mode using DMA

• Low-power, high-speed Flash technology

• Fully static design

- DeviceNet™ addressing support

• Parallel Master Slave Port (PMP/EPSP):

- Supports 8-bit or 16-bit data

• 3.3V (±10%) operating voltage

• Industrial and Extended temperature

• Low power consumption

- Supports 16 address lines

• Programmable Cyclic Redundancy Check (CRC):

- Programmable bit length for the CRC

generator polynomial (up to 16-bit length)

Packaging:

• 28-pin SPDIP/SOIC/QFN-S

• 44-pin TQFP/QFN

- 8-deep, 16-bit or 16-deep, 8-bit FIFO for data

input

Note:

See Table 1 for exact peripheral features

per device.

DS70293F-page 4

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 AND

PIC24HJ128GPX02/X04 PRODUCT

FAMILIES

The device names, pin counts, memory sizes and

peripheral availability of each device are listed below.

The following pages show their pinout diagrams.

TABLE 1:

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

CONTROLLER FAMILIES

Remappable Peripheral

Device

PIC24HJ128GP804 44 128

PIC24HJ128GP802 28 128

8

26

16

5

4

2

1

3

1

13

10

1/1

1/0

11 35 QFN

TQFP

2

21 SPDIP

SOIC

QFN-S

PIC24HJ128GP204 44 128

PIC24HJ128GP202 28 128

8

26

16

5

4

2

0

3

1

13

10

1/1

1/0

11 35 QFN

TQFP

2

21 SPDIP

SOIC

QFN-S

PIC24HJ64GP804 44 64

PIC24HJ64GP802 28 64

8

26

16

5

4

2

1

3

1

13

10

1/1

1/0

11 35 QFN

TQFP

2

21 SPDIP

SOIC

QFN-S

PIC24HJ64GP204 44 64

PIC24HJ64GP202 28 64

8

26

16

5

4

2

0

3

1

13

10

1/1

1/0

11 35 QFN

TQFP

2

21 SPDIP

SOIC

QFN-S

PIC24HJ32GP304 44 32

PIC24HJ32GP302 28 32

4

26

16

5

4

2

0

3

1

13

10

1/1

1/0

11 35 QFN

TQFP

2

21 SPDIP

SOIC

QFN-S

Note 1: RAM size is inclusive of 2 Kbytes of DMA RAM for all devices except PIC24HJ32GP302/304, which

include 1 Kbyte of DMA RAM.

2: Only four out of five timers are remappable.

3: Only two out of three interrupts are remappable.

DS70293F-page 5

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

Pin Diagrams

28-Pin SPDIP, SOIC

Pins are up to 5V tolerant

MCLR

AN0/VREF+/CN2/RA0

AN1/VREF-/CN3/RA1

AVDD

AVSS

1

2

3

4

5

28

27

26

25

24

(1)

AN9/RP15 /CN11/PMCS1/RB15

(1)

PGED1/AN2/C2IN-/RP0 /CN4/RB0

AN10/RTCC/RP14 /CN12/PMWR/RB14

(1)

PGEC1/ AN3/C2IN+/RP1 /CN5/RB1

AN11/RP13 /CN13/PMRD/RB13

(1)

AN4/C1IN-/RP2 /CN6/RB2

AN12/RP12 /CN14/PMD0/RB12

6

7

8

23

22

21

(1)

AN5/C1IN+/RP3 /CN7/RB3

PGEC2/TMS/RP11 /CN15/PMD1/RB11

(1)

VSS

OSC1/CLKI/CN30/RA2

PGED2/TDI/RP10 /CN16/PMD2/RB10

(3)

VCAP

9

20

19

18

17

16

15

OSC2/CLKO/CN29/PMA0/RA3

VSS

10

11

12

13

14

(1)

SOSCI/RP4 /CN1/PMBE/RB4

TDO/SDA1/RP9 /CN21/PMD3/RB9

(1)

SOSCO/T1CK/CN0/PMA1/RA4

VDD

TCK/SCL1/RP8 /CN22/PMD4/RB8

(1)

INT0/RP7 /CN23/PMD5/RB7

(1)

PGED3/ASDA1/RP5 /CN27/PMD7/RB5

PGEC3/ASCL1/RP6 /CN24/PMD6/RB6

(2)

Pins are up to 5V tolerant

28-Pin QFN-S

(1)

PGED1/AN2/C2IN-/RP0 /CN4/RB0

AN11/RP13 /CN13/PMRD/RB13

1

2

3

4

5

6

7

21

20

19

18

17

16

15

(1)

PGEC1/AN3/C2IN+/RP1 /CN5/RB1

AN12/RP12 /CN14/PMD0/RB12

PIC24HJ32GP302

PIC24HJ64GP202

PIC24HJ64GP502

PIC24HJ128GP202

PIC24HJ128GP502

(1)

AN4/C1IN-/RP2 /CN6/RB2

PGEC2/TMS/RP11 /CN15/PMD1/RB11

(1)

AN5/C1IN+/RP3 /CN7/RB3

PGED2/TDI/RP10 /CN16/PMD2/RB10

(3)

VSS

VCAP

OSC1/CLKI/CN30/RA2

VSS

(1)

OSC2/CLKO/CN29/PMA0/RA3

TDO/SDA1/RP9 /CN21/PMD3/RB9

Note 1: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals.

2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

3: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (Vcap)” for proper connection to this pin.

DS70293F-page 6

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

Pin Diagrams (Continued)

(2)

44-Pin QFN

Pins are up to 5V tolerant

(1)

AN4/C1IN-/RP2 /CN6/RB2

AN11/RP13 /CN13/PMRD/RB13

11

10

9

23

24

25

26

27

28

29

30

31

32

33

(1)

AN5/C1IN+/RP3 /CN7/RB3

AN12/RP12 /CN14/PMD0/RB12

(1)

AN6/RP16 /CN8/RC0

PGEC2/RP11 /CN15/PMD1/RB11

(1)

AN7/RP17 /CN9/RC1

PGED2/RP10 /CN16/PMD2/RB10

8

PIC24HJ32GP304

PIC24HJ64GP204

PIC24HJ64GP504

PIC24HJ128GP204

PIC24HJ128GP504

(1)

(3)

AN8/CVREF/RP18 /PMA2/CN10/RC2

VCAP

7

VDD

VSS

6

(1)

RP25 /CN19/PMA6/RC9

5

(1)

OSC1/CLKI/CN30/RA2

OSC2/CLKO/CN29/RA3

TDO/PMA8/RA8

RP24 /CN20/PMA5/RC8

4

(1)

RP23 /CN17/PMA0/RC7

3

(1)

RP22 /CN18/PMA1/RC6

2

(1)

SOSCI/RP4 /CN1/RB4

SDA1/RP9 /CN21/PMD3/RB9

1

Note 1: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals.

2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

3: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (Vcap)” for proper connection to this pin.

DS70293F-page 7

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

Pin Diagrams (Continued)

44-Pin TQFP

Pins are up to 5V tolerant

(1)

AN4/C1IN-/RP2 /CN6/RB2

AN11/RP13 /CN13/PMRD/RB13

11

10

9

8

7

6

5

4

3

23

24

25

26

27

28

29

30

31

32

33

(1)

AN12/RP12 /CN14/PMD0/RB12

AN5/C1IN+/RP3 /CN7/RB3

(1)

PGEC2/RP11 /CN15/PMD1/RB11

AN6/RP16 /CN8/RC0

(1)

PIC24HJ32GP304

PIC24HJ64GP204

PIC24HJ64GP504

PIC24HJ128GP204

PIC24HJ128GP504

PGED2/EMCD2/RP10 /CN16/PMD2/RB10

AN7/RP17 /CN9/RC1

(2)

(1)

VCAP

AN8/CVREF/RP18 /PMA2/CN10/RC2

VSS

VDD

VSS

(1)

RP25 /CN19/PMA6/RC9

RP24 /CN20/PMA5/RC8

RP23 /CN17/PMA0/RC7

(1)

OSC1/CLKI/CN30/RA2

OSC2/CLKO/CN29/RA3

TDO/PMA8/RA8

(1)

RP22 /CN18/PMA1/RC6

2

1

(1)

SDA1/RP9 /CN21/PMD3/RB9

SOSCI/RP4 /CN1/RB4

Note 1: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals.

2: Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (Vcap)” for proper connection to this pin.

DS70293F-page 8

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

Table of Contents

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 Product Families ....................................................... 5

Device Overview ................................................................................................................................................................................ 11

Guidelines for Getting Started with 16-bit Microcontrollers ................................................................................................................. 17

CPU ................................................................................................................................................................................................... 21

Memory Organization .......................................................................................................................................................................... 27

Flash Program Memory ...................................................................................................................................................................... 55

Resets ................................................................................................................................................................................................ 61

Interrupt Controller .............................................................................................................................................................................. 69

Direct Memory Access (DMA) ........................................................................................................................................................... 107

Oscillator Configuration ..................................................................................................................................................................... 119

Power-Saving Features .................................................................................................................................................................... 129

I/O Ports ............................................................................................................................................................................................ 135

Timer1 ............................................................................................................................................................................................... 161

Timer2/3 And TImer4/5 Feature ....................................................................................................................................................... 163

Input Capture .................................................................................................................................................................................... 169

Output Compare ............................................................................................................................................................................... 171

Serial Peripheral Interface (SPI) ....................................................................................................................................................... 175

Inter-Integrated Circuit™ (I²C™) ...................................................................................................................................................... 181

Universal Asynchronous Receiver Transmitter (UART) .................................................................................................................... 189

Enhanced CAN (ECAN™) Module ................................................................................................................................................... 195

10-bit/12-bit Analog-to-Digital Converter (ADC1) .............................................................................................................................. 221

Comparator Module .......................................................................................................................................................................... 233

Real-Time Clock and Calendar (RTCC) ........................................................................................................................................... 239

Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................................... 249

Parallel Master Port (PMP) ............................................................................................................................................................... 253

Special Features ............................................................................................................................................................................... 261

Instruction Set Summary ................................................................................................................................................................... 271

Development Support ....................................................................................................................................................................... 279

Electrical Characteristics ................................................................................................................................................................... 283

High Temperature Electrical Characteristics..................................................................................................................................... 333

Packaging Information ...................................................................................................................................................................... 343

Appendix A: Revision History ............................................................................................................................................................ 353

Index ................................................................................................................................................................................................. 363

The Microchip Web Site .................................................................................................................................................................... 367

Customer Change Notification Service............................................................................................................................................. 367

Customer Support ............................................................................................................................................................................. 367

Reader Response ............................................................................................................................................................................. 368

Product Identification System ........................................................................................................................................................... 369

DS70293F-page 9

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We

welcome your feedback.

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

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To determine if an errata sheet exists for a particular device, please check with one of the following:

•

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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DS70293F-page 10

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

DEVICE OVERVIEW

1.0

Note 1: This data sheet summarizes the features

of the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to the “dsPIC33F/PIC24H Family

Reference Manual”. Please see the

Microchip web site (www.microchip.com)

for the latest dsPIC33F/PIC24H Family

Reference Manual sections.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

This document contains device specific information for

the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 devices.

Figure 1-1 shows a general block diagram of the

core

and

peripheral

modules

in

the

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 families of devices.

Table 1-1 lists the functions of the various pins

shown in the pinout diagrams.

DS70293F-page 11

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 1-1:

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

BLOCK DIAGRAM

PSV and Table

Data Access

Control Block

X Data Bus

Interrupt

Controller

PORTA

PORTB

16

8

Data Latch

X RAM

DMA

RAM

23

PCH PCL

Program Counter

PCU

23

Address

Latch

Loop

Control

Logic

Stack

Control

Logic

16

23

16

DMA

PORTC

Controller

Address Generator Units

Address Latch

Program Memory

Data Latch

Remappable

Pins

EA MUX

ROM Latch

24

16

Instruction

Decode and

Control

Instruction Reg

16

Control Signals

to Various Blocks

17 x 17 Multiplier

16 x 16

W Register Array

Power-up

Timer

Timing

Generation

OSC2/CLKO

OSC1/CLKI

Divide Support

16

Oscillator

Start-up Timer

FRC/LPRC

Oscillators

Power-on

Reset

16-bit ALU

Precision

Band Gap

Reference

Watchdog

Timer

16

Brown-out

Reset

Voltage

Regulator

VCAP

VDD, VSS

MCLR

OC/

PWM1-4

Comparator

2 Ch.

ECAN1

Timers

1-5

PMP/

EPSP

UART1, 2

ADC1

SPI1, 2

RTCC

IC1, 2, 7, 8

CNx

I2C1

Note:

Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specific pins and features

present on each device.

DS70293F-page 12

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 1-1:

Pin Name

AN0-AN12

PINOUT I/O DESCRIPTIONS

Type

Buffer

Type

PPS

Description

I

Analog

Analog input channels.

CLKI

ST/CMOS No External clock source input. Always associated with OSC1 pin function.

Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillator mode. Optionally functions as CLKO in RC and EC modes.

CLKO

OSC1

O

I

—

No Always associated with OSC2 pin function.

ST/CMOS No Oscillator crystal input. ST buffer when configured in RC mode; CMOS

otherwise.

OSC2

I/O

—

No Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillator mode. Optionally functions as CLKO in RC and EC modes.

SOSCI

I

ST/CMOS No 32.768 kHz low-power oscillator crystal input; CMOS otherwise.

SOSCO

O

—

No 32.768 kHz low-power oscillator crystal output.

CN0-CN30

I

ST

No Change notification inputs. Can be software programmed for internal

weak pull-ups on all inputs.

IC1-IC2

IC7-IC8

I

ST

Yes Capture inputs 1/2

Yes Capture inputs 7/8.

OCFA

OC1-OC4

I

O

ST

—

Yes Compare Fault A input (for Compare Channels 1, 2, 3 and 4).

Yes Compare outputs 1 through 4.

INT0

INT1

INT2

I

ST

No External interrupt 0.

Yes External interrupt 1.

Yes External interrupt 2.

RA0-RA4

RA7-RA10

I/O

ST

No PORTA is a bidirectional I/O port.

RB0-RB15

RC0-RC9

I/O

ST

No PORTB is a bidirectional I/O port.

No PORTC is a bidirectional I/O port.

T1CK

T2CK

T3CK

T4CK

T5CK

I

ST

No Timer1 external clock input.

Yes Timer2 external clock input.

Yes Timer3 external clock input.

Yes Timer4 external clock input.

Yes Timer5 external clock input.

U1CTS

U1RTS

U1RX

I

O

I

ST

—

ST

—

Yes UART1 clear to send.

Yes UART1 ready to send.

Yes UART1 receive.

U1TX

O

Yes UART1 transmit.

U2CTS

U2RTS

U2RX

I

O

I

ST

—

ST

—

Yes UART2 clear to send.

Yes UART2 ready to send.

Yes UART2 receive.

U2TX

O

Yes UART2 transmit.

SCK1

SDI1

SDO1

SS1

I/O

I

O

ST

—

Yes Synchronous serial clock input/output for SPI1.

Yes SPI1 data in.

Yes SPI1 data out.

I/O

ST

Yes SPI1 slave synchronization or frame pulse I/O.

SCK2

SDI2

SDO2

SS2

I/O

I

O

ST

—

Yes Synchronous serial clock input/output for SPI2.

Yes SPI2 data in.

Yes SPI2 data out.

I/O

ST

Yes SPI2 slave synchronization or frame pulse I/O.

Legend: CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

PPS = Peripheral Pin Select

Analog = Analog input

O = Output

TTL = TTL input buffer

P = Power

I = Input

DS70293F-page 13

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 1-1:

Pin Name

PINOUT I/O DESCRIPTIONS (CONTINUED)

Buffer

Type

PPS

Description

Type

SCL1

SDA1

ASCL1

ASDA1

I/O

ST

No Synchronous serial clock input/output for I2C1.

No Synchronous serial data input/output for I2C1.

No Alternate synchronous serial clock input/output for I2C1.

No Alternate synchronous serial data input/output for I2C1.

TMS

TCK

TDI

I

ST

—

No JTAG Test mode select pin.

No JTAG test clock input pin.

No JTAG test data input pin.

No JTAG test data output pin.

TDO

O

C1RX

C1TX

I

O

ST

—

Yes ECAN1 bus receive pin.

Yes ECAN1 bus transmit pin.

RTCC

CVREF

O

—

No Real-Time Clock Alarm Output.

ANA

No Comparator Voltage Reference Output.

C1IN-

C1IN+

C1OUT

I

O

ANA

—

No Comparator 1 Negative Input.

No Comparator 1 Positive Input.

Yes Comparator 1 Output.

C2IN-

C2IN+

C2OUT

I

O

ANA

—

No Comparator 2 Negative Input.

No Comparator 2 Positive Input.

Yes Comparator 2 Output.

PMA0

I/O

TTL/ST

No Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and

Output (Master modes).

PMA1

I/O

TTL/ST

No Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and

Output (Master modes).

PMA2 -PMPA10

PMBE

PMCS1

O

—

No Parallel Master Port Address (Demultiplexed Master Modes).

No Parallel Master Port Byte Enable Strobe.

No Parallel Master Port Chip Select 1 Strobe.

No Parallel Master Port Data (Demultiplexed Master mode) or Address/

Data (Multiplexed Master modes).

PMD0-PMPD7

I/O

TTL/ST

PMRD

PMWR

O

—

No Parallel Master Port Read Strobe.

No Parallel Master Port Write Strobe.

PGED1

PGEC1

PGED2

PGEC2

PGED3

PGEC3

I/O

ST

No Data I/O pin for programming/debugging communication channel 1.

No Clock input pin for programming/debugging communication channel 1.

No Data I/O pin for programming/debugging communication channel 2.

No Clock input pin for programming/debugging communication channel 2.

No Data I/O pin for programming/debugging communication channel 3.

No Clock input pin for programming/debugging communication channel 3.

I

I/O

I

I/O

I

MCLR

AVDD

I/P

P

ST

P

No Master Clear (Reset) input. This pin is an active-low Reset to the device.

No Positive supply for analog modules. This pin must be connected at all

times.

AVSS

VDD

P

I

P

—

No Ground reference for analog modules.

No Positive supply for peripheral logic and I/O pins.

No CPU logic filter capacitor connection.

No Ground reference for logic and I/O pins.

No Analog voltage reference (high) input.

No Analog voltage reference (low) input.

VCAP

VSS

—

VREF+

VREF-

Analog

I

Legend: CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

PPS = Peripheral Pin Select

Analog = Analog input

O = Output

TTL = TTL input buffer

P = Power

I = Input

DS70293F-page 14

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

Referenced Sources

1.1

This device data sheet is based on the following

individual chapters of the “dsPIC33F/PIC24H Family

Reference Manual”. These documents should be

considered as the general reference for the operation

of a particular module or device feature.

Note 1: To access the documents listed below,

browse to the documentation section of

the PIC24HJ64GP204 product page of

the

Microchip

web

site

(www.microchip.com) or select a family

reference manual section from the

following list.

In addition to parameters, features, and

other documentation, the resulting page

provides links to the related family

reference manual sections.

• Section 1. “Introduction” (DS70197)

• Section 2. “CPU” (DS70204)

• Section 3. “Data Memory” (DS70202)

• Section 4. “Program Memory” (DS70202)

• Section 5. “Flash Programming” (DS70191)

• Section 8. “Reset” (DS70192)

• Section 9. “Watchdog Timer and Power-saving Modes” (DS70196)

• Section 11. “Timers” (DS70205)

• Section 12. “Input Capture” (DS70198)

• Section 13. “Output Compare” (DS70209)

• Section 16. “Analog-to-Digital Converter (ADC)” (DS70183)

• Section 17. “UART” (DS70188)

• Section 18. “Serial Peripheral Interface (SPI)” (DS70206)

• Section 19. “Inter-Integrated Circuit™ (I²C™)” (DS70195)

• Section 23. “CodeGuard™ Security (DS70199)

• Section 24. “Programming and Diagnostics” (DS70209)

• Section 25. “Device Configuration (DS70194)

• Section 26. “Development Tool Support” (DS70209)

• Section 30. “I/O Ports with Peripheral Pin Select (PPS)” (DS70190)

• Section 32. “Interrupts (Part III)” (DS70214)

• Section 33. “Audio Digital-to-Analog Converter (DAC)” (DS70211)

• Section 34. “Comparator” (DS70212)

• Section 35. “Parallel Master Port (PMP)” (DS70299)

• Section 36. “Programmable Cyclic Redundancy Check (CRC)” (DS70298)

• Section 37. “Real-Time Clock and Calendar (RTCC)” (DS70301)

• Section 38. “Direct Memory Access” (DS70215)

• Section 39. “Oscillator (Part III)” (DS70216)

DS70293F-page 15

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

NOTES:

DS70293F-page 16

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

2.2

Decoupling Capacitors

2.0

GUIDELINES FOR GETTING

STARTED WITH 16-BIT

MICROCONTROLLERS

The use of decoupling capacitors on every pair of

power supply pins, such as VDD, VSS, AVDD and

AVSS is required.

Note 1: This data sheet summarizes the features

of the PIC24HJ32GP302/304,

Consider the following criteria when using decoupling

capacitors:

PIC24HJ64GPX02/X04

PIC24HJ128GPX02/X04

and

of

• Value and type of capacitor: Recommendation

of 0.1 µF (100 nF), 10-20V. This capacitor should

be a low-ESR and have resonance frequency in

the range of 20 MHz and higher. It is

family

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to the “dsPIC33F/PIC24H

Family Reference Manual”. Please see

recommended that ceramic capacitors be used.

• Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended to

place the capacitors on the same side of the

board as the device. If space is constricted, the

capacitor can be placed on another layer on the

PCB using a via; however, ensure that the trace

length from the pin to the capacitor is within

one-quarter inch (6 mm) in length.

the

Microchip

web

site

(www.microchip.com) for the latest

dsPIC33F/PIC24H Family Reference

Manual sections.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

• Handling high frequency noise: If the board is

experiencing high frequency noise, upward of

tens of MHz, add a second ceramic-type capacitor

in parallel to the above described decoupling

capacitor. The value of the second capacitor can

be in the range of 0.01 µF to 0.001 µF. Place this

second capacitor next to the primary decoupling

capacitor. In high-speed circuit designs, consider

implementing a decade pair of capacitances as

close to the power and ground pins as possible.

For example, 0.1 µF in parallel with 0.001 µF.

2.1

Basic Connection Requirements

Getting started with the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04

family of 16-bit Microcontrollers (MCUs) requires

attention to a minimal set of device pin connections

before proceeding with development. The following is a

list of pin names, which must always be connected:

• Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a

minimum thereby reducing PCB track inductance.

• All VDD and VSS pins

(see Section 2.2 “Decoupling Capacitors”)

• All AVDD and AVSS pins (regardless if ADC module

is not used)

(see Section 2.2 “Decoupling Capacitors”)

• VCAP

(see Section 2.3 “CPU Logic Filter Capacitor

Connection (VCAP)”)

• MCLR pin

(see Section 2.4 “Master Clear (MCLR) Pin”)

• PGECx/PGEDx pins used for In-Circuit Serial

Programming™ (ICSP™) and debugging purposes

(see Section 2.5 “ICSP Pins”)

• OSC1 and OSC2 pins when external oscillator

source is used

(see Section 2.6 “External Oscillator Pins”)

Additionally, the following pins may be required:

• VREF+/VREF- pins used when external voltage

reference for ADC module is implemented

Note:

The AVDD and AVSS pins must be

connected independent of the ADC

voltage reference source.

DS70293F-page 17

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

The placement of this capacitor should be close to the

VCAP. It is recommended that the trace length not

exceed one-quarter inch (6 mm). Refer to Section 25.2

“On-Chip Voltage Regulator” for details.

FIGURE 2-1:

RECOMMENDED

MINIMUM CONNECTION

0.1 µF

Ceramic

10 µF

VDD

Tantalum

2.4

Master Clear (MCLR) Pin

R

The MCLR pin provides for two specific device

functions:

R1

MCLR

• Device Reset

C

• Device programming and debugging

dsPIC33F

During device programming and debugging, the

resistance and capacitance that can be added to the

pin must be considered. Device programmers and

debuggers drive the MCLR pin. Consequently,

specific voltage levels (VIH and VIL) and fast signal

transitions must not be adversely affected. Therefore,

specific values of R and C will need to be adjusted

based on the application and PCB requirements.

VDD

VSS

VDD

VSS

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

L1⁽¹⁾

For example, as shown in Figure 2-2, it is

recommended that the capacitor C, be isolated from

the MCLR pin during programming and debugging

operations.

Note 1: As an option, instead of a hard-wired connection, an

inductor (L1) can be substituted between VDD and

AVDD to improve ADC noise rejection. The inductor

impedence should be less than 1Ω and the inductor

capacity greater than 10 mA.

Place the components shown in Figure 2-2 within

one-quarter inch (6 mm) from the MCLR pin.

Where:

FCNV

-------------

2

f =

(i.e., ADC conversion rate/2)

FIGURE 2-2:

EXAMPLE OF MCLR PIN

CONNECTIONS

1

-----------------------

(2π LC)

VDD

2

1

⎛

⎝

⎞

---------------------

L =

⎠

(2πf C)

R

R1

MCLR

PIC24H

JP

C

2.2.1

TANK CAPACITORS

On boards with power traces running longer than six

inches in length, it is suggested to use a tank capacitor

for integrated circuits including MCUs to supply a local

power source. The value of the tank capacitor should

be determined based on the trace resistance that

connects the power supply source to the device, and

the maximum current drawn by the device in the

application. In other words, select the tank capacitor so

that it meets the acceptable voltage sag at the device.

Typical values range from 4.7 µF to 47 µF.

Note 1: R ≤ 10 kΩ is recommended. A suggested

starting value is 10 kΩ. Ensure that the

MCLR pin VIH and VIL specifications are met.

2: R1 ≤ 470Ω will limit any current flowing into

MCLR from the external capacitor C, in the

event of MCLR pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR pin

VIH and VIL specifications are met.

2.3

CPU Logic Filter Capacitor

Connection (VCAP)

A low-ESR (< 5 Ohms) capacitor is required on the

VCAP pin, which is used to stabilize the voltage

regulator output voltage. The VCAP pin must not be

connected to VDD, and must have a capacitor between

4.7 µF and 10 µF, 16V connected to ground. The type

can be ceramic or tantalum. Refer to Section 28.0

“Electrical

Characteristics”

for

additional

information.

DS70293F-page 18

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

2.5

ICSP Pins

2.6

External Oscillator Pins

The PGECx and PGEDx pins are used for In-Circuit

Serial Programming™ (ICSP™) and debugging

purposes. It is recommended to keep the trace length

between the ICSP connector and the ICSP pins on the

device as short as possible. If the ICSP connector is

expected to experience an ESD event, a series resistor

is recommended, with the value in the range of a few

tens of Ohms, not to exceed 100 Ohms.

Many MCUs have options for at least two oscillators: a

high-frequency primary oscillator and a low-frequency

secondary oscillator (refer to Section 9.0 “Oscillator

Configuration” for details).

The oscillator circuit should be placed on the same

side of the board as the device. Also, place the

oscillator circuit close to the respective oscillator pins,

not exceeding one-half inch (12 mm) distance

between them. The load capacitors should be placed

next to the oscillator itself, on the same side of the

board. Use a grounded copper pour around the

oscillator circuit to isolate them from surrounding

circuits. The grounded copper pour should be routed

directly to the MCU ground. Do not run any signal

traces or power traces inside the ground pour. Also, if

using a two-sided board, avoid any traces on the

other side of the board where the crystal is placed. A

suggested layout is shown in Figure 2-3.

Pull-up resistors, series diodes, and capacitors on the

PGECx and PGEDx pins are not recommended as they

will interfere with the programmer/debugger

communications to the device. If such discrete

components are an application requirement, they

should be removed from the circuit during

programming and debugging. Alternatively, refer to the

AC/DC characteristics and timing requirements

information in the respective device Flash

programming specification for information on

capacitive loading limits and pin input voltage high (VIH)

and input low (VIL) requirements.

FIGURE 2-3:

SUGGESTED PLACEMENT

OF THE OSCILLATOR

CIRCUIT

Ensure that the “Communication Channel Select”

(i.e., PGECx/PGEDx pins) programmed into the device

matches the physical connections for the ICSP to

MPLAB^®ICD 2, MPLAB^®ICD 3 or MPLAB^®REAL

ICE™.

Main Oscillator

Guard Ring

13

14

15

16

17

18

19

20

For more information on ICD 2, ICD 3 and REAL ICE

connection requirements, refer to the following

documents that are available on the Microchip website.

• “MPLAB^®ICD 2 In-Circuit Debugger User’s

Guide” DS51331

• “Using MPLAB^®ICD 2” (poster) DS51265

• “MPLAB^®ICD 2 Design Advisory” DS51566

• “Using MPLAB^®ICD 3” (poster) DS51765

• “MPLAB^®ICD 3 Design Advisory” DS51764

Guard Trace

Secondary

Oscillator

• “MPLAB^®REAL ICE™ In-Circuit Emulator User’s

Guide” DS51616

• “Using MPLAB^®REAL ICE™” (poster) DS51749

DS70293F-page 19

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

2.7

Oscillator Value Conditions on

Device Start-up

2.9

Unused I/Os

Unused I/O pins should be configured as outputs and

driven to a logic-low state.

If the PLL of the target device is enabled and

configured for the device start-up oscillator, the

maximum oscillator source frequency must be limited

to ≤ 8 MHz for start-up with the PLL enabled to comply

with device PLL start-up conditions. This means that if

the external oscillator frequency is outside this range,

the application must start-up in the FRC mode first. The

default PLL settings after a POR with an oscillator

frequency outside this range will violate the device

operating speed.

Alternatively, connect a 1k to 10k resistor between VSS

and the unused pins.

Once the device powers up, the application firmware

can initialize the PLL SFRs, CLKDIV and PLLDBF to a

suitable value, and then perform a clock switch to the

Oscillator + PLL clock source. Note that clock switching

must be enabled in the device Configuration word.

2.8

Configuration of Analog and

Digital Pins During ICSP

Operations

If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a

debugger, it automatically initializes all of the A/D input

pins (ANx) as “digital” pins, by setting all bits in the

AD1PCFGL register.

The bits in this register that correspond to the A/D pins

that are initialized by MPLAB ICD 2, ICD 3 or REAL

ICE, must not be cleared by the user application

firmware; otherwise, communication errors will result

between the debugger and the device.

If your application needs to use certain A/D pins as

analog input pins during the debug session, the user

application must clear the corresponding bits in the

AD1PCFGL register during initialization of the ADC

module.

When MPLAB ICD 2, ICD 3 or REAL ICE is used as a

programmer, the user application firmware must

correctly configure the AD1PCFGL register. Automatic

initialization of this register is only done during

debugger operation. Failure to correctly configure the

register(s) will result in all A/D pins being recognized as

analog input pins, resulting in the port value being read

as a logic ‘0’, which may affect user application

functionality.

DS70293F-page 20

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

3.0

CPU

and PIC24HJ128GPX02/X04 devices have sixteen,

16-bit working registers in the programmer’s model.

Each of the working registers can serve as a data,

address or address offset register. The 16th working

register (W15) operates as a software Stack Pointer

(SP) for interrupts and calls.

Note 1: This data sheet summarizes the features

of the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to “Section 2. CPU” (DS70204) of

the “dsPIC33F/PIC24H Family Refer-

ence Manual”, which is available from the

Microchip website (www.microchip.com).

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 instruction set includes

many addressing modes and is designed for optimum

C compiler efficiency. For most instructions, the

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 is capable of executing a data

(or program data) memory read, a working register

(data) read, a data memory write and a program

(instruction) memory read per instruction cycle. As a

result, three parameter instructions can be supported,

allowing A + B = C operations to be executed in a single

cycle.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

A block diagram of the CPU is shown in Figure 3-1, and

the programmer’s model for the PIC24HJ32GP302/

304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/

X04 is shown in Figure 3-2.

3.1

Overview

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 CPU module has a 16-bit

(data) modified Harvard architecture with an enhanced

instruction set and addressing modes. The CPU has a

24-bit instruction word with a variable length opcode

field. The Program Counter (PC) is 23 bits wide and

addresses up to 4M x 24 bits of user program memory

space. The actual amount of program memory

3.2

Data Addressing Overview

The data space can be linearly addressed as 32K words

or 64 Kbytes using an Address Generation Unit (AGU).

The upper 32 Kbytes of the data space memory map can

optionally be mapped into program space at any 16K

program word boundary defined by the 8-bit Program

Space Visibility Page (PSVPAG) register. The program to

data space mapping feature lets any instruction access

program space as if it were data space.

implemented varies by device.

A

single-cycle

instruction prefetch mechanism is used to help

maintain throughput and provides predictable

execution. All instructions execute in a single cycle,

with the exception of instructions that change the

program flow, the double word move (MOV.D)

instruction and the table instructions. Overhead-free,

single-cycle program loop constructs are supported

using the REPEATinstruction, which is interruptible at

any point.

The data space also includes 2 Kbytes of DMA RAM,

which is primarily used for DMA data transfers, but may

be used as general purpose RAM.

DS70293F-page 21

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

3.3

Special MCU Features

and PIC24HJ128GPX02/X04 devices support 16/16

and 32/16 integer divide operations. All divide

instructions are iterative operations. They must be

executed within a REPEAT loop, resulting in a total

execution time of 19 instruction cycles. The divide

operation can be interrupted during any of those

19 cycles without loss of data.

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 features a 17-bit by 17-

bit, single-cycle multiplier. The multiplier can perform

signed, unsigned and mixed-sign multiplication. Using

a 17-bit by 17-bit multiplier for 16-bit by 16-bit

multiplication

possible.

makes

mixed-sign

multiplication

A multi-bit data shifter is used to perform up to a 16-bit,

left or right shift in a single cycle.

FIGURE 3-1:

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 CPU

CORE BLOCK DIAGRAM

PSV and Table

Data Access

Control Block

X Data Bus

Interrupt

Controller

16

8

Data Latch

X RAM

DMA

RAM

23

16

PCH PCL

Program Counter

PCU

23

Address

Latch

Loop

Control

Logic

Stack

Control

Logic

23

16

DMA

Controller

Address Generator Units

Address Latch

Program Memory

Data Latch

EA MUX

ROM Latch

24

16

Instruction

Decode and

Control

Instruction Reg

16

Control Signals

to Various Blocks

17 x 17 Multiplier

16 x 16

W Register Array

Divide Support

16

16-bit ALU

16

To Peripheral Modules

DS70293F-page 22

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 3-2:

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

PROGRAMMER’S MODEL

D15

D0

W0/WREG

W1

PUSH.SShadow

Legend

W2

W3

W4

W5

W6

W7

Working Registers

W8

W9

W10

W11

W12

W13

W14/Frame Pointer

W15/Stack Pointer

SPLIM

Stack Pointer Limit Register

Program Counter

PC22

PC0

0

7

TBLPAG

Data Table Page Address

7

0

PSVPAG

Program Space Visibility Page Address

15

0

RCOUNT

REPEATLoop Counter

15

Core Configuration Register

CORCON

—

DC

N

Z

C

IPL2 IPL1 IPL0 RA

SRL

OV

STATUS Register

SRH

DS70293F-page 23

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

3.4

CPU Control Registers

REGISTER 3-1:

SR: CPU STATUS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

DC

bit 15

bit 8

R/W-0⁽¹⁾

R/W-0⁽²⁾

IPL<2:0>⁽²⁾

R/W-0⁽²⁾

R-0

RA

R/W-0

N

R/W-0

OV

R/W-0

Z

R/W-0

C

bit 7

bit 0

Legend:

C = Clear only bit

S = Set only bit

‘1’ = Bit is set

R = Readable bit

W = Writable bit

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n = Value at POR

x = Bit is unknown

bit 15-9

bit 8

Unimplemented: Read as ‘0’

DC: MCU ALU Half Carry/Borrow bit

1= A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

of the result occurred

0= No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized

data) of the result occurred

bit 7-5

IPL<2:0>: CPU Interrupt Priority Level Status bits⁽²⁾

111= CPU Interrupt Priority Level is 7 (15), user interrupts disabled

110= CPU Interrupt Priority Level is 6 (14)

101= CPU Interrupt Priority Level is 5 (13)

100= CPU Interrupt Priority Level is 4 (12)

011= CPU Interrupt Priority Level is 3 (11)

010= CPU Interrupt Priority Level is 2 (10)

001= CPU Interrupt Priority Level is 1 (9)

000= CPU Interrupt Priority Level is 0 (8)

bit 4

bit 3

bit 2

RA: REPEATLoop Active bit

1= REPEATloop in progress

0= REPEATloop not in progress

N: MCU ALU Negative bit

1= Result was negative

0= Result was non-negative (zero or positive)

OV: MCU ALU Overflow bit

This bit is used for signed arithmetic (two’s complement). It indicates an overflow of a magnitude that

causes the sign bit to change state.

1= Overflow occurred for signed arithmetic (in this arithmetic operation)

0= No overflow occurred

bit 1

bit 0

Z: MCU ALU Zero bit

1= An operation that affects the Z bit has set it at some time in the past

0= The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)

C: MCU ALU Carry/Borrow bit

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when

IPL<3> = 1.

2: The IPL<2:0> Status bits are read only when the NSTDIS bit (INTCON1<15>) = 1.

DS70293F-page 24

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 3-2:

CORCON: CORE CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

R/C-0

IPL3⁽¹⁾

R/W-0

PSV

U-0

—

U-0

—

bit 7

Legend:

C = Clear only bit

W = Writable bit

‘x = Bit is unknown

R = Readable bit

0’ = Bit is cleared

-n = Value at POR

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

bit 15-4

bit 3

Unimplemented: Read as ‘0’

IPL3: CPU Interrupt Priority Level Status bit 3⁽¹⁾

1= CPU interrupt priority level is greater than 7

0= CPU interrupt priority level is 7 or less

bit 2

PSV: Program Space Visibility in Data Space Enable bit

1= Program space visible in data space

0= Program space not visible in data space

bit 1-0

Unimplemented: Read as ‘0’

Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.

DS70293F-page 25

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

3.5.2

DIVIDER

3.5

Arithmetic Logic Unit (ALU)

The divide block supports 32-bit/16-bit and 16-bit/16-bit

signed and unsigned integer divide operations with the

following data sizes:

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 ALU is 16 bits wide and

is capable of addition, subtraction, bit shifts and logic

operations. Unless otherwise mentioned, arithmetic

operations are two’s complement in nature. Depending

on the operation, the ALU can affect the values of the

Carry (C), Zero (Z), Negative (N), Overflow (OV) and

Digit Carry (DC) Status bits in the SR register. The C

and DC Status bits operate as Borrow and Digit Borrow

bits, respectively, for subtraction operations.

• 32-bit signed/16-bit signed divide

• 32-bit unsigned/16-bit unsigned divide

• 16-bit signed/16-bit signed divide

• 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0

and the remainder in W1. 16-bit signed and unsigned

DIV instructions can specify any W register for both

the 16-bit divisor (Wn) and any W register (aligned)

pair (W(m + 1):Wm) for the 32-bit dividend. The divide

algorithm takes one cycle per bit of divisor, so both

32-bit/16-bit and 16-bit/16-bit instructions take the

same number of cycles to execute.

The ALU can perform 8-bit or 16-bit operations,

depending on the mode of the instruction that is used.

Data for the ALU operation can come from the W

register array or data memory, depending on the

addressing mode of the instruction. Likewise, output

data from the ALU can be written to the W register array

or a data memory location.

3.5.3

MULTI-BIT DATA SHIFTER

For information on the SR bits affected by each instruc-

tion, refer to the “16-bit MCU and DSC Programmer’s

Reference Manual” (DS70157).

The multi-bit data shifter is capable of performing up to

16-bit arithmetic or logic right shifts, or up to 16-bit left

shifts in a single cycle. The source can be either a

working register or a memory location.

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 CPU incorporates

hardware support for both multiplication and division.

This includes a dedicated hardware multiplier and

support hardware for 16-bit-divisor division.

The shifter requires a signed binary value to determine

both the magnitude (number of bits) and direction of the

shift operation. A positive value shifts the operand right.

A negative value shifts the operand left. A value of ‘0’

does not modify the operand.

3.5.1

MULTIPLIER

Using the high-speed 17-bit x 17-bit multiplier, the ALU

supports unsigned, signed or mixed-sign operation in

several MCU multiplication modes:

• 16-bit x 16-bit signed

• 16-bit x 16-bit unsigned

• 16-bit signed x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit unsigned

• 16-bit unsigned x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit signed

• 8-bit unsigned x 8-bit unsigned

DS70293F-page 26

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

4.1

Program Address Space

4.0

MEMORY ORGANIZATION

The program address memory space of the

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 devices is 4M instructions.

The space is addressable by a 24-bit value derived

either from the 23-bit Program Counter (PC) during

program execution, or from table operation or data

space remapping as described in Section 4.4

“Interfacing Program and Data Memory Spaces”.

Note:

This data sheet summarizes the features

of

the

PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04

PIC24HJ128GPX02/X04

and

of

families

devices. It is not intended to be a compre-

hensive reference source. To complement

the information in this data sheet, refer to

Section

4.

“Program

Memory”

(DS70203) of the “dsPIC33F/PIC24H

Family Reference Manual”, which is avail-

able from the Microchip website

(www.microchip.com).

User application access to the program memory space

is restricted to the lower half of the address range

(0x000000 to 0x7FFFFF). The exception is the use of

TBLRD/TBLWT operations, which use TBLPAG<7> to

permit access to the Configuration bits and Device ID

sections of the configuration memory space.

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 architecture features

separate program and data memory spaces and

buses. This architecture also allows the direct access

of program memory from the data space during code

execution.

The memory map for the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04

devices is shown in Figure 4-1.

FIGURE 4-1:

PROGRAM MEMORY MAP FOR PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

AND PIC24HJ128GPX02/X04 DEVICES

PIC24HJ32GP302/304

PIC24HJ64GPX02/X04

PIC24HJ128GPX02/X04

0x000000

0x000002

0x000004

GOTOInstruction

Reset Address

GOTOInstruction

Reset Address

GOTOInstruction

Reset Address

Interrupt Vector Table

Reserved

Interrupt Vector Table

Reserved

Interrupt Vector Table

Reserved

0x0000FE

0x000100

0x000104

0x0001FE

0x000200

Alternate Vector Table

User Program

Flash Memory

(11264 instructions)

User Program

Flash Memory

(22016 instructions)

0x0057FE

0x005800

User Program

Flash Memory

(44032 instructions)

0x00ABFE

0x00AC00

Unimplemented

(Read ‘0’s)

0x0157FE

0x015800

(Read ‘0’s)

Unimplemented

(Read ‘0’s)

0x7FFFFE

0x800000

Reserved

0xF7FFFE

0xF80000

0xF80017

0xF80018

Device Configuration

Registers

Device Configuration

Registers

Device Configuration

Registers

Reserved

0xFEFFFE

0xFF0000

0xFF0002

DEVID (2)

Reserved

DEVID (2)

Reserved

DEVID (2)

Reserved

0xFFFFFE

Note:

Memory areas are not shown to scale.

DS70293F-page 27

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

4.1.1

PROGRAM MEMORY

ORGANIZATION

4.1.2

INTERRUPT AND TRAP VECTORS

All PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 devices reserve the

addresses between 0x00000 and 0x000200 for

hard-coded program execution vectors. A hardware

Reset vector is provided to redirect code execution

from the default value of the PC on device Reset to the

actual start of code. A GOTOinstruction is programmed

by the user application at 0x000000, with the actual

address for the start of code at 0x000002.

The program memory space is organized in

word-addressable blocks. Although it is treated as

24 bits wide, it is more appropriate to think of each

address of the program memory as a lower and upper

word, with the upper byte of the upper word being

unimplemented. The lower word always has an even

address, while the upper word has an odd address, as

shown in Figure 4-2.

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 devices also have two

interrupt vector tables, located from 0x000004 to

0x0000FF and 0x000100 to 0x0001FF. These vector

tables allow each of the device interrupt sources to be

handled by separate Interrupt Service Routines (ISRs).

A more detailed discussion of the interrupt vector

tables is provided in Section 7.1 “Interrupt Vector

Table”.

Program memory addresses are always word-aligned

on the lower word, and addresses are incremented or

decremented by two during code execution. This

arrangement provides compatibility with data memory

space addressing and makes data in the program

memory space accessible.

FIGURE 4-2:

PROGRAM MEMORY ORGANIZATION

least significant word

PC Address

most significant word

23

msw

Address

(lsw Address)

16

8

0

0x000001

0x000003

0x000005

0x000007

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

Instruction Width

DS70293F-page 28

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported, so

4.2

Data Address Space

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 CPU has a separate

16-bit wide data memory space. The data space is

accessed using separate Address Generation Units

(AGUs) for read and write operations. The data

memory maps are shown in Figure 4-3 and Figure 4-4.

care must be taken when mixing byte and word

operations, or translating from 8-bit MCU code. If a

misaligned read or write is attempted, an address error

trap is generated. If the error occurred on a read, the

instruction underway is completed. If the error occurred

on a write, the instruction is executed but the write does

not occur. In either case, a trap is then executed,

allowing the system and/or user application to examine

the machine state prior to execution of the address

Fault.

All Effective Addresses (EAs) in the data memory space

are 16 bits wide and point to bytes within the data space.

This arrangement gives a data space address range of

64 Kbytes or 32K words. The lower half of the data

memory space (that is, when EA<15> = 0) is used for

implemented memory addresses, while the upper half

(EA<15> = 1) is reserved for the Program Space

Visibility area (see Section 4.4.3 “Reading Data from

Program Memory Using Program Space Visibility”).

All byte loads into any W register are loaded into the

Least Significant Byte. The Most Significant Byte is not

modified.

A sign-extend instruction (SE) is provided to allow user

applications to translate 8-bit signed data to 16-bit

signed values. Alternatively, for 16-bit unsigned data,

user applications can clear the MSB of any W register

by executing a zero-extend (ZE) instruction on the

appropriate address.

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 devices implement up to

8 Kbytes of data memory. Should an EA point to a

location outside of this area, an all-zero word or byte is

returned.

4.2.3

SFR SPACE

4.2.1

DATA SPACE WIDTH

The first 2 Kbytes of the Near Data Space, from 0x0000

to 0x07FF, is primarily occupied by Special Function

Registers (SFRs). These are used by the

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 core and peripheral modules

for controlling the operation of the device.

The data memory space is organized in byte

addressable, 16-bit wide blocks. Data is aligned in data

memory and registers as 16-bit words, but all data

space EAs resolve to bytes. The Least Significant

Bytes (LSBs) of each word have even addresses, while

the Most Significant Bytes (MSBs) have odd

addresses.

SFRs are distributed among the modules that they

control, and are generally grouped together by module.

Much of the SFR space contains unused addresses;

these are read as ‘0’.

4.2.2

DATA MEMORY ORGANIZATION

AND ALIGNMENT

To maintain backward compatibility with PIC^®MCU

devices and improve data space memory usage

Note:

The actual set of peripheral features and

interrupts varies by the device. Refer to

the corresponding device tables and

pinout diagrams for device-specific

information.

efficiency,

the

PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04

instruction set supports both word and byte operations.

As a consequence of byte accessibility, all effective

address calculations are internally scaled to step

through word-aligned memory. For example, the core

recognizes that Post-Modified Register Indirect

Addressing mode [Ws++] results in a value of Ws + 1

for byte operations and Ws + 2 for word operations.

4.2.4

NEAR DATA SPACE

The 8 Kbyte area between 0x0000 and 0x1FFF is

referred to as the near data space. Locations in this

space are directly addressable via a 13-bit absolute

address field within all memory direct instructions.

Additionally, the whole data space is addressable using

MOV instructions, which support Memory Direct

Addressing mode with a 16-bit address field, or by

using Indirect Addressing mode using a working

register as an address pointer.

A data byte read, reads the complete word that

contains the byte, using the LSB of any EA to

determine which byte to select. The selected byte is

placed onto the LSB of the data path. That is, data

memory and registers are organized as two parallel

byte-wide entities with shared (word) address decode

but separate write lines. Data byte writes only write to

the corresponding side of the array or register that

matches the byte address.

DS70293F-page 29

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

When the CPU and the DMA controller attempt to

concurrently write to the same DMA RAM location, the

hardware ensures that the CPU is given precedence in

accessing the DMA RAM location. Therefore, the DMA

RAM provides a reliable means of transferring DMA

data without ever having to stall the CPU.

4.2.5

DMA RAM

The PIC24HJ32GP302/304 devices contain 1 Kbytes

of dual ported DMA RAM located at the end of X data

space.

The

PIC24HJ64GPX02/X04

and

PIC24HJ128GPX02/X04 devices contain 2 Kbytes of

dual ported DMA RAM located at the end of X data

space, and is a part of X data space. Memory

locations in the DMA RAM space are accessible

simultaneously by the CPU and the DMA controller

module. DMA RAM is utilized by the DMA controller to

store data to be transferred to various peripherals

using DMA, as well as data transferred from various

peripherals using DMA. The DMA RAM can be

accessed by the DMA controller without having to

steal cycles from the CPU.

Note:

DMA RAM can be used for general

purpose data storage if the DMA function

is not required in an application.

FIGURE 4-3:

DATA MEMORY MAP FOR PIC24HJ32GP302/304 DEVICES WITH 4 KB RAM

MSb

LSb

Address

16 bits

MSb

LSb

0x0000

2 Kbyte

SFR Space

0x07FF

0x0801

0x07FE

0x0800

6 Kbyte

Near

Data

X Data RAM (X)

DMA RAM

Space

4 Kbyte

SRAM Space

0x13FE

0x1400

0x13FF

0x1401

0x17FE

0x1800

0x17FF

0x1801

0x8001

0x8000

Optionally

Mapped

into Program

Memory

X Data

Unimplemented (X)

0xFFFF

0xFFFE

DS70293F-page 30

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 4-4:

DATA MEMORY MAP FOR PIC24HJ128GP202/204, PIC24HJ64GP202/204,

PIC24HJ128GP502/504 AND PIC24HJ64GP502/504 DEVICES WITH 8 KB RAM

MSb

Address

LSb

Address

16 bits

MSb

LSb

0x0000

0x0001

2 Kbyte

SFR Space

0x07FE

0x0800

0x07FF

0x0801

8 Kbyte

Near

Data

X Data RAM (X)

DMA RAM

8 Kbyte

Space

SRAM Space

0x1FFF

0x2001

0x1FFE

0x2000

0x27FF

0x2801

0x27FE

0x2800

0x8001

0x8000

X Data

Unimplemented (X)

Optionally

Mapped

into Program

Memory

0xFFFF

0xFFFE

DS70293F-page 31

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

4.2.6

SOFTWARE STACK

4.2.7

DATA RAM PROTECTION FEATURE

The PIC24H product family supports Data RAM

protection features that enable segments of RAM to be

protected when used in conjunction with Boot and

Secure Code Segment Security. BSRAM (Secure RAM

segment for BS) is accessible only from the Boot

Segment Flash code when enabled. SSRAM (Secure

RAM segment for RAM) is accessible only from the

Secure Segment Flash code when enabled. See

Table 4-1 for an overview of the BSRAM and SSRAM

SFRs.

In addition to its use as a working register, the W15

register in the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04

devices is also used as a software Stack Pointer. The

Stack Pointer always points to the first available free

word and grows from lower to higher addresses. It

pre-decrements for stack pops and post-increments for

stack pushes, as shown in Figure 4-5. For a PC push

during any CALL instruction, the MSb of the PC is

zero-extended before the push, ensuring that the MSb

is always clear.

4.3

Instruction Addressing Modes

Note:

A PC push during exception processing

concatenates the SRL register to the MSb

of the PC prior to the push.

The addressing modes shown in Table 4-35 form the

basis of the addressing modes optimized to support the

specific features of individual instructions. The

addressing modes provided in the MAC class of

instructions differ from those in the other instruction

types.

The Stack Pointer Limit register (SPLIM) associated

with the Stack Pointer sets an upper address boundary

for the stack. SPLIM is uninitialized at Reset. As is the

case for the Stack Pointer, SPLIM<0> is forced to ‘0’

because all stack operations must be word aligned.

4.3.1

FILE REGISTER INSTRUCTIONS

Whenever an EA is generated using W15 as a source

or destination pointer, the resulting address is

compared with the value in SPLIM. If the contents of

the Stack Pointer (W15) and the SPLIM register are

equal and a push operation is performed, a stack error

trap does not occur. The stack error trap occurs on a

subsequent push operation. For example, to cause a

stack error trap when the stack grows beyond address

0x2000 in RAM, initialize the SPLIM with the value

0x1FFE.

Most file register instructions use a 13-bit address field

(f) to directly address data present in the first 8192

bytes of data memory (near data space). Most file

register instructions employ a working register, W0,

which is denoted as WREG in these instructions. The

destination is typically either the same file register or

WREG (with the exception of the MUL instruction),

which writes the result to a register or register pair. The

MOV instruction allows additional flexibility and can

access the entire data space.

Similarly, a Stack Pointer underflow (stack error) trap is

generated when the Stack Pointer address is found to

be less than 0x0800. This prevents the stack from

interfering with the Special Function Register (SFR)

space.

4.3.2

MCU INSTRUCTIONS

The three-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

where:

A write to the SPLIM register should not be immediately

followed by an indirect read operation using W15.

Operand 1 is always a working register (that is, the

addressing mode can only be register direct), which is

referred to as Wb.

FIGURE 4-5:

CALLSTACK FRAME

Operand 2 can be a W register, fetched from data

memory, or a 5-bit literal. The result location can be

either a W register or a data memory location. The fol-

lowing addressing modes are supported by MCU

instructions:

0x0000

15

0

• Register Direct

PC<15:0>

000000000

W15 (before CALL)

• Register Indirect

PC<22:16>

• Register Indirect Post-Modified

• Register Indirect Pre-Modified

• 5-bit or 10-bit Literal

W15 (after CALL)

POP : [--W15]

PUSH: [W15++]

Note:

Not all instructions support all the

addressing modes given above.

Individual instructions can support

different subsets of these addressing

modes.

DS70293F-page 49

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 4-35: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode

File Register Direct

Description

The address of the file register is specified explicitly.

The contents of a register are accessed directly.

The contents of Wn forms the Effective Address (EA).

Register Direct

Register Indirect

Register Indirect Post-Modified

The contents of Wn forms the EA. Wn is post-modified (incremented

or decremented) by a constant value.

Register Indirect Pre-Modified

Wn is pre-modified (incremented or decremented) by a signed constant value

to form the EA.

Register Indirect with Register Offset The sum of Wn and Wb forms the EA.

(Register Indexed)

Register Indirect with Literal Offset

The sum of Wn and a literal forms the EA.

4.3.3

MOVE (MOV) INSTRUCTION

4.3.4

OTHER INSTRUCTIONS

Move instructions provide a greater degree of address-

ing flexibility than other instructions. In addition to the

Addressing modes supported by most MCU instruc-

tions, MOV instructions also support Register Indirect

with Register Offset Addressing mode, also referred to

as Register Indexed mode.

Besides the addressing modes outlined previously, some

instructions use literal constants of various sizes. For

example, BRA(branch) instructions use 16-bit signed lit-

erals to specify the branch destination directly, whereas

the DISIinstruction uses a 14-bit unsigned literal field. In

some instructions, such as ADD Acc, the source of an

operand or result is implied by the opcode itself. Certain

operations, such as NOP, do not have any operands.

Note:

For the MOV instructions, the addressing

mode specified in the instruction can differ

for the source and destination EA.

However, the 4-bit Wb (Register Offset)

field is shared by both source and

destination (but typically only used by

one).

In summary, the following addressing modes are

supported by move instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

Note:

Not all instructions support all the

addressing modes given above. Individual

instructions may support different subsets

of these addressing modes.

DS70293F-page 50

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

4.4.1

ADDRESSING PROGRAM SPACE

4.4

Interfacing Program and Data

Memory Spaces

Since the address ranges for the data and program

spaces are 16 and 24 bits, respectively, a method is

needed to create a 23-bit or 24-bit program address

from 16-bit data registers. The solution depends on the

interface method to be used.

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 architecture uses

a

24-bit-wide program space and a 16-bit-wide data

space. The architecture is also a modified Harvard

scheme, meaning that data can also be present in the

program space. To use this data successfully, it must

be accessed in a way that preserves the alignment of

information in both spaces.

For table operations, the 8-bit Table Page register

(TBLPAG) is used to define a 32K word region within

the program space. This is concatenated with a 16-bit

EA to arrive at a full 24-bit program space address. In

this format, the Most Significant bit (MSb) of TBLPAG

is used to determine if the operation occurs in the user

memory (TBLPAG<7> = 0) or the configuration mem-

ory (TBLPAG<7> = 1).

Aside

from

normal

execution,

the

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 architecture provides two

methods by which program space can be accessed

during operation:

For remapping operations, the 8-bit Program Space

Visibility register (PSVPAG) is used to define a

16K word page in the program space. When the MSb

of the EA is ‘1’, PSVPAG is concatenated with the lower

15 bits of the EA to form a 23-bit program space

address. Unlike table operations, this limits remapping

operations strictly to the user memory area.

• Using table instructions to access individual bytes

or words anywhere in the program space

• Remapping a portion of the program space into

the data space (Program Space Visibility)

Table instructions allow an application to read or write

to small areas of the program memory. This capability

makes the method ideal for accessing data tables that

need to be updated periodically. It also allows access

to all bytes of the program word. The remapping

method allows an application to access a large block of

data on a read-only basis, which is ideal for look-ups

from a large table of static data. The application can

only access the least significant word of the program

word.

Table 4-36 and Figure 4-6 show how the program EA is

created for table operations and remapping accesses

from the data EA. Here, P<23:0> refers to a program

space word, and D<15:0> refers to a data space word.

TABLE 4-36: PROGRAM SPACE ADDRESS CONSTRUCTION

Program Space Address

Access

Space

Access Type

<23>

<22:16>

<15>

<14:1>

<0>

Instruction Access

(Code Execution)

User

0

PC<22:1>

0

0xx xxxx xxxx xxxx xxxx xxx0

TBLRD/TBLWT

(Byte/Word Read/Write)

TBLPAG<7:0>

0xxx xxxx

Data EA<15:0>

xxxx xxxx xxxx xxxx

Data EA<15:0>

Configuration

TBLPAG<7:0>

1xxx xxxx

xxxx xxxx xxxx xxxx

Program Space Visibility User

(Block Remap/Read)

0

PSVPAG<7:0>

xxxx xxxx

Data EA<14:0>⁽¹⁾

0

xxx xxxx xxxx xxxx

Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of

the address is PSVPAG<0>.

DS70293F-page 51

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 4-6:

DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

Program Counter⁽¹⁾

Program Counter

23 bits

0

1/0

EA

Table Operations⁽²⁾

1/0

TBLPAG

8 bits

16 bits

24 bits

Select

1

0

EA

Program Space Visibility⁽¹⁾

(Remapping)

0

PSVPAG

8 bits

15 bits

23 bits

Byte Select

User/Configuration

Space Select

Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain

word alignment of data in the program and data spaces.

2: Table operations are not required to be word aligned. Table read operations are permitted

in the configuration memory space.

DS70293F-page 52

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

- In Byte mode, either the upper or lower byte

of the lower program word is mapped to the

lower byte of a data address. The upper byte

is selected when Byte Select is ‘1’; the lower

byte is selected when it is ‘0’.

4.4.2

DATA ACCESS FROM PROGRAM

MEMORY USING TABLE

INSTRUCTIONS

The TBLRDL and TBLWTL instructions offer a direct

method of reading or writing the lower word of any

address within the program space without going

through data space. The TBLRDH and TBLWTH

instructions are the only method to read or write the

upper 8 bits of a program space word as data.

• TBLRDH (Table Read High):

- In Word mode, this instruction maps the entire

upper word of a program address (P<23:16>)

to a data address. The ‘phantom’ byte

(D<15:8>), is always ‘0’.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two 16-bit

wide word address spaces, residing side by side, each

with the same address range. TBLRDL and TBLWTL

access the space that contains the least significant

data word. TBLRDHand TBLWTHaccess the space that

contains the upper data byte.

- In Byte mode, this instruction maps the upper

or lower byte of the program word to D<7:0>

of the data address, in the TBLRDL instruc-

tion. The data is always ‘0’ when the upper

‘phantom’ byte is selected (Byte Select = 1).

Similarly, two table instructions, TBLWTHand TBLWTL,

are used to write individual bytes or words to a pro-

gram space address. The details of their operation are

explained in Section 5.0 “Flash Program Memory”.

Two table instructions are provided to move byte or

word-sized (16-bit) data to and from program space.

Both function as either byte or word operations.

For all table operations, the area of program memory

space to be accessed is determined by the Table Page

register (TBLPAG). TBLPAG covers the entire program

memory space of the device, including user application

and configuration spaces. When TBLPAG<7> = 0, the

table page is located in the user memory space. When

TBLPAG<7> = 1, the page is located in configuration

space.

• TBLRDL(Table Read Low):

- In Word mode, this instruction maps the

lower word of the program space

location (P<15:0>) to a data address

(D<15:0>).

FIGURE 4-7:

ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Program Space

TBLPAG

02

23

15

0

0x000000

23

16

8

0

00000000

0x020000

0x030000

00000000

‘Phantom’ Byte

TBLRDH.B (Wn<0> = 0)

TBLRDL.B (Wn<0> = 1)

TBLRDL.B (Wn<0> = 0)

TBLRDL.W

The address for the table operation is determined by the data EA

within the page defined by the TBLPAG register.

Only read operations are shown; write operations are also valid in

the user memory area.

0x800000

DS70293F-page 53

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

24-bit program word are used to contain the data. The

upper 8 bits of any program space location used as

data should be programmed with ‘1111 1111’ or

‘0000 0000’ to force a NOP. This prevents possible

issues should the area of code ever be accidentally

executed.

4.4.3

READING DATA FROM PROGRAM

MEMORY USING PROGRAM SPACE

VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word page of the program space.

This option provides transparent access to stored

constant data from the data space without the need to

use special instructions, such as TBLRDL/TBLRDH.

Note:

PSV access is temporarily disabled during

table reads/writes.

Program space access through the data space occurs

if the MSb of the data space EA is ‘1’ and program

space visibility is enabled by setting the PSV bit in the

Core Control register (CORCON<2>). The location of

the program memory space to be mapped into the data

space is determined by the Program Space Visibility

Page register (PSVPAG). This 8-bit register defines

any one of 256 possible pages of 16K words in

program space. In effect, PSVPAG functions as the

upper 8 bits of the program memory address, with the

15 bits of the EA functioning as the lower bits. By

incrementing the PC by 2 for each program memory

word, the lower 15 bits of data space addresses directly

map to the lower 15 bits in the corresponding program

space addresses.

For operations that use PSV and are executed outside

a REPEAT loop, the MOV and MOV.D instructions

require one instruction cycle in addition to the specified

execution time. All other instructions require two

instruction cycles in addition to the specified execution

time.

For operations that use PSV, and are executed inside

a REPEATloop, these instances require two instruction

cycles in addition to the specified execution time of the

instruction:

• Execution in the first iteration

• Execution in the last iteration

• Execution prior to exiting the loop due to an

interrupt

Data reads to this area add a cycle to the instruction

being executed, since two program memory fetches

are required.

• Execution upon re-entering the loop after an

interrupt is serviced

Any other iteration of the REPEAT loop allows the

instruction using PSV to access data, to execute in a

single cycle.

Although each data space address 0x8000 and higher

maps directly into a corresponding program memory

address (see Figure 4-8), only the lower 16 bits of the

FIGURE 4-8:

PROGRAM SPACE VISIBILITY OPERATION

When CORCON<2> = 1and EA<15> = 1:

Program Space

Data Space

PSVPAG

02

23

15

0

0x000000

0x0000

Data EA<14:0>

0x010000

0x018000

The data in the page

designated by

PSVPAG is mapped

into the upper half of

the data memory

space...

0x8000

PSV Area

...whilethelower15bits

of the EA specify an

exact address within

the PSV area. This

corresponds exactly to

the same lower 15 bits

of the actual program

space address.

0xFFFF

0x800000

DS70293F-page 54

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

PGEC2/PGED2 or PGEC3/PGED3), and three other

lines for power (VDD), ground (VSS) and Master Clear

5.0

FLASH PROGRAM MEMORY

Note 1: This data sheet summarizes the features

of the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and

(MCLR). This allows customers to manufacture boards

with unprogrammed devices and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed.

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to “Section 5. Flash Pro-

RTSP is accomplished using TBLRD (table read) and

TBLWT (table write) instructions. With RTSP, the user

application can write program memory data either in

blocks or ‘rows’ of 64 instructions (192 bytes) at a time

or a single program memory word, and erase program

memory in blocks or ‘pages’ of 512 instructions (1536

bytes) at a time.

gramming”

(DS70191)

of

the

“dsPIC33F/PIC24H Family Reference

Manual”, which is available from the

Microchip website (www.microchip.com).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

5.1

Table Instructions and Flash

Programming

Regardless of the method used, all programming of

Flash memory is done with the table read and table

write instructions. These allow direct read and write

access to the program memory space from the data

memory while the device is in normal operating mode.

The 24-bit target address in the program memory is

formed using bits <7:0> of the TBLPAG register and the

Effective Address (EA) from a W register specified in

the table instruction, as shown in Figure 5-1.

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 devices contain internal

Flash program memory for storing and executing

application code. The memory is readable, writable and

erasable during normal operation over the entire VDD

range.

Flash memory can be programmed in two ways:

The TBLRDLand the TBLWTLinstructions are used to

read or write to bits <15:0> of program memory.

TBLRDLand TBLWTLcan access program memory in

both Word and Byte modes.

• In-Circuit Serial Programming™ (ICSP™)

programming capability

• Run-Time Self-Programming (RTSP)

The TBLRDHand TBLWTHinstructions are used to read

or write to bits <23:16> of program memory. TBLRDH

and TBLWTHcan also access program memory in Word

or Byte mode.

ICSP

allows

the

PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04

devices to be serially programmed while in the end

application circuit. This is done with two lines for

programming clock and programming data (one of the

alternate programming pin pairs: PGEC1/PGED1,

FIGURE 5-1:

ADDRESSING FOR TABLE REGISTERS

24 bits

Program Counter

Using

Program Counter

0

Working Reg EA

Using

Table Instruction

1/0

TBLPAG Reg

8 bits

16 bits

User/Configuration

Space Select

Byte

Select

24-bit EA

DS70293F-page 55

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

For example, if the device is operating at +125°C,

5.2

RTSP Operation

the FRC accuracy will be ±5%. If the TUN<5:0> bits

(see Register 9-4) are set to ‘b111111, the

minimum row write time is equal to Equation 5-2.

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 Flash program memory

array is organized into rows of 64 instructions or 192

bytes. RTSP allows the user application to erase a

page of memory, which consists of eight rows (512

instructions) at a time, and to program one row or one

word at a time. Table 28-12 shows typical erase and

programming times. The 8-row erase pages and single

row write rows are edge-aligned from the beginning of

program memory, on boundaries of 1536 bytes and

192 bytes, respectively.

EQUATION 5-2:

MINIMUM ROW WRITE

TIME

11064 Cycles

7.37 MHz × (1 + 0.05) × (1 – 0.00375)

----------------------------------------------------------------------------------------------

= 1.435ms

T_RW

=

The maximum row write time is equal to Equation 5-3.

The program memory implements holding buffers that

can contain 64 instructions of programming data. Prior

to the actual programming operation, the write data

must be loaded into the buffers sequentially. The

instruction words loaded must always be from a group

of 64 boundary.

EQUATION 5-3:

MAXIMUM ROW WRITE

TIME

11064 Cycles

---------------------------------------------------------------------------------------------

= 1.586ms

T_RW

=

7.37 MHz × (1 – 0.05) × (1 – 0.00375)

The basic sequence for RTSP programming is to set up

a Table Pointer, then do a series of TBLWTinstructions

to load the buffers. Programming is performed by

setting the control bits in the NVMCON register. A total

of 64 TBLWTL and TBLWTH instructions are required

to load the instructions.

Setting the WR bit (NVMCON<15>) starts the opera-

tion, and the WR bit is automatically cleared when the

operation is finished.

All of the table write operations are single-word writes

(two instruction cycles) because only the buffers are

5.4

Control Registers

Two SFRs are used to read and write the program

Flash memory: NVMCON and NVMKEY.

written.

A

programming cycle is required for

programming each row.

The NVMCON register (Register 5-1) controls which

blocks are to be erased, which memory type is to be

programmed and the start of the programming cycle.

5.3

Programming Operations

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. The processor stalls (waits) until the

programming operation is finished.

NVMKEY (Register 5-2) is a write-only register that is

used for write protection. To start a programming or erase

sequence, the user application must consecutively write

0x55 and 0xAA to the NVMKEY register. Refer to

Section 5.3 “Programming Operations” for further

details.

The programming time depends on the FRC accuracy

(see Table 28-19) and the value of the FRC Oscillator

Tuning register (see Register 9-4). Use the following

formula to calculate the minimum and maximum values

for the Row Write Time, Page Erase Time, and Word

Write Cycle Time parameters (see Table 28-12).

EQUATION 5-1:

PROGRAMMING TIME

T

-------------------------------------------------------------------------------------------------------------------------

7.37 MHz × (FRC Accuracy)% × (FRC Tuning)%

DS70293F-page 56

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 5-1:

NVMCON: FLASH MEMORY CONTROL REGISTER

R/SO-0⁽¹⁾

WR

R/W-0⁽¹⁾

WREN

R/W-0⁽¹⁾

WRERR

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0⁽¹⁾

bit 0

U-0

—

R/W-0⁽¹⁾

ERASE

U-0

—

U-0

—

R/W-0⁽¹⁾

NVMOP<3:0>⁽²⁾

bit 7

Legend:

SO = Settable only bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

WR: Write Control bit

1= Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once operation is complete

0= Program or erase operation is complete and inactive

bit 14

bit 13

WREN: Write Enable bit

1= Enable Flash program/erase operations

0= Inhibit Flash program/erase operations

WRERR: Write Sequence Error Flag bit

1= An improper program or erase sequence attempt or termination has occurred (bit is set

automatically on any set attempt of the WR bit)

0= The program or erase operation completed normally

bit 12-7

bit 6

Unimplemented: Read as ‘0’

ERASE: Erase/Program Enable bit

1= Perform the erase operation specified by NVMOP<3:0> on the next WR command

0= Perform the program operation specified by NVMOP<3:0> on the next WR command

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

NVMOP<3:0>: NVM Operation Select bits⁽²⁾

If ERASE = 1:

1111= Memory bulk erase operation

1110= Reserved

1101= Erase General Segment

1100= Erase Secure Segment

1011= Reserved

0011= No operation

0010= Memory page erase operation

0001= No operation

0000= Erase a single Configuration register byte

If ERASE = 0:

1111= No operation

1110= Reserved

1101= No operation

1100= No operation

1011= Reserved

0011= Memory word program operation

0010= No operation

0001= Memory row program operation

0000= Program a single Configuration register byte

Note 1: These bits can only be reset on a POR.

2: All other combinations of NVMOP<3:0> are unimplemented.

DS70293F-page 57

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 5-2:

NVMKEY: NONVOLATILE MEMORY KEY REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

W-0

bit 7

W-0

NVMKEY<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

Unimplemented: Read as ‘0’

NVMKEY<7:0>: Key Register (write-only) bits

DS70293F-page 58

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

4. Write the first 64 instructions from data RAM into

the program memory buffers (see Example 5-2).

5.4.1

PROGRAMMING ALGORITHM FOR

FLASH PROGRAM MEMORY

5. Write the program block to Flash memory:

Programmers can program one row of program Flash

memory at a time. To do this, it is necessary to erase

the 8-row erase page that contains the desired row.

The general process is:

a) Set the NVMOP bits to ‘0001’ to configure

for row programming. Clear the ERASE bit

and set the WREN bit.

b) Write 0x55 to NVMKEY.

c) Write 0xAA to NVMKEY.

1. Read eight rows of program memory

(512 instructions) and store in data RAM.

d) Set the WR bit. The programming cycle

begins and the CPU stalls for the duration of

the write cycle. When the write to Flash mem-

ory is done, the WR bit is cleared

automatically.

2. Update the program data in RAM with the

desired new data.

3. Erase the block (see Example 5-1):

a) Set the NVMOP bits (NVMCON<3:0>) to

‘0010’ to configure for block erase. Set the

ERASE (NVMCON<6>) and WREN

(NVMCON<14>) bits.

6. Repeat steps 4 and 5, using the next available

64 instructions from the block in data RAM by

incrementing the value in TBLPAG, until all

512 instructions are written back to Flash memory.

b) Write the starting address of the page to be

erased into the TBLPAG and W registers.

For protection against accidental operations, the write

initiate sequence for NVMKEY must be used to allow

any erase or program operation to proceed. After the

programming command has been executed, the user

application must wait for the programming time until

programming is complete. The two instructions

following the start of the programming sequence

should be NOPs, as shown in Example 5-3.

c) Write 0x55 to NVMKEY.

d) Write 0xAA to NVMKEY.

e) Set the WR bit (NVMCON<15>). The erase

cycle begins and the CPU stalls for the dura-

tion of the erase cycle. When the erase is

done, the WR bit is cleared automatically.

EXAMPLE 5-1:

ERASING A PROGRAM MEMORY PAGE

; Set up NVMCON for block erase operation

MOV

#0x4042, W0

W0, NVMCON

;

; Initialize NVMCON

; Init pointer to row to be ERASED

MOV

#tblpage(PROG_ADDR), W0

W0, TBLPAG

#tbloffset(PROG_ADDR), W0

;

; Initialize PM Page Boundary SFR

; Initialize in-page EA[15:0] pointer

; Set base address of erase block

; Block all interrupts with priority <7

; for next 5 instructions

TBLWTL W0, [W0]

DISI

#5

MOV

BSET

NOP

#0x55, W0

W0, NVMKEY

#0xAA, W1

W1, NVMKEY

NVMCON, #WR

; Write the 55 key

;

; Write the AA key

; Start the erase sequence

; Insert two NOPs after the erase

; command is asserted

DS70293F-page 59

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

EXAMPLE 5-2:

LOADING THE WRITE BUFFERS

; Set up NVMCON for row programming operations

MOV

#0x4001, W0

W0, NVMCON

;

; Initialize NVMCON

; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled

MOV

#0x0000, W0

W0, TBLPAG

#0x6000, W0

;

; Initialize PM Page Boundary SFR

; An example program memory address

; Perform the TBLWT instructions to write the latches

; 0th_program_word

MOV

#LOW_WORD_0, W2

#HIGH_BYTE_0, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

; 1st_program_word

MOV

#LOW_WORD_1, W2

#HIGH_BYTE_1, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

;

2nd_program_word

MOV

#LOW_WORD_2, W2

#HIGH_BYTE_2, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

•

; 63rd_program_word

MOV

#LOW_WORD_31, W2

#HIGH_BYTE_31, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

EXAMPLE 5-3:

INITIATING A PROGRAMMING SEQUENCE

DISI

#5

; Block all interrupts with priority <7

; for next 5 instructions

MOV

BSET

NOP

#0x55, W0

W0, NVMKEY

#0xAA, W1

W1, NVMKEY

NVMCON, #WR

; Write the 55 key

;

; Write the AA key

; Start the erase sequence

; Insert two NOPs after the

; erase command is asserted

DS70293F-page 60

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

A simplified block diagram of the Reset module is

shown in Figure 6-1.

6.0

RESETS

Note 1: This data sheet summarizes the features

of the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and

Any active source of reset will make the SYSRST

signal active. On system Reset, some of the registers

associated with the CPU and peripherals are forced to

a known Reset state and some are unaffected.

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to Section 8. “Reset” (DS70192) of

the “dsPIC33F/PIC24H Family Refer-

ence Manual”, which is available from the

Microchip website (www.microchip.com).

Note:

Refer to the specific peripheral section or

Section 3.0 “CPU” of this manual for

register Reset states.

All types of device Reset sets a corresponding status

bit in the RCON register to indicate the type of Reset

(see Register 6-1).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

A POR clears all the bits, except for the POR bit

(RCON<0>), that are set. The user application can set

or clear any bit at any time during code execution. The

RCON bits only serve as status bits. Setting a particular

Reset status bit in software does not cause a device

Reset to occur.

The Reset module combines all reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

The RCON register also has other bits associated with

the Watchdog Timer and device power-saving states.

The function of these bits is discussed in other sections

of this manual.

• POR: Power-on Reset

Note:

The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset is meaningful.

• BOR: Brown-out Reset

• MCLR: Master Clear Pin Reset

• SWR: RESETInstruction

• WDTO: Watchdog Timer Reset

• CM: Configuration Mismatch Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Condition Device Reset

- Illegal Opcode Reset

- Uninitialized W Register Reset

- Security Reset

FIGURE 6-1:

RESET SYSTEM BLOCK DIAGRAM

RESETInstruction

Glitch Filter

MCLR

WDT

Module

Sleep or Idle

BOR

Internal

Regulator

SYSRST

VDD

POR

VDD Rise

Detect

Trap Conflict

Illegal Opcode

Uninitialized W Register

Configuration Mismatch

DS70293F-page 61

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(1)

REGISTER 6-1:

RCON: RESET CONTROL REGISTER

R/W-0

TRAPR

bit 15

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CM

R/W-0

IOPUWR

VREGS

bit 8

R/W-0

EXTR

R/W-0

SWR

R/W-0

SWDTEN⁽²⁾

R/W-0

WDTO

R/W-0

IDLE

R/W-1

BOR

R/W-1

POR

SLEEP

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

TRAPR: Trap Reset Flag bit

1= A Trap Conflict Reset has occurred

0= A Trap Conflict Reset has not occurred

IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit

1= An illegal opcode detection, an illegal address mode or uninitialized W register used as an

Address Pointer caused a Reset

0= An illegal opcode or uninitialized W Reset has not occurred

bit 13-10

bit 9

Unimplemented: Read as ‘0’

CM: Configuration Mismatch Flag bit

1= A configuration mismatch Reset has occurred.

0= A configuration mismatch Reset has NOT occurred

bit 8

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

VREGS: Voltage Regulator Standby During Sleep bit

1= Voltage regulator is active during Sleep

0= Voltage regulator goes into Standby mode during Sleep

EXTR: External Reset (MCLR) Pin bit

1= A Master Clear (pin) Reset has occurred

0= A Master Clear (pin) Reset has not occurred

SWR: Software Reset (Instruction) Flag bit

1= A RESETinstruction has been executed

0= A RESETinstruction has not been executed

SWDTEN: Software Enable/Disable of WDT bit⁽²⁾

1= WDT is enabled

0= WDT is disabled

WDTO: Watchdog Timer Time-out Flag bit

1= WDT time-out has occurred

0= WDT time-out has not occurred

SLEEP: Wake-up from Sleep Flag bit

1= Device has been in Sleep mode

0= Device has not been in Sleep mode

IDLE: Wake-up from Idle Flag bit

1= Device was in Idle mode

0= Device was not in Idle mode

Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

DS70293F-page 62

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(1)

REGISTER 6-1:

RCON: RESET CONTROL REGISTER (CONTINUED)

bit 1

BOR: Brown-out Reset Flag bit

1= A Brown-out Reset has occurred

0= A Brown-out Reset has not occurred

bit 0

POR: Power-on Reset Flag bit

1= A Power-on Reset has occurred

0= A Power-on Reset has not occurred

Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

DS70293F-page 63

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

A warm Reset is the result of all other reset sources,

6.1

System Reset

including the RESET instruction. On warm Reset, the

device will continue to operate from the current clock

source as indicated by the Current Oscillator Selection

bits (COSC<2:0>) in the Oscillator Control register

(OSCCON<14:12>).

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 family of devices have

two types of Reset:

• Cold Reset

• Warm Reset

The device is kept in a Reset state until the system

power supplies have stabilized at appropriate levels

and the oscillator clock is ready. A description of the

sequence in which this occurs and is shown in

Figure 6-2.

A cold Reset is the result of a Power-on Reset (POR)

or a Brown-out Reset (BOR). On a cold Reset, the

FNOSC configuration bits in the FOSC device

configuration register selects the device clock source.

TABLE 6-1:

OSCILLATOR DELAY

Oscillator

Oscillator Startup

Timer

Oscillator Mode

PLL Lock Time

Total Delay

Startup Delay

FRC, FRCDIV16,

FRCDIVN

TOSCD

—

TOSCD

FRCPLL

XT

TOSCD

—

TOST

—

TLOCK

—

TOSCD + TLOCK

TOSCD + TOST

—

HS

—

EC

—

XTPLL

HSPLL

ECPLL

SOSC

LPRC

TOSCD

—

TOST

—

TLOCK

—

TOSCD + TOST + TLOCK

TLOCK

TOSCD

TOST

—

TOSCD + TOST

TOSCD

—

Note 1: TOSCD = Oscillator Start-up Delay (1.1 μs max for FRC, 70 μs max for LPRC). Crystal Oscillator start-up

times vary with crystal characteristics, load capacitance, etc.

2: TOST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4 μs for a

10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.

3: TLOCK = PLL lock time (1.5 ms nominal), if PLL is enabled.

DS70293F-page 64

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 6-2:

SYSTEM RESET TIMING

VBOR

Vbor

VPOR

TPOR

VDD

1

POR

BOR

TBOR

2

3

TPWRT

SYSRST

4

Oscillator Clock

TLOCK

TOSCD

TOST

6

TFSCM

FSCM

5

Reset

Device Status

Run

Time

Note 1: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active

until VDD crosses the VPOR threshold and the delay TPOR has elapsed.

2: BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the

VBOR threshold and the delay TBOR has elapsed. The delay TBOR ensures the voltage regulator output

becomes stable.

3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific

period of time (TPWRT) after a BOR. The delay TPWRT ensures that the system power supplies have stabilized

at the appropriate level for full-speed operation. After the delay TPWRT has elapsed, the SYSRST becomes

inactive, which in turn enables the selected oscillator to start generating clock cycles.

4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in

Table 6-1. Refer to Section 9.0 “Oscillator Configuration” for more information.

5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user

application programs a GOTO instruction at the reset address, which redirects program execution to the

appropriate start-up routine.

6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock

is ready and the delay TFSCM elapsed.

DS70293F-page 65

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 6-2:

OSCILLATOR DELAY

Symbol

Parameter

POR threshold

Value

VPOR

TPOR

VBOR

TBOR

TPWRT

TFSCM

1.8V nominal

POR extension time

30 μs maximum

2.5V nominal

BOR threshold

BOR extension time

100 μs maximum

Programmable power-up time delay

Fail-Safe Clock Monitor Delay

0-128 ms nominal

900 μs maximum

6.2.1 Brown-out Reset (BOR) and

Power-up timer (PWRT)

Note: When the device exits the Reset

condition (begins normal operation), the

device operating parameters (voltage,

frequency, temperature, etc.) must be

within their operating ranges, otherwise

the device may not function correctly.

The user application must ensure that

the delay between the time power is

first applied, and the time SYSRST

becomes inactive, is long enough to get

The on-chip regulator has a Brown-out Reset (BOR)

circuit that resets the device when the VDD is too low

(VDD < VBOR) for proper device operation. The BOR cir-

cuit keeps the device in Reset until VDD crosses VBOR

threshold and the delay TBOR has elapsed. The delay

TBOR ensures the voltage regulator output becomes

stable.

The Brown-out Reset status bit (BOR) in the Reset

Control register (RCON<1>) is set to indicate the BOR.

all

operating

parameters

within

specification.

The device will not run at full speed after a BOR as the

VDD should rise to acceptable levels for full-speed

operation. The PWRT provides power-up time delay

(TPWRT) to ensure that the system power supplies have

stabilized at the appropriate levels for full-speed

operation before the SYSRST is released.

6.2

Power-on Reset (POR)

A Power-on Reset (POR) circuit ensures the device is

reset from power-on. The POR circuit is active until

VDD crosses the VPOR threshold and the delay TPOR

has elapsed. The delay TPOR ensures the internal

device bias circuits become stable.

The power-up timer delay (TPWRT) is programmed by

the Power-on Reset Timer Value Select bits

(FPWRT<2:0>) in the POR Configuration register

(FPOR<2:0>), which provides eight settings (from 0 ms

to 128 ms). Refer to Section 25.0 “Special Features”

for further details.

The device supply voltage characteristics must meet

the specified starting voltage and rise rate

requirements to generate the POR. Refer to

Section 28.0 “Electrical Characteristics” for details.

The POR status bit (POR) in the Reset Control register

(RCON<0>) is set to indicate the Power-on Reset.

Figure 6-3 shows the typical brown-out scenarios. The

reset delay (TBOR + TPWRT) is initiated each time VDD

rises above the VBOR trip point

DS70293F-page 66

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 6-3:

BROWN-OUT SITUATIONS

VDD

VBOR

TBOR + TPWRT

SYSRST

VDD

VBOR

TBOR + TPWRT

SYSRST

VDD dips before PWRTexpires

VDD

VBOR

TBOR + TPWRT

SYSRST

The Software Reset (Instruction) Flag bit (SWR) in the

Reset Control register (RCON<6>) is set to indicate

the software Reset.

6.3

External Reset (EXTR)

The external Reset is generated by driving the MCLR

pin low. The MCLR pin is a Schmitt trigger input with an

additional glitch filter. Reset pulses that are longer than

the minimum pulse width will generate a Reset. Refer

to Section 28.0 “Electrical Characteristics” for

minimum pulse width specifications. The External

Reset (MCLR) Pin (EXTR) bit in the Reset Control

(RCON) register is set to indicate the MCLR Reset.

6.5

Watchdog Time-out Reset (WDTO)

Whenever a Watchdog time-out occurs, the device will

asynchronously assert SYSRST. The clock source will

remain unchanged. A WDT time-out during Sleep or

Idle mode will wake-up the processor, but will not reset

the processor.

6.3.0.1

EXTERNAL SUPERVISORY CIRCUIT

The Watchdog Timer Time-out Flag bit (WDTO) in the

Reset Control register (RCON<4>) is set to indicate

the Watchdog Reset. Refer to Section 25.4

“Watchdog Timer (WDT)” for more information on

Watchdog Reset.

Many systems have external supervisory circuits that

generate reset signals to reset multiple devices in the

system. This external Reset signal can be directly con-

nected to the MCLR pin to reset the device when the

rest of system is Reset.

6.6

Trap Conflict Reset

6.3.0.2

INTERNAL SUPERVISORY CIRCUIT

If a lower-priority hard trap occurs while a higher-prior-

ity trap is being processed, a hard trap conflict Reset

occurs. The hard traps include exceptions of priority

level 13 through level 15, inclusive. The address error

(level 13) and oscillator error (level 14) traps fall into

this category.

When using the internal power supervisory circuit to

reset the device, the external reset pin (MCLR) should

be tied directly or resistively to VDD. In this case, the

MCLR pin will not be used to generate a Reset. The

external reset pin (MCLR) does not have an internal

pull-up and must not be left unconnected.

The Trap Reset Flag bit (TRAPR) in the Reset Control

register (RCON<15>) is set to indicate the Trap Conflict

Reset. Refer to Section 7.0 “Interrupt Controller” for

more information on trap conflict Resets.

6.4

Software RESETInstruction (SWR)

Whenever the RESET instruction is executed, the

device will assert SYSRST, placing the device in a

special Reset state. This Reset state will not re-

initialize the clock. The clock source in effect prior to the

RESETinstruction will remain. SYSRST is released at

the next instruction cycle, and the reset vector fetch will

commence.

DS70293F-page 67

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

each program memory section to store the data values.

The upper 8 bits should be programmed with 3Fh,

which is an illegal opcode value.

6.7

Configuration Mismatch Reset

To maintain the integrity of the peripheral pin select

control registers, they are constantly monitored with

shadow registers in hardware. If an unexpected

change in any of the registers occur (such as cell dis-

turbances caused by ESD or other external events), a

configuration mismatch Reset occurs.

6.8.0.2

UNINITIALIZED W REGISTER

RESET

Any attempts to use the uninitialized W register as an

address pointer will Reset the device. The W register

array (with the exception of W15) is cleared during all

resets and is considered uninitialized until written to.

The Configuration Mismatch Flag bit (CM) in the Reset

Control register (RCON<9>) is set to indicate the

configuration mismatch Reset. Refer to Section 11.0

“I/O Ports” for more information on the configuration

mismatch Reset.

6.8.0.3

SECURITY RESET

If a Program Flow Change (PFC) or Vector Flow

Change (VFC) targets a restricted location in a

protected segment (Boot and Secure Segment), that

operation will cause a security Reset.

Note:

The configuration mismatch feature and

associated reset flag is not available on all

devices.

The PFC occurs when the Program Counter is

reloaded as a result of a Call, Jump, Computed Jump,

Return, Return from Subroutine, or other form of

branch instruction.

6.8

Illegal Condition Device Reset

An illegal condition device Reset occurs due to the

following sources:

The VFC occurs when the Program Counter is

reloaded with an Interrupt or Trap vector.

• Illegal Opcode Reset

• Uninitialized W Register Reset

• Security Reset

Refer to Section 25.8 “Code Protection and

CodeGuard™ Security” for more information on

Security Reset.

The Illegal Opcode or Uninitialized W Access Reset

Flag bit (IOPUWR) in the Reset Control register

(RCON<14>) is set to indicate the illegal condition

device Reset.

6.9

Using the RCON Status Bits

The user application can read the Reset Control regis-

ter (RCON) after any device Reset to determine the

cause of the reset.

6.8.0.1

ILLEGAL OPCODE RESET

A device Reset is generated if the device attempts to

execute an illegal opcode value that is fetched from

program memory.

Note: The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset will be meaningful.

The illegal opcode Reset function can prevent the

device from executing program memory sections that

are used to store constant data. To take advantage of

the illegal opcode Reset, use only the lower 16 bits of

Table 6-3 provides a summary of the reset flag bit

operation.

TABLE 6-3:

RESET FLAG BIT OPERATION

Flag Bit

Set by:

Cleared by:

TRAPR (RCON<15>)

IOPWR (RCON<14>)

Trap conflict event

POR, BOR

Illegal opcode or uninitialized

W register access or Security Reset

CM (RCON<9>)

Configuration Mismatch

MCLR Reset

POR, BOR

POR

EXTR (RCON<7>)

SWR (RCON<6>)

WDTO (RCON<4>)

RESETinstruction

WDT time-out

POR, BOR

PWRSAVinstruction,

CLRWDTinstruction, POR, BOR

SLEEP (RCON<3>)

IDLE (RCON<2>)

BOR (RCON<1>)

POR (RCON<0>)

PWRSAV #SLEEPinstruction

PWRSAV #IDLEinstruction

POR, BOR

—

POR

Note: All Reset flag bits can be set or cleared by user software.

DS70293F-page 68

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

7.1

Interrupt Vector Table

7.0

INTERRUPT CONTROLLER

The Interrupt Vector Table (IVT), shown in Figure 7-1,

resides in program memory, starting at location

000004h. The IVT contains 126 vectors consisting of

eight nonmaskable trap vectors plus up to 118 sources

of interrupt. In general, each interrupt source has its

own vector. Each interrupt vector contains a 24 bit wide

address. The value programmed into each interrupt

vector location is the starting address of the associated

Interrupt Service Routine (ISR).

Note 1: This data sheet summarizes the features

of the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to Section 32. “Interrupts

(Part III)”

(DS70214)

of

the”dsPIC33F/PIC24H Family Reference

Manual”, which is available from the

Microchip website (www.microchip.com).

Interrupt vectors are prioritized in terms of their natural

priority. This priority is linked to their position in the

vector table. Lower addresses generally have a higher

natural priority. For example, the interrupt associated

with vector 0 takes priority over interrupts at any other

vector address.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 devices implement up to 45

unique interrupts and five nonmaskable traps. These

are summarized in Table 7-1.

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 interrupt controller

reduces the numerous peripheral interrupt request sig-

nals to a single interrupt request signal to the

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 CPU.

7.1.1

ALTERNATE INTERRUPT VECTOR

TABLE

The Alternate Interrupt Vector Table (AIVT) is located

after the IVT, as shown in Figure 7-1. Access to the

AIVT is provided by the ALTIVT control bit

(INTCON2<15>). If the ALTIVT bit is set, all interrupt

and exception processes use the alternate vectors

instead of the default vectors. The alternate vectors are

organized in the same manner as the default vectors.

The interrupt controller has the following features:

• Up to eight processor exceptions and software

traps

• Eight user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

The AIVT supports debugging by providing a means to

switch between an application and

a

support

• A unique vector for each interrupt or exception

source

environment without requiring the interrupt vectors to

be reprogrammed. This feature also enables switching

between applications for evaluation of different

software algorithms at run time. If the AIVT is not

needed, the AIVT should be programmed with the

same addresses used in the IVT.

• Fixed priority within a specified user priority level

• Alternate Interrupt Vector Table (AIVT) for debug

support

• Fixed interrupt entry and return latencies

7.2

Reset Sequence

A device Reset is not a true exception because the

interrupt controller is not involved in the Reset process.

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 device clears its

registers in response to a Reset, which forces the PC

to zero. The microcontroller then begins program

execution at location 0x000000. A GOTOinstruction at

the Reset address can redirect program execution to

the appropriate start-up routine.

Note: Any unimplemented or unused vector

locations in the IVT and AIVT should be

programmed with the address of a default

interrupt handler routine that contains a

RESETinstruction.

DS70293F-page 69

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 7-1:

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04

INTERRUPT VECTOR TABLE

Reset – GOTOInstruction

Reset – GOTOAddress

Reserved

0x000000

0x000002

0x000004

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

DMA Error Trap Vector

Reserved

Interrupt Vector 0

Interrupt Vector 1

~

0x000014

~

Interrupt Vector 52

Interrupt Vector 53

Interrupt Vector 54

~

0x00007C

0x00007E

0x000080

Interrupt Vector Table (IVT)⁽¹⁾

~

Interrupt Vector 116

Interrupt Vector 117

Reserved

0x0000FC

0x0000FE

0x000100

0x000102

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

DMA Error Trap Vector

Reserved

Interrupt Vector 0

Interrupt Vector 1

~

0x000114

~

Alternate Interrupt Vector Table (AIVT)⁽¹⁾

Interrupt Vector 52

Interrupt Vector 53

Interrupt Vector 54

~

0x00017C

0x00017E

0x000180

~

Interrupt Vector 116

Interrupt Vector 117

Start of Code

0x0001FE

0x000200

Note 1: See Table 7-1 for the list of implemented interrupt vectors.

DS70293F-page 70

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 7-1:

INTERRUPT VECTORS

Vector

Number

IVT Address

AIVT Address

Interrupt Source

0

0x000004

0x000006

0x000008

0x00000A

0x00000C

0x00000E

0x000010

0x000012

0x000014

0x000016

0x000018

0x00001A

0x00001C

0x00001E

0x000020

0x000022

0x000024

0x000026

0x000028

0x00002A

0x00002C

0x00002E

0x000030

0x000032

0x000034

0x000036

0x000038

0x00003A

0x00003C

0x00003E

0x000040

0x000042

0x000044

0x000046

0x000048

0x00004A

0x00004C

0x00004E

0x000050

0x000052

0x000054

0x000056

0x000058

0x00005A

0x00005C

0x00005E

0x000060

0x000104

0x000106

0x000108

0x00010A

0x00010C

0x00010E

0x000110

0x000112

0x000114

0x000116

0x000118

0x00011A

0x00011C

0x00011E

0x000120

0x000122

0x000124

0x000126

0x000128

0x00012A

0x00012C

0x00012E

0x000130

0x000132

0x000134

0x000136

0x000138

0x00013A

0x00013C

0x00013E

0x000140

0x000142

0x000144

0x000146

0x000148

0x00014A

0x00014C

0x00014E

0x000150

0x000152

0x000154

0x000156

0x000158

0x00015A

0x00015C

0x00015E

0x000160

Reserved

1

Oscillator Failure

Address Error

Stack Error

Math Error

DMA Error

Reserved

2

3

4

5

6

7

Reserved

8

INT0 – External Interrupt 0

IC1 – Input Capture 1

OC1 – Output Compare 1

T1 – Timer1

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

DMA0 – DMA Channel 0

IC2 – Input Capture 2

OC2 – Output Compare 2

T2 – Timer2

T3 – Timer3

SPI1E – SPI1 Error

SPI1 – SPI1 Transfer Done

U1RX – UART1 Receiver

U1TX – UART1 Transmitter

ADC1 – ADC 1

DMA1 – DMA Channel 1

Reserved

SI2C1 – I2C1 Slave Events

MI2C1 – I2C1 Master Events

CM – Comparator Interrupt

CN – Change Notification Interrupt

INT1 – External Interrupt 1

Reserved

IC7 – Input Capture 7

IC8 – Input Capture 8

DMA2 – DMA Channel 2

OC3 – Output Compare 3

OC4 – Output Compare 4

T4 – Timer4

T5 – Timer5

INT2 – External Interrupt 2

U2RX – UART2 Receiver

U2TX – UART2 Transmitter

SPI2E – SPI2 Error

SPI2 – SPI2 Transfer Done

C1RX – ECAN1 RX Data Ready

C1 – ECAN1 Event

DMA3 – DMA Channel 3

Reserved

DS70293F-page 71

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 7-1:

INTERRUPT VECTORS (CONTINUED)

Vector

Number

IVT Address

AIVT Address

Interrupt Source

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88-126

0x000062

0x000064

0x000066

0x000068

0x00006A

0x00006C

0x00006E

0x000070

0x000072

0x000074

0x000076

0x000078

0x00007A

0x00007C

0x00007E

0x000080

0x000082

0x000084

0x000086

0x000088

0x00008A

0x00008C

0x00008E

0x000090

0x000092

0x000094

0x000096

0x000098

0x00009A

0x00009C

0x00009E

0x0000A0

0x0000A2

0x0000A4

0x0000A6

0x0000A8

0x0000AA

0x0000AC

0x0000AE

0x0000B0

0x0000B2

0x000162

0x000164

0x000166

0x000168

0x00016A

0x00016C

0x00016E

0x000170

0x000172

0x000174

0x000176

0x000178

0x00017A

0x00017C

0x00017E

0x000180

0x000182

0x000184

0x000186

0x000188

0x00018A

0x00018C

0x00018E

0x000190

0x000192

0x000194

0x000196

0x000198

0x00019A

0x00019C

0x00019E

0x0001A0

0x0001A2

0x0001A4

0x0001A6

0x0001A8

0x0001AA

0x0001AC

0x0001AE

0x0001B0

0x0001B2

Reserved

PMP – Parallel Master Port

DMA – DMA Channel 4

Reserved

DMA5 – DMA Channel 5

RTCC – Real Time Clock

Reserved

U1E – UART1 Error

U2E – UART2 Error

CRC – CRC Generator Interrupt

DMA6 – DMA Channel 6

DMA7 – DMA Channel 7

C1TX – ECAN1 TX Data Request

Reserved

0x0000B4-0x0000FE 0x0001B4-0x0001FE Reserved

DS70293F-page 72

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

7.3.4

IPCx

7.3

Interrupt Control and Status

Registers

The IPC registers are used to set the interrupt priority

level for each source of interrupt. Each user interrupt

source can be assigned to one of eight priority levels.

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 devices implement a total of

30 registers for the interrupt controller:

7.3.5

INTTREG

• INTCON1

• INTCON2

• IFSx

The INTTREG register contains the associated

interrupt vector number and the new CPU interrupt

priority level, which are latched into vector number

(VECNUM<6:0>) and Interrupt level (ILR<3:0>) bit

fields in the INTTREG register. The new interrupt

priority level is the priority of the pending interrupt.

• IECx

• IPCx

• INTTREG

The interrupt sources are assigned to the IFSx, IECx

and IPCx registers in the same sequence that they are

listed in Table 7-1. For example, the INT0 (External

Interrupt 0) is shown as having vector number 8 and a

natural order priority of 0. Thus, the INT0IF bit is found

in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP

bits in the first position of IPC0 (IPC0<2:0>).

7.3.1

INTCON1 AND INTCON2

Global interrupt control functions are controlled from

INTCON1 and INTCON2. INTCON1 contains the

Interrupt Nesting Disable (NSTDIS) bit as well as the

control and status flags for the processor trap sources.

The INTCON2 register controls the external interrupt

request signal behavior and the use of the Alternate

Interrupt Vector Table.

7.3.6

STATUS/CONTROL REGISTERS

Although they are not specifically part of the interrupt

control hardware, two of the CPU Control registers

contain bits that control interrupt functionality.

7.3.2

IFSx

The IFS registers maintain all of the interrupt request

flags. Each source of interrupt has a status bit, which is

set by the respective peripherals or external signal and

is cleared via software.

• The CPU STATUS register, SR, contains the

IPL<2:0> bits (SR<7:5>). These bits indicate the

current CPU interrupt priority level. The user

software can change the current CPU priority

level by writing to the IPL bits.

7.3.3

IECx

• The CORCON register contains the IPL3 bit

which, together with IPL<2:0>, also indicates the

current CPU priority level. IPL3 is a read-only bit

so that trap events cannot be masked by the user

software.

The IEC registers maintain all of the interrupt enable

bits. These control bits are used to individually enable

interrupts from the peripherals or external signals.

All Interrupt registers are described in Register 7-1

through Register 7-29.

DS70293F-page 73

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(1)

REGISTER 7-1:

SR: CPU STATUS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

DC

bit 15

bit 8

R/W-0⁽³⁾

IPL<2:0>⁽²⁾

R/W-0⁽³⁾

R-0

RA

R/W-0

N

R/W-0

OV

R/W-0

Z

R/W-0

C

bit 7

bit 0

Legend:

C = Clear only bit

S = Set only bit

‘1’ = Bit is set

R = Readable bit

W = Writable bit

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n = Value at POR

x = Bit is unknown

bit 7-5

IPL<2:0>: CPU Interrupt Priority Level Status bits⁽²⁾

111= CPU Interrupt Priority Level is 7 (15), user interrupts disabled

110= CPU Interrupt Priority Level is 6 (14)

101= CPU Interrupt Priority Level is 5 (13)

100= CPU Interrupt Priority Level is 4 (12)

011= CPU Interrupt Priority Level is 3 (11)

010= CPU Interrupt Priority Level is 2 (10)

001= CPU Interrupt Priority Level is 1 (9)

000= CPU Interrupt Priority Level is 0 (8)

Note 1: For complete register details, see Register 3-1.

2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when

IPL<3> = 1.

3: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.

(1)

REGISTER 7-2:

CORCON: CORE CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

R/C-0

IPL3⁽²⁾

R/W-0

PSV

U-0

—

U-0

—

bit 7

Legend:

C = Clear only bit

W = Writable bit

‘x = Bit is unknown

R = Readable bit

0’ = Bit is cleared

-n = Value at POR

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

bit 3

IPL3: CPU Interrupt Priority Level Status bit 3⁽²⁾

1= CPU interrupt priority level is greater than 7

0= CPU interrupt priority level is 7 or less

Note 1: For complete register details, see Register 3-2.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

DS70293F-page 74

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-3:

INTCON1: INTERRUPT CONTROL REGISTER 1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

NSTDIS

bit 15

bit 8

bit 0

U-0

—

R/W-0

U-0

—

DIV0ERR

DMACERR MATHERR ADDRERR

STKERR

OSCFAIL

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

NSTDIS: Interrupt Nesting Disable bit

1= Interrupt nesting is disabled

0= Interrupt nesting is enabled

bit 14-7

bit 6

Unimplemented: Read as ‘0’

DIV0ERR: Arithmetic Error Status bit

1= Math error trap was caused by a divide by zero

0= Math error trap was not caused by a divide by zero

bit 5

bit 4

DMACERR: DMA Controller Error Status bit

1= DMA controller error trap has occurred

0= DMA controller error trap has not occurred

MATHERR: Arithmetic Error Status bit

1= Math error trap has occurred

0= Math error trap has not occurred

bit 3

bit 2

bit 1

bit 0

ADDRERR: Address Error Trap Status bit

1= Address error trap has occurred

0= Address error trap has not occurred

STKERR: Stack Error Trap Status bit

1= Stack error trap has occurred

0= Stack error trap has not occurred

OSCFAIL: Oscillator Failure Trap Status bit

1= Oscillator failure trap has occurred

0= Oscillator failure trap has not occurred

Unimplemented: Read as ‘0’

DS70293F-page 75

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-4:

INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-0

ALTIVT

bit 15

R-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

DISI

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

INT2EP

INT1EP

INT0EP

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

ALTIVT: Enable Alternate Interrupt Vector Table bit

1= Use alternate vector table

0= Use standard (default) vector table

DISI: DISIInstruction Status bit

1= DISIinstruction is active

0= DISIinstruction is not active

bit 13-3

bit 2

Unimplemented: Read as ‘0’

INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

bit 1

bit 0

INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

DS70293F-page 76

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-5:

IFS0: INTERRUPT FLAG STATUS REGISTER 0

U-0

—

R/W-0

AD1IF

R/W-0

SPI1IF

R/W-0

T3IF

DMA1IF

U1TXIF

U1RXIF

SPI1EIF

bit 15

bit 8

R/W-0

T2IF

R/W-0

OC2IF

R/W-0

IC2IF

R/W-0

T1IF

R/W-0

OC1IF

R/W-0

IC1IF

R/W-0

INT0IF

DMA0IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

DMA1IF: DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 13

bit 12

bit 11

bit 10

bit 9

AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U1TXIF: UART1 Transmitter Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U1RXIF: UART1 Receiver Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPI1IF: SPI1 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPI1EIF: SPI1 Error Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8

T3IF: Timer3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 7

T2IF: Timer2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 6

OC2IF: Output Compare Channel 2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 5

IC2IF: Input Capture Channel 2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 4

DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 3

T1IF: Timer1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DS70293F-page 77

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-5:

IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)

bit 2

bit 1

bit 0

OC1IF: Output Compare Channel 1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

IC1IF: Input Capture Channel 1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT0IF: External Interrupt 0 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DS70293F-page 78

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-6:

IFS1: INTERRUPT FLAG STATUS REGISTER 1

R/W-0

INT2IF

R/W-0

T5IF

R/W-0

T4IF

R/W-0

OC4IF

R/W-0

OC3IF

R/W-0

U2TXIF

U2RXIF

DMA2IF

bit 15

bit 8

R/W-0

IC8IF

R/W-0

IC7IF

U-0

—

R/W-0

INT1IF

R/W-0

CNIF

R/W-0

CMIF

R/W-0

MI2C1IF

SI2C1IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

U2TXIF: UART2 Transmitter Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U2RXIF: UART2 Receiver Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT2IF: External Interrupt 2 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T5IF: Timer5 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T4IF: Timer4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

OC4IF: Output Compare Channel 4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

OC3IF: Output Compare Channel 3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8

DMA2IF: DMA Channel 2 Data Transfer Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 7

IC8IF: Input Capture Channel 8 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 6

IC7IF: Input Capture Channel 7 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 5

bit 4

Unimplemented: Read as ‘0’

INT1IF: External Interrupt 1 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 3

CNIF: Input Change Notification Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DS70293F-page 79

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-6:

IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED)

bit 2

bit 1

bit 0

CMIF: Comparator Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

MI2C1IF: I2C1 Master Events Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DS70293F-page 80

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-7:

IFS2: INTERRUPT FLAG STATUS REGISTER 2

U-0

—

R/W-0

PMPIF

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

DMA4IF

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

C1IF⁽¹⁾

R/W-0

C1RXIF⁽¹⁾

R/W-0

SPI2IF

R/W-0

DMA3IF

SPI2EIF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

DMA4IF: DMA Channel 4 Data Transfer Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 13

PMPIF: Parallel Master Port Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 12-5

bit 4

Unimplemented: Read as ‘0’

DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 3

bit 2

bit 1

bit 0

C1IF: ECAN1 Event Interrupt Flag Status bit⁽¹⁾

1= Interrupt request has occurred

0= Interrupt request has not occurred

C1RXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit⁽¹⁾

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPI2IF: SPI2 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPI2EIF: SPI2 Error Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

Note 1: Interrupts disabled on devices without ECAN™ modules.

DS70293F-page 81

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-8:

IFS3: INTERRUPT FLAG STATUS REGISTER 3

U-0

—

R/W-0

RTCIF

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

DMA5IF

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

RTCIF: Real-Time Clock and Calendar Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 13

DMA5IF: DMA Channel 5 Data Transfer Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 12-0

Unimplemented: Read as ‘0’

DS70293F-page 82

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-9:

IFS4: INTERRUPT FLAG STATUS REGISTER 4

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

C1TXIF⁽¹⁾

R/W-0

CRCIF

R/W-0

U2EIF

R/W-0

U1EIF

U-0

—

DMA7IF

DMA6IF

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-7

bit 6

Unimplemented: Read as ‘0’

C1TXIF: ECAN1 Transmit Data Request Interrupt Flag Status bit⁽¹⁾

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

DMA7IF: DMA Channel 7 Data Transfer Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DMA6IF: DMA Channel 6 Data Transfer Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

CRCIF: CRC Generator Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U2EIF: UART2 Error Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U1EIF: UART1 Error Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

Unimplemented: Read as ‘0’

Note 1: Interrupts disabled on devices without ECAN™ modules.

DS70293F-page 83

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0

U-0

—

R/W-0

AD1IE

R/W-0

T3IE

DMA1IE

U1TXIE

U1RXIE

SPI1IE

SPI1EIE

bit 15

bit 8

R/W-0

T2IE

R/W-0

OC2IE

R/W-0

IC2IE

R/W-0

T1IE

R/W-0

OC1IE

R/W-0

IC1IE

R/W-0

DMA0IE

INT0IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

DMA1IE: DMA Channel 1 Data Transfer Complete Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 13

bit 12

bit 11

bit 10

bit 9

AD1IE: ADC1 Conversion Complete Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

U1TXIE: UART1 Transmitter Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

U1RXIE: UART1 Receiver Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

SPI1IE: SPI1 Event Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

SPI1EIE: SPI1 Error Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 8

T3IE: Timer3 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 7

T2IE: Timer2 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 6

OC2IE: Output Compare Channel 2 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 5

IC2IE: Input Capture Channel 2 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 4

DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 3

T1IE: Timer1 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

DS70293F-page 84

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)

bit 2

bit 1

bit 0

OC1IE: Output Compare Channel 1 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

IC1IE: Input Capture Channel 1 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

INT0IE: External Interrupt 0 Flag Status bit

1= Interrupt request enabled

0= Interrupt request not enabled

DS70293F-page 85

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1

R/W-0

T5IE

R/W-0

T4IE

R/W-0

OC4IE

R/W-0

OC3IE

R/W-0

U2TXIE

U2RXIE

INT2IE

DMA2IE

bit 15

bit 8

R/W-0

IC8IE

R/W-0

IC7IE

U-0

—

R/W-0

CNIE

R/W-0

CMIE

R/W-0

INT1IE

MI2C1IE

SI2C1IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

U2TXIE: UART2 Transmitter Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

U2RXIE: UART2 Receiver Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

INT2IE: External Interrupt 2 Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

T5IE: Timer5 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

T4IE: Timer4 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

OC4IE: Output Compare Channel 4 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

OC3IE: Output Compare Channel 3 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 8

DMA2IE: DMA Channel 2 Data Transfer Complete Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 7

IC8IE: Input Capture Channel 8 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 6

IC7IE: Input Capture Channel 7 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 5

bit 4

Unimplemented: Read as ‘0’

INT1IE: External Interrupt 1 Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 3

CNIE: Input Change Notification Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

DS70293F-page 86

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED)

bit 2

bit 1

bit 0

CMIE: Comparator Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

MI2C1IE: I2C1 Master Events Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

SI2C1IE: I2C1 Slave Events Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

DS70293F-page 87

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

DMA4IE

PMPIE

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

C1IE⁽¹⁾

R/W-0

C1RXIE⁽¹⁾

R/W-0

DMA3IE

SPI2IE

SPI2EIE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

DMA4IE: DMA Channel 4 Data Transfer Complete Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 13

PMPIE: Parallel Master Port Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 12-5

bit 4

Unimplemented: Read as ‘0’

DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request has enabled

bit 3

bit 2

bit 1

bit 0

C1IE: ECAN1 Event Interrupt Enable bit⁽¹⁾

1= Interrupt request enabled

0= Interrupt request not enabled

C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit⁽¹⁾

1= Interrupt request enabled

0= Interrupt request not enabled

SPI2IE: SPI2 Event Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

SPI2EIE: SPI2 Error Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

Note 1: Interrupts disabled on devices without ECAN™ modules.

DS70293F-page 88

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3

U-0

—

R/W-0

RTCIE

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

DMA5IE

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

RTCIE: Real-Time Clock and Calendar Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 13

DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 12-0

Unimplemented: Read as ‘0’

DS70293F-page 89

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

C1TXIE⁽¹⁾

R/W-0

U2EIE

R/W-0

U1EIE

U-0

—

DMA7IE

DMA6IE

CRCIE

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-7

bit 6

Unimplemented: Read as ‘0’

C1TXIE: ECAN1 Transmit data request Interrupt Enable bit⁽¹⁾

1= Interrupt request occurred

0= Interrupt request not occurred

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

DMA7IE: DMA Channel 7 Data Transfer Complete Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

DMA6IE: DMA Channel 6 Data Transfer Complete Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

CRCIE: CRC Generator Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

U2EIE: UART2 Error Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

U1EIE: UART1 Error Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

Unimplemented: Read as ‘0’

Note 1: Interrupts disabled on devices without ECAN™ modules.

DS70293F-page 90

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

bit 0

T1IP<2:0>

OC1IP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

IC1IP<2:0>

INT0IP<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

T1IP<2:0>: Timer1 Interrupt Priority bits

bit 14-12

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

INT0IP<2:0>: External Interrupt 0 Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70293F-page 91

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

bit 0

T2IP<2:0>

OC2IP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

IC2IP<2:0>

DMA0IP<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

T2IP<2:0>: Timer2 Interrupt Priority bits

bit 14-12

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70293F-page 92

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

bit 0

U1RXIP<2:0>

SPI1IP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

SPI1EIP<2:0>

T3IP<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

SPI1IP<2:0>: SPI1 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

T3IP<2:0>: Timer3 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70293F-page 93

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

bit 0

DMA1IP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

AD1IP<2:0>

U1TXIP<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

DMA1IP<2:0>: DMA Channel 1 Data Transfer Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70293F-page 94

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

bit 0

CNIP<2:0>

CMIP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

MI2C1IP<2:0>

SI2C1IP<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

CNIP<2:0>: Change Notification Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

CMIP<2:0>: Comparator Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70293F-page 95

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

bit 0

IC8IP<2:0>

IC7IP<2:0>

bit 15

U-0

—

U-1

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

INT1IP<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

INT1IP<2:0>: External Interrupt 1 Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70293F-page 96

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

bit 0

T4IP<2:0>

OC4IP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

OC3IP<2:0>

DMA2IP<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

T4IP<2:0>: Timer4 Interrupt Priority bits

bit 14-12

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70293F-page 97

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

bit 0

U2TXIP<2:0>

U2RXIP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

INT2IP<2:0>

T5IP<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

INT2IP<2:0>: External Interrupt 2 Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

T5IP<2:0>: Timer5 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70293F-page 98

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8

U-0

—

R/W-1

R/W-0

C1IP<2:0>⁽¹⁾

R/W-0

U-0

—

R/W-1

R/W-0

C1RXIP<2:0>⁽¹⁾

R/W-0

bit 8

R/W-0

bit 0

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

SPI2IP<2:0>

SPI2EIP<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

C1IP<2:0>: ECAN1 Event Interrupt Priority bits⁽¹⁾

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

C1RXIP<2:0>: ECAN1 Receive Data Ready Interrupt Priority bits⁽¹⁾

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

SPI2IP<2:0>: SPI2 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

Note 1: Interrupts disabled on devices without ECAN™ modules.

DS70293F-page 99

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

DMA3IP<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-0

Unimplemented: Read as ‘0’

DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70293F-page 100

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-25: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

bit 8

DMA4IP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

PMPIP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

DMA4IP<2:0>: DMA Channel 4 Data Transfer Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

PMPIP<2:0>: Parallel Master Port Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

DS70293F-page 101

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-26: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

bit 8

RTCIP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

DMA5IP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Flag Status bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

DMA5IP<2:0>: DMA Channel 5 Data Transfer Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

DS70293F-page 102

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-27: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

CRCIP<2:0>

U2EIP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U1EIP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

CRCIP<2:0>: CRC Generator Error Interrupt Flag Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

U2EIP<2:0>: UART2 Error Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

U1EIP<2:0>: UART1 Error Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

DS70293F-page 103

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-28: IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

C1TXIP<2:0>⁽¹⁾

R/W-0

bit 8

R/W-0

bit 0

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

DMA7IP<2:0>

DMA6IP<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

C1TXIP<2:0>: ECAN1 Transmit Data Request Interrupt Priority bits⁽¹⁾

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

DMA7IP<2:0>: DMA Channel 7 Data Transfer Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

Note 1: Interrupts disabled on devices without ECAN™ modules.

DS70293F-page 104

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 7-29: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R-0

ILR<3:0>

bit 15

bit 8

bit 0

U-0

—

R-0

VECNUM<6:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

bit 11-8

Unimplemented: Read as ‘0’

ILR: New CPU Interrupt Priority Level bits

1111= CPU Interrupt Priority Level is 15

•

0001= CPU Interrupt Priority Level is 1

0000= CPU Interrupt Priority Level is 0

bit 7

Unimplemented: Read as ‘0’

bit 6-0

VECNUM: Vector Number of Pending Interrupt bits

0111111= Interrupt Vector pending is number 135

•

0000001= Interrupt Vector pending is number 9

0000000= Interrupt Vector pending is number 8

DS70293F-page 105

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

7.4.3

TRAP SERVICE ROUTINE

7.4

Interrupt Setup Procedures

A Trap Service Routine (TSR) is coded like an ISR,

except that the appropriate trap status flag in the

INTCON1 register must be cleared to avoid re-entry

into the TSR.

7.4.1

INITIALIZATION

To configure an interrupt source at initialization:

1. Set the NSTDIS bit (INTCON1<15>) if nested

interrupts are not desired.

7.4.4

INTERRUPT DISABLE

2. Select the user-assigned priority level for the

interrupt source by writing the control bits in the

appropriate IPCx register. The priority level

depends on the specific application and type of

interrupt source. If multiple priority levels are not

desired, the IPCx register control bits for all

enabled interrupt sources can be programmed

to the same non-zero value.

All user interrupts can be disabled using this

procedure:

1. Push the current SR value onto the software

stack using the PUSHinstruction.

2. Force the CPU to priority level 7 by inclusive

ORing the value 0xOE with SRL.

To enable user interrupts, the POP instruction can be

used to restore the previous SR value.

Note: At a device Reset, the IPCx registers are

initialized such that all user interrupt

sources are assigned to priority level 4.

Note:

Only user interrupts with a priority level of

7 or lower can be disabled. Trap sources

(level 8-level 15) cannot be disabled.

3. Clear the interrupt flag status bit associated with

the peripheral in the associated IFSx register.

The DISI instruction provides a convenient way to

disable interrupts of priority levels 1-6 for a fixed period

of time. Level 7 interrupt sources are not disabled by

the DISI instruction.

4. Enable the interrupt source by setting the inter-

rupt enable control bit associated with the

source in the appropriate IECx register.

7.4.2

INTERRUPT SERVICE ROUTINE

The method used to declare an ISR and initialize the

IVT with the correct vector address depends on the

programming language (C or assembler) and the

language development tool suite used to develop the

application.

In general, the user application must clear the interrupt

flag in the appropriate IFSx register for the source of

interrupt that the ISR handles. Otherwise, the program

re-enters the ISR immediately after exiting the routine.

If the ISR is coded in assembly language, it must be

terminated using a RETFIEinstruction to unstack the

saved PC value, SRL value and old CPU priority level.

DS70293F-page 106

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

Direct Memory Access (DMA) is a very efficient

mechanism of copying data between peripheral SFRs

(e.g., UART Receive register, Input Capture 1 buffer),

8.0

DIRECT MEMORY ACCESS

(DMA)

and buffers or variables stored in RAM, with minimal

Note 1: This data sheet summarizes the features

of the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and

CPU intervention. The DMA controller can

automatically copy entire blocks of data without

requiring the user software to read or write the

peripheral Special Function Registers (SFRs) every

time a peripheral interrupt occurs. The DMA controller

uses a dedicated bus for data transfers and therefore,

does not steal cycles from the code execution flow of

the CPU. To exploit the DMA capability, the

corresponding user buffers or variables must be

located in DMA RAM.

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to Section 38. “Direct Memory

Access (DMA) (Part III)” (DS70215) of

the “dsPIC33F/PIC24H Family Refer-

ence Manual”, which is available from the

Microchip website (www.microchip.com).

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 peripherals that can

utilize DMA are listed in Table 8-1.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

TABLE 8-1:

DMA CHANNEL TO PERIPHERAL ASSOCIATIONS

DMAxPAD Register

Values to Read from

Peripheral

DMAxPAD Register

Values to Write to

Peripheral

DMAxREQ Register

IRQSEL<6:0> Bits

Peripheral to DMA Association

INT0 – External Interrupt 0

IC1 – Input Capture 1

0000000

0000001

0000010

0000101

0000110

0000111

0001000

0001010

0001011

0001100

0001101

0011110

0011111

0100001

0100010

0101101

1000110

—

0x0140 (IC1BUF)

—

OC1 – Output Compare 1 Data

OC1 – Output Compare 1 Secondary Data

IC2 – Input Capture 2

—

0x0182 (OC1R)

—

0x0180 (OC1RS)

0x0144 (IC2BUF)

—

OC2 – Output Compare 2 Data

OC2 – Output Compare 2 Secondary Data

TMR2 – Timer2

—

0x0188 (OC2R)

—

0x0186 (OC2RS)

—

TMR3 – Timer3

—

0x0248 (SPI1BUF)

—

SPI1 – Transfer Done

0x0248 (SPI1BUF)

0x0226 (U1RXREG)

—

UART1RX – UART1 Receiver

UART1TX – UART1 Transmitter

ADC1 – ADC1 Convert Done

UART2RX – UART2 Receiver

UART2TX – UART2 Transmitter

SPI2 – Transfer Done

0x0224 (U1TXREG)

—

0x0300 (ADC1BUF0)

0x0236 (U2RXREG)

—

0x0234 (U2TXREG)

0x0268 (SPI2BUF)

—

0x0268 (SPI2BUF)

0x0440 (C1RXD)

0x0608 (PMDIN1)

—

ECAN1 – RX Data Ready

PMP – Master Data Transfer

ECAN1 – TX Data Request

0x0608 (PMDIN1)

0x0442 (C1TXD)

DS70293F-page 107

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

The DMA controller features eight identical data

transfer channels.

• Byte or word transfers

• Fixed priority channel arbitration

• Manual (software) or Automatic (peripheral DMA

requests) transfer initiation

Each channel has its own set of control and status

registers. Each DMA channel can be configured to

copy data either from buffers stored in dual port DMA

RAM to peripheral SFRs, or from peripheral SFRs to

buffers in DMA RAM.

• One-Shot or Auto-Repeat block transfer modes

• Ping-Pong mode (automatic switch between two

DPSRAM start addresses after each block

transfer complete)

The DMA controller supports the following features:

• Eight DMA channels

• DMA request for each channel can be selected

from any supported interrupt source

• Register Indirect with Post-increment Addressing

mode

• Debug support features

For each DMA channel, a DMA interrupt request is

• Register Indirect without Post-increment

Addressing mode

generated when

a

block transfer is complete.

Alternatively, an interrupt can be generated when half of

the block has been filled.

• Peripheral Indirect Addressing mode (peripheral

generates destination address)

• CPU interrupt after half or full block transfer

complete

FIGURE 8-1:

TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS

Peripheral Indirect Address

DMA Controller

DMA

Ready

Peripheral 3

DMA

DMA RAM

SRAM

Channels

PORT 1 PORT 2

CPU DMA

SRAM X-Bus

DMA DS Bus

CPU Peripheral DS Bus

CPU DMA

CPU

DMA

Non-DMA

Ready

Peripheral

DMA

Ready

Peripheral 2

DMA

Ready

Peripheral 1

CPU

Note:

CPU and DMA address buses are not shown for clarity.

DS70293F-page 108

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

The DMAxCON, DMAxREQ, DMAxPAD and

DMAxCNT are all conventional read/write registers.

8.1

DMAC Registers

Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)

contains the following registers:

Reads of DMAxSTA or DMAxSTB reads the contents

of the DMA RAM Address register. Writes to

DMAxSTA or DMAxSTB write to the registers. This

allows the user to determine the DMA buffer pointer

value (address) at any time.

• A 16-bit DMA Channel Control register

(DMAxCON)

• A 16-bit DMA Channel IRQ Select register

(DMAxREQ)

The interrupt flags (DMAxIF) are located in an IFSx

register in the interrupt controller. The corresponding

interrupt enable control bits (DMAxIE) are located in

an IECx register in the interrupt controller, and the

corresponding interrupt priority control bits (DMAxIP)

are located in an IPCx register in the interrupt

controller.

• A 16-bit DMA RAM Primary Start Address register

(DMAxSTA)

• A 16-bit DMA RAM Secondary Start Address

register (DMAxSTB)

• A 16-bit DMA Peripheral Address register

(DMAxPAD)

• A 10-bit DMA Transfer Count register (DMAxCNT)

An additional pair of status registers, DMACS0 and

DMACS1, are common to all DMAC channels.

DMACS0 contains the DMA RAM and SFR write

collision flags, XWCOLx and PWCOLx, respectively.

DMACS1 indicates DMA channel and Ping-Pong mode

status.

DS70293F-page 109

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 8-1:

DMAxCON: DMA CHANNEL x CONTROL REGISTER

R/W-0

CHEN

R/W-0

SIZE

R/W-0

DIR

R/W-0

HALF

R/W-0

U-0

—

U-0

—

U-0

—

NULLW

bit 15

bit 8

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0

AMODE<1:0>

MODE<1:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

bit 12

bit 11

CHEN: Channel Enable bit

1= Channel enabled

0= Channel disabled

SIZE: Data Transfer Size bit

1= Byte

0= Word

DIR: Transfer Direction bit (source/destination bus select)

1= Read from DMA RAM address, write to peripheral address

0= Read from peripheral address, write to DMA RAM address

HALF: Early Block Transfer Complete Interrupt Select bit

1= Initiate block transfer complete interrupt when half of the data has been moved

0= Initiate block transfer complete interrupt when all of the data has been moved

NULLW: Null Data Peripheral Write Mode Select bit

1= Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear)

0= Normal operation

bit 10-6

bit 5-4

Unimplemented: Read as ‘0’

AMODE<1:0>: DMA Channel Operating Mode Select bits

11= Reserved (acts as Peripheral Indirect Addressing mode)

10= Peripheral Indirect Addressing mode

01= Register Indirect without Post-Increment mode

00= Register Indirect with Post-Increment mode

bit 3-2

bit 1-0

Unimplemented: Read as ‘0’

MODE<1:0>: DMA Channel Operating Mode Select bits

11= One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer)

10= Continuous, Ping-Pong modes enabled

01= One-Shot, Ping-Pong modes disabled

00= Continuous, Ping-Pong modes disabled

DS70293F-page 110

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 8-2:

DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER

R/W-0

FORCE⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

bit 0

U-0

—

R/W-0

U-0

R/W-0

IRQSEL<6:0>⁽²⁾

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

FORCE: Force DMA Transfer bit⁽¹⁾

1= Force a single DMA transfer (Manual mode)

0= Automatic DMA transfer initiation by DMA request

bit 14-7

bit 6-0

Unimplemented: Read as ‘0’

IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits⁽²⁾

0000000-1111111= DMAIRQ0-DMAIRQ127 selected to be Channel DMAREQ

Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced

DMA transfer is complete.

2: Refer to Table 7-1 for a complete listing of IRQ numbers for all interrupt sources.

DS70293F-page 111

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(1)

REGISTER 8-3:

DMAxSTA: DMA CHANNEL x RAM START ADDRESS REGISTER A

R/W-0

bit 8

R/W-0

bit 0

STA<15:8>

bit 15

R/W-0

bit 7

R/W-0

STA<7:0>

R/W-0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

STA<15:0>: Primary DMA RAM Start Address bits (source or destination)

Note 1: A read of this address register returns the current contents of the DMA RAM Address register, not the con-

tents written to STA<15:0>. If the channel is enabled (i.e., active), writes to this register may result in

unpredictable behavior of the DMA channel and should be avoided.

(1)

REGISTER 8-4:

DMAxSTB: DMA CHANNEL x RAM START ADDRESS REGISTER B

R/W-0

bit 8

R/W-0

bit 0

STB<15:8>

bit 15

R/W-0

bit 7

R/W-0

STB<7:0>

R/W-0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

STB<15:0>: Secondary DMA RAM Start Address bits (source or destination)

Note 1: A read of this address register returns the current contents of the DMA RAM Address register, not the con-

tents written to STB<15:0>. If the channel is enabled (i.e., active), writes to this register may result in

unpredictable behavior of the DMA channel and should be avoided.

DS70293F-page 112

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(1)

REGISTER 8-5:

R/W-0

DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER

R/W-0

bit 8

R/W-0

bit 0

PAD<15:8>

bit 15

R/W-0

bit 7

R/W-0

R/W-0 R/W-0

PAD<7:0>

R/W-0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

PAD<15:0>: Peripheral Address Register bits

Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the

DMA channel and should be avoided.

(1)

REGISTER 8-6:

DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CNT<9:8>⁽²⁾

bit 15

bit 8

R/W-0

bit 0

R/W-0

bit 7

R/W-0

CNT<7:0>⁽²⁾

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-10

bit 9-0

Unimplemented: Read as ‘0’

CNT<9:0>: DMA Transfer Count Register bits⁽²⁾

Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the

DMA channel and should be avoided.

2: Number of DMA transfers = CNT<9:0> + 1.

DS70293F-page 113

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 8-7:

DMACS0: DMA CONTROLLER STATUS REGISTER 0

R/C-0

PWCOL7

bit 15

R/C-0

PWCOL6

PWCOL5

PWCOL4

PWCOL3

PWCOL2

PWCOL1

PWCOL0

bit 8

R/C-0

XWCOL7

bit 7

R/C-0

XWCOL6

XWCOL5

XWCOL4

XWCOL3

XWCOL2

XWCOL1

XWCOL0

bit 0

Legend:

C = Clear only bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

W = Writable bit

‘1’ = Bit is set

-n = Value at POR

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

PWCOL7: Channel 7 Peripheral Write Collision Flag bit

1= Write collision detected

0= No write collision detected

PWCOL6: Channel 6 Peripheral Write Collision Flag bit

1= Write collision detected

0= No write collision detected

PWCOL5: Channel 5 Peripheral Write Collision Flag bit

1= Write collision detected

0= No write collision detected

PWCOL4: Channel 4 Peripheral Write Collision Flag bit

1= Write collision detected

0= No write collision detected

PWCOL3: Channel 3 Peripheral Write Collision Flag bit

1= Write collision detected

0= No write collision detected

PWCOL2: Channel 2 Peripheral Write Collision Flag bit

1= Write collision detected

0= No write collision detected

PWCOL1: Channel 1 Peripheral Write Collision Flag bit

1= Write collision detected

0= No write collision detected

bit 8

PWCOL0: Channel 0 Peripheral Write Collision Flag bit

1= Write collision detected

0= No write collision detected

bit 7

XWCOL7: Channel 7 DMA RAM Write Collision Flag bit

1= Write collision detected

0= No write collision detected

bit 6

XWCOL6: Channel 6 DMA RAM Write Collision Flag bit

1= Write collision detected

0= No write collision detected

bit 5

XWCOL5: Channel 5 DMA RAM Write Collision Flag bit

1= Write collision detected

0= No write collision detected

bit 4

XWCOL4: Channel 4 DMA RAM Write Collision Flag bit

1= Write collision detected

0= No write collision detected

DS70293F-page 114

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 8-7:

DMACS0: DMA CONTROLLER STATUS REGISTER 0 (CONTINUED)

bit 3

bit 2

bit 1

bit 0

XWCOL3: Channel 3 DMA RAM Write Collision Flag bit

1= Write collision detected

0= No write collision detected

XWCOL2: Channel 2 DMA RAM Write Collision Flag bit

1= Write collision detected

0= No write collision detected

XWCOL1: Channel 1 DMA RAM Write Collision Flag bit

1= Write collision detected

0= No write collision detected

XWCOL0: Channel 0 DMA RAM Write Collision Flag bit

1= Write collision detected

0= No write collision detected

DS70293F-page 115

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 8-8:

DMACS1: DMA CONTROLLER STATUS REGISTER 1

U-0

—

U-0

—

U-0

—

U-0

—

R-1

R-0

LSTCH<3:0>

bit 15

bit 8

R-0

PPST7

bit 7

R-0

PPST6

PPST5

PPST4

PPST3

PPST2

PPST1

PPST0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

bit 11-8

Unimplemented: Read as ‘0’

LSTCH<3:0>: Last DMA Channel Active bits

1111= No DMA transfer has occurred since system Reset

1110-1000= Reserved

0111= Last data transfer was by DMA Channel 7

0110= Last data transfer was by DMA Channel 6

0101= Last data transfer was by DMA Channel 5

0100= Last data transfer was by DMA Channel 4

0011= Last data transfer was by DMA Channel 3

0010= Last data transfer was by DMA Channel 2

0001= Last data transfer was by DMA Channel 1

0000= Last data transfer was by DMA Channel 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PPST7: Channel 7 Ping-Pong Mode Status Flag bit

1= DMA7STB register selected

0= DMA7STA register selected

PPST6: Channel 6 Ping-Pong Mode Status Flag bit

1= DMA6STB register selected

0= DMA6STA register selected

PPST5: Channel 5 Ping-Pong Mode Status Flag bit

1= DMA5STB register selected

0= DMA5STA register selected

PPST4: Channel 4 Ping-Pong Mode Status Flag bit

1= DMA4STB register selected

0= DMA4STA register selected

PPST3: Channel 3 Ping-Pong Mode Status Flag bit

1= DMA3STB register selected

0= DMA3STA register selected

PPST2: Channel 2 Ping-Pong Mode Status Flag bit

1= DMA2STB register selected

0= DMA2STA register selected

PPST1: Channel 1 Ping-Pong Mode Status Flag bit

1= DMA1STB register selected

0= DMA1STA register selected

PPST0: Channel 0 Ping-Pong Mode Status Flag bit

1= DMA0STB register selected

0= DMA0STA register selected

DS70293F-page 116

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 8-9:

R-0

DSADR: MOST RECENT DMA RAM ADDRESS

R-0

DSADR<15:8>

bit 15

R-0

bit 8

bit 0

R-0

DSADR<7:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits

DS70293F-page 117

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

NOTES:

DS70293F-page 118

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 oscillator system

provides:

9.0

OSCILLATOR

CONFIGURATION

Note 1: This data sheet summarizes the features

of the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and

• External and internal oscillator options as clock

sources

• An on-chip Phase-Locked Loop (PLL) to scale the

internal operating frequency to the required

system clock frequency

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to Section 39. “Oscillator (Part

III)” (DS70216) of the “dsPIC33F/

PIC24H Family Reference Manual”,

which is available from the Microchip

website (www.microchip.com).

• An internal FRC oscillator that can also be used

with the PLL, thereby allowing full-speed

operation without any external clock generation

hardware

• Clock switching between various clock sources

• Programmable clock postscaler for system power

savings

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and takes fail-safe measures

• An Oscillator Control register (OSCCON)

• Nonvolatile Configuration bits for main oscillator

selection.

A simplified diagram of the oscillator system is shown

in Figure 9-1.

FIGURE 9-1:

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

OSCILLATOR SYSTEM DIAGRAM

DOZE<2:0>

Primary Oscillator

OSC1

POSCCLK

XT, HS, EC

S2

(3)

CY

F

(2)

R

XTPLL, HSPLL,

ECPLL, FRCPLL

S3

S1

(1)

S1/S3

PLL

(1)

FVCO

OSC2

(3)

P

F

POSCMD<1:0>

÷ 2

FRC

Oscillator

FRCDIVN

S7

FOSC

FRCDIV<2:0>

FRCDIV16

FRC

TUN<5:0>

S6

S0

÷ 16

LPRC

Oscillator

S5

Secondary Oscillator

SOSC

SOSCO

SOSCI

S4

LPOSCEN

Clock Switch

Reset

Clock Fail

S7

NOSC<2:0> FNOSC<2:0>

WDT, PWRT,

FSCM

Timer1

Note 1: See Figure 9-2 for PLL details.

2: If the Oscillator is used with XT or HS modes, an extended parallel resistor with the value of 1 MΩ must be connected.

3: The term FP refers to the clock source for all the peripherals, while FCY refers to the clock source for the CPU. Throughout this

document FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze

mode is used in any ratio other than 1:1, which is the default.

DS70293F-page 119

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

9.1.2

SYSTEM CLOCK SELECTION

9.1

CPU Clocking System

The oscillator source used at a device Power-on

Reset event is selected using Configuration bit

settings. The oscillator Configuration bit settings are

located in the Configuration registers in the program

memory. (Refer to Section 25.1 “Configuration

Bits” for further details.) The Initial Oscillator

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 devices provide seven

system clock options:

• Fast RC (FRC) Oscillator

• FRC Oscillator with Phase Locked Loop (PLL)

• Primary (XT, HS or EC) Oscillator

• Primary Oscillator with PLL

Selection

(FOSCSEL<2:0>), and the Primary Oscillator Mode

Select Configuration bits, POSCMD<1:0>

Configuration

bits,

FNOSC<2:0>

• Secondary (LP) Oscillator

(FOSC<1:0>), select the oscillator source that is used

at a Power-on Reset. The FRC primary oscillator is

the default (unprogrammed) selection.

• Low-Power RC (LPRC) Oscillator

• FRC Oscillator with postscaler

The Configuration bits allow users to choose among 12

different clock modes, shown in Table 9-1.

9.1.1

SYSTEM CLOCK SOURCES

The Fast RC (FRC) internal oscillator runs at a nominal

frequency of 7.37 MHz. User software can tune the

FRC frequency. User software can optionally specify a

factor (ranging from 1:2 to 1:256) by which the FRC

clock frequency is divided. This factor is selected using

the FRCDIV<2:0> (CLKDIV<10:8>) bits.

The output of the oscillator (or the output of the PLL if

a PLL mode has been selected) FOSC is divided by 2 to

generate the device instruction clock (FCY) and the

peripheral clock time base (FP). FCY defines the

operating speed of the device, and speeds up to 40

MHz are supported by the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04

architecture.

The primary oscillator can use one of the following as

its clock source:

• Crystal (XT): Crystals and ceramic resonators in

the range of 3 MHz to 10 MHz. The crystal is

connected to the OSC1 and OSC2 pins.

Instruction execution speed or device operating

frequency, FCY, is given by:

• High-Speed Crystal (HS): Crystals in the range of

10 MHz to 40 MHz. The crystal is connected to

the OSC1 and OSC2 pins.

EQUATION 9-1:

DEVICE OPERATING

FREQUENCY

• External Clock (EC): External clock signal is

directly applied to the OSC1 pin.

FOSC

2

-------------

FCY =

The secondary (LP) oscillator is designed for low power

and uses a 32.768 kHz crystal or ceramic resonator.

The LP oscillator uses the SOSCI and SOSCO pins.

The Low-Power RC (LPRC) internal oscIllator runs at a

nominal frequency of 32.768 kHz. It is also used as a

reference clock by the Watchdog Timer (WDT) and

Fail-Safe Clock Monitor (FSCM).

The clock signals generated by the FRC and primary

oscillators can be optionally applied to an on-chip PLL

to provide a wide range of output frequencies for device

operation. PLL configuration is described in

Section 9.1.3 “PLL Configuration”.

The FRC frequency depends on the FRC accuracy

(see Table 28-19) and the value of the FRC Oscillator

Tuning register (see Register 9-4).

DS70293F-page 120

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

For a primary oscillator or FRC oscillator, output ‘FIN’,

the PLL output ‘FOSC’ is given by:

9.1.3

PLL CONFIGURATION

The primary oscillator and internal FRC oscillator can

optionally use an on-chip PLL to obtain higher speeds

of operation. The PLL provides significant flexibility in

selecting the device operating speed. A block diagram

of the PLL is shown in Figure 9-2.

EQUATION 9-2:

FOSC CALCULATION

M

⎛

⎝

⎞

⎠

-------------------

FOSC = F^IN•

N1 • N2

The output of the primary oscillator or FRC, denoted as

‘FIN’, is divided down by a prescale factor (N1) of 2, 3,

... or 33 before being provided to the PLL’s Voltage

Controlled Oscillator (VCO). The input to the VCO must

be selected in the range of 0.8 MHz to 8 MHz. The

prescale factor ‘N1’ is selected using the

PLLPRE<4:0> bits (CLKDIV<4:0>).

For example, suppose a 10 MHz crystal is being used

with the selected oscillator mode of XT with PLL.

• If PLLPRE<4:0> = 0, then N1 = 2. This yields a

VCO input of 10/2 = 5 MHz, which is within the

acceptable range of 0.8-8 MHz.

The PLL Feedback Divisor, selected using the

PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M’,

by which the input to the VCO is multiplied. This factor

must be selected such that the resulting VCO output

frequency is in the range of 100 MHz to 200 MHz.

• If PLLDIV<8:0> = 0x1E, then M = 32. This yields a

VCO output of 5 x 32 = 160 MHz, which is within

the 100-200 MHz ranged needed.

• If PLLPOST<1:0> = 0, then N2 = 2. This provides

a Fosc of 160/2 = 80 MHz. The resultant device

operating speed is 80/2 = 40 MIPS.

The VCO output is further divided by a postscale factor

‘N2’. This factor is selected using the PLLPOST<1:0>

bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and

must be selected such that the PLL output frequency

(FOSC) is in the range of 12.5 MHz to 80 MHz, which

generates device operating speeds of 6.25-40 MIPS.

EQUATION 9-3:

XT WITH PLL MODE

EXAMPLE

FOSC

2

1 10000000 • 32

⎛

⎞

⎠

-------------

-- -----------------------------------

FCY =

=

= 40MIPS

⎝

2

2 • 2

FIGURE 9-2:

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 PLL

BLOCK DIAGRAM

FVCO

100-200 MHz

(1)

0.8-8.0 MHz

12.5-80 MHz

Source (Crystal, External Clock

or Internal RC)

FOSC

PLLPRE

VCO

PLLPOST

X

PLLDIV

N1

Divide by

2-33

N2

Divide by

2, 4, 8

M

Divide by

2-513

Note 1: This frequency range must be satisfied at all times.

DS70293F-page 121

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 9-1:

CONFIGURATION BIT VALUES FOR CLOCK SELECTION

See

Note

Oscillator Mode

Oscillator Source

POSCMD<1:0>

FNOSC<2:0>

Fast RC Oscillator with Divide-by-N

(FRCDIVN)

Internal

xx

111

1, 2

Internal

xx

110

1

Fast RC Oscillator with Divide-by-16

(FRCDIV16)

Low-Power RC Oscillator (LPRC)

Internal

Secondary

Primary

xx

10

101

100

011

1

Secondary (Timer1) Oscillator (SOSC)

Primary Oscillator (HS) with PLL

(HSPLL)

—

Primary Oscillator (XT) with PLL

(XTPLL)

Primary

01

00

011

—

1

Primary Oscillator (EC) with PLL

(ECPLL)

Primary Oscillator (HS)

Primary

Internal

10

01

00

xx

010

001

000

—

1

Primary Oscillator (XT)

Primary Oscillator (EC)

Fast RC Oscillator with PLL (FRCPLL)

Fast RC Oscillator (FRC)

1

Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.

2: This is the default oscillator mode for an unprogrammed (erased) device.

DS70293F-page 122

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(1,3)

REGISTER 9-1:

OSCCON: OSCILLATOR CONTROL REGISTER

U-0

—

R-0

U-0

—

R/W-y

NOSC<2:0>⁽²⁾

R/W-y

bit 8

COSC<2:0>

bit 15

R/W-0

R-0

U-0

—

R/C-0

CF

U-0

—

R/W-0

CLKLOCK

IOLOCK

LOCK

LPOSCEN

OSWEN

bit 7

bit 0

Legend:

y = Value set from Configuration bits on POR

C = Clear only bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

COSC<2:0>: Current Oscillator Selection bits (read-only)

111= Fast RC oscillator (FRC) with Divide-by-n

110= Fast RC oscillator (FRC) with Divide-by-16

101= Low-Power RC oscillator (LPRC)

100= Secondary oscillator (SOSC)

011= Primary oscillator (XT, HS, EC) with PLL

010= Primary oscillator (XT, HS, EC)

001= Fast RC Oscillator (FRC) with divide-by-N and PLL (FRCDIVN + PLL)

000= Fast RC oscillator (FRC)

bit 11

Unimplemented: Read as ‘0’

bit 10-8

NOSC<2:0>: New Oscillator Selection bits⁽²⁾

111= Fast RC oscillator (FRC) with Divide-by-n

110= Fast RC oscillator (FRC) with Divide-by-16

101= Low-Power RC oscillator (LPRC)

100= Secondary oscillator (SOSC)

011= Primary oscillator (XT, HS, EC) with PLL

010= Primary oscillator (XT, HS, EC)

001= Fast RC Oscillator (FRC) with divide-by-N and PLL (FRCDIVN + PLL)

000= Fast RC oscillator (FRC)

bit 7

CLKLOCK: Clock Lock Enable bit

If clock switching is enabled and FSCM is disabled, FCKSM<1:0>(FOSC<7:6>) = 0b01)

1= Clock switching is disabled, system clock source is locked

0= Clock switching is enabled, system clock source can be modified by clock switching

bit 6

bit 5

IOLOCK: Peripheral Pin Select Lock bit

1= Peripherial pin select is locked, write to peripheral pin select registers not allowed

0= Peripherial pin select is not locked, write to peripheral pin select registers allowed

LOCK: PLL Lock Status bit (read-only)

1= Indicates that PLL is in lock, or PLL start-up timer is satisfied

0= Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled

bit 4

Unimplemented: Read as ‘0’

Note 1: Writes to this register require an unlock sequence. Refer to Section 39. “Oscillator (Part III)” (DS70308)

in the “dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip website) for details.

2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.

This applies to clock switches in either direction. In these instances, the application must switch to FRC

mode as a transition clock source between the two PLL modes.

3: This register is reset only on a Power-on Reset (POR).

DS70293F-page 123

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(1,3)

REGISTER 9-1:

OSCCON: OSCILLATOR CONTROL REGISTER

(CONTINUED)

bit 3

CF: Clock Fail Detect bit (read/clear by application)

1= FSCM has detected clock failure

0= FSCM has not detected clock failure

bit 2

bit 1

Unimplemented: Read as ‘0’

LPOSCEN: Secondary (LP) Oscillator Enable bit

1= Enable secondary oscillator

0= Disable secondary oscillator

bit 0

OSWEN: Oscillator Switch Enable bit

1= Request oscillator switch to selection specified by NOSC<2:0> bits

0= Oscillator switch is complete

Note 1: Writes to this register require an unlock sequence. Refer to Section 39. “Oscillator (Part III)” (DS70308)

in the “dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip website) for details.

2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.

This applies to clock switches in either direction. In these instances, the application must switch to FRC

mode as a transition clock source between the two PLL modes.

3: This register is reset only on a Power-on Reset (POR).

DS70293F-page 124

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(2)

REGISTER 9-2:

CLKDIV: CLOCK DIVISOR REGISTER

R/W-0

ROI

R/W-0

R/W-1

R/W-0

DOZEN⁽¹⁾

R/W-0

bit 8

R/W-0

bit 0

DOZE<2:0>

FRCDIV<2:0>

bit 15

R/W-0

R/W-1

U-0

—

R/W-0

PLLPOST<1:0>

PLLPRE<4:0>

bit 7

Legend:

y = Value set from Configuration bits on POR

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

ROI: Recover on Interrupt bit

1= Interrupts clears the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1

0= Interrupts have no effect on the DOZEN bit

bit 14-12

DOZE<2:0>: Processor Clock Reduction Select bits

111= FCY/128

110= FCY/64

101= FCY/32

100= FCY/16

011= FCY/8 (default)

010= FCY/4

001= FCY/2

000= FCY/1

bit 11

DOZEN: DOZE Mode Enable bit⁽¹⁾

1= The DOZE<2:0> bits specify the ratio between the peripheral clocks and the processor clocks

0= Processor clock/peripheral clock ratio forced to 1:1

bit 10-8

FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits

111= FRC divide by 256

110= FRC divide by 64

101= FRC divide by 32

100= FRC divide by 16

011= FRC divide by 8

010= FRC divide by 4

001= FRC divide by 2

000= FRC divide by 1 (default)

bit 7-6

PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)

11= Output/8

10= Reserved

01= Output/4 (default)

00= Output/2

bit 5

Unimplemented: Read as ‘0’

bit 4-0

PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler)

11111= Input/33

•

00001= Input/3

00000= Input/2 (default)

Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.

2: This register is reset only on a Power-on Reset (POR).

DS70293F-page 125

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(1)

REGISTER 9-3:

PLLFBD: PLL FEEDBACK DIVISOR REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

PLLDIV<8>

bit 8

bit 15

R/W-0

bit 7

R/W-0

R/W-1

R/W-0

bit 0

PLLDIV<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-9

bit 8-0

Unimplemented: Read as ‘0’

PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)

111111111= 513

•

000110000= 50 (default)

•

000000010= 4

000000001= 3

000000000= 2

Note 1: This register is reset only on a Power-on Reset (POR).

DS70293F-page 126

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(2)

REGISTER 9-4:

OSCTUN: FRC OSCILLATOR TUNING REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

bit 0

U-0

—

U-0

—

R/W-0

TUN<5:0>⁽¹⁾

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-6

bit 5-0

Unimplemented: Read as ‘0’

TUN<5:0>: FRC Oscillator Tuning bits⁽¹⁾

111111= Center frequency -0.375% (7.345 MHz)

•

100001= Center frequency -11.625% (6.52 MHz)

100000= Center frequency -12% (6.49 MHz)

011111= Center frequency +11.625% (8.23 MHz)

011110= Center frequency +11.25% (8.20 MHz)

•

000001= Center frequency +0.375% (7.40 MHz)

000000= Center frequency (7.37 MHz nominal)

Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the

FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither

characterized nor tested.

2: This register is reset only on a Power-on Reset (POR).

DS70293F-page 127

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(OSCCON<3>) status bits are cleared.

9.2

Clock Switching Operation

3. The new oscillator is turned on by the hardware

if it is not currently running. If a crystal oscillator

must be turned on, the hardware waits until the

Oscillator Start-up Timer (OST) expires. If the

new source is using the PLL, the hardware waits

until a PLL lock is detected (LOCK = 1).

Applications are free to switch among any of the four

clock sources (Primary, LP, FRC and LPRC) under

software control at any time. To limit the possible side

effects of this flexibility, PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04

devices have a safeguard lock built into the switch

process.

4. The hardware waits for 10 clock cycles from the

new clock source and then performs the clock

switch.

Note:

Primary Oscillator mode has three different

submodes (XT, HS and EC), which are

determined by the POSCMD<1:0> Config-

uration bits. While an application can

switch to and from Primary Oscillator

mode in software, it cannot switch among

the different primary submodes without

reprogramming the device.

5. The hardware clears the OSWEN bit to indicate a

successful clock transition. In addition, the NOSC

bit values are transferred to the COSC<2:0>

status bits.

6. The old clock source is turned off at this time,

with the exception of LPRC (if WDT or FSCM

are enabled) or LP (if LPOSCEN remains set).

Note 1: The processor continues to execute code

throughout the clock switching sequence.

Timing-sensitive code should not be

executed during this time.

9.2.1

ENABLING CLOCK SWITCHING

To enable clock switching, the FCKSM1 Configuration

bit in the Configuration register must be programmed to

‘0’. (Refer to Section 25.1 “Configuration Bits” for

further details.) If the FCKSM1 Configuration bit is

unprogrammed (‘1’), the clock switching function and

FSCM function are disabled. This is the default setting.

2: Direct clock switches between any pri-

mary oscillator mode with PLL and

FRCPLL mode are not permitted. This

applies to clock switches in either direc-

tion. In these instances, the application

must switch to FRC mode as a transition

clock source between the two PLL modes.

3: Refer to Section 39. “Oscillator

(Part III)” (DS70308) in the “dsPIC33F/

PIC24H Family Reference Manual” for

details.

The NOSC<2:0> control bits (OSCCON<10:8>) do not

control the clock selection when clock switching is

disabled. However, the COSC<2:0> bits (OSC-

CON<14:12>) reflect the clock source selected by the

FNOSC<2:0> Configuration bits FOSCSEL<2:0>.

The OSWEN control bit (OSCCON<0>) has no effect

when clock switching is disabled. It is held at ‘0’ at all

times.

9.3

Fail-Safe Clock Monitor (FSCM)

9.2.2

OSCILLATOR SWITCHING SEQUENCE

Performing

sequence:

a

clock switch requires this basic

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue to operate even in the event of an oscillator

failure. The FSCM function is enabled by programming.

If the FSCM function is enabled, the LPRC internal

oscillator runs at all times (except during Sleep mode)

and is not subject to control by the Watchdog Timer.

1. If required, read the COSC<2:0> bits to deter-

mine the current oscillator source.

2. Perform the unlock sequence to allow a write to

the OSCCON register high byte.

If an oscillator fails, the FSCM generates a clock failure

trap event and switches the system clock over to the

FRC oscillator. Then the application program can either

attempt to restart the oscillator or execute a controlled

shutdown. The trap can be treated as a warm Reset by

simply loading the Reset address into the oscillator fail

trap vector.

3. Write the appropriate value to the NOSC<2:0>

control bits for the new oscillator source.

4. Perform the unlock sequence to allow a write to

the OSCCON register low byte.

5. Set the OSWEN bit to initiate the oscillator

switch.

After the basic sequence is completed, the system

clock hardware responds automatically as follows:

If the PLL multiplier is used to scale the system clock,

the internal FRC is also multiplied by the same factor

on clock failure. Essentially, the device switches to

FRC with PLL on a clock failure.

1. The clock switching hardware compares the

COSC<2:0> status bits with the new value of the

NOSC<2:0> control bits. If they are the same,

the clock switch is a redundant operation. In this

case, the OSWEN bit is cleared automatically

and the clock switch is aborted.

2. If a valid clock switch has been initiated, the

LOCK

(OSCCON<5>)

and

the

CF

DS70293F-page 128

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

10.2 Instruction-Based Power-Saving

Modes

10.0 POWER-SAVING FEATURES

Note 1: This data sheet summarizes the features

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 devices have two special

power-saving modes that are entered through the

execution of a special PWRSAVinstruction. Sleep mode

stops clock operation and halts all code execution. Idle

mode halts the CPU and code execution, but allows

peripheral modules to continue operation. The

assembler syntax of the PWRSAVinstruction is shown in

Example 10-1.

of

the

PIC24HJ32GP302/304,

and

PIC24HJ64GPX02/X04

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to Section 9. “Watchdog Timer

and Power Savings Modes” (DS70196)

of the “dsPIC33F/PIC24H Family Refer-

ence Manual”, which is available from the

Microchip website (www.microchip.com).

Note: SLEEP_MODE and IDLE_MODE are con-

stants defined in the assembler include

file for the selected device.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Sleep and Idle modes can be exited as a result of an

enabled interrupt, WDT time-out or a device Reset. When

the device exits these modes, it is said to wake up.

10.2.1

SLEEP MODE

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 devices provide the

ability to manage power consumption by selectively

managing clocking to the CPU and the peripherals. In

general, a lower clock frequency and a reduction in the

number of circuits being clocked constitutes lower

The following occur in Sleep mode:

• The system clock source is shut down. If an

on-chip oscillator is used, it is turned off.

• The device current consumption is reduced to a

minimum, provided that no I/O pin is sourcing

current.

consumed

power.

PIC24HJ32GP302/304,

• The Fail-Safe Clock Monitor does not operate,

since the system clock source is disabled.

PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04

devices can manage power consumption in four ways:

• The LPRC clock continues to run in Sleep mode if

the WDT is enabled.

• Clock frequency

• Instruction-based Sleep and Idle modes

• Software-controlled Doze mode

• Selective peripheral control in software

• The WDT, if enabled, is automatically cleared

prior to entering Sleep mode.

• Some device features or peripherals can continue

to operate. This includes items such as the input

change notification on the I/O ports, or peripherals

that use an external clock input.

Combinations of these methods can be used to selec-

tively tailor an application’s power consumption while

still maintaining critical application features, such as

timing-sensitive communications.

• Any peripheral that requires the system clock

source for its operation is disabled.

10.1 Clock Frequency and Clock

Switching

The device wakes up from Sleep mode on any of the

these events:

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 devices allow a wide range of

clock frequencies to be selected under application

control. If the system clock configuration is not locked,

users can choose low-power or high-precision

oscillators by simply changing the NOSC bits

(OSCCON<10:8>). The process of changing a system

clock during operation, as well as limitations to the

process, are discussed in more detail in Section 9.0

“Oscillator Configuration”.

• Any interrupt source that is individually enabled

• Any form of device Reset

• A WDT time-out

On wake-up from Sleep mode, the processor restarts

with the same clock source that was active when Sleep

mode was entered.

EXAMPLE 10-1:

PWRSAVINSTRUCTION SYNTAX

PWRSAV #SLEEP_MODE

PWRSAV #IDLE_MODE

; Put the device into SLEEP mode

; Put the device into IDLE mode

DS70293F-page 129

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

Doze mode is enabled by setting the DOZEN bit

(CLKDIV<11>). The ratio between peripheral and core

clock speed is determined by the DOZE<2:0> bits

(CLKDIV<14:12>). There are eight possible

configurations, from 1:1 to 1:128, with 1:1 being the

default setting.

10.2.2

IDLE MODE

The following occur in Idle mode:

• The CPU stops executing instructions.

• The WDT is automatically cleared.

• The system clock source remains active. By

default, all peripheral modules continue to operate

normally from the system clock source, but can

also be selectively disabled (see Section 10.4

“Peripheral Module Disable”).

Programs can use Doze mode to selectively reduce

power consumption in event-driven applications. This

allows clock-sensitive functions, such as synchronous

communications, to continue without interruption while

the CPU idles, waiting for something to invoke an

interrupt routine. An automatic return to full-speed CPU

operation on interrupts can be enabled by setting the

ROI bit (CLKDIV<15>). By default, interrupt events

have no effect on Doze mode operation.

• If the WDT or FSCM is enabled, the LPRC also

remains active.

The device wakes from Idle mode on any of these

events:

• Any interrupt that is individually enabled

• Any device Reset

For example, suppose the device is operating at

20 MIPS and the ECAN module has been configured

for 500 kbps based on this device operating speed. If

the device is placed in Doze mode with a clock

frequency ratio of 1:4, the ECAN module continues to

communicate at the required bit rate of 500 kbps, but

the CPU now starts executing instructions at a

frequency of 5 MIPS.

• A WDT time-out

On wake-up from Idle mode, the clock is reapplied to

the CPU and instruction execution will begin (2 to 4

cycles later), starting with the instruction following the

PWRSAVinstruction, or the first instruction in the ISR.

10.2.3

INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS

10.4 Peripheral Module Disable

Any interrupt that coincides with the execution of a

PWRSAVinstruction is held off until entry into Sleep or

Idle mode has completed. The device then wakes up

from Sleep or Idle mode.

The Peripheral Module Disable (PMD) registers

provide a method to disable a peripheral module by

stopping all clock sources supplied to that module.

When a peripheral is disabled using the appropriate

PMD control bit, the peripheral is in a minimum power

consumption state. The control and status registers

associated with the peripheral are also disabled, so

writes to those registers do not have effect and read

values are invalid.

10.3 Doze Mode

The preferred strategies for reducing power

consumption are changing clock speed and invoking

one of the power-saving modes. In some

circumstances, this cannot be practical. For example, it

may be necessary for an application to maintain

uninterrupted synchronous communication, even while

it is doing nothing else. Reducing system clock speed

can introduce communication errors, while using a

power-saving mode can stop communications

completely.

A peripheral module is enabled only if both the

associated bit in the PMD register is cleared and the

peripheral is supported by the specific PIC MCU

variant. If the peripheral is present in the device, it is

enabled in the PMD register by default.

Note:

If a PMD bit is set, the corresponding

module is disabled after a delay of one

instruction cycle. Similarly, if a PMD bit is

cleared, the corresponding module is

enabled after a delay of one instruction

cycle (assuming the module control regis-

ters are already configured to enable

module operation).

Doze mode is a simple and effective alternative method

to reduce power consumption while the device is still

executing code. In this mode, the system clock

continues to operate from the same source and at the

same speed. Peripheral modules continue to be

clocked at the same speed, while the CPU clock speed

is reduced. Synchronization between the two clock

domains is maintained, allowing the peripherals to

access the SFRs while the CPU executes code at a

slower rate.

DS70293F-page 130

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1

R/W-0

T5MD

R/W-0

T4MD

R/W-0

T3MD

R/W-0

T2MD

R/W-0

T1MD

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

U2MD

R/W-0

U1MD

R/W-0

U-0

—

R/W-0

C1MD

R/W-0

I2C1MD

SPI2MD

SPI1MD

AD1MD

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

bit 12

bit 11

T5MD: Timer5 Module Disable bit

1= Timer5 module is disabled

0= Timer5 module is enabled

T4MD: Timer4 Module Disable bit

1= Timer4 module is disabled

0= Timer4 module is enabled

T3MD: Timer3 Module Disable bit

1= Timer3 module is disabled

0= Timer3 module is enabled

T2MD: Timer2 Module Disable bit

1= Timer2 module is disabled

0= Timer2 module is enabled

T1MD: Timer1 Module Disable bit

1= Timer1 module is disabled

0= Timer1 module is enabled

bit 10-8

bit 7

Unimplemented: Read as ‘0’

I2C1MD: I²C1 Module Disable bit

1= I²C1 module is disabled

0= I²C1 module is enabled

bit 6

bit 5

bit 4

bit 3

U2MD: UART2 Module Disable bit

1= UART2 module is disabled

0= UART2 module is enabled

U1MD: UART1 Module Disable bit

1= UART1 module is disabled

0= UART1 module is enabled

SPI2MD: SPI2 Module Disable bit

1= SPI2 module is disabled

0= SPI2 module is enabled

SPI1MD: SPI1 Module Disable bit

1= SPI1 module is disabled

0= SPI1 module is enabled

bit 2

bit 1

Unimplemented: Read as ‘0’

C1MD: ECAN1 Module Disable bit

1= ECAN1 module is disabled

0= ECAN1 module is enabled

bit 0

AD1MD: ADC1 Module Disable bit

1= ADC1 module is disabled

0= ADC1 module is enabled

DS70293F-page 131

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

IC8MD

IC7MD

IC2MD

IC1MD

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

OC4MD

OC3MD

OC2MD

OC1MD

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

IC8MD: Input Capture 8 Module Disable bit

1= Input Capture 8 module is disabled

0= Input Capture 8 module is enabled

IC7MD: Input Capture 2 Module Disable bit

1= Input Capture 7 module is disabled

0= Input Capture 7 module is enabled

bit 13-10

bit 9

Unimplemented: Read as ‘0’

IC2MD: Input Capture 2 Module Disable bit

1= Input Capture 2 module is disabled

0= Input Capture 2 module is enabled

bit 8

IC1MD: Input Capture 1 Module Disable bit

1= Input Capture 1 module is disabled

0= Input Capture 1 module is enabled

bit 7-4

bit 3

Unimplemented: Read as ‘0’

OC4MD: Output Compare 4 Module Disable bit

1= Output Compare 4 module is disabled

0= Output Compare 4 module is enabled

bit 2

bit 1

bit 0

OC3MD: Output Compare 3 Module Disable bit

1= Output Compare 3 module is disabled

0= Output Compare 3 module is enabled

OC2MD: Output Compare 2 Module Disable bit

1= Output Compare 2 module is disabled

0= Output Compare 2 module is enabled

OC1MD: Output Compare 1 Module Disable bit

1= Output Compare 1 module is disabled

0= Output Compare 1 module is enabled

DS70293F-page 132

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CMPMD

RTCCMD

PMPMD

bit 15

bit 8

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

CRCMD

DAC1MD

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-11

bit 10

Unimplemented: Read as ‘0’

CMPMD: Comparator Module Disable bit

1= Comparator module is disabled

0= Comparator module is enabled

bit 9

bit 8

bit 7

bit 6

bit 5-0

RTCCMD: RTCC Module Disable bit

1= RTCC module is disabled

0= RTCC module is enabled

PMPMD: PMP Module Disable bit

1= PMP module is disabled

0= PMP module is enabled

CRCMD: CRC Module Disable bit

1= CRC module is disabled

0= CRC module is enabled

DAC1MD: DAC1 Module Disable bit

1= DAC1 module is disabled

0= DAC1 module is enabled

Unimplemented: Read as ‘0’

DS70293F-page 133

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

NOTES:

DS70293F-page 134

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

has ownership of the output data and control signals of

11.0 I/O PORTS

the I/O pin. The logic also prevents “loop through”, in

which a port’s digital output can drive the input of a

peripheral that shares the same pin. Figure 11-1 shows

how ports are shared with other peripherals and the

associated I/O pin to which they are connected.

Note 1: This data sheet summarizes the features

of the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to Section 10. “I/O Ports”

(DS70193) of the “dsPIC33F/PIC24H

Family Reference Manual”, which is

available from the Microchip website

(www.microchip.com).

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

a general purpose output pin is disabled. The I/O pin

can be read, but the output driver for the parallel port bit

is disabled. If a peripheral is enabled, but the peripheral

is not actively driving a pin, that pin can be driven by a

port.

All port pins have three registers directly associated

with their operation as digital I/O. The data direction

register (TRISx) determines whether the pin is an input

or an output. If the data direction bit is a ‘1’, then the pin

is an input. All port pins are defined as inputs after a

Reset. Reads from the latch (LATx) read the latch.

Writes to the latch write the latch. Reads from the port

(PORTx) read the port pins, while writes to the port pins

write the latch.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

All of the device pins (except VDD, VSS, MCLR and

OSC1/CLKI) are shared among the peripherals and the

parallel I/O ports. All I/O input ports feature Schmitt

Trigger inputs for improved noise immunity.

Any bit and its associated data and control registers

that are not valid for a particular device is disabled.

This means the corresponding LATx and TRISx

registers and the port pin are read as zeros.

11.1 Parallel I/O (PIO) Ports

Generally a parallel I/O port that shares a pin with a

peripheral is subservient to the peripheral. The

peripheral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

When a pin is shared with another peripheral or

function that is defined as an input only, it is

nevertheless regarded as a dedicated port because

there is no other competing source of outputs.

FIGURE 11-1:

BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Peripheral Module

Output Multiplexers

Peripheral Input Data

Peripheral Module Enable

I/O

Peripheral Output Enable

Peripheral Output Data

1

0

Output Enable

Output Data

1

0

PIO Module

Read TRIS

Data Bus

WR TRIS

D

Q

I/O Pin

CK

TRIS Latch

D

Q

WR LAT +

WR Port

CK

Data Latch

Read LAT

Read Port

Input Data

DS70293F-page 135

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

11.2 Open-Drain Configuration

11.4 I/O Port Write/Read Timing

In addition to the PORT, LAT and TRIS registers for

data control, some port pins can also be individually

configured for either digital or open-drain output. This

is controlled by the Open-Drain Control register,

ODCx, associated with each port. Setting any of the

bits configures the corresponding pin to act as an

open-drain output.

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically this instruction

would be an NOP, as shown in Example 11-1.

11.5 Input Change Notification

The input change notification function of the I/O ports

allows the PIC24HJ32GP302/304, PIC24HJ64GPX02/

X04 and PIC24HJ128GPX02/X04 devices to generate

interrupt requests to the processor in response to a

change-of-state on selected input pins. This feature

can detect input change-of-states even in Sleep mode,

when the clocks are disabled. Depending on the device

pin count, up to 21 external signals (CNx pin) can be

selected (enabled) for generating an interrupt request

on a change-of-state.

The open-drain feature allows the generation of

outputs higher than VDD (e.g., 5V) on any desired 5V

tolerant pins by using external pull-up resistors. The

maximum open-drain voltage allowed is the same as

the maximum VIH specification.

See “Pin Diagrams” for the available pins and their

functionality.

11.3 Configuring Analog Port Pins

Four control registers are associated with the CN mod-

ule. The CNEN1 and CNEN2 registers contain the

interrupt enable control bits for each of the CN input

pins. Setting any of these bits enables a CN interrupt

for the corresponding pins.

The AD1PCFGL and TRIS registers control the opera-

tion of the analog-to-digital (A/D) port pins. The port

pins that are to function as analog inputs must have

their corresponding TRIS bit set (input). If the TRIS bit

is cleared (output), the digital output level (VOH or VOL)

is converted.

Each CN pin also has a weak pull-up connected to it.

The pull-ups act as a current source connected to the

pin, and eliminate the need for external resistors when

push-button or keypad devices are connected. The

pull-ups are enabled separately using the CNPU1 and

CNPU2 registers, which contain the control bits for

each of the CN pins. Setting any of the control bits

enables the weak pull-ups for the corresponding pins.

The AD1PCFGL register has a default value of 0x0000;

therefore, all pins that share ANx functions are analog

(not digital) by default.

When the PORT register is read, all pins configured as

analog input channels are read as cleared (a low level).

Pins configured as digital inputs do not convert an

analog input. Analog levels on any pin defined as a

digital input (including the ANx pins) can cause the

input buffer to consume current that exceeds the

device specifications.

Note:

Pull-ups on change notification pins

should always be disabled when the port

pin is configured as a digital output.

EXAMPLE 11-1:

PORT WRITE/READ EXAMPLE

MOV

NOP

0xFF00, W0

W0, TRISBB

; Configure PORTB<15:8> as inputs

; and PORTB<7:0> as outputs

; Delay 1 cycle

btss PORTB, #13

; Next Instruction

DS70293F-page 136

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

11.6.2.1

Input Mapping

11.6 Peripheral Pin Select

The inputs of the peripheral pin select options are

mapped on the basis of the peripheral. A control

register associated with a peripheral dictates the pin it

is mapped to. The RPINRx registers are used to

configure peripheral input mapping (see Register 11-1

through Register 11-14). Each register contains sets of

5-bit fields, with each set associated with one of the

Peripheral pin select configuration enables peripheral

set selection and placement on a wide range of I/O

pins. By increasing the pinout options available on a

particular device, programmers can better tailor the

microcontroller to their entire application, rather than

trimming the application to fit the device.

The peripheral pin select configuration feature

operates over a fixed subset of digital I/O pins.

Programmers can independently map the input and/or

output of most digital peripherals to any one of these

I/O pins. Peripheral pin select is performed in

software, and generally does not require the device to

be reprogrammed. Hardware safeguards are included

that prevent accidental or spurious changes to the

peripheral mapping, once it has been established.

remappable peripherals. Programming

a

given

peripheral’s bit field with an appropriate 5-bit value

maps the RPn pin with that value to that peripheral.

For any given device, the valid range of values for any

bit field corresponds to the maximum number of

peripheral pin selections supported by the device.

Figure 11-2 illustrates remappable pin selection for

U1RX input.

Note:

For input mapping only, the Peripheral Pin

Select (PPS) functionality does not have

priority over the TRISx settings. There-

fore, when configuring the RPx pin for

input, the corresponding bit in the TRISx

register must also be configured for input

(i.e., set to ‘1’).

11.6.1

AVAILABLE PINS

The peripheral pin select feature is used with a range

of up to 26 pins. The number of available pins depends

on the particular device and its pin count. Pins that

support the peripheral pin select feature include the

designation “RPn” in their full pin designation, where

“RP” designates a remappable peripheral and “n” is the

remappable pin number.

FIGURE 11-2:

REMAPPABLE MUX

INPUT FOR U1RX

11.6.2

CONTROLLING PERIPHERAL PIN

SELECT

U1RXR<4:0>

Peripheral pin select features are controlled through

two sets of special function registers: one to map

peripheral inputs, and another one to map outputs.

Because they are separately controlled, a particular

peripheral’s input and output (if the peripheral has both)

can be placed on any selectable function pin without

constraint.

0

RP0

RP1

RP2

1

U1RX input

to peripheral

2

The association of a peripheral to a peripheral select-

able pin is handled in two different ways, depending on

whether an input or output is being mapped.

25

RP 25

DS70293F-page 137

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(1)

TABLE 11-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)

Configuration

Bits

Input Name

Function Name

Register

External Interrupt 1

INT1

INT2

T2CK

T3CK

T4CK

T5CK

IC1

RPINR0

RPINR1

RPINR3

RPINR4

RPINR7

RPINR10

RPINR11

RPINR18

RPINR19

RPINR20

RPINR21

RPINR22

RPINR23

RPINR26

INT1R<4:0>

INT2R<4:0>

T2CKR<4:0>

T3CKR<4:0>

T4CKR<4:0>

T5CKR<4:0>

IC1R<4:0>

External Interrupt 2

Timer2 External Clock

Timer3 External Clock

Timer4 External Clock

Timer5 External Clock

Input Capture 1

Input Capture 2

IC2

IC2R<4:0>

Input Capture 7

IC7

IC7R<4:0>

Input Capture 8

IC8

IC8R<4:0>

Output Compare Fault A

UART1 Receive

OCFA

U1RX

U1CTS

U2RX

U2CTS

SDI1

SCK1

SS1

OCFAR<4:0>

U1RXR<4:0>

U1CTSR<4:0>

U2RXR<4:0>

U2CTSR<4:0>

SDI1R<4:0>

SCK1R<4:0>

SS1R<4:0>

SDI2R<4:0>

SCK2R<4:0>

SS2R<4:0>

CIRXR<4:0>

UART1 Clear To Send

UART2 Receive

UART2 Clear To Send

SPI1 Data Input

SPI1 Clock Input

SPI1 Slave Select Input

SPI2 Data Input

SDI2

SCK2

SS2

SPI2 Clock Input

SPI2 Slave Select Input

ECAN1 Receive

CIRX

Note 1: Unless otherwise noted, all inputs use Schmitt input buffers.

DS70293F-page 138

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

11.6.2.2

Output Mapping

FIGURE 11-3:

MULTIPLEXING OF

REMAPPABLE OUTPUT

FOR RPn

In contrast to inputs, the outputs of the peripheral pin

select options are mapped on the basis of the pin. In

this case, a control register associated with a particular

pin dictates the peripheral output to be mapped. The

RPORx registers are used to control output mapping.

Like the RPINRx registers, each register contains sets

of 5-bit fields, with each set associated with one RPn

pin (see Register 11-15 through Register 11-27). The

value of the bit field corresponds to one of the

peripherals, and that peripheral’s output is mapped to

the pin (see Table 11-2 and Figure 11-3).

RPnR<4:0>

default

0

3

4

U1TX Output enable

U1RTS Output enable

Output Enable

The list of peripherals for output mapping also includes

a null value of ‘00000’ because of the mapping

technique. This permits any given pin to remain

unconnected from the output of any of the pin

selectable peripherals.

OC4 Output

21

default

0

3

4

U1TX Output

U1RTS Output

RPn

Output Data

OC4 Output

21

TABLE 11-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)

Function

RPnR<4:0>

Output Name

RPn tied to default port pin

NULL

C1OUT

C2OUT

U1TX

U1RTS

U2TX

U2RTS

SDO1

SCK1

SS1

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

10000

10010

10011

10100

10101

RPn tied to Comparator1 Output

RPn tied to Comparator2 Output

RPn tied to UART1 Transmit

RPn tied to UART1 Ready To Send

RPn tied to UART2 Transmit

RPn tied to UART2 Ready To Send

RPn tied to SPI1 Data Output

RPn tied to SPI1 Clock Output

RPn tied to SPI1 Slave Select Output

RPn tied to SPI2 Data Output

RPn tied to SPI2 Clock Output

RPn tied to SPI2 Slave Select Output

RPn tied to ECAN1 Transmit

SDO2

SCK2

SS2

C1TX

OC1

RPn tied to Output Compare 1

RPn tied to Output Compare 2

RPn tied to Output Compare 3

RPn tied to Output Compare 4

OC2

OC3

OC4

DS70293F-page 139

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

11.6.3

CONTROLLING CONFIGURATION

CHANGES

11.6.3.2

Continuous State Monitoring

In addition to being protected from direct writes, the

contents of the RPINRx and RPORx registers are

constantly monitored in hardware by shadow registers.

If an unexpected change in any of the registers occurs

(such as cell disturbances caused by ESD or other

external events), a configuration mismatch Reset is

triggered.

Because peripheral remapping can be changed during

run time, some restrictions on peripheral remapping

are needed to prevent accidental configuration

changes. PIC24H devices include three features to

prevent alterations to the peripheral map:

• Control register lock sequence

• Continuous state monitoring

• Configuration bit pin select lock

11.6.3.3

Configuration Bit Pin Select Lock

As an additional level of safety, the device can be

configured to prevent more than one write session to

the RPINRx and RPORx registers. The IOL1WAY Con-

figuration bit (FOSC<5>) blocks the IOLOCK bit from

being cleared after it has been set once. If IOLOCK

remains set, the register unlock procedure does not

execute, and the peripheral pin select control registers

cannot be written to. The only way to clear the bit and

re-enable peripheral remapping is to perform a device

Reset.

11.6.3.1

Control Register Lock

Under normal operation, writes to the RPINRx and

RPORx registers are not allowed. Attempted writes

appear to execute normally, but the contents of the reg-

isters remain unchanged. To change these registers,

they must be unlocked in hardware. The register lock is

controlled by the IOLOCK bit (OSCCON<6>). Setting

IOLOCK prevents writes to the control registers;

clearing IOLOCK allows writes.

In the default (unprogrammed) state, IOL1WAY is set,

restricting users to one write session. Programming

IOL1WAY allows user applications unlimited access

(with the proper use of the unlock sequence) to the

peripheral pin select registers.

To set or clear IOLOCK, a specific command sequence

must be executed:

1. Write 0x46 to OSCCON<7:0>.

2. Write 0x57 to OSCCON<7:0>.

3. Clear (or set) the IOLOCK bit as a single

operation.

Note:

MPLAB^®C30 provides built-in

C

language functions for unlocking the

OSCCON register:

__builtin_write_OSCCONL(value)

__builtin_write_OSCCONH(value)

See MPLAB Help for more information.

Unlike the similar sequence with the oscillator’s LOCK

bit, IOLOCK remains in one state until changed. This

allows all of the peripheral pin selects to be configured

with a single unlock sequence followed by an update to

all control registers, then locked with a second lock

sequence.

DS70293F-page 140

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

11.7 Peripheral Pin Select Registers

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 family of devices

implement 27 registers for remappable peripheral

configuration:

• 14 Input Remappable Peripheral Registers:

- RPINR0-RPINR1, RPINR3-RPINR4,

RPINR7, RPINR10-RPINR11, RPINR18-

RPINR23 and PRINR26

• 13 Output Remappable Peripheral Registers:

- RPOR0-RPOR12

Note:

Input and Output Register values can only

be changed if the IOLOCK bit

(OSCCON<6>) is set to ‘0’. See

Section 11.6.3.1 “Control Register

Lock” for a specific command sequence.

REGISTER 11-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0

U-0

—

U-0

—

U-0

—

R/W-1

bit 8

INT1R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

bit 7-0

Unimplemented: Read as ‘0’

DS70293F-page 141

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 11-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-1

bit 0

U-0

—

U-0

—

U-0

—

R/W-1

INT2R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

bit 4-0

Unimplemented: Read as ‘0’

INTR2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

DS70293F-page 142

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 11-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3

U-0

—

U-0

—

U-0

—

R/W-1

bit 8

R/W-1

bit 0

T3CKR<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-1

T2CKR<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

T3CKR<4:0>: Assign Timer3 External Clock (T3CK) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

DS70293F-page 143

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 11-4: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4

U-0

—

U-0

—

U-0

—

R/W-1

bit 8

R/W-1

bit 0

T5CKR<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-1

T4CKR<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

T5CKR<4:0>: Assign Timer5 External Clock (T5CK) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

T4CKR<4:0>: Assign Timer4 External Clock (T4CK) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

DS70293F-page 144

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 11-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7

U-0

—

U-0

—

U-0

—

R/W-1

bit 8

R/W-1

bit 0

IC2R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-1

IC1R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

IC2R<4:0>: Assign Input Capture 2 (IC2) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin

11111= Input tied to VSS

11001 = Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

DS70293F-page 145

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 11-6: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTERS 10

U-0

—

U-0

—

U-0

—

R/W-1

bit 8

R/W-1

bit 0

IC8R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-1

IC7R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

IC8R<4:0>: Assign Input Capture 8 (IC8) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

IC7R<4:0>: Assign Input Capture 7 (IC7) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

DS70293F-page 146

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 11-7: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-1

bit 0

U-0

—

U-0

—

U-0

—

R/W-1

OCFAR<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

bit 4-0

Unimplemented: Read as ‘0’

OCFAR<4:0>: Assign Output Compare A (OCFA) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

DS70293F-page 147

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 11-8: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18

U-0

—

U-0

—

U-0

—

R/W-1

bit 8

R/W-1

bit 0

U1CTSR<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-1

U1RXR<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

U1CTSR<4:0>: Assign UART1 Clear to Send (U1CTS) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

DS70293F-page 148

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 11-9: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19

U-0

—

U-0

—

U-0

—

R/W-1

bit 8

R/W-1

bit 0

U2CTSR<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-1

U2RXR<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

U2CTSR<4:0>: Assign UART2 Clear to Send (U2CTS) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

U2RXR<4:0>: Assign UART2 Receive (U2RX) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

DS70293F-page 149

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 11-10: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20

U-0

—

U-0

—

U-0

—

R/W-1

bit 8

R/W-1

bit 0

SCK1R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-1

SDI1R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

SCK1R<4:0>: Assign SPI1 Clock Input (SCK1) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

DS70293F-page 150

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 11-11: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-1

bit 0

U-0

—

U-0

—

U-0

—

R/W-1

SS1R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

bit 4-0

Unimplemented: Read as ‘0’

SS1R<4:0>: Assign SPI1 Slave Select Input (SS1) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

DS70293F-page 151

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 11-12: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22

U-0

—

U-0

—

U-0

—

R/W-1

bit 8

R/W-1

bit 0

SCK2R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-1

SDI2R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

SCK2R<4:0>: Assign SPI2 Clock Input (SCK2) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

DS70293F-page 152

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 11-13: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-1

bit 0

U-0

—

U-0

—

U-0

—

R/W-1

SS2R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

bit 4-0

Unimplemented: Read as ‘0’

SS2R<4:0>: Assign SPI2 Slave Select Input (SS2) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

(1)

REGISTER 11-14: RPINR26: PERIPHERAL PIN SELECT INPUT REGISTER 26

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-1

bit 0

U-0

—

U-0

—

U-0

—

R/W-1

C1RXR<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

bit 4-0

Unimplemented: Read as ‘0’

C1RXR<4:0>: Assign ECAN1 Receive (C1RX) to the corresponding RPn pin

11111= Input tied to VSS

11001= Input tied to RP25

•

00001= Input tied to RP1

00000= Input tied to RP0

Note 1: This register is disabled on devices without ECAN™ modules.

DS70293F-page 153

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 11-15: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTERS 0

U-0

—

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

RP1R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-0

RP0R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table 11-2 for

peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP0R<4:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table 11-2 for

peripheral function numbers)

REGISTER 11-16: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTERS 1

U-0

—

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

RP3R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-0

RP2R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 11-2 for

peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 11-2 for

peripheral function numbers)

DS70293F-page 154

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 11-17: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTERS 2

U-0

—

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

RP5R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-0

RP4R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table 11-2 for

peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP4R<4:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table 11-2 for

peripheral function numbers)

REGISTER 11-18: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTERS 3

U-0

—

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

RP7R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-0

RP6R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 11-2 for

peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 11-2 for

peripheral function numbers)

DS70293F-page 155

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 11-19: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTERS 4

U-0

—

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

RP9R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-0

RP8R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP9R<4:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits (see Table 11-2 for

peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table 11-2 for

peripheral function numbers)

REGISTER 11-20: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTERS 5

U-0

—

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

RP11R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-0

RP10R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 11-2 for

peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 11-2 for

peripheral function numbers)

DS70293F-page 156

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 11-21: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTERS 6

U-0

—

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

RP13R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-0

RP12R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP13R<4:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits (see Table 11-2 for

peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP12R<4:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits (see Table 11-2 for

peripheral function numbers)

REGISTER 11-22: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTERS 7

U-0

—

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

RP15R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-0

RP14R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 11-2 for

peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 11-2 for

peripheral function numbers)

DS70293F-page 157

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(1)

REGISTER 11-23: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTERS 8

U-0

—

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

RP17R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-0

RP16R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP17R<4:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits (see Table 11-2 for

peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP16R<4:0>: Peripheral Output Function is Assigned to RP16 Output Pin bits (see Table 11-2 for

peripheral function numbers)

Note 1: This register is implemented in 44-pin devices only.

(1)

REGISTER 11-24: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTERS 9

U-0

—

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

RP19R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-0

RP18R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP19R<4:0>: Peripheral Output Function is Assigned to RP19 Output Pin bits (see Table 11-2 for

peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits (see Table 11-2 for

peripheral function numbers)

Note 1: This register is implemented in 44-pin devices only.

DS70293F-page 158

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(1)

REGISTER 11-25: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTERS 10

U-0

—

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

RP21R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-0

RP20R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP21R<4:0>: Peripheral Output Function is Assigned to RP21 Output Pin bits (see Table 11-2 for

peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP20R<4:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table 11-2 for

peripheral function numbers)

Note 1: This register is implemented in 44-pin devices only.

(1)

REGISTER 11-26: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTERS 11

U-0

—

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

RP23R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-0

RP22R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits (see Table 11-2 for

peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table 11-2 for

peripheral function numbers)

Note 1: This register is implemented in 44-pin devices only.

DS70293F-page 159

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(1)

REGISTER 11-27: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTERS 12

U-0

—

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

RP25R<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-0

RP24R<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

RP25R<4:0>: Peripheral Output Function is Assigned to RP25 Output Pin bits (see Table 11-2 for

peripheral function numbers)

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 11-2 for

peripheral function numbers)

Note 1: This register is implemented in 44-pin devices only.

DS70293F-page 160

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

The unique features of Timer1 allow it to be used for

Real Time Clock (RTC) applications. A block diagram

of Timer1 is shown in Figure 12-1.

12.0 TIMER1

Note 1: This data sheet summarizes the features

of the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and

The Timer1 module can operate in one of the following

modes:

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 11. “Timers”

(DS70205) of the “dsPIC33F/PIC24H

Family Reference Manual”, which is

available from the Microchip website

(www.microchip.com).

• Timer mode

• Gated Timer mode

• Synchronous Counter mode

• Asynchronous Counter mode

In Timer and Gated Timer modes, the input clock is

derived from the internal instruction cycle clock (FCY).

In Synchronous and Asynchronous Counter modes,

the input clock is derived from the external clock input

at the T1CK pin.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

The Timer modes are determined by the following bits:

• Timer Clock Source Control bit (TCS): T1CON<1>

• Timer Synchronization Control bit (TSYNC):

T1CON<2>

• Timer Gate Control bit (TGATE): T1CON<6>

The Timer1 module is a 16-bit timer, which can serve

as the time counter for the real-time clock, or operate

as a free-running interval timer/counter.

Timer control bit setting for different operating modes

are given in the Table 12-1.

The Timer1 module has the following unique features

over other timers:

TABLE 12-1: TIMER MODE SETTINGS

Mode

Timer

TCS

TGATE

TSYNC

• Can be operated from the low power 32 kHz

crystal oscillator available on the device

0

1

0

1

x

1

• Can be operated in Asynchronous Counter mode

from an external clock source.

Gated timer

Synchronous

counter

• The external clock input (T1CK) can optionally be

synchronized to the internal device clock and the

clock synchronization is performed after the

prescaler.

Asynchronous

counter

1

x

0

FIGURE 12-1:

16-BIT TIMER1 MODULE BLOCK DIAGRAM

Falling Edge

Gate

Sync

1

0

Detect

Set T1IF flag

FCY

10

Prescaler

(/n)

TGATE

Reset

Equal

TMR1

00

x1

TCKPS<1:0>

0

1

SOSCO/

T1CK

Prescaler

(/n)

Comparator

PR1

Sync

TGATE

TCS

TSYNC

TCKPS<1:0>

SOSCI

(1)

LPOSCEN

Note 1: Refer to Section 9.0 “Oscillator Configuration” for information on enabling the secondary oscillator.

DS70293F-page 161

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0

TON

U-0

—

R/W-0

TSIDL

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

U-0

—

R/W-0

TCS

U-0

—

TGATE

TCKPS<1:0>

TSYNC

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

TON: Timer1 On bit

1= Starts 16-bit Timer1

0= Stops 16-bit Timer1

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timer1 Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation enabled

0= Gated time accumulation disabled

bit 5-4

TCKPS<1:0>: Timer1 Input Clock Prescaler Select bits

11 = 1:256

10 = 1:64

01 = 1:8

00 = 1:1

bit 3

bit 2

Unimplemented: Read as ‘0’

TSYNC: Timer1 External Clock Input Synchronization Select bit

When TCS = 1:

1= Synchronize external clock input

0= Do not synchronize external clock input

When TCS = 0:

This bit is ignored.

bit 1

bit 0

TCS: Timer1 Clock Source Select bit

1= External clock from pin T1CK (on the rising edge)

0= Internal clock (FCY)

Unimplemented: Read as ‘0’

DS70293F-page 162

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

DS70293F-page 163

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

• A Type B timer can be concatenated with a Type

C timer to form a 32-bit timer

13.0 TIMER2/3 AND TIMER4/5

FEATURE

• The external clock input (TxCK) is always

synchronized to the internal device clock and the

clock synchronization is performed after the

prescaler

Note 1: This data sheet summarizes the features

of

the

PIC24HJ32GP302/304,

and

PIC24HJ64GPX02/X04

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 11. “Timers”

(DS70205) of the “dsPIC33F/PIC24H

Family Reference Manual”, which is

available from the Microchip website

(www.microchip.com).

A block diagram of the Type B timer is shown in

Figure 13-1.

Timer3 and Timer5 are Type C timers with the following

specific features:

• A Type C timer can be concatenated with a Type

B timer to form a 32-bit timer

• At least one Type C timer has the ability to trigger

an A/D conversion

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

• The external clock input (TxCK) is always

synchronized to the internal device clock and the

clock synchronization is performed before the

prescaler

A block diagram of the Type C timer is shown in

Figure 13-2.

Timer2 and Timer4 are Type B timers with the following

specific features:

FIGURE 13-1:

TYPE B TIMER BLOCK DIAGRAM (x = 2 or 4)

Falling Edge

Detect

Gate

Sync

1

Set TxIF flag

0

FCY

10

Prescaler

(/n)

Reset

00

x1

TMRx

Comparator

PRx

TGATE

TCKPS<1:0>

Sync

Prescaler

(/n)

Equal

TxCK

TCKPS<1:0>

TGATE

TCS

FIGURE 13-2:

TYPE C TIMER BLOCK DIAGRAM (x = 3 or 5)

Falling Edge

Detect

Gate

Sync

1

Set TxIF flag

0

Prescaler

(/n)

10

00

x1

FCY

Reset

Equal

TMRx

TGATE

TCKPS<1:0>

Prescaler

(/n)

Sync

ADC SOC Trigger

Comparator

TxCK

TCKPS<1:0>

TGATE

TCS

PRx

DS70293F-page 163

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

The Timer2/3 and Timer4/5 modules can operate in

one of the following modes:

When configured for 32-bit operation, only the Type B

Timer Control register (TxCON) bits are required for

setup and control. Type C timer control register bits are

ignored (except TSIDL bit).

• Timer mode

• Gated Timer mode

• Synchronous Counter mode

For interrupt control, the combined 32-bit timer uses

the interrupt enable, interrupt flag and interrupt priority

control bits of the Type C timer. The interrupt control

and status bits for the Type B timer are ignored during

32-bit timer operation.

In Timer and Gated Timer modes, the input clock is

derived from the internal instruction cycle clock (FCY).

In Synchronous Counter mode, the input clock is

derived from the external clock input at TxCK pin.

The Type B and Type C timers that can be combined to

form a 32-bit timer are listed in Table 13-2.

The timer modes are determined by the following bits:

• TCS (TxCON<1>): Timer Clock Source Control bit

• TGATE (TxCON<6>): Timer Gate Control bit

TABLE 13-2: 32-BIT TIMER

Timer control bit settings for different operating modes

are given in the Table 13-1.

TYPE B Timer (lsw)

TYPE C Timer (msw)

Timer2

Timer4

Timer3

Timer5

TABLE 13-1: TIMER MODE SETTINGS

A block diagram representation of the 32-bit timer mod-

ule is shown in Figure 13-3. The 32-timer module can

operate in one of the following modes:

Mode

TCS

TGATE

Timer

0

1

0

1

x

Gated timer

• Timer mode

Synchronous counter

• Gated Timer mode

• Synchronous Counter mode

13.1 16-Bit Operation

To configure the features of Timer2/3 or Timer4/5 for

32-bit operation:

To configure any of the timers for individual 16-bit

operation:

1. Set the T32 control bit.

1. Clear the T32 bit corresponding to that timer.

2. Select the prescaler ratio for Timer2 or Timer4

using the TCKPS<1:0> bits.

2. Select the timer prescaler ratio using the

TCKPS<1:0> bits.

3. Set the Clock and Gating modes using the

corresponding TCS and TGATE bits.

3. Set the Clock and Gating modes using the TCS

and TGATE bits.

4. Load the timer period value. PR3 or PR5 con-

tains the most significant word of the value,

while PR2 or PR4 contains the least significant

word.

4. Load the timer period value into the PRx

register.

5. If interrupts are required, set the interrupt enable

bit, TxIE. Use the priority bits, TxIP<2:0>, to set

the interrupt priority.

5. If interrupts are required, set the interrupt enable

bits, T3IE or T5IE. Use the priority bits,

T3IP<2:0> or T5IP<2:0> to set the interrupt pri-

ority. While Timer2 or Timer4 controls the timer,

the interrupt appears as a Timer3 or Timer5

interrupt.

6. Set the TON bit.

Note:

Only Timer2 and Timer3 can trigger a

DMA data transfer.

6. Set the corresponding TON bit.

The timer value at any point is stored in the register

pair, TMR3:TMR2 or TMR5:TMR4, which always

contains the most significant word of the count, while

TMR2 or TMR4 contains the least significant word.

13.2 32-Bit Operation

A 32-bit timer module can be formed by combining a

Type B and a Type C 16-bit timer module. For 32-bit

timer operation, the T32 control bit in the Type B Timer

Control register (TxCON<3>) must be set. The Type C

timer holds the most significant word (msw) and the

Type B timer holds the least significant word (lsw) for

32-bit operation.

DS70293F-page 164

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 13-3:

32-BIT TIMER BLOCK DIAGRAM

Falling Edge

Detect

Gate

Sync

1

0

Set TyIF

Flag

PRy

PRx

Equal

Reset

Comparator

TGATE

Prescaler

(/n)

10

00

x1

FCY

lsw

TMRx

msw

ADC SOC trigger

TMRy

TCKPS<1:0>

Sync

Prescaler

(/n)

TxCK

TMRyHLD

TGATE

TCS

TCKPS<1:0>

Data Bus <15:0>

Note 1: ADC trigger is available only on TMR3:TMR2 and TMR5:TMR2 32-bit timers.

2: Timer x is a Type B Timer (x = 2 and 4).

3: Timer y is a Type C Timer (y = 3 and 5).

DS70293F-page 165

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 13-1: TxCON: TIMER CONTROL REGISTER (x = 2 OR 4, y = 3 OR 5)

R/W-0

TON

U-0

—

R/W-0

TSIDL

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

T32

U-0

—

R/W-0

TCS

U-0

—

TGATE

TCKPS<1:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

TON: Timerx On bit

When T32 = 1(in 32-bit Timer mode):

1= Starts 32-bit TMRx:TMRy timer pair

0= Stops 32-bit TMRx:TMRy timer pair

When T32 = 0(in 16-bit Timer mode):

1= Starts 16-bit timer

0= Stops 16-bit timer

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit

1= Discontinue timer operation when device enters Idle mode

0= Continue timer operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timerx Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation enabled

0= Gated time accumulation disabled

bit 5-4

bit 3

TCKPS<1:0>: Timerx Input Clock Prescale Select bits

11= 1:256 prescale value

10= 1:64 prescale value

01= 1:8 prescale value

00= 1:1 prescale value

T32: 32-bit Timerx Mode Select bit

1= TMRx and TMRy form a 32-bit timer

0= TMRx and TMRy form separate 16-bit timer

bit 2

bit 1

Unimplemented: Read as ‘0’

TCS: Timerx Clock Source Select bit

1= External clock from TxCK pin

0= Internal clock (FOSC/2)

bit 0

Unimplemented: Read as ‘0’

DS70293F-page 166

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 13-2: TxCON: TIMER CONTROL REGISTER (x = 3 OR 5)

R/W-0

TON⁽²⁾

U-0

—

R/W-0

TSIDL⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

TGATE⁽²⁾

R/W-0

TCKPS<1:0>⁽²⁾

R/W-0

U-0

—

U-0

—

R/W-0

TCS⁽²⁾

U-0

—

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

TON: Timery On bit⁽²⁾

1= Starts 16-bit Timerx

0= Stops 16-bit Timerx

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit⁽¹⁾

1= Discontinue timer operation when device enters Idle mode

0= Continue timer operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timerx Gated Time Accumulation Enable bit⁽²⁾

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation enabled

0= Gated time accumulation disabled

bit 5-4

TCKPS<1:0>: Timerx Input Clock Prescale Select bits⁽²⁾

11= 1:256 prescale value

10= 1:64 prescale value

01= 1:8 prescale value

00= 1:1 prescale value

bit 3-2

bit 1

Unimplemented: Read as ‘0’

TCS: Timerx Clock Source Select bit⁽²⁾

1= External clock from TxCK pin

0= Internal clock (FOSC/2)

bit 0

Unimplemented: Read as ‘0’

Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), the TSIDL bit

must be cleared to operate the 32-bit timer in Idle mode.

2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control register (TxCON<3>), these bits

have no effect.

DS70293F-page 167

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

NOTES:

DS70293F-page 168

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

• Simple Capture Event modes:

14.0 INPUT CAPTURE

- Capture timer value on every falling edge of

input at ICx pin

- Capture timer value on every rising edge of

input at ICx pin

Note 1: This data sheet summarizes the features

of the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to Section 12. “Input Capture”

(DS70198) of the “dsPIC33F/PIC24H

Family Reference Manual”, which is

available from the Microchip website

(www.microchip.com).

• Capture timer value on every edge (rising and

falling)

• Prescaler Capture Event modes:

- Capture timer value on every 4th rising edge

of input at ICx pin

- Capture timer value on every 16th rising

edge of input at ICx pin

Each input capture channel can select one of two

16-bit timers (Timer2 or Timer3) for the time base.

The selected timer can use either an internal or

external clock.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Other operational features include:

• Device wake-up from capture pin during CPU

Sleep and Idle modes

The input capture module is useful in applications

requiring frequency (period) and pulse measurement.

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 devices support up to

four input capture channels.

• Interrupt on input capture event

• 4-word FIFO buffer for capture values:

- Interrupt optionally generated after 1, 2, 3 or

4 buffer locations are filled

• Use of input capture to provide additional sources

of external interrupts

The input capture module captures the 16-bit value of

the selected Time Base register when an event occurs

at the ICx pin. The events that cause a capture event

are listed below in three categories:

Note:

Only IC1 and IC2 can trigger a DMA data

transfer. If DMA data transfers are

required, the FIFO buffer size must be set

to ‘1’ (ICI<1:0> = 00).

FIGURE 14-1:

INPUT CAPTURE BLOCK DIAGRAM

ICM<2:0>

Prescaler Mode

(16th Rising Edge)

101

100

TMR2 TMR3

Prescaler Mode

(4th Rising Edge)

ICTMR

Rising Edge Mode

Falling Edge Mode

To CPU

ICx pin

011

010

CaptureEvent

FIFO CONTROL

ICxBUF

FIFO

Edge Detection

Mode

ICI<1:0>

/N

ICM<2:0>

001

Set Flag ICxIF

(In IFSx Register)

Sleep/Idle

Wake-up Mode

001

111

Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.

DS70293F-page 169

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

14.1 Input Capture Registers

REGISTER 14-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER (x = 1, 2, 7 OR 8)

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

ICSIDL

bit 15

bit 8

R/W-0

bit 0

R/W-0

R-0, HC

ICOV

R-0, HC

ICBNE

R/W-0

ICTMR

ICI<1:0>

ICM<2:0>

bit 7

Legend:

HC = Cleared in Hardware

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15-14

bit 13

Unimplemented: Read as ‘0’

ICSIDL: Input Capture Module Stop in Idle Control bit

1= Input capture module halts in CPU Idle mode

0= Input capture module continues to operate in CPU Idle mode

bit 12-8

bit 7

Unimplemented: Read as ‘0’

ICTMR: Input Capture Timer Select bits

1= TMR2 contents are captured on capture event

0= TMR3 contents are captured on capture event

bit 6-5

ICI<1:0>: Select Number of Captures per Interrupt bits

11= Interrupt on every fourth capture event

10= Interrupt on every third capture event

01= Interrupt on every second capture event

00= Interrupt on every capture event

bit 4

ICOV: Input Capture Overflow Status Flag bit (read-only)

1= Input capture overflow occurred

0= No input capture overflow occurred

bit 3

ICBNE: Input Capture Buffer Empty Status bit (read-only)

1= Input capture buffer is not empty, at least one more capture value can be read

0= Input capture buffer is empty

bit 2-0

ICM<2:0>: Input Capture Mode Select bits

111= Input capture functions as interrupt pin only when device is in Sleep or Idle mode

(Rising edge detect only, all other control bits are not applicable)

110= Unused (module disabled)

101= Capture mode, every 16th rising edge

100= Capture mode, every 4th rising edge

011= Capture mode, every rising edge

010= Capture mode, every falling edge

001= Capture mode, every edge (rising and falling)

(ICI<1:0> bits do not control interrupt generation for this mode)

000= Input capture module turned off

DS70293F-page 170

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

The Output Compare module can select either Timer2

15.0 OUTPUT COMPARE

or Timer3 for its time base. The module compares the

value of the timer with the value of one or two compare

registers depending on the operating mode selected.

The state of the output pin changes when the timer

value matches the compare register value. The Output

Compare module generates either a single output

pulse or a sequence of output pulses, by changing the

state of the output pin on the compare match events.

The Output Compare module can also generate

interrupts on compare match events.

Note 1: This data sheet summarizes the features

of the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 13. “Output

Compare” (DS70209) of the “dsPIC33F/

PIC24H Family Reference Manual”,

which is available from the Microchip

website (www.microchip.com).

The Output Compare module has multiple operating

modes:

• Active-Low One-Shot mode

• Active-High One-Shot mode

• Toggle mode

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

• Delayed One-Shot mode

• Continuous Pulse mode

• PWM mode without fault protection

• PWM mode with fault protection

FIGURE 15-1:

OUTPUT COMPARE MODULE BLOCK DIAGRAM

Set Flag bit

OCxIF

OCxRS

OCxR

Output

Logic

S

R

Q

OCx

3

Output

Enable

Logic

Output

Enable

OCM<2:0>

Mode Select

Comparator

OCFA

0

OCTSEL

1

16

TMR2

Rollover

TMR3

Rollover

TMR3

TMR2

DS70293F-page 171

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

15.1 Output Compare Modes

Note 1: Only OC1 and OC2 can trigger a DMA

data transfer.

Configure the Output Compare modes by setting the

appropriate Output Compare Mode bits (OCM<2:0>) in

the Output Compare Control register (OCxCON<2:0>).

Table 15-1 lists the different bit settings for the Output

Compare modes. Figure 15-2 illustrates the output

compare operation for various modes. The user

application must disable the associated timer when

writing to the output compare control registers to avoid

malfunctions.

2: See Section 13. “Output Compare”

(DS70209) in the “dsPIC33F/PIC24H

Family Reference Manual” for OCxR and

OCxRS register restrictions.

TABLE 15-1: OUTPUT COMPARE MODES

OCM<2:0>

Mode

Module Disabled

OCx Pin Initial State

OCx Interrupt Generation

000

001

010

011

100

101

110

Controlled by GPIO register

—

Active-Low One-Shot

Active-High One-Shot

Toggle Mode

0

1

OCx Rising edge

OCx Falling edge

Current output is maintained OCx Rising and Falling edge

Delayed One-Shot

Continuous Pulse mode

0

OCx Falling edge

No interrupt

PWM mode without fault

protection

0, if OCxR is zero

1, if OCxR is non-zero

111

PWM mode with fault protection 0, if OCxR is zero

1, if OCxR is non-zero

OCFA Falling edge for OC1 to OC4

FIGURE 15-2:

OUTPUT COMPARE OPERATION

Output Compare

Mode enabled

Timer is reset on

period match

OCxRS

OCxR

TMRy

Active Low One-Shot

(OCM = 001)

Active High One-Shot

(OCM = 010)

Toggle Mode

(OCM = 011)

Delayed One-Shot

(OCM = 100)

Continuous Pulse Mode

(OCM = 101)

PWM Mode

(OCM = 110or 111)

DS70293F-page 172

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 15-1: OCxCON: OUTPUT COMPAREx CONTROL REGISTER (x = 1, 2, 3 OR 4)

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

OCSIDL

bit 15

bit 8

R/W-0

bit 0

U-0

—

U-0

—

U-0

—

R-0 HC

OCFLT

R/W-0

OCTSEL

OCM<2:0>

bit 7

Legend:

HC = Cleared in Hardware

W = Writable bit

HS = Set in Hardware

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

‘1’ = Bit is set

bit 15-14

bit 13

Unimplemented: Read as ‘0’

OCSIDL: Stop Output Compare in Idle Mode Control bit

1= Output Compare x halts in CPU Idle mode

0= Output Compare x continues to operate in CPU Idle mode

bit 12-5

bit 4

Unimplemented: Read as ‘0’

OCFLT: PWM Fault Condition Status bit

1= PWM Fault condition has occurred (cleared in hardware only)

0= No PWM Fault condition has occurred

(This bit is only used when OCM<2:0> = 111)

bit 3

OCTSEL: Output Compare Timer Select bit

1= Timer3 is the clock source for Compare x

0= Timer2 is the clock source for Compare x

bit 2-0

OCM<2:0>: Output Compare Mode Select bits

111= PWM mode on OCx, Fault pin enabled

110= PWM mode on OCx, Fault pin disabled

101= Initialize OCx pin low, generate continuous output pulses on OCx pin

100= Initialize OCx pin low, generate single output pulse on OCx pin

011= Compare event toggles OCx pin

010= Initialize OCx pin high, compare event forces OCx pin low

001= Initialize OCx pin low, compare event forces OCx pin high

000= Output compare channel is disabled

DS70293F-page 173

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

NOTES:

DS70293F-page 174

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

The Serial Peripheral Interface (SPI) module is a

16.0 SERIAL PERIPHERAL

synchronous serial interface useful for communicating

with other peripheral or microcontroller devices. These

peripheral devices can be serial EEPROMs, shift

registers, display drivers, analog-to-digital converters,

etc. The SPI module is compatible with Motorola^®SPI

and SIOP.

INTERFACE (SPI)

Note 1: This data sheet summarizes the features

of

the

PIC24HJ32GP302/304,

and

PIC24HJ64GPX02/X04

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to “Section 18. Serial Peripheral

Interface (SPI)” (DS70206) of the

“dsPIC33F/PIC24H Family Reference

Manual”, which is available from the

Microchip website (www.microchip.com).

Each SPI module consists of a 16-bit shift register,

SPIxSR (where x = 1 or 2), used for shifting data in and

out, and a buffer register, SPIxBUF. A control register,

SPIxCON, configures the module. Additionally, a status

register, SPIxSTAT, indicates status conditions.

The serial interface consists of 4 pins:

• SDIx (serial data input)

• SDOx (serial data output)

• SCKx (shift clock input or output)

• SSx (active-low slave select)

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

In Master mode operation, SCK is a clock output. In

Slave mode, it is a clock input.

FIGURE 16-1:

SPI MODULE BLOCK DIAGRAM

SCKx

SSx

1:1 to 1:8

Secondary

Prescaler

1:1/4/16/64

Primary

Prescaler

FCY

Sync

Control

Select

Edge

Control

Clock

SPIxCON1<1:0>

SPIxCON1<4:2>

Shift Control

SDOx

SDIx

Enable

Master Clock

bit 0

SPIxSR

Transfer

SPIxRXB SPIxTXB

SPIxBUF

Write SPIxBUF

Read SPIxBUF

16

Internal Data Bus

DS70293F-page 175

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER

R/W-0

SPIEN

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

SPISIDL

bit 15

bit 8

U-0

—

R/C-0

U-0

—

U-0

—

U-0

—

U-0

—

R-0

SPIROV

SPITBF

SPIRBF

bit 0

bit 7

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

SPIEN: SPIx Enable bit

1= Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins

0= Disables module

bit 14

bit 13

Unimplemented: Read as ‘0’

SPISIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

SPIROV: Receive Overflow Flag bit

1= A new byte/word is completely received and discarded. The user software has not read the

previous data in the SPIxBUF register

0= No overflow has occurred.

bit 5-2

bit 1

Unimplemented: Read as ‘0’

SPITBF: SPIx Transmit Buffer Full Status bit

1= Transmit not yet started, SPIxTXB is full

0= Transmit started, SPIxTXB is empty

Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB.

Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.

bit 0

SPIRBF: SPIx Receive Buffer Full Status bit

1= Receive complete, SPIxRXB is full

0= Receive is not complete, SPIxRXB is empty

Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.

Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.

DS70293F-page 176

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

R/W-0

SMP

R/W-0

CKE⁽¹⁾

DISSCK

DISSDO

MODE16

bit 15

bit 8

R/W-0

SSEN⁽³⁾

R/W-0

CKP

R/W-0

SPRE<2:0>⁽²⁾

R/W-0

MSTEN

PPRE<1:0>⁽²⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12

Unimplemented: Read as ‘0’

DISSCK: Disable SCKx pin bit (SPI Master modes only)

1= Internal SPI clock is disabled, pin functions as I/O

0= Internal SPI clock is enabled

bit 11

bit 10

bit 9

DISSDO: Disable SDOx pin bit

1= SDOx pin is not used by module; pin functions as I/O

0= SDOx pin is controlled by the module

MODE16: Word/Byte Communication Select bit

1= Communication is word-wide (16 bits)

0= Communication is byte-wide (8 bits)

SMP: SPIx Data Input Sample Phase bit

Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

Slave mode:

SMP must be cleared when SPIx is used in Slave mode.

bit 8

bit 7

bit 6

bit 5

CKE: SPIx Clock Edge Select bit⁽¹⁾

1= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)

0= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)

SSEN: Slave Select Enable bit (Slave mode)⁽³⁾

1= SSx pin used for Slave mode

0= SSx pin not used by module. Pin controlled by port function

CKP: Clock Polarity Select bit

1= Idle state for clock is a high level; active state is a low level

0= Idle state for clock is a low level; active state is a high level

MSTEN: Master Mode Enable bit

1= Master mode

0= Slave mode

Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes

(FRMEN = 1).

2: Do not set both Primary and Secondary prescalers to a value of 1:1.

3: This bit must be cleared when FRMEN = 1.

DS70293F-page 177

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)

bit 4-2

SPRE<2:0>: Secondary Prescale bits (Master mode)⁽²⁾

111= Secondary prescale 1:1

110= Secondary prescale 2:1

•

000= Secondary prescale 8:1

bit 1-0

PPRE<1:0>: Primary Prescale bits (Master mode)⁽²⁾

11= Primary prescale 1:1

10= Primary prescale 4:1

01= Primary prescale 16:1

00= Primary prescale 64:1

Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes

(FRMEN = 1).

2: Do not set both Primary and Secondary prescalers to a value of 1:1.

3: This bit must be cleared when FRMEN = 1.

DS70293F-page 178

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

FRMEN

SPIFSD

FRMPOL

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

FRMDLY

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

FRMEN: Framed SPIx Support bit

1= Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)

0= Framed SPIx support disabled

SPIFSD: Frame Sync Pulse Direction Control bit

1= Frame sync pulse input (slave)

0= Frame sync pulse output (master)

FRMPOL: Frame Sync Pulse Polarity bit

1= Frame sync pulse is active-high

0= Frame sync pulse is active-low

bit 12-2

bit 1

Unimplemented: Read as ‘0’

FRMDLY: Frame Sync Pulse Edge Select bit

1= Frame sync pulse coincides with first bit clock

0= Frame sync pulse precedes first bit clock

bit 0

Unimplemented: This bit must not be set to ‘1’ by the user application

DS70293F-page 179

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

NOTES:

DS70293F-page 180

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

17.1 Operating Modes

17.0 INTER-INTEGRATED

2

CIRCUIT™ (I C™)

The hardware fully implements all the master and slave

functions of the I²C Standard and Fast mode

specifications, as well as 7-bit and 10-bit addressing.

The I²C module can operate either as a slave or a

master on an I²C bus.

Note 1: This data sheet summarizes the features

of

the

PIC24HJ32GP302/304,

and

PIC24HJ64GPX02/X04

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to Section 19. “Inter-Integrated

Circuit™ (I²C™)” (DS70195) of the

“dsPIC33F/PIC24H Family Reference

Manual”, which is available from the

Microchip website (www.microchip.com).

The following types of I²C operation are supported:

• I²C slave operation with 7-bit addressing

• I²C slave operation with 10-bit addressing

• I²C master operation with 7-bit or 10-bit addressing

For details about the communication sequence in each

of these modes, refer to the “dsPIC33F/PIC24H Family

Reference Manual”. Please see the Microchip website

(www.microchip.com) for the latest dsPIC33F/PIC24H

Family Reference Manual chapters.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

17.2 I²C Registers

I2CxCON and I2CxSTAT are control and status

registers, respectively. The I2CxCON register is

readable and writable. The lower six bits of I2CxSTAT

are read-only. The remaining bits of the I2CSTAT are

read/write:

The Inter-Integrated Circuit (I²C) module provides

complete hardware support for both Slave and

Multi-Master modes of the I²C serial communication

standard, with a 16-bit interface.

• I2CxRSR is the shift register used for shifting data

internal to the module and the user application

has no access to it

The I²C module has a 2-pin interface:

• The SCLx pin is clock.

• The SDAx pin is data.

The I²C module offers the following key features:

• I²C interface supporting both Master and Slave

modes of operation.

• I²C Slave mode supports 7-bit and 10-bit

addressing

• I²C Master mode supports 7-bit and 10-bit

addressing

• I²C port allows bidirectional transfers between

master and slaves

• Serial clock synchronization for I²C port can be

used as a handshake mechanism to suspend and

resume serial transfer (SCLREL control)

• I²C supports multi-master operation, detects bus

collision and arbitrates accordingly

• I2CxRCV is the receive buffer and the register to

which data bytes are written, or from which data

bytes are read

• I2CxTRN is the transmit register to which bytes

are written during a transmit operation

• The I2CxADD register holds the slave address

• A status bit, ADD10, indicates 10-bit Address

mode

• The I2CxBRG acts as the Baud Rate Generator

(BRG) reload value

In receive operations, I2CxRSR and I2CxRCV together

form a double-buffered receiver. When I2CxRSR

receives a complete byte, it is transferred to I2CxRCV,

and an interrupt pulse is generated.

DS70293F-page 181

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

2

FIGURE 17-1:

I C™ BLOCK DIAGRAM (X = 1)

Internal

Data Bus

I2CxRCV

Read

Shift

Clock

SCLx

SDAx

I2CxRSR

LSb

Address Match

Write

Read

Match Detect

I2CxMSK

Write

Read

I2CxADD

Start and Stop

Bit Detect

Write

Start and Stop

Bit Generation

I2CxSTAT

I2CxCON

Read

Write

Collision

Detect

Acknowledge

Generation

Read

Clock

Stretching

Write

Read

I2CxTRN

LSb

Shift Clock

Reload

Control

Write

Read

BRG Down Counter

TCY/2

I2CxBRG

DS70293F-page 182

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER

R/W-0

I2CEN

U-0

—

R/W-0

R/W-1 HC

SCLREL

R/W-0

A10M

R/W-0

SMEN

I2CSIDL

IPMIEN

DISSLW

bit 15

bit 8

R/W-0

GCEN

R/W-0

R/W-0 HC

ACKEN

R/W-0 HC

RCEN

R/W-0 HC

PEN

R/W-0 HC

RSEN

R/W-0 HC

SEN

STREN

ACKDT

bit 7

bit 0

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

HS = Set in hardware

‘0’ = Bit is cleared

HC = Cleared in hardware

x = Bit is unknown

bit 15

I2CEN: I2Cx Enable bit

1= Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins

0= Disables the I2Cx module. All I²C pins are controlled by port functions

bit 14

bit 13

Unimplemented: Read as ‘0’

I2CSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters an Idle mode

0= Continue module operation in Idle mode

bit 12

SCLREL: SCLx Release Control bit (when operating as I²C slave)

1= Release SCLx clock

0= Hold SCLx clock low (clock stretch)

If STREN = 1:

Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear

at beginning of slave transmission. Hardware clear at end of slave reception.

If STREN = 0:

Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave

transmission.

bit 11

bit 10

bit 9

IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit

1= IPMI mode is enabled; all addresses Acknowledged

0= IPMI mode disabled

A10M: 10-bit Slave Address bit

1= I2CxADD is a 10-bit slave address

0= I2CxADD is a 7-bit slave address

DISSLW: Disable Slew Rate Control bit

1= Slew rate control disabled

0= Slew rate control enabled

bit 8

SMEN: SMbus Input Levels bit

1= Enable I/O pin thresholds compliant with SMbus specification

0= Disable SMbus input thresholds

bit 7

GCEN: General Call Enable bit (when operating as I²C slave)

1= Enable interrupt when a general call address is received in the I2CxRSR

(module is enabled for reception)

0= General call address disabled

bit 6

STREN: SCLx Clock Stretch Enable bit (when operating as I²C slave)

Used in conjunction with SCLREL bit.

1= Enable software or receive clock stretching

0= Disable software or receive clock stretching

DS70293F-page 183

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)

bit 5

bit 4

ACKDT: Acknowledge Data bit (when operating as I²C master, applicable during master receive)

Value that is transmitted when the software initiates an Acknowledge sequence.

1= Send NACK during Acknowledge

0= Send ACK during Acknowledge

ACKEN: Acknowledge Sequence Enable bit

(when operating as I²C master, applicable during master receive)

1= Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.

Hardware clear at end of master Acknowledge sequence

0= Acknowledge sequence not in progress

bit 3

bit 2

bit 1

RCEN: Receive Enable bit (when operating as I²C master)

1= Enables Receive mode for I²C. Hardware clear at end of eighth bit of master receive data byte

0= Receive sequence not in progress

PEN: Stop Condition Enable bit (when operating as I²C master)

1= Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence

0= Stop condition not in progress

RSEN: Repeated Start Condition Enable bit (when operating as I²C master)

1= Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of

master Repeated Start sequence

0= Repeated Start condition not in progress

bit 0

SEN: Start Condition Enable bit (when operating as I²C master)

1= Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence

0= Start condition not in progress

DS70293F-page 184

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER

R-0 HSC

TRSTAT

U-0

—

U-0

—

U-0

—

R/C-0 HS

BCL

R-0 HSC

GCSTAT

R-0 HSC

ADD10

ACKSTAT

bit 15

bit 8

R/C-0 HS

IWCOL

R/C-0 HS

I2COV

R-0 HSC

D_A

R/C-0 HSC R/C-0 HSC

R-0 HSC

R_W

R-0 HSC

RBF

R-0 HSC

TBF

P

S

bit 7

bit 0

Legend:

U = Unimplemented bit, read as ‘0’

C = Clear only bit

R = Readable bit

W = Writable bit

‘1’ = Bit is set

HS = Set in hardware

‘0’ = Bit is cleared

HSC = Hardware set/cleared

x = Bit is unknown

-n = Value at POR

bit 15

bit 14

ACKSTAT: Acknowledge Status bit

(when operating as I²C™ master, applicable to master transmit operation)

1= NACK received from slave

0= ACK received from slave

Hardware set or clear at end of slave Acknowledge.

TRSTAT: Transmit Status bit (when operating as I²C master, applicable to master transmit operation)

1= Master transmit is in progress (8 bits + ACK)

0= Master transmit is not in progress

Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.

bit 13-11

bit 10

Unimplemented: Read as ‘0’

BCL: Master Bus Collision Detect bit

1= A bus collision has been detected during a master operation

0= No collision

Hardware set at detection of bus collision.

bit 9

bit 8

bit 7

bit 6

bit 5

bit 4

GCSTAT: General Call Status bit

1= General call address was received

0= General call address was not received

Hardware set when address matches general call address. Hardware clear at Stop detection.

ADD10: 10-bit Address Status bit

1= 10-bit address was matched

0= 10-bit address was not matched

Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.

IWCOL: Write Collision Detect bit

1= An attempt to write the I2CxTRN register failed because the I²C module is busy

0= No collision

Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).

I2COV: Receive Overflow Flag bit

1= A byte was received while the I2CxRCV register is still holding the previous byte

0= No overflow

Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).

D_A: Data/Address bit (when operating as I²C slave)

1= Indicates that the last byte received was data

0= Indicates that the last byte received was device address

Hardware clear at device address match. Hardware set by reception of slave byte.

P: Stop bit

1= Indicates that a Stop bit has been detected last

0= Stop bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop detected.

DS70293F-page 185

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)

bit 3

bit 2

bit 1

S: Start bit

1= Indicates that a Start (or Repeated Start) bit has been detected last

0= Start bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop detected.

R_W: Read/Write Information bit (when operating as I²C slave)

1= Read – indicates data transfer is output from slave

0= Write – indicates data transfer is input to slave

Hardware set or clear after reception of I²C device address byte.

RBF: Receive Buffer Full Status bit

1= Receive complete, I2CxRCV is full

0= Receive not complete, I2CxRCV is empty

Hardware set when I2CxRCV is written with received byte. Hardware clear when software

reads I2CxRCV.

bit 0

TBF: Transmit Buffer Full Status bit

1= Transmit in progress, I2CxTRN is full

0= Transmit complete, I2CxTRN is empty

Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.

DS70293F-page 186

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

AMSK9

AMSK8

bit 15

bit 8

R/W-0

AMSK7

AMSK6

AMSK5

AMSK4

AMSK3

AMSK2

AMSK1

AMSK0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-10

bit 9-0

Unimplemented: Read as ‘0’

AMSKx: Mask for Address bit x Select bit

1= Enable masking for bit x of incoming message address; bit match not required in this position

0= Disable masking for bit x; bit match required in this position

DS70293F-page 187

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

NOTES:

DS70293F-page 188

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

The primary features of the UART module are:

18.0 UNIVERSAL ASYNCHRONOUS

• Full-Duplex, 8- or 9-bit Data Transmission through

the UxTX and UxRX pins

RECEIVER TRANSMITTER

(UART)

• Even, Odd or No Parity Options (for 8-bit data)

Note 1: This data sheet summarizes the features

of the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and

• One or two stop bits

• Hardware flow control option with UxCTS and

UxRTS pins

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 17. “UART”

(DS70188) of the “dsPIC33F/PIC24H

Family Reference Manual”, which is

available from the Microchip website

(www.microchip.com).

• Fully integrated Baud Rate Generator with 16-bit

prescaler

• Baud rates ranging from 10 Mbps to 38 bps at 40

MIPS

• 4-deep First-In First-Out (FIFO) Transmit Data

buffer

• 4-deep FIFO Receive Data buffer

• Parity, framing and buffer overrun error detection

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

• Support for 9-bit mode with Address Detect

(9th bit = 1)

• Transmit and Receive interrupts

• A separate interrupt for all UART error conditions

• Loopback mode for diagnostic support

• Support for sync and break characters

• Support for automatic baud rate detection

• IrDA^®encoder and decoder logic

The Universal Asynchronous Receiver Transmitter

(UART) module is one of the serial I/O modules avail-

able in the PIC24HJ32GP302/304, PIC24HJ64GPX02/

X04 and PIC24HJ128GPX02/X04 device family. The

UART is a full-duplex asynchronous system that can

communicate with peripheral devices, such as per-

sonal computers, LIN 2.0, RS-232 and RS-485 inter-

faces. The module also supports a hardware flow

control option with the UxCTS and UxRTS pins and

also includes an IrDA^®encoder and decoder.

• 16x baud clock output for IrDA^®support

A simplified block diagram of the UART module is

shown in Figure 18-1. The UART module consists of

these key hardware elements:

• Baud Rate Generator

• Asynchronous Transmitter

• Asynchronous Receiver

FIGURE 18-1:

UART SIMPLIFIED BLOCK DIAGRAM

Baud Rate Generator

IrDA^®

Hardware Flow Control

UART Receiver

UxRTS/BLCKx

UxCTS

UxRX

UxTX

UART Transmitter

Note 1: Both UART1 and UART2 can trigger a DMA data transfer.

2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word

(i.e., UTXISEL<1:0> = 00and URXISEL<1:0> = 00).

DS70293F-page 189

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 18-1: UxMODE: UARTx MODE REGISTER

R/W-0

UARTEN⁽¹⁾

U-0

—

R/W-0

USIDL

R/W-0

IREN⁽²⁾

R/W-0

U-0

—

R/W-0

RTSMD

UEN<1:0>

bit 15

bit 8

R/W-0 HC

WAKE

R/W-0

R/W-0 HC

ABAUD

R/W-0

BRGH

R/W-0

LPBACK

URXINV

PDSEL<1:0>

STSEL

bit 7

bit 0

Legend:

HC = Hardware cleared

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15

UARTEN: UARTx Enable bit⁽¹⁾

1= UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>

0= UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption

minimal

bit 14

bit 13

Unimplemented: Read as ‘0’

USIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12

bit 11

IREN: IrDA^®Encoder and Decoder Enable bit⁽²⁾

1= IrDA encoder and decoder enabled

0= IrDA encoder and decoder disabled

RTSMD: Mode Selection for UxRTS Pin bit

1= UxRTS pin in Simplex mode

0= UxRTS pin in Flow Control mode

bit 10

Unimplemented: Read as ‘0’

UEN<1:0>: UARTx Enable bits

bit 9-8

11= UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches

10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used

01= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches

00= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by

port latches

bit 7

WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit

1= UARTx continues to sample the UxRX pin; interrupt generated on falling edge; bit cleared

in hardware on following rising edge

0= No wake-up enabled

bit 6

bit 5

LPBACK: UARTx Loopback Mode Select bit

1= Enable Loopback mode

0= Loopback mode is disabled

ABAUD: Auto-Baud Enable bit

1= Enable baud rate measurement on the next character – requires reception of a Sync field (55h)

before other data; cleared in hardware upon completion

0= Baud rate measurement disabled or completed

Note 1: Refer to Section 17. “UART” (DS70232) in the “dsPIC33F/PIC24H Family Reference Manual” for

information on enabling the UART module for receive or transmit operation.

2: This feature is only available for the 16x BRG mode (BRGH = 0).

DS70293F-page 190

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED)

bit 4

URXINV: Receive Polarity Inversion bit

1= UxRX Idle state is ‘0’

0= UxRX Idle state is ‘1’

bit 3

BRGH: High Baud Rate Enable bit

1= BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)

0= BRG generates 16 clocks per bit period (16x baud clock, Standard mode)

bit 2-1

PDSEL<1:0>: Parity and Data Selection bits

11= 9-bit data, no parity

10= 8-bit data, odd parity

01= 8-bit data, even parity

00= 8-bit data, no parity

bit 0

STSEL: Stop Bit Selection bit

1= Two Stop bits

0= One Stop bit

Note 1: Refer to Section 17. “UART” (DS70232) in the “dsPIC33F/PIC24H Family Reference Manual” for

information on enabling the UART module for receive or transmit operation.

2: This feature is only available for the 16x BRG mode (BRGH = 0).

DS70293F-page 191

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER

R/W-0

U-0

—

R/W-0 HC

UTXBRK

R/W-0

UTXEN⁽¹⁾

R-0

R-1

UTXISEL1

UTXINV

UTXISEL0

UTXBF

TRMT

bit 15

bit 8

R/W-0

R-1

R-0

R/C-0

R-0

URXISEL<1:0>

ADDEN

RIDLE

PERR

FERR

OERR

URXDA

bit 7

bit 0

Legend:

HC = Hardware cleared

W = Writable bit

C = Clear only bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

‘1’ = Bit is set

bit 15,13

UTXISEL<1:0>: Transmission Interrupt Mode Selection bits

11= Reserved; do not use

10= Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the

transmit buffer becomes empty

01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit

operations are completed

00= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is

at least one character open in the transmit buffer)

bit 14

UTXINV: Transmit Polarity Inversion bit

If IREN = 0:

1= UxTX Idle state is ‘0’

0= UxTX Idle state is ‘1’

If IREN = 1:

1= IrDA^®encoded UxTX Idle state is ‘1’

0= IrDA^®encoded UxTX Idle state is ‘0’

bit 12

bit 11

Unimplemented: Read as ‘0’

UTXBRK: Transmit Break bit

1= Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;

cleared by hardware upon completion

0= Sync Break transmission disabled or completed

bit 10

UTXEN: Transmit Enable bit⁽¹⁾

1= Transmit enabled, UxTX pin controlled by UARTx

0= Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled

by port

bit 9

UTXBF: Transmit Buffer Full Status bit (read-only)

1= Transmit buffer is full

0= Transmit buffer is not full, at least one more character can be written

bit 8

TRMT: Transmit Shift Register Empty bit (read-only)

1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)

0= Transmit Shift Register is not empty, a transmission is in progress or queued

bit 7-6

URXISEL<1:0>: Receive Interrupt Mode Selection bits

11= Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters)

10= Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters)

0x= Interrupt is set when any character is received and transferred from the UxRSR to the receive

buffer. Receive buffer has one or more characters

Note 1: Refer to Section 17. “UART” (DS70232) in the “dsPIC33F/PIC24H Family Reference Manual” for

information on enabling the UART module for transmit operation.

DS70293F-page 192

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)

bit 5

bit 4

bit 3

bit 2

ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1= Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect

0= Address Detect mode disabled

RIDLE: Receiver Idle bit (read-only)

1= Receiver is Idle

0= Receiver is active

PERR: Parity Error Status bit (read-only)

1= Parity error has been detected for the current character (character at the top of the receive FIFO)

0= Parity error has not been detected

FERR: Framing Error Status bit (read-only)

1= Framing error has been detected for the current character (character at the top of the receive

FIFO)

0= Framing error has not been detected

bit 1

bit 0

OERR: Receive Buffer Overrun Error Status bit (read/clear only)

1= Receive buffer has overflowed

0= Receive buffer has not overflowed. Clearing a previously set OERR bit (1→ 0transition) resets

the receiver buffer and the UxRSR to the empty state

URXDA: Receive Buffer Data Available bit (read-only)

1= Receive buffer has data, at least one more character can be read

0= Receive buffer is empty

Note 1: Refer to Section 17. “UART” (DS70232) in the “dsPIC33F/PIC24H Family Reference Manual” for

information on enabling the UART module for transmit operation.

DS70293F-page 193

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

NOTES:

DS70293F-page 194

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

• Programmable Loopback mode supports self-test

operation

19.0 ENHANCED CAN (ECAN™)

MODULE

Note 1: This data sheet summarizes the features

• Signaling via interrupt capabilities for all CAN

receiver and transmitter error states

of

the

PIC24HJ32GP302/304,

and

• Programmable clock source

PIC24HJ64GPX02/X04

• Programmable link to input capture module (IC2

for CAN1) for time-stamping and network

synchronization

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to Section 21. “Enhanced

Controller Area Network (ECAN™)”

(DS70185) of the “dsPIC33F/PIC24H

Family Reference Manual”, which is

available from the Microchip website

(www.microchip.com).

• Low-power Sleep and Idle mode

The CAN bus module consists of a protocol engine and

message buffering/control. The CAN protocol engine

handles all functions for receiving and transmitting

messages on the CAN bus. Messages are transmitted

by first loading the appropriate data registers. Status

and errors can be checked by reading the appropriate

registers. Any message detected on the CAN bus is

checked for errors and then matched against filters to

see if it should be received and stored in one of the

receive registers.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

19.2 Frame Types

The ECAN module transmits various types of frames

which include data messages, or remote transmission

requests initiated by the user, as other frames that are

automatically generated for control purposes. The

following frame types are supported:

19.1 Overview

The Enhanced Controller Area Network (ECAN) module

is a serial interface, useful for communicating with other

CAN modules or microcontroller devices. This interface/

protocol was designed to allow communications within

noisy environments. The PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04

devices contain up to two ECAN modules.

• Standard Data Frame:

A standard data frame is generated by a node when

the node wishes to transmit data. It includes an 11-bit

Standard Identifier (SID), but not an 18-bit Extended

Identifier (EID).

The ECAN module is a communication controller

implementing the CAN 2.0 A/B protocol, as defined in

the BOSCH CAN specification. The module supports

CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B

Active versions of the protocol. The module

implementation is a full CAN system. The CAN specifi-

cation is not covered within this data sheet. The reader

can refer to the BOSCH CAN specification for further

details.

• Extended Data Frame:

An extended data frame is similar to a standard data

frame, but includes an extended identifier as well.

• Remote Frame:

It is possible for a destination node to request the

data from the source. For this purpose, the

destination node sends a remote frame with an iden-

tifier that matches the identifier of the required data

frame. The appropriate data source node sends a

data frame as a response to this remote request.

The module features are as follows:

• Implementation of the CAN protocol, CAN 1.2,

CAN 2.0A and CAN 2.0B

• Error Frame:

• Standard and extended data frames

• Data length of 0-8 bytes

An error frame is generated by any node that detects

a bus error. An error frame consists of two fields: an

error flag field and an error delimiter field.

• Programmable bit rate up to 1 Mbit/sec

• Automatic response to remote transmission

requests

• Overload Frame:

An overload frame can be generated by a node as a

result of two conditions. First, the node detects a

dominant bit during interframe space which is an ille-

gal condition. Second, due to internal conditions, the

node is not yet able to start reception of the next

message. A node can generate a maximum of 2

sequential overload frames to delay the start of the

next message.

• Up to eight transmit buffers with application speci-

fied prioritization and abort capability (each buffer

can contain up to 8 bytes of data)

• Up to 32 receive buffers (each buffer can contain

up to 8 bytes of data)

• Up to 16 full (standard/extended identifier)

acceptance filters

• Three full acceptance filter masks

• DeviceNet™ addressing support

• Interframe Space:

Interframe space separates a proceeding frame (of

whatever type) from a following data or remote

frame.

• Programmable wake-up functionality with

integrated low-pass filter

DS70293F-page 195

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 19-1:

ECAN™ MODULE BLOCK DIAGRAM

RxF15 Filter

RxF14 Filter

RxF13 Filter

RxF12 Filter

RxF11 Filter

RxF10 Filter

RxF9 Filter

RxF8 Filter

RxF7 Filter

RxF6 Filter

RxF5 Filter

RxF4 Filter

RxF3 Filter

RxF2 Filter

RxF1 Filter

RxF0 Filter

DMA Controller

TRB7 TX/RX Buffer Control Register

TRB6 TX/RX Buffer Control Register

TRB5 TX/RX Buffer Control Register

TRB4 TX/RX Buffer Control Register

TRB3 TX/RX Buffer Control Register

TRB2 TX/RX Buffer Control Register

TRB1 TX/RX Buffer Control Register

TRB0 TX/RX Buffer Control Register

RxM2 Mask

RxM1 Mask

RxM0 Mask

Transmit Byte

Sequencer

Message Assembly

Buffer

Control

Configuration

Logic

CPU

Bus

CAN Protocol

Engine

Interrupts

C1Tx

C1Rx

DS70293F-page 196

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

The module can be programmed to apply a low-pass

19.3 Modes of Operation

filter function to the CiRX input line while the module or

the CPU is in Sleep mode. The WAKFIL bit

(CiCFG2<14>) enables or disables the filter.

The ECAN module can operate in one of several

operation modes selected by the user. These modes

include:

Note:

Typically, if the ECAN module is allowed to

transmit in a particular mode of operation

and a transmission is requested immedi-

ately after the ECAN module has been

placed in that mode of operation, the mod-

ule waits for 11 consecutive recessive bits

on the bus before starting transmission. If

the user switches to Disable mode within

this 11-bit period, then this transmission is

aborted and the corresponding TXABT bit

is set and TXREQ bit is cleared.

• Initialization mode

• Disable mode

• Normal Operation mode

• Listen Only mode

• Listen All Messages mode

• Loopback mode

Modes are requested by setting the REQOP<2:0> bits

(CiCTRL1<10:8>). Entry into a mode is Acknowledged

by

monitoring

the

OPMODE<2:0>

bits

(CiCTRL1<7:5>). The module does not change the

mode and the OPMODE bits until a change in mode is

acceptable, generally during bus Idle time, which is

defined as at least 11 consecutive recessive bits.

19.3.3

NORMAL OPERATION MODE

Normal Operation mode is selected when

REQOP<2:0> = 000. In this mode, the module is

activated and the I/O pins assumes the CAN bus

functions. The module transmits and receive CAN bus

messages via the CiTX and CiRX pins.

19.3.1

INITIALIZATION MODE

In the Initialization mode, the module does not transmit

or receive. The error counters are cleared and the inter-

rupt flags remain unchanged. The user application has

access to Configuration registers that are access

restricted in other modes. The module protects the user

from accidentally violating the CAN protocol through

programming errors. All registers which control the

configuration of the module can not be modified while

the module is on-line. The ECAN module is not allowed

to enter the Configuration mode while a transmission is

taking place. The Configuration mode serves as a lock

to protect the following registers:

19.3.4

LISTEN ONLY MODE

If the Listen Only mode is activated, the module on the

CAN bus is passive. The transmitter buffers revert to

the port I/O function. The receive pins remain inputs.

For the receiver, no error flags or Acknowledge signals

are sent. The error counters are deactivated in this

state. The Listen Only mode can be used for detecting

the baud rate on the CAN bus. To use this, it is neces-

sary that there are at least two further nodes that

communicate with each other.

• All Module Control registers

• Baud Rate and Interrupt Configuration registers

• Bus Timing registers

• Identifier Acceptance Filter registers

• Identifier Acceptance Mask registers

19.3.5

LISTEN ALL MESSAGES MODE

The module can be set to ignore all errors and receive

any message. The Listen All Messages mode is

activated by setting REQOP<2:0> = 111. In this mode,

the data which is in the message assembly buffer, until

the time an error occurred, is copied in the receive

buffer and can be read via the CPU interface.

19.3.2

DISABLE MODE

In Disable mode, the ECAN module does not transmit

or receive. The module can set the WAKIF bit due to

bus activity, however, any pending interrupts remains

and the error counters retains their value.

19.3.6

LOOPBACK MODE

If the Loopback mode is activated, the module con-

nects the internal transmit signal to the internal receive

signal at the module boundary. The transmit and

receive pins revert to their port I/O function.

If the REQOP<2:0> bits (CiCTRL1<10:8>) = 001, the

module enters the Module Disable mode. If the module is

active, the module waits for 11 recessive bits on the CAN

bus, detect that condition as an Idle bus, then accept the

module disable command. When the OPMODE<2:0>

bits (CiCTRL1<7:5>) = 001, that indicates whether the

module successfully went into Module Disable mode.

The I/O pins reverts to normal I/O function when the

module is in the Module Disable mode.

DS70293F-page 197

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-1: CiCTRL1: ECAN™ CONTROL REGISTER 1

U-0

—

U-0

—

R/W-0

CSIDL

R/W-0

ABAT

r-0

—

R/W-1

R/W-0

bit 8

REQOP<2:0>

bit 15

R-1

R-0

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0

WIN

OPMODE<2:0>

CANCAP

bit 7

Legend:

bit 0

C = Writable bit, but only ‘0’ can be written to clear the bit r = Bit is Reserved

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

CSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12

ABAT: Abort All Pending Transmissions bit

1= Signal all transmit buffers to abort transmission

0= Module will clear this bit when all transmissions are aborted

bit 11

Reserved: Do not use

bit 10-8

REQOP<2:0>: Request Operation Mode bits

000= Set Normal Operation mode

001= Set Disable mode

010= Set Loopback mode

011= Set Listen Only Mode

100= Set Configuration mode

101= Reserved

110= Reserved

111= Set Listen All Messages mode

bit 7-5

OPMODE<2:0>: Operation Mode bits

000= Module is in Normal Operation mode

001= Module is in Disable mode

010= Module is in Loopback mode

011= Module is in Listen Only mode

100= Module is in Configuration mode

101= Reserved

110= Reserved

111= Module is in Listen All Messages mode

bit 4

bit 3

Unimplemented: Read as ‘0’

CANCAP: CAN Message Receive Timer Capture Event Enable bit

1= Enable input capture based on CAN message receive

0= Disable CAN capture

bit 2-1

bit 0

Unimplemented: Read as ‘0’

WIN: SFR Map Window Select bit

1= Use filter window

0= Use buffer window

DS70293F-page 198

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-2: CiCTRL2: ECAN™ CONTROL REGISTER 2

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

R-0

DNCNT<4:0>

bit 7

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

bit 4-0

Unimplemented: Read as ‘0’

DNCNT<4:0>: DeviceNet™ Filter Bit Number bits

10010-11111= Invalid selection

10001= Compare up to data byte 3, bit 6 with EID<17>

•

00001= Compare up to data byte 1, bit 7 with EID<0>

00000= Do not compare data bytes

DS70293F-page 199

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-3: CiVEC: ECAN™ INTERRUPT CODE REGISTER

U-0

—

U-0

—

U-0

—

R-0

FILHIT<4:0>

bit 15

bit 8

bit 0

U-0

—

R-1

R-0

ICODE<6:0>

bit 7

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

FILHIT<4:0>: Filter Hit Number bits

10000-11111= Reserved

01111= Filter 15

•

00001= Filter 1

00000= Filter 0

bit 7

Unimplemented: Read as ‘0’

bit 6-0

ICODE<6:0>: Interrupt Flag Code bits

1000101-1111111= Reserved

1000100= FIFO almost full interrupt

1000011= Receiver overflow interrupt

1000010= Wake-up interrupt

1000001= Error interrupt

1000000= No interrupt

•

0010000-0111111= Reserved

0001111= RB15 buffer Interrupt

•

0001001= RB9 buffer interrupt

0001000= RB8 buffer interrupt

0000111= TRB7 buffer interrupt

0000110= TRB6 buffer interrupt

0000101= TRB5 buffer interrupt

0000100= TRB4 buffer interrupt

0000011= TRB3 buffer interrupt

0000010= TRB2 buffer interrupt

0000001= TRB1 buffer interrupt

0000000= TRB0 Buffer interrupt

DS70293F-page 200

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-4: CiFCTRL: ECAN™ FIFO CONTROL REGISTER

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

DMABS<2:0>

bit 15

bit 8

R/W-0

bit 0

U-0

—

U-0

—

U-0

—

R/W-0

FSA<4:0>

bit 7

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

DMABS<2:0>: DMA Buffer Size bits

111= Reserved

110= 32 buffers in DMA RAM

101= 24 buffers in DMA RAM

100= 16 buffers in DMA RAM

011= 12 buffers in DMA RAM

010= 8 buffers in DMA RAM

001= 6 buffers in DMA RAM

000= 4 buffers in DMA RAM

bit 12-5

bit 4-0

Unimplemented: Read as ‘0’

FSA<4:0>: FIFO Area Starts with Buffer bits

11111= Read buffer RB31

11110= Read buffer RB30

•

00001= TX/RX buffer TRB1

00000= TX/RX buffer TRB0

DS70293F-page 201

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-5: CiFIFO: ECAN™ FIFO STATUS REGISTER

U-0

—

U-0

—

R-0

FBP<5:0>

R-0

bit 15

bit 8

bit 0

U-0

—

U-0

—

R-0

FNRB<5:0>

bit 7

Legend:

C = Writable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-8

Unimplemented: Read as ‘0’

FBP<5:0>: FIFO Buffer Pointer bits

011111= RB31 buffer

011110= RB30 buffer

•

000001= TRB1 buffer

000000= TRB0 buffer

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

FNRB<5:0>: FIFO Next Read Buffer Pointer bits

011111= RB31 buffer

011110= RB30 buffer

•

000001= TRB1 buffer

000000= TRB0 buffer

DS70293F-page 202

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-6: CiINTF: ECAN™ INTERRUPT FLAG REGISTER

U-0

—

U-0

—

R-0

TXBO

TXBP

RXBP

TXWAR

RXWAR

EWARN

bit 15

bit 8

R/C-0

IVRIF

R/C-0

U-0

—

R/C-0

RBIF

R/C-0

TBIF

WAKIF

ERRIF

FIFOIF

RBOVIF

bit 7

bit 0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

TXBO: Transmitter in Error State Bus Off bit

1= Transmitter is in Bus Off state

0= Transmitter is not in Bus Off state

bit 12

bit 11

bit 10

bit 9

TXBP: Transmitter in Error State Bus Passive bit

1= Transmitter is in Bus Passive state

0= Transmitter is not in Bus Passive state

RXBP: Receiver in Error State Bus Passive bit

1= Receiver is in Bus Passive state

0= Receiver is not in Bus Passive state

TXWAR: Transmitter in Error State Warning bit

1= Transmitter is in Error Warning state

0= Transmitter is not in Error Warning state

RXWAR: Receiver in Error State Warning bit

1= Receiver is in Error Warning state

0= Receiver is not in Error Warning state

bit 8

EWARN: Transmitter or Receiver in Error State Warning bit

1= Transmitter or Receiver is in Error State Warning state

0= Transmitter or Receiver is not in Error State Warning state

bit 7

IVRIF: Invalid Message Received Interrupt Flag bit

1= Interrupt Request has occurred

0= Interrupt Request has not occurred

bit 6

WAKIF: Bus Wake-up Activity Interrupt Flag bit

1= Interrupt Request has occurred

0= Interrupt Request has not occurred

bit 5

ERRIF: Error Interrupt Flag bit (multiple sources in CiINTF<13:8> register)

1= Interrupt Request has occurred

0= Interrupt Request has not occurred

bit 4

bit 3

Unimplemented: Read as ‘0’

FIFOIF: FIFO Almost Full Interrupt Flag bit

1= Interrupt Request has occurred

0= Interrupt Request has not occurred

bit 2

bit 1

bit 0

RBOVIF: RX Buffer Overflow Interrupt Flag bit

1= Interrupt Request has occurred

0= Interrupt Request has not occurred

RBIF: RX Buffer Interrupt Flag bit

1= Interrupt Request has occurred

0= Interrupt Request has not occurred

TBIF: TX Buffer Interrupt Flag bit

1= Interrupt Request has occurred

0= Interrupt Request has not occurred

DS70293F-page 203

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-7: CiINTE: ECAN™ INTERRUPT ENABLE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

IVRIE

R/W-0

ERRIE

U-0

—

R/W-0

RBIE

R/W-0

TBIE

WAKIE

FIFOIE

RBOVIE

bit 7

bit 0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

IVRIE: Invalid Message Received Interrupt Enable bit

1= Interrupt Request Enabled

0= Interrupt Request not enabled

bit 6

bit 5

WAKIE: Bus Wake-up Activity Interrupt Flag bit

1= Interrupt Request Enabled

0= Interrupt Request not enabled

ERRIE: Error Interrupt Enable bit

1= Interrupt Request Enabled

0= Interrupt Request not enabled

bit 4

bit 3

Unimplemented: Read as ‘0’

FIFOIE: FIFO Almost Full Interrupt Enable bit

1= Interrupt Request Enabled

0= Interrupt Request not enabled

bit 2

bit 1

bit 0

RBOVIE: RX Buffer Overflow Interrupt Enable bit

1= Interrupt Request Enabled

0= Interrupt Request not enabled

RBIE: RX Buffer Interrupt Enable bit

1= Interrupt Request Enabled

0= Interrupt Request not enabled

TBIE: TX Buffer Interrupt Enable bit

1= Interrupt Request Enabled

0= Interrupt Request not enabled

DS70293F-page 204

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-8: CiEC: ECAN™ TRANSMIT/RECEIVE ERROR COUNT REGISTER

R-0

bit 15

R-0

TERRCNT<7:0>

bit 8

bit 0

R-0

RERRCNT<7:0>

bit 7

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

TERRCNT<7:0>: Transmit Error Count bits

RERRCNT<7:0>: Receive Error Count bits

REGISTER 19-9: CiCFG1: ECAN™ BAUD RATE CONFIGURATION REGISTER 1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

bit 0

SJW<1:0>

BRP<5:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-6

Unimplemented: Read as ‘0’

SJW<1:0>: Synchronization Jump Width bits

11= Length is 4 x TQ

10= Length is 3 x TQ

01= Length is 2 x TQ

00= Length is 1 x TQ

bit 5-0

BRP<5:0>: Baud Rate Prescaler bits

11 1111= TQ = 2 x 64 x 1/FCAN

•

00 0010= TQ = 2 x 3 x 1/FCAN

00 0001= TQ = 2 x 2 x 1/FCAN

00 0000= TQ = 2 x 1 x 1/FCAN

DS70293F-page 205

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-10: CiCFG2: ECAN™ BAUD RATE CONFIGURATION REGISTER 2

U-0

—

R/W-x

U-0

—

U-0

—

U-0

—

R/W-x

bit 8

R/W-x

bit 0

WAKFIL

SEG2PH<2:0>

bit 15

R/W-x

SAM

R/W-x

SEG2PHTS

SEG1PH<2:0>

PRSEG<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

WAKFIL: Select CAN bus Line Filter for Wake-up bit

1= Use CAN bus line filter for wake-up

0= CAN bus line filter is not used for wake-up

bit 13-11

bit 10-8

Unimplemented: Read as ‘0’

SEG2PH<2:0>: Phase Segment 2 bits

111= Length is 8 x TQ

•

000= Length is 1 x TQ

bit 7

SEG2PHTS: Phase Segment 2 Time Select bit

1= Freely programmable

0= Maximum of SEG1PH bits or Information Processing Time (IPT), whichever is greater

bit 6

SAM: Sample of the CAN bus Line bit

1= Bus line is sampled three times at the sample point

0= Bus line is sampled once at the sample point

bit 5-3

SEG1PH<2:0>: Phase Segment 1 bits

111= Length is 8 x TQ

•

000= Length is 1 x TQ

bit 2-0

PRSEG<2:0>: Propagation Time Segment bits

111= Length is 8 x TQ

•

000= Length is 1 x TQ

DS70293F-page 206

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-11: CiFEN1: ECAN™ ACCEPTANCE FILTER ENABLE REGISTER

R/W-1

FLTEN15

FLTEN14

FLTEN13

FLTEN12

FLTEN11

FLTEN10

FLTEN9

FLTEN8

bit 15

bit 8

R/W-1

FLTEN7

FLTEN6

FLTEN5

FLTEN4

FLTEN3

FLTEN2

FLTEN1

FLTEN0

bit 7

bit 0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-0

FLTENn: Enable Filter n to Accept Messages bits

1= Enable Filter n

0= Disable Filter n

REGISTER 19-12: CiBUFPNT1: ECAN™ FILTER 0-3 BUFFER POINTER REGISTER

R/W-0

bit 15

R/W-0

bit 7

R/W-0

bit 8

R/W-0

bit 0

F3BP<3:0>

F2BP<3:0>

R/W-0

F1BP<3:0>

R/W-0

F0BP<3:0>

R/W-0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

F3BP<3:0>: RX Buffer mask for Filter 3

1111= Filter hits received in RX FIFO buffer

1110= Filter hits received in RX Buffer 14

•

0001= Filter hits received in RX Buffer 1

0000= Filter hits received in RX Buffer 0

bit 11-8

bit 7-4

bit 3-0

F2BP<3:0>: RX Buffer mask for Filter 2 (same values as bit 15-12)

F1BP<3:0>: RX Buffer mask for Filter 1 (same values as bit 15-12)

F0BP<3:0>: RX Buffer mask for Filter 0 (same values as bit 15-12)

DS70293F-page 207

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-13: CiBUFPNT2: ECAN™ FILTER 4-7 BUFFER POINTER REGISTER

R/W-0

bit 15

R/W-0

bit 7

R/W-0

bit 8

R/W-0

bit 0

F7BP<3:0>

F6BP<3:0>

R/W-0

F5BP<3:0>

R/W-0

F4BP<3:0>

R/W-0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

F7BP<3:0>: RX Buffer mask for Filter 7

1111= Filter hits received in RX FIFO buffer

1110= Filter hits received in RX Buffer 14

•

0001= Filter hits received in RX Buffer 1

0000= Filter hits received in RX Buffer 0

bit 11-8

bit 7-4

bit 3-0

F6BP<3:0>: RX Buffer mask for Filter 6 (same values as bit 15-12)

F5BP<3:0>: RX Buffer mask for Filter 5 (same values as bit 15-12)

F4BP<3:0>: RX Buffer mask for Filter 4 (same values as bit 15-12)

REGISTER 19-14: CiBUFPNT3: ECAN™ FILTER 8-11 BUFFER POINTER REGISTER

R/W-0

bit 15

R/W-0

bit 7

R/W-0

bit 8

R/W-0

bit 0

F11BP<3:0>

F10BP<3:0>

R/W-0

F9BP<3:0>

R/W-0

F8BP<3:0>

R/W-0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

F11BP<3:0>: RX Buffer mask for Filter 11

1111= Filter hits received in RX FIFO buffer

1110= Filter hits received in RX Buffer 14

•

0001= Filter hits received in RX Buffer 1

0000= Filter hits received in RX Buffer 0

bit 11-8

bit 7-4

bit 3-0

F10BP<3:0>: RX Buffer mask for Filter 10 (same values as bit 15-12)

F9BP<3:0>: RX Buffer mask for Filter 9 (same values as bit 15-12)

F8BP<3:0>: RX Buffer mask for Filter 8 (same values as bit 15-12)

DS70293F-page 208

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-15: CiBUFPNT4: ECAN™ FILTER 12-15 BUFFER POINTER REGISTER

R/W-0

bit 15

R/W-0

bit 7

R/W-0

bit 8

R/W-0

bit 0

F15BP<3:0>

F14BP<3:0>

R/W-0

F13BP<3:0>

R/W-0

F12BP<3:0>

R/W-0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

F15BP<3:0>: RX Buffer mask for Filter 15

1111= Filter hits received in RX FIFO buffer

1110= Filter hits received in RX Buffer 14

•

0001= Filter hits received in RX Buffer 1

0000= Filter hits received in RX Buffer 0

bit 11-8

bit 7-4

bit 3-0

F14BP<3:0>: RX Buffer mask for Filter 14 (same values as bit 15-12)

F13BP<3:0>: RX Buffer mask for Filter 13 (same values as bit 15-12)

F12BP<3:0>: RX Buffer mask for Filter 12 (same values as bit 15-12)

DS70293F-page 209

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-16: CiRXFnSID: ECAN™ ACCEPTANCE FILTER STANDARD IDENTIFIER REGISTER

n (n = 0-15)

R/W-x

SID10

R/W-x

SID9

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

bit 15

bit 8

R/W-x

SID2

R/W-x

SID1

R/W-x

SID0

U-0

—

R/W-x

EXIDE

U-0

—

R/W-x

EID17

R/W-x

EID16

bit 7

bit 0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

SID<10:0>: Standard Identifier bits

1= Message address bit SIDx must be ‘1’ to match filter

0= Message address bit SIDx must be ‘0’ to match filter

bit 4

bit 3

Unimplemented: Read as ‘0’

EXIDE: Extended Identifier Enable bit

If MIDE = 1, then:

1= Match only messages with extended identifier addresses

0= Match only messages with standard identifier addresses

If MIDE = 0, then:

Ignore the EXIDE bit.

bit 2

Unimplemented: Read as ‘0’

bit 1-0

EID<17:16>: Extended Identifier bits

1= Message address bit EIDx must be ‘1’ to match filter

0= Message address bit EIDx must be ‘0’ to match filter

DS70293F-page 210

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-17: CiRXFnEID: ECAN™ ACCEPTANCE FILTER EXTENDED IDENTIFIER REGISTER

n (n = 0-15)

R/W-x

EID15

R/W-x

EID14

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

bit 15

bit 8

R/W-x

EID7

R/W-x

EID6

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

bit 7

bit 0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

EID<15:0>: Extended Identifier bits

1= Message address bit EIDx must be ‘1’ to match filter

0= Message address bit EIDx must be ‘0’ to match filter

REGISTER 19-18: CiFMSKSEL1: ECAN™ FILTER 7-0 MASK SELECTION REGISTER

R/W-0

F7MSK<1:0>

F6MSK<1:0>

F5MSK<1:0>

F4MSK<1:0>

bit 15

bit 8

R/W-0 R/W-0

F3MSK<1:0>

R/W-0

F2MSK<1:0>

F1MSK<1:0>

F0MSK<1:0>

bit 7

bit 0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

F7MSK<1:0>: Mask Source for Filter 7 bit

11= No mask

10= Acceptance Mask 2 registers contain mask

01= Acceptance Mask 1 registers contain mask

00= Acceptance Mask 0 registers contain mask

bit 13-12

bit 11-10

bit 9-8

F6MSK<1:0>: Mask Source for Filter 6 bit (same values as bit 15-14)

F5MSK<1:0>: Mask Source for Filter 5 bit (same values as bit 15-14)

F4MSK<1:0>: Mask Source for Filter 4 bit (same values as bit 15-14)

F3MSK<1:0>: Mask Source for Filter 3 bit (same values as bit 15-14)

F2MSK<1:0>: Mask Source for Filter 2 bit (same values as bit 15-14)

F1MSK<1:0>: Mask Source for Filter 1 bit (same values as bit 15-14)

F0MSK<1:0>: Mask Source for Filter 0 bit (same values as bit 15-14)

bit 7-6

bit 5-4

bit 3-2

bit 1-0

DS70293F-page 211

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-19: CiFMSKSEL2: ECAN™ FILTER 15-8 MASK SELECTION REGISTER

R/W-0

F15MSK<1:0>

F14MSK<1:0>

F13MSK<1:0>

F12MSK<1:0>

bit 15

R/W-0

bit 8

R/W-0

F11MSK<1:0>

F10MSK<1:0>

F9MSK<1:0>

F8MSK<1:0>

bit 7

bit 0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

F15MSK<1:0>: Mask Source for Filter 15 bit

11= No mask

10= Acceptance Mask 2 registers contain mask

01= Acceptance Mask 1 registers contain mask

00= Acceptance Mask 0 registers contain mask

bit 13-12

bit 11-10

bit 9-8

F14MSK<1:0>: Mask Source for Filter 14 bit (same values as bit 15-14)

F13MSK<1:0>: Mask Source for Filter 13 bit (same values as bit 15-14)

F12MSK<1:0>: Mask Source for Filter 12 bit (same values as bit 15-14)

F11MSK<1:0>: Mask Source for Filter 11 bit (same values as bit 15-14)

F10MSK<1:0>: Mask Source for Filter 10 bit (same values as bit 15-14)

F9MSK<1:0>: Mask Source for Filter 9 bit (same values as bit 15-14)

F8MSK<1:0>: Mask Source for Filter 8 bit (same values as bit 15-14)

bit 7-6

bit 5-4

bit 3-2

bit 1-0

DS70293F-page 212

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-20: CiRXMnSID: ECAN™ ACCEPTANCE FILTER MASK STANDARD IDENTIFIER

REGISTER n (n = 0-2)

R/W-x

SID10

R/W-x

SID9

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

bit 15

bit 8

R/W-x

SID2

R/W-x

SID1

R/W-x

SID0

U-0

—

R/W-x

MIDE

U-0

—

R/W-x

EID17

R/W-x

EID16

bit 7

bit 0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

SID<10:0>: Standard Identifier bits

1= Include bit SIDx in filter comparison

0= Bit SIDx is don’t care in filter comparison

bit 4

bit 3

Unimplemented: Read as ‘0’

MIDE: Identifier Receive Mode bit

1= Match only message types (standard or extended address) that correspond to EXIDE bit in filter

0= Match either standard or extended address message if filters match

(i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID))

bit 2

Unimplemented: Read as ‘0’

bit 1-0

EID<17:16>: Extended Identifier bits

1= Include bit EIDx in filter comparison

0= Bit EIDx is don’t care in filter comparison

REGISTER 19-21: CiRXMnEID: ECAN™ ACCEPTANCE FILTER MASK EXTENDED IDENTIFIER

REGISTER n (n = 0-2)

R/W-x

EID15

R/W-x

EID14

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

bit 15

bit 8

R/W-x

EID7

R/W-x

EID6

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

bit 7

bit 0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

EID<15:0>: Extended Identifier bits

1= Include bit EIDx in filter comparison

0= Bit EIDx is don’t care in filter comparison

DS70293F-page 213

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-22: CiRXFUL1: ECAN™ RECEIVE BUFFER FULL REGISTER 1

R/C-0

RXFUL15

RXFUL14

RXFUL13

RXFUL12

RXFUL11

RXFUL10

RXFUL9

RXFUL8

bit 15

bit 8

R/C-0

RXFUL7

RXFUL6

RXFUL5

RXFUL4

RXFUL3

RXFUL2

RXFUL1

RXFUL0

bit 7

bit 0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-0

RXFUL<15:0>: Receive Buffer n Full bits

1= Buffer is full (set by module)

0= Buffer is empty

REGISTER 19-23: CiRXFUL2: ECAN™ RECEIVE BUFFER FULL REGISTER 2

R/C-0

RXFUL24

bit 8

RXFUL31

RXFUL30

RXFUL29

RXFUL28

RXFUL27

RXFUL26

RXFUL25

bit 15

R/C-0

RXFUL23

RXFUL22

RXFUL21

RXFUL20

RXFUL19

RXFUL18

RXFUL17

RXFUL16

bit 7

bit 0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-0

RXFUL<31:16>: Receive Buffer n Full bits

1= Buffer is full (set by module)

0= Buffer is empty

DS70293F-page 214

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-24: CiRXOVF1: ECAN™ RECEIVE BUFFER OVERFLOW REGISTER 1

R/C-0

RXOVF15

RXOVF14

RXOVF13

RXOVF12

RXOVF11

RXOVF10

RXOVF9

RXOVF8

bit 15

bit 8

R/C-0

RXOVF7

RXOVF6

RXOVF5

RXOVF4

RXOVF3

RXOVF2

RXOVF1

RXOVF0

bit 7

bit 0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-0

RXOVF<15:0>: Receive Buffer n Overflow bits

1= Module attempted to write to a full buffer (set by module)

0= No overflow condition

REGISTER 19-25: CiRXOVF2: ECAN™ RECEIVE BUFFER OVERFLOW REGISTER 2

R/C-0

RXOVF24

bit 8

RXOVF31

RXOVF30

RXOVF29

RXOVF28

RXOVF27

RXOVF26

RXOVF25

bit 15

R/C-0

RXOVF23

RXOVF22

RXOVF21

RXOVF20

RXOVF19

RXOVF18

RXOVF17

RXOVF16

bit 7

bit 0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-0

RXOVF<31:16>: Receive Buffer n Overflow bits

1= Module attempted to write to a full buffer (set by module)

0= No overflow condition

DS70293F-page 215

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 19-26: CiTRmnCON: ECAN™ TX/RX BUFFER m CONTROL REGISTER

(m = 0,2,4,6; n = 1,3,5,7)

R/W-0

R-0

R/W-0

TXENn

TXABTn

TXLARBn

TXERRn

TXREQn

RTRENn

TXnPRI<1:0>

bit 15

bit 8

R/W-0

R-0

R/W-0

TXENm

TXABTm⁽¹⁾TXLARBm⁽¹⁾TXERRm⁽¹⁾TXREQm

RTRENm

TXmPRI<1:0>

bit 7

bit 0

Legend:

C = Writeable bit, but only ‘0’ can be written to clear the bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

See Definition for Bits 7-0, Controls Buffer n

TXENm: TX/RX Buffer Selection bit

1= Buffer TRBn is a transmit buffer

0= Buffer TRBn is a receive buffer

bit 6

bit 5

bit 4

bit 3

TXABTm: Message Aborted bit⁽¹⁾

1= Message was aborted

0= Message completed transmission successfully

TXLARBm: Message Lost Arbitration bit⁽¹⁾

1= Message lost arbitration while being sent

0= Message did not lose arbitration while being sent

TXERRm: Error Detected During Transmission bit⁽¹⁾

1= A bus error occurred while the message was being sent

0= A bus error did not occur while the message was being sent

TXREQm: Message Send Request bit

1= Requests that a message be sent. The bit automatically clears when the message is successfully

sent

0= Clearing the bit to ‘0’ while set requests a message abort

bit 2

RTRENm: Auto-Remote Transmit Enable bit

1= When a remote transmit is received, TXREQ will be set

0= When a remote transmit is received, TXREQ will be unaffected

bit 1-0

TXmPRI<1:0>: Message Transmission Priority bits

11= Highest message priority

10= High intermediate message priority

01= Low intermediate message priority

00= Lowest message priority

Note 1: This bit is cleared when the TXREQ bit is set.

Note:

The buffers, SID, EID, DLC, Data Field and Receive Status registers are located in DMA RAM.

DS70293F-page 216

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

19.4 ECAN Message Buffers

ECAN Message Buffers are part of DMA RAM Memory.

They are not ECAN special function registers. The user

application must directly write into the DMA RAM area

that is configured for ECAN Message Buffers. The

location and size of the buffer area is defined by the

user application.

BUFFER 19-1:

ECAN™ MESSAGE BUFFER WORD 0

U-0

—

U-0

—

U-0

—

R/W-x

SID10

R/W-x

SID9

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

bit 15

bit 8

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

R/W-x

SID2

R/W-x

SID1

R/W-x

SID0

R/W-x

SRR

R/W-x

IDE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-2

bit 1

Unimplemented: Read as ‘0’

SID<10:0>: Standard Identifier bits

SRR: Substitute Remote Request bit

1= Message will request remote transmission

0= Normal message

bit 0

IDE: Extended Identifier bit

1= Message will transmit extended identifier

0= Message will transmit standard identifier

BUFFER 19-2:

ECAN™ MESSAGE BUFFER WORD 1

U-0

—

U-0

—

U-0

—

U-0

—

R/W-x

EID17

R/W-x

EID16

R/W-x

EID15

R/W-x

EID14

bit 15

bit 8

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

R/W-x

EID7

R/W-x

EID6

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

bit 11-0

Unimplemented: Read as ‘0’

EID<17:6>: Extended Identifier bits

DS70293F-page 217

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(

BUFFER 19-3:

ECAN™ MESSAGE BUFFER WORD 2

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

R/W-x

RTR

R/W-x

RB1

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-x

RB0

R/W-x

DLC3

R/W-x

DLC2

R/W-x

DLC1

R/W-x

DLC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-10

bit 9

EID<5:0>: Extended Identifier bits

RTR: Remote Transmission Request bit

1= Message will request remote transmission

0= Normal message

bit 8

RB1: Reserved Bit 1

User must set this bit to ‘0’ per CAN protocol.

Unimplemented: Read as ‘0’

RB0: Reserved Bit 0

bit 7-5

bit 4

User must set this bit to ‘0’ per CAN protocol.

DLC<3:0>: Data Length Code bits

bit 3-0

BUFFER 19-4:

ECAN

R/W-x

™ MESSAGE BUFFER WORD 3

R/W-x

bit 8

R/W-x

bit 0

Byte 1

bit 15

R/W-x

Byte 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

Byte 1<15:8>: ECAN™ Message Byte 0

Byte 0<7:0>: ECAN Message Byte 1

DS70293F-page 218

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

BUFFER 19-5:

ECAN

R/W-x

™ MESSAGE BUFFER WORD 4

R/W-x

bit 8

R/W-x

bit 0

Byte 3

bit 15

R/W-x

Byte 2

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

Byte 3<15:8>: ECAN™ Message Byte 3

Byte 2<7:0>: ECAN Message Byte 2

BUFFER 19-6:

ECAN

R/W-x

™ MESSAGE BUFFER WORD 5

R/W-x

bit 8

R/W-x

bit 0

Byte 5

bit 15

R/W-x

Byte 4

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

Byte 5<15:8>: ECAN™ Message Byte 5

Byte 4<7:0>: ECAN Message Byte 4

DS70293F-page 219

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

BUFFER 19-7:

ECAN

R/W-x

™ MESSAGE BUFFER WORD 6

R/W-x

bit 8

R/W-x

bit 0

Byte 7

bit 15

R/W-x

Byte 6

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

Byte 7<15:8>: ECAN™ Message Byte 7

Byte 6<7:0>: ECAN Message Byte 6

BUFFER 19-8:

ECAN™ MESSAGE BUFFER WORD 7

U-0

—

U-0

—

U-0

—

R/W-x

FILHIT<4:0>⁽¹⁾

R/W-x

bit 8

bit 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

FILHIT<4:0>: Filter Hit Code bits⁽¹⁾

Encodes number of filter that resulted in writing this buffer.

bit 7-0

Unimplemented: Read as ‘0’

Note 1: Only written by module for receive buffers, unused for transmit buffers.

DS70293F-page 220

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

Depending on the particular device pinout, the ADC

20.0 10-BIT/12-BIT

can have up to 13 analog input pins, designated AN0

through AN12. In addition, there are two analog input

pins for external voltage reference connections. These

voltage reference inputs can be shared with other

analog input pins. The actual number of analog input

pins and external voltage reference input configuration

depends on the specific device.

ANALOG-TO-DIGITAL

CONVERTER (ADC1)

Note 1: This data sheet summarizes the features

of

the

PIC24HJ32GP302/304,

and

PIC24HJ64GPX02/X04

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to Section 16. “Analog-to-Digital

Converter (ADC)” (DS70183) of the

“dsPIC33F/PIC24H Family Reference

Manual”, which is available from the

Microchip website (www.microchip.com).

Block diagrams of the ADC module are shown in

Figure 20-1 and Figure 20-2.

20.2 ADC Initialization

The following configuration steps should be performed.

1. Configure the ADC module:

a) Select port pins as analog inputs

(AD1PCFGH<15:0> or AD1PCFGL<15:0>)

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

b) Select voltage reference source to match

expected range on analog inputs

(AD1CON2<15:13>)

c) Select the analog conversion clock to

match desired data rate with processor

clock (AD1CON3<7:0>)

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 devices have up to 13

ADC input channels.

d) Determine how many S/H channels are

used

(AD1CON2<9:8>

and

AD1PCFGH<15:0> or AD1PCFGL<15:0>)

The AD12B bit (AD1CON1<10>) allows each of the

ADC modules to be configured by the user as either a

10-bit, 4-sample/hold ADC (default configuration) or a

12-bit, 1-sample/hold ADC.

e) Select the appropriate sample/conversion

sequence

(AD1CON1<7:5>

and

AD1CON3<12:8>)

f) Select how conversion results are

presented in the buffer (AD1CON1<9:8>)

Note:

The ADC module needs to be disabled

before modifying the AD12B bit.

g) Turn on ADC module (AD1CON1<15>)

2. Configure ADC interrupt (if required):

a) Clear the AD1IF bit

20.1 Key Features

b) Select ADC interrupt priority

The 10-bit ADC configuration has the following key

features:

20.3 ADC and DMA

• Successive Approximation (SAR) conversion

• Conversion speeds of up to 1.1 Msps

• Up to 13 analog input pins

If more than one conversion result needs to be buffered

before triggering an interrupt, DMA data transfers can

be used. ADC1 can trigger a DMA data transfer. If

ADC1 is selected as the DMA IRQ source, a DMA

transfer occurs when the AD1IF bit gets set as a result

of an ADC1 sample conversion sequence.

• External voltage reference input pins

• Simultaneous sampling of up to four analog input

pins

• Automatic Channel Scan mode

The SMPI<3:0> bits (AD1CON2<5:2>) are used to

select how often the DMA RAM buffer pointer is

incremented.

• Selectable conversion trigger source

• Selectable Buffer Fill modes

• Operation during CPU Sleep and Idle modes

The ADDMABM bit (AD1CON1<12>) determines how

the conversion results are filled in the DMA RAM buffer

area being used for ADC. If this bit is set, DMA buffers

are written in the order of conversion. The module

provides an address to the DMA channel that is the

same as the address used for the non-DMA

stand-alone buffer. If the ADDMABM bit is cleared, then

DMA buffers are written in Scatter/Gather mode. The

module provides a scatter/gather address to the DMA

channel, based on the index of the analog input and the

size of the DMA buffer.

The 12-bit ADC configuration supports all the above

features, except:

• In the 12-bit configuration, conversion speeds of

up to 500 ksps are supported

• There is only one sample/hold amplifier in the

12-bit configuration, so simultaneous sampling of

multiple channels is not supported.

DS70293F-page 221

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 20-1:

ADC1 MODULE BLOCK DIAGRAM FOR PIC24HJ32GP304, PIC24HJ64GP204/504

AND PIC24HJ128GP204/504 DEVICES

AN0

AN12

S/H0

CHANNEL

SCAN

+

CH0SB<4:0>

-

CH0SA<4:0>

CH0

CSCNA

AN1

VREFL

CH0NB

CH0NA

AN0

AN3

(1)

VREF-

AVSS

VREF+

AVDD

S/H1

+

-

CH123SA

CH123SB

(2)

CH1

AN6

VCFG<2:0>

AN9

VREFL

VREFH

VREFL

CH123NB

CH123NA

ADC1BUF0

SAR ADC

AN1

AN4

S/H2

+

-

CH123SA

CH123SB

(2)

CH2

AN7

AN10

VREFL

CH123NA

CH123NB

AN2

AN5

S/H3

+

-

CH123SA CH123SB

AN8

(2)

CH3

AN11

VREFL

CH123NA

CH123NB

Alternate

Input Selection

Note 1:VREF+, VREF- inputs can be multiplexed with other analog inputs.

2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.

DS70293F-page 222

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 20-2:

ADC1 MODULE BLOCK DIAGRAM FOR PIC24HJ32GP302, PIC24HJ64GP202/502

AND PIC24HJ128GP202/502 DEVICES

AN0

AN12

S/H0

CHANNEL

+

SCAN

CH0SB<4:0>

-

CH0SA<4:0>

CH0

CSCNA

AN1

VREFL

CH0NB

CH0NA

AN0

AN3

(1)

VREF-

AVSS

VREF+

AVDD

S/H1

+

-

CH123SA

CH123SB

(2)

CH1

VCFG<2:0>

AN9

VREFL

VREFH

VREFL

CH123NB

CH123NA

ADC1BUF0

SAR ADC

AN1

AN4

S/H2

+

-

CH123SA

CH123SB

(2)

CH2

AN10

VREFL

CH123NA

CH123NB

AN2

AN5

S/H3

+

-

CH123SA CH123SB

(2)

CH3

AN11

VREFL

CH123NA

CH123NB

Alternate

Input Selection

Note 1:VREF+, VREF- inputs can be multiplexed with other analog inputs.

2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.

DS70293F-page 223

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 20-3:

ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM

AD1CON3<15>

ADC Internal

RC Clock⁽²⁾

1

0

TAD

AD1CON3<7:0>

6

ADC Conversion

Clock Multiplier

TCY

(1)

X2

TOSC

1, 2, 3, 4, 5,..., 64

Note 1: Refer to Figure 9-2 for the derivation of Fosc when the PLL is enabled. If the PLL is not used, Fosc is equal to

the clock source frequency. Tosc = 1/Fosc

2: See the ADC electrical characteristics for the exact RC clock value.

DS70293F-page 224

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 20-1: AD1CON1: ADC1 CONTROL REGISTER 1

R/W-0

ADON

U-0

—

R/W-0

U-0

—

R/W-0

ADSIDL

ADDMABM

AD12B

FORM<1:0>

bit 15

bit 8

R/W-0

U-0

—

R/W-0

ASAM

R/W-0

HC,HS

R/C-0

HC, HS

SSRC<2:0>

SIMSAM

SAMP

DONE

bit 7

Legend:

bit 0

HC = Cleared by hardware

W = Writable bit

HS = Set by hardware

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

C = Clear only bit

R = Readable bit

-n = Value at POR

‘1’ = Bit is set

bit 15

ADON: ADC Operating Mode bit

1= ADC module is operating

0= ADC is off

bit 14

bit 13

Unimplemented: Read as ‘0’

ADSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12

ADDMABM: DMA Buffer Build Mode bit

1= DMA buffers are written in the order of conversion. The module provides an address to the DMA

channel that is the same as the address used for the non-DMA stand-alone buffer

0= DMA buffers are written in Scatter/Gather mode. The module provides a scatter/gather address

to the DMA channel, based on the index of the analog input and the size of the DMA buffer

bit 11

bit 10

Unimplemented: Read as ‘0’

AD12B: 10-bit or 12-bit Operation Mode bit

1= 12-bit, 1-channel ADC operation

0= 10-bit, 4-channel ADC operation

bit 9-8

FORM<1:0>: Data Output Format bits

For 10-bit operation:

11= Reserved

10= Reserved

01= Signed integer (DOUT = ssss sssd dddd dddd, where s= .NOT.d<9>)

00= Integer (DOUT = 0000 00dd dddd dddd)

For 12-bit operation:

11= Reserved

10= Reserved

01= Signed Integer (DOUT = ssss sddd dddd dddd, where s= .NOT.d<11>)

00= Integer (DOUT = 0000 dddd dddd dddd)

bit 7-5

SSRC<2:0>: Sample Clock Source Select bits

111= Internal counter ends sampling and starts conversion (auto-convert)

110= Reserved

101= Reserved

100= GP timer (Timer5 for ADC1) compare ends sampling and starts conversion

011= Reserved

010= GP timer (Timer3 for ADC1) compare ends sampling and starts conversion

001= Active transition on INT0 pin ends sampling and starts conversion

000= Clearing sample bit ends sampling and starts conversion

bit 4

Unimplemented: Read as ‘0’

DS70293F-page 225

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 20-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED)

bit 3

SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01or 1x)

When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’

1= Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or

Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)

0= Samples multiple channels individually in sequence

bit 2

bit 1

ASAM: ADC Sample Auto-Start bit

1= Sampling begins immediately after last conversion. SAMP bit is auto-set

0= Sampling begins when SAMP bit is set

SAMP: ADC Sample Enable bit

1= ADC sample/hold amplifiers are sampling

0= ADC sample/hold amplifiers are holding

If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.

If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC ≠ 000,

automatically cleared by hardware to end sampling and start conversion.

bit 0

DONE: ADC Conversion Status bit

1= ADC conversion cycle is completed

0= ADC conversion not started or in progress

Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear

DONE status (software not allowed to write ‘1’). Clearing this bit does NOT affect any operation in

progress. Automatically cleared by hardware at start of a new conversion.

DS70293F-page 226

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 20-2: AD1CON2: ADC1 CONTROL REGISTER 2

R/W-0

U-0

—

U-0

—

R/W-0

VCFG<2:0>

CSCNA

CHPS<1:0>

bit 15

bit 8

R-0

U-0

—

R/W-0

BUFM

R/W-0

ALTS

BUFS

SMPI<3:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

VCFG<2:0>: Converter Voltage Reference Configuration bits

ADREF+

ADREF-

000

AVDD

AVSS

001 External VREF+

010

011 External VREF+

1xx

AVDD

External VREF-

Avss

AVDD

bit 12-11

bit 10

Unimplemented: Read as ‘0’

CSCNA: Scan Input Selections for CH0+ during Sample A bit

1= Scan inputs

0= Do not scan inputs

bit 9-8

bit 7

CHPS<1:0>: Selects Channels Utilized bits

When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’

1x= Converts CH0, CH1, CH2 and CH3

01= Converts CH0 and CH1

00= Converts CH0

BUFS: Buffer Fill Status bit (only valid when BUFM = 1)

1= ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7

0= ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF

bit 6

Unimplemented: Read as ‘0’

bit 5-2

SMPI<3:0>: Selects Increment Rate for DMA Addresses bits or number of sample/conversion

operations per interrupt

1111= Increments the DMA address or generates interrupt after completion of every 16th

sample/conversion operation

1110= Increments the DMA address or generates interrupt after completion of every 15th

sample/conversion operation

•

0001= Increments the DMA address after completion of every 2nd sample/conversion operation

0000= Increments the DMA address after completion of every sample/conversion operation

bit 1

bit 0

BUFM: Buffer Fill Mode Select bit

1= Starts buffer filling at address 0x0 on first interrupt and 0x8 on next interrupt

0= Always starts filling buffer at address 0x0

ALTS: Alternate Input Sample Mode Select bit

1= Uses channel input selects for Sample A on first sample and Sample B on next sample

0= Always uses channel input selects for Sample A

DS70293F-page 227

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 20-3: AD1CON3: ADC1 CONTROL REGISTER 3

R/W-0

ADRC

U-0

—

U-0

—

R/W-0

SAMC<4:0>⁽¹⁾

R/W-0

bit 8

R/W-0

bit 0

bit 15

R/W-0

bit 7

R/W-0

ADCS<7:0>⁽²⁾

R/W-0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

ADRC: ADC Conversion Clock Source bit

1= ADC internal RC clock

0= Clock derived from system clock

bit 14-13

bit 12-8

Unimplemented: Read as ‘0’

SAMC<4:0>: Auto Sample Time bits⁽¹⁾

11111= 31 TAD

•

00001= 1 TAD

00000= 0 TAD

bit 7-0

ADCS<7:0>: ADC Conversion Clock Select bits⁽²⁾

11111111= Reserved

•

01000000= Reserved

00111111= TCY ·(ADCS<7:0> + 1) = 64 ·TCY = TAD

•

00000010= TCY ·(ADCS<7:0> + 1) = 3 ·TCY = TAD

00000001= TCY ·(ADCS<7:0> + 1) = 2 ·TCY = TAD

00000000= TCY ·(ADCS<7:0> + 1) = 1 ·TCY = TAD

Note 1: This bit only used if AD1CON1<7:5 (SSRC<2:0>) = 111.

2: This bit is not used if AD1CON3<15> (ADRC) = 1.

DS70293F-page 228

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 20-4: AD1CON4: ADC1 CONTROL REGISTER 4

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

DMABL<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-0

Unimplemented: Read as ‘0’

DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog Input bits

111= Allocates 128 words of buffer to each analog input

110= Allocates 64 words of buffer to each analog input

101= Allocates 32 words of buffer to each analog input

100= Allocates 16 words of buffer to each analog input

011= Allocates 8 words of buffer to each analog input

010= Allocates 4 words of buffer to each analog input

001= Allocates 2 words of buffer to each analog input

000= Allocates 1 word of buffer to each analog input

DS70293F-page 229

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 20-5: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CH123NB<1:0>

CH123SB

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CH123NA<1:0>

CH123SA

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-9

Unimplemented: Read as ‘0’

CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits

When AD12B = 1, CHxNB is: U-0, Unimplemented, Read as ‘0’

11= CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11

10= CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8⁽¹⁾

0x= CH1, CH2, CH3 negative input is VREF-

bit 8

CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit

When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’

1= CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5

0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2

bit 7-3

bit 2-1

Unimplemented: Read as ‘0’

CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits

When AD12B = 1, CHxNA is: U-0, Unimplemented, Read as ‘0’

11= CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11

10= CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8⁽¹⁾

0x= CH1, CH2, CH3 negative input is VREF-

bit 0

CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit

When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’

1= CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5

0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2

Note 1: This bit setting is Reserved in PIC24HJ128GPX02, PIC24HJ64GPX02 and PIC24HJ32GPX02 (28-pin)

devices.

DS70293F-page 230

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 20-6: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER

R/W-0

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

CH0NB

CH0SB<4:0>

bit 15

R/W-0

U-0

—

U-0

—

R/W-0

CH0NA

CH0SA<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

CH0NB: Channel 0 Negative Input Select for Sample B bit

Same definition as bit 7.

bit 14-13

bit 12-8

Unimplemented: Read as ‘0’

CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits

01100= Channel 0 positive input is AN12

01011= Channel 0 positive input is AN11

•

01000= Channel 0 positive input is AN8⁽¹⁾

00111= Channel 0 positive input is AN7⁽¹⁾

00110= Channel 0 positive input is AN6⁽¹⁾

•

00010= Channel 0 positive input is AN2

00001= Channel 0 positive input is AN1

00000= Channel 0 positive input is AN0

bit 7

CH0NA: Channel 0 Negative Input Select for Sample A bit

1= Channel 0 negative input is AN1

0= Channel 0 negative input is VREF-

bit 6-5

bit 4-0

Unimplemented: Read as ‘0’

CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits

01100= Channel 0 positive input is AN12

01011= Channel 0 positive input is AN11

•

01000= Channel 0 positive input is AN8⁽¹⁾

00111= Channel 0 positive input is AN7⁽¹⁾

00110= Channel 0 positive input is AN6⁽¹⁾

•

00010= Channel 0 positive input is AN2

00001= Channel 0 positive input is AN1

00000= Channel 0 positive input is AN0

Note 1: These bit settings (AN6, AN7 and AN8) are reserved on PIC24HJ128GPX02, PIC24HJ64GPX02 and

PIC24HJ32GPX02 (28-pin) devices.

DS70293F-page 231

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(1,2)

REGISTER 20-7: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW

U-0

—

U-0

—

U-0

—

R/W-0

CSS9

R/W-0

CSS8

CSS12

CSS11

CSS10

bit 15

bit 8

R/W-0

CSS7

R/W-0

CSS6

R/W-0

CSS5

R/W-0

CSS4

R/W-0

CSS3

R/W-0

CSS2

R/W-0

CSS1

R/W-0

CSS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-0

Unimplemented: Read as ‘0’

CSS<12:0>: ADC Input Scan Selection bits

1= Select ANx for input scan

0= Skip ANx for input scan

Note 1: On devices without 13 analog inputs, all AD1CSSL bits can be selected by user application. However,

inputs selected for scan without a corresponding input on device converts VREF-.

2: CSSx = ANx, where x = 0 through 12.

(1,2,3)

REGISTER 20-8: AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW

U-0

—

U-0

—

U-0

—

R/W-0

PCFG12

PCFG11

PCFG10

PCFG9

PCFG8

bit 15

bit 8

R/W-0

PCFG7

PCFG6

PCFG5

PCFG4

PCFG3

PCFG2

PCFG1

PCFG0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-0

Unimplemented: Read as ‘0’

PCFG<12:0>: ADC Port Configuration Control bits

1= Port pin in Digital mode, port read input enabled, ADC input multiplexor connected to AVSS

0= Port pin in Analog mode, port read input disabled, ADC samples pin voltage

Note 1: On devices without 13 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on

ports without a corresponding input on device.

2: PCFGx = ANx, where x = 0 through 12.

3: PCFGX bits have no effect if ADC module is disabled by setting ADXMD bit in the PMDX register. In this

case, all port pins multiplexed with ANX will be in Digital mode.

DS70293F-page 232

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

The Comparator module provides a set of dual input

21.0 COMPARATOR MODULE

comparators. The inputs to the comparator can be

configured to use any one of the four pin inputs

(C1IN+, C1IN-, C2IN+ and C2IN-) as well as the

Comparator Voltage Reference Input (CVREF).

Note 1: This data sheet summarizes the features

of the PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to “Section 34. Compara-

tor” (DS70212) of the “dsPIC33F/

PIC24H Family Reference Manual”,

which is available from the Microchip

website (www.microchip.com).

Note:

This peripheral contains output func-

tions that may need to be configured by

the peripheral pin select feature. For

more information, see Section 11.6

“Peripheral Pin Select”.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

FIGURE 21-1:

COMPARATOR I/O OPERATING MODES

C1NEG

C1EN

CMCON<6>

C1INV

C1IN+

C1IN-

VIN-

(1)

C1OUT

C1POS

C1

C1IN+

CVREF

VIN+

C1OUTEN

C2NEG

C2POS

CMCON<7>

C2EN

C2INV

C2IN+

C2IN-

VIN-

(1)

C2OUT

C2

C2IN+

CVREF

VIN+

C2OUTEN

Note 1: This peripheral’s outputs must be assigned to an available RPn pin before use. Refer to Section 11.6 “Peripheral

Pin Select” for more information.

DS70293F-page 233

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 21-1: CMCON: COMPARATOR CONTROL REGISTER

R/W-0

U-0

—

R/W-0

C2EN

R/W-0

C1EN

R/W-0

CMIDL

C2EVT

C1EVT

C2OUTEN⁽¹⁾C1OUTEN⁽²⁾

bit 15

bit 8

R-0

R/W-0

C2INV

R/W-0

C1INV

R/W-0

C2OUT

C1OUT

C2NEG

C2POS

C1NEG

C1POS

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

CMIDL: Stop in Idle Mode

1= When device enters Idle mode, module does not generate interrupts. Module is still enabled

0= Continue normal module operation in Idle mode

bit 14

bit 13

Unimplemented: Read as ‘0’

C2EVT: Comparator 2 Event

1= Comparator output changed states

0= Comparator output did not change states

bit 12

bit 11

bit 10

bit 9

C1EVT: Comparator 1 Event

1= Comparator output changed states

0= Comparator output did not change states

C2EN: Comparator 2 Enable

1= Comparator is enabled

0= Comparator is disabled

C1EN: Comparator 1 Enable

1= Comparator is enabled

0= Comparator is disabled

C2OUTEN: Comparator 2 Output Enable⁽¹⁾

1= Comparator output is driven on the output pad

0= Comparator output is not driven on the output pad

bit 8

C1OUTEN: Comparator 1 Output Enable⁽²⁾

1= Comparator output is driven on the output pad

0= Comparator output is not driven on the output pad

bit 7

C2OUT: Comparator 2 Output bit

When C2INV = 0:

1= C2 VIN+ > C2 VIN-

0= C2 VIN+ < C2 VIN-

When C2INV = 1:

0= C2 VIN+ > C2 VIN-

1= C2 VIN+ < C2 VIN-

Note 1: If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPx pin. See

Section 11.6 “Peripheral Pin Select” for more information.

2: If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPx pin. See

Section 11.6 “Peripheral Pin Select” for more information.

DS70293F-page 234

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 21-1: CMCON: COMPARATOR CONTROL REGISTER (CONTINUED)

bit 6

C1OUT: Comparator 1 Output bit

When C1INV = 0:

1= C1 VIN+ > C1 VIN-

0= C1 VIN+ < C1 VIN-

When C1INV = 1:

0= C1 VIN+ > C1 VIN-

1= C1 VIN+ < C1 VIN-

bit 5

bit 4

bit 3

C2INV: Comparator 2 Output Inversion bit

1= C2 output inverted

0= C2 output not inverted

C1INV: Comparator 1 Output Inversion bit

1= C1 output inverted

0= C1 output not inverted

C2NEG: Comparator 2 Negative Input Configure bit

1= Input is connected to VIN+

0= Input is connected to VIN-

See Figure 21-1 for the comparator modes.

bit 2

bit 1

bit 0

C2POS: Comparator 2 Positive Input Configure bit

1= Input is connected to VIN+

0= Input is connected to CVREF

See Figure 21-1 for the comparator modes.

C1NEG: Comparator 1 Negative Input Configure bit

1= Input is connected to VIN+

0= Input is connected to VIN-

See Figure 21-1 for the comparator modes.

C1POS: Comparator 1 Positive Input Configure bit

1= Input is connected to VIN+

0= Input is connected to CVREF

See Figure 21-1 for the comparator modes.

Note 1: If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPx pin. See

Section 11.6 “Peripheral Pin Select” for more information.

2: If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPx pin. See

Section 11.6 “Peripheral Pin Select” for more information.

DS70293F-page 235

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

The comparator reference supply voltage can come

from either VDD and VSS, or the external VREF+ and

21.1 Comparator Voltage Reference

VREF-. The voltage source is selected by the CVRSS

bit (CVRCON<4>).

21.1.1

CONFIGURING THE COMPARATOR

VOLTAGE REFERENCE

The settling time of the comparator voltage reference

must be considered when changing the CVREF

output.

The Voltage Reference module is controlled through

the CVRCON register (Register 21-2). The comparator

voltage reference provides two ranges of output

voltage, each with 16 distinct levels. The range to be

used is selected by the CVRR bit (CVRCON<5>). The

primary difference between the ranges is the size of the

steps selected by the CVREF Selection bits

(CVR3:CVR0), with one range offering finer resolution.

FIGURE 21-2:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

CVRSS = 1

CVRSS = 0

CVRSRC

8R

VREF+

AVDD

CVRCON<3:0>

R

CVREFIN

CVREN

R

16 Steps

CVREF

R

CVROE (CVRCON<6>)

CVRR

VREF-

8R

CVRSS = 1

CVRSS = 0

AVSS

DS70293F-page 236

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 21-2: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

CVRR

R/W-0

bit 0

CVREN

CVROE

CVRSS

CVR<3:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

CVREN: Comparator Voltage Reference Enable bit

1= CVREF circuit powered on

0= CVREF circuit powered down

bit 6

CVROE: Comparator VREF Output Enable bit

1= CVREF voltage level is output on CVREF pin

0= CVREF voltage level is disconnected from CVREF pin

bit 5

CVRR: Comparator VREF Range Selection bit

1= CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size

0= CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size

bit 4

CVRSS: Comparator VREF Source Selection bit

1= Comparator reference source CVRSRC = VREF+ – VREF-

0= Comparator reference source CVRSRC = AVDD – AVSS

bit 3-0

CVR<3:0>: Comparator VREF Value Selection 0 ≤ CVR<3:0> ≤ 15 bits

When CVRR = 1:

CVREF = (CVR<3:0>/ 24) • (CVRSRC)

When CVRR = 0:

CVREF = 1/4 • (CVRSRC) + (CVR<3:0>/32) • (CVRSRC)

DS70293F-page 237

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

NOTES:

DS70293F-page 238

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

• Time: hours, minutes and seconds

22.0 REAL-TIME CLOCK AND

• 24-hour format (military time)

CALENDAR (RTCC)

• Calendar: weekday, date, month and year

• Alarm configurable

Note 1: This data sheet summarizes the features

of

the

PIC24HJ32GP302/304,

and

PIC24HJ64GPX02/X04

• Year range: 2000 to 2099

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to Section 37. “Real-Time Clock

and Calendar (RTCC)” (DS70301) of

the “dsPIC33F/PIC24H Family Refer-

ence Manual”, which is available from the

Microchip website (www.microchip.com).

• Leap year correction

• BCD format for compact firmware

• Optimized for low-power operation

• User calibration with auto-adjust

• Calibration range: ±2.64 seconds error per month

• Requirements: External 32.768 kHz clock crystal

• Alarm pulse or seconds clock output on RTCC pin

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

The RTCC module is intended for applications where

accurate time must be maintained for extended periods

of time with minimum to no intervention from the CPU.

The RTCC module is optimized for low-power usage to

provide extended battery lifetime while keeping track of

time.

This chapter discusses the Real-Time Clock and

The RTCC module is a 100-year clock and calendar

with automatic leap year detection. The range of the

clock is from 00:00:00 (midnight) on January 1, 2000 to

23:59:59 on December 31, 2099.

Calendar

(RTCC)

module,

available

on

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 devices, and its operation.

The following are some of the key features of this

module:

The hours are available in 24-hour (military time)

format. The clock provides a granularity of one second

with half-second visibility to the user.

FIGURE 22-1:

RTCC BLOCK DIAGRAM

CPU Clock Domain

RTCC Clock Domain

32.768 kHz Input

from SOSC Oscillator

RCFGCAL

RTCC Prescalers

0.5s

ALCFGRPT

RTCVAL

RTCC Timer

Alarm

Event

Comparator

Compare Registers

with Masks

ALRMVAL

Repeat Counter

RTCC Interrupt

RTCC Interrupt Logic

Alarm Pulse

RTCC Pin

RTCOE

DS70293F-page 239

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

By writing the ALRMVALH byte, the Alarm Pointer

value, ALRMPTR<1:0> bits, decrement by one until

they reach ‘00’. Once they reach ‘00’, the ALRMMIN

and ALRMSEC value will be accessible through

22.1 RTCC Module Registers

The RTCC module registers are organized into three

categories:

ALRMVALH and ALRMVALL until the pointer value is

manually changed.

• RTCC Control Registers

• RTCC Value Registers

• Alarm Value Registers

TABLE 22-2: ALRMVAL REGISTER

MAPPING

22.1.1

REGISTER MAPPING

To limit the register interface, the RTCC Timer and

Alarm Time registers are accessed through

corresponding register pointers. The RTCC Value

register window (RTCVALH and RTCVALL) uses the

RTCPTR bits (RCFGCAL<9:8>) to select the desired

timer register pair (see Table 22-1).

Alarm Value Register Window

ALRMPTR

<1:0>

ALRMVAL<15:8> ALRMVAL<7:0>

00

01

10

11

ALRMMIN

ALRMWD

ALRMMNTH

—

ALRMSEC

ALRMHR

ALRMDAY

—

By writing the RTCVALH byte, the RTCC Pointer value,

RTCPTR<1:0> bits, decrement by one until they reach

‘00’. Once they reach ‘00’, the MINUTES and

SECONDS value will be accessible through RTCVALH

and RTCVALL until the pointer value is manually

changed.

Considering that the 16-bit core does not distinguish

between 8-bit and 16-bit read operations, the user must

be aware that when reading either the ALRMVALH or

ALRMVALL bytes will decrement the ALRMPTR<1:0>

value. The same applies to the RTCVALH or RTCVALL

bytes with the RTCPTR<1:0> being decremented.

TABLE 22-1: RTCVAL REGISTER MAPPING

RTCC Value Register Window

RTCPTR

Note:

This only applies to read operations and

not write operations.

<1:0>

RTCVAL<15:8> RTCVAL<7:0>

22.1.2

WRITE LOCK

00

01

10

11

MINUTES

WEEKDAY

MONTH

—

SECONDS

HOURS

DAY

In order to perform a write to any of the RTCC Timer

registers, the RTCWREN bit (RCFGCAL<13>) must be

set (refer to Example 22-1).

YEAR

Note:

To avoid accidental writes to the timer, it is

recommended that the RTCWREN bit

(RCFGCAL<13>) is kept clear at any

other time. For the RTCWREN bit to be

set, there is only 1 instruction cycle time

window allowed between the 55h/AA

sequence and the setting of RTCWREN;

therefore, it is recommended that code

follow the procedure in Example 22-1.

The Alarm Value register window (ALRMVALH and

ALRMVALL) uses the ALRMPTR bits

(ALCFGRPT<9:8>) to select the desired Alarm register

pair (see Table 22-2).

EXAMPLE 22-1:

SETTING THE RTCWREN BIT

MOV

BSET

#NVMKEY, W1

;move the address of NVMKEY into W1

#0x55, W2

#0xAA, W3

W2, [W1]

W3, [W1]

RCFGCAL, #13

;start 55/AA sequence

;set the RTCWREN bit

DS70293F-page 240

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(1)

REGISTER 22-1:

RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER

R/W-0

RTCEN⁽²⁾

U-0

—

R/W-0

R-0

R/W-0

RTCWREN RTCSYNC HALFSEC⁽³⁾

RTCOE

RTCPTR<1:0>

bit 15

bit 8

R/W-0

bit 7

R/W-0

bit 0

CAL<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

RTCEN: RTCC Enable bit⁽²⁾

1= RTCC module is enabled

0= RTCC module is disabled

bit 14

bit 13

Unimplemented: Read as ‘0’

RTCWREN: RTCC Value Registers Write Enable bit

1= RTCVALH and RTCVALL registers can be written to by the user

0= RTCVALH and RTCVALL registers are locked out from being written to by the user

bit 12

RTCSYNC: RTCC Value Registers Read Synchronization bit

1= RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple

resulting in an invalid data read. If the register is read twice and results in the same data, the data

can be assumed to be valid

0= RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple

bit 11

bit 10

bit 9-8

HALFSEC: Half-Second Status bit⁽³⁾

1= Second half period of a second

0= First half period of a second

RTCOE: RTCC Output Enable bit

1= RTCC output enabled

0= RTCC output disabled

RTCPTR<1:0>: RTCC Value Register Window Pointer bits

Points to the corresponding RTCC Value registers when reading RTCVALH and RTCVALL registers;

the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.

RTCVAL<15:8>:

11= Reserved

10= MONTH

01= WEEKDAY

00= MINUTES

RTCVAL<7:0>:

11= YEAR

10= DAY

01= HOURS

00= SECONDS

Note 1: The RCFGCAL register is only affected by a POR.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.

3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.

DS70293F-page 241

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(1)

REGISTER 22-1:

bit 7-0

RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER (CONTINUED)

CAL<7:0>: RTC Drift Calibration bits

11111111= Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute

•

10000000= Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute

01111111= Maximum positive adjustment; adds 508 RTC clock pulses every one minute

•

00000001= Minimum positive adjustment; adds 4 RTC clock pulses every one minute

00000000= No adjustment

Note 1: The RCFGCAL register is only affected by a POR.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.

3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.

DS70293F-page 242

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 22-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

RTSECSEL⁽¹⁾

R/W-0

PMPTTL

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-2

bit 1

Unimplemented: Read as ‘0’

RTSECSEL: RTCC Seconds Clock Output Select bit⁽¹⁾

1= RTCC seconds clock is selected for the RTCC pin

0= RTCC alarm pulse is selected for the RTCC pin

bit 0

PMPTTL: PMP Module TTL Input Buffer Select bit

1= PMP module uses TTL input buffers

0= PMP module uses Schmitt Trigger input buffers

Note 1: To enable the actual RTCC output, the RTCOE bit (RCFGCAL<10>) needs to be set.

DS70293F-page 243

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 22-3: ALCFGRPT: ALARM CONFIGURATION REGISTER

R/W-0

ALRMEN

CHIME

AMASK<3:0>

ALRMPTR<1:0>

bit 15

R/W-0

bit 7

bit 8

R/W-0

bit 0

R/W-0

R/W-0 R/W-0

ARPT<7:0>

R/W-0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

ALRMEN: Alarm Enable bit

1= Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 0x00 and

CHIME = 0)

0= Alarm is disabled

bit 14

CHIME: Chime Enable bit

1= Chime is enabled; ARPT<7:0> bits are allowed to roll over from 0x00 to 0xFF

0= Chime is disabled; ARPT<7:0> bits stop once they reach 0x00

bit 13-10

AMASK<3:0>: Alarm Mask Configuration bits

11xx= Reserved – do not use

101x= Reserved – do not use

1001= Once a year (except when configured for February 29th, once every 4 years)

1000= Once a month

0111= Once a week

0110= Once a day

0101= Every hour

0100= Every 10 minutes

0011= Every minute

0010= Every 10 seconds

0001= Every second

0000= Every half second

bit 9-8

ALRMPTR<1:0>: Alarm Value Register Window Pointer bits

Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers;

the ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’.

ALRMVAL<15:8>:

11= Unimplemented

10= ALRMMNTH

01= ALRMWD

00= ALRMMIN

ALRMVAL<7:0>:

11= Unimplemented

10= ALRMDAY

01= ALRMHR

00= ALRMSEC

bit 7-0

ARPT<7:0>: Alarm Repeat Counter Value bits

11111111= Alarm will repeat 255 more times

•

00000000= Alarm will not repeat

The counter decrements on any alarm event. The counter is prevented from rolling over from 0x00 to

0xFF unless CHIME = 1.

DS70293F-page 244

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

(1)

REGISTER 22-4: RTCVAL (WHEN RTCPTR<1:0> = 11): YEAR VALUE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-x

bit 7

R/W-x

bit 0

YRTEN<3:0>

YRONE<3:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit; contains a value from 0 to 9

YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit; contains a value from 0 to 9

Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.

(1)

REGISTER 22-5: RTCVAL (WHEN RTCPTR<1:0> = 10): MONTH AND DAY VALUE REGISTER

U-0

—

U-0

—

U-0

—

R-x

MTHTEN0

MTHONE<3:0>

bit 15

bit 8

U-0

—

U-0

—

R/W-x

DAYTEN<1:0>

DAYONE<3:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12

Unimplemented: Read as ‘0’

MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; contains a value of 0 or 1

bit 11-8

bit 7-6

bit 5-4

bit 3-0

MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit; contains a value from 0 to 9

Unimplemented: Read as ‘0’

DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit; contains a value from 0 to 3

DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit; contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

DS70293F-page 245

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 22-6: RTCVAL (WHEN RTCPTR<1:0> = 01): WKDYHR: WEEKDAY AND HOURS VALUE

(1)

REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-x

bit 8

WDAY<2:0>

bit 15

U-0

—

U-0

—

R/W-x

bit 0

HRTEN<1:0>

HRONE<3:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

bit 7-6

Unimplemented: Read as ‘0’

WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit; contains a value from 0 to 6

Unimplemented: Read as ‘0’

bit 5-4

HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit; contains a value from 0 to 2

HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit; contains a value from 0 to 9

bit 3-0

Note 1: A write to this register is only allowed when RTCWREN = 1.

REGISTER 22-7: RTCVAL (WHEN RTCPTR<1:0> = 00): MINUTES AND SECONDS VALUE

REGISTER

U-0

—

R/W-x

bit 8

MINTEN<2:0>

MINONE<3:0>

bit 15

U-0

—

R/W-x

bit 0

SECTEN<2:0>

SECONE<3:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

bit 11-8

bit 7

MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit; contains a value from 0 to 5

MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit; contains a value from 0 to 9

Unimplemented: Read as ‘0’

bit 6-4

bit 3-0

SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit; contains a value from 0 to 5

SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit; contains a value from 0 to 9

DS70293F-page 246

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 22-8: ALRMVAL (WHEN ALRMPTR<1:0> = 10): ALARM MONTH AND DAY VALUE

(1)

REGISTER

U-0

—

U-0

—

U-0

—

R/W-x

bit 8

MTHTEN0

MTHONE<3:0>

bit 15

U-0

—

U-0

—

R/W-x

bit 0

DAYTEN<1:0>

DAYONE<3:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12

Unimplemented: Read as ‘0’

MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; contains a value of 0 or 1

bit 11-8

bit 7-6

bit 5-4

bit 3-0

MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit; contains a value from 0 to 9

Unimplemented: Read as ‘0’

DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit; contains a value from 0 to 3

DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit; contains a value from 0 to 9

Note 1: A write to this register is only allowed when RTCWREN = 1.

REGISTER 22-9: ALRMVAL (WHEN ALRMPTR<1:0> = 01): ALARM WEEKDAY AND HOURS

(1)

VALUE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-x

WDAY0

bit 8

WDAY2

WDAY1

bit 15

U-0

—

U-0

—

R/W-x

HRTEN<1:0>

HRONE<3:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

bit 7-6

Unimplemented: Read as ‘0’

WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit; contains a value from 0 to 6

Unimplemented: Read as ‘0’

bit 5-4

HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit; contains a value from 0 to 2

HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit; contains a value from 0 to 9

bit 3-0

Note 1: A write to this register is only allowed when RTCWREN = 1.

DS70293F-page 247

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 22-10: ALRMVAL (WHEN ALRMPTR<1:0> = 00): ALARM MINUTES AND SECONDS

VALUE REGISTER

U-0

—

R/W-x

bit 8

MINTEN<2:0>

MINONE<3:0>

bit 15

U-0

—

R/W-x

bit 0

SECTEN<2:0>

SECONE<3:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit; contains a value from 0 to 5

bit 14-12

bit 11-8

bit 7

MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit; contains a value from 0 to 9

Unimplemented: Read as ‘0’

bit 6-4

bit 3-0

SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit; contains a value from 0 to 5

SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit; contains a value from 0 to 9

DS70293F-page 248

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

23.1 Overview

23.0 PROGRAMMABLE CYCLIC

REDUNDANCY CHECK (CRC)

GENERATOR

The module implements a software configurable CRC

generator. The terms of the polynomial and its length

can be programmed using the CRCXOR bits (X<15:1>)

and the CRCCON bits (PLEN<3:0>), respectively.

Note 1: This data sheet summarizes the features

of

the

PIC24HJ32GP302/304,

and

PIC24HJ64GPX02/X04

EQUATION 23-1: CRC EQUATION

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

16

12

5

x

+ x + x + 1

sheet,

refer

to

Section

36.

To program this polynomial into the CRC generator,

the CRC register bits should be set as shown in

Table 23-1.

“Programmable Cyclic Redundancy

Check (CRC)” (DS70298) of the

“dsPIC33F/PIC24H Family Reference

Manual”, which is available from the

Microchip website (www.microchip.com).

TABLE 23-1: EXAMPLE CRC SETUP

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Bit Name

Bit Value

PLEN<3:0>

X<15:1>

1111

000100000010000

For the value of X<15:1>, the 12th bit and the 5th bit are

set to ‘1’, as required by the CRC equation. The 0th bit

required by the CRC equation is always XORed. For a

16-bit polynomial, the 16th bit is also always assumed

to be XORed; therefore, the X<15:1> bits do not have

the 0th bit or the 16th bit.

The programmable CRC generator offers the following

features:

• User-programmable polynomial CRC equation

• Interrupt output

The topology of a standard CRC generator is shown in

Figure 23-2.

• Data FIFO

FIGURE 23-1:

CRC SHIFTER DETAILS

PLEN<3:0>

0

1

2

15

CRC Shift Register

Hold

X2

Hold

X1

X3

X15

0

XOR

OUT

IN

BIT 0

IN

BIT 1

IN

BIT 2

IN

BIT 15

DOUT

1

p_clk

CRC Read Bus

CRC Write Bus

DS70293F-page 249

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

16

12

5

FIGURE 23-2:

CRC GENERATOR RECONFIGURED FOR x + x + x + 1

XOR

D

Q

D

Q

D

Q

D

Q

D

Q

SDOx

BIT 0

BIT 4

BIT 5

BIT 12

BIT 15

p_clk

CRC Read Bus

CRC Write Bus

To empty words already written into a FIFO, the

CRCGO bit must be set to ‘1’ and the CRC shifter

allowed to run until the CRCMPT bit is set.

23.2 User Interface

23.2.1

DATA INTERFACE

Also, to get the correct CRC reading, it is necessary to

wait for the CRCMPT bit to go high before reading the

CRCWDAT register.

To start serial shifting, a ‘1’ must be written to the

CRCGO bit.

The module incorporates a FIFO that is 8 deep when

PLEN (PLEN<3:0>) > 7, and 16 deep, otherwise. The

data for which the CRC is to be calculated must first be

written into the FIFO. The smallest data element that

can be written into the FIFO is one byte. For example,

if PLEN = 5, then the size of the data is PLEN + 1 = 6.

The data must be written as follows:

If a word is written when the CRCFUL bit is set, the

VWORD Pointer will roll over to 0. The hardware will

then behave like the FIFO is empty. However, the

condition to generate an interrupt will not be met;

therefore, no interrupt will be generated (See

Section 23.2.2 “Interrupt Operation”).

At least one instruction cycle must pass after a write to

CRCWDAT before a read of the VWORD bits is done.

data[5:0] = crc_input[5:0]

data[7:6] = ‘bxx

Once data is written into the CRCWDAT MSb (as

defined by PLEN), the value of VWORD

(VWORD<4:0>) increments by one. The serial shifter

starts shifting data into the CRC engine when

CRCGO = 1 and VWORD > 0. When the MSb is

shifted out, VWORD decrements by one. The serial

shifter continues shifting until the VWORD reaches 0.

Therefore, for a given value of PLEN, it will take

(PLEN + 1) * VWORD number of clock cycles to

complete the CRC calculations.

23.2.2

INTERRUPT OPERATION

When the VWORD<4:0> bits make a transition from a

value of ‘1’ to ‘0’, an interrupt will be generated.

23.3 Operation in Power-Saving Modes

23.3.1

SLEEP MODE

If Sleep mode is entered while the module is operating,

the module will be suspended in its current state until

clock execution resumes.

When VWORD reaches 8 (or 16), the CRCFUL bit will

be set. When VWORD reaches 0, the CRCMPT bit will

be set.

23.3.2

IDLE MODE

To continue full module operation in Idle mode, the

CSIDL bit must be cleared prior to entry into the mode.

To continually feed data into the CRC engine, the

recommended mode of operation is to initially “prime”

the FIFO with a sufficient number of words so no

interrupt is generated before the next word can be

written. Once that is done, start the CRC by setting the

CRCGO bit to ‘1’. From that point onward, the

VWORD<4:0> bits should be polled. If they read less

than 8 or 16, another word can be written into the FIFO.

If CSIDL = 1, the module will behave the same way as

it does in Sleep mode; pending interrupt events will be

passed on, even though the module clocks are not

available.

DS70293F-page 250

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

23.4 Registers

The CRC module provides the following registers:

• CRC Control Register

• CRC XOR Polynomial Register

REGISTER 23-1: CRCCON: CRC CONTROL REGISTER

U-0

—

U-0

—

R/W-0

CSIDL

R-0

VWORD<4:0>

bit 15

bit 8

R-0

R-1

U-0

—

R/W-0

bit 0

CRCFUL

CRCMPT

CRCGO

PLEN<3:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-14

bit 13

Unimplemented: Read as ‘0’

CSIDL: CRC Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-8

bit 7

VWORD<4:0>: Pointer Value bits

Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<3:0> is

greater than 7, or 16 when PLEN<3:0> is less than or equal to 7.

CRCFUL: FIFO Full bit

1= FIFO is full

0= FIFO is not full

bit 6

CRCMPT: FIFO Empty Bit

1= FIFO is empty

0= FIFO is not empty

bit 5

bit 4

Unimplemented: Read as ‘0’

CRCGO: Start CRC bit

1= Start CRC serial shifter

0= Turn off CRC serial shifter after FIFO is empty

bit 3-0

PLEN<3:0>: Polynomial Length bits

Denotes the length of the polynomial to be generated minus 1.

DS70293F-page 251

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 23-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER

R/W-0

bit 8

X<15:8>

bit 15

R/W-0

bit 7

R/W-0

U-0

—

X<7:1>

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-1

bit 0

X<15:1>: XOR of Polynomial Term XⁿEnable bits

Unimplemented: Read as ‘0’

DS70293F-page 252

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

devices and microcontrollers. Because the interface

to parallel peripherals varies significantly, the PMP is

highly configurable.

24.0 PARALLEL MASTER PORT

(PMP)

Note 1: This data sheet summarizes the features

Key features of the PMP module include:

• Fully Multiplexed Address/Data Mode

of

the

PIC24HJ32GP302/304,

and

PIC24HJ64GPX02/X04

• Demultiplexed or Partially Multiplexed Address/

Data Mode:

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to Section 35. “Parallel Master

Port (PMP)” (DS70299) of the

“dsPIC33F/PIC24H Family Reference

Manual”, which is available from the

Microchip website (www.microchip.com).

- Up to 11 address lines with single Chip Select

- Up to 12 address lines without Chip Select

• Single Chip Select Line

• Programmable Strobe Options:

- Individual Read and Write Strobes or;

- Read/Write Strobe with Enable Strobe

• Address Auto-Increment/Auto-Decrement

• Programmable Address/Data Multiplexing

• Programmable Polarity on Control Signals

• Legacy Parallel Slave Port Support

• Enhanced Parallel Slave Support:

- Address Support

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

- 4-Byte Deep Auto-Incrementing Buffer

• Programmable Wait States

The Parallel Master Port (PMP) module is a parallel

8-bit I/O module, specifically designed to communi-

cate with a wide variety of parallel devices, such as

communication peripherals, LCDs, external memory

• Selectable Input Voltage Levels

FIGURE 24-1:

PMP MODULE OVERVIEW

Address Bus

Data Bus

PMA<0>

PMALL

Control Lines

PIC24H

Parallel Master Port

PMA<1>

PMALH

Up to 11-Bit Address

EEPROM

(1)

PMA<10:2>

PMA<14>

PMCS1

PMBE

PMRD

PMRD/PMWR

PMWR

PMENB

FIFO

Buffer

Microcontroller

LCD

PMD<7:0>

PMA<7:0>

PMA<10:8>

8-Bit Data

Note 1: 28-pin devices do not have PMA<10:2>.

DS70293F-page 253

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 24-1: PMCON: PARALLEL PORT CONTROL REGISTER

R/W-0

U-0

—

R/W-0

PSIDL

R/W-0

PMPEN

ADRMUX1 ADRMUX0

PTBEEN

PTWREN

PTRDEN

bit 15

bit 8

R/W-0

CSF1

R/W-0

CSF0

R/W-0⁽¹⁾

ALP

U-0

—

R/W-0⁽¹⁾

CS1P

R/W-0

BEP

R/W-0

WRSP

R/W-0

RDSP

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

PMPEN: Parallel Master Port Enable bit

1= PMP enabled

0= PMP disabled, no off-chip access performed

bit 14

bit 13

Unimplemented: Read as ‘0’

PSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-11

ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits⁽¹⁾

11= Reserved

10= All 16 bits of address are multiplexed on PMD<7:0> pins

01= Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 3 bits are multiplexed on

PMA<10:8>

00= Address and data appear on separate pins

bit 10

bit 9

PTBEEN: Byte Enable Port Enable bit (16-bit Master mode)

1= PMBE port enabled

0= PMBE port disabled

PTWREN: Write Enable Strobe Port Enable bit

1= PMWR/PMENB port enabled

0= PMWR/PMENB port disabled

bit 8

PTRDEN: Read/Write Strobe Port Enable bit

1= PMRD/PMWR port enabled

0= PMRD/PMWR port disabled

bit 7-6

CSF1:CSF0: Chip Select Function bits

11= Reserved

10= PMCS1 functions as chip select

0x= PMCS1 functions as address bit 14

bit 5

ALP: Address Latch Polarity bit⁽¹⁾

1= Active-high (PMALL and PMALH)

0= Active-low (PMALL and PMALH)

bit 4

bit 3

Unimplemented: Read as ‘0’

CS1P: Chip Select 1 Polarity bit⁽¹⁾

1= Active-high (PMCS1/PMCS1)

0= Active-low (PMCS1/PMCS1)

bit 2

BEP: Byte Enable Polarity bit

1= Byte enable active-high (PMBE)

0= Byte enable active-low (PMBE)

Note 1: These bits have no effect when their corresponding pins are used as address lines.

DS70293F-page 254

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 24-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)

bit 1

WRSP: Write Strobe Polarity bit

For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10):

1= Write strobe active-high (PMWR)

0= Write strobe active-low (PMWR)

For Master mode 1 (PMMODE<9:8> = 11):

1= Enable strobe active-high (PMENB)

0= Enable strobe active-low (PMENB)

bit 0

RDSP: Read Strobe Polarity bit

For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10):

1= Read strobe active-high (PMRD)

0= Read strobe active-low (PMRD)

For Master mode 1 (PMMODE<9:8> = 11):

1= Read/write strobe active-high (PMRD/PMWR)

0= Read/write strobe active-low (PMRD/PMWR)

Note 1: These bits have no effect when their corresponding pins are used as address lines.

DS70293F-page 255

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

Register 24-2:

PMMODE: PARALLEL PORT MODE REGISTER

R-0

BUSY

R/W-0

IRQM<1:0>

INCM<1:0>

MODE16

MODE<1:0>

bit 15

bit 8

R/W-0

WAITB<1:0>⁽¹⁾

WAITM<3:0>

WAITE<1:0>⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

BUSY: Busy bit (Master mode only)

1= Port is busy (not useful when the processor stall is active)

0= Port is not busy

bit 14-13

IRQM<1:0>: Interrupt Request Mode bits

11= Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)

or on a read or write operation when PMA<1:0> = 11(Addressable PSP mode only)

10= No interrupt generated, processor stall activated

01= Interrupt generated at the end of the read/write cycle

00= No interrupt generated

bit 12-11

INCM<1:0>: Increment Mode bits

11= PSP read and write buffers auto-increment (Legacy PSP mode only)

10= Decrement ADDR<10:0> by 1 every read/write cycle

01= Increment ADDR<10:0> by 1 every read/write cycle

00= No increment or decrement of address

bit 10

MODE16: 8/16-bit Mode bit

1= 16-bit mode: data register is 16 bits, a read or write to the data register invokes two 8-bit transfers

0= 8-bit mode: data register is 8 bits, a read or write to the data register invokes one 8-bit transfer

bit 9-8

MODE<1:0>: Parallel Port Mode Select bits

11=Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)

10=Master mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)

01=Enhanced PSP, control signals (PMRD, PMWR, PMCS1, PMD<7:0> and PMA<1:0>)

00=Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1 and PMD<7:0>)

bit 7-6

bit 5-2

WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits⁽¹⁾

11= Data wait of 4 TCY; multiplexed address phase of 4 TCY

10= Data wait of 3 TCY; multiplexed address phase of 3 TCY

01= Data wait of 2 TCY; multiplexed address phase of 2 TCY

00= Data wait of 1 TCY; multiplexed address phase of 1 TCY

WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits

1111= Wait of additional 15 TCY

•

0001= Wait of additional 1 TCY

0000= No additional wait cycles (operation forced into one TCY)

WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits⁽¹⁾

bit 1-0

11= Wait of 4 TCY

10= Wait of 3 TCY

01= Wait of 2 TCY

00= Wait of 1 TCY

Note 1: WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000.

DS70293F-page 256

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 24-3: PMADDR: PARALLEL PORT ADDRESS REGISTER

R/W-0

CS1

R/W-0

bit 8

ADDR15

ADDR<13:8>

bit 15

R/W-0

bit 7

R/W-0

bit 0

ADDR<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

ADDR15: Parallel Port Destination Address bits

CS1: Chip Select 1 bit

1= Chip select 1 is active

0= Chip select 1 is inactive

bit 13-0

ADDR13:ADDR0: Parallel Port Destination Address bits

REGISTER 24-4: PMAEN: PARALLEL PORT ENABLE REGISTER

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

PTEN<10:8>⁽¹⁾

R/W-0

bit 8

PTEN14

bit 15

R/W-0

bit 7

R/W-0

PTEN<7:2>⁽¹⁾

PTEN<1:0>

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

PTEN14: PMCS1 Strobe Enable bit

1= PMA14 functions as either PMA<14> bit or PMCS1

0= PMA14 pin functions as port I/O

bit 13-11

bit 10-2

Unimplemented: Read as ‘0’

PTEN<10:2>: PMP Address Port Enable bits⁽¹⁾

1= PMA<10:2> function as PMP address lines

0= PMA<10:2> function as port I/O

bit 1-0

PTEN<1:0>: PMALH/PMALL Strobe Enable bits

1= PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL

0= PMA1 and PMA0 pads functions as port I/O

Note 1: Devices with 28 pins do not have PMA<10:2>.

DS70293F-page 257

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 24-5: PMSTAT: PARALLEL PORT STATUS REGISTER

R-0

IBF

R/W-0, HS

IBOV

U-0

—

U-0

—

R-0

IB3F

IB2F

IB1F

IB0F

bit 15

bit 8

R-1

R/W-0, HS

OBUF

U-0

—

U-0

—

R-1

OBE

OB3E

OB2E

OB1E

OB0E

bit 0

bit 7

Legend:

HS = Hardware Set bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

IBF: Input Buffer Full Status bit

1= All writable input buffer registers are full

0= Some or all of the writable input buffer registers are empty

IBOV: Input Buffer Overflow Status bit

1= A write attempt to a full input byte register occurred (must be cleared in software)

0= No overflow occurred

bit 13-12

bit 11-8

Unimplemented: Read as ‘0’

IB3F:IB0F Input Buffer x Status Full bits

1= Input buffer contains data that has not been read (reading buffer will clear this bit)

0= Input buffer does not contain any unread data

bit 7

bit 6

OBE: Output Buffer Empty Status bit

1= All readable output buffer registers are empty

0= Some or all of the readable output buffer registers are full

OBUF: Output Buffer Underflow Status bits

1= A read occurred from an empty output byte register (must be cleared in software)

0= No underflow occurred

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

OB3E:OB0E Output Buffer x Status Empty bit

1= Output buffer is empty (writing data to the buffer will clear this bit)

0= Output buffer contains data that has not been transmitted

DS70293F-page 258

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

REGISTER 24-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

RTSECSEL⁽¹⁾

R/W-0

PMPTTL

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-2

bit 1

Unimplemented: Read as ‘0’

RTSECSEL: RTCC Seconds Clock Output Select bit⁽¹⁾

1= RTCC seconds clock is selected for the RTCC pin

0= RTCC alarm pulse is selected for the RTCC pin

bit 0

PMPTTL: PMP Module TTL Input Buffer Select bit

1= PMP module uses TTL input buffers

0= PMP module uses Schmitt Trigger input buffers

Note 1: To enable the actual RTCC output, the RTCOE bit (RCFGCAL<10>) needs to be set.

DS70293F-page 259

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

NOTES:

DS70293F-page 260

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

25.1 Configuration Bits

25.0 SPECIAL FEATURES

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 devices provide nonvola-

tile memory implementation for device configuration

bits. Refer to Section 25. “Device Configuration”

(DS70194), in the “dsPIC33F/PIC24H Family

Reference Manual” for more information on this

implementation.

Note 1: This data sheet summarizes the features

of

the

PIC24HJ32GP302/304,

and

PIC24HJ64GPX02/X04

PIC24HJ128GPX02/X04 families of

devices. It is not intended to be a compre-

hensive reference source. To comple-

ment the information in this data sheet,

refer to the “dsPIC33F/PIC24H Family

Reference Manual”. Please see the

Microchip web site (www.microchip.com)

for the latest dsPIC33F/PIC24H Family

Reference Manual sections.

The Configuration bits can be programmed (read as

‘0’), or left unprogrammed (read as ‘1’), to select

various device configurations. These bits are mapped

starting at program memory location 0xF80000.

The individual Configuration bit descriptions for the

Configuration registers are shown in Table 25-1.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note that address 0xF80000 is beyond the user program

memory space. It belongs to the configuration memory

space (0x800000-0xFFFFFF), which can only be

accessed using table reads and table writes.

The Device Configuration register map is shown in

Table 25-1.

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 devices include the

following features that are intended to maximize

application flexibility and reliability, and minimize cost

through elimination of external components:

• Flexible configuration

• Watchdog Timer (WDT)

• Code Protection and CodeGuard™ Security

• JTAG Boundary Scan Interface

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit Emulation

TABLE 25-1: DEVICE CONFIGURATION REGISTER MAP

Address

Name

Bit 7

RBS<1:0>

RSS<1:0>

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0xF80000 FBS

0xF80002 FSS⁽¹⁾

—

BSS<2:0>

SSS<2:0>

BWRP

SWRP

GWRP

—

0xF80004 FGS

—

GSS<1:0>

FNOSC<2:0>

0xF80006 FOSCSEL

0xF80008 FOSC

0xF8000A FWDT

0xF8000C FPOR

0xF8000E FICD

0xF80010 FUID0

0xF80012 FUID1

0xF80014 FUID2

0xF80016 FUID3

IESO

—

FCKSM<1:0>

FWDTEN WINDIS

Reserved⁽²⁾

IOL1WAY

—

OSCIOFNC POSCMD<1:0>

WDTPOST<3:0>

—

WDTPRE

ALTI2C

—

FPWRT<2:0>

Reserved⁽³⁾

JTAGEN

—

ICS<1:0>

User Unit ID Byte 0

User Unit ID Byte 1

User Unit ID Byte 2

User Unit ID Byte 3

Legend: — = unimplemented bit, read as ‘0’.

Note 1: This Configuration register is not available and reads as 0xFF on PIC24HJ32GP302/304 devices.

2: These bits are reserved and always read as ‘1’.

3: These bits are reserved for use by development tools and must be programmed as ‘1’.

DS70293F-page 261

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 25-2: PIC24H CONFIGURATION BITS DESCRIPTION

Bit Field

Register

RTSP Effect

Description

BWRP

FBS

Immediate

Boot Segment Program Flash Write Protection

1= Boot segment can be written

0= Boot segment is write-protected

BSS<2:0>

FBS

Immediate

Boot Segment Program Flash Code Protection Size

X11= No Boot program Flash segment

Boot space is 1K Instruction Words (except interrupt vectors)

110= Standard security; boot program Flash segment ends

at 0x0007FE

010= High security; boot program Flash segment ends at

0x0007FE

Boot space is 4K Instruction Words (except interrupt vectors)

101= Standard security; boot program Flash segment, ends

at 0x001FFE

001= High security; boot program Flash segment ends at

0x001FFE

Boot space is 8K Instruction Words (except interrupt vectors)

100= Standard security; boot program Flash segment ends

at 0x003FFE

000= High security; boot program Flash segment ends at

0x003FFE

RBS<1:0>⁽¹⁾

FBS

Immediate

Boot Segment RAM Code Protection Size

11= No Boot RAM defined

10= Boot RAM is 128 bytes

01= Boot RAM is 256 bytes

00= Boot RAM is 1024 bytes

SWRP⁽¹⁾

FSS⁽¹⁾

Immediate

Secure Segment Program Flash Write-Protect bit

1= Secure Segment can bet written

0= Secure Segment is write-protected

SSS<2:0>⁽¹⁾

Secure Segment Program Flash Code Protection Size

(Secure segment is not implemented on 32K devices)

X11= No Secure program flash segment

Secure space is 4K IW less BS

110= Standard security; secure program flash segment starts

at End of BS, ends at 0x001FFE

010= High security; secure program flash segment starts at

End of BS, ends at 0x001FFE

Secure space is 8K IW less BS

101= Standard security; secure program flash segment starts

at End of BS, ends at 0x003FFE

001= High security; secure program flash segment starts at

End of BS, ends at 0x003FFE

Secure space is 16K IW less BS

100= Standard security; secure program flash segment starts

at End of BS, ends at 007FFEh

000= High security; secure program flash segment starts at

End of BS, ends at 0x007FFE

Note 1: This Configuration register is not available on PIC24HJ32GP302/304 devices.

DS70293F-page 262

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 25-2: PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED)

Bit Field

Register

RTSP Effect

Description

RSS<1:0>⁽¹⁾

FSS⁽¹⁾

Immediate

Secure Segment RAM Code Protection

11= No Secure RAM defined

10= Secure RAM is 256 Bytes less BS RAM

01= Secure RAM is 2048 Bytes less BS RAM

00= Secure RAM is 4096 Bytes less BS RAM

GSS<1:0>

FGS

Immediate

General Segment Code-Protect bit

11= User program memory is not code-protected

10= Standard security

0x= High security

GWRP

IESO

FGS

Immediate

General Segment Write-Protect bit

1= User program memory is not write-protected

0= User program memory is write-protected

FOSCSEL

Two-speed Oscillator Start-up Enable bit

1= Start-up device with FRC, then automatically switch to the

user-selected oscillator source when ready

0= Start-up device with user-selected oscillator source

FNOSC<2:0>

FOSCSEL

If clock switch is Initial Oscillator Source Selection bits

enabled, RTSP 111= Internal Fast RC (FRC) oscillator with postscaler

effect is on any 110= Internal Fast RC (FRC) oscillator with divide-by-16

device Reset; 101= LPRC oscillator

otherwise,

Immediate

100= Secondary (LP) oscillator

011= Primary (XT, HS, EC) oscillator with PLL

010= Primary (XT, HS, EC) oscillator

001= Internal Fast RC (FRC) oscillator with PLL

000= FRC oscillator

FCKSM<1:0>

FOSC

Immediate

Clock Switching Mode bits

1x= Clock switching is disabled, Fail-Safe Clock Monitor is

disabled

01= Clock switching is enabled, Fail-Safe Clock Monitor is

disabled

00= Clock switching is enabled, Fail-Safe Clock Monitor is

enabled

IOL1WAY

OSCIOFNC

FOSC

Immediate

Peripheral pin select configuration

1= Allow only one reconfiguration

0= Allow multiple reconfigurations

OSC2 Pin Function bit (except in XT and HS modes)

1= OSC2 is clock output

0= OSC2 is general purpose digital I/O pin

POSCMD<1:0>

Primary Oscillator Mode Select bits

11= Primary oscillator disabled

10= HS Crystal Oscillator mode

01= XT Crystal Oscillator mode

00= EC (External Clock) mode

FWDTEN

FWDT

Immediate

Watchdog Timer Enable bit

1= Watchdog Timer always enabled (LPRC oscillator cannot

be disabled. Clearing the SWDTEN bit in the RCON register

has no effect.)

0= Watchdog Timer enabled/disabled by user software

(LPRC can be disabled by clearing the SWDTEN bit in the

RCON register)

WINDIS

FWDT

Immediate

Watchdog Timer Window Enable bit

1= Watchdog Timer in Non-Window mode

0= Watchdog Timer in Window mode

Note 1: This Configuration register is not available on PIC24HJ32GP302/304 devices.

DS70293F-page 263

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 25-2: PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED)

Bit Field

Register

RTSP Effect

Description

WDTPRE

FWDT

Immediate

Watchdog Timer Prescaler bit

1= 1:128

0= 1:32

WDTPOST<3:0>

FWDT

Immediate

Watchdog Timer Postscaler bits

1111= 1:32,768

1110= 1:16,384

•

0001= 1:2

0000= 1:1

FPWRT<2:0>

FPOR

Immediate

Power-on Reset Timer Value Select bits

111= PWRT = 128 ms

110= PWRT = 64 ms

101= PWRT = 32 ms

100= PWRT = 16 ms

011= PWRT = 8 ms

010= PWRT = 4 ms

001= PWRT = 2 ms

000= PWRT = Disabled

ALTI2C

FPOR

FICD

Immediate

Alternate I²C™ pins

1 = I²C mapped to SDA1/SCL1 pins

0 = I²C mapped to ASDA1/ASCL1 pins

JTAGEN

JTAG Enable bit

1= JTAG enabled

0= JTAG disabled

ICS<1:0>

FICD

Immediate

ICD Communication Channel Select bits

11= Communicate on PGEC1 and PGED1

10= Communicate on PGEC2 and PGED2

01= Communicate on PGEC3 and PGED3

00= Reserved, do not use

Note 1: This Configuration register is not available on PIC24HJ32GP302/304 devices.

DS70293F-page 264

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

25.2 On-Chip Voltage Regulator

25.3 Brown-out Reset (BOR)

All

of

the

PIC24HJ32GP302/304,

The Brown-out Reset (BOR) module is based on an

internal voltage reference circuit that monitors the

regulated supply voltage VCAP. The main purpose of

the BOR module is to generate a device Reset when a

brown-out condition occurs. Brown-out conditions are

generally caused by glitches on the AC mains (for

example, missing portions of the AC cycle waveform

due to bad power transmission lines, or voltage sags

due to excessive current draw when a large inductive

load is turned on).

PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04

devices power their core digital logic at a nominal 2.5V.

This can create a conflict for designs that are required

to operate at a higher typical voltage, such as 3.3V. To

simplify system design, all devices in the

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 family incorporate an on-chip

regulator that allows the device to run its core logic from

VDD.

The regulator provides power to the core from the other

VDD pins. When the regulator is enabled, a low-ESR

(less than 5 Ohms) capacitor (such as tantalum or

ceramic) must be connected to the VCAP pin

(Figure 25-1). This helps to maintain the stability of the

regulator. The recommended value for the filter capac-

itor is provided in Table 28-13 located in Section 28.1

“DC Characteristics”.

A BOR generates a Reset pulse, which resets the

device. The BOR selects the clock source, based on

the device Configuration bit values (FNOSC<2:0> and

POSCMD<1:0>).

If an oscillator mode is selected, the BOR activates the

Oscillator Start-up Timer (OST). The system clock is

held until OST expires. If the PLL is used, the clock is

held until the LOCK bit (OSCCON<5>) is ‘1’.

Note:

It is important for the low-ESR capacitor to

be placed as close as possible to the VCAP

pin.

Concurrently, the PWRT time-out (TPWRT) is applied

before the internal Reset is released. If TPWRT = 0and

a crystal oscillator is being used, then a nominal delay

of TFSCM = 100 is applied. The total delay in this case

is TFSCM.

On a POR, it takes approximately 20 μs for the on-chip

voltage regulator to generate an output voltage. During

this time, designated as TSTARTUP, code execution is

disabled. TSTARTUP is applied every time the device

resumes operation after any power-down.

The BOR Status bit (RCON<1>) is set to indicate that a

BOR has occurred. The BOR circuit continues to oper-

ate while in Sleep or Idle modes and resets the device

should VDD fall below the BOR threshold voltage.

FIGURE 25-1:

CONNECTIONS FOR THE

ON-CHIP VOLTAGE

REGULATOR

(1,2,3)

3.3V

PIC24H

VDD

VCAP

VSS

CEFC

10 µF

Tantalum

Note 1: These are typical operating voltages. Refer to

Table 28-13, located in Section 28.1 “DC

Characteristics” for the full operating ranges

of VDD and VCAP.

2: It is important for the low-ESR capacitor to be

placed as close as possible to the VCAP pin.

3: Typical VCAP pin voltage = 2.5V when VDD ≥

VDDMIN.

DS70293F-page 265

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

25.4.2

SLEEP AND IDLE MODES

25.4 Watchdog Timer (WDT)

If the WDT is enabled, it continues to run during Sleep or

Idle modes. When the WDT time-out occurs, the device

wakes the device and code execution continues from

where the PWRSAVinstruction was executed. The corre-

sponding SLEEP or IDLE bits (RCON<3,2>) needs to be

cleared in software after the device wakes up.

For PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 devices, the WDT is

driven by the LPRC oscillator. When the WDT is

enabled, the clock source is also enabled.

25.4.1

PRESCALER/POSTSCALER

The nominal WDT clock source from LPRC is 32 kHz.

This feeds a prescaler that can be configured for either

5-bit (divide-by-32) or 7-bit (divide-by-128) operation.

The prescaler is set by the WDTPRE Configuration bit.

With a 32 kHz input, the prescaler yields a nominal

WDT time-out period (TWDT) of 1 ms in 5-bit mode, or

4 ms in 7-bit mode.

25.4.3

ENABLING WDT

The WDT is enabled or disabled by the FWDTEN

Configuration bit in the FWDT Configuration register.

When the FWDTEN Configuration bit is set, the WDT is

always enabled.

The WDT can be optionally controlled in software

when the FWDTEN Configuration bit has been

programmed to ‘0’. The WDT is enabled in software

by setting the SWDTEN control bit (RCON<5>). The

SWDTEN control bit is cleared on any device Reset.

The software WDT option allows the user application

to enable the WDT for critical code segments and

disable the WDT during non-critical segments for

maximum power savings.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the WDTPOST<3:0>

Configuration bits (FWDT<3:0>), which allow the

selection of 16 settings, from 1:1 to 1:32,768. Using the

prescaler and postscaler, time-out periods ranging from

1 ms to 131 seconds can be achieved.

The WDT, prescaler and postscaler are reset:

• On any device Reset

Note:

If the WINDIS bit (FWDT<6>) is cleared,

the CLRWDTinstruction should be executed

by the application software only during the

last 1/4 of the WDT period. This CLRWDT

window can be determined by using a timer.

If a CLRWDTinstruction is executed before

this window, a WDT Reset occurs.

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSC bits) or by hardware

(i.e., Fail-Safe Clock Monitor)

• When a PWRSAVinstruction is executed

(i.e., Sleep or Idle mode is entered)

The WDT flag bit, WDTO (RCON<4>), is not automatically

cleared following a WDT time-out. To detect subsequent

WDT events, the flag must be cleared in software.

• When the device exits Sleep or Idle mode to

resume normal operation

• By a CLRWDTinstruction during normal execution

Note:

The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

FIGURE 25-2:

WDT BLOCK DIAGRAM

All Device Resets

Transition to New Clock Source

Exit Sleep or Idle Mode

PWRSAVInstruction

CLRWDTInstruction

Watchdog Timer

Sleep/Idle

WDTPRE

WDTPOST<3:0>

SWDTEN

FWDTEN

WDT

Wake-up

1

RS

Prescaler

(divide by N1)

Postscaler

WDT

Reset

LPRC Clock

(divide by N2)

0

WDT Window Select

WINDIS

CLRWDTInstruction

DS70293F-page 266

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

25.5 JTAG Interface

25.8 Code Protection and

CodeGuard™ Security

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 devices implement a

JTAG interface, which supports boundary scan device

testing, as well as in-circuit programming. Detailed

information on this interface is provided in future

revisions of the document.

The

PIC24HJ64GPX02/X04

and

PIC24HJ128GPX02/X04 devices offer advanced

implementation of CodeGuard Security that supports

BS, SS and GS while, the PIC24HJ32GP302/304

devices offer the intermediate level of CodeGuard

Security that supports only BS and GS. CodeGuard

Security enables multiple parties to securely share

resources (memory, interrupts and peripherals) on a

single chip. This feature helps protect individual

Intellectual Property in collaborative system designs.

Note:

Refer to Section 24. “Programming and

Diagnostics” (DS70246) of the

“dsPIC33F/PIC24H Family Reference

Manual” for further information on usage,

configuration and operation of the JTAG

interface.

When coupled with software encryption libraries,

CodeGuard Security can be used to securely update

Flash even when multiple IPs reside on the single chip.

The code protection features vary depending on the

actual PIC24H implemented. The following sections

provide an overview of these features.

25.6

In-Circuit Serial Programming

The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04

and PIC24HJ128GPX02/X04 devices can be serially

programmed while in the end application circuit. This is

done with two lines for clock and data and three other

lines for power, ground and the programming

sequence. Serial programming allows customers to

manufacture boards with unprogrammed devices and

then program the microcontroller just before shipping

the product. Serial programming also allows the most

Secure segment and RAM protection is implemented

on

the

PIC24HJ64GPX02/X04

devices.

and

The

PIC24HJ128GPX02/X04

PIC24HJ32GP302/304 devices do not support secure

segment and RAM protection.

Note:

Refer to Section 23. “CodeGuard™

Security” (DS70239) of the

recent firmware or

a custom firmware to be

programmed. Refer to the “dsPIC33F/PIC24H Flash

Programming Specification” (DS70152) for details

about In-Circuit Serial Programming (ICSP).

“dsPIC33F/PIC24H Family Reference

Manual” for further information on usage,

configuration

and

operation

of

Any of the three pairs of programming clock/data pins

can be used:

CodeGuard Security.

• PGEC1 and PGED1

• PGEC2 and PGED2

• PGEC3 and PGED3

25.7 In-Circuit Debugger

When MPLAB^®ICD 2 is selected as a debugger, the

in-circuit debugging functionality is enabled. This

function allows simple debugging functions when used

with MPLAB IDE. Debugging functionality is controlled

through the PGECx (Emulation/Debug Clock) and

PGEDx (Emulation/Debug Data) pin functions.

Any of the three pairs of debugging clock/data pins can

be used:

• PGEC1 and PGED1

• PGEC2 and PGED2

• PGEC3 and PGED3

To use the in-circuit debugger function of the device,

the design must implement ICSP connections to

MCLR, VDD, VSS, and the PGECx/PGEDx pin pair. In

addition, when the feature is enabled, some of the

resources are not available for general use. These

resources include the first 80 bytes of data RAM and

two I/O pins.

DS70293F-page 267

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

Most bit-oriented instructions (including simple

rotate/shift instructions) have two operands:

26.0 INSTRUCTION SET SUMMARY

Note:

This data sheet summarizes the

features of the PIC24HJ32GP302/304,

• The W register (with or without an address

modifier) or file register (specified by the value of

‘Ws’ or ‘f’)

PIC24HJ64GPX02/X04

PIC24HJ128GPX02/X04

and

of

families

• The bit in the W register or file register

(specified by a literal value or indirectly by the

contents of register ‘Wb’)

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to the “dsPIC33F/PIC24H

Family Reference Manual”. Please see

The literal instructions that involve data movement may

use some of the following operands:

the

Microchip

web

site

• A literal value to be loaded into a W register or file

register (specified by the value of ‘k’)

(www.microchip.com) for the latest

dsPIC33F/PIC24H Family Reference

Manual sections.

• The W register or file register where the literal

value is to be loaded (specified by ‘Wb’ or ‘f’)

The PIC24H instruction set is identical to the PIC24F,

and is a subset of the dsPIC30F/33F instruction set.

However, literal instructions that involve arithmetic or

logical operations use some of the following operands:

Most instructions are a single program memory word

(24 bits). Only three instructions require two program

memory locations.

• The first source operand which is a register ‘Wb’

without any address modifier

• The second source operand which is a literal

value

Each single-word instruction is a 24-bit word, divided

into an 8-bit opcode, which specifies the instruction

type and one or more operands, which further specify

the operation of the instruction.

• The destination of the result (only if not the same

as the first source operand) which is typically a

register ‘Wd’ with or without an address modifier

The instruction set is highly orthogonal and is grouped

into five basic categories:

The control instructions may use some of the following

operands:

• Word or byte-oriented operations

• Bit-oriented operations

• Literal operations

• A program memory address

• The mode of the table read and table write

instructions

• Control operations

All instructions are a single word, except for certain

double word instructions, which were made double

word instructions so that all the required information is

available in these 48 bits. In the second word, the

8 MSbs are ‘0’s. If this second word is executed as an

instruction (by itself), it will execute as a NOP.

Table 26-1 shows the general symbols used in

describing the instructions.

The PIC24H instruction set summary in Table 26-2 lists

all the instructions, along with the status flags affected

by each instruction.

Most single-word instructions are executed in a single

instruction cycle, unless a conditional test is true, or the

program counter is changed as a result of the

instruction. In these cases, the execution takes two

instruction cycles with the additional instruction cycle(s)

executed as a NOP. Notable exceptions are the BRA

(unconditional/computed branch), indirect CALL/GOTO,

all table reads and writes and RETURN/RETFIE

instructions, which are single-word instructions but take

two or three cycles. Certain instructions that involve skip-

ping over the subsequent instruction require either two

or three cycles if the skip is performed, depending on

whether the instruction being skipped is a single-word or

double word instruction. Moreover, double word moves

require two cycles. The double word instructions

execute in two instruction cycles.

Most word or byte-oriented W register instructions

(including barrel shift instructions) have three

operands:

• The first source operand which is typically a

register ‘Wb’ without any address modifier

• The second source operand which is typically a

register ‘Ws’ with or without an address modifier

• The destination of the result which is typically a

register ‘Wd’ with or without an address modifier

However, word or byte-oriented file register instructions

have two operands:

• The file register specified by the value ‘f’

• The destination, which could either be the file

register ‘f’ or the W0 register, which is denoted as

‘WREG’

Note:

For more details on the instruction set,

refer to the “16-bit MCU and DSC

Programmer’s

Reference

Manual”

(DS70157).

DS70293F-page 271

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 26-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field

Description

#text

(text)

[text]

{ }

Means literal defined by “text”

Means “content of text”

Means “the location addressed by text”

Optional field or operation

Register bit field

<n:m>

.b

Byte mode selection

.d

Double Word mode selection

Shadow register select

.S

.w

Word mode selection (default)

bit4

4-bit bit selection field (used in word addressed instructions) ∈ {0...15}

MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero

Absolute address, label or expression (resolved by the linker)

File register address ∈ {0x0000...0x1FFF}

1-bit unsigned literal ∈ {0,1}

C, DC, N, OV, Z

Expr

f

lit1

lit4

4-bit unsigned literal ∈ {0...15}

lit5

5-bit unsigned literal ∈ {0...31}

lit8

8-bit unsigned literal ∈ {0...255}

lit10

lit14

lit16

lit23

None

PC

10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode

14-bit unsigned literal ∈ {0...16384}

16-bit unsigned literal ∈ {0...65535}

23-bit unsigned literal ∈ {0...8388608}; LSB must be ‘0’

Field does not require an entry, may be blank

Program Counter

Slit10

Slit16

Slit6

Wb

10-bit signed literal ∈ {-512...511}

16-bit signed literal ∈ {-32768...32767}

6-bit signed literal ∈ {-16...16}

Base W register ∈ {W0..W15}

Wd

Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }

Wdo

Destination W register ∈

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }

Wm,Wn

Dividend, Divisor working register pair (direct addressing)

Wm*Wm

Multiplicand and Multiplier working register pair for Square instructions ∈

{W4 * W4,W5 * W5,W6 * W6,W7 * W7}

Wn

One of 16 working registers ∈ {W0..W15}

Wnd

Wns

WREG

Ws

One of 16 destination working registers ∈ {W0...W15}

One of 16 source working registers ∈ {W0...W15}

W0 (working register used in file register instructions)

Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }

Wso

Source W register ∈

{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

DS70293F-page 272

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 26-2: INSTRUCTION SET OVERVIEW

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

ADD

f = f + WREG

1

C,DC,N,OV,Z

N,Z

1

ADD

ADDC

AND

ASR

f

ADD

f,WREG

WREG = f + WREG

1

ADD

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

Wd = lit10 + Wd

1

ADD

Wd = Wb + Ws

1

ADD

Wd = Wb + lit5

1

2

3

4

ADDC

AND

f = f + WREG + (C)

f,WREG

WREG = f + WREG + (C)

Wd = lit10 + Wd + (C)

Wd = Wb + Ws + (C)

Wd = Wb + lit5 + (C)

f = f .AND. WREG

1

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

1

AND

f,WREG

WREG = f .AND. WREG

Wd = lit10 .AND. Wd

Wd = Wb .AND. Ws

Wd = Wb .AND. lit5

1

N,Z

AND

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

1

N,Z

AND

1

N,Z

AND

1

N,Z

ASR

f = Arithmetic Right Shift f

WREG = Arithmetic Right Shift f

Wd = Arithmetic Right Shift Ws

Wnd = Arithmetic Right Shift Wb by Wns

Wnd = Arithmetic Right Shift Wb by lit5

Bit Clear f

1

C,N,OV,Z

N,Z

ASR

f,WREG

1

ASR

Ws,Wd

1

ASR

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,#bit4

Ws,#bit4

C,Expr

1

ASR

1

N,Z

5

6

BCLR

BRA

BCLR

BRA

1

None

Bit Clear Ws

1

None

Branch if Carry

1 (2)

2

None

BRA

GE,Expr

GEU,Expr

GT,Expr

GTU,Expr

LE,Expr

LEU,Expr

LT,Expr

LTU,Expr

N,Expr

Branch if greater than or equal

Branch if unsigned greater than or equal

Branch if greater than

Branch if unsigned greater than

Branch if less than or equal

Branch if unsigned less than or equal

Branch if less than

None

BRA

None

BRA

None

BRA

None

BRA

None

BRA

None

BRA

None

BRA

Branch if unsigned less than

Branch if Negative

None

BRA

None

BRA

NC,Expr

NN,Expr

NZ,Expr

Expr

Branch if Not Carry

None

BRA

Branch if Not Negative

Branch if Not Zero

None

BRA

None

BRA

Branch Unconditionally

Branch if Zero

None

BRA

Z,Expr

1 (2)

2

None

BRA

Wn

Computed Branch

None

7

BSET

BSW

BSET

BSW.C

BSW.Z

BTG

f,#bit4

Ws,#bit4

Ws,Wb

Bit Set f

1

None

Bit Set Ws

1

None

8

Write C bit to Ws<Wb>

Write Z bit to Ws<Wb>

Bit Toggle f

1

None

Ws,Wb

1

None

9

BTG

f,#bit4

Ws,#bit4

f,#bit4

1

None

BTG

Bit Toggle Ws

1

None

10

BTSC

Bit Test f, Skip if Clear

1

None

(2 or 3)

BTSC

BTSS

Ws,#bit4

f,#bit4

Ws,#bit4

Bit Test Ws, Skip if Clear

Bit Test f, Skip if Set

1

None

(2 or 3)

11

BTSS

1

(2 or 3)

Bit Test Ws, Skip if Set

1

(2 or 3)

DS70293F-page 273

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 26-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

12

BTST

f,#bit4

Ws,#bit4

Ws,Wb

Bit Test f

1

2

1

2

1

Z

BTST.C

BTST.Z

BTST.C

BTST.Z

BTSTS

Bit Test Ws to C

Bit Test Ws to Z

C

Z

Bit Test Ws<Wb> to C

Bit Test Ws<Wb> to Z

Bit Test then Set f

C

Z

Ws,Wb

13

BTSTS

f,#bit4

Z

BTSTS.C Ws,#bit4

BTSTS.Z Ws,#bit4

Bit Test Ws to C, then Set

Bit Test Ws to Z, then Set

Call subroutine

C

Z

14

15

CALL

CLR

CALL

CLR

CLRWDT

COM

CP

lit23

Wn

None

Call indirect subroutine

f = 0x0000

None

f

None

WREG

Ws

WREG = 0x0000

None

Ws = 0x0000

None

16

17

CLRWDT

COM

Clear Watchdog Timer

f = f

WDTO,Sleep

N,Z

f

f,WREG

Ws,Wd

f

WREG = f

N,Z

Wd = Ws

N,Z

18

CP

Compare f with WREG

Compare Wb with lit5

Compare Wb with Ws (Wb – Ws)

Compare f with 0x0000

Compare Ws with 0x0000

Compare f with WREG, with Borrow

Compare Wb with lit5, with Borrow

C,DC,N,OV,Z

CP

Wb,#lit5

Wb,Ws

f

CP

19

20

CP0

CPB

CP0

CPB

Ws

f

Wb,#lit5

Wb,Ws

Compare Wb with Ws, with Borrow

(Wb – Ws – C)

21

22

23

24

CPSEQ

CPSGT

CPSLT

CPSNE

CPSEQ

CPSGT

CPSLT

CPSNE

Wb, Wn

Compare Wb with Wn, skip if =

Compare Wb with Wn, skip if >

Compare Wb with Wn, skip if <

Compare Wb with Wn, skip if ≠

1

None

(2 or 3)

1

(2 or 3)

1

(2 or 3)

1

(2 or 3)

25

26

DAW

DEC

DAW

Wn

Wn = decimal adjust Wn

f = f – 1

1

2

1

C

DEC

f

C,DC,N,OV,Z

None

DEC

f,WREG

Ws,Wd

f

WREG = f – 1

1

DEC

Wd = Ws – 1

1

27

DEC2

DISI

DIV.S

DIV.SD

DIV.U

DIV.UD

EXCH

FBCL

FF1L

FF1R

GOTO

f = f – 2

1

f,WREG

Ws,Wd

#lit14

Wm,Wn

Wns,Wnd

Ws,Wnd

Expr

WREG = f – 2

1

Wd = Ws – 2

1

28

29

DISI

DIV

Disable Interrupts for k instruction cycles

Signed 16/16-bit Integer Divide

Signed 32/16-bit Integer Divide

Unsigned 16/16-bit Integer Divide

Unsigned 32/16-bit Integer Divide

Swap Wns with Wnd

1

18

1

N,Z,C,OV

None

30

31

32

33

34

EXCH

FBCL

FF1L

FF1R

GOTO

Find Bit Change from Left (MSb) Side

Find First One from Left (MSb) Side

Find First One from Right (LSb) Side

Go to address

1

C

1

C

1

C

2

None

Wn

Go to indirect

2

None

DS70293F-page 274

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 26-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

35

INC

f

f = f + 1

1

2

1

C,DC,N,OV,Z

N,Z

INC

f,WREG

Ws,Wd

WREG = f + 1

Wd = Ws + 1

f = f + 2

INC

36

37

INC2

IOR

INC2

IOR

f

f,WREG

Ws,Wd

WREG = f + 2

Wd = Ws + 2

f

f = f .IOR. WREG

IOR

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

#lit14

f

WREG = f .IOR. WREG

Wd = lit10 .IOR. Wd

N,Z

IOR

N,Z

IOR

Wd = Wb .IOR. Ws

N,Z

IOR

Wd = Wb .IOR. lit5

N,Z

38

39

LNK

LSR

LNK

Link Frame Pointer

None

LSR

f = Logical Right Shift f

C,N,OV,Z

N,Z

LSR

f,WREG

Ws,Wd

WREG = Logical Right Shift f

Wd = Logical Right Shift Ws

Wnd = Logical Right Shift Wb by Wns

Wnd = Logical Right Shift Wb by lit5

Move f to Wn

LSR

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,Wn

LSR

N,Z

40

MOV

None

MOV

f

Move f to f

None

MOV

f,WREG

#lit16,Wn

#lit8,Wn

Wn,f

Move f to WREG

N,Z

MOV

Move 16-bit literal to Wn

Move 8-bit literal to Wn

None

MOV.b

MOV

None

Move Wn to f

None

MOV

Wso,Wdo

WREG,f

Wns,Wd

Ws,Wnd

Wb,Ws,Wnd

Move Ws to Wd

None

MOV

Move WREG to f

None

MOV.D

MUL.SS

MUL.SU

MUL.US

MUL.UU

Move Double from W(ns):W(ns + 1) to Wd

Move Double from Ws to W(nd + 1):W(nd)

{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)

{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)

{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)

None

41

MUL

None

{Wnd + 1, Wnd} = unsigned(Wb) *

unsigned(Ws)

None

MUL.SU

MUL.UU

Wb,#lit5,Wnd

{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)

1

None

{Wnd + 1, Wnd} = unsigned(Wb) *

unsigned(lit5)

MUL

f

W3:W2 = f * WREG

f = f + 1

1

2

None

C,DC,N,OV,Z

None

42

NEG

f

NEG

f,WREG

Ws,Wd

WREG = f + 1

NEG

Wd = Ws + 1

43

44

NOP

POP

NOP

No Operation

NOPR

POP

No Operation

None

f

Pop f from Top-of-Stack (TOS)

Pop from Top-of-Stack (TOS) to Wdo

None

POP

Wdo

Wnd

None

POP.D

Pop from Top-of-Stack (TOS) to

W(nd):W(nd + 1)

None

POP.S

PUSH

Pop Shadow Registers

1

2

1

2

All

None

45

PUSH

f

Push f to Top-of-Stack (TOS)

Push Wso to Top-of-Stack (TOS)

Push W(ns):W(ns + 1) to Top-of-Stack (TOS)

Push Shadow Registers

Go into Sleep or Idle mode

Relative Call

PUSH

Wso

Wns

None

PUSH.D

PUSH.S

PWRSAV

RCALL

None

46

47

PWRSAV

RCALL

#lit1

Expr

Wn

WDTO,Sleep

None

Computed Call

None

DS70293F-page 275

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 26-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

48

REPEAT

RESET

RETFIE

RETLW

RETURN

RLC

#lit14

Wn

Repeat Next Instruction lit14 + 1 times

Repeat Next Instruction (Wn) + 1 times

Software device Reset

Return from interrupt

1

None

49

50

51

52

53

RESET

RETFIE

RETLW

RETURN

RLC

1

None

3 (2)

1

None

#lit10,Wn

Return with literal in Wn

Return from Subroutine

f = Rotate Left through Carry f

WREG = Rotate Left through Carry f

Wd = Rotate Left through Carry Ws

f = Rotate Left (No Carry) f

WREG = Rotate Left (No Carry) f

Wd = Rotate Left (No Carry) Ws

f = Rotate Right through Carry f

WREG = Rotate Right through Carry f

Wd = Rotate Right through Carry Ws

f = Rotate Right (No Carry) f

WREG = Rotate Right (No Carry) f

Wd = Rotate Right (No Carry) Ws

Wnd = sign-extended Ws

f = 0xFFFF

None

f

C,N,Z

RLC

f,WREG

Ws,Wd

f

1

C,N,Z

RLC

1

C,N,Z

54

55

56

RLNC

RRC

RLNC

RRC

1

N,Z

f,WREG

Ws,Wd

f

1

N,Z

1

N,Z

1

C,N,Z

RRC

f,WREG

Ws,Wd

f

1

C,N,Z

RRC

1

C,N,Z

RRNC

SE

1

N,Z

f,WREG

Ws,Wd

Ws,Wnd

f

1

N,Z

1

N,Z

57

58

SE

1

C,N,Z

SETM

SL

1

None

WREG

WREG = 0xFFFF

1

None

Ws

Ws = 0xFFFF

1

None

59

60

61

SL

f

f = Left Shift f

1

C,N,OV,Z

N,Z

SL

f,WREG

Ws,Wd

Wb,Wns,Wnd

Wb,#lit5,Wnd

f

WREG = Left Shift f

1

SL

Wd = Left Shift Ws

1

SL

Wnd = Left Shift Wb by Wns

Wnd = Left Shift Wb by lit5

f = f – WREG

1

SL

1

N,Z

SUB

SUBB

SUB

1

C,DC,N,OV,Z

None

SUB

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f – WREG

1

SUB

Wn = Wn – lit10

1

SUB

Wd = Wb – Ws

1

SUB

Wd = Wb – lit5

1

SUBB

SUBR

SUBBR

SWAP.b

SWAP

TBLRDH

TBLRDL

TBLWTH

TBLWTL

f = f – WREG – (C)

1

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f – WREG – (C)

Wn = Wn – lit10 – (C)

1

Wd = Wb – Ws – (C)

1

Wd = Wb – lit5 – (C)

1

62

63

SUBR

f = WREG – f

1

f,WREG

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = WREG – f

1

Wd = Ws – Wb

1

Wd = lit5 – Wb

1

SUBBR

f = WREG – f – (C)

1

f,WREG

Wb,Ws,Wd

Wb,#lit5,Wd

Wn

WREG = WREG – f – (C)

Wd = Ws – Wb – (C)

1

Wd = lit5 – Wb – (C)

1

64

SWAP

Wn = nibble swap Wn

Wn = byte swap Wn

1

Wn

1

None

65

66

67

68

TBLRDH

TBLRDL

TBLWTH

TBLWTL

Ws,Wd

Read Prog<23:16> to Wd<7:0>

Read Prog<15:0> to Wd

Write Ws<7:0> to Prog<23:16>

Write Ws to Prog<15:0>

2

None

2

None

2

None

2

None

DS70293F-page 276

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 26-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

69

ULNK

XOR

ULNK

XOR

ZE

Unlink Frame Pointer

1

None

N,Z

70

f

f = f .XOR. WREG

f,WREG

WREG = f .XOR. WREG

Wd = lit10 .XOR. Wd

Wd = Wb .XOR. Ws

Wd = Wb .XOR. lit5

Wnd = Zero-extend Ws

N,Z

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

Ws,Wnd

N,Z

71

ZE

C,Z,N

DS70293F-page 277

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

NOTES:

DS70293F-page 278

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

27.1 MPLAB Integrated Development

Environment Software

27.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers and dsPIC^®digital signal

controllers are supported with a full range of software

and hardware development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit

microcontroller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• A single graphical interface to all debugging tools

- Simulator

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Various Device

Families

- Programmer (sold separately)

- In-Circuit Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- HI-TECH C for Various Device Families

- MPASM^TMAssembler

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Customizable data windows with direct edit of

contents

• Simulators

• High-level source code debugging

• Mouse over variable inspection

- MPLAB SIM Software Simulator

• Emulators

• Drag and drop variables from source to watch

windows

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

• Extensive on-line help

• Integration of select third party tools, such as

IAR C Compilers

- MPLAB ICD 3

- PICkit™ 3 Debug Express

• Device Programmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)

• One-touch compile or assemble, and download to

emulator and simulator tools (automatically

updates all project information)

• Low-Cost Demonstration/Development Boards,

Evaluation Kits, and Starter Kits

• Debug using:

- Source files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

DS70293F-page 279

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

27.2 MPLAB C Compilers for Various

Device Families

27.5 MPLINK Object Linker/

MPLIB Object Librarian

The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the

dsPIC30 and dsPIC33 families of digital signal control-

lers. These compilers provide powerful integration

capabilities, superior code optimization and ease of

use.

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

27.3 HI-TECH C for Various Device

Families

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC

family of microcontrollers and the dsPIC family of digital

signal controllers. These compilers provide powerful

integration capabilities, omniscient code generation

and ease of use.

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

27.6 MPLAB Assembler, Linker and

Librarian for Various Device

Families

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The compilers include a macro assembler, linker, pre-

processor, and one-step driver, and can run on multiple

platforms.

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses

the assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

27.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• MPLAB IDE compatibility

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

source files

• Directives that allow complete control over the

assembly process

DS70293F-page 280

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

27.7 MPLAB SIM Software Simulator

27.9 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

MPLAB ICD 3 In-Circuit Debugger System is Micro-

chip's most cost effective high-speed hardware

debugger/programmer for Microchip Flash Digital Sig-

nal Controller (DSC) and microcontroller (MCU)

devices. It debugs and programs PIC^®Flash microcon-

trollers and dsPIC^®DSCs with the powerful, yet easy-

to-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-

nected to the design engineer's PC using a high-speed

USB 2.0 interface and is connected to the target with a

connector compatible with the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 supports all

MPLAB ICD 2 headers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

27.10 PICkit 3 In-Circuit Debugger/

Programmer and

27.8 MPLAB REAL ICE In-Circuit

Emulator System

PICkit 3 Debug Express

The MPLAB PICkit

programming of

3

allows debugging and

and Flash

dsPIC^®

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC^®Flash MCUs and dsPIC^®Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

PIC^®

microcontrollers at a most affordable price point using

the powerful graphical user interface of the MPLAB

Integrated Development Environment (IDE). The

MPLAB PICkit 3 is connected to the design engineer's

PC using a full speed USB interface and can be

connected to the target via an Microchip debug (RJ-11)

connector (compatible with MPLAB ICD 3 and MPLAB

REAL ICE). The connector uses two device I/O pins

and the reset line to implement in-circuit debugging and

In-Circuit Serial Programming™.

The emulator is connected to the design engineer’s PC

using a high-speed USB 2.0 interface and is connected

to the target with either a connector compatible with in-

circuit debugger systems (RJ11) or with the new high-

speed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnection (CAT5).

The PICkit 3 Debug Express include the PICkit 3, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

The emulator is field upgradable through future firmware

downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new

features will be added. MPLAB REAL ICE offers

significant advantages over competitive emulators

including low-cost, full-speed emulation, run-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

DS70293F-page 281

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

27.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

27.13 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

The PICkit™ 2 Development Programmer/Debugger is

a low-cost development tool with an easy to use

interface for programming and debugging Microchip’s

Flash families of microcontrollers. The full featured

Windows^®programming interface supports baseline

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

(PIC10F,

PIC12F5xx,

PIC16F5xx),

midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,

dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit

microcontrollers, and many Microchip Serial EEPROM

products. With Microchip’s powerful MPLAB Integrated

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

Development Environment (IDE) the PICkit™

2

enables in-circuit debugging on most PIC^®

microcontrollers. In-Circuit-Debugging runs, halts and

single steps the program while the PIC microcontroller

is embedded in the application. When halted at a

breakpoint, the file registers can be examined and

modified.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

The PICkit 2 Debug Express include the PICkit 2, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

27.12 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an MMC card for file

storage and data applications.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

DS70293F-page 282

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

28.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04

electrical characteristics. Additional information is provided in future revisions of this document as it becomes available.

Absolute maximum ratings for the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 family

are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Func-

tional operation of the device at these or any other conditions above the parameters indicated in the operation listings

of this specification is not implied.

Absolute Maximum Ratings⁽¹⁾

Ambient temperature under bias.............................................................................................................-40°C to +125°C

Storage temperature .............................................................................................................................. -65°C to +160°C

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V

Voltage on any pin that is not 5V tolerant with respect to VSS⁽⁴⁾.................................................... -0.3V to (VDD + 0.3V)

Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V⁽⁴⁾.................................................. -0.3V to +5.6V

Voltage on any 5V tolerant pin with respect to Vss when VDD < 3.0V⁽⁴⁾...................................................... -0.3V to 3.6V

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin⁽²⁾...........................................................................................................................250 mA

Maximum output current sunk by any I/O pin⁽³⁾........................................................................................................4 mA

Maximum output current sourced by any I/O pin⁽³⁾...................................................................................................4 mA

Maximum current sunk by all ports .......................................................................................................................200 mA

Maximum current sourced by all ports⁽²⁾...............................................................................................................200 mA

Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the

device. This is a stress rating only, and functional operation of the device at those or any other conditions

above those indicated in the operation listings of this specification is not implied. Exposure to maximum

rating conditions for extended periods can affect device reliability.

2: Maximum allowable current is a function of device maximum power dissipation (see Table 28-2).

3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGECx

and PGEDx pins, which are able to sink/source 12 mA.

4: See the “Pin Diagrams” section for 5V tolerant pins.

DS70293F-page 283

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

28.1 DC Characteristics

TABLE 28-1: OPERATING MIPS VS. VOLTAGE

Max MIPS

VDD Range

(in Volts)

Temp Range

(in °C)

PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04

Characteristic

3.0-3.6V

-40°C to +85°C

-40°C to +125°C

40

TABLE 28-2: THERMAL OPERATING CONDITIONS

Rating

Symbol

Min

Typ

Max

Unit

Industrial Temperature Devices

Operating Junction Temperature Range

Operating Ambient Temperature Range

Extended Temperature Devices

TJ

TA

-40

—

+125

+85

°C

Operating Junction Temperature Range

Operating Ambient Temperature Range

TJ

TA

-40

—

+155

+125

°C

Power Dissipation:

Internal chip power dissipation:

PINT = VDD x (IDD – Σ IOH)

PD

PINT + PI/O

W

I/O Pin Power Dissipation:

I/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL)

Maximum Allowed Power Dissipation

PDMAX

(TJ – TA)/θJA

TABLE 28-3: THERMAL PACKAGING CHARACTERISTICS

Characteristic

Symbol

Typ

Max

Unit

Notes

Package Thermal Resistance, 44-pin QFN

Package Thermal Resistance, 44-pin TFQP

Package Thermal Resistance, 28-pin SPDIP

Package Thermal Resistance, 28-pin SOIC

Package Thermal Resistance, 28-pin QFN-S

θJA

30

40

45

50

30

—

°C/W

1

Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.

DS70293F-page 284

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Min

Typ⁽¹⁾

Max Units

Conditions

Operating Voltage

DC10 Supply Voltage

VDD

3.0

1.8

—

3.6

—

V

Industrial and Extended

DC12

DC16

VDR

RAM Data Retention Voltage⁽²⁾

—

VPOR

VDD Start Voltage

to ensure internal

VSS

Power-on Reset signal

DC17

SVDD

VDD Rise Rate

0.03

—

V/ms 0-3.0V in 0.1s

to ensure internal

Power-on Reset signal

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: This is the limit to which VDD can be lowered without losing RAM data.

DS70293F-page 285

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Parameter

Typical⁽¹⁾

Max

Units

Conditions

No.

Operating Current (IDD)⁽²⁾

DC20d

DC20a

DC20b

DC20c

DC21d

DC21a

DC21b

DC21c

DC22d

DC22a

DC22b

DC22c

DC23d

DC23a

DC23b

DC23c

DC24d

DC24a

DC24b

DC24c

18

30

34

35

49

63

21

22

25

35

34

36

42

41

42

44

58

57

60

75

74

76

mA

-40°C

+25°C

+85°C

+125°C

-40°C

3.3V

10 MIPS

16 MIPS

20 MIPS

30 MIPS

40 MIPS

+25°C

+85°C

+125°C

-40°C

+25°C

+85°C

+125°C

-40°C

+25°C

+85°C

+125°C

-40°C

+25°C

+85°C

+125°C

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1

driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS.

MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are

operational. No peripheral modules are operating; however, every peripheral is being clocked (PMD bits

are all zeroed).

DS70293F-page 286

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Parameter

Typical⁽¹⁾

Max

Units

Conditions

No.

Idle Current (IIDLE): Core OFF Clock ON Base Current⁽²⁾

DC40d

DC40a

DC40b

DC40c

DC41d

DC41a

DC41b

DC41c

DC42d

DC42a

DC42b

DC42c

DC43a

DC43d

DC43b

DC43c

DC44d

DC44a

DC44b

DC44c

8

10

13

15

16

19

18

19

22

27

26

28

31

42

36

39

43

mA

-40°C

+25°C

+85°C

+125°C

-40°C

8

10 MIPS

16 MIPS

20 MIPS

30 MIPS

40 MIPS

3.3V

9

10

13

15

16

17

23

24

25

31

32

34

+25°C

+85°C

+125°C

-40°C

+25°C

+85°C

+125°C

+25°C

-40°C

3.3V

+85°C

+125°C

-40°C

+25°C

+85°C

+125°C

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.

2: Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral Module

Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS.

DS70293F-page 287

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Parameter

Typical⁽¹⁾

Max

Units

Conditions

No.

Power-Down Current (IPD)⁽²⁾

DC60d

DC60a

DC60b

DC60c

DC61d

DC61a

DC61b

DC61c

24

28

124

350

8

68

87

μA

-40°C

+25°C

+85°C

+125°C

-40°C

3.3V

Base Power-Down Current^(2,4)

292

1000

13

10

12

13

15

+25°C

+85°C

+125°C

(3)

Watchdog Timer Current: ΔIWDT

20

25

Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.

2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and

pulled to VSS. WDT, etc., are all switched off and VREGS (RCON<8>) = 1.

3: The Δ current is the additional current consumed when the module is enabled. This current should be

added to the base IPD current.

4: These currents are measured on the device containing the most memory in this family.

TABLE 28-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Doze

Ratio

Parameter No.

Typical⁽¹⁾

Max

Units

Conditions

DC73a

DC73f

DC73g

DC70a

DC70f

DC70g

DC71a

DC71f

DC71g

DC72a

DC72f

DC72g

20

17

20

17

20

17

21

18

50

30

50

30

50

30

50

30

1:2

1:64

1:128

1:2

mA

-40°C

+25°C

+85°C

3.3V

40 MIPS

1:64

1:128

1:2

1:64

1:128

1:2

1:64

1:128

+125°C 3.3V

Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.

DS70293F-page 288

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

VIL

Input Low Voltage

I/O pins

DI10

VSS

—

0.2 VDD

0.15 VDD

0.2 VDD

0.3 VDD

0.8

V

DI11

DI15

DI16

DI18

DI19

PMP pins

PMPTTL = 1

MCLR

I/O Pins with OSC1 or SOSCI

I/O Pins with SDAx, SCLx

Input High Voltage

SMbus disabled

SMbus enabled

VIH

DI20

DI21

I/O Pins Not 5V Tolerant⁽⁴⁾

0.7 VDD

—

VDD

5.5

VDD

V

—

I/O Pins 5V Tolerant⁽⁴⁾

I/O Pins Not 5V Tolerant with 0.24 VDD + 0.8

PMP⁽⁴⁾

I/O Pins 5V Tolerant with

PMP⁽⁴⁾

0.24 VDD + 0.8

—

5.5

V

DI28

DI29

SDAx, SCLx

0.7 VDD

2.1

—

5.5

V

SMbus disabled

SMbus enabled

SDAx, SCLx

ICNPU

CNx Pull-up Current

DI30

50

250

400

μA VDD = 3.3V, VPIN = VSS

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current can be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: See “Pin Diagrams” for the 5V tolerant I/O pins.

5: VIL source < (VSS – 0.3). Characterized but not tested.

6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not

tested.

7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.

8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.

9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-

vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not

exceed the specified limit. Characterized but not tested.

DS70293F-page 289

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

IIL

Input Leakage Current^(2,3)

DI50

I/O pins 5V Tolerant⁽⁴⁾

—

±2

±1

μA VSS ≤ VPIN ≤ VDD,

Pin at high-impedance

DI51

I/O Pins Not 5V Tolerant⁽⁴⁾

μA VSS ≤ VPIN ≤ VDD,

Pin at high-impedance,

40°C ≤ TA ≤ +85°C

DI51a

DI51b

DI51c

—

±2

±3.5

±8

μA Shared with external

reference pins,

40°C ≤ TA ≤ +85°C

μA VSS ≤ VPIN ≤ VDD, Pin

at high-impedance,

-40°C ≤ TA ≤ +125°C

μA Analog pins shared

with external reference

pins,

-40°C ≤ TA ≤ +125°C

—

DI55

DI56

MCLR

OSC1

—

±2

μA VSS ≤ VPIN ≤ VDD

μA VSS ≤ VPIN ≤ VDD,

XT and HS modes

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current can be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: See “Pin Diagrams” for the 5V tolerant I/O pins.

5: VIL source < (VSS – 0.3). Characterized but not tested.

6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not

tested.

7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.

8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.

9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-

vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not

exceed the specified limit. Characterized but not tested.

DS70293F-page 290

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

IICL

Input Low Injection Current

DI60a

All pins except VDD,

VSS, AVDD, AVSS,

MCLR, VCAP, SOSCI,

SOSCO, and RB14

0

—

-5^(5,8)

mA

IICH

Input High Injection Current

DI60b

DI60c

All pins except VDD,

VSS, AVDD, AVSS,

MCLR, VCAP, SOSCI,

SOSCO, RB14, and

digital 5V-tolerant

designated pins

0

—

+5^(6,7,8)

mA

∑IICT

Total Input Injection Current

(sum of all I/O and control

pins)

-20⁽⁹⁾

+20⁽⁹⁾

mA Absolute instantaneous

sum of all ± input

injection currents from

all I/O pins

( | IICL + | IICH | ) ≤ ∑IICT

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current can be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: See “Pin Diagrams” for the 5V tolerant I/O pins.

5: VIL source < (VSS – 0.3). Characterized but not tested.

6: Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not

tested.

7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.

8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.

9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-

vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not

exceed the specified limit. Characterized but not tested.

DS70293F-page 291

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Min

Typ

Max Units

Conditions

VOL

Output Low Voltage

I/O ports

DO10

DO16

—

0.4

V

IOL = 2 mA, VDD = 3.3V

OSC2/CLKO

VOH

Output High Voltage

I/O ports

DO20

DO26

2.40

2.41

—

V

IOH = -2.3 mA, VDD = 3.3V

IOH = -1.3 mA, VDD = 3.3V

OSC2/CLKO

TABLE 28-11: ELECTRICAL CHARACTERISTICS: BOR

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

DC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min⁽¹⁾Typ Max⁽¹⁾Units

2.40 2.55

Conditions

BO10

VBOR

BOR Event on VDD transition

high-to-low

—

V

VDD

Note 1: Parameters are for design guidance only and are not tested in manufacturing.

DS70293F-page 292

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-12: DC CHARACTERISTICS: PROGRAM MEMORY

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Min Typ⁽¹⁾

Max

Units

Conditions

Program Flash Memory

Cell Endurance

D130a EP

10,000

VMIN

—

E/W -40°C to +125°C

D131

VPR

VDD for Read

3.6

V

VMIN = Minimum operating

voltage

D132B VPEW

VDD for Self-Timed Write

Characteristic Retention

VMIN

20

—

10

—

3.6

—

V

VMIN = Minimum operating

voltage

D134

D135

TRETD

IDDP

Year Provided no other specifications

are violated

Supply Current during

Programming

—

mA

—

D136a TRW

D136b TRW

D137a TPE

D137b TPE

D138a TWW

D138b TWW

Row Write Time

1.32

1.28

20.1

19.5

42.3

41.1

1.74

1.79

26.5

27.3

55.9

57.6

ms TRW = 11064 FRC cycles,

TA = +85°C, See Note 2

Row Write Time

ms TRW = 11064 FRC cycles,

TA = +125°C, See Note 2

Page Erase Time

Word Write Cycle Time

ms TPE = 168517 FRC cycles,

TA = +85°C, See Note 2

ms TPE = 168517 FRC cycles,

TA = +125°C, See Note 2

µs TWW = 355 FRC cycles,

TA = +85°C, See Note 2

µs TWW = 355 FRC cycles,

TA = +125°C, See Note 2

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111(for Min), TUN<5:0> = b'100000(for Max).

This parameter depends on the FRC accuracy (see Table 28-19) and the value of the FRC Oscillator

Tuning register (see Register 9-4). For complete details on calculating the Minimum and Maximum time

see Section 5.3 “Programming Operations”.

TABLE 28-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated):

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristics

Min

Typ

Max

Units

Comments

—

CEFC

External Filter Capacitor

Value⁽¹⁾

4.7

10

—

μF

Capacitor must be low

series resistance

(< 5 Ohms)

Note 1: Typical VCAP voltage = 2.5V when VDD ≥ VDDMIN.

DS70293F-page 293

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

28.2 AC Characteristics and Timing

Parameters

This

section

defines

PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04

AC characteristics and timing parameters.

TABLE 28-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Operating voltage VDD range as described in Table 28-1.

FIGURE 28-1:

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 – for all pins except OSC2

VDD/2

Load Condition 2 – for OSC2

CL

RL

VSS

CL

RL = 464Ω

CL = 50 pF for all pins except OSC2

15 pF for OSC2 output

VSS

TABLE 28-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

Param

Symbol

Characteristic

Min

Typ

Max Units

Conditions

No.

DO50 COSC2

OSC2/SOSC2 pin

—

15

pF In XT and HS modes when

external clock is used to drive

OSC1

DO56 CIO

DO58 CB

All I/O pins and OSC2

SCLx, SDAx

—

50

pF EC mode

pF In I²C™ mode

400

DS70293F-page 294

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-2:

EXTERNAL CLOCK TIMING

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

OSC1

CLKO

OS20

OS30 OS30

OS31 OS31

OS25

OS41

OS40

TABLE 28-16: EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symb

No.

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

OS10

FIN

External CLKI Frequency

(External clocks allowed only

in EC and ECPLL modes)

DC

—

40

MHz EC

Oscillator Crystal Frequency

3.5

10

—

10

40

33

MHz XT

MHz HS

kHz SOSC

OS20

OS25

OS30

TOSC

TCY

TOSC = 1/FOSC

Instruction Cycle Time⁽²⁾

12.5

25

—

DC

ns

TosL, External Clock in (OSC1)

TosH High or Low Time

0.375 x TOSC

0.625 x TOSC

ns

EC

OS31

TosR, External Clock in (OSC1)

TosF Rise or Fall Time

—

20

ns

OS40

OS41

OS42

TckR CLKO Rise Time⁽³⁾

—

14

5.2

16

—

18

ns

—

TckF

GM

CLKO Fall Time⁽³⁾

External Oscillator

mA/V VDD = 3.3V

TA = +25ºC

Transconductance⁽⁴⁾

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

2: Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator

operation and/or higher than expected current consumption. All devices are tested to operate at “min.”

values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the

“max.” cycle time limit is “DC” (no clock) for all devices.

3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.

4: Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing.

DS70293F-page 295

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

No.

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

OS50

FPLLI

PLL Voltage Controlled

Oscillator (VCO) Input

Frequency Range

0.8

—

8

MHz ECPLL, HSPLL, XTPLL

modes

OS51

FSYS

On-Chip VCO System

Frequency

100

—

200

MHz

—

OS52

OS53

TLOCK

DCLK

PLL Start-up Time (Lock Time)

CLKO Stability (Jitter)

0.9

-3

1.5

0.5

3.1

3

mS

%

—

Measured over 100 ms

period

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is

based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases

or communication clocks use this formula:

DCLK

-----------------------------------------------------------------------

Peripheral Clock Jitter =

FOSC

⎛

⎝

⎞

-------------------------------------------------------------

⎠

Peripheral Bit Rate Clock

For example: Fosc = 32 MHz, DCLK = 3%, SPI bit rate clock, (i.e., SCK) is 2 MHz.

DCLK

3%

-------

-----------------------------

---------

SPI SCK Jitter =

=

= 0.75%

4

16

32 MHz

⎛

⎝

⎞

⎠

--------------------

2 MHz

TABLE 28-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

AC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Characteristic

Min

Typ

Max

Units

Conditions

Internal FRC Accuracy @ 7.3728 MHz⁽¹⁾

F20

FRC

-2

-5

—

+2

+5

%

-40°C ≤ TA ≤ +85°C

-40°C ≤ TA ≤ +125°C

VDD = 3.0-3.6V

Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift.

TABLE 28-19: INTERNAL RC ACCURACY

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Characteristic

Min

Typ

Max

Units

Conditions

LPRC @ 32.768 kHz⁽¹⁾

F21

LPRC

-20

-30

±6

—

+20

+30

%

-40°C ≤ TA ≤ +85°C

-40°C ≤ TA ≤ +125°C

VDD = 3.0-3.6V

Note 1: Change of LPRC frequency as VDD changes.

DS70293F-page 296

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-3:

CLKO AND I/O TIMING CHARACTERISTICS

I/O Pin

(Input)

DI35

DI40

I/O Pin

(Output)

New Value

Old Value

DO31

DO32

Note: Refer to Figure 28-1 for load conditions.

TABLE 28-20: I/O TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

DO31

DO32

DI35

TIOR

TIOF

TINP

TRBP

Port Output Rise Time

—

20

2

10

—

25

—

ns

—

Port Output Fall Time

INTx Pin High or Low Time (input)

CNx High or Low Time (input)

ns

DI40

TCY

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

DS70293F-page 297

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-4:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING CHARACTERISTICS

VDD

SY12

MCLR

SY10

Internal

POR

SY11

PWRT

Time-out

SY30

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

SY20

SY13

I/O Pins

SY35

FSCM

Delay

Note: Refer to Figure 28-1 for load conditions.

DS70293F-page 298

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max Units

Conditions

SY10

SY11

TMCL

MCLR Pulse Width (low)

Power-up Timer Period

2

—

μs

-40°C to +85°C

TPWRT

—

2

4

ms

-40°C to +85°C

User programmable

8

16

32

64

128

SY12

SY13

TPOR

TIOZ

Power-on Reset Delay

3

10

30

μs

-40°C to +85°C

—

I/O High-Impedance from

MCLR Low or Watchdog

Timer Reset

0.68

0.72

1.2

SY20

TWDT1

Watchdog Timer

Time-out Period

—

See Section 25.4

“Watchdog Timer (WDT)”

and LPRC specification F21

(Table 28-19)

SY30

SY35

TOST

Oscillator Start-up Timer

Period

—

1024 TOSC

500

—

TOSC = OSC1 period

TFSCM

Fail-Safe Clock Monitor

Delay

900

μs

-40°C to +85°C

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

DS70293F-page 299

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-5:

TIMER1, 2, 3 AND 4 EXTERNAL CLOCK TIMING CHARACTERISTICS

TxCK

Tx11

Tx10

Tx15

Tx20

OS60

TMRx

Note: Refer to Figure 28-1 for load conditions.

(1)

TABLE 28-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Typ

Max

Units

Conditions

TA10

TA11

TA15

TTXH

TTXL

TTXP

TxCK High Time Synchronous,

no prescaler

TCY + 20

—

ns

Must also meet

parameterTA15.

N = prescale

value

Synchronous, (TCY + 20)/N

with prescaler

—

ns

(1, 8, 64, 256)

Asynchronous

20

—

ns

TxCK Low Time Synchronous,

no prescaler

(TCY + 20)

Must also meet

parameterTA15.

N = prescale

value

Synchronous, (TCY + 20)/N

with prescaler

—

ns

(1, 8, 64, 256)

Asynchronous

20

—

ns

TxCK Input Period Synchronous,

no prescaler

2 TCY + 40

—

Synchronous,

with prescaler

Greater of:

40 ns or

(2 TCY + 40)/

N

—

N = prescale

value

(1, 8, 64, 256)

Asynchronous

40

—

ns

—

OS60 Ft1

SOSCI/T1CK Oscillator Input

frequency Range (oscillator

enabled by setting bit TCS

(T1CON<1>))

DC

50

kHz

TA20

TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment

0.75 TCY +

40

1.75 TCY +

40

—

Note 1: Timer1 is a Type A.

DS70293F-page 300

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-23: TIMER2 AND TIMER 4 EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic⁽¹⁾

Synchronous

Min

Typ

Max

Units

Conditions

Greater of:

20 or

(TCY + 20)/N

—

ns

TB10 TtxH

TB11 TtxL

TB15 TtxP

TxCKHigh

Must also meet

parameter TB15

N = prescale

value

mode

Time

(1, 8, 64, 256)

TxCK Low Synchronous

Greater of:

20 or

(TCY + 20)/N

—

ns

Must also meet

parameter TB15

N = prescale

value

Time

mode

(1, 8, 64, 256)

TxCK

Input

Synchronous

mode

Greater of:

40 or

(2 TCY + 40)/N

—

ns

N = prescale

value

(1, 8, 64, 256)

Period

TB20 TCKEXTMRL Delay from External TxCK 0.75 TCY + 40

1.75 TCY + 40

Clock Edge to Timer Incre-

ment

Note 1: These parameters are characterized, but are not tested in manufacturing.

TABLE 28-24: TIMER3 AND TIMER5 EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

No.

Symbol

TtxH

Characteristic⁽¹⁾

Min

Typ

Max

Units

Conditions

TC10

TC11

TC15

TxCK High Synchronous

Time

TCY + 20

—

ns

Must also meet

parameter TC15

TtxL

TtxP

TxCK Low Synchronous

Time

TCY + 20

—

ns

Must also meet

parameter TC15

TxCK Input Synchronous,

2 TCY + 40

N = prescale

value

Period

with prescaler

(1, 8, 64, 256)

TC20

TCKEXTMRL Delay from External TxCK

Clock Edge to Timer Incre-

ment

0.75 TCY + 40

—

1.75 TCY + 40

ns

Note 1: These parameters are characterized, but are not tested in manufacturing.

DS70293F-page 301

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-6:

INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS

ICx

IC10

IC11

IC15

Note: Refer to Figure 28-1 for load conditions.

TABLE 28-25: INPUT CAPTURE TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Max

Units

Conditions

IC10

IC11

IC15

TccL

TccH

TccP

ICx Input Low Time No Prescaler

With Prescaler

0.5 TCY + 20

10

—

ns

—

ICx Input High Time No Prescaler

With Prescaler

0.5 TCY + 20

10

—

ICx Input Period

(TCY + 40)/N

N = prescale

value (1, 4, 16)

Note 1: These parameters are characterized but not tested in manufacturing.

FIGURE 28-7:

OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS

OCx

(Output Compare

or PWM Mode)

OC10

OC11

Note: Refer to Figure 28-1 for load conditions.

TABLE 28-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ

Max

Units

Conditions

OC10 TccF

OC11 TccR

OCx Output Fall Time

OCx Output Rise Time

—

ns

See parameter DO32

See parameter DO31

Note 1: These parameters are characterized but not tested in manufacturing.

DS70293F-page 302

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-8:

OC/PWM MODULE TIMING CHARACTERISTICS

OC20

OCFA

OCx

OC15

Tri-state

Active

TABLE 28-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ

Max

Units

Conditions

OC15

TFD

Fault Input to PWM I/O

Change

—

TCY + 20

ns

—

OC20

TFLT

Fault Input Pulse Width

TCY + 20

—

ns

—

Note 1: These parameters are characterized but not tested in manufacturing.

DS70293F-page 303

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-28: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Master

Transmit Only

(Half-Duplex)

Master

Slave

Maximum

Data Rate

Transmit/Receive Transmit/Receive

(Full-Duplex)

CKE

CKP

SMP

(Full-Duplex)

15 Mhz

9 Mhz

Table 28-29

—

0,1

1

0,1

0

0,1

1

—

Table 28-30

—

9 Mhz

Table 28-31

—

0

1

15 Mhz

11 Mhz

15 Mhz

11 Mhz

—

Table 28-32

Table 28-33

Table 28-34

Table 28-35

1

0

1

0

1

0

FIGURE 28-9:

SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 0) TIMING

CHARACTERISTICS

SCKx

(CKP = 0)

SP10

SP21

SP20

SCKx

(CKP = 1)

SP35

SP21

LSb

Bit 14 - - - - - -1

MSb

SDOx

SP30, SP31

Note: Refer to Figure 28-1 for load conditions.

FIGURE 28-10:

SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 1) TIMING

CHARACTERISTICS

SP36

SCKx

(CKP = 0)

SP10

SP21

SP20

SP21

SCKx

(CKP = 1)

SP35

Bit 14 - - - - - -1

SP30, SP31

MSb

LSb

SDOx

Note: Refer to Figure 28-1 for load conditions.

DS70293F-page 304

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-29: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

TscP

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

See Note 3

SP10

SP20

Maximum SCK Frequency

SCKx Output Fall Time

—

15

—

MHz

ns

TscF

TscR

TdoF

TdoR

See parameter DO32

and Note 4

SP21

SP30

SP31

SP35

SP36

SCKx Output Rise Time

—

30

—

6

—

20

—

ns

See parameter DO31

and Note 4

SDOx Data Output Fall Time

SDOx Data Output Rise Time

See parameter DO32

and Note 4

See parameter DO31

and Note 4

TscH2doV, SDOx Data Output Valid after

TscL2doV SCKx Edge

—

TdiV2scH, SDOx Data Output Setup to

—

TdiV2scL

First SCKx Edge

Note 1: These parameters are characterized, but are not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all SPIx pins.

DS70293F-page 305

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-11:

SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = X, SMP = 1) TIMING

CHARACTERISTICS

SP36

SCKx

(CKP = 0)

SP10

SP21

SP20

SP21

SCKx

(CKP = 1)

SP35

Bit 14 - - - - - -1

SP30, SP31

MSb

LSb

SDOx

SDIx

SP40

MSb In

SP41

LSb In

Bit 14 - - - -1

Note: Refer to Figure 28-1 for load conditions.

TABLE 28-30: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING

REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

TscP

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

See Note 3

SP10

SP20

Maximum SCK Frequency

SCKx Output Fall Time

—

9

MHz

ns

TscF

TscR

TdoF

TdoR

—

See parameter DO32

and Note 4

SP21

SP30

SP31

SP35

SP36

SP40

SP41

SCKx Output Rise Time

—

30

—

6

—

20

—

ns

See parameter DO31

and Note 4

SDOx Data Output Fall Time

SDOx Data Output Rise Time

See parameter DO32

and Note 4

See parameter DO31

and Note 4

TscH2doV, SDOx Data Output Valid after

TscL2doV SCKx Edge

—

TdoV2sc, SDOx Data Output Setup to

TdoV2scL First SCKx Edge

—

TdiV2scH, Setup Time of SDIx Data

TdiV2scL Input to SCKx Edge

TscH2diL, Hold Time of SDIx Data Input

TscL2diL

to SCKx Edge

Note 1: These parameters are characterized, but are not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this

specification.

4: Assumes 50 pF load on all SPIx pins.

DS70293F-page 306

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-12:

SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = X, SMP = 1) TIMING

CHARACTERISTICS

SCKx

(CKP = 0)

SP10

SP21

SP20

SCKx

(CKP = 1)

SP35

SP21

LSb

Bit 14 - - - - - -1

MSb

SDOx

SDIx

SP30, SP31

MSb In

SP30, SP31

LSb In

Bit 14 - - - -1

SP40

SP41

Note: Refer to Figure 28-1 for load conditions.

TABLE 28-31: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING

REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

TscP

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

-40ºC to +125ºC and

SP10

Maximum SCK Frequency

—

9

MHz

see Note 3

SP20

SP21

SP30

SP31

SP35

SP36

SP40

SP41

TscF

TscR

TdoF

TdoR

SCKx Output Fall Time

—

30

—

6

—

20

—

ns

See parameter DO32

and Note 4

SCKx Output Rise Time

SDOx Data Output Fall Time

SDOx Data Output Rise Time

See parameter DO31

and Note 4

See parameter DO32

and Note 4

See parameter DO31

and Note 4

TscH2doV, SDOx Data Output Valid after

TscL2doV SCKx Edge

—

TdoV2scH, SDOx Data Output Setup to

TdoV2scL First SCKx Edge

—

TdiV2scH, Setup Time of SDIx Data

TdiV2scL Input to SCKx Edge

TscH2diL, Hold Time of SDIx Data Input

TscL2diL

to SCKx Edge

Note 1: These parameters are characterized, but are not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this

specification.

4: Assumes 50 pF load on all SPIx pins.

DS70293F-page 307

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-13:

SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING

CHARACTERISTICS

SP60

SSx

SP52

SP50

SCKx

(CKP = 0)

SP70

SP72

SP73

SCKx

(CKP = 1)

SP35

SP72

LSb

MSb

Bit 14 - - - - - -1

SDOx

SDIx

SP30,SP31

Bit 14 - - - -1

SP51

MSb In

SP41

LSb In

SP40

Note: Refer to Figure 28-1 for load conditions.

DS70293F-page 308

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-32: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING

REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

TscP

Characteristic⁽¹⁾

Min

Typ⁽²⁾Max Units

Conditions

See Note 3

SP70

SP72

Maximum SCK Input Frequency

SCKx Input Fall Time

—

15

—

MHz

ns

TscF

TscR

TdoF

TdoR

See parameterDO32

and Note 4

SP73

SP30

SP31

SP35

SP36

SP40

SCKx Input Rise Time

—

30

—

6

—

20

—

ns

See parameter DO31

and Note 4

SDOx Data Output Fall Time

SDOx Data Output Rise Time

See parameter DO32

and Note 4

See parameter DO31

and Note 4

TscH2doV, SDOx Data Output Valid after

TscL2doV SCKx Edge

—

TdoV2scH, SDOx Data Output Setup to

TdoV2scL First SCKx Edge

—

TdiV2scH, Setup Time of SDIx Data Input

TdiV2scL

TscH2diL, Hold Time of SDIx Data Input

TscL2diL to SCKx Edge

to SCKx Edge

SP41

SP50

SP51

SP52

SP60

30

—

50

—

50

ns

—

TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input

TssL2scL

120

TssH2doZ SSx ↑ to SDOx Output

10

1.5 TCY + 40

—

High-Impedance⁽⁴⁾

See Note 4

TscH2ssH SSx after SCKx Edge

TscL2ssH

TssL2doV SDOx Data Output Valid after

SSx Edge

—

Note 1: These parameters are characterized, but are not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must

not violate this specification.

4: Assumes 50 pF load on all SPIx pins.

DS70293F-page 309

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-14:

SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING

CHARACTERISTICS

SP60

SSx

SP52

SP50

SCKx

(CKP = 0)

SP72

SP73

SP70

SP73

SCKx

(CKP = 1)

SP35

SP72

LSb

SP52

Bit 14 - - - - - -1

MSb

SDOx

SDIx

SP30,SP31

Bit 14 - - - -1

SP51

MSb In

SP41

LSb In

SP40

Note: Refer to Figure 28-1 for load conditions.

DS70293F-page 310

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-33: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING

REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

TscP

Characteristic⁽¹⁾

Min

Typ⁽²⁾Max Units

Conditions

See Note 3

SP70

SP72

Maximum SCK Input Frequency

SCKx Input Fall Time

—

11

—

MHz

ns

TscF

TscR

TdoF

TdoR

See parameterDO32

and Note 4

SP73

SP30

SP31

SP35

SP36

SP40

SP41

SCKx Input Rise Time

—

30

—

6

—

20

—

ns

See parameter DO31

and Note 4

SDOx Data Output Fall Time

SDOx Data Output Rise Time

See parameter DO32

and Note 4

See parameter DO31

and Note 4

TscH2doV, SDOx Data Output Valid after

TscL2doV SCKx Edge

—

TdoV2scH, SDOx Data Output Setup to

TdoV2scL First SCKx Edge

—

TdiV2scH, Setup Time of SDIx Data Input

TdiV2scL

TscH2diL, Hold Time of SDIx Data Input

TscL2diL to SCKx Edge

to SCKx Edge

SP50

SP51

SP52

SP60

TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input

TssL2scL

120

—

50

—

50

ns

—

TssH2doZ SSx ↑ to SDOx Output

10

1.5 TCY + 40

—

High-Impedance⁽⁴⁾

See Note 4

TscH2ssH SSx after SCKx Edge

TscL2ssH

TssL2doV SDOx Data Output Valid after

SSx Edge

—

Note 1: These parameters are characterized, but are not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3: The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not

violate this specification.

4: Assumes 50 pF load on all SPIx pins.

DS70293F-page 311

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-15:

SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING

CHARACTERISTICS

SSX

SP52

SP50

SCKX

(CKP = 0)

SP70

SP72

SP73

SP72

SCKX

(CKP = 1)

SP73

LSb

SP35

MSb

Bit 14 - - - - - -1

SDOX

SDIX

SP51

SP30,SP31

Bit 14 - - - -1

MSb In

SP41

LSb In

SP40

Note: Refer to Figure 28-1 for load conditions.

DS70293F-page 312

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING

REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

TscP

Characteristic⁽¹⁾

Min

Typ⁽²⁾Max Units

Conditions

See Note 3

SP70

SP72

Maximum SCK Input Frequency

SCKx Input Fall Time

—

15

—

MHz

ns

TscF

TscR

TdoF

TdoR

See parameterDO32

and Note 4

SP73

SP30

SP31

SP35

SP36

SP40

SP41

SCKx Input Rise Time

—

30

—

6

—

20

—

ns

See parameter DO31

and Note 4

SDOx Data Output Fall Time

SDOx Data Output Rise Time

See parameter DO32

and Note 4

See parameter DO31

and Note 4

TscH2doV, SDOx Data Output Valid after

TscL2doV SCKx Edge

—

TdoV2scH, SDOx Data Output Setup to

TdoV2scL First SCKx Edge

—

TdiV2scH, Setup Time of SDIx Data Input

TdiV2scL

TscH2diL, Hold Time of SDIx Data Input

TscL2diL to SCKx Edge

to SCKx Edge

SP50

SP51

SP52

TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input

TssL2scL

120

10

—

50

—

ns

—

TssH2doZ SSx ↑ to SDOx Output

High-Impedance⁽⁴⁾

See Note 4

TscH2ssH SSx after SCKx Edge

TscL2ssH

1.5 TCY + 40

Note 1: These parameters are characterized, but are not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must

not violate this specification.

4: Assumes 50 pF load on all SPIx pins.

DS70293F-page 313

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-16:

SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING

CHARACTERISTICS

SSX

SP52

SP50

SCKX

(CKP = 0)

SP70

SP72

SP73

SP72

SCKX

(CKP = 1)

SP73

LSb

SP35

MSb

SDOX

SDIX

Bit 14 - - - - - -1

SP51

SP30,SP31

Bit 14 - - - -1

MSb In

SP41

LSb In

SP40

Note: Refer to Figure 28-1 for load conditions.

DS70293F-page 314

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING

REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

TscP

Characteristic⁽¹⁾

Min

Typ⁽²⁾Max Units

Conditions

See Note 3

SP70

SP72

Maximum SCK Input Frequency

SCKx Input Fall Time

—

11

—

MHz

ns

TscF

TscR

TdoF

TdoR

See parameterDO32

and Note 4

SP73

SP30

SP31

SP35

SP36

SP40

SP41

SCKx Input Rise Time

—

30

—

6

—

20

—

ns

See parameter DO31

and Note 4

SDOx Data Output Fall Time

SDOx Data Output Rise Time

See parameter DO32

and Note 4

See parameter DO31

and Note 4

TscH2doV, SDOx Data Output Valid after

TscL2doV SCKx Edge

—

TdoV2scH, SDOx Data Output Setup to

TdoV2scL First SCKx Edge

—

TdiV2scH, Setup Time of SDIx Data Input

TdiV2scL

TscH2diL, Hold Time of SDIx Data Input

TscL2diL to SCKx Edge

to SCKx Edge

SP50

SP51

SP52

TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input

TssL2scL

120

10

—

50

—

ns

—

TssH2doZ SSx ↑ to SDOx Output

High-Impedance⁽⁴⁾

See Note 4

TscH2ssH SSx after SCKx Edge

TscL2ssH

1.5 TCY + 40

Note 1: These parameters are characterized, but are not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

3: The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not

violate this specification.

4: Assumes 50 pF load on all SPIx pins.

DS70293F-page 315

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-17:

I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)

SCLx

IM31

IM34

IM30

IM33

SDAx

Stop

Condition

Start

Condition

Note: Refer to Figure 28-1 for load conditions.

FIGURE 28-18:

I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

IM20

IM21

IM11

IM10

SCLx

IM11

IM26

IM10

IM33

IM25

SDAx

In

IM45

IM40

SDAx

Out

Note: Refer to Figure 28-1 for load conditions.

DS70293F-page 316

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-36: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Min⁽¹⁾

Max

Units

Conditions

IM10

TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1)

400 kHz mode TCY/2 (BRG + 1)

—

μs

ns

μs

ns

μs

pF

ns

—

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

IM11

IM20

IM21

IM25

IM26

IM30

IM31

IM33

IM34

IM40

IM45

THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1)

400 kHz mode TCY/2 (BRG + 1)

—

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

TF:SCL

TR:SCL

SDAx and SCLx 100 kHz mode

—

300

100

1000

300

—

CB is specified to be

from 10 to 400 pF

Fall Time

400 kHz mode

1 MHz mode⁽²⁾

20 + 0.1 CB

—

SDAx and SCLx 100 kHz mode

—

CB is specified to be

from 10 to 400 pF

Rise Time

400 kHz mode

1 MHz mode⁽²⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽²⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽²⁾

20 + 0.1 CB

—

250

100

40

0

TSU:DAT Data Input

Setup Time

—

THD:DAT Data Input

Hold Time

—

0

0.9

—

0.2

TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)

—

Only relevant for

Repeated Start

condition

Setup Time

400 kHz mode TCY/2 (BRG + 1)

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)

—

After this period the

first clock pulse is

generated

Hold Time

400 kHz mode TCY/2 (BRG + 1)

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)

—

Setup Time

400 kHz mode TCY/2 (BRG + 1)

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

100 kHz mode TCY/2 (BRG + 1)

400 kHz mode TCY/2 (BRG + 1)

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

THD:STO Stop Condition

Hold Time

—

TAA:SCL Output Valid

From Clock

100 kHz mode

400 kHz mode

1 MHz mode⁽²⁾

—

3500

1000

400

—

TBF:SDA Bus Free Time 100 kHz mode

4.7

1.3

0.5

—

Time the bus must be

free before a new

transmission can start

400 kHz mode

1 MHz mode⁽²⁾

—

IM50

IM51

CB

Bus Capacitive Loading

Pulse Gobbler Delay

400

390

—

TPGD

65

See Note 3

Note 1: BRG is the value of the I²C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit (I²C™)”

(DS70235) in the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip website

(www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual chapters.

2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

3: Typical value for this parameter is 130 ns.

DS70293F-page 317

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-19:

I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

SCLx

IS34

IS31

IS30

IS33

SDAx

Stop

Condition

Start

Condition

FIGURE 28-20:

I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

IS20

IS21

IS11

IS10

SCLx

IS30

IS26

IS31

IS33

IS25

SDAx

In

IS45

IS40

SDAx

Out

DS70293F-page 318

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-37: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for

Extended

Param. Symbol

Characteristic

Min

Max

Units

Conditions

IS10

IS11

TLO:SCL Clock Low Time 100 kHz mode

4.7

—

μs

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

1.3

—

μs

Device must operate at a

minimum of 10 MHz

1 MHz mode⁽¹⁾

0.5

4.0

—

μs

—

THI:SCL Clock High Time 100 kHz mode

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

1 MHz mode⁽¹⁾

0.6

—

μs

Device must operate at a

minimum of 10 MHz

0.5

—

300

100

1000

300

—

μs

ns

μs

ns

μs

pF

—

IS20

IS21

IS25

IS26

IS30

IS31

IS33

IS34

IS40

IS45

IS50

TF:SCL

SDAx and SCLx 100 kHz mode

—

CB is specified to be from

10 to 400 pF

Fall Time

400 kHz mode

1 MHz mode⁽¹⁾

20 + 0.1 CB

—

TR:SCL SDAx and SCLx 100 kHz mode

CB is specified to be from

10 to 400 pF

Rise Time

400 kHz mode

1 MHz mode⁽¹⁾

20 + 0.1 CB

—

TSU:DAT Data Input

Setup Time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

250

100

0

—

THD:DAT Data Input

Hold Time

—

0

0.9

0.3

—

0

TSU:STA Start Condition

Setup Time

4.7

0.6

0.25

4.0

0.6

0.25

4.7

0.6

4000

600

250

0

Only relevant for Repeated

Start condition

—

THD:STA Start Condition

Hold Time

—

After this period, the first

clock pulse is generated

—

TSU:STO Stop Condition

Setup Time

—

THD:ST Stop Condition

O

—

Hold Time

—

TAA:SCL Output Valid

From Clock

3500

1000

350

—

0

TBF:SDA Bus Free Time

4.7

1.3

0.5

—

Time the bus must be free

before a new transmission

can start

—

CB

Bus Capacitive Loading

400

—

Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

DS70293F-page 319

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-21:

ECAN™ MODULE I/O TIMING CHARACTERISTICS

CiTx Pin

(output)

New Value

Old Value

CA10 CA11

CiRx Pin

(input)

CA20

TABLE 28-38: ECAN™ MODULE I/O TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

CA10

CA11

CA20

TioF

TioR

Tcwf

Port Output Fall Time

Port Output Rise Time

—

ns

See parameter D032

See parameter D031

—

Pulse Width to Trigger

CAN Wake-up Filter

120

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

DS70293F-page 320

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-39: ADC MODULE SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Min.

Typ

Max.

Units

Conditions

Device Supply

AD01

AVDD

Module VDD Supply

Greater of

VDD – 0.3

or 3.0

—

Lesser of

VDD + 0.3

or 3.6

V

—

AD02

AVSS

Module VSS Supply

VSS – 0.3

VSS + 0.3

Reference Inputs

AD05

VREFH

Reference Voltage High

AVSS + 2.5

3.0

—

AVDD

3.6

V

AD05a

VREFH = AVDD

VREFL = AVSS = 0

AD06

VREFL

VREF

Reference Voltage Low

AVSS

0

—

AVDD – 2.5

0

V

AD06a

VREFH = AVDD

VREFL = AVSS = 0

AD07

Absolute Reference

Voltage

2.5

—

3.6

V

VREF = VREFH - VREFL

AD08

AD09

IREF

IAD

Current Drain

—

10

μA ADC off

Operating Current

7.0

9.0

mA ADC operating in 10-bit

mode, see Note 1

—

2.7

3.2

mA ADC operating in 12-bit

mode, see Note 1

Analog Input

AD12

AD13

AD17

VINH

VINL

RIN

Input Voltage Range VINH

Input Voltage Range VINL

VINL

—

VREFH

V

This voltage reflects Sample

and Hold Channels 0, 1, 2,

and 3 (CH0-CH3), positive

input

VREFL

—

AVSS + 1V

V

This voltage reflects Sample

and Hold Channels 0, 1, 2,

and 3 (CH0-CH3), negative

input

Recommended Imped-

ance of Analog Voltage

Source

—

200

Ω

10-bit ADC

12-bit ADC

Note 1: These parameters are not characterized or tested in manufacturing.

DS70293F-page 321

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-40: ADC MODULE SPECIFICATIONS (12-BIT MODE)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Min.

Typ

Max. Units

Conditions

ADC Accuracy (12-bit Mode) – Measurements with external VREF+/VREF-

AD20a Nr

AD21a INL

Resolution⁽¹⁾

12 data bits

—

bits

Integral Nonlinearity

-2

> -1

—

+2

< 1

10

5

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V

AD22a DNL

Differential Nonlinearity

Gain Error

—

3.4

0.9

—

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V

AD23a

AD24a

AD25a

GERR

EOFF

—

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V

Offset Error

—

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V

Monotonicity

—

Guaranteed

ADC Accuracy (12-bit Mode) – Measurements with internal VREF+/VREF-

AD20a Nr

AD21a INL

AD22a DNL

Resolution⁽¹⁾

12 data bits

bits

Integral Nonlinearity

Differential Nonlinearity

Gain Error

-2

> -1

2

—

+2

< 1

20

10

—

LSb VINL = AVSS = 0V, AVDD = 3.6V

AD23a

AD24a

AD25a

GERR

EOFF

—

10.5

3.8

—

Offset Error

2

Monotonicity

—

Guaranteed

Dynamic Performance (12-bit Mode)

AD30a THD

Total Harmonic Distortion

—

-75

—

dB

—

AD31a SINAD

Signal to Noise and

Distortion

68.5

69.5

AD32a SFDR

Spurious Free Dynamic

Range

80

—

dB

—

AD33a

FNYQ

Input Signal Bandwidth

Effective Number of Bits

—

250

—

kHz

bits

—

AD34a ENOB

11.09

11.3

Note 1: Injection currents > |0| can affect the ADC results by approximately 4 to 6 counts (i.e., VIH source > (VDD +

0.3V) or VIL source < (VSS – 0.3V).

DS70293F-page 322

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-41: ADC MODULE SPECIFICATIONS (10-BIT MODE)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Min.

Typ

Max. Units

Conditions

ADC Accuracy (10-bit Mode) – Measurements with external VREF+/VREF-

AD20b Nr

AD21b INL

Resolution⁽¹⁾

10 data bits

—

bits

Integral Nonlinearity

-1.5

> -1

—

+1.5

< 1

6

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V

AD22b DNL

Differential Nonlinearity

Gain Error

—

3

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V

AD23b

AD24b

AD25b

GERR

EOFF

—

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V

Offset Error

—

2

5

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V

Monotonicity

—

Guaranteed

ADC Accuracy (10-bit Mode) – Measurements with internal VREF+/VREF-

AD20b Nr

AD21b INL

AD22b DNL

Resolution⁽¹⁾

10 data bits

bits

Integral Nonlinearity

Differential Nonlinearity

Gain Error

-1

> -1

3

—

7

+1

< 1

15

7

LSb VINL = AVSS = 0V, AVDD = 3.6V

AD23b

AD24b

AD25b

GERR

EOFF

—

Offset Error

1.5

—

3

Monotonicity

—

Guaranteed

Dynamic Performance (10-bit Mode)

AD30b THD

Total Harmonic Distortion

—

-64

—

dB

—

AD31b SINAD

Signal to Noise and

Distortion

57

58.5

AD32b SFDR

Spurious Free Dynamic

Range

72

—

dB

—

AD33b

FNYQ

Input Signal Bandwidth

Effective Number of Bits

—

550

—

kHz

bits

—

AD34b ENOB

9.16

9.4

Note 1: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.

DS70293F-page 323

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-22:

ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS

(ASAM = 0, SSRC<2:0> = 000)

AD50

ADCLK

Instruction

Execution

Set SAMP

AD61

Clear SAMP

SAMP

AD60

TSAMP

AD55

DONE

AD1IF

1

2

3

4

5

6

7

8

9

– Software sets AD1CON. SAMP to start sampling.

– Convert bit 11.

– Convert bit 10.

– Convert bit 1.

– Convert bit 0.

1

2

5

6

7

8

9

– Sampling starts after discharge period. TSAMP is described in

Section 16. “Analog-to-Digital Converter” (DS70183) in the

“dsPIC33F/PIC24H Family Reference Manual”.

– Software clears AD1CON. SAMP to start conversion.

3

4

– One TAD for end of conversion.

– Sampling ends, conversion sequence starts.

DS70293F-page 324

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-42: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Min.

Typ⁽²⁾Max.

Units

Conditions

Clock Parameters⁽¹⁾

AD50

AD51

TAD

ADC Clock Period

117.6

—

ns

—

tRC

ADC Internal RC Oscillator

Period

250

Conversion Rate

AD55

AD56

AD57

tCONV

FCNV

Conversion Time

Throughput Rate

Sample Time

—

14 TAD

ns

Ksps

—

500

—

TSAMP

3 TAD

Timing Parameters

AD60

tPCS

2 TAD

—

3 TAD

—

Auto convert trigger not

selected

Conversion Start from Sample

Trigger⁽²⁾

AD61

AD62

AD63

tPSS

tCSS

tDPU

Sample Start from Setting

Sample (SAMP) bit⁽²⁾

2 TAD

—

0.5 TAD

—

3 TAD

—

μs

—

Conversion Completion to

Sample Start (ASAM = 1)⁽²⁾

Time to Stabilize Analog Stage

from ADC Off to ADC On^(2,3)

—

20

Note 1: Because the sample caps eventually loses charge, clock rates below 10 kHz may affect linearity

performance, especially at elevated temperatures.

2: These parameters are characterized but not tested in manufacturing.

3: The tDPU is the time required for the ADC module to stabilize at the appropriate level when the module is

turned on (ADxCON1<ADON>=‘1’). During this time, the ADC result is indeterminate.

DS70293F-page 325

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-23:

ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS

(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)

AD50

Set SAMP

AD61

ADCLK

Instruction

Execution

Clear SAMP

AD60

SAMP

TSAMP

AD55

DONE

AD1IF

1

2

3

4

5

6

7

8

5

6

7

8

– Software sets AD1CON. SAMP to start sampling.

1

2

– Sampling starts after discharge period. TSAMP is described in Section 16. “Analog-to-Digital Converter”

(DS70183) in the “dsPIC33F/PIC24H Family Reference Manual”.

– Software clears AD1CON. SAMP to start conversion.

– Sampling ends, conversion sequence starts.

– Convert bit 9.

3

4

5

6

7

8

– Convert bit 8.

– Convert bit 0.

– One TAD for end of conversion.

FIGURE 28-24:

ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,

SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)

AD50

ADCLK

Instruction

Set ADON

Execution

SAMP

AD1IF

TSAMP

AD55

DONE

1

2

3

4

5

6

7

3

4

5

6

8

– Software sets AD1CON. ADON to start AD operation.

– Convert bit 0.

5

1

2

– Sampling starts after discharge period. TSAMP is described in

Section 16. “Analog-to-Digital Converter” (DS70183) in the

“dsPIC33F/PIC24H Family Reference Manual'.

– One TAD for end of conversion.

– Begin conversion of next channel.

6

7

8

– Convert bit 9.

3

4

– Sample for time specified by SAMC<4:0>.

– Convert bit 8.

DS70293F-page 326

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-43: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Min.

Typ⁽¹⁾

Max.

Units

Conditions

Clock Parameters

AD50 TAD

AD51 tRC

ADC Clock Period

ADC Internal RC Oscillator Period

76

—

ns

—

250

Conversion Rate

AD55 tCONV

AD56 FCNV

Conversion Time

Throughput Rate

—

12 TAD

—

1.1

—

Msps

—

AD57 TSAMP Sample Time

2 TAD

Timing Parameters

AD60 tPCS

AD61 tPSS

AD62 tCSS

AD63 tDPU

Conversion Start from Sample

2 TAD

—

3 TAD

—

μs

Auto-Convert Trigger

not selected

Trigger⁽¹⁾

Sample Start from Setting

Sample (SAMP) bit⁽¹⁾

—

0.5 TAD

—

Conversion Completion to

Sample Start (ASAM = 1)⁽¹⁾

Time to Stabilize Analog Stage

from ADC Off to ADC On^(1,3)

—

20

Note 1: These parameters are characterized but not tested in manufacturing.

2: Because the sample caps eventually loses charge, clock rates below 10 kHz may affect linearity

performance, especially at elevated temperatures.

3: The tDPU is the time required for the ADC module to stabilize at the appropriate level when the module is

turned on (ADxCON1<ADON>=‘1’). During this time, the ADC result is indeterminate.

TABLE 28-44: COMPARATOR TIMING SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

Symbol

Characteristic

Min.

Typ

Max. Units

Conditions

No.

300

301

TRESP

Response Time^(1,2)

—

150

—

400

10

ns

—

TMC2OV

Comparator Mode Change

to Output Valid⁽¹⁾

μs

Note 1: Parameters are characterized but not tested.

2: Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from

VSS to VDD.

DS70293F-page 327

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 28-45: COMPARATOR MODULE SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Min.

Typ

Max.

Units

Conditions

D300

D301

VIOFF

VICM

Input Offset Voltage⁽¹⁾

Input Common Mode Voltage⁽¹⁾

—

0

±10

—

mV

V

—

AVDD-1.5V

D302

CMRR

Common Mode Rejection Ratio⁽¹⁾

-54

—

dB

—

Note 1: Parameters are characterized but not tested.

TABLE 28-46: COMPARATOR REFERENCE VOLTAGE SETTLING TIME SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Settling Time⁽¹⁾

Min.

Typ

Max.

Units

Conditions

VR310

TSET

—

10

μs

Note 1: Setting time measured while CVRR = 1and CVR3:CVR0 bits transition from ‘0000’ to ‘1111’.

TABLE 28-47: COMPARATOR REFERENCE VOLTAGE SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Resolution

Min.

Typ

Max.

Units

Conditions

VRD310 CVRES

VRD311 CVRAA

VRD312 CVRUR

CVRSRC/24

—

2k

CVRSRC/32 LSb

—

Absolute Accuracy

—

0.5

—

LSb

Unit Resistor Value (R)

Ω

DS70293F-page 328

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-25:

PARALLEL SLAVE PORT TIMING DIAGRAM

CS

RD

WR

PS4

PMD<7:0>

PS1

PS3

PS2

TABLE 28-48: SETTING TIME SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No.

Symbol

Characteristic

Min.

Typ

Max.

Units

Conditions

PS1

TdtV2wrH Data in Valid before WR or CS

Inactive (setup time)

20

—

ns

—

PS2

PS3

PS4

TwrH2dtI

WR or CS Inactive to Data-In

Invalid (hold time)

20

—

10

—

80

30

ns

—

TrdL2dtV RD and CS to Active Data-Out

Valid

TrdH2dtI

RD Active or CS Inactive to

Data-Out Invalid

DS70293F-page 329

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-26:

PARALLEL MASTER PORT READ TIMING DIAGRAM

P2

P1

P3

P4

P3

P1

P4

P2

P1

System

Clock

PMA<13:8>

PMD<7:0>

Address

Data

PM7

Address <7:0>

PM2

PM6

PM3

PMRD

PMWR

PM5

PMALL/PMALH

PMCS1

PM1

TABLE 28-49: PARALLEL MASTER PORT READ TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for

Extended

Param

Characteristic

Min.

Typ

Max.

Units

Conditions

No.

PM1

PMALL/PMALH Pulse Width

—

0.5 TCY

—

ns

—

PM2

Address Out Valid to PMALL/PMALH Invalid

(address setup time)

0.75 TCY

PM3

PMALL/PMALH Invalid to Address Out Invalid

(address hold time)

—

0.25 TCY

—

ns

—

PM5

PM6

PMRD Pulse Width

—

0.5 TCY

—

ns

—

PMRD or PMENB Active to Data In Valid (data

setup time)

150

PM7

PMRD or PMENB Inactive to Data In Invalid

(data hold time)

—

5

ns

—

DS70293F-page 330

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

FIGURE 28-27:

PARALLEL MASTER PORT WRITE TIMING DIAGRAM

P2

P1

P3

P2

P3

P4

P1

P4

P2

P1

System

Clock

PMA<13:8>

PMD<7:0>

Address

Address <7:0>

Data

D ta

PM12

PM13

PMRD

PMWR

PM11

PMALL/PMALH

PM16

PMCS1

TABLE 28-50: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

No.

Characteristic

Min.

Typ

Max.

Units

Conditions

PM11 PMWR Pulse Width

—

0.5 TCY

—

ns

—

PM12 Data Out Valid before PMWR or PMENB goes

Inactive (data setup time)

PM13 PMWR or PMEMB Invalid to Data Out Invalid

(data hold time)

—

ns

—

PM16 PMCSx Pulse Width

TCY - 5

TABLE 28-51: DMA READ/WRITE TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

AC CHARACTERISTICS

Param

No.

Characteristic

Min.

Typ

Max.

Units

Conditions

DM1

DMA Read/Write Cycle Time

—

1 TCY

ns

—

DS70293F-page 331

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

NOTES:

DS70293F-page 332

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

29.0 HIGH TEMPERATURE ELECTRICAL CHARACTERISTICS

This section provides an overview of PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04

electrical characteristics for devices operating in an ambient temperature range of -40°C to +150°C.

Note:

Programming of the Flash memory is not allowed above 125°C.

The specifications between -40°C to +150°C are identical to those shown in Section 28.0 “Electrical Characteristics”

for operation between -40°C to +125°C, with the exception of the parameters listed in this section.

Parameters in this section begin with an H, which denotes High temperature. For example, parameter DC10 in

Section 28.0 “Electrical Characteristics” is the Industrial and Extended temperature equivalent of HDC10.

Absolute maximum ratings for the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 high

temperature devices are listed below. Exposure to these maximum rating conditions for extended periods can affect

device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in

the operation listings of this specification is not implied.

Absolute Maximum Ratings⁽¹⁾

Ambient temperature under bias⁽⁴⁾.........................................................................................................-40°C to +150°C

Storage temperature .............................................................................................................................. -65°C to +160°C

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V

Voltage on any pin that is not 5V tolerant with respect to VSS⁽⁵⁾.................................................... -0.3V to (VDD + 0.3V)

Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V⁽⁵⁾....................................... -0.3V to (VDD + 0.3V)

Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V⁽⁵⁾.................................................... -0.3V to 5.6V

Maximum current out of VSS pin .............................................................................................................................60 mA

Maximum current into VDD pin⁽²⁾.............................................................................................................................60 mA

Maximum junction temperature............................................................................................................................. +155°C

Maximum output current sunk by any I/O pin⁽³⁾........................................................................................................1 mA

Maximum output current sourced by any I/O pin⁽³⁾...................................................................................................1 mA

Maximum current sunk by all ports combined ........................................................................................................10 mA

Maximum current sourced by all ports combined⁽²⁾................................................................................................10 mA

Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the

device. This is a stress rating only, and functional operation of the device at those or any other conditions

above those indicated in the operation listings of this specification is not implied. Exposure to maximum

rating conditions for extended periods can affect device reliability.

2: Maximum allowable current is a function of device maximum power dissipation (see Table 29-2).

3: Unlike devices at 125°C and below, the specifications in this section also apply to the CLKOUT, VREF+,

VREF-, SCLx, SDAx, PGCx and PGDx pins.

4: AEC-Q100 reliability testing for devices intended to operate at 150°C is 1,000 hours. Any design in which

the total operating time from 125°C to 150°C will be greater than 1,000 hours is not warranted without prior

written approval from Microchip Technology Inc.

5: Refer to the “Pin Diagrams” section for 5V tolerant pins.

DS70293F-page 333

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

29.1 High Temperature DC Characteristics

TABLE 29-1: OPERATING MIPS VS. VOLTAGE

Max MIPS

VDD Range

(in Volts)

Temperature Range

(in °C)

PIC24HJ32GP302/304,

PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04

Characteristic

3.0V to 3.6V

-40°C to +150°C

20

TABLE 29-2: THERMAL OPERATING CONDITIONS

Rating

Symbol

Min

Typ

Max

Unit

High Temperature Devices

Operating Junction Temperature Range

Operating Ambient Temperature Range

TJ

TA

-40

—

+155

+150

°C

Power Dissipation:

Internal chip power dissipation:

PINT = VDD x (IDD - Σ IOH)

PD

PINT + PI/O

W

I/O Pin Power Dissipation:

I/O = Σ ({VDD - VOH} x IOH) + Σ (VOL x IOL)

Maximum Allowed Power Dissipation

PDMAX

(TJ - TA)/θJA

TABLE 29-3: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature

DC CHARACTERISTICS

Parameter

Symbol

No.

Characteristic

Min

Typ

Max

Units

Conditions

Operating Voltage

HDC10

Supply Voltage

VDD

—

3.0

3.3

3.6

V

-40°C to +140°C

TABLE 29-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

Standard Operating Conditions: 3.0V to 3.6V

DC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature

Parameter

Typical

No.

Max

Units

Conditions

Power-Down Current (IPD)

HDC60e

HDC61c

250

3

2000

5

μA

+150°C

3.3V

Base Power-Down Current^(1,3)

(2,4)

Watchdog Timer Current: ΔIWDT

Note 1: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and

pulled to VSS. WDT, etc., are all switched off, and VREGS (RCON<8>) = 1.

2: The Δ current is the additional current consumed when the module is enabled. This current should be

added to the base IPD current.

3: These currents are measured on the device containing the most memory in this family.

4: These parameters are characterized, but are not tested in manufacturing.

DS70293F-page 334

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 29-5: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)

Standard Operating Conditions: 3.0V to 3.6V

DC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature

Parameter

Typical⁽¹⁾

No.

Doze

Ratio

Max

Units

Conditions

HDC72a

HDC72f

HDC72g

39

18

45

25

1:2

1:64

1:128

mA

+150°C

3.3V

20 MIPS

Note 1: Parameters with Doze ratios of 1:2 and 1:64 are characterized, but are not tested in manufacturing.

TABLE 29-6: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

DC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature

Param

Symbol

No.

Characteristic

Min

Typ

Max Units

Conditions

VOL

Output Low Voltage

I/O ports

HDO10

HDO16

—

0.4

V

IOL = 1 mA, VDD = 3.3V

OSC2/CLKO

VOH

Output High Voltage

I/O ports

HDO20

HDO26

2.40

2.41

—

V

IOH = -1 mA, VDD = 3.3V

OSC2/CLKO

TABLE 29-7: DC CHARACTERISTICS: PROGRAM MEMORY

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature

Param

No.

Symbol

Characteristic⁽¹⁾

Min

Typ

Max

Units

Conditions

Program Flash Memory

Cell Endurance

HD130 EP

10,000

20

—

E/W -40°C to +150°C⁽²⁾

HD134 TRETD

Characteristic Retention

Year 1000 E/W cycles or less and no

other specifications are violated

Note 1: These parameters are assured by design, but are not characterized or tested in manufacturing.

2: Programming of the Flash memory is not allowed above 125°C.

DS70293F-page 335

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

29.2 AC Characteristics and Timing

Parameters

The information contained in this section defines

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 AC characteristics and timing

parameters for high temperature devices. However, all

AC timing specifications in this section are the same as

those in Section 28.2 “AC Characteristics and

Timing Parameters”, with the exception of the

parameters listed in this section.

Parameters in this section begin with an H, which

denotes High temperature. For example, parameter

OS53 in Section 28.2 “AC Characteristics and

Timing Parameters” is the Industrial and Extended

temperature equivalent of HOS53.

TABLE 29-8: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature

AC CHARACTERISTICS

Operating voltage VDD range as described in Table 29-1.

FIGURE 29-1:

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 – for all pins except OSC2

VDD/2

Load Condition 2 – for OSC2

CL

RL

VSS

CL

RL = 464Ω

CL = 50 pF for all pins except OSC2

15 pF for OSC2 output

VSS

TABLE 29-9: PLL CLOCK TIMING SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature

AC

CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Typ

Max

Units

Conditions

HOS53

DCLK

CLKO Stability (Jitter)⁽¹⁾

-5

0.5

5

%

Measured over 100 ms

period

Note 1: These parameters are characterized, but are not tested in manufacturing.

DS70293F-page 336

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 29-10: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature

AC

CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ

Max

Units

Conditions

HSP35

HSP40

HSP41

TscH2doV, SDOx Data Output Valid after

TscL2doV SCKx Edge

—

10

25

ns

—

TdiV2scH, Setup Time of SDIx Data Input

TdiV2scL to SCKx Edge

28

35

—

ns

—

TscH2diL, Hold Time of SDIx Data Input

TscL2diL to SCKx Edge

Note 1: These parameters are characterized but not tested in manufacturing.

TABLE 29-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature

AC

CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ

Max

Units

Conditions

HSP35 TscH2doV, SDOx Data Output Valid after

TscL2doV SCKx Edge

—

10

25

ns

—

HSP36 TdoV2sc, SDOx Data Output Setup to

TdoV2scL First SCKx Edge

35

28

35

—

ns

—

HSP40 TdiV2scH, Setup Time of SDIx Data Input

TdiV2scL to SCKx Edge

HSP41 TscH2diL, Hold Time of SDIx Data Input

TscL2diL

to SCKx Edge

Note 1: These parameters are characterized but not tested in manufacturing.

DS70293F-page 337

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 29-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature

AC

CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ

Max Units

Conditions

HSP35 TscH2doV, SDOx Data Output Valid after

TscL2doV SCKx Edge

HSP40 TdiV2scH, Setup Time of SDIx Data Input

—

35

—

55

ns

—

25

15

—

TdiV2scL

to SCKx Edge

HSP41 TscH2diL,

TscL2diL

Hold Time of SDIx Data Input to

SCKx Edge

See Note 2

HSP51 TssH2doZ SSx ↑ to SDOx Output

High-Impedance

Note 1: These parameters are characterized but not tested in manufacturing.

2: Assumes 50 pF load on all SPIx pins.

TABLE 29-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature

AC

CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ

Max

Units

Conditions

HSP35

HSP40

HSP41

HSP51

HSP60

TscH2doV, SDOx Data Output Valid after

TscL2doV SCKx Edge

—

35

ns

—

TdiV2scH, Setup Time of SDIx Data Input

TdiV2scL to SCKx Edge

25

15

—

55

ns

—

TscH2diL, Hold Time of SDIx Data Input

TscL2diL

to SCKx Edge

See Note 2

TssH2doZ SSx ↑ to SDOX Output

High-Impedance

TssL2doV SDOx Data Output Valid after

SSx Edge

—

Note 1: These parameters are characterized but not tested in manufacturing.

2: Assumes 50 pF load on all SPIx pins.

DS70293F-page 338

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 29-14: ADC MODULE SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature

AC

CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Typ

Max Units

Conditions

Reference Inputs

HAD08

IREF

Current Drain

—

250

—

600

50

μA ADC operating, See Note 1

μA ADC off, See Note 1

Note 1: These parameters are not characterized or tested in manufacturing.

2: These parameters are characterized, but are not tested in manufacturing.

TABLE 29-15: ADC MODULE SPECIFICATIONS (12-BIT MODE)

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature

AC

CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Typ

Max

Units

Conditions

ADC Accuracy (12-bit Mode) – Measurements with External VREF+/VREF-⁽¹⁾

HAD20a Nr

HAD21a INL

Resolution⁽³⁾

12 data bits

—

bits

—

Integral Nonlinearity

-2

> -1

-2

+2

< 1

10

5

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V

HAD22a DNL

HAD23a GERR

HAD24a EOFF

Differential Nonlinearity

Gain Error

—

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V

Offset Error

-3

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V

ADC Accuracy (12-bit Mode) – Measurements with Internal VREF+/VREF-⁽¹⁾

HAD20a Nr

Resolution⁽³⁾

12 data bits

bits

—

HAD21a INL

HAD22a DNL

HAD23a GERR

HAD24a EOFF

Integral Nonlinearity

Differential Nonlinearity

Gain Error

-2

> -1

2

—

+2

< 1

20

LSb VINL = AVSS = 0V, AVDD = 3.6V

Offset Error

2

10

Dynamic Performance (12-bit Mode)⁽²⁾

HAD33a FNYQ

Input Signal Bandwidth 200 kHz

—

Note 1: These parameters are characterized, but are tested at 20 ksps only.

2: These parameters are characterized by similarity, but are not tested in manufacturing.

3: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.

DS70293F-page 339

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 29-16: ADC MODULE SPECIFICATIONS (10-BIT MODE)

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature

AC

CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Typ

Max

Units

Conditions

ADC Accuracy (10-bit Mode) – Measurements with External VREF+/VREF-⁽¹⁾

HAD20b Nr

HAD21b INL

Resolution⁽³⁾

10 data bits

—

bits

—

Integral Nonlinearity

-3

> -1

-5

3

< 1

6

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V

HAD22b DNL

HAD23b GERR

HAD24b EOFF

Differential Nonlinearity

Gain Error

—

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V

Offset Error

-1

5

LSb VINL = AVSS = VREFL = 0V,

AVDD = VREFH = 3.6V

ADC Accuracy (10-bit Mode) – Measurements with Internal VREF+/VREF-⁽¹⁾

HAD20b Nr

Resolution⁽³⁾

10 data bits

bits

—

HAD21b INL

HAD22b DNL

HAD23b GERR

HAD24b EOFF

Integral Nonlinearity

Differential Nonlinearity

Gain Error

-2

> -1

-5

—

2

< 1

15

7

LSb VINL = AVSS = 0V, AVDD = 3.6V

Offset Error

-1.5

Dynamic Performance (10-bit Mode)⁽²⁾

HAD33b FNYQ

Input Signal Bandwidth 400 kHz

—

Note 1: These parameters are characterized, but are tested at 20 ksps only.

2: These parameters are characterized by similarity, but are not tested in manufacturing.

3: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.

DS70293F-page 340

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE 29-17: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature

AC

CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Typ

Max

Units

Conditions

Clock Parameters

HAD50 TAD

ADC Clock Period⁽¹⁾

Throughput Rate⁽¹⁾

147

Conversion Rate

—

ns

—

HAD56 FCNV

—

400

Ksps

Note 1: These parameters are characterized but not tested in manufacturing.

TABLE 29-18: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature

AC

CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Typ

Max

Units

Conditions

Clock Parameters

HAD50

HAD56

TAD

ADC Clock Period⁽¹⁾

Throughput Rate⁽¹⁾

104

—

ns

—

Conversion Rate

FCNV

—

800

Ksps

Note 1: These parameters are characterized but not tested in manufacturing.

DS70293F-page 341

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

NOTES:

DS70293F-page 342

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

30.0 PACKAGING INFORMATION

28-Lead SPDIP

Example

PIC24HJ32GP

302-E/SP

0730235

XXXXXXXXXXXXXXXXX

YYWWNNN

e

3

28-Lead SOIC (.300”)

Example

XXXXXXXXXXXXXXXXXXXX

PIC24HJ32GP

302-E/SO

e

3

0730235

YYWWNNN

28-Lead QFN-S

Example

XXXXXXXX

YYWWNNN

24HJ32GP

302EMM

0730235

44-Lead QFN

Example

XXXXXXXXXX

YYWWNNN

PIC

24HJ32GP304

-E/ML

0730235

e

3

Example

44-Lead TQFP

PIC

24HJ32GP304

-I/PT

XXXXXXXXXX

YYWWNNN

e

3

0730235

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

e

3

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next

line, thus limiting the number of available characters for customer-specific information.

DS70293F-page 343

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

30.1 Package Details

28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

1

2 3

D

E

A2

A

L

c

b1

A1

b

e

eB

Units

Dimension Limits

INCHES

NOM

28

.100 BSC

–

MIN

MAX

Number of Pins

Pitch

N

e

A

Top to Seating Plane

–

.200

.150

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

Tip to Seating Plane

Lead Thickness

Upper Lead Width

A2

A1

E

E1

D

L

c

b1

b

eB

.120

.015

.290

.240

1.345

.110

.008

.040

.014

–

.135

–

.310

.285

1.365

.130

.010

.050

.018

–

.335

.295

1.400

.150

.015

.070

.022

.430

Lower Lead Width

Overall Row Spacing §

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-070B

DS70293F-page 344

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

3

e

b

h

α

h

c

φ

A2

A

L

A1

L1

β

Units

MILLMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

28

1.27 BSC

Overall Height

Molded Package Thickness

Standoff §

A

–

2.05

0.10

–

2.65

–

0.30

A2

A1

E

Overall Width

10.30 BSC

Molded Package Width

Overall Length

Chamfer (optional)

Foot Length

E1

D

h

7.50 BSC

17.90 BSC

0.25

0.40

–

0.75

1.27

L

Footprint

L1

φ

1.40 REF

Foot Angle Top

Lead Thickness

Lead Width

Mold Draft Angle Top

Mold Draft Angle Bottom

0°

0.18

0.31

5°

–

8°

c

b

α

0.33

0.51

15°

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-052B

DS70293F-page 345

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

28-Lead Plastic Quad Flat, No Lead Package (MM) – 6x6x0.9 mm Body [QFN-S]

with 0.40 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D2

D

EXPOSED

PAD

e

E2

E

b

2

1

2

1

K

N

L

NOTE 1

BOTTOM VIEW

TOP VIEW

A

A3

A1

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Pins

Pitch

Overall Height

Standoff

Contact Thickness

Overall Width

Exposed Pad Width

Overall Length

Exposed Pad Length

Contact Width

Contact Length

Contact-to-Exposed Pad

N

e

A

A1

A3

E

E2

D

28

0.65 BSC

0.90

0.80

0.00

1.00

0.05

0.02

0.20 REF

6.00 BSC

3.70

6.00 BSC

3.70

0.38

0.40

–

3.65

4.70

D2

b

L

3.65

0.23

0.30

0.20

4.70

0.43

0.50

–

K

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-124B

DS70293F-page 346

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢅꢆꢇꢐꢉꢅꢋꢑꢇꢒꢓꢇꢃꢄꢅꢆꢇꢈꢅꢍꢔꢅꢕꢄꢇꢖꢗꢗꢘꢇMꢇꢙꢚꢙꢚꢛꢜ ꢇ!!ꢇ"ꢓꢆ#ꢇ$ꢎꢐꢒꢂ%&

'ꢌꢋ(ꢇꢛꢜ)ꢛꢇ!!ꢇ*ꢓ+ꢋꢅꢍꢋꢇꢃꢄ+ꢕꢋ(

ꢒꢓꢋꢄ, ꢀꢁꢂꢃ ꢄꢅꢃ!ꢁ" ꢃꢆ#ꢂꢂꢅꢇ ꢃꢈꢉꢆ$ꢉꢊꢅꢃ%ꢂꢉ&ꢋꢇꢊ"'ꢃꢈꢌꢅꢉ"ꢅꢃ"ꢅꢅꢃ ꢄꢅꢃꢍꢋꢆꢂꢁꢆꢄꢋꢈꢃ(ꢉꢆ$ꢉꢊꢋꢇꢊꢃꢎꢈꢅꢆꢋ)ꢋꢆꢉ ꢋꢁꢇꢃꢌꢁꢆꢉ ꢅ%ꢃꢉ ꢃ

ꢄ ꢈ*++&&&ꢏ!ꢋꢆꢂꢁꢆꢄꢋꢈꢏꢆꢁ!+ꢈꢉꢆ$ꢉꢊꢋꢇꢊ

DS70293F-page 347

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D2

D

EXPOSED

PAD

e

b

K

E

E2

2

1

2

1

N

NOTE 1

L

TOP VIEW

BOTTOM VIEW

A

A3

A1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

44

0.65 BSC

0.90

MAX

Number of Pins

Pitch

Overall Height

Standoff

Contact Thickness

Overall Width

N

e

A

A1

A3

E

E2

D

0.80

0.00

1.00

0.05

0.02

0.20 REF

8.00 BSC

6.45

8.00 BSC

6.45

0.30

0.40

–

Exposed Pad Width

Overall Length

Exposed Pad Length

Contact Width

Contact Length

Contact-to-Exposed Pad

6.30

6.80

D2

b

L

6.30

0.25

0.30

0.20

6.80

0.38

0.50

–

K

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-103B

DS70293F-page 348

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

))ꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢅꢆꢇꢐꢉꢅꢋꢑꢇꢒꢓꢇꢃꢄꢅꢆꢇꢈꢅꢍꢔꢅꢕꢄꢇꢖꢗꢃꢘꢇMꢇꢁꢚꢁꢇ!!ꢇ"ꢓꢆ#ꢇ$ꢎꢐꢒ&

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ꢄ ꢈ*++&&&ꢏ!ꢋꢆꢂꢁꢆꢄꢋꢈꢏꢆꢁ!+ꢈꢉꢆ$ꢉꢊꢋꢇꢊ

DS70293F-page 349

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

D1

E

e

E1

N

b

NOTE 1

1 2 3

NOTE 2

α

A

c

φ

A2

β

A1

L

L1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

44

0.80 BSC

–

1.00

–

MAX

Number of Leads

Lead Pitch

Overall Height

Molded Package Thickness

Standoff

Foot Length

N

e

A

A2

A1

L

–

1.20

1.05

0.15

0.75

0.95

0.05

0.45

0.60

Footprint

Foot Angle

L1

φ

1.00 REF

3.5°

0°

7°

Overall Width

Overall Length

E

D

E1

D1

c

12.00 BSC

10.00 BSC

–

Molded Package Width

Molded Package Length

Lead Thickness

Lead Width

Mold Draft Angle Top

Mold Draft Angle Bottom

0.09

0.30

11°

0.20

0.45

13°

b

α

0.37

12°

β

11°

13°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Chamfers at corners are optional; size may vary.

3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-076B

DS70293F-page 350

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

))ꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ-(ꢌ+ꢇꢎꢏꢅꢆꢇꢐꢉꢅꢋ.ꢅꢍꢔꢇꢖꢈ-ꢘꢇMꢇ/ꢛꢚ/ꢛꢚ/ꢇ!!ꢇ"ꢓꢆ#ꢑꢇꢀꢜꢛꢛꢇ!!ꢇ$-ꢎꢐꢈ&

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ꢄ ꢈ*++&&&ꢏ!ꢋꢆꢂꢁꢆꢄꢋꢈꢏꢆꢁ!+ꢈꢉꢆ$ꢉꢊꢋꢇꢊ

DS70293F-page 351

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

NOTES:

DS70293F-page 352

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

APPENDIX A: REVISION HISTORY

Revision A (September 2007)

Initial release of this document.

Revision B (March 2008)

This revision includes minor typographical and

formatting changes throughout the data sheet text. In

addition, redundant information was removed that is

now available in the respective chapters of the

dsPIC33F/PIC24H Family Reference Manual, which

can be obtained from the Microchip website

(www.microchip.com).

The major changes are referenced by their respective

section in the following table.

TABLE A-1:

MAJOR SECTION UPDATES

Section Name

Update Description

“High-Performance, 16-bit Microcontrollers” Note 1 added to all pin diagrams (see “Pin Diagrams”)

Updated the “PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04 Controller Families” table as follows:

• PIC24HJ128GP804 changed to PIC24HJ128GP504

• Added new column: External Interrupts

• Added Note 3

Section 1.0 “Device Overview”

Section 6.0 “Interrupt Controller”

Updated parameters PMA0, PMA1 and PMD0 through PMPD7

(Table 1-1)

IFS0-IFSO4 changed to IFSX (see Section 6.3.2 “IFSx”)

IEC0-IEC4 changed to IECX (see Section 6.3.3 “IECx”)

IPC0-IPC19 changed to IPCx (see Section 6.3.4 “IPCx”)

Section 7.0 “Direct Memory Access (DMA)” Updated parameter PMP (see Table 7-1)

Section 8.0 “Oscillator Configuration” Updated the third clock source item (External Clock) in

Section 8.1.1 “System Clock Sources”

Updated TUN<5:0> (OSCTUN<5:0>) bit description (see

Register 8-4)

Section 19.0 “10-bit/12-bit Analog-to-Digital Added Note 2 to Figure 19-3

Converter (ADC1)”

Section 24.0 “Special Features”

Added Note 2 to Figure 24-1

Added Note after second paragraph in Section 24.2 “On-Chip

Voltage Regulator”

DS70293F-page 353

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE A-1:

MAJOR SECTION UPDATES (CONTINUED)

Section Name

Update Description

Section 27.0 “Electrical Characteristics”

Updated Max MIPS for temperature range of -40ºC to +125ºC in

Table 27-1

Updated typical values in Thermal Packaging Characteristics in

Table 27-3

Added parameters DI11 and DI12 to Table 27-9

Updated minimum values for parameters D136 (TRW) and D137

(TPE) and removed typical values in Table 27-12

Added Extended temperature range to Table 27-13

Updated parameter AD63 and added Note 3 to Table 27-38 and

Table 27-39

DS70293F-page 354

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

Revision C (May 2009)

This revision includes minor typographical and

formatting changes throughout the data sheet text.

Global changes include:

• Changed all instances of OSCI to OSC1 and

OSCO to OSC2

• Changed all instances of VDDCORE and VDDCORE/

VCAP to VCAP/VDDCORE

The other changes are referenced by their respective

section in the following table.

TABLE A-2:

MAJOR SECTION UPDATES

Section Name

Update Description

“High-Performance, 16-bit

Microcontrollers”

Updated all pin diagrams to denote the pin voltage tolerance (see “Pin

Diagrams”).

Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which

references pin connections to VSS.

Section 1.0 “Device Overview”

Updated AVDD in the PINOUT I/O Descriptions (see Table 1-1).

Section 2.0 “Guidelines for Getting

Added new section to the data sheet that provides guidelines on getting

Started with 16-bit Microcontrollers” started with 16-bit Digital Signal Controllers.

Added Peripheral Pin Select (PPS) capability column to Pinout I/O

Descriptions (see Table 1-1).

Section 3.0 “CPU”

Updated CPU Core Block Diagram with a connection from the DSP

Engine to the Y Data Bus (see Figure 3-1).

Section 4.0 “Memory Organization”

Updated Reset value for CORCON in the CPU Core Register Map (see

Table 4-1).

Updated Reset value for IPC15 in the Interrupt Controller Register Map

(see Table 4-4).

Removed the FLTA1IE bit (IEC3) from the Interrupt Controller Register

Map (see Table 4-4).

Updated bit locations for RPINR25 in the Peripheral Pin Select Input

Register Map (see Table 4-19).

Updated the Reset value for CLKDIV in the System Control Register Map

(see Table 4-31).

Section 5.0 “Flash Program Memory” Updated Section 5.3 “Programming Operations” with programming

time formula.

Section 9.0 “Oscillator Configuration” Updated the Oscillator System Diagram and added Note 2 (see

Figure 9-1).

Updated default bit values for DOZE<2:0> and FRCDIV<2:0> in the Clock

Divisor (CLKDIV) Register (see Register 9-2).

Added a paragraph regarding FRC accuracy at the end of Section 9.1.1

“System Clock Sources”.

Added Note 3 to Section 9.2.2 “Oscillator Switching Sequence”.

Added Note 1 to the FRC Oscillator Tuning (OSCTUN) Register (see

Register 9-4).

DS70293F-page 355

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE A-2:

MAJOR SECTION UPDATES (CONTINUED)

Section Name

Update Description

Added the following registers:

Section 10.0 “Power-Saving

Features”

• PMD1: Peripheral Module Disable Control Register 1 (Register 10-1)

• PMD2: Peripheral Module Disable Control Register 2 (Register 10-2)

• PMD3: Peripheral Module Disable Control Register 3 (Register 10-3)

Section 11.0 “I/O Ports”

Removed Table 11-1 and added reference to pin diagrams for I/O pin

availability and functionality.

Added paragraph on ADPCFG register default values to Section 11.3

“Configuring Analog Port Pins”.

Added Note box regarding PPS functionality with input mapping to

Section 11.6.2.1 “Input Mapping”.

Section 16.0 “Serial Peripheral

Interface (SPI)”

Added Note 2 and 3 to the SPIxCON1 register (see Register 16-2).

Updated the Notes in the UxMode register (see Register 18-1).

Section 18.0 “Universal

Asynchronous Receiver Transmitter

(UART)”

Updated the UTXINV bit settings in the UxSTA register (see

Register 18-2).

Section 19.0 “Enhanced CAN

(ECAN™) Module”

Changed bit 11 in the ECAN Control Register 1 (CiCTRL1) to Reserved

(see Register 19-1).

Section 20.0 “10-bit/12-bit Analog-to- Replaced the ADC1 Module Block Diagrams with new diagrams (see

Digital Converter (ADC1)”

Figure 20-1 and Figure 20-2).

Updated bit values for ADCS<7:0> and added Notes 1 and 2 to the ADC1

Control Register 3 (AD1CON3) (see Register 20-3).

Added Note 2 to the ADC1 Input Scan Select Register Low (AD1CSSL)

(see Register 20-7).

Added Note 2 to the ADC1 Port Configuration Register Low (AD1PCFGL)

(see Register 20-8).

Section 21.0 “Comparator Module”

Updated the Comparator Voltage Reference Block Diagram

(see Figure 21-2).

Section 22.0 “Real-Time Clock and

Calendar (RTCC)”

Updated the minimum positive adjust value for CAL<7:0> in the RTCC

Calibration and Configuration (RCFGCAL) Register (see Register 22-1).

Section 25.0 “Special Features”

Added Note 1 to the Device Configuration Register Map (see Table 25-1).

Updated Note 1 in the PIC24H Configuration Bits Description (see

Table 25-2).

DS70293F-page 356

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE A-2:

MAJOR SECTION UPDATES (CONTINUED)

Section Name

Update Description

Section 28.0 “Electrical

Characteristics”

Updated Typical values for Thermal Packaging Characteristics (see

Table 28-3).

Updated Min and Max values for parameter DC12 (RAM Data Retention

Voltage) and added Note 4 (see Table 28-4).

Updated Power-Down Current Max values for parameters DC60b and

DC60c (see Table 28-7).

Updated Characteristics for I/O Pin Input Specifications (see Table 28-9).

Updated Program Memory values for parameters 136, 137 and 138

(renamed to 136a, 137a and 138a), added parameters 136b, 137b and

138b, and added Note 2 (see Table 28-12).

Added parameter OS42 (GM) to the External Clock Timing Requirements

(see Table 28-16).

Updated Watchdog Timer Time-out Period parameter SY20 (see

Table 28-21).

DS70293F-page 357

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

Revision D (November 2009)

The revision includes the following global update:

• Added Note 2 to the shaded table that appears at

the beginning of each chapter. This new note

provides information regarding the availability of

registers and their associated bits

This revision also includes minor typographical and

formatting changes throughout the data sheet text.

All other major changes are referenced by their

respective section in the following table.

TABLE A-3:

MAJOR SECTION UPDATES

Section Name

Update Description

“High-Performance, 16-bit

Microcontrollers”

Added information on high temperature operation (see “Operating

Range:”).

Section 11.0 “I/O Ports”

Changed the reference to digital-only pins to 5V tolerant pins in the

second paragraph of Section 11.2 “Open-Drain Configuration”.

Section 18.0 “Universal Asynchronous

Receiver Transmitter (UART)”

Updated the two baud rate range features to: 10 Mbps to 38 bps at

40 MIPS.

Section 20.0 “10-bit/12-bit Analog-to-Digital Updated the ADC block diagrams (see Figure 20-1 and Figure 20-2).

Converter (ADC1)”

Section 25.0 “Special Features”

Updated the second paragraph and removed the fourth paragraph in

Section 25.1 “Configuration Bits”.

Updated the Device Configuration Register Map (see Table 28-1).

Section 28.0 “Electrical Characteristics”

Updated the Absolute Maximum Ratings for high temperature and

added Note 4.

Removed parameters DI26, DI28 and DI29 from the I/O Pin Input

Specifications (see Table 28-9).

Updated the SPIx Module Slave Mode (CKE = 1) Timing

Characteristics (see Figure 28-12).

Section 29.0 “High Temperature Electrical Added new chapter with high temperature specifications.

Characteristics”

“Product Identification System”

Added the “H” definition for high temperature.

DS70293F-page 358

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

Revision E (January 2011)

This includes typographical and formatting changes

throughout the data sheet text. In addition, the

Preliminary marking in the footer was removed.

All occurrences of VDDCORE have been removed

throughout the document.

All other major changes are referenced by their

respective section in the following table.

TABLE A-4:

MAJOR SECTION UPDATES

Section Name

Update Description

“High-Performance, 16-bit

Microcontrollers”

The high temperature end range was updated to +150ºC (see

“Operating Range:”).

Section 2.0 “Guidelines for Getting Started The frequency limitation for device PLL start-up conditions was

with 16-bit Microcontrollers”

updated in Section 2.7 “Oscillator Value Conditions on Device

Start-up”.

The second paragraph in Section 2.9 “Unused I/Os” was updated.

Section 4.0 “Memory Organization”

The All Resets values for the following SFRs in the Timer Register

Map were changed (see Table 4-5):

• TMR1

• TMR2

• TMR3

• TMR4

• TMR5

Section 9.0 “Oscillator Configuration”

Added Note 3 to the OSCCON: Oscillator Control Register (see

Register 9-1).

Added Note 2 to the CLKDIV: Clock Divisor Register (see

Register 9-2).

Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see

Register 9-3).

Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see

Register 9-4).

Section 20.0 “10-bit/12-bit Analog-to-Digital Updated the VREFL references in the ADC1 module block diagrams

Converter (ADC1)”

(see Figure 20-1 and Figure 20-2).

Section 25.0 “Special Features”

Added a new paragraph and removed the third paragraph in

Section 25.1 “Configuration Bits”.

Added the column “RTSP Effects” to the dsPIC33F Configuration

Bits Descriptions (see Table 25-2).

DS70293F-page 359

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE A-4:

MAJOR SECTION UPDATES (CONTINUED)

Section Name

Update Description

Section 28.0 “Electrical Characteristics”

Updated the maximum value for Extended Temperature Devices in

the Thermal Operating Conditions (see Table 28-2).

Removed Note 4 from the DC Temperature and Voltage

Specifications (see Table 28-4).

Updated all typical and maximum Operating Current (IDD) values

(see Table 28-5).

Updated all typical and maximum Idle Current (IIDLE) values (see

Table 28-6).

Updated the maximum Power-Down Current (IPD) values for

parameters DC60d, DC60a, and DC60b (see Table 28-7).

Updated all typical Doze Current (Idoze) values (see Table 28-8).

Updated the maximum value for parameter DI19 and added

parameters DI28, DI29, DI60a, DI60b, and DI60c to the I/O Pin Input

Specifications (see Table 28-9).

Added Note 2 to the PLL Clock Timing Specifications (see Table 28-

17)

Removed Note 2 from the AC Characteristics: Internal RC Accuracy

(see Table 28-18).

Updated the Internal RC Accuracy minimum and maximum values

for parameter F21b (see Table 28-19).

Updated the characteristic description for parameter DI35 in the I/O

Timing Requirements (see Table 28-20).

Updated all SPI specifications (see Table 28-28 through Table 28-35

and Figure 28-10 through Figure 28-16)

Updated the ADC Module Specification minimum values for

parameters AD05 and AD07, and updated the maximum value for

parameter AD06 (see Table 28-41).

Updated the ADC Module Specifications (12-bit Mode) minimum and

maximum values for parameter AD21a (see Table 28-42).

Updated all ADC Module Specifications (10-bit Mode) values, with

the exception of Dynamic Performance (see Table 28-43).

Updated the minimum value for parameter PM6 and the maximum

value for parameter PM7 in the Parallel Master Port Read Timing

Requirements (see Table 28-49).

Added DMA Read/Write Timing Requirements (see Table 28-51).

DS70293F-page 360

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

TABLE A-4:

MAJOR SECTION UPDATES (CONTINUED)

Section Name

Update Description

Section 29.0 “High Temperature Electrical

Characteristics”

Updated all ambient temperature end range values to +150ºC

throughout the chapter.

Updated the storage temperature end range to +160ºC.

Updated the maximum junction temperature from +145ºC to +155ºC.

Updated the maximum values for High Temperature Devices in the

Thermal Operating Conditions (see Table 29-2).

Updated the ADC Module Specifications (12-bit Mode), removing all

parameters with the exception of HAD33a (see Table 29-14).

Updated the ADC Module Specifications (10-bit Mode), removing all

parameters with the exception of HAD33b (see Table 29-16).

“Product Identification System”

Updated the end range temperature value for H (High) devices.

DS70293F-page 361

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

Revision F (August 2011)

This revision includes typographical and formatting

changes throughout the data sheet text.

All other major changes are referenced by their

respective section in the following table.

TABLE A-5:

MAJOR SECTION UPDATES

Section Name

Update Description

Section 25.0 “Special Features”

Added Note 3 to the Connections for the On-chip Voltage Regulator

diagram (see Figure 25-1).

Section 28.0 “Electrical Characteristics”

Removed Voltage on VCAP with respect to Vss from the Absolute

Maximum Ratings.

Removed Note 3 and parameter DC10 (VCORE) from the DC

Temperature and Voltage Specifications (see Table 28-4).

Updated the Characteristics definition and Conditions for parameter

BO10 in the Electrical Characteristics: BOR (see Table 28-11).

Added Note 1 to the Internal Voltage Regulator Specifications (see

Table 28-13).

DS70293F-page 362

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

INDEX

A

D

A/D Converter ................................................................... 221

Data Address Space........................................................... 29

Alignment.................................................................... 29

Memory Map for PIC24HJ128GP202/204 and

DMA.......................................................................... 221

Initialization ............................................................... 221

Key Features............................................................. 221

AC Characteristics .................................................... 294, 336

ADC Module.............................................................. 339

ADC Module (10-bit Mode) ....................................... 340

ADC Module (12-bit Mode) ....................................... 339

Internal RC Accuracy................................................ 296

Load Conditions................................................ 294, 336

ADC Module

PIC24HJ64GP202/204 Devices

with 8 KB RAM ................................................... 31

Memory Map for PIC24HJ32GP302/304 Devices

with 4 KB RAM ................................................... 30

Near Data Space........................................................ 29

Software Stack ........................................................... 49

Width .......................................................................... 29

DC Characteristics............................................................ 284

Doze Current (IDOZE)................................................ 335

High Temperature..................................................... 334

I/O Pin Input Specifications ...................................... 289

I/O Pin Output........................................................... 335

I/O Pin Output Specifications.................................... 292

Idle Current (IDOZE) .................................................. 288

Idle Current (IIDLE).................................................... 287

Operating Current (IDD) ............................................ 286

Operating MIPS vs. Voltage ..................................... 334

Power-Down Current (IPD)........................................ 288

Power-down Current (IPD) ........................................ 334

Program Memory.............................................. 293, 335

Temperature and Voltage......................................... 334

Temperature and Voltage Specifications.................. 285

Thermal Operating Conditions.................................. 334

Development Support....................................................... 279

DMA Module

DMA Register Map ..................................................... 39

DMAC Registers............................................................... 109

DMAxCNT ................................................................ 109

DMAxCON................................................................ 109

DMAxPAD ................................................................ 109

DMAxREQ................................................................ 109

DMAxSTA................................................................. 109

DMAxSTB................................................................. 109

Doze Mode ....................................................................... 130

ADC11 Register Map.................................................. 38

Alternate Interrupt Vector Table (AIVT) .............................. 69

Arithmetic Logic Unit (ALU)................................................. 26

Assembler

MPASM Assembler................................................... 280

B

Block Diagrams

16-bit Timer1 Module................................................ 161

A/D Module ....................................................... 222, 223

Connections for On-Chip Voltage Regulator............. 265

Device Clock..................................................... 119, 121

ECAN Module ........................................................... 196

Input Capture ............................................................ 169

Output Compare ....................................................... 171

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and

PIC24HJ128GPX02/X04 .................................... 12

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and

PIC24HJ128GPX02/X04 CPU Core................... 22

PLL............................................................................ 121

Reset System.............................................................. 61

Shared Port Structure ............................................... 135

SPI ............................................................................ 175

Timer2 (16-bit) .......................................................... 163

Timer2/3 (32-bit) ....................................................... 165

UART ........................................................................ 189

Watchdog Timer (WDT)............................................ 266

E

C

ECAN Module

C Compilers

CiBUFPNT1 register................................................. 207

CiBUFPNT2 register................................................. 208

CiBUFPNT3 register................................................. 208

CiBUFPNT4 register................................................. 209

CiCFG1 register........................................................ 205

CiCFG2 register........................................................ 206

CiCTRL1 register...................................................... 198

CiCTRL2 register...................................................... 199

CiEC register ............................................................ 205

CiFCTRL register...................................................... 201

CiFEN1 register........................................................ 207

CiFIFO register......................................................... 202

CiFMSKSEL1 register .............................................. 211

CiFMSKSEL2 register .............................................. 212

CiINTE register......................................................... 204

CiINTF register ......................................................... 203

CiRXFnEID register.................................................. 211

CiRXFnSID register.................................................. 210

CiRXFUL1 register ................................................... 214

CiRXFUL2 register ................................................... 214

CiRXMnEID register ................................................. 213

CiRXMnSID register ................................................. 213

CiRXOVF1 register................................................... 215

CiRXOVF2 register................................................... 215

CiTRmnCON register ............................................... 216

MPLAB C18 .............................................................. 280

Clock Switching................................................................. 128

Enabling.................................................................... 128

Sequence.................................................................. 128

Code Examples

Erasing a Program Memory Page............................... 59

Initiating a Programming Sequence............................ 60

Loading Write Buffers ................................................. 60

Port Write/Read ........................................................ 136

PWRSAV Instruction Syntax..................................... 129

Code Protection ........................................................ 261, 267

Configuration Bits.............................................................. 261

Configuration Register Map .............................................. 261

Configuring Analog Port Pins............................................ 136

CPU

Control Register.......................................................... 24

CPU Clocking System....................................................... 120

PLL Configuration ..................................................... 121

Selection ................................................................... 120

Sources..................................................................... 120

Customer Change Notification Service............................. 367

Customer Notification Service........................................... 367

Customer Support............................................................. 367

DS70293F-page 363

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

CiVEC register ..........................................................200

ECAN1 Register Map (C1CTRL1.WIN = 0 or 1).........41

ECAN1 Register Map (C1CTRL1.WIN = 0) ................41

ECAN1 Register Map (C1CTRL1.WIN = 1) ................42

Frame Types.............................................................195

Modes of Operation ..................................................197

Overview...................................................................195

Input Capture.................................................................... 169

Registers .................................................................. 170

Input Change Notification ................................................. 136

Instruction Addressing Modes ............................................ 49

File Register Instructions ............................................ 49

Fundamental Modes Supported ................................. 50

MCU Instructions ........................................................ 49

Move and Accumulator Instructions............................ 50

Other Instructions ....................................................... 50

Instruction Set

ECAN Registers

Acceptance Filter Enable Register (CiFEN1)............207

Acceptance Filter Extended Identifier Register n

(CiRXFnEID).....................................................211

Acceptance Filter Mask Extended Identifier Register n

(CiRXMnEID) ....................................................213

Acceptance Filter Mask Standard Identifier Register n

(CiRXMnSID) ....................................................213

Acceptance Filter Standard Identifier Register n

Overview................................................................... 273

Summary .................................................................. 271

Instruction-Based Power-Saving Modes........................... 129

Idle............................................................................ 130

Sleep ........................................................................ 129

Internal RC Oscillator

(CiRXFnSID).....................................................210

Baud Rate Configuration Register 1 (CiCFG1).........205

Baud Rate Configuration Register 2 (CiCFG2).........206

Control Register 1 (CiCTRL1)...................................198

Control Register 2 (CiCTRL2)...................................199

FIFO Control Register (CiFCTRL) ............................201

FIFO Status Register (CiFIFO) .................................202

Filter 0-3 Buffer Pointer Register (CiBUFPNT1) .......207

Filter 12-15 Buffer Pointer Register (CiBUFPNT4) ...209

Filter 15-8 Mask Selection Register (CiFMSKSEL2).212

Filter 4-7 Buffer Pointer Register (CiBUFPNT2) .......208

Filter 7-0 Mask Selection Register (CiFMSKSEL1)...211

Filter 8-11 Buffer Pointer Register (CiBUFPNT3) .....208

Interrupt Code Register (CiVEC) ..............................200

Interrupt Enable Register (CiINTE)...........................204

Interrupt Flag Register (CiINTF) ...............................203

Receive Buffer Full Register 1 (CiRXFUL1)..............214

Receive Buffer Full Register 2 (CiRXFUL2)..............214

Receive Buffer Overflow Register 2 (CiRXOVF2).....215

Receive Overflow Register (CiRXOVF1) ..................215

ECAN Transmit/Receive Error Count Register (CiEC) .....205

ECAN TX/RX Buffer m Control Register (CiTRmnCON) ..216

Electrical Characteristics...................................................283

AC.....................................................................294, 336

Enhanced CAN Module.....................................................195

Equations

Use with WDT........................................................... 266

Internet Address ............................................................... 367

Interrupt Control and Status Registers ............................... 73

IECx............................................................................ 73

IFSx ............................................................................ 73

INTCON1.................................................................... 73

INTCON2.................................................................... 73

IPCx............................................................................ 73

Interrupt Setup Procedures............................................... 106

Initialization............................................................... 106

Interrupt Disable ....................................................... 106

Interrupt Service Routine.......................................... 106

Trap Service Routine................................................ 106

Interrupt Vector Table (IVT)................................................ 69

Interrupts Coincident with Power Save Instructions ......... 130

J

JTAG Boundary Scan Interface........................................ 261

JTAG Interface.................................................................. 267

M

Memory Organization ......................................................... 27

Microchip Internet Web Site.............................................. 367

Modes of Operation

Disable...................................................................... 197

Initialization............................................................... 197

Listen All Messages.................................................. 197

Listen Only................................................................ 197

Loopback .................................................................. 197

Normal Operation ..................................................... 197

MPLAB ASM30 Assembler, Linker, Librarian................... 280

MPLAB Integrated Development Environment Software.. 279

MPLAB PM3 Device Programmer .................................... 282

MPLAB REAL ICE In-Circuit Emulator System ................ 281

MPLINK Object Linker/MPLIB Object Librarian................ 280

Multi-Bit Data Shifter........................................................... 26

Device Operating Frequency ....................................120

Errata ..................................................................................10

F

Flash Program Memory.......................................................55

Control Registers ........................................................56

Operations ..................................................................56

Programming Algorithm ..............................................59

RTSP Operation..........................................................56

Table Instructions........................................................55

Flexible Configuration .......................................................261

N

H

NVM Module

Register Map .............................................................. 48

High Temperature Electrical Characteristics.....................333

O

I

Open-Drain Configuration................................................. 136

Output Compare ............................................................... 171

I/O Ports............................................................................135

Parallel I/O (PIO).......................................................135

Write/Read Timing ....................................................136

I²C

P

Packaging......................................................................... 343

Details....................................................................... 344

Marking..................................................................... 343

Peripheral Module Disable (PMD) .................................... 130

Pinout I/O Descriptions....................................................... 13

Operating Modes ......................................................181

Registers...................................................................181

In-Circuit Debugger...........................................................267

In-Circuit Emulation...........................................................261

In-Circuit Serial Programming (ICSP) .......................261, 267

DS70293F-page 364

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

PMD Module

Register Map............................................................... 48

PORTA

Register Map......................................................... 46, 47

PORTB

Register Map............................................................... 47

Power-on Reset (POR)....................................................... 66

Power-Saving Features .................................................... 129

Clock Frequency and Switching................................ 129

Program Address Space..................................................... 27

Construction................................................................ 51

Data Access from Program Memory

Standard Identifier)........................................... 213

CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 215

CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 215

CiTRBnSID (ECAN Buffer n Standard Identifier)..... 217,

218, 220

CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 216

CiVEC (ECAN Interrupt Code) ................................. 200

CLKDIV (Clock Divisor) ............................................ 125

CORCON (Core Control)...................................... 25, 74

DMACS0 (DMA Controller Status 0) ........................ 114

DMACS1 (DMA Controller Status 1) ........................ 116

DMAxCNT (DMA Channel x Transfer Count)........... 113

DMAxCON (DMA Channel x Control)....................... 110

DMAxPAD (DMA Channel x Peripheral Address) .... 113

DMAxREQ (DMA Channel x IRQ Select)................. 111

DMAxSTA (DMA Channel x RAM Start Address A). 112

DMAxSTB (DMA Channel x RAM Start Address B). 112

DSADR (Most Recent DMA RAM Address) ............. 117

I2CxCON (I2Cx Control)........................................... 183

I2CxMSK (I2Cx Slave Mode Address Mask)............ 187

I2CxSTAT (I2Cx Status)........................................... 185

IFS0 (Interrupt Flag Status 0)............................... 77, 84

IFS1 (Interrupt Flag Status 1)............................... 79, 86

IFS2 (Interrupt Flag Status 2)............................... 81, 88

IFS3 (Interrupt Flag Status 3)............................... 82, 89

IFS4 (Interrupt Flag Status 4)............................... 83, 90

INTCON1 (Interrupt Control 1) ................................... 75

INTCON2 (Interrupt Control 2) ................................... 76

INTTREG Interrupt Control and Status Register ...... 105

IPC0 (Interrupt Priority Control 0)............................... 91

IPC1 (Interrupt Priority Control 1)............................... 92

IPC11 (Interrupt Priority Control 11)......................... 101

IPC15 (Interrupt Priority Control 15)......................... 102

IPC16 (Interrupt Priority Control 16)......................... 103

IPC17 (Interrupt Priority Control 17)......................... 104

IPC2 (Interrupt Priority Control 2)............................... 93

IPC3 (Interrupt Priority Control 3)............................... 94

IPC4 (Interrupt Priority Control 4)............................... 95

IPC5 (Interrupt Priority Control 5)............................... 96

IPC6 (Interrupt Priority Control 6)............................... 97

IPC7 (Interrupt Priority Control 7)............................... 98

IPC8 (Interrupt Priority Control 8)............................... 99

IPC9 (Interrupt Priority Control 9)............................. 100

NVMCON (Flash Memory Control)............................. 57

NVMKEY (Nonvolatile Memory Key).......................... 58

OCxCON (Output Compare x Control)..................... 173

OSCCON (Oscillator Control)................................... 123

OSCTUN (FRC Oscillator Tuning)............................ 127

PLLFBD (PLL Feedback Divisor) ............................. 126

PMD1 (Peripheral Module Disable

Using Program Space Visibility........................... 54

Data Access from Program Memory

Using Table Instructions ..................................... 53

Data Access from, Address Generation...................... 52

Memory Map............................................................... 27

Table Read Instructions

TBLRDH ............................................................. 53

TBLRDL.............................................................. 53

Visibility Operation ...................................................... 54

Program Memory

Interrupt Vector ........................................................... 28

Organization................................................................ 28

Reset Vector ............................................................... 28

R

Reader Response............................................................. 368

Register Map

CRC ............................................................................ 46

Dual Comparator......................................................... 46

Parallel Master/Slave Port .......................................... 45

Real-Time Clock and Calendar................................... 46

Registers

AD1CHS0 (ADC1 Input Channel 0 Select ................ 231

AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 230

AD1CON1 (ADC1 Control 1) .................................... 225

AD1CON2 (ADC1 Control 2) .................................... 227

AD1CON3 (ADC1 Control 3) .................................... 228

AD1CON4 (ADC1 Control 4) .................................... 229

AD1CSSL (ADC1 Input Scan Select Low)................ 232

AD1PCFGL (ADC1 Port Configuration Low) ............ 232

CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer)........... 207

CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer)........... 208

CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer)......... 208

CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer)....... 209

CiCFG1 (ECAN Baud Rate Configuration 1) ............ 205

CiCFG2 (ECAN Baud Rate Configuration 2) ............ 206

CiCTRL1 (ECAN Control 1) ...................................... 198

CiCTRL2 (ECAN Control 2) ...................................... 199

CiEC (ECAN Transmit/Receive Error Count)............ 205

CiFCTRL (ECAN FIFO Control)................................ 201

CiFEN1 (ECAN Acceptance Filter Enable)............... 207

CiFIFO (ECAN FIFO Status)..................................... 202

CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection)..... 211,

212

CiINTE (ECAN Interrupt Enable) .............................. 204

CiINTF (ECAN Interrupt Flag)................................... 203

CiRXFnEID (ECAN Acceptance Filter n

Extended Identifier)........................................... 211

CiRXFnSID (ECAN Acceptance Filter n

Standard Identifier) ........................................... 210

CiRXFUL1 (ECAN Receive Buffer Full 1)................. 214

CiRXFUL2 (ECAN Receive Buffer Full 2)................. 214

CiRXMnEID (ECAN Acceptance Filter Mask n

Extended Identifier)........................................... 213

CiRXMnSID (ECAN Acceptance Filter Mask n

Control Register 1) ........................................... 131

PMD2 (Peripheral Module Disable

Control Register 2) ........................................... 132

PMD3 (Peripheral Module Disable

Control Register 3) ........................................... 133

RCON (Reset Control)................................................ 62

SPIxCON1 (SPIx Control 1) ..................................... 177

SPIxCON2 (SPIx Control 2) ..................................... 179

SPIxSTAT (SPIx Status and Control)....................... 176

SR (CPU Status) .................................................. 24, 74

T1CON (Timer1 Control) .......................................... 162

TCxCON (Input Capture x Control) .......................... 170

TxCON (Type B Time Base Control)........................ 166

TyCON (Type C Time Base Control)........................ 167

UxMODE (UARTx Mode) ......................................... 190

UxSTA (UARTx Status and Control) ........................ 192

Reset

DS70293F-page 365

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

Illegal Opcode.......................................................61, 68

Trap Conflict..........................................................67, 68

Uninitialized W Register........................................61, 68

Reset Sequence..................................................................69

Resets.................................................................................61

OC/PWM................................................................... 303

Output Compare (OCx)............................................. 302

Reset, Watchdog Timer, Oscillator Start-up Timer

and Power-up Timer......................................... 298

Timer1, 2 and 3 External Clock ................................ 300

Timing Requirements

ADC Conversion (10-bit mode)................................. 341

ADC Conversion (12-bit Mode)................................. 341

CLKO and I/O ........................................................... 297

External Clock........................................................... 295

Input Capture............................................................ 302

SPIx Master Mode (CKE = 0) ................................... 337

SPIx Module Master Mode (CKE = 1) ...................... 337

SPIx Module Slave Mode (CKE = 0) ........................ 338

SPIx Module Slave Mode (CKE = 1) ........................ 338

Timing Specifications

S

Serial Peripheral Interface (SPI) .......................................175

Software Reset Instruction (SWR) ......................................67

Software Simulator (MPLAB SIM).....................................281

Software Stack Pointer, Frame Pointer

CALLL Stack Frame....................................................49

Special Features of the CPU.............................................261

SPI Module

SPI1 Register Map......................................................37

Symbols Used in Opcode Descriptions.............................272

System Control

10-bit A/D Conversion Requirements ....................... 327

12-bit A/D Conversion Requirements ....................... 325

CAN I/O Requirements............................................. 320

I2Cx Bus Data Requirements (Master Mode)........... 317

I2Cx Bus Data Requirements (Slave Mode)............. 319

Output Compare Requirements................................ 302

PLL Clock ......................................................... 296, 336

Reset, Watchdog Timer,

Register Map.........................................................47, 48

T

Temperature and Voltage Specifications

AC.....................................................................294, 336

Timer1...............................................................................161

Timer2/3............................................................................163

Timing Characteristics

Oscillator Start-up Timer, Power-up Timer

CLKO and I/O ...........................................................297

Timing Diagrams

and Brown-out Reset Requirements ................ 299

Simple OC/PWM Mode Requirements ..................... 303

Timer1 External Clock Requirements....................... 300

Timer2 External Clock Requirements....................... 301

Timer3 External Clock Requirements....................... 301

10-bit A/D Conversion (CHPS<1:0> = 01,

SIMSAM = 0, ASAM = 0,

SSRC<2:0> = 000) ...........................................326

10-bit A/D Conversion (CHPS<1:0> = 01,

SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111,

SAMC<4:0> = 00001).......................................326

10-bit A/D Conversion (CHPS<1:0> = 01, SIMSAM = 0,

ASAM = 1, SSRC<2:0> = 111,

SAMC<4:0> = 00001).......................................326

12-bit A/D Conversion

(ASAM = 0, SSRC<2:0> = 000)........................324

Brown-out Situations...................................................67

ECAN I/O ..................................................................320

External Clock...........................................................295

I2Cx Bus Data (Master Mode) ..................................316

I2Cx Bus Data (Slave Mode) ....................................318

I2Cx Bus Start/Stop Bits (Master Mode) ...................316

I2Cx Bus Start/Stop Bits (Slave Mode).....................318

Input Capture (CAPx)................................................302

U

UART Module

UART1 Register Map............................................ 36, 37

Universal Asynchronous Receiver Transmitter (UART) ... 189

Using the RCON Status Bits............................................... 68

V

Voltage Regulator (On-Chip) ............................................ 265

W

Watchdog Time-out Reset (WDTR).................................... 67

Watchdog Timer (WDT)............................................ 261, 266

Programming Considerations ................................... 266

WWW Address ................................................................. 367

WWW, On-Line Support ..................................................... 10

DS70293F-page 366

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://microchip.com/support

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the

registration instructions.

DS70293F-page 367

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip

product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our

documentation can better serve you, please FAX your comments to the Technical Publications Manager at

(480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

TO:

RE:

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Reader Response

Total Pages Sent ________

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and

PIC24HJ128GPX02/X04

DS70293F

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS70293F-page 368

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PIC 24 HJ 32 GP3 02 T E / SP - XXX

a) PIC24HJ32GP302-E/SP:

General Purpose PIC24H, 32 KB program

memory, 28-pin, Extended temperature,

SPDIP package.

Microchip Trademark

Architecture

Flash Memory Family

Program Memory Size (KB)

Product Group

Pin Count

Tape and Reel Flag (if applicable)

Temperature Range

Package

Pattern

Architecture:

24

=

16-bit Microcontroller

Flash Memory Family: HJ

Flash program memory, 3.3V

Product Group:

GP2

GP3

GP8

=

General Purpose family

Pin Count:

02

04

=

28-pin

44-pin

Temperature Range:

I

E

H

=

-40°C to+85°C (Industrial)

-40°C to+125°C (Extended)

-40°C to+150°C (High)

Package:

SP

SO

ML

MM

PT

=

Skinny Plastic Dual In-Line - 300 mil body (SPDIP)

Plastic Small Outline - Wide - 300 mil body (SOIC)

Plastic Quad, No Lead Package - 8x8 mm body (QFN)

Plastic Quad, No Lead Package - 6x6x0.9 mm body (QFN-S)

Plastic Thin Quad Flatpack - 10x10x1 mm body (TQFP)

DS70293F-page 369

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

Germany - Munich

Tel: 49-89-627-144-0

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Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hangzhou

Tel: 86-571-2819-3187

Fax: 86-571-2819-3189

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-330-9305

Los Angeles

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Toronto

Mississauga, Ontario,

Canada

China - Xiamen

Tel: 905-673-0699

Fax: 905-673-6509

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

08/02/11

DS70293F-page 372


型号：	PIC24HJ128GP804-H/ML
厂家：	MICROCHIP
描述：	16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQCC44, 8 X 8 MM, LEAD FREE, PLASTIC, QFN-44
文件：	总371页 (文件大小：2327K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC24HJ128GP804-H/ML [MICROCHIP]

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