PIC24H_技术文档

PIC24H Family

Data Sheet

High-Performance, 16-bit

Microcontrollers

Preliminary

DS70175D

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

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OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

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suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its

PICmicro^®8-bit MCUs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS70175D-page ii

Preliminary

PIC24H

High-Performance, 16-bit Microcontrollers

• 4 mA sink on all I/O pins

Operating Range:

• DC – 40 MIPS (40 MIPS @ 3.0-3.6V,

-40°C to +85°C)

On-Chip Flash and SRAM:

• Flash program memory, up to 256 Kbytes

• Industrial temperature range (-40°C to +85°C)

• Data SRAM, up to 16 Kbytes (includes 2 Kbytes

of DMA RAM)

High-Performance DSC CPU:

• Modified Harvard architecture

• C compiler optimized instruction set

• 16-bit wide data path

System Management:

• Flexible clock options:

- External, crystal, resonator, internal RC

- Fully integrated PLL

• 24-bit wide instructions

• Linear program memory addressing up to 4M

instruction words

- Extremely low jitter PLL

• Power-up Timer

• Linear data memory addressing up to 64 Kbytes

• 71 base instructions: mostly 1 word/1 cycle

• Sixteen 16-bit General Purpose Registers

• Flexible and powerful Indirect Addressing modes

• Software stack

• Oscillator Start-up Timer/Stabilizer

• Watchdog Timer with its own RC oscillator

• Fail-Safe Clock Monitor

• Reset by multiple sources

• 16 x 16 multiply operations

Power Management:

• 32/16 and 16/16 divide operations

• Up to ±16-bit data shifts

• On-chip 2.5V voltage regulator

• Switch between clock sources in real time

• Idle, Sleep and Doze modes with fast wake-up

Direct Memory Access (DMA):

• 8-channel hardware DMA

Timers/Capture/Compare/PWM:

• 2 Kbytes dual ported DMA buffer area

(DMA RAM) to store data transferred via DMA:

• Timer/Counters, up to nine 16-bit timers:

- Can pair up to make four 32-bit timers

- Allows data transfer between RAM and a

peripheral while CPU is executing code

(no cycle stealing)

- 1 timer runs as Real-Time Clock with external

32.768 kHz oscillator

• Most peripherals support DMA

- Programmable prescaler

• Input Capture (up to 8 channels):

- Capture on up, down or both edges

- 16-bit capture input functions

- 4-deep FIFO on each capture

• Output Compare (up to 8 channels):

- Single or Dual 16-Bit Compare mode

- 16-bit Glitchless PWM mode

Interrupt Controller:

• 5-cycle latency

• 118 interrupt vectors

• Up to 61 available interrupt sources

• Up to 5 external interrupts

• 7 programmable priority levels

• 5 processor exceptions

Digital I/O:

• Up to 85 programmable digital I/O pins

• Wake-up/Interrupt-on-Change on up to 24 pins

• Output pins can drive from 3.0V to 3.6V

• All digital input pins are 5V tolerant

Preliminary

DS70175D-page 1

PIC24H

Communication Modules:

Analog-to-Digital Converters:

• 3-wire SPI (up to 2 modules):

• Up to two A/D modules in a device

- Framing supports I/O interface to simple

codecs

• 10-bit, 1.1 Msps or 12-bit, 500 ksps conversion:

- 2, 4 or 8 simultaneous samples

- Supports 8-bit and 16-bit data

- Up to 32 input channels with auto-scanning

- Supports all serial clock formats and

sampling modes

- Conversion start can be manual or

synchronized with 1 of 4 trigger sources

• I²C™ (up to 2 modules):

- Conversion possible in Sleep mode

- ±2 LSb max integral nonlinearity

- ±1 LSb max differential nonlinearity

- Full Multi-Master Slave mode support

- 7-bit and 10-bit addressing

- Bus collision detection and arbitration

- Integrated signal conditioning

- Slave address masking

CMOS Flash Technology:

• Low-power, high-speed Flash technology

• Fully static design

• UART (up to 2 modules):

- Interrupt on address bit detect

- Interrupt on UART error

• 3.3V (±10%) operating voltage

• Industrial temperature

- Wake-up on Start bit from Sleep mode

- 4-character TX and RX FIFO buffers

- LIN bus support

• Low-power consumption

Packaging:

- IrDA^®encoding and decoding in hardware

• 100-pin TQFP (14x14x1 mm and 12x12x1 mm)

• 64-pin TQFP (10x10x1 mm)

- High-Speed Baud mode

- Hardware Flow Control with CTS and RTS

• Enhanced CAN (ECAN™ module) 2.0B active

(up to 2 modules):

Note:

See the device variant tables for exact

peripheral features per device.

- Up to 8 transmit and up to 32 receive buffers

- 16 receive filters and 3 masks

- Loopback, Listen Only and Listen All

Messages modes for diagnostics and bus

monitoring

- Wake-up on CAN message

- Automatic processing of Remote

Transmission Requests

- FIFO mode using DMA

- DeviceNet™ addressing support

DS70175D-page 2

Preliminary

PIC24H

PIC24H PRODUCT FAMILIES

The PIC24H General Purpose Family is ideal for a wide

variety of 16-bit MCU embedded applications. The

device names, pin counts, memory sizes and periph-

eral availability of each family are listed below, followed

by their pinout diagrams.

PIC24H General Purpose Family Variants

Program

Device

Pins

Flash

Packages

Memory (KB)

PIC24HJ64GP206

PIC24HJ64GP210

PIC24HJ64GP506

PIC24HJ64GP510

64

100

64

8

9

8

0

1 ADC,

18 ch

2

1

2

0

1

0

1

0

2

53

85

53

85

53

85

53

85

53

85

53

85

PT

PF, PT

PT

1 ADC,

32 ch

64

8

1 ADC,

18 ch

100

64

8

1 ADC,

32 ch

PF, PT

PT

PIC24HJ128GP206 64

PIC24HJ128GP210 100

PIC24HJ128GP506 64

PIC24HJ128GP510 100

PIC24HJ128GP306 64

PIC24HJ128GP310 100

PIC24HJ256GP206 64

PIC24HJ256GP210 100

PIC24HJ256GP610 100

128

256

8

1 ADC,

18 ch

8

1 ADC,

32 ch

PF, PT

PT

8

1 ADC,

18 ch

8

1 ADC,

32 ch

PF, PT

PT

16

1 ADC,

18 ch

1 ADC,

32 ch

PF, PT

PT

1 ADC,

18 ch

1 ADC,

32 ch

PF, PT

2 ADC,

32 ch

Note 1: RAM size is inclusive of 2 Kbytes DMA RAM.

2: Maximum I/O pin count includes pins shared by the peripheral functions.

Preliminary

DS70175D-page 3

PIC24H

Pin Diagrams

64-Pin TQFP

RG15

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

OC1/RD0

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6

2

3

4

IC4/INT4/RD11

SDI2/CN9/RG7

5

IC3/INT3/RD10

SDO2/CN10/RG8

MCLR

6

IC2/U1CTS/INT2/RD9

IC1/INT1/RD8

7

SS2/T5CK/CN11/RG9

VSS

8

VSS

PIC24HJ64GP206

PIC24HJ128GP206

PIC24HJ256GP206

9

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

VDD

10

11

12

13

14

15

16

AN5/IC8/CN7/RB5

AN4/IC7/CN6/RB4

AN3/CN5/RB3

SCL1/RG2

SDA1/RG3

AN2/SS1/CN4/RB2

PGC3/EMUC3/AN1/VREF-/CN3/RB1

PGD3/EMUD3/AN0/VREF+/CN2/RB0

U1RTS/SCK1/INT0/RF6

U1RX/SDI1/RF2

U1TX/SDO1/RF3

Note:

The PIC24HJ64GP206 device does not have the SCL2 and SDA2 pins.

DS70175D-page 4

Preliminary

PIC24H

Pin Diagrams (Continued)

64-Pin TQFP

RG15

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

OC1/RD0

2

3

4

IC4/INT4/RD11

SDI2/CN9/RG7

5

IC3/INT3/RD10

SDO2/CN10/RG8

MCLR

6

IC2/U1CTS/INT2/RD9

IC1/INT1/RD8

7

PIC24HJ128GP306

SS2/T5CK/CN11/RG9

VSS

8

VSS

9

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

VDD

10

11

12

13

14

15

16

AN5/IC8/CN7/RB5

AN4/IC7/CN6/RB4

AN3/CN5/RB3

SCL1/RG2

SDA1/RG3

AN2/SS1/CN4/RB2

PGC3/EMUC3/AN1/VREF-/CN3/RB1

PGD3/EMUD3/AN0/VREF+/CN2/RB0

U1RTS/SCK1/INT0/RF6

U1RX/SDI1/RF2

U1TX/SDO1/RF3

Preliminary

DS70175D-page 5

PIC24H

Pin Diagrams (Continued)

64-Pin TQFP

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

PGD2/EMUD2/SOSCI/T4CK/CN1/RC13

OC1/RD0

COFS/RG15

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

SCK2/CN8/RG6

1

2

3

4

IC4/INT4/RD11

SDI2/CN9/RG7

5

IC3/INT3/RD10

SDO2/CN10/RG8

MCLR

6

IC2/U1CTS/INT2/RD9

IC1/INT1/RD8

7

SS2/T5CK/CN11/RG9

VSS

8

VSS

PIC24HJ64GP506

PIC24HJ128GP506

9

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

VDD

10

11

12

13

14

15

16

AN5/IC8/CN7/RB5

AN4/IC7/CN6/RB4

AN3/CN5/RB3

SCL1/RG2

SDA1/RG3

AN2/SS1/CN4/RB2

PGC3/EMUC3/AN1/VREF-/CN3/RB1

PGD3/EMUD3/AN0/VREF+/CN2/RB0

U1RTS/SCK1/INT0/RF6

U1RX/SDI1/RF2

U1TX/SDO1/RF3

DS70175D-page 6

Preliminary

PIC24H

Pin Diagrams (Continued)

100-Pin TQFP

V

SS

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

RG15

1

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

VDD

2

PGD2/EMUD2/SOSCI/CN1/RC13

OC1/RD0

AN29/RE5

AN30/RE6

3

4

IC4/RD11

AN31/RE7

5

IC3/RD10

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3

AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

SDI2/CN9/RG7

6

IC2/RD9

7

IC1/RD8

8

INT4/RA15

9

INT3/RA14

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

VSS

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

SDO2/CN10/RG8

MCLR

PIC24HJ64GP210

PIC24HJ128GP210

PIC24HJ128GP310

PIC24HJ256GP210

SS2/CN11/RG9

VDD

VSS

TDO/RA5

VDD

TDI/RA4

TMS/RA0

AN20/INT1/RA12

SDA2/RA3

SCL2/RA2

SCL1/RG2

SDA1/RG3

SCK1/INT0/RF6

SDI1/RF7

AN21/INT2/RA13

AN5/CN7/RB5

AN4/CN6/RB4

AN3/CN5/RB3

AN2/SS1/CN4/RB2

PGC3/EMUC3/AN1/CN3/RB1

PGD3/EMUD3/AN0/CN2/RB0

SDO1/RF8

U1RX/RF2

U1TX/RF3

Preliminary

DS70175D-page 7

PIC24H

Pin Diagrams (Continued)

100-Pin TQFP

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

V

SS

1

RG15

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

VDD

2

PGD2/EMUD2/SOSCI/CN1/RC13

OC1/RD0

3

AN29/RE5

AN30/RE6

4

IC4/RD11

AN31/RE7

5

IC3/RD10

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3

AN19/T5CK/T8CK/RC4

6

IC2/RD9

7

IC1/RD8

8

INT4/RA15

9

INT3/RA14

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

SCK2/CN8/RG6

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

VSS

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

PIC24HJ64GP510

PIC24HJ128GP510

SS2/CN11/RG9

VDD

VSS

TDO/RA5

VDD

TDI/RA4

TMS/RA0

AN20/INT1/RA12

SDA2/RA3

SCL2/RA2

SCL1/RG2

SDA1/RG3

SCK1/INT0/RF6

SDI1/RF7

AN21/INT2/RA13

AN5/CN7/RB5

AN4/CN6/RB4

AN3/CN5/RB3

AN2/SS1/CN4/RB2

PGC3/EMUC3/AN1/CN3/RB1

PGD3/EMUD3/AN0/CN2/RB0

SDO1/RF8

U1RX/RF2

U1TX/RF3

DS70175D-page 8

Preliminary

PIC24H

Pin Diagrams (Continued)

100-Pin TQFP

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VSS

1

RG15

PGC2/EMUC2/SOSCO/T1CK/CN0/RC14

VDD

2

PGD2/EMUD2/SOSCI/CN1/RC13

AN29/RE5

AN30/RE6

3

OC1/RD0

IC4/RD11

IC3/RD10

IC2/RD9

4

AN31/RE7

5

AN16/T2CK/T7CK/RC1

AN17/T3CK/T6CK/RC2

AN18/T4CK/T9CK/RC3

AN19/T5CK/T8CK/RC4

SCK2/CN8/RG6

6

7

IC1/RD8

8

INT4/RA15

9

INT3/RA14

10

11

12

VSS

SDI2/CN9/RG7

SDO2/CN10/RG8

MCLR

OSC2/CLKO/RC15

OSC1/CLKIN/RC12

PIC24HJ256GP610

13

14

15

16

17

18

19

20

21

22

23

24

25

SS2/CN11/RG9

VDD

VSS

TDO/RA5

VDD

TDI/RA4

TMS/RA0

AN20/INT1/RA12

SDA2/RA3

SCL2/RA2

SCL1/RG2

SDA1/RG3

SCK1/INT0/RF6

SDI1/RF7

AN21/INT2/RA13

AN5/CN7/RB5

AN4/CN6/RB4

AN3/CN5/RB3

AN2/SS1/CN4/RB2

PGC3/EMUC3/AN1/CN3/RB1

PGD3/EMUD3/AN0/CN2/RB0

SDO1/RF8

U1RX/RF2

U1TX/RF3

Preliminary

DS70175D-page 9

PIC24H

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 13

2.0 CPU............................................................................................................................................................................................ 17

3.0 Memory Organization................................................................................................................................................................. 25

4.0 Flash Program Memory.............................................................................................................................................................. 55

5.0 Resets ....................................................................................................................................................................................... 61

6.0 Interrupt Controller ..................................................................................................................................................................... 67

7.0 Direct Memory Access (DMA) .................................................................................................................................................. 113

8.0 Oscillator Configuration ............................................................................................................................................................ 127

9.0 Power-Saving Features............................................................................................................................................................ 135

10.0 I/O Ports ................................................................................................................................................................................... 137

11.0 Timer1 ...................................................................................................................................................................................... 139

12.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................ 141

13.0 Input Capture............................................................................................................................................................................ 147

14.0 Output Compare....................................................................................................................................................................... 149

15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 153

2

16.0 Inter-Integrated Circuit (I C)..................................................................................................................................................... 161

17.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 171

18.0 Enhanced CAN Module............................................................................................................................................................ 179

19.0 10-bit/12-bit A/D Converter....................................................................................................................................................... 209

20.0 Special Features ...................................................................................................................................................................... 223

21.0 Instruction Set Summary.......................................................................................................................................................... 231

22.0 Development Support............................................................................................................................................................... 239

23.0 Electrical Characteristics.......................................................................................................................................................... 243

24.0 Packaging Information.............................................................................................................................................................. 277

Appendix A: Revision History............................................................................................................................................................. 281

Index ................................................................................................................................................................................................. 283

The Microchip Web Site..................................................................................................................................................................... 287

Customer Change Notification Service .............................................................................................................................................. 287

Customer Support.............................................................................................................................................................................. 287

Reader Response .............................................................................................................................................................................. 288

Product Identification System............................................................................................................................................................. 289

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DS70175D-page 10

Preliminary

PIC24H

control applications. Further, Direct Memory Access

(DMA) enables overhead-free transfer of data between

several peripherals and a dedicated DMA RAM.

Reliable, field programmable Flash program memory

ensures scalability of applications that use PIC24H

devices.

1.0

DEVICE OVERVIEW

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Figure 1-1 shows a general block diagram of the

various core and peripheral modules in the PIC24H

family of devices, while Table 1-1 lists the functions of

the various pins shown in the pinout diagrams.

This document contains device specific information for

the following devices:

• PIC24HJ64GP206

• PIC24HJ64GP210

• PIC24HJ64GP506

• PIC24HJ64GP510

• PIC24HJ128GP206

• PIC24HJ128GP210

• PIC24HJ128GP506

• PIC24HJ128GP510

• PIC24HJ128GP306

• PIC24HJ128GP310

• PIC24HJ256GP206

• PIC24HJ256GP210

• PIC24HJ256GP610

The PIC24H device family includes devices with differ-

ent pin counts (64 and 100 pins), different program

memory sizes (64 Kbytes, 128 Kbytes and 256 Kbytes)

and different RAM sizes (8 Kbytes and 16 Kbytes).

This makes these families suitable for a wide variety of

high-performance digital signal control applications.

The devices are pin compatible with the dsPIC33F fam-

ily of devices, and also share a very high degree of

compatibility with the dsPIC30F family devices. This

allows easy migration between device families as may

be necessitated by the specific functionality, computa-

tional resource and system cost requirements of the

application.

The PIC24H device family employs a powerful 16-bit

architecture, ideal for applications that rely on

high-speed, repetitive computations, as well as control.

The 17 x 17 multiplier, hardware support for division

operations, multi-bit data shifter, a large array of 16-bit

working registers and a wide variety of data addressing

modes, together provide the PIC24H Central

Processing Unit (CPU) with extensive mathematical

processing capability. Flexible and deterministic

interrupt handling, coupled with a powerful array of

peripherals, renders the PIC24H devices suitable for

Preliminary

DS70175D-page 13

PIC24H

FIGURE 1-1:

PIC24H GENERAL BLOCK DIAGRAM

PSV & Table

Data Access

Control Block

Data Bus

Interrupt

Controller

PORTA

PORTB

16

8

DMA

RAM

Data Latch

X RAM

23

PCH PCL

Program Counter

PCU

23

Address

Latch

Loop

Control

Logic

Stack

Control

Logic

DMA

16

Controller

23

16

PORTC

PORTD

PORTE

PORTF

PORTG

Address Generator Units

Address Latch

Program Memory

Data Latch

EA MUX

Address Bus

ROM Latch

24

16

Instruction

Decode &

Control

Instruction Reg

16

Control Signals

to Various Blocks

17 x 17 Multiplier

Divide Support

16 x 16

W Register Array

Power-up

Timer

Timing

Generation

OSC2/CLKO

OSC1/CLKI

16

Oscillator

Start-up Timer

FRC/LPRC

Oscillators

Power-on

Reset

16-bit ALU

Precision

Band Gap

Reference

Watchdog

Timer

16

Brown-out

Reset

Voltage

Regulator

VDDCORE/VCAP

VDD, VSS

MCLR

Timers

1-9

ADC1,2

ECAN1,2

UART1,2

OC/

IC1-8

CN1-23

SPI1,2

I2C1,2

PWM1-8

Note:

Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins

and features present on each device.

DS70175D-page 14

Preliminary

PIC24H

TABLE 1-1:

PINOUT I/O DESCRIPTIONS

Type

Buffer

Type

Pin Name

Description

AN0-AN31

AVDD

I

Analog

Analog input channels.

P

Positive supply for analog modules.

AVSS

Ground reference for analog modules.

CLKI

I

ST/CMOS External clock source input. Always associated with OSC1 pin function.

CLKO

O

—

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.

Optionally functions as CLKO in RC and EC modes. Always associated with OSC2

pin function.

CN0-CN23

I

ST

Input change notification inputs.

Can be software programmed for internal weak pull-ups on all inputs.

C1RX

C1TX

C2RX

C2TX

I

O

I

ST

—

ST

—

ECAN1 bus receive pin.

ECAN1 bus transmit pin.

ECAN2 bus receive pin.

ECAN2 bus transmit pin.

O

PGD1/EMUD1

PGC1/EMUC1

PGD2/EMUD2

PGC2/EMUC2

PGD3/EMUD3

PGC3/EMUC3

I/O

ST

Data I/O pin for programming/debugging communication channel 1.

Clock input pin for programming/debugging communication channel 1.

Data I/O pin for programming/debugging communication channel 2.

Clock input pin for programming/debugging communication channel 2.

Data I/O pin for programming/debugging communication channel 3.

Clock input pin for programming/debugging communication channel 3.

I

I/O

I

I/O

I

IC1-IC8

I

ST

Capture inputs 1 through 8.

INT0

INT1

INT2

INT3

INT4

I

ST

External interrupt 0.

External interrupt 1.

External interrupt 2.

External interrupt 3.

External interrupt 4.

MCLR

I/P

ST

Master Clear (Reset) input. This pin is an active-low Reset to the device.

OCFA

OCFB

OC1-OC8

I

O

ST

—

Compare Fault A input (for Compare Channels 1, 2, 3 and 4).

Compare Fault B input (for Compare Channels 5, 6, 7 and 8).

Compare outputs 1 through 8.

OSC1

OSC2

I

ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.

I/O

—

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.

Optionally functions as CLKO in RC and EC modes.

RA0-RA7

RA9-RA10

RA12-RA15

I/O

ST

PORTA is a bidirectional I/O port.

RB0-RB15

I/O

ST

PORTB is a bidirectional I/O port.

PORTC is a bidirectional I/O port.

RC1-RC4

RC12-RC15

I/O

ST

RD0-RD15

RE0-RE7

I/O

ST

PORTD is a bidirectional I/O port.

PORTE is a bidirectional I/O port.

PORTF is a bidirectional I/O port.

RF0-RF8

RF12-RF13

RG0-RG3

RG6-RG9

RG12-RG15

I/O

ST

PORTG is a bidirectional I/O port.

Legend: CMOS = CMOS compatible input or output; Analog = Analog input

ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power

Preliminary

DS70175D-page 15

PIC24H

TABLE 1-1:

PINOUT I/O DESCRIPTIONS (CONTINUED)

Type

Buffer

Type

Pin Name

Description

SCK1

SDI1

SDO1

SS1

SCK2

SDI2

SDO2

SS2

I/O

I

O

I/O

I

ST

—

ST

—

Synchronous serial clock input/output for SPI1.

SPI1 data in.

SPI1 data out.

SPI1 slave synchronization or frame pulse I/O.

Synchronous serial clock input/output for SPI2.

SPI2 data in.

O

I/O

SPI2 data out.

SPI2 slave synchronization or frame pulse I/O.

ST

SCL1

SDA1

SCL2

SDA2

I/O

ST

Synchronous serial clock input/output for I2C1.

Synchronous serial data input/output for I2C1.

Synchronous serial clock input/output for I2C2.

Synchronous serial data input/output for I2C2.

SOSCI

I

ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise.

SOSCO

O

—

32.768 kHz low-power oscillator crystal output.

TMS

TCK

TDI

I

ST

—

JTAG Test mode select pin.

JTAG test clock input pin.

JTAG test data input pin.

JTAG test data output pin.

TDO

O

T1CK

T2CK

T3CK

T4CK

T5CK

T6CK

T7CK

T8CK

T9CK

I

ST

Timer1 external clock input.

Timer2 external clock input.

Timer3 external clock input.

Timer4 external clock input.

Timer5 external clock input.

Timer6 external clock input.

Timer7 external clock input.

Timer8 external clock input.

Timer9 external clock input.

U1CTS

U1RTS

U1RX

U1TX

U2CTS

U2RTS

U2RX

U2TX

I

O

I

O

I

O

I

O

ST

—

ST

—

ST

—

ST

—

UART1 clear to send.

UART1 ready to send.

UART1 receive.

UART1 transmit.

UART2 clear to send.

UART2 ready to send.

UART2 receive.

UART2 transmit.

VDD

P

I

—

Positive supply for peripheral logic and I/O pins.

CPU logic filter capacitor connection.

Ground reference for logic and I/O pins.

Analog voltage reference (high) input.

Analog voltage reference (low) input.

VDDCORE

VSS

—

VREF+

VREF-

Analog

I

Legend: CMOS = CMOS compatible input or output; Analog = Analog input

ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power

DS70175D-page 16

Preliminary

PIC24H

2.2

Special MCU Features

2.0

CPU

The PIC24H features a 17-bit by 17-bit, single-cycle

multiplier. The multiplier can perform signed, unsigned

and mixed-sign multiplication. Using a 17-bit by 17-bit

multiplier for 16-bit by 16-bit multiplication makes

mixed-sign multiplication possible.

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

The PIC24H supports 16/16 and 32/16 integer divide

operations. All divide instructions are iterative

operations. They must be executed within a REPEAT

loop, resulting in a total execution time of 19 instruction

cycles. The divide operation can be interrupted during

any of those 19 cycles without loss of data.

The PIC24H CPU module has a 16-bit (data) modified

Harvard architecture with an enhanced instruction set

and addressing modes. The CPU has a 24-bit instruction

word with a variable length opcode field. The Program

Counter (PC) is 23 bits wide and addresses up to 4M x

24 bits of user program memory space. The actual

amount of program memory implemented varies by

device. A single-cycle instruction prefetch mechanism is

used to help maintain throughput and provides

predictable execution. All instructions execute in a single

cycle, with the exception of instructions that change the

program flow, the double word move (MOV.D) instruction

and the table instructions. Overhead-free, single-cycle

program loop constructs are supported using the

REPEATinstruction, which is interruptible at any point.

A multi-bit data shifter is used to perform up to a 16-bit,

left or right shift in a single cycle.

The PIC24H devices have sixteen, 16-bit working

registers in the programmer’s model. Each of the working

registers can serve as a data, address or address offset

register. The 16th working register (W15) operates as a

software Stack Pointer (SP) for interrupts and calls.

The PIC24H instruction set includes many addressing

modes and is designed for optimum C compiler

efficiency. For most instructions, the PIC24H is capable

of executing a data (or program data) memory read, a

working register (data) read, a data memory write and

a program (instruction) memory read per instruction

cycle. As a result, three parameter instructions can be

supported, allowing A + B = C operations to be

executed in a single cycle.

A block diagram of the CPU is shown in Figure 2-1,

and the programmer’s model for the PIC24H is shown

in Figure 2-2.

2.1

Data Addressing Overview

The data space can be linearly addressed as 32K words

or 64 Kbytes using an Address Generation Unit (AGU).

The upper 32 Kbytes of the data space memory map can

optionally be mapped into program space at any 16K

program word boundary defined by the 8-bit Program

Space Visibility Page (PSVPAG) register. The program

to data space mapping feature lets any instruction

access program space as if it were data space.

The data space also includes 2 Kbytes of DMA RAM,

which is primarily used for DMA data transfers, but may

be used as general purpose RAM.

Preliminary

DS70175D-page 17

PIC24H

FIGURE 2-1:

PIC24H CPU CORE BLOCK DIAGRAM

PSV & Table

Data Access

Control Block

X Data Bus

Interrupt

Controller

16

8

Data Latch

X RAM

DMA

RAM

23

16

PCH PCL

Program Counter

PCU

23

Address

Latch

Stack

Control

Logic

Loop

Control

Logic

23

16

DMA

Controller

Address Generator Units

Address Latch

Program Memory

Data Latch

EA MUX

Address Bus

ROM Latch

24

16

Instruction

Decode &

Control

Instruction Reg

16

17 x 17

Multiplier

Control Signals

to Various Blocks

16 x 16

W Register Array

Divide Support

16

16-bit ALU

16

To Peripheral Modules

DS70175D-page 18

Preliminary

PIC24H

FIGURE 2-2:

PIC24H PROGRAMMER’S MODEL

D15

D0

W0/WREG

W1

PUSH.S Shadow

DO Shadow

W2

W3

Legend

W4

W5

W6

W7

Working Registers

W8

W9

W10

W11

W12

W13

W14/Frame Pointer

W15/Stack Pointer

SPLIM

Stack Pointer Limit Register

Program Counter

PC22

PC0

0

7

TBLPAG

Data Table Page Address

7

0

PSVPAG

Program Space Visibility Page Address

15

0

RCOUNT

REPEAT Loop Counter

15

Core Configuration Register

CORCON

—

DC

N

Z

C

IPL2 IPL1 IPL0 RA

SRL

OV

STATUS Register

SRH

Preliminary

DS70175D-page 19

PIC24H

2.3

CPU Control Registers

REGISTER 2-1:

SR: CPU STATUS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

DC

bit 15

bit 8

R/W-0⁽¹⁾

R/W-0⁽²⁾

IPL<2:0>⁽²⁾

R/W-0⁽²⁾

R-0

RA

R/W-0

N

R/W-0

OV

R/W-0

Z

R/W-0

C

bit 7

bit 0

Legend:

C = Clear only bit

S = Set only bit

‘1’ = Bit is set

R = Readable bit

W = Writable bit

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n = Value at POR

x = Bit is unknown

bit 15-9

bit 8

Unimplemented: Read as ‘0’

DC: MCU ALU Half Carry/Borrow bit

1= A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data)

of the result occurred

0= No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized

data) of the result occurred

bit 7-5

IPL<2:0>: CPU Interrupt Priority Level Status bits⁽²⁾

111= CPU Interrupt Priority Level is 7 (15), user interrupts disabled

110= CPU Interrupt Priority Level is 6 (14)

101= CPU Interrupt Priority Level is 5 (13)

100= CPU Interrupt Priority Level is 4 (12)

011= CPU Interrupt Priority Level is 3 (11)

010= CPU Interrupt Priority Level is 2 (10)

001= CPU Interrupt Priority Level is 1 (9)

000= CPU Interrupt Priority Level is 0 (8)

bit 4

bit 3

bit 2

RA: REPEAT Loop Active bit

1= REPEAT loop in progress

0= REPEAT loop not in progress

N: MCU ALU Negative bit

1= Result was negative

0= Result was non-negative (zero or positive)

OV: MCU ALU Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which

causes the sign bit to change state.

1= Overflow occurred for signed arithmetic (in this arithmetic operation)

0= No overflow occurred

bit 1

Z: MCU ALU Zero bit

1= An operation which affects the Z bit has set it at some time in the past

0= The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result)

Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when

IPL<3> = 1.

2: The IPL<2:0> Status bits are read only when NSTDIS = 1(INTCON1<15>).

DS70175D-page 20

Preliminary

PIC24H

REGISTER 2-1:

bit 0

SR: CPU STATUS REGISTER (CONTINUED)

C: MCU ALU Carry/Borrow bit

1= A carry-out from the Most Significant bit (MSb) of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when

IPL<3> = 1.

2: The IPL<2:0> Status bits are read only when NSTDIS = 1(INTCON1<15>).

Preliminary

DS70175D-page 21

PIC24H

REGISTER 2-2:

CORCON: CORE CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

R/C-0

IPL3⁽¹⁾

R/W-0

PSV

U-0

—

U-0

—

bit 7

Legend:

C = Clear only bit

W = Writable bit

‘x = Bit is unknown

R = Readable bit

0’ = Bit is cleared

-n = Value at POR

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

bit 15-4

bit 3

Unimplemented: Read as ‘0’

IPL3: CPU Interrupt Priority Level Status bit 3⁽¹⁾

1= CPU interrupt priority level is greater than 7

0= CPU interrupt priority level is 7 or less

bit 2

PSV: Program Space Visibility in Data Space Enable bit

1= Program space visible in data space

0= Program space not visible in data space

bit 1-0

Unimplemented: Read as ‘0’

Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.

DS70175D-page 22

Preliminary

PIC24H

2.4.3

MULTI-BIT DATA SHIFTER

2.4

Arithmetic Logic Unit (ALU)

The multi-bit data shifter is capable of performing up to

16-bit arithmetic or logic right shifts, or up to 16-bit left

shifts in a single cycle. The source can be either a

working register or a memory location.

The PIC24H ALU is 16 bits wide and is capable of addi-

tion, subtraction, bit shifts and logic operations. Unless

otherwise mentioned, arithmetic operations are 2’s

complement in nature. Depending on the operation, the

ALU may affect the values of the Carry (C), Zero (Z),

Negative (N), Overflow (OV) and Digit Carry (DC) Sta-

tus bits in the SR register. The C and DC Status bits

operate as Borrow and Digit Borrow bits, respectively,

for subtraction operations.

The shifter requires a signed binary value to determine

both the magnitude (number of bits) and direction of the

shift operation. A positive value shifts the operand right.

A negative value shifts the operand left. A value of ‘0’

does not modify the operand.

The ALU can perform 8-bit or 16-bit operations,

depending on the mode of the instruction that is used.

Data for the ALU operation can come from the W reg-

ister array, or data memory, depending on the address-

ing mode of the instruction. Likewise, output data from

the ALU can be written to the W register array or a data

memory location.

Refer to the “dsPIC30F/33F Programmer’s Reference

Manual” (DS70157) for information on the SR bits

affected by each instruction.

The PIC24H CPU incorporates hardware support for

both multiplication and division. This includes a dedi-

cated hardware multiplier and support hardware for

16-bit divisor division.

2.4.1

MULTIPLIER

Using the high-speed 17-bit x 17-bit multiplier, the ALU

supports unsigned, signed or mixed-sign operation in

several multiplication modes:

1. 16-bit x 16-bit signed

2. 16-bit x 16-bit unsigned

3. 16-bit signed x 5-bit (literal) unsigned

4. 16-bit unsigned x 16-bit unsigned

5. 16-bit unsigned x 5-bit (literal) unsigned

6. 16-bit unsigned x 16-bit signed

7. 8-bit unsigned x 8-bit unsigned

2.4.2

DIVIDER

The divide block supports 32-bit/16-bit and 16-bit/16-bit

signed and unsigned integer divide operations with the

following data sizes:

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0

and the remainder in W1. Sixteen-bit signed and

unsigned DIV instructions can specify any W register

for both the 16-bit divisor (Wn) and any W register

(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.

The divide algorithm takes one cycle per bit of divisor,

so both 32-bit/16-bit and 16-bit/16-bit instructions take

the same number of cycles to execute.

Preliminary

DS70175D-page 23

PIC24H

NOTES:

DS70175D-page 24

Preliminary

PIC24H

3.1

Program Address Space

3.0

MEMORY ORGANIZATION

The program address memory space of the PIC24H

devices is 4M instructions. The space is addressable by a

24-bit value derived from either the 23-bit Program Counter

(PC) during program execution, or from table operation

or data space remapping as described in Section 3.4

“Interfacing Program and Data Memory Spaces”.

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

User access to the program memory space is restricted

to the lower half of the address range (0x000000 to

0x7FFFFF). The exception is the use of TBLRD/TBLWT

operations, which use TBLPAG<7> to permit access to

the Configuration bits and Device ID sections of the

configuration memory space.

The PIC24H architecture features separate program

and data memory spaces and buses. This architecture

also allows the direct access of program memory from

the data space during code execution.

Memory maps for the PIC24H family of devices are

shown in Figure 3-1.

FIGURE 3-1:

PROGRAM MEMORY MAP FOR PIC24H FAMILY DEVICES

PIC24HJ64XXXXX

PIC24HJ128XXXXX

PIC24HJ256XXXXX

0x000000

0x000002

0x000004

GOTOInstruction

Reset Address

Interrupt Vector Table

Reserved

GOTOInstruction

Reset Address

GOTOInstruction

Reset Address

Interrupt Vector Table

Reserved

Interrupt Vector Table

Reserved

0x0000FE

0x000100

0x000104

0x0001FE

0x000200

Alternate Vector Table

User Program

Flash Memory

(22K instructions)

User Program

Flash Memory

(44K instructions)

User Program

Flash Memory

(88K instructions)

0x00ABFE

0x00AC00

0x0157FE

0x015800

Unimplemented

(Read ‘0’s)

0x02ABFE

0x02AC00

(Read ‘0’s)

Unimplemented

(Read ‘0’s)

0x7FFFFE

0x800000

Reserved

0xF7FFFE

0xF80000

Device Configuration

Registers

Device Configuration

Registers

Device Configuration

Registers

0xF80017

0xF80010

Reserved

DEVID (2)

Reserved

DEVID (2)

0xFEFFFE

0xFF0000

DEVID (2)

0xFFFFFE

Preliminary

DS70175D-page 25

PIC24H

3.1.1

PROGRAM MEMORY

ORGANIZATION

3.1.2

INTERRUPT AND TRAP VECTORS

All PIC24H devices reserve the addresses between

0x00000 and 0x000200 for hard-coded program exe-

cution vectors. A hardware Reset vector is provided to

redirect code execution from the default value of the

PC on device Reset to the actual start of code. A GOTO

instruction is programmed by the user at 0x000000,

with the actual address for the start of code at

0x000002.

The program memory space is organized in word-

addressable blocks. Although it is treated as 24 bits

wide, it is more appropriate to think of each address of

the program memory as a lower and upper word, with

the upper byte of the upper word being unimplemented.

The lower word always has an even address, while the

upper word has an odd address (Figure 3-2).

PIC24H devices also have two interrupt vector tables,

located from 0x000004 to 0x0000FF and 0x000100 to

0x0001FF. These vector tables allow each of the many

device interrupt sources to be handled by separate

Interrupt Service Routines (ISRs). A more detailed dis-

cussion of the interrupt vector tables is provided in

Section 6.1 “Interrupt Vector Table”.

Program memory addresses are always word-aligned

on the lower word, and addresses are incremented or

decremented by two during code execution. This

arrangement also provides compatibility with data

memory space addressing and makes it possible to

access data in the program memory space.

FIGURE 3-2:

PROGRAM MEMORY ORGANIZATION

least significant word

PC Address

most significant word

23

msw

Address

(lsw Address)

16

8

0

0x000001

0x000003

0x000005

0x000007

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

Instruction Width

DS70175D-page 26

Preliminary

PIC24H

All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported, so

care must be taken when mixing byte and word opera-

tions, or translating from 8-bit MCU code. If a mis-

aligned read or write is attempted, an address error

trap is generated. If the error occurred on a read, the

instruction underway is completed; if it occurred on a

write, the instruction will be executed but the write does

not occur. In either case, a trap is then executed, allow-

ing the system and/or user to examine the machine

state prior to execution of the address Fault.

3.2

Data Address Space

The PIC24H CPU has a separate 16-bit wide data

memory space. The data space is accessed using sep-

arate Address Generation Units (AGUs) for read and

write operations. Data memory maps of devices with

different RAM sizes are shown in Figure 3-3 and

Figure 3-4.

All Effective Addresses (EAs) in the data memory space

are 16 bits wide and point to bytes within the data space.

This arrangement gives a data space address range of

64 Kbytes or 32K words. The lower half of the data

memory space (that is, when EA<15> = 0) is used for

implemented memory addresses, while the upper half

(EA<15> = 1) is reserved for the Program Space

Visibility area (see Section 3.4.3 “Reading Data From

Program Memory Using Program Space Visibility”).

All byte loads into any W register are loaded into the

Least Significant Byte. The Most Significant Byte

(MSB) is not modified.

A sign-extend instruction (SE) is provided to allow

users to translate 8-bit signed data to 16-bit signed

values. Alternatively, for 16-bit unsigned data, users

can clear the Most Significant Byte of any W register by

executing a zero-extend (ZE) instruction on the

appropriate address.

PIC24H devices implement up to 16 Kbytes of data

memory. Should an EA point to a location outside of

this area, an all-zero word or byte will be returned.

3.2.1

DATA SPACE WIDTH

3.2.3

SFR SPACE

The data memory space is organized in byte address-

able, 16-bit wide blocks. Data is aligned in data

memory and registers as 16-bit words, but all data

space EAs resolve to bytes. The Least Significant

Bytes of each word have even addresses, while the

Most Significant Bytes have odd addresses.

The first 2 Kbytes of the Near Data Space, from 0x0000

to 0x07FF, is primarily occupied by Special Function

Registers (SFRs). These are used by the PIC24H core

and peripheral modules for controlling the operation of

the device.

SFRs are distributed among the modules that they

control, and are generally grouped together by module.

Much of the SFR space contains unused addresses;

these are read as ‘0’. A complete listing of implemented

SFRs, including their addresses, is shown in Table 3-1

through Table 3-31.

3.2.2

DATA MEMORY ORGANIZATION

AND ALIGNMENT

To maintain backward compatibility with PICmicro^®

MCU devices and improve data space memory usage

efficiency, the PIC24H instruction set supports both

word and byte operations. As a consequence of byte

accessibility, all effective address calculations are inter-

nally scaled to step through word-aligned memory. For

example, the core recognizes that Post-Modified

Register Indirect Addressing mode [Ws++] will result in

a value of Ws + 1 for byte operations and Ws + 2 for

word operations.

Note:

The actual set of peripheral features and

interrupts varies by the device. Please

refer to the corresponding device tables

and pinout diagrams for device-specific

information.

3.2.4

NEAR DATA SPACE

The 8-Kbyte area between 0x0000 and 0x1FFF is

referred to as the Near Data Space. Locations in this

space are directly addressable via a 13-bit absolute

address field within all memory direct instructions.

Additionally, the whole data space is addressable using

MOV instructions, which support Memory Direct

Addressing mode with a 16-bit address field, or by

using Indirect Addressing mode using a working

register as an Address Pointer.

Data byte reads will read the complete word that

contains the byte, using the Least Significant bit (LSb)

of any EA to determine which byte to select. The

selected byte is placed onto the Least Significant Byte

(LSB) of the data path. That is, data memory and reg-

isters are organized as two parallel byte-wide entities

with shared (word) address decode but separate write

lines. Data byte writes only write to the corresponding

side of the array or register which matches the byte

address.

Preliminary

DS70175D-page 27

PIC24H

FIGURE 3-3:

DATA MEMORY MAP FOR PIC24H DEVICES WITH 8 KBYTES RAM

MSB

Address

LSB

Address

16 bits

MSB

LSB

0x0000

0x0001

2-Kbyte

SFR Space

0x07FE

0x0800

0x07FF

0x0801

8-Kbyte

Near

Data

Space

X Data RAM (X)

8-Kbyte

SRAM Space

0x1FFF

0x2001

0x1FFE

0x2000

DMA RAM

0x27FF

0x2801

0x27FE

0x2800

0x8001

0x8000

X Data

Optionally

Mapped

Unimplemented (X)

into Program

Memory

0xFFFF

0xFFFE

DS70175D-page 28

Preliminary

PIC24H

FIGURE 3-4:

DATA MEMORY MAP FOR PIC24H DEVICES WITH 16 KBYTES RAM

LSB

Address

MSB

Address

16 bits

MSB

LSB

0x0000

0x0001

2-Kbyte

SFR Space

8-Kbyte

Near

Data

0x07FE

0x0800

0x07FF

0x0801

Space

0x1FFF

0x1FFE

X Data RAM (X)

16-Kbyte

SRAM Space

0x3FFF

0x4001

0x3FFE

0x4000

DMA RAM

0x47FF

0x4801

0x47FE

0x4800

0x8001

0x8000

X Data

Unimplemented (X)

Optionally

Mapped

into Program

Memory

0xFFFF

0xFFFE

peripherals using DMA. The DMA RAM can be

accessed by the DMA controller without having to steal

cycles from the CPU.

3.2.5

DMA RAM

Every PIC24H device contains 2 Kbytes of dual ported

DMA RAM located at the end of data space. Memory

locations in the DMA RAM space are accessible

simultaneously by the CPU and the DMA controller

module. DMA RAM is utilized by the DMA controller to

store data to be transferred to various peripherals using

DMA, as well as data transferred from various

When the CPU and the DMA controller attempt to

concurrently write to the same DMA RAM location, the

hardware ensures that the CPU is given precedence in

accessing the DMA RAM location. Therefore, the DMA

RAM provides a reliable means of transferring DMA

data without ever having to stall the CPU.

Note:

DMA RAM can be used for general

purpose data storage if the DMA function

is not required in an application.

Preliminary

DS70175D-page 29

PIC24H

3.2.6

SOFTWARE STACK

3.2.7

DATA RAM PROTECTION FEATURE

The PIC24H product family supports Data RAM protec-

tion features that enable segments of RAM to be

protected when used in conjunction with Boot and

Secure Code Segment Security. BSRAM (Secure RAM

segment for BS) is accessible only from the Boot Seg-

ment Flash code, when enabled. SSRAM (Secure

RAM segment for RAM) is accessible only from the

Secure Segment Flash code, when enabled. See

Table 3-1 for an overview of the BSRAM and SSRAM

SFRs.

In addition to its use as a working register, the W15

register in the PIC24H devices is also used as a soft-

ware Stack Pointer. The Stack Pointer always points to

the first available free word and grows from lower to

higher addresses. It pre-decrements for stack pops and

post-increments for stack pushes, as shown in

Figure 3-5. For a PC push during any CALLinstruction,

the MSB of the PC is zero-extended before the push,

ensuring that the MSB is always clear.

Note:

A PC push during exception processing

concatenates the SRL register to the MSB

of the PC prior to the push.

3.3

Instruction Addressing Modes

The addressing modes in Table 3-32 form the basis of

the addressing modes optimized to support the specific

features of individual instructions. The addressing

modes provided in the MAC class of instructions are

somewhat different from those in the other instruction

types.

The Stack Pointer Limit register (SPLIM) associated

with the Stack Pointer sets an upper address boundary

for the stack. SPLIM is uninitialized at Reset. As is the

case for the Stack Pointer, SPLIM<0> is forced to ‘0’

because all stack operations must be word-aligned.

Whenever an EA is generated using W15 as a source

or destination pointer, the resulting address is

compared with the value in SPLIM. If the contents of

the Stack Pointer (W15) and the SPLIM register are

equal and a push operation is performed, a stack error

trap will not occur. The stack error trap will occur on a

subsequent push operation. Thus, for example, if it is

desirable to cause a stack error trap when the stack

grows beyond address 0x2000 in RAM, initialize the

SPLIM with the value 0x1FFE.

3.3.1

FILE REGISTER INSTRUCTIONS

Most file register instructions use a 13-bit address field

(f) to directly address data present in the first 8192

bytes of data memory (Near Data Space). Most file

register instructions employ a working register, W0,

which is denoted as WREG in these instructions. The

destination is typically either the same file register or

WREG (with the exception of the MUL instruction),

which writes the result to a register or register pair. The

MOV instruction allows additional flexibility and can

access the entire data space.

Similarly, a Stack Pointer underflow (stack error) trap is

generated when the Stack Pointer address is found to

be less than 0x0800. This prevents the stack from

interfering with the Special Function Register (SFR)

space.

3.3.2

MCU INSTRUCTIONS

The 3-operand MCU instructions are of the form:

Operand 3 = Operand 1 <function> Operand 2

A write to the SPLIM register should not be immediately

followed by an indirect read operation using W15.

where Operand 1 is always a working register (i.e., the

addressing mode can only be Register Direct) which is

referred to as Wb. Operand 2 can be a W register,

fetched from data memory, or a 5-bit literal. The result

location can be either a W register or a data memory

location. The following addressing modes are

supported by MCU instructions:

FIGURE 3-5:

CALLSTACK FRAME

0x0000

15

0

• Register Direct

PC<15:0>

000000000

W15 (before CALL)

• Register Indirect

PC<22:16>

• Register Indirect Post-Modified

• Register Indirect Pre-Modified

• 5-bit or 10-bit Literal

W15 (after CALL)

POP : [--W15]

PUSH: [W15++]

Note:

Not all instructions support all the

addressing modes given above. Individual

instructions may support different subsets

of these addressing modes.

DS70175D-page 48

Preliminary

PIC24H

TABLE 3-32: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode Description

File Register Direct

The address of the file register is specified explicitly.

The contents of a register are accessed directly.

The contents of Wn forms the EA.

Register Direct

Register Indirect

Register Indirect Post-Modified

The contents of Wn forms the EA. Wn is post-modified (incremented or

decremented) by a constant value.

Register Indirect Pre-Modified

Wn is pre-modified (incremented or decremented) by a signed constant value

to form the EA.

Register Indirect with Register Offset The sum of Wn and Wb forms the EA.

Register Indirect with Literal Offset The sum of Wn and a literal forms the EA.

3.3.3

MOVE INSTRUCTIONS

3.4

Interfacing Program and Data

Memory Spaces

Move instructions provide a greater degree of address-

ing flexibility than other instructions. In addition to the

Addressing modes supported by most MCU instruc-

tions, move instructions also support Register Indirect

with Register Offset Addressing mode, also referred to

as Register Indexed mode.

The PIC24H architecture uses a 24-bit wide program

space and a 16-bit wide data space. The architecture is

also a modified Harvard scheme, meaning that data

can also be present in the program space. To use this

data successfully, it must be accessed in a way that

preserves the alignment of information in both spaces.

Note:

For the MOV instructions, the Addressing

mode specified in the instruction can differ

for the source and destination EA.

However, the 4-bit Wb (Register Offset)

field is shared between both source and

destination (but typically only used by

one).

Aside from normal execution, the PIC24H architecture

provides two methods by which program space can be

accessed during operation:

• Using table instructions to access individual bytes

or words anywhere in the program space

• Remapping a portion of the program space into

the data space (Program Space Visibility)

In summary, the following Addressing modes are

supported by move instructions:

Table instructions allow an application to read or write

to small areas of the program memory. This capability

makes the method ideal for accessing data tables that

need to be updated from time to time. It also allows

access to all bytes of the program word. The remap-

ping method allows an application to access a large

block of data on a read-only basis, which is ideal for

look ups from a large table of static data. It can only

access the least significant word of the program word.

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

3.4.1

ADDRESSING PROGRAM SPACE

Note:

Not all instructions support all the

Addressing modes given above. Individual

instructions may support different subsets

of these Addressing modes.

Since the address ranges for the data and program

spaces are 16 and 24 bits, respectively, a method is

needed to create a 23-bit or 24-bit program address

from 16-bit data registers. The solution depends on the

interface method to be used.

3.3.4

OTHER INSTRUCTIONS

Besides the various addressing modes outlined above,

some instructions use literal constants of various sizes.

For example, BRA (branch) instructions use 16-bit

signed literals to specify the branch destination directly,

whereas the DISI instruction uses a 14-bit unsigned

literal field. In some instructions, the source of an oper-

and or result is implied by the opcode itself. Certain

operations, such as NOP, do not have any operands.

For table operations, the 8-bit Table Page register

(TBLPAG) is used to define a 32K word region within

the program space. This is concatenated with a 16-bit

EA to arrive at a full 24-bit program space address. In

this format, the Most Significant bit of TBLPAG is used

to determine if the operation occurs in the user memory

(TBLPAG<7> = 0) or the configuration memory

(TBLPAG<7> = 1).

Preliminary

DS70175D-page 49

PIC24H

For remapping operations, the 8-bit Program Space

Visibility register (PSVPAG) is used to define a

16K word page in the program space. When the Most

Significant bit of the EA is ‘1’, PSVPAG is concatenated

with the lower 15 bits of the EA to form a 23-bit program

space address. Unlike table operations, this limits

remapping operations strictly to the user memory area.

Table 3-33 and Figure 3-6 show how the program EA is

created for table operations and remapping accesses

from the data EA. Here, P<23:0> refers to a program

space word, whereas D<15:0> refers to a data space

word.

TABLE 3-33: PROGRAM SPACE ADDRESS CONSTRUCTION

Program Space Address

Access

Space

Access Type

<23>

<22:16>

<15>

<14:1>

<0>

Instruction Access

(Code Execution)

User

0

PC<22:1>

0

0xx xxxx xxxx xxxx xxxx xxx0

TBLRD/TBLWT

(Byte/Word Read/Write)

TBLPAG<7:0>

0xxx xxxx

Data EA<15:0>

xxxx xxxx xxxx xxxx

Data EA<15:0>

Configuration

TBLPAG<7:0>

1xxx xxxx

xxxx xxxx xxxx xxxx

Program Space Visibility User

(Block Remap/Read)

0

PSVPAG<7:0>

xxxx xxxx

Data EA<14:0>⁽¹⁾

xxx xxxx xxxx xxxx

Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of

the address is PSVPAG<0>.

DS70175D-page 50

Preliminary

PIC24H

FIGURE 3-6:

DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

Program Counter⁽¹⁾

Program Counter

23 bits

0

1/0

EA

Table Operations⁽²⁾

1/0

TBLPAG

8 bits

16 bits

24 bits

Select

1

0

EA

Program Space Visibility⁽¹⁾

(Remapping)

0

PSVPAG

8 bits

15 bits

23 bits

Byte Select

User/Configuration

Space Select

Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word

alignment of data in the program and data spaces.

2: Table operations are not required to be word-aligned. Table read operations are permitted

in the configuration memory space.

Preliminary

DS70175D-page 51

PIC24H

2. TBLRDH (Table Read High): In Word mode, it

maps the entire upper word of a program address

(P<23:16>) to a data address. Note that

D<15:8>, the ‘phantom byte’, will always be ‘0’.

3.4.2

DATA ACCESS FROM PROGRAM

MEMORY USING TABLE

INSTRUCTIONS

The TBLRDL and TBLWTL instructions offer a direct

method of reading or writing the lower word of any

address within the program space without going

through data space. The TBLRDHand TBLWTHinstruc-

tions are the only method to read or write the upper

8 bits of a program space word as data.

In Byte mode, it maps the upper or lower byte of

the program word to D<7:0> of the data

address, as above. Note that the data will

always be ‘0’ when the upper ‘phantom’ byte is

selected (Byte Select = 1).

In a similar fashion, two table instructions, TBLWTH

and TBLWTL, are used to write individual bytes or

words to a program space address. The details of

their operation are explained in Section 4.0 “Flash

Program Memory”.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two 16-bit,

word wide address spaces, residing side by side, each

with the same address range. TBLRDL and TBLWTL

access the space which contains the least significant

data word and TBLRDHand TBLWTHaccess the space

which contains the upper data byte.

For all table operations, the area of program memory

space to be accessed is determined by the Table Page

register (TBLPAG). TBLPAG covers the entire program

memory space of the device, including user and config-

uration spaces. When TBLPAG<7> = 0, the table page

is located in the user memory space. When

TBLPAG<7> = 1, the page is located in configuration

space.

Two table instructions are provided to move byte or

word sized (16-bit) data to and from program space.

Both function as either byte or word operations.

1. TBLRDL (Table Read Low): In Word mode, it

maps the lower word of the program space

location (P<15:0>) to a data address (D<15:0>).

In Byte mode, either the upper or lower byte of

the lower program word is mapped to the lower

byte of a data address. The upper byte is

selected when Byte Select is ‘1’; the lower byte

is selected when it is ‘0’.

FIGURE 3-7:

ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Program Space

TBLPAG

02

23

15

0

0x000000

23

16

8

0

00000000

0x020000

0x030000

00000000

‘Phantom’ Byte

TBLRDH.B(Wn<0> = 0)

TBLRDL.B(Wn<0> = 1)

TBLRDL.B(Wn<0> = 0)

TBLRDL.W

The address for the table operation is determined by the data EA

within the page defined by the TBLPAG register.

Only read operations are shown; write operations are also valid in

the user memory area.

0x800000

DS70175D-page 52

Preliminary

PIC24H

24-bit program word are used to contain the data. The

upper 8 bits of any program space location used as

data should be programmed with ‘1111 1111’ or

‘0000 0000’ to force a NOP. This prevents possible

issues should the area of code ever be accidentally

executed.

3.4.3

READING DATA FROM PROGRAM

MEMORY USING PROGRAM SPACE

VISIBILITY

The upper 32 Kbytes of data space may optionally be

mapped into any 16K word page of the program space.

This option provides transparent access of stored con-

stant data from the data space without the need to use

special instructions (i.e., TBLRDL/H).

Note:

PSV access is temporarily disabled during

table reads/writes.

Program space access through the data space occurs

if the Most Significant bit of the data space EA is ‘1’ and

program space visibility is enabled by setting the PSV

bit in the Core Control register (CORCON<2>). The

location of the program memory space to be mapped

into the data space is determined by the Program

Space Visibility Page register (PSVPAG). This 8-bit

register defines any one of 256 possible pages of

16K words in program space. In effect, PSVPAG func-

tions as the upper 8 bits of the program memory

address, with the 15 bits of the EA functioning as the

lower bits. Note that by incrementing the PC by 2 for

each program memory word, the lower 15 bits of data

space addresses directly map to the lower 15 bits in the

corresponding program space addresses.

For operations that use PSV and are executed outside

a REPEAT loop, the MOV and MOV.D instructions

require one instruction cycle in addition to the specified

execution time. All other instructions require two

instruction cycles in addition to the specified execution

time.

For operations that use PSV, which are executed inside

a REPEAT loop, there will be some instances that

require two instruction cycles in addition to the

specified execution time of the instruction:

• Execution in the first iteration

• Execution in the last iteration

• Execution prior to exiting the loop due to an

interrupt

• Execution upon re-entering the loop after an

interrupt is serviced

Data reads to this area add an additional cycle to the

instruction being executed, since two program memory

fetches are required.

Any other iteration of the REPEAT loop will allow the

instruction accessing data, using PSV, to execute in a

single cycle.

Although each data space address, 8000h and higher,

maps directly into a corresponding program memory

address (see Figure 3-8), only the lower 16 bits of the

FIGURE 3-8:

PROGRAM SPACE VISIBILITY OPERATION

When CORCON<2> = 1and EA<15> = 1:

Program Space

Data Space

PSVPAG

02

23

15

0

0x000000

0x0000

Data EA<14:0>

0x010000

0x018000

The data in the page

designated by

PSVPAG is mapped

into the upper half of

the data memory

space...

0x8000

PSV Area

...while the lower15 bits

of the EA specify an

exact address within

the PSV area. This

corresponds exactly to

the same lower 15 bits

of the actual program

space address.

0xFFFF

0x800000

Preliminary

DS70175D-page 53

PIC24H

NOTES:

DS70175D-page 54

Preliminary

PIC24H

RTSP is accomplished using TBLRD (table read) and

TBLWT (table write) instructions. With RTSP, the user

can write program memory data either in blocks or

‘rows’ of 64 instructions (192 bytes) at a time, or single

instructions and erase program memory in blocks or

‘pages’ of 512 instructions (1536 bytes) at a time.

4.0

FLASH PROGRAM MEMORY

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

4.1

Table Instructions and Flash

Programming

The PIC24H devices contain internal Flash program

memory for storing and executing application code.

The memory is readable, writable and erasable during

normal operation over the entire VDD range.

Regardless of the method used, all programming of

Flash memory is done with the table read and table

write instructions. These allow direct read and write

access to the program memory space from the data

memory while the device is in normal operating mode.

The 24-bit target address in the program memory is

formed using bits<7:0> of the TBLPAG register and the

Effective Address (EA) from a W register specified in

the table instruction, as shown in Figure 4-1.

Flash memory can be programmed in two ways:

1. In-Circuit Serial Programming™ (ICSP™)

programming capability

2. Run-Time Self-Programming (RTSP)

ICSP programming capability allows a PIC24H device

to be serially programmed while in the end application

circuit. This is simply done with two lines for program-

ming clock and programming data (one of the alternate

programming pin pairs: PGC1/PGD1, PGC2/PGD2 or

PGC3/PGD3, and three other lines for power (VDD),

ground (VSS) and Master Clear (MCLR). This allows

customers to manufacture boards with unprogrammed

devices and then program the digital signal controller

just before shipping the product. This also allows the

most recent firmware or a custom firmware to be

programmed.

The TBLRDLand the TBLWTLinstructions are used to

read or write to bits<15:0> of program memory.

TBLRDLand TBLWTLcan access program memory in

both Word and Byte modes.

The TBLRDHand TBLWTHinstructions are used to read

or write to bits<23:16> of program memory. TBLRDH

and TBLWTHcan also access program memory in Word

or Byte mode.

FIGURE 4-1:

ADDRESSING FOR TABLE REGISTERS

24 bits

Program Counter

Using

Program Counter

0

Working Reg EA

Using

Table Instruction

1/0

TBLPAG Reg

8 bits

16 bits

User/Configuration

Space Select

Byte

Select

24-bit EA

Preliminary

DS70175D-page 55

PIC24H

4.2

RTSP Operation

4.3

Control Registers

The PIC24H Flash program memory array is organized

into rows of 64 instructions or 192 bytes. RTSP allows

the user to erase a page of memory, which consists of

eight rows (512 instructions) at a time, and to program

one row or one word at a time. TABLE 23-11: “DC

Characteristics: Program Memory” displays typical

erase and programming times. The 8-row erase pages

and single row write rows are edge-aligned, from the

beginning of program memory, on boundaries of 1536

bytes and 192 bytes, respectively.

There are two SFRs used to read and write the

program Flash memory: NVMCON and NVMKEY.

The NVMCON register (Register 4-1) controls which

blocks are to be erased, which memory type is to be

programmed and the start of the programming cycle.

NVMKEY is a write-only register that is used for write

protection. To start a programming or erase sequence,

the user must consecutively write 55h and AAh to the

NVMKEY register. Refer to Section 4.4 “Programming

Operations” for further details.

The program memory implements holding buffers that

can contain 64 instructions of programming data. Prior

to the actual programming operation, the write data

must be loaded into the buffers in sequential order. The

instruction words loaded must always be from a group

of 64 boundary.

4.4

Programming Operations

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. A programming operation is nominally 4 ms in

duration and the processor stalls (waits) until the oper-

ation is finished. Setting the WR bit (NVMCON<15>)

starts the operation, and the WR bit is automatically

cleared when the operation is finished.

The basic sequence for RTSP programming is to set up

a Table Pointer, then do a series of TBLWTinstructions

to load the buffers. Programming is performed by set-

ting the control bits in the NVMCON register. A total of

64 TBLWTL and TBLWTH instructions are required to

load the instructions.

All of the table write operations are single-word writes

(two instruction cycles) because only the buffers are

written.

A

programming cycle is required for

programming each row.

DS70175D-page 56

Preliminary

PIC24H

REGISTER 4-1:

NVMCON: FLASH MEMORY CONTROL REGISTER

R/SO-0⁽¹⁾

WR

R/W-0⁽¹⁾

WREN

R/W-0⁽¹⁾

WRERR

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

R/W-0⁽¹⁾

ERASE

U-0

—

U-0

—

R/W-0⁽¹⁾

NVMOP<3:0>⁽²⁾

bit 7

bit 0

Legend:

SO = Satiable only bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

WR: Write Control bit

1= Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once operation is complete.

0= Program or erase operation is complete and inactive

bit 14

bit 13

WREN: Write Enable bit

1= Enable Flash program/erase operations

0= Inhibit Flash program/erase operations

WRERR: Write Sequence Error Flag bit

1= An improper program or erase sequence attempt or termination has occurred (bit is set

automatically on any set attempt of the WR bit)

0= The program or erase operation completed normally

bit 12-7

bit 6

Unimplemented: Read as ‘0’

ERASE: Erase/Program Enable bit

1= Perform the erase operation specified by NVMOP<3:0> on the next WR command

0= Perform the program operation specified by NVMOP<3:0> on the next WR command

bit 5-4

bit 3-0

Unimplemented: Read as ‘0’

NVMOP<3:0>: NVM Operation Select bits⁽²⁾

1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)

1110 = Reserved

1101 = Erase General Segment and FGS Configuration Register

(ERASE = 1) or no operation (ERASE = 0)

1100 = Erase Secure Segment and FSS Configuration Register

(ERASE = 1) or no operation (ERASE = 0)

1011-0100 = Reserved

0011= Memory word program operation (ERASE = 0) or no operation (ERASE = 1)

0010= Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)

0001= Memory row program operation (ERASE = 0) or no operation (ERASE = 1)

0000= Program or erase a single Configuration register byte

Note 1: These bits can only be reset on POR.

2: All other combinations of NVMOP<3:0> are unimplemented.

Preliminary

DS70175D-page 57

PIC24H

4. Write the first 64 instructions from data RAM into

the program memory buffers (see Example 4-2).

4.4.1

PROGRAMMING ALGORITHM FOR

FLASH PROGRAM MEMORY

5. Write the program block to Flash memory:

The user can program one row of program Flash

memory at a time. To do this, it is necessary to erase

the 8-row erase page that contains the desired row.

The general process is:

a) Set the NVMOP bits to ‘0001’ to configure

for row programming. Clear the ERASE bit

and set the WREN bit.

b) Write 0x55 to NVMKEY.

c) Write 0xAA to NVMKEY.

1. Read eight rows of program memory

(512 instructions) and store in data RAM.

d) Set the WR bit. The programming cycle

begins and the CPU stalls for the duration of

the write cycle. When the write to Flash mem-

ory is done, the WR bit is cleared

automatically.

2. Update the program data in RAM with the

desired new data.

3. Erase the page (see Example 4-1):

a) Set the NVMOP bits (NVMCON<3:0>) to

‘0010’ to configure for block erase. Set the

ERASE (NVMCON<6>) and WREN

(NVMCON<14>) bits.

6. Repeat steps 4 and 5, using the next available

64 instructions from the block in data RAM by

incrementing the value in TBLPAG, until all

512 instructions are written back to Flash mem-

ory.

b) Write the starting address of the page to be

erased into the TBLPAG and W registers.

c) Perform a dummy table write operation

(TBLWTL) to any address within the page

that needs to be erased.

For protection against accidental operations, the write

initiate sequence for NVMKEY must be used to allow

any erase or program operation to proceed. After the

programming command has been executed, the user

must wait for the programming time until programming

is complete. The two instructions following the start of

the programming sequence should be NOPs, as shown

in Example 4-3.

d) Write 0x55 to NVMKEY.

e) Write 0xAA to NVMKEY.

f) Set the WR bit (NVMCON<15>). The erase

cycle begins and the CPU stalls for the dura-

tion of the erase cycle. When the erase is

done, the WR bit is cleared automatically.

EXAMPLE 4-1:

ERASING A PROGRAM MEMORY PAGE

; Set up NVMCON for block erase operation

MOV

#0x4042, W0

W0, NVMCON

;

; Initialize NVMCON

; Init pointer to row to be ERASED

MOV

#tblpage(PROG_ADDR), W0

W0, TBLPAG

#tbloffset(PROG_ADDR), W0

;

; Initialize PM Page Boundary SFR

; Initialize in-page EA<15:0> pointer

; Set base address of erase block

; Block all interrupts with priority <7

; for next 5 instructions

TBLWTL W0, [W0]

DISI

#5

MOV

BSET

NOP

#0x55, W0

W0, NVMKEY

#0xAA, W1

W1, NVMKEY

NVMCON, #WR

; Write the 55 key

;

; Write the AA key

; Start the erase sequence

; Insert two NOPs after the erase

; command is asserted

Note:

A program memory page erase operation

is set up by performing a dummy table

write (TBLWTL) operation to any address

within the page. This methodology is dif-

ferent from the page erase operation on

dsPIC30F devices in which the erase

page was selected using a dedicated pair

of registers (NVMADRU and NVMADR).

DS70175D-page 58

Preliminary

PIC24H

EXAMPLE 4-2:

LOADING THE WRITE BUFFERS

; Set up NVMCON for row programming operations

MOV

#0x4001, W0

W0, NVMCON

;

; Initialize NVMCON

; Set up a pointer to the first program memory location to be written

; program memory selected, and writes enabled

MOV

#0x0000, W0

W0, TBLPAG

#0x6000, W0

;

; Initialize PM Page Boundary SFR

; An example program memory address

; Perform the TBLWT instructions to write the latches

; 0th_program_word

MOV

#LOW_WORD_0, W2

#HIGH_BYTE_0, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

; 1st_program_word

MOV

#LOW_WORD_1, W2

#HIGH_BYTE_1, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

;

2nd_program_word

MOV

#LOW_WORD_2, W2

#HIGH_BYTE_2, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

•

; 63rd_program_word

MOV

#LOW_WORD_31, W2

#HIGH_BYTE_31, W3

;

TBLWTL W2, [W0]

TBLWTH W3, [W0++]

; Write PM low word into program latch

; Write PM high byte into program latch

EXAMPLE 4-3:

INITIATING A PROGRAMMING SEQUENCE

DISI

#5

; Block all interrupts with priority <7

; for next 5 instructions

MOV

BSET

NOP

#0x55, W0

W0, NVMKEY

#0xAA, W1

W1, NVMKEY

NVMCON, #WR

; Write the 55 key

;

; Write the AA key

; Start the erase sequence

; Insert two NOPs after the

; erase command is asserted

Preliminary

DS70175D-page 59

PIC24H

NOTES:

DS70175D-page 60

Preliminary

PIC24H

5.0

RESETS

Note:

Refer to the specific peripheral or CPU

section of this manual for register Reset

states.

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

All types of device Reset will set a corresponding status

bit in the RCON register to indicate the type of Reset

(see Register 5-1). A POR will clear all bits, except for

the POR bit (RCON<0>), that are set. The user can set

or clear any bit at any time during code execution. The

RCON bits only serve as status bits. Setting a particular

Reset status bit in software does not cause a device

Reset to occur.

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

• POR: Power-on Reset

The RCON register also has other bits associated with

the Watchdog Timer and device power-saving states.

The function of these bits is discussed in other sections

of this manual.

• BOR: Brown-out Reset

• MCLR: Master Clear Pin Reset

• SWR: RESETInstruction

• WDT: Watchdog Timer Reset

• TRAPR: Trap Conflict Reset

Note:

The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset will be meaningful.

• IOPUWR: Illegal Opcode and Uninitialized W

Register Reset

A simplified block diagram of the Reset module is

shown in Figure 5-1.

Any active source of Reset will make the SYSRST sig-

nal active. Many registers associated with the CPU and

peripherals are forced to a known Reset state. Most

registers are unaffected by a Reset; their status is

unknown on POR and unchanged by all other Resets.

FIGURE 5-1:

RESET SYSTEM BLOCK DIAGRAM

RESETInstruction

Glitch Filter

MCLR

WDT

Module

Sleep or Idle

POR

BOR

VDD Rise

Detect

SYSRST

VDD

Internal

Regulator

Trap Conflict

Illegal Opcode

Uninitialized W Register

Preliminary

DS70175D-page 61

PIC24H

REGISTER 5-1:

RCON: RESET CONTROL REGISTER⁽¹⁾

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

TRAPR

bit 15

IOPUWR

VREGS

bit 8

R/W-0

EXTR

R/W-0

SWR

R/W-0

SWDTEN⁽²⁾

R/W-0

WDTO

R/W-0

IDLE

R/W-1

BOR

R/W-1

POR

SLEEP

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

TRAPR: Trap Reset Flag bit

1= A Trap Conflict Reset has occurred

0= A Trap Conflict Reset has not occurred

IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit

1= An illegal opcode detection, an illegal address mode or uninitialized W register used as an

Address Pointer caused a Reset

0= An illegal opcode or uninitialized W Reset has not occurred

bit 13-9

bit 8

Unimplemented: Read as ‘0’

VREGS: Voltage Regulator Standby During Sleep bit

1= Voltage regulator goes into Standby mode during Sleep

0= Voltage regulator is active during Sleep

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

EXTR: External Reset (MCLR) Pin bit

1= A Master Clear (pin) Reset has occurred

0= A Master Clear (pin) Reset has not occurred

SWR: Software Reset (Instruction) Flag bit

1= A RESETinstruction has been executed

0= A RESETinstruction has not been executed

SWDTEN: Software Enable/Disable of WDT bit⁽²⁾

1= WDT is enabled

0= WDT is disabled

WDTO: Watchdog Timer Time-out Flag bit

1= WDT time-out has occurred

0= WDT time-out has not occurred

SLEEP: Wake-up from Sleep Flag bit

1= Device has been in Sleep mode

0= Device has not been in Sleep mode

IDLE: Wake-up from Idle Flag bit

1= Device was in Idle mode

0= Device was not in Idle mode

BOR: Brown-out Reset Flag bit

1= A Brown-out Reset has occurred

0= A Brown-out Reset has not occurred

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

DS70175D-page 62

Preliminary

PIC24H

REGISTER 5-1:

bit 0

RCON: RESET CONTROL REGISTER⁽¹⁾

POR: Power-on Reset Flag bit

1= A Power-on Reset has occurred

0= A Power-on Reset has not occurred

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

Preliminary

DS70175D-page 63

PIC24H

TABLE 5-1:

RESET FLAG BIT OPERATION

Flag Bit Setting Event

Trap conflict event

Clearing Event

TRAPR (RCON<15>)

IOPUWR (RCON<14>)

POR

Illegal opcode or uninitialized

W register access

EXTR (RCON<7>)

SWR (RCON<6>)

WDTO (RCON<4>)

SLEEP (RCON<3>)

IDLE (RCON<2>)

BOR (RCON<1>)

POR (RCON<0>)

MCLR Reset

POR

RESETinstruction

WDT time-out

PWRSAVinstruction, POR

PWRSAV #SLEEPinstruction

PWRSAV #IDLEinstruction

BOR

POR

—

POR

—

Note: All Reset flag bits may be set or cleared by the user software.

5.1

Clock Source Selection at Reset

5.2

Device Reset Times

If clock switching is enabled, the system clock source at

device Reset is chosen, as shown in Table 5-2. If clock

switching is disabled, the system clock source is always

selected according to the oscillator Configuration bits.

Refer to Section 8.0 “Oscillator Configuration” for

further details.

The Reset times for various types of device Reset are

summarized in Table 5-3. The system Reset signal is

released after the POR and PWRT delay times expire.

The time at which the device actually begins to execute

code also depends on the system oscillator delays,

which include the Oscillator Start-up Timer (OST) and

the PLL lock time. The OST and PLL lock times occur

in parallel with the applicable reset delay times.

TABLE 5-2:

OSCILLATOR SELECTION vs.

TYPE OF RESET (CLOCK

SWITCHING ENABLED)

The FSCM delay determines the time at which the

FSCM begins to monitor the system clock source after

the reset signal is released.

Reset Type

Clock Source Determinant

POR

BOR

Oscillator Configuration bits

(FNOSC<2:0>)

MCLR

WDTR

SWR

COSC Control bits

(OSCCON<14:12>)

DS70175D-page 64

Preliminary

PIC24H

TABLE 5-3:

Reset Type

POR

RESET DELAY TIMES FOR VARIOUS DEVICE RESETS

System Clock

Delay

FSCM

Delay

Clock Source

SYSRST Delay

Notes

1, 2, 3

EC, FRC, LPRC

ECPLL, FRCPLL

XT, HS, SOSC

XTPLL, HSPLL

Any Clock

TPOR + TSTARTUP + TRST

—

TFSCM

—

TPOR + TSTARTUP + TRST

TLOCK

1, 2, 3, 5, 6

TPOR + TSTARTUP + TRST

TOST

1, 2, 3, 4, 6

TPOR + TSTARTUP + TRST

TOST + TLOCK

1, 2, 3, 4, 5, 6

MCLR

TRST

—

3

WDT

Any Clock

—

Software

Any clock

—

Illegal Opcode

Uninitialized W

Trap Conflict

Any Clock

—

Any Clock

—

Any Clock

—

Note 1: TPOR = Power-on Reset delay (10 μs nominal).

2: TSTARTUP = Conditional POR delay of 20 μs nominal (if on-chip regulator is enabled) or 64 ms nominal

Power-up Timer delay (if regulator is disabled). TSTARTUP is also applied to all returns from powered-down

states, including waking from Sleep mode, only if the regulator is enabled.

3: TRST = Internal state Reset time (20 μs nominal).

4: TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the

oscillator clock to the system.

5: TLOCK = PLL lock time (20 μs nominal).

6: TFSCM = Fail-Safe Clock Monitor delay (100 μs nominal).

5.2.1

POR AND LONG OSCILLATOR

START-UP TIMES

5.2.2.1

FSCM Delay for Crystal and PLL

Clock Sources

The oscillator start-up circuitry and its associated delay

timers are not linked to the device Reset delays that

occur at power-up. Some crystal circuits (especially

low-frequency crystals) have a relatively long start-up

time. Therefore, one or more of the following conditions

is possible after the Reset signal is released:

When the system clock source is provided by a crystal

oscillator and/or the PLL, a small delay, TFSCM, is auto-

matically inserted after the POR and PWRT delay

times. The FSCM does not begin to monitor the system

clock source until this delay expires. The FSCM delay

time is nominally 100 μs and provides additional time

for the oscillator and/or PLL to stabilize. In most cases,

the FSCM delay prevents an oscillator failure trap at a

device Reset when the PWRT is disabled.

• The oscillator circuit has not begun to oscillate.

• The Oscillator Start-up Timer has not expired (if a

crystal oscillator is used).

• The PLL has not achieved a lock (if PLL is used).

5.3

Special Function Register Reset

States

The device will not begin to execute code until a valid

clock source has been released to the system. There-

fore, the oscillator and PLL start-up delays must be

considered when the Reset delay time must be known.

Most of the Special Function Registers (SFRs) associ-

ated with the CPU and peripherals are reset to a

particular value at a device Reset. The SFRs are

grouped by their peripheral or CPU function and their

Reset values are specified in each section of this

manual.

5.2.2

FAIL-SAFE CLOCK MONITOR

(FSCM) AND DEVICE RESETS

If the FSCM is enabled, it begins to monitor the system

clock source when the Reset signal is released. If a

valid clock source is not available at this time, the

device automatically switches to the FRC oscillator and

the user can switch to the desired crystal oscillator in

the Trap Service Routine.

The Reset value for each SFR does not depend on the

type of Reset, with the exception of two registers. The

Reset value for the Reset Control register, RCON,

depends on the type of device Reset. The Reset value

for the Oscillator Control register, OSCCON, depends

on the type of Reset and the programmed values of the

oscillator Configuration bits in the FOSC Configuration

register.

Preliminary

DS70175D-page 65

PIC24H

NOTES:

DS70175D-page 66

Preliminary

PIC24H

6.1.1

ALTERNATE VECTOR TABLE

6.0

INTERRUPT CONTROLLER

The Alternate Interrupt Vector Table (AIVT) is located

after the IVT, as shown in Figure 6-1. Access to the

AIVT is provided by the ALTIVT control bit

(INTCON2<15>). If the ALTIVT bit is set, all interrupt

and exception processes use the alternate vectors

instead of the default vectors. The alternate vectors are

organized in the same manner as the default vectors.

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

The PIC24H interrupt controller reduces the numerous

peripheral interrupt request signals to a single interrupt

request signal to the PIC24H CPU. It has the following

features:

The AIVT supports debugging by providing a means to

switch between an application and a support environ-

ment without requiring the interrupt vectors to be

reprogrammed. This feature also enables switching

between applications for evaluation of different soft-

ware algorithms at run time. If the AIVT is not needed,

the AIVT should be programmed with the same

addresses used in the IVT.

• Up to 8 processor exceptions and software traps

• 7 user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• A unique vector for each interrupt or exception

source

6.2

Reset Sequence

• Fixed priority within a specified user priority level

A device Reset is not a true exception because the

interrupt controller is not involved in the Reset process.

The PIC24H device clears its registers in response to a

Reset which forces the PC to zero. The digital signal

controller then begins program execution at location

0x000000. The user programs a GOTOinstruction at the

Reset address which redirects program execution to

the appropriate start-up routine.

• Alternate Interrupt Vector Table (AIVT) for debug

support

• Fixed interrupt entry and return latencies

6.1

Interrupt Vector Table

The Interrupt Vector Table (IVT) is shown in Figure 6-1.

The IVT resides in program memory, starting at location

000004h. The IVT contains 126 vectors consisting of

8 nonmaskable trap vectors plus up to 118 sources of

interrupt. In general, each interrupt source has its own

vector. Each interrupt vector contains a 24-bit wide

address. The value programmed into each interrupt

vector location is the starting address of the associated

Interrupt Service Routine (ISR).

Note: Any unimplemented or unused vector

locations in the IVT and AIVT should be

programmed with the address of a default

interrupt handler routine that contains a

RESETinstruction.

Interrupt vectors are prioritized in terms of their natural

priority; this priority is linked to their position in the

vector table. All other things being equal, lower

addresses have a higher natural priority. For example,

the interrupt associated with vector 0 will take priority

over interrupts at any other vector address.

PIC24H devices implement up to 61 unique interrupts

and 5 nonmaskable traps. These are summarized in

Table 6-1 and Table 6-2.

Preliminary

DS70175D-page 67

PIC24H

FIGURE 6-1:

PIC24H INTERRUPT VECTOR TABLE

Reset – GOTOInstruction

Reset – GOTOAddress

Reserved

0x000000

0x000002

0x000004

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

DMA Error Trap Vector

Reserved

Interrupt Vector 0

Interrupt Vector 1

~

0x000014

~

Interrupt Vector 52

Interrupt Vector 53

Interrupt Vector 54

~

0x00007C

0x00007E

0x000080

(1)

Interrupt Vector Table (IVT)

~

Interrupt Vector 116

Interrupt Vector 117

Reserved

0x0000FC

0x0000FE

0x000100

0x000102

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

DMA Error Trap Vector

Reserved

Interrupt Vector 0

Interrupt Vector 1

~

0x000114

~

(1)

Alternate Interrupt Vector Table (AIVT)

Interrupt Vector 52

Interrupt Vector 53

Interrupt Vector 54

~

0x00017C

0x00017E

0x000180

~

Interrupt Vector 116

Interrupt Vector 117

Start of Code

0x0001FE

0x000200

Note 1: See Table 6-1 for the list of implemented interrupt vectors.

DS70175D-page 68

Preliminary

PIC24H

TABLE 6-1:

INTERRUPT VECTORS

Interrupt

Vector

Number

Request(IRQ)

Number

IVT Address

AIVT Address

Interrupt Source

INT0 – External Interrupt 0

8

0

0x000014

0x000016

0x000018

0x00001A

0x00001C

0x00001E

0x000020

0x000022

0x000024

0x000026

0x000028

0x00002A

0x00002C

0x00002E

0x000030

0x000032

0x000034

0x000036

0x000038

0x00003A

0x00003C

0x00003E

0x000040

0x000042

0x000044

0x000046

0x000048

0x00004A

0x00004C

0x00004E

0x000050

0x000052

0x000054

0x000056

0x000058

0x00005A

0x00005C

0x00005E

0x000060

0x000062

0x000064

0x000066

0x000068

0x00006A

0x00006C

0x00006E

0x000114

0x000116

0x000118

0x00011A

0x00011C

0x00011E

0x000120

0x000122

0x000124

0x000126

0x000128

0x00012A

0x00012C

0x00012E

0x000130

0x000132

0x000134

0x000136

0x000138

0x00013A

0x00013C

0x00013E

0x000140

0x000142

0x000144

0x000146

0x000148

0x00014A

0x00014C

0x00014E

0x000150

0x000152

0x000154

0x000156

0x000158

0x00015A

0x00015C

0x00015E

0x000160

0x000162

0x000164

0x000166

0x000168

0x00016A

0x00016C

0x00016E

9

1

IC1 – Input Compare 1

OC1 – Output Compare 1

T1 – Timer1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

2

3

4

DMA0 – DMA Channel 0

IC2 – Input Capture 2

OC2 – Output Compare 2

T2 – Timer2

5

6

7

8

T3 – Timer3

9

SPI1E – SPI1 Error

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

SPI1 – SPI1 Transfer Done

U1RX – UART1 Receiver

U1TX – UART1 Transmitter

ADC1 – A/D Converter 1

DMA1 – DMA Channel 1

Reserved

SI2C1 – I2C1 Slave Events

MI2C1 – I2C1 Master Events

Reserved

CN - Change Notification Interrupt

INT1 – External Interrupt 1

ADC2 – A/D Converter 2

IC7 – Input Capture 7

IC8 – Input Capture 8

DMA2 – DMA Channel 2

OC3 – Output Compare 3

OC4 – Output Compare 4

T4 – Timer4

T5 – Timer5

INT2 – External Interrupt 2

U2RX – UART2 Receiver

U2TX – UART2 Transmitter

SPI2E – SPI2 Error

SPI1 – SPI1 Transfer Done

C1RX – ECAN1 Receive Data Ready

C1 – ECAN1 Event

DMA3 – DMA Channel 3

IC3 – Input Capture 3

IC4 – Input Capture 4

IC5 – Input Capture 5

IC6 – Input Capture 6

OC5 – Output Compare 5

OC6 – Output Compare 6

OC7 – Output Compare 7

OC8 – Output Compare 8

Reserved

Preliminary

DS70175D-page 69

PIC24H

TABLE 6-1:

INTERRUPT VECTORS (CONTINUED)

Interrupt

Request(IRQ)

Number

Vector

Number

IVT Address

AIVT Address

Interrupt Source

DMA4 – DMA Channel 4

54

55

46

47

0x000070

0x000072

0x000074

0x000076

0x000078

0x00007A

0x00007C

0x00007E

0x000080

0x000082

0x000084

0x000170

0x000172

0x000174

0x000176

0x000178

0x00017A

0x00017C

0x00017E

0x000180

0x000182

0x000184

T6 – Timer6

56

48

T7 – Timer7

57

49

SI2C2 – I2C2 Slave Events

MI2C2 – I2C2 Master Events

T8 – Timer8

58

50

59

51

60

52

T9 – Timer9

61

53

INT3 – External Interrupt 3

INT4 – External Interrupt 4

C2RX – ECAN2 Receive Data Ready

C2 – ECAN2 Event

Reserved

62

54

63

55

64

56

65-68

57-60

0x000086-

0x00008C

0x000186-

0x00018C

69

61

0x00008E

0x00018E

DMA5 – DMA Channel 5

Reserved

70-72

62-64

0x000090-

0x000094

0x000190-

0x000194

73

74

65

66

0x000096

0x000098

0x00009A

0x00009C

0x00009E

0x0000A0

0x0000A2

0x000196

0x000198

0x00019A

0x00019C

0x00019E

0x0001A0

0x0001A2

U1E – UART1 Error

U2E – UART2 Error

75

67

Reserved

76

68

DMA6 – DMA Channel 6

DMA7 – DMA Channel 7

C1TX – ECAN1 Transmit Data Request

C2TX – ECAN2 Transmit Data Request

Reserved

77

69

78

70

79

71

80-125

72-117

0x0000A4-

0x0000FE

0x0001A4-

0x0001FE

TABLE 6-2:

TRAP VECTORS

Vector Number

IVT Address

AIVT Address

Trap Source

Reserved

0

1

2

3

4

5

6

7

0x000004

0x000006

0x000008

0x00000A

0x00000C

0x00000E

0x000010

0x000012

0x000084

0x000086

0x000088

0x00008A

0x00008C

0x00008E

0x000090

0x000092

Oscillator Failure

Address Error

Stack Error

Math Error

DMA Error Trap

Reserved

DS70175D-page 70

Preliminary

PIC24H

The IPC registers are used to set the interrupt priority

level for each source of interrupt. Each user interrupt

source can be assigned to one of eight priority levels.

6.3

Interrupt Control and Status

Registers

PIC24H devices implement a total of 30 registers for

the interrupt controller:

The INTTREG register contains the associated inter-

rupt vector number and the new CPU interrupt priority

level, which are latched into vector number (VEC-

NUM<6:0>) and Interrupt level (ILR<3:0>) bit fields in

the INTTREG register. The new interrupt priority level

is the priority of the pending interrupt.

• INTCON1

• INTCON2

• IFS0 through IFS4

• IEC0 through IEC4

• IPC0 through IPC17

• INTTREG

The interrupt sources are assigned to the IFSx, IECx

and IPCx registers in the same sequence that they are

listed in Table 6-1. For example, the INT0 (External

Interrupt 0) is shown as having vector number 8 and a

natural order priority of 0. Thus, the INT0IF bit is found

in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP

bits in the first position of IPC0 (IPC0<2:0>).

Global interrupt control functions are controlled from

INTCON1 and INTCON2. INTCON1 contains the Inter-

rupt Nesting Disable (NSTDIS) bit as well as the control

and status flags for the processor trap sources. The

INTCON2 register controls the external interrupt

request signal behavior and the use of the Alternate

Interrupt Vector Table.

Although they are not specifically part of the interrupt

control hardware, two of the CPU Control registers con-

tain bits that control interrupt functionality. The CPU

STATUS register, SR, contains the IPL<2:0> bits

(SR<7:5>). These bits indicate the current CPU inter-

rupt priority level. The user can change the current

CPU priority level by writing to the IPL bits.

The IFS registers maintain all of the interrupt request

flags. Each source of interrupt has a Status bit, which

is set by the respective peripherals or external signal

and is cleared via software.

The IEC registers maintain all of the interrupt enable

bits. These control bits are used to individually enable

interrupts from the peripherals or external signals.

The CORCON register contains the IPL3 bit which,

together with IPL<2:0>, also indicates the current CPU

priority level. IPL3 is a read-only bit so that trap events

cannot be masked by the user software.

All Interrupt registers are described in Register 6-1,

SR: CPU STATUS Register⁽¹⁾through Register 6-32,

IPC17: Interrupt Priority Control Register 17, in the

following pages.

Preliminary

DS70175D-page 71

PIC24H

REGISTER 6-1:

SR: CPU STATUS REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

DC

bit 15

bit 8

R/W-0⁽³⁾

IPL2⁽²⁾

R/W-0⁽³⁾

IPL1⁽²⁾

R/W-0⁽³⁾

IPL0⁽²⁾

R-0

RA

R/W-0

N

R/W-0

OV

R/W-0

Z

R/W-0

C

bit 7

bit 0

Legend:

C = Clear only bit

S = Set only bit

‘1’ = Bit is set

R = Readable bit

W = Writable bit

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n = Value at POR

x = Bit is unknown

bit 7-5

IPL<2:0>: CPU Interrupt Priority Level Status bits⁽²⁾

111= CPU Interrupt Priority Level is 7 (15), user interrupts disabled

110= CPU Interrupt Priority Level is 6 (14)

101= CPU Interrupt Priority Level is 5 (13)

100= CPU Interrupt Priority Level is 4 (12)

011= CPU Interrupt Priority Level is 3 (11)

010= CPU Interrupt Priority Level is 2 (10)

001= CPU Interrupt Priority Level is 1 (9)

000= CPU Interrupt Priority Level is 0 (8)

Note 1: For complete register details, see Register 2-1, SR: CPU STATUS Register.

2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when

IPL<3> = 1.

3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

REGISTER 6-2:

CORCON: CORE CONTROL REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

R/C-0

IPL3⁽²⁾

R/W-0

PSV

U-0

—

U-0

—

bit 7

Legend:

C = Clear only bit

W = Writable bit

‘x = Bit is unknown

R = Readable bit

0’ = Bit is cleared

-n = Value at POR

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

bit 3

IPL3: CPU Interrupt Priority Level Status bit 3⁽²⁾

1= CPU interrupt priority level is greater than 7

0= CPU interrupt priority level is 7 or less

Note 1: For complete register details, see Register 2-2, CORCON: CORE Control Register.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

DS70175D-page 72

Preliminary

PIC24H

REGISTER 6-3:

INTCON1: INTERRUPT CONTROL REGISTER 1

R/W-0

NSTDIS

bit 15

R/W-0

OVAERR

OVBERR

COVAERR COVBERR

OVATE

OVBTE

COVTE

bit 8

R/W-0

SFTACERR

bit 7

R/W-0

U-0

—

DIV0ERR

DMACERR MATHERR ADDRERR

STKERR

OSCFAIL

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

NSTDIS: Interrupt Nesting Disable bit

1= Interrupt nesting is disabled

0= Interrupt nesting is enabled

OVAERR: Accumulator A Overflow Trap Flag bit

1= Trap was caused by overflow of Accumulator A

0= Trap was not caused by overflow of Accumulator A

OVBERR: Accumulator B Overflow Trap Flag bit

1= Trap was caused by overflow of Accumulator B

0= Trap was not caused by overflow of Accumulator B

COVAERR: Accumulator A Catastrophic Overflow Trap Enable bit

1= Trap was caused by catastrophic overflow of Accumulator A

0= Trap was not caused by catastrophic overflow of Accumulator A

COVBERR: Accumulator B Catastrophic Overflow Trap Enable bit

1= Trap was caused by catastrophic overflow of Accumulator B

0= Trap was not caused by catastrophic overflow of Accumulator B

OVATE: Accumulator A Overflow Trap Enable bit

1= Trap overflow of Accumulator A

0= Trap disabled

OVBTE: Accumulator B Overflow Trap Enable bit

1= Trap overflow of Accumulator B

0= Trap disabled

bit 8

COVTE: Catastrophic Overflow Trap Enable bit

1= Trap on catastrophic overflow of Accumulator A or B enabled

0= Trap disabled

bit 7

SFTACERR: Shift Accumulator Error Status bit

1= Math error trap was caused by an invalid accumulator shift

0= Math error trap was not caused by an invalid accumulator shift

bit 6

DIV0ERR: Arithmetic Error Status bit

1= Math error trap was caused by a divide by zero

0= Math error trap was not caused by a divide by zero

bit 5

DMACERR: DMA Controller Error Status bit

1= DMA controller error trap has occurred

0= DMA controller error trap has not occurred

bit 4

MATHERR: Arithmetic Error Status bit

1= Math error trap has occurred

0= Math error trap has not occurred

Preliminary

DS70175D-page 73

PIC24H

REGISTER 6-3:

INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)

bit 3

bit 2

bit 1

bit 0

ADDRERR: Address Error Trap Status bit

1= Address error trap has occurred

0= Address error trap has not occurred

STKERR: Stack Error Trap Status bit

1= Stack error trap has occurred

0= Stack error trap has not occurred

OSCFAIL: Oscillator Failure Trap Status bit

1= Oscillator failure trap has occurred

0= Oscillator failure trap has not occurred

Unimplemented: Read as ‘0’

DS70175D-page 74

Preliminary

PIC24H

REGISTER 6-4:

INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-0

ALTIVT

bit 15

R-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

DISI

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

INT4EP

INT3EP

INT2EP

INT1EP

INT0EP

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

ALTIVT: Enable Alternate Interrupt Vector Table bit

1= Use alternate vector table

0= Use standard (default) vector table

DISI: DISIInstruction Status bit

1= DISIinstruction is active

0= DISIinstruction is not active

bit 13-5

bit 4

Unimplemented: Read as ‘0’

INT4EP: External Interrupt 4 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

bit 3

bit 2

bit 1

bit 0

INT3EP: External Interrupt 3 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

Preliminary

DS70175D-page 75

PIC24H

REGISTER 6-5:

IFS0: INTERRUPT FLAG STATUS REGISTER 0

U-0

—

R/W-0

AD1IF

R/W-0

SPI1IF

R/W-0

T3IF

DMA1IF

U1TXIF

U1RXIF

SPI1EIF

bit 15

bit 8

R/W-0

T2IF

R/W-0

OC2IF

R/W-0

IC2IF

R/W-0

T1IF

R/W-0

OC1IF

R/W-0

IC1IF

R/W-0

INT0IF

DMA01IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

DMA1IF: DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 13

bit 12

bit 11

bit 10

bit 9

AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U1TXIF: UART1 Transmitter Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U1RXIF: UART1 Receiver Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPI1IF: SPI1 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPI1EIF: SPI1 Fault Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8

T3IF: Timer3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 7

T2IF: Timer2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 6

OC2IF: Output Compare Channel 2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 5

IC2IF: Input Capture Channel 2 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 4

DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 3

T1IF: Timer1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DS70175D-page 76

Preliminary

PIC24H

REGISTER 6-5:

IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)

bit 2

bit 1

bit 0

OC1IF: Output Compare Channel 1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

IC1IF: Input Capture Channel 1 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT0IF: External Interrupt 0 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

Preliminary

DS70175D-page 77

PIC24H

REGISTER 6-6:

IFS1: INTERRUPT FLAG STATUS REGISTER 1

R/W-0

U2TXIF

bit 15

R/W-0

INT2IF

R/W-0

T5IF

R/W-0

T4IF

R/W-0

OC4IF

R/W-0

OC3IF

R/W-0

U2RXIF

DMA21IF

bit 8

R/W-0

IC8IF

R/W-0

IC7IF

R/W-0

AD2IF

R/W-0

INT1IF

R/W-0

CNIF

R/W-0

—

R/W-0

MI2C1IF

SI2C1IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

U2TXIF: UART2 Transmitter Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

U2RXIF: UART2 Receiver Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT2IF: External Interrupt 2 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T5IF: Timer5 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T4IF: Timer4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

OC4IF: Output Compare Channel 4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

OC3IF: Output Compare Channel 3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 8

DMA2IF: DMA Channel 2 Data Transfer Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 7

IC8IF: Input Capture Channel 8 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 6

IC7IF: Input Capture Channel 7 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 5

AD2IF: ADC2 Conversion Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 4

INT1IF: External Interrupt 1 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DS70175D-page 78

Preliminary

PIC24H

REGISTER 6-6:

IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED)

bit 3

CNIF: Input Change Notification Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 2

bit 1

Unimplemented: Read as ‘0’

MI2C1IF: I2C1 Master Events Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 0

SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

Preliminary

DS70175D-page 79

PIC24H

REGISTER 6-7:

IFS2: INTERRUPT FLAG STATUS REGISTER 2

R/W-0

T6IF

R/W-0

U-0

—

R/W-0

OC8IF

R/W-0

OC7IF

R/W-0

OC6IF

R/W-0

OC5IF

R/W-0

IC6IF

DMA4IF

bit 15

bit 8

R/W-0

IC5IF

R/W-0

IC4IF

R/W-0

IC3IF

R/W-0

C1IF

R/W-0

SPI2IF

R/W-0

DMA3IF

C1RXIF

SPI2EIF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

T6IF: Timer6 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DMA4IF: DMA Channel 4 Data Transfer Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 13

bit 12

Unimplemented: Read as ‘0’

OC8IF: Output Compare Channel 8 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 11

bit 10

bit 9

bit 8

bit 7

bit 6

bit 5

bit 4

bit 3

OC7IF: Output Compare Channel 7 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

OC6IF: Output Compare Channel 6 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

OC5IF: Output Compare Channel 5 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

IC6IF: Input Capture Channel 6 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

IC5IF: Input Capture Channel 5 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

IC4IF: Input Capture Channel 4 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

IC3IF: Input Capture Channel 3 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

C1IF: ECAN1 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DS70175D-page 80

Preliminary

PIC24H

REGISTER 6-7:

IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED)

bit 2

bit 1

bit 0

C1RXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPI2IF: SPI2 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPI2EIF: SPI2 Error Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

Preliminary

DS70175D-page 81

PIC24H

REGISTER 6-8:

IFS3: INTERRUPT FLAG STATUS REGISTER 3

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

C2IF

DMA5IF

bit 15

bit 8

R/W-0

C2RXIF

bit 7

R/W-0

INT4IF

R/W-0

INT3IF

R/W-0

T9IF

R/W-0

T8IF

R/W-0

T7IF

MI2C2IF

SI2C2IF

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

DMA5IF: DMA Channel 5 Data Transfer Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 12-9

bit 8

Unimplemented: Read as ‘0’

C2IF: ECAN2 Event Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

C2RXIF: ECAN2 Receive Data Ready Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT4IF: External Interrupt 4 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT3IF: External Interrupt 3 Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T9IF: Timer9 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T8IF: Timer8 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

MI2C2IF: I2C2 Master Events Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SI2C2IF: I2C2 Slave Events Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T7IF: Timer7 Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DS70175D-page 82

Preliminary

PIC24H

REGISTER 6-9:

IFS4: INTERRUPT FLAG STATUS REGISTER 4

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

C2TXIF

bit 7

R/W-0

U-0

—

R/W-0

U2EIF

R/W-0

U1EIF

U-0

—

C1TXIF

DMA7IF

DMA6IF

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

C2TXIF: ECAN2 Transmit Data Request Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 6

bit 5

bit 4

C1TXIF: ECAN1 Transmit Data Request Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DMA7IF: DMA Channel 7 Data Transfer Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DMA6IF: DMA Channel 6 Data Transfer Complete Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 3

bit 2

Unimplemented: Read as ‘0’

U2EIF: UART2 Error Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 1

bit 0

U1EIF: UART1 Error Interrupt Flag Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

Unimplemented: Read as ‘0’

Preliminary

DS70175D-page 83

PIC24H

REGISTER 6-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0

U-0

—

R/W-0

AD1IE

R/W-0

T3IE

DMA1IE

U1TXIE

U1RXIE

SPI1IE

SPI1EIE

bit 15

bit 8

R/W-0

T2IE

R/W-0

OC2IE

R/W-0

IC2IE

R/W-0

T1IE

R/W-0

OC1IE

R/W-0

IC1IE

R/W-0

DMA0IE

INT0IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

DMA1IE: DMA Channel 1 Data Transfer Complete Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 13

bit 12

bit 11

bit 10

bit 9

AD1IE: ADC1 Conversion Complete Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

U1TXIE: UART1 Transmitter Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

U1RXIE: UART1 Receiver Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

SPI1IE: SPI1 Event Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

SPI1EIE: SPI1 Error Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 8

T3IE: Timer3 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 7

T2IE: Timer2 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 6

OC2IE: Output Compare Channel 2 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 5

IC2IE: Input Capture Channel 2 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 4

DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 3

T1IE: Timer1 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

DS70175D-page 84

Preliminary

PIC24H

REGISTER 6-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)

bit 2

bit 1

bit 0

OC1IE: Output Compare Channel 1 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

IC1IE: Input Capture Channel 1 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

INT0IE: External Interrupt 0 Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

Preliminary

DS70175D-page 85

PIC24H

REGISTER 6-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1

R/W-0

T5IE

R/W-0

T4IE

R/W-0

OC4IE

R/W-0

OC3IE

R/W-0

U2TXIE

U2RXIE

INT2IE

DMA2IE

bit 15

bit 8

R/W-0

IC8IE

R/W-0

IC7IE

R/W-0

AD2IE

R/W-0

CNIE

U-0

—

R/W-0

INT1IE

MI2C1IE

SI2C1IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

U2TXIE: UART2 Transmitter Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

U2RXIE: UART2 Receiver Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

INT2IE: External Interrupt 2 Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

T5IE: Timer5 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

T4IE: Timer4 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

OC4IE: Output Compare Channel 4 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

OC3IE: Output Compare Channel 3 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 8

DMA2IE: DMA Channel 2 Data Transfer Complete Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 7

IC8IE: Input Capture Channel 8 Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 6

IC7IE: Input Capture Channel 7 Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 5

AD2IE: ADC2 Conversion Complete Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 4

INT1IE: External Interrupt 1 Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

DS70175D-page 86

Preliminary

PIC24H

REGISTER 6-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED)

bit 3

CNIE: Input Change Notification Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 2

bit 1

Unimplemented: Read as ‘0’

MI2C1IE: I2C1 Master Events Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 0

SI2C1IE: I2C1 Slave Events Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

Preliminary

DS70175D-page 87

PIC24H

REGISTER 6-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2

R/W-0

T6IE

R/W-0

U-0

—

R/W-0

OC8IE

R/W-0

OC7IE

R/W-0

OC6IE

R/W-0

OC5IE

R/W-0

IC6IE

DMA4IE

bit 15

bit 8

R/W-0

IC5IE

R/W-0

IC4IE

R/W-0

IC3IE

R/W-0

C1IE

R/W-0

DMA3IE

C1RXIE

SPI2IE

SPI2EIE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

T6IE: Timer6 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

DMA4IE: DMA Channel 4 Data Transfer Complete Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 13

bit 12

Unimplemented: Read as ‘0’

OC8IE: Output Compare Channel 8 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

bit 11

bit 10

bit 9

bit 8

bit 7

bit 6

bit 5

bit 4

bit 3

OC7IE: Output Compare Channel 7 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

OC6IE: Output Compare Channel 6 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

OC5IE: Output Compare Channel 5 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

IC6IE: Input Capture Channel 6 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

IC5IE: Input Capture Channel 5 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

IC4IE: Input Capture Channel 4 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

IC3IE: Input Capture Channel 3 Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

C1IE: ECAN1 Event Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DS70175D-page 88

Preliminary

PIC24H

REGISTER 6-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 (CONTINUED)

bit 2

bit 1

bit 0

C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SPI2IE: SPI2 Event Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

SPI2EIE: SPI2 Error Interrupt Enable bit

1= Interrupt request enabled

0= Interrupt request not enabled

Preliminary

DS70175D-page 89

PIC24H

REGISTER 6-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

C2IE

DMA5IE

bit 15

bit 8

R/W-0

T9IE

R/W-0

T8IE

R/W-0

T7IE

C2RXIE

INT4IE

INT3IE

MI2C2IE

SI2C2IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 12-9

bit 8

Unimplemented: Read as ‘0’

C2IE: ECAN2 Event Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

C2RXIE: ECAN2 Receive Data Ready Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT4IE: External Interrupt 4 Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

INT3IE: External Interrupt 3 Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T9IE: Timer9 Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T8IE: Timer8 Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

MI2C2IE: I2C2 Master Events Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

SI2C2IE: I2C2 Slave Events Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

T7IE: Timer7 Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DS70175D-page 90

Preliminary

PIC24H

REGISTER 6-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

U-0

—

R/W-0

U2EIE

R/W-0

U1EIE

U-0

—

C2TXIE

C1TXIE

DMA7IE

DMA6IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

C2TXIE: ECAN2 Transmit Data Request Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 6

bit 5

bit 4

C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DMA7IE: DMA Channel 7 Data Transfer Complete Enable Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

DMA6IE: DMA Channel 6 Data Transfer Complete Enable Status bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 3

bit 2

Unimplemented: Read as ‘0’

U2EIE: UART2 Error Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

bit 1

bit 0

U1EIE: UART1 Error Interrupt Enable bit

1= Interrupt request has occurred

0= Interrupt request has not occurred

Unimplemented: Read as ‘0’

Preliminary

DS70175D-page 91

PIC24H

REGISTER 6-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

T1IP<2:0>

OC1IP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

IC1IP<2:0>

INT0IP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

T1IP<2:0>: Timer1 Interrupt Priority bits

bit 14-12

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

INT0IP<2:0>: External Interrupt 0 Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70175D-page 92

Preliminary

PIC24H

REGISTER 6-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

T2IP<2:0>

OC2IP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

IC2IP<2:0>

DMA0IP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

T2IP<2:0>: Timer2 Interrupt Priority bits

bit 14-12

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

Preliminary

DS70175D-page 93

PIC24H

REGISTER 6-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

U1RXIP<2:0>

SPI1IP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

SPI1EIP<2:0>

T3IP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

SPI1IP<2:0>: SPI1 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

T3IP<2:0>: Timer3 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70175D-page 94

Preliminary

PIC24H

REGISTER 6-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

DMA1IP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

AD1IP<2:0>

U1TXIP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

DMA1IP<2:0>: DMA Channel 1 Data Transfer Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

Preliminary

DS70175D-page 95

PIC24H

REGISTER 6-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

CNIP<2:0>

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

MI2C1IP<2:0>

SI2C1IP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

CNIP<2:0>: Change Notification Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11-7

bit 6-4

Unimplemented: Read as ‘0’

MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70175D-page 96

Preliminary

PIC24H

REGISTER 6-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

IC8IP<2:0>

IC7IP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

AD2IP<2:0>

INT1IP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

AD2IP<2:0>: ADC2 Conversion Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

INT1IP<2:0>: External Interrupt 1 Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

Preliminary

DS70175D-page 97

PIC24H

REGISTER 6-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

T4IP<2:0>

OC4IP<2:0>

bit 15

bit 8

R/W-0

bit 0

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

OC3IP<2:0>

DMA2IP<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

T4IP<2:0>: Timer4 Interrupt Priority bits

bit 14-12

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70175D-page 98

Preliminary

PIC24H

REGISTER 6-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

U2TXIP<2:0>

U2RXIP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

INT2IP<2:0>

T5IP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

INT2IP<2:0>: External Interrupt 2 Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

T5IP<2:0>: Timer5 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

Preliminary

DS70175D-page 99

PIC24H

REGISTER 6-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

C1IP<2:0>

C1RXIP<2:0>

bit 15

bit 8

R/W-0

bit 0

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

SPI2IP<2:0>

SPI2EIP<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

C1IP<2:0>: ECAN1 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

C1RXIP<2:0>: ECAN1 Receive Data Ready Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

SPI2IP<2:0>: SPI2 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70175D-page 100

Preliminary

PIC24H

REGISTER 6-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

IC5IP<2:0>

IC4IP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

IC3IP<2:0>

DMA3IP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

Preliminary

DS70175D-page 101

PIC24H

REGISTER 6-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

OC7IP<2:0>

OC6IP<2:0>

bit 15

bit 8

R/W-0

bit 0

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

OC5IP<2:0>

IC6IP<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

OC7IP<2:0>: Output Compare Channel 7 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

OC6IP<2:0>: Output Compare Channel 6 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70175D-page 102

Preliminary

PIC24H

REGISTER 6-26: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

T6IP<2:0>

DMA4IP<2:0>

bit 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

OC8IP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

T6IP<2:0>: Timer6 Interrupt Priority bits

bit 14-12

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

DMA4IP<2:0>: DMA Channel 4 Data Transfer Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

OC8IP<2:0>: Output Compare Channel 8 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

Preliminary

DS70175D-page 103

PIC24H

REGISTER 6-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

T8IP<2:0>

MI2C2IP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

SI2C2IP<2:0>

T7IP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

T8IP<2:0>: Timer8 Interrupt Priority bits

bit 14-12

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

MI2C2IP<2:0>: I2C2 Master Events Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

SI2C2IP<2:0>: I2C2 Slave Events Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

T7IP<2:0>: Timer7 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70175D-page 104

Preliminary

PIC24H

REGISTER 6-28: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

C2RXIP<2:0>

INT4IP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

INT3IP<2:0>

T9IP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

C2RXIP<2:0>: ECAN2 Receive Data Ready Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

INT4IP<2:0>: External Interrupt 4 Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

INT3IP<2:0>: External Interrupt 3 Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

T9IP<2:0>: Timer9 Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

Preliminary

DS70175D-page 105

PIC24H

REGISTER 6-29: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

C2IP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-0

Unimplemented: Read as ‘0’

C2IP<2:0>: ECAN2 Event Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

DS70175D-page 106

Preliminary

PIC24H

REGISTER 6-30: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

DMA5IP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-7

bit 6-4

Unimplemented: Read as ‘0’

DMA5IP<2:0>: DMA Channel 5 Data Transfer Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

Preliminary

DS70175D-page 107

PIC24H

REGISTER 6-31: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

bit 8

U2EIP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U1EIP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

U2EIP<2:0>: UART2 Error Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

U1EIP<2:0>: UART1 Error Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3-0

Unimplemented: Read as ‘0’

DS70175D-page 108

Preliminary

PIC24H

REGISTER 6-32: IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

bit 8

R/W-0

C2TXIP<2:0>

C1TXIP<2:0>

bit 15

U-0

—

R/W-1

R/W-0

U-0

—

R/W-1

R/W-0

DMA7IP<2:0>

DMA6IP<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

C2TXIP<2:0>: ECAN2 Transmit Data Request Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 11

Unimplemented: Read as ‘0’

bit 10-8

C1TXIP<2:0>: ECAN1 Transmit Data Request Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 7

Unimplemented: Read as ‘0’

bit 6-4

DMA7IP<2:0>: DMA Channel 7 Data Transfer Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits

111= Interrupt is priority 7 (highest priority interrupt)

•

001= Interrupt is priority 1

000= Interrupt source is disabled

Preliminary

DS70175D-page 109

PIC24H

REGISTER 6-33: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER

R-0

—

R/W-0

—

U-0

—

U-0

—

R-0

ILR<3:0>

bit 15

bit 8

bit 0

U-0

—

U-0

R-0

VECNUM<6:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

bit 11-8

Unimplemented: Read as ‘0’

ILR<3:0>: New CPU Interrupt Priority Level bits

1111= CPU Interrupt Priority Level is 15

•

0001 = CPU Interrupt Priority Level is 1

0000= CPU Interrupt Priority Level is 0

bit 7

Unimplemented: Read as ‘0’

bit 6-0

VECNUM<6:0>: Vector Number of Pending Interrupt bits

1111111= Interrupt Vector pending is number 135

•

0000001= Interrupt Vector pending is number 9

0000000= Interrupt Vector pending is number 8

DS70175D-page 110

Preliminary

PIC24H

6.4.3

TRAP SERVICE ROUTINE

6.4

Interrupt Setup Procedures

A Trap Service Routine (TSR) is coded like an ISR,

except that the appropriate trap status flag in the

INTCON1 register must be cleared to avoid re-entry

into the TSR.

6.4.1

INITIALIZATION

To configure an interrupt source:

1. Set the NSTDIS bit (INTCON1<15>) if nested

interrupts are not desired.

6.4.4

INTERRUPT DISABLE

2. Select the user-assigned priority level for the

interrupt source by writing the control bits in the

appropriate IPCx register. The priority level will

depend on the specific application and type of

interrupt source. If multiple priority levels are not

desired, the IPCx register control bits for all

enabled interrupt sources may be programmed

to the same non-zero value.

All user interrupts can be disabled using the following

procedure:

1. Push the current SR value onto the software

stack using the PUSHinstruction.

2. Force the CPU to priority level 7 by inclusive

ORing the value 0x0E with SRL.

To enable user interrupts, the POPinstruction may be

Note: At a device Reset, the IPCx registers are

initialized, such that all user interrupt

sources are assigned to priority level 4.

used to restore the previous SR value.

Note that only user interrupts with a priority level of 7 or

less can be disabled. Trap sources (level 8-level 15)

cannot be disabled.

3. Clear the interrupt flag status bit associated with

the peripheral in the associated IFSx register.

The DISIinstruction provides a convenient way to dis-

able interrupts of priority levels 1-6 for a fixed period of

time. Level 7 interrupt sources are not disabled by the

DISI instruction.

4. Enable the interrupt source by setting the inter-

rupt enable control bit associated with the

source in the appropriate IECx register.

6.4.2

INTERRUPT SERVICE ROUTINE

The method that is used to declare an ISR and initialize

the IVT with the correct vector address will depend on

the programming language (i.e., C or assembler) and

the language development toolsuite that is used to

develop the application. In general, the user must clear

the interrupt flag in the appropriate IFSx register for the

source of interrupt that the ISR handles. Otherwise, the

ISR will be re-entered immediately after exiting the

routine. If the ISR is coded in assembly language, it

must be terminated using a RETFIE instruction to

unstack the saved PC value, SRL value and old CPU

priority level.

Preliminary

DS70175D-page 111

PIC24H

NOTES:

DS70175D-page 112

Preliminary

PIC24H

Each channel has its own set of control and status

registers. Each DMA channel can be configured to

copy data either from buffers stored in dual port DMA

RAM to peripheral SFRs, or from peripheral SFRs to

buffers in DMA RAM.

7.0

DIRECT MEMORY ACCESS

(DMA)

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

The DMA controller supports the following features:

• Word or byte sized data transfers.

• Transfers from peripheral to DMA RAM or DMA

RAM to peripheral.

Direct Memory Access (DMA) is a very efficient

mechanism of copying data between peripheral SFRs

(e.g., UART Receive register, Input Capture 1 buffer),

and buffers or variables stored in RAM, with minimal

CPU intervention. The DMA controller can

automatically copy entire blocks of data without

requiring the user software to read or write the

peripheral Special Function Registers (SFRs) every

time a peripheral interrupt occurs. The DMA controller

uses a dedicated bus for data transfers and, therefore,

does not steal cycles from the code execution flow of

the CPU. To exploit the DMA capability, the

corresponding user buffers or variables must be

located in DMA RAM.

• Indirect Addressing of DMA RAM locations with or

without automatic post-increment.

• Peripheral Indirect Addressing – In some periph-

erals, the DMA RAM read/write addresses may

be partially derived from the peripheral.

• One-Shot Block Transfers – Terminating DMA

transfer after one block transfer.

• Continuous Block Transfers – Reloading DMA

RAM buffer start address after every block

transfer is complete.

• Ping-Pong Mode – Switching between two DMA

RAM start addresses between successive block

transfers, thereby filling two buffers alternately.

• Automatic or manual initiation of block transfers

The PIC24H peripherals that can utilize DMA are listed

in Table 7-1 along with their associated Interrupt

Request (IRQ) numbers.

• Each channel can select from 19 possible

sources of data sources or destinations.

For each DMA channel, a DMA interrupt request is

TABLE 7-1:

PERIPHERALS WITH DMA

SUPPORT

generated when

a

block transfer is complete.

Alternatively, an interrupt can be generated when half of

the block has been filled.

Peripheral

IRQ Number

INT0

0

Input Capture 1

Input Capture 2

Output Compare 1

Output Compare 2

Timer2

1

5

2

6

7

Timer3

8

SPI1

10

33

11

12

30

31

13

21

34

70

55

71

SPI2

UART1 Reception

UART1 Transmission

UART2 Reception

UART2 Transmission

ADC1

ADC2

ECAN1 Reception

ECAN1 Transmission

ECAN2 Reception

ECAN2 Transmission

The DMA controller features eight identical data

transfer channels.

Preliminary

DS70175D-page 113

PIC24H

FIGURE 7-1:

TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS

Peripheral Indirect Address

DMA Controller

DMA

Ready

Peripheral 3

DMA

Channels

DMA RAM

SRAM

PORT 1 PORT 2

CPU

DMA

SRAM X-Bus

DMA DS Bus

CPU Peripheral DS Bus

CPU

DMA

CPU

DMA

Non-DMA

Ready

Peripheral

DMA

Ready

Peripheral 2

DMA

Ready

Peripheral 1

CPU

Note: CPU and DMA address buses are not shown for clarity.

an IECx register in the interrupt controller, and the cor-

responding interrupt priority control bits (DMAxIP) are

located in an IPCx register in the interrupt controller.

7.1

DMAC Registers

Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)

contains the following registers:

• A 16-bit DMA Channel Control register

(DMAxCON)

7.2

DMAC Operating Modes

Each DMA channel has its own status and control reg-

ister (DMAxCON) that is used to configure the channel

to support the following operating modes:

• A 16-bit DMA Channel IRQ Select register

(DMAxREQ)

• A 16-bit DMA RAM Primary Start Address register

(DMAxSTA)

• Word or byte size data transfers

• Peripheral to DMA RAM or DMA RAM to

peripheral transfers

• A 16-bit DMA RAM Secondary Start Address

register (DMAxSTB)

• Post-increment or static DMA RAM address

• One-shot or continuous block transfers

• A 16-bit DMA Peripheral Address register

(DMAxPAD)

• Auto-switch between two start addresses after

each transfer complete (Ping-Pong mode)

• A 10-bit DMA Transfer Count register (DMAx-

CNT)

• Force a single DMA transfer (Manual mode)

An additional status register, DMACS, is common to

all DMAC channels. It contains the DMA RAM and

SFR write collision flags, XWCOLx and PWCOLx,

respectively.

Each DMA channel can be independently configured

to:

• Select from one of 19 DMA request sources

• Manually enable or disable the DMA channel

The DMAxCON, DMAxREQ, DMAxPAD and

DMAxCNT are all conventional read/write registers.

Reads of DMAxSTA or DMAxSTB will read the con-

tents of the DMA RAM Address register. Writes to

DMAxSTA or DMAxSTB write to the registers. This

allows the user to determine the DMA buffer pointer

value (address) at any time.

• Interrupt the CPU when the transfer is half or fully

complete

DMA channel interrupts are routed to the interrupt con-

troller module and enabled through associated enable

flags.

The channel DMA RAM and peripheral write collision

Faults are combined into a single DMAC error trap

(Level 10) and are not maskable. Each channel has

DMA RAM write collision (XWCOLx) and peripheral

The interrupt flags (DMAxIF) are located in an IFSx

register in the interrupt controller. The corresponding

interrupt enable control bits (DMAxIE) are located in

DS70175D-page 114

Preliminary

PIC24H

write collision (PWCOLx) status bits in the DMAC Sta-

tus register (DMACS) to allow the DMAC error trap

handler to determine the source of the Fault condition.

Any DMA channel can be configured to operate in

Peripheral Indirect Addressing mode by setting the

AMODE<1:0> bits to ‘10’. In this mode, the DMA RAM

source or destination address is partially derived from

the peripheral as well as the DMA Address registers.

Each peripheral module has a pre-assigned peripheral

indirect address which is logically ORed with the DMA

Start Address register to obtain the effective DMA RAM

address. The DMA RAM Start Address register value

must be aligned to a power-of-two boundary.

7.2.1

BYTE OR WORD TRANSFER

Each DMA channel can be configured to transfer

words or bytes. As usual, words can only be moved to

and from aligned (even) addresses. Bytes can be

moved to or from any (legal) address.

If the SIZE bit (DMAxCON<14>) is clear, word sized

data is transferred. The LSb of the DMA RAM Address

register (DMAxSTA or DMAxSTB) is ignored. If

Post-Increment Addressing mode is enabled, the DMA

RAM Address register is incremented by 2 after every

word transfer.

Note:

Only the ECAN and A/D modules can

utilize Peripheral Indirect Addressing.

7.2.3

DMA TRANSFER DIRECTION

Each DMA channel can be configured to transfer data

from a peripheral to DMA RAM, or from DMA RAM to a

peripheral.

If the SIZE bit is set, byte sized data is transferred. If

Post-Increment Addressing is enabled, the DMA RAM

Address register is incremented by 1 after every byte

transfer.

If the DIR bit (DMAxCON<13>) is clear, the reads

occur from a peripheral SFR (using the DMA Periph-

eral Address register, DMAxPAD) and the writes are

directed to the DMA RAM (using the DMA RAM

Address register).

Note:

DMAxCNT value is independent of data

transfer size (byte/word). If an address off-

set is required, a 1-bit left shift of the

counter is required to generate the correct

offset for (aligned) word transfers.

If the DIR bit (DMAxCON<13>) is set, the reads occur

from the DMA RAM (using the DMA RAM Address

register) and the writes are directed to the peripheral

(using the DMA Peripheral Address register,

DMAxPAD).

7.2.2

ADDRESSING MODES

The DMAC supports Register Indirect and Register

Indirect Post-Increment Addressing modes for DMA

RAM addresses (source or destination). Each channel

can select the DMA RAM Addressing mode indepen-

dently. The Peripheral SFR is always accessed using

Register Indirect Addressing.

7.2.4

NULL DATA PERIPHERAL WRITE

MODE

If the NULLW bit (DMAxCON<11>) is set, a null data

write to the peripheral SFR is performed in addition to

a data transfer from the peripheral SFR to DMA RAM

(assuming the DIR bit is clear). This mode is most use-

ful in applications in which sequential reception of data

is required without any data transmission.

If the AMODE<1:0> bits (DMAxCON<5:4>) are set to

‘01’,

Register

Indirect

Addressing

without

Post-Increment is used, which implies that the DMA

RAM address remains constant.

If the AMODE<1:0> bits are clear, DMA RAM is

accessed using Register Indirect Addressing with

Post-Increment, which means the DMA RAM address

will be incremented after every access.

Preliminary

DS70175D-page 115

PIC24H

serial peripheral allows subsequent data within the

buffer to be moved automatically by the DMAC using a

‘transmit buffer empty’ DMA request.

7.2.5

CONTINUOUS OR ONE-SHOT

OPERATION

Each DMA channel can be configured for One-Shot or

Continuous mode operation.

7.2.8

DMA REQUEST SOURCE

SELECTION

If MODE<0> (DMAxCON<0>) is clear, the channel

operates in Continuous mode.

Each DMA channel can select between one of 128

interrupt sources to be a DMA request for that chan-

nel, based on the contents of the IRQSEL<6:0> bits

(DMAxREQ<6:0>. The available interrupt sources are

device dependent. Please refer to Table 7-1 for IRQ

numbers associated with each of the interrupt sources

that can generate a DMA transfer.

When all data has been moved (i.e., buffer end has

been detected), the channel is automatically reconfig-

ured for subsequent use. During the last data transfer,

the next Effective Address generated will be the origi-

nal start address (from the selected DMAxSTA or

DMAxSTB register). If the HALF bit (DMAxCON<12>)

is clear, the transfer complete interrupt flag (DMAxIF)

is set. If the HALF bit is set, DMAxIF will not be set at

this time and the channel will remain enabled.

7.3

DMA Interrupts and Traps

Each DMA channel can generate an independent

‘block transfer complete’ (HALF = 0) or ‘half block

transfer complete’ (HALF = 1) interrupt. Every DMA

channel has its own interrupt vector and therefore,

does not use the interrupt vector of the peripheral to

which it is assigned. If a peripheral contains multi-word

buffers, the buffering function must be disabled in the

peripheral in order to use DMA. DMA interrupt

requests are only generated by data transfers and not

by peripheral error conditions.

If MODE<0> is set, the channel operates in One-Shot

mode. When all data has been moved (i.e., buffer end

has been detected), the channel is automatically dis-

abled. During the last data transfer, no new Effective

Address is generated and the DMA RAM Address

register retains the last DMA RAM address that was

accessed. If the HALF bit is clear, the DMAxIF bit is

set. If the HALF bit is set, the DMAxIF will not be set at

this time and the channel is automatically disabled.

7.2.6

PING-PONG MODE

The DMA controller can also react to peripheral and

DMA RAM write collision error conditions through a

nonmaskable CPU trap event. A DMA error trap is

generated in either of the following Fault conditions:

When the MODE<1> bit (DMAxCON<1>) is set by the

user, Ping-Pong mode is enabled.

In this mode, successive block transfers alternately

select DMAxSTA and DMAxSTB as the DMA RAM

start address. In this way, a single DMA channel can

be used to support two buffers of the same length in

DMA RAM. Using this technique maximizes data

throughput by allowing the CPU time to process one

buffer while the other is being loaded.

• DMA RAM data write collision between the CPU

and a peripheral

- This condition occurs when the CPU and a

peripheral attempt to write to the same DMA

RAM address simultaneously

• Peripheral SFR data write collision between the

CPU and the DMA controller

7.2.7

MANUAL TRANSFER MODE

- This condition occurs when the CPU and the

DMA controller attempt to write to the same

peripheral SFR simultaneously

A manual DMA request can be created by setting the

FORCE bit (DMAxREQ<15>) in software. If already

enabled, the corresponding DMA channel executes a

single data element transfer rather than a block trans-

fer.

The channel DMA RAM and peripheral write collision

Faults are combined into a single DMAC error trap

(Level 10) and are nonmaskable. Each channel has

DMA RAM Write Collision (XWCOLx) and Peripheral

Write Collision (PWCOLx) status bits in the DMAC

Status register (DMACS) to allow the DMAC error trap

handler to determine the source of the Fault condition.

The FORCE bit is cleared by hardware when the

forced DMA transfer is complete and cannot be

cleared by the user. Any attempt to set this bit prior to

completion of a DMA request that is underway will

have no effect.

The manual DMA transfer function is a one-time event.

The DMA channel always reverts to normal operation

(i.e., based on hardware DMA requests) after a forced

(manual) transfer.

This mode provides the user a straightforward method

of initiating a block transfer. For example, using

Manual mode to transfer the first data element into a

DS70175D-page 116

Preliminary

PIC24H

7.4

DMA Initialization Example

The following is a DMA initialization example:

EXAMPLE 7-1:

DMA SAMPLE INITIALIZATION METHOD

// Clear all DMA controller status bits to a known state

DMACS0 = 0;

// Set up DMA Channel 0: Word mode, Read from Peripheral & Write to DMA; Interrupt when all the

data has been moved; Indirect with post-increment; Continuous mode with Ping-Pong Disabled

DMA0CON = 0x000D;

//Automatic DMA transfer initiation by DMA request; DMA Peripheral IRQ Number set up for ADC1

DMA0REQ = 0x0000;

// Set up offset into DMA RAM so that the buffer that collects A/D result data starts at the base

of DMA RAM

DMA0STA = 0x0000;

// DMA0PAD should be loaded with the address of the A/D conversion result register

DMA0PAD = (volatile unsigned int) &ADC1BUF0;

// DMA transfer of 256 words of data

DMA0CNT = 0x0100 ;

//Clear the DMA0 Interrupt Flag

IFS0bits.DMA0IF = 0;

//Enable DMA0 Interrupts

IEC0bits.DMA0IE = 1;

//Enable the DMA0 Channel

DMA0CONbits.CHEN = 1;

Preliminary

DS70175D-page 117

PIC24H

REGISTER 7-1:

DMAxCON: DMA CHANNEL x CONTROL REGISTER

R/W-0

CHEN

R/W-0

SIZE

R/W-0

DIR

R/W-0

HALF

R/W-0

U-0

—

U-0

—

U-0

—

NULLW

bit 15

bit 8

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0

AMODE<1:0>

MODE<1:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

bit 12

bit 11

CHEN: Channel Enable bit

1= Channel enabled

0= Channel disabled

SIZE: Data Transfer Size bit

1= Byte

0= Word

DIR: Transfer Direction bit (source/destination bus select)

1= Read from DMA RAM address, write to peripheral address

0= Read from peripheral address, write to DMA RAM address

HALF: Early Block Transfer Complete Interrupt Select bit

1= Initiate block transfer complete interrupt when half of the data has been moved

0= Initiate block transfer complete interrupt when all of the data has been moved

NULLW: Null Data Peripheral Write Mode Select bit

1= Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear)

0= Normal operation

bit 10-6

bit 5-4

Unimplemented: Read as ‘0’

AMODE<1:0>: DMA Channel Operating Mode Select bits

11= Reserved (will act as Peripheral Indirect Addressing mode)

10= Peripheral Indirect Addressing mode

01= Register Indirect without Post-Increment mode

00= Register Indirect with Post-Increment mode

bit 3-2

bit 1-0

Unimplemented: Read as ‘0’

MODE<1:0>: DMA Channel Operating Mode Select bits

11= One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer)

10= Continuous, Ping-Pong modes enabled

01= One-Shot, Ping-Pong modes disabled

00= Continuous, Ping-Pong modes disabled

DS70175D-page 118

Preliminary

PIC24H

REGISTER 7-2:

DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER

R/W-0

FORCE⁽¹⁾

bit 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 8

U-0

—

R/W-0

U-0

R/W-0

IRQSEL6⁽²⁾IRQSEL5⁽²⁾IRQSEL4⁽²⁾IRQSEL3⁽²⁾IRQSEL2⁽²⁾

IRQSEL1⁽²⁾IRQSEL0⁽²⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

FORCE: Force DMA Transfer bit⁽¹⁾

1= Force a single DMA transfer (Manual mode)

0= Automatic DMA transfer initiation by DMA request

bit 14-7

bit 6-0

Unimplemented: Read as ‘0’

IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits⁽²⁾

0000000-1111111= DMAIRQ0-DMAIRQ127 selected to be Channel DMAREQ

Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced

DMA transfer is complete.

2: Please see Table 6-1 for a complete listing of IRQ numbers for all interrupt sources.

Preliminary

DS70175D-page 119

PIC24H

REGISTER 7-3:

DMAxSTA: DMA CHANNEL x RAM START ADDRESS REGISTER A⁽¹⁾

R/W-0

bit 8

R/W-0

STA<15:8>

bit 15

R/W-0

bit 7

R/W-0

STA<7:0>

R/W-0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

STA<15:0>: Primary DMA RAM Start Address bits (source or destination)

Note 1: A read of this address register will return the current contents of the DMA RAM Address register, not the

contents written to STA<15:0>. If the channel is enabled (i.e., active), writes to this register may result in

unpredictable behavior of the DMA channel and should be avoided.

REGISTER 7-4:

DMAxSTB: DMA CHANNEL x RAM START ADDRESS REGISTER B⁽¹⁾

R/W-0

bit 8

R/W-0

STB<15:8>

bit 15

R/W-0

bit 7

R/W-0

STB<7:0>

R/W-0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

STB<15:0>: Secondary DMA RAM Start Address bits (source or destination)

Note 1: A read of this address register will return the current contents of the DMA RAM Address register, not the

contents written to STB<15:0>. If the channel is enabled (i.e., active), writes to this register may result in

unpredictable behavior of the DMA channel and should be avoided.

DS70175D-page 120

Preliminary

PIC24H

REGISTER 7-5:

DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER⁽¹⁾

R/W-0

PAD<15:8>

bit 15

R/W-0

bit 7

bit 8

R/W-0

bit 0

R/W-0

R/W-0 R/W-0

PAD<7:0>

R/W-0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

PAD<15:0>: Peripheral Address Register bits

Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the

DMA channel and should be avoided.

REGISTER 7-6:

DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CNT<9:8>⁽²⁾

bit 8

bit 15

R/W-0

bit 7

R/W-0

bit 0

CNT<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-10

bit 9-0

Unimplemented: Read as ‘0’

CNT<9:0>: DMA Transfer Count Register bits⁽²⁾

Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the

DMA channel and should be avoided.

2: Number of DMA transfers = CNT<9:0> + 1.

Preliminary

DS70175D-page 121

PIC24H

REGISTER 7-7:

DMACS0: DMA CONTROLLER STATUS REGISTER 0

R/C-0

PWCOL7

bit 15

PWCOL6

PWCOL5

PWCOL4

PWCOL3

PWCOL2

PWCOL1

PWCOL0

bit 8

R/C-0

XWCOL7

XWCOL6

XWCOL5

XWCOL4

XWCOL3

XWCOL2

XWCOL1

XWCOL0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

PWCOL7: Channel 7 Peripheral Write Collision Flag bit

1= Write collision detected

0= No write collision detected

PWCOL6: Channel 6 Peripheral Write Collision Flag bit

1= Write collision detected

0= No write collision detected

PWCOL5: Channel 5 Peripheral Write Collision Flag bit

1= Write collision detected

0= No write collision detected

PWCOL4: Channel 4 Peripheral Write Collision Flag bit

1= Write collision detected

0= No write collision detected

PWCOL3: Channel 3 Peripheral Write Collision Flag bit

1= Write collision detected

0= No write collision detected

PWCOL2: Channel 2 Peripheral Write Collision Flag bit

1= Write collision detected

0= No write collision detected

PWCOL1: Channel 1 Peripheral Write Collision Flag bit

1= Write collision detected

0= No write collision detected

bit 8

PWCOL0: Channel 0 Peripheral Write Collision Flag bit

1= Write collision detected

0= No write collision detected

bit 7

XWCOL7: Channel 7 DMA RAM Write Collision Flag bit

1= Write collision detected

0= No write collision detected

bit 6

XWCOL6: Channel 6 DMA RAM Write Collision Flag bit

1= Write collision detected

0= No write collision detected

bit 5

XWCOL5: Channel 5 DMA RAM Write Collision Flag bit

1= Write collision detected

0= No write collision detected

bit 4

XWCOL4: Channel 4 DMA RAM Write Collision Flag bit

1= Write collision detected

0= No write collision detected

DS70175D-page 122

Preliminary

PIC24H

REGISTER 7-7:

DMACS0: DMA CONTROLLER STATUS REGISTER 0 (CONTINUED)

bit 3

bit 2

bit 1

bit 0

XWCOL3: Channel 3 DMA RAM Write Collision Flag bit

1= Write collision detected

0= No write collision detected

XWCOL2: Channel 2 DMA RAM Write Collision Flag bit

1= Write collision detected

0= No write collision detected

XWCOL1: Channel 1 DMA RAM Write Collision Flag bit

1= Write collision detected

0= No write collision detected

XWCOL0: Channel 0 DMA RAM Write Collision Flag bit

1= Write collision detected

0= No write collision detected

Preliminary

DS70175D-page 123

PIC24H

REGISTER 7-8:

DMACS1: DMA CONTROLLER STATUS REGISTER 1

U-0

—

U-0

—

U-0

—

U-0

—

R-1

R-0

LSTCH<3:0>

bit 15

bit 8

R-0

PPST7

bit 7

R-0

PPST6

PPST5

PPST4

PPST3

PPST2

PPST1

PPST0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

bit 11-8

Unimplemented: Read as ‘0’

LSTCH<3:0>: Last DMA Channel Active bits

1111= No DMA transfer has occurred since system Reset

1110-1000= Reserved

0111= Last data transfer was by DMA Channel 7

0110= Last data transfer was by DMA Channel 6

0101= Last data transfer was by DMA Channel 5

0100= Last data transfer was by DMA Channel 4

0011= Last data transfer was by DMA Channel 3

0010= Last data transfer was by DMA Channel 2

0001= Last data transfer was by DMA Channel 1

0000= Last data transfer was by DMA Channel 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PPST7: Channel 7 Ping-Pong Mode Status Flag bit

1= DMA7STB register selected

0= DMA7STA register selected

PPST6: Channel 6 Ping-Pong Mode Status Flag bit

1= DMA6STB register selected

0= DMA6STA register selected

PPST5: Channel 5 Ping-Pong Mode Status Flag bit

1= DMA5STB register selected

0= DMA5STA register selected

PPST4: Channel 4 Ping-Pong Mode Status Flag bit

1= DMA4STB register selected

0= DMA4STA register selected

PPST3: Channel 3 Ping-Pong Mode Status Flag bit

1= DMA3STB register selected

0= DMA3STA register selected

PPST2: Channel 2 Ping-Pong Mode Status Flag bit

1= DMA2STB register selected

0= DMA2STA register selected

PPST1: Channel 1 Ping-Pong Mode Status Flag bit

1= DMA1STB register selected

0= DMA1STA register selected

PPST0: Channel 0 Ping-Pong Mode Status Flag bit

1= DMA0STB register selected

0= DMA0STA register selected

DS70175D-page 124

Preliminary

PIC24H

REGISTER 7-9:

DSADR: MOST RECENT DMA RAM ADDRESS

R-0

bit 8

R-0

bit 0

DSADR<15:8>

bit 15

R-0

DSADR<7:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits

Preliminary

DS70175D-page 125

PIC24H

NOTES:

DS70175D-page 126

Preliminary

PIC24H

• The internal FRC oscillator can also be used with

the PLL, thereby allowing full-speed operation

without any external clock generation hardware

8.0

OSCILLATOR

CONFIGURATION

• Clock switching between various clock sources

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

• Programmable clock postscaler for system power

savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and takes fail-safe measures

• A Clock Control register (OSCCON)

The PIC24H oscillator system provides:

• Nonvolatile Configuration bits for main oscillator

selection.

• Various external and internal oscillator options as

clock sources

A simplified diagram of the oscillator system is shown

in Figure 8-1.

• An on-chip PLL to scale the internal operating

frequency to the required system clock frequency

FIGURE 8-1:

PIC24H OSCILLATOR SYSTEM DIAGRAM

PIC24H

Primary Oscillator

XT, HS, EC

DOZE<2:0>

OSC2

OSC1

XTPLL, HSPLL,

ECPLL, FRCPLL

CPU

PLL

FRC, FRCDIVN

Peripherals

FRC

Oscillator

FRCDIV<2:0>

, FRCDIV16

LPRC

Divide

by 16

LPRC

Oscillator

Secondary Oscillator

SOSC

SOSCO

SOSCI

SOSCEN

Enable

Oscillator

Clock Control Logic

Fail-Safe

Clock

Monitor

WDT, PWRT

Clock Source Option

for other Modules

Preliminary

DS70175D-page 127

PIC24H

(FOSC<1:0>), select the oscillator source that is used at

a Power-on Reset. The FRC primary oscillator is the

default (unprogrammed) selection.

8.1

CPU Clocking System

There are seven system clock options provided by the

PIC24H:

The Configuration bits allow users to choose between

twelve different clock modes, shown in Table 8-1.

• FRC Oscillator

• FRC Oscillator with PLL

• Primary (XT, HS or EC) Oscillator

• Primary Oscillator with PLL

• Secondary (LP) Oscillator

• LPRC Oscillator

The output of the oscillator (or the output of the PLL if

a PLL mode has been selected) FOSC is divided by 2 to

generate the device instruction clock (FCY). FCY

defines the operating speed of the device, and speeds

up to 40 MHz are supported by the PIC24H

architecture.

• FRC Oscillator with postscaler

Instruction execution speed or device operating

frequency, FCY, is given by:

8.1.1

SYSTEM CLOCK SOURCES

The FRC (Fast RC) internal oscillator runs at a nominal

frequency of 7.37 MHz. The user software can tune the

FRC frequency. User software can optionally specify a

factor (ranging from 1:2 to 1:256) by which the FRC

clock frequency is divided. This factor is selected using

the FRCDIV<2:0> (CLKDIV<10:8>) bits.

EQUATION 8-1:

DEVICE OPERATING

FREQUENCY

FCY = FOSC/2

8.1.3

PLL CONFIGURATION

The primary oscillator can use one of the following as

its clock source:

The primary oscillator and internal FRC oscillator can

optionally use an on-chip PLL to obtain higher speeds

of operation. The PLL provides a significant amount of

flexibility in selecting the device operating speed. A

block diagram of the PLL is shown in Figure 8-2.

1. XT (Crystal): Crystals and ceramic resonators in

the range of 3 MHz to 10 MHz. The crystal is

connected to the OSC1 and OSC2 pins.

2. HS (High-Speed Crystal): Crystals in the range

of 10 MHz to 40 MHz. The crystal is connected

to the OSC1 and OSC2 pins.

The output of the primary oscillator or FRC, denoted as

‘FIN’, is divided down by a prescale factor (N1) of 2, 3,

... or 33 before being provided to the PLL’s Voltage

Controlled Oscillator (VCO). The input to the VCO must

be selected to be in the range of 0.8 MHz to 8 MHz.

Since the minimum prescale factor is 2, this implies that

FIN must be chosen to be in the range of 1.6 MHz to 16

MHz. The prescale factor ‘N1’ is selected using the

PLLPRE<4:0> bits (CLKDIV<4:0>).

3. EC (External Clock): External clock signal in the

range of 0.8 MHz to 64 MHz. The external clock

signal is directly applied to the OSC1 pin.

The secondary (LP) oscillator is designed for low power

and uses a 32.768 kHz crystal or ceramic resonator.

The LP oscillator uses the SOSCI and SOSCO pins.

The LPRC (Low-Power RC) internal oscIllator runs at a

nominal frequency of 32.768 kHz. It is also used as a

reference clock by the Watchdog Timer (WDT) and

Fail-Safe Clock Monitor (FSCM).

The PLL Feedback Divisor, selected using the

PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M’,

by which the input to the VCO is multiplied. This factor

must be selected such that the resulting VCO output

frequency is in the range of 100 MHz to 200 MHz.

The clock signals generated by the FRC and primary

oscillators can be optionally applied to an on-chip

Phase Locked Loop (PLL) to provide a wide range of

output frequencies for device operation. PLL

configuration is described in Section 8.1.3 “PLL

Configuration”.

The VCO output is further divided by a postscale factor

‘N2’. This factor is selected using the PLLPOST<1:0>

bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and

must be selected such that the PLL output frequency

(FOSC) is in the range of 12.5 MHz to 80 MHz, which

generates device operating speeds of 6.25-40 MIPS.

8.1.2

SYSTEM CLOCK SELECTION

For a primary oscillator or FRC oscillator, output ‘FIN’,

the PLL output ‘FOSC’ is given by:

The oscillator source that is used at a device Power-on

Reset event is selected using Configuration bit settings.

The oscillator Configuration bit settings are located in the

Configuration registers in the program memory. (Refer to

Section 20.1 “Configuration Bits” for further details.)

The Initial Oscillator Selection Configuration bits,

FNOSC<2:0> (FOSCSEL<2:0>), and the Primary Oscil-

lator Mode Select Configuration bits, POSCMD<1:0>

EQUATION 8-2:

FOSC CALCULATION

M

N1*N2

FOSC = FIN*

(

)

DS70175D-page 128

Preliminary

PIC24H

For example, suppose a 10 MHz crystal is being used,

with “XT with PLL” being the selected oscillator mode.

If PLLPRE<4:0> = 0, then N1 = 2. This yields a VCO

input of 10/2 = 5 MHz, which is within the acceptable

range of 0.8-8 MHz. If PLLDIV<8:0> = 0x1E, then

M = 32. This yields a VCO output of 5 x 32 = 160 MHz,

which is within the 100-200 MHz ranged needed.

EQUATION 8-3:

XT WITH PLL MODE

EXAMPLE

FOSC

2

1

10000000*32

FCY =

=

(

)

= 40 MIPS

2

2*2

If PLLPOST<1:0> = 0, then N2 = 2. This provides a

Fosc of 160/2 = 80 MHz. The resultant device operating

speed is 80/2 = 40 MIPS.

FIGURE 8-2:

PIC24H PLL BLOCK DIAGRAM

0.8-8.0 MHz

Here

100-200 MHz

Here

12.5-80 MHz

Here

Source (Crystal, External

Clock or Internal RC)

FOSC

PLLPRE

VCO

PLLPOST

X

PLLDIV

1.6-16.0 MHz

Here

Divide by

2-33

Divide by

2, 4, 8

Divide by

2-513

TABLE 8-1:

CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator Mode

Oscillator Source

POSCMD<1:0>

FNOSC<2:0>

Note

1, 2

Fast RC Oscillator with Divide-by-N

(FRCDIVN)

Internal

11

111

Internal

11

110

1

Fast RC Oscillator with Divide-by-16

(FRCDIV16)

Low-Power RC Oscillator (LPRC)

Internal

Secondary

Primary

11

10

101

100

011

1

Secondary (Timer1) Oscillator (SOSC)

Primary Oscillator (HS) with PLL

(HSPLL)

Primary Oscillator (XT) with PLL

(XTPLL)

Primary

01

00

011

Primary Oscillator (EC) with PLL

(ECPLL)

1

Primary Oscillator (HS)

Primary

Internal

10

01

00

11

010

001

000

Primary Oscillator (XT)

Primary Oscillator (EC)

1

Fast RC Oscillator with PLL (FRCPLL)

Fast RC Oscillator (FRC)

Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.

2: This is the default oscillator mode for an unprogrammed (erased) device.

Preliminary

DS70175D-page 129

PIC24H

REGISTER 8-1:

OSCCON: OSCILLATOR CONTROL REGISTER

U-0

—

R-0

U-0

—

R/W-y

bit 8

COSC<2:0>

NOSC<2:0>

bit 15

R/W-0

CLKLOCK

bit 7

U-0

—

R-0

U-0

—

R/C-0

CF

U-0

—

R/W-0

LOCK

LPOSCEN

OSWEN

bit 0

Legend:

y = Value set from Configuration bits on POR

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

COSC<2:0>: Current Oscillator Selection bits (read-only)

000= Fast RC oscillator (FRC)

001= Fast RC oscillator (FRC) with PLL

010= Primary oscillator (XT, HS, EC)

011= Primary oscillator (XT, HS, EC) with PLL

100= Secondary oscillator (SOSC)

101= Low-Power RC oscillator (LPRC)

110= Fast RC oscillator (FRC) with Divide-by-16

111= Fast RC oscillator (FRC) with Divide-by-n

bit 11

Unimplemented: Read as ‘0’

bit 10-8

NOSC<2:0>: New Oscillator Selection bits

000= Fast RC oscillator (FRC)

001= Fast RC oscillator (FRC) with PLL

010= Primary oscillator (XT, HS, EC)

011= Primary oscillator (XT, HS, EC) with PLL

100= Secondary oscillator (SOSC)

101= Low-Power RC oscillator (LPRC)

110= Fast RC oscillator (FRC) with Divide-by-16

111= Fast RC oscillator (FRC) with Divide-by-n

bit 7

CLKLOCK: Clock Lock Enable bit

1= If (FCKSM1 = 1), then clock and PLL configurations are locked.

If (FCKSM1 = 0), then clock and PLL configurations may be modified.

0= Clock and PLL selections are not locked, configurations may be modified

bit 6

bit 5

Unimplemented: Read as ‘0’

LOCK: PLL Lock Status bit (read-only)

1= Indicates that PLL is in lock, or PLL start-up timer is satisfied

0= Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled

bit 4

bit 3

Unimplemented: Read as ‘0’

CF: Clock Fail Detect bit (read/clear by application)

1= FSCM has detected clock failure

0= FSCM has not detected clock failure

bit 2

bit 1

Unimplemented: Read as ‘0’

LPOSCEN: Secondary (LP) Oscillator Enable bit

1= Enable secondary oscillator

0= Disable secondary oscillator

bit 0

OSWEN: Oscillator Switch Enable bit

1= Request oscillator switch to selection specified by NOSC<2:0> bits

0= Oscillator switch is complete

DS70175D-page 130

Preliminary

PIC24H

REGISTER 8-2:

CLKDIV: CLOCK DIVISOR REGISTER

R/W-0

ROI

R/W-0

DOZEN⁽¹⁾

R/W-1

R/W-0

DOZE<2:0>

FRCDIV<2:0>

bit 15

bit 8

R/W-0

bit 0

R/W-0

R/W-1

U-0

—

R/W-0

PLLPOST<1:0>

PLLPRE<4:0>

bit 7

Legend:

y = Value set from Configuration bits on POR

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

ROI: Recover on Interrupt bit

1= Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1

0= Interrupts have no effect on the DOZEN bit

bit 14-12

DOZE<2:0>: Processor Clock Reduction Select bits

000= FCY/1 (default)

001= FCY/2

010= FCY/4

011= FCY/8

100= FCY/16

101= FCY/32

110= FCY/64

111= FCY/128

bit 11

DOZEN: DOZE Mode Enable bit⁽¹⁾

1= DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks

0= Processor clock/peripheral clock ratio forced to 1:1

bit 10-8

FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits

000= FRC divide by 1

001= FRC divide by 2

010= FRC divide by 4

011= FRC divide by 8 (default)

100= FRC divide by 16

101= FRC divide by 32

110= FRC divide by 64

111= FRC divide by 256

bit 7-6

PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)

00= Output/2

01= Output/4

10= Reserved (defaults to output/4)

11= Output/8

bit 5

Unimplemented: Read as ‘0’

bit 4-0

PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler)

00000= Input/2

00001= Input/3

• • •

11111= Input/33

Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.

Preliminary

DS70175D-page 131

PIC24H

REGISTER 8-3:

PLLFBD: PLL FEEDBACK DIVISOR REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

PLLDIV<8>

bit 8

bit 15

R/W-0

bit 7

R/W-0

R/W-1

R/W-0

bit 0

PLLDIV<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-9

bit 8-0

Unimplemented: Read as ‘0’

PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)

000000000= 2

000000001= 3

000000010= 4

•

111111111= 513

DS70175D-page 132

Preliminary

PIC24H

REGISTER 8-4:

OSCTUN: FRC OSCILLATOR TUNING REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

R/W-0

TUN5

R/W-0

TUN4

R/W-0

TUN3

R/W-0

TUN2

R/W-0

TUN1

R/W-0

TUN0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-6

bit 5-0

Unimplemented: Read as ‘0’

TUN<5:0>: FRC Oscillator Tuning bits

011111= Center frequency + 11.625% (8.23 MHz)

011110= Center frequency + 11.25% (8.20 MHz)

•

000001= Center frequency + 0.375% (7.40 MHz)

000000= Center frequency (7.37 MHz nominal)

111111= Center frequency – 0.375% (7.345 MHz)

•

100001= Center frequency – 11.625% (6.52 MHz)

100000= Center frequency – 12% (6.49 MHz)

Preliminary

DS70175D-page 133

PIC24H

Once the basic sequence is completed, the system

clock hardware responds automatically as follows:

8.2

Clock Switching Operation

Applications are free to switch between any of the four

clock sources (Primary, LP, FRC and LPRC) under

software control at any time. To limit the possible side

effects that could result from this flexibility, PIC24H

devices have a safeguard lock built into the switch

process.

1. The clock switching hardware compares the

COSC status bits with the new value of the

NOSC control bits. If they are the same, then the

clock switch is a redundant operation. In this

case, the OSWEN bit is cleared automatically

and the clock switch is aborted.

Note:

Primary Oscillator mode has three different

submodes (XT, HS and EC) which are

determined by the POSCMD<1:0> Config-

uration bits. While an application can

switch to and from Primary Oscillator

mode in software, it cannot switch

between the different primary submodes

without reprogramming the device.

2. If a valid clock switch has been initiated, the

LOCK

(OSCCON<5>)

and

the

CF

(OSCCON<3>) status bits are cleared.

3. The new oscillator is turned on by the hardware

if it is not currently running. If a crystal oscillator

must be turned on, the hardware waits until the

Oscillator Start-up Timer (OST) expires. If the

new source is using the PLL, the hardware waits

until a PLL lock is detected (LOCK = 1).

8.2.1

ENABLING CLOCK SWITCHING

4. The hardware waits for 10 clock cycles from the

new clock source and then performs the clock

switch.

To enable clock switching, the FCKSM1 Configuration

bit in the Configuration register must be programmed to

‘0’. (Refer to Section 20.1 “Configuration Bits” for

further details.) If the FCKSM1 Configuration bit is

unprogrammed (‘1’), the clock switching function and

Fail-Safe Clock Monitor function are disabled. This is

the default setting.

5. The hardware clears the OSWEN bit to indicate a

successful clock transition. In addition, the NOSC

bit values are transferred to the COSC status bits.

6. The old clock source is turned off at this time,

with the exception of LPRC (if WDT or FSCM

are enabled) or LP (if LPOSCEN remains set).

The NOSC control bits (OSCCON<10:8>) do not

control the clock selection when clock switching is

disabled. However, the COSC bits (OSCCON<14:12>)

reflect the clock source selected by the FNOSC

Configuration bits.

Note 1: The processor continues to execute code

throughout the clock switching sequence.

Timing sensitive code should not be

executed during this time.

The OSWEN control bit (OSCCON<0>) has no effect

when clock switching is disabled. It is held at ‘0’ at all

times.

2: Direct clock switches between any primary

oscillator mode with PLL and FRCPLL

mode are not permitted. This applies to

clock switches in either direction. In these

instances, the application must switch to

FRC mode as a transition clock source

between the two PLL modes.

8.2.2

OSCILLATOR SWITCHING

SEQUENCE

At a minimum, performing a clock switch requires this

basic sequence:

1. If

desired,

read

the

COSC

bits

8.3

Fail-Safe Clock Monitor (FSCM)

(OSCCON<14:12>) to determine the current

oscillator source.

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue to operate even in the event of an oscillator

failure. The FSCM function is enabled by programming.

If the FSCM function is enabled, the LPRC internal

oscillator runs at all times (except during Sleep mode)

and is not subject to control by the Watchdog Timer.

2. Perform the unlock sequence to allow a write to

the OSCCON register high byte.

3. Write the appropriate value to the NOSC control

bits (OSCCON<10:8>) for the new oscillator

source.

If an oscillator failure occurs, the FSCM generates a

clock failure trap event and switches the system clock

over to the FRC oscillator. Then the application

program can either attempt to restart the oscillator or

execute a controlled shutdown. The trap can be treated

as a warm Reset by simply loading the Reset address

into the oscillator fail trap vector.

4. Perform the unlock sequence to allow a write to

the OSCCON register low byte.

5. Set the OSWEN bit to initiate the oscillator

switch.

If the PLL multiplier is used to scale the system clock,

the internal FRC is also multiplied by the same factor

on clock failure. Essentially, the device switches to

FRC with PLL on a clock failure.

DS70175D-page 134

Preliminary

PIC24H

and halts all code execution. Idle mode halts the CPU

and code execution, but allows peripheral modules to

continue operation. The assembly syntax of the

PWRSAVinstruction is shown in Example 9-1.

9.0

POWER-SAVING FEATURES

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Note: SLEEP_MODE and IDLE_MODE are

constants defined in the assembler

include file for the selected device.

Sleep and Idle modes can be exited as a result of an

enabled interrupt, WDT time-out or a device Reset. When

the device exits these modes, it is said to “wake-up”.

The PIC24H devices provide the ability to manage

power consumption by selectively managing clocking

to the CPU and the peripherals. In general, a lower

clock frequency and a reduction in the number of cir-

cuits being clocked constitutes lower consumed power.

PIC24H devices can manage power consumption in

four different ways:

9.2.1

SLEEP MODE

Sleep mode has these features:

• The system clock source is shut down. If an

on-chip oscillator is used, it is turned off.

• Clock frequency

• The device current consumption is reduced to a

minimum, provided that no I/O pin is sourcing

current.

• Instruction-based Sleep and Idle modes

• Software-controlled Doze mode

• Selective peripheral control in software

• The Fail-Safe Clock Monitor does not operate

during Sleep mode since the system clock source

is disabled.

Combinations of these methods can be used to selec-

tively tailor an application’s power consumption while

still maintaining critical application features, such as

timing-sensitive communications.

• The LPRC clock continues to run in Sleep mode if

the WDT is enabled.

• The WDT, if enabled, is automatically cleared

prior to entering Sleep mode.

9.1

Clock Frequency and Clock

Switching

• Some device features or peripherals may continue

to operate in Sleep mode. This includes items such

as the input change notification on the I/O ports, or

peripherals that use an external clock input. Any

peripheral that requires the system clock source for

its operation is disabled in Sleep mode.

PIC24H devices allow a wide range of clock frequen-

cies to be selected under application control. If the

system clock configuration is not locked, users can

choose low-power or high-precision oscillators by

simply changing the NOSC bits (OSCCON<10:8>).

The process of changing a system clock during

operation, as well as limitations to the process, are

discussed in more detail in Section 8.0 “Oscillator

Configuration”.

The device will wake-up from Sleep mode on any of the

these events:

• Any interrupt source that is individually enabled.

• Any form of device Reset.

• A WDT time-out.

9.2

Instruction-Based Power-Saving

Modes

On wake-up from Sleep, the processor restarts with the

same clock source that was active when Sleep mode

was entered.

PIC24H devices have two special power-saving modes

that are entered through the execution of a special

PWRSAVinstruction. Sleep mode stops clock operation

EXAMPLE 9-1:

PWRSAVINSTRUCTION SYNTAX

PWRSAV #SLEEP_MODE

PWRSAV #IDLE_MODE

; Put the device into SLEEP mode

; Put the device into IDLE mode

Preliminary

DS70175D-page 135

PIC24H

Doze mode is enabled by setting the DOZEN bit

(CLKDIV<11>). The ratio between peripheral and core

clock speed is determined by the DOZE<2:0> bits

(CLKDIV<14:12>). There are eight possible

configurations, from 1:1 to 1:128, with 1:1 being the

default setting.

9.2.2

IDLE MODE

Idle mode has these features:

• The CPU stops executing instructions.

• The WDT is automatically cleared.

• The system clock source remains active. By

default, all peripheral modules continue to operate

normally from the system clock source, but can

also be selectively disabled (see Section 9.4

“Peripheral Module Disable”).

It is also possible to use Doze mode to selectively

reduce power consumption in event-driven applica-

tions. This allows clock-sensitive functions, such as

synchronous communications, to continue without

interruption while the CPU idles, waiting for something

to invoke an interrupt routine. Enabling the automatic

return to full-speed CPU operation on interrupts is

enabled by setting the ROI bit (CLKDIV<15>). By

default, interrupt events have no effect on Doze mode

operation.

• If the WDT or FSCM is enabled, the LPRC also

remains active.

The device will wake from Idle mode on any of these

events:

• Any interrupt that is individually enabled.

• Any device Reset.

For example, suppose the device is operating at

20 MIPS and the CAN module has been configured for

500 kbps based on this device operating speed. If the

device is now placed in Doze mode with a clock

frequency ratio of 1:4, the CAN module continues to

communicate at the required bit rate of 500 kbps, but

the CPU now starts executing instructions at a

frequency of 5 MIPS.

• A WDT time-out.

On wake-up from Idle, the clock is reapplied to the CPU

and instruction execution begins immediately, starting

with the instruction following the PWRSAVinstruction, or

the first instruction in the ISR.

9.2.3

INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS

9.4

Peripheral Module Disable

Any interrupt that coincides with the execution of a

PWRSAVinstruction is held off until entry into Sleep or

Idle mode has completed. The device then wakes up

from Sleep or Idle mode.

The Peripheral Module Disable (PMD) registers

provide a method to disable a peripheral module by

stopping all clock sources supplied to that module.

When a peripheral is disabled via the appropriate PMD

control bit, the peripheral is in a minimum power

consumption state. The control and status registers

associated with the peripheral are also disabled, so

writes to those registers will have no effect and read

values will be invalid.

9.3

Doze Mode

Generally, changing clock speed and invoking one of the

power-saving modes are the preferred strategies for

reducing power consumption. There may be cir-

cumstances, however, where this is not practical. For

example, it may be necessary for an application to main-

tain uninterrupted synchronous communication, even

while it is doing nothing else. Reducing system clock

speed may introduce communication errors, while using

a power-saving mode may stop communications

completely.

A peripheral module is only enabled if both the associ-

ated bit in the PMD register is cleared and the peripheral

is supported by the specific dsPIC^®DSC variant. If the

peripheral is present in the device, it is enabled in the

PMD register by default.

Note:

If a PMD bit is set, the corresponding mod-

ule is disabled after a delay of 1 instruction

cycle. Similarly, if a PMD bit is cleared, the

corresponding module is enabled after a

delay of 1 instruction cycle (assuming the

module control registers are already

configured to enable module operation).

Doze mode is a simple and effective alternative method

to reduce power consumption while the device is still

executing code. In this mode, the system clock contin-

ues to operate from the same source and at the same

speed. Peripheral modules continue to be clocked at

the same speed, while the CPU clock speed is

reduced. Synchronization between the two clock

domains is maintained, allowing the peripherals to

access the SFRs while the CPU executes code at a

slower rate.

DS70175D-page 136

Preliminary

PIC24H

When a peripheral is enabled and actively driving an

associated pin, the use of the pin as a general purpose

output pin is disabled. The I/O pin may be read, but the

output driver for the parallel port bit will be disabled. If

a peripheral is enabled, but the peripheral is not

actively driving a pin, that pin may be driven by a port.

10.0 I/O PORTS

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

All port pins have three registers directly associated

with their operation as digital I/O. The data direction

register (TRISx) determines whether the pin is an input

or an output. If the data direction bit is a ‘1’, then the pin

is an input. All port pins are defined as inputs after a

Reset. Reads from the latch (LATx), read the latch.

Writes to the latch, write the latch. Reads from the port

(PORTx), read the port pins, while writes to the port

pins, write the latch.

All of the device pins (except VDD, VSS, MCLR and

OSC1/CLKIN) are shared between the peripherals and

the parallel I/O ports. All I/O input ports feature Schmitt

Trigger inputs for improved noise immunity.

10.1 Parallel I/O (PIO) Ports

A parallel I/O port that shares a pin with a peripheral is,

in general, subservient to the peripheral. The periph-

eral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pin. The logic also prevents “loop through”, in

which a port’s digital output can drive the input of a

peripheral that shares the same pin. Figure 10-1 shows

how ports are shared with other peripherals and the

associated I/O pin to which they are connected.

Any bit and its associated data and control registers

that are not valid for a particular device will be

disabled. That means the corresponding LATx and

TRISx registers and the port pins will read as zeros.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is nevertheless

regarded as a dedicated port because there is no

other competing source of outputs. An example is the

INT4 pin.

Note:

The voltage on a digital input pin can be

between -0.3V to 5.6V.

FIGURE 10-1:

BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Peripheral Module

Output Multiplexers

Peripheral Input Data

Peripheral Module Enable

I/O

Peripheral Output Enable

Peripheral Output Data

1

Output Enable

0

1

0

PIO Module

Output Data

Read TRIS

Data Bus

WR TRIS

D

Q

I/O Pin

CK

TRIS Latch

D

Q

WR LAT +

WR PORT

CK

Data Latch

Read LAT

Read Port

Input Data

Preliminary

DS70175D-page 137

PIC24H

10.2 Open-Drain Configuration

10.4 I/O Port Write/Read Timing

In addition to the PORT, LAT and TRIS registers for

data control, each port pin can also be individually

configured for either digital or open-drain output. This is

controlled by the Open-Drain Control register, ODCx,

associated with each port. Setting any of the bits con-

figures the corresponding pin to act as an open-drain

output.

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically, this instruction

would be a NOP.

10.5 Input Change Notification

The input change notification function of the I/O ports

allows the PIC24H devices to generate interrupt

The open-drain feature allows the generation of

outputs higher than VDD (e.g., 5V) on any desired digi-

tal only pins by using external pull-up resistors. (The

open-drain I/O feature is not supported on pins that

have analog functionality multiplexed on the pin.) The

maximum open-drain voltage allowed is the same as

the maximum VIH specification. The open-drain output

feature is supported for both port pin and peripheral

configurations.

requests to the processor in response to

a

change-of-state on selected input pins. This feature is

capable of detecting input change-of-states even in

Sleep mode, when the clocks are disabled. Depending

on the device pin count, there are up to 24 external sig-

nals (CN0 through CN23) that can be selected

(enabled) for generating an interrupt request on a

change-of-state.

There are four control registers associated with the CN

module. The CNEN1 and CNEN2 registers contain the

CN interrupt enable (CNxIE) control bits for each of the

CN input pins. Setting any of these bits enables a CN

interrupt for the corresponding pins.

10.3 Configuring Analog Port Pins

The use of the ADxPCFGH, ADxPCFGL and TRIS

registers control the operation of the A/D port pins. The

port pins that are desired as analog inputs must have

their corresponding TRIS bit set (input). If the TRIS bit

is cleared (output), the digital output level (VOH or VOL)

is converted.

Each CN pin also has a weak pull-up connected to it.

The pull-ups act as a current source that is connected

to the pin and eliminate the need for external resistors

when push button or keypad devices are connected.

The pull-ups are enabled separately using the CNPU1

and CNPU2 registers, which contain the weak pull-up

enable (CNxPUE) bits for each of the CN pins. Setting

any of the control bits enables the weak pull-ups for the

corresponding pins.

Clearing any bit in the ADxPCFGH or ADxPCFGL reg-

ister configures the corresponding bit to be an analog

pin. This is also the Reset state of any I/O pin that has

an analog (ANx) function associated with it.

Note:

In devices with two A/D modules, if the

corresponding PCFG bit in either

AD1PCFGH(L) and AD2PCFGH(L) is

cleared, the pin is configured as an analog

input.

Note:

Pull-ups on change notification pins

should always be disabled whenever the

port pin is configured as a digital output.

When reading the PORT register, all pins configured as

analog input channels will read as cleared (a low level).

Pins configured as digital inputs will not convert an

analog input. Analog levels on any pin that is defined as

a digital input (including the ANx pins) can cause the

input buffer to consume current that exceeds the

device specifications.

Note:

The voltage on an analog input pin can be

between -0.3V to (VDD + 0.3 V).

EXAMPLE 10-1:

PORT WRITE/READ EXAMPLE

MOV

NOP

0xFF00, W0

W0, TRISBB

; Configure PORTB<15:8> as inputs

; and PORTB<7:0> as outputs

; Delay 1 cycle

btss PORTB, #13

; Next Instruction

DS70175D-page 138

Preliminary

PIC24H

Figure 11-1 presents a block diagram of the 16-bit

timer module.

11.0 TIMER1

Note:

This data sheet summarizes the features

To configure Timer1 for operation:

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

1. Set the TON bit (= 1) in the T1CON register.

2. Select the timer prescaler ratio using the

TCKPS<1:0> bits in the T1CON register.

3. Set the Clock and Gating modes using the TCS

and TGATE bits in the T1CON register.

The Timer1 module is a 16-bit timer, which can serve

as the time counter for the real-time clock, or operate

as a free-running interval timer/counter. Timer1 can

operate in three modes:

4. Set or clear the TSYNC bit in T1CON to select

synchronous or asynchronous operation.

5. Load the timer period value into the PR1

register.

• 16-bit Timer

6. If interrupts are required, set the interrupt enable

bit, T1IE. Use the priority bits, T1IP<2:0>, to set

the interrupt priority.

• 16-bit Synchronous Counter

• 16-bit Asynchronous Counter

Timer1 also supports these features:

• Timer gate operation

• Selectable prescaler settings

• Timer operation during CPU Idle and Sleep

modes

• Interrupt on 16-bit Period register match or falling

edge of external gate signal

FIGURE 11-1:

16-BIT TIMER1 MODULE BLOCK DIAGRAM

TCKPS<1:0>

TON

2

SOSCO/

1x

01

00

T1CK

Prescaler

1, 8, 64, 256

Gate

Sync

SOSCEN

SOSCI

TCY

TGATE

TCS

TGATE

1

0

Q

D

Set T1IF

CK

0

Reset

Equal

TMR1

1

Sync

TSYNC

Comparator

PR1

Preliminary

DS70175D-page 139

PIC24H

REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0

TON

U-0

—

R/W-0

TSIDL

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

U-0

—

R/W-0

TCS

U-0

—

TGATE

TCKPS<1:0>

TSYNC

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

TON: Timer1 On bit

1= Starts 16-bit Timer1

0= Stops 16-bit Timer1

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timer1 Gated Time Accumulation Enable bit

When T1CS = 1:

This bit is ignored.

When T1CS = 0:

1= Gated time accumulation enabled

0= Gated time accumulation disabled

bit 5-4

TCKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:256

10= 1:64

01= 1:8

00 = 1:1

bit 3

bit 2

Unimplemented: Read as ‘0’

TSYNC: Timer1 External Clock Input Synchronization Select bit

When TCS = 1:

1= Synchronize external clock input

0= Do not synchronize external clock input

When TCS = 0:

This bit is ignored.

bit 1

bit 0

TCS: Timer1 Clock Source Select bit

1= External clock from pin T1CK (on the rising edge)

0= Internal clock (FCY)

Unimplemented: Read as ‘0’

DS70175D-page 140

Preliminary

PIC24H

To configure Timer2/3, Timer4/5, Timer6/7 or Timer8/9

for 32-bit operation:

12.0 TIMER2/3, TIMER4/5, TIMER6/7

AND TIMER8/9

1. Set the corresponding T32 control bit.

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

2. Select the prescaler ratio for Timer2, Timer4,

Timer6 or Timer8 using the TCKPS<1:0> bits.

3. Set the Clock and Gating modes using the

corresponding TCS and TGATE bits.

4. Load the timer period value. PR3, PR5, PR7 or

PR9 contains the most significant word of the

value, while PR2, PR4, PR6 or PR8 contains the

least significant word.

The Timer2/3, Timer4/5, Timer6/7 and Timer8/9

modules are 32-bit timers, which can also be config-

ured as four independent 16-bit timers with selectable

operating modes.

5. If interrupts are required, set the interrupt enable

bit, T3IE, T5IE, T7IE or T9IE. Use the priority

bits, T3IP<2:0>, T5IP<2:0>, T7IP<2:0> or

T9IP<2:0>, to set the interrupt priority. While

Timer2, Timer4, Timer6 or Timer8 control the

timer, the interrupt appears as a Timer3, Timer5,

Timer7 or Timer9 interrupt.

As a 32-bit timer, Timer2/3, Timer4/5, Timer6/7 and

Timer8/9 operate in three modes:

• Two Independent 16-bit Timers (e.g., Timer2 and

Timer3) with all 16-bit operating modes (except

Asynchronous Counter mode)

6. Set the corresponding TON bit.

• Single 32-bit Timer

The timer value at any point is stored in the register

pair, TMR3:TMR2, TMR5:TMR4, TMR7:TMR6 or

TMR9:TMR8. TMR3, TMR5, TMR7 or TMR9 always

contains the most significant word of the count, while

TMR2, TMR4, TMR6 or TMR8 contains the least

significant word.

• Single 32-bit Synchronous Counter

They also support these features:

• Timer Gate Operation

• Selectable Prescaler Settings

• Timer Operation during Idle and Sleep modes

• Interrupt on a 32-bit Period Register Match

To configure any of the timers for individual 16-bit

operation:

• Time Base for Input Capture and Output Compare

Modules (Timer2 and Timer3 only)

1. Clear the T32 bit corresponding to that timer.

• ADC1 Event Trigger (Timer2/3 only)

• ADC2 Event Trigger (Timer4/5 only)

2. Select the timer prescaler ratio using the

TCKPS<1:0> bits.

3. Set the Clock and Gating modes using the TCS

and TGATE bits.

Individually, all eight of the 16-bit timers can function as

synchronous timers or counters. They also offer the

features listed above, except for the event trigger; this

is implemented only with Timer2/3. The operating

modes and enabled features are determined by setting

the appropriate bit(s) in the T2CON, T3CON, T4CON,

T5CON, T6CON, T7CON, T8CON and T9CON regis-

ters. T2CON, T4CON, T6CON and T8CON are shown

in generic form in Register 12-1. T3CON, T5CON,

T7CON and T9CON are shown in Register 12-2.

4. Load the timer period value into the PRx

register.

5. If interrupts are required, set the interrupt enable

bit, TxIE. Use the priority bits, TxIP<2:0>, to set

the interrupt priority.

6. Set the TON bit.

A block diagram for a 32-bit timer pair (Timer4/5)

example is shown in Figure 12-1 and a timer (Timer4)

operating in 16-bit mode example is shown in

Figure 12-2.

For 32-bit timer/counter operation, Timer2, Timer4,

Timer6 or Timer8 is the least significant word; Timer3,

Timer5, Timer7 or Timer9 is the most significant word

of the 32-bit timers.

Note:

Only Timer2 and Timer3 can trigger a

DMA data transfer.

Note:

For 32-bit operation, T3CON, T5CON,

T7CON and T9CON control bits are

ignored. Only T2CON, T4CON, T6CON

and T8CON control bits are used for setup

and control. Timer2, Timer4, Timer6 and

Timer8 clock and gate inputs are utilized

for the 32-bit timer modules, but an inter-

rupt is generated with the Timer3, Timer5,

Ttimer7 and Timer9 interrupt flags.

Preliminary

DS70175D-page 141

PIC24H

FIGURE 12-1:

TIMER2/3 (32-BIT) BLOCK DIAGRAM⁽¹⁾

TCKPS<1:0>

2

TON

1x

01

00

T2CK

Gate

Sync

Prescaler

1, 8, 64, 256

TCY

TGATE

TCS

TGATE

1

Q

D

Set T3IF

CK

0

PR2

PR3

(2)

ADC Event Trigger

Equal

Reset

Comparator

MSB

LSB

TMR3

TMR2

Sync

16

Read TMR2

Write TMR2

16

TMR3HLD

16

Data Bus<15:0>

Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective

to the T2CON register.

2: The ADC event trigger is available only on Timer2/3.

DS70175D-page 142

Preliminary

PIC24H

FIGURE 12-2:

TIMER2 (16-BIT) BLOCK DIAGRAM

TCKPS<1:0>

TON

2

T2CK

1x

01

00

Prescaler

1, 8, 64, 256

Gate

Sync

TGATE

TCS

TGATE

TCY

1

0

Q

D

Set T2IF

CK

Reset

Equal

TMR2

Sync

Comparator

PR2

Preliminary

DS70175D-page 143

PIC24H

REGISTER 12-1: TxCON (T2CON, T4CON, T6CON OR T8CON) CONTROL REGISTER

R/W-0

TON

U-0

—

R/W-0

TSIDL

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

T32⁽¹⁾

U-0

—

R/W-0

TCS

U-0

—

TGATE

TCKPS<1:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

TON: Timerx On bit

When T32 = 1:

1= Starts 32-bit Timerx/y

0= Stops 32-bit Timerx/y

When T32 = 0:

1= Starts 16-bit Timerx

0= Stops 16-bit Timerx

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timerx Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation enabled

0= Gated time accumulation disabled

bit 5-4

bit 3

TCKPS<1:0>: Timerx Input Clock Prescale Select bits

11= 1:256

10= 1:64

01= 1:8

00= 1:1

T32: 32-bit Timer Mode Select bit⁽¹⁾

1= Timerx and Timery form a single 32-bit timer

0= Timerx and Timery act as two 16-bit timers

bit 2

bit 1

Unimplemented: Read as ‘0’

TCS: Timerx Clock Source Select bit

1= External clock from pin TxCK (on the rising edge)

0= Internal clock (FCY)

bit 0

Unimplemented: Read as ‘0’

Note 1: In 32-bit mode, T3CON control bits do not affect 32-bit timer operation.

DS70175D-page 144

Preliminary

PIC24H

REGISTER 12-2: TyCON (T3CON, T5CON, T7CON OR T9CON) CONTROL REGISTER

R/W-0

TON⁽¹⁾

U-0

—

R/W-0

TSIDL⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

TGATE⁽¹⁾

R/W-0

TCKPS<1:0>⁽¹⁾

R/W-0

U-0

—

U-0

—

R/W-0

TCS⁽¹⁾

U-0

—

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

TON: Timery On bit⁽¹⁾

1= Starts 16-bit Timery

0= Stops 16-bit Timery

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Stop in Idle Mode bit⁽¹⁾

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timery Gated Time Accumulation Enable bit⁽¹⁾

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation enabled

0= Gated time accumulation disabled

bit 5-4

TCKPS<1:0>: Timer3 Input Clock Prescale Select bits⁽¹⁾

11= 1:256

10= 1:64

01= 1:8

00= 1:1

bit 3-2

bit 1

Unimplemented: Read as ‘0’

TCS: Timery Clock Source Select bit⁽¹⁾

1= External clock from pin TyCK (on the rising edge)

0= Internal clock (FCY)

bit 0

Unimplemented: Read as ‘0’

Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timery operation; all timer

functions are set through T2CON.

Preliminary

DS70175D-page 145

PIC24H

NOTES:

DS70175D-page 146

Preliminary

PIC24H

Each input capture channel can select between one of

two 16-bit timers (Timer2 or Timer3) for the time base.

The selected timer can use either an internal or

external clock.

13.0 INPUT CAPTURE

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Other operational features include:

• Device wake-up from capture pin during CPU

Sleep and Idle modes

• Interrupt on input capture event

The input capture module is useful in applications

requiring frequency (period) and pulse measurement.

The PIC24H devices support up to eight input capture

channels.

• 4-word FIFO buffer for capture values

- Interrupt optionally generated after 1, 2, 3 or

4 buffer locations are filled

• Input capture can also be used to provide

additional sources of external interrupts

The input capture module captures the 16-bit value of

the selected Time Base register when an event occurs

at the ICx pin. The events that cause a capture event

are listed below in three categories:

Note:

Only IC1 and IC2 can trigger a DMA data

transfer. If DMA data transfers are

required, the FIFO buffer size must be set

to 1 (ICI<1:0> = 00).

1. Simple Capture Event modes

-Capture timer value on every falling edge of

input at ICx pin

-Capture timer value on every rising edge of

input at ICx pin

2. Capture timer value on every edge (rising and

falling)

3. Prescaler Capture Event modes

-Capture timer value on every 4th rising edge

of input at ICx pin

-Capture timer value on every 16th rising

edge of input at ICx pin

FIGURE 13-1:

INPUT CAPTURE BLOCK DIAGRAM

From 16-bit Timers

TMRy TMRz

16

ICTMR

(ICxCON<7>)

1

0

Edge Detection Logic

and

Clock Synchronizer

FIFO

R/W

Logic

Prescaler

Counter

(1, 4, 16)

ICx Pin

ICM<2:0> (ICxCON<2:0>)

3

Mode Select

ICOV, ICBNE (ICxCON<4:3>)

ICxBUF

ICxI<1:0>

Interrupt

Logic

ICxCON

System Bus

Set Flag ICxIF

(in IFSn Register)

Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.

Preliminary

DS70175D-page 147

PIC24H

13.1 Input Capture Registers

REGISTER 13-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

ICSIDL

bit 15

bit 8

R/W-0

bit 0

R/W-0

ICTMR⁽¹⁾

R/W-0

R-0, HC

ICOV

R-0, HC

ICBNE

R/W-0

ICI<1:0>

ICM<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

ICSIDL: Input Capture Module Stop in Idle Control bit

1= Input capture module will halt in CPU Idle mode

0= Input capture module will continue to operate in CPU Idle mode

bit 12-8

bit 7

Unimplemented: Read as ‘0’

ICTMR: Input Capture Timer Select bits⁽¹⁾

1= TMR2 contents are captured on capture event

0= TMR3 contents are captured on capture event

bit 6-5

ICI<1:0>: Select Number of Captures per Interrupt bits

11= Interrupt on every fourth capture event

10= Interrupt on every third capture event

01= Interrupt on every second capture event

00= Interrupt on every capture event

bit 4

ICOV: Input Capture Overflow Status Flag bit (read-only)

1= Input capture overflow occurred

0= No input capture overflow occurred

bit 3

ICBNE: Input Capture Buffer Empty Status bit (read-only)

1= Input capture buffer is not empty, at least one more capture value can be read

0= Input capture buffer is empty

bit 2-0

ICM<2:0>: Input Capture Mode Select bits

111=Input capture functions as interrupt pin only when device is in Sleep or Idle mode

(Rising edge detect only, all other control bits are not applicable.)

110=Unused (module disabled)

101=Capture mode, every 16th rising edge

100=Capture mode, every 4th rising edge

011=Capture mode, every rising edge

010=Capture mode, every falling edge

001=Capture mode, every edge (rising and falling)

(ICI<1:0> bits do not control interrupt generation for this mode.)

000=Input capture module turned off

Note 1: Timer selections may vary. Refer to the device data sheet for details.

DS70175D-page 148

Preliminary

PIC24H

The output compare module does not have to be dis-

abled after the falling edge of the output pulse. Another

pulse can be initiated by rewriting the value of the

OCxCON register.

14.0 OUTPUT COMPARE

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

14.2 Setup for Continuous Output

Pulse Generation

When the OCM control bits (OCxCON<2:0>) are set to

‘101’, the selected output compare channel initializes

the OCx pin to the low state and generates output

pulses on each and every compare match event.

14.1 Setup for Single Output Pulse

Generation

When the OCM control bits (OCxCON<2:0>) are set to

‘100’, the selected output compare channel initializes

the OCx pin to the low state and generates a single

output pulse.

For the user to configure the module for the generation

of a continuous stream of output pulses, the following

steps are required (these steps assume timer source is

initially turned off but this is not a requirement for the

module operation):

To generate a single output pulse, the following steps

are required (these steps assume timer source is

initially turned off but this is not a requirement for the

module operation):

1. Determine the instruction clock cycle time. Take

into account the frequency of the external clock

to the timer source (if one is used) and the timer

prescaler settings.

1. Determine the instruction clock cycle time. Take

into account the frequency of the external clock

to the timer source (if one is used) and the timer

prescaler settings.

2. Calculate time to the rising edge of the output

pulse relative to the TMRy start value (0000h).

2. Calculate time to the rising edge of the output

pulse relative to the TMRy start value (0000h).

3. Calculate the time to the falling edge of the pulse

based on the desired pulse width and the time to

the rising edge of the pulse.

4. Write the values computed in steps 2 and 3 above

into the Output Compare register, OCxR, and the

Output Compare Secondary register, OCxRS,

respectively.

5. Set Timer Period register, PRy, to value equal to

or greater than value in OCxRS, the Output

Compare Secondary register.

3. Calculate the time to the falling edge of the pulse,

based on the desired pulse width and the time to

the rising edge of the pulse.

4. Write the values computed in step 2 and 3 above

into the Output Compare register, OCxR, and the

Output Compare Secondary register, OCxRS,

respectively.

5. Set Timer Period register, PRy, to value equal to

or greater than value in OCxRS, the Output

Compare Secondary register.

6. Set the OCM bits to ‘101’ and the OCTSEL bit to

the desired timer source. The OCx pin state will

now be driven low.

6. Set the OCM bits to ‘100’ and the OCTSEL

(OCxCON<3>) bit to the desired timer source.

The OCx pin state will now be driven low.

7. Enable the compare time base by setting the TON

(TyCON<15>) bit to ‘1’.

7. Set the TON (TyCON<15>) bit to ‘1’, which

8. Upon the first match between TMRy and OCxR,

the OCx pin will be driven high.

enables the compare time base to count.

8. Upon the first match between TMRy and OCxR,

the OCx pin will be driven high.

9. When the compare time base, TMRy, matches

the Output Compare Secondary register, OCxRS,

the second and trailing edge (high-to-low) of the

pulse is driven onto the OCx pin.

9. When the incrementing timer, TMRy, matches

the Output Compare Secondary register,

OCxRS, the second and trailing edge (high-to-

low) of the pulse is driven onto the OCx pin. No

additional pulses are driven onto the OCx pin

and it remains at low. As a result of the second

compare match event, the OCxIF interrupt flag

bit is set, which will result in an interrupt if it is

enabled, by setting the OCxIE bit. For further

information on peripheral interrupts, refer to

Section 6.0 “Interrupt Controller”.

10. As a result of the second compare match event,

the OCxIF interrupt flag bit set.

11. When the compare time base and the value in its

respective Timer Period register match, the TMRy

register resets to 0x0000 and resumes counting.

12. Steps 8 through 11 are repeated and a continu-

ous stream of pulses is generated, indefinitely.

The OCxIF flag is set on each OCxRS-TMRy

compare match event.

10. To initiate another single pulse output, change the

Timer and Compare register settings, if needed,

and then issue a write to set the OCM bits to ‘100’.

Disabling and re-enabling of the timer, and clear-

ing the TMRy register, are not required but may

be advantageous for defining a pulse from a

known event time boundary.

Preliminary

DS70175D-page 149

PIC24H

EQUATION 14-1: CALCULATING THE PWM

PERIOD

14.3 Pulse-Width Modulation Mode

The following steps should be taken when configuring

the output compare module for PWM operation:

PWM Period = [(PRy) + 1] • TCY • (Timer Prescale Value)

where:

1. Set the PWM period by writing to the selected

Timer Period register (PRy).

PWM Frequency = 1/[PWM Period]

2. Set the PWM duty cycle by writing to the OCxRS

register.

Note: A PRy value of N will produce a PWM

period of N + 1 time base count cycles. For

example, a value of 7 written into the PRy

register will yield a period consisting of

eight time base cycles.

3. Write the OxCR register with the initial duty cycle.

4. Enable interrupts, if required, for the timer and

output compare modules. The output compare

interrupt is required for PWM Fault pin utilization.

5. Configure the output compare module for one of

two PWM operation modes by writing to the Out-

14.3.2

PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the OCxRS

register. The OCxRS register can be written to at any time,

but the duty cycle value is not latched into OCxR until a

match between PRy and TMRy occurs (i.e., the period is

complete). This provides a double buffer for the PWM duty

cycle and is essential for glitchless PWM operation. In the

PWM mode, OCxR is a read-only register.

put

Compare

Mode

bits,

OCM<2:0>

(OCxCON<2:0>).

6. Set the TMRy prescale value and enable the

time base by setting TON = 1(TxCON<15>).

Note: The OCxR register should be initialized

before the output compare module is first

enabled. The OCxR register becomes a

read-only duty cycle register when the

module is operated in the PWM modes.

The value held in OCxR will become the

PWM duty cycle for the first PWM period.

The contents of the Output Compare

Secondary register, OCxRS, will not be

transferred into OCxR until a time base

period match occurs.

Some important boundary parameters of the PWM duty

cycle include:

• If the Output Compare register, OCxR, is loaded

with 0000h, the OCx pin will remain low (0% duty

cycle).

• If OCxR is greater than PRy (Timer Period register),

the pin will remain high (100% duty cycle).

• If OCxR is equal to PRy, the OCx pin will be low

for one time base count value and high for all

other count values.

14.3.1

PWM PERIOD

The PWM period is specified by writing to PRy, the

Timer Period register. The PWM period can be

calculated using Equation 14-1:

See Example 14-1 for PWM mode timing details.

Table 14-1 shows example PWM frequencies and

resolutions for a device operating at 10 MIPS.

EQUATION 14-2: CALCULATION FOR MAXIMUM PWM RESOLUTION

FCY

FPWM

log₁₀

(

)

bits

Maximum PWM Resolution (bits) =

log₁₀(2)

EXAMPLE 14-1:

PWM PERIOD AND DUTY CYCLE CALCULATIONS

1. Find the Timer Period register value for a desired PWM frequency that is 52.08 kHz, where FCY = 16 MHz and a Timer2

prescaler setting of 1:1.

TCY

= 62.5 ns

PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 μs

PWM Period = (PR2 + 1) • TCY • (Timer2 Prescale Value)

19.2 μs

PR2

= (PR2 + 1) • 62.5 ns • 1

= 306

2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate:

PWM Resolution

=

log₁₀(FCY/FPWM)/log₁₀2) bits

(log₁₀(16 MHz/52.08 kHz)/log₁₀2) bits

8.3 bits

DS70175D-page 150

Preliminary

PIC24H

TABLE 14-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)

PWM Frequency

7.6 Hz

61 Hz

122 Hz

977 Hz

3.9 kHz

31.3 kHz

125 kHz

Timer Prescaler Ratio

Period Register Value

Resolution (bits)

8

1

007Fh

7

1

001Fh

5

FFFFh

16

FFFFh

16

7FFFh

15

0FFFh

12

03FFh

10

TABLE 14-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)

PWM Frequency

30.5 Hz

244 Hz

488 Hz

3.9 kHz

15.6 kHz

125 kHz

500 kHz

Timer Prescaler Ratio

Period Register Value

Resolution (bits)

8

1

007Fh

7

1

001Fh

5

FFFFh

16

FFFFh

16

7FFFh

15

0FFFh

12

03FFh

10

TABLE 14-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MIPS (FCY = 40 MHz)

PWM Frequency

76 Hz

610 Hz

1.22 Hz

9.77 kHz

39 kHz

313 kHz 1.25 MHz

Timer Prescaler Ratio

Period Register Value

Resolution (bits)

8

1

007Fh

7

1

001Fh

5

FFFFh

16

FFFFh

16

7FFFh

15

0FFFh

12

03FFh

10

FIGURE 14-1:

OUTPUT COMPARE MODULE BLOCK DIAGRAM

Set Flag bit

(1)

OCxIF

(1)

OCxRS

S

R

Q

Output

Logic

(1)

OCxR

OCx

Output Enable

3

OCM2:OCM0

Mode Select

(2)

OCFA or OCFB

Comparator

0

OCTSEL

1

0

1

16

TMR register inputs

from time bases

Period match signals

from time bases

(3)

Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels

1 through 8.

2: OCFA pin controls OC1-OC4 channels. OCFB pin controls OC5-OC8 channels.

3: Each output compare channel can use one of two selectable time bases. Refer to the device data sheet for the

time bases associated with the module.

Note:

Only OC1 and OC2 can trigger a DMA data transfer.

Preliminary

DS70175D-page 151

PIC24H

14.4 Output Compare Register

REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

OCSIDL

bit 15

bit 8

R/W-0

bit 0

U-0

—

U-0

—

U-0

—

R-0 HC

OCFLT

R/W-0

OCTSEL⁽¹⁾

R/W-0

OCM<2:0>

bit 7

Legend:

HC = Cleared in Hardware

W = Writable bit

HS = Set in Hardware

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

‘1’ = Bit is set

bit 15-14

bit 13

Unimplemented: Read as ‘0’

OCSIDL: Stop Output Compare in Idle Mode Control bit

1= Output Compare x will halt in CPU Idle mode

0= Output Compare x will continue to operate in CPU Idle mode

bit 12-5

bit 4

Unimplemented: Read as ‘0’

OCFLT: PWM Fault Condition Status bit

1= PWM Fault condition has occurred (cleared in HW only)

0= No PWM Fault condition has occurred

(This bit is only used when OCM<2:0> = 111.)

bit 3

OCTSEL: Output Compare Timer Select bit⁽¹⁾

1= Timer3 is the clock source for Compare x

0= Timer2 is the clock source for Compare x

bit 2-0

OCM<2:0>: Output Compare Mode Select bits

111= PWM mode on OCx, Fault pin enabled

110= PWM mode on OCx, Fault pin disabled

101= Initialize OCx pin low, generate continuous output pulses on OCx pin

100= Initialize OCx pin low, generate single output pulse on OCx pin

011= Compare event toggles OCx pin

010= Initialize OCx pin high, compare event forces OCx pin low

001= Initialize OCx pin low, compare event forces OCx pin high

000= Output compare channel is disabled

Note 1: Refer to the device data sheet for specific time bases available to the output compare module.

DS70175D-page 152

Preliminary

PIC24H

are moved to the receive buffer. If any transmit data

has been written to the buffer register, the contents of

the transmit buffer are moved to SPIxSR. The received

data is thus placed in SPIxBUF and the transmit data in

SPIxSR is ready for the next transfer.

15.0 SERIAL PERIPHERAL

INTERFACE (SPI)

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Note:

Both the transmit buffer (SPIxTXB) and

the receive buffer (SPIxRXB) are mapped

to the same register address, SPIxBUF.

The Serial Peripheral Interface (SPI) module is a syn-

chronous serial interface useful for communicating with

other peripheral or microcontroller devices. These

peripheral devices may be serial EEPROMs, shift regis-

ters, display drivers, A/D converters, etc. The SPI module

is compatible with SPI and SIOP from Motorola^®.

Note:

Do not perform read-modify-write opera-

tions (such as bit-oriented instructions) on

the SPIxBUF register.

The module supports a basic framed SPI protocol while

operating in either Master or Slave mode. A total of four

framed SPI configurations are supported.

Note: In this section, the SPI modules are

referred to together as SPIx, or separately

as SPI1 and SPI2. Special Function Reg-

isters will follow a similar notation. For

example, SPIxCON refers to the control

register for the SPI1 or SPI2 module.

The SPI serial interface consists of four pins:

• SDIx: Serial Data Input

• SDOx: Serial Data Output

• SCKx: Shift Clock Input or Output

• SSx: Active-Low Slave Select or Frame

Synchronization I/O Pulse

15.1 Operating Function Description

The SPI module can be configured to operate using 2,

3 or 4 pins. In the 3-pin mode, SSx is not used. In the

2-pin mode, both SDOx and SSx are not used.

Each SPI module consists of a 16-bit shift register,

SPIxSR (where x = 1 or 2), used for shifting data in and

out, and a buffer register, SPIxBUF. A control register,

SPIxCON, configures the module. Additionally, a sta-

tus register, SPIxSTAT, indicates various status condi-

tions.

A block diagram of an SPI module is shown in

Figure 15-1. All PIC24H devices contain two SPI

modules on a single device.

The SPI module contains an 8-word deep FIFO buffer;

the top of the buffer is denoted as SPIxBUF. If DMA

transfers are enabled, the FIFO buffer must be

disabled by clearing the ENHBUF bit (SPIxCON2<0>).

The serial interface consists of 4 pins: SDIx (serial data

input), SDOx (serial data output), SCKx (shift clock

input or output), and SSx (active low slave select).

In Master mode operation, SCK is a clock output but in

Slave mode, it is a clock input.

To set up the SPI module for the Master mode of

operation:

A series of eight (8) or sixteen (16) clock pulses shift

out bits from the SPIxSR to SDOx pin and simulta-

neously shift in data from SDIx pin. An interrupt is gen-

erated when the transfer is complete and the

corresponding interrupt flag bit (SPI1IF or SPI2IF) is

set. This interrupt can be disabled through an interrupt

enable bit (SPI1IE or SPI2IE).

1. If using interrupts:

a) Clear the SPIxIF bit in the respective IFSn

register.

b) Set the SPIxIE bit in the respective IECn

register.

c) Write the SPIxIP bits in the respective IPCn

register to set the interrupt priority.

The receive operation is double-buffered. When a com-

plete byte is received, it is transferred from SPIxSR to

SPIxBUF.

2. Write the desired settings to the SPIxCON

register with MSTEN (SPIxCON1<5>) = 1.

3. Clear the SPIROV bit (SPIxSTAT<6>).

If the receive buffer is full when new data is being trans-

ferred from SPIxSR to SPIxBUF, the module will set the

SPIROV bit indicating an overflow condition. The trans-

fer of the data from SPIxSR to SPIxBUF will not be

completed and the new data will be lost. The module

will not respond to SCL transitions while SPIROV is ‘1’,

effectively disabling the module until SPIxBUF is read

by user software.

4. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

5. Write the data to be transmitted to the SPIxBUF

register. Transmission (and reception) will start as

soon as data is written to the SPIxBUF register.

Transmit writes are also double-buffered. The user

writes to SPIxBUF. When the master or slave transfer

is completed, the contents of the shift register (SPIxSR)

Preliminary

DS70175D-page 153

PIC24H

To set up the SPI module for the Slave mode of operation:

5. If the CKE bit is set, then the SSEN bit

(SPIxCON1<7>) must be set to enable the SSx

pin.

1. Clear the SPIxBUF register.

2. If using interrupts:

6. Clear the SPIROV bit (SPIxSTAT<6>).

a) Clear the SPIxIF bit in the respective IFSn

register.

7. Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

b) Set the SPIxIE bit in the respective IECn

register.

The SPI module generates an interrupt indicating com-

pletion of a byte or word transfer, as well as a separate

interrupt for all SPI error conditions.

c) Write the SPIxIP bits in the respective IPCn

register to set the interrupt priority.

3. Write the desired settings to the SPIxCON1 and

Note:

Both SPI1 and SPI2 can trigger a DMA

data transfer. If SPI1 or SPI2 is selected

as the DMA IRQ source, a DMA transfer

occurs when the SPI1IF or SPI2IF bit gets

set as a result of an SPI1 or SPI2 byte or

word transfer.

SPIxCON2

registers

with

MSTEN

(SPIxCON1<5>) = 0.

4. Clear the SMP bit.

FIGURE 15-1:

SPI MODULE BLOCK DIAGRAM

SCKx

1:1 to 1:8

Secondary

Prescaler

1:1/4/16/64

Primary

Prescaler

FCY

SSx

Sync

Control

Select

Edge

Control

Clock

SPIxCON1<1:0>

SPIxCON1<4:2>

Shift Control

SDOx

SDIx

Enable

Master Clock

bit 0

SPIxSR

Transfer

SPIxRXB SPIxTXB

SPIxBUF

Write SPIxBUF

Read SPIxBUF

16

Internal Data Bus

DS70175D-page 154

Preliminary

PIC24H

FIGURE 15-2:

SPI MASTER/SLAVE CONNECTION

PROCESSOR 1 (SPI Master)

PROCESSOR 2 (SPI Slave)

SDOx

SDIx

Serial Receive Buffer

(SPIxRXB)

Serial Receive Buffer

(SPIxRXB)

SDIx

SDOx

Shift Register

(SPIxSR)

Shift Register

(SPIxSR)

LSb

MSb

LSb

Serial Transmit Buffer

(SPIxTXB)

Serial Transmit Buffer

(SPIxTXB)

Serial Clock

SCKx

SSx⁽¹⁾

SPI Buffer

(SPIxBUF)⁽²⁾

(MSTEN (SPIxCON1<5>) = 1)

(SSEN (SPIxCON1<7>) = 1and MSTEN (SPIxCON1<5>) = 0)

Note 1: Using the SSx pin in Slave mode of operation is optional.

2: User must write transmit data to/read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory

mapped to SPIxBUF.

FIGURE 15-3:

SPI MASTER, FRAME MASTER CONNECTION DIAGRAM

PIC24H

PROCESSOR 2

(SPI Slave, Frame Slave)

SDIx

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync

Pulse

FIGURE 15-4:

SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM

PIC24H

PROCESSOR 2

(SPI Master, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync

Pulse

Preliminary

DS70175D-page 155

PIC24H

FIGURE 15-5:

SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM

PIC24H

PROCESSOR 2

(SPI Slave, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync

Pulse

FIGURE 15-6:

SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM

PIC24H

PROCESSOR 2

(SPI Master, Frame Slave)

SDOx

SDIx

SDOx

Serial Clock

SCKx

SSx

SCKx

SSx

Frame Sync

Pulse

EQUATION 15-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED

FCY

FSCK =

Primary Prescaler * Secondary Prescaler

TABLE 15-1: SAMPLE SCKx FREQUENCIES

Secondary Prescaler Settings

FCY = 40 MHz

1:1

2:1

4:1

6:1

8:1

Primary Prescaler Settings

1:1

4:1

Invalid

10000

2500

625

Invalid

5000

10000

2500

6666.67

1666.67

416.67

104.17

5000

1250

16:1

64:1

1250

625

312.50

78.125

312.5

156.25

FCY = 5 MHz

Primary Prescaler Settings

1:1

4:1

5000

1250

313

78

2500

625

156

39

1250

313

78

833

208

52

625

156

39

16:1

64:1

20

13

10

Note: SCKx frequencies shown in kHz.

DS70175D-page 156

Preliminary

PIC24H

REGISTER 15-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER

R/W-0

SPIEN

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

SPISIDL

bit 15

bit 8

U-0

—

R/C-0

U-0

—

U-0

—

U-0

—

U-0

—

R-0

SPIROV

SPITBF

SPIRBF

bit 0

bit 7

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

SPIEN: SPIx Enable bit

1= Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins

0= Disables module

bit 14

bit 13

Unimplemented: Read as ‘0’

SPISIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

SPIROV: Receive Overflow Flag bit

1= A new byte/word is completely received and discarded. The user software has not read the

previous data in the SPIxBUF register.

0= No overflow has occurred

bit 5-2

bit 1

Unimplemented: Read as ‘0’

SPITBF: SPIx Transmit Buffer Full Status bit

1= Transmit not yet started, SPIxTXB is full

0= Transmit started, SPIxTXB is empty

Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB.

Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.

bit 0

SPIRBF: SPIx Receive Buffer Full Status bit

1= Receive complete, SPIxRXB is full

0= Receive is not complete, SPIxRXB is empty

Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.

Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.

Preliminary

DS70175D-page 157

PIC24H

REGISTER 15-2: SPIXCON1: SPIx CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

R/W-0

SMP

R/W-0

CKE⁽¹⁾

DISSCK

DISSDO

MODE16

bit 15

bit 8

R/W-0

SSEN

R/W-0

CKP

R/W-0

MSTEN

SPRE<2:0>

PPRE<1:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12

Unimplemented: Read as ‘0’

DISSCK: Disable SCKx pin bit (SPI Master modes only)

1= Internal SPI clock is disabled, pin functions as I/O

0= Internal SPI clock is enabled

bit 11

bit 10

bit 9

DISSDO: Disable SDOx pin bit

1= SDOx pin is not used by module; pin functions as I/O

0= SDOx pin is controlled by the module

MODE16: Word/Byte Communication Select bit

1= Communication is word-wide (16 bits)

0= Communication is byte-wide (8 bits)

SMP: SPIx Data Input Sample Phase bit

Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

Slave mode:

SMP must be cleared when SPIx is used in Slave mode.

bit 8

bit 7

bit 6

bit 5

bit 4-2

CKE: SPIx Clock Edge Select bit⁽¹⁾

1= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)

0= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)

SSEN: Slave Select Enable bit (Slave mode)

1= SSx pin used for Slave mode

0= SSx pin not used by module. Pin controlled by port function.

CKP: Clock Polarity Select bit

1= Idle state for clock is a high level; active state is a low level

0= Idle state for clock is a low level; active state is a high level

MSTEN: Master Mode Enable bit

1= Master mode

0= Slave mode

SPRE<2:0>: Secondary Prescale bits (Master mode)

111= Secondary prescale 1:1

110= Secondary prescale 2:1

...

000= Secondary prescale 8:1

bit 1-0

PPRE<1:0>: Primary Prescale bits (Master mode)

11= Primary prescale 1:1

10= Primary prescale 4:1

01= Primary prescale 16:1

00= Primary prescale 64:1

Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed

SPI modes (FRMEN = 1).

DS70175D-page 158

Preliminary

PIC24H

REGISTER 15-3: SPIxCON2: SPIx CONTROL REGISTER 2

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

FRMEN

SPIFSD

FRMPOL

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

FRMDLY

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

FRMEN: Framed SPIx Support bit

1= Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)

0= Framed SPIx support disabled

SPIFSD: Frame Sync Pulse Direction Control bit

1= Frame sync pulse input (slave)

0= Frame sync pulse output (master)

FRMPOL: Frame Sync Pulse Polarity bit

1= Frame sync pulse is active-high

0= Frame sync pulse is active-low

bit 12-2

bit 1

Unimplemented: Read as ‘0’

FRMDLY: Frame Sync Pulse Edge Select bit

1= Frame sync pulse coincides with first bit clock

0= Frame sync pulse precedes first bit clock

bit 0

Unimplemented: Read as ‘0’

This bit must not be set to ‘1’ by the user application.

Preliminary

DS70175D-page 159

PIC24H

NOTES:

DS70175D-page 160

Preliminary

PIC24H

2

16.2 I C Registers

16.0 INTER-INTEGRATED CIRCUIT

2

(I C)

I2CxCON and I2CxSTAT are control and status

registers, respectively. The I2CxCON register is

readable and writable. The lower six bits of I2CxSTAT

are read-only. The remaining bits of the I2CSTAT are

read/write.

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

I2CxRSR is the shift register used for shifting data,

whereas I2CxRCV is the buffer register to which data

bytes are written, or from which data bytes are read.

I2CxRCV is the receive buffer. I2CxTRN is the transmit

register to which bytes are written during a transmit

operation.

The Inter-Integrated Circuit (I²C) module provides

complete hardware support for both Slave and Multi-

Master modes of the I²C serial communication

standard, with a 16-bit interface.

The PIC24H devices have up to two I²C interface mod-

ules, denoted as I2C1 and I2C2. Each I²C module has

a 2-pin interface: the SCLx pin is clock and the SDAx

pin is data.

Each I²C module ‘x’ (x = 1 or 2) offers the following key

features:

• I²C interface supporting both master and slave

operation.

• I²C Slave mode supports 7 and 10-bit address.

• I²C Master mode supports 7 and 10-bit address.

• I²C port allows bidirectional transfers between

master and slaves.

• Serial clock synchronization for I²C port can be

used as a handshake mechanism to suspend and

resume serial transfer (SCLREL control).

• I²C supports multi-master operation; detects bus

collision and will arbitrate accordingly.

The I2CxADD register holds the slave address. A

status bit, ADD10, indicates 10-bit Address mode. The

I2CxBRG acts as the Baud Rate Generator (BRG)

reload value.

In receive operations, I2CxRSR and I2CxRCV together

form a double-buffered receiver. When I2CxRSR

receives a complete byte, it is transferred to I2CxRCV

and an interrupt pulse is generated.

2

16.3 I C Interrupts

The I²C module generates two interrupt flags, MI2CxIF

(I²C Master Events Interrupt Flag) and SI2CxIF (I²C

Slave Events Interrupt Flag). A separate interrupt is

generated for all I²C error conditions.

16.4 Baud Rate Generator

In I²C Master mode, the reload value for the BRG is

located in the I2CxBRG register. When the BRG is

loaded with this value, the BRG counts down to ‘0’ and

stops until another reload has taken place. If clock arbi-

tration is taking place, for instance, the BRG is reloaded

when the SCLx pin is sampled high.

As per the I²C standard, FSCL may be 100 kHz or

400 kHz. However, the user can specify any baud rate

up to 1 MHz. I2CxBRG values of ‘0’ or ‘1’ are illegal.

16.1 Operating Modes

The hardware fully implements all the master and slave

functions of the I²C Standard and Fast mode

specifications, as well as 7 and 10-bit addressing.

The I²C module can operate either as a slave or a

master on an I²C bus.

The following types of I²C operation are supported:

EQUATION 16-1: SERIAL CLOCK RATE

• I²C slave operation with 7-bit address

• I²C slave operation with 10-bit address

• I²C master operation with 7 or 10-bit address

FCY

1,111,111

– 1

–

I2CxBRG =

)

(

FSCL

For details about the communication sequence in each

of these modes, please refer to the “dsPIC30F Family

Reference Manual” (DS70046).

Preliminary

DS70175D-page 161

PIC24H

FIGURE 16-1:

I²C™ BLOCK DIAGRAM (X = 1 OR 2)

Internal

Data Bus

I2CxRCV

Read

Shift

Clock

SCLx

SDAx

I2CxRSR

LSB

Address Match

Match Detect

Write

Read

I2CxMSK

Write

Read

I2CxADD

Start and Stop

Bit Detect

Write

Start and Stop

Bit Generation

I2CxSTAT

I2CxCON

Read

Write

Collision

Detect

Acknowledge

Generation

Read

Clock

Stretching

Write

Read

I2CxTRN

LSB

Shift Clock

Reload

Control

Write

Read

BRG Down Counter

TCY/2

I2CxBRG

DS70175D-page 162

Preliminary

PIC24H

2

16.5 I C Module Addresses

16.8 General Call Address Support

The I2CxADD register contains the Slave mode

addresses. The register is a 10-bit register.

The general call address can address all devices.

When this address is used, all devices should, in

theory, respond with an Acknowledgement.

If the A10M bit (I2CxCON<10>) is ‘0’, the address is

interpreted by the module as a 7-bit address. When an

address is received, it is compared to the 7 Least

Significant bits of the I2CxADD register.

The general call address is one of eight addresses

reserved for specific purposes by the I²C protocol. It

consists of all ‘0’s with R_W = 0.

If the A10M bit is ‘1’, the address is assumed to be a

10-bit address. When an address is received, it will be

compared with the binary value, ‘11110 A9 A8’

(where A9 and A8 are two Most Significant bits of

I2CxADD). If that value matches, the next address will

be compared with the Least Significant 8 bits of

I2CxADD, as specified in the 10-bit addressing

protocol.

The general call address is recognized when the General

Call Enable (GCEN) bit is set (I2CxCON<7> = 1). When

the interrupt is serviced, the source for the interrupt can

be checked by reading the contents of the I2CxRCV to

determine if the address was device-specific or a general

call address.

16.9 Automatic Clock Stretch

TABLE 16-1: 7-BIT I²C™ SLAVE

ADDRESSES SUPPORTED BY

PIC24H

In Slave modes, the module can synchronize buffer

reads and writes to the master device by clock

stretching.

0x00

General call address or Start byte

Reserved

16.9.1

TRANSMIT CLOCK STRETCHING

0x01-0x03

0x04-0x07

0x08-0x77

0x78-0x7b

Both 10-bit and 7-bit Transmit modes implement clock

stretching by asserting the SCLREL bit after the falling

edge of the ninth clock, if the TBF bit is cleared,

indicating the buffer is empty.

Hs mode Master codes

Valid 7-bit addresses

Valid 10-bit addresses

(lower 7 bits)

In Slave Transmit modes, clock stretching is always

performed, irrespective of the STREN bit. The user’s

ISR must set the SCLREL bit before transmission is

allowed to continue. By holding the SCLx line low, the

user has time to service the ISR and load the contents

of the I2CxTRN before the master device can initiate

another transmit sequence.

0x7c-0x7f

Reserved

16.6 Slave Address Masking

The I2CxMSK register (Register 16-3) designates

address bit positions as “don’t care” for both 7-bit and

10-bit Address modes. Setting a particular bit location

(= 1) in the I2CxMSK register, causes the slave module

to respond, whether the corresponding address bit

value is a ‘0’ or ‘1’. For example, when I2CxMSK is set

to ‘00100000’, the slave module will detect both

addresses, ‘0000000’ and ‘00100000’.

16.9.2

RECEIVE CLOCK STRETCHING

The STREN bit in the I2CxCON register can be used to

enable clock stretching in Slave Receive mode. When

the STREN bit is set, the SCLx pin will be held low at

the end of each data receive sequence.

The user’s ISR must set the SCLREL bit before recep-

tion is allowed to continue. By holding the SCLx line

low, the user has time to service the ISR and read the

contents of the I2CxRCV before the master device can

initiate another receive sequence. This will prevent

buffer overruns from occurring.

To enable address masking, the Intelligent Peripheral

Management Interface (IPMI) must be disabled by

clearing the IPMIEN bit (I2CxCON<11>).

16.7 IPMI Support

The control bit, IPMIEN, enables the module to support

the Intelligent Peripheral Management Interface (IPMI).

When this bit is set, the module accepts and acts upon

all addresses.

16.10 Software Controlled Clock

Stretching (STREN = 1)

When the STREN bit is ‘1’, the SCLREL bit may be

cleared by software to allow software to control the

clock stretching.

If the STREN bit is ‘0’, a software write to the SCLREL

bit will be disregarded and have no effect on the

SCLREL bit.

Preliminary

DS70175D-page 163

PIC24H

16.11 Slope Control

16.13 Multi-Master Communication, Bus

Collision and Bus Arbitration

The I²C standard requires slope control on the SDAx

and SCLx signals for Fast mode (400 kHz). The control

bit, DISSLW, enables the user to disable slew rate con-

trol if desired. It is necessary to disable the slew rate

control for 1 MHz mode.

Multi-Master mode support is achieved by bus

arbitration. When the master outputs address/data bits

onto the SDAx pin, arbitration takes place when the

master outputs a ‘1’ on SDAx by letting SDAx float high

while another master asserts a ‘0’. When the SCLx pin

floats high, data should be stable. If the expected data

on SDAx is a ‘1’ and the data sampled on the

SDAx pin = 0, then a bus collision has taken place. The

master will set the I²C master events interrupt flag and

reset the master portion of the I²C port to its Idle state.

16.12 Clock Arbitration

Clock arbitration occurs when the master deasserts the

SCLx pin (SCLx allowed to float high) during any

receive, transmit or Restart/Stop condition. When the

SCLx pin is allowed to float high, the Baud Rate Gen-

erator (BRG) is suspended from counting until the

SCLx pin is actually sampled high. When the SCLx pin

is sampled high, the Baud Rate Generator is reloaded

with the contents of I2CxBRG and begins counting.

This ensures that the SCLx high time will always be at

least one BRG rollover count in the event that the clock

is held low by an external device.

DS70175D-page 164

Preliminary

PIC24H

REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER

R/W-0

I2CEN

U-0

—

R/W-0

R/W-1 HC

SCLREL

R/W-0

A10M

R/W-0

SMEN

I2CSIDL

IPMIEN

DISSLW

bit 15

bit 8

R/W-0

GCEN

R/W-0

R/W-0 HC

ACKEN

R/W-0 HC

RCEN

R/W-0 HC

PEN

R/W-0 HC

RSEN

R/W-0 HC

SEN

STREN

ACKDT

bit 7

bit 0

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

HS = Set in hardware

‘0’ = Bit is cleared

HC = Cleared in hardware

x = Bit is unknown

bit 15

I2CEN: I2Cx Enable bit

1= Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins

0= Disables the I2Cx module. All I²C pins are controlled by port functions.

bit 14

bit 13

Unimplemented: Read as ‘0’

I2CSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters an Idle mode

0= Continue module operation in Idle mode

bit 12

SCLREL: SCLx Release Control bit (when operating as I²C slave)

1= Release SCLx clock

0= Hold SCLx clock low (clock stretch)

If STREN = 1:

Bit is R/W (i.e., software may write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear

at beginning of slave transmission. Hardware clear at end of slave reception.

If STREN = 0:

Bit is R/S (i.e., software may only write ‘1’ to release clock). Hardware clear at beginning of slave

transmission.

bit 11

bit 10

bit 9

IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit

1= IPMI mode is enabled; all addresses Acknowledged

0= IPMI mode disabled

A10M: 10-bit Slave Address bit

1= I2CxADD is a 10-bit slave address

0= I2CxADD is a 7-bit slave address

DISSLW: Disable Slew Rate Control bit

1= Slew rate control disabled

0= Slew rate control enabled

bit 8

SMEN: SMBus Input Levels bit

1= Enable I/O pin thresholds compliant with SMBus specification

0= Disable SMBus input thresholds

bit 7

GCEN: General Call Enable bit (when operating as I²C slave)

1= Enable interrupt when a general call address is received in the I2CxRSR

(module is enabled for reception)

0= General call address disabled

bit 6

STREN: SCLx Clock Stretch Enable bit (when operating as I²C slave)

Used in conjunction with SCLREL bit.

1= Enable software or receive clock stretching

0= Disable software or receive clock stretching

Preliminary

DS70175D-page 165

PIC24H

REGISTER 16-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)

bit 5

ACKDT: Acknowledge Data bit (when operating as I²C master, applicable during master receive)

Value that will be transmitted when the software initiates an Acknowledge sequence.

1= Send NACK during Acknowledge

0= Send ACK during Acknowledge

bit 4

ACKEN: Acknowledge Sequence Enable bit

(when operating as I²C master, applicable during master receive)

1= Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.

Hardware clear at end of master Acknowledge sequence.

0= Acknowledge sequence not in progress

bit 3

bit 2

bit 1

RCEN: Receive Enable bit (when operating as I²C master)

1= Enables Receive mode for I²C. Hardware clear at end of eighth bit of master receive data byte.

0= Receive sequence not in progress

PEN: Stop Condition Enable bit (when operating as I²C master)

1= Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.

0= Stop condition not in progress

RSEN: Repeated Start Condition Enable bit (when operating as I²C master)

1= Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of

master Repeated Start sequence.

0= Repeated Start condition not in progress

bit 0

SEN: Start Condition Enable bit (when operating as I²C master)

1= Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.

0= Start condition not in progress

DS70175D-page 166

Preliminary

PIC24H

REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER

R-0 HSC

TRSTAT

U-0

—

U-0

—

U-0

—

R/C-0 HS

BCL

R-0 HSC

ADD10

ACKSTAT

GCSTAT

bit 15

bit 8

R/C-0 HS

IWCOL

R/C-0 HS

I2COV

R-0 HSC

D_A

R/C-0 HSC R/C-0 HSC

R-0 HSC

R_W

R-0 HSC

RBF

R-0 HSC

TBF

P

S

bit 7

bit 0

Legend:

U = Unimplemented bit, read as ‘0’

R = Readable bit

W = Writable bit

‘1’ = Bit is set

HS = Set in hardware

‘0’ = Bit is cleared

HSC = Hardware set/cleared

x = Bit is unknown

-n = Value at POR

bit 15

bit 14

ACKSTAT: Acknowledge Status bit

(when operating as I²C master, applicable to master transmit operation)

1= NACK received from slave

0= ACK received from slave

Hardware set or clear at end of slave Acknowledge.

TRSTAT: Transmit Status bit (when operating as I²C master, applicable to master transmit operation)

1= Master transmit is in progress (8 bits + ACK)

0= Master transmit is not in progress

Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.

bit 13-11

bit 10

Unimplemented: Read as ‘0’

BCL: Master Bus Collision Detect bit

1= A bus collision has been detected during a master operation

0= No collision

Hardware set at detection of bus collision.

bit 9

bit 8

bit 7

bit 6

bit 5

bit 4

GCSTAT: General Call Status bit

1= General call address was received

0= General call address was not received

Hardware set when address matches general call address. Hardware clear at Stop detection.

ADD10: 10-bit Address Status bit

1= 10-bit address was matched

0= 10-bit address was not matched

Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.

IWCOL: Write Collision Detect bit

1= An attempt to write the I2CxTRN register failed because the I²C module is busy

0= No collision

Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).

I2COV: Receive Overflow Flag bit

1= A byte was received while the I2CxRCV register is still holding the previous byte

0= No overflow

Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).

D_A: Data/Address bit (when operating as I²C slave)

1= Indicates that the last byte received was data

0= Indicates that the last byte received was device address

Hardware clear at device address match. Hardware set by reception of slave byte.

P: Stop bit

1= Indicates that a Stop bit has been detected last

0= Stop bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop detected.

Preliminary

DS70175D-page 167

PIC24H

REGISTER 16-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)

bit 3

bit 2

bit 1

S: Start bit

1= Indicates that a Start (or Repeated Start) bit has been detected last

0= Start bit was not detected last

Hardware set or clear when Start, Repeated Start or Stop detected.

R_W: Read/Write Information bit (when operating as I²C slave)

1= Read – indicates data transfer is output from slave

0= Write – indicates data transfer is input to slave

Hardware set or clear after reception of I²C device address byte.

RBF: Receive Buffer Full Status bit

1= Receive complete, I2CxRCV is full

0= Receive not complete, I2CxRCV is empty

Hardware set when I2CxRCV is written with received byte. Hardware clear when software

reads I2CxRCV.

bit 0

TBF: Transmit Buffer Full Status bit

1= Transmit in progress, I2CxTRN is full

0= Transmit complete, I2CxTRN is empty

Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.

DS70175D-page 168

Preliminary

PIC24H

REGISTER 16-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

AMSK9

AMSK8

bit 15

bit 8

R/W-0

AMSK7

AMSK6

AMSK5

AMSK4

AMSK3

AMSK2

AMSK1

AMSK0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-10

bit 9-0

Unimplemented: Read as ‘0’

AMSKx: Mask for Address bit x Select bit

1= Enable masking for bit x of incoming message address; bit match not required in this position

0= Disable masking for bit x; bit match required in this position

Preliminary

DS70175D-page 169

PIC24H

NOTES:

DS70175D-page 170

Preliminary

PIC24H

• Fully Integrated Baud Rate Generator with 16-bit

Prescaler

17.0 UNIVERSAL ASYNCHRONOUS

RECEIVER TRANSMITTER

(UART)

• Baud Rates Ranging from 1 Mbps to 15 bps at

16 MIPS

• 4-deep First-In-First-Out (FIFO) Transmit Data

Buffer

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

• 4-Deep FIFO Receive Data Buffer

• Parity, Framing and Buffer Overrun Error Detection

• Support for 9-bit mode with Address Detect

(9th bit = 1)

• Transmit and Receive Interrupts

The Universal Asynchronous Receiver Transmitter

(UART) module is one of the serial I/O modules avail-

able in the PIC24H device family. The UART is a full-

duplex asynchronous system that can communicate

with peripheral devices, such as personal computers,

LIN, RS-232 and RS-485 interfaces. The module also

supports a hardware flow control option with the

UxCTS and UxRTS pins and also includes an IrDA^®

encoder and decoder.

• A Separate Interrupt for all UART Error Conditions

• Loopback mode for Diagnostic Support

• Support for Sync and Break Characters

• Supports Automatic Baud Rate Detection

• IrDA Encoder and Decoder Logic

• 16x Baud Clock Output for IrDA Support

A simplified block diagram of the UART is shown in

Figure 17-1. The UART module consists of the key

important hardware elements:

The primary features of the UART module are:

• Full-Duplex, 8 or 9-bit Data Transmission through

the UxTX and UxRX pins

• Baud Rate Generator

• Even, Odd or No Parity Options (for 8-bit data)

• One or Two Stop bits

• Asynchronous Transmitter

• Asynchronous Receiver

• Hardware Flow Control Option with UxCTS and

UxRTS pins

FIGURE 17-1:

UART SIMPLIFIED BLOCK DIAGRAM

Baud Rate Generator

IrDA^®

BCLK

Hardware Flow Control

UART Receiver

UxRTS

UxCTS

UxRX

UxTX

UART Transmitter

Note 1: Both UART1 and UART2 can trigger a DMA data transfer. If U1TX, U1RX, U2TX or U2RX is selected as

a DMA IRQ source, a DMA transfer occurs when the U1TXIF, U1RXIF, U2TXIF or U2RXIF bit gets set as

a result of a UART1 or UART2 transmission or reception.

2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word

(i.e., UTXISEL<1:0> = 00and URXISEL<1:0> = 00).

Preliminary

DS70175D-page 171

PIC24H

Equation 17-2 shows the formula for computation of

the baud rate with BRGH = 1.

17.1 UART Baud Rate Generator (BRG)

The UART module includes a dedicated 16-bit Baud

Rate Generator. The BRGx register controls the period

of a free-running 16-bit timer. Equation 17-1 shows the

formula for computation of the baud rate with

BRGH = 0.

EQUATION 17-2: UART BAUD RATE WITH

BRGH = 1

FCY

Baud Rate =

4 • (BRGx + 1)

EQUATION 17-1: UART BAUD RATE WITH

BRGH = 0

FCY

4 • Baud Rate

– 1

BRGx =

FCY

Baud Rate =

16 • (BRGx + 1)

Note: FCY denotes the instruction cycle clock

frequency (FOSC/2).

FCY

16 • Baud Rate

– 1

BRGx =

The maximum baud rate (BRGH = 1) possible is FCY/4

(for BRGx = 0), and the minimum baud rate possible is

FCY/(4 * 65536).

Note: FCY denotes the instruction cycle clock

frequency (FOSC/2).

Writing a new value to the BRGx register causes the

BRG timer to be reset (cleared). This ensures the BRG

does not wait for a timer overflow before generating the

new baud rate.

Example 17-1 shows the calculation of the baud rate

error for the following conditions:

• FCY = 4 MHz

• Desired Baud Rate = 9600

The maximum baud rate (BRGH = 0) possible is

FCY/16 (for BRGx = 0), and the minimum baud rate

possible is FCY/(16 * 65536).

EXAMPLE 17-1:

BAUD RATE ERROR CALCULATION (BRGH = 0)

Desired Baud Rate

=

FCY/(16 (BRGx + 1))

Solving for BRGx Value:

BRGx

=

((FCY/Desired Baud Rate)/16) – 1

((4000000/9600)/16) – 1

25

Calculated Baud Rate

=

4000000/(16 (25 + 1))

9615

Error

=

(Calculated Baud Rate – Desired Baud Rate)

Desired Baud Rate

=

(9615 – 9600)/9600

0.16%

DS70175D-page 172

Preliminary

PIC24H

17.2 Transmitting in 8-bit Data Mode

17.5 Receiving in 8-bit or 9-bit Data

Mode

1. Set up the UART:

a) Write appropriate values for data, parity

and Stop bits.

1. Set up the UART (as described in Section 17.2

“Transmitting in 8-bit Data Mode”).

b) Write appropriate baud rate value to the

BRGx register.

2. Enable the UART.

3. A receive interrupt will be generated when one

or more data characters have been received as

per interrupt control bits, URXISEL<1:0>.

c) Set up transmit and receive interrupt enable

and priority bits.

2. Enable the UART.

4. Read the OERR bit to determine if an overrun

error has occurred. The OERR bit must be reset

in software.

3. Set the UTXEN bit (causes a transmit interrupt).

4. Write data byte to lower byte of UxTXREG word.

The value will be immediately transferred to the

Transmit Shift Register (TSR) and the serial bit

stream will start shifting out with the next rising

edge of the baud clock.

5. Read UxRXREG.

The act of reading the UxRXREG character will move

the next character to the top of the receive FIFO,

including a new set of PERR and FERR values.

5. Alternately, the data byte may be transferred

while UTXEN = 0, and then the user may set

UTXEN. This will cause the serial bit stream to

begin immediately because the baud clock will

start from a cleared state.

17.6 Flow Control Using UxCTS and

UxRTS Pins

UARTx Clear to Send (UxCTS) and Request to Send

(UxRTS) are the two hardware controlled active-low

pins that are associated with the UART module. These

two pins allow the UART to operate in Simplex and

Flow Control modes. They are implemented to control

the transmission and the reception between the Data

Terminal Equipment (DTE). The UEN<1:0> bits in the

UxMODE register configures these pins.

6. A transmit interrupt will be generated as per

interrupt control bits, UTXISEL<1:0>.

17.3 Transmitting in 9-bit Data Mode

1. Set up the UART (as described in Section 17.2

“Transmitting in 8-bit Data Mode”).

2. Enable the UART.

17.7 Infrared Support

3. Set the UTXEN bit (causes a transmit interrupt).

4. Write UxTXREG as a 16-bit value only.

The UART module provides two types of infrared

UART support:

5. A word write to UxTXREG triggers the transfer

of the 9-bit data to the TSR. Serial bit stream will

start shifting out with the first rising edge of the

baud clock.

• IrDA clock output to support external IrDA

encoder and decoder device (legacy module

support)

6. A transmit interrupt will be generated as per the

setting of control bits, UTXISEL<1:0>.

• Full implementation of the IrDA encoder and

decoder.

17.4 Break and Sync Transmit

Sequence

17.7.1

EXTERNAL IrDA SUPPORT – IrDA

CLOCK OUTPUT

To support external IrDA encoder and decoder

devices, the BCLK pin (same as the UxRTS pin) can be

configured to generate the 16x baud clock. With

UEN<1:0> = 11, the BCLK pin will output the 16x baud

clock if the UART module is enabled; it can be used to

support the IrDA codec chip.

The following sequence will send a message frame

header made up of a Break, followed by an auto-baud

Sync byte.

1. Configure the UART for the desired mode.

2. Set UTXEN and UTXBRK – sets up the Break

character.

17.7.2

BUILT-IN IrDA ENCODER AND

DECODER

3. Load the UxTXREG register with a dummy

character to initiate transmission (value is

ignored).

The UART has full implementation of the IrDA encoder

and decoder as part of the UART module. The built-in

IrDA encoder and decoder functionality is enabled

using the IREN bit (UxMODE<12>). When enabled

(IREN = 1), the receive pin (UxRX) acts as the input

from the infrared receiver. The transmit pin (UxTX) acts

as the output to the infrared transmitter.

4. Write 0x55 to UxTXREG – loads Sync character

into the transmit FIFO.

5. After the Break has been sent, the UTXBRK bit

is reset by hardware. The Sync character now

transmits.

Preliminary

DS70175D-page 173

PIC24H

REGISTER 17-1: UxMODE: UARTx MODE REGISTER

R/W-0

U-0

—

R/W-0

USIDL

R/W-0

IREN⁽¹⁾

R/W-0

U-0

—

R/W-0⁽²⁾

UARTEN

RTSMD

UEN<1:0>

bit 15

bit 8

R/W-0 HC

WAKE

R/W-0

R/W-0 HC

ABAUD

R/W-0

BRGH

R/W-0

LPBACK

URXINV

PDSEL<1:0>

STSEL

bit 7

bit 0

Legend:

HC = Hardware cleared

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15

UARTEN: UARTx Enable bit

1= UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>

0= UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption

minimal

bit 14

bit 13

Unimplemented: Read as ‘0’

USIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode.

0= Continue module operation in Idle mode

bit 12

bit 11

IREN: IrDA Encoder and Decoder Enable bit⁽¹⁾

1= IrDA encoder and decoder enabled

0= IrDA encoder and decoder disabled

RTSMD: Mode Selection for UxRTS Pin bit

1= UxRTS pin in Simplex mode

0= UxRTS pin in Flow Control mode

bit 10

Unimplemented: Read as ‘0’

UEN<1:0>: UARTx Enable bits

bit 9-8

11=UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches

10=UxTX, UxRX, UxCTS and UxRTS pins are enabled and used

01=UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches

00=UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by

port latches

bit 7

WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit

1= UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared

in hardware on following rising edge

0= No wake-up enabled

bit 6

bit 5

LPBACK: UARTx Loopback Mode Select bit

1= Enable Loopback mode

0= Loopback mode is disabled

ABAUD: Auto-Baud Enable bit

1= Enable baud rate measurement on the next character – requires reception of a Sync field (55h);

cleared in hardware upon completion

0= Baud rate measurement disabled or completed

bit 4

URXINV: Receive Polarity Inversion bit

1= UxRX Idle state is ‘0’

0= UxRX Idle state is ‘1’

Note 1: This feature is only available for the 16x BRG mode (BRGH = 0).

2: Bit availability depends on pin availability.

DS70175D-page 174

Preliminary

PIC24H

REGISTER 17-1: UxMODE: UARTx MODE REGISTER (CONTINUED)

bit 3

BRGH: High Baud Rate Enable bit

1= BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)

0= BRG generates 16 clocks per bit period (16x baud clock, Standard mode)

bit 2-1

PDSEL<1:0>: Parity and Data Selection bits

11= 9-bit data, no parity

10= 8-bit data, odd parity

01= 8-bit data, even parity

00= 8-bit data, no parity

bit 0

STSEL: Stop Bit Selection bit

1= Two Stop bits

0= One Stop bit

Note 1: This feature is only available for the 16x BRG mode (BRGH = 0).

2: Bit availability depends on pin availability.

Preliminary

DS70175D-page 175

PIC24H

REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER

R/W-0

UTXINV⁽¹⁾

R/W-0

U-0

—

R/W-0 HC

UTXBRK

R/W-0

R-0

R-1

UTXISEL1

UTXISEL0

UTXEN

UTXBF

TRMT

bit 15

bit 8

R/W-0

R-1

R-0

R/C-0

R-0

URXISEL<1:0>

ADDEN

RIDLE

PERR

FERR

OERR

URXDA

bit 7

bit 0

Legend:

HC = Hardware cleared

W = Writable bit

R = Readable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15,13

‘1’ = Bit is set

UTXISEL<1:0>: Transmission Interrupt Mode Selection bits

11=Reserved; do not use

10=Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the

transmit buffer becomes empty

01=Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit

operations are completed

00=Interrupt when a character is transferred to the Transmit Shift Register (this implies there is

at least one character open in the transmit buffer)

bit 14

UTXINV: IrDA Encoder Transmit Polarity Inversion bit⁽¹⁾

1= IrDA encoded, UxTX Idle state is ‘1’

0= IrDA encoded, UxTX Idle state is ‘0’

bit 12

bit 11

Unimplemented: Read as ‘0’

UTXBRK: Transmit Break bit

1= Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;

cleared by hardware upon completion

0= Sync Break transmission disabled or completed

bit 10

UTXEN: Transmit Enable bit

1= Transmit enabled, UxTX pin controlled by UARTx

0= Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled

by port.

bit 9

UTXBF: Transmit Buffer Full Status bit (read-only)

1= Transmit buffer is full

0= Transmit buffer is not full, at least one more character can be written

bit 8

TRMT: Transmit Shift Register Empty bit (read-only)

1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)

0= Transmit Shift Register is not empty, a transmission is in progress or queued

bit 7-6

URXISEL<1:0>: Receive Interrupt Mode Selection bits

11=Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters)

10=Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters)

0x=Interrupt is set when any character is received and transferred from the UxRSR to the receive

buffer. Receive buffer has one or more characters.

bit 5

ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1= Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.

0= Address Detect mode disabled

Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled

(IREN = 1).

DS70175D-page 176

Preliminary

PIC24H

REGISTER 17-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)

bit 4

bit 3

bit 2

RIDLE: Receiver Idle bit (read-only)

1= Receiver is Idle

0= Receiver is active

PERR: Parity Error Status bit (read-only)

1= Parity error has been detected for the current character (character at the top of the receive FIFO)

0= Parity error has not been detected

FERR: Framing Error Status bit (read-only)

1= Framing error has been detected for the current character (character at the top of the receive

FIFO)

0= Framing error has not been detected

bit 1

bit 0

OERR: Receive Buffer Overrun Error Status bit (read/clear only)

1= Receive buffer has overflowed

0= Receive buffer has not overflowed. Clearing a previously set OERR bit (1→ 0transition) will reset

the receiver buffer and the UxRSR to the empty state.

URXDA: Receive Buffer Data Available bit (read-only)

1= Receive buffer has data, at least one more character can be read

0= Receive buffer is empty

Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled

(IREN = 1).

Preliminary

DS70175D-page 177

PIC24H

NOTES:

DS70175D-page 178

Preliminary

PIC24H

The CAN bus module consists of a protocol engine and

message buffering/control. The CAN protocol engine

handles all functions for receiving and transmitting

messages on the CAN bus. Messages are transmitted

by first loading the appropriate data registers. Status

and errors can be checked by reading the appropriate

registers. Any message detected on the CAN bus is

checked for errors and then matched against filters to

see if it should be received and stored in one of the

receive registers.

18.0 ENHANCED CAN MODULE

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

18.1 Overview

The Enhanced Controller Area Network (ECAN) mod-

ule is a serial interface, useful for communicating with

other CAN modules or microcontroller devices. This

interface/protocol was designed to allow communica-

tions within noisy environments. The PIC24H devices

contain up to two ECAN modules.

18.2 Frame Types

The CAN module transmits various types of frames

which include data messages, remote transmission

requests and as other frames that are automatically

generated for control purposes. The following frame

types are supported:

The CAN module is a communication controller imple-

menting the CAN 2.0 A/B protocol, as defined in the

BOSCH specification. The module will support CAN 1.2,

CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active

versions of the protocol. The module implementation is

a full CAN system. The CAN specification is not covered

within this data sheet. The reader may refer to the

BOSCH CAN specification for further details.

• Standard Data Frame:

A standard data frame is generated by a node

when the node wishes to transmit data. It includes

an 11-bit standard identifier (SID) but not an 18-bit

extended identifier (EID).

• Extended Data Frame:

An extended data frame is similar to a standard

data frame but includes an extended identifier as

well.

The module features are as follows:

• Implementation of the CAN protocol, CAN 1.2,

CAN 2.0A and CAN 2.0B

• Remote Frame:

• Standard and extended data frames

• 0-8 bytes data length

It is possible for a destination node to request the

data from the source. For this purpose, the

destination node sends a remote frame with an

identifier that matches the identifier of the required

data frame. The appropriate data source node will

then send a data frame as a response to this

remote request.

• Programmable bit rate up to 1 Mbit/sec

• Automatic response to remote transmission

requests

• Up to 8 transmit buffers with application specified

prioritization and abort capability (each buffer may

contain up to 8 bytes of data)

• Error Frame:

• Up to 32 receive buffers (each buffer may contain

up to 8 bytes of data)

An error frame is generated by any node that

detects a bus error. An error frame consists of two

fields: an error flag field and an error delimiter

field.

• Up to 16 full (standard/extended identifier)

acceptance filters

• 3 full acceptance filter masks

• Overload Frame:

• DeviceNet™ addressing support

An overload frame can be generated by a node as

a result of two conditions. First, the node detects

a dominant bit during interframe space which is an

illegal condition. Second, due to internal condi-

tions, the node is not yet able to start reception of

the next message. A node may generate a maxi-

mum of 2 sequential overload frames to delay the

start of the next message.

• Programmable wake-up functionality with

integrated low-pass filter

• Programmable Loopback mode supports self-test

operation

• Signaling via interrupt capabilities for all CAN

receiver and transmitter error states

• Programmable clock source

• Programmable link to input capture module (IC2

for both CAN1 and CAN2) for time-stamping and

network synchronization

• Interframe Space:

Interframe space separates a proceeding frame

(of whatever type) from a following data or remote

frame.

• Low-power Sleep and Idle mode

Preliminary

DS70175D-page 179

PIC24H

FIGURE 18-1:

ECAN™ MODULE BLOCK

DIAGRAM

RXF15 Filter

RXF14 Filter

RXF13 Filter

RXF12 Filter

RXF11 Filter

RXF10 Filter

RXF9 Filter

RXF8 Filter

RXF7 Filter

RXF6 Filter

RXF5 Filter

RXF4 Filter

RXF3 Filter

RXF2 Filter

RXF1 Filter

RXF0 Filter

DMA Controller

TRB7 TX/RX Buffer Control Register

TRB6 TX/RX Buffer Control Register

TRB5 TX/RX Buffer Control Register

TRB4 TX/RX Buffer Control Register

TRB3 TX/RX Buffer Control Register

TRB2 TX/RX Buffer Control Register

TRB1 TX/RX Buffer Control Register

TRB0 TX/RX Buffer Control Register

RXM2 Mask

RXM1 Mask

RXM0 Mask

Transmit Byte

Sequencer

Message Assembly

Buffer

Control

Configuration

Logic

CPU

Bus

CAN Protocol

Engine

Interrupts

(1)

CiTX

CiRX

Note 1: i = 1 or 2 refers to a particular ECAN module (ECAN1 or ECAN2).

DS70175D-page 180

Preliminary

PIC24H

18.3 Modes of Operation

Note:

Typically, if the CAN module is allowed to

transmit in a particular mode of operation

and a transmission is requested immedi-

ately after the CAN module has been

placed in that mode of operation, the mod-

ule waits for 11 consecutive recessive bits

on the bus before starting transmission. If

the user switches to Disable mode within

this 11-bit period, then this transmission is

aborted and the corresponding TXABT bit

is set and TXREQ bit is cleared.

The CAN module can operate in one of several operation

modes selected by the user. These modes include:

• Initialization Mode

• Disable Mode

• Normal Operation Mode

• Listen Only Mode

• Listen All Messages Mode

• Loopback Mode

Modes are requested by setting the REQOP<2:0> bits

(CiCTRL1<10:8>). Entry into a mode is Acknowledged

18.3.3

NORMAL OPERATION MODE

by

monitoring

the

OPMODE<2:0>

bits

Normal Operation mode is selected when

REQOP<2:0> = 000. In this mode, the module is

activated and the I/O pins will assume the CAN bus

functions. The module will transmit and receive CAN

bus messages via the CiTX and CiRX pins.

(CiCTRL1<7:5>). The module will not change the mode

and the OPMODE bits until a change in mode is

acceptable, generally during bus Idle time, which is

defined as at least 11 consecutive recessive bits.

18.3.1

INITIALIZATION MODE

18.3.4

LISTEN ONLY MODE

In the Initialization mode, the module will not transmit or

receive. The error counters are cleared and the inter-

rupt flags remain unchanged. The programmer will

have access to Configuration registers that are access

restricted in other modes. The module will protect the

user from accidentally violating the CAN protocol

through programming errors. All registers which control

the configuration of the module can not be modified

while the module is on-line. The CAN module will not

be allowed to enter the Configuration mode while a

transmission is taking place. The Configuration mode

serves as a lock to protect the following registers.

If the Listen Only mode is activated, the module on the

CAN bus is passive. The transmitter buffers revert to

the port I/O function. The receive pins remain inputs.

For the receiver, no error flags or Acknowledge signals

are sent. The error counters are deactivated in this

state. The Listen Only mode can be used for detecting

the baud rate on the CAN bus. To use this, it is neces-

sary that there are at least two further nodes that

communicate with each other.

18.3.5

LISTEN ALL MESSAGES MODE

The module can be set to ignore all errors and receive

any message. The Listen All Messages mode is acti-

vated by setting REQOP<2:0> = ‘111’. In this mode,

the data which is in the message assembly buffer, until

the time an error occurred, is copied in the receive

buffer and can be read via the CPU interface.

• All Module Control Registers

• Baud Rate and Interrupt Configuration Registers

• Bus Timing Registers

• Identifier Acceptance Filter Registers

• Identifier Acceptance Mask Registers

18.3.2

DISABLE MODE

18.3.6

LOOPBACK MODE

In Disable mode, the module will not transmit or

receive. The module has the ability to set the WAKIF bit

due to bus activity, however, any pending interrupts will

remain and the error counters will retain their value.

If the Loopback mode is activated, the module will con-

nect the internal transmit signal to the internal receive

signal at the module boundary. The transmit and

receive pins revert to their port I/O function.

If the REQOP<2:0> bits (CiCTRL1<10:8>) = 001, the

module will enter the Module Disable mode. If the module

is active, the module will wait for 11 recessive bits on the

CAN bus, detect that condition as an Idle bus, then

accept the module disable command. When the

OPMODE<2:0> bits (CiCTRL1<7:5>) = 001, that indi-

cates whether the module successfully went into Module

Disable mode. The I/O pins will revert to normal I/O

function when the module is in the Module Disable mode.

18.4 Message Reception

18.4.1

RECEIVE BUFFERS

The CAN bus module has up to 32 receive buffers,

located in DMA RAM. The first 8 buffers need to be

configured as receive buffers by clearing the

corresponding TX/RX buffer selection (TXENn) bit in a

CiTRmnCON register. The overall size of the CAN

buffer area in DMA RAM is selectable by the user and

The module can be programmed to apply a low-pass

filter function to the CiRX input line while the module or

the CPU is in Sleep mode. The WAKFIL bit

(CiCFG2<14>) enables or disables the filter.

is

defined

by

the

DMABS<2:0>

bits

(CiFCTRL<15:13>). The first 16 buffers can be

assigned to receive filters, while the rest can be used

only as a FIFO buffer.

Preliminary

DS70175D-page 181

PIC24H

An additional buffer is always committed to monitoring

the bus for incoming messages. This buffer is called

the Message Assembly Buffer (MAB).

18.4.5

RECEIVE ERRORS

The CAN module will detect the following receive

errors:

All messages are assembled by the MAB and are trans-

ferred to the buffers only if the acceptance filter criterion

are met. When a message is received, the RBIF flag

(CiINTF<1>) will be set. The user would then need to

inspect the CiVEC and/or CiRXFUL1 register to deter-

mine which filter and buffer caused the interrupt to get

generated. The RBIF bit can only be set by the module

when a message is received. The bit is cleared by the

user when it has completed processing the message in

the buffer. If the RBIE bit is set, an interrupt will be

generated when a message is received.

• Cyclic Redundancy Check (CRC) Error

• Bit Stuffing Error

• Invalid Message Receive Error

These receive errors do not generate an interrupt.

However, the receive error counter is incremented by

one in case one of these errors occur. The RXWAR bit

(CiINTF<9>) indicates that the receive error counter

has reached the CPU warning limit of 96 and an

interrupt is generated.

18.4.6

RECEIVE INTERRUPTS

18.4.2

FIFO BUFFER MODE

Receive interrupts can be divided into 3 major groups,

each including various conditions that generate

interrupts:

The ECAN module provides FIFO buffer functionality if

the buffer pointer for a filter has a value of ‘1111’. In this

mode, the results of a hit on that buffer will write to the

next available buffer location within the FIFO.

• Receive Interrupt:

A message has been successfully received and

loaded into one of the receive buffers. This inter-

rupt is activated immediately after receiving the

End-of-Frame (EOF) field. Reading the RXnIF flag

will indicate which receive buffer caused the

interrupt.

The CiFCTRL register defines the size of the FIFO. The

FSA<4:0> bits in this register define the start of the

FIFO buffers. The end of the FIFO is defined by the

DMABS<2:0> bits if DMA is enabled. Thus, FIFO sizes

up to 32 buffers are supported.

18.4.3

MESSAGE ACCEPTANCE FILTERS

• Wake-up Interrupt:

The CAN module has woken up from Disable

mode or the device has woken up from Sleep

mode.

The message acceptance filters and masks are used to

determine if a message in the message assembly

buffer should be loaded into either of the receive buff-

ers. Once a valid message has been received into the

Message Assembly Buffer (MAB), the identifier fields of

the message are compared to the filter values. If there

is a match, that message will be loaded into the

appropriate receive buffer. Each filter is associated with

a buffer pointer (FnBP<3:0>), which is used to link the

filter to one of 16 receive buffers.

• Receive Error Interrupts:

A receive error interrupt will be indicated by the

ERRIF bit. This bit shows that an error condition

occurred. The source of the error can be deter-

mined by checking the bits in the CAN Interrupt

Flag register, CiINTF.

- Invalid Message Received:

The acceptance filter looks at incoming messages for

the IDE bit (CiTRBnSID<0>) to determine how to com-

pare the identifiers. If the IDE bit is clear, the message

is a standard frame and only filters with the EXIDE bit

(CiRXFnSID<3>) clear are compared. If the IDE bit is

set, the message is an extended frame, and only filters

with the EXIDE bit set are compared.

If any type of error occurred during reception of

the last message, an error will be indicated by

the IVRIF bit.

- Receiver Overrun:

The RBOVIF bit (CiINTF<2>) indicates that an

overrun condition occurred.

18.4.4

MESSAGE ACCEPTANCE FILTER

MASKS

- Receiver Warning:

The RXWAR bit indicates that the receive error

counter (RERRCNT<7:0>) has reached the

warning limit of 96.

The mask bits essentially determine which bits to apply

the filter to. If any mask bit is set to a zero, then that bit

will automatically be accepted regardless of the filter

bit. There are three programmable acceptance filter

masks associated with the receive buffers. Any of

these three masks can be linked to each filter by select-

ing the desired mask in the FnMSK<1:0> bits in the

appropriate CiFMSKSELn register.

- Receiver Error Passive:

The RXEP bit indicates that the receive error

counter has exceeded the error passive limit of

127 and the module has gone into error passive

state.

DS70175D-page 182

Preliminary

PIC24H

18.5.4

AUTOMATIC PROCESSING OF

REMOTE TRANSMISSION

REQUESTS

18.5 Message Transmission

18.5.1 TRANSMIT BUFFERS

The CAN module has up to eight transmit buffers,

located in DMA RAM. These 8 buffers need to be con-

figured as transmit buffers by setting the corresponding

TX/RX buffer selection (TXENn or TXENm) bit in a

CiTRmnCON register. The overall size of the CAN

buffer area in DMA RAM is selectable by the user and

If the RTRENn bit (in the CiTRmnCON register) for a

particular transmit buffer is set, the hardware automat-

ically transmits the data in that buffer in response to

remote transmission requests matching the filter that

points to that particular buffer. The user does not need

to manually initiate a transmission in this case.

is

defined

by

the

DMABS<2:0>

bits

(CiFCTRL<15:13>).

18.5.5

ABORTING MESSAGE

TRANSMISSION

Each transmit buffer occupies 16 bytes of data. Eight of

the bytes are the maximum 8 bytes of the transmitted

message. Five bytes hold the standard and extended

identifiers and other message arbitration information.

The last byte is unused.

The system can also abort a message by clearing the

TXREQ bit associated with each message buffer. Set-

ting the ABAT bit (CiCTRL1<12>) will request an abort

of all pending messages. If the message has not yet

started transmission, or if the message started but is

interrupted by loss of arbitration or an error, the abort

will be processed. The abort is indicated when the

module sets the TXABT bit and the TXnIF flag is not

automatically set.

18.5.2

TRANSMIT MESSAGE PRIORITY

Transmit priority is a prioritization within each node of

the pending transmittable messages. There are four

levels of transmit priority. If the TXnPRI<1:0> bits (in

CiTRmnCON) for a particular message buffer are set to

‘11’, that buffer has the highest priority. If the

18.5.6

TRANSMISSION ERRORS

TXnPRI<1:0> bits for a particular message buffer are

set to ‘10’ or ‘01’, that buffer has an intermediate prior-

ity. If the TXnPRI<1:0> bits for a particular message

buffer are ‘00’, that buffer has the lowest priority. If two

or more pending messages have the same priority, the

messages are transmitted in decreasing order of buffer

index.

The CAN module will detect the following transmission

errors:

• Acknowledge Error

• Form Error

• Bit Error

These transmission errors will not necessarily generate

an interrupt, but are indicated by the transmission error

counter. However, each of these errors will cause the

transmission error counter to be incremented by one.

Once the value of the error counter exceeds the value

of 96, the ERRIF (CiINTF<5>) and the TXWAR bit

(CiINTF<10>) are set. Once the value of the error

counter exceeds the value of 96, an interrupt is

generated and the TXWAR bit in the Interrupt Flag

register is set.

18.5.3

TRANSMISSION SEQUENCE

To initiate transmission of the message, the TXREQn

bit (in CiTRmnCON) must be set. The CAN bus module

resolves any timing conflicts between the setting of the

TXREQn bit and the Start-of-Frame (SOF), ensuring

that if the priority was changed, it is resolved correctly

before the SOF occurs. When TXREQn is set, the

TXABTn, TXLARBn and TXERRn flag bits are

automatically cleared.

Setting the TXREQn bit simply flags a message buffer

as enqueued for transmission. When the module

detects an available bus, it begins transmitting the

message which has been determined to have the

highest priority.

If the transmission completes successfully on the first

attempt, the TXREQn bit is cleared automatically and

an interrupt is generated if TXnIE was set.

If the message transmission fails, one of the error con-

dition flags will be set and the TXREQn bit will remain

set, indicating that the message is still pending for

transmission. If the message encountered an error

condition during the transmission attempt, the TXERRn

bit will be set and the error condition may cause an

interrupt. If the message loses arbitration during the

transmission attempt, the TXLARBn bit is set. No

interrupt is generated to signal the loss of arbitration.

Preliminary

DS70175D-page 183

PIC24H

18.5.7

TRANSMIT INTERRUPTS

18.6 Baud Rate Setting

Transmit interrupts can be divided into 2 major groups,

each including various conditions that generate

interrupts:

All nodes on any particular CAN bus must have the

same nominal bit rate. In order to set the baud rate, the

following parameters have to be initialized:

• Transmit Interrupt:

• Synchronization Jump Width

• Baud Rate Prescaler

At least one of the three transmit buffers is empty

(not scheduled) and can be loaded to schedule a

message for transmission. Reading the TXnIF

flags will indicate which transmit buffer is available

and caused the interrupt.

• Phase Segments

• Length Determination of Phase Segment 2

• Sample Point

• Propagation Segment bits

• Transmit Error Interrupts:

A transmission error interrupt will be indicated by

the ERRIF flag. This flag shows that an error con-

dition occurred. The source of the error can be

determined by checking the error flags in the CAN

Interrupt Flag register, CiINTF. The flags in this

register are related to receive and transmit errors.

18.6.1

BIT TIMING

All controllers on the CAN bus must have the same

baud rate and bit length. However, different controllers

are not required to have the same master oscillator

clock. At different clock frequencies of the individual

controllers, the baud rate has to be adjusted by

adjusting the number of time quanta in each segment.

- Transmitter Warning Interrupt:

The TXWAR bit indicates that the transmit error

counter has reached the CPU warning limit

of 96.

The nominal bit time can be thought of as being divided

into separate non-overlapping time segments. These

segments are shown in Figure 18-2.

- Transmitter Error Passive:

•

Synchronization Segment (Sync Seg)

Propagation Time Segment (Prop Seg)

Phase Segment 1 (Phase1 Seg)

Phase Segment 2 (Phase2 Seg)

The TXEP bit (CiINTF<12>) indicates that the

transmit error counter has exceeded the error

passive limit of 127 and the module has gone to

error passive state.

The time segments and also the nominal bit time are

made up of integer units of time called time quanta or

TQ. By definition, the nominal bit time has a minimum

of 8 TQ and a maximum of 25 TQ. Also, by definition,

the minimum nominal bit time is 1 μsec corresponding

to a maximum bit rate of 1 MHz.

- Bus Off:

The TXBO bit (CiINTF<13>) indicates that the

transmit error counter has exceeded 255 and

the module has gone to the bus off state.

Note:

Both ECAN1 and ECAN2 can trigger a

DMA data transfer. If C1TX, C1RX, C2TX

or C2RX is selected as a DMA IRQ

source, a DMA transfer occurs when the

C1TXIF, C1RXIF, C2TXIF or C2RXIF bit

gets set as a result of an ECAN1 or

ECAN2 transmission or reception.

FIGURE 18-2:

ECAN™ MODULE BIT TIMING

Input Signal

Prop

Segment

Phase

Segment 1

Phase

Segment 2

Sync

Sample Point

TQ

DS70175D-page 184

Preliminary

PIC24H

Typically, the sampling of the bit should take place at

about 60-70% through the bit time, depending on the

system parameters.

18.6.2

PRESCALER SETTING

There is a programmable prescaler with integral values

ranging from 1 to 64, in addition to a fixed divide-by-2

for clock generation. The time quantum (TQ) is a fixed

unit of time derived from the oscillator period and is

given by Equation 18-1.

18.6.6

SYNCHRONIZATION

To compensate for phase shifts between the oscillator

frequencies of the different bus stations, each CAN

controller must be able to synchronize to the relevant

signal edge of the incoming signal. When an edge in

the transmitted data is detected, the logic will compare

the location of the edge to the expected time (Synchro-

nous Segment). The circuit will then adjust the values

of Phase1 Seg and Phase2 Seg. There are two

mechanisms used to synchronize.

Note:

FCAN must not exceed 40 MHz. If

CANCKS = 0, then FCY must not exceed

20 MHz.

EQUATION 18-1: TIME QUANTUM FOR

CLOCK GENERATION

TQ = 2 (BRP<5:0> + 1)/FCAN

18.6.6.1

Hard Synchronization

Hard synchronization is only done whenever there is a

‘recessive’ to ‘dominant’ edge during bus Idle, indicat-

ing the start of a message. After hard synchronization,

the bit time counters are restarted with the Sync Seg.

Hard synchronization forces the edge which has

caused the hard synchronization to lie within the

synchronization segment of the restarted bit time. If a

hard synchronization is done, there will not be a

resynchronization within that bit time.

18.6.3

PROPAGATION SEGMENT

This part of the bit time is used to compensate physical

delay times within the network. These delay times con-

sist of the signal propagation time on the bus line and

the internal delay time of the nodes. The Prop Seg can

be programmed from 1 TQ to 8 TQ by setting the

PRSEG<2:0> bits (CiCFG2<2:0>).

18.6.4

PHASE SEGMENTS

18.6.6.2

Resynchronization

The phase segments are used to optimally locate the

sampling of the received bit within the transmitted bit

time. The sampling point is between Phase1 Seg and

Phase2 Seg. These segments are lengthened or short-

ened by resynchronization. The end of the Phase1 Seg

determines the sampling point within a bit period. The

segment is programmable from 1 TQ to 8 TQ. Phase2

Seg provides delay to the next transmitted data transi-

tion. The segment is programmable from 1 TQ to 8 TQ,

or it may be defined to be equal to the greater of

Phase1 Seg or the information processing time (2 TQ).

The Phase1 Seg is initialized by setting bits

SEG1PH<2:0> (CiCFG2<5:3>) and Phase2 Seg is

initialized by setting SEG2PH<2:0> (CiCFG2<10:8>).

As a result of resynchronization, Phase1 Seg may be

lengthened or Phase2 Seg may be shortened. The

amount of lengthening or shortening of the phase

buffer segment has an upper boundary known as the

synchronization jump width, and is specified by the

SJW<1:0> bits (CiCFG1<7:6>). The value of the syn-

chronization jump width will be added to Phase1 Seg or

subtracted from Phase2 Seg. The resynchronization

jump width is programmable between 1 TQ and 4 TQ.

The following requirement must be fulfilled while setting

the SJW<1:0> bits:

Phase2 Seg > Synchronization Jump Width

The following requirement must be fulfilled while setting

the lengths of the phase segments:

Note:

In the register descriptions that follow, ‘i’ in

the register identifier denotes the specific

ECAN module (ECAN1 or ECAN2).

Prop Seg + Phase1 Seg ≥ Phase2 Seg

‘n’ in the register identifier denotes the

buffer, filter or mask number.

18.6.5

SAMPLE POINT

The sample point is the point of time at which the bus

level is read and interpreted as the value of that respec-

tive bit. The location is at the end of Phase1 Seg. If the

bit timing is slow and contains many TQ, it is possible to

specify multiple sampling of the bus line at the sample

point. The level determined by the CAN bus then corre-

sponds to the result from the majority decision of three

values. The majority samples are taken at the sample

point and twice before with a distance of TQ/2. The

CAN module allows the user to choose between sam-

pling three times at the same point or once at the same

point, by setting or clearing the SAM bit (CiCFG2<6>).

‘m’ in the register identifier denotes the

word number within a particular CAN data

field.

Preliminary

DS70175D-page 185

PIC24H

REGISTER 18-1: CiCTRL1: ECAN MODULE CONTROL REGISTER 1

U-0

—

U-0

—

R/W-0

CSIDL

R/W-0

ABAT

R/W-0

R/W-1

R/W-0

bit 8

CANCKS

REQOP<2:0>

bit 15

R-1

R-0

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0

WIN

OPMODE<2:0>

CANCAP

bit 7

Legend:

bit 0

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

CSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12

ABAT: Abort All Pending Transmissions bit

Signal all transmit buffers to abort transmission. Module will clear this bit when all transmissions

are aborted

bit 11

CANCKS: CAN Master Clock Select bit

1= CAN FCAN clock is FCY

0= CAN FCAN clock is FOSC

bit 10-8

REQOP<2:0>: Request Operation Mode bits

000= Set Normal Operation mode

001= Set Disable mode

010= Set Loopback mode

011= Set Listen Only Mode

100= Set Configuration mode

101= Reserved – do not use

110= Reserved – do not use

111= Set Listen All Messages mode

bit 7-5

OPMODE<2:0>: Operation Mode bits

000= Module is in Normal Operation mode

001= Module is in Disable mode

010= Module is in Loopback mode

011= Module is in Listen Only mode

100= Module is in Configuration mode

101= Reserved

110= Reserved

111= Module is in Listen All Messages mode

bit 4

bit 3

Unimplemented: Read as ‘0’

CANCAP: CAN Message Receive Timer Capture Event Enable bit

1= Enable input capture based on CAN message receive

0= Disable CAN capture

bit 2-1

bit 0

Unimplemented: Read as ‘0’

WIN: SFR Map Window Select bit

1= Use filter window

0= Use buffer window

DS70175D-page 186

Preliminary

PIC24H

REGISTER 18-2: CiCTRL2: ECAN MODULE CONTROL REGISTER 2

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R-0

DNCNT<4:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

bit 4-0

Unimplemented: Read as ‘0’

DNCNT<4:0>: DeviceNet™ Filter Bit Number bits

10010-11111= Invalid selection

10001= Compare up to data byte 3, bit 6 with EID<17>

....

00001= Compare up to data byte 1, bit 7 with EID<0>

00000= Do not compare data bytes

Preliminary

DS70175D-page 187

PIC24H

REGISTER 18-3: CiVEC: ECAN MODULE INTERRUPT CODE REGISTER

U-0

—

U-0

—

U-0

—

R-0

FILHIT<4:0>

bit 15

bit 8

bit 0

U-0

—

R-1

R-0

ICODE<6:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

FILHIT<4:0>: Filter Hit Number bits

10000-11111= Reserved

01111= Filter 15

....

00001= Filter 1

00000= Filter 0

bit 7

Unimplemented: Read as ‘0’

bit 6-0

ICODE<6:0>: Interrupt Flag Code bits

1000101-1111111= Reserved

1000100= FIFO almost full interrupt

1000011= Receiver overflow interrupt

1000010= Wake-up interrupt

1000001= Error interrupt

1000000= No interrupt

0010000-0111111= Reserved

0001111= RB15 buffer Interrupt

....

0001001= RB9 buffer interrupt

0001000= RB8 buffer interrupt

0000111= TRB7 buffer interrupt

0000110= TRB6 buffer interrupt

0000101= TRB5 buffer interrupt

0000100= TRB4 buffer interrupt

0000011= TRB3 buffer interrupt

0000010= TRB2 buffer interrupt

0000001= TRB1 buffer interrupt

0000000= TRB0 Buffer interrupt

DS70175D-page 188

Preliminary

PIC24H

REGISTER 18-4: CiFCTRL: ECAN MODULE FIFO CONTROL REGISTER

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

DMABS<2:0>

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

bit 0

FSA<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

DMABS<2:0>: DMA Buffer Size bits

111= Reserved

110= 32 buffers in DMA RAM

101= 24 buffers in DMA RAM

100= 16 buffers in DMA RAM

011= 12 buffers in DMA RAM

010= 8 buffers in DMA RAM

001= 6 buffers in DMA RAM

000= 4 buffers in DMA RAM

bit 12-5

bit 4-0

Unimplemented: Read as ‘0’

FSA<4:0>: FIFO Area Starts with Buffer bits

11111= RB31 buffer

11110= RB30 buffer

....

00001= TRB1 buffer

00000= TRB0 buffer

Preliminary

DS70175D-page 189

PIC24H

REGISTER 18-5: CiFIFO: ECAN MODULE FIFO STATUS REGISTER

U-0

—

U-0

—

R-0

FBP<5:0>

R-0

bit 15

bit 8

bit 0

U-0

—

U-0

—

R-0

FNRB<5:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-8

Unimplemented: Read as ‘0’

FBP<5:0>: FIFO Write Buffer Pointer bits

011111= RB31 buffer

011110= RB30 buffer

....

000001= TRB1 buffer

000000= TRB0 buffer

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

FNRB<5:0>: FIFO Next Read Buffer Pointer bits

011111= RB31 buffer

011110= RB30 buffer

....

000001= TRB1 buffer

000000= TRB0 buffer

DS70175D-page 190

Preliminary

PIC24H

REGISTER 18-6: CiINTF: ECAN MODULE INTERRUPT FLAG REGISTER

U-0

—

U-0

—

R-0

TXBO

TXBP

RXBP

TXWAR

RXWAR

EWARN

bit 8

bit 15

R/C-0

IVRIF

R/C-0

U-0

—

R/C-0

RBIF

R/C-0

TBIF

WAKIF

ERRIF

FIFOIF

RBOVIF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

bit 12

bit 11

bit 10

bit 9

Unimplemented: Read as ‘0’

TXBO: Transmitter in Error State Bus Off bit

TXBP: Transmitter in Error State Bus Passive bit

RXBP: Receiver in Error State Bus Passive bit

TXWAR: Transmitter in Error State Warning bit

RXWAR: Receiver in Error State Warning bit

EWARN: Transmitter or Receiver in Error State Warning bit

IVRIF: Invalid Message Received Interrupt Flag bit

WAKIF: Bus Wake-up Activity Interrupt Flag bit

ERRIF: Error Interrupt Flag bit (multiple sources in CiINTF<13:8> register)

Unimplemented: Read as ‘0’

bit 8

bit 7

bit 6

bit 5

bit 4

bit 3

FIFOIF: FIFO Almost Full Interrupt Flag bit

RBOVIF: RX Buffer Overflow Interrupt Flag bit

RBIF: RX Buffer Interrupt Flag bit

bit 2

bit 1

bit 0

TBIF: TX Buffer Interrupt Flag bit

Preliminary

DS70175D-page 191

PIC24H

REGISTER 18-7: CiINTE: ECAN MODULE INTERRUPT ENABLE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

IVRIE

R/W-0

ERRIE

R/W-0

—

R/W-0

RBIE

R/W-0

TBIE

WAKIE

FIFOIE

RBOVIE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Unimplemented: Read as ‘0’

IVRIE: Invalid Message Received Interrupt Enable bit

WAKIE: Bus Wake-up Activity Interrupt Flag bit

ERRIE: Error Interrupt Enable bit

Unimplemented: Read as ‘0’

FIFOIE: FIFO Almost Full Interrupt Enable bit

RBOVIE: RX Buffer Overflow Interrupt Enable bit

RBIE: RX Buffer Interrupt Enable bit

TBIE: TX Buffer Interrupt Enable bit

DS70175D-page 192

Preliminary

PIC24H

REGISTER 18-8: CiEC: ECAN MODULE TRANSMIT/RECEIVE ERROR COUNT REGISTER

R-0

TERRCNT<7:0>

bit 15

bit 8

bit 0

R-0

RERRCNT<7:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

TERRCNT<7:0>: Transmit Error Count bits

RERRCNT<7:0>: Receive Error Count bits

Preliminary

DS70175D-page 193

PIC24H

REGISTER 18-9: CiCFG1: ECAN MODULE BAUD RATE CONFIGURATION REGISTER 1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

bit 0

R/W-0

SJW<1:0>

BRP<5:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-6

Unimplemented: Read as ‘0’

SJW<1:0>: Synchronization Jump Width bits

11= Length is 4 x TQ

10= Length is 3 x TQ

01= Length is 2 x TQ

00= Length is 1 x TQ

bit 5-0

BRP<5:0>: Baud Rate Prescaler bits

11 1111= TQ = 2 x 64 x 1/FCAN

00 0010= TA = 2 x 3 x 1/FCAN

00 0001= TA = 2 x 2 x 1/FCAN

00 0000= TQ = 2 x 1 x 1/FCAN

DS70175D-page 194

Preliminary

PIC24H

REGISTER 18-10: CiCFG2: ECAN MODULE BAUD RATE CONFIGURATION REGISTER 2

U-0

—

R/W-x

U-0

—

U-0

—

U-0

—

R/W-x

bit 8

WAKFIL

SEG2PH<2:0>

bit 15

R/W-x

SAM

R/W-x

bit 0

SEG2PHTS

SEG1PH<2:0>

PRSEG<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

Unimplemented: Read as ‘0’

WAKFIL: Select CAN bus Line Filter for Wake-up bit

1= Use CAN bus line filter for wake-up

0= CAN bus line filter is not used for wake-up

bit 13-11

bit 10-8

Unimplemented: Read as ‘0’

SEG2PH<2:0>: Phase Buffer Segment 2 bits

111= Length is 8 x TQ

000= Length is 1 x TQ

bit 7

SEG2PHTS: Phase Segment 2 Time Select bit

1= Freely programmable

0= Maximum of SEG1PH bits or Information Processing Time (IPT), whichever is greater

bit 6

SAM: Sample of the CAN bus Line bit

1= Bus line is sampled three times at the sample point

0= Bus line is sampled once at the sample point

bit 5-3

bit 2-0

SEG1PH<2:0>: Phase Buffer Segment 1 bits

111= Length is 8 x TQ

000= Length is 1 x TQ

PRSEG<2:0>: Propagation Time Segment bits

111= Length is 8 x TQ

000= Length is 1 x TQ

Preliminary

DS70175D-page 195

PIC24H

REGISTER 18-11: CiFEN1: ECAN MODULE ACCEPTANCE FILTER ENABLE REGISTER

R/W-0

FLTEN15

FLTEN14

FLTEN13

FLTEN12

FLTEN11

FLTEN10

FLTEN9

FLTEN8

bit 15

bit 8

R/W-0

R/W-1

FLTEN7

FLTEN6

FLTEN5

FLTEN4

FLTEN3

FLTEN2

FLTEN1

FLTEN0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-0

FLTENn: Enable Filter n to Accept Messages bits

1= Enable Filter n

0= Disable Filter n

REGISTER 18-12: CiBUFPNT1: ECAN MODULE FILTER 0-3 BUFFER POINTER REGISTER

R/W-0

bit 8

F3BP<3:0>

F2BP<3:0>

bit 15

R/W-0

bit 7

R/W-0 R/W-0

F1BP<3:0>

R/W-0

R/W-0 R/W-0

F0BP<3:0>

R/W-0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

bit 11-8

bit 7-4

F3BP<3:0>: RX Buffer Written when Filter 3 Hits bits

F2BP<3:0>: RX Buffer Written when Filter 2 Hits bits

F1BP<3:0>: RX Buffer Written when Filter 1 Hits bits

F0BP<3:0>: RX Buffer Written when Filter 0 Hits bits

bit 3-0

1111= Filter hits received in RX FIFO buffer

1110= Filter hits received in RX Buffer 14

....

0001= Filter hits received in RX Buffer 1

0000= Filter hits received in RX Buffer 0

DS70175D-page 196

Preliminary

PIC24H

REGISTER 18-13: CiBUFPNT2: ECAN MODULE FILTER 4-7 BUFFER POINTER REGISTER

R/W-0

F7BP<3:0>

F6BP<3:0>

bit 15

R/W-0

bit 7

bit 8

R/W-0

bit 0

R/W-0 R/W-0

F5BP<3:0>

R/W-0

R/W-0 R/W-0

F4BP<3:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

bit 11-8

bit 7-4

F7BP<3:0>: RX Buffer Written when Filter 7 Hits bits

F6BP<3:0>: RX Buffer Written when Filter 6 Hits bits

F5BP<3:0>: RX Buffer Written when Filter 5 Hits bits

F4BP<3:0>: RX Buffer Written when Filter 4 Hits bits

bit 3-0

REGISTER 18-14: CiBUFPNT3: ECAN MODULE FILTER 8-11 BUFFER POINTER REGISTER

R/W-0

F11BP<3:0>

F10BP<3:0>

bit 15

bit 8

R/W-0

bit 7

R/W-0 R/W-0

F9BP<3:0>

R/W-0

R/W-0 R/W-0

F8BP<3:0>

R/W-0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

bit 11-8

bit 7-4

F11BP<3:0>: RX Buffer Written when Filter 11 Hits bits

F10BP<3:0>: RX Buffer Written when Filter 10 Hits bits

F9BP<3:0>: RX Buffer Written when Filter 9 Hits bits

F8BP<3:0>: RX Buffer Written when Filter 8 Hits bits

bit 3-0

Preliminary

DS70175D-page 197

PIC24H

REGISTER 18-15: CiBUFPNT4: ECAN MODULE FILTER 12-15 BUFFER POINTER REGISTER

R/W-0

bit 15

R/W-0

F15BP<3:0>

F14BP<3:0>

bit 8

R/W-0

bit 7

R/W-0 R/W-0

F13BP<3:0>

R/W-0

R/W-0 R/W-0

F12BP<3:0>

R/W-0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

bit 11-8

bit 7-4

F15BP<3:0>: RX Buffer Written when Filter 15 Hits bits

F14BP<3:0>: RX Buffer Written when Filter 14 Hits bits

F13BP<3:0>: RX Buffer Written when Filter 13 Hits bits

F12BP<3:0>: RX Buffer Written when Filter 12 Hits bits

bit 3-0

DS70175D-page 198

Preliminary

PIC24H

REGISTER 18-16: CiRXFnSID: ECAN MODULE ACCEPTANCE FILTER n STANDARD IDENTIFIER

(n = 0, 1, ..., 15)

R/W-x

SID10

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

SID9

bit 15

bit 8

R/W-x

SID2

R/W-x

SID1

R/W-x

SID0

U-0

—

R/W-x

EXIDE

U-0

—

R/W-x

EID17

R/W-x

EID16

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

SID<10:0>: Standard Identifier bits

1= Message address bit SIDx must be ‘1’ to match filter

0= Message address bit SIDx must be ‘0’ to match filter

bit 4

bit 3

Unimplemented: Read as ‘0’

EXIDE: Extended Identifier Enable bit

If MIDE = 1then:

1= Match only messages with extended identifier addresses

0= Match only messages with standard identifier addresses

If MIDE = 0then:

Ignore EXIDE bit.

bit 2

Unimplemented: Read as ‘0’

bit 1-0

EID<17:16>: Extended Identifier bits

1= Message address bit EIDx must be ‘1’ to match filter

0= Message address bit EIDx must be ‘0’ to match filter

REGISTER 18-17: CiRXFnEID: ECAN MODULE ACCEPTANCE FILTER n EXTENDED IDENTIFIER

(n = 0, 1, ..., 15)

R/W-x

EID15

R/W-x

EID14

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

bit 8

bit 15

R/W-x

EID7

R/W-x

EID6

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

EID<15:0>: Extended Identifier bits

1= Message address bit EIDx must be ‘1’ to match filter

0= Message address bit EIDx must be ‘0’ to match filter

Preliminary

DS70175D-page 199

PIC24H

REGISTER 18-18: CiFMSKSEL1: ECAN MODULE FILTER 7-0 MASK SELECTION REGISTER

R/W-0

F7MSK<1:0>

F6MSK<1:0>

F5MSK<1:0>

F4MSK<1:0>

bit 15

bit 8

R/W-0 R/W-0

F3MSK<1:0>

R/W-0

F2MSK<1:0>

F1MSK<1:0>

F0MSK<1:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-12

bit 11-10

bit 9-8

F7MSK<1:0>: Mask Source for Filter 7 bit

F6MSK<1:0>: Mask Source for Filter 6 bit

F5MSK<1:0>: Mask Source for Filter 5 bit

F4MSK<1:0>: Mask Source for Filter 4 bit

F3MSK<1:0>: Mask Source for Filter 3 bit

F2MSK<1:0>: Mask Source for Filter 2 bit

F1MSK<1:0>: Mask Source for Filter 1 bit

F0MSK<1:0>: Mask Source for Filter 0 bit

11= No mask

bit 7-6

bit 5-4

bit 3-2

bit 1-0

10= Acceptance Mask 2 registers contain mask

01= Acceptance Mask 1 registers contain mask

00= Acceptance Mask 0 registers contain mask

DS70175D-page 200

Preliminary

PIC24H

REGISTER 18-19: CiRXMnSID: ECAN MODULE ACCEPTANCE FILTER MASK n STANDARD

IDENTIFIER

R/W-x

SID10

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

SID9

bit 15

bit 8

R/W-x

SID2

R/W-x

SID1

R/W-x

SID0

U-0

—

R/W-x

MIDE

U-0

—

R/W-x

EID17

R/W-x

EID16

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-5

SID<10:0>: Standard Identifier bits

1= Include bit SIDx in filter comparison

0= Bit SIDx is don’t care in filter comparison

bit 4

bit 3

Unimplemented: Read as ‘0’

MIDE: Identifier Receive Mode bit

1= Match only message types (standard or extended address) that correspond to EXIDE bit in filter

0= Match either standard or extended address message if filters match

(i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID))

bit 2

Unimplemented: Read as ‘0’

bit 1-0

EID<17:16>: Extended Identifier bits

1= Include bit EIDx in filter comparison

0= Bit EIDx is don’t care in filter comparison

REGISTER 18-20: CiRXMnEID: ECAN TECHNOLOGY ACCEPTANCE FILTER MASK n EXTENDED

IDENTIFIER

R/W-x

EID15

R/W-x

EID14

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

bit 15

bit 8

R/W-x

EID7

R/W-x

EID6

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

EID<15:0>: Extended Identifier bits

1= Include bit EIDx in filter comparison

0= Bit EIDx is don’t care in filter comparison

Preliminary

DS70175D-page 201

PIC24H

REGISTER 18-21: CiRXFUL1: ECAN MODULE RECEIVE BUFFER FULL REGISTER 1

R/C-0

RXFUL15

RXFUL14

RXFUL13

RXFUL12

RXFUL11

RXFUL10

RXFUL9

RXFUL8

bit 15

bit 8

R/C-0

RXFUL7

RXFUL6

RXFUL5

RXFUL4

RXFUL3

RXFUL2

RXFUL1

RXFUL0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-0

RXFUL<15:0>: Receive Buffer n Full bits

1= Buffer is full (set by module)

0= Buffer is empty (clear by application software)

REGISTER 18-22: CiRXFUL2: ECAN MODULE RECEIVE BUFFER FULL REGISTER 2

R/C-0

RXFUL31

RXFUL30

RXFUL29

RXFUL28

RXFUL27

RXFUL26

RXFUL25

RXFUL24

bit 15

bit 8

R/C-0

RXFUL23

RXFUL22

RXFUL21

RXFUL20

RXFUL19

RXFUL18

RXFUL17

RXFUL16

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-0

RXFUL<31:16>: Receive Buffer n Full bits

1= Buffer is full (set by module)

0= Buffer is empty (clear by application software)

DS70175D-page 202

Preliminary

PIC24H

REGISTER 18-23: CiRXOVF1: ECAN MODULE RECEIVE BUFFER OVERFLOW REGISTER 1

R/C-0

RXOVF15

RXOVF14

RXOVF13

RXOVF12

RXOVF11

RXOVF10

RXOVF9

RXOVF8

bit 15

bit 8

R/C-0

RXOVF7

RXOVF6

RXOVF5

RXOVF4

RXOVF3

RXOVF2

RXOVF1

RXOVF0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-0

RXOVF<15:0>: Receive Buffer n Overflow bits

1= Module pointed a write to a full buffer (set by module)

0= Overflow is cleared (clear by application software)

REGISTER 18-24: CiRXOVF2: ECAN MODULE RECEIVE BUFFER OVERFLOW REGISTER 2

R/C-0

RXOVF24

bit 8

RXOVF31

RXOVF30

RXOVF29

RXOVF28

RXOVF27

RXOVF26

RXOVF25

bit 15

R/C-0

RXOVF23

RXOVF22

RXOVF21

RXOVF20

RXOVF19

RXOVF18

RXOVF17

RXOVF16

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-0

RXOVF<31:16>: Receive Buffer n Overflow bits

1= Module pointed a write to a full buffer (set by module)

0= Overflow is cleared (clear by application software)

Preliminary

DS70175D-page 203

PIC24H

REGISTER 18-25: CiTRmnCON: ECAN MODULE TX/RX BUFFER m CONTROL REGISTER

(m = 0,2,4,6; n = 1,3,5,7)

R/W-0

R-0

R/W-0

TXENn

TXABTn

TXLARBn

TXERRn

TXREQn

RTRENn

TXnPRI<1:0>

bit 15

bit 8

R/W-0

R-0

R/W-0

TXENm

TXABTm⁽¹⁾TXLARBm⁽¹⁾TXERRm⁽¹⁾TXREQm

RTRENm

TXmPRI<1:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7

See Definition for Bits 7-0, Controls Buffer n

TXENm: TX/RX Buffer Selection bit

1= Buffer TRBn is a transmit buffer

0= Buffer TRBn is a receive buffer

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1-0

TXABTm: Message Aborted bit⁽¹⁾

1= Message was aborted

0= Message completed transmission successfully

TXLARBm: Message Lost Arbitration bit⁽¹⁾

1= Message lost arbitration while being sent

0= Message did not lose arbitration while being sent

TXERRm: Error Detected During Transmission bit⁽¹⁾

1= A bus error occurred while the message was being sent

0= A bus error did not occur while the message was being sent

TXREQm: Message Send Request bit

Setting this bit to ‘1’ requests sending a message. The bit will automatically clear when the message

is successfully sent. Clearing the bit to ‘0’ while set will request a message abort.

RTRENm: Auto-Remote Transmit Enable bit

1= When a remote transmit is received, TXREQ will be set

0= When a remote transmit is received, TXREQ will be unaffected

TXmPRI<1:0>: Message Transmission Priority bits

11= Highest message priority

10= High intermediate message priority

01= Low intermediate message priority

00= Lowest message priority

Note 1: This bit is cleared when TXREQ is set.

DS70175D-page 204

Preliminary

PIC24H

Note:

The buffers, SID, EID, DLC, Data Field and Receive Status registers are stored in DMA RAM. These are

not Special Function Registers.

REGISTER 18-26: CiTRBnSID: ECAN MODULE BUFFER n STANDARD IDENTIFIER

(n = 0, 1, ..., 31)

U-0

—

U-0

—

U-0

—

R/W-x

SID10

R/W-x

SID9

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

bit 15

bit 8

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

R/W-x

SID2

R/W-x

SID1

R/W-x

SID0

R/W-x

SRR

R/W-x

IDE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-2

bit 1

Unimplemented: Read as ‘0’

SID<10:0>: Standard Identifier bits

SRR: Substitute Remote Request bit

1= Message will request remote transmission

0= Normal message

bit 0

IDE: Extended Identifier bit

1= Message will transmit extended identifier

0= Message will transmit standard identifier

REGISTER 18-27: CiTRBnEID: ECAN MODULE BUFFER n EXTENDED IDENTIFIER

(n = 0, 1, ..., 31)

U-0

—

U-0

—

U-0

—

U-0

—

R/W-x

EID17

R/W-x

EID16

R/W-x

EID15

R/W-x

EID14

bit 15

bit 8

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

R/W-x

EID7

R/W-x

EID6

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

bit 11-0

Unimplemented: Read as ‘0’

EID<17:6>: Extended Identifier bits

Preliminary

DS70175D-page 205

PIC24H

REGISTER 18-28: CiTRBnDLC: ECAN MODULE BUFFER n DATA LENGTH CONTROL

(n = 0, 1, ..., 31)

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

R/W-x

RTR

R/W-x

RB1

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-x

RB0

R/W-x

DLC3

R/W-x

DLC2

R/W-x

DLC1

R/W-x

DLC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-10

bit 9

EID<5:0>: Extended Identifier bits

RTR: Remote Transmission Request bit

1= Message will request remote transmission

0= Normal message

bit 8

RB1: Reserved Bit 1

User must set this bit to ‘0’ per CAN protocol.

Unimplemented: Read as ‘0’

bit 7-5

bit 4

RB0: Reserved Bit 0

User must set this bit to ‘0’ per CAN protocol.

DLC<3:0>: Data Length Code bits

bit 3-0

REGISTER 18-29: CiTRBnDm: ECAN MODULE BUFFER n DATA FIELD BYTE m

(n = 0, 1, ..., 31; m = 0, 1, ..., 7)⁽¹⁾

R/W-x

TRBnDm7

TRBnDm6

TRBnDm5

TRBnDm4 TRBnDm3

TRBnDm2

TRBnDm1

TRBnDm0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7-0

Note 1: The Most Significant Byte contains byte (m + 1) of the buffer.

TRnDm<7:0>: Data Field Buffer ‘n’ Byte ‘m’ bits

DS70175D-page 206

Preliminary

PIC24H

REGISTER 18-30: CiTRBnSTAT: ECAN MODULE RECEIVE BUFFER n STATUS

(n = 0, 1, ..., 31)

U-0

—

U-0

—

U-0

—

R/W-x

FILHIT4

FILHIT3

FILHIT2

FILHIT1

FILHIT0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

FILHIT<4:0>: Filter Hit Code bits (only written by module for receive buffers, unused for transmit buffers)

Encodes number of filter that resulted in writing this buffer.

Unimplemented: Read as ‘0’

bit 7-0

Preliminary

DS70175D-page 207

PIC24H

NOTES:

DS70175D-page 208

Preliminary

PIC24H

19.2 A/D Initialization

19.0 10-BIT/12-BIT A/D CONVERTER

The following configuration steps should be performed.

1. Configure the A/D module:

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

a) Select port pins as analog inputs

(ADxPCFGH<15:0> or ADxPCFGL<15:0>)

b) Select voltage reference source to match

expected range on analog inputs

(ADxCON2<15:13>)

The PIC24H devices have up to 32 A/D input channels.

These devices also have up to 2 A/D converter mod-

ules (ADCx, where ‘x’ = 1 or 2), each with its own set of

Special Function Registers.

c) Select the analog conversion clock to

match desired data rate with processor

clock (ADxCON3<5:0>)

d) Determine how many S/H channels will

The AD12B bit (ADxCON1<10>) allows each of the

A/D modules to be configured by the user as either a

10-bit, 4-sample/hold A/D (default configuration) or a

12-bit, 1-sample/hold A/D.

be

used

(ADxCON2<9:8>

and

ADxPCFGH<15:0> or ADxPCFGL<15:0>)

e) Select the appropriate sample/conversion

sequence

ADxCON3<12:8>)

(ADxCON1<7:5>

and

Note:

The A/D module needs to be disabled

before modifying the AD12B bit.

f) Select how conversion results are

presented in the buffer (ADxCON1<9:8>)

19.1 Key Features

g) Turn on A/D module (ADxCON1<15>)

2. Configure A/D interrupt (if required):

a) Clear the ADxIF bit

The 10-bit A/D configuration has the following key

features:

• Successive Approximation (SAR) conversion

• Conversion speeds of up to 1.1 Msps

• Up to 32 analog input pins

b) Select A/D interrupt priority

19.3 ADC and DMA

• External voltage reference input pins

If more than one conversion result needs to be buffered

before triggering an interrupt, DMA data transfers can

be used. Both ADC1 and ADC2 can trigger a DMA data

transfer. If ADC1 or ADC2 is selected as the DMA IRQ

source, a DMA transfer occurs when the AD1IF or

AD2IF bit gets set as a result of an ADC1 or ADC2

sample conversion sequence.

• Simultaneous sampling of up to four analog input

pins

• Automatic Channel Scan mode

• Selectable conversion trigger source

• Selectable Buffer Fill modes

• Four result alignment options (signed/unsigned,

fractional/integer)

The SMPI<3:0> bits (ADxCON2<5:2>) are used to

select how often the DMA RAM buffer pointer is

incremented.

• Operation during CPU Sleep and Idle modes

The 12-bit A/D configuration supports all the above

features, except:

The ADDMABM bit (ADxCON1<12>) determines how

the conversion results are filled in the DMA RAM buffer

area being used for ADC. If this bit is set, DMA buffers

are written in the order of conversion. The module will

provide an address to the DMA channel that is the

same as the address used for the non-DMA

stand-alone buffer. If the ADDMABM bit is cleared,

then DMA buffers are written in Scatter/Gather mode.

The module will provide a scatter/gather address to the

DMA channel, based on the index of the analog input

and the size of the DMA buffer.

• In the 12-bit configuration, conversion speeds of

up to 500 ksps are supported

• There is only 1 sample/hold amplifier in the 12-bit

configuration, so simultaneous sampling of

multiple channels is not supported.

Depending on the particular device pinout, the A/D con-

verter can have up to 32 analog input pins, designated

AN0 through AN31. In addition, there are two analog

input pins for external voltage reference connections.

These voltage reference inputs may be shared with

other analog input pins. The actual number of analog

input pins and external voltage reference input config-

uration will depend on the specific device. Refer to the

device data sheet for further details.

A block diagram of the A/D converter is shown in

Figure 19-1.

Preliminary

DS70175D-page 209

PIC24H

FIGURE 19-1:

ADC1 MODULE BLOCK DIAGRAM

AVDD

AVSS

VREF+⁽¹⁾

VREF-⁽¹⁾

AN0

AN3

AN0

AN1

AN2

+

CH1⁽²⁾

CH2⁽²⁾

CH3⁽²⁾

S/H

ADC1

AN6

AN9

VREF-

-

Conversion Logic

Conversion

Result

AN1

AN4

+

S/H

AN7

AN10

VREF-

-

16-bit

ADC Output

Buffer

AN2

AN5

+

S/H

AN8

AN11

VREF-

CH1,CH2,

CH3,CH0

-

Sample/Sequence

Control

Sample

00000

00001

00010

00011

Input

Switches

Input MUX

Control

AN3

00100

00101

00110

00111

01000

01001

01010

01011

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

11110

11111

AN30

AN31

+

CH0

VREF-

AN1

S/H

-

Note 1: VREF+, VREF- inputs may be multiplexed with other analog inputs. See device data sheet for details.

2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.

DS70175D-page 210

Preliminary

PIC24H

FIGURE 19-2:

ADC2 MODULE BLOCK DIAGRAM⁽¹⁾

AVDD

AVSS

VREF+⁽²⁾

VREF-⁽²⁾

AN0

AN3

AN0

AN1

AN2

+

CH1⁽³⁾

CH2⁽³⁾

CH3⁽³⁾

S/H

ADC2

AN6

AN9

VREF-

-

Conversion Logic

Conversion

Result

AN1

AN4

+

S/H

AN7

AN10

VREF-

-

16-bit

ADC Output

Buffer

AN2

AN5

+

S/H

AN8

AN11

VREF-

CH1,CH2,

CH3,CH0

-

Sample/Sequence

Control

Sample

00000

00001

00010

00011

Input

Switches

Input MUX

Control

AN3

00100

00101

00110

00111

01000

01001

01010

01011

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

11110

11111

AN14

AN15

+

CH0

VREF-

AN1

S/H

-

Note 1: On devices with two ADC modules, AN0-AN15 can be read by either ADC1, ADC2 or both ADCs.

2: VREF+, VREF- inputs may be multiplexed with other analog inputs. See device data sheet for details.

3: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.

Preliminary

DS70175D-page 211

PIC24H

EQUATION 19-1: A/D CONVERSION CLOCK PERIOD

TAD = TCY(ADCS + 1)

TAD

– 1

ADCS =

TCY

FIGURE 19-3:

A/D TRANSFER FUNCTION (10-BIT EXAMPLE)

Output Code

11 1111 1111 (= 1023)

11 1111 1110 (= 1022)

10 0000 0011 (= 515)

10 0000 0010 (= 514)

10 0000 0001 (= 513)

10 0000 0000 (= 512)

01 1111 1111 (= 511)

01 1111 1110 (= 510)

01 1111 1101 (= 509)

00 0000 0001 (= 1)

00 0000 0000 (= 0)

VREFL

VREFH

VREFH – VREFL

1024

512 * (VREFH – VREFL)

1024

1023 * (VREFH – VREFL)

1024

VREFL +

(VINH – VINL)

FIGURE 19-4:

ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM

ADxCON3<15>

ADC Internal

RC Clock

0

1

TAD

ADxCON3<5:0>

6

ADC Conversion

Clock Multiplier

TCY

(1)

TOSC

X2

1, 2, 3, 4, 5,..., 64

1. Refer to Figure 8-2 for the derivation of FOSC when the PLL is enabled. If the PLL is not used, FOSC is equal to the clock

source frequency. Tosc = 1/Fosc.

DS70175D-page 212

Preliminary

PIC24H

REGISTER 19-1: ADxCON1: ADCx CONTROL REGISTER 1 (where x = 1 or 2)

R/W-0

ADON

U-0

—

R/W-0

U-0

—

R/W-0

ADSIDL

ADDMABM

AD12B

FORM<1:0>

bit 15

bit 8

R/W-0

U-0

—

R/W-0

ASAM

R/W-0

HC,HS

R/C-0

HC, HS

SSRC<2:0>

SIMSAM

SAMP

DONE

bit 7

bit 0

Legend:

HC = Cleared by hardware

W = Writable bit

HS = Set by hardware

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

‘1’ = Bit is set

bit 15

ADON: A/D Operating Mode bit

1= A/D converter module is operating

0= A/D converter is off

bit 14

bit 13

Unimplemented: Read as ‘0’

ADSIDL: Stop in Idle Mode bit

1= Discontinue module operation when device enters Idle mode

0= Continue module operation in Idle mode

bit 12

ADDMABM: DMA Buffer Build Mode bit

1= DMA buffers are written in the order of conversion. The module will provide an address to the

DMA channel that is the same as the address used for the non-DMA stand-alone buffer.

0= DMA buffers are written in Scatter/Gather mode. The module will provide a scatter/gather address

to the DMA channel, based on the index of the analog input and the size of the DMA buffer.

bit 11

bit 10

Unimplemented: Read as ‘0’

AD12B: 10-bit or 12-bit Operation Mode bit

1= 12-bit, 1-channel A/D operation

0= 10-bit, 4-channel A/D operation

bit 9-8

FORM<1:0>: Data Output Format bits

For 10-bit operation:

11= Signed fractional (DOUT = sddd dddd dd00 0000, where s= .NOT.d<9>)

10= Fractional (DOUT = dddd dddd dd00 0000)

01= Signed integer (DOUT = ssss sssd dddd dddd, where s= .NOT.d<9>)

00= Integer (DOUT = 0000 00dd dddd dddd)

For 12-bit operation:

11= Signed fractional (DOUT = sddd dddd dddd 0000, where s= .NOT.d<11>)

10= Fractional (DOUT = dddd dddd dddd 0000)

01= Signed Integer (DOUT = ssss sddd dddd dddd, where s= .NOT.d<11>)

00= Integer (DOUT = 0000 dddd dddd dddd)

bit 7-5

SSRC<2:0>: Sample Clock Source Select bits

111= Internal counter ends sampling and starts conversion (auto-convert)

110= Reserved

101= Reserved

100= Reserved

011= Reserved

010= GP timer (Timer3 for ADC1, Timer5 for ADC2) compare ends sampling and starts conversion

001= Active transition on INTx pin ends sampling and starts conversion

000= Clearing sample bit ends sampling and starts conversion

bit 4

Unimplemented: Read as ‘0’

Preliminary

DS70175D-page 213

PIC24H

REGISTER 19-1: ADxCON1: ADCx CONTROL REGISTER 1 (CONTINUED)(where x = 1 or 2)

bit 3

SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01or 1x)

When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’

1= Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or

Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)

0= Samples multiple channels individually in sequence

bit 2

bit 1

ASAM: A/D Sample Auto-Start bit

1= Sampling begins immediately after last conversion. SAMP bit is auto-set.

0= Sampling begins when SAMP bit is set

SAMP: A/D Sample Enable bit

1= A/D sample/hold amplifiers are sampling

0= A/D sample/hold amplifiers are holding

If ASAM = 0, software may write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.

If SSRC = 000, software may write ‘0’ to end sampling and start conversion. If SSRC ≠ 000,

automatically cleared by hardware to end sampling and start conversion.

bit 0

DONE: A/D Conversion Status bit

1= A/D conversion cycle is completed.

0= A/D conversion not started or in progress

Automatically set by hardware when A/D conversion is complete. Software may write ‘0’ to clear

DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in

progress. Automatically cleared by hardware at start of a new conversion.

DS70175D-page 214

Preliminary

PIC24H

REGISTER 19-2: ADxCON2: ADCx CONTROL REGISTER 2 (where x = 1 or 2)

R/W-0

U-0

—

U-0

—

R/W-0

VCFG<2:0>

CSCNA

CHPS<1:0>

bit 15

bit 8

R-0

U-0

—

R/W-0

BUFM

R/W-0

ALTS

BUFS

SMPI<3:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

VCFG<2:0>: Converter Voltage Reference Configuration bits

ADREF+

ADREF-

000

001

010

011

1xx

AVDD

External VREF+

AVDD

AVSS

External VREF-

AVSS

External VREF+

AVDD

bit 12-11

bit 10

Unimplemented: Read as ‘0’

CSCNA: Scan Input Selections for CH0+ during Sample A bit

1= Scan inputs

0= Do not scan inputs

bit 9-8

bit 7

CHPS<1:0>: Selects Channels Utilized bits

When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’

1x=Converts CH0, CH1, CH2 and CH3

01=Converts CH0 and CH1

00=Converts CH0

BUFS: Buffer Fill Status bit (only valid when BUFM = 1)

1= A/D is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7

0= A/D is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF

bit 6

Unimplemented: Read as ‘0’

bit 5-2

SMPI<3:0>: Selects Increment Rate for DMA Addresses bits or number of sample/conversion

operations per interrupt

1111= Increments the DMA address or generates interrupt after completion of every 16th

sample/conversion operation

1110= Increments the DMA address or generates interrupt after completion of every 15th

sample/conversion operation

• • •

0001= Increments the DMA address or generates interrupt after completion of every 2nd

sample/conversion operation

0000= Increments the DMA address or generates interrupt after completion of every

sample/conversion operation

bit 1

bit 0

BUFM: Buffer Fill Mode Select bit

1= Starts buffer filling at address 0x0 on first interrupt and 0x8 on next interrupt

0= Always starts filling buffer at address 0x0

ALTS: Alternate Input Sample Mode Select bit

1= Uses channel input selects for Sample A on first sample and Sample B on next sample

0= Always uses channel input selects for Sample A

Preliminary

DS70175D-page 215

PIC24H

REGISTER 19-3: ADxCON3: ADCx CONTROL REGISTER 3

U-0

—

U-0

—

R/W-0

bit 8

ADRC

SAMC<4:0>

bit 15

R/W-0

—

U-0

—

R/W-0

bit 0

ADCS<5:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

ADRC: A/D Conversion Clock Source bit

1= A/D internal RC clock

0= Clock derived from system clock

bit 14-13

bit 12-8

Unimplemented: Read as ‘0’

SAMC<4:0>: Auto Sample Time bits

11111= 31 TAD

• • •

00001= 1 TAD

00000= 0 TAD

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

ADCS<5:0>: A/D Conversion Clock Select bits

111111= TCY ·(ADCS<7:0> + 1) = 64 ·TCY = TAD

• • •

000010= TCY ·(ADCS<7:0> + 1) = 3 ·TCY = TAD

000001= TCY ·(ADCS<7:0> + 1) = 2 ·TCY = TAD

000000= TCY ·(ADCS<7:0> + 1) = 1 ·TCY = TAD

DS70175D-page 216

Preliminary

PIC24H

REGISTER 19-4: ADxCON4: ADCx CONTROL REGISTER 4

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

DMABL<2:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-0

Unimplemented: Read as ‘0’

DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog Input bits

111=Allocates 128 words of buffer to each analog input

110=Allocates 64 words of buffer to each analog input

101=Allocates 32 words of buffer to each analog input

100=Allocates 16 words of buffer to each analog input

011=Allocates 8 words of buffer to each analog input

010=Allocates 4 words of buffer to each analog input

001=Allocates 2 words of buffer to each analog input

000=Allocates 1 word of buffer to each analog input

Preliminary

DS70175D-page 217

PIC24H

REGISTER 19-5: ADxCHS123: ADCx INPUT CHANNEL 1, 2, 3 SELECT REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CH123NB<1:0>

CH123SB

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CH123NA<1:0>

CH123SA

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-9

Unimplemented: Read as ‘0’

CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits

When AD12B = 1, CHxNB is: U-0, Unimplemented, Read as ‘0’

11= CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11

10= CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8

0x= CH1, CH2, CH3 negative input is VREF-

bit 8

CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit

When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’

1= CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5

0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2

bit 7-3

bit 2-1

Unimplemented: Read as ‘0’

CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits

When AD12B = 1, CHxNA is: U-0, Unimplemented, Read as ‘0’

11= CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11

10= CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8

0x= CH1, CH2, CH3 negative input is VREF-

bit 0

CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit

When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’

1= CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5

0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2

DS70175D-page 218

Preliminary

PIC24H

REGISTER 19-6: ADxCHS0: ADCx INPUT CHANNEL 0 SELECT REGISTER

R/W-0

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

CH0NB

CH0SB<4:0>

bit 15

R/W-0

U-0

—

U-0

—

R/W-0

CH0NA

CH0SA<4:0>

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

CH0NB: Channel 0 Negative Input Select for Sample B bit

Same definition as bit 7.

bit 14-13

bit 12-8

Unimplemented: Read as ‘0’

CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits

Same definition as bit<4:0>.

bit 7

CH0NA: Channel 0 Negative Input Select for Sample A bit

1= Channel 0 negative input is AN1

0= Channel 0 negative input is VREF-

bit 6-5

bit 4-0

Unimplemented: Read as ‘0’

CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits

11111= Channel 0 positive input is AN31

11110= Channel 0 positive input is AN30

• • •

00010= Channel 0 positive input is AN2

00001= Channel 0 positive input is AN1

00000= Channel 0 positive input is AN0

Preliminary

DS70175D-page 219

PIC24H

REGISTER 19-7: ADxCSSH: ADCx INPUT SCAN SELECT REGISTER HIGH⁽¹⁾

R/W-0

CSS31

CSS30

CSS29

CSS28

CSS27

CSS26

CSS25

CSS24

bit 15

bit 8

R/W-0

CSS23

CSS22

CSS21

CSS20

CSS19

CSS18

CSS17

CSS16

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

CSS<31:16>: A/D Input Scan Selection bits

1= Select ANx for input scan

0= Skip ANx for input scan

Note 1: On devices without 32 analog inputs, all ADxCSSL bits may be selected by user. However, inputs

selected for scan without a corresponding input on device will convert ADREF-.

REGISTER 19-8: ADxCSSL: ADCx INPUT SCAN SELECT REGISTER LOW⁽¹⁾

R/W-0

CSS11

R/W-0

CSS9

R/W-0

CSS8

bit 8

CSS15

CSS14

CSS13

CSS12

CSS10

bit 15

R/W-0

CSS7

R/W-0

CSS6

R/W-0

CSS5

R/W-0

CSS4

R/W-0

CSS3

R/W-0

CSS2

R/W-0

CSS1

R/W-0

CSS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

CSS<15:0>: A/D Input Scan Selection bits

1= Select ANx for input scan

0= Skip ANx for input scan

Note 1: On devices without 16 analog inputs, all ADxCSSL bits may be selected by user. However, inputs

selected for scan without a corresponding input on device will convert ADREF-.

DS70175D-page 220

Preliminary

PIC24H

REGISTER 19-9: AD1PCFGH: ADC1 PORT CONFIGURATION REGISTER HIGH^(1,2)

R/W-0

PCFG31

PCFG30

PCFG29

PCFG28

PCFG27

PCFG26

PCFG25

PCFG24

bit 15

bit 8

R/W-0

PCFG23

PCFG22

PCFG21

PCFG20

PCFG19

PCFG18

PCFG17

PCFG16

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

PCFG<31:16>: A/D Port Configuration Control bits

1= Port pin in Digital mode, port read input enabled, A/D input multiplexor connected to AVSS

0= Port pin in Analog mode, port read input disabled, A/D samples pin voltage

Note 1: On devices without 32 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on

ports without a corresponding input on device.

2: ADC2 only supports analog inputs AN0-AN15; therefore, no ADC2 high port Configuration register exists.

REGISTER 19-10: ADxPCFGL: ADCx PORT CONFIGURATION REGISTER LOW^(1,2)

R/W-0

PCFG15

PCFG14

PCFG13

PCFG12

PCFG11

PCFG10

PCFG9

PCFG8

bit 15

bit 8

R/W-0

PCFG7

PCFG6

PCFG5

PCFG4

PCFG3

PCFG2

PCFG1

PCFG0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

PCFG<15:0>: A/D Port Configuration Control bits

1= Port pin in Digital mode, port read input enabled, A/D input multiplexor connected to AVSS

0= Port pin in Analog mode, port read input disabled, A/D samples pin voltage

Note 1: On devices without 16 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on

ports without a corresponding input on device.

2: On devices with 2 analog-to-digital modules, both AD1PCFGL and AD2PCFGL will affect the configuration

of port pins multiplexed with AN0-AN15.

Preliminary

DS70175D-page 221

PIC24H

NOTES:

DS70175D-page 222

Preliminary

PIC24H

The device Configuration register map is shown in

Table 20-1.

20.0 SPECIAL FEATURES

Note:

This data sheet summarizes the features

The individual Configuration bit descriptions for the

FBS, FSS, FGS, FOSCSEL, FOSC, FWDT and FPOR

Configuration registers are shown in Table 20-1.

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

Note that address 0xF80000 is beyond the user program

memory space. In fact, it belongs to the configuration

memory space (0x800000-0xFFFFFF), which can only

be accessed using table reads and table writes.

PIC24H devices include several features intended to

maximize application flexibility and reliability, and mini-

mize cost through elimination of external components.

These are:

The upper byte of all device Configuration registers

should always be ‘1111 1111’. This makes them

appear to be NOPinstructions in the remote event that

their locations are ever executed by accident. Since

Configuration bits are not implemented in the

corresponding locations, writing ‘1’s to these locations

has no effect on device operation.

• Flexible Configuration

• Watchdog Timer (WDT)

• Code Protection and CodeGuard™ Security

• JTAG Boundary Scan Interface

To prevent inadvertent configuration changes during

code execution, all programmable Configuration bits

are write-once. After a bit is initially programmed during

a power cycle, it cannot be written to again. Changing

a device configuration requires that power to the device

be cycled.

• In-Circuit Serial Programming™ (ICSP™)

programming capability

• In-Circuit Emulation

20.1 Configuration Bits

The Configuration bits can be programmed (read as

‘0’), or left unprogrammed (read as ‘1’), to select vari-

ous device configurations. These bits are mapped

starting at program memory location 0xF80000.

TABLE 20-1: DEVICE CONFIGURATION REGISTER MAP

Address

Name

Bit 7

RBS<1:0>

RSS<1:0>

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

—

BSS<2:0>

SSS<2:0>

BWRP

SWRP

GWRP

0xF80000 FBS

0xF80002 FSS

—

0xF80004 FGS

—

GSS<1:0>

FNOSC<2:0>

0xF80006 FOSCSEL

0xF80008 FOSC

0xF8000A FWDT

0xF8000C FPOR

0xF8000E RESERVED3

0xF80010 FUID0

0xF80012 FUID1

0xF80014 FUID2

0xF80016 FUID3

IESO

TEMP

—

FCKSM<1:0>

FWDTEN WINDIS

Reserved⁽²⁾

OSCIOFNC POSCMD<1:0>

WDTPOST<3:0>

—

WDTPRE

—

FPWRT<2:0>

Reserved

User Unit ID Byte 0

User Unit ID Byte 1

User Unit ID Byte 2

User Unit ID Byte 3

Note 1: This reserved bit is a read-only copy of the GCP bit.

2: Reserved bits are read as ‘1’ and must be programmed as ‘1’.

Preliminary

DS70175D-page 223

PIC24H

TABLE 20-2: PIC24H CONFIGURATION BITS DESCRIPTION

Bit Field

Register

Description

BWRP

FBS

Boot Segment Program Flash Write Protection

1= Boot segment may be written

0= Boot segment is write-protected

BSS<2:0>

FBS

Boot Segment Program Flash Code Protection Size

X11= No Boot program Flash segment

Boot space is 1K IW less VS

110= Standard security; boot program Flash segment starts at End of

VS, ends at 0x0007FE

010= High security; boot program Flash segment starts at End of VS,

ends at 0x0007FE

Boot space is 4K IW less VS

101= Standard security; boot program Flash segment starts at End of

VS, ends at 0x001FFE

001= High security; boot program Flash segment starts at End of VS,

ends at 0x001FFE

Boot space is 8K IW less VS

100= Standard security; boot program Flash segment starts at End of

VS, ends at 0x003FFE

000= High security; boot program Flash segment starts at End of VS,

ends at 0x003FFE

RBS<1:0>

SWRP

FBS

FSS

Boot Segment RAM Code Protection

10= No Boot RAM defined

10= Boot RAM is 128 Bytes

01= Boot RAM is 256 Bytes

00 = Boot RAM is 1024 Bytes

Secure Segment Program Flash Write Protection

1= Secure segment may be written

0= Secure segment is write-protected.

DS70175D-page 224

Preliminary

PIC24H

TABLE 20-2: PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED)

Bit Field

Register

Description

SSS<2:0>

FSS

Secure Segment Program Flash Code Protection Size

(FOR 128K and 256K DEVICES)

X11= No Secure program Flash segment

Secure space is 8K IW less BS

110= Standard security; secure program Flash segment starts at End

of BS, ends at 0x003FFE

010= High security; secure program Flash segment starts at End of

BS, ends at 0x003FFE

Secure space is 16K IW less BS

101= Standard security; secure program Flash segment starts at End

of BS, ends at 0x007FFE

001= High security; secure program Flash segment starts at End of

BS, ends at 0x007FFE

Secure space is 32K IW less BS

100= Standard security; secure program Flash segment starts at End

of BS, ends at 0x00FFFE

000= High security; secure program Flash segment starts at End of

BS, ends at 0x00FFFE

(FOR 64K DEVICES)

X11= No Secure program Flash segment

Secure space is 4K IW less BS

110= Standard security; secure program Flash segment starts at End

of BS, ends at 0x001FFE

010= High security; secure program Flash segment starts at End of

BS, ends at 0x001FFE

Secure space is 8K IW less BS

101= Standard security; secure program Flash segment starts at End

of BS, ends at 0x003FFE

001= High security; secure program Flash segment starts at End of

BS, ends at 0x003FFE

Secure space is 16K IW less BS

100= Standard security; secure program Flash segment starts at End

of BS, ends at 0x007FFE

000= High security; secure program Flash segment starts at End of

BS, ends at 0x007FFE

RSS<1:0>

GSS<1:0>

FSS

FGS

Secure Segment RAM Code Protection

10= No Secure RAM defined

10= Secure RAM is 256 Bytes less BS RAM

01= Secure RAM is 2048 Bytes less BS RAM

00= Secure RAM is 4096 Bytes less BS RAM

General Segment Code-Protect bit

11= User program memory is not code-protected

10= Standard Security; general program Flash segment starts at End

of SS, ends at EOM

0x= High Security; general program Flash segment starts at End of

ESS, ends at EOM

Preliminary

DS70175D-page 225

PIC24H

TABLE 20-2: PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED)

Bit Field

Register

Description

GWRP

FGS

General Segment Write-Protect bit

1= User program memory is not write-protected

0= User program memory is write-protected

IESO

FOSCSEL

Internal External Start-up Option bit

1= Start-up device with FRC, then automatically switch to the

user-selected oscillator source when ready

0= Start-up device with user-selected oscillator source

TEMP

FOSCSEL

Temperature Protection Enable bit

1= Temperature protection disabled

0= Temperature protection enabled

FNOSC<2:0>

Initial Oscillator Source Selection bits

111= Internal Fast RC (FRC) oscillator with postscaler

110= Reserved

101= LPRC oscillator

100= Secondary (LP) oscillator

011= Primary (XT, HS, EC) oscillator with PLL

010= Primary (XT, HS, EC) oscillator

001= Internal Fast RC (FRC) oscillator with PLL

000= FRC oscillator

FCKSM<1:0>

FOSC

Clock Switching Mode bits

1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled

01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled

00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled

OSCIOFNC

FOSC

OSC2 Pin Function bit (except in XT and HS modes)

1= OSC2 is clock output

0= OSC2 is general purpose digital I/O pin

POSCMD<1:0>

Primary Oscillator Mode Select bits

11= Primary oscillator disabled

10= HS Crystal Oscillator mode

01= XT Crystal Oscillator mode

00= EC (External Clock) mode

FWDTEN

FWDT

Watchdog Timer Enable bit

1= Watchdog Timer always enabled (LPRC oscillator cannot be disabled.

Clearing the SWDTEN bit in the RCON register will have no effect.)

0= Watchdog Timer enabled/disabled by user software (LPRC can be

disabled by clearing the SWDTEN bit in the RCON register)

WINDIS

WDTPRE

WDTPOST

FWDT

Watchdog Timer Window Enable bit

1= Watchdog Timer in Non-Window mode

0= Watchdog Timer in Window mode

Watchdog Timer Prescaler bit

1= 1:128

0= 1:32

Watchdog Timer Postscaler bits

1111= 1:32,768

1110= 1:16,384

.

0001= 1:2

0000= 1:1

DS70175D-page 226

Preliminary

PIC24H

TABLE 20-2: PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED)

Bit Field

Register

Description

FPWRT<2:0>

FPOR

Power-on Reset Timer Value Select bits

111= PWRT = 128 ms

110= PWRT = 64 ms

101= PWRT = 32 ms

100= PWRT = 16 ms

011= PWRT = 8 ms

010= PWRT = 4 ms

001= PWRT = 2 ms

000= PWRT = Disabled

Reserved

—

FPOR,

RESERVED3

Reserved (read as ‘1’ and must be programmed as ‘1’)

FGS, FOSCSEL, Unimplemented (read as ‘0’, write as ‘0’)

FOSC, FWDT,

FPOR

FIGURE 20-1:

CONNECTIONS FOR THE

ON-CHIP VOLTAGE

REGULATOR⁽¹⁾

20.2 On-Chip Voltage Regulator

All of the PIC24H devices power their core digital logic

at a nominal 2.5V. This may create an issue for designs

that are required to operate at a higher typical voltage,

such as 3.3V. To simplify system design, all devices in

the PIC24H family incorporate an on-chip regulator that

allows the device to run its core logic from VDD.

3.3V

PIC24H

The regulator provides power to the core from the other

VDD pins. When the regulator is enabled, a low-ESR

(less than 5 ohms) capacitor (such as tantalum or

ceramic) must be connected to the VDDCORE/VCAP pin

(Figure 20-1). This helps to maintain the stability of the

regulator. The recommended value for the filter capac-

itor is provided in TABLE 23-12: “Internal Voltage

Regulator Specifications” located in Section 23.1

“DC Characteristics”.

VDD

VDDCORE/VCAP

VSS

10 μF

Note 1: These are typical operating voltages. Refer

to TABLE 23-12: “Internal Voltage Regu-

lator Specifications” located in

On a POR, it takes approximately 20 μs for the on-chip

voltage regulator to generate an output voltage. During

this time, designated as TSTARTUP, code execution is

disabled. TSTARTUP is applied every time the device

resumes operation after any power-down.

Section 23.1 “DC Characteristics” for the

full operating ranges of VDD and VDDCORE.

Preliminary

DS70175D-page 227

PIC24H

If the WDT is enabled, it will continue to run during Sleep

or Idle modes. When the WDT time-out occurs, the

device will wake the device and code execution will con-

tinue from where the PWRSAVinstruction was executed.

The corresponding SLEEP or IDLE bits (RCON<3,2>)

will need to be cleared in software after the device wakes

up.

20.3 Watchdog Timer (WDT)

For PIC24H devices, the WDT is driven by the LPRC

oscillator. When the WDT is enabled, the clock source

is also enabled.

The nominal WDT clock source from LPRC is 32 kHz.

This feeds a prescaler than can be configured for either

5-bit (divide-by-32) or 7-bit (divide-by-128) operation.

The prescaler is set by the WDTPRE Configuration bit.

With a 32 kHz input, the prescaler yields a nominal

WDT time-out period (TWDT) of 1 ms in 5-bit mode, or

4 ms in 7-bit mode.

The WDT flag bit, WDTO (RCON<4>), is not automatically

cleared following a WDT time-out. To detect subsequent

WDT events, the flag must be cleared in software.

Note:

The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the WDTPOST<3:0>

Configuration bits (FWDT<3:0>) which allow the selec-

tion of a total of 16 settings, from 1:1 to 1:32,768. Using

the prescaler and postscaler, time-out periods ranging

from 1 ms to 131 seconds can be achieved.

The WDT is enabled or disabled by the FWDTEN

Configuration bit in the FWDT Configuration register.

When the FWDTEN Configuration bit is set, the WDT is

always enabled.

The WDT can be optionally controlled in software when

the FWDTEN Configuration bit has been programmed

to ‘0’. The WDT is enabled in software by setting the

SWDTEN control bit (RCON<5>). The SWDTEN con-

trol bit is cleared on any device Reset. The software

WDT option allows the user to enable the WDT for crit-

ical code segments and disable the WDT during

non-critical segments for maximum power savings.

The WDT, prescaler and postscaler are reset:

• On any device Reset

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSC bits) or by hardware

(i.e., Fail-Safe Clock Monitor)

• When a PWRSAVinstruction is executed

(i.e., Sleep or Idle mode is entered)

Note:

If the WINDIS bit (FWDT<6>) is cleared, the

CLRWDTinstruction should be executed by

the application software only during the last

1/4 of the WDT period. This CLRWDT win-

dow can be determined by using a timer. If

a CLRWDT instruction is executed before

this window, a WDT Reset occurs.

• When the device exits Sleep or Idle mode to

resume normal operation

• By a CLRWDTinstruction during normal execution

FIGURE 20-2:

WDT BLOCK DIAGRAM

SWDTEN

FWDTEN

LPRC Control

Wake from Sleep

WDTPRE

Prescaler

WDTPOST<3:0>

WDT

Counter

WDT Overflow

Reset

Postscaler

LPRC Input

32.768 kHz

1 ms/4 ms

All Device Resets

Transition to

New Clock Source

Exit Sleep or

Idle Mode

CLRWDTInstr.

PWRSAVInstr.

Sleep or Idle Mode

DS70175D-page 228

Preliminary

PIC24H

20.4 JTAG Interface

20.7 In-Circuit Debugger

PIC24H devices implement a JTAG interface, which

supports boundary scan device testing, as well as

in-circuit programming. Detailed information on the

interface will be provided in future revisions of the

document.

When MPLAB^®ICD 2 is selected as a debugger, the

in-circuit debugging functionality is enabled. This func-

tion allows simple debugging functions when used with

MPLAB IDE. Debugging functionality is controlled

through the EMUCx (Emulation/Debug Clock) and

EMUDx (Emulation/Debug Data) pin functions.

20.5 Code Protection and

CodeGuard™ Security

Any 1 out of 3 pairs of debugging clock/data pins may

be used:

• PGC1/EMUC1 and PGD1/EMUD1

• PGC2/EMUC2 and PGD2/EMUD2

• PGC3/EMUC3 and PGD3/EMUD3

The PIC24H product families offer advanced imple-

mentation of CodeGuard™ Security. CodeGuard

Security enables multiple parties to securely share

resources (memory, interrupts and peripherals) on a

single chip. This feature helps protect individual

Intellectual Property in collaborative system designs.

To use the in-circuit debugger function of the device,

the design must implement ICSP programming capa-

bility connections to MCLR, VDD, VSS, PGC, PGD and

the EMUDx/EMUCx pin pair. In addition, when the fea-

ture is enabled, some of the resources are not available

for general use. These resources include the first 80

bytes of data RAM and two I/O pins.

When coupled with software encryption libraries,

CodeGuard Security can be used to securely update

Flash even when multiple IP are resident on the single

chip. The code protection features vary depending on

the actual PIC24H implemented. The following

sections provide an overview these features.

The code protection features are controlled by the

Configuration registers: FBS, FSS and FGS.

Note:

Refer to CodeGuard Security Reference

Manual (DS70180) for further information

on usage, configuration and operation of

CodeGuard Security.

20.6 In-Circuit Serial Programming

Programming Capability

PIC24H family digital signal controllers can be serially

programmed while in the end application circuit. This is

simply done with two lines for clock and data and three

other lines for power, ground and the programming

sequence. This allows customers to manufacture

boards with unprogrammed devices and then program

the digital signal controller just before shipping the

product. This also allows the most recent firmware or a

custom firmware, to be programmed. Please refer to

the “dsPIC33F Flash Programming Specification”

(DS70152) document for details about ICSP

programming capability.

Any 1 out of 3 pairs of programming clock/data pins

may be used:

• PGC1/EMUC1 and PGD1/EMUD1

• PGC2/EMUC2 and PGD2/EMUD2

• PGC3/EMUC3 and PGD3/EMUD3

Preliminary

DS70175D-page 229

PIC24H

NOTES:

DS70175D-page 230

Preliminary

PIC24H

Most bit-oriented instructions (including simple

rotate/shift instructions) have two operands:

21.0 INSTRUCTION SET SUMMARY

Note:

This data sheet summarizes the features

of this group of PIC24H devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “dsPIC30F

Family Reference Manual” (DS70046).

• The W register (with or without an address

modifier) or file register (specified by the value of

‘Ws’ or ‘f’)

• The bit in the W register or file register

(specified by a literal value or indirectly by the

contents of register ‘Wb’)

The PIC24H instruction set is identical to that of the

PIC24F, and is a subset of the dsPIC30F/33F

instruction set.

The literal instructions that involve data movement may

use some of the following operands:

• A literal value to be loaded into a W register or file

register (specified by the value of ‘k’)

Most instructions are a single program memory word

(24 bits). Only three instructions require two program

memory locations.

• The W register or file register where the literal

value is to be loaded (specified by ‘Wb’ or ‘f’)

Each single-word instruction is a 24-bit word, divided

into an 8-bit opcode, which specifies the instruction

type and one or more operands, which further specify

the operation of the instruction.

However, literal instructions that involve arithmetic or

logical operations use some of the following operands:

• The first source operand which is a register ‘Wb’

without any address modifier

The instruction set is highly orthogonal and is grouped

into five basic categories:

• The second source operand which is a literal

value

• Word or byte-oriented operations

• Bit-oriented operations

• Literal operations

• The destination of the result (only if not the same

as the first source operand) which is typically a

register ‘Wd’ with or without an address modifier

• DSP operations

The control instructions may use some of the following

operands:

• Control operations

Table 21-1 shows the general symbols used in

describing the instructions.

• A program memory address

• The mode of the table read and table write

instructions

The PIC24H instruction set summary in Table 21-2 lists

all the instructions, along with the status flags affected

by each instruction.

Most word or byte-oriented W register instructions

(including barrel shift instructions) have three

operands:

• The first source operand which is typically a

register ‘Wb’ without any address modifier

• The second source operand which is typically a

register ‘Ws’ with or without an address modifier

• The destination of the result which is typically a

register ‘Wd’ with or without an address modifier

However, word or byte-oriented file register instruc-

tions have two operands:

• The file register specified by the value ‘f’

• The destination, which could either be the file

register ‘f’ or the W0 register, which is denoted as

‘WREG’

Preliminary

DS70175D-page 231

PIC24H

All instructions are a single word, except for certain

double word instructions, which were made double

word instructions so that all the required information is

available in these 48 bits. In the second word, the

8 MSbs are ‘0’s. If this second word is executed as an

instruction (by itself), it will execute as a NOP.

reads and writes and RETURN/RETFIE instructions,

which are single-word instructions but take two or three

cycles. Certain instructions that involve skipping over the

subsequent instruction require either two or three cycles

if the skip is performed, depending on whether the

instruction being skipped is a single-word or double word

instruction. Moreover, double word moves require two

cycles. The double word instructions execute in two

instruction cycles.

Most single-word instructions are executed in a single

instruction cycle, unless a conditional test is true, or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles with the additional instruction cycle(s) executed

as a NOP. Notable exceptions are the BRA (uncondi-

tional/computed branch), indirect CALL/GOTO, all table

Note:

For more details on the instruction set,

refer to the “dsPIC30F/33F Programmer’s

Reference Manual” (DS70157).

TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field

Description

#text

(text)

[text]

{ }

Means literal defined by “text”

Means “content of text”

Means “the location addressed by text”

Optional field or operation

Register bit field

<n:m>

.b

Byte mode selection

.d

Double Word mode selection

Shadow register select

.S

.w

Word mode selection (default)

bit4

4-bit bit selection field (used in word addressed instructions) ∈ {0...15}

MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero

Absolute address, label or expression (resolved by the linker)

File register address ∈ {0x0000...0x1FFF}

1-bit unsigned literal ∈ {0,1}

C, DC, N, OV, Z

Expr

f

lit1

lit4

4-bit unsigned literal ∈ {0...15}

lit5

5-bit unsigned literal ∈ {0...31}

lit8

8-bit unsigned literal ∈ {0...255}

lit10

lit14

lit16

lit23

None

PC

10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode

14-bit unsigned literal ∈ {0...16384}

16-bit unsigned literal ∈ {0...65535}

23-bit unsigned literal ∈ {0...8388608}; LSB must be ‘0’

Field does not require an entry, may be blank

Program Counter

Slit10

Slit16

Slit6

Wb

10-bit signed literal ∈ {-512...511}

16-bit signed literal ∈ {-32768...32767}

6-bit signed literal ∈ {-16...16}

Base W register ∈ {W0..W15}

Wd

Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }

Wdo

Destination W register ∈

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }

Wm,Wn

Dividend, Divisor working register pair (direct addressing)

Wm*Wm

Multiplicand and Multiplier working register pair for Square instructions ∈

{W4 * W4,W5 * W5,W6 * W6,W7 * W7}

Wm*Wn

Wn

Multiplicand and Multiplier working register pair for DSP instructions ∈

{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}

One of 16 working registers ∈ {W0..W15}

DS70175D-page 232

Preliminary

PIC24H

TABLE 21-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)

Field

Description

Wnd

Wns

WREG

Ws

One of 16 destination working registers ∈ {W0..W15}

One of 16 source working registers ∈ {W0..W15}

W0 (working register used in file register instructions)

Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }

Wso

Source W register ∈

{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

Preliminary

DS70175D-page 233

PIC24H

TABLE 21-2: INSTRUCTION SET OVERVIEW

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

ADD

ADDC

AND

ASR

f

f = f + WREG

1

C,DC,N,OV,Z

N,Z

1

ADD

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f + WREG

1

Wd = lit10 + Wd

1

Wd = Wb + Ws

1

Wd = Wb + lit5

1

2

3

4

ADDC

f = f + WREG + (C)

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f + WREG + (C)

Wd = lit10 + Wd + (C)

Wd = Wb + Ws + (C)

Wd = Wb + lit5 + (C)

f = f .AND. WREG

1

AND

1

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f .AND. WREG

Wd = lit10 .AND. Wd

Wd = Wb .AND. Ws

Wd = Wb .AND. lit5

1

N,Z

1

N,Z

1

N,Z

1

N,Z

ASR

f = Arithmetic Right Shift f

WREG = Arithmetic Right Shift f

Wd = Arithmetic Right Shift Ws

Wnd = Arithmetic Right Shift Wb by Wns

Wnd = Arithmetic Right Shift Wb by lit5

Bit Clear f

1

C,N,OV,Z

N,Z

ASR

f,WREG

Ws,Wd

1

ASR

1

ASR

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,#bit4

1

ASR

1

N,Z

5

6

BCLR

BRA

BCLR

BRA

1

None

Ws,#bit4

C,Expr

Bit Clear Ws

1

None

Branch if Carry

1 (2)

2

None

BRA

GE,Expr

GEU,Expr

GT,Expr

GTU,Expr

LE,Expr

LEU,Expr

LT,Expr

LTU,Expr

N,Expr

Branch if greater than or equal

Branch if unsigned greater than or equal

Branch if greater than

Branch if unsigned greater than

Branch if less than or equal

Branch if unsigned less than or equal

Branch if less than

None

BRA

None

BRA

None

BRA

None

BRA

None

BRA

None

BRA

None

BRA

Branch if unsigned less than

Branch if Negative

None

BRA

None

BRA

NC,Expr

NN,Expr

NZ,Expr

Expr

Branch if Not Carry

None

BRA

Branch if Not Negative

Branch if Not Zero

None

BRA

None

BRA

Branch Unconditionally

Branch if Zero

None

BRA

Z,Expr

1 (2)

2

None

BRA

Wn

Computed Branch

None

7

BSET

BSW

BTG

BSET

BSW.C

BSW.Z

BTG

f,#bit4

Bit Set f

1

None

Ws,#bit4

Ws,Wb

Bit Set Ws

1

None

8

Write C bit to Ws<Wb>

Write Z bit to Ws<Wb>

Bit Toggle f

1

None

Ws,Wb

1

None

9

f,#bit4

1

None

BTG

Ws,#bit4

f,#bit4

Bit Toggle Ws

1

None

10

BTSC

Bit Test f, Skip if Clear

1

None

(2 or 3)

BTSC

BTSS

Ws,#bit4

f,#bit4

Bit Test Ws, Skip if Clear

Bit Test f, Skip if Set

1

None

(2 or 3)

11

BTSS

1

(2 or 3)

Ws,#bit4

Bit Test Ws, Skip if Set

1

(2 or 3)

DS70175D-page 234

Preliminary

PIC24H

TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

12

BTST

f,#bit4

Bit Test f

1

2

1

2

1

Z

BTST.C

BTST.Z

BTST.C

BTST.Z

BTSTS

Ws,#bit4

Ws,Wb

f,#bit4

Bit Test Ws to C

Bit Test Ws to Z

C

Z

Bit Test Ws<Wb> to C

Bit Test Ws<Wb> to Z

Bit Test then Set f

Bit Test Ws to C, then Set

Bit Test Ws to Z, then Set

Call subroutine

C

Z

13

BTSTS

BTSTS.C Ws,#bit4

BTSTS.Z Ws,#bit4

C

Z

14

15

CALL

CLR

CALL

CLR

lit23

Wn

f

None

WDTO,Sleep

N,Z

Call indirect subroutine

f = 0x0000

CLR

WREG

Ws

WREG = 0x0000

Ws = 0x0000

CLR

16

17

CLRWDT

COM

CLRWDT

COM

Clear Watchdog Timer

f = f

f

f,WREG

WREG = f

N,Z

COM

CP

Ws,Wd

Wd = Ws

1

N,Z

18

CP

f

Compare f with WREG

C,DC,N,OV,Z

CP

Wb,#lit5

Wb,Ws

f

Compare Wb with lit5

CP

Compare Wb with Ws (Wb – Ws)

Compare f with 0x0000

19

20

CP0

CPB

CP0

CPB

Ws

Compare Ws with 0x0000

Compare f with WREG, with Borrow

Compare Wb with lit5, with Borrow

f

Wb,#lit5

Wb,Ws

Compare Wb with Ws, with Borrow

(Wb – Ws – C)

21

22

23

24

CPSEQ

CPSGT

CPSLT

CPSNE

CPSEQ

CPSGT

CPSLT

CPSNE

Wb, Wn

Compare Wb with Wn, skip if =

Compare Wb with Wn, skip if >

Compare Wb with Wn, skip if <

Compare Wb with Wn, skip if ≠

1

None

(2 or 3)

1

(2 or 3)

1

(2 or 3)

1

(2 or 3)

25

26

DAW

DEC

DAW

DEC

Wn

Wn = decimal adjust Wn

f = f – 1

1

C

f

C,DC,N,OV,Z

None

DEC

f,WREG

Ws,Wd

f

WREG = f – 1

DEC

Wd = Ws – 1

27

DEC2

DISI

f = f – 2

f,WREG

Ws,Wd

#lit14

WREG = f – 2

Wd = Ws – 2

28

29

DISI

DIV

Disable Interrupts for k instruction cycles

DIV.S

DIV.SD

DIV.U

DIV.UD

EXCH

FBCL

FF1L

Wm,Wn

Wns,Wnd

Ws,Wnd

Expr

Signed 16/16-bit Integer Divide

Signed 32/16-bit Integer Divide

Unsigned 16/16-bit Integer Divide

Unsigned 32/16-bit Integer Divide

Swap Wns with Wnd

1

2

1

18

1

N,Z,C,OV

None

30

31

32

33

34

EXCH

FBCL

FF1L

Find Bit Change from Left (MSb) Side

Find First One from Left (MSb) Side

Find First One from Right (LSb) Side

Go to address

1

C

1

C

FF1R

GOTO

FF1R

1

C

GOTO

2

None

Wn

Go to indirect

2

None

Preliminary

DS70175D-page 235

PIC24H

TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

35

INC

f

f = f + 1

1

2

1

C,DC,N,OV,Z

N,Z

INC

f,WREG

Ws,Wd

f

WREG = f + 1

Wd = Ws + 1

f = f + 2

INC

36

37

INC2

IOR

INC2

IOR

f,WREG

Ws,Wd

f

WREG = f + 2

Wd = Ws + 2

f = f .IOR. WREG

IOR

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

#lit14

WREG = f .IOR. WREG

Wd = lit10 .IOR. Wd

N,Z

IOR

N,Z

IOR

Wd = Wb .IOR. Ws

N,Z

IOR

Wd = Wb .IOR. lit5

N,Z

38

39

LNK

LSR

LNK

Link Frame Pointer

None

LSR

f

f = Logical Right Shift f

C,N,OV,Z

N,Z

LSR

f,WREG

Ws,Wd

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,Wn

WREG = Logical Right Shift f

Wd = Logical Right Shift Ws

Wnd = Logical Right Shift Wb by Wns

Wnd = Logical Right Shift Wb by lit5

Move f to Wn

LSR

N,Z

40

MOV

MOV.b

MOV

MOV.D

MUL.SS

MUL.SU

MUL.US

None

f

Move f to f

N,Z

f,WREG

#lit16,Wn

#lit8,Wn

Wn,f

Move f to WREG

N,Z

Move 16-bit literal to Wn

Move 8-bit literal to Wn

None

Move Wn to f

None

Wso,Wdo

WREG,f

Wns,Wd

Ws,Wnd

Wb,Ws,Wnd

Move Ws to Wd

None

Move WREG to f

N,Z

Move Double from W(ns):W(ns + 1) to Wd

Move Double from Ws to W(nd + 1):W(nd)

{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)

{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)

{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)

None

41

MUL

None

MUL.UU Wb,Ws,Wnd

{Wnd + 1, Wnd} = unsigned(Wb) *

unsigned(Ws)

None

MUL.SU

Wb,#lit5,Wnd

{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)

1

None

MUL.UU Wb,#lit5,Wnd

{Wnd + 1, Wnd} = unsigned(Wb) *

unsigned(lit5)

MUL

NEG

f

W3:W2 = f * WREG

f = f + 1

1

None

42

NEG

f

C,DC,N,OV,Z

f,WREG

Ws,Wd

WREG = f + 1

NEG

Wd = Ws + 1

1

2

C,DC,N,OV,Z

None

43

44

NOP

POP

NOP

No Operation

NOPR

POP

No Operation

None

f

Pop f from Top-of-Stack (TOS)

Pop from Top-of-Stack (TOS) to Wdo

None

POP

Wdo

Wnd

None

POP.D

Pop from Top-of-Stack (TOS) to

W(nd):W(nd + 1)

None

POP.S

PUSH

Pop Shadow Registers

1

2

All

45

46

PUSH

f

Push f to Top-of-Stack (TOS)

Push Wso to Top-of-Stack (TOS)

None

PUSH

Wso

Wns

PUSH.D

Push W(ns):W(ns + 1) to Top-of-Stack

(TOS)

PUSH.S

Push Shadow Registers

1

None

PWRSAV

PWRSAV #lit1

Go into Sleep or Idle mode

WDTO,Sleep

DS70175D-page 236

Preliminary

PIC24H

TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

47

RCALL

Expr

Wn

Relative Call

1

2

None

Computed Call

48

REPEAT

REPEAT #lit14

REPEAT Wn

RESET

Repeat Next Instruction lit14 + 1 times

Repeat Next Instruction (Wn) + 1 times

Software device Reset

1

None

1

None

49

50

51

52

53

RESET

RETFIE

RETLW

RETURN

RLC

1

None

RETFIE

Return from interrupt

3 (2)

1

None

RETLW

RETURN

RLC

#lit10,Wn

Return with literal in Wn

Return from Subroutine

f = Rotate Left through Carry f

WREG = Rotate Left through Carry f

Wd = Rotate Left through Carry Ws

f = Rotate Left (No Carry) f

WREG = Rotate Left (No Carry) f

Wd = Rotate Left (No Carry) Ws

f = Rotate Right through Carry f

WREG = Rotate Right through Carry f

Wd = Rotate Right through Carry Ws

f = Rotate Right (No Carry) f

WREG = Rotate Right (No Carry) f

Wd = Rotate Right (No Carry) Ws

Wnd = sign-extended Ws

f = 0xFFFF

None

f

C,N,Z

RLC

f,WREG

Ws,Wd

f

1

C,N,Z

RLC

1

C,N,Z

54

55

56

RLNC

RRC

RLNC

RRC

RRNC

SE

1

N,Z

f,WREG

Ws,Wd

f

1

N,Z

1

N,Z

1

C,N,Z

f,WREG

Ws,Wd

f

1

C,N,Z

1

C,N,Z

RRNC

1

N,Z

f,WREG

Ws,Wd

Ws,Wnd

f

1

N,Z

1

N,Z

57

58

SE

1

C,N,Z

SETM

SL

1

None

WREG

Ws

WREG = 0xFFFF

1

None

Ws = 0xFFFF

1

None

59

60

61

SL

f

f = Left Shift f

1

C,N,OV,Z

N,Z

SL

f,WREG

Ws,Wd

Wb,Wns,Wnd

Wb,#lit5,Wnd

f

WREG = Left Shift f

1

SL

Wd = Left Shift Ws

1

SL

Wnd = Left Shift Wb by Wns

Wnd = Left Shift Wb by lit5

f = f – WREG

1

SL

1

N,Z

SUB

SUBB

SUB

1

C,DC,N,OV,Z

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

WREG = f – WREG

1

Wn = Wn – lit10

1

Wd = Wb – Ws

1

Wd = Wb – lit5

1

SUBB

f

f = f – WREG – (C)

1

C,DC,N,OV,Z

f,WREG

#lit10,Wn

WREG = f – WREG – (C)

Wn = Wn – lit10 – (C)

SUBB

SUBR

SUBBR

Wb,Ws,Wd

Wb,#lit5,Wd

f

Wd = Wb – Ws – (C)

Wd = Wb – lit5 – (C)

f = WREG – f

1

C,DC,N,OV,Z

62

63

SUBR

f,WREG

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = WREG – f

Wd = Ws – Wb

Wd = lit5 – Wb

SUBBR

f = WREG – f – (C)

SUBBR

SWAP.b

SWAP

f,WREG

Wb,Ws,Wd

Wb,#lit5,Wd

Wn

WREG = WREG – f – (C)

Wd = Ws – Wb – (C)

1

2

C,DC,N,OV,Z

None

Wd = lit5 – Wb – (C)

64

65

SWAP

Wn = nibble swap Wn

Wn = byte swap Wn

Wn

None

TBLRDH

TBLRDH Ws,Wd

Read Prog<23:16> to Wd<7:0>

None

Preliminary

DS70175D-page 237

PIC24H

TABLE 21-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

66

TBLRDL

TBLWTH

TBLWTL

ULNK

TBLRDL Ws,Wd

Read Prog<15:0> to Wd

1

2

1

None

N,Z

67

68

69

70

TBLWTH Ws,Wd

TBLWTL Ws,Wd

ULNK

Write Ws<7:0> to Prog<23:16>

Write Ws to Prog<15:0>

Unlink Frame Pointer

f = f .XOR. WREG

XOR

ZE

f

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

Ws,Wnd

WREG = f .XOR. WREG

Wd = lit10 .XOR. Wd

Wd = Wb .XOR. Ws

N,Z

Wd = Wb .XOR. lit5

N,Z

71

ZE

Wnd = Zero-extend Ws

C,Z,N

DS70175D-page 238

Preliminary

PIC24H

22.1 MPLAB Integrated Development

Environment Software

22.0 DEVELOPMENT SUPPORT

The PICmicro^®microcontrollers are supported with a

full range of hardware and software development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

• A single graphical interface to all debugging tools

- Simulator

- MPLAB C18 and MPLAB C30 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- Programmer (sold separately)

- Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

• Emulators

• Customizable data windows with direct edit of

contents

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB ICE 4000 In-Circuit Emulator

• In-Circuit Debugger

• High-level source code debugging

• Visual device initializer for easy register

initialization

- MPLAB ICD 2

• Mouse over variable inspection

• Device Programmers

• Drag and drop variables from source to watch

windows

- PICSTART^®Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Extensive on-line help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

• One touch assemble (or compile) and download

to PICmicro MCU emulator and simulator tools

(automatically updates all project information)

• Debug using:

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

Preliminary

DS70175D-page 239

PIC24H

22.2 MPASM Assembler

22.5 MPLAB ASM30 Assembler, Linker

and Librarian

The MPASM Assembler is a full-featured, universal

macro assembler for all PICmicro MCUs.

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• User-defined macros to streamline

assembly code

• Rich directive set

• Conditional assembly for multi-purpose

source files

• Flexible macro language

• MPLAB IDE compatibility

• Directives that allow complete control over the

assembly process

22.6 MPLAB SIM Software Simulator

22.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PICmicro MCUs and dsPIC^®DSCs on an

instruction level. On any given instruction, the data

areas can be examined or modified and stimuli can be

applied from a comprehensive stimulus controller.

Registers can be logged to files for further run-time

analysis. The trace buffer and logic analyzer display

extend the power of the simulator to record and track

program execution, actions on I/O, most peripherals

and internal registers.

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI

C

compilers for

Microchip’s PIC18 family of microcontrollers and the

dsPIC30, dsPIC33 and PIC24 family of digital signal

controllers. These compilers provide powerful integra-

tion capabilities, superior code optimization and ease

of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

22.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

DS70175D-page 240

Preliminary

PIC24H

22.7 MPLAB ICE 2000

High-Performance

22.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PICmicro

MCUs and can be used to develop for these and other

PICmicro MCUs and dsPIC DSCs. The MPLAB ICD 2

utilizes the in-circuit debugging capability built into

the Flash devices. This feature, along with Microchip’s

In-Circuit Serial Programming^TM(ICSP^TM) protocol,

offers cost-effective, in-circuit Flash debugging from the

graphical user interface of the MPLAB Integrated

Development Environment. This enables a designer to

develop and debug source code by setting breakpoints,

single stepping and watching variables, and CPU

status and peripheral registers. Running at full speed

enables testing hardware and applications in real

time. MPLAB ICD 2 also serves as a development

programmer for selected PICmicro MCU devices.

In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PICmicro

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing features. Interchangeable processor modules allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PICmicro microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft^®Windows^®32-bit operating system were

chosen to best make these features available in a

simple, unified application.

22.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ programming capability

cable assembly is included as a standard item. In

Stand-Alone mode, the MPLAB PM3 Device Program-

mer can read, verify and program PICmicro MCU

devices without a PC connection. It can also set code

protection in this mode. The MPLAB PM3 connects to

the host PC via an RS-232 or USB cable. The MPLAB

PM3 has high-speed communications and optimized

algorithms for quick programming of large memory

devices and incorporates an SD/MMC card for file stor-

age and secure data applications.

22.8 MPLAB ICE 4000

High-Performance

In-Circuit Emulator

The MPLAB ICE 4000 In-Circuit Emulator is intended to

provide the product development engineer with a

complete microcontroller design tool set for high-end

PICmicro MCUs and dsPIC DSCs. Software control of

the MPLAB ICE 4000 In-Circuit Emulator is provided by

the MPLAB Integrated Development Environment,

which allows editing, building, downloading and source

debugging from a single environment.

The MPLAB ICE 4000 is a premium emulator system,

providing the features of MPLAB ICE 2000, but with

increased emulation memory and high-speed perfor-

mance for dsPIC30F and PIC18XXXX devices. Its

advanced emulator features include complex triggering

and timing, and up to 2 Mb of emulation memory.

The MPLAB ICE 4000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

Preliminary

DS70175D-page 241

PIC24H

22.11 PICSTART Plus Development

Programmer

22.13 Demonstration, Development and

Evaluation Boards

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PICmicro MCU devices in DIP packages up to 40

pins. Larger pin count devices, such as the PIC16C92X

and PIC17C76X, may be supported with an adapter

socket. The PICSTART Plus Development

A wide variety of demonstration, development and

evaluation boards for various PICmicro MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

Programmer is CE compliant.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

22.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer with an easy-to-use interface for pro-

gramming many of Microchip’s baseline, mid-range

and PIC18F families of Flash memory microcontrollers.

The PICkit 2 Starter Kit includes a prototyping develop-

ment board, twelve sequential lessons, software and

HI-TECH’s PICC™ Lite C compiler, and is designed to

help get up to speed quickly using PIC^®micro-

controllers. The kit provides everything needed to

program, evaluate and develop applications using

Microchip’s powerful, mid-range Flash memory family

of microcontrollers.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart^®battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

DS70175D-page 242

Preliminary

PIC24H

23.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of PIC24H electrical characteristics. Additional information will be provided in future

revisions of this document as it becomes available.

Absolute maximum ratings for the PIC24H family are listed below. Exposure to these maximum rating conditions for

extended periods may affect device reliability. Functional operation of the device at these or any other conditions above

the parameters indicated in the operation listings of this specification is not implied.

(Note 1)

Absolute Maximum Ratings

Ambient temperature under bias...............................................................................................................-40°C to +85°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V

Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V)

Voltage on any digital-only pin with respect to VSS .................................................................................. -0.3V to +5.6V

Voltage on VDDCORE with respect to VSS ................................................................................................ 2.25V to 2.75V

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin (Note 2)................................................................................................................250 mA

Maximum output current sunk by any I/O pin (Note 3) .............................................................................................4 mA

Maximum output current sourced by any I/O pin (Note 3)........................................................................................4 mA

Maximum current sunk by all ports .......................................................................................................................200 mA

Maximum current sourced by all ports (Note 2)....................................................................................................200 mA

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions

above those indicated in the operation listings of this specification is not implied. Exposure to maximum

rating conditions for extended periods may affect device reliability.

2: Maximum allowable current is a function of device maximum power dissipation (see Table 23-2).

3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGCx

and PGDx pins, which are able to sink/source 12 mA.

Preliminary

DS70175D-page 243

PIC24H

23.1 DC Characteristics

TABLE 23-1: OPERATING MIPS VS. VOLTAGE

Max MIPS

PIC24H

40

VDD Range

(in Volts)

Temp Range

Characteristic

(in °C)

DC5

3.0-3.6V

-40°C to +85°C

TABLE 23-2: THERMAL OPERATING CONDITIONS

Rating

Symbol

Min

Typ

Max

Unit

PIC24H

Operating Junction Temperature Range

Operating Ambient Temperature Range

TJ

TA

-40

—

+125

+85

°C

Power Dissipation:

Internal chip power dissipation:

PINT = VDD x (IDD – Σ IOH)

PD

PINT + PI/O

W

I/O Pin Power Dissipation:

I/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL)

Maximum Allowed Power Dissipation

PDMAX

(TJ – TA)/θJA

TABLE 23-3: THERMAL PACKAGING CHARACTERISTICS

Characteristic

Symbol

Typ

Max

Unit

Notes

Package Thermal Resistance, 100-pin TQFP (14x14x1 mm)

Package Thermal Resistance, 100-pin TQFP (12x12x1 mm)

Package Thermal Resistance, 80-pin TQFP (12x12x1 mm)

Package Thermal Resistance, 64-pin TQFP (10x10x1 mm)

Legend: TBD = To Be Determined

θJA

48.4

52.3

38.7

38.3

—

°C/W

1

Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.

TABLE 23-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

DC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Param

Symbol

No.

Characteristic

Min

Typ⁽¹⁾

Max Units

Conditions

Operating Voltage

DC10 Supply Voltage

VDD

3.0

—

2.8

VSS

3.6

—

V

DC12

DC16

VDR

RAM Data Retention Voltage⁽²⁾

VPOR

VDD Start Voltage

to ensure internal

—

Power-on Reset signal

DC17

SVDD

VDD Rise Rate

to ensure internal

Power-on Reset signal

0.05

—

V/ms 0-3.3V in 0.1s

0-2.5V in 60 ms

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: This is the limit to which VDD can be lowered without losing RAM data.

DS70175D-page 244

Preliminary

PIC24H

TABLE 23-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)

Standard Operating Conditions: 3.0V to 3.6V

DC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Parameter

Typical⁽¹⁾

No.

Max

Units

Conditions

Operating Current (IDD)⁽²⁾

DC20

27

26

33

32

44

43

60

58

74

72

—

mA

+25°C

+85°C

+25°C

+85°C

+25°C

+85°C

+25°C

+85°C

+25°C

+85°C

3.3V

10 MIPS

16 MIPS

20 MIPS

30 MIPS

40 MIPS

DC20a

DC21

DC21a

DC22

DC22a

DC23

DC23a

DC24

DC24a

Legend: TBD = To Be Determined

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1

driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS.

MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are

operational. No peripheral modules are operating; however, every peripheral is being clocked (PMD bits

are all zeroed.

Preliminary

DS70175D-page 245

PIC24H

TABLE 23-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

Parameter

Typical⁽¹⁾

No.

Max

Units

Conditions

Idle Current (IIDLE): Core OFF Clock ON Base Current⁽²⁾

DC40

TBD

16.5

16

—

mA

+25°C

+85°C

+25°C

+85°C

+25°C

+85°C

+25°C

+85°C

+25°C

+85°C

10 MIPS

16 MIPS

20 MIPS

30 MIPS

40 MIPS

3.3V

DC40a

DC41

DC41a

DC42

3.3V

DC42a

DC43

DC43a

DC44

DC44a

Legend: TBD = To Be Determined

Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral Module

Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS.

TABLE 23-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)

Standard Operating Conditions: 3.0V to 3.6V

DC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Parameter

Typical⁽¹⁾

No.

Max

Units

Conditions

Power-Down Current (IPD)⁽²⁾

DC60

200

TBD

—

μA

+25°C

+85°C

+25°C

+85°C

3.0V

Base Power-Down Current^(3,4)

DC60a

DC61

(3)

Watchdog Timer Current: ΔIWDT

DC61a

Legend: TBD = To Be Determined

Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

2: Base IPD is measured with all peripherals and clocks shut down. All I/O pins are configured as inputs and

pulled to VSS. WDT, etc., are all switched off.

3: The Δ current is the additional current consumed when the module is enabled. This current should be

added to the base IPD current.

4: These currents are measured on the device containing the most memory in this family.

DS70175D-page 246

Preliminary

PIC24H

TABLE 23-8: DC CHARACTERISTICS:DOZE CURRENT (IDOZE)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Doze

Ratio

Parameter No.

Typical⁽¹⁾

Max

Units

Conditions

DC70a

DC70f

DC70g

DC71a

DC71f

DC71g

42

26

25

41

25

24

—

1:2

1:64

1:128

1:2

mA

25°C

3.3V

40 MIPS

mA

85°C

1:64

1:128

Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance

only and are not tested.

Preliminary

DS70175D-page 247

PIC24H

TABLE 23-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

DC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Input Low Voltage

Min

Typ⁽¹⁾

Max

Units

Conditions

VIL

DI10

DI15

DI16

DI17

DI18

DI19

I/O pins

MCLR

VSS

—

0.2 VDD

0.3 VDD

0.2 VDD

V

OSC1 (XT mode)

OSC1 (HS mode)

SDAx, SCLx

SMBus disabled

SDAx, SCLx

SMBus enabled

VIH

Input High Voltage

DI20

I/O pins:

with analog functions

digital-only

0.8 VDD

—

VDD

5.5

V

DI25

DI26

DI27

DI28

DI29

MCLR

0.8 VDD

0.7 VDD

0.8 VDD

—

VDD

V

OSC1 (XT mode)

OSC1 (HS mode)

SDAx, SCLx

SMBus disabled

SMBus enabled

SDAx, SCLx

ICNPU

IIL

CNx Pull-up Current

DI30

50

250

400

μA VDD = 3.3V, VPIN = VSS

Input Leakage Current⁽²⁾⁽³⁾

DI50

DI51

I/O ports

—

TBD

μA VSS ≤ VPIN ≤ VDD,

Pin at high-impedance

Analog Input Pins

μA VSS ≤ VPIN ≤ VDD,

Pin at high-impedance

DI55

DI56

MCLR

OSC1

—

TBD

μA

VSS ≤ VPIN ≤ VDD

μA VSS ≤ VPIN ≤ VDD,

XT and HS modes

Legend: TBD = To Be Determined

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

DS70175D-page 248

Preliminary

PIC24H

TABLE 23-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

DC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Param

Symbol

No.

Characteristic

Min

Typ⁽¹⁾Max Units

Conditions

VOL

Output Low Voltage

I/O ports

DO10

DO16

—

0.4

V

IOL = TBD mA, VDD = 3.3V

OSC2/CLKO

VOH

Output High Voltage

I/O ports

DO20

DO26

2.4

—

V

IOH = -3.0 mA, VDD = 3.3V

IOH = -1.3 mA, VDD = 3.3V

OSC2/CLKO

Legend: TBD = To Be Determined

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

TABLE 23-11: DC CHARACTERISTICS: PROGRAM MEMORY

Standard Operating Conditions: 3.0V to 3.6V

DC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Param

Symbol

No.

Characteristic

Min Typ⁽¹⁾

Max

Units

Conditions

Program Flash Memory

Cell Endurance

D130

D131

EP

100

1000

—

E/W -40°C to +85°C

VPR

VDD for Read

VMIN

3.6

V

VMIN = Minimum operating

voltage

D132B VPEW

VDD for Self-Timed Write

VMIN

—

3.6

V

VMIN = Minimum operating

voltage

D133A TIW

Self-Timed Write Cycle Time

Characteristic Retention

—

1.5

—

ms

D134

D135

D136

D137

D138

TRETD

IDDP

TRW

TPE

20

Year Provided no other specifications

are violated

Supply Current during

Programming

—

20

10

1.6

20.5

—

40

mA

ms

μs

Self-Timed Row Write Cycle

Time

Self-Timed Page Erase

Cycle Time

TWW

Word Write Cycle Time

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

TABLE 23-12: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

Operating Conditions: -40°C < TA < +85°C (unless otherwise stated)

Param

No.

Symbol

Characteristics

Min

Typ

Max

Units

Comments

CEFC

External Filter Capacitor

Value

1

10

—

μF

Capacitor must be low series

resistance (< 5 ohms)

Preliminary

DS70175D-page 249

PIC24H

23.2 AC Characteristics and Timing

Parameters

The information contained in this section defines

PIC24H AC characteristics and timing parameters.

TABLE 23-13: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Operating voltage VDD range as described in Section 23.0 “Electrical

Characteristics”.

FIGURE 23-1:

Load Condition 1 – for all pins except OSC2

VDD/2

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 2 – for OSC2

CL

RL

VSS

CL

RL = 464Ω

CL = 50 pF for all pins except OSC2

VSS

15 pF for OSC2 output

TABLE 23-14: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

Param

Symbol

Characteristic

Min

Typ⁽¹⁾Max Units

Conditions

No.

DO50 COSC2

OSC2/SOSC2 pin

—

15

pF In XT and HS modes when

external clock is used to drive

OSC1

DO56 CIO

DO58 CB

All I/O pins and OSC2

SCLx, SDAx

—

50

pF EC mode

pF In I²C™ mode

400

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

DS70175D-page 250

Preliminary

PIC24H

FIGURE 23-2:

EXTERNAL CLOCK TIMING

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

OSC1

CLKO

OS20

OS30 OS30

OS25

OS31 OS31

OS41

OS40

TABLE 23-15: EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 2.5V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Param

Symb

No.

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

OS10

FIN

External CLKI Frequency

(External clocks allowed only

in EC and ECPLL modes)

0.8

4

—

64

8

MHz EC

MHz ECPLL

Oscillator Crystal Frequency

3

10

—

10

40

33

MHz XT

MHz XTPLL

MHz HS

MHz HSPLL

kHz SOSC

OS20

OS25

OS30

TOSC

TCY

TOSC = 1/FOSC

Instruction Cycle Time⁽²⁾

12.5

25

—

DC

—

ns

TosL, External Clock in (OSC1)

TosH High or Low Time

0.625 x TOSC

ns

EC

OS31

TosR, External Clock in (OSC1)

TosF Rise or Fall Time

—

TBD

ns

OS40

OS41

TckR CLKO Rise Time⁽³⁾

—

6

TBD

ns

TckF

CLKO Fall Time⁽³⁾

Legend: TBD = To Be Determined

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator

operation and/or higher than expected current consumption. All devices are tested to operate at “min.”

values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the

“max.” cycle time limit is “DC” (no clock) for all devices.

3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.

Preliminary

DS70175D-page 251

PIC24H

TABLE 23-16: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

OS50

FPLLI

PLL Voltage Controlled

Oscillator (VCO) Input

Frequency Range

0.8

—

8

MHz ECPLL, HSPLL, XTPLL

modes

OS51

FSYS

On-Chip VCO System

Frequency

100

—

200

MHz

OS52

OS53

TLOC

DCLK

PLL Start-up Time (Lock Time)

CLKO Stability (Jitter)

TBD

100

1

TBD

μs

%

Measured over 100 ms

period

Legend: TBD = To Be Determined

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

TABLE 23-17: AC CHARACTERISTICS: INTERNAL RC ACCURACY

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

AC CHARACTERISTICS

Operating temperature

^-40°C≤ TA ≤ +85°C for industrial

Param

No.

Characteristic

Min

Typ

Max

Units

Conditions

Internal FRC Accuracy @ 7.3728 MHz⁽¹⁾

F20

FRC

TBD

—

TBD

%

+25°C

-40°C ≤ TA ≤ +85°C

VDD = 3.0-3.6V

Legend: TBD = To Be Determined

Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift.

TABLE 23-18: INTERNAL RC ACCURACY

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

AC CHARACTERISTICS

Param

No.

Characteristic

Min

Typ

Max

Units

Conditions

LPRC @ 32.768 kHz⁽¹⁾

F21

TBD

—

TBD

%

+25°C

-40°C ≤ TA ≤ +85°C

VDD = 3.0-3.6V

Legend: TBD = To Be Determined

Note 1: Change of LPRC frequency as VDD changes.

DS70175D-page 252

Preliminary

PIC24H

FIGURE 23-3:

CLKO AND I/O TIMING CHARACTERISTICS

I/O Pin

(Input)

DI35

DI40

I/O Pin

(Output)

New Value

Old Value

DO31

DO32

Note: Refer to Figure 23-1 for load conditions.

TABLE 23-19: CLKO AND I/O TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Param

Symbol

No.

Characteristic

Min

Typ⁽¹⁾

Max

Units

Conditions

DO31

DO32

DI35

TIOR

TIOF

TINP

TRBP

Port Output Rise Time

—

20

2

10

—

25

—

ns

—

Port Output Fall Time

INTx Pin High or Low Time (output)

CNx High or Low Time (input)

ns

DI40

TCY

Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.

Preliminary

DS70175D-page 253

PIC24H

FIGURE 23-4:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING CHARACTERISTICS

VDD

SY12

MCLR

SY10

Internal

POR

SY11

PWRT

Time-out

SY30

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

SY20

SY13

I/O Pins

SY35

FSCM

Delay

Note: Refer to Figure 23-1 for load conditions.

DS70175D-page 254

Preliminary

PIC24H

TABLE 23-20: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

AC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max Units

Conditions

SY10

SY11

TMCL

MCLR Pulse Width (low)

Power-up Timer Period

2

—

μs

-40°C to +85°C

TPWRT

0.75

1.5

3

1

2

4

1.25

2.5

5

ms -40°C to +85°C

User programmable

6

8

10

12

24

48

96

16

32

64

128

20

40

80

160

SY12

SY13

TPOR

TIOZ

Power-on Reset Delay

3

10

30

μs

-40°C to +85°C

I/O High-Impedance from MCLR

Low or Watchdog Timer Reset

—

0.8

1.0

SY20

TWDT1

Watchdog Timer Time-out Period

(No Prescaler)

1.8

2.0

2.2

ms VDD = 5V, -40°C to +85°C

TWDT2

TOST

1.9

—

2.1

1024 TOSC

500

2.3

—

ms VDD = 3V, -40°C to +85°C

SY30

SY35

Oscillator Start-up Timer Period

Fail-Safe Clock Monitor Delay

—

TOSC = OSC1 period

-40°C to +85°C

TFSCM

—

900

μs

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated.

3: Characterized by design but not tested.

Preliminary

DS70175D-page 255

PIC24H

FIGURE 23-5:

TIMER1, 2, 3, 4, 5, 6, 7, 8 AND 9 EXTERNAL CLOCK TIMING CHARACTERISTICS

TxCK

Tx11

Tx10

Tx15

Tx20

OS60

TMRx

Note: Refer to Figure 23-1 for load conditions.

TABLE 23-21: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS⁽¹⁾

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C

Param

Symbol

No.

Characteristic

Min

Typ

Max Units

Conditions

TA10

TA11

TA15

TTXH

TTXL

TTXP

TxCK High Time

TxCK Low Time

Synchronous,

no prescaler

0.5 TCY + 20

—

ns Must also meet

parameter TA15

Synchronous,

with prescaler

10

—

ns

Asynchronous

10

—

ns

Synchronous,

no prescaler

0.5 TCY + 20

ns Must also meet

parameter TA15

Synchronous,

with prescaler

10

—

ns

Asynchronous

10

—

ns

TxCK Input Period Synchronous,

no prescaler

TCY + 10

Synchronous,

with prescaler

Greater of:

20 ns or

—

N = prescale

value

(TCY + 40)/N

(1, 8, 64, 256)

Asynchronous

20

—

ns

OS60

TA20

Ft1

SOSC1/T1CK Oscillator Input

frequency Range (oscillator enabled

by setting bit TCS (T1CON<1>))

DC

50

kHz

TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment

0.5 TCY

1.5 TCY

—

Note 1: Timer1 is a Type A.

DS70175D-page 256

Preliminary

PIC24H

TABLE 23-22: TIMER2, TIMER4, TIMER6 AND TIMER8 EXTERNAL CLOCK TIMING

REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

AC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

Symbol

No.

Characteristic

Min

Typ

Max

Units

Conditions

TB10

TB11

TB15

TtxH

TtxL

TtxP

TxCK High Time Synchronous, 0.5 TCY + 20

no prescaler

—

ns

Must also meet

parameter TB15

Synchronous,

with prescaler

10

—

ns

TxCK Low Time

Synchronous, 0.5 TCY + 20

no prescaler

Must also meet

parameter TB15

Synchronous,

with prescaler

10

TxCK Input Period Synchronous,

no prescaler

TCY + 10

N = prescale

value

(1, 8, 64, 256)

Synchronous,

with prescaler

Greater of:

20 ns or

(TCY + 40)/N

TB20

TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment

0.5 TCY

—

1.5 TCY

—

TABLE 23-23: TIMER3, TIMER5, TIMER7 AND TIMER9 EXTERNAL CLOCK TIMING

REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

AC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

Symbol

No.

Characteristic

Min

Typ

Max Units

Conditions

TC10

TC11

TC15

TtxH

TtxL

TtxP

TxCK High Time

TxCK Low Time

Synchronous

0.5 TCY + 20

—

ns Must also meet

parameter TC15

0.5 TCY + 20

TCY + 10

—

ns Must also meet

parameter TC15

TxCK Input Period Synchronous,

no prescaler

ns N = prescale

value

(1, 8, 64, 256)

Synchronous,

with prescaler

Greater of:

20 ns or

(TCY + 40)/N

TC20

TCKEXTMRL Delay from External TxCK Clock

Edge to Timer Increment

0.5 TCY

—

1.5 TCY

—

Preliminary

DS70175D-page 257

PIC24H

FIGURE 23-6:

INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS

ICx

IC10

IC11

IC15

Note: Refer to Figure 23-1 for load conditions.

TABLE 23-24: INPUT CAPTURE TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Max

Units

Conditions

IC10

IC11

IC15

TccL

TccH

TccP

ICx Input Low Time No Prescaler

With Prescaler

0.5 TCY + 20

10

—

ns

ICx Input High Time No Prescaler

With Prescaler

0.5 TCY + 20

10

ICx Input Period

(2 TCY + 40)/N

N = prescale

value (1, 4, 16)

Note 1: These parameters are characterized but not tested in manufacturing.

FIGURE 23-7:

OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS

OCx

(Output Compare

or PWM Mode)

OC10

OC11

Note: Refer to Figure 23-1 for load conditions.

TABLE 23-25: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

OC10 TccF

OC11 TccR

OCx Output Fall Time

OCx Output Rise Time

—

ns

See parameter D032

See parameter D031

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

DS70175D-page 258

Preliminary

PIC24H

FIGURE 23-8:

OC/PWM MODULE TIMING CHARACTERISTICS

OC20

OCFA/OCFB

OC15

OCx

TABLE 23-26: SIMPLE OC/PWM MODE TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

OC15

TFD

Fault Input to PWM I/O

Change

—

50

ns

—

OC20

TFLT

Fault Input Pulse Width

50

—

ns

—

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

FIGURE 23-9:

SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS

SCKx

(CKP = 0)

SP11

SP10

SP21

SP20

SCKx

(CKP = 1)

SP35

SP31

SP21

LSb

Bit 14 - - - - - -1

MSb

SDOx

SDIx

SP30

MSb In

SP40

LSb In

Bit 14 - - - -1

SP41

Note: Refer to Figure 23-1 for load conditions.

Preliminary

DS70175D-page 259

PIC24H

TABLE 23-27: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

SP10

SP11

SP20

SP21

SP30

SP31

SP35

TscL

TscH

TscF

TscR

TdoF

TdoR

SCKx Output Low Time⁽³⁾

SCKx Output High Time⁽³⁾

SCKx Output Fall Time⁽⁴⁾

SCKx Output Rise Time⁽⁴⁾

SDOx Data Output Fall Time⁽⁴⁾

SDOx Data Output Rise Time⁽⁴⁾

TCY/2

—

30

ns

—

See parameter D032

See parameter D031

See parameter D032

See parameter D031

—

TscH2doV, SDOx Data Output Valid after

TscL2doV SCKx Edge

—

SP40

SP41

TdiV2scH, Setup Time of SDIx Data Input

20

—

ns

—

TdiV2scL

TscH2diL, Hold Time of SDIx Data Input

TscL2diL to SCKx Edge

Note 1: These parameters are characterized but not tested in manufacturing.

to SCKx Edge

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all SPIx pins.

FIGURE 23-10:

SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS

SP36

SCKX

(CKP = 0)

SP11

SP10

SP21

SP20

SP21

SCKX

(CKP = 1)

SP35

LSb

MSb

SP40

Bit 14 - - - - - -1

SDOX

SDIX

SP30,SP31

Bit 14 - - - -1

MSb In

SP41

LSb In

Note: Refer to Figure 23-1 for load conditions.

DS70175D-page 260

Preliminary

PIC24H

TABLE 23-28: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

SP10

SP11

SP20

SP21

SP30

TscL

TscH

TscF

TscR

TdoF

SCKx Output Low Time⁽³⁾

SCKx Output High Time⁽³⁾

SCKx Output Fall Time⁽⁴⁾

SCKx Output Rise Time⁽⁴⁾

TCY/2

—

ns

—

See parameter D032

See parameter D031

See parameter D032

—

SDOx Data Output Fall

Time⁽⁴⁾

—

SP31

SP35

SP36

SP40

SP41

TdoR

SDOx Data Output Rise

Time⁽⁴⁾

—

30

20

—

ns

See parameter D031

TscH2doV, SDOx Data Output Valid after

TscL2doV SCKx Edge

—

TdoV2sc, SDOx Data Output Setup to

TdoV2scL First SCKx Edge

TdiV2scH, Setup Time of SDIx Data

TdiV2scL Input to SCKx Edge

TscH2diL, Hold Time of SDIx Data Input

TscL2diL

to SCKx Edge

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all SPIx pins.

FIGURE 23-11:

SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS

SSX

SP52

SP50

SCKX

(CKP =

0

)

SP71

SP70

SP72

SP73

SP72

SCKX

(CKP =

1

SP73

LSb

SP35

MSb

Bit 14 - - - - - -1

SP30,SP31

SDOX

SDIX

SP51

Bit 14 - - - -1

MSb In

SP41

LSb In

SP40

Note: Refer to Figure 23-1 for load conditions.

Preliminary

DS70175D-page 261

PIC24H

TABLE 23-29: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

AC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ⁽²⁾Max Units

Conditions

SP70

SP71

SP72

SP73

SP30

SP31

SP35

TscL

TscH

TscF

TscR

TdoF

TdoR

SCKx Input Low Time

30

—

10

—

25

—

30

ns

—

SCKx Input High Time

—

SCKx Input Fall Time⁽³⁾

SCKx Input Rise Time⁽³⁾

SDOx Data Output Fall Time⁽³⁾

SDOx Data Output Rise Time⁽³⁾

—

See parameter D032

See parameter D031

—

TscH2doV, SDOx Data Output Valid after

TscL2doV SCKx Edge

SP40

SP41

SP50

SP51

SP52

TdiV2scH, Setup Time of SDIx Data Input

TdiV2scL to SCKx Edge

20

—

50

—

ns

—

TscH2diL, Hold Time of SDIx Data Input

TscL2diL

to SCKx Edge

TssL2scH, SSx ↓ to SCKx ↑ or SCKx Input

TssL2scL

120

TssH2doZ SSx ↑ to SDOx Output

10

High-Impedance⁽³⁾

TscH2ssH SSx after SCKx Edge

TscL2ssH

1.5 TCY +40

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: Assumes 50 pF load on all SPIx pins.

DS70175D-page 262

Preliminary

PIC24H

FIGURE 23-12:

SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS

SP60

SSx

SP52

SP50

SCKx

(CKP = 0)

SP71

SP70

SP72

SP73

SCKx

(CKP = 1)

SP35

SP72

LSb

SP52

Bit 14 - - - - - -1

MSb

SDOx

SDIx

SP30,SP31

Bit 14 - - - -1

SP51

MSb In

SP41

LSb In

SP40

Note: Refer to Figure 23-1 for load conditions.

Preliminary

DS70175D-page 263

PIC24H

TABLE 23-30: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

AC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ⁽²⁾

Max

Units

Conditions

SP70

SP71

SP72

SP73

SP30

SP31

SP35

TscL

TscH

TscF

TscR

TdoF

TdoR

SCKx Input Low Time

30

—

10

—

25

—

30

ns

—

SCKx Input High Time

—

SCKx Input Fall Time⁽³⁾

SCKx Input Rise Time⁽³⁾

SDOx Data Output Fall Time⁽³⁾

SDOx Data Output Rise Time⁽³⁾

—

See parameter D032

See parameter D031

—

TscH2doV, SDOx Data Output Valid after

TscL2doV SCKx Edge

SP40

SP41

SP50

SP51

SP52

SP60

TdiV2scH, Setup Time of SDIx Data Input

TdiV2scL to SCKx Edge

20

—

50

—

50

ns

—

TscH2diL, Hold Time of SDIx Data Input

TscL2diL to SCKx Edge

20

TssL2scH, SSx ↓ to SCKx ↓ or SCKx ↑

TssL2scL Input

120

TssH2doZ SSx ↑ to SDOX Output

10

1.5 TCY + 40

—

High-Impedance⁽⁴⁾

TscH2ssH SSx ↑ after SCKx Edge

TscL2ssH

TssL2doV SDOx Data Output Valid after

SSx Edge

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all SPIx pins.

DS70175D-page 264

Preliminary

PIC24H

FIGURE 23-13:

I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)

SCLx

IM31

IM34

IM30

IM33

SDAx

Stop

Condition

Start

Condition

Note: Refer to Figure 23-1 for load conditions.

FIGURE 23-14:

I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

IM20

IM21

IM11

IM10

SCLx

IM11

IM26

IM10

IM33

IM25

SDAx

In

IM45

IM40

SDAx

Out

Note: Refer to Figure 23-1 for load conditions.

Preliminary

DS70175D-page 265

PIC24H

TABLE 23-31: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min⁽¹⁾

Max

Units

Conditions

IM10

IM11

IM20

IM21

IM25

IM26

IM30

IM31

IM33

IM34

IM40

IM45

IM50

TLO:SCL Clock Low Time 100 kHz mode

400 kHz mode

TCY/2 (BRG + 1)

—

μs

ns

μs

ns

μs

ns

μs

pF

—

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

THI:SCL Clock High Time 100 kHz mode

400 kHz mode

TCY/2 (BRG + 1)

—

TCY/2 (BRG + 1)

—

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

TF:SCL

TR:SCL

SDAx and SCLx 100 kHz mode

—

300

100

1000

300

—

CB is specified to be

from 10 to 400 pF

Fall Time

400 kHz mode

1 MHz mode⁽²⁾

20 + 0.1 CB

—

SDAx and SCLx 100 kHz mode

—

CB is specified to be

from 10 to 400 pF

Rise Time

400 kHz mode

20 + 0.1 CB

1 MHz mode⁽²⁾

—

TSU:DAT Data Input

Setup Time

100 kHz mode

400 kHz mode

1 MHz mode⁽²⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽²⁾

250

—

100

—

TBD

—

THD:DAT Data Input

Hold Time

0

—

0.9

—

TBD

TSU:STA Start Condition 100 kHz mode

TCY/2 (BRG + 1)

—

Only relevant for

Repeated Start

condition

Setup Time

400 kHz mode

TCY/2 (BRG + 1)

—

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

THD:STA Start Condition 100 kHz mode

Hold Time

TCY/2 (BRG + 1)

—

After this period the

first clock pulse is

generated

400 kHz mode

TCY/2 (BRG + 1)

—

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

TSU:STO Stop Condition 100 kHz mode

TCY/2 (BRG + 1)

—

Setup Time

400 kHz mode

TCY/2 (BRG + 1)

—

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

THD:STO Stop Condition

Hold Time

100 kHz mode

400 kHz mode

TCY/2 (BRG + 1)

—

TCY/2 (BRG + 1)

—

1 MHz mode⁽²⁾TCY/2 (BRG + 1)

—

TAA:SCL Output Valid

From Clock

100 kHz mode

400 kHz mode

1 MHz mode⁽²⁾

—

3500

1000

—

TBF:SDA Bus Free Time 100 kHz mode

4.7

1.3

TBD

—

Time the bus must be

free before a new

transmission can start

400 kHz mode

1 MHz mode⁽²⁾

—

CB

Bus Capacitive Loading

400

Legend: TBD = To Be Determined

Note 1: BRG is the value of the I²C Baud Rate Generator. Refer to Section 21. “Inter-Integrated Circuit (I²C™)”

in the “dsPIC30F Family Reference Manual” (DS70046).

2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

DS70175D-page 266

Preliminary

PIC24H

FIGURE 23-15:

I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

SCLx

IS34

IS31

IS30

IS33

SDAx

Stop

Condition

Start

Condition

FIGURE 23-16:

I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

IS20

IS21

IS11

IS10

SCLx

IS30

IS26

IS31

IS33

IS25

SDAx

In

IS45

IS40

SDAx

Out

Preliminary

DS70175D-page 267

PIC24H

TABLE 23-32: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min

Max Units

Conditions

IS10

TLO:SCL Clock Low Time 100 kHz mode

400 kHz mode

4.7

—

μs

Device must operate at a

minimum of 1.5 MHz

1.3

Device must operate at a

minimum of 10 MHz

1 MHz mode⁽¹⁾

0.5

4.0

—

μs

—

IS11

THI:SCL

Clock High Time 100 kHz mode

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

—

μs

Device must operate at a

minimum of 10 MHz

1 MHz mode⁽¹⁾

0.5

—

300

100

1000

300

—

μs

ns

μs

ns

μs

pF

—

IS20

IS21

IS25

IS26

IS30

IS31

IS33

IS34

IS40

IS45

IS50

TF:SCL

TR:SCL

SDAx and SCLx 100 kHz mode

—

CB is specified to be from

10 to 400 pF

Fall Time

400 kHz mode

1 MHz mode⁽¹⁾

20 + 0.1 CB

—

SDAx and SCLx 100 kHz mode

CB is specified to be from

10 to 400 pF

Rise Time

400 kHz mode

1 MHz mode⁽¹⁾

20 + 0.1 CB

—

TSU:DAT Data Input

Setup Time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

250

100

0

—

THD:DAT Data Input

Hold Time

—

0

0.9

0.3

—

0

TSU:STA Start Condition

Setup Time

4.7

0.6

0.25

4.0

0.6

0.25

4.7

0.6

4000

600

250

0

Only relevant for Repeated

Start condition

—

THD:STA Start Condition

Hold Time

—

After this period, the first

clock pulse is generated

—

TSU:STO Stop Condition

Setup Time

—

THD:STO Stop Condition

Hold Time

—

TAA:SCL

Output Valid From 100 kHz mode

3500

1000

350

—

Clock

400 kHz mode

1 MHz mode⁽¹⁾

0

TBF:SDA Bus Free Time

100 kHz mode

400 kHz mode

1 MHz mode⁽¹⁾

4.7

1.3

0.5

—

Time the bus must be free

before a new transmission

can start

—

CB

Bus Capacitive Loading

400

—

Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).

DS70175D-page 268

Preliminary

PIC24H

FIGURE 23-17:

ECAN™ MODULE I/O TIMING CHARACTERISTICS

CiTx Pin

(output)

New Value

Old Value

CA10 CA11

CiRx Pin

(input)

CA20

TABLE 23-33: ECAN™ MODULE I/O TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic⁽¹⁾

Min

Typ⁽²⁾Max

Units

Conditions

CA10

CA11

CA20

TioF

TioR

Tcwf

Port Output Fall Time

Port Output Rise Time

—

ns

See parameter D032

See parameter D031

—

Pulse Width to Trigger

CAN Wake-up Filter

500

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and

are not tested.

Preliminary

DS70175D-page 269

PIC24H

TABLE 23-34: A/D MODULE SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

AC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

Symbol

No.

Characteristic

Min.

Typ

Max.

Units

Conditions

Device Supply

AD01 AVDD

AD02 AVSS

Module VDD Supply

Module VSS Supply

Greater of

VDD - 0.3

or 3.0

—

Lesser of

VDD + 0.3

or 3.6

V

—

VSS - 0.3

VSS + 0.3

Reference Inputs

AD05

AD06

AD07

VREFH

VREFL

VREF

Reference Voltage High

Reference Voltage Low

AVSS + 1.7

AVSS

—

AVDD

V

—

AVDD - 1.7

AVDD + 0.3

Absolute Reference

Voltage

AVSS – 0.3

AD08

IREF

Current Drain

—

200

.001

300

3

μA

A/D operating

A/D off

Analog Input

VREFL

AD10 VINH-VINL Full-Scale Input Span

VREFH

AVDD + 0.3

±0.610

V

See Note

AD11

AD12

VIN

—

Absolute Input Voltage

Leakage Current

AVSS – 0.3

—

±0.001

μA

VINL = AVSS = VREFL =

0V, AVDD = VREFH = 5V

Source Impedance =

2.5 KΩ

AD13

—

Leakage Current

±0.001

—

±0.610

μA

VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

Source Impedance =

2.5 KΩ

AD17 RIN

Recommended Impedance

of Analog Voltage Source

1K

2.5K

Ω

10-bit

12-bit

ADC Accuracy (12-bit Mode)

AD20a Nr

Resolution

12 data bits

bits

AD21a INL

Integral Nonlinearity⁽²⁾

—

<±2

<±1

±3

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

AD22a DNL

AD23a GERR

AD24a EOFF

AD25a —

Differential Nonlinearity⁽²⁾

Gain Error⁽²⁾

—

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

TBD

—

TBD

—

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

Offset Error⁽²⁾

±2

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

Monotonicity⁽¹⁾

—

Guaranteed

Dynamic Performance (12-bit Mode)

AD30a THD

Total Harmonic Distortion

—

TBD

—

dB

—

AD31a SINAD

Signal to Noise and

Distortion

—

Legend: TBD = To Be Determined

Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing

codes.

2: Measurements taken with external VREF+ and VREF- used as the ADC voltage reference.

DS70175D-page 270

Preliminary

PIC24H

TABLE 23-34: A/D MODULE SPECIFICATIONS (CONTINUED)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min.

Typ

Max.

Units

Conditions

AD32a SFDR

Spurious Free Dynamic

Range

—

TBD

—

dB

—

AD33a FNYQ

AD34a ENOB

Input Signal Bandwidth

Effective Number of Bits

—

250

kHz

bits

—

TBD

ADC Accuracy (10-bit Mode)

AD20b Nr

Resolution

10 data bits

bits

AD21b INL

Integral Nonlinearity

—

TBD

—

<±2

<±1

<±3

<±2

—

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

AD22b DNL

AD23b GERR

AD24b EOFF

AD25b —

Differential Nonlinearity

Gain Error

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

Offset Error

LSb VINL = AVSS = VREFL =

0V, AVDD = VREFH = 3V

Monotonicity⁽¹⁾

—

Guaranteed

Dynamic Performance (10-bit Mode)

AD30b THD

Total Harmonic Distortion

—

dB

—

AD31b SINAD

Signal to Noise and

Distortion

TBD

—

AD32b SFDR

Spurious Free Dynamic

Range

—

TBD

—

dB

—

AD33b FNYQ

AD34b ENOB

Input Signal Bandwidth

Effective Number of Bits

—

550

kHz

bits

—

TBD

Legend: TBD = To Be Determined

Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing

codes.

2: Measurements taken with external VREF+ and VREF- used as the ADC voltage reference.

Preliminary

DS70175D-page 271

PIC24H

FIGURE 23-18:

A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS

(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)

AD50

ADCLK

Instruction

Execution

Set SAMP

Clear SAMP

SAMP

ch0_dischrg

ch0_samp

ch1_dischrg

ch1_samp

eoc

AD61

AD60

TSAMP

AD55

CONV

ADxIF

Buffer(0)

Buffer(1)

1

2

3

4

5

6

7

8

5

6

7

8

– Software sets ADxCON. SAMP to start sampling.

1

2

– Sampling starts after discharge period. TSAMP is described in Section 17 in the “dsPIC30F Family Reference Manual”

(DS70046).

– Software clears ADxCON. SAMP to start conversion.

– Sampling ends, conversion sequence starts.

– Convert bit 9.

3

4

5

6

7

8

– Convert bit 8.

– Convert bit 0.

– One TAD for end of conversion.

DS70175D-page 272

Preliminary

PIC24H

FIGURE 23-19:

A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,

SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)

AD50

ADCLK

Instruction

Execution

Set ADON

SAMP

ch0_dischrg

ch0_samp

ch1_dischrg

ch1_samp

eoc

TSAMP

AD55

TCONV

CONV

ADxIF

Buffer(0)

Buffer(1)

1

2

3

4

5

6

7

3

4

5

6

8

3

4

– Software sets ADxCON. ADON to start AD operation.

– Convert bit 0.

5

1

2

– Sampling starts after discharge period.

TSAMP is described in the “dsPIC30F

Family Reference Manual” (DS70046), Section 17.

– One TAD for end of conversion.

– Begin conversion of next channel.

6

7

8

– Sample for time specified by SAMC<4:0>.

– Convert bit 9.

– Convert bit 8.

3

4

Preliminary

DS70175D-page 273

PIC24H

TABLE 23-35: A/D CONVERSION (10-BIT MODE) TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

AC CHARACTERISTICS

Param

Symbol

No.

Characteristic

Min.

Typ⁽¹⁾

Max.

Units

Conditions

Clock Parameters

AD50 TAD

AD51 tRC

A/D Clock Period⁽²⁾

70

—

ns

TCY = 70 ms, ADxCON3

in default state

A/D Internal RC Oscillator Period

250

—

Conversion Rate

AD55 tCONV

AD56 FCNV

Conversion Time

Throughput Rate

—

12 TAD

—

1.1

—

Msps

—

AD57 TSAMP Sample Time

1 TAD

Timing Parameters

AD60 tPCS

Conversion Start from Sample

—

1.0 TAD

—

Auto-Convert Trigger

(SSRC<2:0> = 111) not

selected

Trigger⁽³⁾

AD61 tPSS

AD62 tCSS

AD63 tDPU

Sample Start from Setting

Sample (SAMP) bit

0.5 TAD

—

0.5 TAD

20

1.5 TAD

—

μs

—

Conversion Completion to

Sample Start (ASAM = 1)⁽³⁾

Time to Stabilize Analog Stage

from A/D Off to A/D On⁽³⁾

—

Note 1: These parameters are characterized but not tested in manufacturing.

2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

3: Characterized by design but not tested.

DS70175D-page 274

Preliminary

PIC24H

FIGURE 23-20:

A/D CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS

(ASAM = 0, SSRC<2:0> = 000)

AD50

ADCLK

Instruction

Execution

Set SAMP

Clear SAMP

SAMP

ch0_dischrg

ch0_samp

eoc

AD61

AD60

TSAMP

AD55

CONV

ADxIF

Buffer(0)

1

2

3

4

5

6

7

8

9

– Software sets ADxCON. SAMP to start sampling.

– Sampling starts after discharge period.

1

2

TSAMP is described in the “dsPIC30F Family Reference Manual” (DS70046), Section 17.

– Software clears ADxCON. SAMP to start conversion.

– Sampling ends, conversion sequence starts.

– Convert bit 11.

3

4

5

6

7

8

9

– Convert bit 10.

– Convert bit 1.

– Convert bit 0.

– One TAD for end of conversion.

Preliminary

DS70175D-page 275

PIC24H

TABLE 23-36: A/D CONVERSION (12-BIT MODE) TIMING REQUIREMENTS)

Standard Operating Conditions: 3.0V to 3.6V

AC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

Param

Symbol

No.

Characteristic

Min.

Typ

Max.

Units

Conditions

Clock Parameters

AD50

AD51

TAD

tRC

A/D Clock Period⁽¹⁾

133

—

ns

Tcy = 133 ns, ADxCON3

in default state

A/D Internal RC Oscillator

Period

250

—

Conversion Rate

AD55

AD56

AD57

tCONV

FCNV

Conversion Time

Throughput Rate

Sample Time

—

14 TAD

ns

ksps

ns

—

500

—

TSAMP

1 TAD

Timing Parameters

AD60

AD61

AD62

AD63

tPCS

tPSS

tCSS

tDPU

Conversion Start from Sample

Trigger

—

0.5 TAD

—

1.0 TAD

—

1.5 TAD

—

ns

μs

—

Sample Start from Setting

Sample (SAMP) bit

—

Conversion Completion to

Sample Start (ASAM = 1)

—

Time to Stabilize Analog Stage

from A/D Off to A/D On

—

20

—

Legend: TBD = To Be Determined

Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures.

DS70175D-page 276

Preliminary

PIC24H

24.0 PACKAGING INFORMATION

24.1 Package Marking Information

64-Lead TQFP (10x10x1 mm)

Example

XXXXXXXXXX

YYWWNNN

PIC24HJ

256GP706

-I/PT

0510017

e

3

100-Lead TQFP (12x12x1 mm)

Example

XXXXXXXXXXXX

YYWWNNN

PIC24HJ256

GP710-I/PT

0510017

e

3

100-Lead TQFP (14x14x1mm)

XXXXXXXXXXXX

YYWWNNN

PIC24HJ256

GP710-I/PF

0510017

e

3

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Preliminary

DS70175D-page 277

PIC24H

24.2 Package Details

The following sections give the technical details of the

packages.

64-Lead Plastic Thin-Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

E

E1

#leads=n1

p

D1

D

2

1

B

n

CH x 45°

α

A

φ

c

A2

L

A1

β

F

Units

Dimension Limits

INCHES

NOM

MILLIMETERS

NOM

64

*

MIN

MAX

MIN

MAX

n

p

Number of Pins

Pitch

64

.020

16

0.50

Pins per Side

n1

A

16

Overall Height

.039

.043

.039

.006

.024

.047

1.00

1.10

1.20

1.05

0.25

0.75

Molded Package Thickness

Standoff

A2

A1

L

.037

.002

.018

.041

.010

.030

0.95

0.05

0.45

1.00

0.15

Foot Length

0.60

Footprint

F

.039 REF.

1.00 REF.

φ

Foot Angle

0

3.5

.472

.394

.007

.009

.035

10

7

0

3.5

12.00

7

Overall Width

E

D

.463

.390

.005

.007

.025

.482

.398

.009

.011

.045

15

11.75

9.90

0.13

0.17

0.64

12.25

10.10

0.23

0.27

1.14

15

Overall Length

Molded Package Width

Molded Package Length

Lead Thickness

Lead Width

12.00

10.00

0.18

0.22

0.89

10

E1

D1

c

B

CH

α

Pin 1 Corner Chamfer

Mold Draft Angle Top

Mold Draft Angle Bottom

5

β

5

10

15

5

10

15

*

Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.

REF: Reference Dimension, usually without tolerance, for information purposes only.

See ASME Y14.5M

JEDEC Equivalent: MS-026

Drawing No. C04-085

Revised 07-22-05

DS70175D-page 278

Preliminary

PIC24H

100-Lead Plastic Thin-Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

E

E1

#leads=n1

p

D1

D

2

1

B

n

CH x 45°

A

α

c

φ

A1

β

A2

L

F

Units

Dimension Limits

INCHES

NOM

MILLIMETERS

*

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

100

.016 BSC

100

0.40 BSC

25

Pins per Side

Overall Height

n1

A

25

.039

.037

.002

.018

.043

.039

.004

.024

.047

1.00

1.10

1.00

0.10

0.60

1.20

Molded Package Thickness

Standoff

A2

A1

L

.041

.006

.030

0.95

0.05

0.45

1.05

0.15

0.75

Foot Length

Footprint (Reference)

Foot Angle

F

φ

.039 REF.

3.5°

.551 BSC

1.00 REF.

3.5°

0°

7°

0°

7°

Overall Width

E

D

14.00 BSC

Overall Length

.551 BSC

.472 BSC

14.00 BSC

12.00 BSC

Molded Package Width

Molded Package Length

Lead Thickness

E1

D1

c

.004

.005

5°

.006

.008

.009

15°

0.09

0.15

0.18

10°

0.20

0.23

15°

Lead Width

B

α

β

.007

10°

0.13

5°

Mold Draft Angle Top

Mold Draft Angle Bottom

5°

15°

5°

10°

15°

*

Controlling Parameter

Notes:

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

See ASME Y14.5M

REF: Reference Dimension, usually without tolerance, for information purposes only.

See ASME Y14.5M

JEDEC Equivalent: MS-026

Drawing No. C04-100

Revised 07-22-05

Preliminary

DS70175D-page 279

PIC24H

100-Lead Plastic Thin-Quad Flatpack (PF) 14x14x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

E

E1

#leads=n1

p

D1

D

B

2

1

α

n

A

φ

A2

c

A1

β

L

F

Units

Dimension Limits

INCHES

NOM

MILLIMETERS

*

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

100

.020 BSC

100

0.50 BSC

25

Pins per Side

n1

A

25

Overall Height

Molded Package Thickness

Standoff

.047

.041

.006

.030

1.20

1.05

0.15

0.75

A2

A1

L

.037

.039

.024

0.95

1.00

.002

.018

0.05

0.45

Foot Length

0.60

Footprint

F

φ

.039 REF

3.5°

.630 BSC

1.00 REF

Foot Angle

0°

7°

0°

3.5°

16.00 BSC

7°

Overall Width

E

D

Overall Length

Molded Package Width

Molded Package Length

Lead Thickness

Lead Width

.630 BSC

.551 BSC

16.00 BSC

14.00 BSC

E1

D1

c

.004

.007

11°

.008

.011

13°

0.09

0.17

11°

0.20

0.27

13°

B

α

β

.009

12°

0.22

12°

Mold Draft Angle Top

Mold Draft Angle Bottom

13°

11°

13°

*

Controlling Parameter

Notes:

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

See ASME Y14.5M

REF: Reference Dimension, usually without tolerance, for information purposes only.

See ASME Y14.5M

JEDEC Equivalent: MS-026

Drawing No. C04-110

Revised 07-21-05

DS70175D-page 280

Preliminary

PIC24H

APPENDIX A: REVISION HISTORY

Revision A (February 2006)

• Initial release of this document

Revision B (March 2006)

• Updated the Configuration Bits Description table

(Table 20.1)

• Updated registers and register maps

• Updated Section 15.0 “Serial Peripheral Inter-

face (SPI)”

• Updated Section 23.0 “Electrical Characteris-

tics”

• Updated pinout diagrams

• Additional minor corrections throughout document

text

Revision C (May 2006)

• Updated Section 23.0 “Electrical Characteris-

tics”

• Updated the Configuration Bits Description table

(Table 20.1)

• Additional minor corrections throughout document

text

Revision D (July 2006)

• Added FBS and FSS Device Configuration regis-

ters (see Table 20-1) and corresponding bit field

descriptions (see Table 20-2). These added regis-

ters replaced the former RESERVED1 and

RESERVED2 registers.

• Added INTTREG Interrupt Control and Status

register. (See Section 6.3 “Interrupt Control

and Status Registers”. See also Register 6-33.)

• Added Core Registers BSRAM and SSRAM (see

Section 3.2.7 “Data Ram Protection Feature”)

• Clarified Fail-Safe Clock Monitor operation (see

Section 8.3 “Fail-Safe Clock Monitor (FSCM)”)

• Updated COSC<2:0> and NOSC<2:0> bit config-

urations in OSCCON register (see Register 8-1)

• Updated CLKDIV register bit configurations (see

Register 8-2)

• Added Word Write Cycle Time parameter (TWW)

to Program Flash Memory (see Table 23-11)

• Noted exceptions to Absolute Maximum Ratings

on I/O pin output current (see Section 23.0

“Electrical Characteristics”)

• Added ADC2 Event Trigger for Timer4/5

(Section 12.0 “Timer2/3, Timer4/5, Timer6/7

and Timer8/9”)

• Corrected mislabeled I2COV bit in I2CxSTAT

register (see Register 16-2)

• Removed AD26a, AD27a, AD28a, AD26b, AD27b

and AD28b from Table 23-34 (A/D Module)

• Revised Table 23-36 (AD63)

Preliminary

DS70175D-page 281

PIC24H

NOTES:

DS70175D-page 282

Preliminary

PIC24H

INDEX

A

D

A/D Converter ................................................................... 209

DMA.......................................................................... 209

Initialization ............................................................... 209

Key Features............................................................. 209

AC Characteristics ............................................................ 250

Internal RC Accuracy................................................ 252

Load Conditions........................................................ 250

ADC Module

ADC1 Register Map.................................................... 37

ADC2 Register Map.................................................... 37

Alternate Vector Table (AIVT)............................................. 67

Arithmetic Logic Unit (ALU)................................................. 23

Assembler

Data Address Space........................................................... 27

Alignment.................................................................... 27

Memory Map for PIC24H Devices with 16 KBs RAM. 29

Memory Map for PIC24H Devices with 8 KBs RAM... 28

Near Data Space........................................................ 27

Software Stack ........................................................... 48

Width .......................................................................... 27

DC Characteristics............................................................ 244

I/O Pin Input Specifications ...................................... 248

I/O Pin Output Specifications.................................... 249

Idle Current (IDOZE) .................................................. 247

Idle Current (IIDLE).................................................... 246

Operating Current (IDD) ............................................ 245

Power-Down Current (IPD)........................................ 246

Program Memory...................................................... 249

Temperature and Voltage Specifications.................. 244

Development Support....................................................... 239

DMA

MPASM Assembler................................................... 240

Automatic Clock Stretch.................................................... 163

Receive Mode........................................................... 163

Transmit Mode.......................................................... 163

B

Interrupts and Traps ................................................. 116

Request Source Selection........................................ 116

DMA Module

Block Diagrams

16-bit Timer1 Module................................................ 139

A/D Module ....................................................... 210, 211

Connections for On-Chip Voltage Regulator............. 227

ECAN Module ........................................................... 180

Input Capture ............................................................ 147

Output Compare ....................................................... 151

PIC24H ....................................................................... 14

PIC24H CPU Core...................................................... 18

PIC24H Oscillator System Diagram.......................... 127

PIC24H PLL.............................................................. 129

Reset System.............................................................. 61

Shared Port Structure ............................................... 137

SPI ............................................................................ 154

Timer2 (16-bit) .......................................................... 143

Timer2/3 (32-bit) ....................................................... 142

UART ........................................................................ 171

Watchdog Timer (WDT)............................................ 228

DMA Register Map ..................................................... 38

DMAC Operating Modes................................................... 114

Addressing................................................................ 115

Byte or Word Transfer .............................................. 115

Continuous or One-Shot........................................... 116

Manual Transfer ....................................................... 116

Null Data Peripheral Write........................................ 115

Ping-Pong................................................................. 116

Transfer Direction..................................................... 115

DMAC Registers............................................................... 114

DMAxCNT ................................................................ 114

DMAxCON................................................................ 114

DMAxPAD ................................................................ 114

DMAxREQ................................................................ 114

DMAxSTA................................................................. 114

DMAxSTB................................................................. 114

C

E

C Compilers

ECAN Module

MPLAB C18 .............................................................. 240

MPLAB C30 .............................................................. 240

Clock Switching................................................................. 134

Enabling.................................................................... 134

Sequence.................................................................. 134

Code Examples

DMA Sample Initialization Method............................ 117

Erasing a Program Memory Page............................... 58

Initiating a Programming Sequence............................ 59

Loading Write Buffers ................................................. 59

Port Write/Read ........................................................ 138

PWRSAV Instruction Syntax..................................... 135

Code Protection ........................................................ 223, 229

Configuration Bits.............................................................. 223

Description (Table).................................................... 224

Configuration Register Map .............................................. 223

Configuring Analog Port Pins............................................ 138

CPU

Baud Rate Setting .................................................... 184

ECAN1 Register Map (C1CTRL1.WIN = 0 or 1)......... 39

ECAN1 Register Map (C1CTRL1.WIN = 0)................ 40

ECAN1 Register Map (C1CTRL1.WIN = 1)................ 40

ECAN2 Register Map (C2CTRL1.WIN = 0 or 1)......... 42

ECAN2 Register Map (C2CTRL1.WIN = 0)................ 42

ECAN2 Register Map (C2CTRL1.WIN = 1)................ 43

Frame Types ............................................................ 179

Message Reception.................................................. 181

Message Transmission............................................. 183

Modes of Operation.................................................. 181

Overview................................................................... 179

Electrical Characteristics .................................................. 243

AC............................................................................. 250

Enhanced CAN Module .................................................... 179

Equations

A/D Conversion Clock Period................................... 212

Calculating the PWM Period..................................... 150

Calculation for Maximum PWM Resolution .............. 150

Device Operating Frequency.................................... 128

FOSC Calculation..................................................... 128

Relationship Between Device and

Control Register.......................................................... 20

CPU Clocking System....................................................... 128

PLL Configuration ..................................................... 128

Selection ................................................................... 128

Sources..................................................................... 128

Customer Change Notification Service ............................. 287

Customer Support............................................................. 287

SPI Clock Speed .............................................. 156

Serial Clock Rate...................................................... 161

Preliminary

DS70175D-page 283

PIC24H

Time Quantum for Clock Generation ........................185

UART Baud Rate with BRGH = 0 .............................172

UART Baud Rate with BRGH = 1 .............................172

XT with PLL Mode Example......................................129

Errata ..................................................................................11

IFSx ............................................................................ 71

INTCON1.................................................................... 71

INTCON2.................................................................... 71

INTTREG.................................................................... 71

IPCx............................................................................ 71

Interrupt Setup Procedures............................................... 111

Initialization............................................................... 111

Interrupt Disable ....................................................... 111

Interrupt Service Routine.......................................... 111

Trap Service Routine................................................ 111

Interrupt Vector Table (IVT)................................................ 67

Interrupts Coincident with Power Save Instructions ......... 136

F

Flash Program Memory.......................................................55

Control Registers ........................................................56

Operations ..................................................................56

Programming Algorithm ..............................................58

RTSP Operation..........................................................56

Table Instructions........................................................55

Flexible Configuration .......................................................223

FSCM

J

JTAG Boundary Scan Interface........................................ 223

Delay for Crystal and PLL Clock Sources...................65

Device Resets.............................................................65

M

Memory Organization ......................................................... 25

Microchip Internet Web Site.............................................. 287

Modes of Operation

I

I/O Ports............................................................................137

Parallel I/O (PIO).......................................................137

Write/Read Timing ....................................................138

Disable...................................................................... 181

Initialization............................................................... 181

Listen All Messages.................................................. 181

Listen Only................................................................ 181

Loopback .................................................................. 181

Normal Operation ..................................................... 181

MPLAB ASM30 Assembler, Linker, Librarian................... 240

MPLAB ICD 2 In-Circuit Debugger ................................... 241

MPLAB ICE 2000 High-Performance Universal

2

I C

Addresses.................................................................163

Baud Rate Generator................................................161

General Call Address Support ..................................163

Interrupts...................................................................161

IPMI Support.............................................................163

Master Mode Operation

Clock Arbitration................................................164

Multi-Master Communication, Bus

In-Circuit Emulator.................................................... 241

MPLAB ICE 4000 High-Performance Universal

Collision and Bus Arbitration.....................164

In-Circuit Emulator.................................................... 241

MPLAB Integrated Development Environment Software.. 239

MPLAB PM3 Device Programmer .................................... 241

MPLINK Object Linker/MPLIB Object Librarian................ 240

Multi-Bit Data Shifter........................................................... 23

Operating Modes ......................................................161

Registers...................................................................161

Slave Address Masking ............................................163

Slope Control ............................................................164

Software Controlled Clock Stretching (STREN = 1)..163

N

2

I C Module

NVM Module

I2C1 Register Map ......................................................35

I2C2 Register Map ......................................................35

In-Circuit Debugger...........................................................229

In-Circuit Emulation...........................................................223

In-Circuit Serial Programming (ICSP) ....................... 223, 229

Infrared Support

Built-in IrDA Encoder and Decoder...........................173

External IrDA, IrDA Clock Output..............................173

Input Capture

Register Map .............................................................. 47

O

Open-Drain Configuration................................................. 138

Output Compare ............................................................... 149

Registers .................................................................. 152

P

Packaging......................................................................... 277

Details....................................................................... 278

Marking..................................................................... 277

Peripheral Module Disable (PMD) .................................... 136

PICSTART Plus Development Programmer..................... 242

Pinout I/O Descriptions (table)............................................ 15

PMD Module

Register Map .............................................................. 47

POR and Long Oscillator Start-up Times ........................... 65

PORTA

Register Map .............................................................. 45

PORTB

Register Map .............................................................. 45

PORTC

Register Map .............................................................. 45

PORTD

Register Map .............................................................. 45

PORTE

Registers...................................................................148

Input Change Notification Module.....................................138

Instruction Addressing Modes.............................................48

File Register Instructions ............................................48

Fundamental Modes Supported..................................49

MCU Instructions ........................................................48

Move and Accumulator Instructions............................49

Other Instructions........................................................49

Instruction Set

Overview ...................................................................234

Summary...................................................................231

Instruction-Based Power-Saving Modes...........................135

Idle ............................................................................136

Sleep.........................................................................135

Internal RC Oscillator

Use with WDT...........................................................228

Internet Address................................................................287

Interrupt Control and Status Registers................................71

IECx ............................................................................71

Register Map .............................................................. 46

DS70175D-page 284

Preliminary

PIC24H

PORTF

Register Map............................................................... 46

PORTG

Register Map............................................................... 46

Power-Saving Features .................................................... 135

Clock Frequency and Switching................................ 135

Program Address Space..................................................... 25

Construction................................................................ 50

Data Access from Program Memory

CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 203

CiTRBnDLC (ECAN Buffer n Data Length Control).. 206

CiTRBnEID (ECAN Buffer n Extended Identifier)..... 205

CiTRBnSID (ECAN Buffer n Standard Identifier)...... 205

CiTRBnSTAT (ECAN Receive Buffer n Status)........ 207

CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 204

CiVEC (ECAN Interrupt Code) ................................. 188

CLKDIV (Clock Divisor) ............................................ 131

CORCON (Core Control)...................................... 22, 72

DMACS0 (DMA Controller Status 0) ........................ 122

DMACS1 (DMA Controller Status 1) ........................ 124

DMAxCNT (DMA Channel x Transfer Count)........... 121

DMAxCON (DMA Channel x Control)....................... 118

DMAxPAD (DMA Channel x Peripheral Address) .... 121

DMAxREQ (DMA Channel x IRQ Select)................. 119

DMAxSTA (DMA Channel x RAM Start Address A). 120

DMAxSTB (DMA Channel x RAM Start Address B). 120

DSADR (Most Recent DMA RAM Address) ............. 125

I2CxCON (I2Cx Control)........................................... 165

I2CxMSK (I2Cx Slave Mode Address Mask)............ 169

I2CxSTAT (I2Cx Status)........................................... 167

ICxCON (Input Capture x Control)............................ 148

IEC0 (Interrupt Enable Control 0)............................... 84

IEC1 (Interrupt Enable Control 1)............................... 86

IEC2 (Interrupt Enable Control 2)............................... 88

IEC3 (Interrupt Enable Control 3)............................... 90

IEC4 (Interrupt Enable Control 4)............................... 91

IFS0 (Interrupt Flag Status 0)..................................... 76

IFS1 (Interrupt Flag Status 1)..................................... 78

IFS2 (Interrupt Flag Status 2)..................................... 80

IFS3 (Interrupt Flag Status 3)..................................... 82

IFS4 (Interrupt Flag Status 4)..................................... 83

INTCON1 (Interrupt Control 1) ................................... 73

INTCON2 (Interrupt Control 2) ................................... 75

IPC0 (Interrupt Priority Control 0)............................... 92

IPC1 (Interrupt Priority Control 1)............................... 93

IPC10 (Interrupt Priority Control 10)......................... 102

IPC11 (Interrupt Priority Control 11)......................... 103

IPC12 (Interrupt Priority Control 12)......................... 104

IPC13 (Interrupt Priority Control 13)......................... 105

IPC14 (Interrupt Priority Control 14)......................... 106

IPC15 (Interrupt Priority Control 15)......................... 107

IPC16 (Interrupt Priority Control 16)................. 108, 110

IPC17 (Interrupt Priority Control 17)......................... 109

IPC2 (Interrupt Priority Control 2)............................... 94

IPC3 (Interrupt Priority Control 3)............................... 95

IPC4 (Interrupt Priority Control 4)............................... 96

IPC5 (Interrupt Priority Control 5)............................... 97

IPC6 (Interrupt Priority Control 6)............................... 98

IPC7 (Interrupt Priority Control 7)............................... 99

IPC8 (Interrupt Priority Control 8)............................. 100

IPC9 (Interrupt Priority Control 9)............................. 101

NVMCON (Flash Memory Control)............................. 57

OCxCON (Output Compare x Control)..................... 152

OSCCON (Oscillator Control)................................... 130

OSCTUN (FRC Oscillator Tuning)............................ 133

PLLFBD (PLL Feedback Divisor) ............................. 132

RCON (Reset Control)................................................ 62

SPIxCON1 (SPIx Control 1) ..................................... 158

SPIxCON2 (SPIx Control 2) ..................................... 159

SPIxSTAT (SPIx Status and Control)....................... 157

SR (CPU Status) .................................................. 20, 72

T1CON (Timer1 Control) .......................................... 140

TxCON (T2CON, T4CON, T6CON or

Using Program Space Visibility........................... 53

Data Access from Program Memory Using

Table Instructions ............................................... 52

Data Access from, Address Generation...................... 51

Memory Map............................................................... 25

Table Read Instructions

TBLRDH ............................................................. 52

TBLRDL .............................................................. 52

Visibility Operation ...................................................... 53

Program Memory

Interrupt Vector ........................................................... 26

Organization................................................................ 26

Reset Vector ............................................................... 26

Pulse-Width Modulation Mode .......................................... 150

PWM

Duty Cycle................................................................. 150

Period........................................................................ 150

R

Reader Response............................................................. 288

Registers

ADxCHS0 (ADCx Input Channel 0 Select................. 219

ADxCHS123 (ADCx Input Channel 1, 2, 3 Select) ... 218

ADxCON1 (ADCx Control 1)..................................... 213

ADxCON2 (ADCx Control 2)..................................... 215

ADxCON3 (ADCx Control 3)..................................... 216

ADxCON4 (ADCx Control 4)..................................... 217

ADxCSSH (ADCx Input Scan Select High)............... 220

ADxCSSL (ADCx Input Scan Select Low) ................ 220

ADxPCFGH (ADCx Port Configuration High) ........... 221

ADxPCFGL (ADCx Port Configuration Low)............. 221

CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer)........... 196

CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer)........... 197

CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer)......... 197

CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer)....... 198

CiCFG1 (ECAN Baud Rate Configuration 1) ............ 194

CiCFG2 (ECAN Baud Rate Configuration 2) ............ 195

CiCTRL1 (ECAN Control 1) ...................................... 186

CiCTRL2 (ECAN Control 2) ...................................... 187

CiEC (ECAN Transmit/Receive Error Count)............ 193

CiFCTRL (ECAN FIFO Control)................................ 189

CiFEN1 (ECAN Acceptance Filter Enable)............... 196

CiFIFO (ECAN FIFO Status)..................................... 190

CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection)...... 200

CiINTE (ECAN Interrupt Enable) .............................. 192

CiINTF (ECAN Interrupt Flag)................................... 191

CiRXFnEID (ECAN Acceptance Filter n

Extended Identifier)........................................... 199

CiRXFnSID (ECAN Acceptance Filter n

Standard Identifier) ........................................... 199

CiRXFUL1 (ECAN Receive Buffer Full 1)................. 202

CiRXFUL2 (ECAN Receive Buffer Full 2)................. 202

CiRXMnEID (ECAN Acceptance Filter Mask n

Extended Identifier)........................................... 201

CiRXMnSID (ECAN Acceptance Filter Mask n

Standard Identifier) ........................................... 201

CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 203

T8CON Control)................................................ 144

Preliminary

DS70175D-page 285

PIC24H

TyCON (T3CON, T5CON, T7CON or

Input Capture............................................................ 258

Timing Specifications

T9CON Control)................................................145

UxMODE (UARTx Mode)..........................................174

UxSTA (UARTx Status and Control).........................176

Reset

Clock Source Selection...............................................64

Special Function Register Reset States .....................65

Times ..........................................................................64

Reset Sequence..................................................................67

Resets.................................................................................61

10-bit A/D Conversion Requirements....................... 274

12-bit A/D Conversion Requirements....................... 276

CAN I/O Requirements............................................. 269

I2Cx Bus Data Requirements (Master Mode)........... 266

I2Cx Bus Data Requirements (Slave Mode)............. 268

Output Compare Requirements................................ 258

PLL Clock ................................................................. 252

Reset, Watchdog Timer, Oscillator Start-up

Timer, Power-up Timer and Brown-out

S

Reset Requirements......................................... 255

Simple OC/PWM Mode Requirements ..................... 259

SPIx Master Mode (CKE = 0) Requirements............ 260

SPIx Master Mode (CKE = 1) Requirements............ 261

SPIx Slave Mode (CKE = 0) Requirements.............. 262

SPIx Slave Mode (CKE = 1) Requirements.............. 264

Timer1 External Clock Requirements....................... 256

Timer2, Timer4, Timer6 and Timer8 External

Serial Peripheral Interface (SPI) .......................................153

Setup for Continuous Output Pulse Generation................149

Setup for Single Output Pulse Generation........................149

Software Simulator (MPLAB SIM).....................................240

Software Stack Pointer, Frame Pointer

CALL Stack Frame......................................................48

Special Features ...............................................................223

SPI

Master, Frame Master Connection ...........................155

Master/Slave Connection..........................................155

Slave, Frame Master Connection .............................156

Slave, Frame Slave Connection ...............................156

SPI Module

Clock Requirements ......................................... 257

Timer3, Timer5, Timer7 and Timer9 External

Clock Requirements ......................................... 257

U

UART

Operating Function Description ................................153

SPI1 Register Map......................................................36

SPI2 Register Map......................................................36

Symbols Used in Opcode Descriptions.............................232

System Control

Baud Rate

Generator (BRG) .............................................. 172

Break and Sync Transmit Sequence ........................ 173

Flow Control Using UxCTS and UxRTS Pins ........... 173

Receiving in 8-bit or 9-bit Data Mode ....................... 173

Transmitting in 8-bit Data Mode................................ 173

Transmitting in 9-bit Data Mode................................ 173

UART Module

Register Map...............................................................47

T

Temperature and Voltage Specifications

UART1 Register Map.................................................. 35

UART2 Register Map.................................................. 36

AC .............................................................................250

Timer1...............................................................................139

Timer2/3, Timer4/5, Timer6/7 and Timer8/9 .....................141

Timing Characteristics

V

Voltage Regulator (On-Chip) ............................................ 227

CLKO and I/O ...........................................................253

Timing Diagrams

W

Watchdog Timer (WDT)............................................ 223, 228

Programming Considerations ................................... 228

WWW Address ................................................................. 287

WWW, On-Line Support ..................................................... 11

10-bit A/D Conversion (CHPS = 01, SIMSAM = 0,

ASAM = 0, SSRC = 000) ..................................272

^{10-bit A/D Conversion (CHPS}= 01, SIMSAM =

0, ASAM = 1, SSRC = 111, SAMC =

00001)^{...........................................................273}

12-bit A/D Conversion (ASAM = 0, SSRC = 000) .....275

CAN I/O.....................................................................269

ECAN Bit...................................................................184

External Clock...........................................................251

I2Cx Bus Data (Master Mode) ..................................265

I2Cx Bus Data (Slave Mode) ....................................267

I2Cx Bus Start/Stop Bits (Master Mode)...................265

I2Cx Bus Start/Stop Bits (Slave Mode).....................267

Input Capture (CAPx)................................................258

OC/PWM...................................................................259

Output Compare (OCx).............................................258

Reset, Watchdog Timer, Oscillator Start-up

Timer and Power-up Timer ...............................254

SPIx Master Mode (CKE = 0)....................................259

SPIx Master Mode (CKE = 1)....................................260

SPIx Slave Mode (CKE = 0)......................................261

SPIx Slave Mode (CKE = 1)......................................263

Timer1, 2, 3, 4, 5, 6, 7, 8, 9 External Clock...............256

Timing Requirements

CLKO and I/O ...........................................................253

External Clock...........................................................251

DS70175D-page 286

Preliminary

PIC24H

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following informa-

tion:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata, appli-

cation notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

Customers should contact their distributor, representa-

tive or field application engineer (FAE) for support.

Local sales offices are also available to help custom-

ers. A listing of sales offices and locations is included

in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

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• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of Micro-

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CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a spec-

ified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change Notifi-

cation and follow the registration instructions.

Preliminary

DS70175D-page 287

PIC24H

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

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City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

PIC24H

DS70175D

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS70175D-page 288

Preliminary

PIC24H

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PIC 24 HJ 256 GP6 10 T I / PT - XXX

a)

b)

PIC24HJ256GP210I/PT:

General-purpose PIC24H, 256 KB program

memory, 100-pin, Industrial temp.,

TQFP package.

Microchip Trademark

Architecture

PIC24HJ64GP506I/PT-ES:

Flash Memory Family

Program Memory Size (KB)

Product Group

General-purpose PIC24H, 64 KB program

memory, 64-pin, Industrial temp.,

TQFP package, Engineering Sample.

Pin Count

Tape and Reel Flag (if applicable)

Temperature Range

Package

Pattern

Architecture:

24

=

16-bit Microcontroller

Flash Memory Family: HJ

Flash program memory, 3.3V, High-speed

Product Group:

GP2

=

General purpose family

GP3

GP5

GP6

Pin Count:

06

10

=

64-pin

100-pin

Temperature Range:

Package:

I

=

-40°C to +85°C (Industrial)

PT

PF

=

10x10 or 12x12 mmTQFP (Thin Quad Flatpack)

14x14 mmTQFP (Thin Quad Flatpack)

Pattern:

Three-digit QTP, SQTP, Code or Special Requirements

(blank otherwise)

ES

=

Engineering Sample

Preliminary

DS70175D-page 289

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Australia - Sydney

Tel: 61-2-9868-6733

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Web Address:

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Tel: 86-10-8528-2100

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Fax: 86-757-2839-5571

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Detroit

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

San Jose

Mountain View, CA

Tel: 650-215-1444

Fax: 650-961-0286

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

06/08/06

DS70175D-page 290

Preliminary


型号：	PIC24H
厂家：	MICROCHIP
描述：	High-Performance, 16-bit Microcontrollers 微控制器
文件：	总290页 (文件大小：4590K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC24H [MICROCHIP]

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