PIC32MX795F512LT-80I/PT [MICROCHIP]
32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100, 12 X 12 MM, 1 MM HEIGHT, LEAD FREE, PLASTIC, TQFP-100;
| 型号： | PIC32MX795F512LT-80I/PT |
| 厂家： | 
MICROCHIP |
| 描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100, 12 X 12 MM, 1 MM HEIGHT, LEAD FREE, PLASTIC, TQFP-100 时钟 微控制器 外围集成电路 |
| 文件： | 总236页 (文件大小：2088K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC32MX5XX/6XX/7XX
Family Data Sheet
High-Performance, USB, CAN and Ethernet
32-Bit Flash Microcontrollers
2010 Microchip Technology Inc.
Preliminary
DS61156C
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
32
PIC logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-037-9
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS61156C-page 2
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
High-Performance, USB, CAN and Ethernet
32-Bit Flash Microcontrollers
High-Performance 32-Bit RISC CPU:
Peripheral Features (Continued):
• MIPS32® M4K™ 32-bit core with 5-stage pipeline
• 80 MHz maximum frequency
• Internal 8 MHz and 32 kHz oscillators
• Six UART modules with:
• 1.56 DMIPS/MHz (Dhrystone 2.1) performance
at zero Wait state Flash access
- RS-232, RS-485 and LIN 1.2 support
- IrDA® with on-chip hardware encoder and
• Single-cycle multiply and high-performance divide
unit
decoder
• Up to four SPI modules
• Up to five I2C™ modules
• MIPS16e™ mode for up to 40% smaller code size
• Two sets of 32 core register files (32-bit) to reduce
interrupt latency
• Separate PLLs for CPU and USB clocks
• Parallel Master and Slave Port (PMP/PSP) with
8-bit and 16-bit data, and up to 16 address lines
• Prefetch Cache module to speed execution from
Flash
• Hardware Real-Time Clock/Calendar (RTCC)
• Five 16-bit Timers/Counters (two 16-bit pairs
combine to create two 32-bit timers)
Microcontroller Features:
• Five Capture inputs
• Operating voltage range of 2.3V to 3.6V
• Five Compare/PWM outputs
• Five external interrupt pins
• 256K to 512K Flash memory (plus an additional
12 KB of Boot Flash)
• 64K to 128K SRAM memory
• Pin-compatible with most PIC24/dsPIC® devices
• High-speed I/O pins capable of toggling at up to
80 MHz
• High-current sink/source (18 mA/18 mA) on
all I/O pins
• Multiple power management modes
• Multiple interrupt vectors with individually
programmable priority
• Configurable open-drain output on digital I/O pins
• Fail-Safe Clock Monitor mode
Debug Features:
• Configurable Watchdog Timer with on-chip
Low-Power RC oscillator for reliable operation
• Two programming and debugging Interfaces:
- 2-wire interface with unintrusive access and
real-time data exchange with application
Peripheral Features:
- 4-wire MIPS® standard enhanced JTAG
interface
• Atomic Set, Clear and Invert operation on select
peripheral registers
• Unintrusive hardware-based instruction trace
• 8-channel hardware DMA with automatic data
size detection
• IEEE Standard 1149.2 compatible (JTAG)
boundary scan
• USB 2.0-compliant full-speed device and
On-The-Go (OTG) controller:
Analog Features:
- Dedicated DMA channels
• 10/100 Mbps Ethernet MAC with MII and RMII
interface:
• Up to 16-channel, 10-bit Analog-to-Digital
Converter:
- Dedicated DMA channels
• CAN module:
- 1 Msps conversion rate
- Conversion available during Sleep and Idle
• Two Analog Comparators
- 2.0B Active with DeviceNet™ addressing
support
• 5V tolerant input pins (digital pins only)
- Dedicated DMA channels
• 3 MHz to 25 MHz crystal oscillator
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 3
PIC32MX5XX/6XX/7XX
TABLE 1:
PIC32MX FEATURES
PT,
MR
(1)
PIC32MX575F256H 64 256 + 12
PIC32MX675F256H 64 256 + 12
PIC32MX775F256H 64 256 + 12
PIC32MX575F512H 64 512 + 12
PIC32MX675F512H 64 512 + 12
PIC32MX695F512H 64 512 + 12
PIC32MX775F512H 64 512 + 12
PIC32MX795F512H 64 512 + 12
64
64
1
1
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
0
2
1
0
0
2
2
5/5/5
5/5/5
5/5/5
5/5/5
5/5/5
5/5/5
5/5/5
5/5/5
8/4
8/4
8/8
8/4
8/4
8/4
8/8
8/8
6
6
6
6
6
6
6
6
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
16
16
16
16
16
16
16
16
2
2
2
2
2
2
2
2
Yes Yes No
Yes Yes No
Yes Yes No
Yes Yes No
Yes Yes No
Yes Yes No
Yes Yes No
Yes Yes No
PT,
MR
(1)
(1)
(1)
(1)
(1)
(1)
(1)
PT,
MR
64
PT,
MR
64
PT,
MR
64
PT,
MR
128
64
PT,
MR
PT,
MR
128
PT,
(1)
(1)
(1)
(1)
PIC32MX575F256L 100 256 + 12
PIC32MX675F256L 100 256 + 12
PIC32MX775F256L 100 256 + 12
PIC32MX575F512L 100 512 + 12
PIC32MX675F512L 100 512 + 12
64
64
1
1
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
0
2
1
0
0
2
2
5/5/5
5/5/5
5/5/5
5/5/5
5/5/5
5/5/5
5/5/5
5/5/5
8/4
8/4
8/8
8/4
8/4
8/4
8/8
8/8
6
6
6
6
6
6
6
6
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
16
16
16
16
16
16
16
16
2
2
2
2
2
2
2
2
Yes Yes Yes PF,
BG
PT,
Yes Yes Yes PF,
BG
PT,
Yes Yes Yes PF,
BG
64
PT,
Yes Yes Yes PF,
BG
64
PT,
Yes Yes Yes PF,
BG
(1)
(1)
64
PT,
Yes Yes Yes PF,
BG
512 + 12
PIC32MX695F512L 100
128
64
PT,
Yes Yes Yes PF,
BG
(1)
(1)
PIC32MX775F512L 100 512 + 12
PIC32MX795F512L 100 512 + 12
PT,
Yes Yes Yes PF,
BG
128
Legend:
PF, PT = TQFP
MR = QFN
BG = XBGA
Note 1: This device features 12 KB boot Flash memory.
2: CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more
information.
2
3: Some pins between the UART, SPI and I C modules may be shared. Refer to the “Pin Diagrams” section for more
information.
4: Refer to Section 32.0 “Packaging Information” for detailed information.
DS61156C-page 4
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams
64-Pin QFN
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PMD5/RE5
PMD6/RE6
PMD7/RE7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48 SOSCO/T1CK/CN0/RC14
47 SOSCI/CN1/RC13
OC1/INT0/RD0
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
MCLR
IC4/PMCS1/PMA14/INT4/RD11
SCL1/IC3/PMCS2/PMA15/INT3/RD10
SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9
RTCC/IC1/INT1/RD8
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
Vss
PIC32MX575F256H
PIC32MX575F512H
VSS
OSC2/CLKO/RC15
V
DD
OSC1/CLKI/RC12
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
V
DD
D+/RG2
D-/RG3
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
VUSB
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
V
BUS
USBID/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 5
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin QFN
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SOSCO/T1CK/CN0/RC14
ETXEN/PMD5/RE5
ETXD0/PMD6/RE6
1
2
SOSCI/CN1/RC13
OC1/INT0/RD0
ETXD1/PMD7/RE7
3
ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9
RTCC/AERXD1/ETXD3/IC1/INT1/RD8
Vss
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
4
5
6
MCLR
7
PIC32MX675F256H
PIC32MX675F512H
PIC32MX695F512H
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
8
OSC2/CLKO/RC15
VSS
9
OSC1/CLKI/RC12
VDD
10
11
12
13
14
15
16
VDD
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
D+/RG2
D-/RG3
AN3/C2IN+/CN5/RB3
VUSB
AN2/C2IN-/CN4/RB2
VBUS
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
USBID/RF3
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
DS61156C-page 6
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin QFN
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
SOSCO/T1CK/CN0/RC14
ETXEN/PMD5/RE5
ETXD0/PMD6/RE6
1
2
SOSCI/CN1/RC13
47
46
45
44
43
42
41
40
39
38
37
36
35
34
OC1/INT0/RD0
ETXD1/PMD7/RE7
3
ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9
RTCC/AERXD1/ETXD3/IC1/INT1/RD8
Vss
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
4
5
6
PIC32MX775F256H
PIC32MX775F512H
PIC32MX795F512H
MCLR
7
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
8
OSC2/CLKO/RC15
VSS
9
OSC1/CLKI/RC12
VDD
10
11
12
13
14
15
16
VDD
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
D+/RG2
D-/RG3
AN3/C2IN+/CN5/RB3
VUSB
AN2/C2IN-/CN4/RB2
VBUS
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
33 USBID/RF3
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to
VSS externally.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 7
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin TQFP
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PMD5/RE5
PMD6/RE6
1
2
3
48 SOSCO/T1CK/CN0/RC14
47 SOSCI/CN1/RC13
46 OC1/INT0/RD0
PMD7/RE7
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
4
5
6
7
8
9
10
11
12
13
14
15
16
IC4/PMCS1/PMA14/INT4/RD11
SCL1/IC3/PMCS2/PMA15/INT3/RD10
SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9
RTCC/IC1/INT1/RD8
45
44
43
42
41
40
39
38
37
36
35
34
33
MCLR
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
Vss
PIC32MX575F256H
PIC32MX575F512H
VSS
OSC2/CLKO/RC15
VDD
OSC1/CLKI/RC12
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
VDD
D+/RG2
D-/RG3
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
VUSB
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
VBUS
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
USBID/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DS61156C-page 8
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin TQFP
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SOSCO/T1CK/CN0/RC14
ETXEN/PMD5/RE5
ETXD0/PMD6/RE6
1
2
SOSCI/CN1/RC13
OC1/INT0/RD0
ETXD1/PMD7/RE7
3
ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9
RTCC/AERXD1/ETXD3/IC1/INT1/RD8
Vss
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
4
5
6
MCLR
7
PIC32MX675F256H
PIC32MX675F512H
PIC32MX695F512H
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
8
OSC2/CLKO/RC15
VSS
9
OSC1/CLKI/RC12
VDD
10
11
12
13
14
15
16
VDD
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
D+/RG2
D-/RG3
AN3/C2IN+/CN5/RB3
VUSB
AN2/C2IN-/CN4/RB2
VBUS
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
USBID/RF3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 9
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin TQFP
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SOSCO/T1CK/CN0/RC14
ETXEN/PMD5/RE5
ETXD0/PMD6/RE6
1
2
SOSCI/CN1/RC13
OC1/INT0/RD0
ETXD1/PMD7/RE7
3
ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9
RTCC/AERXD1/ETXD3/IC1/INT1/RD8
Vss
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
4
5
6
MCLR
7
PIC32MX775F256H
PIC32MX775F512H
PIC32MX795F512H
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
8
OSC2/CLKO/RC15
VSS
9
OSC1/CLKI/RC12
VDD
10
11
12
13
14
15
16
V
DD
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
D+/RG2
D-/RG3
AN3/C2IN+/CN5/RB3
VUSB
AN2/C2IN-/CN4/RB2
V
BUS
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
USBID/RF3
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DS61156C-page 10
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
100-Pin TQFP
= Pins are up to 5V tolerant
RG15
VSS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
VDD
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
2
PMD5/RE5
PMD6/RE6
3
SDO1/OC1/INT0/RD0
IC4/PMCS1/PMA14/RD11
SCK1/IC3/PMCS2/PMA15/RD10
SS1/IC2/RD9
4
PMD7/RE7
5
T2CK/RC1
6
T3CK/RC2
7
T4CK/RC3
RTCC/IC1/RD8
8
T5CK/SDI1/RC4
SDA1/INT4/RA15
9
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
MCLR
SCL1/INT3/RA14
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
OSC2/CLKO/RC15
OSC1/CLKI/RC12
PIC32MX575F512L
PIC32MX575F256L
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
VDD
VSS
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
D+/RG2
VDD
TMS/RA0
INT1/RE8
INT2/RE9
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/CN3/RB1
PGED1/AN0/CN2/RB0
D-/RG3
VUSB
VBUS
SCL1A/SDO1A/U1ATX/RF8
SDA1A/SDI1A/U1ARX/RF2
USBID/RF3
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 11
Pin Diagrams (Continued)
100-Pin TQFP
= Pins are up to 5V tolerant
V
SS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
AERXERR/RG15
1
VDD
2
SDO1/OC1/INT0/RD0
PMD5/RE5
PMD6/RE6
3
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
SCK1/IC3/PMCS2/PMA15/RD10
PIC32MX675F256L
PIC32MX675F512L
PIC32MX695F512L
4
PMD7/RE7
5
SS1/IC2/RD9
T2CK/RC1
6
RTCC/EMDIO/AEMDIO/IC1/RD8
AETXEN/SDA1/INT4/RA15
AETXCLK/SCL1/INT3/RA14
T3CK/RC2
7
T4CK/RC3
8
T5CK/SDI1/RC4
9
VSS
ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
OSC2/CLKO/RC15
OSC1/CLKI/RC12
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
MCLR
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
D+/RG2
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
VSS
VDD
TMS/RA0
AERXD0/INT1/RE8
D-/RG3
AERXD1/INT2/RE9
VUSB
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
VBUS
SCL1A/SDO1A/U1ATX/RF8
SDA1A/SDI1A/U1ARX/RF2
USBID/RF3
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/CN3/RB1
PGED1/AN0/CN2/RB0
Pin Diagrams (Continued)
100-Pin TQFP
= Pins are up to 5V tolerant
V
SS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
SDO1/OC1/INT0/RD0
AERXERR/RG15
1
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
SCK1/IC3/PMCS2/PMA15/RD10
VDD
2
PMD5/RE5
PMD6/RE6
3
SS1/IC2/RD9
PIC32MX775F256L
PIC32MX775F512L
PIC32MX795F512L
4
RTCC/EMDIO/AEMDIO/IC1/RD8
AETXEN/SDA1/INT4/RA15
AETXCLK/SCL1/INT3/RA14
PMD7/RE7
5
T2CK/RC1
6
T3CK/AC2TX/RC2
T4CK/AC2RX/RC3
T5CK/SDI1/RC4
7
VSS
8
OSC2/CLKO/RC15
OSC1/CLKI/RC12
9
ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
D+/RG2
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
MCLR
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
VSS
VDD
D-/RG3
TMS/RA0
AERXD0/INT1/RE8
VUSB
VBUS
AERXD1/INT2/RE9
SCL1A/SDO1A/U1ATX/RF8
SDA1A/SDI1A/U1ARX/RF2
USBID/RF3
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/CN3/RB1
PGED1/AN0/CN2/RB0
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
121-Pin XBGA(1)
= Pins are up to 5V tolerant
PIC32MX575F256L
PIC32MX675F256L
PIC32MX775F256L
PIC32MX575F512L
PIC32MX675F512L
PIC32MX695F512L
PIC32MX775F512L
PIC32MX795F512L
1
2
3
4
5
6
7
8
9
10
11
A
B
RE4
NC
RE3
RG13
RE2
RE0
RE1
RG0
RA7
RF1
RF0
VDD
VSS
RD12
RD3
RD2
VSS
RD1
RG15
VCAP/
RD5
RC14
VDDCORE
C
D
E
F
RE6
RC1
RC4
MCLR
RE8
RB5
RB3
RB1
RB6
VDD
RE7
RC3
RG8
RE9
RB4
RB2
RB0
RA9
RG12
RE5
RG6
RG9
RA0
VSS
RG14
VSS
RA6
VSS
VDD
VSS
VDD
NC
NC
NC
RD7
RD6
VSS
RD4
RD13
RA15
VDD
VDD
RD0
RD8
RC12
RA5
RC13
NC
RD11
RD10
RA14
RC15
RA4
RC2
RG7
NC
RG1
NC
RD9
VSS
NC
G
H
J
VSS
VDD
RA1
RF12
VSS
NC
RA3
RG2
RF8
RF3
RF4
VDD
AVDD
RB8
RB9
NC
VBUS
NC
VUSB
NC
RA2
RB7
RA10
AVSS
RB11
NC
RB12
RB14
RB13
RG3
RF2
K
L
VDD
RD15
RD14
RB10
RB15
RF5
RF13
Note 1: Refer to Table 2, Table 3 and Table 4 for full pin names.
DS61156C-page 14
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 2:
PIN NAMES: PIC32MX575F256L AND PIC32MX575F512L DEVICES
Pin
Number
Pin
Number
Full Pin Name
Full Pin Name
A1
A2
PMD4/RE4
PMD3/RE3
E8
E9
SDA1/INT4/RA15
RTCC/IC1/RD8
A3
A4
A5
A6
TRD0/RG13
PMD0/RE0
E10
E11
F1
SS1/IC2/RD9
SCL1/INT3/RA14
MCLR
PMD8/RG0
C1TX/PMD10/RF1
F2
SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8
A7
A8
VDD
F3
F4
SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9
VSS
SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
VSS
A9
IC5/PMD12/RD12
OC3/RD2
F5
A10
A11
B1
F6
No Connect (NC)
No Connect (NC)
VDD
OC2/RD1
F7
No Connect (NC)
RG15
F8
B2
F9
OSC1/CLKI/RC12
VSS
B3
PMD2/RE2
PMD1/RE1
TRD3/RA7
C1RX/PMD11/RF0
VCAP/VDDCORE
PMRD/CN14/RD5
OC4/RD3
F10
F11
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
J1
B4
OSC2/CLKO/RC15
INT1/RE8
B5
B6
INT2/RE9
B7
TMS/RA0
B8
No Connect (NC)
VDD
B9
B10
B11
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
E1
VSS
VSS
SOSCO/T1CK/CN0/RC14
PMD6/RE6
VSS
No Connect (NC)
TDO/RA5
VDD
TRD1/RG12
SDA2/RA3
TRD2/RG14
TDI/RA4
TRCLK/RA6
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
VSS
No Connect (NC)
PMD15/CN16/RD7
OC5/PMWR/CN13/RD4
VDD
VDD
No Connect (NC)
VDD
SOSCI/CN1/RC13
IC4/PMCS1/PMA14/RD11
T2CK/RC1
No Connect (NC)
VBUS
PMD7/RE7
VUSB
PMD5/RE5
D+/RG2
VSS
SCL2/RA2
VSS
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGED2/AN7/RB7
AVDD
No Connect (NC)
PMD14/CN15/RD6
PMD13/CN19/RD13
SDO1/OC1/INT0/RD0
No Connect (NC)
SCK1/IC3/PMCS2/PMA15/RD10
T5CK/SDI1/RC4
T4CK/RC3
J2
J3
J4
J5
AN11/PMA12/RB11
TCK/RA1
J6
J7
AN12/PMA11/RB12
No Connect (NC)
No Connect (NC)
J8
E2
J9
E3
E4
E5
E6
E7
SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
J10
J11
K1
SCL1A/SDO1A/U1ATX/RF8
D-/RG3
T3CK/RC2
VDD
PGEC1/AN1/CN3/RB1
PGED1/AN0/CN2/RB0
VREF+/CVREF+/PMA6/RA10
PMD9/RG1
VSS
K2
K3
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 15
PIC32MX5XX/6XX/7XX
TABLE 2:
PIN NAMES: PIC32MX575F256L AND PIC32MX575F512L DEVICES (CONTINUED)
Pin
Number
Pin
Number
Full Pin Name
Full Pin Name
K4
K5
AN8/C1OUT/RB8
No Connect (NC)
L3
L4
AVSS
AN9/C2OUT/RB9
K6
AC1RX/SS3A/U3BRX/U3ACTS/RF12
L5
AN10/CVREFOUT/PMA13/RB10
K7
K8
AN14/PMALH/PMA1/RB14
VDD
L6
L7
AC1TX/SCK3A/U3BTX/U3ARTS/RF13
AN13/PMA10/RB13
K9
SCK1A/U1BTX/U1ARTS/CN21/RD15
L8
AN15/OCFB/PMALL/PMA0/CN12/RB15
K10
K11
L1
USBID/RF3
L9
SS1A/U1BRX/U1ACTS/CN20/RD14
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
SDA1A/SDI1A/U1ARX/RF2
PGEC2/AN6/OCFA/RB6
VREF-/CVREF-/PMA7/RA9
L10
L11
L2
DS61156C-page 16
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 3:
PIN NAMES: PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES
Pin
Number
Pin
Number
Full Pin Name
Full Pin Name
A1
A2
PMD4/RE4
E8
E9
AETXEN/SDA1/INT4/RA15
PMD3/RE3
RTCC/EMDIO/AEMDIO/IC1/RD8
A3
A4
TRD0/RG13
PMD0/RE0
E10
E11
SS1/IC2/RD9
AETXCLK/SCL1/INT3/RA14
A5
A6
PMD8/RG0
F1
F2
MCLR
ETXD0/PMD10/RF1
ERXDV/AERXDV/ECRSDV/AECRSDV//SCL2A/SDO2A/
U2ATX/PMA3/CN10/RG8
A7
VDD
VSS
F3
ERXCLK/AERXCLK/EREFCLK/AEREFCLK//SS2A/U2BRX/
U2ACTS/PMA2/CN11/RG9
A8
A9
F4
F5
ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
ETXD2/IC5/PMD12/RD12
OC3/RD2
VSS
A10
A11
B1
F6
No Connect (NC)
No Connect (NC)
VDD
OC2/RD1
F7
No Connect (NC)
AERXERR/RG15
PMD2/RE2
F8
B2
F9
OSC1/CLKI/RC12
VSS
B3
F10
F11
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
J1
B4
PMD1/RE1
OSC2/CLKO/RC15
AERXD0/INT1/RE8
AERXD1/INT2/RE9
TMS/RA0
B5
TRD3/RA7
B6
ETXD1/PMD11/RF0
VCAP/VDDCORE
PMRD/CN14/RD5
OC4/RD3
B7
B8
No Connect (NC)
VDD
B9
B10
B11
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
E1
VSS
VSS
SOSCO/T1CK/CN0/RC14
PMD6/RE6
VSS
No Connect (NC)
TDO/RA5
VDD
TRD1/RG12
SDA2/RA3
TRD2/RG14
TDI/RA4
TRCLK/RA6
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
VSS
No Connect (NC)
ETXCLK/PMD15/CN16/RD7
OC5/PMWR/CN13/RD4
VDD
VDD
No Connect (NC)
VDD
SOSCI/CN1/RC13
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
T2CK/RC1
No Connect (NC)
VBUS
PMD7/RE7
VUSB
PMD5/RE5
D+/RG2
VSS
SCL2/RA2
VSS
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGED2/AN7/RB7
AVDD
No Connect (NC)
ETXEN/PMD14/CN15/RD6
ETXD3/PMD13/CN19/RD13
SDO1/OC1/INT0/RD0
No Connect (NC)
SCK1/IC3/PMCS2/PMA15/RD10
T5CK/SDI1/RC4
T4CK/RC3
J2
J3
J4
J5
AN11/ERXERR/AETXERR/PMA12/RB11
TCK/RA1
J6
J7
AN12/ERXD0/AECRS/PMA11/RB12
No Connect (NC)
No Connect (NC)
SCL1A/SDO1A/U1ATX/RF8
D-/RG3
J8
E2
J9
E3
ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
T3CK/RC2
J10
J11
K1
K2
K3
E4
E5
VDD
PGEC1/AN1/CN3/RB1
PGED1/AN0/CN2/RB0
VREF+/CVREF+/AERXD3/PMA6/RA10
E6
EXTERR/PMD9/RG1
VSS
E7
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 17
PIC32MX5XX/6XX/7XX
TABLE 3:
PIN NAMES: PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES
Pin
Number
Pin
Number
Full Pin Name
Full Pin Name
K4
K5
AN8/C1OUT/RB8
No Connect (NC)
L3
L4
AVSS
AN9/C2OUT/RB9
K6
K7
K8
K9
SS3A/U3BRX/U3ACTS/RF12
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
VDD
L5
L6
L7
L8
AN10/CVREFOUT/PMA13/RB10
SCK3A/U3BTX/U3ARTS/RF13
AN13/ERXD1/AECOL/PMA10/RB13
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15
K10
K11
L1
USBID/RF3
L9
AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
SDA1A/SDI1A/U1ARX/RF2
PGEC2/AN6/OCFA/RB6
VREF-/CVREF-/AERXD2/PMA7/RA9
L10
L11
L2
DS61156C-page 18
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 4:
PIN NAMES: PIC32MX775F256L, PIC32MX775F512L, PIC32MX795F512L AND DEVICES
Pin
Number
Pin
Number
Full Pin Name
Full Pin Name
A1
A2
A3
A4
A5
A6
PMD4/RE4
E8
E9
AETXEN/SDA1/INT4/RA15
PMD3/RE3
RTCC/EMDIO/AEMDIO/IC1/RD8
SS1/IC2/RD9
TRD0/RG13
PMD0/RE0
E10
E11
F1
AETXCLK/SCL1/INT3/RA14
MCLR
C2RX/PMD8/RG0
C1TX/ETXD0/PMD10/RF1
F2
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/
U2ATX/PMA3/CN10/RG8
A7
VDD
F3
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/
U2ACTS/PMA2/CN11/RG9
A8
A9
VSS
F4
F5
ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7
ETXD2/IC5/PMD12/RD12
OC3/RD2
VSS
A10
A11
B1
F6
No Connect (NC)
No Connect (NC)
VDD
OC2/RD1
F7
No Connect (NC)
AERXERR/RG15
PMD2/RE2
F8
B2
F9
OSC1/CLKI/RC12
VSS
B3
F10
F11
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
J1
B4
PMD1/RE1
OSC2/CLKO/RC15
AERXD0/INT1/RE8
AERXD1/INT2/RE9
TMS/RA0
B5
TRD3/RA7
B6
C1RX/ETXD1/PMD11/RF0
VCAP/VDDCORE
PMRD/CN14/RD5
OC4/RD3
B7
B8
No Connect (NC)
VDD
B9
B10
B11
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
E1
VSS
VSS
SOSCO/T1CK/CN0/RC14
PMD6/RE6
VSS
No Connect (NC)
TDO/RA5
VDD
TRD1/RG12
SDA2/RA3
TRD2/RG14
TDI/RA4
TRCLK/RA6
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
VSS
No Connect (NC)
ETXCLK/PMD15/CN16/RD7
OC5/PMWR/CN13/RD4
VDD
VDD
No Connect (NC)
VDD
SOSCI/CN1/RC13
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
T2CK/RC1
No Connect (NC)
VBUS
PMD7/RE7
VUSB
PMD5/RE5
D+/RG2
VSS
SCL2/RA2
VSS
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGED2/AN7/RB7
AVDD
No Connect (NC)
ETXEN/PMD14/CN15/RD6
ETXD3/PMD13/CN19/RD13
SDO1/OC1/INT0/RD0
No Connect (NC)
SCK1/IC3/PMCS2/PMA15/RD10
T5CK/SDI1/RC4
T4CK/AC2RX/RC3
J2
J3
J4
J5
AN11/ERXERR/AETXERR/PMA12/RB11
TCK/RA1
J6
J7
AN12/ERXD0/AECRS/PMA11/RB12
No Connect (NC)
No Connect (NC)
J8
E2
J9
E3
E4
E5
E6
E7
ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6
J10
J11
K1
SCL1A/SDO1A/U1ATX/RF8
D-/RG3
T3CK/AC2TX/RC2
VDD
PGEC1/AN1/CN3/RB1
PGED1/AN0/CN2/RB0
VREF+/CVREF+/AERXD3/PMA6/RA10
C2TX/EXTERR/PMD9/RG1
VSS
K2
K3
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 19
PIC32MX5XX/6XX/7XX
TABLE 4:
PIN NAMES: PIC32MX775F256L, PIC32MX775F512L, PIC32MX795F512L AND DEVICES
Pin
Number
Pin
Number
Full Pin Name
Full Pin Name
K4
K5
K6
K7
K8
AN8/C1OUT/RB8
No Connect (NC)
L3
L4
L5
L6
L7
AVSS
AN9/C2OUT/RB9
AC1RX/SS3A/U3BRX/U3ACTS/RF12
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
VDD
AN10/CVREFOUT/PMA13/RB10
AC1TX/SCK3A/U3BTX/U3ARTS/RF13
AN13/ERXD1/AECOL/PMA10/RB13
K9
K10
K11
L1
AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15
USBID/RF3
L8
L9
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14
SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4
SDA1A/SDI1A/U1ARX/RF2
PGEC2/AN6/OCFA/RB6
L10
L11
SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5
L2
VREF-/CVREF-/AERXD2/PMA7/RA9
DS61156C-page 20
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 23
2.0 Guidelines for Getting Started with 32-Bit Microcontrollers........................................................................................................ 35
3.0 PIC32MX MCU........................................................................................................................................................................... 39
4.0 Memory Organization................................................................................................................................................................. 45
5.0 Flash Program Memory............................................................................................................................................................ 105
6.0 Resets ...................................................................................................................................................................................... 107
7.0 Interrupt Controller ................................................................................................................................................................... 109
8.0 Oscillator Configuration............................................................................................................................................................ 113
9.0 Prefetch Cache......................................................................................................................................................................... 115
10.0 Direct Memory Access (DMA) Controller ................................................................................................................................ 117
11.0 USB On-The-Go (OTG)............................................................................................................................................................ 119
12.0 I/O Ports ................................................................................................................................................................................... 121
13.0 Timer1 ...................................................................................................................................................................................... 123
14.0 Timer2/3, Timer4/5................................................................................................................................................................... 125
15.0 Input Capture............................................................................................................................................................................ 127
16.0 Output Compare....................................................................................................................................................................... 129
17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 131
2
18.0 Inter-Integrated Circuit (I C™) ................................................................................................................................................. 133
19.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 135
20.0 Parallel Master Port (PMP) ...................................................................................................................................................... 137
21.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 139
22.0 10-Bit Analog-to-Digital Converter (ADC)................................................................................................................................. 141
23.0 Controller Area Network (CAN)................................................................................................................................................ 143
24.0 Ethernet Controller ................................................................................................................................................................... 145
25.0 Comparator .............................................................................................................................................................................. 147
26.0 Comparator Voltage Reference (CVref)................................................................................................................................... 149
27.0 Power-Saving Features ........................................................................................................................................................... 151
28.0 Special Features ...................................................................................................................................................................... 153
29.0 Instruction Set .......................................................................................................................................................................... 165
30.0 Development Support............................................................................................................................................................... 167
31.0 Electrical Characteristics.......................................................................................................................................................... 171
32.0 Packaging Information.............................................................................................................................................................. 213
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
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2010 Microchip Technology Inc.
Preliminary
DS61156C-page 21
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 22
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
This document contains device-specific information for
PIC32MX5XX/6XX/7XX devices.
1.0
DEVICE OVERVIEW
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“PIC32MX Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
Figure 1-1 shows a general block diagram of the core
and peripheral modules in the PIC32MX5XX/6XX/7XX
family of devices.
Table 1-1 lists the functions of the various pins shown
in the pinout diagrams.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
FIGURE 1-1:
BLOCK DIAGRAM(1,2)
VCAP/VDDCORE
OSC2/CLKO
OSC1/CLKI
OSC/SOSC
Oscillators
Power-up
VDD, VSS
Timer
FRC/LPRC
Oscillators
MCLR
Voltage
Oscillator
Start-up Timer
Regulator
PLL
Power-on
Reset
Precision
Band Gap
Reference
Dividers
PLL-USB
Watchdog
Timer
USBCLK
SYSCLK
PBCLK
Brown-out
Reset
Timing
Generation
Peripheral Bus Clocked by SYSCLK
CN1-22
PORTA
Timer1-5
Priority
JTAG
BSCAN
Interrupt
Controller
PWM
OC1-5
PORTB
PORTC
PORTD
PORTE
PORTF
PORTG
32
EJTAG
INT
MIPS32® M4K™
CPU Core
IC1-5
IS
DS
32
32
32
32
32
32
32
SPI1,1A,2A,3A
32
Bus Matrix
32
I2C1,2,1A,
2A,3A
32
32
32
Prefetch
Module
Peripheral Bridge
Data RAM
PMP
10-Bit ADC
128
UART1A,1B,2A,
2B,3A,3B
128-Bit Wide
Program Flash Memory
RTCC
Comparators
Note 1: Some features are not available on all device variants.
2: BOR functionality is provided when the on-board voltage regulator is enabled.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 23
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin Number(1)
Pin
Type
Buffer
Type
Pin Name
Description
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
AN0
16
15
14
13
12
11
17
18
21
22
23
24
27
28
29
30
39
25
24
23
22
21
20
26
27
32
33
34
35
41
42
43
44
63
K2
K1
J2
J1
H2
H1
L1
J3
K4
L4
L5
J5
J7
L7
K7
L8
F9
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog Analog input channels.
AN1
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
AN14
AN15
CLKI
ST/CMOS External clock source input. Always associated
with OSC1 pin function.
CLKO
40
64
F11
O
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode. Optionally
functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
OSC1
OSC2
39
40
63
64
F9
I
ST/CMOS Oscillator crystal input. ST buffer when
configured in RC mode; CMOS otherwise.
F11
I/O
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode. Optionally
functions as CLKO in RC and EC modes.
SOSCI
47
48
73
74
C10
B11
I
ST/CMOS 32.768 kHz low-power oscillator crystal input;
CMOS otherwise.
SOSCO
O
—
32.768 kHz low-power oscillator crystal output.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
DS61156C-page 24
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
Description
64-Pin
100-Pin
121-Pin
XBGA
QFN/TQFP
TQFP
CN0
CN1
CN2
CN3
CN4
CN5
CN6
CN7
CN8
CN9
CN10
CN11
CN12
CN13
CN14
CN15
CN16
CN17
CN18
CN19
CN20
CN21
IC1
48
47
16
15
14
13
12
11
4
74
73
25
24
23
22
21
20
10
11
12
14
44
81
82
83
84
49
50
80
47
48
68
69
70
71
79
26
72
76
77
78
81
44
72
18
19
66
67
B11
C10
K2
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
Change notification inputs.
Can be software programmed for internal weak
pull-ups on all inputs.
I
K1
I
J2
I
J1
I
H2
H1
E3
I
I
I
5
F4
I
6
F2
I
8
F3
I
30
52
53
54
55
31
32
—
—
—
42
43
44
45
52
17
46
49
50
51
52
30
46
42
43
44
45
L8
I
C8
B8
I
I
D7
C7
L10
L11
D8
L9
I
I
I
I
I
I
K9
I
E9
I
Capture Inputs 1-5.
IC2
E10
D11
C11
A9
I
IC3
I
IC4
I
IC5
I
OCFA
OC1
OC2
OC3
OC4
OC5
OCFB
INT0
INT1
INT2
INT3
INT4
L1
I
Output Compare Fault A input.
Output Compare Output 1.
Output Compare Output 2
Output Compare Output 3.
Output Compare Output 4.
Output Compare Output 5.
Output Compare Fault B input.
External Interrupt 0.
D9
A11
A10
B9
O
O
O
O
O
I
—
—
—
C8
L8
—
ST
ST
ST
ST
ST
ST
D9
G1
G2
E11
E8
I
I
External Interrupt 1.
I
External Interrupt 2.
I
External Interrupt 3.
I
External Interrupt 4.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 25
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Buffer
Type
Pin Name
Description
64-Pin
100-Pin
TQFP
121-Pin
XBGA
Type
QFN/TQFP
RA0
—
—
—
—
—
—
—
—
—
—
—
—
16
15
14
13
12
11
17
18
21
22
23
24
27
28
29
30
—
—
—
—
39
47
48
40
17
38
58
59
60
61
91
92
28
29
66
67
25
24
23
22
21
20
26
27
32
33
34
35
41
42
43
44
6
G3
J6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
PORTA is a bidirectional I/O port.
RA1
RA2
H11
G10
G11
G9
C5
B5
L2
RA3
RA4
RA5
RA6
RA7
RA9
RA10
RA14
RA15
RB0
K3
E11
E8
K2
K1
J2
PORTB is a bidirectional I/O port.
RB1
RB2
RB3
J1
RB4
H2
H1
L1
RB5
RB6
RB7
J3
RB8
K4
L4
RB9
RB10
RB11
RB12
RB13
RB14
RB15
RC1
RC2
RC3
RC4
RC12
RC13
RC14
RC15
L5
J5
J7
L7
K7
L8
D1
E4
E2
E1
F9
PORTC is a bidirectional I/O port.
7
8
9
63
73
74
64
C10
B11
F11
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
DS61156C-page 26
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
Description
64-Pin
100-Pin
121-Pin
XBGA
QFN/TQFP
TQFP
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RD8
RD9
RD10
RD11
RD12
RD13
RD14
RD15
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
RE8
RE9
RF0
46
49
50
51
52
53
54
55
42
43
44
45
—
—
—
—
60
61
62
63
64
1
72
76
77
78
81
82
83
84
68
69
70
71
79
80
47
48
93
94
98
99
100
3
D9
A11
A10
B9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
PORTD is a bidirectional I/O port.
C8
B8
D7
C7
E9
E10
D11
C11
A9
D8
L9
K9
A4
PORTE is a bidirectional I/O port.
B4
B3
A2
A1
D3
C1
D2
G1
G2
B6
2
4
3
5
—
—
58
59
—
33
31
32
—
—
—
18
19
87
88
52
51
49
50
53
40
39
PORTF is a bidirectional I/O port.
RF1
A6
RF2
K11
K10
L10
L11
J10
K6
RF3
RF4
RF5
RF8
RF12
RF13
L6
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 27
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Buffer
Type
Pin Name
Description
64-Pin
100-Pin
TQFP
121-Pin
XBGA
Type
QFN/TQFP
RG0
—
—
4
90
89
10
11
12
14
96
97
95
1
A5
E6
E3
F4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
PORTG is a bidirectional I/O port.
RG1
RG6
RG7
5
RG8
6
F2
RG9
8
F3
RG12
RG13
RG14
RG15
RG2
—
—
—
—
37
36
48
—
—
—
—
43
49
50
51
C3
A3
C4
B2
H10
J11
B11
D1
E4
E2
E1
L9
57
56
74
6
PORTG input pins.
RG3
I
T1CK
T2CK
T3CK
T4CK
T5CK
U1ACTS
U1ARTS
U1ARX
U1ATX
U2ACTS
U2ARTS
I
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
UART1A clear to send.
UART1A ready to send.
UART1A receive.
I
7
I
8
I
9
I
47
48
52
53
I
K9
K11
J10
O
I
ST
—
O
I
UART1A transmit.
8
4
5
14
10
11
F3
E3
F4
ST
—
UART2A clear to send.
UART2A ready to send.
O
U2ARX
U2ATX
I
O
I
ST
—
UART2A receive.
6
12
F2
UART2A transmit.
UART3A clear to send.
UART3A ready to send.
UART3A receive.
U3ACTS
U3ARTS
U3ARX
21
29
31
40
39
49
K6
L6
ST
—
O
I
L10
ST
32
50
L11
U3ATX
U1BRX
U1BTX
U2BRX
U2BTX
U3BRX
U3BTX
SCK1
O
I
—
ST
—
UART3A transmit.
43
49
8
47
48
14
10
40
39
70
9
L9
K9
F3
UART1B receive.
O
I
UART1B transmit.
ST
—
UART2B receive.
4
E3
K6
L6
O
I
UART2B transmit.
21
29
—
—
ST
—
UART3B receive.
O
I/O
I
UART3B transmit.
D11
E1
ST
ST
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SDI1
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
DS61156C-page 28
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
Description
64-Pin
100-Pin
121-Pin
XBGA
QFN/TQFP
TQFP
SDO1
SS1
—
—
49
72
69
48
D9
E10
K9
O
—
ST
ST
SPI1 data out.
I/O
I/O
SPI1 slave synchronization or frame pulse I/O.
SCK1A
Synchronous serial clock input/output for
SPI1A.
SDI1A
SDO1A
SS1A
50
51
43
52
53
47
K11
J10
L9
I
ST
—
SPI1A data in.
SPI1A data out.
O
I/O
ST
SPI1A slave synchronization or frame pulse
I/O.
SCK2A
4
10
E3
I/O
ST
Synchronous serial clock input/output for
SPI2A.
SDI2A
SDO2A
SS2A
5
6
8
11
12
14
F4
F2
F3
I
ST
—
SPI2A data in.
SPI2A data out.
O
I/O
ST
SPI2A slave synchronization or frame pulse
I/O.
SCK3A
29
39
L6
I/O
ST
Synchronous serial clock input/output for
SPI3A.
SDI3A
SDO3A
SS3A
31
32
21
49
50
40
L10
L11
K6
I
ST
—
SPI3A data in.
SPI3A data out.
O
I/O
ST
SPI3A slave synchronization or frame pulse
I/O.
SCL1
44
43
51
66
67
53
E11
E8
I/O
I/O
I/O
ST
ST
ST
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
SDA1
SCL1A
J10
Synchronous serial clock input/output for
I2C1A.
SDA1A
50
52
K11
I/O
ST
Synchronous serial data input/output for
I2C1A.
SCL2
—
—
6
58
59
12
H11
G10
F2
I/O
I/O
I/O
ST
ST
ST
Synchronous serial clock input/output for I2C2.
Synchronous serial data input/output for I2C2.
SDA2
SCL2A
Synchronous serial clock input/output for
I2C2A.
SDA2A
SCL3A
SDA3A
5
11
50
49
F4
I/O
I/O
I/O
ST
ST
ST
Synchronous serial data input/output for
I2C2A.
32
31
L11
L10
Synchronous serial clock input/output for
I2C3A.
Synchronous serial data input/output for
I2C3A.
TMS
TCK
TDI
23
27
28
24
42
17
38
60
61
68
G3
J6
I
I
ST
ST
ST
—
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
Real-Time Clock alarm output.
G11
G9
E9
I
TDO
RTCC
O
O
—
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 29
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Buffer
Type
Pin Name
Description
64-Pin
100-Pin
TQFP
121-Pin
XBGA
Type
QFN/TQFP
CVREF-
CVREF+
CVREFOUT
C1IN-
15
16
23
12
11
21
14
13
22
—
28
29
34
21
20
32
23
22
33
44
L2
K3
L5
H2
H1
K4
J2
I
I
Analog Comparator Voltage Reference (low).
Analog Comparator Voltage Reference (high).
Analog Comparator Voltage Reference output.
Analog Comparator 1 negative input.
O
I
C1IN+
I
Analog Comparator 1 positive input.
C1OUT
C2IN-
O
I
—
Comparator 1 output.
Analog Comparator 2 negative input.
Analog Comparator 2 positive input.
C2IN+
J1
I
C2OUT
PMA0
L4
L8
O
I/O
—
Comparator 2 output.
TTL/ST Parallel Master Port Address Bit 0 input
(Buffered Slave modes) and output (Master
modes).
PMA1
—
43
K7
I/O
TTL/ST Parallel Master Port Address Bit 1 input
(Buffered Slave modes) and output (Master
modes).
PMA2
8
14
12
11
10
29
28
50
49
42
41
35
34
71
70
71
70
F3
F2
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Parallel Master Port address (Demultiplexed
Master modes).
PMA3
6
PMA4
5
F4
PMA5
4
E3
PMA6
16
22
32
31
28
27
24
23
45
44
45
44
K3
PMA7
L2
PMA8
L11
L10
L7
PMA9
PMA10
PMA11
PMA12
PMA13
PMA14
PMA15
PMCS1
PMCS2
J7
J5
L5
C11
D11
C11
D11
Parallel Master Port Chip Select 1 strobe.
Parallel Master Port Chip Select 2 strobe.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
DS61156C-page 30
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
Description
64-Pin
100-Pin
121-Pin
XBGA
QFN/TQFP
TQFP
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
PMD7
PMD8
PMD9
PMD10
PMD11
PMD12
PMD13
PMD14
PMD15
PMALL
60
61
62
63
64
1
93
94
98
99
100
3
A4
B4
B3
A2
A1
D3
C1
D2
A5
E6
A6
B6
A9
D8
D7
C7
L8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
TTL/ST Parallel Master Port data (Demultiplexed
Master mode) or address/data (Multiplexed
Master modes).
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
2
4
3
5
—
—
—
—
—
—
—
—
30
90
89
88
87
79
80
83
84
44
—
Parallel Master Port address latch enable
low byte (Multiplexed Master modes).
PMALH
29
43
K7
O
—
Parallel Master Port address latch enable
high byte (Multiplexed Master modes).
PMRD
PMWR
VBUS
53
52
34
35
11
37
36
33
58
59
32
31
29
21
—
—
61
60
59
82
81
54
55
20
57
56
51
87
88
40
39
90
89
8
B8
C8
H8
H9
H1
H10
J11
K10
B6
A6
K6
L6
O
O
I
—
—
Parallel Master Port read strobe.
Parallel Master Port write strobe.
Analog USB bus power monitor.
VUSB
P
O
I/O
I/O
I
—
—
USB internal transceiver supply.
VBUSON
D+
USB Host and OTG bus power control output.
Analog USB D+.
Analog USB D-.
D-
USBID
C1RX
C1TX
AC1RX
AC1TX
C2RX
C2TX
AC2RX
AC2TX
ERXD0
ERXD1
ERXD2
ST
ST
—
USB OTG ID detect.
I
CAN1 bus receive pin.
O
I
CAN1 bus transmit pin.
ST
—
Alternate CAN1 bus receive pin.
Alternate CAN1 bus transmit pin.
CAN2 bus receive pin.
O
I
A5
E6
E2
E4
J7
ST
—
O
1
CAN2 bus transmit pin.
ST
—
Alternate CAN2 bus receive pin.
Alternate CAN2 bus transmit pin.
Ethernet Receive Data 0.(2)
Ethernet Receive Data 1.(2)
Ethernet Receive Data 2.(2)
7
O
I
41
42
43
ST
ST
ST
L7
I
K7
I
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 31
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Buffer
Type
Pin Name
Description
64-Pin
100-Pin
TQFP
121-Pin
XBGA
Type
QFN/TQFP
ERXD3
58
64
62
61
63
63
2
44
35
12
12
14
14
88
87
79
80
89
83
84
10
11
71
68
18
19
28
29
1
L8
J5
I
I
ST
ST
ST
ST
ST
ST
—
Ethernet Receive Data 3.(2)
ERXERR
ERXDV
Ethernet receive error input.(2)
Ethernet receive data valid.(2)
Ethernet carrier sense data valid.(2)
Ethernet receive clock.(2)
Ethernet reference clock.(2)
Ethernet Transmit Data 0.(2)
Ethernet Transmit Data 1.(2)
Ethernet Transmit Data 2.(2)
Ethernet Transmit Data 3.(2)
Ethernet transmit error.(2)
F2
F2
F3
F3
A6
B6
A9
D8
E6
D7
C7
E3
F4
C11
E9
G1
G2
L2
K3
B2
—
I
ECRSDV
ERXCLK
EREFCLK
ETXD0
I
I
I
O
O
O
O
O
O
I
ETXD1
3
—
ETXD2
43
42
54
1
—
ETXD3
—
ETXERR
ETXEN
—
—
Ethernet transmit enable.(2)
Ethernet transmit clock.(2)
Ethernet collision detect.(2)
Ethernet carrier sense.(2)
ETXCLK
ECOL
55
44
45
30
49
43
42
—
—
55
44
44
45
45
59
58
—
—
—
54
—
—
—
—
ST
ST
ST
—
I
ECRS
I
EMDC
O
I/O
I
Ethernet management data clock.(2)
Ethernet management data.(2)
Alternate Ethernet Receive Data 0.(2)
Alternate Ethernet Receive Data 1.(2)
Alternate Ethernet Receive Data 2.(2)
Alternate Ethernet Receive Data 3.(2)
Alternate Ethernet receive error input.(2)
Alternate Ethernet receive data valid.(2)
Alternate Ethernet carrier sense data valid.(2)
Alternate Ethernet receive clock.(2)
Alternate Ethernet reference clock.(2)
Alternate Ethernet Transmit Data 0.(2)
Alternate Ethernet Transmit Data 1.(2)
Alternate Ethernet Transmit Data 2.(2)
Alternate Ethernet Transmit Data 3.(2)
Alternate Ethernet transmit error.(2)
Alternate Ethernet transmit enable.(2)
Alternate Ethernet transmit clock.(2)
Alternate Ethernet collision detect.(2)
Alternate Ethernet carrier sense.(2)
Trace clock.
EMDIO
—
AERXD0
AERXD1
AERXD2
AERXD3
AERXERR
AERXDV
AECRSDV
AERXCLK
AEREFCLK
AETXD0
AETXD1
AETXD2
AETXD3
AETXERR
AETXEN
AETXCLK
AECOL
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
I
I
I
I
—
—
—
—
47
48
44
43
35
67
66
42
41
91
I
—
I
—
I
—
I
L9
K9
L8
K7
J5
O
O
O
O
O
O
I
—
—
—
—
E8
E11
L7
J7
—
ST
ST
ST
—
I
AECRS
I
TRCLK
C5
O
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
DS61156C-page 32
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
Description
64-Pin
100-Pin
121-Pin
XBGA
QFN/TQFP
TQFP
TRD0
TRD1
TRD2
TRD3
PGED1
—
—
—
—
16
97
96
95
92
25
A3
C3
C4
B5
K2
O
O
—
—
—
—
ST
Trace Data Bits 0-3.
O
O
I/O
Data I/O pin for Programming/Debugging
Communication Channel 1.
PGEC1
PGED2
PGEC2
MCLR
AVDD
15
18
17
7
24
27
26
13
30
31
K1
J3
L1
F1
J4
I
I/O
I
ST
ST
ST
ST
P
Clock input pin for Programming/Debugging
Communication Channel 1.
Data I/O pin for Programming/Debugging
Communication Channel 2.
Clock input pin for Programming/Debugging
Communication Channel 2.
I/P
P
Master Clear (Reset) input. This pin is an
active-low Reset to the device.
19
20
Positive supply for analog modules. This pin
must be connected at all times.
AVSS
VDD
L3
P
P
P
Ground reference for analog modules.
10, 26, 38, 2, 16, 37,
A7, C2,
—
Positive supply for peripheral logic and I/O
pins.
57
46, 62, 86 C9, E5,
K8, F8,
G5, H4, H6
VCAP/
VDDCORE
56
85
B7
P
P
—
—
CPU logic filter capacitor connection.
VSS
9, 25, 41 15, 36, 45, A8, B10,
Ground reference for logic and I/O pins. This
pin must be connected at all times.
65, 75
D4, D5,
E7, F5,
F10, G6,
G7, H3
VREF+
VREF-
16
15
29
28
K3
L2
I
I
Analog Analog voltage reference (high) input.
Analog Analog voltage reference (low) input.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
P = Power
I = Input
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 33
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 34
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
2.2
Decoupling Capacitors
2.0
GUIDELINES FOR GETTING
STARTED WITH 32-BIT
MICROCONTROLLERS
The use of decoupling capacitors on power supply
pins, such as VDD, VSS, AVDD and AVSS is required.
See Figure 2-1.
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32)
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A value of 0.1 µF
(100 nF), 10-20V is recommended. The capacitor
should be a low Equivalent Series Resistance
(low-ESR) capacitor and have resonance fre-
quency in the range of 20 MHz and higher. It is
further recommended that ceramic capacitors be
used.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended that
the capacitors be placed on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within one-
quarter inch (6 mm) in length.
2.1
Basic Connection Requirements
Getting started with the PIC32MX5XX/6XX/7XX family
of 32-bit Microcontrollers (MCU) requires attention to a
minimal set of device pin connections before proceed-
ing with development. The following is a list of pin
names, which must always be connected:
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins–even if the ADC module
is not used
(see Section 2.2 “Decoupling Capacitors”)
• VCAP/VDDCORE pin
(see Section 2.3 “Capacitor on Internal
Voltage Regulator (VCAP/VDDCORE)”)
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins–used for In-Circuit Serial
Programming (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins–when external oscillator
source is used
(see Section 2.8 “External Oscillator Pins”)
The following pin may be required, as well:
VREF+/VREF- pins–used when external voltage refer-
ence for ADC module is implemented
Note:
The AVDD and AVSS pins must be
connected, regardless of ADC use and the
ADC voltage reference source.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 35
PIC32MX5XX/6XX/7XX
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
2.4
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
0.1 µF
Ceramic
• Device Reset
CEFC
VDD
CBP
• Device programming and debugging
Pulling The MCLR pin low generates a device Reset.
Figure 2-2 shows a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
R
R1
MCLR
C
PIC32MX
VDD
VSS
VDD
VSS
0.1 µF
Ceramic
CBP
0.1 µF
Ceramic
CBP
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
0.1 µF
Ceramic
CBP
0.1 µF
Ceramic
CBP
10
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
2.2.1
BULK CAPACITORS
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
2.3
Capacitor on Internal Voltage
Regulator (VCAP/VDDCORE)
R
R1
MCLR
2.3.1
INTERNAL REGULATOR MODE
PIC32MX
JP
C
A low-ESR (1 ohm) capacitor is required on the
VCAP/VDDCORE pin, which is used to stabilize the inter-
nal voltage regulator output. The VCAP/VDDCORE pin
must not be connected to VDD, and must have a CEFC
capacitor, with at least a 6V rating, connected to
ground. The type can be ceramic or tantalum. Refer to
Section 31.0 "Electrical Characteristics" for
additional information on CEFC specifications.
Note 1: R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
2: R1 470 will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
3: The capacitor can be sized to prevent uninten-
tional Resets from brief glitches or to extend
the device Reset period during POR.
DS61156C-page 36
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
2.5
ICSP Pins
2.6
JTAG
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging pur-
poses. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
The TMS, TDO, TDI and TCK pins are used for testing
and debugging according to the Joint Test Action
Group (JTAG) standard. It is recommended to keep the
trace length between the JTAG connector and the
JTAG pins on the device as short as possible. If the
JTAG connector is expected to experience an ESD
event, a series resistor is recommended, with the value
in the range of a few tens of Ohms, not to exceed 100
Ohms.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended
as they will interfere with the programmer/debugger
communications to the device. If such discrete compo-
nents are an application requirement, they should be
removed from the circuit during programming and
debugging. Alternatively, refer to the AC/DC character-
istics and timing requirements information in the
respective device Flash programming specification for
information on capacitive loading limits and pin input
voltage high (VIH) and input low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 2, MPLAB ICD 3, or MPLAB REAL
ICE™.
2.7
Trace
The trace pins can be connected to a hardware-trace-
enabled programmer to provide a compress real time
instruction trace. When used for trace the TRD3,
TRD2, TRD1, TRD0 and TRCLK pins should be dedi-
cated for this use. The trace hardware requires a
22 ohm series resistor between the trace pins and the
trace connector.
For more information on ICD 2, ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web
site.
• “MPLAB® ICD 2 In-Circuit Debugger User's
Guide” DS51331
• “Using MPLAB® ICD 2” (poster) DS51265
• “MPLAB® ICD 2 Design Advisory” DS51566
• “Using MPLAB® ICD 3” (poster) DS51765
• “MPLAB® ICD 3 Design Advisory” DS51764
• “MPLAB® REAL ICE™ In-Circuit Debugger
User's Guide” DS51616
• “Using MPLAB® REAL ICE™ Emulator” (poster)
DS51749
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 37
PIC32MX5XX/6XX/7XX
2.8
External Oscillator Pins
2.9
Configuration of Analog and
Digital Pins During ICSP
Operations
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 8.0 "Oscillator
Configuration" for details).
If MPLAB ICD 2, ICD 3, or REAL ICE is selected as a
debugger, it automatically initializes all of the A/D input
pins (ANx) as “digital” pins by setting all bits in the
ADPCFG register.
The oscillator circuit should be placed on the same side
of the board as the device. Also, place the oscillator cir-
cuit close to the respective oscillator pins, not exceed-
ing one-half inch (12 mm) distance between them. The
load capacitors should be placed next to the oscillator
itself, on the same side of the board. Use a grounded
copper pour around the oscillator circuit to isolate them
from surrounding circuits. The grounded copper pour
should be routed directly to the MCU ground. Do not
run any signal traces or power traces inside the ground
pour. Also, if using a two-sided board, avoid any traces
on the other side of the board where the crystal is
placed. A suggested layout is shown in Figure 2-3.
The bits in this register that correspond to the A/D pins
that are initialized by MPLAB ICD 2, ICD 3, or REAL
ICE, must not be cleared by the user application
firmware; otherwise, communication errors will result
between the debugger and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
ADPCFG register during initialization of the ADC
module.
When MPLAB ICD 2, ICD 3, or REAL ICE is used as a
programmer, the user application firmware must cor-
rectly configure the ADPCFG register. Automatic initial-
ization of this register is only done during debugger
operation. Failure to correctly configure the register(s)
will result in all A/D pins being recognized as analog
input pins, resulting in the port value being read as a
logic '0', which may affect user application functionality.
FIGURE 2-3:
SUGGESTED OSCILLATOR
CIRCUIT PLACEMENT
Oscillator
Secondary
2.10 Unused I/Os
Guard Trace
Guard Ring
Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
to a logic-low state.
Alternatively, inputs can be reserved by connecting the
pin to VSS through a 1k to 10k resistor and configuring
the pin as an input.
Main Oscillator
DS61156C-page 38
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
- Atomic interrupt enable/disable
3.0
PIC32MX MCU
- GPR shadow registers to minimize latency
for interrupt handlers
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “MCU”
(DS61113) in the “PIC32MX Family
Reference Manual”, which is available
- Bit field manipulation instructions
• MIPS16e™ Code Compression
- 16-bit encoding of 32-bit instructions to
improve code density
- Special PC-relative instructions for efficient
loading of addresses and constants
from
the
Microchip
web
site
- SAVE & RESTORE macro instructions for
setting up and tearing down stack frames
within subroutines
(www.microchip.com/PIC32). Resources
for the MIPS32® M4K® Processor Core
are available at http://www.mips.com.
- Improved support for handling 8 and 16-bit
data types
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
• Simple Fixed Mapping Translation (FMT)
mechanism
• Simple Dual Bus Interface
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
interrupt latency
The MCU module is the heart of the
PIC32MX5XX/6XX/7XX family processor. The MCU
fetches instructions, decodes each instruction, fetches
source operands, executes each instruction and writes
the results of instruction execution to the proper
destinations.
• Autonomous Multiply/Divide Unit
- Maximum issue rate of one 32x16 multiply
per clock
- Maximum issue rate of one 32x32 multiply
every other clock
- Early-in iterative divide. Minimum 11 and
maximum 33 clock latency (dividend (rs) sign
extension-dependent)
3.1
Features
• 5-Stage Pipeline
• Power Control
• 32-Bit Address and Data Paths
• MIPS32 Enhanced Architecture (Release 2)
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
instruction)
- Multiply-Accumulate and Multiply-Subtract
instructions
- Extensive use of local gated clocks
• EJTAG Debug and Instruction Trace
- Support for single stepping
- Targeted Multiply instruction
- Zero/One Detect instructions
- WAITinstruction
- Virtual instruction and data address/value
- Breakpoints
- Conditional Move instructions (MOVN, MOVZ)
- Vectored interrupts
- PC tracing with trace compression
- Programmable exception vector base
FIGURE 3-1:
MCU
MCU BLOCK DIAGRAM
Trace I/F
EJTAG
MDU
Trace
TAP
Off-Chip
Debug I/F
Execution
Core
(RF/ALU/Shift)
FMT
Bus Interface
Dual Bus I/F
System
Coprocessor
Power
Management
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 39
PIC32MX5XX/6XX/7XX
3.2.2
MULTIPLY/DIVIDE UNIT (MDU)
3.2
Architecture Overview
The PIC32MX5XX/6XX/7XX family core includes a
Multiply/Divide Unit (MDU) that contains a separate
pipeline for multiply and divide operations. This pipeline
operates in parallel with the Integer Unit (IU) pipeline
and does not stall when the IU pipeline stalls. This
allows MDU operations to be partially masked by
system stalls and/or other integer unit instructions.
The PIC32MX5XX/6XX/7XX family core contains sev-
eral logic blocks working together in parallel, providing
an efficient high-performance computing engine. The
following blocks are included with the core:
• Execution Unit
• Multiply/Divide Unit (MDU)
• System Control Coprocessor (CP0)
• Fixed Mapping Translation (FMT)
• Dual Internal Bus interfaces
• Power Management
The high-performance MDU consists of a 32x16 booth
recoded multiplier, result/accumulation registers (HI
and LO), a divide state machine, and the necessary
multiplexers and control logic. The first number shown
(‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
PIC32MX core only checks the value of the latter (rt)
operand to determine how many times the operation
must pass through the multiplier. The 16x16 and 32x16
operations pass through the multiplier once. A 32x32
operation passes through the multiplier twice.
• MIPS16e Support
• Enhanced JTAG (EJTAG) Controller
3.2.1
EXECUTION UNIT
The PIC32MX5XX/6XX/7XX family core execution unit
implements a load/store architecture with single-cycle
ALU operations (logical, shift, add, subtract) and an
autonomous multiply/divide unit. The core contains
thirty-two 32-bit General Purpose Registers (GPRs)
used for integer operations and address calculation.
One additional register file shadow set (containing
thirty-two registers) is added to minimize context
switching overhead during interrupt/exception process-
ing. The register file consists of two read ports and one
write port and is fully bypassed to minimize operation
latency in the pipeline.
The MDU supports execution of one 16x16 or 32x16
multiply operation every clock cycle; 32x32 multiply
operations can be issued every other clock cycle.
Appropriate interlocks are implemented to stall the
issuance of back-to-back 32x32 multiply operations.
The multiply operand size is automatically determined
by logic built into the MDU.
Divide operations are implemented with a simple 1 bit
per clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand.
If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit
wide rs, 15 iterations are skipped and for a 24-bit wide
rs, 7 iterations are skipped. Any attempt to issue a sub-
sequent MDU instruction while a divide is still active
causes an IU pipeline stall until the divide operation is
completed.
The execution unit includes:
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
address
• Logic for branch determination and branch target
address calculation
• Load aligner
Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency (num-
ber of cycles until a result is available) for the PIC32MX
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
• Bypass multiplexers used to avoid stalls when
executing instruction streams where data
producing instructions are followed closely by
consumers of their results
• Leading Zero/One detect unit for implementing
the CLZand CLOinstructions
• Arithmetic Logic Unit (ALU) for performing bitwise
logical operations
• Shifter and store aligner
DS61156C-page 40
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 3-1:
PIC32MX5XX/6XX/7XX FAMILY CORE HIGH-PERFORMANCE INTEGER
MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
Opcode
Operand Size (mul rt) (div rs)
Latency
Repeat Rate
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU
16 bits
32 bits
16 bits
32 bits
8 bits
1
2
1
2
MUL
2
1
3
2
DIV/DIVU
12
19
26
33
11
18
25
32
16 bits
24 bits
32 bits
The MIPS architecture defines that the result of a
multiply or divide operation be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and Move-
From-LO (MFLO) instructions, these values can be
transferred to the General Purpose Register file.
3.2.3
SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (Kernel, User and Debug) and
whether interrupts are enabled or disabled. Configura-
tion information, such as presence of options like
MIPS16e, is also available by accessing the CP0
registers, listed in Table 3-2.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction,
MUL, which places the least significant results in the pri-
mary register file instead of the HI/LO register pair. By
avoiding the explicit MFLO instruction required when
using the LO register, and by supporting multiple desti-
nation registers, the throughput of multiply-intensive
operations is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADDinstruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUBinstruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 41
PIC32MX5XX/6XX/7XX
TABLE 3-2:
COPROCESSOR 0 REGISTERS
Register
Number
Register
Name
Function
0-6
7
Reserved
Reserved in the PIC32MX5XX/6XX/7XX family core.
Enables access via the RDHWRinstruction to selected hardware registers.
Reports the address for the most recent address-related exception.
Processor cycle count.
HWREna
BadVAddr(1)
Count(1)
Reserved
Compare(1)
Status(1)
IntCtl(1)
SRSCtl(1)
SRSMap(1)
Cause(1)
EPC(1)
8
9
10
11
Reserved in the PIC32MX5XX/6XX/7XX family core.
Timer interrupt control.
12
12
12
12
13
14
15
15
16
16
16
16
17-22
23
24
25-29
30
31
Processor status and control.
Interrupt system status and control.
Shadow register set status and control.
Provides mapping from vectored interrupt to a shadow set.
Cause of last general exception.
Program counter at last exception.
PRId
Processor identification and revision.
Exception vector base register.
EBASE
Config
Configuration register.
Config1
Configuration Register 1.
Config2
Configuration Register 2.
Config3
Configuration Register 3.
Reserved
Debug(2)
DEPC(2)
Reserved
ErrorEPC(1)
DESAVE(2)
Reserved in the PIC32MX5XX/6XX/7XX family core.
Debug control and exception status.
Program counter at last debug exception.
Reserved in the PIC32MX5XX/6XX/7XX family core.
Program counter at last error.
Debug handler scratchpad register.
Note 1: Registers used in exception processing.
2: Registers used during debug.
DS61156C-page 42
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events or program errors. Table 3-3 lists
the exception types in order of priority.
TABLE 3-3:
Exception
PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES
Description
Reset
DSS
Assertion MCLR or a Power-on Reset (POR).
EJTAG debug single step.
DINT
EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
NMI
Assertion of NMI signal.
Interrupt
DIB
Assertion of unmasked hardware or software interrupt signal.
EJTAG debug hardware instruction break matched.
AdEL
Fetch address alignment error.
Fetch reference to protected address.
IBE
Instruction fetch bus error.
DBp
Sys
EJTAG breakpoint (execution of SDBBPinstruction).
Execution of SYSCALLinstruction.
Bp
Execution of BREAKinstruction.
RI
Execution of a reserved instruction.
CpU
CEU
Ov
Execution of a coprocessor instruction for a coprocessor that is not enabled.
Execution of a CorExtend instruction when CorExtendis not enabled.
Execution of an arithmetic instruction that overflowed.
Execution of a trap (when trap condition is true).
EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).
Tr
DDBL/DDBS
AdEL
Load address alignment error.
Load reference to protected address.
AdES
Store address alignment error.
Store to protected address.
DBE
Load or store bus error.
DDBL
EJTAG data hardware breakpoint matched in load data compare.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 43
PIC32MX5XX/6XX/7XX
3.3
Power Management
3.4
EJTAG Debug Support
The PIC32MX5XX/6XX/7XX family core offers a number
of power management features, including low-power
design, active power management and power-down
modes of operation. The core is a static design that
supports slowing or Halting the clocks, which reduces
system power consumption during Idle periods.
The PIC32MX5XX/6XX/7XX family core provides for
an Enhanced JTAG (EJTAG) interface for use in the
software debug of application and kernel code. In
addition to standard User mode and Kernel modes of
operation, the PIC32MX5XX/6XX/7XX family core pro-
vides a Debug mode that is entered after a debug
exception (derived from a hardware breakpoint, single-
step exception, etc.) is taken and continues until a
Debug Exception Return (DERET) instruction is
executed. During this time, the processor executes the
debug exception handler routine.
3.3.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 27.0
“Power-Saving Features”.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for trans-
ferring
test
data
in
and
out
of
the
3.3.2
LOCAL CLOCK GATING
PIC32MX5XX/6XX/7XX family core. In addition to the
standard JTAG instructions, special instructions
defined in the EJTAG specification define which
registers are selected and how they are used.
The majority of the power consumed by the
PIC32MX5XX/6XX/7XX family core is in the clock tree
and clocking registers. The PIC32MX family uses
extensive use of local gated clocks to reduce this
dynamic power consumption.
DS61156C-page 44
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
4.1
PIC32MX5XX/6XX/7XX Memory
Layout
4.0
MEMORY ORGANIZATION
Note:
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a compre-
hensive reference source. For detailed
information, refer to Section 3. “Memory
PIC32MX5XX/6XX/7XX microcontrollers implement
two address schemes: virtual and physical. All
hardware resources, such as program memory, data
memory and peripherals, are located at their respective
physical addresses. Virtual addresses are exclusively
used by the CPU to fetch and execute instructions as
well as access peripherals. Physical addresses are
used by bus master peripherals, such as DMA and the
Flash controller, that access memory independently of
the CPU.
Organization”
(DS61115)
in
the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB
of unified virtual memory address space. All memory
regions, including program, data memory, SFRs and
Configuration registers, reside in this address space at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, the data memory can
be made executable, allowing PIC32MX5XX/6XX/7XX
devices to execute from data memory.
The memory maps for the PIC32MX5XX/6XX/7XX
devices are shown in Figure 4-1, Figure 4-2 and
Figure 4-3.
4.1.1
PERIPHERAL REGISTERS
LOCATIONS
Table 4-1 through Table 4-44 contain the peripheral
address maps for the PIC32MX5XX/6XX/7XX
devices. Peripherals located on the PB bus are
mapped to 512-byte boundaries. Peripherals on the
FPB bus are mapped to 4-Kbyte boundaries.
Key features include:
• 32-bit native data width
• Separate User (KUSEG) and Kernel
(KSEG0/KSEG1) mode address space
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
program space
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
runaway code
• Simple memory mapping with Fixed Mapping
Translation (FMT) unit
• Cacheable (KSEG0) and non-cacheable (KSEG1)
address regions
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 45
PIC32MX5XX/6XX/7XX
FIGURE 4-1:
MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L,
PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND
PIC32MX775F256L DEVICES(1)
Virtual
Memory Map
Physical
Memory Map
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FF0
0xBFC02FEF
Boot Flash
Reserved
SFRs
0xBFC00000
0xBF900000
0xBF8FFFFF
Reserved
0xBF800000
Reserved
0xBD040000
0xBD03FFFF
(2)
Program Flash
Reserved
0xBD000000
0xA0010000
0xA000FFFF
(2)
RAM
0xA0000000
0x1FC03000
0x1FC02FFF
Device
Configuration
Registers
Reserved
0x9FC02FF0
0x9FC02FFF
Device
Configuration
Registers
0x1FC02FF0
0x1FC02FEF
0x9FC02FEF
0x9FC02FEF
Boot Flash
Reserved
SFRs
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x1F8FFFFF
0x9D040000
0x9D03FFFF
0x1F800000
(2)
Program Flash
Reserved
Reserved
0x9D000000
0x1D040000
0x1D03FFFF
(2)
0x80008000
0x80007FFF
Program Flash
Reserved
0x1D000000
(2)
RAM
0x80000000
0x00000000
0x00010000
0x0000FFFF
0x00000000
(2)
Reserved
RAM
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end user development
tools (refer to the specific development tool documentation for information).
DS61156C-page 46
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 4-2:
MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L,
PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND
PIC32MX775F512L DEVICES
Virtual
Physical
Memory Map
Memory Map
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FF0
0xBFC02FEF
Boot Flash
Reserved
SFRs
0xBFC00000
0xBF900000
0xBF8FFFFF
Reserved
0xBF800000
Reserved
0xBD080000
0xBD07FFFF
(2)
Program Flash
Reserved
0xBD000000
0xA0010000
0xA000FFFF
(2)
RAM
0xA0000000
0x1FC03000
0x1FC02FFF
Device
Configuration
Registers
Reserved
0x9FC02FF0
0x9FC02FFF
Device
Configuration
Registers
0x1FC02FF0
0x1FC02FEF
0x9FC02FEF
0x9FC02FEF
Boot Flash
Reserved
SFRs
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x1F8FFFFF
0x9D080000
0x9D07FFFF
0x1F800000
(2)
Program Flash
Reserved
Reserved
0x9D000000
0x1D080000
0x1D07FFFF
(2)
0x80010000
0x8000FFFF
Program Flash
Reserved
0x1D000000
(2)
RAM
0x80000000
0x00000000
0x00010000
0x0000FFFF
0x00000000
(2)
Reserved
RAM
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end user development
tools (refer to the specific development tool documentation for information).
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 47
PIC32MX5XX/6XX/7XX
FIGURE 4-3:
MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L,
PIC32MX795F512H AND PIC32MX795F512L DEVICES
Virtual
Physical
Memory Map
Memory Map
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FF0
0xBFC02FEF
Boot Flash
Reserved
SFRs
0xBFC00000
0xBF900000
0xBF8FFFFF
Reserved
0xBF800000
Reserved
0xBD080000
0xBD07FFFF
(2)
Program Flash
Reserved
0xBD000000
0xA0020000
0xA001FFFF
(2)
RAM
0xA0000000
0x1FC03000
0x1FC02FFF
Device
Configuration
Registers
Reserved
0x9FC02FF0
0x9FC02FFF
Device
Configuration
Registers
0x1FC02FF0
0x1FC02FEF
0x9FC02FEF
0x9FC02FEF
Boot Flash
Reserved
SFRs
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x1F8FFFFF
0x9D080000
0x9D07FFFF
0x1F800000
(2)
Program Flash
Reserved
Reserved
0x9D000000
0x1D080000
0x1D07FFFF
(2)
0x80020000
0x8001FFFF
Program Flash
Reserved
0x1D000000
(2)
RAM
0x80000000
0x00000000
0x00020000
0x0001FFFF
0x00000000
(2)
Reserved
RAM
Note 1: Memory areas are not shown to scale.
2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end user development
tools (refer to the specific development tool documentation for information).
DS61156C-page 48
Preliminary
2010 Microchip Technology Inc.
TABLE 4-1:
BUS MATRIX REGISTER MAP
Bits
31/15
30/14
29/13 28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
BMXCHEDMA
—
—
—
—
—
BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F
2000 BMXCON(1)
2010 BMXDKPBA(1)
2020 BMXDUDBA(1)
2030 BMXDUPBA(1)
2040 BMXDRMSZ
2050 BMXPUPBA(1)
2060 BMXPFMSZ
2070 BMXBOOTSZ
15:0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BMXWSDRM
—
—
—
—
—
—
—
BMXARB<2:0>
—
0040
0000
0000
0000
0000
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
3000
—
—
—
—
—
—
BMXDKPBA<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BMXDUDBA<15:0>
31:16
15:0
—
—
BMXDUPBA<15:0>
31:16
15:0
BMXDRMSZ<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
BMXPUPBA<19:16>
BMXPUPBA<15:0>
31:16
15:0
BMXPFMSZ<31:0>
31:16
15:0
BMXBOOTSZ<31:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-2:
INTERRUPT REGISTER MAP FOR THE PIC32MX575F256H AND PIC32MX575F512H DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
FRZ
—
—
—
—
—
—
MVEC
—
—
—
—
—
—
—
—
TPC<2:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4EP
—
—
—
—
SS0
0000
1000 INTCON
1010 INTSTAT
1020 IPTMR
INT3EP INT2EP INT1EP INT0EP 0000
31:16
15:0
—
—
—
—
0000
0000
0000
0000
—
—
RIPL<2:0>
VEC<5:0>
31:16
15:0
IPTMR<31:0>
U1ATXIF U1ARXIF
U1AEIF
31:16 I2C1MIF I2CSIF
I2CBIF SPI1ATXIF SPI1ARXIF SPI1AEIF
I2C1AMIF I2C1ASIF I2C1ABIF
—
—
—
OC5IF
IC5IF
IC1IF
T5IF
T1IF
INT4IF
INT0IF
OC4IF
CS1IF
IC4IF
T4IF 0000
CTIF 0000
1030
IFS0
15:0
INT3IF
OC3IF
IC2EIF
IC3IF
T3IF
—
INT2IF
—
OC2IF
IC2IF
T2IF
INT1IF
OC1IF
CS0IF
31:16 IC3EIF
IC1EIF
CAN1IF
USBIF
FCEIF
DMA7IF
DMA6IF
DMA5IF DMA4IF DMA3IF DMA2IF DMA1IF DMA0IF 0000
U3ATXIF U3ARXIF U3AEIF
U2ATXIF U2ARXIF
U2AEIF
1040
1050
1060
IFS1
IFS2
IEC0
15:0 RTCCIF FSCMIF
—
—
—
—
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF CMP2IF CMP1IF
I2C3AMIF I2C3ASIF I2C3ASIF I2C2AMIF I2C2ASIF I2C2ABIF
PMPIF
AD1IF
CNIF 0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
U3BTXIF U3BRXIF
U1AEIE
U3BEIF
U2BTXIF U2BRXIF
U2BEIF
U1BTXIF U1BRXIF U1BEIF PMPEIF IC5EIF IC4EIF 0000
U1ATXIE U1ARXIE
31:16 I2C1MIE I2C1SIE I2C1BIE SPI1ATXIE SPI1ARXIE SPI1AEIE
I2C1AMIE I2C1ASIE I2C1ABIE
—
—
—
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE 0000
CTIE 0000
15:0
INT3IE
OC3IE
IC2EIE
IC3IE
T3IE
—
INT2IE
—
OC2IE
IC2IE
T2IE
INT1IE
OC1IE
IC1IE
T1IE
INT0IE
CS1IE
CS0IE
31:16 IC3EIE
IC1EIE
CAN1IE
USBIE
FCEIE
DMA7IE
DMA6IE
DMA5IE DMA4IE DMA3IE DMA2IE DMA1IE DMA0IE 0000
U3ATXIE U3ARXIE U3AEIE U2ATXIE U2ARXIE U2AEIE
1070
IEC1
15:0 RTCCIE FSCMIE
—
—
—
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE CMP2IE CMP1IE
I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE I2C2ABIE
PMPIE
AD1IE
CNIE 0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U2BEIE
—
—
—
—
—
—
—
0000
1080
1090
IEC2
IPC0
U3BTXIE U3BRXIE
INT0IP<2:0>
U3BEIE U2BTXIE U2BRXIE
U1BTXIE U1BRXIE U1BEIE PMPEIE IC5EIE IC4EIE 0000
31:16
15:0
INT0IS<1:0>
CS0IS<1:0>
INT1IS<1:0>
IC1IS<1:0>
—
—
—
—
—
—
—
—
CS1IP<2:0>
CTIP<2:0>
OC1IP<2:0>
T1IP<2:0>
CS1IS<1:0>
CTIS<1:0>
OC1IS<1:0>
T1IS<1:0>
0000
0000
0000
0000
CS0IP<2:0>
—
31:16
15:0
INT1IP<2:0>
—
10A0 IPC1
IC1IP<2:0>
—
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
TABLE 4-2:
INTERRUPT REGISTER MAP FOR THE PIC32MX575F256H AND PIC32MX575F512H DEVICES(1) (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT2IP<2:0>
IC2IP<2:0>
INT3IP<2:0>
IC3IP<2:0>
INT4IP<2:0>
IC4IP<2:0>
—
INT2IS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OC2IP<2:0>
T2IP<2:0>
OC2IS<1:0>
T2IS<1:0>
0000
0000
0000
0000
0000
0000
0000
0000
0000
10B0 IPC2
10C0 IPC3
10D0 IPC4
10E0 IPC5
IC2IS<1:0>
INT3IS<1:0>
IC3IS<1:0>
INT4IS<1:0>
IC4IS<1:0>
31:16
15:0
OC3IP<2:0>
T3IP<2:0>
OC3IS<1:0>
T3IS<1:0>
31:16
15:0
OC4IP<2:0>
T4IP<2:0>
OC4IS<1:0>
T4IS<1:0>
31:16
15:0
—
—
—
—
OC5IP<2:0>
T5IP<2:0>
OC5IS<1:0>
T5IS<1:0>
IC5IP<2:0>
AD1IP<2:0>
IC5IS<1:0>
31:16
AD1IS<1:0>
CNIP<2:0>
U1AIP<2:0>
SPI1AIP<2:0>
I2C1AIP<2:0>
CNIS<1:0>
U1AIS<1:0>
SPI1AIS<1:0>
I2C1AIS<1:0>
10F0 IPC6
15:0
—
—
—
—
—
—
I2C1IP<2:0>
I2C1IS<1:0>
—
—
—
—
—
—
0000
0000
U2AIP<2:0>
SPI2AIP<2:0>
I2C2AIP<2:0>
CMP1IP<2:0>
RTCCIP<2:0>
U2AIS<1:0>
SPI2AIS<1:0>
I2C2AIS<1:0>
CMP1IS<1:0>
RTCCIS<1:0>
31:16
CMP2IP<2:0>
CMP2IS<1:0>
1100
IPC7
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PMPIP<2:0>
FSCMIP<2:0>
U3AIP<2:0>
SPI3AIP<2:0>
I2C3AIP<2:0>
DMA2IP<2:0>
DMA0IP<2:0>
DMA6IP<2:0>
DMA4IP<2:0>
CAN1IP<2:0>
FCEIP<2:0>
U2BIP<2:0>
—
PMPIS<1:0>
FSCMIS<1:0>
U3AIS<1:0>
0000
0000
31:16
1110
1120
IPC8
IPC9
15:0
—
—
—
—
—
—
—
—
—
—
—
SPI3AIS<1:0>
I2C3AIS<1:0>
DMA2IS<1:0>
DMA0IS<1:0>
DMA6IS<1:0>
DMA4IS<1:0>
CAN1IS<1:0>
FCEIS<1:0>
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMA3IP<2:0>
DMA1IP<2:0>
DMA7IP<2:0>
DMA5IP<2:0>
—
DMA3IS<1:0>
DMA1IS<1:0>
DMA7IS<1:0>
DMA5IS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
31:16
15:0
1130 IPC10
1140 IPC11
1150 IPC12
31:16
15:0
—
—
—
—
USBIP<2:0>
U3BIP<2:0>
U1BIP<2:0>
USBIS<1:0>
31:16
15:0
U3BIS<1:0>
U1BIS<1:0>
U2BIS<1:0>
—
—
—
—
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
TABLE 4-3:
INTERRUPT REGISTER MAP FOR THE PIC32MX675F256H, PIC32MX675F512H AND
PIC32MX695F512H DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
FRZ
—
—
—
—
—
—
MVEC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4EP
—
—
INT3EP
—
—
INT2EP
—
—
INT1EP
—
SS0
INT0EP
—
0000
0000
0000
0000
0000
0000
1000 INTCON
1010 INTSTAT
1020 IPTMR
TPC<2:0>
—
31:16
15:0
—
—
RIPL<2:0>
VEC<5:0>
31:16
15:0
IPTMR<31:0>
U1ATXIF U1ARXIF
U1AEIF
31:16 I2C1MIF
I2CSIF
I2CBIF SPI1ATXIF SPI1ARXIF SPI1AEIF
I2C1AMIF I2C1ASIF I2C1ABIF
—
—
—
OC5IF
IC5IF
T5IF
INT4IF
OC4IF
IC4IF
T4IF
0000
1030
IFS0
15:0 INT3IF
OC3IF
IC2EIF
IC3IF
T3IF
INT2IF
—
OC2IF
—
IC2IF
T2IF
INT1IF
OC1IF
IC1IF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
0000
31:16 IC3EIF
15:0 RTCCIF
IC1EIF
ETHIF
USBIF
FCEIF
U3AEIF
DMA7IF
DMA6IF
DMA5IF
U2AEIF
DMA4IF
DMA3IF
DMA2IF
DMA1IF
DMA0IF
U3ATXIF U3ARXIF
U2ATXIF U2ARXIF
1040
1050
1060
IFS1
IFS2
IEC0
FSCMIF
—
—
—
—
—
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF CMP2IF
I2C3AMIF I2C3ASIF I2C3ASIF I2C2AMIF I2C2ASIF I2C2ABIF
CMP1IF
PMPIF
AD1IF
CNIF
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
U3BTXIF U3BRXIF
U1AEIE
U3BEIF
U2BTXIF U2BRXIF
U2BEIF
U1BTXIF U1BRXIF
U1BEIF
PMPEIF
IC5EIF
IC4EIF
U1ATXIE U1ARXIE
31:16 I2C1MIE
I2C1SIE
I2C1BIE SPI1ATXIE SPI1ARXIE SPI1AEIE
I2C1AMIE I2C1ASIE I2C1ABIE
—
—
—
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
15:0 INT3IE
OC3IE
IC2EIE
IC3IE
T3IE
INT2IE
—
OC2IE
—
IC2IE
T2IE
INT1IE
OC1IE
IC1IE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
0000
0000
31:16 IC3EIE
15:0 RTCCIE
IC1EIE
ETHIE
USBIE
FCEIE
DMA7IE
DMA6IE
DMA5IE
DMA4IE
DMA3IE
DMA2IE
DMA1IE
DMA0IE
U3ATXIE U3ARXIE U3AEIE
U2ATXIE U2ARXIE U2AEIE
1070
IEC1
FSCMIE
—
—
—
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE CMP2IE
I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE I2C2ABIE
CMP1IE
PMPIE
AD1IE
CNIE
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1080
1090
10A0
10B0
10C0
IEC2
IPC0
IPC1
IPC2
IPC3
U3BTXIE U3BRXIE
INT0IP<2:0>
CS0IP<2:0>
INT1IP<2:0>
IC1IP<2:0>
U3BEIE
U2BTXIE U2BRXIE U2BEIE
U1BTXIE U1BRXIE
U1BEIE
PMPEIE
IC5EIE
IC4EIE
31:16
15:0
INT0IS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CS1IP<2:0>
CTIP<2:0>
OC1IP<2:0>
T1IP<2:0>
OC2IP<2:0>
T2IP<2:0>
OC3IP<2:0>
T3IP<2:0>
CS1IS<1:0>
CS0IS<1:0>
INT1IS<1:0>
IC1IS<1:0>
INT2IS<1:0>
IC2IS<1:0>
INT3IS<1:0>
IC3IS<1:0>
CTIS<1:0>
OC1IS<1:0>
T1IS<1:0>
OC2IS<1:0>
T2IS<1:0>
OC3IS<1:0>
T3IS<1:0>
31:16
15:0
31:16
15:0
INT2IP<2:0>
IC2IP<2:0>
31:16
15:0
INT3IP<2:0>
IC3IP<2:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-3:
INTERRUPT REGISTER MAP FOR THE PIC32MX675F256H, PIC32MX675F512H AND
PIC32MX695F512H DEVICES(1) (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4IP<2:0>
IC4IP<2:0>
—
INT4IS<1:0>
IC4IS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OC4IP<2:0>
T4IP<2:0>
OC4IS<1:0>
0000
0000
0000
0000
0000
10D0
10E0
IPC4
IPC5
T4IS<1:0>
OC5IS<1:0>
T5IS<1:0>
31:16
15:0
—
—
—
—
OC5IP<2:0>
T5IP<2:0>
IC5IP<2:0>
AD1IP<2:0>
IC5IS<1:0>
AD1IS<1:0>
31:16
CNIP<2:0>
CNIS<1:0>
U1AIP<2:0>
SPI1AIP<2:0>
I2C1AIP<2:0>
U1AIS<1:0>
SPI1AIS<1:0>
I2C1AIS<1:0>
10F0
1100
IPC6
IPC7
15:0
—
—
—
—
—
—
I2C1IP<2:0>
I2C1IS<1:0>
—
—
—
—
—
—
0000
0000
U2AIP<2:0>
SPI2AIP<2:0>
I2C2AIP<2:0>
CMP1IP<2:0>
RTCCIP<2:0>
U2AIS<1:0>
SPI2AIS<1:0>
I2C2AIS<1:0>
CMP1IS<1:0>
RTCCIS<1:0>
31:16
CMP2IP<2:0>
CMP2IS<1:0>
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PMPIP<2:0>
FSCMIP<2:0>
U3AIP<2:0>
SPI3AIP<2:0>
I2C3AIP<2:0>
DMA2IP<2:0>
DMA0IP<2:0>
DMA6IP<2:0>
DMA4IP<2:0>
—
PMPIS<1:0>
FSCMIS<1:0>
U3AIS<1:0>
0000
0000
31:16
1110
1120
IPC8
IPC9
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
SPI3AIS<1:0>
I2C3AIS<1:0>
DMA2IS<1:0>
DMA0IS<1:0>
DMA6IS<1:0>
DMA4IS<1:0>
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMA3IP<2:0>
DMA1IP<2:0>
DMA7IP<2:0>
DMA5IP<2:0>
—
DMA3IS<1:0>
DMA1IS<1:0>
DMA7IS<1:0>
DMA5IS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
31:16
15:0
1130 IPC10
1140 IPC11
1150 IPC12
31:16
15:0
—
—
—
—
—
—
USBIP<2:0>
U3BIP<2:0>
U1BIP<2:0>
USBIS<1:0>
FCEIP<2:0>
U2BIP<2:0>
ETHIP<2:0>
FCEIS<1:0>
31:16
15:0
U3BIS<1:0>
U1BIS<1:0>
U2BIS<1:0>
ETHIS<1:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-4:
INTERRUPT REGISTER MAP FOR PIC32MX775F256H, PIC32MX775F512H AND
PIC32MX795F512H DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
FRZ
—
—
—
—
—
—
MVEC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4EP
—
—
INT3EP
—
—
INT2EP
—
—
INT1EP
—
SS0
INT0EP
—
0000
0000
0000
0000
0000
0000
1000 INTCON
1010 INTSTAT
1020 IPTMR
TPC<2:0>
—
31:16
15:0
—
—
RIPL<2:0>
VEC<5:0>
31:16
15:0
IPTMR<31:0>
U1ATXIF U1ARXIF
U1AEIF
31:16 I2C1MIF
I2CSIF
I2CBIF SPI1ATXIF SPI1ARXIF SPI1AEIF
I2C1AMIF I2C1ASIF I2C1ABIF
—
—
—
OC5IF
IC5IF
T5IF
INT4IF
OC4IF
IC4IF
T4IF
0000
1030
IFS0
15:0 INT3IF
OC3IF
IC2EIF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
INT1IF
OC1IF
IC1IF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
0000
31:16 IC3EIF
15:0 RTCCIF
IC1EIF
ETHIF
CAN2IF
CAN1IF
USBIF
FCEIF
U3AEIF
DMA7IF
DMA6IF
DMA5IF
U2AEIF
DMA4IF
DMA3IF
DMA2IF
DMA1IF
DMA0IF
U3ATXIF U3ARXIF
U2ATXIF U2ARXIF
1040
1050
1060
IFS1
IFS2
IEC0
FSCMIF
—
—
—
—
SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF CMP2IF
I2C3AMIF I2C3ASIF I2C3ASIF I2C2AMIF I2C2ASIF I2C2ABIF
CMP1IF
PMPIF
AD1IF
CNIF
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
U3BTXIF U3BRXIF
U3BEIF
U2BTXIF U2BRXIF
U2BEIF
U1BTXIF U1BRXIF
U1BEIF
PMPEIF
IC5EIF
IC4EIF
U1ATXIE U1ARXIE U1AEIE
31:16 I2C1MIE
I2C1SIE
I2C1BIE SPI1ATXIE SPI1ARXIE SPI1AEIE
I2C1AMIE I2C1ASIE I2C1ABIE
—
—
—
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
15:0 INT3IE
OC3IE
IC2EIE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
INT1IE
OC1IE
IC1IE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
0000
0000
31:16 IC3EIE
15:0 RTCCIE
IC1EIE
ETHIE
CAN2IE
CAN1IE
USBIE
FCEIE
DMA7IE
DMA6IE
DMA5IE
DMA4IE
DMA3IE
DMA2IE
DMA1IE
DMA0IE
U3ATXIE U3ARXIE U3AEIE
U2ATXIE U2ARXIE U2AEIE
1070
IEC1
FSCMIE
—
—
—
—
SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE CMP2IE
I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE I2C2ABIE
CMP1IE
—
PMPIE
AD1IE
CNIE
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U2BEIE
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
1080
1090
10A0
10B0
10C0
IEC2
IPC0
IPC1
U3BTXIE U3BRXIE U3BEIE
U2BTXIE U2BRXIE
—
U1BTXIE U1BRXIE U1BEIE
PMPEIE
IC5EIE
IC4EIE
31:16
15:0
INT0IP<2:0>
CS0IP<2:0>
INT1IP<2:0>
IC1IP<2:0>
INT0IS<1:0>
—
—
—
—
CS1IP<2:0>
CTIP<2:0>
OC1IP<2:0>
T1IP<2:0>
CS1IS<1:0>
CS0IS<1:0>
—
—
—
—
CTIS<1:0>
OC1IS<1:0>
T1IS<1:0>
31:16
15:0
INT1IS<1:0>
IC1IS<1:0>
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
INT2IP<2:0>
IC2IP<2:0>
INT3IP<2:0>
IC3IP<2:0>
INT2IS<1:0>
IC2IS<1:0>
INT3IS<1:0>
IC3IS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
OC2IP<2:0>
T2IP<2:0>
OC3IP<2:0>
T3IP<2:0>
OC2IS<1:0>
T2IS<1:0>
OC3IS<1:0>
T3IS<1:0>
0000
0000
0000
0000
IPC2
IPC3
31:16
15:0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-4:
INTERRUPT REGISTER MAP FOR PIC32MX775F256H, PIC32MX775F512H AND
PIC32MX795F512H DEVICES(1) (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4IP<2:0>
IC4IP<2:0>
—
INT4IS<1:0>
IC4IS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OC4IP<2:0>
T4IP<2:0>
OC4IS<1:0>
0000
0000
0000
0000
0000
10D0
10E0
IPC4
IPC5
T4IS<1:0>
OC5IS<1:0>
T5IS<1:0>
31:16
15:0
—
—
—
—
OC5IP<2:0>
T5IP<2:0>
IC5IP<2:0>
AD1IP<2:0>
IC5IS<1:0>
AD1IS<1:0>
31:16
CNIP<2:0>
CNIS<1:0>
U1AIP<2:0>
SPI1AIP<2:0>
I2C1AIP<2:0>
U1AIS<1:0>
SPI1AIS<1:0>
I2C1AIS<1:0>
10F0
1100
IPC6
IPC7
15:0
—
—
—
—
—
—
I2C1IP<2:0>
I2C1IS<1:0>
—
—
—
—
—
—
0000
0000
U2AIP<2:0>
SPI2AIP<2:0>
I2C2AIP<2:0>
CMP1IP<2:0>
RTCCIP<2:0>
U2AIS<1:0>
SPI2AIS<1:0>
I2C2AIS<1:0>
CMP1IS<1:0>
RTCCIS<1:0>
31:16
CMP2IP<2:0>
CMP2IS<1:0>
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PMPIP<2:0>
FSCMIP<2:0>
U3AIP<2:0>
PMPIS<1:0>
FSCMIS<1:0>
U3AIS<1:0>
0000
0000
31:16
1110
1120
IPC8
IPC9
15:0
—
—
—
—
—
—
—
—
—
—
—
SPI3AIP<2:0>
I2C3AIP<2:0>
DMA2IP<2:0>
DMA0IP<2:0>
DMA6IP<2:0>
DMA4IP<2:0>
CAN1IP<2:0>
FCEIP<2:0>
U2BIP<2:0>
SPI3AIS<1:0>
I2C3AIS<1:0>
DMA2IS<1:0>
DMA0IS<1:0>
DMA6IS<1:0>
DMA4IS<1:0>
CAN1IS<1:0>
FCEIS<1:0>
U2BIS<1:0>
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMA3IP<2:0>
DMA1IP<2:0>
DMA7IP<2:0>
DMA5IP<2:0>
CAN2IP<2:0>
USBIP<2:0>
U3BIP<2:0>
U1BIP<2:0>
DMA3IS<1:0>
DMA1IS<1:0>
DMA7IS<1:0>
DMA5IS<1:0>
CAN2IS<1:0>
USBIS<1:0>
U3BIS<1:0>
U1BIS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
31:16
15:0
1130 IPC10
1140 IPC11
1150 IPC12
31:16
15:0
31:16
15:0
ETHIP<2:0>
ETHIS<1:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-5:
INTERRUPT REGISTER MAP FOR THE PIC32MX575F512L AND PIC32MX575F256L DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
FRZ
—
—
—
—
—
—
MVEC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4EP
—
—
INT3EP
—
—
INT2EP
—
—
INT1EP
—
SS0
0000
1000 INTCON
1010 INTSTAT
1020 IPTMR
TPC<2:0>
—
INT0EP 0000
31:16
15:0
—
0000
0000
0000
0000
—
—
RIPL<2:0>
VEC<5:0>
31:16
15:0
IPTMR<31:0>
U1ATXIF U1ARXIF
U1AEIF
31:16 I2C1MIF
I2CSIF
I2CBIF SPI1ATXIF SPI1ARXIF SPI1AEIF SPI1TXIF SPI1RXIF SPI1EIF
I2C1AMIF I2C1ASIF I2C1ABIF
OC5IF
IC5IF
T5IF
INT4IF
OC4IF
IC4IF
T4IF
CTIF
0000
1030
IFS0
15:0
INT3IF
IC3EIF
OC3IF
IC2EIF
IC3IF
T3IF
—
INT2IF
—
OC2IF
IC2IF
T2IF
INT1IF
OC1IF
IC1IF
T1IF
INT0IF
CS1IF
CS0IF
0000
31:16
IC1EIF
CAN1IF
USBIF
FCEIF
U3AEIF
DMA7IF
DMA6IF
DMA5IF
U2AEIF
DMA4IF
DMA3IF
DMA2IF
DMA1IF
DMA0IF 0000
U3ATXIF U3ARXIF
U2ATXIF U2ARXIF
1040
1050
1060
IFS1
IFS2
IEC0
15:0
RTCCIF
FSCMIF
I2C2MIF
I2C2SIF
I2C2BIF SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF CMP2IF
I2C3AMIF I2C3ASIF I2C3ASIF I2C2AMIF I2C2ASIF I2C2ABIF
CMP1IF
PMPIF
AD1IF
CNIF
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
U3BTXIF U3BRXIF
U3BEIF
U2BTXIF U2BRXIF
U2BEIF
U1BTXIF U1BRXIF
U1BEIF
PMPEIF
IC5EIF
IC4EIF
U1ATXIE U1ARXIE U1AEIE
31:16 I2C1MIE
I2C1SIE
I2C1BIE SPI1ATXIE SPI1ARXIE SPI1AEIE SPI1TXIE SPI1RXIE SPI1EIE
I2C1AMIE I2C1ASIE I2C1ABIE
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
15:0
INT3IE
IC3EIE
OC3IE
IC2EIE
IC3IE
T3IE
—
INT2IE
—
OC2IE
IC2IE
T2IE
INT1IE
OC1IE
IC1IE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
0000
31:16
IC1EIE
CAN1IE
USBIE
FCEIE
DMA7IE
DMA6IE
DMA5IE
DMA4IE
DMA3IE
DMA2IE
DMA1IE
DMA0IE 0000
U3ATXIE U3ARXIE U3AEIE
U2ATXIE U2ARXIE U2AEIE
1070
IEC1
15:0
RTCCIE
FSCMIE
I2C2MIE
I2C2SIE
I2C2BIE SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE CMP2IE
I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE I2C2ABIE
CMP1IE
—
PMPIE
AD1IE
CNIE
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U2BEIE
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1080
1090
10A0
10B0
10C0
10D0
IEC2
IPC0
IPC1
IPC2
IPC3
IPC4
U3BTXIE U3BRXIE U3BEIE
U2BTXIE U2BRXIE
—
U1BTXIE U1BRXIE U1BEIE
PMPEIE
IC5EIE
IC4EIE
31:16
15:0
INT0IP<2:0>
CS0IP<2:0>
INT1IP<2:0>
IC1IP<2:0>
INT2IP<2:0>
IC2IP<2:0>
INT3IP<2:0>
IC3IP<2:0>
INT4IP<2:0>
IC4IP<2:0>
INT0IS<1:0>
—
—
—
—
—
—
—
—
—
—
CS1IP<2:0>
CTIP<2:0>
OC1IP<2:0>
T1IP<2:0>
OC2IP<2:0>
T2IP<2:0>
OC3IP<2:0>
T3IP<2:0>
OC4IP<2:0>
T4IP<2:0>
CS1IS<1:0>
CS0IS<1:0>
—
—
—
—
—
—
—
—
—
—
CTIS<1:0>
OC1IS<1:0>
T1IS<1:0>
OC2IS<1:0>
T2IS<1:0>
OC3IS<1:0>
T3IS<1:0>
OC4IS<1:0>
T4IS<1:0>
31:16
15:0
INT1IS<1:0>
IC1IS<1:0>
INT2IS<1:0>
IC2IS<1:0>
INT3IS<1:0>
IC3IS<1:0>
INT4IS<1:0>
IC4IS<1:0>
—
—
31:16
15:0
—
—
31:16
15:0
—
—
31:16
15:0
—
—
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-5:
INTERRUPT REGISTER MAP FOR THE PIC32MX575F512L AND PIC32MX575F256L DEVICES(1) (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
SPI1IP<2:0>
IC5IP<2:0>
AD1IP<2:0>
SPI1IS<1:0>
—
—
—
—
—
—
—
—
—
OC5IP<2:0>
T5IP<2:0>
OC5IS<1:0>
0000
0000
0000
10E0
10F0
IPC5
IPC6
IC5IS<1:0>
AD1IS<1:0>
T5IS<1:0>
CNIS<1:0>
31:16
CNIP<2:0>
U1AIP<2:0>
SPI1AIP<2:0>
I2C1AIP<2:0>
U1AIS<1:0>
SPI1AIS<1:0>
I2C1AIS<1:0>
15:0
—
—
—
—
—
—
I2C1IP<2:0>
I2C1IS<1:0>
—
—
—
—
—
—
0000
0000
U2AIP<2:0>
SPI2AIP<2:0>
I2C2AIP<2:0>
CMP1IP<2:0>
RTCCIP<2:0>
U2AIS<1:0>
SPI2AIS<1:0>
I2C2AIS<1:0>
CMP1IS<1:0>
RTCCIS<1:0>
31:16
CMP2IP<2:0>
CMP2IS<1:0>
1100
1110
IPC7
IPC8
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PMPIP<2:0>
FSCMIP<2:0>
U3AIP<2:0>
SPI3AIP<2:0>
I2C3AIP<2:0>
DMA2IP<2:0>
DMA0IP<2:0>
DMA6IP<2:0>
DMA4IP<2:0>
CAN1IP<2:0>
FCEIP<2:0>
U2BIP<2:0>
—
PMPIS<1:0>
FSCMIS<1:0>
U3AIS<1:0>
0000
0000
31:16
15:0
—
—
—
I2C2IP<2:0>
I2C2IS<1:0>
—
—
—
SPI3AIS<1:0>
I2C3AIS<1:0>
DMA2IS<1:0>
DMA0IS<1:0>
DMA6IS<1:0>
DMA4IS<1:0>
CAN1IS<1:0>
FCEIS<1:0>
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMA3IP<2:0>
DMA1IP<2:0>
DMA7IP<2:0>
DMA5IP<2:0>
—
DMA3IS<1:0>
DMA1IS<1:0>
DMA7IS<1:0>
DMA5IS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
1120
1130
1140
1150
IPC9
IPC10
IPC11
IPC12
31:16
15:0
31:16
15:0
—
—
—
—
USBIP<2:0>
U3BIP<2:0>
U1BIP<2:0>
USBIS<1:0>
31:16
15:0
U3BIS<1:0>
U1BIS<1:0>
U2BIS<1:0>
—
—
—
—
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-6:
INTERRUPT REGISTER MAP FOR PIC32MX675F256L, PIC32MX675F512L AND
PIC32MX695F512L DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
FRZ
—
—
—
—
—
—
MVEC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4EP
—
—
INT3EP
—
—
INT2EP
—
—
INT1EP
—
SS0
INT0EP
—
0000
0000
0000
0000
0000
0000
1000 INTCON
1010 INTSTAT
1020 IPTMR
15:0
31:16
15:0
TPC<2:0>
—
—
—
RIPL<2:0>
VEC<5:0>
31:16
15:0
IPTMR<31:0>
U1ATXIF U1ARXIF
U1AEIF
31:16 I2C1MIF
I2CSIF
I2CBIF SPI1ATXIF SPI1ARXIF SPI1AEIF SPI1TXIF SPI1RXIF SPI1EIF
I2C1AMIF I2C1ASIF I2C1ABIF
OC5IF
IC5IF
T5IF
INT4IF
OC4IF
IC4IF
T4IF
0000
1030
IFS0
15:0 INT3IF
OC3IF
IC2EIF
IC3IF
T3IF
INT2IF
—
OC2IF
—
IC2IF
T2IF
INT1IF
OC1IF
IC1IF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
0000
31:16 IC3EIF
15:0 RTCCIF
IC1EIF
ETHIF
USBIF
FCEIF
U3AEIF
DMA7IF
DMA6IF
DMA5IF
U2AEIF
DMA4IF
DMA3IF
DMA2IF
DMA1IF
DMA0IF
U3ATXIF U3ARXIF
U2ATXIF U2ARXIF
1040
1050
1060
IFS1
IFS2
IEC0
FSCMIF
I2C2MIF
I2C2SIF
I2C2BIF SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF CMP2IF
I2C3AMIF I2C3ASIF I2C3ASIF I2C2AMIF I2C2ASIF I2C2ABIF
CMP1IF
PMPIF
AD1IF
CNIF
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
U3BTXIF U3BRXIF
U1AEIE
U3BEIF
U2BTXIF U2BRXIF
U2BEIF
U1BTXIF U1BRXIF
U1BEIF
PMPEIF
IC5EIF
IC4EIF
U1ATXIE U1ARXIE
31:16 I2C1MIE
I2C1SIE
I2C1BIE SPI1ATXIE SPI1ARXIE SPI1AEIE SPI1TXIE SPI1RXIE SPI1EIE
I2C1AMIE I2C1ASIE I2C1ABIE
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
15:0 INT3IE
OC3IE
IC2EIE
IC3IE
T3IE
INT2IE
—
OC2IE
—
IC2IE
T2IE
INT1IE
OC1IE
IC1IE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
0000
0000
31:16 IC3EIE
15:0 RTCCIE
IC1EIE
ETHIE
USBIE
FCEIE
DMA7IE
DMA6IE
DMA5IE
DMA4IE
DMA3IE
DMA2IE
DMA1IE
DMA0IE
U3ATXIE U3ARXIE U3AEIE
U2ATXIE U2ARXIE U2AEIE
1070
IEC1
FSCMIE
I2C2MIE
I2C2SIE
I2C2BIE SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE CMP2IE
I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE I2C2ABIE
CMP1IE
PMPIE
AD1IE
CNIE
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1080
1090
10A0
10B0
10C0
IEC2
IPC0
IPC1
IPC2
IPC3
U3BTXIE U3BRXIE
INT0IP<2:0>
CS0IP<2:0>
INT1IP<2:0>
IC1IP<2:0>
U3BEIE
U2BTXIE U2BRXIE U2BEIE
U1BTXIE U1BRXIE
U1BEIE
PMPEIE
IC5EIE
IC4EIE
31:16
15:0
INT0IS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CS1IP<2:0>
CTIP<2:0>
OC1IP<2:0>
T1IP<2:0>
OC2IP<2:0>
T2IP<2:0>
OC3IP<2:0>
T3IP<2:0>
CS1IS<1:0>
CS0IS<1:0>
INT1IS<1:0>
IC1IS<1:0>
INT2IS<1:0>
IC2IS<1:0>
INT3IS<1:0>
IC3IS<1:0>
CTIS<1:0>
OC1IS<1:0>
T1IS<1:0>
OC2IS<1:0>
T2IS<1:0>
OC3IS<1:0>
T3IS<1:0>
31:16
15:0
31:16
15:0
INT2IP<2:0>
IC2IP<2:0>
31:16
15:0
INT3IP<2:0>
IC3IP<2:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-6:
INTERRUPT REGISTER MAP FOR PIC32MX675F256L, PIC32MX675F512L AND
PIC32MX695F512L DEVICES(1) (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4IP<2:0>
IC4IP<2:0>
SPI1IP<2:0>
IC5IP<2:0>
AD1IP<2:0>
INT4IS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OC4IP<2:0>
T4IP<2:0>
OC4IS<1:0>
0000
0000
0000
0000
0000
10D0
10E0
IPC4
IPC5
IC4IS<1:0>
SPI1IS<1:0>
IC5IS<1:0>
AD1IS<1:0>
T4IS<1:0>
OC5IS<1:0>
T5IS<1:0>
31:16
15:0
OC5IP<2:0>
T5IP<2:0>
31:16
CNIP<2:0>
CNIS<1:0>
U1AIP<2:0>
SPI1AIP<2:0>
I2C1AIP<2:0>
U1AIS<1:0>
SPI1AIS<1:0>
I2C1AIS<1:0>
10F0
1100
IPC6
IPC7
15:0
—
—
—
—
—
—
I2C1IP<2:0>
I2C1IS<1:0>
—
—
—
—
—
—
0000
0000
U2AIP<2:0>
SPI2AIP<2:0>
I2C2AIP<2:0>
CMP1IP<2:0>
RTCCIP<2:0>
U2AIS<1:0>
SPI2AIS<1:0>
I2C2AIS<1:0>
CMP1IS<1:0>
RTCCIS<1:0>
31:16
CMP2IP<2:0>
CMP2IS<1:0>
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PMPIP<2:0>
FSCMIP<2:0>
U3AIP<2:0>
SPI3AIP<2:0>
I2C3AIP<2:0>
DMA2IP<2:0>
DMA0IP<2:0>
DMA6IP<2:0>
DMA4IP<2:0>
—
PMPIS<1:0>
FSCMIS<1:0>
U3AIS<1:0>
0000
0000
31:16
1110
1120
IPC8
IPC9
15:0
—
—
—
I2C2IP<2:0>
I2C2IS<1:0>
—
—
—
SPI3AIS<1:0>
I2C3AIS<1:0>
DMA2IS<1:0>
DMA0IS<1:0>
DMA6IS<1:0>
DMA4IS<1:0>
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMA3IP<2:0>
DMA1IP<2:0>
DMA7IP<2:0>
DMA5IP<2:0>
—
DMA3IS<1:0>
DMA1IS<1:0>
DMA7IS<1:0>
DMA5IS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
31:16
15:0
1130 IPC10
1140 IPC11
1150 IPC12
31:16
15:0
—
—
—
—
—
—
—
—
USBIP<2:0>
U3BIP<2:0>
U1BIP<2:0>
USBIS<1:0>
FCEIP<2:0>
U2BIP<2:0>
ETHIP<2:0>
FCEIS<1:0>
31:16
15:0
U3BIS<1:0>
U1BIS<1:0>
U2BIS<1:0>
ETHIS<1:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-7:
INTERRUPT REGISTER MAP FOR PIC32MX775F256L, PIC32MX775F512L AND
PIC32MX795F512L DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
FRZ
—
—
—
—
—
—
MVEC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4EP
—
—
INT3EP
—
—
INT2EP
—
—
INT1EP
—
SS0
INT0EP
—
0000
0000
0000
0000
0000
0000
1000 INTCON
1010 INTSTAT
1020 IPTMR
TPC<2:0>
—
31:16
15:0
—
—
RIPL<2:0>
VEC<5:0>
31:16
15:0
IPTMR<31:0>
U1ATXIF U1ARXIF
U1AEIF
31:16 I2C1MIF
I2CSIF
I2CBIF SPI1ATXIF SPI1ARXIF SPI1AEIF SPI1TXIF SPI1RXIF SPI1EIF
I2C1AMIF I2C1ASIF I2C1ABIF
OC5IF
IC5IF
T5IF
INT4IF
OC4IF
IC4IF
T4IF
0000
1030
IFS0
15:0 INT3IF
OC3IF
IC2EIF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
INT1IF
OC1IF
IC1IF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
0000
31:16 IC3EIF
15:0 RTCCIF
IC1EIF
ETHIF
CAN2IF
CAN1IF
USBIF
FCEIF
U3AEIF
DMA7IF
DMA6IF
DMA5IF
U2AEIF
DMA4IF
DMA3IF
DMA2IF
DMA1IF
DMA0IF
U3ATXIF U3ARXIF
U2ATXIF U2ARXIF
1040
1050
1060
IFS1
IFS2
IEC0
FSCMIF
I2C2MIF
I2C2SIF
I2C2BIF SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF CMP2IF
I2C3AMIF I2C3ASIF I2C3ASIF I2C2AMIF I2C2ASIF I2C2ABIF
CMP1IF
PMPIF
AD1IF
CNIF
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
U3BTXIF U3BRXIF
U3BEIF
U2BTXIF U2BRXIF
U2BEIF
U1BTXIF U1BRXIF
U1BEIF
PMPEIF
IC5EIF
IC4EIF
U1ATXIE U1ARXIE U1AEIE
31:16 I2C1MIE
I2C1SIE
I2C1BIE SPI1ATXIE SPI1ARXIE SPI1AEIE SPI1TXIE SPI1RXIE SPI1EIE
I2C1AMIE I2C1ASIE I2C1ABIE
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
15:0 INT3IE
OC3IE
IC2EIE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
FCEIE
U3AEIE
INT1IE
OC1IE
IC1IE
T1IE
INT0IE
CS1IE
CS0IE
CTIE
0000
0000
31:16 IC3EIE
15:0 RTCCIE
IC1EIE
ETHIE
CAN2IE
CAN1IE
USBIE
DMA7IE
DMA6IE
DMA5IE
DMA4IE
DMA3IE
DMA2IE
DMA1IE
DMA0IE
U3ATXIE U3ARXIE
U2ATXIE U2ARXIE U2AEIE
1070
IEC1
FSCMIE
I2C2MIE
I2C2SIE
I2C2BIE SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE CMP2IE
I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE I2C2ABIE
CMP1IE
—
PMPIE
AD1IE
CNIE
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1080
1090
10A0
10B0
10C0
IEC2
IPC0
IPC1
IPC2
IPC3
U3BTXIE U3BRXIE U3BEIE
U2BTXIE U2BRXIE U2BEIE
U1BTXIE U1BRXIE U1BEIE
PMPEIE
IC5EIE
IC4EIE
31:16
15:0
INT0IP<2:0>
CS0IP<2:0>
INT1IP<2:0>
IC1IP<2:0>
INT2IP<2:0>
IC2IP<2:0>
INT3IP<2:0>
IC3IP<2:0>
INT0IS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CS1IP<2:0>
CTIP<2:0>
OC1IP<2:0>
T1IP<2:0>
OC2IP<2:0>
T2IP<2:0>
OC3IP<2:0>
T3IP<2:0>
CS1IS<1:0>
CS0IS<1:0>
INT1IS<1:0>
IC1IS<1:0>
INT2IS<1:0>
IC2IS<1:0>
INT3IS<1:0>
IC3IS<1:0>
CTIS<1:0>
OC1IS<1:0>
T1IS<1:0>
OC2IS<1:0>
T2IS<1:0>
OC3IS<1:0>
T3IS<1:0>
31:16
15:0
31:16
15:0
31:16
15:0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-7:
INTERRUPT REGISTER MAP FOR PIC32MX775F256L, PIC32MX775F512L AND
PIC32MX795F512L DEVICES(1) (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT4IP<2:0>
IC4IP<2:0>
SPI1IP<2:0>
IC5IP<2:0>
AD1IP<2:0>
INT4IS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OC4IP<2:0>
T4IP<2:0>
OC4IS<1:0>
0000
0000
0000
0000
0000
10D0
10E0
IPC4
IPC5
IC4IS<1:0>
SPI1IS<1:0>
IC5IS<1:0>
AD1IS<1:0>
T4IS<1:0>
OC5IS<1:0>
T5IS<1:0>
31:16
15:0
OC5IP<2:0>
T5IP<2:0>
31:16
CNIP<2:0>
CNIS<1:0>
U1AIP<2:0>
SPI1AIP<2:0>
I2C1AIP<2:0>
U1AIS<1:0>
SPI1AIS<1:0>
I2C1AIS<1:0>
10F0
1100
IPC6
IPC7
15:0
—
—
—
—
—
—
I2C1IP<2:0>
I2C1IS<1:0>
—
—
—
—
—
—
0000
0000
U2AIP<2:0>
SPI2AIP<2:0>
I2C2AIP<2:0>
CMP1IP<2:0>
RTCCIP<2:0>
U2AIS<1:0>
SPI2AIS<1:0>
I2C2AIS<1:0>
CMP1IS<1:0>
RTCCIS<1:0>
31:16
CMP2IP<2:0>
CMP2IS<1:0>
15:0
—
—
—
—
—
—
—
—
—
—
—
—
PMPIP<2:0>
FSCMIP<2:0>
U3AIP<2:0>
PMPIS<1:0>
FSCMIS<1:0>
U3AIS<1:0>
0000
0000
31:16
1110
1120
IPC8
IPC9
15:0
—
—
—
I2C2IP<2:0>
I2C2IS<1:0>
—
—
—
SPI3AIP<2:0>
I2C3AIP<2:0>
DMA2IP<2:0>
DMA0IP<2:0>
DMA6IP<2:0>
DMA4IP<2:0>
CAN1IP<2:0>
FCEIP<2:0>
U2BIP<2:0>
SPI3AIS<1:0>
I2C3AIS<1:0>
DMA2IS<1:0>
DMA0IS<1:0>
DMA6IS<1:0>
DMA4IS<1:0>
CAN1IS<1:0>
FCEIS<1:0>
U2BIS<1:0>
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMA3IP<2:0>
DMA1IP<2:0>
DMA7IP<2:0>
DMA5IP<2:0>
CAN2IP<2:0>
USBIP<2:0>
U3BIP<2:0>
U1BIP<2:0>
DMA3IS<1:0>
DMA1IS<1:0>
DMA7IS<1:0>
DMA5IS<1:0>
CAN2IS<1:0>
USBIS<1:0>
U3BIS<1:0>
U1BIS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
31:16
15:0
1130 IPC10
1140 IPC11
1150 IPC12
31:16
15:0
31:16
15:0
ETHIP<2:0>
ETHIS<1:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-8:
TIMER1-TIMER5 REGISTER MAP(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
ON
—
—
FRZ
—
—
SIDL
—
—
TWDIS
—
—
TWIP
—
—
—
—
—
—
—
—
—
—
—
TGATE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TSYNC
—
—
TCS
—
—
—
—
0000
0000
0000
0000
0000
FFFF
0000
0000
0000
0000
0000
FFFF
0000
0000
0000
0000
0000
FFFF
0000
0000
0000
0000
0000
FFFF
0000
0000
0000
0000
0000
FFFF
0600 T1CON
0610 TMR1
15:0
31:16
15:0
TCKPS<1:0>
—
—
TMR1<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0620
PR1
PR1<15:0>
31:16
15:0
—
ON
—
—
FRZ
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
—
—
TCKPS<2:0>
—
—
T32
—
—
—
—
—
TCS
—
—
—
—
0800 T2CON
0810 TMR2
—
—
31:16
15:0
TMR2<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0820
PR2
PR2<15:0>
31:16
15:0
—
ON
—
—
FRZ
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
—
—
TCKPS<2:0>
—
—
—
—
—
—
—
—
TCS
—
—
—
—
0A00 T3CON
0A10 TMR3
31:16
15:0
TMR3<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0A20
PR3
PR3<15:0>
31:16
15:0
—
ON
—
—
FRZ
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
—
—
TCKPS<2:0>
—
—
T32
—
—
—
—
—
TCS
—
—
—
—
0C00 T4CON
0C10 TMR4
31:16
15:0
TMR4<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0C20
PR4
PR4<15:0>
31:16
15:0
—
ON
—
—
FRZ
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
—
—
TCKPS<2:0>
—
—
—
—
—
—
—
—
TCS
—
—
—
—
0E00 T5CON
0E10 TMR5
31:16
15:0
TMR5<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0E20
PR5
PR5<15:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-9:
INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
2000 IC1CON(1)
15:0
31:16
15:0
ON
FRZ
SIDL
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
0000
0000
xxxx
xxxx
2010
IC1BUF
IC1BUF<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2200 IC2CON(1)
ON
FRZ
SIDL
FEDGE
C32
ICTMR
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
31:16
15:0
2210
IC2BUF
IC2BUF<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2400 IC3CON(1)
ON
FRZ
SIDL
FEDGE
C32
ICTMR
ICI<1:0>
ICI<1:0>
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
31:16
15:0
2410
IC3BUF
IC3BUF<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2600 IC4CON(1)
ON
FRZ
SIDL
FEDGE
C32
ICTMR
ICOV
ICBNE
ICM<2:0>
31:16
15:0
2610
IC4BUF
IC4BUF<31:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2800 IC5CON(1)
ON
FRZ
SIDL
FEDGE
C32
ICTMR
ICOV
ICBNE
ICM<2:0>
31:16
15:0
2810
IC5BUF
IC5BUF<31:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-10: OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
3000 OC1CON
ON
FRZ
SIDL
OC32
OCFLT
OCTSEL
OCM<2:0>
31:16
15:0
3010
OC1R
OC1R<31:0>
OC1RS<31:0>
31:16
15:0
3020 OC1RS
3200 OC2CON
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
FRZ
SIDL
OC32
OCFLT
OCTSEL
OCM<2:0>
31:16
15:0
3210
OC2R
OC2R<31:0>
OC2RS<31:0>
31:16
15:0
3220 OC2RS
3400 OC3CON
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
FRZ
SIDL
OC32
OCFLT
OCTSEL
OCM<2:0>
31:16
15:0
3410
OC3R
OC3R<31:0>
OC3RS<31:0>
31:16
15:0
3420 OC3RS
3600 OC4CON
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
FRZ
SIDL
OC32
OCFLT
OCTSEL
OCM<2:0>
31:16
15:0
3610
OC4R
OC4R<31:0>
OC4RS<31:0>
31:16
15:0
3620 OC4RS
3800 OC5CON
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
FRZ
SIDL
OC32
OCFLT
OCTSEL
OCM<2:0>
31:16
15:0
3810
OC5R
OC5R<31:0>
OC5RS<31:0>
31:16
15:0
3820 OC5RS
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
TABLE 4-11: I2C1, I2C1A, I2C2A AND I2C3A REGISTER MAP(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
FRZ
—
—
SIDL
—
—
—
STRICT
—
—
A10M
—
—
DISSLW
—
—
SMEN
—
—
GCEN
—
—
STREN
—
—
ACKDT
—
—
ACKEN
—
—
RCEN
—
—
PEN
—
—
RSEN
—
—
SEN
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
5000 I2C1ACON
5010 I2C1ASTAT
5020 I2C1AADD
5030 I2C1AMSK
5040 I2C1ABRG
5050 I2C1ATRN
5060 I2C1ARCV
5100 I2C2ACON
5110 I2C2ASTAT
5120 I2C2AADD
5130 I2C2AMSK
5140 I2C2ABRG
5150 I2C2ATRN
5160 I2C2ARCV
5200 I2C3ACON
5210 I2C3ASTAT
SCLREL
31:16
—
—
15:0 ACKSTAT TRSTAT
—
—
BCL
—
GCSTAT
—
ADD10
—
IWCOL
—
I2COV
—
D/A
P
S
R/W
—
RBF
—
TBF
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
ADD<9:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MSK<9:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
I2C1BRG<11:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2CT1DATA<7:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2CR1DATA<7:0>
31:16
15:0
—
—
—
—
—
—
—
—
GCEN
—
—
STREN
—
—
ACKDT
—
—
ACKEN
—
—
RCEN
—
—
PEN
—
—
RSEN
—
—
SEN
—
FRZ
—
SIDL
—
SCLREL
—
STRICT
—
A10M
—
DISSLW
—
SMEN
—
31:16
15:0 ACKSTAT TRSTAT
—
—
—
BCL
—
GCSTAT
—
ADD10
—
IWCOL
—
I2COV
—
D/A
P
S
R/W
—
RBF
—
TBF
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
ADD<9:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MSK<9:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
I2C1BRG<11:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2CT1DATA<7:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2CR1DATA<7:0>
31:16
15:0
—
—
—
—
—
—
—
—
GCEN
—
—
STREN
—
—
ACKDT
—
—
ACKEN
—
—
RCEN
—
—
PEN
—
—
RSEN
—
—
SEN
—
FRZ
—
SIDL
—
SCLREL
—
STRICT
—
A10M
—
DISSLW
—
SMEN
—
31:16
15:0 ACKSTAT TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-11: I2C1, I2C1A, I2C2A AND I2C3A REGISTER MAP(1) (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
5220 I2C3AADD
5230 I2C3AMSK
5240 I2C3ABRG
5250 I2C3ATRN
5260 I2C3ARCV
5300 I2C1CON
5310 I2C1STAT
5320 I2C1ADD
5330 I2C1MSK
5340 I2C1BRG
5350 I2C1TRN
5360 I2C1RCV
ADD<9:0>
31:16
15:0
—
—
—
—
—
—
MSK<9:0>
31:16
15:0
—
—
—
—
—
—
I2C1BRG<11:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2CT1DATA<7:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2CR1DATA<7:0>
31:16
15:0
—
—
—
—
—
—
—
GCEN
—
—
STREN
—
—
ACKDT
—
—
ACKEN
—
—
RCEN
—
—
PEN
—
—
RSEN
—
—
SEN
—
FRZ
—
SCLREL
—
STRICT
—
A10M
—
DISSLW
—
SMEN
—
31:16
15:0 ACKSTAT TRSTAT
—
—
BCL
—
GCSTAT
—
ADD10
—
IWCOL
—
I2COV
—
D/A
P
S
R/W
—
RBF
—
TBF
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADD<9:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MSK<9:0>
31:16
15:0
—
—
—
—
—
I2C1BRG<11:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2CT1DATA<7:0>
31:16
15:0
—
—
—
—
I2CR1DATA<7:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-12: I2C2 REGISTER MAP FOR PIC32MX575F512L, PIC32MX575F256L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
FRZ
—
—
SIDL
—
—
SCLREL
—
—
STRICT
—
—
A10M
—
—
DISSLW
—
—
SMEN
—
—
GCEN
—
—
STREN
—
—
ACKDT
—
—
ACKEN
—
—
RCEN
—
—
PEN
—
—
RSEN
—
—
SEN
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
5400 I2C2CON
5410 I2C2STAT
5420 I2C2ADD
5430 I2C2MSK
5440 I2C2BRG
5450 I2C2TRN
5460 I2C2RCV
31:16
15:0 ACKSTAT TRSTAT
—
—
—
BCL
—
GCSTAT
—
ADD10
—
IWCOL
—
I2COV
—
D/A
P
S
R/W
—
RBF
—
TBF
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADD<9:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MSK<9:0>
31:16
15:0
—
—
—
—
—
—
—
—
I2C2BRG<11:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I2CT1DATA<7:0>
31:16
15:0
—
—
—
—
—
—
—
I2CR1DATA<7:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-13: UART1A, UART1B, UART2A, UART2B, UART3A AND UART3B REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
FRZ
—
—
SIDL
—
—
IREN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
6000 U1AMODE(1)
6010 U1ASTA(1)
6020 U1ATXREG
6030 U1ARXREG
6040 U1ABRG(1)
6200 U1BMODE(1)
6210 U1BSTA(1)
6220 U1BTXREG
6230 U1BRXREG
6240 U1BBRG(1)
6400 U2AMODE(1)
6410 U2ASTA(1)
6420 U2ATXREG
6430 U2ARXREG
6440 U2ABRG(1)
6600 U2BMODE(1)
6610 U2BSTA(1)
6620 U2BTXREG
RTSMD
UEN<1:0>
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL<1:0>
STSEL 0000
0000
31:16
15:0
—
—
—
UTXBF
—
ADM_EN
TRMT
—
ADDR<7:0>
UTXISEL<1:0>
UTXINV
—
URXEN
—
UTXBRK
UTXEN
—
URXISEL<1:0>
ADDEN
—
RIDLE
—
PERR
—
FERR
—
OERR
—
URXDA 0110
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
—
—
—
—
TX8
—
Transmit Register
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RX8
—
Receive Register
31:16
15:0
—
—
—
—
—
—
BRG<15:0>
—
ON
—
—
FRZ
—
—
SIDL
—
—
IREN
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
15:0
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL<1:0>
STSEL 0000
0000
31:16
15:0
—
—
—
ADM_EN
TRMT
—
ADDR<7:0>
UTXISEL<1:0>
UTXINV
—
URXEN
—
UTXBRK
UTXEN
—
UTXBF
—
URXISEL<1:0>
ADDEN
—
RIDLE
—
PERR
—
FERR
—
OERR
—
URXDA 0110
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
—
—
—
—
TX8
—
Transmit Register
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RX8
—
Receive Register
31:16
15:0
—
—
—
—
—
—
BRG<15:0>
31:16
15:0
—
ON
—
—
FRZ
—
—
SIDL
—
—
IREN
—
—
—
—
—
—
—
—
—
—
—
RTSMD
UEN<1:0>
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL<1:0>
STSEL 0000
0000
31:16
15:0
—
—
—
UTXBF
—
ADM_EN
TRMT
—
ADDR<7:0>
UTXISEL<1:0>
UTXINV
—
URXEN
—
UTXBRK
UTXEN
—
URXISEL<1:0>
ADDEN
—
RIDLE
—
PERR
—
FERR
—
OERR
—
URXDA 0110
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
—
—
—
—
TX8
—
Transmit Register
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RX8
—
Receive Register
31:16
15:0
—
—
—
—
—
—
BRG<15:0>
31:16
15:0
—
ON
—
—
FRZ
—
—
SIDL
—
—
IREN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL<1:0>
STSEL 0000
0000
31:16
15:0
—
—
ADM_EN
TRMT
—
ADDR<7:0>
UTXISEL<1:0>
UTXINV
—
URXEN
—
UTXBRK
—
UTXEN
—
UTXBF
—
URXISEL<1:0>
ADDEN
—
RIDLE
—
PERR
—
FERR
—
OERR
—
URXDA 0110
31:16
15:0
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
TX8
Transmit Register
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-13: UART1A, UART1B, UART2A, UART2B, UART3A AND UART3B REGISTER MAP (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RX8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
6630 U2BRXREG
6640 U2BBRG(1)
6800 U3AMODE(1)
6810 U3ASTA(1)
6820 U3ATXREG
6830 U3ARXREG
6840 U3ABRG(1)
6A00 U3BMODE(1)
6A10 U3BSTA(1)
6A20 U3BTXREG
6A30 U3BRXREG
6A40 U3BBRG(1)
Receive Register
31:16
15:0
—
—
BRG<15:0>
31:16
15:0
—
ON
—
—
FRZ
—
—
SIDL
—
—
IREN
—
—
—
—
—
—
—
—
—
—
—
RTSMD
UEN<1:0>
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL<1:0>
STSEL 0000
0000
31:16
15:0
—
—
—
UTXBF
—
ADM_EN
TRMT
—
ADDR<7:0>
UTXISEL<1:0>
UTXINV
—
URXEN
—
UTXBRK
UTXEN
—
URXISEL<1:0>
ADDEN
—
RIDLE
—
PERR
—
FERR
—
OERR
—
URXDA 0110
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
—
—
—
—
TX8
—
Transmit Register
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RX8
—
Receive Register
31:16
15:0
—
—
—
—
—
—
BRG<15:0>
31:16
15:0
—
ON
—
—
FRZ
—
—
SIDL
—
—
IREN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
PDSEL<1:0>
STSEL 0000
0000
31:16
15:0
—
—
—
ADM_EN
TRMT
—
ADDR<7:0>
UTXISEL<1:0>
UTXINV
—
URXEN
—
UTXBRK
UTXEN
—
UTXBF
—
URXISEL<1:0>
ADDEN
—
RIDLE
—
PERR
—
FERR
—
OERR
—
URXDA 0110
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
—
—
—
—
TX8
—
Transmit Register
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RX8
—
Receive Register
31:16
15:0
—
—
—
—
—
—
BRG<15:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-14: SPI1A, SPI2A AND SPI3A REGISTER MAP(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 FRMEN FRMSYNC FRMPOL
MSSEN FRMSYPW
FRMCNT<2:0>
SMP
—
—
CKP
—
—
—
—
—
SPIFE
ENHBUF 0000
5800 SPI1ACON
15:0
31:16
15:0
ON
—
FRZ
—
SIDL
—
DISSDO MODE32 MODE16
CKE
SSEN
—
MSTEN
—
STXISEL<1:0>
TXBUFELM<4:0>
SRXISEL<1:0>
0000
0000
RXBUFELM<4:0>
—
SPI1ASTAT
SPI1ABUF
SPI1ABRG
SPI2ACON
SPI2ASTAT
SPI2ABUF
SPI2ABRG
SPI3ACON
SPI3ASTAT
SPI3ABUF
SPI3ABRG
5810
5820
5830
5A00
5A10
5A20
5A30
5C00
5C10
5C20
5C30
—
—
—
—
SPIBUSY
—
—
SPITUR
—
SRMT
SPIROV
SPIRBE
—
SPITBE
—
SPITBF
SPIRBF 0000
0000
31:16
15:0
DATA<31:0>
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRG<8:0>
—
—
—
—
—
—
—
0000
0000
31:16 FRMEN FRMSYNC FRMPOL
MSSEN FRMSYPW
FRMCNT<2:0>
SMP
—
—
CKP
—
SPIFE
ENHBUF 0000
15:0
31:16
15:0
ON
—
FRZ
—
SIDL
—
DISSDO MODE32 MODE16
CKE
SSEN
—
MSTEN
—
—
STXISEL<1:0>
TXBUFELM<4:0>
SRXISEL<1:0>
0000
0000
RXBUFELM<4:0>
—
—
—
—
—
SPIBUSY
—
—
SPITUR
SRMT
SPIROV
SPIRBE
—
SPITBE
—
SPITBF
SPIRBF 0000
0000
31:16
15:0
DATA<31:0>
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRG<8:0>
—
—
—
—
—
—
—
0000
0000
31:16 FRMEN FRMSYNC FRMPOL
MSSEN FRMSYPW
FRMCNT<2:0>
SMP
—
—
CKP
—
SPIFE
ENHBUF 0000
15:0
31:16
15:0
ON
—
FRZ
—
SIDL
—
DISSDO MODE32 MODE16
CKE
SSEN
—
MSTEN
—
—
STXISEL<1:0>
TXBUFELM<4:0>
SRXISEL<1:0>
0000
0000
RXBUFELM<4:0>
—
—
—
—
—
SPIBUSY
—
—
SPITUR
SRMT
SPIROV
SPIRBE
—
SPITBE
—
—
SPITBF
—
SPIRBF 0000
0000
31:16
15:0
DATA<31:0>
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
BRG<8:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-15: SPI1 REGISTER MAP FOR PIC32MX575F512L, PIC32MX575F256L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits
Register
Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 FRMEN FRMSYNC FRMPOL
MSSEN FRMSYPW
FRMCNT<2:0>
SMP
—
—
CKP
—
—
—
—
—
SPIFE
ENHBUF 0000
5E00 SPI1CON
5E10 SPI1STAT
5E20 SPI1BUF
5E30 SPI1BRG
15:0
31:16
15:0
ON
—
FRZ
—
SIDL
—
DISSDO MODE32 MODE16
CKE
SSEN
—
MSTEN
—
STXISEL<1:0>
TXBUFELM<4:0>
SRXISEL<1:0>
0000
0000
RXBUFELM<4:0>
—
—
—
—
—
SPIBUSY
—
—
SPITUR
SRMT
SPIROV
SPIRBE
—
SPITBE
—
—
SPITBF
—
SPIRBF 0000
0000
31:16
15:0
DATA<31:0>
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
BRG<8:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-16: ADC REGISTER MAP
Bits
Register
Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
FRZ
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLRASAM
—
—
—
—
—
ASAM
—
—
SAMP
—
—
DONE
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
9000 AD1CON1(1)
9010 AD1CON2(1)
9020 AD1CON3(1)
9040 AD1CHS(1)
9060 AD1PCFG(1)
9050 AD1CSSL(1)
9070 ADC1BUF0
9080 ADC1BUF1
9090 ADC1BUF2
90A0 ADC1BUF3
90B0 ADC1BUF4
90C0 ADC1BUF5
90D0 ADC1BUF6
90E0 ADC1BUF7
90F0 ADC1BUF8
9100 ADC1BUF9
9110 ADC1BUFA
9120 ADC1BUFB
FORM<2:0>
SSRC<2:0>
31:16
15:0
—
—
—
CSCNA
—
—
—
—
—
—
—
—
BUFS
—
—
—
—
VCFG2
—
VCFG1
—
VCFG0
—
OFFCAL
—
SMPI<3:0>
BUFM
—
ALTS
—
31:16
15:0
—
—
—
ADRC
—
—
SAMC<4:0>
ADCS<7:0>
31:16 CH0NB
—
—
—
—
—
CH0SB<3:0>
CH0NA
—
—
—
—
—
—
—
CH0SA<3:0>
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0 PCFG15 PCFG14 PCFG13 PCFG12
PCFG11
—
PCFG10
—
PCFG9
—
PCFG8
—
PCFG7
—
PCFG6
—
PCFG5
—
PCFG4
—
PCFG3
—
PCFG2
—
PCFG1
—
PCFG0 0000
0000
31:16
—
—
—
—
—
15:0 CSSL15
31:16
15:0
CSSL14
CSSL13
CSSL12
CSSL11
CSSL10
CSSL9
CSSL8
CSSL7
CSSL6
CSSL5
CSSL4
CSSL3
CSSL2
CSSL1
CSSL0 0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
ADC Result Word 0 (ADC1BUF0<31:0>)
ADC Result Word 1 (ADC1BUF1<31:0>)
ADC Result Word 2 (ADC1BUF2<31:0>)
ADC Result Word 3 (ADC1BUF3<31:0>)
ADC Result Word 4 (ADC1BUF4<31:0>)
ADC Result Word 5 (ADC1BUF5<31:0>)
ADC Result Word 6 (ADC1BUF6<31:0>)
ADC Result Word 7 (ADC1BUF7<31:0>)
ADC Result Word 8 (ADC1BUF8<31:0>)
ADC Result Word 9 (ADC1BUF9<31:0>)
ADC Result Word A (ADC1BUFA<31:0>)
ADC Result Word B (ADC1BUFB<31:0>)
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-16: ADC REGISTER MAP (CONTINUED)
Bits
Register
Name
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
0000
0000
0000
0000
0000
0000
0000
0000
9130 ADC1BUFC
9140 ADC1BUFD
9150 ADC1BUFE
9160 ADC1BUFF
ADC Result Word C (ADC1BUFC<31:0>)
ADC Result Word D (ADC1BUFD<31:0>)
ADC Result Word E (ADC1BUFE<31:0>)
ADC Result Word F (ADC1BUFF<31:0>)
31:16
15:0
31:16
15:0
31:16
15:0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-17: DMA GLOBAL REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
FRZ
—
—
—
—
—
—
—
BUSY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
3000 DMACON(1)
3010 DMASTAT
3020 DMAADDR
SUSPEND
—
—
31:16
15:0
—
—
—
—
—
—
RDWR
DMACH<2:0>
31:16
15:0
DMAADDR<31:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
TABLE 4-18: DMA CRC REGISTER MAP(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
BYTO<1:0>
WBO
—
—
BITO
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
3030 DCRCCON
3040 DCRCDATA
3050 DCRCXOR
—
PLEN<4:0>
CRCEN CRCAPP CRCTYP
CRCCH<2:0>
31:16
15:0
DCRCDATA<31:0>
DCRCXOR<31:0>
31:16
15:0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
00FF
FF00
3060 DCH0CON
3070 DCH0ECON
3080 DCH0INT
3090 DCH0SSA
30A0 DCH0DSA
30B0 DCH0SSIZ
30C0 DCH0DSIZ
30D0 DCH0SPTR
30E0 DCH0DPTR
30F0 DCH0CSIZ
3100 DCH0CPTR
3110 DCH0DAT
3120 DCH1CON
3130 DCH1ECON
3140 DCH1INT
3150 DCH1SSA
3160 DCH1DSA
3170 DCH1SSIZ
15:0 CHBUSY
CHCHNS
—
CHEN
CHAED
CHCHN
CHAEN
CHEDET
CHPRI<1:0>
31:16
15:0
—
CHAIRQ<7:0>
CHSIRQ<7:0>
CFORCE CABORT
PATEN
CHDDIE
CHDDIF
SIRQEN
AIRQEN
CHBCIE
CHBCIF
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE
CHSDIF
CHSHIE
CHSHIF
CHDHIE
CHDHIF
CHCCIE
CHCCIF
CHTAIE
CHTAIF
CHERIE 0000
CHERIF 0000
0000
31:16
15:0
CHSSA<31:0>
CHDSA<31:0>
0000
31:16
15:0
0000
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00FF
FF00
CHSSIZ<15:0>
31:16
15:0
—
—
CHDSIZ<15:0>
31:16
15:0
—
—
CHSPTR<15:0>
31:16
15:0
—
—
CHDPTR<15:0>
31:16
15:0
—
—
CHCSIZ<15:0>
31:16
15:0
—
—
CHCPTR<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPDAT<7:0>
31:16
—
—
—
—
—
—
—
15:0 CHBUSY
CHCHNS
—
CHEN
CHAED
CHCHN
CHAEN
CHEDET
CHPRI<1:0>
31:16
15:0
—
CHAIRQ<7:0>
CHSIRQ<7:0>
CFORCE CABORT
PATEN
CHDDIE
CHDDIF
SIRQEN
AIRQEN
CHBCIE
CHBCIF
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE
CHSDIF
CHSHIE
CHSHIF
CHDHIE
CHDHIF
CHCCIE
CHCCIF
CHTAIE
CHTAIF
CHERIE 0000
CHERIF 0000
0000
31:16
15:0
CHSSA<31:0>
CHDSA<31:0>
0000
31:16
15:0
0000
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
CHSSIZ<15:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00FF
FF00
3180 DCH1DSIZ
3190 DCH1SPTR
31A0 DCH1DPTR
31B0 DCH1CSIZ
31C0 DCH1CPTR
31D0 DCH1DAT
31E0 DCH2CON
31F0 DCH2ECON
3200 DCH2INT
3210 DCH2SSA
3220 DCH2DSA
3230 DCH2SSIZ
3240 DCH2DSIZ
3250 DCH2SPTR
3260 DCH2DPTR
3270 DCH2CSIZ
CHDSIZ<15:0>
31:16
15:0
—
—
CHSPTR<15:0>
31:16
15:0
—
—
CHDPTR<15:0>
31:16
15:0
—
—
CHCSIZ<15:0>
31:16
15:0
—
—
CHCPTR<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPDAT<7:0>
31:16
—
—
—
—
—
—
—
15:0 CHBUSY
CHCHNS
—
CHEN
CHAED
CHCHN
CHAEN
CHEDET
CHPRI<1:0>
31:16
15:0
—
CHAIRQ<7:0>
CHSIRQ<7:0>
CFORCE CABORT
PATEN
CHDDIE
CHDDIF
SIRQEN
AIRQEN
CHBCIE
CHBCIF
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE
CHSDIF
CHSHIE
CHSHIF
CHDHIE
CHDHIF
CHCCIE
CHCCIF
CHTAIE
CHTAIF
CHERIE 0000
CHERIF 0000
0000
31:16
15:0
CHSSA<31:0>
CHDSA<31:0>
0000
31:16
15:0
0000
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
CHSSIZ<15:0>
31:16
15:0
—
—
CHDSIZ<15:0>
31:16
15:0
—
—
CHSPTR<15:0>
31:16
15:0
—
—
CHDPTR<15:0>
31:16
15:0
—
—
CHCSIZ<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
3280 DCH2CPTR
3290 DCH2DAT
CHCPTR<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPDAT<7:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
00FF
FF00
32A0 DCH3CON
32B0 DCH3ECON
32C0 DCH3INT
32D0 DCH3SSA
32E0 DCH3DSA
32F0 DCH3SSIZ
3300 DCH3DSIZ
3310 DCH3SPTR
3320 DCH3DPTR
3330 DCH3CSIZ
3340 DCH3CPTR
3350 DCH3DAT
3360 DCH4CON
3370 DCH4ECON
3380 DCH4INT
3390 DCH4SSA
33A0 DCH4DSA
33B0 DCH4SSIZ
15:0 CHBUSY
CHCHNS
—
CHEN
CHAED
CHCHN
CHAEN
CHEDET
CHPRI<1:0>
31:16
15:0
—
CHAIRQ<7:0>
CHSIRQ<7:0>
CFORCE CABORT
PATEN
CHDDIE
CHDDIF
SIRQEN
AIRQEN
CHBCIE
CHBCIF
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE
CHSDIF
CHSHIE
CHSHIF
CHDHIE
CHDHIF
CHCCIE
CHCCIF
CHTAIE
CHTAIF
CHERIE 0000
CHERIF 0000
0000
31:16
15:0
CHSSA<31:0>
CHDSA<31:0>
0000
31:16
15:0
0000
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00FF
FF00
CHSSIZ<15:0>
31:16
15:0
—
—
CHDSIZ<15:0>
31:16
15:0
—
—
CHSPTR<15:0>
31:16
15:0
—
—
CHDPTR<15:0>
31:16
15:0
—
—
CHCSIZ<15:0>
31:16
15:0
—
—
CHCPTR<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPDAT<7:0>
31:16
—
—
—
—
—
—
—
15:0 CHBUSY
CHCHNS
—
CHEN
CHAED
CHCHN
CHAEN
CHEDET
CHPRI<1:0>
31:16
15:0
—
CHAIRQ<7:0>
CHSIRQ<7:0>
CFORCE CABORT
PATEN
CHDDIE
CHDDIF
SIRQEN
AIRQEN
CHBCIE
CHBCIF
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE
CHSDIF
CHSHIE
CHSHIF
CHDHIE
CHDHIF
CHCCIE
CHCCIF
CHTAIE
CHTAIF
CHERIE 0000
CHERIF 0000
0000
31:16
15:0
CHSSA<31:0>
CHDSA<31:0>
0000
31:16
15:0
0000
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
CHSSIZ15:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00FF
FF00
33C0 DCH4DSIZ
CHDSIZ<15:0>
31:16
15:0
—
—
DCH4SPTR
DCH4DPTR
DCH4CSIZ
DCH4CPTR
DCH4DAT
DCH5CON
DCH5ECON
DCH5INT
33D0
33E0
33F0
3400
3410
3420
3430
3440
3450
3460
3470
3480
3490
34A0
34B0
CHSPTR<15:0>
31:16
15:0
—
—
CHDPTR<15:0>
31:16
15:0
—
—
CHCSIZ<15:0>
31:16
15:0
—
—
CHCPTR<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPDAT<7:0>
31:16
—
—
—
—
—
—
—
15:0 CHBUSY
CHCHNS
—
CHEN
CHAED
CHCHN
CHAEN
CHEDET
CHPRI<1:0>
31:16
15:0
—
CHAIRQ<7:0>
CHSIRQ<7:0>
CFORCE CABORT
PATEN
CHDDIE
CHDDIF
SIRQEN
AIRQEN
CHBCIE
CHBCIF
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE
CHSDIF
CHSHIE
CHSHIF
CHDHIE
CHDHIF
CHCCIE
CHCCIF
CHTAIE
CHTAIF
CHERIE 0000
CHERIF 0000
0000
31:16
15:0
DCH5SSA
DCH5DSA
DCH5SSIZ
DCH5DSIZ
DCH5SPTR
DCH5DPTR
DCH5CSIZ
CHSSA<31:0>
CHDSA<31:0>
0000
31:16
15:0
0000
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
CHSSIZ<15:0>
31:16
15:0
—
—
CHDSIZ<15:0>
31:16
15:0
—
—
CHSPTR<15:0>
31:16
15:0
—
—
CHDPTR<15:0>
31:16
15:0
—
—
CHCSIZ<15:0>
31:16
15:0
—
—
34C0 DCH5CPTR
34D0 DCH5DAT
CHCPTR<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPDAT<7:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
00FF
FF00
34E0 DCH6CON
34F0 DCH6ECON
3500 DCH6INT
3510 DCH6SSA
3520 DCH6DSA
3530 DCH6SSIZ
3540 DCH6DSIZ
3550 DCH6SPTR
3560 DCH6DPTR
3570 DCH6CSIZ
3580 DCH6CPTR
3590 DCH6DAT
35A0 DCH7CON
35B0 DCH7ECON
35C0 DCH7INT
35D0 DCH7SSA
35E0 DCH7DSA
35F0 DCH7SSIZ
15:0 CHBUSY
CHCHNS
—
CHEN
CHAED
CHCHN
CHAEN
CHEDET
CHPRI<1:0>
31:16
15:0
—
CHAIRQ<7:0>
CHSIRQ<7:0>
CFORCE CABORT
PATEN
CHDDIE
CHDDIF
SIRQEN
AIRQEN
CHBCIE
CHBCIF
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE
CHSDIF
CHSHIE
CHSHIF
CHDHIE
CHDHIF
CHCCIE
CHCCIF
CHTAIE
CHTAIF
CHERIE 0000
CHERIF 0000
0000
31:16
15:0
CHSSA<31:0>
CHDSA<31:0>
0000
31:16
15:0
0000
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00FF
FF00
CHSSIZ<15:0>
31:16
15:0
—
—
CHDSIZ<15:0>
31:16
15:0
—
—
CHSPTR<15:0>
31:16
15:0
—
—
CHDPTR<15:0>
31:16
15:0
—
—
CHCSIZ<15:0>
31:16
15:0
—
—
CHCPTR<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPDAT<7:0>
31:16
—
—
—
—
—
—
—
15:0 CHBUSY
CHCHNS
—
CHEN
CHAED
CHCHN
CHAEN
CHEDET
CHPRI<1:0>
31:16
15:0
—
CHAIRQ<7:0>
CHSIRQ<7:0>
CFORCE CABORT
PATEN
CHDDIE
CHDDIF
SIRQEN
AIRQEN
CHBCIE
CHBCIF
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSDIE
CHSDIF
CHSHIE
CHSHIF
CHDHIE
CHDHIF
CHCCIE
CHCCIF
CHTAIE
CHTAIF
CHERIE 0000
CHERIF 0000
0000
31:16
15:0
CHSSA<31:0>
CHDSA<31:0>
0000
31:16
15:0
0000
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
CHSSIZ<15:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-19: DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
3600 DCH7DSIZ
3610 DCH7SPTR
3620 DCH7DPTR
3630 DCH7CSIZ
3640 DCH7CPTR
3650 DCH7DAT
CHDSIZ<15:0>
31:16
15:0
—
—
CHSPTR<15:0>
31:16
15:0
—
—
CHDPTR<15:0>
31:16
15:0
—
—
CHCSIZ<15:0>
31:16
15:0
—
—
CHCPTR<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPDAT<7:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-20: COMPARATOR REGISTER MAP(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
COE
—
—
CPOL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
COUT
—
—
—
—
—
—
—
—
—
—
—
CREF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
A000 CM1CON
A010 CM2CON
A060 CMSTAT
EVPOL<1:0>
CCH<1:0>
31:16
15:0
—
—
ON
—
COE
—
CPOL
—
COUT
—
EVPOL<1:0>
CREF
—
CCH<1:0>
31:16
15:0
—
—
—
—
—
—
FRZ
SIDL
—
—
—
C2OUT
C1OUT 0000
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-21: COMPARATOR VOLTAGE REFERENCE REGISTER MAP(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
9800 CVRCON
ON
CVROE
CVRR
CVRSS
CVR<3:0>
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-22: FLASH CONTROLLER REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
F400 NVMCON(1)
F410 NVMKEY
WR
WREN
WRERR
LVDERR LVDSTAT
NVMOP<3:0>
31:16
15:0
NVMKEY<31:0>
NVMADDR<31:0>
NVMDATA<31:0>
31:16
15:0
(1)
F420 NVMADDR
31:16
15:0
F430 NVMDATA
31:16
15:0
NVMSRC
F440
NVMSRCADDR<31:0>
ADDR
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-23: SYSTEM CONTROL REGISTER MAP(1,2)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
ON
—
—
—
—
—
PLLODIV<2:0>
RCDIV<2:0>
—
SOSCRDY
—
LOCK
—
PBDIV<1:0>
PLLMULT<2:0>
0000
F000 OSCCON
F010 OSCTUN
0000 WDTCON
COSC<2:0>
—
—
—
—
—
—
—
—
—
NOSC<2:0>
CLKLOCK ULOCK
SLPEN
—
CF
—
UFRCEN SOSCEN OSWEN 0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
TUN<5:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
SWDTPS<4:0>
WDTCLR 0000
31:16
15:0
—
—
—
—
SWR
—
—
—
—
—
—
WDTO
—
—
SLEEP
—
—
IDLE
—
—
—
POR
—
0000
0000
0000
F600
RCON
CM
—
VREGS
—
EXTR
—
BOR
—
31:16
15:0
F610 RSWRST
—
—
—
—
—
—
—
—
SWRST 0000
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2:
Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
TABLE 4-24: PORTA REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISA10
—
—
TRISA9
—
—
—
—
—
—
—
—
—
—
TRISA7
—
—
TRISA6
—
—
TRISA5
—
—
TRISA4
—
—
TRISA3
—
—
TRISA2
—
—
TRISA1
—
—
TRISA0
—
0000
C6FF
0000
xxxx
0000
xxxx
0000
0000
6000 TRISA
6010 PORTA
15:0 TRISA15 TRISA14
31:16
15:0
—
RA15
—
—
RA14
—
RA10
—
RA9
—
RA7
—
RA6
—
RA5
—
RA4
—
RA3
—
RA2
—
RA1
—
RA0
—
31:16
15:0
6020
LATA
LATA15
—
LATA14
—
LATA10
—
LATA9
—
LATA7
—
LATA6
—
LATA5
—
LATA4
—
LATA3
—
LATA2
—
LATA1
—
LATA0
—
31:16
6030 ODCA
15:0 ODCA15 ODCA14
ODCA10
ODCA9
ODCA7
ODCA6
ODCA5
ODCA4
ODCA3
ODCA2
ODCA1
ODCA0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-25: PORTB REGISTER MAP(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
TRISB9
—
—
TRISB8
—
—
TRISB7
—
—
TRISB6
—
—
TRISB5
—
—
TRISB4
—
—
TRISB3
—
—
TRISB2
—
—
TRISB1
—
—
TRISB0
—
0000
FFFF
0000
xxxx
0000
xxxx
0000
0000
6040 TRISB
6050 PORTB
15:0 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10
31:16
15:0
—
RB15
—
—
RB14
—
—
RB13
—
—
RB12
—
—
RB11
—
—
RB10
—
RB9
RB8
RB7
RB6
—
RB5
RB4
RB3
RB2
RB1
RB0
31:16
15:0
—
—
—
—
—
—
—
—
—
6060
LATB
LATB15
—
LATB14
—
LATB13
—
LATB12
—
LATB11
—
LATB10
—
LATB9
—
LATB8
—
LATB7
—
LATB6
—
LATB5
—
LATB4
—
LATB3
—
LATB2
—
LATB1
—
LATB0
—
31:16
6070 ODCB
15:0 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10
ODCB9
ODCB8
ODCB7
ODCB6
ODCB5
ODCB4
ODCB3
ODCB2
ODCB1
ODCB0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-26: PORTC REGISTER MAP FOR PIC32MX575F256H, PIC32MX675F256H, PIC32MX575F512H, PIC32MX675F512H,
PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
F000
0000
xxxx
0000
xxxx
0000
0000
6080 TRISC
6090 PORTC
15:0 TRISC15 TRISC14 TRISC13 TRISC12
31:16
15:0
—
RC15
—
—
RC14
—
—
RC13
—
—
RC12
—
31:16
15:0
60A0
LATC
LATC15
—
LATC14
—
LATC13
—
LATC12
—
31:16
60B0 ODCC
15:0 ODCC15 ODCC14 ODCC13 ODCC12
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-27: PORTC REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISC4
—
—
TRISC3
—
—
TRISC2
—
—
TRISC1
—
—
—
—
—
—
—
—
—
0000
F00F
0000
xxxx
0000
xxxx
0000
0000
6080 TRISC
6090 PORTC
60A0 LATC
60B0 ODCC
15:0 TRISC15 TRISC14 TRISC13 TRISC12
31:16
15:0
—
RC15
—
—
RC14
—
—
RC13
—
—
RC12
—
RC4
—
RC3
—
RC2
—
RC1
—
31:16
15:0
LATC15
—
LATC14
—
LATC13
—
LATC12
—
LATC4
—
LATC3
—
LATC2
—
LATC1
—
31:16
15:0 ODCC15 ODCC14 ODCC13 ODCC12
ODCC4
ODCC3
ODCC2
ODCC1
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-28: PORTD REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H,
PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISD9
—
—
TRISD8
—
—
TRISD7
—
—
TRISD6
—
—
TRISD5
—
—
TRISD4
—
—
TRISD3
—
—
TRISD2
—
—
TRISD1
—
—
TRISD0
—
0000
0FFF
0000
xxxx
0000
xxxx
0000
0000
60C0 TRISD
60D0 PORTD
TRISD11 TRISD10
31:16
15:0
—
RD11
—
—
RD10
—
RD9
—
RD8
—
RD7
—
RD6
—
RD5
—
RD4
—
RD3
—
RD2
—
RD1
—
RD0
—
31:16
15:0
60E0
LATD
LATD11
—
LATD10
—
LATD9
—
LATD8
—
LATD7
—
LATD6
—
LATD5
—
LATD4
—
LATD3
—
LATD2
—
LATD1
—
LATD0
—
31:16
15:0
60F0 ODCD
ODCD11 ODCD10
ODCD9
ODCD8
ODCD7
ODCD6
ODCD5
ODCD4
ODCD3
ODCD2
ODCD1
ODCD0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-29: PORTD REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
TRISD9
—
—
TRISD8
—
—
TRISD7
—
—
TRISD6
—
—
TRISD5
—
—
TRISD4
—
—
TRISD3
—
—
TRISD2
—
—
TRISD1
—
—
TRISD0
—
0000
FFFF
0000
xxxx
0000
xxxx
0000
0000
60C0 TRISD
60D0 PORTD
60E0 LATD
60F0 ODCD
15:0 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10
31:16
15:0
—
RD15
—
—
RD14
—
—
RD13
—
—
RD12
—
—
RD11
—
—
RD10
—
RD9
—
RD8
—
RD7
—
RD6
—
RD5
—
RD4
—
RD3
—
RD2
—
RD1
—
RD0
—
31:16
15:0
LAT15
—
LAT14
—
LAT13
—
LAT12
—
LATD11
—
LATD10
—
LATD9
—
LATD8
—
LATD7
—
LATD6
—
LATD5
—
LATD4
—
LATD3
—
LATD2
—
LATD1
—
LATD0
—
31:16
15:0 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10
ODCD9
ODCD8
ODCD7
ODCD6
ODCD5
ODCD4
ODCD3
ODCD2
ODCD1
ODCD0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-30: PORTE REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H,
PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISE7
—
—
TRISE6
—
—
TRISE5
—
—
TRISE4
—
—
TRISE3
—
—
TRISE2
—
—
TRISE1
—
—
TRISE0
—
0000
00FF
0000
xxxx
0000
xxxx
0000
0000
6100 TRISE
6110 PORTE
31:16
15:0
RE7
—
RE6
—
RE5
RE4
RE3
RE2
RE1
RE0
31:16
15:0
—
—
—
—
—
—
6120
LATE
LATE7
—
LATE6
—
LATE5
—
LATE4
—
LATE3
—
LATE2
—
LATE1
—
LATE0
—
31:16
15:0
6130 ODCE
ODCE7
0DCE6
ODCE5
ODCE4
ODCE3
ODCE2
ODCE1
ODCE0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-31: PORTE REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISE9
—
—
TRISE8
—
—
TRISE7
—
—
TRISE6
—
—
TRISE5
—
—
TRISE4
—
—
TRISE3
—
—
TRISE2
—
—
TRISE1
—
—
TRISE0
—
0000
03FF
0000
xxxx
0000
xxxx
0000
0000
6100 TRISE
6110 PORTE
31:16
15:0
RE9
RE8
RE7
RE6
—
RE5
RE4
RE3
RE2
RE1
RE0
31:16
15:0
—
—
—
—
—
—
—
—
—
6120
LATE
LATE9
—
LATE8
—
LATE7
—
LATE6
—
LATE5
—
LATE4
—
LATE3
—
LATE2
—
LATE1
—
LATE0
—
31:16
15:0
6130 ODCE
ODCE9
ODCE8
ODCE7
0DCE6
ODCE5
ODCE4
ODCE3
ODCE2
ODCE1
ODCE0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-32: PORTF REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H,
PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF5
—
—
TRISF4
—
—
TRISF3
—
—
—
—
—
—
—
—
—
—
TRISF1
—
—
TRISF0
—
0000
003B
0000
xxxx
0000
xxxx
0000
0000
6140 TRISF
6150 PORTF
6160 LATF
6170 ODCF
31:16
15:0
RF5
RF4
RF3
RF1
RF0
31:16
15:0
—
—
—
—
—
LATF5
—
LATF4
—
LATF3
—
LATF1
—
LATF0
—
31:16
15:0
ODCF5
ODCF4
ODCF3
ODCF1
ODCF0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-33: PORTF REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISF5
—
—
TRISF4
—
—
TRISF3
—
—
TRISF2
—
—
TRISF1
—
—
TRISF0
—
0000
313F
0000
xxxx
0000
xxxx
0000
0000
6140 TRISF
6150 PORTF
TRISF13 TRISF12
31:16
15:0
—
RF13
—
—
RF12
—
RF8
RF5
RF4
RF3
RF2
RF1
RF0
31:16
15:0
—
—
—
—
—
—
—
6160
LATF
LATF13
—
LATF12
—
LATF8
—
LATF5
—
LATF4
—
LATF3
—
LATF2
—
LATF1
—
LATF0
—
31:16
15:0
6170 ODCF
ODCF13 ODCF12
ODCF8
ODCF5
ODCF4
ODCF3
ODCF2
ODCF1
ODCF0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-34: PORTG REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H,
PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISG9
—
—
TRISG8
—
—
TRISG7
—
—
TRISG6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISG3
—
—
TRISG2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
03CC
0000
xxxx
0000
xxxx
0000
0000
TRISG
6180
31:16
15:0
6190 PORTG
61A0 LATG
61B0 ODCG
RG9
—
RG8
—
RG7
—
RG6
—
RG3
—
RG2
—
31:16
15:0
LATG9
—
LATG8
—
LATG7
—
LATG6
—
LATG3
—
LATG2
—
31:16
15:0
ODCG9
ODCG8
ODCG7
ODCG6
ODCG3
ODCG2
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-35: PORTG REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISG9
—
—
TRISG8
—
—
TRISG7
—
—
TRISG6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISG3
—
—
TRISG2
—
—
TRISG1
—
—
TRISG0
—
0000
F3CF
0000
xxxx
0000
xxxx
0000
0000
6180 TRISG
6190 PORTG
61A0 LATG
61B0 ODCG
15:0 TRISG15 TRISG14 TRISG13 TRISG12
31:16
15:0
—
RG15
—
—
RG14
—
—
RG13
—
—
RG12
—
RG9
—
RG8
—
RG7
—
RG6
—
RG3
—
RG2
—
RG1
—
RG0
—
31:16
15:0
LATG15
—
LATG14
—
LATG13
—
LATG12
—
LATG9
—
LATG8
—
LATG7
—
LATG6
—
LATG3
—
LATG2
—
LATG1
—
LATG0
—
31:16
15:0 ODCG15 ODCG14 ODCG13 ODCG12
ODCG9
ODCG8
ODCG7
ODCG6
ODCG3
ODCG2
ODCG1
ODCG0
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-36: CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L,
PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512 AND PIC32MX795F512L DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
FRZ
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
61C0 CNCON
61D0 CNEN
61E0 CNPUE
31:16
—
—
—
—
CNEN21 CNEN20 CNEN19 CNEN18 CNEN17 CNEN16 0000
CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0 0000
CNPUE21 CNPUE20 CNPUE19 CNPUE18 CNPUE17 CNPUE16 0000
15:0 CNEN15 CNEN14 CNEN13 CNEN12
31:16
CNEN11 CNEN10
CNEN9
—
CNEN8
—
CNEN7
—
CNEN6
—
—
—
—
—
—
—
15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0 0000
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-37: CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H,
PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
FRZ
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
61C0 CNCON
61D0 CNEN
61E0 CNPUE
31:16
—
—
—
—
—
—
—
CNEN18 CNEN17 CNEN16 0000
CNEN2 CNEN1 CNEN0 0000
CNPUE18 CNPUE17 CNPUE16 0000
15:0 CNEN15 CNEN14 CNEN13 CNEN12
31:16
CNEN11 CNEN10
CNEN9
—
CNEN8
—
CNEN7
—
CNEN6
—
CNEN5
—
CNEN4
—
CNEN3
—
—
—
—
—
—
—
15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0 0000
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-38: PARALLEL MASTER PORT REGISTER MAP(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
FRZ
—
—
SIDL
—
—
—
—
—
—
—
—
—
—
ALP
—
—
CS2P
—
—
CS1P
—
—
—
—
—
WRSP
—
—
RDSP
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0080
7000 PMCON
7010 PMMODE
7020 PMADDR
7030 PMDOUT
ADRMUX<1:0>
PMPTTL PTWREN PTRDEN
CSF<1:0>
31:16
15:0
—
—
—
—
MODE16
—
—
—
—
—
—
BUSY
—
IRQM<1:0>
INCM<1:0>
MODE<1:0>
WAITB<1:0>
WAITM<3:0>
WAITE<1:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0 CS2EN/A15 CS1EN/A14
ADDR<13:0>
31:16
15:0
DATAOUT<31:0>
DATAIN<31:0>
31:16
15:0
7040
PMDIN
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7050 PMAEN
7060 PMSTAT
PTEN<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IBF
IBOV
IB3F
IB2F
IB1F
IB0F
OBE
OBUF
OB3E
OB2E
OB1E
OB0E
Legend:
Note 1:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
TABLE 4-39: PROGRAMMING AND DIAGNOSTICS REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0008
F200 DDPCON
Legend:
JTAGEN
TROEN
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-40: PREFETCH REGISTER MAP
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PFMWS<2:0>
—
CHECOH 0000
4000 CHECON(1,2)
4010 CHEACC(1)
4020 CHETAG(1)
4030 CHEMSK(1)
DCSZ<1:0>
PREFEN<1:0>
0000
31:16 CHEWEN
15:0
—
—
—
—
—
—
—
—
—
—
—
0000
0000
00xx
xxx0
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
—
CHEIDX<3:0>
31:16 LTAGBOOT
15:0
LTAG<23:16>
LVALID
LTAG<15:4>
LLOCK
—
LTYPE
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LMASK<15:5>
—
—
—
31:16
15:0
4040
4050
4060
4070
CHEW0
CHEW1
CHEW2
CHEW3
CHEW0<31:0>
CHEW1<31:0>
CHEW2<31:0>
CHEW3<31:0>
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
—
—
—
—
—
—
—
CHELRU<24:16>
4080 CHELRU
CHELRU<15:0>
CHEHIT<31:0>
31:16
15:0
4090
40A0
CHEHIT
CHEMIS
31:16
15:0
CHEMIS<31:0>
31:16
15:0
40C0 CHEPFABT
CHEPFABT<31:0>
Legend:
Note
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
2:
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
Reset value is dependent on DEVCFGx configuration.
TABLE 4-41: RTCC REGISTER MAP(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
FRZ
—
—
SIDL
—
—
—
—
—
—
—
—
CAL<9:0>
0000
RTCWREN RTCSYNC HALFSEC RTCOE 0000
0200 RTCCON
0210 RTCALRM
0220 RTCTIME
0230 RTCDATE
0240 ALRMTIME
0250 ALRMDATE
—
—
—
—
—
—
RTSECSEL RTCCLKON
—
—
—
—
31:16
—
—
—
—
—
—
0000
0000
xxxx
xx00
xxxx
xx00
xxxx
xx00
00xx
xx0x
15:0 ALRMEN
31:16
CHIME
PIV
ALRMSYNC
AMASK<3:0>
ARPT<7:0>
HR10<3:0>
HR01<3:0>
SEC01<3:0>
YEAR01<3:0>
DAY01<3:0>
HR01<3:0>
MIN10<3:0>
MIN01<3:0>
15:0
SEC10<3:0>
YEAR10<3:0>
DAY10<3:0>
HR10<3:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
MONTH10<3:0>
MONTH01<3:0>
WDAY01<3:0>
MIN01<3:0>
15:0
—
—
31:16
MIN10<3:0>
15:0
SEC10<3:0>
SEC01<3:0>
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
MONTH10<3:0>
MONTH01<3:0>
WDAY01<3:0>
DAY10<3:0>
DAY01<3:0>
—
—
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-42: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 FVBUSIO FUSBIDIO FSCMIO
15:0
—
—
FCANIO
—
FETHIO
—
FMIIEN
—
—
—
—
—
—
—
FSRSSEL<2:0>
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
2FF0 DEVCFG3
2FF4 DEVCFG2
2FF8 DEVCFG1
2FFC DEVCFG0
USERID<15:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FPLLODIV<2:0>
FPLLIDIV<2:0>
15:0 FUPLLEN
FUPLLIDIV<2:0>
—
FPLLMULT<2:0>
31:16
15:0
—
—
FWDTEN
IESO
—
—
—
—
—
—
WDTPS<4:0>
FNOSC<2:0>
PWP<7:4>
FCKSM<1:0>
FPBDIV<1:0>
CP
OSCIOFNC
POSCMOD<1:0>
FSOSCEN
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
BWP
—
—
—
PWP<3:0>
—
ICESEL
—
DEBUG<1:0>
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-43: DEVICE AND REVISION ID SUMMARY(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
VER<3:0>
DEVID<27:16>
xxxx
xxxx
F220
DEVID
DEVID<15:0>
Legend:
Note
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset values are dependent on the device variant. Refer to the “PIC32MX5XX/6XX/7XX Family Silicon Errata and Data Sheet Clarification” (DS80480) for more information.
1:
TABLE 4-44: USB REGISTER MAP
Bits
23/7
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IDIF
—
—
—
—
ACTVIF
—
—
—
—
—
—
—
—
—
—
—
0000
5040 U1OTGIR
5050 U1OTGIE
5060 U1OTGSTAT
5070 U1OTGCON
T1MSECIF LSTATEIF
SESVDIF SESENDIF
VBUSVDIF 0000
0000
VBUSVDIE 0000
0000
VBUSVD 0000
0000
31:16
15:0
—
—
—
—
—
IDIE
—
T1MSECIE LSTATEIE
ACTVIE
—
SESVDIE SESENDIE
31:16
15:0
—
—
—
—
LSTATE
—
—
SESVD
—
—
SESEND
—
—
ID
—
31:16
15:0
—
—
—
DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS 0000
31:16
15:0
—
UACTPND
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
5080
5200
U1PWRC
U1IR
USLPGRD USBBUSY
USUSPEND USBPWR 0000
31:16
—
IDLEIF
—
—
TRNIF
—
—
—
0000
0000
URSTIF
15:0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STALLIF ATTACHIF RESUMEIF
SOFIF
—
UERRIF
—
DETACHIF 0000
—
—
—
—
0000
0000
5210
5220
U1IE
URSTIE
STALLIE ATTACHIE RESUMEIE
IDLEIE
—
TRNIE
—
SOFIE
—
UERRIE
DETACHIE 0000
31:16
15:0
—
BTSEF
—
—
BMXEF
—
—
DMAEF
—
—
CRC5EF
EOFEF
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
U1EIR
BTOEF
—
DFN8EF CRC16EF
PIDEF
—
31:16
15:0
—
—
5230
5240
5250
5260
U1EIE
U1STAT
U1CON
U1ADDR
CRC5EE
EOFEE
—
BTSEE
—
BMXEE
—
DMAEE
—
BTOEE
—
DFN8EE CRC16EE
PIDEE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DIR
—
—
PPBI
—
—
—
ENDPT<3:0>
—
31:16
—
—
SE0
—
—
PKTDIS
TOKBUSY
—
—
USBRST
—
—
—
USBEN
SOFEN
—
15:0
—
—
—
—
—
—
—
—
JSTATE
HOSTEN RESUME PPBRST
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LSPDEN
—
—
DEVADDR<6:0>
—
—
—
—
—
—
—
—
—
31:16
15:0
—
—
—
—
—
—
—
—
5270 U1BDTP1
BDTPTRL<7:1>
—
31:16
15:0
—
—
5280
5290
U1FRML
U1FRMH
U1TOK
FRML<7:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FRMH<2:0>
—
—
—
31:16
15:0
52A0
PID<3:0>
EP<3:0>
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-44: USB REGISTER MAP (CONTINUED)
Bits
23/7
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
52B0
U1SOF
CNT<7:0>
31:16
15:0
—
52C0 U1BDTP2
52D0 U1BDTP3
52E0 U1CNFG1
BDTPTRH<7:0>
31:16
15:0
—
—
BDTPTRU<7:0>
31:16
15:0
—
USBSIDL
—
—
—
—
—
—
—
—
—
—
UTEYE UOEMON USBFRZ
UASUSPND 0001
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
0000
EPHSHK 0000
31:16
15:0
—
LSPD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5300
5310
5320
5330
5340
5350
5360
5370
5380
5390
53A0
53B0
53C0
U1EP0
U1EP1
U1EP2
U1EP3
U1EP4
U1EP5
U1EP6
U1EP7
U1EP8
U1EP9
U1EP10
U1EP11
U1EP12
U1EP13
RETRYDIS
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
EPCONDIS EPRXEN EPTXEN EPSTALL
31:16
15:0
—
—
—
—
—
53D0
EPCONDIS EPRXEN EPTXEN EPSTALL
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-44: USB REGISTER MAP (CONTINUED)
Bits
23/7
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
53E0
U1EP14
U1EP15
EPCONDIS EPRXEN EPTXEN EPSTALL
EPHSHK 0000
0000
EPHSHK 0000
31:16
15:0
—
—
—
—
—
53F0
EPCONDIS EPRXEN EPTXEN EPSTALL
Legend:
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-45: CAN1 REGISTER SUMMARY FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX575F256L, PIC32MX575F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L
DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
—
—
SIDLE
—
—
ABAT
BUSY
—
REQOP<2:0>
OPMOD<2:0>
—
CANCAP
—
—
—
—
—
—
0400
0000
0000
0000
0000
0000
0000
0000
B000
B010
B020
B030
B040
B050
C1CON
C1CFG
C1INT
—
—
—
—
—
—
—
—
—
—
—
DNCNT<4:0>
31:16
—
—
WAKFIL
SEG2PH<2:0>
15:0 SEG2PHTS
SAM
WAKIE
WAKIF
—
SEG1PH<2:0>
SERRIE
SERRIF
—
PRSEG<2:0>
SJW<1:0>
BRP<5:0>
31:16
15:0
IVRIE
IVRIF
—
CERRIE
CERRIF
—
RBOVIE
RBOVIF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MODIE
MODIF
—
CTMRIE
CTMRIF
—
RBIE
RBIF
—
TBIE
TBIF
—
31:16
15:0
C1VEC
C1TREC
C1FSTAT
—
—
—
FILHIT<4:0>
—
ICOD<6:0>
RXBP
31:16
15:0
—
—
—
—
—
—
—
—
TXBO
TXBP
TXWARN RXWARN EWARN 0000
TEC<7:0>
REC<7:0>
0000
31:16 FIFOIP31 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP26 FIFOIP25 FIFOIP24 FIFOIP23 FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16 0000
15:0 FIFOIP15 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9 FIFOIP8 FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0 0000
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
B060 C1RXOVF
15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9
31:16
RXOVF8
RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000
CANTS<15:0>
0000
0000
B070
B080
B090
B0A0
B0B0
C1TMR
C1RXM0
C1RXM1
C1RXM2
C1RXM3
15:0
CANTSPRE<15:0>
EID<15:0>
31:16
SID<10:0>
SID<10:0>
SID<10:0>
SID<10:0>
-—
-—
-—
-—
MIDE
MIDE
MIDE
MIDE
—
—
—
—
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
xxxx
xxxx
15:0
31:16
xxxx
xxxx
15:0
EID<15:0>
31:16
xxxx
xxxx
15:0
EID<15:0>
31:16
xxxx
xxxx
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
15:0
EID<15:0>
31:16 FLTEN3
15:0 FLTEN1
31:16 FLTEN7
15:0 FLTEN5
31:16 FLTEN11
15:0 FLTEN9
31:16 FLTEN15
15:0 FLTEN13
31:16 FLTEN19
15:0 FLTEN17
MSEL3<1:0>
MSEL1<1:0>
MSEL7<1:0>
MSEL5<1:0>
MSEL11<1:0>
MSEL9<1:0>
MSEL15<1:0>
MSEL13<1:0>
MSEL19<1:0>
MSEL17<1:0>
FSEL3<4:0>
FSEL1<4:0>
FSEL7<4:0>
FSEL5<4:0>
FSEL11<4:0>
FSEL9<4:0>
FSEL15<4:0>
FSEL13<4:0>
FSEL19<4:0>
FSEL17<4:0>
FLTEN2
MSEL2<1:0>
MSEL0<1:0>
MSEL6<1:0>
MSEL4<1:0>
MSEL10<1:0>
MSEL8<1:0>
MSEL14<1:0>
MSEL12<1:0>
MSEL18<1:0>
MSEL16<1:0>
FSEL2<4:0>
FSEL0<4:0>
FSEL6<4:0>
FSEL4<4:0>
FSEL10<4:0>
FSEL8<4:0>
FSEL14<4:0>
FSEL12<4:0>
FSEL18<4:0>
FSEL16<4:0:
B0C0 C1FLTCON0
B0D0 C1FLTCON1
B0E0 C1FLTCON2
B0F0 C1FLTCON3
B100 C1FLTCON4
FLTEN0
FLTEN6
FLTEN4
FLTEN10
FLTEN8
FLTEN14
FLTEN12
FLTEN18
FLTEN16
Legend:
Note
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
1:
information.
TABLE 4-45: CAN1 REGISTER SUMMARY FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX575F256L, PIC32MX575F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L
DEVICES(1) (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 FLTEN23
15:0 FLTEN21
31:16 FLTEN27
15:0 FLTEN25
31:16 FLTEN31
15:0 FLTEN29
31:16
MSEL23<1:0>
FSEL23<4:0>
FSEL21<4:0>
FSEL27<4:0>
FSEL25<4:0>
FSEL31<4:0>
FSEL29<4:0>
SID<10:0>
FLTEN22
FLTEN20
FLTEN26
FLTEN24
FLTEN30
FLTEN28
MSEL22<1:0>
MSEL20<1:0>
MSEL26<1:0>
MSEL24<1:0>
MSEL30<1:0>
MSEL28<1:0>
FSEL22<4:0>
FSEL20<4:0>
FSEL26<4:0>
FSEL24<4:0>
FSEL30<4:0>
FSEL28<4:0>
—
0000
0000
0000
0000
0000
0000
B110 C1FLTCON5
B120 C1FLTCON6
B130 C1FLTCON7
MSEL21<1:0>
MSEL27<1:0>
MSEL25<1:0>
MSEL31<1:0>
MSEL29<1:0>
-—
EXID
EID<17:16>
xxxx
xxxx
0000
0000
0000
0000
C1RXFn
B140
(n = 0-31)
15:0
EID<15:0>
C1FIFOBA<31:0>
31:16
B340 C1FIFOBA
15:0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FSIZE<4:0>
RTREN
C1FIFOCONn
B350
(n = 0-31)
FRESET
UINC
DONLY
TXEN
TXABAT TXLARB
TXERR
—
TXREQ
TXPRI<1:0>
RXN
EMPTYIE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
TXNFULLIE TXHALFIE TXEMPTYIE
TXNFULLIF TXHALFIF TXEMPTYIF
—
—
—
—
—
—
RXOVFLIE RXFULLIE RXHALFIE
RXOVFLIF RXFULLIF RXHALFIF
0000
0000
C1FIFOINTn
B360
(n = 0-31)
RXN
EMPTYIF
—
31:16
15:0
0000
0000
0000
0000
C1FIFOUAn
B370
C1FIFOUA<31:0>
(n = 0-31)
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C1FIFOCIn
B380
(n = 0-31)
C1FIFOCI<4:0>
Legend:
Note
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
1:
information.
TABLE 4-46: CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
ON
—
—
—
—
SIDLE
—
—
ABAT
BUSY
—
REQOP<2:0>
OPMOD<2:0>
—
CANCAP
—
—
—
—
—
—
0400
0000
C000
C010
C020
C030
C040
C2CON
C2CFG
C2INT
—
—
—
—
—
—
—
—
—
—
—
DNCNT<4:0>
31:16
—
—
WAKFIL
SEG2PH<2:0>
0000
0000
0000
0000
15:0 SEG2PHTS
SAM
WAKIE
WAKIF
—
SEG1PH<2:0>
SERRIE
SERRIF
—
PRSEG<2:0>
SJW<1:0>
BRP<5:0>
31:16
15:0
IVRIE
IVRIF
—
CERRIE
CERRIF
—
RBOVIE
RBOVIF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MODIE
MODIF
—
CTMRIE
CTMRIF
—
RBIE
RBIF
—
TBIE
TBIF
—
31:16
15:0
0000
0000
C2VEC
C2TREC
—
—
—
FILHIT<4:0>
—
ICOD<6:0>
RXBP
31:16
15:0
—
—
—
—
—
—
—
—
TXBO
TXBP
TXWARN RXWARN EWARN 0000
TEC<7:0>
REC<7:0>
0000
31:16 FIFOIP31 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP26 FIFOIP25 FIFOIP24 FIFOIP23 FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16
0000
0000
C050 C2FSTAT
C060 C2RXOVF
15:0 FIFOIP15 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9
FIFOIP8
FIFOIP7
FIFOIP6
FIFOIP5
FIFOIP4
FIFOIP3
FIFOIP2
FIFOIP1
FIFOIP0
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9
31:16
RXOVF8
RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000
CANTS<15:0>
0000
0000
C070
C080
C2TMR
15:0
CANTSPRE<15:0>
EID<15:0>
31:16
SID<10:0>
SID<10:0>
SID<10:0>
SID<10:0>
-—
-—
-—
-—
MIDE
MIDE
MIDE
MIDE
—
—
—
—
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
xxxx
xxxx
C2RXM0
15:0
31:16
xxxx
xxxx
C0A0 C2RXM1
C0B0 C2RXM2
C0B0 C2RXM3
C0C0 C2FLTCON0
C0D0 C2FLTCON1
C0E0 C2FLTCON2
C0F0 C2FLTCON3
15:0
EID<15:0>
31:16
xxxx
xxxx
15:0
EID<15:0>
31:16
xxxx
xxxx
15:0
EID<15:0>
31:16 FLTEN3
15:0 FLTEN1
31:16 FLTEN7
15:0 FLTEN5
31:16 FLTEN11
15:0 FLTEN9
31:16 FLTEN15
15:0 FLTEN13
MSEL3<1:0>
MSEL1<1:0>
MSEL7<1:0>
MSEL5<1:0>
MSEL11<1:0>
MSEL9<1:0>
MSEL15<1:0>
MSEL13<1:0>
FSEL3<4:0>
FSEL1<4:0>
FSEL7<4:0>
FSEL5<4:0>
FSEL11<4:0>
FSEL9<4:0>
FSEL15<4:0>
FSEL13<4:0>
FLTEN2
MSEL2<1:0>
MSEL0<1:0>
MSEL6<1:0>
MSEL4<1:0>
MSEL10<1:0>
MSEL8<1:0>
MSEL14<1:0>
MSEL12<1:0>
FSEL2<4:0>
FSEL0<4:0>
FSEL6<4:0>
FSEL4<4:0>
FSEL10<4:0>
FSEL8<4:0>
FSEL14<4:0>
FSEL12<4:0>
0000
0000
0000
0000
0000
0000
0000
0000
FLTEN0
FLTEN6
FLTEN4
FLTEN10
FLTEN8
FLTEN14
FLTEN12
Legend:
Note
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
1:
information.
TABLE 4-46: CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16 FLTEN19
15:0 FLTEN17
31:16 FLTEN23
15:0 FLTEN21
31:16 FLTEN27
15:0 FLTEN25
31:16 FLTEN31
15:0 FLTEN29
31:16
MSEL19<1:0>
FSEL19<4:0>
FSEL17<4:0>
FSEL23<4:0>
FSEL21<4:0>
FSEL27<4:0>
FSEL25<4:0>
FSEL31<4:0>
FSEL29<4:0>
SID<10:0>
FLTEN18
FLTEN16
FLTEN22
FLTEN20
FLTEN26
FLTEN24
FLTEN30
FLTEN28
MSEL18<1:0>
FSEL18<4:0>
FSEL16<4:0:
FSEL22<4:0>
FSEL20<4:0>
FSEL26<4:0>
FSEL24<4:0>
FSEL30<4:0>
FSEL28<4:0>
—
0000
0000
0000
0000
C100 C2FLTCON4
C110 C2FLTCON5
C120 C2FLTCON6
C130 C2FLTCON7
MSEL17<1:0>
MSEL23<1:0>
MSEL21<1:0>
MSEL27<1:0>
MSEL25<1:0>
MSEL31<1:0>
MSEL29<1:0>
MSEL16<1:0>
MSEL22<1:0>
MSEL20<1:0>
MSEL26<1:0>
MSEL24<1:0>
MSEL30<1:0>
MSEL28<1:0>
0000
0000
0000
0000
xxxx
xxxx
-—
EXID
EID<17:16>
C2RXFn
C140
(n = 0-31)
15:0
EID<15:0>
C2FIFOBA<31:0>
31:16
0000
0000
0000
0000
0000
C340 C2FIFOBA
15:0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FSIZE<4:0>
RTREN
C2FIFOCONn
C350
(n = 0-31)
FRESET
UINC
DONLY
TXEN
TXABAT
TXLARB
TXERR
—
TXREQ
TXPRI<1:0>
RXN
EMPTYIE
31:16
15:0
—
—
—
—
—
—
—
—
—
—
TXNFULLIE TXHALFIE TXEMPTYIE
TXNFULLIF TXHALFIF TXEMPTYIF
—
—
—
—
—
—
RXOVFLIE RXFULLIE RXHALFIE
RXOVFLIF RXFULLIF RXHALFIF
C2FIFOINTn
C360
(n = 0-31)
RXN
EMPTYIF
0000
—
31:16
15:0
0000
0000
0000
0000
C2FIFOUAn
C370
C2FIFOUA<31:0>
(n = 0-31)
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C2FIFOCIn
C380
(n = 0-31)
C2FIFOCI<4:0>
Legend:
Note
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
1:
information.
TABLE 4-47: ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
PTV<15:0>
0000
BUFCDEC 0000
9000 ETHCON1
9010 ETHCON2
9020 ETHTXST
9030 ETHRXST
ON
—
FRZ
—
SIDL
—
—
—
—
—
—
—
—
—
TXRTS
—
RXEN
—
AUTOFC
—
—
—
—
—
MANFC
—
—
—
—
—
—
—
—
—
—
31:16
15:0
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
—
—
—
RXBUFSZ<6:0>
31:16
15:0
TXSTADDR<31:16>
TXSTADDR<15:2>
RXSTADDR<31:16>
RXSTADDR<15:2>
—
—
—
—
31:16
15:0
31:16
15:0
9040
9050
ETHHT0
ETHHT1
HT<31:0>
31:16
15:0
HT<63:32>
PMM<31:0>
PMM<63:32>
31:16
15:0
9060 ETHPMM0
9070 ETHPMM1
9080 ETHPMCS
9090 ETHPMO
31:16
15:0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PMCS<15:0>
31:16
15:0
—
—
PMO<15:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
90A0 ETHRXFC
90B0 ETHRXWM
CRC
ERREN
CRC
OKEN
RUNT
ERREN
NOT
MEEN
15:0
HTEN
MPEN
NOTPM
PMMODE<3:0>
RUNTEN
UCEN
MCEN
BCEN
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RXFWM<7:0>
RXEWM<7:0>
0000
0000
0000
31:16
—
—
—
—
—
—
—
—
90C0
ETHIEN
ETHIRQ
TX
BUSEIE
RX
BUSEIE
EW
MARKIE
FW
MARKIE
RX
DONEIE
PK
TPENDIE
RX
ACTIE
TX
DONEIE
TX
ABORTIE
RX
BUFNAIE
RX
OVFLWIE
15:0
—
—
—
—
—
0000
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
90D0
TXBUSE
RXBUSE
EWMARK FWMARK
RXDONE PKTPEND
RXACT
TXDONE TXABORT RXBUFNA RXOVFLW 0000
Legend:
Note
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
1:
2:
Reset values default to the factory programmed value.
TABLE 4-47: ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BUFCNT<7:0>
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
90E0 ETHSTAT
BUSY
—
TXBUSY
—
RXBUSY
—
—
—
—
—
—
—
—
—
—
—
31:16
15:0
ETH
9100
RXOVFLOW
RXOVFLWCNT<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ETH
9110
FRMTXOK
FRMTXOKCNT<15:0>
31:16
15:0
—
—
ETH
9120
SCOLFRM
SCOLFRMCNT<15:0>
31:16
15:0
—
—
ETH
9130
MCOLFRM
MCOLFRMCNT<15:0>
31:16
15:0
—
—
ETH
9140
FRMRXOK
FRMRXOKCNT<15:0>
31:16
15:0
—
—
ETH
9150
FCSERR
FCSERRCNT<15:0>
31:16
15:0
—
—
ETH
9160
ALGNERR
ALGNERRCNT<15:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EMACx
9200
SOFT
RESET
SIM
RESET
RESET
RMCS
RESET
RFUN
RESET
TMCS
RESET
TFUN
CFG1
15:0
31:16
15:0
—
—
LOOPBACK TXPAUSE RXPAUSE PASSALL RXENABLE 800D
—
—
—
—
—
—
—
—
—
—
—
0000
EMACx
9210
EXCESS
DFR
BP
NOBKOFF
PAD
ENABLE
CRC
ENABLE
CFG2
—
NOBKOFF
—
—
LONGPRE PUREPRE AUTOPAD VLANPAD
DELAYCRC HUGEFRM LENGTHCK FULLDPLX 4082
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B2BIPKTGP<6:0>
—
—
—
—
—
—
—
—
—
—
—
—
0000
0012
0000
0C12
0000
370F
0000
05EE
EMACx
9220
IPGT
31:16
15:0
—
—
—
EMACx
9230
IPGR
NB2BIPKTGP1<6:0>
—
NB2BIPKTGP2<6:0>
—
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EMACx
9240
CLRT
CWINDOW<5:0>
RETX<3:0>
31:16
15:0
—
—
—
—
—
EMACx
9250
MAXF
MACMAXF<15:0>
Legend:
Note
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
1:
2:
Reset values default to the factory programmed value.
TABLE 4-47: ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
1000
EMACx
SUPP
9260
9270
9280
RESET
RMII
SPEED
RMII
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
EMACx
TEST
SHRTQNTA
TESTBP TESTPAUSE
31:16
—
—
—
EMACx
MCFG
RESET
MGMT
15:0
—
—
—
—
—
—
—
—
—
CLKSEL<3:0>
NOPRE
SCANINC 0020
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCAN
—
—
READ
—
0000
0000
0000
0100
0000
0000
0000
0000
0000
EMACx
MCMD
9290
92A0
92B0
92C0
92D0
9300
9310
9320
—
—
31:16
15:0
—
PHYADDR<4:0>
—
—
REGADDR<4:0>
—
EMACx
MADR
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EMACx
MWTD
MWTD<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
EMACx
MRDD
MRDD<15:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCAN
—
EMACx
MIND
LINKFAIL NOTVALID
MIIMBUSY 0000
31:16
15:0
—
—
—
—
—
—
—
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
EMACx
(2)
SA0
STNADDR6<7:0>
STNADDR5<7:0>
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EMACx
(2)
SA1
STNADDR4<7:0>
STNADDR3<7:0>
31:16
15:0
—
—
—
—
EMACx
(2)
SA2
STNADDR2<7:0>
STNADDR1<7:0>
Legend:
Note
x= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
1:
2:
Reset values default to the factory programmed value.
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 104
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
PIC32MX5XX/6XX/7XX devices contain an internal
Flash program memory for executing user code. There
are three methods by which the user can program this
memory:
5.0
FLASH PROGRAM MEMORY
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 5. “Flash Pro-
gram Memory” (DS61121) in the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
1. Run-Time Self Programming (RTSP)
2. EJTAG Programming
3. In-Circuit Serial Programming™ (ICSP™)
RTSP is performed by software executing from either
Flash or RAM memory. Information about RTSP
techniques is available in Section 5. “Flash Program
Memory” (DS61121) in the “PIC32MX Family
Reference Manual”.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
EJTAG is performed using the EJTAG port of the
device and an EJTAG capable programmer.
ICSP is performed using a serial data connection to the
device and allows much faster programming times than
RTSP.
The EJTAG and ICSP methods are described in the
“PIC32MX
Flash
Programming
Specification”
(DS61145), which can be downloaded from the
Microchip web site.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 105
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 106
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
The Reset module combines all Reset sources and
controls the device Master Reset signal, SYSRST. The
following is a list of device Reset sources:
6.0
RESETS
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 7. “Resets”
(DS61118) in the “PIC32MX Family
Reference Manual”, which is available
• POR: Power-on Reset
• MCLR: Master Clear Reset Pin
• SWR: Software Reset
• WDTR: Watchdog Timer Reset
• BOR: Brown-out Reset
• CMR: Configuration Mismatch Reset
from
the
Microchip
web
site
A simplified block diagram of the Reset module is
shown in Figure 6-1.
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
FIGURE 6-1:
SYSTEM RESET BLOCK DIAGRAM
MCLR
MCLR
WDTR
Glitch Filter
Sleep or Idle
WDT
Time-out
Voltage
Regulator
Enabled
POR
Power-up
Timer
SYSRST
VDD
VDD Rise
Detect
BOR
Brown-out
Reset
Configuration
Mismatch
Reset
CMR
SWR
Software Reset
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 107
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 108
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
The PIC32MX5XX/6XX/7XX interrupt module includes
the following features:
7.0
INTERRUPT CONTROLLER
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Interrupt
Controller” (DS61108) in the “PIC32MX
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
• Up to 96 Interrupt Sources
• Up to 64 Interrupt Vectors
• Single and Multi-Vector mode Operations
• Five External Interrupts with Edge Polarity Control
• Interrupt Proximity Timer
• Module Freeze in Debug mode
• Seven User-Selectable Priority Levels for each
Vector
• Four User-Selectable Subpriority Levels within
each Priority
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to
4.0 “Memory Organization” in this data
sheet for device-specific register and bit
information.
• Dedicated Shadow Set for User-Selectable
Priority Level
• Software can Generate any Interrupt
• User-Configurable Interrupt Vector Table Location
• User-Configurable Interrupt Vector Spacing
PIC32MX5XX/6XX/7XX devices generate interrupt
requests in response to interrupt events from peripheral
modules. The interrupt control module exists externally
to the CPU logic and prioritizes the interrupt events
before presenting them to the CPU.
FIGURE 7-1:
INTERRUPT CONTROLLER MODULE
Vector Number
Interrupt Controller
CPU Core
Priority Level
Shadow Set Number
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 109
PIC32MX5XX/6XX/7XX
TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION
Interrupt Bit Location
Vector
Number
Interrupt Source(1)
IRQ
Flag
Enable
Priority
Sub-Priority
Highest Natural Order Priority
CT – Core Timer Interrupt
CS0 – Core Software Interrupt 0
CS1 – Core Software Interrupt 1
INT0 – External Interrupt 0
T1 – Timer1
0
1
0
1
IFS0<0>
IFS0<1>
IFS0<2>
IFS0<3>
IFS0<4>
IFS0<5>
IFS0<6>
IFS0<7>
IFS0<8>
IFS0<9>
IEC0<0>
IPC0<4:2>
IPC0<1:0>
IPC0<9:8>
IEC0<1> IPC0<12:10>
2
2
IEC0<2> IPC0<20:18> IPC0<17:16>
IEC0<3> IPC0<28:26> IPC0<25:24>
3
3
4
4
IEC0<4>
IPC1<4:2>
IPC1<1:0>
IPC1<9:8>
IC1 – Input Capture 1
5
5
IEC0<5> IPC1<12:10>
OC1 – Output Compare 1
INT1 – External Interrupt 1
T2 – Timer2
6
6
IEC0<6> IPC1<20:18> IPC1<17:16>
IEC0<7> IPC1<28:26> IPC1<25:24>
7
7
8
8
IEC0<8>
IPC2<4:2>
IPC2<1:0>
IPC2<9:8>
IC2 – Input Capture 2
9
9
IEC0<9> IPC2<12:10>
OC2 – Output Compare 2
INT2 – External Interrupt 2
T3 – Timer3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
10
11
12
13
14
15
16
17
18
19
20
21
22
23
23
23
IFS0<10> IEC0<10> IPC2<20:18> IPC2<17:16>
IFS0<11> IEC0<11> IPC2<28:26> IPC2<25:24>
IFS0<12> IEC0<12>
IPC3<4:2>
IPC3<1:0>
IPC3<9:8>
IC3 – Input Capture 3
IFS0<13> IEC0<13> IPC3<12:10>
OC3 – Output Compare 3
INT3 – External Interrupt 3
T4 – Timer4
IFS0<14> IEC0<14> IPC3<20:18> IPC3<17:16>
IFS0<15> IEC0<15> IPC3<28:26> IPC3<25:24>
IFS0<16> IEC0<16>
IPC4<4:2>
IPC4<1:0>
IPC4<9:8>
IC4 – Input Capture 4
IFS0<17> IEC0<17> IPC4<12:10>
OC4 – Output Compare 4
INT4 – External Interrupt 4
T5 – Timer5
IFS0<18> IEC0<18> IPC4<20:18> IPC4<17:16>
IFS0<19> IEC0<19> IPC4<28:26> IPC4<25:24>
IFS0<20> IEC0<20>
IPC5<4:2>
IPC5<1:0>
IPC5<9:8>
IC5 – Input Capture 5
IFS0<21> IEC0<21> IPC5<12:10>
OC5 – Output Compare 5
SPI1E – SPI1 Fault
IFS0<22> IEC0<22> IPC5<20:18> IPC5<17:16>
IFS0<23> IEC0<23> IPC5<28:26> IPC5<25:24>
IFS0<24> IEC0<24> IPC5<28:26> IPC5<25:24>
IFS0<25> IEC0<25> IPC5<28:26> IPC5<25:24>
SPI1RX – SPI1 Receive Done
SPI1TX – SPI1 Transfer Done
U1AE – UART1A Error
SPI1AE – SPI1A Fault
26
27
28
24
24
24
IFS0<26> IEC0<26>
IFS0<27> IEC0<27>
IFS0<28> IEC0<28>
IPC6<4:2>
IPC6<4:2>
IPC6<4:2>
IPC6<1:0>
IPC6<1:0>
IPC6<1:0>
I2C1AB – I2C1A Bus Collision Event
U1ARX – UART1A Receiver
SPI1ARX – SPI1A Receive Done
I2C1AS – I2C1A Slave Event
U1ATX – UART1A Transmitter
SPI1ATX – SPI1A Transfer Done
I2C1AM – I2C1A Master Event
I2C1B – I2C1 Bus Collision Event
I2C1S – I2C1 Slave Event
I2C1M – I2C1 Master Event
CN – Input Change Interrupt
AD1 – ADC1 Convert Done
PMP – Parallel Master Port
29
30
31
32
33
34
25
25
25
26
27
28
IFS0<29> IEC0<29> IPC6<12:10>
IFS0<30> IEC0<30> IPC6<12:10>
IFS0<31> IEC0<31> IPC6<12:10>
IPC6<9:8>
IPC6<9:8>
IPC6<9:8>
IFS1<0>
IFS1<1>
IFS1<2>
IEC1<0> IPC6<20:18> IPC6<17:16>
IEC1<1> IPC6<28:26> IPC6<25:24>
IEC1<2>
IPC7<4:2>
IPC7<1:0>
Note 1: Not all interrupt sources are available on all devices. See Table 1 for the list of available peripherals.
DS61156C-page 110
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Bit Location
Vector
Number
Interrupt Source(1)
IRQ
Flag
Enable
Priority
Sub-Priority
CMP1 – Comparator Interrupt
CMP2 – Comparator Interrupt
35
36
29
30
IFS1<3>
IFS1<4>
IEC1<3> IPC7<12:10>
IPC7<9:8>
IEC1<4> IPC7<20:18> IPC7<17:16>
U2AE – UART2A Error
SPI2AE – SPI2A Fault
I2C2AB – I2C2A Bus Collision Event
37
38
39
40
41
42
31
31
31
32
32
32
IFS1<5>
IFS1<6>
IFS1<7>
IFS1<8>
IFS1<9>
IEC1<5> IPC7<28:26> IPC7<25:24>
U2ARX – UART2A Receiver
SPI2ARX – SPI2A Receive Done
I2C2AS – I2C2A Slave Event
IEC1<6> IPC7<28:26> IPC7<25:24>
IEC1<7> IPC7<28:26> IPC7<25:24>
U2ATX – UART2A Transmitter
SPI2ATX – SPI2A Transfer Done
IC2AM – I2C2A Master Event
U3AE – UART3A Error
SPI3AE – SPI3A Fault
I2C3AB – I2C3A Bus Collision Event
IEC1<8>
IEC1<9>
IPC8<4:2>
IPC8<4:2>
IPC8<4:2>
IPC8<1:0>
IPC8<1:0>
IPC8<1:0>
U3ARX – UART3A Receiver
SPI3ARX – SPI3A Receive Done
I2C3AS – I2C3A Slave Event
U3ATX – UART3A Transmitter
SPI3ATX – SPI3A Transfer Done
IC3AM – I2C3A Master Event
IFS1<10> IEC1<10>
I2C2B – I2C2 Bus Collision Event
I2C2S – I2C2 Slave Event
I2C2M – I2C2 Master Event
FSCM – Fail-Safe Clock Monitor
RTCC – Real-Time Clock
DMA0 – DMA Channel 0
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
33
33
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
5
IFS1<11> IEC1<11> IPC8<12:10>
IFS1<12> IEC1<12> IPC8<12:10>
IFS1<13> IEC1<13> IPC8<12:10>
IPC8<9:8>
IPC8<9:8>
IPC8<9:8>
IFS1<14> IEC1<14> IPC8<20:18> IPC8<17:16>
IFS1<15> IEC1<15> IPC8<28:26> IPC8<25:24>
IFS1<16> IEC1<16>
IPC9<4:2>
IPC9<1:0>
IPC9<9:8>
DMA1 – DMA Channel 1
IFS1<17> IEC1<17> IPC9<12:10>
DMA2 – DMA Channel 2
IFS1<18> IEC1<18> IPC9<20:18> IPC9<17:16>
IFS1<19> IEC1<19> IPC9<28:26> IPC9<25:24>
DMA3 – DMA Channel 3
DMA4 – DMA Channel 4
IFS1<20> IEC1<20> IPC10<4:2>
IPC10<1:0>
DMA5 – DMA Channel 5
IFS1<21> IEC1<21> IPC10<12:10> IPC10<9:8>
IFS1<22> IEC1<22> IPC10<20:18> IPC10<17:16>
IFS1<23> IEC1<23> IPC10<28:26> IPC10<25:24>
DMA6 – DMA Channel 6
DMA7 – DMA Channel 7
FCE – Flash Control Event
USB – USB Interrupt
IFS1<24> IEC1<24> IPC11<4:2>
IPC11<1:0>
IFS1<25> IEC1<25> IPC11<12:10> IPC11<9:8>
IFS1<26> IEC1<26> IPC11<20:18> IPC11<17:16>
IFS1<27> IEC1<27> IPC11<28:26> IPC11<25:24>
CAN1 – Control Area Network 1
CAN2 – Control Area Network 2
ETH – Ethernet Interrupt
IFS1<28> IEC1<28> IPC12<4:2>
IFS1<29> IEC1<29> IPC1<12:10>
IFS1<30> IEC1<30> IPC2<12:10>
IFS1<31> IEC1<31> IPC3<12:10>
IPC12<1:0>
IPC1<9:8>
IPC2<9:8>
IPC3<9:8>
IPC4<9:8>
IPC5<9:8>
IPC7<1:0>
IC1E – Input Capture 1 Error
IC2E – Input Capture 2 Error
IC3E – Input Capture 3 Error
IC4E – Input Capture 4 Error
IC4E – Input Capture 5 Error
PMPE – Parallel Master Port Error
U1BE – UART1B Error
9
13
17
21
28
49
IFS2<0>
IFS2<1>
IFS2<2>
IFS2<3>
IEC2<0> IPC4<12:10>
IEC2<1> IPC5<12:10>
IEC2<2>
IPC7<4:2>
IEC2<3> IPC12<12:10> IPC12<9:8>
Note 1: Not all interrupt sources are available on all devices. See Table 1 for the list of available peripherals.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 111
PIC32MX5XX/6XX/7XX
TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Bit Location
Enable Priority
Vector
Number
Interrupt Source(1)
IRQ
Flag
Sub-Priority
U1BRX – UART1B Receiver
U1BTX – UART1B Transmitter
U2BE – UART2B Error
68
69
70
71
72
73
74
75
—
49
49
50
50
50
51
51
51
—
IFS2<4>
IFS2<5>
IFS2<6>
IFS2<7>
IFS2<8>
IFS2<9>
IEC2<4> IPC12<12:10> IPC12<9:8>
IEC2<5> IPC12<12:10> IPC12<9:8>
IEC2<6> IPC12<20:18> IPC12<17:16>
IEC2<7> IPC12<20:18> IPC12<17:16>
IEC2<8> IPC12<20:18> IPC12<17:16>
IEC2<9> IPC12<28:26> IPC12<25:24>
U2BRX – UART2B Receiver
U2BTX – UART2B Transmitter
U3BE – UART3B Error
U3BRX – UART3B Receiver
U3BTX – UART3B Transmitter
(Reserved)
IFS2<10> IEC2<10> IPC12<28:26> IPC12<25:24>
IFS2<11> IEC2<11> IPC12<28:26> IPC12<25:24>
—
—
—
—
Lowest Natural Order Priority
Note 1: Not all interrupt sources are available on all devices. See Table 1 for the list of available peripherals.
DS61156C-page 112
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
The PIC32MX5XX/6XX/7XX oscillator system has the
following modules and features:
8.0
OSCILLATOR
CONFIGURATION
• A Total of Four External and Internal Oscillator
Options as Clock Sources
• On-Chip PLL with User-Selectable Input Divider,
Multiplier and Output Divider to Boost Operating
Frequency on Select Internal and External
Oscillator Sources
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 6. “Oscillator
• On-Chip User-Selectable Divisor Postscaler on
Select Oscillator Sources
Configuration”
(DS61112) in the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
• Software-Controllable Switching Between
Various Clock Sources
• A Fail-Safe Clock Monitor (FSCM) that Detects
Clock Failure and Permits Safe Application
Recovery or Shutdown
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
• Dedicated On-Chip PLL for USB Peripheral
FIGURE 8-1:
PIC32MX5XX/6XX/7XX FAMILY CLOCK DIAGRAM
USB PLL
USB Clock (48 MHz)
UFIN
div 2
div x
PLL x24
UFRCEN
FUPLLEN
UFIN 4 MHz
FUPLLDIV<2:0>
Primary Oscillator
(POSC)
C1(3)
OSC1
XT, HS, EC
To Internal
Logic
(2)
F
R
Peripherals
PBCLK
Postscaler
div x
4 MHz FIN 5 MHz
FIN
XTPLL, HSPLL,
ECPLL, FRCPLL
XTAL
Enable
div x
div y
PLL
(1)
S
R
div 2
C2(3)
OSC2(4)
PLL Input Divider
FPLLIDIV<2:0>
PLL Output Divider
PLLODIV<2:0>
PBDIV<2:0>
ADC
PLL Multiplier
PLLMULT<2:0>
FRC
Oscillator
COSC<2:0>
FRC
CPU and Select Peripherals
8 MHz typical
FRC/16
FRCDIV
div 16
TUN<5:0>
Postscaler
FRCDIV<2:0>
31.25 kHz typical
LPRC
SOSC
LPRC
Oscillator
Secondary Oscillator (SOSC)
SOSCO
SOSCI
32.768 kHz
SOSCEN and FSOSCEN
Clock Control Logic
FSCM INT
Fail-Safe
Clock
Monitor
FSCM Event
Notes: 1. A series resistor, RS, may be required for AT strip cut crystals.
2. The internal feedback resistor, RF, is typically in the range of 2 to 10 M
3. Refer to Section 6. “Oscillator Configuration” (DS61112) in the
“PIC32MX Family Reference Manual” for help in determining the best
oscillator components.
NOSC<2:0>
COSC<2:0>
FSCMEN<1:0>
OSWEN
WDT, PWRT
Timer1, RTCC
4. PBCLK out is available on the OSC2 pin in certain clock modes.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 113
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 114
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Prefetch cache increases performance for applications
executing out of the cacheable program Flash memory
regions by implementing instruction caching, constant
data caching and instruction prefetching.
9.0
PREFETCH CACHE
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
Cache” (DS61119) in the “PIC32MX
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
9.1
Features
• 16 Fully Associative Lockable Cache Lines
• 16-Byte Cache Lines
• Up to Four Cache Lines Allocated to Data
• Two Cache Lines with Address Mask to Hold
Repeated Instructions
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to
4.0 “Memory Organization” in this data
sheet for device-specific register and bit
information.
• Pseudo LRU Replacement Policy
• All Cache Lines are Software Writable
• 16-Byte Parallel Memory Fetch
• Predictive Instruction Prefetch
FIGURE 9-1:
PREFETCH MODULE BLOCK DIAGRAM
FSM
CTRL
Tag Logic
Cache Line
CTRL
Bus Ctrl
Cache Ctrl
Prefetch Ctrl
Hit LRU
Cache
Line
RDATA
Address
Encode
Miss LRU
Hit Logic
Prefetch
Prefetch
PFM
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 115
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 116
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
• Automatic Word-Size Detection:
10.0 DIRECT MEMORY ACCESS
(DMA) CONTROLLER
- Transfer granularity, down to byte level
- Bytes need not be word-aligned at source
and destination
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 31. “Direct
Memory Access (DMA) Controller”
(DS61117) in the “PIC32MX Family
Reference Manual”, which is available
• Fixed Priority Channel Arbitration
• Flexible DMA Channel Operating modes:
- Manual (software) or automatic (interrupt)
DMA requests
- One-Shot or Auto-Repeat Block Transfer
modes
- Channel-to-channel chaining
• Flexible DMA Requests:
from
the
Microchip
web
site
- A DMA request can be selected from any of
the peripheral interrupt sources
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
- Each channel can select any (appropriate)
observable interrupt as its DMA request
source
- A DMA transfer abort can be selected from
any of the peripheral interrupt sources
- Pattern (data) match transfer termination
• Multiple DMA Channel Status Interrupts:
- DMA channel block transfer complete
- Source empty or half empty
The PIC32MX Direct Memory Access (DMA) controller
is a bus master module useful for data transfers
between different devices without CPU intervention.
The source and destination of a DMA transfer can be
any of the memory mapped modules existent in the
PIC32MX (such as Peripheral Bus (PBUS) devices:
SPI, UART, I2C™, etc.) or memory itself.
- Destination full or half full
- DMA transfer aborted due to an external
event
- Invalid DMA address generated
• DMA Debug Support Features:
Following are some of the key features of the DMA
controller module:
- Most recent address accessed by a DMA
channel
• Four Identical Channels, each Featuring:
- Auto-Increment Source and Destination
Address registers
- Most recent DMA channel to transfer data
• CRC Generation Module:
- Source and Destination Pointers
- CRC module can be assigned to any of the
available channels
- Memory to memory and memory to
peripheral transfers
- CRC module is highly configurable
FIGURE 10-1:
DMA BLOCK DIAGRAM
INT Controller
System IRQ
Peripheral Bus
Address Decoder
Channel 0 Control
I0
I1
I2
Channel 1 Control
Channel n Control
Y
Device Bus + Bus Arbitration
Bus Interface
In
Global Control
(DMACON)
Channel Priority
Arbitration
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 117
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 118
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
The clock generator provides the 48 MHz clock
required for USB full-speed and low-speed communi-
cation. The voltage comparators monitor the voltage on
the VBUS pin to determine the state of the bus. The
transceiver provides the analog translation between
the USB bus and the digital logic. The SIE is a state
machine that transfers data to and from the endpoint
buffers and generates the hardware protocol for data
transfers. The USB DMA controller transfers data
between the data buffers in RAM and the SIE. The inte-
grated pull-up and pull-down resistors eliminate the
need for external signaling components. The register
interface allows the CPU to configure and
communicate with the module.
11.0 USB ON-THE-GO (OTG)
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 27. “USB On-
The-Go (OTG)” (DS61126) in the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The PIC32MX USB module includes the following
features:
• USB Full-Speed Support for Host and Device
• Low-Speed Host Support
The Universal Serial Bus (USB) module contains
analog and digital components to provide a USB 2.0
full-speed and low-speed embedded host, full-speed
device or OTG implementation with a minimum of
external components. This module in Host mode is
intended for use as an embedded host and therefore
does not implement a UHCI or OHCI controller.
• USB OTG Support
• Integrated Signaling Resistors
• Integrated Analog Comparators for VBUS
Monitoring
• Integrated USB Transceiver
• Transaction Handshaking Performed by
Hardware
The USB module consists of the clock generator, the
USB voltage comparators, the transceiver, the Serial
Interface Engine (SIE), a dedicated USB DMA control-
ler, pull-up and pull-down resistors, and the register
interface. A block diagram of the PIC32MX USB OTG
module is presented in Figure 11-1.
• Endpoint Buffering Anywhere in System RAM
• Integrated DMA to Access System RAM and
Flash
Note:
IMPORTANT! The implementation and
use of the USB specifications, as well as
other third party specifications or technol-
ogies, may require licensing; including,
but not limited to, USB Implementers
Forum, Inc. (also referred to as USB-IF).
The user is fully responsible for investigat-
ing and satisfying any applicable licensing
obligations.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 119
PIC32MX5XX/6XX/7XX
FIGURE 11-1:
PIC32MX5XX/6XX/7XX FAMILY USB INTERFACE DIAGRAM
USBEN
FRC
USB Suspend
Oscillator
8 MHz Typical
CPU Clock Not POST
Sleep
(4)
TUN<5:0>
Primary Oscillator
(POST)
(5)
UFIN
PLL
Div x
Div 2
(3)
UFRCEN
OSC1
OSC2
(6)
(6)
FUPLLEN
To Clock Generator for Core and Peripherals
Sleep or Idle
FUPLLIDIV
USB Suspend
(1)
(PB Out)
USB Module
USB
SRP Charge
SRP Discharge
Voltage
Bus
Comparators
(7)
48 MHz USB Clock
Full Speed Pull-up
(2)
D+
Registers
and
Control
Interface
Host Pull-down
SIE
Transceiver
Low Speed Pull-up
(2)
D-
DMA
System
RAM
Host Pull-down
ID Pull-up
(8)
ID
(8)
Vibes
Transceiver Power 3.3V
VUSB
Note 1: PB clock is only available on this pin for select EC modes.
2: Pins can be used as digital inputs when USB is not enabled.
3: This bit field is contained in the OSCCON register.
4: This bit field is contained in the OSCTRM register.
5: USB PLL UFIN requirements: 4 MHz.
6: This bit field is contained in the DEVCFG2 register.
7: A 48 MHz clock is required for proper USB operation.
8: Pins can be used as GPIO when the USB module is disabled.
DS61156C-page 120
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
General purpose I/O pins are the simplest of peripher-
als. They allow the PIC® MCU to monitor and control
other devices. To add flexibility and functionality, some
pins are multiplexed with alternate function(s). These
functions depend on which peripheral features are on
the device. In general, when a peripheral is functioning,
that pin may not be used as a general purpose I/O pin.
12.0 I/O PORTS
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS61120) in the “PIC32MX Family
Reference Manual”, which is available
Following are some of the key features of this module:
• Individual Output Pin Open-Drain Enable/Disable
• Individual Input Pin Weak Pull-up Enable/Disable
from
the
Microchip
web
site
• Monitor Selective Inputs and Generate Interrupt
when Change in Pin State is Detected
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
• Operation during CPU Sleep and Idle modes
• Fast Bit Manipulation using CLR, SET and INV
Registers
Figure 12-1 shows a block diagram of a typical
multiplexed I/O port.
FIGURE 12-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Peripheral Module
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
PIO Module
RD ODC
Data Bus
SYSCLK
D
Q
Q
ODC
CK
EN
WR ODC
RD TRIS
1
0
IO Cell
0
1
D
Q
Q
1
0
TRIS
LAT
CK
EN
WR TRIS
Output Multiplexers
D
Q
Q
IO Pin
CK
EN
WR LAT
WR PORT
RD LAT
1
0
RD PORT
Q
Q
D
Q
Q
D
Sleep
CK
CK
SYSCLK
Synchronization
Peripheral Input
R
Peripheral Input Buffer
Legend:
Note:
R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure
for any specific port/peripheral combination may be different than it is shown here.
2010 Microchip Technology Inc.
Preliminary
DS61156C - page 121
PIC32MX5XX/6XX/7XX
12.1.2
DIGITAL INPUTS
12.1 Parallel I/O (PIO) Ports
Pins are configured as digital inputs by setting the cor-
responding TRIS register bits = 1. When configured as
inputs, they are either TTL buffers or Schmitt Triggers.
Several digital pins share functionality with analog
inputs and default to the analog inputs at POR. Setting
the corresponding bit in the AD1PCFG register = 1
enables the pin as a digital pin.
All port pins have three registers (TRIS, LAT and
PORT) that are directly associated with their operation.
TRIS is a Data Direction or Tri-State Control register
that determines whether a digital pin is an input or an
output. Setting a TRISx register bit = 1configures the
corresponding I/O pin as an input; setting a TRISx
register bit = 0configures the corresponding I/O pin as
an output. All port I/O pins are defined as inputs after a
device Reset. Certain I/O pins are shared with analog
peripherals and default to analog inputs after a device
Reset.
The maximum input voltage allowed on the input pins
is the same as the maximum VIH specification. Refer to
Section 31.0 “Electrical Characteristics” for VIH
specification details.
Note:
Analog levels on any pin that is defined as
a digital input (including the ANx pins) may
cause the input buffer to consume current
that exceeds the device specifications.
PORT is a register used to read the current state of the
signal applied to the port I/O pins. Writing to a PORTx
register performs a write to the port’s latch, LATx
register, latching the data to the port’s I/O pins.
LAT is a register used to write data to the port I/O pins.
The LATx Latch register holds the data written to either
the LATx or PORTx registers. Reading the LATx Latch
register reads the last value written to the
corresponding PORT or Latch register.
12.1.3
ANALOG INPUTS
Certain pins can be configured as analog inputs used
by the ADC and comparator modules. Setting the cor-
responding bits in the AD1PCFG register = 0enables
the pin as an analog input pin and must have the corre-
sponding TRIS bit set = 1 (input). If the TRIS bit is
cleared = 0 (output), the digital output level (VOH or
VOL) will be converted. Any time a port I/O pin is config-
ured as analog, its digital input is disabled and the
corresponding PORTx register bit will read ‘0’. The
AD1PCFG register has a default value of ‘0x0000’;
therefore, all pins that share ANx functions are analog
(not digital) by default.
Not all port I/O pins are implemented on some devices,
therefore, the corresponding PORTx, LATx and TRISx
register bits will read as zeros.
12.1.1
CLR, SET AND INV REGISTERS
Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
12.1.4
DIGITAL OUTPUTS
Pins are configured as digital outputs by setting the
corresponding TRIS register bits = 0. When configured
as digital outputs, these pins are CMOS drivers or can
be configured as open-drain outputs by setting the cor-
responding bits in the ODCx Open-Drain Configuration
register.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
To set PORTC bit 0, write to the LATSET register:
The open-drain feature allows generation of outputs
higher than VDD (e.g., 5V) on any desired 5V tolerant
pins by using external pull-up resistors. The maximum
open-drain voltage allowed is the same as the
maximum VIH specification.
LATCSET = 0x0001;
To clear PORTC bit 0, write to the LATCLR register:
LATCCLR = 0x0001;
To toggle PORTC bit 0, write to the LATINV register:
See the “Pin Diagrams” section for the available pins
and their functionality.
LATCINV = 0x0001;
12.1.5
ANALOG OUTPUTS
Note:
Using a PORTxINV register to toggle a bit
is recommended because the operation is
performed in hardware atomically, using
fewer instructions, as compared to the
Certain pins can be configured as analog outputs, such
as the CVREF output voltage used by the comparator
module. Configuring the comparator reference module
to provide this output will present the analog output
voltage on the pin, independent of the TRIS register
setting for the corresponding pin.
traditional
read-modify-write
method
shown below:
PORTC ^= 0x0001;
DS61156C - page 122
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
This family of PIC32MX devices features one
synchronous/asynchronous 16-bit timer that can operate
as a free-running interval timer for various timing applica-
tions and counting external events. This timer can also
be used with the Low-Power Secondary Oscillator
(SOSC) for Real-Time Clock (RTC) applications. The
following modes are supported:
13.0 TIMER1
Note 1: This data sheet summarizes the features of
the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS61105) in the “PIC32MX Family
Reference Manual”, which is available
• Synchronous Internal Timer
• Synchronous Internal Gated Timer
• Synchronous External Timer
• Asynchronous External Timer
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to
4.0 “Memory Organization” in this data
sheet for device-specific register and bit
information.
13.1 Additional Supported Features
• Selectable Clock Prescaler
• Timer Operation during CPU Idle and Sleep mode
• Fast Bit Manipulation using CLR, SET and INV
registers
• Asynchronous mode can be used with the SOSC
to Function as a Real-Time Clock (RTC).
FIGURE 13-1:
TIMER1 BLOCK DIAGRAM(1)
PR1
Equal
16-Bit Comparator
TSYNC (T1CON<2>)
1
0
Sync
TMR1
Reset
0
T1IF
Event Flag
1
Q
Q
D
TGATE (T1CON<7>)
TCS (T1CON<1>)
ON (T1CON<15>)
TGATE (T1CON<7>)
SOSCO/T1CK
x1
Prescaler
Gate
Sync
SOSCEN
10
00
1, 8, 64, 256
SOSCI
PBCLK
2
TCKPS<1:0>
(T1CON<5:4>)
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in
Configuration Word, DEVCFG1.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 123
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 124
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Two 32-bit synchronous timers are available by
combining Timer2 with Timer3 and Timer4 with Timer5.
The 32-bit timers can operate in three modes:
14.0 TIMER2/3, TIMER4/5
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS61105) of the “PIC32MX Family
Reference Manual”, which is available
• Synchronous Internal 32-Bit Timer
• Synchronous Internal 32-Bit Gated Timer
• Synchronous External 32-Bit Timer
Note:
In this chapter, references to registers,
TxCON, TMRx and PRx, use ‘x’ to repre-
sent Timer2 through 5 in 16-bit modes. In
32-bit modes, ‘x’ represents Timer2 or 4;
‘y’ represents Timer3 or 5.
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to
4.0 “Memory Organization” in this data
sheet for device-specific register and bit
information.
14.1 Additional Supported Features
• Selectable Clock Prescaler
• Timers Operational during CPU Idle
• Time Base for Input Capture and Output Compare
modules (Timer2 and Timer3 only)
This family of PIC32MX devices features four
synchronous 16-bit timers (default) that can operate as
a free-running interval timer for various timing applica-
tions and counting external events. The following
modes are supported:
• ADC Event Trigger (Timer3 only)
• Fast Bit Manipulation using CLR, SET and INV
registers
• Synchronous Internal 16-Bit Timer
• Synchronous Internal 16-Bit Gated Timer
• Synchronous External 16-Bit Timer
FIGURE 14-1:
TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT)
Sync
TMRx
ADC Event
Trigger
(1)
Comparator x 16
PRx
Equal
Reset
0
1
TxIF
Event Flag
TGATE (TxCON<7>)
TCS (TxCON<1>)
ON (TxCON<15>)
Q
Q
D
TGATE (TxCON<7>)
(2)
TxCK
x1
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
Gate
Sync
10
PBCLK
00
3
TCKPS (TxCON<6:4>)
Note 1: ADC event trigger is available on Timer3 only.
2: TxCK pins are not available on 64-pin devices.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 125
PIC32MX5XX/6XX/7XX
FIGURE 14-2:
TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)(1)
Reset
TMRy
TMRx
Sync
LS Half Word
MS Half Word
ADC Event
(3)
Trigger
32-Bit Comparator
Equal
PRy
PRx
TyIF Event
Flag
0
1
Q
Q
D
TGATE (TxCON<7>)
TCS (TxCON<1>)
ON (TxCON<15>)
TGATE (TxCON<7>)
(2)
TxCK
x1
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
Gate
Sync
10
00
PBCLK
3
TCKPS (TxCON<6:4>)
Note 1: In this diagram, the use of “x’ in registers, TxCON, TMRx, PRx, TxCK, refers to either Timer2 or Timer4; the use of
‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5.
2: TxCK pins are not available on 64-pin devices.
3: ADC event trigger is available only on the Timer2/3 pair.
DS61156C-page 126
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
2. Capture timer value on every edge (rising and
falling)
15.0 INPUT CAPTURE
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 15. “Input
Capture” (DS61122) of the “PIC32MX
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
3. Capture timer value on every edge (rising and
falling), specified edge first.
4. Prescaler Capture Event modes
- Capture timer value on every 4th rising
edge of input at ICx pin
- Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base,
or two 16-bit timers (Timer2 and Timer3) together to
form a 32-bit timer. The selected timer can use either
an internal or external clock.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
Other operational features include:
• Device Wake-up from Capture Pin during CPU
Sleep and Idle modes
• Interrupt on Input Capture Event
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
• 4-Word FIFO Buffer for Capture Values
Interrupt Optionally Generated after 1, 2, 3 or 4
Buffer Locations are Filled
The input capture module captures the 16-bit or 32-bit
value of the selected Time Base registers when an
event occurs at the ICx pin. The following events cause
capture events:
• Input Capture can also be used to Provide
Additional Sources of External Interrupts
1. Simple Capture Event modes
- Capture timer value on every falling edge of
input at ICx pin
- Capture timer value on every rising edge of
input at ICx pin
FIGURE 15-1:
INPUT CAPTURE BLOCK DIAGRAM
ICx Input
Timer3 Timer2
ICTMR
0
1
C32
FIFO Control
ICxBUF<31:16>
ICxBUF<15:0>
Prescaler
1, 4, 16
Edge Detect
ICM<2:0>
FEDGE
ICM<2:0>
ICBNE
ICOV
Interrupt
Event
Generation
ICxCON
ICI<1:0>
Data Space Interface
Peripheral Data Bus
Interrupt
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 127
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 128
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
The Output Compare module (OCMP) is used to gen-
erate a single pulse or a train of pulses in response to
selected time base events. For all modes of operation,
the OCMP module compares the values stored in the
OCxR and/or the OCxRS registers to the value in the
selected timer. When a match occurs, the OCMP
module generates an event based on the selected
mode of operation.
16.0 OUTPUT COMPARE
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 16. “Output
Capture” (DS61111) in the “PIC32MX
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
The following are some of the key features:
• Multiple Output Compare Modules in a Device
• Programmable Interrupt Generation on Compare
Event
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
• Single and Dual Compare modes
• Single and Continuous Output Pulse Generation
• Pulse-Width Modulation (PWM) mode
• Hardware-Based PWM Fault Detection and
Automatic Output Disable
• Programmable Selection of 16-Bit or 32-Bit Time
Bases
• Can Operate from Either of Two Available 16-Bit
Time Bases or a Single 32-Bit Time Base
FIGURE 16-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit
OCxIF(1)
OCxRS(1)
Output
Logic
S
R
Q
OCxR(1)
OCx(1)
Output Enable
3
OCM<2:0>
Mode Select
OCFA or OCFB(2)
Comparator
0
0
OCTSEL
1
1
16
16
Period Match Signals
from Time Bases(3)
TMR Register Inputs
from Time Bases(3)
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels,
1 through 5.
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.
3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 129
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 130
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
The SPI module is a synchronous serial interface that
is useful for communicating with external peripherals
and other microcontroller devices. These peripheral
devices may be Serial EEPROMs, Shift registers, dis-
play drivers, A/D Converters, etc. The PIC32MX SPI
module is compatible with Motorola® SPI and SIOP
interfaces.
17.0 SERIAL PERIPHERAL
INTERFACE (SPI)
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
Section 23. “Serial Peripheral Interface
Following are some of the key features of this module:
• Master and Slave modes Support
• Four Different Clock Formats
(SPI)”
(DS61106) in the “PIC32MX
Family Reference Manual”, which is avail-
able from the Microchip web site
(www.microchip.com/PIC32).
• Enhanced Framed SPI Protocol Support
• User-Configurable 8-Bit, 16-Bit and 32-Bit Data
Width
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
• Separate SPI FIFO Buffers for Receive and
Transmit
- FIFO buffers act as 4/8/16-level deep FIFOs
based on 32/16/8-bit data width
• Programmable Interrupt Event on Every 8-Bit,
16-Bit and 32-Bit Data Transfer
• Operation during CPU Sleep and Idle mode
• Fast Bit Manipulation using CLR, SET and INV
Registers
FIGURE 17-1:
SPI MODULE BLOCK DIAGRAM
Internal
Data Bus
SPIxBUF
Read
Write
FIFOs Share Address SPIxBUF
SPIxRXB FIFO
SPIxTXB FIFO
Transmit
Receive
SPIxSR
SDIx
bit 0
SDOx
Shift
Control
Slave Select
and Frame
Sync Control
Clock
Control
Edge
Select
PBCLK
SSx/FSYNC
SCKx
Baud Rate
Generator
Enable Master Clock
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 131
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 132
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
The I2C module provides complete hardware support
for both Slave and Multi-Master modes of the I2C serial
communication standard. Figure 18-1 shows the I2C
module block diagram.
Each I2C module has a 2-pin interface: the SCLx pin is
clock and the SDAx pin is data.
Each I2C module offers the following key features:
• I2C Interface Supporting both Master and Slave
Operation
• I2C Slave mode Supports 7 and 10-Bit Address
• I2C Master mode Supports 7 and 10-Bit Address
• I2C Port allows Bidirectional Transfers between
Master and Slaves
• Serial Clock Synchronization for I2C Port can be
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control)
• I2C Supports Multi-Master Operation; Detects Bus
Collision and Arbitrates Accordingly
18.0 INTER-INTEGRATED CIRCUIT
2
(I C™)
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 24. “Inter-
Integrated Circuit” (DS61116) in the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
• Provides Support for Address Bit Masking
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 133
PIC32MX5XX/6XX/7XX
FIGURE 18-1:
I2C™ BLOCK DIAGRAM (X = 1 OR 2)
Internal
Data Bus
I2CxRCV
Read
Shift
Clock
SCLx
SDAx
I2CxRSR
LSB
Address Match
Match Detect
Write
Read
I2CxMSK
Write
Read
I2CxADD
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
I2CxSTAT
I2CxCON
Read
Write
Collision
Detect
Acknowledge
Generation
Read
Clock
Stretching
Write
Read
I2CxTRN
LSB
Shift Clock
Reload
Control
Write
Read
BRG Down Counter
PBCLK
I2CxBRG
DS61156C-page 134
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
The primary features of the UART module are:
19.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
• Full-Duplex, 8-Bit or 9-Bit Data Transmission
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop Bits
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 21. “Universal
Asynchronous Receiver Transmitter
• Hardware Auto-Baud Feature
• Hardware Flow Control Option
• Fully Integrated Baud Rate Generator (BRG) with
16-Bit Prescaler
• Baud Rates Ranging from 76 bps to 20 Mbps at
80 MHz
(UART)”
(DS61107) in the “PIC32MX
• 8-Level Deep First-In-First-Out (FIFO) Transmit
Data Buffer
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
• 8-Level Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error
Detection
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
• Support for Interrupt Only on Address Detect
(9th bit = 1)
• Separate Transmit and Receive Interrupts
• Loopback mode for Diagnostic Support
• LIN 1.2 Protocol Support
The UART module is one of the serial I/O modules
available in PIC32MX5XX/6XX/7XX family devices.
The UART is a full-duplex, asynchronous communica-
tion channel that communicates with peripheral
devices and personal computers through protocols,
such as RS-232, RS-485, LIN 1.2 and IrDA®. The
module also supports the hardware flow control option,
with UxCTS and UxRTS pins, and also includes an
IrDA encoder and decoder.
• IrDA Encoder and Decoder with 16x Baud Clock
Output for External IrDA Encoder/Decoder
Support
Figure 19-1 shows a simplified block diagram of the
UART.
FIGURE 19-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
BCLKx
UxRTS
UxCTS
Hardware Flow Control
UARTx Receiver
UxRX
UxTX
UARTx Transmitter
Note:
Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 135
PIC32MX5XX/6XX/7XX
Figure 19-2 and Figure 19-3 illustrate typical receive
and transmit timing for the UART module.
FIGURE 19-2:
UART RECEPTION
Char 1
Char 2-4
Char 11-13
Char 5-10
Read to
UxRXREG
Start
1
Stop
Start 2
Stop 4
Start 5
Stop 10 Start 11
Stop 13
UxRX
RIDLE
Cleared by
Software
OERR
Cleared by
Software
UxRXIF
URXISEL = 00
Cleared by
Software
UxRXIF
URXISEL = 01
UxRXIF
URXISEL = 10
FIGURE 19-3:
TRANSMISSION (8-BIT OR 9-BIT DATA)
8 into TxBUF
Write to
UxTXREG
TSR
Pull from Buffer
BCLK/16
(Shift Clock)
UxTX
Start
Bit 0
Bit 1
Stop
Start
Bit 1
UxTXIF
UTXISEL = 00
UxTXIF
UTXISEL = 01
UxTXIF
UTXISEL = 10
DS61156C-page 136
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Key features of the PMP module include:
20.0 PARALLEL MASTER PORT
(PMP)
• 8-Bit, 16-Bit Interface
• Up to 16 Programmable Address Lines
• Up to Two Chip Select Lines
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 13. “Parallel
Master Port (PMP)” (DS61128) in the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
• Programmable Strobe Options
- Individual read and write strobes, or
- Read/write strobe with enable strobe
• Address Auto-Increment/Auto-Decrement
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Parallel Slave Port Support
- Legacy addressable
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
- Address support
- 4-byte deep auto-incrementing buffer
• Programmable Wait States
• Operates during CPU Sleep and Idle modes
• Fast Bit Manipulation using CLR, SET and INV
Registers
The PMP is a parallel 8-bit/16-bit input/output module
specifically designed to communicate with a wide
variety of parallel devices, such as communications
peripherals, LCDs, external memory devices and
microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP module is
highly configurable.
• Freeze Option for In-Circuit Debugging
Note:
On 64-pin devices, data pins, PMD<15:8>,
are not available.
FIGURE 20-1:
PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
Address Bus
Data Bus
Control Lines
PMA<0>
PMALL
PIC32MX5XX/6XX/7XX
Parallel
Master Port
PMA<1>
PMALH
Flash
EEPROM
SRAM
Up to 16-Bit Address
PMA<13:2>
PMA<14>
PMCS1
PMA<15>
PMCS2
PMRD
PMRD/PMWR
FIFO
Buffer
PMWR
PMENB
Microcontroller
LCD
PMD<7:0>
PMD<15:8>(1)
16/8-Bit Data (with or without multiplexed addressing)
Note 1: On 64-pin devices, data pins, PMD<15:8>, are not available in 16-Bit Master modes.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 137
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 138
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Following are some of the key features of this module:
21.0 REAL-TIME CLOCK AND
CALENDAR (RTCC)
• Time: Hours, Minutes and Seconds
• 24-Hour Format (Military Time)
• Visibility of One Half Second Period
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 29. “Real-Time
• Provides Calendar: Weekday, Date, Month and
Year
• Alarm Intervals are Configurable for Half of a
Second, One Second, 10 Seconds, One Minute,
10 Minutes, One Hour, One Day, One Week, One
Month and One Year
Clock
and
Calendar
(RTCC)”
(DS61125) in the “PIC32MX Family
Reference Manual”, which is available
• Alarm Repeat with Decrementing Counter
• Alarm with Indefinite Repeat: Chime
• Year Range: 2000 to 2099
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
• Leap Year Correction
• BCD Format for Smaller Firmware Overhead
• Optimized for Long-Term Battery Operation
• Fractional Second Synchronization
• User Calibration of the Clock Crystal Frequency
with Auto-Adjust
The PIC32MX RTCC module is intended for applica-
tions in which accurate time must be maintained for
extended periods of time with minimal or no CPU
• Calibration Range: 0.66 Seconds Error per
Month
• Calibrates up to 260 ppm of Crystal Error
intervention.
Low-power
optimization
provides
• Requirements: External 32.768 kHz Clock Crystal
extended battery lifetime while keeping track of time.
• Alarm Pulse or Seconds Clock Output on
RTCC Pin
FIGURE 21-1:
RTCC BLOCK DIAGRAM
32.768 kHz Input
from Secondary
Oscillator (SOSC)
RTCC Prescalers
0.5s
YEAR, MTH, DAY
RTCVAL
WKDAY
RTCC Timer
Alarm
HR, MIN, SEC
Event
Comparator
MTH, DAY
WKDAY
Compare Registers
with Masks
ALRMVAL
HR, MIN, SEC
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
Seconds Pulse
RTCC Pin
RTCOE
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 139
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 140
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
• One Unipolar, Differential Sample and Hold
Amplifier (SHA)
22.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (ADC)
• Automatic Channel Scan mode
• Selectable Conversion Trigger Source
• 16-word Conversion Result Buffer
• Selectable Buffer Fill modes
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 17. “10-Bit
Analog-to-Digital Converter (ADC)”
(DS61104) in the “PIC32MX Family
Reference Manual”, which is available
• Eight Conversion Result Format Options
• Operation during CPU Sleep and Idle modes
A block diagram of the 10-bit ADC is shown in
Figure 22-1. The 10-bit ADC has up to 16 analog input
pins, designated AN0-AN15. In addition, there are two
analog input pins for external voltage reference
connections. These voltage reference inputs may be
shared with other analog input pins and may be
common to other analog module references.
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The analog inputs are connected through two multi-
plexers (MUXs) to one SHA. The analog input MUXs
can be switched between two sets of analog inputs
between conversions. Unipolar differential conversions
are possible on all channels, other than the pin used as
the reference, using a reference input pin (see
Figure 22-1).
The PIC32MX5XX/6XX/7XX 10-bit Analog-to-Digital
(A/D) Converter (or ADC) includes the following
features:
The Analog Input Scan mode sequentially converts
user-specified channels. A control register specifies
which analog input channels will be included in the
scanning sequence.
• Successive Approximation Register (SAR)
Conversion
• Up to 1 Msps Conversion Speed
• Up to 16 Analog Input Pins
The 10-bit ADC is connected to a 16-word result buffer.
Each 10-bit result is converted to one of eight 32-bit
output formats when it is read from the result buffer.
• External Voltage Reference Input Pins
FIGURE 22-1:
ADC1 MODULE BLOCK DIAGRAM
VREF+(1)
VREF-(1)
AVDD
AVSS
VCFG<2:0>
AN0
ADC1BUF0
ADC1BUF1
ADC1BUF2
AN15
VREFH
VREFL
S/H
Channel
Scan
+
-
CH0SB<4:0>
SAR ADC
CH0SA<4:0>
CSCNA
AN1
ADC1BUFE
ADC1BUFF
VREFL
CH0NA CH0NB
Alternate
Input Selection
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 141
PIC32MX5XX/6XX/7XX
FIGURE 22-2:
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
ADRC
FRC
Div 2
0
1
TAD
ADCS<7:0>
8
ADC Conversion
Clock Multiplier
TPB
2, 4,..., 512
DS61156C-page 142
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
• Message Reception and Transmission:
- 32 message FIFOs
23.0 CONTROLLER AREA
NETWORK (CAN)
- Each FIFO can have up to 32 messages for a
total of 1024 messages
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 34. “Controller
Area Network (CAN)” in the “PIC32MX
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
- FIFO can be a transmit message FIFO or a
receive message FIFO
- User-defined priority levels for message
FIFOs used for transmission
- 32 acceptance filters for message filtering
- Four acceptance filter mask registers for
message filtering
- Automatic response to remote transmit request
- DeviceNet™ addressing support
• Additional Features:
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
- Loopback, Listen All Messages and Listen
Only modes for self-test, system diagnostics
and bus monitoring
- Low-power operating modes
- CAN module is a bus master on the
PIC32MX system bus
The Controller Area Network (CAN) module supports
the following key features:
- Use of DMA is not required
- Dedicated time-stamp timer
- Dedicated DMA channels
• Standards Compliance:
- Full CAN 2.0B compliance
- Programmable bit rate up to 1 Mbps
- Data Only Message Reception mode
Figure 23-1 illustrates the general structure of the CAN
module.
FIGURE 23-1:
PIC32MX CAN MODULE BLOCK DIAGRAM
CxTX
32 Filters
4 Masks
CPU
CxRX
CAN Module
System Bus
Message
Buffer Size
2 or 4 Words
System RAM
Message Buffer 31
Message Buffer 31
Message Buffer 31
Message Buffer 1
Message Buffer 0
Message Buffer 1
Message Buffer 0
Message Buffer 1
Message Buffer 0
FIFO0
FIFO1
FIFO31
CAN Message FIFO (up to 32 FIFOs)
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 143
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 144
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Following are some of the key features of this module:
24.0
ETHERNET CONTROLLER
• Supports 10/100 Mbps Data Transfer Rates
• Supports Full-Duplex and Half-Duplex Operation
• Supports RMII and MII PHY Interface
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 35. “Ethernet
Controller” in the “PIC32MX Family
Reference Manual”, which is available
• Supports MIIM PHY Management Interface
• Supports both Manual and Automatic Flow Control
• RAM Descriptor-Based DMA Operation for Both
Receive and Transmit Path
• Fully Configurable Interrupts
• Configurable Receive Packet Filtering
- CRC Check
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
- 64-Byte Pattern Match
- Broadcast, Multicast and Unicast packets
- Magic Packet™
- 64-Bit Hash Table
- Runt Packet
• Supports Packet Payload Checksum Calculation
• Supports Various Hardware Statistics Counters
The Ethernet controller is a bus master module that
interfaces with an off-chip Physical Layer (PHY) to
implement a complete Ethernet node in a system.
Figure 24-1 shows a block diagram of the Ethernet
controller.
FIGURE 24-1:
ETHERNET CONTROLLER BLOCK DIAGRAM
TX DMA
TX BM
TX Bus
Master
TX Function
TX Flow Control
MII/RMII
IF
RX Flow
Control
RX DMA
RX BM
External
MAC
PHY
RX Bus
Master
RX Filter
RX Function
Checksum
MIIM
IF
MAC Control
and
DMA
Control
Registers
Configuration
Ethernet DMA
Host IF
Registers
Ethernet Controller
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 145
PIC32MX5XX/6XX/7XX
Table 24-1, Table 24-2, Table 24-3 and Table 24-4
show four interfaces and the associated pins that can
be used with the Ethernet Controller.
TABLE 24-3: MII MODE ALTERNATE
INTERFACE SIGNALS
(FMIIEN = 1, FETHIO = 0)(1)
TABLE 24-1: MII MODE DEFAULT
INTERFACE SIGNALS
Pin Name
AEMDC
Description
Management Clock
(FMIIEN = 1, FETHIO = 1)
AEMDIO
AETXCLK
AETXEN
AETXD0
AETXD1
AETXD2
AETXD3
AETXERR
AERXCLK
AERXDV
AERXD0
AERXD1
AERXD2
AERXD3
AERXERR
AECRS
Management IO
Transmit Clock
Transmit Enable
Transmit Data
Transmit Data
Transmit Data
Transmit Data
Transmit Error
Receive Clock
Receive Data Valid
Receive Data
Receive Data
Receive Data
Receive Data
Receive Error
Carrier Sense
Collision Indication
Pin Name
EMDC
Description
Management Clock
EMDIO
ETXCLK
ETXEN
ETXD0
ETXD1
ETXD2
ETXD3
ETXERR
ERXCLK
ERXDV
ERXD0
ERXD1
ERXD2
ERXD3
ERXERR
ECRS
Management IO
Transmit Clock
Transmit Enable
Transmit Data
Transmit Data
Transmit Data
Transmit Data
Transmit Error
Receive Clock
Receive Data Valid
Receive Data
Receive Data
Receive Data
Receive Data
Receive Error
Carrier Sense
Collision Indication
AECOL
Note 1: MII Alternate Interface is not available on
64-pin devices.
ECOL
TABLE 24-4: RMII MODE ALTERNATE
INTERFACE SIGNALS
TABLE 24-2: RMII MODE DEFAULT
INTERFACE SIGNALS
(FMIIEN = 0, FETHIO = 0)
(FMIIEN = 0, FETHIO = 1)
Pin Name
AEMDC
Description
Management Clock
Pin Name
EMDC
Description
Management Clock
AEMDIO
AETXEN
AETXD0
Management IO
Transmit Enable
Transmit Data
EMDIO
Management IO
Transmit Enable
Transmit Data
ETXEN
ETXD0
AETXD1
Transmit Data
ETXD1
Transmit Data
AEREFCLK
AECRSDV
AERXD0
AERXD1
AERXERR
Reference Clock
Carrier Sense – Receive Data Valid
Receive Data
EREFCLK
ECRSDV
ERXDV
ERXD0
ERXD1
ERXERR
Reference Clock
Carrier Sense – Receive Data Valid
Receive Data Valid
Receive Data
Receive Data
Receive Error
Receive Data
Receive Error
DS61156C-page 146
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
The PIC32MX5XX/6XX/7XX analog comparator
module contains two comparators that can be
configured in a variety of ways.
25.0
COMPARATOR
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this
data sheet, refer to Section 19.
Following are some of the key features of this module:
• Selectable Inputs Available Include:
- Analog inputs multiplexed with I/O pins
- On-chip internal absolute Voltage Reference
(IVREF)
“Comparator”
(DS61110) in the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
- Comparator Voltage Reference (CVREF)
• Outputs can be Inverted
• Selectable Interrupt Generation
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
A block diagram of the comparator module is shown in
Figure 25-1.
FIGURE 25-1:
COMPARATOR BLOCK DIAGRAM
Comparator 1
COUT (CM1CON)
C1OUT (CMSTAT)
CREF
ON
CPOL
(1)
C1IN+
(2)
CVREF
C1OUT
CCH<1:0>
C1
C1IN-
C1IN+
C2IN+
COE
(2)
IVREF
Comparator 2
COUT (CM2CON)
C2OUT (CMSTAT)
CREF
ON
CPOL
C2IN+
(2)
CVREF
C2OUT
CCH<1:0>
C2
C2IN-
COE
C2IN+
C1IN+
(2)
IVREF
Note 1: On devices with a USB module, and when the module is enabled, this pin is controlled by the USB module,
and therefore, is not available as a comparator input.
2: Internally connected.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 147
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 148
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
The CVREF module is a 16-tap, resistor ladder network
that provides a selectable reference voltage. Although
its primary purpose is to provide a reference for the
analog comparators, it also may be used independently
of them.
26.0 COMPARATOR VOLTAGE
REFERENCE (CVREF)
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
Section 20. “Comparator Voltage
A block diagram of the module is shown in Figure 26-1.
The resistor ladder is segmented to provide two ranges
of voltage reference values and has a power-down
function to conserve power when the reference is not
being used. The module’s supply reference can be pro-
vided from either device VDD/VSS or an external
voltage reference. The CVREF output is available for
the comparators and typically available for pin output.
Reference (CVREF)”
(DS61109) in the
“PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The comparator voltage reference has the following
features:
• High and low range selection
• Sixteen output levels available for each range
• Internally connected to comparators to conserve
device pins
• Output can be connected to a pin
FIGURE 26-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
CVRSS = 0
VREF+
AVDD
8R
CVR<3:0>
R
CVREN
CVREF
R
R
R
16 Steps
CVREFOUT
CVRCON<CVROE>
R
R
R
CVRR
VREF-
AVSS
8R
CVRSS = 1
CVRSS = 0
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 149
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 150
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
• SOSC Idle mode: the system clock is derived from
the SOSC.
27.0 POWER-SAVING FEATURES
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
Section 10. “Power-Saving Features”
(DS61130) in the “PIC32MX Family
Reference Manual”, which is available
Peripherals continue to operate, but can
optionally be individually disabled.
• LPRC Idle mode: the system clock is derived from
the LPRC.
Peripherals continue to operate, but can option-
ally be individually disabled. This is the lowest
power mode for the device with a clock running.
• Sleep mode: the CPU, the system clock source
and any peripherals that operate from the system
clock source are Halted.
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
Some peripherals can operate in Sleep using
specific clock sources. This is the lowest power
mode for the device.
27.3 Power-Saving Operation
Peripherals and the CPU can be Halted or disabled to
further reduce power consumption.
This section describes power-saving features for the
PIC32MX5XX/6XX/7XX. The PIC32MX devices offer a
total of nine methods and modes, organized into two
categories, that allow the user to balance power
consumption with device performance. In all of the
methods and modes described in this section, power
saving is controlled by software.
27.3.1
SLEEP MODE
Sleep mode has the lowest power consumption of the
device power-saving operating modes. The CPU and
most peripherals are Halted. Select peripherals can
continue to operate in Sleep mode and can be used to
wake the device from Sleep. See the individual periph-
eral module sections for descriptions of behavior in
Sleep.
27.1 Power Saving with CPU Running
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency, lower-
ing the PBCLK and by individually disabling modules.
These methods are grouped into the following
categories:
Sleep mode includes the following characteristics:
• The CPU is Halted.
• The system clock source is typically shut down.
See Section 27.3.3 “Peripheral Bus Scaling
Method” for specific information.
• FRC Run mode: the CPU is clocked from the FRC
clock source with or without postscalers.
• There can be a wake-up delay based on the
oscillator selection.
• LPRC Run mode: the CPU is clocked from the
LPRC clock source.
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode.
• SOSC Run mode: the CPU is clocked from the
SOSC clock source.
• The BOR circuit, if enabled, remains operative
during Sleep mode.
In addition, the Peripheral Bus Scaling mode is available
where peripherals are clocked at the programmable
fraction of the CPU clock (SYSCLK).
• The WDT, if enabled, is not automatically cleared
prior to entering Sleep mode.
• Some peripherals can continue to operate at
limited functionality in Sleep mode. These periph-
erals include I/O pins that detect a change in the
input signal, WDT, ADC, UART and peripherals
that use an external clock input or the internal
LPRC oscillator (e.g., RTCC, Timer1 and Input
Capture).
27.2 CPU Halted Methods
The device supports two power-saving modes, Sleep
and Idle, both of which Halt the clock to the CPU. These
modes operate with all clock sources, as listed below:
• POSC Idle mode: the system clock is derived from
the POSC. The system clock source continues to
operate.
• I/O pins continue to sink or source current in the
same manner as they do when the device is not in
Sleep.
Peripherals continue to operate, but can
optionally be individually disabled.
• The USB module can override the disabling of the
Posc or FRC. Refer to the USB section for
specific details.
• FRC Idle mode: the system clock is derived from
the FRC with or without postscalers.
• Modules can be individually disabled by software
prior to entering Sleep in order to further reduce
consumption.
Peripherals continue to operate, but can
optionally be individually disabled.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 151
PIC32MX5XX/6XX/7XX
The processor will exit, or ‘wake-up’, from Sleep on one
of the following events:
The processor will wake or exit from Idle mode on the
following events:
• On any interrupt from an enabled source that is
operating in Sleep. The interrupt priority must be
greater than the current CPU priority.
• On any interrupt event for which the interrupt
source is enabled. The priority of the interrupt
event must be greater than the current priority of
the CPU. If the priority of the interrupt event is
lower than or equal to current priority of the CPU,
the CPU will remain Halted and the device will
remain in Idle mode.
• On any form of device Reset.
• On a WDT time-out.
If the interrupt priority is lower than or equal to the
current priority, the CPU will remain Halted, but the
PBCLK will start running and the device will enter into
Idle mode.
• On any form of device Reset
• On a WDT time-out interrupt
27.3.3
PERIPHERAL BUS SCALING
METHOD
27.3.2
IDLE MODE
In Idle mode, the CPU is Halted but the System Clock
(SYSCLK) source is still enabled. This allows peripher-
als to continue operation when the CPU is Halted.
Peripherals can be individually configured to Halt when
entering Idle by setting their respective SIDL bit.
Latency, when exiting Idle mode, is very low due to the
CPU oscillator source remaining active.
Most of the peripherals on the device are clocked using
the PBCLK. The peripheral bus can be scaled relative to
the SYSCLK to minimize the dynamic power consumed
by the peripherals. The PBCLK divisor is controlled by
PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to
PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals
using PBCLK are affected when the divisor is changed.
Peripherals, such as the interrupt controller, DMA, bus
matrix and prefetch cache, are clocked directly from
SYSCLK. As a result, they are not affected by PBCLK
divisor changes.
Notes: Changing the PBCLK divider ratio
requires recalculation of peripheral timing.
For example, assume the UART is config-
ured for 9600 baud with a PB clock ratio of
1:1 and a POSC of 8 MHz. When the PB
clock divisor of 1:2 is used, the input
frequency to the baud clock is cut in half;
therefore, the baud rate is reduced to 1/2
its former value. Due to numeric truncation
in calculations (such as the baud rate divi-
sor), the actual baud rate may be a tiny
percentage different than expected. For
this reason, any timing calculation
required for a peripheral should be per-
formed with the new PB clock frequency
instead of scaling the previous value
based on a change in the PB divisor ratio.
Most of the peripherals on the device are clocked using
the PBCLK. The peripheral bus can be scaled relative to
the SYSCLK to minimize the dynamic power consumed
by the peripherals. The PBCLK divisor is controlled by
PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to
PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals
using PBCLK are affected when the divisor is changed.
Peripherals such as USB, interrupt controller, DMA, bus
matrix and prefetch cache are clocked directly from
SYSCLK. As a result, they are not affected by PBCLK
divisor changes
Changing the PBCLK divisor affects:
• The CPU to peripheral access latency. The CPU
has to wait for next PBCLK edge for a read to
complete. In 1:8 mode, this results in a latency of
one to seven SYSCLKs.
Oscillator start-up and PLL lock delays
are applied when switching to a clock
source that was disabled and that uses a
crystal and/or the PLL. For example,
assume the clock source is switched from
POSC to LPRC just prior to entering Sleep
in order to save power. No oscillator start-
up delay would be applied when exiting
Idle. However, when switching back to
POSC, the appropriate PLL and or oscilla-
tor start-up/lock delays would be applied.
• The power consumption of the peripherals. Power
consumption is directly proportional to the fre-
quency at which the peripherals are clocked. The
greater the divisor, the lower the power consumed
by the peripherals.
To minimize dynamic power, the PB divisor should be
chosen to run the peripherals at the lowest frequency
that provides acceptable system performance. When
selecting a PBCLK divider, peripheral clock require-
ments, such as baud rate accuracy, should be taken
into account. For example, the UART peripheral may
not be able to achieve all baud rate values at some
PBCLK divider depending on the SYSCLK value.
The device enters Idle mode when the SLPEN
(OSCCON<4>) bit is clear and a WAIT instruction is
executed.
DS61156C-page 152
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
PIC32MX5XX/6XX/7XX devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
28.0 SPECIAL FEATURES
Note:
This data sheet summarizes the features of
the PIC32MX5XX/6XX/7XX family family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
the related section in the “PIC32MX Family
Reference Manual” (DS61132), which is
available from the Microchip web site
(www.microchip.com/PIC32).
• Flexible Device Configuration
• Watchdog Timer
• JTAG Interface
• In-Circuit Serial Programming™ (ICSP™)
28.1 Configuration Bits
The Configuration bits can be programmed to select
various device configurations.
REGISTER 28-1: DEVCFG0: DEVICE CONFIGURATION WORD 0
r-0
—
r-1
—
r-1
—
R/P-1
CP
r-1
—
r-1
—
r-1
—
R/P-1
BWP
bit 31
bit 24
r-1
—
r-1
—
r-1
—
r-1
—
R/P-1
R/P-1
R/P-1
R/P-1
PWP<7:4>
bit 23
bit 16
R/P-1
bit 15
R/P-1
R/P-1
R/P-1
r-1
—
r-1
—
r-1
—
r-1
—
PWP<3:0>
bit 8
r-1
—
r-1
—
r-1
—
r-1
—
R/P-1
r-1
—
R/P-1
R/P-1
ICESEL
DEBUG<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
P = Programmable bit
r = Reserved bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31
Reserved: Write ‘0’
Reserved: Write ‘1’
CP: Code-Protect bit
bit 30-29
bit 28
Prevents boot and program Flash memory from being read or modified by an external
programming device.
1= Protection is disabled
0= Protection is enabled
bit 27-25
bit 24
Reserved: Write ‘1’
BWP: Boot Flash Write-Protect bit
Prevents boot Flash memory from being modified during code execution.
1= Boot Flash is writable
0= Boot Flash is not writable
bit 23-20
Reserved: Write ‘1’
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 153
PIC32MX5XX/6XX/7XX
REGISTER 28-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)
bit 19-12
PWP<7:0>: Program Flash Write-Protect bits
Prevents selected program Flash memory pages from being modified during code execution.
The PWP bits represent the one’s compliment of the number of write-protected program Flash
memory pages.
11111111= Disabled
11111110= 0xBD00_0FFF
11111101= 0xBD00_1FFF
11111100= 0xBD00_2FFF
11111011= 0xBD00_3FFF
11111010= 0xBD00_4FFF
11111001= 0xBD00_5FFF
11111000= 0xBD00_6FFF
11110111= 0xBD00_7FFF
11110110= 0xBD00_8FFF
11110101= 0xBD00_9FFF
11110100= 0xBD00_AFFF
11110011= 0xBD00_BFFF
11110010= 0xBD00_CFFF
11110001= 0xBD00_DFFF
11110000= 0xBD00_EFFF
11101111= 0xBD00_FFFF
•
•
•
01111111= 0xBD07_FFFF
bit 11-4
bit 3
Reserved: Write ‘1’
ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit
1= PGEC2/PGED2 pair is used
0= PGEC1/PGED1 pair is used
bit 2
Reserved: Write ‘1’
bit 1-0
DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)
11= Debugger is disabled
10= Debugger is enabled
01= Reserved (same as ‘11’ setting)
00= Reserved (same as ‘11’ setting)
DS61156C-page 154
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 28-2: DEVCFG1: DEVICE CONFIGURATION WORD 1
r-1
—
r-1
—
r-1
—
r-1
—
r-1
—
r-1
—
r-1
—
r-1
—
bit 31
bit 24
R/P-1
r-1
—
r-1
—
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
FWDTEN
WDTPS<4:0>
bit 23
bit 16
R/P-1
R/P-1
R/P-1
R/P-1
r-1
—
R/P-1
FCKSM<1:0>
FPBDIV<1:0>
OSCIOFNC
POSCMOD<1:0>
bit 15
bit 8
R/P-1
IESO
r-1
—
R/P-1
r-1
—
r-1
—
R/P-1
R/P-1
R/P-1
bit 0
FSOSCEN
FNOSC<2:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
P = Programmable bit
r = Reserved bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31-24
bit 23
Reserved: Write ‘1’
FWDTEN: Watchdog Timer Enable bit
1= The WDT is enabled and cannot be disabled by software
0= The WDT is not enabled; it can be enabled in software
bit 22-21
bit 20-16
Reserved: Write ‘1’
WDTPS<4:0>: Watchdog Timer Postscale Select bits
10100= 1:1048576
10011= 1:524288
10010= 1:262144
10001= 1:131072
10000= 1:65536
01111= 1:32768
01110= 1:16384
01101= 1:8192
01100= 1:4096
01011= 1:2048
01010= 1:1024
01001= 1:512
01000= 1:256
00111= 1:128
00110= 1:64
00101= 1:32
00100= 1:16
00011= 1:8
00010= 1:4
00001= 1:2
00000= 1:1
All other combinations not shown result in operation = 10100
Note 1: Do not disable POSC (POSCMOD = 11) when using this oscillator source.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 155
PIC32MX5XX/6XX/7XX
REGISTER 28-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED)
bit 15-14
FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits
1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled
bit 13-12
FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits
11= PBCLK is SYSCLK divided by 8
10= PBCLK is SYSCLK divided by 4
01= PBCLK is SYSCLK divided by 2
00= PBCLK is SYSCLK divided by 1
bit 11
bit 10
Reserved: Write ‘1’
OSCIOFNC: CLKO Enable Configuration bit
1= CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for
the External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11or 00)
0= CLKO output disabled
bit 9-8
bit 7
POSCMOD<1:0>: Primary Oscillator Configuration bits
11= Primary oscillator disabled
10= HS Oscillator mode selected
01= XT Oscillator mode selected
00= External Clock mode selected
IESO: Internal External Switchover bit
1= Internal External Switchover mode is enabled (Two-Speed Start-up is enabled)
0= Internal External Switchover mode is disabled (Two-Speed Start-up is disabled)
bit 6
bit 5
Reserved: Write ‘1’
FSOSCEN: Secondary Oscillator Enable bit
1= Enable Secondary Oscillator
0= Disable Secondary Oscillator
bit 4-3
bit 2-0
Reserved: Write ‘1’
FNOSC<2:0>: Oscillator Selection bits
000= Fast RC Oscillator (FRC)
001= Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)
010= Primary Oscillator (XT, HS, EC)(1)
011= Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL)
100= Secondary Oscillator (SOSC)
101= Low-Power RC Oscillator (LPRC)
110= FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler
111= Fast RC Oscillator with divide-by-N (FRCDIV)
Note 1: Do not disable POSC (POSCMOD = 11) when using this oscillator source.
DS61156C-page 156
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 28-3: DEVCFG2: DEVICE CONFIGURATION WORD 2
r-1
—
r-1
—
r-1
—
r-1
—
r-1
—
r-1
—
r-1
—
r-1
—
bit 31
bit 23
bit 24
R/P-1
bit 16
r-1
—
r-1
—
r-1
—
r-1
—
r-1
—
R/P-1
R/P-1
R/P-1
R/P-1
FPLLODIV<2:0>
R/P-1
r-1
—
r-1
—
r-1
—
r-1
—
R/P-1
R/P-1
bit 8
R/P-1
UPLLEN
UPLLIDIV<2:0>
bit 15
r-1
—
R/P-1
R/P-1
R/P-1
r-1
—
R/P-1
FPLLMULT<2:0>
FPLLIDIV<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
P = Programmable bit
r = Reserved bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31-19
bit 18-16
Reserved: Write ‘1’
FPLLODIV<2:0>: Default Postscaler for PLL bits
111= PLL output divided by 256
110= PLL output divided by 64
101= PLL output divided by 32
100= PLL output divided by 16
011= PLL output divided by 8
010= PLL output divided by 4
001= PLL output divided by 2
000= PLL output divided by 1
bit 15
UPLLEN: USB PLL Enable bit
1= Enable USB PLL
0= Disable and bypass USB PLL
bit 14-11
bit 10-8
Reserved: Write ‘1’
UPLLIDIV<2:0>: PLL Input Divider bits
111= 12x divider
110= 10x divider
101= 6x divider
100= 5x divider
011= 4x divider
010= 3x divider
010= 3x divider
001= 2x divider
000= 1x divider
bit 7
Reserved: Write ‘1’
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 157
PIC32MX5XX/6XX/7XX
REGISTER 28-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED)
bit 6-4
FPLLMULT<2:0>: PLL Multiplier bits
111= 24x multiplier
110= 21x multiplier
101= 20x multiplier
100= 19x multiplier
011= 18x multiplier
010= 17x multiplier
001= 16x multiplier
000= 15x multiplier
bit 3
Reserved: Write ‘1’
bit 2-0
FPLLIDIV<2:0>: PLL Input Divider bits
111= 12x divider
110= 10x divider
101= 6x divider
100= 5x divider
011= 4x divider
010= 3x divider
001= 2x divider
000= 1x divider
DS61156C-page 158
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 28-4: DEVCFG3: DEVICE CONFIGURATION WORD 3
R/P-1
FVBUSONIO
bit 31
R/P-1
r-1
—
r-1
—
r-1
—
R/P-1
R/P-1
R/P-1
FUSBIDIO
FCANIO
FETHIO
FMIIEN
bit 24
r-1
—
r-1
—
r-1
—
r-1
—
r-1
—
R/P-1
R/P-x
R/P-x
R/P-1
R/P-1
FSRSSEL<2:0>
bit 23
bit 16
R/P-x
bit 8
R/P-x
bit 15
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
R/P-x
USERID<15:8>
R/P-x
R/P-x
R/P-x
R/P-x
bit 0
USERID<7:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
P = Programmable bit
r = Reserved bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31
bit 30
FVBUSONIO: USB VBUS_ON Selection bit
1= VBUSON pin is controlled by the USB module
0= VBUSON pin is controlled by the port function
FUSBIDIO: USB USBID Selection bit
1= USBID pin is controlled by the USB module
0= USBID pin is controlled by the port function
bit 29-27
bit 26
Reserved: Write ‘1’
FCANIO: CAN I/O Pin Selection bit
1= Default CAN I/O Pins
0= Alternate CAN I/O Pins
bit 25
bit 24
FETHIO: Ethernet I/O Pin Selection bit
1= Default Ethernet I/O Pins
0= Alternate Ethernet I/O Pins
FMIIEN: Ethernet MII Enable bit
1= MII is enabled
0= RMII is enabled
bit 23-19
bit 18-16
Reserved: Write ‘1’
FSRSSEL<2:0>: SRS Select bits
111= Assign Interrupt Priority 7 to a shadow register set
110= Assign Interrupt Priority 6 to a shadow register set
•
•
•
001= Assign Interrupt Priority 1 to a shadow register set
000= All interrupt priorities are assigned to a shadow register set
bit 15-0
USERID<15:0>: This is a 16-bit value that is user-defined and is readable via ICSP™ and JTAG
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 159
PIC32MX5XX/6XX/7XX
REGISTER 28-5: DEVID: DEVICE AND REVISION ID REGISTER
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
VER<3:0>(1)
DEVID<27:24>(1)
bit 31
bit 23
bit 15
bit 7
bit 24
bit 16
bit 8
R
R
R
R
R
R
R
R
R
R
R
DEVID<23:16>(1)
R
R
DEVID<15:8>(1)
R
R
DEVID<7:0>(1)
bit 0
Legend:
R = Readable bit
W = Writable bit
P = Programmable bit
r = Reserved bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31-28
bit 27-0
VER<3:0>: Revision Identifier bits(1)
DEVID<27:0>: Device ID(1)
Note 1: See the “PIC32MX Flash Programming Specification” (DS61145) for a list of Revision and Device ID values.
DS61156C-page 160
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
The following are some of the key features of the WDT
module:
28.2 Watchdog Timer (WDT)
This section describes the operation of the WDT and
Power-up Timer of the PIC32MX5XX/6XX/7XX.
• Configuration or software controlled
• User-configurable time-out period
• Can wake the device from Sleep or Idle
The WDT, when enabled, operates from the internal
Low-Power Oscillator (LPRC) clock source and can be
used to detect system software malfunctions by reset-
ting the device if the WDT is not cleared periodically in
software. Various WDT time-out periods can be
selected using the WDT postscaler. The WDT can also
be used to wake the device from Sleep or Idle mode.
FIGURE 28-1:
WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM
PWRT Enable
WDT Enable
LPRC
Control
PWRT Enable
1:64 Output
PWRT
LPRC
Oscillator
1
Clock
25-Bit Counter
25
WDTCLR = 1
WDT Enable
Wake
Device Reset
0
1
WDT Counter Reset
WDT Enable
Reset Event
NMI (Wake-up)
Power Save
Decoder
FWDTPS<4:0>(DEVCFG1<20:16>)
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 161
PIC32MX5XX/6XX/7XX
28.3.3
POWER-UP REQUIREMENTS
28.3 On-Chip Voltage Regulator
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, VDDCORE must
never exceed VDD by 0.3 volts.
All PIC32MX5XX/6XX/7XX devices’ core and digital
logic are designed to operate at a nominal 1.8V. To
simplify system designs, most devices in the
PIC32MX5XX/6XX/7XX family incorporate an on-chip
regulator providing the required core logic voltage from
VDD.
A low-ESR capacitor (such as tantalum) must be con-
nected to the VCAP/VDDCORE pin (see Figure 28-2).
This helps to maintain the stability of the regulator.
The recommended value for the filter capacitor is
provided in Section 31.1 “DC Characteristics”.
FIGURE 28-2:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
(1)
3.3V
PIC32MX
Note:
It is important that the low-ESR capacitor
is placed as close as possible to the
VCAP/VDDCORE pin.
VDD
VCAP/VDDCORE
VSS
(2)
28.3.1
ON-CHIP REGULATOR AND POR
CEFC
(10 F typ)
It takes a fixed delay for the on-chip regulator to generate
an output. During this time, designated as TPU, code exe-
cution is disabled. TPU is applied every time the device
resumes operation after any power-down, including
Sleep mode.
Note 1: These are typical operating voltages. Refer
to Section 31.1 “DC Characteristics” for
the full operating ranges of VDD and
VDDCORE.
If the regulator is disabled, a separate Power-up Timer
(PWRT) is automatically enabled. The PWRT adds a
fixed delay of TPWRT at device start-up. See
Section 31.0 “Electrical Characteristics” for more
information on TPU AND TPWRT.
2: It is important that the low-ESR capacitor
is placed as close as possible to the
VCAP/VDDCORE pin.
28.3.2
ON-CHIP REGULATOR AND BOR
PIC32MX5XX/6XX/7XX devices also have a simple
brown-out capability. If the voltage supplied to the reg-
ulator is inadequate to maintain a regulated level, the
regulator Reset circuitry will generate a Brown-out
Reset. This event is captured by the BOR flag bit
(RCON<1>). The brown-out voltage levels are specific
in Section 31.1 “DC Characteristics”.
DS61156C-page 162
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
PIC32MX devices incorporate two programming and
diagnostic modules, and a trace controller, that provide
a range of functions to the application developer.
28.4 Programming and Diagnostics
PIC32MX5XX/6XX/7XX devices provide a complete
range of programming and diagnostic features that can
increase the flexibility of any application using them.
These features allow system designers to include:
• Simplified field programmability using two-wire
In-Circuit Serial Programming™ (ICSP™)
interfaces
• Debugging using ICSP
• Programming and debugging capabilities using
the EJTAG extension of JTAG
• JTAG boundary scan testing for device and board
diagnostics
FIGURE 28-3:
BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS
PGEC1
PGED1
ICSP™
Controller
PGEC2
PGED2
ICESEL
TDI
TDO
JTAG
Core
Controller
TCK
TMS
JTAGEN
DEBUG<1:0>
TRCLK
TRD0
TRD1
TRD2
TRD3
Instruction Trace
Controller
DEBUG<1:0>
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 163
PIC32MX5XX/6XX/7XX
REGISTER 28-6: DDPCON: DEBUG DATA PORT CONTROL REGISTER
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
bit 31
bit 24
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
bit 23
bit 16
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
bit 15
bit 8
bit 0
r-0
—
r-0
—
r-0
—
r-0
—
R/W-1
R/W-0
r-0
—
r-0
—
JTAGEN
TROEN
bit 7
Legend:
R = Readable bit
W = Writable bit
P = Programmable bit
r = Reserved bit
U = Unimplemented bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
bit 31-4
bit 3
Reserved: Write ‘0’; ignore read
JTAGEN: JTAG Port Enable bit
1= Enable the JTAG port
0= Disable the JTAG port
bit 2
TROEN: Trace Output Enable bit
1= Enable the trace port
0= Disable the trace port
bit 1-0
Reserved: Write ‘1’; ignore read
DS61156C-page 164
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
29.0 INSTRUCTION SET
The PIC32MX5XX/6XX/7XX family instruction set
complies with the MIPS32 Release 2 instruction set
architecture. PIC32MX does not support the following
features:
• Core Extend Instructions
• Coprocessor 1 Instructions
• Coprocessor 2 Instructions
Note:
Refer to “MIPS32® Architecture for Pro-
grammers Volume II: The MIPS32®
Instruction Set” at www.mips.com for more
information.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 165
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 166
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
30.1 MPLAB Integrated Development
Environment Software
30.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• A single graphical interface to all debugging tools
- Simulator
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Customizable data windows with direct edit of
contents
• Simulators
• High-level source code debugging
• Mouse over variable inspection
- MPLAB SIM Software Simulator
• Emulators
• Drag and drop variables from source to watch
windows
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 167
PIC32MX5XX/6XX/7XX
30.2 MPLAB C Compilers for Various
Device Families
30.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
30.3 HI-TECH C for Various Device
Families
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
30.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
30.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• MPLAB IDE compatibility
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS61156C-page 168
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
30.7 MPLAB SIM Software Simulator
30.9 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
30.10 PICkit 3 In-Circuit Debugger/
Programmer and
30.8 MPLAB REAL ICE In-Circuit
Emulator System
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers signifi-
cant advantages over competitive emulators including
low-cost, full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, a rugge-
dized probe interface and long (up to three meters) inter-
connection cables.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 169
PIC32MX5XX/6XX/7XX
30.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
30.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
Development Environment (IDE) the PICkit™
2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
30.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS61156C-page 170
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
31.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC32MX5XX/6XX/7XX electrical characteristics. Additional information will be
provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC32MX5XX/6XX/7XX devices are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these or any other
conditions, above the parameters indicated in the operation listings of this specification, is not implied.
(1)
Absolute Maximum Ratings
Ambient temperature under bias...............................................................................................................-40°C to +85°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)......................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 2.3V (Note 3)........................................ -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)............................. -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS ................................................................................................... -0.3V to 2.0V
Maximum current out of VSS pin(s).......................................................................................................................300 mA
Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 2)....................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions,
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 31-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 171
PIC32MX5XX/6XX/7XX
31.1 DC Characteristics
TABLE 31-1: OPERATING MIPS VS. VOLTAGE
Max. Frequency
PIC32MX5XX/6XX/7XX
80 MHz (Note 1)
VDD Range
(in Volts)
Temp. Range
Characteristic
(in °C)
DC5
2.3-3.6V
-40°C to +85°C
Note 1: 40 MHz maximum for PIC32MX 40 MHz family variants.
TABLE 31-2: THERMAL OPERATING CONDITIONS
Rating
Symbol
Min.
Typical
Max.
Unit
PIC32MX5XX/6XX/7XX
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
—
—
+125
+85
°C
°C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – S IOH)
PD
PINT + PI/O
W
W
I/O Pin Power Dissipation:
I/O = S ({VDD – VOH} x IOH) + S (VOL x IOL))
Maximum Allowed Power Dissipation
PDMAX
(TJ – TA)/JA
TABLE 31-3: THERMAL PACKAGING CHARACTERISTICS
Characteristics
Symbol Typical
Max.
Unit
Notes
Package Thermal Resistance, 121-Pin XBGA (10x10x1.1 mm)
Package Thermal Resistance, 100-Pin TQFP (14x14x1 mm)
Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm)
Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm)
Package Thermal Resistance, 64-Pin QFN (9x9x0,9 mm)
JA
JA
JA
JA
JA
40
43
43
47
28
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
1
1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
TABLE 31-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
DC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics
Min.
Typical
Max. Units
Conditions
Operating Voltage
DC10 Supply Voltage
VDD
2.3
—
—
3.6
—
V
V
DC12
VDR
RAM Data Retention Voltage
(Note 1)
1.75
DC16
VPOR
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
1.75
—
—
1.95
V
DC17
SVDD
VDD Rise Rate
0.00005
0.115 V/s
to Ensure Internal
Power-on Reset Signal
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
DS61156C-page 172
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
Parameter
Typical(3)
No.
Max.
Units
Conditions
Operating Current (IDD)(1,2)
DC20
DC20c
DC21
DC21c
DC22
DC22c
DC23
DC23c
6
9
mA
mA
mA
mA
mA
mA
mA
mA
Code executing from Flash
—
—
—
—
—
—
—
—
4 MHz
4
—
40
—
70
—
98
—
Code executing from SRAM
Code executing from Flash
Code executing from SRAM
Code executing from Flash
Code executing from SRAM
Code executing from Flash
Code executing from SRAM
37
25
64
61
85
85
25 MHz
(Note 4)
60 MHz
(Note 4)
80 MHz
LPRC (31 kHz)
DC25a
125
150
µA
+25°C
3.3V
(Note 4)
Note 1: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
2: The test conditions for IDD measurements are as follows: Oscillator mode = EC+PLL with OSC1 driven by
external square wave from rail-to-rail and PBCLK divisor = 1:8. CPU, Program Flash and SRAM data
memory are operational, Program Flash memory Wait states = 7, program cache and prefetch are dis-
abled and SRAM data memory Wait states = 1. All peripheral modules are disabled (ON bit = 0). WDT and
FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD.
3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
4: This parameter is characterized, but not tested in manufacturing.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 173
PIC32MX5XX/6XX/7XX
TABLE 31-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
Typical(2)
No.
Max.
Units
Conditions
Idle Current (IIDLE): Core Off, Clock On Base Current (Note 1)
DC30
DC31
4.5
13
28
36
—
6.5
15
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
4 MHz
25 MHz (Note 3)
60 MHz (Note 3)
80 MHz
DC32
30
DC33
DC34
DC34a
DC34b
DC35
DC35a
DC35b
DC36
DC36a
DC36b
42
40
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
-40°C
+25°C
+85°C
—
75
2.3V
3.3V
3.6V
—
800
—
35
65
600
—
LPRC (31 kHz)
—
(Note 3)
—
43
—
106
800
—
Note 1: The test conditions for base IDLE current measurements are as follows: System clock is enabled and
PBCLK divisor = 1:8. CPU in Idle mode (CPU core Halted). Only digital peripheral modules are enabled
(ON bit = 1) and being clocked. WDT and FSCM are disabled. All I/O pins are configured as inputs and
pulled to VSS. MCLR = VDD.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
3: This parameter is characterized, but not tested in manufacturing.
DS61156C-page 174
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
Parameter
Typical(2)
No.
Max.
Units
Conditions
Power-Down Current (IPD) (Note 1)
DC40
10
36
40
A
A
A
A
A
A
A
A
-40°C
+25°C
+85°C
+25°C
-40°C
+25°C
+70°C
+85°C
DC40a
DC40b
DC40c
DC40d
DC40e
DC40g
DC40f
100
720
120
80
2.3V Base Power-Down Current (Note 6)
400
41
3.3V Base Power-Down Current
22
42
120
400
800
3.6V Base Power-Down Current
315
410
Module Differential Current
DC41
—
5
10
—
20
40
A
A
A
A
2.3V
Watchdog Timer Current: IWDT (Notes 3, 6)
Watchdog Timer Current: IWDT (Note 3)
Watchdog Timer Current: IWDT (Note 3)
DC41c
DC41d
DC42
3.3V
3.6V
—
—
RTCC + Timer1 w/32 kHz Crystal: IRTCC
(Notes 3, 6)
2.3V
3.3V
DC42c
DC42e
23
—
—
A
A
RTCC + Timer1 w/32 kHz Crystal: IRTCC
(Note 3)
50
RTCC + Timer1 w/32 kHz Crystal: IRTCC
(Note 3)
3.6V
DC43
—
1100
—
1300
—
A
A
A
2.5V
3.3V
3.6V
ADC: IADC (Notes 3, 4, 6)
ADC: IADC (Notes 3, 4)
ADC: IADC (Notes 3, 4)
DC43c
DC43e
1300
Note 1: Base IPD is measured with all digital peripheral modules and being clocked, CPU clock is disabled. All I/Os
are configured as inputs and pulled low. WDT and FSCM are disabled.
2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
3: The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
5: Data is characterized at +70°C and not tested. Parameter is for design guidance only.
6: This parameter is characterized, but not tested in manufacturing.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 175
PIC32MX5XX/6XX/7XX
TABLE 31-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise
stated)
Operating temperature
DC CHARACTERISTICS
-40°C TA +85°C for Industrial
Param.
No.
Symbol
Characteristics
Min.
Typical(1)
Max.
Units
Conditions
VIL
Input Low Voltage
I/O Pins:
DI10
with TTL Buffer
with Schmitt Trigger Buffer
MCLR(2)
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
0.15 VDD
0.2 VDD
0.2 VDD
0.2 VDD
0.2 VDD
0.3 VDD
V
V
V
V
V
V
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
DI15
DI16
DI17
DI18
OSC1 (XT mode)
OSC1 (HS mode)
SDAx, SCLx
SMBus disabled
(Note 4)
DI19
DI20
SDAx, SCLx
VSS
—
0.8
V
SMBus enabled
(Note 4)
VIH
Input High Voltage
I/O Pins:
with Analog Functions
0.8 VDD
0.8 VDD
—
—
—
—
—
—
—
—
VDD
V
V
V
V
V
V
V
V
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 4)
Digital Only
with TTL Buffer
with Schmitt Trigger Buffer
MCLR(2)
0.25 VDD + 0.8V
0.8 VDD
5.5
5.5
DI25
DI26
DI27
DI28
0.8 VDD
VDD
VDD
VDD
5.5
OSC1 (XT mode)
OSC1 (HS mode)
SDAx, SCLx
0.7 VDD
0.7 VDD
0.7 VDD
SMBus disabled
(Note 4)
DI29
DI30
SDAx, SCLx
2.1
50
—
5.5
V
SMBus enabled,
2.3V VPIN 5.5
(Note 4)
ICNPU
IIL
CNxx Pull up Current
250
400
A VDD = 3.3V, VPIN = VSS
Input Leakage Current
(Note 3)
DI50
DI51
I/O Ports
—
—
—
—
+1
+1
A VSS VPIN VDD,
Pin at high-impedance
Analog Input Pins
A VSS VPIN VDD,
Pin at high-impedance
DI55
DI56
MCLR(2)
OSC1
—
—
—
—
+1
+1
A VSS VPIN VDD
A VSS VPIN VDD,
XT and HS modes
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: This parameter is characterized, but not tested in manufacturing.
DS61156C-page 176
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise
stated)
DC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
Param.
No.
Symbol
Characteristics
Min.
Typical
Max. Units Conditions
VOL
Output Low Voltage
DO10
DO16
I/O Ports
—
—
—
—
—
—
—
—
0.4
0.4
0.4
0.4
V
V
V
V
IOL = 7 mA, VDD = 3.6V
IOL = 6 mA, VDD = 2.3V
IOL = 3.5 mA, VDD = 3.6V
IOL = 2.5 mA, VDD = 2.3V
OSC2/CLKO
VOH
Output High Voltage
DO20
DO26
I/O Ports
2.4
1.4
2.4
1.4
—
—
—
—
—
—
—
—
V
V
V
V
IOH = -12 mA, VDD = 3.6V
IOH = -12 mA, VDD = 2.3V
IOH = -12 mA, VDD = 3.6V
IOH = -12 mA, VDD = 2.3V
OSC2/CLKO
TABLE 31-10: DC CHARACTERISTICS: PROGRAM MEMORY(3)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Programming temperature 0°C TA +70°C (25°C recommended)
DC CHARACTERISTICS
Param.
No.
Symbol
Characteristics
Min. Typical(1) Max. Units
Conditions
Program Flash Memory
Cell Endurance
D130
D131
EP
1000
VMIN
—
—
—
E/W -40°C to +85°C
VPR
VDD for Read
3.6
V
VMIN = Minimum operating
voltage
D132
D134
VPEW
VDD for Erase or Write
Characteristic Retention
3.0
20
—
—
3.6
—
V
0°C to +40°C
TRETD
Year Provided no other specifications
are violated
D135
IDDP
Supply Current during
Programming
—
10
—
mA 0°C to +40°C
TWW
TRW
Word Write Cycle Time
20
3
—
40
—
s 0°C to +40°C
D136
D137
Row Write Cycle Time
(Note 2)
(128 words per row)
4.5
ms 0°C to +40°C
TPE
TCE
Page Erase Cycle Time
Chip Erase Cycle Time
20
80
—
—
—
—
ms 0°C to +40°C
ms 0°C to +40°C
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities
during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads
are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default
Arbitration mode is mode 1 (CPU has lowest priority).
3: Refer to the “PIC32MX Flash Programming Specification” (DS61145) for operating conditions during
programming and erase cycles.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 177
PIC32MX5XX/6XX/7XX
TABLE 31-11: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
DC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Required Flash Wait States
SYSCLK
Units
Comments
0 Wait State
1 Wait State
2 Wait States
0 to 30
31 to 60
61 to 80
MHz
TABLE 31-12: COMPARATOR SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics
Input Offset Voltage
Min. Typical Max.
Units
Comments
D300
VIOFF
—
0
±7.5
—
±25
VDD
mV
AVDD = VDD,
AVSS = VSS
D301
VICM
Input Common Mode Voltage
V
AVDD = VDD,
AVSS = VSS
(Note 2)
D302
D303
CMRR
TRESP
Common Mode Rejection Ratio
Response Time
55
—
—
—
dB
ns
Max VICM = (VDD – 1)V
(Note 2)
150
400
AVDD = VDD,
AVSS = VSS
(Notes 1, 2)
D304
ON2OV
Comparator Enabled to Output
Valid
—
—
10
s
Comparator module is
configured before setting
the comparator ON bit.
(Note 2)
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
2: These parameters are characterized but not tested.
DS61156C-page 178
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-13: VOLTAGE REFERENCE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics
Resolution
Min. Typical Max.
Units
Comments
D310
D311
D312
D313
VRES
VRAA
TSET
VDD/24
—
—
—
VDD/32
1/2
LSb
LSb
s
Absolute Accuracy
Settling Time(1)
—
—
10
VIREF
Internal Voltage Reference
—
0.6
—
V
Note 1: Settling time measured while CVRR = 1and CVR<3:0> transitions from ‘0000’ to ‘1111’. This parameter is
characterized, but not tested in manufacturing.
TABLE 31-14: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
DC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics
Min. Typical Max. Units
Comments
D320
D321
VDDCORE Regulator Output Voltage
1.62
8
1.80
10
1.98
—
V
CEFC
External Filter Capacitor Value
F Capacitor must be low series
resistance (1 ohm)
D322
TPWRT
Power-up Timer Period
—
64
—
ms
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 179
PIC32MX5XX/6XX/7XX
31.2 AC Characteristics and Timing
Parameters
The information contained in this section defines
PIC32MX5XX/6XX/7XX AC characteristics and timing
parameters.
TABLE 31-15: AC CHARACTERISTICS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Operating voltage VDD range.
FIGURE 31-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins
50 pF for OSC2 pin (EC mode)
VSS
TABLE 31-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Standard Operating Conditions: 2.3V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param.
No.
Symbol
Characteristics
Min. Typical(1) Max. Units
Conditions
DO56
DO58
CIO
CB
All I/O pins and OSC2
SCLx, SDAx
—
—
—
—
50
pF EC mode
pF In I2C™ mode
400
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 31-2:
EXTERNAL CLOCK TIMING
OS30
OS31
OS20
OSC1
OS31
OS30
DS61156C-page 180
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics
Min.
Typical(1)
Max.
Units
Conditions
OS10
FOSC
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
4
—
—
50 (Note 3) MHz EC (Note 5)
50 (Note 5) MHz ECPLL (Note 4)
OS11
OS12
Oscillator Crystal Frequency
3
4
—
—
10
10
MHz XT (Note 5)
MHz XTPLL
(Notes 4, 5)
OS13
OS14
10
10
—
—
25
25
MHz HS (Note 5)
MHz HSPLL
(Notes 4, 5)
OS15
OS20
32
—
32.768
—
100
—
kHz SOSC (Note 5)
TOSC
TOSC = 1/FOSC = TCY (Note 2)
—
See parameter
OS10 for FOSC
value
OS30
OS31
OS40
TOSL,
TOSH
External Clock In (OSC1)
High or Low Time
0.45 x TOSC
—
—
—
0.05 x TOSC
—
ns
ns
EC (Note 5)
TOSR,
TOSF
External Clock In (OSC1)
Rise or Fall Time
—
—
EC (Note 5)
TOST
Oscillator Start-up Timer Period
(Only applies to HS, HSPLL,
XT, XTPLL and SOSC Clock
Oscillator modes)
1024
TOSC (Note 5)
OS41
OS42
TFSCM
GM
Primary Clock Fail Safe
Time-out Period
—
—
2
—
—
ms (Note 5)
External Oscillator
Transconductance
12
mA/V VDD = 3.3V,
TA = +25°C
(Note 5)
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are not
tested.
2: Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device
executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min.” values with an
external clock applied to the OSC1/CLKI pin.
3: 40 MHz maximum for PIC32MX 40 MHz family variants.
4: PLL input requirements: 4 MHZ FPLLIN 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is
characterized, but tested at 10 MHz only at manufacturing.
5: This parameter is characterized, but not tested in manufacturing.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 181
PIC32MX5XX/6XX/7XX
TABLE 31-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V)
Standard Operating Conditions: 2.3V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics(1)
Min. Typical(2) Max. Units
Conditions
OS50
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
4
—
5
MHz ECPLL, HSPLL, XTPLL,
FRCPLL modes
OS51
FSYS
On-Chip VCO System
Frequency
60
—
120
MHz
OS52
OS53
TLOCK
DCLK
PLL Start-up Time (Lock Time)
—
—
—
2
ms
CLKO Stability
(Period Jitter or Cumulative)
-0.25
+0.25
%
Measured over 100 ms
period
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 31-19: INTERNAL FRC ACCURACY
Standard Operating Conditions: 2.3V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
Units Conditions
Param.
No.
Characteristics
Min. Typical Max.
Internal FRC Accuracy @ 8.00 MHz (Note 1)
F20 FRC -2
—
+2
%
Note 1: Frequency calibrated at 25°C and 3.3V. The TUN bits can be used to compensate for temperature drift.
TABLE 31-20: INTERNAL RC ACCURACY
Standard Operating Conditions: 2.3V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param.
No.
Characteristics
Min. Typical Max.
Units
Conditions
LPRC @ 31.25 kHz (Note 1)
F21
LPRC
-15
—
+15
%
Note 1: Change of LPRC frequency as VDD changes.
DS61156C-page 182
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
DO31
DO32
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-21: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(2)
Min.
Typical(1)
Max.
Units
Conditions
DO31
TIOR
Port Output Rise Time
Port Output Fall Time
—
—
—
—
10
2
5
5
15
10
15
10
—
—
ns
ns
VDD < 2.5V
VDD > 2.5V
VDD < 2.5V
VDD > 2.5V
DO32
TIOF
5
ns
5
ns
DI35
DI40
TINP
INTx Pin High or Low Time
—
—
ns
TRBP
CNx High or Low Time (input)
TSYSCLK
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: This parameter is characterized, but not tested in manufacturing.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 183
PIC32MX5XX/6XX/7XX
FIGURE 31-4:
POWER-ON RESET TIMING CHARACTERISTICS
Internal Voltage Regulator Enabled
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
CPU Starts Fetching Code
SY00
(TPU)
(Note 1)
Internal Voltage Regulator Enabled
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
VDD
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
CPU Starts Fetching Code
SY00
(TPU)
SY10
(TOST)
(Note 1)
External VDDCORE Provided
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VDDCORE
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 3)
CPU Starts Fetching Code
SY01
(TPWRT)
(Note 1)
Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from BOR
(VDD < VDDMIN).
2: Includes interval voltage regulator stabilization delay.
3: Power-up Timer (PWRT); only active when the internal voltage regulator is disabled.
DS61156C-page 184
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-5:
EXTERNAL RESET TIMING CHARACTERISTICS
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
MCLR
TMCLR
(SY20)
BOR
TBOR
(SY30)
(TSYSDLY)
SY02
Reset Sequence
CPU Starts Fetching Code
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
(TSYSDLY)
SY02
Reset Sequence
CPU Starts Fetching Code
TOST
(SY10)
TABLE 31-22: RESETS TIMING
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics(1)
Power-up Period
Min.
Typical(2)
Max.
Units
Conditions
SY00
TPU
—
400
600
s
-40°C to +85°C
Internal Voltage Regulator Enabled
SY01
TPWRT
Power-up Period
External VDDCORE Applied
(Power-up timer active)
48
—
64
80
—
ms -40°C to +85°C
SY02
TSYSDLY System Delay Period:
Time Required to Reload Device
s +
8 SYSCLK
cycles
—
-40°C to +85°C
Configuration Fuses plus SYSCLK
Delay before First instruction is
Fetched.
SY20
SY30
TMCLR
TBOR
MCLR Pulse Width (low)
BOR Pulse Width (low)
—
—
2
1
—
—
s
s
-40°C to +85°C
-40°C to +85°C
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 185
PIC32MX5XX/6XX/7XX
FIGURE 31-6:
TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRx
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics(2)
Min.
Typical Max. Units
Conditions
TA10
TA11
TA15
TTXH
TTXL
TTXP
TxCK Synchronous,
High Time with prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter TA15
Asynchronous,
with prescaler
10
ns
TxCK
Low Time
Synchronous,
with prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
ns Must also meet
parameter TA15
Asynchronous,
with prescaler
10
ns
TxCK
Synchronous,
[(Greater of 25 ns or
2 TPB)/N] + 30 ns
ns VDD > 2.7V
ns VDD < 2.7V
Input Period with prescaler
[(Greater of 25 ns or
2 TPB)/N] + 50 ns
Asynchronous,
with prescaler
20
50
32
ns VDD > 2.7V
(Note 3)
ns VDD < 2.7V
(Note 3)
OS60 FT1
SOSC1/T1CK Oscillator
Input Frequency Range
(oscillator enabled by setting
TCS bit (T1CON<1>))
100 kHz
TA20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
—
1
TPB
Increment
Note 1: Timer1 is a Type A.
2: This parameter is characterized, but not tested in manufacturing.
3: N = Prescale Value (1, 8, 64, 256)
DS61156C-page 186
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
Param.
Symbol
No.
(1)
Characteristics
Min.
Max. Units Conditions
TB10
TB11
TB15
TTXH
TTXL
TTXP
TxCK
High Time prescaler
Synchronous, with
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
—
—
—
1
ns Must also meet N = prescale
parameter TB15 value
(1, 2, 4, 8, 16,
32, 64, 256)
TxCK
Low Time prescaler
Synchronous, with
[(12.5 ns or 1 TPB)/N]
+ 25 ns
ns Must also meet
parameter TB15
TxCKInput Synchronous, with
Period
[(Greater of [(25 ns or
2 TPB)/N] + 30 ns
ns VDD > 2.7V
ns VDD < 2.7V
TPB
prescaler
[(Greater of [(25 ns or
2 TPB)/N] + 50 ns
TB20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
—
Note 1: These parameters are characterized, but not tested in manufacturing.
FIGURE 31-7:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
Characteristics(1)
Min.
Max. Units
Conditions
No.
IC10
TCCL
ICx Input Low Time
ICx Input High Time
ICx Input Period
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
—
—
ns
ns
ns
Must also
N = prescale
meet
value (1, 4, 16)
parameter
IC15.
IC11
IC15
TCCH
[(12.5 ns or 1 TPB)/N]
+ 25 ns
Must also
meet
parameter
IC15.
TCCP
[(25 ns or 2 TPB)/N]
+ 50 ns
Note 1: These parameters are characterized, but not tested in manufacturing.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 187
PIC32MX5XX/6XX/7XX
FIGURE 31-8:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM mode)
OC10
OC11
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
No.
OC10
OC11
TCCF
TCCR
OCx Output Fall Time
OCx Output Rise Time
—
—
—
—
—
—
ns
ns
See parameter DO32
See parameter DO31
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 31-9:
OCx/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCx
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param
Symbol
No.
Characteristics(1)
Min
Typical(2)
Max
Units
Conditions
OC15
OC20
TFD
Fault Input to PWM I/O Change
Fault Input Pulse Width
—
—
—
50
—
ns
ns
TFLT
50
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
DS61156C-page 188
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-10:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SCKx
(CKP = 1)
SP35
SP31
SP21
LSb
Bit 14 - - - - - -1
MSb
SDOx
SDIx
SP30
MSb In
SP40
LSb In
Bit 14 - - - -1
SP41
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical(2) Max. Units
Conditions
SCKx Output Low Time
(Note 3)
SP10
SP11
SP20
SP21
SP30
SP31
SP35
TSCL
TSCH
TSCF
TSCR
TDOF
TDOR
TSCK/2
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
SCKx Output High Time
(Note 3)
TSCK/2
—
SCKx Output Fall Time
(Note 4)
See parameter DO32
See parameter DO31
See parameter DO32
See parameter DO31
SCKx Output Rise Time
(Note 4)
—
—
—
—
—
—
—
SDOx Data Output Fall Time
(Note 4)
—
SDOx Data Output Rise Time
(Note 4)
—
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
10
—
—
—
ns
ns
ns
VDD > 2.7V
VDD < 2.7V
15
20
—
SP40
SP41
TDIV2SCH, Setup Time of SDIx Data Input
TDIV2SCL
TSCH2DIL, Hold Time of SDIx Data Input
TSCL2DIL to SCKx Edge
Note 1: These parameters are characterized, but not tested in manufacturing.
to SCKx Edge
—
—
ns
10
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 189
PIC32MX5XX/6XX/7XX
FIGURE 31-11:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11
SP10
SP21
SP20
SP21
SCKX
(CKP = 1)
SP35
SP20
Bit 14 - - - - - -1
LSb
MSb
SDOX
SDIX
SP30,SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +85°Cfor Industrial
Param.
Symbol
No.
Characteristics(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
SP11
SP20
SP21
SP30
TSCL
TSCH
TSCF
TSCR
TDOF
SCKx Output Low Time (Note 3) TSCK/2
SCKx Output High Time (Note 3) TSCK/2
—
—
—
—
—
—
—
—
—
—
ns
ns
SCKx Output Fall Time (Note 4)
SCKx Output Rise Time (Note 4)
—
—
—
ns See parameter DO32
ns See parameter DO31
ns See parameter DO32
SDOx Data Output Fall Time
(Note 4)
SP31
SP35
TDOR
SDOx Data Output Rise Time
(Note 4)
—
—
—
ns See parameter DO31
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
15
—
—
—
15
20
—
ns
ns
ns
VDD > 2.7V
VDD < 2.7V
SP36
SP40
TDOV2SC, SDOx Data Output Setup to
TDOV2SCL First SCKx Edge
TDIV2SCH, Setup Time of SDIx Data Input to
TDIV2SCL SCKx Edge
15
20
15
20
—
—
—
—
—
—
—
—
ns
ns
ns
ns
VDD > 2.7V
VDD < 2.7V
VDD > 2.7V
VDD < 2.7V
SP41
TSCH2DIL, Hold Time of SDIx Data Input
TSCL2DIL
to SCKx Edge
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
DS61156C-page 190
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-12:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP72
SP73
SP73
SP72
SCKX
(CKP = 1)
SP35
MSb
LSb
SDOX
SDIX
Bit 14 - - - - - -1
SP51
SP30,SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typ.(2) Max. Units
Conditions
SP70
SP71
SP72
SP73
SP30
SP31
TSCL
TSCH
TSCF
TSCR
TDOF
TDOR
SCKx Input Low Time (Note 3)
SCKx Input High Time (Note 3)
SCKx Input Fall Time
TSCK/2
TSCK/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
20
—
ns
ns
ns See parameter DO32
ns See parameter DO31
ns See parameter DO32
ns See parameter DO31
ns VDD > 2.7V
SCKx Input Rise Time
—
SDOx Data Output Fall Time (Note 4)
SDOx Data Output Rise Time (Note 4)
—
—
SP35 TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
ns VDD < 2.7V
SP40 TDIV2SCH, Setup Time of SDIx Data Input
TDIV2SCL to SCKx Edge
10
ns
SP41 TSCH2DIL, Hold Time of SDIx Data Input
TSCL2DIL to SCKx Edge
10
175
—
—
—
—
—
—
25
—
ns
ns
ns
ns
SP50 TSSL2SCH, SSx to SCKx or SCKx Input
TSSL2SCL
SP51 TSSH2DOZ SSx to SDOx Output
High-Impedance (Note 3)
5
SP52
TSCH2SSH SSx after SCKx Edge
TSCL2SSH
TSCK + 20
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The minimum clock period for SCKx is 40 ns.
4: Assumes 50 pF load on all SPIx pins.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 191
PIC32MX5XX/6XX/7XX
FIGURE 31-13:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP72
SP73
SP73
SCKx
(CKP = 1)
SP35
SP72
LSb
MSb
Bit 14 - - - - - -1
SDOx
SDIx
SP30,SP31
Bit 14 - - - -1
SP51
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics(1)
Min.
Typical(2) Max. Units
Conditions
SP70
SP71
SP72
SP73
SP30
TSCL
TSCH
TSCF
TSCR
TDOF
SCKx Input Low Time (Note 3)
SCKx Input High Time (Note 3)
SCKx Input Fall Time
TSCK/2
TSCK/2
—
—
—
5
—
—
10
10
—
ns
ns
ns
ns
SCKx Input Rise Time
—
5
SDOx Data Output Fall Time
—
—
ns See parameter DO32
(Note 4)
SP31
SP35
TDOR
SDOx Data Output Rise Time
(Note 4)
—
—
—
ns See parameter DO31
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
10
—
—
—
20
30
—
ns VDD > 2.7V
ns VDD < 2.7V
ns
SP40
SP41
SP50
TDIV2SCH, Setup Time of SDIx Data Input
TDIV2SCL to SCKx Edge
TSCH2DIL, Hold Time of SDIx Data Input
TSCL2DIL
10
—
—
—
—
ns
ns
to SCKx Edge
TSSL2SCH, SSx to SCKx or SCKx Input
175
TSSL2SCL
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The minimum clock period for SCKx is 40 ns.
4: Assumes 50 pF load on all SPIx pins.
DS61156C-page 192
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics(1)
Min.
Typical(2) Max. Units
Conditions
SP51
TSSH2DOZ SSx to SDOX Output
High-Impedance
5
—
25
ns
(Note 4)
SP52
SP60
TSCH2SSH SSx after SCKx Edge
TSCL2SSH
TSCK +
20
—
—
—
ns
ns
TSSL2DOV SDOx Data Output Valid after
SSx Edge
—
25
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The minimum clock period for SCKx is 40 ns.
4: Assumes 50 pF load on all SPIx pins.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 193
PIC32MX5XX/6XX/7XX
FIGURE 31-14:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 31-1 for load conditions.
FIGURE 31-15:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM33
IM25
SDAx
In
IM45
IM40
IM40
SDAx
Out
Note: Refer to Figure 31-1 for load conditions.
DS61156C-page 194
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics
Min.(1)
Max.
Units
Conditions
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
TLO:SCL Clock Low Time 100 kHz mode
400 kHz mode
TPB * (BRG + 2)
TPB * (BRG + 2)
TPB * (BRG + 2)
—
—
—
s
s
s
1 MHz mode
(Note 2)
THI:SCL Clock High Time 100 kHz mode
400 kHz mode
TPB * (BRG + 2)
TPB * (BRG + 2)
TPB * (BRG + 2)
—
—
—
s
s
s
1 MHz mode
(Note 2)
TF:SCL
TR:SCL
SDAx and SCLx 100 kHz mode
—
20 + 0.1 CB
—
300
300
100
ns
ns
ns
CB is specified to be
from 10 to 400 pF
Fall Time
400 kHz mode
1 MHz mode
(Note 2)
SDAx and SCLx 100 kHz mode
—
20 + 0.1 CB
—
1000
300
ns
ns
ns
CB is specified to be
from 10 to 400 pF
Rise Time
400 kHz mode
1 MHz mode
(Note 2)
300
TSU:DAT Data Input
Setup Time
100 kHz mode
400 kHz mode
250
100
100
—
—
—
ns
ns
ns
1 MHz mode
(Note 2)
THD:DAT Data Input
Hold Time
100 kHz mode
400 kHz mode
0
0
0
—
s
s
s
0.9
0.3
1 MHz mode
(Note 2)
TSU:STA Start Condition 100 kHz mode
TPB * (BRG + 2)
TPB * (BRG + 2)
TPB * (BRG + 2)
—
—
—
s
s
s
Only relevant for
Repeated Start
condition
Setup Time
400 kHz mode
1 MHz mode
(Note 2)
THD:STA Start Condition 100 kHz mode
TPB * (BRG + 2)
TPB * (BRG + 2)
TPB * (BRG + 2)
—
—
—
s
s
s
After this period, the
first clock pulse is
generated
Hold Time
400 kHz mode
1 MHz mode
(Note 2)
TSU:STO Stop Condition 100 kHz mode
TPB * (BRG + 2)
TPB * (BRG + 2)
TPB * (BRG + 2)
—
—
—
s
s
s
Setup Time
400 kHz mode
1 MHz mode
(Note 2)
THD:STO Stop Condition
Hold Time
100 kHz mode
400 kHz mode
TPB * (BRG + 2)
TPB * (BRG + 2)
TPB * (BRG + 2)
—
—
—
ns
ns
ns
1 MHz mode
(Note 2)
Note 1: BRG is the value of the I2C™ Baud Rate Generator.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 195
PIC32MX5XX/6XX/7XX
TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics
Min.(1)
Max.
Units
Conditions
IM40
IM45
IM50
TAA:SCL Output Valid
From Clock
100 kHz mode
—
—
—
3500
1000
350
ns
ns
ns
400 kHz mode
1 MHz mode
(Note 2)
TBF:SDA Bus Free Time 100 kHz mode
400 kHz mode
4.7
1.3
0.5
—
—
—
s
s
s
The amount of time the
bus must be free
before a new
1 MHz mode
(Note 2)
transmission can start
CB
Bus Capacitive Loading
—
400
pF
Note 1: BRG is the value of the I2C™ Baud Rate Generator.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS61156C-page 196
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-16:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 31-1 for load conditions.
FIGURE 31-17:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS33
IS25
SDAx
In
IS45
IS40
IS40
SDAx
Out
Note: Refer to Figure 31-1 for load conditions.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 197
PIC32MX5XX/6XX/7XX
TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Max. Units
Conditions
IS10
IS11
TLO:SCL Clock Low Time 100 kHz mode
400 kHz mode
4.7
—
—
—
—
—
—
s
s
s
s
s
s
PBCLK must operate at a
minimum of 800 kHz
1.3
0.5
4.0
0.6
0.5
PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode
(Note 1)
THI:SCL
Clock High Time 100 kHz mode
PBCLK must operate at a
minimum of 800 kHz
400 kHz mode
PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode
(Note 1)
IS20
IS21
IS25
IS26
IS30
IS31
IS33
TF:SCL
TR:SCL
SDAx and SCLx 100 kHz mode
—
20 + 0.1 CB
—
300
300
100
ns
ns
ns
CB is specified to be from
10 to 400 pF
Fall Time
400 kHz mode
1 MHz mode
(Note 1)
SDAx and SCLx 100 kHz mode
—
20 + 0.1 CB
—
1000
300
ns
ns
ns
CB is specified to be from
10 to 400 pF
Rise Time
400 kHz mode
1 MHz mode
(Note 1)
300
TSU:DAT Data Input
Setup Time
100 kHz mode
400 kHz mode
250
100
100
—
—
—
ns
ns
ns
1 MHz mode
(Note 1)
THD:DAT Data Input
Hold Time
100 kHz mode
400 kHz mode
0
0
0
—
0.9
0.3
ns
s
s
1 MHz mode
(Note 1)
TSU:STA Start Condition
Setup Time
100 kHz mode
400 kHz mode
4700
600
—
—
—
s
s
s
Only relevant for Repeated
Start condition
1 MHz mode
(Note 1)
250
THD:STA Start Condition
Hold Time
100 kHz mode
400 kHz mode
4000
600
—
—
—
s
s
s
After this period, the first
clock pulse is generated
1 MHz mode
(Note 1)
250
TSU:STO Stop Condition
Setup Time
100 kHz mode
400 kHz mode
4000
600
—
—
—
s
s
s
1 MHz mode
600
(Note 1)
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS61156C-page 198
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics
Min.
Max. Units
Conditions
IS34
IS40
IS45
IS50
THD:STO Stop Condition
Hold Time
100 kHz mode
4000
600
—
—
ns
ns
ns
400 kHz mode
1 MHz mode
(Note 1)
250
TAA:SCL
Output Valid From 100 kHz mode
0
0
0
3500
1000
350
ns
ns
ns
Clock
400 kHz mode
1 MHz mode
(Note 1)
TBF:SDA Bus Free Time
100 kHz mode
400 kHz mode
4.7
1.3
0.5
—
—
—
s
s
s
The amount of time the bus
must be free before a new
transmission can start
1 MHz mode
(Note 1)
CB
Bus Capacitive Loading
—
400
pF
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 199
PIC32MX5XX/6XX/7XX
FIGURE 31-18:
CAN MODULE I/O TIMING CHARACTERISTICS
CiTx Pin
(output)
New Value
Old Value
CA10 CA11
CA20
CiRx Pin
(input)
TABLE 31-34: CAN MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
CA10
CA11
CA20
TioF
TioR
Tcwf
Port Output Fall Time
Port Output Rise Time
—
—
—
—
—
—
—
—
ns
ns
ns
See parameter D032
See parameter D031
—
Pulse Width to Trigger
CAN Wake-up Filter
500
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
DS61156C-page 200
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-35: ETHERNET MODULE SPECIFICATIONS
Standard Operating Conditions: 2.5V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature
-40°C TA +85°C for Industrial
Param.
No.
Characteristic
Min.
Typical
Max.
Units
Conditions
Device Supply
ET20a
ET20b
Module VDD Supply
Module VDD Supply
2.5
2.7
—
—
3.6
3.6
V
V
For RMII mode only
MIIM Timing Requirements
ET1
ET2
ET3
ET4
MDC Duty Cycle
MDC Period
40
400
10
0
—
—
—
—
60
—
%
ns
ns
ns
MDIO Output Delay
MDIO Input Delay
10
300
MII Timing Requirements
ET5
ET6
ET7
TX Clock Frequency
—
35
0
25
—
—
—
65
25
MHz
%
TX Clock Duty Cycle
ETXDx, ETEN, ETXERR
Delay
ns
ET8
ET9
RX Clock Frequency
RX Clock Duty Cycle
—
35
10
25
—
—
—
65
30
MHz
%
ET10
ERXDx, ERXDV, ERXERR
Delay
ns
RMII Timing Requirements
ET11
ET12
ET13
ET14
Reference Clock Frequency
—
35
2
50
—
—
—
—
65
16
16
MHz
%
Reference Clock Duty Cycle
ETXDx, ETEN, Delay
ns
ERXDx, ERXDV, ERXERR
Delay
2
ns
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 201
PIC32MX5XX/6XX/7XX
TABLE 31-36: ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 2.5V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
Characteristics
Min.
Typical
—
Max.
Units
Conditions
No.
Device Supply
AD01
AVDD
Module VDD Supply
Module VSS Supply
Greater of
VDD – 0.3
or 2.5
Lesser of
VDD + 0.3
or 3.6
V
V
AD02
AVSS
VSS
—
VSS + 0.3
Reference Inputs
AD05
AD05a
AD06
AD07
VREFH
Reference Voltage High AVSS + 2.0
2.5
—
—
—
—
AVDD
3.6
V
V
V
V
(Note 1)
VREFH = AVDD (Note 3)
(Note 1)
VREFL
VREF
Reference Voltage Low
AVSS
2.0
VREFH – 2.0
AVDD
Absolute Reference
(Note 3)
Voltage (VREFH – VREFL)
AD08
IREF
Current Drain
—
250
—
400
3
A ADC operating
A ADC off
Analog Input
AD12 VINH-VINL Full-Scale Input Span
VREFL
—
—
VREFH
V
V
VINL
Absolute VINL Input
Voltage
AVSS – 0.3
AVDD/2
VIN
Absolute Input Voltage
Leakage Current
AVSS – 0.3
—
—
AVDD + 0.3
V
+/- 0.001 +/-0.610
A VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
Source Impedance = 10 k
AD17
RIN
Recommended
—
—
5K
(Note 1)
Impedance of Analog
Voltage Source
ADC Accuracy – Measurements with External VREF+/VREF-
AD20c Nr
Resolution
10 data bits
—
bits
AD21c INL
Integral Nonlinearity
> -1
> -1
< 1
< 1
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD22c DNL
Differential Nonlinearity
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
(Note 2)
AD23c GERR
AD24n EOFF
Gain Error
> -1
> -1
—
—
—
—
< 1
< 1
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
Offset Error
LSb VINL = AVSS = 0V,
AVDD = 3.3V
AD25c
—
Monotonicity
—
Guaranteed
Note 1: These parameters are not characterized or tested in manufacturing.
2: With no missing codes.
3: These parameters are characterized, but not tested in manufacturing.
4: Characterized with a 1 kHz sinewave.
DS61156C-page 202
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-36: ADC MODULE SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
Param.
No.
ADC Accuracy – Measurements with Internal VREF+/VREF-
Symbol
Characteristics
Min.
Typical
Max.
Units
Conditions
AD20d Nr
Resolution
10 data bits
—
bits (Note 3)
AD21d INL
Integral Nonlinearity
> -1
> -1
> -4
> -2
—
< 1
< 1
< 4
< 2
—
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD22d DNL
AD23d GERR
AD24d EOFF
Differential Nonlinearity
Gain Error
—
—
—
—
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Notes 2, 3)
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
Offset Error
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD25d
—
Monotonicity
—
Guaranteed
Dynamic Performance
AD31b SINAD
Signal to Noise and
Distortion
55
58.5
9.5
—
—
dB (Notes 3, 4)
bits (Notes 3, 4)
AD34b ENOB
Effective Number of Bits
9.0
Note 1: These parameters are not characterized or tested in manufacturing.
2: With no missing codes.
3: These parameters are characterized, but not tested in manufacturing.
4: Characterized with a 1 kHz sinewave.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 203
PIC32MX5XX/6XX/7XX
TABLE 31-37: 10-BIT CONVERSION RATE PARAMETERS
PIC32MX 10-Bit A/D Converter Conversion Rates(2)
TAD
Sampling
ADC Speed
RS Max
VDD
Temperature
ADC Channels Configuration
Minimum Time Min
1 Msps to
65 ns
200 ns
200 ns
132 ns
200 ns
200 ns
500
3.0V to
3.6V
-40°C to
+85°C
400 ksps(1)
VREF- VREF+
CH
X
ANx
SHA
ADC
Up to 400 ksps
5.0 k 2.5V to
-40°C to
+85°C
3.6V
V
REF
or
-
V
REF
or
+
AVSS AVDD
CHX
ANx
SHA
ADC
ANx or VREF
-
Up to 300 ksps
5.0 k 2.5V to
-40°C to
+85°C
3.6V
V
REF- VREF+
or
or
AVSS AVDD
CHX
ANx
SHA
ADC
ANx or VREF
-
Note 1: External VREF- and VREF+ pins must be used for correct operation.
2: These parameters are characterized, but not tested in manufacturing.
DS61156C-page 204
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-38: A/D CONVERSION TIMING REQUIREMENTS
Standard Operating Conditions: 2.5V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics
Min.
Typical(1) Max.
Units
Conditions
Clock Parameters
AD50
TAD
A/D Clock Period(2)
65
—
—
ns
—
See Table 31-37
Conversion Rate
AD55
AD56
TCONV
FCNV
Conversion Time
—
—
—
1
12 TAD
—
—
1000
400
31
Throughput Rate
(Sampling Speed)
ksps AVDD = 3.0V to 3.6V
ksps AVDD = 2.5V to 3.6V
—
AD57
TSAMP
Sample Time
—
TAD
TSAMP must be 132 ns
Timing Parameters
AD60
TPCS
Conversion Start from Sample
Trigger(3)
—
1.0 TAD
—
—
Auto-Convert Trigger
(SSRC<2:0> = 111)
not selected
AD61
AD62
AD63
TPSS
TCSS
TDPU
Sample Start from Setting
Sample (SAMP) bit
0.5 TAD
—
—
0.5 TAD
—
1.5 TAD
—
—
s
Conversion Completion to
—
2
Sample Start (ASAM = 1)(3)
Time to Stabilize Analog Stage
from A/D Off to A/D On(3)
—
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
3: Characterized by design but not tested.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 205
PIC32MX5XX/6XX/7XX
FIGURE 31-19:
A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)
AD50
ADCLK
Instruction
Execution
Set SAMP
Clear SAMP
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
AD61
AD60
TSAMP
AD55
AD55
CONV
ADxIF
Buffer(0)
Buffer(1)
1
2
3
4
5
6
7
8
5
6
7
8
– Software sets ADxCON. SAMP to start sampling.
1
2
– Sampling starts after discharge period. TSAMP is described in the “PIC32MX Family Reference Manual” (DS61132).
– Software clears ADxCON. SAMP to start conversion.
– Sampling ends, conversion sequence starts.
– Convert bit 9.
3
4
5
6
7
8
– Convert bit 8.
– Convert bit 0.
– One TAD for end of conversion.
DS61156C-page 206
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-20:
A/D CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)
AD50
ADCLK
Instruction
Execution
Set ADON
SAMP
ch0_dischrg
ch0_samp
ch1_dischrg
ch1_samp
eoc
TSAMP
TSAMP
AD55
AD55
TCONV
CONV
ADxIF
Buffer(0)
Buffer(1)
1
2
3
4
5
6
7
3
4
5
6
8
3
4
– Software sets ADxCON. ADON to start AD operation.
– Convert bit 0.
5
1
2
– Sampling starts after discharge period.
TSAMP is described in the “PIC32MX
Family Reference Manual” (DS61132).
– One TAD for end of conversion.
– Begin conversion of next channel.
6
7
8
– Sample for time specified by SAMC<4:0>.
– Convert bit 9.
– Convert bit 8.
3
4
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 207
PIC32MX5XX/6XX/7XX
FIGURE 31-21:
PARALLEL SLAVE PORT TIMING
CS
PS5
RD
PS6
WR
PS4
PS7
PMD<7:0>
PS1
PS3
PS2
TABLE 31-39: PARALLEL SLAVE PORT REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics(1)
Min.
Typical Max. Units
Conditions
PS1
TdtV2wrH Data In Valid before WR or CS Inactive
(setup time)
20
—
—
—
—
ns
ns
PS2
TwrH2dtI WR or CS Inactive to Data–In Invalid
(hold time)
40
PS3
PS4
TrdL2dtV RD and CS Active to Data–Out Valid
—
0
—
—
60
10
ns
ns
TrdH2dtI RD Activeor CS Inactive to Data–Out
Invalid
PS5
PS6
PS7
Tcs
CS Active Time
WR Active Time
RD Active Time
TPB + 40
TPB + 25
TPB + 25
—
—
—
—
—
—
ns
ns
ns
TWR
TRD
Note 1: These parameters are characterized, but not tested in manufacturing.
DS61156C-page 208
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-22:
PARALLEL MASTER PORT READ TIMING DIAGRAM
TPB
TPB
TPB
TPB
TPB
TPB
TPB
TPB
PB Clock
PM4
Address
PMA<13:18>
PMD<7:0>
PM6
Data
Address<7:0>
PM2
PM7
PM3
PMRD
PM5
PMWR
PM1
PMALL/PMALH
PMCS<2:1>
TABLE 31-40: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics(1)
Min.
Typical
Max.
Units
Conditions
PM1
PM2
TLAT
PMALL/PMALH Pulse Width
—
—
1 TPB
2 TPB
—
—
—
—
TADSU
Address Out Valid to PMALL/PMALH
Invalid (address setup time)
PM3
PM4
TADHOLD PMALL/PMALH Invalid to Address Out
Invalid (address hold time)
—
5
1 TPB
—
—
—
—
ns
TAHOLD
PMRD Inactive to Address Out Invalid
(address hold time)
PM5
PM6
TRD
PMRD Pulse Width
—
1 TPB
—
—
—
—
ns
TDSU
PMRD or PMENB Active to Data In
Valid (data setup time)
15
PM7
TDHOLD PMRD or PMENB Inactive to Data In
Invalid (data hold time)
—
80
—
ns
Note 1: These parameters are characterized, but not tested in manufacturing.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 209
PIC32MX5XX/6XX/7XX
FIGURE 31-23:
PARALLEL MASTER PORT WRITE TIMING DIAGRAM
TPB
TPB
TPB
TPB
TPB
TPB
TPB
TPB
PB Clock
Address
PMA<13:18>
PM2 + PM3
Address<7:0>
PMD<7:0>
Data
PM12
PM13
PMRD
PMWR
PM11
PM1
PMALL/PMALH
PMCS<2:1>
TABLE 31-41: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics(1)
PMWR Pulse Width
Min.
Typical Max.
Units
Conditions
PM11
TWR
—
—
1 TPB
2 TPB
—
—
—
—
PM12 TDVSU
Data Out Valid before PMWR or
PMENB goes Inactive (data setup time)
PM13 TDVHOLD PMWR or PMEMB Invalid to Data Out
Invalid (data hold time)
—
1 TPB
—
—
Note 1: These parameters are characterized, but not tested in manufacturing.
DS61156C-page 210
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-42: OTG ELECTRICAL SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
Param.
Symbol
No.
Characteristics(1)
USB Voltage
Min. Typical Max.
Units
Conditions
USB313 VUSB
3.0
—
3.6
V
Voltage on bus must
be in this range for
proper USB operation
USB315 VILUSB Input Low Voltage for USB Buffer
USB316 VIHUSB Input High Voltage for USB Buffer
—
2.0
—
—
—
—
—
0.8
—
V
V
V
V
USB318 VDIFS
USB319 VCM
Differential Input Sensitivity
0.2
2.5
Differential Common Mode Range
0.8
The difference
between D+ and D-
must exceed this value
while VCM is met
USB320 ZOUT
USB321 VOL
Driver Output Impedance
Voltage Output Low
28.0
0.0
—
—
44.0
0.3
V
14.25 k load
connected to 3.6V
USB322 VOH
Voltage Output High
2.8
—
3.6
V
14.25 k load
connected to ground
Note 1: These parameters are characterized, but not tested in manufacturing.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 211
PIC32MX5XX/6XX/7XX
FIGURE 31-24:
EJTAG TIMING CHARACTERISTICS
T
TCKeye
T
T
TCKlow
TCKhigh
T
rf
TCK
T
rf
TMS
TDI
T
T
T
Thold
rf
Tsetup
T
rf
TDO
TRST*
T
TRST*low
T
TDOout
T
TDOzstate
Undefined
Defined
T
rf
TABLE 31-43: EJTAG TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
Param.
No.
Symbol
Description(1)
TCK Cycle Time
Min.
Max. Units
Conditions
EJ1
TTCKCYC
TTCKHIGH
TTCKLOW
TTSETUP
25
10
10
5
—
—
—
—
ns
ns
ns
ns
EJ2
EJ3
EJ4
TCK High Time
TCK Low Time
TAP Signals Setup Time Before
Rising TCK
EJ5
EJ6
EJ7
TTHOLD
TAP Signals Hold Time After
Rising TCK
3
—
5
ns
ns
ns
TTDOOUT
TDO Output Delay Time From
Falling TCK
—
—
TTDOZSTATE TDO 3-State Delay Time From
Falling TCK
5
EJ8
EJ9
TTRSTLOW
TRF
TRST Low Time
25
—
—
—
ns
ns
TAP Signals Rise/Fall Time, All
Input and Output
Note 1: These parameters are characterized, but not tested in manufacturing.
DS61156C-page 212
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
32.0 PACKAGING INFORMATION
32.1 Package Marking Information
64-Lead TQFP (10x10x1 mm)
Example
PIC32MX575F
512H-80I/PT
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
e
3
0510017
100-Lead TQFP (14x14x1 mm)
Example
PIC32MX575F
512L-80I/PF
0510017
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
e
3
100-Lead TQFP (12x12x1 mm)
Example
PIC32MX575F
512L-80I/PT
0510017
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
e
3
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
e
3
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 213
PIC32MX5XX/6XX/7XX
32.1 Package Marking Information (Continued)
64-Lead QFN (9x9x0.9 mm)
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC32MX575F
512H-80I/MR
e
3
0510017
121-Lead XBGA (10x10x1.1 mm)
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC32MX575F
512H-80I/BG
e
3
0510017
DS61156C-page 214
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
32.2 Package Details
The following sections give the technical details of the packages.
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇMꢇꢘꢙꢚꢘꢙꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&
' ꢋꢄ( 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢏꢆꢌ4ꢆꢕꢈꢅ#ꢉꢆ*ꢃꢄꢕ!(ꢅꢏꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢒꢃꢌꢉꢋꢌꢍꢃꢏꢅꢂꢆꢌ4ꢆꢕꢃꢄꢕꢅꢗꢏꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢏ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢏꢁꢌꢋ'5ꢏꢆꢌ4ꢆꢕꢃꢄꢕ
D
D1
E
e
E1
N
b
1 2 3
NOTE 1
NOTE 2
α
A
c
φ
A2
A1
β
L
L1
6ꢄꢃ&!
ꢒꢚ77ꢚꢒ.ꢘ.ꢙꢗ
ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢅ7ꢃ'ꢃ&!
ꢒꢚ8
89ꢒ
;ꢔ
ꢓꢁ/ꢓꢅ1ꢗ+
M
ꢀꢁꢓꢓ
M
ꢒꢖ:
8"')ꢈꢉꢅꢋ%ꢅ7ꢈꢆ#!
7ꢈꢆ#ꢅꢂꢃ&ꢌꢍ
9 ꢈꢉꢆꢇꢇꢅ<ꢈꢃꢕꢍ&
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅꢘꢍꢃꢌ4ꢄꢈ!!
ꢗ&ꢆꢄ#ꢋ%%ꢅꢅ
3ꢋꢋ&ꢅ7ꢈꢄꢕ&ꢍ
8
ꢈ
ꢖ
ꢖꢎ
ꢖꢀ
7
M
ꢀꢁꢎꢓ
ꢀꢁꢓ/
ꢓꢁꢀ/
ꢓꢁꢜ/
ꢓꢁꢛ/
ꢓꢁꢓ/
ꢓꢁꢔ/
ꢓꢁ;ꢓ
3ꢋꢋ&ꢏꢉꢃꢄ&
3ꢋꢋ&ꢅꢖꢄꢕꢇꢈ
7ꢀ
ꢀ
ꢀꢁꢓꢓꢅꢙ.3
ꢐꢁ/ꢝ
ꢓꢝ
ꢜꢝ
9 ꢈꢉꢆꢇꢇꢅ?ꢃ#&ꢍ
9 ꢈꢉꢆꢇꢇꢅ7ꢈꢄꢕ&ꢍ
.
ꢑ
.ꢀ
ꢑꢀ
ꢌ
ꢀꢎꢁꢓꢓꢅ1ꢗ+
ꢀꢎꢁꢓꢓꢅ1ꢗ+
ꢀꢓꢁꢓꢓꢅ1ꢗ+
ꢀꢓꢁꢓꢓꢅ1ꢗ+
M
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅ?ꢃ#&ꢍ
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅ7ꢈꢄꢕ&ꢍ
7ꢈꢆ#ꢅꢘꢍꢃꢌ4ꢄꢈ!!
7ꢈꢆ#ꢅ?ꢃ#&ꢍ
ꢒꢋꢇ#ꢅꢑꢉꢆ%&ꢅꢖꢄꢕꢇꢈꢅꢘꢋꢏ
ꢒꢋꢇ#ꢅꢑꢉꢆ%&ꢅꢖꢄꢕꢇꢈꢅ1ꢋ&&ꢋ'
ꢓꢁꢓꢛ
ꢓꢁꢀꢜ
ꢀꢀꢝ
ꢓꢁꢎꢓ
ꢓꢁꢎꢜ
ꢀꢐꢝ
)
ꢁ
ꢓꢁꢎꢎ
ꢀꢎꢝ
ꢀꢎꢝ
ꢂ
ꢀꢀꢝ
ꢀꢐꢝ
' ꢋꢄꢊ(
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ +ꢍꢆ'%ꢈꢉ!ꢅꢆ&ꢅꢌꢋꢉꢄꢈꢉ!ꢅꢆꢉꢈꢅꢋꢏ&ꢃꢋꢄꢆꢇ,ꢅ!ꢃ-ꢈꢅ'ꢆꢊꢅ ꢆꢉꢊꢁ
ꢐꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢑꢀꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢒꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢓꢁꢎ/ꢅ''ꢅꢏꢈꢉꢅ!ꢃ#ꢈꢁ
ꢔꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢕꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢕꢅꢏꢈꢉꢅꢖꢗꢒ.ꢅ0ꢀꢔꢁ/ꢒꢁ
1ꢗ+2 1ꢆ!ꢃꢌꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢘꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢙ.32 ꢙꢈ%ꢈꢉꢈꢄꢌꢈꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢏ"ꢉꢏꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢒꢃꢌꢉꢋꢌꢍꢃꢏ ꢘꢈꢌꢍꢄꢋꢇꢋꢕꢊ ꢑꢉꢆ*ꢃꢄꢕ +ꢓꢔꢞꢓ@/1
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 215
PIC32MX5XX/6XX/7XX
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢎꢗꢇMꢇꢘꢙꢚꢘꢙꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&
' ꢋꢄ( 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢏꢆꢌ4ꢆꢕꢈꢅ#ꢉꢆ*ꢃꢄꢕ!(ꢅꢏꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢒꢃꢌꢉꢋꢌꢍꢃꢏꢅꢂꢆꢌ4ꢆꢕꢃꢄꢕꢅꢗꢏꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢏ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢏꢁꢌꢋ'5ꢏꢆꢌ4ꢆꢕꢃꢄꢕ
DS61156C-page 216
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
ꢘꢙꢙꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢌꢐꢇꢑꢒꢅꢆꢇꢓꢉꢅꢋꢔꢅꢍꢕꢇꢖꢈꢓꢗꢇMꢇꢘꢁꢚꢘꢁꢚꢘꢇꢛꢛꢇꢜ ꢆ!"ꢇ#$ꢙꢙꢇꢛꢛꢇ%ꢎꢑꢓꢈ&
' ꢋꢄ( 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢏꢆꢌ4ꢆꢕꢈꢅ#ꢉꢆ*ꢃꢄꢕ!(ꢅꢏꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢒꢃꢌꢉꢋꢌꢍꢃꢏꢅꢂꢆꢌ4ꢆꢕꢃꢄꢕꢅꢗꢏꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢏ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢏꢁꢌꢋ'5ꢏꢆꢌ4ꢆꢕꢃꢄꢕ
D
D1
e
E1
E
b
N
α
NOTE 1
1 23
NOTE 2
A
φ
c
A2
A1
β
L1
L
6ꢄꢃ&!
ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢅ7ꢃ'ꢃ&!
ꢒꢚ77ꢚꢒ.ꢘ.ꢙꢗ
89ꢒ
ꢒꢚ8
ꢒꢖ:
8"')ꢈꢉꢅꢋ%ꢅ7ꢈꢆ#!
7ꢈꢆ#ꢅꢂꢃ&ꢌꢍ
9 ꢈꢉꢆꢇꢇꢅ<ꢈꢃꢕꢍ&
8
ꢈ
ꢖ
ꢀꢓꢓ
ꢓꢁ/ꢓꢅ1ꢗ+
M
M
ꢀꢁꢎꢓ
ꢀꢁꢓ/
ꢓꢁꢀ/
ꢓꢁꢜ/
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅꢘꢍꢃꢌ4ꢄꢈ!!
ꢗ&ꢆꢄ#ꢋ%%ꢅꢅ
3ꢋꢋ&ꢅ7ꢈꢄꢕ&ꢍ
ꢖꢎ
ꢖꢀ
7
ꢓꢁꢛ/
ꢓꢁꢓ/
ꢓꢁꢔ/
ꢀꢁꢓꢓ
M
ꢓꢁ;ꢓ
3ꢋꢋ&ꢏꢉꢃꢄ&
3ꢋꢋ&ꢅꢖꢄꢕꢇꢈ
7ꢀ
ꢀ
ꢀꢁꢓꢓꢅꢙ.3
ꢐꢁ/ꢝ
ꢓꢝ
ꢜꢝ
9 ꢈꢉꢆꢇꢇꢅ?ꢃ#&ꢍ
9 ꢈꢉꢆꢇꢇꢅ7ꢈꢄꢕ&ꢍ
.
ꢑ
.ꢀ
ꢑꢀ
ꢌ
ꢀ;ꢁꢓꢓꢅ1ꢗ+
ꢀ;ꢁꢓꢓꢅ1ꢗ+
ꢀꢔꢁꢓꢓꢅ1ꢗ+
ꢀꢔꢁꢓꢓꢅ1ꢗ+
M
ꢒꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢕꢈꢅ?ꢃ#&ꢍ
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7ꢈꢆ#ꢅꢘꢍꢃꢌ4ꢄꢈ!!
7ꢈꢆ#ꢅ?ꢃ#&ꢍ
ꢒꢋꢇ#ꢅꢑꢉꢆ%&ꢅꢖꢄꢕꢇꢈꢅꢘꢋꢏ
ꢒꢋꢇ#ꢅꢑꢉꢆ%&ꢅꢖꢄꢕꢇꢈꢅ1ꢋ&&ꢋ'
ꢓꢁꢓꢛ
ꢓꢁꢀꢜ
ꢀꢀꢝ
ꢓꢁꢎꢓ
ꢓꢁꢎꢜ
ꢀꢐꢝ
)
ꢁ
ꢓꢁꢎꢎ
ꢀꢎꢝ
ꢀꢎꢝ
ꢂ
ꢀꢀꢝ
ꢀꢐꢝ
' ꢋꢄꢊ(
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ +ꢍꢆ'%ꢈꢉ!ꢅꢆ&ꢅꢌꢋꢉꢄꢈꢉ!ꢅꢆꢉꢈꢅꢋꢏ&ꢃꢋꢄꢆꢇ,ꢅ!ꢃ-ꢈꢅ'ꢆꢊꢅ ꢆꢉꢊꢁ
ꢐꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢑꢀꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢒꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢏꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢓꢁꢎ/ꢅ''ꢅꢏꢈꢉꢅ!ꢃ#ꢈꢁ
ꢔꢁ ꢑꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢕꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢕꢅꢏꢈꢉꢅꢖꢗꢒ.ꢅ0ꢀꢔꢁ/ꢒꢁ
1ꢗ+2 1ꢆ!ꢃꢌꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢘꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢙ.32 ꢙꢈ%ꢈꢉꢈꢄꢌꢈꢅꢑꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢏ"ꢉꢏꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢒꢃꢌꢉꢋꢌꢍꢃꢏ ꢘꢈꢌꢍꢄꢋꢇꢋꢕꢊ ꢑꢉꢆ*ꢃꢄꢕ +ꢓꢔꢞꢀꢀꢓ1
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 217
PIC32MX5XX/6XX/7XX
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DS61156C-page 218
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
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2010 Microchip Technology Inc.
Preliminary
DS61156C-page 219
PIC32MX5XX/6XX/7XX
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DS61156C-page 220
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 221
PIC32MX5XX/6XX/7XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS61156C-page 222
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 223
PIC32MX5XX/6XX/7XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS61156C-page 224
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 225
PIC32MX5XX/6XX/7XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS61156C-page 226
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
A.3
Pin Assignments
APPENDIX A: MIGRATING FROM
PIC32MX3XX/4XX TO
PIC32MX5XX/6XX/7XX
DEVICES
PIC32MX5XX/6XX/7XX devices have the same pin
assignment for peripherals as PIC32MX4XX devices
with the following exceptions:
• Pins associated with the UART1 and UART2
modules on PIC32MX4XX devices are now
associated with the UART1A and UART3A
modules, respectively on PIC32MX5XX/6XX/7XX
devices
This appendix provides an overview of considerations
for migrating from PIC32MX3XX/4XX devices to the
PIC32MX5XX/6XX/7XX family of devices. The code
developed for the PIC32MX3XX/4XX devices can be
ported to the PIC32MX5XX/6XX/7XX devices after
making the appropriate changes outlined below.
• Pins associated with the SPI2 module on
PIC32MX4XX devices are now associated with
the SPI2A module on PIC32MX5XX/6XX/7XX
devices
A.1
DMA
PIC32MX5XX/6XX/7XX devices do not support
stopping DMA transfers in Idle mode.
A.2
Interrupts
PIC32MX5XX/6XX/7XX devices have persistent inter-
rupts for some of the peripheral modules. This means
that the interrupt condition for these peripherals must
be cleared before the interrupt flag can be cleared.
For example, to clear a UART receive interrupt, the
user application must first read the UART Receive reg-
ister to clear the interrupt condition and then clear the
associated UxIF flag to clear the pending UART inter-
rupt. In other words, the UxIF flag cannot be cleared by
software until the UART Receive register is read.
Table A-1 outlines the peripherals and associated
interrupts that are implemented differently on
PIC32MX5XX/6XX/7XX versus PIC32MX3XX/4XX
devices.
In addition, on the SPI module, the IRQ numbers for the
receive done interrupts were changed from 25 to 24
and the transfer done interrupts were changed from 24
to 25.
TABLE A-1:
PIC32MX3XX/4XX vs. PIC32MX5XX/6XX/7XX INTERRUPT IMPLEMENTATION
DIFFERENCES
Module
Interrupt Implementation
Input Capture
To clear an interrupt source, read the Buffer Result (ICxBUF) register to obtain the number of
capture results in the buffer that are below the interrupt threshold (specified by ICI<1:0> bits).
SPI
Receive and transmit interrupts are controlled by the SRXISEL<1:0> and STXISEL<1:0> bits,
respectively. To clear an interrupt source, data must be written to, or read from, the SPIxBUF
register to obtain the number of data to receive/transmit below the level specified by the
SRXISEL<1:0> and STXISEL<1:0> bits.
UART
TX interrupt will be generated as soon as the UART module is enabled.
Receive and transmit interrupts are controlled by the URXISEL<1:0> and UTXISEL<1:0> bits,
respectively. To clear an interrupt source, data must be read from, or written to, the UxRXREG or
UxTXREG registers to obtain the number of data to receive/transmit below the level specified by
the URXISEL<1:0> and UTXISEL<1:0> bits.
ADC
PMP
All samples must be read from the result registers (ADC1BUFx) to clear the interrupt source.
To clear an interrupt source, read the Parallel Master Port Data Input/Output (PMDIN/PMDOUT)
register.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 227
PIC32MX5XX/6XX/7XX
Revision B (November 2009)
APPENDIX B: REVISION HISTORY
The revision includes the following global update:
Revision A (August 2009)
• Added Note 2 to the shaded table that appears at
the beginning of each chapter. This new note
provides information regarding the availability of
registers and their associated bits
This is the initial revision of this document.
Other major changes are referenced by their respective
chapter/section in Table B-1.
TABLE B-1:
MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, USB, CAN and Added the following devices:
Ethernet 32-Bit Flash
Microcontrollers”
- PIC32MX575F256L
- PIC32MX695F512L
- PIC32MX695F512H
The 100-pin TQFP pin diagrams have been updated to reflect the current pin
name locations (see the “Pin Diagrams” section).
Added the 121-pin Ball Grid Array (XBGA) pin diagram.
Updated Table 1: “PIC32MX Features”
Added the following tables:
- Table 2: “Pin Names: PIC32MX575F256L and PIC32MX575F512L
Devices”,
- Table 3: “Pin Names: PIC32MX675F256L, PIC32MX675F512L and
PIC32MX695F512L Devices”
- Table 4: “Pin Names: PIC32MX775F256L, PIC32MX775F512L,
PIC32MX795F512L and Devices”
Updated the following pins as 5V tolerant:
- 64-pin QFN: Pin 36 (D-/RG3) and Pin 37 (D+/RG2)
- 64-pin TQFP: Pin 36 (D-/RG3) and Pin 37 (D+/RG2)
- 100-pin TQFP: Pin 56 (D-/RG3) and Pin 57 (D+/RG2)
Section 2.0 “Guidelines for Getting Removed the last sentence of Section 2.3.1 “Internal Regulator Mode”.
Started with 32-Bit
Microcontrollers”
Removed Section 2.3.2 “External Regulator Mode”
DS61156C-page 228
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE B-1:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
Section 4.0 “Memory
Organization”
Updated all register tables to include the Virtual Address and All Resets
columns.
Updated the title of Figure 4-1 to include the PIC32MX575F256L device.
Updated the title of Figure 4-3 to include the PIC32MX695F512L and
PIC32MX695F512H devices. Also changed PIC32MX795F512L to
PIC32MX795F512H.
Updated the title of Table 4-3 to include the PIC32MX695F512H device.
Updated the title of Table 4-5 to include the PIC32MX575F5256L device.
Updated the title of Table 4-6 to include the PIC32MX695F512L device.
Reversed the order of Table 4-11 and Table 4-12.
Reversed the order of Table 4-14 and Table 4-15.
Updated the title of Table 4-15 to include the PIC32MX575F256L and
PIC32MX695F512L devices.
Updated the title of Table 4-45 to include the PIC32MX575F256L device.
Updated the title of Table 4-47 to include the PIC32MX695F512H and
PIC32MX695F512L devices.
Section 12.0 “I/O Ports”
Updated the second paragraph of Section 12.1.2 “Digital Inputs” and
removed Table 12-1.
Section 22.0 “10-Bit Analog-to-
Digital Converter (ADC)”
Updated the ADC Conversion Clock Period Block Diagram (see Figure 22-2).
Section 28.0 “Special Features”
Removed references to the ENVREG pin in Section 28.3 “On-Chip Voltage
Regulator”.
Updated the first sentence of Section 28.3.1 “On-Chip Regulator and
POR” and Section 28.3.2 “On-Chip Regulator and BOR”.
Updated the Connections for the On-Chip Regulator (see Figure 28-2).
Updated the Absolute Maximum Ratings and added Note 3.
Section 31.0 “Electrical
Characteristics”
Added Thermal Packaging Characteristics for the 121-pin XBGA package
(see Table 31-3).
Updated the Operating Current (IDD) DC Characteristics (see Table 31-5).
Updated the Idle Current (IIDLE) DC Characteristics (see Table 31-6).
Updated the Power-Down Current (IPD) DC Characteristics (see Table 31-7).
Removed Note 1 from the Program Flash Memory Wait State Characteristics
(see Table 31-11).
Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics,
changing SP52 to SP35 between the MSb and Bit 14 on SDOx (see
Figure 31-13).
Section 32.0 “Packaging
Information”
Added the 121-pin XBGA package marking information and package details.
“Product Identification System”
Added the definition for BG (121-lead 10x10x1.1 mm, XBGA).
Added the definition for Speed.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 229
PIC32MX5XX/6XX/7XX
Revision C (February 2010)
The revision includes the following updates, as
described in Table B-2:
TABLE B-2:
MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, USB, CAN Added the following devices:
and Ethernet 32-Bit Flash
Microcontrollers”
• PIC32MX675F256H
• PIC32MX775F256H
• PIC32MX775F512H
• PIC32MX675F256L
• PIC32MX775F256L
• PIC32MX775F512L
Added the following pins:
• EREFCLK
• ECRSDV
• AEREFCLK
• AECRSDV
Added the EREFCLK and ECRSDV pins to Table 3 and Table 4.
Section 1.0 “Device Overview” Updated the pin number pinout I/O descriptions for the following pin names in
Table 1-1:
• SCL1A
• SDA1A
• SCL2
• TMS
• C1IN-
• C1IN+
• C1OUT
• C2IN-
• C2IN+
• C2OUT
• PMA0
• PMA1
• TCK
• TDI
• SDA2
• TDO
• SCL2A
• SDA2A
• SCL3A
• SDA3A
• RTCC
• CVREF-
• CVREF+
• CVREFOUT
Added the following pins to the Pinout I/O Descriptions table (Table 1-1):
• EREFCLK
• ECRSDV
• AEREFCLK
• AECRSDV
DS61156C-page 230
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE B-2:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
Section 4.0 “Memory
Organization”
Added new devices and updated the virtual and physical memory map values in
Figure 4-1.
Added new devices to Figure 4-2.
Added new devices to the following register maps:
• Table 4-3, Table 4-4, Table 4-6 and Table 4-7 (Interrupt Register Maps)
• Table 4-12 (I2C2 Register Map)
• Table 4-15 (SPI1 Register Map)
• Table 4-24 through Table 4-35 (PORTA-PORTG Register Maps)
• Table 4-36 and Table 4-37 (Change Notice and Pull-up Register Maps)
• Table 4-45 (CAN1 Register Map)
• Table 4-46 (CAN2 Register Map)
• Table 4-47 (Ethernet Controller Register Map)
Changed the bits named POSCMD to POSCMOD in Table 4-42 (Device
Configuration Word Summary).
Section 28.0 “Special
Features”
Changed all references of POSCMD to POSCMOD in the Device Configuration
Word 1 register (see Register 28-2).
Appendix A: “Migrating from
PIC32MX3XX/4XX to
PIC32MX5XX/6XX/7XX
Devices”
Added the new section A.3 “Pin Assignments”.
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 231
PIC32MX5XX/6XX/7XX
NOTES:
DS61156C-page 232
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
INDEX
A
D
AC Characteristics ............................................................ 180
10-Bit Conversion Rate Parameters ......................... 204
A/D Conversion Requirements ................................. 205
ADC Specifications ................................................... 202
EJTAG Timing Requirements ................................... 212
Ethernet .................................................................... 201
Internal FRC Accuracy.............................................. 182
Internal RC Accuracy................................................ 182
OTG Electrical Specifications ................................... 211
Parallel Master Port Read Requirements ................. 209
Parallel Master Port Write......................................... 210
Parallel Master Port Write Requirements.................. 210
Parallel Slave Port Requirements............................. 208
PLL Clock Timing...................................................... 182
Assembler
DC Characteristics............................................................ 172
I/O Pin Input Specifications ...................................... 176
I/O Pin Output Specifications.................................... 177
Idle Current (IIDLE).................................................... 174
Operating Current (IDD) ............................................ 173
Power-Down Current (IPD)........................................ 175
Program Memory...................................................... 177
Temperature and Voltage Specifications.................. 172
Development Support....................................................... 167
Direct Memory Access (DMA) Controller.......................... 117
E
Electrical Characteristics .................................................. 171
AC............................................................................. 180
Errata.................................................................................. 21
Ethernet Controller............................................................ 145
External Clock
MPASM Assembler................................................... 168
B
Timer1 Timing Requirements ................................... 186
Timer2, 3, 4, 5 Timing Requirements ....................... 187
Timing Requirements ............................................... 181
Block Diagrams
A/D Module ............................................................... 141
Comparator I/O Operating Modes............................. 147
Comparator Voltage Reference ................................ 149
Connections for On-Chip Voltage Regulator............. 162
Core and Peripheral Modules ..................................... 23
DMA.......................................................................... 117
Ethernet Controller.................................................... 145
I2C Circuit ................................................................. 134
Input Capture ............................................................ 127
Interrupt Controller.................................................... 109
JTAG Programming, Debugging and
Trace Ports ....................................................... 163
MCU............................................................................ 39
Output Compare Module........................................... 129
PIC32MX CAN Module ............................................. 143
PMP Pinout and Connections to External
F
Flash Program Memory.................................................... 105
RTSP Operation ....................................................... 105
I
I/O Ports ........................................................................... 121
Parallel I/O (PIO) ...................................................... 122
Instruction Set................................................................... 165
Inter-Integrated Circuit (I2C .............................................. 133
Internal Voltage Reference Specifications........................ 179
Interrupt Controller............................................................ 109
IRG, Vector and Bit Location.................................... 110
M
MCU
Devices............................................................. 137
Prefetch Module........................................................ 115
Reset System............................................................ 107
RTCC........................................................................ 139
SPI Module ............................................................... 131
Timer1....................................................................... 123
Timer2/3/4/5 (16-Bit)................................................. 125
Typical Multiplexed Port Structure ............................ 121
UART ........................................................................ 135
WDT and Power-up Timer ........................................ 161
Brown-out Reset (BOR)
Architecture Overview ................................................ 40
Coprocessor 0 Registers............................................ 42
Core Exception Types ................................................ 43
EJTAG Debug Support............................................... 44
Power Management ................................................... 44
MCU Module....................................................................... 39
Memory Maps............................................................... 46–48
Memory Organization ......................................................... 45
Layout......................................................................... 45
Migration
PIC32MX3XX/4XX to PIC32MX5XX/6XX/7XX......... 227
MPLAB ASM30 Assembler, Linker, Librarian................... 168
MPLAB Integrated Development
and On-Chip Voltage Regulator................................ 162
C
Environment Software .............................................. 167
MPLAB PM3 Device Programmer .................................... 170
MPLAB REAL ICE In-Circuit Emulator System ................ 169
MPLINK Object Linker/MPLIB Object Librarian................ 168
C Compilers
MPLAB C18 .............................................................. 168
Clock Diagram .................................................................. 113
Comparator
Specifications............................................................ 178
Comparator Module .......................................................... 147
Comparator Voltage Reference (CVREF ........................... 149
Configuration Bit ............................................................... 153
Controller Area Network (CAN)......................................... 143
CPU Module........................................................................ 35
O
Open-Drain Configuration................................................. 122
Oscillator Configuration .................................................... 113
Output Compare ............................................................... 129
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 233
PIC32MX5XX/6XX/7XX
Timing Requirements
P
CLKO and I/O ........................................................... 183
Timing Specifications
Packaging .........................................................................213
Details.......................................................................215
Marking .....................................................................213
Parallel Master Port (PMP) ...............................................137
PIC32MX Family USB Interface Diagram .........................120
Pinout I/O Descriptions (table) ............................................24
Power-on Reset (POR)
and On-Chip Voltage Regulator................................162
Power-Saving Features.....................................................151
CPU Halted Methods ................................................151
Operation ..................................................................151
with CPU Running.....................................................151
Prefetch Cache .................................................................115
Program Flash Memory
CAN I/O Requirements............................................. 200
I2Cx Bus Data Requirements (Master Mode)........... 195
I2Cx Bus Data Requirements (Slave Mode)............. 198
Input Capture Requirements..................................... 187
Output Compare Requirements................................ 188
Simple OCx/PWM Mode Requirements ................... 188
SPIx Master Mode (CKE = 0) Requirements............ 189
SPIx Master Mode (CKE = 1) Requirements............ 190
SPIx Slave Mode (CKE = 1) Requirements.............. 192
SPIx Slave Mode Requirements (CKE = 0).............. 191
U
UART................................................................................ 135
USB On-The-Go (OTG).................................................... 119
Wait State Characteristics.........................................178
R
V
Real-Time Clock and Calendar (RTCC)............................139
Register Maps............................................................. 49–103
Registers
VCAP/VDDCORE pin............................................................ 162
Voltage Reference Specifications..................................... 179
Voltage Regulator (On-Chip) ............................................ 162
DDPCON (Debug Data Port Control)........................164
DEVCFG0 (Device Configuration Word 0.................153
DEVCFG1 (Device Configuration Word 1.................155
DEVCFG2 (Device Configuration Word 2.................157
DEVCFG3 (Device Configuration Word 3.................159
DEVID (Device and Revision ID) ..............................160
Resets...............................................................................107
Revision History ................................................................228
W
Watchdog Timer (WDT).................................................... 161
WWW, On-Line Support ..................................................... 21
S
Serial Peripheral Interface (SPI) .......................................131
Software Simulator (MPLAB SIM).....................................169
Special Features ...............................................................153
T
Timer1 Module ..................................................................123
Timer2/3, Timer4/5 Modules .............................................125
Timing Diagrams
10-Bit A/D Conversion (CHPS = 01, SIMSAM = 0,
ASAM = 0, SSRC = 000) ..................................206
10-Bit A/D Conversion (CHPS = 01, SIMSAM = 0,
ASAM = 1, SSRC = 111, SAMC = 00001)........207
CAN I/O.....................................................................200
EJTAG ......................................................................212
External Clock...........................................................180
I/O Characteristics ....................................................183
I2Cx Bus Data (Master Mode) ..................................194
I2Cx Bus Data (Slave Mode) ....................................197
I2Cx Bus Start/Stop Bits (Master Mode)...................194
I2Cx Bus Start/Stop Bits (Slave Mode).....................197
Input Capture (CAPx)................................................187
OCx/PWM .................................................................188
Output Compare (OCx).............................................188
Parallel Master Port Read.........................................209
Parallel Master Port Write .........................................210
Parallel Slave Port ....................................................208
SPIx Master Mode (CKE = 0)....................................189
SPIx Master Mode (CKE = 1)....................................190
SPIx Slave Mode (CKE = 0)......................................191
SPIx Slave Mode (CKE = 1)......................................192
Timer1, 2, 3, 4, 5 External Clock...............................186
UART Reception.......................................................136
UART Transmission (8-Bit or 9-Bit Data)..................136
DS61156C-page 234
Preliminary
2010 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Example:
PIC32 MX 5XX F 512 H T - 80 I / PT - XXX
PIC32MX575F256H-80I/PT:
General purpose PIC32MX,
256 KB program memory,
64-pin, Industrial temperature,
TQFP package.
Microchip Brand
Architecture
Product Groups
Flash Memory Family
Program Memory Size (KB)
Pin Count
Tape and Reel Flag (if applicable)
Speed
Temperature Range
Package
Pattern
Flash Memory Family
Architecture
MX = 32-bit RISC MCU core
Product Groups
5XX = General purpose microcontroller family
6XX = General purpose microcontroller family
7XX = General purpose microcontroller family
Flash Memory Family
F
= Flash program memory
Program Memory Size 256 = 256K
512 = 512K
Pin Count
H
L
= 64-pin
= 100-pin
Speed
80 = 80 MHz
Temperature Range
Package
I
= -40°C to +85°C (Industrial)
PT = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack)
PT = 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack)
PF = 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack)
MR = 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat)
BG = 121-Lead (10x10x1.1 mm) XBGA (Plastic Thin Profile Ball Grid Array)
Pattern
Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise)
ES = Engineering Sample
2010 Microchip Technology Inc.
Preliminary
DS61156C-page 235
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Boston
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Cleveland
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/05/10
DS61156C-page 236
Preliminary
2010 Microchip Technology Inc.
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