PL123E-05HSC [MICROCHIP]

PL123 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8;
PL123E-05HSC
型号: PL123E-05HSC
厂家: MICROCHIP    MICROCHIP
描述:

PL123 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8

驱动 光电二极管 输出元件 逻辑集成电路
文件: 总10页 (文件大小:307K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
(Preliminary)PL123E-05  
Low Skew Zero Delay Buffer  
FEATURES  
DESCRIPTION  
The PL123E-05 (-05H for High Drive) is a high perfor-  
mance, low skew, low jitter zero delay buffer designed  
to distribute high speed clocks. It has five low-skew  
outputs that are synchronized with the input. The syn-  
chronization is established via CLKOUT feed back to  
the input of the PLL. Since the skew between the input  
and output is less than 100ps, the device acts as a  
zero delay buffer. The input output propagation delay  
can be advanced or delayed by adjusting the load on  
the CLKOUT pin.  
Frequency Range 10MHz to 220MHz  
Zero input - output delay.  
Low output-to-output skew.  
Optional Drive Strength:  
Standard (8mA) PL123E-05  
High (12mA)  
PL123E-05H  
2.5V or 3.3V, ±10% operation.  
Available in 8-pin SOP packaging.  
These parts are not intended for 5V input-tolerant ap-  
plications.  
PIN CONFIGURATION  
REF  
CLK2  
CLK1  
GND  
1
2
3
4
8
7
6
5
CLKOUT  
CLK4  
VDD  
CLK3  
SOP-8L  
BLOCK DIAGRAM  
REF  
CLKOUT  
CLK1  
PLL  
CLK2  
CLK3  
CLK4  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 1  
(Preliminary)PL123E-05  
Low Skew Zero Delay Buffer  
PIN DESCRIPTION  
Package Type  
Name  
Type  
Description  
SOP-8L  
REF[1]  
CLK2[2]  
CLK1[2]  
GND  
1
2
3
4
5
6
7
8
I
Input reference frequency.  
O
O
P
O
P
O
O
Buffered clock output.  
Buffered clock output.  
Ground connection.  
CLK3[2]  
Buffered clock output.  
VDD  
VDD connection.  
CLK4[2]  
CLKOUT[2,3]  
Buffered clock output.  
Buffered clock output. Internal feed back on this pin.  
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs.  
3. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the  
skew between the reference and output.  
INPUT / OUTPUT SKEW CONTROL  
The PL123E-05 will achieve Zero Delay from input to output when all the outputs are loaded equally. Adjust-  
ments to the input/output delay can be made by adjusting the loading on the CLKOUT pin.  
Please contact Micrel for more information.  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 2  
(Preliminary)PL123E-05  
Low Skew Zero Delay Buffer  
LAYOUT RECOMMENDATIONS  
The following guidelines are to assist you with a performance optimized PCB design:  
Signal Integrity and Termination  
Considerations  
Decoupling and Power Supply  
Considerations  
- Keep traces short!  
- Place decoupling capacitors as close as possible to  
the VDD pin(s) to limit noise from the power supply  
- Trace = Inductor. With a capacitive load this  
equals ringing!  
- Addition of a ferrite bead in series with VDD can  
help prevent noise from other board sources  
- Long trace = Transmission Line. Without proper  
termination this will cause reflections ( looks like  
ringing ).  
- Value of decoupling capacitor is frequency de-  
pendant. Typical values to use are 0.1F for de-  
signs using frequencies < 50MHz and 0.01F for  
designs using frequencies > 50MHz.  
- Design long traces as “striplines” or “microstrips”  
with defined impedance.  
- Match trace at one side to avoid reflections bounc-  
ing back and forth.  
Typical CMOS termination  
Place Series Resistor as close as possible to CMOS output  
CMOS Output Buffer  
( Typical buffer impedance 20   
To CMOS Input  
50line  
Connect a 33 series  
resistor at each of the output  
clocks to enhance the  
stability of the output signal  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 3  
(Preliminary)PL123E-05  
Low Skew Zero Delay Buffer  
Absolute Maximum Conditions  
Supply Voltage to Ground Potential ...... 0.5V to 4.6V  
DC Input Voltage.............................VSS 0.5V to 4.6V  
Storage Temperature ......................... 65°C to 150°C  
Junction Temperature ....................................... 150°C  
Static Discharge Voltage  
(per MIL-STD-883, Method 3015)………………> 2000V  
Operating Condition  
Description  
Parameter  
Min  
Max  
3.63  
30  
Unit  
V
Supply Voltage  
VDD  
2.25  
[4]  
Load Capacitance, <100 MHz, 3.3V  
CL  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
MHz  
MHz  
Load Capacitance, <100 MHz, 2.5V with High Drive  
Load Capacitance, <133.3 MHz, 3.3V  
Load Capacitance, <133.3 MHz, 2.5V with High Drive  
Load Capacitance, <133.3 MHz, 2.5V with Standard Drive  
Load Capacitance, >133.3 MHz, 3.3V  
Load Capacitance, >133.3 MHz, 2.5V with High Drive  
Input Capacitance[5]  
30  
22  
22  
15  
15  
15  
CIN  
5
Closed-loop bandwidth (typical), 3.3V  
Closed-loop bandwidth (typical), 2.5V  
Output Impedance (typical), 3.3V High Drive  
Output Impedance (typical), 3.3V Standard Drive  
Output Impedance (typical), 2.5V High Drive  
Output Impedance (typical), 2.5V Standard Drive  
BW  
1
0.5  
23  
33  
26  
39  
ROUT  
Power-up time for all VDD’s to reach minimum specified  
voltage (power ramps must be monotonic)  
tPU  
0.01  
250  
ms  
Notes:  
4. Applies to Test Circuit #1.  
5. Applies to both REF Clock and internal feedback path on CLKOUT.  
6. Theta Ja, EIA JEDEC 51 test board conditions, 2S2P; Theta Jc Mil-Spec 883E Method 1012.1.  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 4  
(Preliminary)PL123E-05  
Low Skew Zero Delay Buffer  
3.3V DC Electrical Specifications  
Description  
Parameter  
Test Conditions  
Min  
Max  
Unit  
Supply Voltage  
VDD  
2.97  
3.63  
V
Input LOW Voltage  
Input HIGH Voltage  
Input Leakage Current  
Input HIGH Current  
VIL  
VIH  
IIL  
2.5  
0.8  
VDD + 0.3  
±10  
V
V
0 < VIN < VIL  
VIN = VDD  
µA  
µA  
IIH  
100  
V
V
IOL = 8 mA (Standard Drive)  
IOL = 12 mA (High Drive)  
0.4  
0.4  
Output LOW Voltage  
VOL  
V
V
IOH = 8 mA (Standard Drive)  
IOH = 12 mA (High Drive)  
2.4  
2.4  
Output HIGH Voltage  
Supply Current  
VOH  
IDD  
Unloaded outputs, 66-MHz REF  
45  
mA  
2.5V DC Electrical Specifications  
Description  
Parameter  
Test Conditions  
Min  
2.25  
Max  
2.75  
Unit  
V
Supply Voltage  
VDD  
VIL  
VIH  
IIL  
Input LOW Voltage  
Input HIGH Voltage  
Input Leakage Current  
Input HIGH Current  
0.7  
V
1.7  
VDD + 0.3  
10  
V
0<VIN < VDD  
VIN = VDD  
µA  
µA  
IIH  
100  
IOL = 8 mA (Standard Drive)  
IOL = 12 mA (High Drive)  
0.5  
0.5  
Output LOW Voltage  
VOL  
V
IOH = 8 mA (Standard Drive)  
IOH = 12 mA (High Drive)  
VDD 0.6  
VDD 0.6  
Output HIGH Voltage  
Supply Current  
VOH  
IDD  
V
Unloaded outputs, 66-MHz REF  
30  
mA  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 5  
(Preliminary)PL123E-05  
Low Skew Zero Delay Buffer  
3.3V and 2.5V AC Electrical Specifications  
Description  
Parameter Test Conditions  
Min  
10  
10  
10  
10  
25  
40  
47  
45  
Typ  
Max Unit  
220 MHz  
167 MHz  
200 MHz  
134 MHz  
3.3V High Drive  
Maximum Frequency[7]  
(Input/Output)  
3.3V Standard Drive  
1/t1  
2.5V High Drive  
2.5V Standard Drive  
<133.3 MHz  
TIDC  
75  
60  
53  
55  
%
%
Input Duty Cycle  
(PLL Mode only)  
>133.3 MHz  
<133.3 MHz  
t2 ÷ t1  
%
Output Duty Cycle[8]  
>133.3 MHz  
%
Standard Drive, CL = 30pF, <100 MHz  
1.6  
1.6  
0.6  
1.2  
1.2  
0.5  
1.5  
2.1  
1.3  
1.2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ps  
ps  
ps  
Standard Drive, CL = 22pF, <133.3 MHz  
Standard Drive, CL = 15pF, <167 MHz  
High Drive, CL = 30pF, <100 MHz  
High Drive, CL = 22pF, <133.3 MHz  
High Drive, CL = 15pF, >133.3 MHz  
Standard Drive, CL = 15pF, <133.33 MHz  
High Drive, CL = 30pF, <100 MHz  
High Drive, CL = 22pF, <133.3 MHz  
High Drive, CL = 15pF, >133.3 MHz  
All outputs equally loaded  
Rise, Fall Time (3.3V)[8]  
t3,t4  
Rise, Fall Time (2.5V)[8]  
t3, t4  
[8]  
Output to Output Skew  
t5  
t6  
100  
100  
200  
PLL enabled @ 3.3V  
100  
200  
Delay, REF Rising Edge  
to CLKOUT Rising Edge[8]  
PLL enabled @2.5V  
Measured at VDD/2.  
±150  
±300  
1.0  
ps  
ps  
Any output to any output, 3.3V supply  
Part to Part Skew[8]  
PLL Lock Time[8]  
t7  
Measured at VDD/2.  
Any output to any output, 2.5V supply  
Stable power supply, valid clocks pre-  
sented on REF and CLKOUT pins  
tLOCK  
ms  
3.3V, >66 MHz, <15pF  
55  
125  
100  
100  
80  
ps  
ps  
ps  
ps  
ps  
ps  
3.3V, >66 MHz, <30pF, Standard. Drive  
3.3V, >66 MHz, <30pF, High Drive  
2.5V, >66 MHz, <15pF, Standard. Drive  
2.5V, >66 MHz, <15pF, High Drive  
2.5V, >66 MHz, <30pF, High Drive  
Cycle-to-Cycle Jitter,  
Peak[8,9]  
TJCC  
125  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 6  
(Preliminary)PL123E-05  
Low Skew Zero Delay Buffer  
3.3V and 2.5V AC Electrical Specifications (continued)  
Description  
Parameter Test Conditions  
3.3V, 66100 MHz, <15 pF  
Min  
Typ  
Max  
Unit  
60  
ps  
3.3V, >100 MHz, <15 pF  
35  
75  
70  
60  
60  
45  
ps  
ps  
ps  
ps  
ps  
ps  
3.3V, >66 MHz, <30 pF, Standard Drive  
3.3V, >66 MHz, <30 pF, High Drive  
2.5V, >66 MHz, <15 pF, Standard. Drive  
2.5V, 66100 MHz, <15 pF, High Drive  
2.5V, >100 MHz, <15 pF, High Drive  
Period Jitter,  
Peak[8,9]  
TPER  
Notes:  
7. For the given maximum loading conditions. See CL in Operating Conditions Table.  
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.  
9. Typical jitter is measured at 3.3V or 2.5V, 29°C, with all outputs driven into the maximum specified load.  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 7  
(Preliminary)PL123E-05  
Low Skew Zero Delay Buffer  
SWITCHING WAVEFORMS  
Duty Cycle Timing  
t1  
t2  
VDD/2  
VDD/2  
OUTPUT  
All Outputs Rise/Fall Time  
2.0V(1.8V)  
3.3V (2.5V)  
0V  
2.0V(1.8V)  
0.8V(0.6V)  
t3  
0.8V(0.6V)  
t4  
Output-Output Skew  
OUTPUT  
VDD/2  
OUTPUT  
VDD/2  
t5  
Input-Output Propagation Delay  
INPUT  
VDD/2  
CLKOUT  
VDD/2  
t6  
Device-Device Skew  
Any Output, Part 1 or 2  
Any Output, Part 1 or 2  
VDD/2  
VDD/2  
t7  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 8  
(Preliminary)PL123E-05  
Low Skew Zero Delay Buffer  
TEST CIRCUITS  
Test Circuit #1  
VDD  
0.1 F  
0.1 F  
CLK  
OUTPUTS  
VDD  
CLOAD  
GND  
GND  
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)  
Recommended Land Pattern (MM)  
3.80 REF  
SOP-8L  
Dimension (MM)  
Symbol  
E
H
Min  
1.35  
0.10  
1.25  
0.33  
0.19  
4.80  
3.80  
5.80  
0.40  
Max  
1.75  
0.25  
1.50  
0.53  
0.27  
5.00  
4.00  
6.20  
0.89  
A
A1  
A2  
b
6.985  
±0.050  
DDD  
2.31  
±0.05  
4.65 REF  
C
C
D
L
2.40 REF  
E
A2  
H
A
A1  
L
1.27  
Nom  
0.53  
±0.05  
1.27 BSC  
e
e
b
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 9  
(Preliminary)PL123E-05  
Low Skew Zero Delay Buffer  
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)  
For part ordering, please contact our Sales Department:  
2180 Fortune Drive, San Jose, CA 95131, USA  
Tel: (408) 944-0800 Fax: (408) 474-1000  
PART NUMBER  
The order number for this device is a combination of the following:  
Part number, Package type and Operating temperature range  
PL123E-05(H) S X - X  
Part Number  
H=High Drive  
None=Tubes  
R=Tape & Reel  
None = Standard Drive  
Temperature Range  
C=Commercial (0°C to 70°C)  
I=Industrial (-40°C to 85°C)  
Package Type  
S=SOP  
Part/Order Number  
Marking*  
Package Option  
P123E05  
SC  
LLLLL  
P123E05H  
SC  
LLLLL  
P123E05  
SI  
LLLLL  
P123E05H  
SI  
PL123E-05SC  
PL123E-05SC-R  
PL123E-05HSC  
PL123E-05HSC-R  
PL123E-05SI  
8-Pin SOP Tube  
8-Pin SOP (Tape and Reel)  
8-Pin SOP Tube  
8-Pin SOP (Tape and Reel)  
8-Pin SOP Tube  
PL123E-05SI-R  
PL123E-05HSI  
8-Pin SOP (Tape and Reel)  
8-Pin SOP Tube  
PL123E-05HSI-R  
*Note: LLLLL designates lot number  
8-Pin SOP (Tape and Reel)  
LLLLL  
Micrel Inc., reserves the right to make changes in its products or specif ications, or both at any time without notice. The information furnished by Micrel  
is believed to be accurate and reliable. However, Micrel makes no guarantee or warranty concerning the accuracy of said info rmation and shall not be  
responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.  
LIFE SUPPORT POLICY: Micrel’s products are not authorized for use as critical components in life support devices or systems without the express  
written approval of the President of Micrel Inc.  
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 10  

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