PL611S-26-XXXGI [MICROCHIP]
IC,FREQUENCY SYNTHESIZER,LLCC,6PIN,PLASTIC;
| 型号： | PL611S-26-XXXGI |
| 厂家： | 
MICROCHIP |
| 描述： | IC,FREQUENCY SYNTHESIZER,LLCC,6PIN,PLASTIC 光电二极管 |
| 文件： | 总8页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.8V-3.3V PicoPLLTM Programmable Clock
FEATURES
DESCRIPTION
The PL611s-26 is a general purpose frequency
synthesizer and a member of PhaseLink’s PicoPLLTM
product family. Designed to fit in a small 6-pin DFN
or 6-pin SOT package for high performance
applications, the PL611s-26 offers very low phase
noise, jitter, and power consumption, while offering
up to 2 clock outputs.. The Frequency Switching
(FSEL) capability of PL611s-26 allows for
programming two sets of frequencies, while the
power down feature of PL611s-26, when activated,
allows the IC to consume less than 50µA of power.
PL611s-26’s programming flexibility allows
Advanced One Time Programmable (OTP) PLL design
Programmable PLL or direct oscillation operation
Very low Jitter and Phase Noise (30-70ps Pk-Pk typ.)
Output Frequency up to
o 110MHz @ 1.8V operation
o 166MHz @ 2.5V operation
o 200MHz @ 3.3V operation
DC Coupled Reference Input Frequency
o 1MHz to 200MHz
Low current consumption, <50µA when PDB is
activated
One programmable I/O pin can be configured as
Output Enable (OE),Power Down (PDB) input or an
additional clock output (CLK1).
generating any output using Reference input signal.
Dedicated Frequency Switching (FSEL) capability
Single 1.8V ~ 3.3V, ± 10% power supply
Operating temperature range from -40C to 85C
Available in 6-pin DFN and SOT23 GREEN/RoHS
compliant packages.
PACKAGE PIN CONFIGURATION AND DESCRIPTION
OE, PDB, CLK1
CLK0
VDD
1
2
3
6
5
4
FIN
OE,PDB,CLK1
GND
FSEL
VDD
CLK0
1
2
3
6
5
4
GND
FIN
FSEL
DFN-6L
(2.0 x 1.3 x 0.6mm)
SOT23-6L
(3.0 x 3.0 x 1.35mm)
BLOCK DIAGRAM
FREF
R-Counter
(8-bit)
FIN
Phase
Detector
Charge
Pump
Loop
Filter
M-Counter
(11-bit)
FVCO = FREF * (2 * M/R)
VCO
P-Counter
(5-bit)
CLK0
/2
FOUT = FVCO / (2 * P)
/1, 2
Programming
Logic
OE, PDB, CLK1
FSEL
Programmable Function
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/5/09 Page 1
1.8V-3.3V PicoPLLTM Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Programmable
Input/Output
Output Drive Strength
Output Frequency
FOUT = FREF * M / (R * P)
Three optional drive strengths to One output pin can be configured
Where M = 11 bit
R = 8 bit
choose from:
as:
P = 5 bit
Low: 4mA
OE - input
CLK0 = FOUT, FREF or FREF / (2*P)
CLK1 = FREF, FREF/2, CLK0 or CLK0/2
Std: 8mA (default)
High: 16mA
PDB - input
CLK1 – output
PIN DESCRIPTION
Pin Assignment
Name
Type
Description
DFN Pin# SOT Pin #
This programmable I/O pin can be configured as an Output Enable (OE)
input, Power Down input (PDB) or CLK1 Clock output. This pin has an
internal 60KΩ pull up resistor (OE and PDB functions only).
OE,
PDB,
CLK1
2
1
I/O
Pin State
OE
PDB
0
Disable CLK
Normal mode
Power Down Mode
Normal mode
1 (default)
GND
FIN
3
1
2
3
P
I
GND connection
Reference input pin
Frequency Switching Input pin. This pin has an internal 60KΩ pull up
resistor.
FSEL
State
FSEL
6
4
I
0
Frequency 2
Frequency 1
1 (default)
VDD
5
4
5
6
P
VDD connection
Programmable Clock Output
CLK0
O
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/5/09 Page 2
1.8V-3.3V PicoPLLTM Programmable Clock
FUNCTIONAL DESCRIPTION
PL611s-26 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-
power, small form-factor applications. The PL611s-26 accepts a reference clock input of 1MHz to 200MHz and is
capable of producing two outputs up to 200MHz. This flexible design allows the PL611s-26 to deliver any PLL
generated frequency, FREF (Ref Clk) frequency or FREF /(2*P) to CLK0 and/or CLK1. Some of the design features
of the PL611s-26 are mentioned below:
PLL Programming
Frequency Select (FSEL)
The PLL in the PL611s-26 is fully programmable.
The PLL is equipped with an 8-bit input frequency
divider (R-Counter), and an 11-bit VCO frequency
feedback loop divider (M-Counter). The output of
the PLL is transferred to a 5-bit post VCO divider (P-
Counter). The output frequency is determined by
the following formula [FOUT = FREF * M / (R * P) ].
The Frequency Select (FSEL) feature allows the
PL611s-26 to switch between two pre-programmed
outputs allowing the device “On the Fly” frequency
switching. The FSEL pin incorporates a pull up
resistor giving a default condition of logic “1”.
Output Enable (OE)
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE
pin. The OE pin incorporates a pull up resistor
giving a default condition of logic “1”.
Clock Output (CLK0)
CLK0 is the main clock output. The PL611s-26 can
also be programmed to provide a second clock
output, CLK1, on the programmable I/O pin (see
OE/PDB/CLK1 pin description below). The output of
CLK0 can be configured as the PLL output
(FVCO/(2*P)), FREF (Ref Clk Frequency) output, or
FREF/(2*P) output. The output drive level can be
programmed to Low Drive (4mA), Standard Drive
(8mA) or High Drive (16mA). The maximum output
frequency is determined by the power supply voltage
as shown below:
Power-Down Control (PDB)
The Power Down (PDB) feature allows the user to
put the PL611s-26 into “Sleep Mode”. When
activated (logic ‘0’), PDB ‘Disables the PLL, the
oscillator circuitry, counters, and all other active
circuitry. In Power Down mode the IC consumes
<50µA of power. The PDB pin incorporates a pull
up resistor giving a default condition of logic “1”.
Clock Output (CLK1)
The CLK1 feature allows the PL611s-26 to have an
additional clock output. This output can be
programmed to one of the following:
FREF - Reference (Ref Clk ) Frequency
FREF / 2
CLK0
CLK0 / 2
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/5/09 Page 3
1.8V-3.3V PicoPLLTM Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
VDD
VI
-0.5
-0.5
-0.5
7
V
V
Input Voltage Range
VDD+0.5
VDD+0.5
260
Output Voltage Range
VO
V
Soldering Temperature (Green package)
Data Retention @ 85C
C
Year
C
C
10
-65
-40
Storage Temperature
TS
150
85
Ambient Operating Temperature*
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
CONDITIONS
MIN. TYP.
MAX. UNITS
@ VDD =3.3V
@ VDD =2.5V
@ VDD =1.8V
200
Input (FIN) Frequency
1
MHz
166
110
Internally DC Coupled, LVCMOS input, High
Internally DC Coupled, LVCMOS input, Low
@ VDD =3.3V
0.7*VDD
Input (FIN) Signal
Amplitude
Vpp
0.3*VDD
200
166
110
2
MHz
MHz
MHz
ms
Output Frequency
@ VDD =2.5V
@ VDD =1.8V
Settling Time
At power-up (after VDD increases over 1.62V)
OE Function; Ta=25º C, 15pF Load. Add one clock
period to this measurement for a usable output.
10
ns
Output Enable Time
PDB Function; Ta=25º C, 15pF Load
15pF Load, 10/90% VDD, High Drive, 3.3V
15pF Load, 90/10% VDD, High Drive, 3.3V
2
ms
ns
ns
Output Rise Time
Output Fall Time
1.2
1.2
1.7
1.7
55
55
60
@2.5V and 3.3V over entire frequency range, VDD/2 45
50
50
Duty Cycle
%
@1.8V, < 75MHz FOUT, VDD/2
45
40
@1.8V, 75MHz < FOUT <110MHz
Period Jitter, Pk-to-Pk*
(10,000 samples measured)
With capacitive decoupling between VDD and GND
70
ps
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/5/09 Page 4
1.8V-3.3V PicoPLLTM Programmable Clock
DC SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX. UNITS
Supply Current, Dynamic
Supply Current, Dynamic
Supply Current, Dynamic
Stand By Current
IDD
IDD
IDD
IDD
VDD
VDD =3.3V, 27MHz, load=15pF
VDD =2.5V, 27MHz, load=15pF
VDD =1.8V, 27MHz, load=15pF
When PDB=0
5.5
3.8
1.8
mA
mA
mA
<50
µA
V
Operating Voltage
1.62
3.63
Time for VDD to reach 90% VDD.
Power ramp must be monotonic.
Power Supply Ramp
tPU
100
0.4
ms
Output Low Voltage
VOL
VOH
IOSD
IOSD
IOHD
IOL = +4mA Standard Drive
IOH = -4mA Standard Drive
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
VOL = 0.4V, VOH = 2.4V
V
Output High Voltage
VDD – 0.4
V
Output Current, Low Drive
Output Current, Standard Drive
Output Current, High Drive
4
8
mA
mA
mA
16
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/5/09 Page 5
1.8V-3.3V PicoPLLTM Programmable Clock
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
Decoupling and Power Supply Considerations
- Keep traces short!
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Trace = Inductor. With a capacitive load this
equals ringing!
- Multiple VDD pins should be decoupled separately
for best performance.
- Long trace = Transmission Line. Without proper
termination this will cause reflections ( looks like
ringing ).
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Design long traces ( > 1 inch ) as “striplines” or
“microstrips” with defined impedance.
- Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1F for
designs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
- Match trace at one side to avoid reflections
bouncing back and forth.
( Typical buffer impedance 20
50 line
Use value to match output
buffer impedance to 50
trace. Typical value 30
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/5/09 Page 6
1.8V-3.3V PicoPLLTM Programmable Clock
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOT23-6L
Dimension in MM
Symbol
Min.
1.05
0.05
1.00
0.30
0.08
2.80
1.50
2.60
0.35
Max.
1.35
0.15
1.20
0.50
0.20
3.00
1.70
3.0
E
H
A
A1
A2
b
c
D
E
H
L
e
D
A2
A
A1
C
0.55
b
e
L
0.95 BSC
DFN-6L
D1
Dimension in MM
e
Symbol
D
b
Min.
0.50
0.00
0.152
0.15
Max.
0.60
0.05
0.152
0.25
Pin 6 ID
Chamfer
A
A1
A3
b
E
E1
e
0.40BSC
D
E
D1
E1
L
1.25
1.95
0.75
0.95
0.20
1.35
2.05
0.85
1.05
0.30
L
Pin1 Dot
A1
A
A3
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/5/09 Page 7
1.8V-3.3V PicoPLLTM Programmable Clock
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
Shipping Option
None=Tube
R=Tape & Reel
Part Number
3 DIGIT ID Code *
(will be assigned at
programming time)
Temperature
C=Commercial (0°C to 70°C)
I=Industrial (-40°C to 85°C)
Package Type
G=DFN-6L
T=SOT23-6L
* PhaseLink will assign a unique 3-digit ID code for each approved programmed part number.
Part/Order Number
Marking†
Package Option
PL611s-26-XXXGC-R
PL611s-26-XXXTC-R
XXX
6-Pin DFN (Tape and Reel)
6-Pin SOT23 (Tape and Reel)
26XXX
† Note: ‘XXX’ designates marking identifier that, at times, could be independent of the part number.
Please consult your PhaseLink sales representative for marking information.
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 2/5/09 Page 8
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