SCH3227 [MICROCHIP]
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports;
| 型号： | SCH3227 |
| 厂家： | 
MICROCHIP |
| 描述： | LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports PC |
| 文件： | 总295页 (文件大小：3184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SCH3227/SCH3226/SCH3224/SCH3222
LPC IO with 8042 KBC, Reset Generation, HWM and
Multiple Serial Ports
-
-
-
480 Address and 15 IRQ Options
Support IRQ Sharing among serial ports
RS485 Auto Direction Control Mode
Product Features
• General Features
-
-
-
-
-
3.3 Volt Operation (SIO Block is 5 Volt Tolerant)
Programmable Wake-up Event (PME) Interface
PC99, PC2001 Compliant
• Infrared Port
-
-
-
-
Multiprotocol Infrared Interface
IrDA 1.0 Compliant
ACPI 2.0 Compliant
SHARP ASK IR
Serial IRQ Interface Compatible with Serialized
IRQ Support for PCI Systems
480 Addresses, Up to 15 IRQ
• Multi-Mode™ Parallel Port with ChiProtect™
-
-
ISA Plug-and-Play Compatible Register Set
Four Address Options for Power On Configuration
Port
-
-
Available in SCH3227, SCH3224
Standard Mode IBM PC/XT®, PC/AT®, and PS/2™
Compatible Bi-directional ParallelPort
Enhanced Parallel Port (EPP) Compatible - EPP
1.7 and EPP 1.9 (IEEE 1284 Compliant)
IEEE 1284 Compliant Enhanced Capabilities Port
(ECP)
-
-
-
-
-
System Management Interrupt (SMI)
General Purpose I/O pins: 23 to 40
GPIOs with VID compatible inputs: 0 to 6
Support for power button on PS/2 Keyboard
Security Key Register (32 byte) for Device Authen-
tication
-
-
-
-
ChiProtect Circuitry for Protection
960 Address, Up to 15 IRQ and Four DMA Options
• Low Pin Count Bus (LPC) Interface
• Hardware Monitor
-
Supports Bus frequencies of 19MHz to 33MHz
-
-
Available in SCH3227, SCH3226, SCH3224
Monitor Power supplies (+2.5V, +5V, +12V, Vccp
(processor voltage), VCC, Vbat and Vtr.
Remote Thermal Diode Sensing for Two External
Temperature Measurements accurate to 1.5°C
Internal Ambient Temperature Measurement
Limit Comparison of all Monitored Values
Programmable Automatic FAN control based on
temperature
• Watchdog Timer
• Resume and Main Power Good Generator
• Programmable Clock Output to 16 Hz
• Keyboard Controller
-
-
-
-
-
-
-
-
-
8042 Software Compatible
8 Bit Microcomputer
2k Bytes of Program ROM
256 Bytes of Data RAM
-
-
nHWM_INT Pin for out-of-limit Temperature or Volt-
age Indication
Four Open Drain Outputs Dedicated for Keyboard/
Mouse Interface
Thermtrip signal for over temperature indication
-
Asynchronous Access to Two Data Registers and
One Status Register
• IDE Reset Output and 3 PCI Reset Buffers with
Software Control Capability (SCH3227 and
SCH3226 by strap option)
-
-
-
-
-
Supports Interrupt and Polling Access
8 Bit Counter Timer
• Power Button Control and AC Power Failure
Recovery (SCH3227 and SCH3226 by strap
option)
Port 92 Support
Fast Gate A20 and KRESET Outputs
Phoenix Keyboard BIOS ROM
• Multiple Serial Ports
• Temperature Ranges Available
-
4 Full Function Serial Ports (SCH3227, SCH3226,
SCH3222)
-
-
Industrial (-40°C to +85°C)
Commercial (0°C to +70°C)
-
-
2 Full Function Serial Ports (SCH3224)
Two additional 4-pin Serial Ports available by strap
option (SCH3227, SCH3226)
•
WFBGA RoHS Compliant Packages
-
144-ball (SCH3227)
-
-
100-ball (SCH3226, SCH3224)
84-ball (SCH3222)
-
-
Two additional 4-pin Serial Ports available always
(SCH3224, SCH3222)
High Speed NS16C550A Compatible UARTs with
Send/Receive 16-Byte FIFOs
-
-
-
Supports 230k, 460k, 921k and 1.5M Baud
Programmable Baud Rate Generator
Modem Control Circuitry
2016-2017 Microchip Technology Inc.
DS00002121B-page 1
SCH3227/SCH3226/SCH3224/SCH3222
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
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Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-
rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
Microchip’s Worldwide Web site; http://www.microchip.com
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
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DS00002121B-page 2
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
Table of Contents
1.0 General Description ........................................................................................................................................................................ 4
2.0 Pin Layouts ..................................................................................................................................................................................... 7
3.0 Block Diagram ............................................................................................................................................................................... 31
4.0 Power Functionality ....................................................................................................................................................................... 32
5.0 LPC Interface ................................................................................................................................................................................ 35
6.0 Serial Port (UART) ........................................................................................................................................................................ 37
7.0 Parallel Port .................................................................................................................................................................................. 56
8.0 Power Management ...................................................................................................................................................................... 73
9.0 Serial IRQ ..................................................................................................................................................................................... 74
10.0 8042 Keyboard Controller Description ........................................................................................................................................ 77
11.0 General Purpose I/O (GPIO) ....................................................................................................................................................... 86
12.0 System Management Interrupt (SMI) .......................................................................................................................................... 93
13.0 PME Support ............................................................................................................................................................................... 94
14.0 Watchdog Timer .......................................................................................................................................................................... 99
15.0 Programmable Clock Output ..................................................................................................................................................... 100
16.0 Reset Generation ...................................................................................................................................................................... 101
17.0 Buffered PCI Outputs ................................................................................................................................................................ 104
18.0 Power Control Features ............................................................................................................................................................ 106
19.0 Low Battery Detection Logic ..................................................................................................................................................... 119
20.0 Battery Backed Security Key Register ...................................................................................................................................... 121
21.0 Temperature Monitoring and Fan Control ................................................................................................................................. 123
22.0 Hardware Monitoring Register Set ............................................................................................................................................ 157
23.0 Configuration Registers ............................................................................................................................................................ 194
24.0 Runtime Register ...................................................................................................................................................................... 213
25.0 Valid Power Modes ................................................................................................................................................................... 251
26.0 Operational Description ............................................................................................................................................................ 252
27.0 Timing Diagrams ....................................................................................................................................................................... 260
28.0 Package Outlines ...................................................................................................................................................................... 281
Appendix A: ADC Voltage Conversion .............................................................................................................................................. 284
Appendix B: Example Fan Circuits ................................................................................................................................................... 285
Appendix C: Test Mode .................................................................................................................................................................... 288
Appendix D: Data Sheet Revision History ........................................................................................................................................ 291
Product Identification System ........................................................................................................................................................... 292
The Microchip Web Site .................................................................................................................................................................... 293
Customer Change Notification Service ............................................................................................................................................. 293
Customer Support ............................................................................................................................................................................. 293
2016-2017 Microchip Technology Inc.
DS00002121B-page 3
SCH3227/SCH3226/SCH3224/SCH3222
1.0
GENERAL DESCRIPTION
The SCH3227/SCH3226/SCH3224/SCH3222 Product Family is a 3.3V (Super I/O Block is 5V tolerant) PC99/PC2001
compliant Super I/O controller with an LPC interface. The Product Family also includes Hardware Monitoring capabili-
ties, enhanced Security features, Power Control logic and Motherboard Glue logic.
1.1
Scope and Definitions
For the purposes of this document, the term “SCH322x Family” refers only to the parts numbered SCH3227, SCH3226,
SCH3224 and SCH3222. Similarly-numbered parts may also exist, but they are outside the scope of this document.
1.2
Important New Usage Considerations
The SCH322x Family is the next generation of the SCH311x family components. They mainly differ in the number of
pins brought out of the package. In some cases (SCH3227, SCH3226) a new pin called STRAPOPT is brought out,
allowing a hard-wired selection between the legacy SCH3114 vs. SCH3116 features of 8 of the pins. This selection also
affects the Device ID register, which will display the legacy SCH3114 or SCH3116 code. Other SCH322x members,
which do not have a STRAPOPT pin, are hard-wired internally to identify themselves as the legacy SCH3116.
CAUTION: This device contains circuits and registers affecting pin functions which must not be used when they are not
brought out of the package. These pins are pulled to known states internally. Any features, especially Logical Devices
and GPIOs, that are not listed in this document for a particular family member must not be activated, accessed, or in
any way changed from its default reset state. Doing so may cause unpredictable behavior and/or excessive currents,
and therefore may damage the device and/or the system. See Table 2-1 SCH3227, Table 2-2 SCH3226, Table 2-3
SCH3224, or Table 2-4 SCH3222, for the pin features that are brought out.
1.3
Feature Sets
See Table 1-1 on page 5 for features available per family member.
The Product Family is ACPI 1.0/2.0 compatible and therefore supports multiple low power-down modes. It incorporates
sophisticated power control circuitry (PCC), which includes support for keyboard.
The Product Family supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address, hardware
IRQ and DMA Channel of each Logical Device may be reprogrammed through the internal configuration registers. There
are up to 480 I/O address location options (960 for the Parallel Port), a Serialized IRQ interface, and a choice of three
Legacy DMA channel assignments.
Super I/O functionality includes an 8042 based keyboard and mouse controller, one IrDA 1.0 infrared port and multiple
serial ports. Some family members (Table 1-1) also provide an IEEE 1284 EPP/ECP compatible parallel port.
The serial ports are fully functional NS16550 compatible UARTs that support data rates up to 1.5 Mbps. There are both
8-pin Serial Ports and 4-pin Serial Ports. The reduced-pin serial ports have selectable input and output controls. The
Serial Ports contain programmable direction control, which will automatically drive nRTS when the Output Buffer is
loaded, then drive nRTS when the Output Buffer is empty.
Hardware Monitoring capability has programmable, automatic fan control. Three fan tachometer inputs and three pulse
width modulator (PWM) fan control outputs are available.
Hardware Monitoring capability also includes temperature, voltage and fan speed monitoring. It has the ability to alert
the system to out-of-limit conditions and automatically control the speeds of multiple fans in response. There are four
analog inputs for monitoring external voltages of +5V, +2.5V, +12V and Vccp (core processor voltage), as well as internal
monitoring of the device’s internal VCC, VTR, and VBAT power supplies. Hardware Monitoring includes support for
monitoring two external temperatures via thermal diode inputs and an internal sensor for measuring local ambient tem-
perature. The nHWM_INT pin is implemented to indicate out-of-limit temperature, voltage, and fan speed conditions.
Hardware Monitoring features are accessible via the LPC bus, and the same interrupt event reported on the nHWM_INT
pin also creates PME wakeup events. A separate THERMTRIP output is available, which generates a pulse output on
a programmed over-temperature condition. This can be used to generate a reset or shutdown indication to the system.
The Motherboard Glue logic includes various power management and system logic including generation of nRSMRST,
a programmable Clock output, and reset generation. The reset generation includes a watchdog timer which can be used
to generate a reset pulse. The width of this pulse is selectable via an external strapping option.
System related functionality, which offers flexibility to the system designer, includes General Purpose I/O control func-
tions, and control of two LED's.
DS00002121B-page 4
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 1-1:
Function
DEVICE SPECIFIC SUMMARY
SCH3227
SCH3226
SCH3224
SCH3222
YES
YES
YES
YES
LPC Bus Interface
YES
YES
YES
YES
PnP Config w/
4 Port Addresses
YES
YES
YES
YES
YES
4
YES
YES
YES
NO
YES
YES
YES
YES
YES
2
YES
YES
YES
NO
YES
4
Serial IRQ and SMI
Keyboard Controller
Watchdog Timer
Parallel Port
YES
4
Reset Generator
Serial Ports, Full
2 avail.
(by strap option)
2 avail.
(by strap option)
2
2
Additional Serial
Ports, 4-Pin
YES
YES
YES
YES
YES
YES
YES
YES
Infrared Port
Programmable Clock
Output
By strap option (vs.
4-pin Serial Ports).
By strap option (vs.
4-pin Serial Ports).
NO
NO
NO
NO
IDE / PCI Reset
Outputs
By strap option (vs.
4-pin Serial Ports).
By strap option (vs.
4-pin Serial Ports).
Power Button / AC
Fail Support
40
6
40
6
24
0
23
6
GPIOs
GPIO with VID
Compatible Inputs
YES
YES
YES
NO
Hardware Monitor
WFBGA Package
144-ball
100-ball
100-ball
84-ball
2016-2017 Microchip Technology Inc.
DS00002121B-page 5
SCH3227/SCH3226/SCH3224/SCH3222
1.4
Reference Documents
1. Intel Low Pin Count Specification, Revision 1.0, September 29, 1997
2. PCI Local Bus Specification, Revision 2.2, December 18, 1998
3. Advanced Configuration and Power Interface Specification, Revision 1.0b, February 2, 1999
4. IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993
5. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook
6. Application Note (AN 8-8) “Keyboard and Mouse Wakeup Functionality”, dated 03/23/02
DS00002121B-page 6
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
2.0
2.1
PIN LAYOUTS
SCH322x Pin Layout Summary
FIGURE 2-1:
SCH3227 PIN DIAGRAM
2016-2017 Microchip Technology Inc.
DS00002121B-page 7
SCH3227/SCH3226/SCH3224/SCH3222
Highlighted rows indicate balls whose function depends on the STRAPOPT strap input.
TABLE 2-1:
Ball#
SCH3227 SUMMARIES BY STRAP OPTION
Function: StrapOPT=1
Function: StrapOPT=0
STRAPOPT (=VSSa)
RESERVED=VTRb
K13
M4
C3
D3
E6
E3
E5
F8
F7
F3
F6
F5
G8
G6
H8
G5
H7
H6
H5
D2
E2
D1
E1
F2
F1
G2
H1
G1
H2
H3
J3
STRAPOPT (=VTRa)
RESERVED=VTRb
+12V_IN
+12V_IN
+5V_IN
+5V_IN
GP40
GP40
VTR
VTR
RESERVED=VSSc
TEST=VSSc
RESERVED=VSSc
VSS
RESERVED=VSSc
TEST=VSSc
RESERVED=VSSc
VSS
RESERVED=VSSc
RESERVED=VSSc
RESERVED=VSSc
RESERVED=VSSc
RESERVED=VSSc
RESERVED=VSSc
RESERVED=VSSc
RESERVED=VSSc
RESERVED=VSSc
CLOCKI
RESERVED=VSSc
RESERVED=VSSc
RESERVED=VSSc
RESERVED=VSSc
RESERVED=VSSc
RESERVED=VSSc
RESERVED=VSSc
RESERVED=VSSc
RESERVED=VSSc
CLOCKI
LAD0
LAD0
LAD1
LAD1
LAD2
LAD2
LAD3
LAD3
LFRAME#
LFRAME#
LDRQ#
LDRQ#
PCI_RESET#
PCI_CLK
PCI_RESET#
PCI_CLK
SER_IRQ
SER_IRQ
VSS
VSS
VCC
VCC
J1
GP44 / TXD6
GP45 / RXD6
GP46 / nSCIN6
GP47 / nSCOUT6
AVSS
nIDE_RSTDRV / GP44
nPCIRST1 / GP45
nPCIRST2 / GP46
nPCIRST3 / GP47
AVSS
J2
K3
L3
K1
L1
VBAT
VBAT
K2
L2
GP27 / nIO_SMI / P17
KDAT / GP21
KCLK / GP22
MDAT / GP32
MCLK / GP33
GP36 / nKBDRST
GP27 / nIO_SMI / P17
KDAT / GP21
KCLK / GP22
MDAT / GP32
MCLK / GP33
GP36 / nKBDRST
M1
M2
N1
M3
DS00002121B-page 8
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 2-1:
Ball#
SCH3227 SUMMARIES BY STRAP OPTION (CONTINUED)
Function: StrapOPT=1
GP37 / A20M
Function: StrapOPT=0
N2
L5
GP37 / A20M
VSS
VSS
N3
VTR
VTR
N4
nINIT
nINIT
nSLCTIN
PD0
M5
nSLCTIN
L6
PD0
N5
PD1
PD1
M6
PD2
PD2
L7
PD3
PD3
N6
PD4
PD4
M7
PD5
PD5
N7
PD6
PD6
L8
PD7
PD7
L9
VSS
VSS
M8
SLCT
SLCT
PE
N8
PE
N9
BUSY
BUSY
nACK
nERROR
nALF
nSTROBE
nRI1
M9
nACK
N10
M10
N11
M11
N12
L11
M12
N13
L12
M13
J12
K12
L13
J13
H11
H12
H13
G13
G12
G11
F13
F12
F11
E13
E12
D13
nERROR
nALF
nSTROBE
nRI1
nDCD1
nDCD1
RXD1
RXD1
TXD1 / SIOXNOROUT
nDSR1
TXD1 / SIOXNOROUT
nDSR1
nRTS1 / SYSOPT0
nCTS1
nRTS1 / SYSOPT0
nCTS1
nDTR1 / SYSOPT1
GP50 / nRI2
VTR
nDTR1 / SYSOPT1
GP50 / nRI2
VTR
VSS
VSS
GP51 / nDCD2
GP52 / RXD2(IRRX2)
GP53 / TXD2(IRTX2)
GP54 / nDSR2
GP55 / nRTS2 / RESGEN
GP56 / nCTS2
GP57 / nDTR2
RXD5
GP51 / nDCD2
GP52 / RXD2(IRRX2)
GP53 / TXD2(IRTX2)
GP54 / nDSR2
GP55 / nRTS2 / RESGEN
GP56 / nCTS2
GP57 / nDTR2
PB_OUT#
TXD5
PS_ON#
nSCOUT5
nSCIN5
PB_IN#
SLP_SX#
GP10 / RXD3
GP10 / RXD3
2016-2017 Microchip Technology Inc.
DS00002121B-page 9
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 2-1:
Ball#
SCH3227 SUMMARIES BY STRAP OPTION (CONTINUED)
Function: StrapOPT=1 Function: StrapOPT=0
GP11 / TXD3
D12
E11
C13
B13
C12
D11
A13
B12
C11
A12
B11
A11
C10
B10
A10
B9
GP11 / TXD3
GP14 / nDSR3
GP17 / nRTS3
GP16 / nCTS3
GP42 / nIO_PME
VTR
GP14 / nDSR3
GP17 / nRTS3
GP16 / nCTS3
GP42 / nIO_PME
VTR
GP15 / nDTR3
GP61 / nLED2 / CLKO
GP60 / nLED1 / WDT
GP13 / nRI3
GP12 / nDCD3
GP31 / nRI4
GP63 / nDCD4
CLKI32
GP15 / nDTR3
GP61 / nLED2 / CLKO
GP60 / nLED1 / WDT
GP13 / nRI3
GP12 / nDCD3
GP31 / nRI4
GP63 / nDCD4
CLKI32
nRSMRST
nRSMRST
VSS
VSS
C9
GP64 / RXD4
GP65 / TXD4
GP66 / nDSR4
GP67 / nRTS4
GP62 / nCTS4
GP34 / nDTR4
PWRGD_OUT
PWRGD_PS
nFPRST / GP30
VTR
GP64 / RXD4
GP65 / TXD4
GP66 / nDSR4
GP67 / nRTS4
GP62 / nCTS4
GP34 / nDTR4
PWRGD_OUT
PWRGD_PS
nFPRST / GP30
VTR
A9
A8
B8
C8
A7
B7
A6
C7
E8
E7
VSS
VSS
B6
nTHERMTRIP
nHWM_INT
PWM3
nTHERMTRIP
nHWM_INT
PWM3
A5
C6
B5
PWM2
PWM2
A4
PWM1
PWM1
B4
FANTACH3
FANTACH2
FANTACH1
HVSS
FANTACH3
FANTACH2
FANTACH1
HVSS
C5
C4
A3
B3
HVTR
HVTR
A2
REMOTE2-
REMOTE2+
REMOTE1-
REMOTE1+
VCCP_IN
REMOTE2-
REMOTE2+
REMOTE1-
REMOTE1+
VCCP_IN
A1
B1
C1
C2
DS00002121B-page 10
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 2-1:
Ball#
SCH3227 SUMMARIES BY STRAP OPTION (CONTINUED)
Function: StrapOPT=1
Function: StrapOPT=0
B2
--
+2.5V_IN
+2.5V_IN
RESERVED=N/Cd: E9, F9, G9, H9, J5, J6, J7, J8, J9, G3, J11, K11, L4, L10
a. The STRAPOPT connection defines pin functions for this package, and also the contents of the Device ID
register at Plug&Play Index 0x20:
When connected to VTR, the table column STRAPOPT=1 applies,
and Device ID = 0x7F.
When connected to VSS, the table column STRAPOPT=0 applies,
and Device ID = 0x7D.
b. For correct operation, this lead must always be connected to VTR.
c. For correct operation and minimal current consumption, this lead must always be connected to VSS.
d. Make No Connection to these leads.
2016-2017 Microchip Technology Inc.
DS00002121B-page 11
SCH3227/SCH3226/SCH3224/SCH3222
FIGURE 2-2:
SCH3226 PIN DIAGRAM
DS00002121B-page 12
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
Highlighted rows indicate balls whose function depends on the STRAPOPT strap input.
TABLE 2-2:
Ball#
SCH3226 SUMMARIES BY STRAP OPTION
Function: StrapOPT=1
Function: StrapOPT=0
STRAPOPT (=VSSa)
L8
C2
C1
C3
D3
G5
D2
E3
F3
E2
D1
F2
E1
G3
F1
G1
G2
H1
H2
H3
J2
STRAPOPT (=VTRa)
+12V_IN
+12V_IN
+5V_IN
+5V_IN
GP40 / DRVDEN0(out)
VTR
GP40 / DRVDEN0(out)
VTR
TEST=VSSb
TEST=VSSb
VSS
VSS
CLOCKI
CLOCKI
LAD0
LAD0
LAD1
LAD1
LAD2
LAD2
LAD3
LAD3
LFRAME#
LDRQ#
LFRAME#
LDRQ#
PCI_RESET#
PCI_CLK
PCI_RESET#
PCI_CLK
SER_IRQ
SER_IRQ
VSS
VSS
VCC
VCC
GP44 / TXD6
GP45 / RXD6
GP46 / nSCIN6
GP47 / nSCOUT6
AVSS
nIDE_RSTDRV / GP44
nPCIRST1 / GP45
nPCIRST2 / GP46
nPCIRST3 / GP47
AVSS
K2
J3
J1
K1
K3
J4
VBAT
VBAT
GP27 / nIO_SMI / P17
KDAT / GP21
KCLK / GP22
MDAT / GP32
MCLK / GP33
GP36 / nKBDRST
GP37 / A20M
VSS
GP27 / nIO_SMI / P17
KDAT / GP21
KCLK / GP22
MDAT / GP32
MCLK / GP33
GP36 / nKBDRST
GP37 / A20M
VSS
L2
L3
K4
L4
L5
G7
G6
K7
L6
K8
J8
VTR
VTR
nRI1
nRI1
nDCD1
nDCD1
RXD1
RXD1
TXD1 / SIOXNOROUT
nDSR1
TXD1 / SIOXNOROUT
nDSR1
K6
K5
J7
nRTS1 / SYSOPT0
nCTS1
nRTS1 / SYSOPT0
nCTS1
J6
nDTR1 / SYSOPT1
GP50 / nRI2
nDTR1 / SYSOPT1
GP50 / nRI2
J5
2016-2017 Microchip Technology Inc.
DS00002121B-page 13
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 2-2:
Ball#
SCH3226 SUMMARIES BY STRAP OPTION (CONTINUED)
Function: StrapOPT=1 Function: StrapOPT=0
L9
VTR
VSS
VTR
L7
VSS
K9
GP51 / nDCD2
GP52 / RXD2(IRRX2)
GP53 / TXD2(IRTX2)
GP54 / nDSR2
GP55 / nRTS2 / RESGEN
GP56 / nCTS2
GP57 / nDTR2
RXD5
GP51 / nDCD2
GP52 / RXD2(IRRX2)
GP53 / TXD2(IRTX2)
GP54 / nDSR2
GP55 / nRTS2 / RESGEN
GP56 / nCTS2
GP57 / nDTR2
PB_OUT#
J9
H9
G9
L10
K10
J10
H10
K11
J11
H11
F9
TXD5
PS_ON#
nSCOUT5
PB_IN#
nSCIN5
SLP_SX#
GP10 / RXD3
GP11 / TXD3
GP14 / nDSR3
GP17 / nRTS3
GP16 / nCTS3
GP42 / nIO_PME
VTR
GP10 / RXD3
GP11 / TXD3
GP14 / nDSR3
GP17 / nRTS3
GP16 / nCTS3
GP42 / nIO_PME
VTR
G10
E9
F10
G11
F11
E10
E11
D9
GP15 / nDTR3
GP61 / nLED2 / CLKO
GP60 / nLED1 / WDT
GP13 / nRI3
GP12 / nDCD3
GP31 / nRI4
GP63 / nDCD4
CLKI32
GP15 / nDTR3
GP61 / nLED2 / CLKO
GP60 / nLED1 / WDT
GP13 / nRI3
GP12 / nDCD3
GP31 / nRI4
GP63 / nDCD4
CLKI32
D10
D11
C11
C10
C9
B11
B10
A10
C8
nRSMRST
nRSMRST
VSS
VSS
GP64 / RXD4
GP65 / TXD4
GP66 / nDSR4
GP67 / nRTS4
GP62 / nCTS4
GP34 / nDTR4
PWRGD_OUT
PWRGD_PS
nFPRST / GP30
VTR
GP64 / RXD4
GP65 / TXD4
GP66 / nDSR4
GP67 / nRTS4
GP62 / nCTS4
GP34 / nDTR4
PWRGD_OUT
PWRGD_PS
nFPRST / GP30
VTR
B9
A9
B8
A8
C7
A7
B7
E7
F7
C6
VSS
VSS
B6
nTHERMTRIP
nHWM_INT
nTHERMTRIP
nHWM_INT
E6
A6
PWM3
PWM3
DS00002121B-page 14
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 2-2:
Ball#
SCH3226 SUMMARIES BY STRAP OPTION (CONTINUED)
Function: StrapOPT=1
Function: StrapOPT=0
F5
A5
E5
B5
C5
B4
C4
A4
A3
A2
B1
B3
B2
PWM2
PWM2
PWM1
PWM1
FANTACH3
FANTACH2
FANTACH1
HVSS
FANTACH3
FANTACH2
FANTACH1
HVSS
HVTR
HVTR
REMOTE2-
REMOTE2+
REMOTE1-
REMOTE1+
VCCP_IN
+2.5V_IN
REMOTE2-
REMOTE2+
REMOTE1-
REMOTE1+
VCCP_IN
+2.5V_IN
a. The STRAPOPT connection defines pin functions for this package, and also the contents of the Device ID
register at Plug&Play Index 0x20:
When connected to VTR, the table column STRAPOPT=1 applies,
and Device ID = 0x7F.
When connected to VSS, the table column STRAPOPT=0 applies,
and Device ID = 0x7D.
b. For correct operation, this lead must always be connected to VSS.
2016-2017 Microchip Technology Inc.
DS00002121B-page 15
SCH3227/SCH3226/SCH3224/SCH3222
FIGURE 2-3:
SCH3224 PIN DIAGRAM
DS00002121B-page 16
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
Highlighted rows indicate balls whose function depends on the STRAPOPT strap input.
TABLE 2-3:
Ball#
SCH3224 SUMMARY
Functiona
C3
C2
D3
E6
D2
F2
E2
D1
E3
F3
E1
G3
F1
G1
G2
H1
H2
H3
F5
E5
J2
+12V_IN
+5V_IN
VTR
TEST=VSSb
VSS
CLOCKI
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
PCI_RESET#
PCI_CLK
SER_IRQ
VSS
VCC
GP44 / TXD6
GP45 / RXD6
GP46 / nSCIN6
GP47 / nSCOUT6
AVSS
J1
K1
J3
VBAT
GP27 / nIO_SMI / P17
KDAT / GP21
KCLK / GP22
MDAT / GP32
MCLK / GP33
GP36 / nKBDRST
GP37 / A20M
J4
K3
K2
L2
L3
J5
K4
G6
K5
G5
J6
RESERVED=N/C (Make no connection.)
VTR
nINIT
nSLCTIN
PD0
L5
K6
L4
L6
C10
K7
J7
PD1
PD2
PD3
PD4
PD5
PD6
PD7
G7
VSS
2016-2017 Microchip Technology Inc.
DS00002121B-page 17
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 2-3:
Ball#
SCH3224 SUMMARY (CONTINUED)
Functiona
C7
SLCT
E7
PE
L8
BUSY
nACK
K8
J8
nERROR
G11
K9
nALF
nSTROBE
L10
J9
nRI1
nDCD1
K10
K11
J10
J11
H9
RXD1
TXD1 / SIOXNOROUT
nDSR1
nRTS1 / SYSOPT0
nCTS1
H10
H11
L9
nDTR1 / SYSOPT1
GP50 / nRI2
VTR
L7
VSS
G9
G10
F11
F10
E11
D11
F9
GP51 / nDCD2
GP52 / RXD2(IRRX2)
GP53 / TXD2(IRTX2)
GP54 / nDSR2
GP55 / nRTS2 / RESGEN
GP56 / nCTS2
GP57 / nDTR2
RXD5
D10
B11
E9
TXD5
nSCOUT5
D9
nSCIN5
C11
E10
B10
C9
GP42 / nIO_PME
VTR
GP61 / nLED2 / CLKO
GP60 / nLED1 / WDT
CLKI32
C1
B9
nRSMRST
A10
C8
VSS
PWRGD_OUT
PWRGD_PS
nFPRST / GP30
VTR
A9
B8
F7
C6
VSS
B7
nTHERMTRIP
nHWM_INT
PWM3
A8
A7
DS00002121B-page 18
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 2-3:
Ball#
SCH3224 SUMMARY (CONTINUED)
Functiona
B6
A6
A5
B5
C5
B4
C4
A4
A3
A2
B1
B3
B2
PWM2
PWM1
FANTACH3
FANTACH2
FANTACH1
HVSS
HVTR
REMOTE2-
REMOTE2+
REMOTE1-
REMOTE1+
VCCP_IN
+2.5V_IN
a. Device ID register at Plug&Play Index 0x20 holds 0x7F.
b. For correct operation, this lead must always be connected to VSS.
2016-2017 Microchip Technology Inc.
DS00002121B-page 19
SCH3227/SCH3226/SCH3224/SCH3222
FIGURE 2-4:
SCH3222 PIN DIAGRAM
DS00002121B-page 20
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 2-4:
BALL#
SCH3222 SUMMARY
FUNCTIONa
B1
A1
C1
A2
D1
E1
B2
C2
B3
D2
F1
F2
F3
E3
G2
G1
H1
J1
+5V_IN
GP40
VTR
TEST=VSSb
VSS
CLOCKI
LAD0
LAD1
LAD2
LAD3
LFRAME#
PCI_RESET#
PCI_CLK
SER_IRQ
VSS
VCC
GP44 / TXD6
GP45 / RXD6
GP46 / nSCIN6
GP47 / nSCOUT6
AVSS
J2
K1
K2
H2
K3
J3
VBAT
GP27 / nIO_SMI / P17
KDAT / GP21
KCLK / GP22
MDAT / GP32
MCLK / GP33
GP36 / nKBDRST
GP37 / A20M
VSS
J4
F4
E4
J5
K4
K6
K5
K7
K8
H5
K10
J10
K9
J9
VTR
VSS
nRI1
nDCD1
RXD1
TXD1 / SIOXNOROUT
nDSR1
nRTS1 / SYSOPT0
nCTS1
H10
H9
J8
nDTR1 / SYSOPT1
GP50 / nRI2
VTR
G9
J7
VSS
G5
GP51 / nDCD2
2016-2017 Microchip Technology Inc.
DS00002121B-page 21
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 2-4:
BALL#
SCH3222 SUMMARY (CONTINUED)
FUNCTIONa
G10
F10
G7
J6
GP52 / RXD2(IRRX2)
GP53 / TXD2(IRTX2)
GP54 / nDSR2
GP55 / nRTS2 / RESGEN
GP56 / nCTS2
GP57 / nDTR2
RXD5
H6
F9
F8
F7
TXD5
G6
E9
E10
D10
G4
E8
E7
D7
D4
C10
D9
C9
B9
B10
A10
A9
D6
B8
A4
A8
A7
C6
B7
C5
B6
B5
B4
A6
A3
D5
A5
E2
nSCOUT5
nSCIN5
GP10 / RXD3
GP11 / TXD3
GP14 / nDSR3
GP17 / nRTS3
GP16 / nCTS3
GP42 / nIO_PME
VTR
GP15 / nDTR3
GP61 / nLED2 / CLKO
GP60 / nLED1 / WDT
GP13 / nRI3
GP12 / nDCD3
GP31 / nRI4
GP63 / nDCD4
CLKI32
nRSMRST
VSS
GP64 / RXD4
GP65 / TXD4
GP66 / nDSR4
GP67 / nRTS4
GP62 / nCTS4
GP34 / nDTR4
PWRGD_OUT
PWRGD_PS
nFPRST / GP30
VTR
VSS
VSS
VSS
a. Device ID register at Plug&Play Index 0x20 holds 0x7F.
b. For correct operation, this lead must always be connected to VSS.
DS00002121B-page 22
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
2.2
Pin Functions
Table 2-5 lists all possible SCH322x pin functions. See Table 2-1 through Table 2-4 for the pins that apply to specific
family members.
These functions are all available only on the SCH3227 device, and then certain functions require specific setting of the
STRAPOPT pin, which is new to the SCH322x family. The STRAPOPT pin appears in the SCH3227 (Table 2-1) and
SCH3226 (Table 2-2) family members only.
TABLE 2-5:
Note
SCH322X PIN FUNCTIONS DESCRIPTION
VCC
VCC=0
Operation
(Note 2-14)
Buffer
Modes
(Note 2-1)
VTR-POWER
Plane
Name
Description
Power
Plane
PACKAGE PINOUT STRAP OPTION PIN (SCH3227 AND SCH3226 ONLY)
Pinout Strap Option STRAPOPT No Gate
I
STRAPOPT
POWER PINS
2-3, 2-4
2-3, 2-4
+3.3 Volt Supply Voltage
VCC
VTR
+3.3 Volt Standby Supply
Voltage
2-8
+3.0 Volt Battery Supply)
Ground
VBAT
VSS
Analog Ground
AVSS
HVTR
2-3
Analog Power. +3.3V VTR
pin dedicated to the
Hardware Monitoring
block. HVTR is powered
by +3.3V Standby power
VTR.
2-3
HVSS
Analog Ground. Internally
connected to all of the
Hardware Monitoring Block
circuitry.
CLOCK PINS
CLKI32
32.768kHz Trickle Clock
Input
CLKI32
No Gate
IS
IS
CLOCKI
14.318MHz Clock Input
CLOCKI
LPC INTERFACE
LAD[3:0]
Multiplexed Command
LAD[3:0]
GATE/ Hi-Z
GATE
PCI_IO
PCI_I
Address and Data
LFRAME#
Frame signal. Indicates
start of new cycle and
termination of broken cycle
LFRAME#
LDRQ#
Encoded DMA Request
PCI Reset
LDRQ#
GATE/Hi-Z
NO GATE
PCI_O
PCI_I
PCI_RESET#
PCI_RESE
T#
PCI_CLK
SER_IRQ
PCI Clock
Serial IRQ
PCI_CLK
SER_IRQ
GATE
PCI_ICLK
PCI_IO
GATE / Hi-Z
SERIAL PORT 1 INTERFACE
RXD1
Receive Data 1
RXD1
GATE
HI-Z
IS
TXD1
/SIO
XNOR_OUT
Transmit Data 1
/ XNOR-Chain test mode
Output for SIO block
TXD1
/SIO
XNOR_OU
T
O12/O12
nDSR1
Data Set Ready 1
nDSR1
GATE
I
2016-2017 Microchip Technology Inc.
DS00002121B-page 23
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 2-5:
SCH322X PIN FUNCTIONS DESCRIPTION (CONTINUED)
VCC
Power
Plane
VCC=0
Operation
(Note 2-14)
Buffer
Modes
(Note 2-1)
VTR-POWER
Note
Name
Description
Plane
2-7
nRTS1/
SYSOPT0
Request to Send 1/
SYSOPT (Configuration
Port Base Address
Control)
nRTS1/
SYSOPT0
GATE/ Hi-Z
OP14 / I
nCTS1
Clear to Send 1
nCTS1
GATE
I
nDTR1 /
SYSOPT1
Data Terminal Ready 1
nDTR1 /
SYSOPT1
GATE/ Hi-Z
O6 / I
2-9
nRI1
Ring Indicator 1
nRI1
nRI2
GATE
GATE
IS
I
nDCD1
Data Carrier Detect 1
nDCD1
SERIAL PORT 2 INTERFACE
2-9
2-9
2-9
GP50 / nRI2
Ring Indicator 2
GP50
NO GATE/ (I/OD8/OD8)/
IS
HI-Z
NO GATE/ (I/OD8/OD8)/
GP51 / nDCD2 Data Carrier Detect 2
GP51 /
nDCD2
I
HI-Z
GP52 / RXD2
(IRRX2)
Receive Data 2 (IRRX2)
Transmit Data 2 (IRTX2)
GP52 /
RXD2
(IRRX2)
NO GATE/ (I/OD8OD8) /
IS
HI-Z
2-11, 2-9 GP53 / TXD2
(IRTX2)
GP53 /
TXD2
(IRTX2)
NO GATE/ (I/O12/OD12)
/ (O12/OD12)
/ (O12/OD12)
HI-Z
2-9
GP54 / nDSR2 Data Set Ready 2
GP54 /
nDSR2
NO GATE/ (I/OD8/OD8)/
I
HI-Z
2-9
2-15
GP55 / nRTS2 / Request to Send 2 /
GP55 /
nRTS2 /
RESGEN
NO GATE/ (I/O8/OD8) / I
RESGEN
Reset Generator Pulse
Width Strap Option
/ IOP8
NO GATE/ (I/OD8OD8) /
HI-Z
2-9
2-9
GP56 / nCTS2 Clear to Send 2
GP56 /
nCTS2
I
HI-Z
GP57 / nDTR2 Data Terminal Ready 2
GP57 /
nDTR2
NO GATE/ (I/OD8OD8) /
O6
HI-Z
SERIAL PORT 3 INTERFACE
2-9
2-9
2-9
GP13 /
nRI3
GPIO /
GP13 /
nRI3
NO GATE (I/O8/OD8) / I
NO GATE (I/O8/OD8) / I
Ring Indicator 3
GP12 /
nDCD3
GPIO /
Data Carrier Detect 3
nDCD3
GP12
GP10 /
RXD3
GPIO /
Receive Data 3
GP10 /
RXD3
/
(IS/O8/OD8)/
IS
HI-Z
2-11, 2-9 GP11 /
TXD3
GPIO /
TXD3
GP11
GP14
/
(I/O8/OD8) /
O8
Transmit Data 3
HI-Z
2-9
GP14 /
nDSR3
GPIO /
Data Set Ready 3
nDSR3
NO GATE (I/O8/OD8) / I
2-9
GP17 /
nRTS3/
GPIO /
GP17 /
nRTS3/
/
(I/O8/OD8) / I
(I/O8/OD8) / I
Request to Send 3
HI-Z
2-9
2-9
GP16 /
nCTS3
GPIO /
Clear to Send 3
GP16 /
nCTS3
/
HI-Z
GP15 /
nDTR3
GPIO /
Data Terminal Ready 3
GP15 /
nDTR3
/
(I/O12/OD12)
/ O12
HI-Z
SERIAL PORT 4 INTERFACE
2-9
GP31 /
nRI4
GPO (OD Only in Output
GP31 /
nRI4
NO GATE (I/OD8) / I
Mode) /
Ring Indicator 4
DS00002121B-page 24
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 2-5:
Note
SCH322X PIN FUNCTIONS DESCRIPTION (CONTINUED)
VCC
Power
Plane
VCC=0
Operation
(Note 2-14)
Buffer
Modes
(Note 2-1)
VTR-POWER
Plane
Name
Description
2-9
2-9
GP63* /
nDCD4
GPIO with I_VID buffer
Input /
nDCD4
GP63*
GP64*
GP65*
GP66*
GP67*
GP62*
GP34
NO GATE (I/O8/OD8) / I
Data Carrier Detect 4
GP64* /
RXD4
GPIO with I_VID buffer
Input /
Receive Data 4
RXD4
NO GATE (IS/O8/OD8)/
IS
2-11, 2-9 GP65* /
TXD4
GPIO with I_VID buffer
Input /
Transmit Data 4
TXD4
/
(I/O8/OD8) /
O8
HI-Z
2-9
2-9
2-9
2-9
GP66* /
nDSR4
GPIO with I_VID buffer
Input /
Data Set Ready 4
nDSR4
nRTS4
nCTS4
nDTR4
NO GATE (I/O8/OD8) / I
GP67* /
nRTS4
GPIO with I_VID buffer
Input /
Request to Send 4
/
(I/O8/OD8) / I
HI-Z
GP62* /
nCTS4
GPIO with I_VID buffer
Input /
Clear to Send 4
NO GATE (I/O8/OD8) / I
GP34 /
nDTR4
GPIO (OD Only in Output
Mode)/
Data Terminal Ready 4
/
(I/OD12) /
O12
HI-Z
SERIAL PORT 5 INTERFACE
nSCOUT5
nSCOUT5
/
(O8/OD8)
Serial Port 5 out control
HI-Z
2-9
nSCIN5
RXD5
TXD5
Serial Port 5 input Control
Receive 5
nSCIN5
GP47 /
NO GATE
GATE
I
IS
RXD5
TXD5
Serial Port 5 Transmit
NO GATE /
HI-Z
(O12.OD12)
SERIAL PORT 6 INTERFACE
2-12
GP47 /
GPIO with Schmitt trigger
input
nSCOUT6
HI-Z
(IS/O4/OD4)/
(O4/OD4)
nSCOUT6
Serial Port 6 output control
2-12
2-12
2-12
GP46 /
nSCIN6
GPIO with Schmitt trigger
input
GP46 /
nSCIN6
NO GATE (IS/O8/OD8)/
(O8/OD8)
Serial Port 6 input Control
GP45 /
RXD6
GPIO with Schmitt trigger
input
Receive serial port 6
RXD6
TXD6
GATE
GP44
PG
(IS/O8/OD8)/
(O8/OD8)
GP44 /
TXD6
GPIO with Schmitt trigger
input
Serial Port 6 Transmit
NO GATE/ (IS/O4/OD4)/
(O4/OD4)
Hi-Z
PARALLEL PORT INTERFACE
2-12
2-12
2-12
2-12
2-12
nINIT
nSLCTIN
PD0
Initiate Output
nINIT
nSLCTIN
PD0
GATE /
HI-Z
(OD14/OP14)
(OD14/OP14)
IOP14
Printer Select Input
(Output to printer)
GATE /
HI-Z
Port Data 0
Port Data 1
Port Data 2
GATE /
HI-Z
PD1
PD1
GATE /
HI-Z
IOP14
PD2
PD2 /
GATE /
HI-Z
IOP14
2016-2017 Microchip Technology Inc.
DS00002121B-page 25
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 2-5:
SCH322X PIN FUNCTIONS DESCRIPTION (CONTINUED)
VCC
Power
Plane
VCC=0
Operation
(Note 2-14)
Buffer
Modes
(Note 2-1)
VTR-POWER
Note
Name
Description
Port Data 3
Plane
2-12
2-12
2-12
2-12
2-12
2-12
2-12
2-12
2-12
2-12
2-12
2-12
PD3
PD3
GATE /
HI-Z
IOP14
PD4
PD5
PD6
PD7
Port Data 4
Port Data 5
Port Data 6
Port Data 7
Printer Selected Status
Paper End
PD4
GATE /
HI-Z
IOP14
PD5
GATE /
HI-Z
IOP14
PD6
GATE /
HI-Z
IOP14
PD7
GATE /
HI-Z
IOP14
SLCT
SLCT
PE
GATE /
HI-Z
I
PE
GATE /
HI-Z
I
BUSY
nACK
Busy
BUSY
nACK
nERROR
nALF
GATE /
HI-Z
I
Acknowledge
Error
GATE /
HI-Z
I
nERROR
nALF
GATE /
HI-Z
I
Autofeed Output
Strobe Output
GATE /
HI-Z
(OD14/OP14)
(OD14/OP14)
nSTROBE
nSTROBE
GATE /
HI-Z
KEYBOARD/MOUSE INTERFACE
2-9
2-9
2-9
KDAT/GPGP21 Keyboard Data I/O
General Purpose I/O
KDAT/GPG
P21
NO GATE /
HI-Z
(I/OD12) /
(I/O12/OD12)
KCLK/GPGP22 Keyboard Clock I/O
General Purpose I/O
KCLK/GPD
P22
NO GATE /
HI-Z
(I/OD12) /
(I/O12/OD12)
MDAT/GPGP32 Mouse Data I/O
/General Purpose I/O
MDAT/GPG
P32
NO GATE /
HI-Z
(I/OD12)
/
(I/O12/OD12)
2-9
2-6
MCLK/GPGP33 Mouse Clock I/O
/General Purpose I/O
MCLK/GPG
P33
NO GATE /
HI-Z
(I/OD12)
/
(I/O12/OD12)
GP36/
nKBDRST
General Purpose I/O.
GP36/
NO GATE /
HI-Z
(I/O8/OD8)
/OD8
GPIO can be configured as nKBDRST
an Open-Drain Output.
Keyboard Reset Open-
Drain Output (Note 2-10)
2-6
GP37/
A20M
General Purpose I/O.
GPIO can be configured as
an Open-Drain Output.
Gate A20 Open-Drain
Output (Note 2-10)
GP37/
A20M
NO GATE /
HI-Z
(I/O8/OD8)
/OD8
RESETS LOGIC
2-12
2-12
nPCIRST3 /
GP47
PCI Reset output 3
nPCIRST3
GP47
GP46
NO GATE
NO GATE
(O4/OD4) /
GPIO with Schmitt trigger
input
(IS/O4/OD4)
nPCIRST2 /
GP46
PCI Reset output 2
GPIO with Schmitt trigger
input
nPCIRST2
(O8/OD8) /
(IS/O8/OD8)
DS00002121B-page 26
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 2-5:
Note
SCH322X PIN FUNCTIONS DESCRIPTION (CONTINUED)
VCC
Power
Plane
VCC=0
Operation
(Note 2-14)
Buffer
Modes
(Note 2-1)
VTR-POWER
Plane
Name
Description
2-12
2-12
nPCIRST1 /
GP45
PCI Reset output 1
GPIO with Schmitt trigger
input
nPCIRST1
GP45
GP44
NO GATE
(O8/OD8) /
(IS/O8/OD8)
nIDE_RSTDRV IDE Reset output
nIDE_RST
DRV
NO GATE
(O4/OD4) /
(IS/O4/OD4)
/
GPIO with Schmitt trigger
input
GP44
GLUE LOGIC
PB_IN#
Power Button In is used to
detect a power button
event
PB_IN#
NO GATE
I
2-9
SLP_SX#
PB_OUT#
PS_ON#
Sx Sleep State Input Pin.
Power Button Out
SLP_SX#
PB_OUT#
PS_ON#
NO GATE
NO GATE
NO GATE
I
O8
O12
Power supply On
MISCELLANEOUS PINS
General Purpose I/O.
Power Management Event
Output. This active low
Power Management Event
signal allows this device to
request wake-up in either
S3 or S5 and below.
GP42/
nIO_PME
GP42/
nIO_PME
NO GATE
(I/O12/OD12)
/(O12/OD12)
2-8, 2-9 GP60
/nLED1
General Purpose I/O
/nLED1
GP60
/nLED1
/WDT
NO GATE
NO GATE
(I/O12/OD12)
/(O12/OD12)
/(O12/OD12)
/WDT
Watchdog Timer Output
nFPRST /
GP30
Front Panel Reset /
General Purpose IO
nFPRST /
GP30
ISPU_400 /
(I/O4/OD4)
PWRGD_PS
Power Good Input from
Power Supply
PWRGD_PS
NO GATE
NO GATE
ISPU_400
OD8
PWRGD_OUT Power Good Output –
Open Drain
PWRGD_OU
T
nRSMRST
Resume Reset Output
nRSMRST
NO GATE
NO GATE
OD24
2-8, 2-9 GP61
General Purpose I/O
/nLED2
/ Programmable Clock
Output
GP61
/nLED2 /
CLKO
(I/O12/OD12)
/ (O12/OD12)
/ (O12/OD12)
/nLED2 /
CLKO
2-9
GP27/nIO_SMI General Purpose I/O
GP27
/nIO_SMI
/P17
GP27
/
(I/O12/OD12)
/(O12/OD12)
/(I/O12/OD12
)
/P17
/System Mgt. Interrupt
/8042 P17 I/O
HI-Z
HARDWARE MONITORING BLOCK
nHWM_INT
nHWM_INT
Interrupt output for
OD8
Hardware monitor
2-10
2-10
2-10
+5V_IN
Analog input for +5V
Analog input for +2.5V
HVTR
HVTR
HVTR
IAN
IAN
IAN
+2.5_IN
VCCP_IN
Analog input for +Vccp
(processor voltage: 1.5 V
nominal).
2-10
+12V_IN
Analog input for +12V
HVTR
IAN
2016-2017 Microchip Technology Inc.
DS00002121B-page 27
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 2-5:
SCH322X PIN FUNCTIONS DESCRIPTION (CONTINUED)
VCC
Power
Plane
VCC=0
Operation
(Note 2-14)
Buffer
Modes
(Note 2-1)
VTR-POWER
Note
Name
Description
Plane
REMOTE1-
REMOTE1+
REMOTE2-
REMOTE2+
This is the negative input
(current sink) from the
remote thermal diode 1.
HVTR
HVTR
HVTR
HVTR
IAND-
IAND+
IAND-
IAND+
This is the positive input
(current source) from the
remote thermal diode 1.
This is the negative input
(current sink) from the
remote thermal diode 2.
This is the positive input
(current source) from the
remote thermal diode 2.
PWM1
PWM2
PWM3
Fan Speed Control 1
Output.
PWM1
PWM2
PWM3
OD8
OD8
OD8
OD_PH
IM
Fan Speed Control 2
Output
Fan Speed Control 3
Output
nTHERMTRIP Thermtrip output
nTHERMTRI
P
FANTACH1
FANTACH2
FANTACH3
Tachometer Input 1 for
monitoring a fan.
FANTACH1
FANTACH2
FANTACH3
Tachometer Input 2 for
monitoring a fan.
IM
Tachometer Input 3 for
monitoring a fan.
IM
Note:
The “n” as the first letter of a signal name or the “#” as the suffix of a signal name indicates an “Active Low”
signal.
Note 2-1
Note 2-2
Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in parenthesis
represent multiple buffer types for a single pin function.
Pins that have input buffers must always be held to either a logical low or a logical high state when
powered. Bi-directional buses that may be trisected should have either weak external pull-ups or pull-
downs to hold the pins in a logic state (i.e., logic states are VCC or ground).
Note 2-3
VCC and VSS pins are for Super I/O Blocks. HVTR and HVSS are dedicated for the Hardware
Monitoring Block.
Note 2-4
Note 2-5
Note 2-6
VTR can be connected to VCC if no wake-up functionality is required.
The Over Current Sense Pin requires an external pull-up (30ua pull-up is suggested).
External pull-ups must be placed on the nKBDRST and A20M pins. These pins are GPIOs that are
inputs after an initial power-up (VTR POR). If the nKBDRST and A20M functions are to be used, the
system must ensure that these pins are high.
Note 2-7
The nRTS1/SYSOPT0 pin requires an external pull-down resistor to put the base I/O address for
configuration at 0x02E. An external pull-up resistor is required to move the base I/O address for
configuration to 0x04E.
Note 2-8
Note 2-9
The LED pins are powered by VTR so that the LEDs can be controlled when the part is under VTR
power.
This pin is an input into the wake-up logic that is powered by VTR. In the case of a ring indicator for
a serial port, or a GPIO it will also go to VCC powered logic. This logic must be disabled when
VCC=0.
DS00002121B-page 28
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
Note 2-10
Note 2-11
This analog input is backdrive protected. Although HVTR is powered by VTR, it is possible that
monitored power supplies may be powered when HVTR is off.
The GP53/TXD2(IRTX) pin defaults to the GPIO input function on a VTR POR and presents a tristate
impedance. When VCC=0 the pin is tristate. If GP53 function is selected and VCC is power is applied,
the pin reflects the current state of GP53. The GP53/TXD2(IRTX) pin is tristate when it is configured
for the TXD2 (IRTX) function under various conditions detailed in Section 6.2.1, "IR Transmit Pin,"
on page 51.
Note 2-12
The Reset and Glue Logic functions are only available on these pins in the SCH3227 and SCH3226
family members, requiring also that the STRAPOPT pin on these devices be tied low.
Serial Ports 5 and 6 are available on all family members, on the same pins, and also require
(SCH3227 and SCH3226 only) that the STRAPOPT pin be pulled high.
In all the SCH322x family, GP44--47 have Schmitt trigger inputs.
Note 2-13
Note 2-14
The pins listed here are pins used in all of the SCH322x devices.
All logic is powered by VTR. Vcc on pin 29 is used as an indication of the presence of the VCC rail
being active. All logic that requires VCC power, is only enabled when the VCC rail is active.
Note 2-15
The GP55/nRTS2/RESGEN pin requires an external pull-down resistor to enable 500ms delay circuit.
An external pull-up resistor is required to enable 200ms delay circuit.
USER’S NOTE:
Open-drain pins should be pulled-up externally to supply shown in the power well column. All other pins are driven under
the power well shown.
• NOMENCLATURE:
- No Gate indicates that the pin is not protected, or affected by VCC=0 operation
- Gate indicates that the pin is protected as an input (if required) or set to a HI-Z state as an output (if required)
- In these columns, information is given in order of pin function: e.g. 1st pin function / 2nd pin function
2.3
Buffer Description
Table 2-6 lists the buffers that are used in this device. A complete description of these buffers can be found in Section
26.0, "Operational Description," on page 252.
TABLE 2-6:
Buffer
BUFFER DESCRIPTION
Description
I
Input TTL Compatible - Super I/O Block.
Input, Low Leakage Current.
IL
IM
Input - Hardware Monitoring Block.
IAN
Analog Input, Hardware Monitoring Block.
Back Bias Protected Analog Input, Hardware Monitoring Block.
Remote Thermal Diode (current sink) Negative Input
Remote Thermal Diode (current source) Positive Input
Input with Schmitt Trigger.
IANP
IAND-
IAND+
IS
I_VID
IMOD3
IMO3
O6
Input. See DC Characteristics Section.
Input/Output (Open Drain), 3mA sink.
Input/Output, 3mA sink, 3mA source.
Output, 6mA sink, 3mA source.
O8
Output, 8mA sink, 4mA source.
OD8
IO8
IOD8
IS/O8
O12
Open Drain Output, 8mA sink.
Input/Output, 8mA sink, 4mA source.
Input/Open Drain Output, 8mA sink, 4mA source.
Input with Schmitt Trigger/Output, 8mA sink, 4mA source.
Output, 12mA sink, 6mA source.
2016-2017 Microchip Technology Inc.
DS00002121B-page 29
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 2-6:
Buffer
BUFFER DESCRIPTION (CONTINUED)
Description
OD12
OD4
Open Drain Output, 12mA sink.
Open Drain Output, 4mA sink.
IO12
Input/Output, 12mA sink, 6mA source.
Input/Open Drain Output, 12mA sink, 6mA source.
Open Drain Output, 14mA sink.
IOD12
OD14
OP14
OD_PH
Output, 14mA sink, 14mA source.
Input/Output (Open Drain), See DC Electrical Characteristics on page
252
IOP14
IO16
Input/Output, 14mA sink, 14mA source. Backdrive protected.
Input/Output 16mA sink.
IOD16
PCI_IO
Input/Output (Open Drain), 16mA sink.
Input/Output. These pins must meet the PCI 3.3V AC and DC
Characteristics.
PCI_O
Output. These pins must meet the PCI 3.3V AC and DC Characteristics.
(Note 2-16)
PCI_I
Input. These pins must meet the PCI 3.3V AC and DC Characteristics.
(Note 2-16)
PCI_ICLK
Clock Input. These pins must meet the PCI 3.3V AC and DC
Characteristics and timing. (Note 2-17)
nSW
n Channel Switch (Ron~25 Ohms)
ISPU_400
ISPU
Input with 400mV Schmitt Trigger and 30uA Integrated Pull-Up.
Input with Schmitt Trigger and Integrated Pull-Up.
Note 2-16
Note 2-17
See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2.
See the “PCI Local Bus Specification,” Revision 2.1, Section 4.2.2 and 4.2.3.
DS00002121B-page 30
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
3.0
BLOCK DIAGRAM
FIGURE 3-1:
SCH322X BLOCK DIAGRAM
1
2
D
E
L
D
E
L
WDT
CLK32
WDT
CLOCK
GEN
LEDs
CLOCKI
PD[7,0]
SERIAL
IRQ
SER_IRQ
PCI_CLK
BUSY, SLCT, PE,
nERROR, nACK
Multi-Mode
Parallel Port
with ChiProtectT
nSTROBE, nINIT,
nSLCTIN, nALF
Internal Bus
(Data, Address, and Control lines)
LPC
Bus Interface
LAD[3:0]
LFRAME#
LDRQ#
TXD1, RXD1
High-Speed
16550A
nCTS1, nRTS1
UART
PORT 1
nDSR1, nDTR1
nDCD1, nRI1
PCI_RESET#
TXD2 (IRTX),
RXD2 (IRRX)
High-Speed
16550A
UART
nIO_PME
nIO_SMI
CTS2, RTS2
DSR2, DTR2
DCD2, RI2
Power Mgmt
PORT 2
32 byte
Security
Key
nIDE_RSTDRV
PCI Reset
Outputs
Register
nPCIRST_OUT[1:3]
General
Purpose
I/O
GPIO Pins
MCLK, MDAT
A20M
Keyboard/Mouse
8042
controller
nKBDRST
KCLK, KDAT
TXD3, RXD3
nRSMRST
PWRGD_PS
nCTS3, nRTS3
nDSR3, nDTR3
PWRGD_OUT
`
Power Control
and Recovery;
Glue
SLP_SX#
PS_ON#
nFPRST
PB_IN#
nDCD3, nRI3
High-Speed
16550A
UART
TXD4, RXD4
PB_OUT#
PORT 3 & 4
nCTS4, nRTS4
nDSR4, nDTR4
TXD5, TXD6
High-Speed
16550A
UART
RXD5, RXD6
nSCIN5, nSCIN6
Hardware
Monitor
nDCD4, nRI4
PORT 5 & 6
nSCOUT5, nSCOUT6
Note 1: This diagram does not show power and ground
connections.
Note 2: Signal names are often located on multifunction
pins. This diagram is designed to show the various
functions available on the chip and should not be used as
a pin layout.
2016-2017 Microchip Technology Inc.
DS00002121B-page 31
SCH3227/SCH3226/SCH3224/SCH3222
4.0
POWER FUNCTIONALITY
The SCH322x has five power planes: VCC, HVTR, VREF, VTR, and Vbat.
4.1
VCC Power
The SCH322x is a 3.3 Volt part. The VCC supply is 3.3 Volts (nominal). VCC is the main power supply for the Super I/O
Block. See Section 26.2, "DC Electrical Characteristics," on page 252.
4.2
HVTR Power
The SCH322x is family of 3.3 Volt devices. The HVTR supply is 3.3 Volts (nominal). HVTR is a dedicated power supply
for the Hardware Monitoring Block. HVTR is connected to the VTR suspend well. See Section 26.2, "DC Electrical Char-
acteristics," on page 252.
Note:
The hardware monitoring logic is powered by HVTR, but only operational when VCC is on. The hardware
monitoring block is connected to the suspend well to retain the programmed configuration through a sleep
cycle.
4.3
VTR Support
The SCH322x requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events in the PME
interface when VCC is removed. The VTR supply is 3.3 Volts (nominal). See Section 26.0, "Operational Description,"
on page 252. The maximum VTR current that is required depends on the functions that are used in the part. See
Section 26.0.
If the SCH322x is not intended to provide wake-up capabilities on standby current, VTR can be connected to VCC. VTR
powers the IR interface, the PME configuration registers, and the PME interface. The VTR pin generates a VTR Power-
on-Reset signal to initialize these components. If VTR is to be used for programmable wake-up events when VCC is
removed, VTR must be at its full minimum potential at least 10 ms before Vcc begins a power-on cycle. Note that under
all circumstances, the hardware monitoring HVTR must be driven as the same source as VTR.
4.3.1
TRICKLE POWER FUNCTIONALITY
When the SCH322x is running under VTR only (VCC removed), PME wakeup events are active and (if enabled) able
to assert the nIO_PME pin active low.
The following requirements apply to all I/O pins that are specified to be 5 volt tolerant.
• I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may
only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR.
• I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by
VTR. This means, at a minimum, they will source their specified current from VTR even when VCC is present.
The GPIOs that are used for PME wakeup as input are GP21-GP22, GP27, GP32, GP33, GP50-GP57, GP60, GP61.
These GPIOs function as follows (with the exception of GP60 and GP61 - see below):
• Buffers are powered by VCC, but in the absence of VCC they are backdrive protected (they do not impose a load
on any external VTR powered circuitry). They are wakeup compatible as inputs under VTR power. These pins
have input buffers into the wakeup logic that are powered by VTR.
All GPIOs listed above are PME wakeup as a GPIO (or alternate function).
GP32 and GP33 revert to their non-inverting GPIO input function when VCC is removed from the part.
The other GPIOs function as follows:
GP36, GP37 and GP40:
• Buffers are powered by VCC. In the absence of VCC they are backdrive protected. These pins do not have input
buffers into the wakeup logic that are powered by VTR, and are not used for wakeup.
GP42, GP60 and GP61:
• Buffers powered by VTR. GP42 are the nIO_PME pin which is active under VTR. GP60 and GP61 have LED as
the alternate function and the logic is able to control the pin under VTR.
DS00002121B-page 32
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
The following list summarizes the blocks, registers and pins that are powered by VTR.
• PME interface block
• PME runtime register block (includes all PME, SMI, GPIO, Fan and other miscellaneous registers)
• Digital logic in the Hardware Monitoring block
• “Wake on Specific Key” logic
• LED control logic
• Watchdog Timer
• Power Recovery Logic
• Pins for PME Wakeup:
- GP42/nIO_PME (output, buffer powered by VTR)
- CLOCKI32 (input, buffer powered by VTR)
- nRI1 (input)
- GP50/nRI2 (input)
- GP52/RXD2(IRRX) (input)
- KDAT/GP21 (input)
- MDAT/GP32 (input)
- GPIOs (GP21-GP22, GP27, GP32, GP33, GP50-GP57, GP60, GP61) – all input-only except GP60, GP61.
See below.
• Other Pins
- GP60/LED1 (output, buffer powered by VTR)
- GP61/LED2 (output, buffer powered by VTR)
- nRSMRST
- PWRGD_PS
- PB_IN#
- PB_OUT#
- PS_ON#
- nFPRST
- SLP_SX#
- PWRGD_OUT
4.4
Vbat Support
Vbat is a battery generated power supply that is needed to support the power recovery logic. The power recovery logic
is used to restore power to the system in the event of a power failure. Power may be returned to the system by a key-
board power button, the main power button, or by the power recovery logic following an unexpected power failure.
The Vbat supply is 3.0 Volts (nominal). See Section 26.0, "Operational Description," on page 252.
The following Runtime Registers are powered by Vbat:
• Bank 2 of the Runtime Register block used for the 32kbyte Security Key register
• PME_EN7 at offset 10h
• PWR_REC Register at offset 49h
• PS_ON Register at offset 4Ah
• PS_ON Previous State Register at offset 53h
• DBLCLICK register at offset 5Bh
• Keyboard Scan Code – Make Byte 1 at offset 5Fh
• Keyboard Scan Code – Make Byte 2 at offset 60h
• Keyboard Scan Code – Break Byte 1 at offset 61h
• Keyboard Scan Code – Break Byte 2 at offset 62h
• Keyboard Scan Code – Break Byte 3 at offset 63h
• Keyboard PWRBTN/SPEKEY at offset 64h
2016-2017 Microchip Technology Inc.
DS00002121B-page 33
SCH3227/SCH3226/SCH3224/SCH3222
Note:
All Vbat powered pins and registers are powered by VTR when VTR power is on and are battery backed-
up when VTR is removed.
4.5
32.768 KHz Trickle Clock Input
The SCH322x utilizes a 32.768 KHz trickle input to supply a clock signal for the WDT, LED blink, Power Recovery Logic,
and wake on specific key function.
Indication of 32KHZ Clock
There is a bit to indicate whether or not the 32KHz clock input is connected to the SCH322x. This bit is located at bit 0
of the CLOCKI32 register at 0xF0 in Logical Device A. This register is powered by VTR and reset on a VTR POR.
Bit[0] (CLK32_PRSN) is defined as follows:
0=32KHz clock is connected to the CLKI32 pin (default)
1=32KHz clock is not connected to the CLKI32 pin (pin is grounded).
Bit 0 controls the source of the 32KHz (nominal) clock for the LED blink logic and the “wake on specific key” logic. When
the external 32KHz clock is connected, that will be the source for the fan, LED and “wake on specific key” logic. When
the external 32KHz clock is not connected, an internal 32KHz clock source will be derived from the 14MHz clock for the
LED and “wake on specific key” logic.
The following functions will not work under VTR power (VCC removed) if the external 32KHz clock is not connected.
These functions will work under VCC power even if the external 32 KHz clock is not connected.
• Wake on specific key
• LED blink
• Power Recovery Logic
• WDT
• Front Panel Reset with Input Debounce, Power Supply Gate, and CPU Powergood Signal Generation
4.6
Super I/O Functions
The maximum VTR current, ITR, is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0V or
3.3V). The total maximum current for the part is the unloaded value PLUS the maximum current sourced by the pin that
is driven by VTR. The super I/O pins that are powered by VTR are as follows: GP42/nIO_PME, GP60/LED1, and
GP61/LED2. These pins, if configured as push-pull outputs, will source a minimum of 6mA at 2.4V when driving.
The maximum VCC current, ICC, is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0V or
3.3V).
The maximum Vbat current, Ibat, is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0V or 3.3V).
4.7
Power Management Events (PME/SCI)
The SCH322x offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI)
events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of an event
to the chipset via the assertion of the nIO_PME output signal. See the Section 13.0, "PME Support," on page 94 section.
DS00002121B-page 34
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
5.0
5.1
LPC INTERFACE
LPC Interface Signal Definition
The signals implemented for the LPC bus interface are described in the tables below. LPC bus signals use PCI 33MHz
electrical signal characteristics.
5.1.1
LPC REQUIRED SIGNALS
Type
I/O
Signal Name
Description
LAD[3:0]
LPC address/data bus. Multiplexed command, address and data bus.
Frame signal. Indicates start of new cycle and termination of broken cycle
LFRAME#
PCI_RESET#
Input
Input
PCI Reset. Used as LPC Interface Reset. Same functionality as RST_DRV but active
low 3.3V.
PCI_CLK
Input
PCI Clock.
5.1.2
LPC OPTIONAL SIGNALS
Signal Name
Type
Description
Comment
Implemented
LDRQ#
Output
I/O
Encoded DMA/Bus Master request for the LPC interface.
SER_IRQ
CLKRUN#
nIO_PME
Serial IRQ.
Clock Run
Implemented
OD
Not Implemented
OD
Same as the PME# or Power Mgt Event signal. Allows the Implemented
SCH3227/SCH3226/SCH3224/SCH3222 to request
wakeup in S3 and below.
LPCPD#
LSMI#
I
Power down - Indicates that the device should prepare for Not Implemented
LPC I/F shutdown
OD
Only need for SMI# generation on I/O instruction for retry. Not Implemented
5.2
Supported LPC Cycles
Table 5-1 summarizes the cycle types are supported by the SCH3227/SCH3226/SCH3224/SCH3222. All other cycle
types are ignored.
TABLE 5-1:
SUPPORTED LPC CYCLES
Cycle Type
Transfer Size
Comment
I/O Write
I/O Read
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
2 Byte
4 Byte
1 Byte
2 Byte
4 Byte
1 Byte
2 Byte
4 Byte
1 Byte
2 Byte
4 Byte
1 Byte
Supported
Supported
Memory Write
Not Supported
Not Supported
Supported
Memory Read
DMA Write
DMA Write
Supported
DMA Write
Not Supported
Supported
DMA Read
DMA Read
Supported
DMA Read
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
Bus Master Memory Write
Bus Master Memory Write
Bus Master Memory Write
Bus Master Memory Read
Bus Master Memory Read
Bus Master Memory Read
Bus Master I/O Write
2016-2017 Microchip Technology Inc.
DS00002121B-page 35
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 5-1:
Cycle Type
Bus Master I/O Write
SUPPORTED LPC CYCLES (CONTINUED)
Transfer Size
Comment
2 Byte
4 Byte
1 Byte
2 Byte
4 Byte
Not Supported
Not Supported
Not Supported
Not Supported
Not Supported
Bus Master I/O Write
Bus Master I/O Read
Bus Master I/O Read
Bus Master I/O Read
5.3
Device Specific Information
The LPC interface conforms to the “Low Pin Count (LPC) Interface Specification”. The following section will review any
implementation specific information for this device.
5.3.1
SYNC PROTOCOL
The SYNC pattern is used to add wait states. For read cycles, the SCH3227/SCH3226/SCH3224/SCH3222 immedi-
ately drives the SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles.
If the SCH3227/SCH3226/SCH3224/SCH3222 needs to assert wait states, it does so by driving 0101 or 0110 on
LAD[3:0] until it is ready, at which point it will drive 0000 or 1001. The SCH3227/SCH3226/SCH3224/SCH3222 will
choose to assert 0101 or 0110, but not switch between the two patterns.
The data (or wait state SYNC) will immediately follow the 0000 or 1001 value. The SYNC value of 0101 is intended to
be used for normal wait states, wherein the cycle will complete within
a
few clocks. The
SCH3227/SCH3226/SCH3224/SCH3222 uses a SYNC of 0101 for all wait states in a DMA transfer.
The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP cycles,
where the number of wait states could be quite large (>1 microsecond). However, the
SCH3227/SCH3226/SCH3224/SCH3222 uses a SYNC of 0110 for all wait states in an I/O transfer.
The SYNC value is driven within 3 clocks.
5.3.2
RESET POLICY
The following rules govern the reset policy:
• When PCI_RESET# goes inactive (high), the PCI clock is assumed to have been running for 100usec prior to the
removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable that
is used for the PCI bus.
• When PCI_RESET# goes active (low):
1. The host drives the LFRAME# signal high, tristates the LAD[3:0] signals, and ignores the LDRQ# signal.
2. The SCH3227/SCH3226/SCH3224/SCH3222 ignores LFRAME#, tristates the LAD[3:0] pins and drives the
LDRQ# signal inactive (high).
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6.0
SERIAL PORT (UART)
The SCH3227/SCH3226/SCH3224/SCH3222 family incorporates up to four full function UARTs and up to two 4 pin
UARTS, for a total of 6 available. They are register compatible with the ACE architecture (NS16450, NS16C550A). The
UARTS perform serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit char-
acters. The data rates are independently programmable from 460.8K baud down to 50 baud. The character options are
programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each
contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to
65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration Registers for informa-
tion on disabling, power down and changing the base address of the UARTs. The interrupt from a UART is enabled by
programming OUT2 of that UART to a logic “1”. OUT2 being a logic “0” disables that UART’s interrupt. The second
UART also supports IrDA, HP-SIR and ASK-IR modes of operation.
6.1
Register Description
Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are
defined by the configuration registers (see Section 23.0, "Configuration Registers," on page 194). The Serial Port reg-
isters are located at sequentially increasing addresses above these base addresses. The register set of the UARTS are
described below.
TABLE 6-1:
DLAB*
ADDRESSING THE SERIAL PORT
A2
A1
A0
Register Name
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
Receive Buffer (read)
Transmit Buffer (write)
0
Interrupt Enable (read/write)
Interrupt Identification (read)
FIFO Control (write)
X
X
X
X
X
X
X
1
Line Control (read/write)
Modem Control (read/write)
Line Status (read/write)
Modem Status (read/write)
Scratchpad (read/write)
Divisor LSB (read/write)
Divisor MSB (read/write
1
Note:
The following section describes the operation of the registers.
6.1.1 RECEIVE BUFFER REGISTER (RB)
*DLAB is Bit 7 of the Line Control Register
Address Offset = 0H, DLAB = 0, READ ONLY
This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received
first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert
it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not accessible.
6.1.2
TRANSMIT BUFFER REGISTER (TB)
Address Offset = 0H, DLAB = 0, WRITE ONLY
This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift
register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the Transmit
Buffer when the transmission of the previous byte is complete.
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6.1.3
INTERRUPT ENABLE REGISTER (IER)
Address Offset = 1H, DLAB = 0, READ/WRITE
The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is possible
to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits
of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identi-
fication Register and disables any Serial Port interrupt out of the SCH3227/SCH3226/SCH3224/SCH3222. All other
system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents
of the Interrupt Enable Register are described below.
Bit 0
This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic “1”.
Bit 1
This bit enables the Transmitter Holding Register Empty Interrupt when set to logic “1”.
Bit 2
This bit enables the Received Line Status Interrupt when set to logic “1”. The error sources causing the interrupt are
Overrun, Parity, Framing and Break. The Line Status Register must be read to determine the source.
Bit 3
This bit enables the MODEM Status Interrupt when set to logic “1”. This is caused when one of the Modem Status Reg-
ister bits changes state.
Bits 4 through 7
These bits are always logic “0”.
6.1.4
FIFO CONTROL REGISTER (FCR)
Address Offset = 2H, DLAB = X, WRITE
This is a write only register at the same location as the IIR. This register is used to enable and clear the FIFOs, set the
RCVR FIFO trigger level.
Note:
DMA is not supported. The UART1 and UART2 FCRs are shadowed in the UART1 FIFO Control Shadow
Register (runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at
offset 0x21).
Bit 0
Setting this bit to a logic “1” enables both the XMIT and RCVR FIFOs. Clearing this bit to a logic “0” disables both the
XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO (16450)
mode, data is automatically cleared from the FIFOs. This bit must be a 1 when other bits in this register are written to
or they will not be properly programmed.
Bit 1
Setting this bit to a logic “1” clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is not
cleared. This bit is self-clearing.
Bit 2
Setting this bit to a logic “1” clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not
cleared. This bit is self-clearing.
Bit 3
Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not available on this chip.
Bit 4,5
Reserved
Bit 6,7
These bits are used to set the Trigger Level For The Rcvr Fifo Interrupt.
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6.1.5
INTERRUPT IDENTIFICATION REGISTER (IIR)
Address Offset = 2H, DLAB = X, READ
By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority
interrupt exist. They are in descending order of priority:
1. Receiver Line Status (highest priority)
2. Received Data Ready
3. Transmitter Holding Register Empty
4. MODEM Status (lowest priority)
Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Iden-
tification Register (refer to Table 6-2 on page 39). When the CPU accesses the IIR, the Serial Port freezes all interrupts
and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records
new interrupts, the current indication does not change until access is completed. The contents of the IIR are described
below.
Bit 0
This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending.
When bit 0 is a logic “0”, an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate
internal service routine. When bit 0 is a logic “1”, no interrupt is pending.
Bits 1 and 2
These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the Interrupt Control
Table (Table 6-2).
Bit 3
In non-FIFO mode, this bit is a logic “0”. In FIFO mode this bit is set along with bit 2 when a timeout interrupt is pending.
Bits 4 and 5
These bits of the IIR are always logic “0”.
Bits 6 and 7
These two bits are set when the FIFO CONTROL Register bit 0 equals 1.
RCVR FIFO
Trigger Level (BYTES)
Bit 7
Bit 6
0
0
1
1
0
1
0
1
1
4
8
14
TABLE 6-2:
INTERRUPT CONTROL
FIFO
Mode
Only
Interrupt Identification
Register
Interrupt Set and Reset Functions
BIT 3
BIT 2
BIT 1
BIT 0
PRIORITY
LEVEL
INTERRUPT
TYPE
INTERRUPT
SOURCE
INTERRUPT
RESET CONTROL
0
0
0
1
0
1
1
0
-
None
None
-
Highest
Receiver Line
Status
Overrun Error, Parity Reading the Line
Error, Framing Error Status Register
or Break Interrupt
0
1
0
0
Second
Received Data
Available
Receiver Data
Available
Read Receiver
Buffer or the FIFO
drops below the
trigger level.
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TABLE 6-2:
INTERRUPT CONTROL (CONTINUED)
FIFO
Mode
Only
Interrupt Identification
Interrupt Set and Reset Functions
Register
1
0
1
0
0
Second
Character
Timeout
No Characters Have Reading the
Been Removed Receiver Buffer
Indication
From or Input to the Register
RCVR FIFO during
the last 4 Char times
and there is at least
1 char in it during
this time
0
0
1
0
0
0
Third
Transmitter
Holding Register Register Empty
Empty
Transmitter Holding Reading the IIR
Register (if Source
of Interrupt) or
Writing the
Transmitter Holding
Register
0
Fourth
MODEM Status Clear to Send or
Data Set Ready or
Reading the
MODEM Status
Register
Ring Indicator or
Data Carrier Detect
6.1.6
LINE CONTROL REGISTER (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE
FIGURE 6-1:
SERIAL DATA
Start LSB Data 5-8 bits MSB Parity Stop
This register contains the format information of the serial line. The bit definitions are:
Bits 0 and 1
These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and 1
is as follows:
The Start, Stop and Parity bits are not included in the word length.
Bit 1
Bit 0
Word Length
0
0
1
1
0
1
0
1
5 Bits
6 Bits
7 Bits
8 Bits
Bit 2
This bit specifies the number of stop bits in each transmitted or received serial character. The following table summa-
rizes the information.
Bit 2
Word Length
Number of Stop Bits
0
1
1
1
1
--
1
1.5
2
5 bits
6 bits
7 bits
8 bits
2
2
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Note:
Bit 3
The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.
Parity Enable bit. When bit 3 is a logic “1”, a parity bit is generated (transmit data) or checked (receive data) between
the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number
of 1s when the data word bits and the parity bit are summed).
Bit 4
Even Parity Select bit. When bit 3 is a logic “1” and bit 4 is a logic “0”, an odd number of logic “1”’s is transmitted or
checked in the data word bits and the parity bit. When bit 3 is a logic “1” and bit 4 is a logic “1” an even number of bits
is transmitted and checked.
Bit 5
This bit is the Stick Parity bit. When parity is enabled it is used in conjunction with bit 4 to select Mark or Space Parity.
When LCR bits 3, 4 and 5 are 1 the Parity bit is transmitted and checked as a 0 (Space Parity). If bits 3 and 5 are 1 and
bit 4 is a 0, then the Parity bit is transmitted and checked as 1 (Mark Parity). If bit 5 is 0 Stick Parity is disabled.
Bit 6
Set Break Control bit. When bit 6 is a logic “1”, the transmit data output (TXD) is forced to the Spacing or logic “0” state
and remains there (until reset by a low level bit 6) regardless of other transmitter activity. This feature enables the Serial
Port to alert a terminal in a communications system.
Bit 7
Divisor Latch Access bit (DLAB). It must be set high (logic “1”) to access the Divisor Latches of the Baud Rate Generator
during read or write operations. It must be set low (logic “0”) to access the Receiver Buffer Register, the Transmitter
Holding Register, or the Interrupt Enable Register.
6.1.7
MODEM CONTROL REGISTER (MCR)
Address Offset = 4H, DLAB = X, READ/WRITE
This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of
the MODEM control register are described below.
Bit 0
This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic “1”, the nDTR output is forced to
a logic “0”. When bit 0 is a logic “0”, the nDTR output is forced to a logic “1”.
Bit 1
This bit controls the Request To Send (nRTS) output. Bit 1 affects the nRTS output in a manner identical to that
described above for bit 0.
Bit 2
This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the CPU.
Bit 3
Output 2 (OUT2). This bit is used to enable an UART interrupt. When OUT2 is a logic "0", the serial port interrupt output
is forced to a high impedance state - disabled. When OUT2 is a logic "1", the serial port interrupt outputs are enabled.
Bit 4
This bit provides the loopback feature for diagnostic testing of the Serial Port. When bit 4 is set to logic “1”, the following
occur:
1. The TXD is set to the Marking State (logic “1”).
2. The receiver Serial Input (RXD) is disconnected.
3. The output of the Transmitter Shift Register is “looped back” into the Receiver Shift Register input.
4. All MODEM Control inputs (nCTS, nDSR, nRI and nDCD) are disconnected.
5. The four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2) are internally connected to the four MODEM
Control inputs (nDSR, nCTS, RI, DCD).
6. The Modem Control output pins are forced inactive high.
7. Data that is transmitted is immediately received.
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This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the diagnostic mode,
the receiver and the transmitter interrupts are fully operational. The MODEM Control Interrupts are also operational but
the interrupts’ sources are now the lower four bits of the MODEM Control Register instead of the MODEM Control inputs.
The interrupts are still controlled by the Interrupt Enable Register.
Bits 5 through 7
These bits are permanently set to logic zero.
6.1.8
LINE STATUS REGISTER (LSR)
Address Offset = 5H, DLAB = X, READ/WRITE
Bit 0
Data Ready (DR). It is set to a logic “1” whenever a complete incoming character has been received and transferred
into the Receiver Buffer Register or the FIFO. Bit 0 is reset to a logic “0” by reading all of the data in the Receive Buffer
Register or the FIFO.
Bit 1
Overrun Error (OE). Bit 1 indicates that data in the Receiver Buffer Register was not read before the next character was
transferred into the register, thereby destroying the previous character. In FIFO mode, an overrun error will occur only
when the FIFO is full and the next character has been completely received in the shift register, the character in the shift
register is overwritten but not transferred to the FIFO. The OE indicator is set to a logic “1” immediately upon detection
of an overrun condition, and reset whenever the Line Status Register is read.
Bit 2
Parity Error (PE). Bit 2 indicates that the received data character does not have the correct even or odd parity, as
selected by the even parity select bit. The PE is set to a logic “1” upon detection of a parity error and is reset to a logic
“0” whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular character in
the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO.
Bit 3
Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic “1”
whenever the stop bit following the last data bit or parity bit is detected as a zero bit (Spacing level). The FE is reset to
a logic “0” whenever the Line Status Register is read. In the FIFO mode this error is associated with the particular char-
acter in the FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. The Serial
Port will try to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start
bit, so it samples this ‘start’ bit twice and then takes in the ‘data’.
Bit 4
Break Interrupt (BI). Bit 4 is set to a logic “1” whenever the received data input is held in the Spacing state (logic “0”) for
longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). The
BI is reset after the CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated with
the particular character in the FIFO it applies to. This error is indicated when the associated character is at the top of
the FIFO. When break occurs only one zero character is loaded into the FIFO. Restarting after a break is received,
requires the serial data (RXD) to be logic “1” for at least ½ bit time.
Note:
Bits 1 through 4 are the error conditions that produce a Receiver Line Status Interrupt whenever any of the
corresponding conditions are detected and the interrupt is enabled.
Bit 5
Transmitter Holding Register Empty (THRE). Bit 5 indicates that the Serial Port is ready to accept a new character for
transmission. In addition, this bit causes the Serial Port to issue an interrupt when the Transmitter Holding Register inter-
rupt enable is set high. The THRE bit is set to a logic “1” when a character is transferred from the Transmitter Holding
Register into the Transmitter Shift Register. The bit is reset to logic “0” whenever the CPU loads the Transmitter Holding
Register. In the FIFO mode this bit is set when the XMIT FIFO is empty, it is cleared when at least 1 byte is written to
the XMIT FIFO. Bit 5 is a read only bit.
Bit 6
Transmitter Empty (TEMT). Bit 6 is set to a logic “1” whenever the Transmitter Holding Register (THR) and Transmitter
Shift Register (TSR) are both empty. It is reset to logic “0” whenever either the THR or TSR contains a data character.
Bit 6 is a read only bit. In the FIFO mode this bit is set whenever the THR and TSR are both empty,
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Bit 7
This bit is permanently set to logic “0” in the 450 mode. In the FIFO mode, this bit is set to a logic “1” when there is at
least one parity error, framing error or break indication in the FIFO. This bit is cleared when the LSR is read if there are
no subsequent errors in the FIFO.
6.1.9
MODEM STATUS REGISTER (MSR)
Address Offset = 6H, DLAB = X, READ/WRITE
This 8 bit register provides the current state of the control lines from the MODEM (or peripheral device). In addition to
this current state information, four bits of the MODEM Status Register (MSR) provide change information. These bits
are set to logic “1” whenever a control input from the MODEM changes state. They are reset to logic “0” whenever the
MODEM Status Register is read.
Bit 0
Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the
MSR was read.
Bit 1
Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input has changed state since the last time the MSR was
read.
Bit 2
Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI input has changed from logic “0” to logic “1”.
Bit 3
Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state.
Note:
Whenever bit 0, 1, 2, or 3 is set to a logic “1”, a MODEM Status Interrupt is generated.
Bit 4
This bit is the complement of the Clear To Send (nCTS) input. If bit 4 of the MCR is set to logic “1”, this bit is equivalent
to nRTS in the MCR.
Bit 5
This bit is the complement of the Data Set Ready (nDSR) input. If bit 4 of the MCR is set to logic “1”, this bit is equivalent
to DTR in the MCR.
Bit 6
This bit is the complement of the Ring Indicator (nRI) input. If bit 4 of the MCR is set to logic “1”, this bit is equivalent to
OUT1 in the MCR.
Bit 7
This bit is the complement of the Data Carrier Detect (nDCD) input. If bit 4 of the MCR is set to logic “1”, this bit is equiv-
alent to OUT2 in the MCR.
6.1.10
SCRATCHPAD REGISTER (SCR)
Address Offset =7H, DLAB =X, READ/WRITE
This 8 bit read/write register has no effect on the operation of the Serial Port. It is intended as a scratchpad register to
be used by the programmer to hold data temporarily.
6.1.11
PROGRAMMABLE BAUD RATE GENERATOR (AND DIVISOR LATCHES DLH, DLL)
The Serial Port contains a programmable Baud Rate Generator that is capable of dividing the internal PLL clock by any
divisor from 1 to 65535. The internal PLL clock is divided down to generate a 1.8462MHz frequency for Baud Rates less
than 38.4k, a 1.8432MHz frequency for 115.2k, a 3.6864MHz frequency for 230.4k and a 7.3728MHz frequency for
460.8k. This output frequency of the Baud Rate Generator is 16x the Baud rate. Two 8 bit latches store the divisor in 16
bit binary format. These Divisor Latches must be loaded during initialization in order to insure desired operation of the
Baud Rate Generator. Upon loading either of the Divisor Latches, a 16 bit Baud counter is immediately loaded. This
prevents long counts on initial load. If a 0 is loaded into the BRG registers the output divides the clock by the number 3.
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If a 1 is loaded the output is the inverse of the input oscillator. If a two is loaded the output is a divide by 2 signal with a
50% duty cycle. If a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. The input
clock to the BRG is a 1.8462 MHz clock.
Programming High Speed Serial Port baud Rates
The SCH322x family of devices supports serial ports with speeds up to 1.5Mb/s. Changing the serial ports baud rates
between standard speeds (115k baud and slower) during runtime is possible with standard drivers. In order to change
baud rates to high speed (230k, 460k, 921k and 1.5M bauds) on the SCH322x devices during runtime, registers in both
Configuration space and Runtime space must be programmed.
Note that this applies only if the application requires a serial port baud rate to change during runtime. Standard windows
drivers could be used to select the specific high speed rate if it will remain unchanged during runtime Table 6-4 on
page 45 shows the baud rates possible.
6.1.12
EFFECT OF THE RESET ON THE REGISTER FILE
The Reset Function (details the effect of the Reset input on each of the registers of the Serial Port.
6.1.13
FIFO INTERRUPT MODE OPERATION
When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = “1”, IER bit 0 = “1”), RCVR interrupts occur as
follows:
• The receive data available interrupt will be issued when the FIFO has reached its programmed trigger level; it is
cleared as soon as the FIFO drops below its programmed trigger level.
• The IIR receive data available indication also occurs when the FIFO trigger level is reached. It is cleared when the
FIFO drops below the trigger level.
• The receiver line status interrupt (IIR=06H), has higher priority than the received data available (IIR=04H) inter-
rupt.
• The data ready bit (LSR bit 0) is set as soon as a character is transferred from the shift register to the RCVR FIFO.
It is reset when the FIFO is empty.
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occur as follows:
• A FIFO timeout interrupt occurs if all the following conditions exist:
At least one character is in the FIFO.
The most recent serial character received was longer than 4 continuous character times ago. (If 2 stop bits are pro-
grammed, the second one is included in this time delay).
The most recent CPU read of the FIFO was longer than 4 continuous character times ago.
This will cause a maximum character received to interrupt issued delay of 160 msec at 300 BAUD with a 12-bit charac-
ter.
• Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the
baud rate).
• When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one character from
the RCVR FIFO.
• When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the
CPU reads the RCVR FIFO.
When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = “1”, IER bit 1 = “1”), XMIT interrupts occur as
follows:
• The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as soon as the
transmitter holding register is written to (1 of 16 characters may be written to the XMIT FIFO while servicing this
interrupt) or the IIR is read.
• The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever the
following occurs: THRE=1 and there have not been at least two bytes at the same time in the transmitter FIFO
since the last THRE=1. The transmitter interrupt after changing FCR0 will be immediate, if it is enabled.
Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data available
interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty interrupt.
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6.1.14
FIFO POLLED MODE OPERATION
With FCR bit 0 = “1” resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of operation.
Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of operation. In
this mode, the user’s program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled
Mode are as follows:
Bit 0=1 as long as there is one byte in the RCVR FIFO.
Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt
mode, the IIR is not affected since EIR bit 2=0.
Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and shift register are empty.
Bit 7 indicates whether there are any errors in the RCVR FIFO.
There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT
FIFOs are still fully capable of holding characters.
6.1.15
FREQUENCY SELECTION
Each Serial Port mode register (at offset 0xF0 in Logical devices 0x4, 0x5, 0xB - 0xE) the frequency is selected as
shown in Table 6-3.
TABLE 6-3:
SERIAL PORTS MODE REGISTER
Serial Port 1-6
Mode Register
0xF0 R/W
In all of the SP
Logical Devices
Bit[0] MIDI Mode
= 0 MIDI support disabled (default)
= 1 MIDI support enabled
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Bit[1] High Speed
= 0 High Speed Disabled (default)
= 1 High Speed Enabled
Bit [3:2] Enhanced Frequency Select
= 00 Standard Mode (default)
= 01 Select 921K
= 10 Select 1.5M
= 11 Reserved
Bit[7:4] Refer to Section 6.3, "Interrupt Sharing" for more detail.
Figure 6-2 illustrates the effect of programming bits[3:0] of the Mode register (at offset 0xF0 in the respective logical
device) on the Baud rate. Table 6-4 summarizes this functionality.
TABLE 6-4:
BAUD RATES
Enhanced
Frequency
Select Bit
Percent Error
Difference
Between Desired
and Actual
Divisor Used to Generate 16X
Clock
Midi
Mode
High
Speed
Desired Baud
Rate
Bits[12:0]
Note 6-2
50
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2304
1536
1047
857
768
384
192
96
0.001
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
75
-
110
-
134.5
150
300
600
1200
1800
2000
0.004
-
-
-
-
64
-
58
0.005
2016-2017 Microchip Technology Inc.
DS00002121B-page 45
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 6-4:
BAUD RATES (CONTINUED)
Enhanced
Frequency
Select Bit
Percent Error
Difference
Between Desired
and Actual
Divisor Used to Generate 16X
Clock
Midi
Mode
High
Speed
Desired Baud
Rate
Bits[12:0]
Note 6-2
2400
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
48
32
24
16
12
6
-
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
X
0
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
1
3600
-
4800
-
7200
-
9600
-
19200
38400
57600
115200
230400
460800
921600
1500000
-
3
0.030
0.16
0.16
0.16
0.16
0.16
0.16
0.16
2
1
2
1
1
1
X
0
31250 (Note 6-
1)
4
0
Note 6-1
31250 Khz is the MIDI frequency. It is possible to program other baud rates when the MIDI bit is set
by changing the divisor register, but the device will not be midi compliant.
Note 6-2
The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
FIGURE 6-2:
BAUD RATE SELECTION
Reg 0xF0 Bit[1]
Divisor Bit[15]
Note: High Speed Mode. When configured
hsp1
for high speed operation, the F0 bits[3:1] are
set to 1 and the hsp bit [3:1] are controlled by
the divisor bits[15:13].
Reg 0xF0 Bit[2]
Divisor Bit[14]
hsp2
Reg 0xF0
Bit[0]
Reg 0xF0 Bit[3]
Divisor Bit[13]
hsp3
DIVIDE
BY 12
hsp1
MIDI
Sel
96M
24M
User
Programmed
Divisor
DIVIDE
BY 13
Baud
Rate
Mux
X 16
0
(13 bit)
1
3:2
DIVIDE
BY 6.5
Frequency
Select
DS00002121B-page 46
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 6-5:
REGISTER RESET
Register Bit
Reset Control
Reset State
Interrupt Enable Register
Interrupt Identification Reg.
FIFO Control
RESET
RESET
RESET
RESET
RESET
RESET
RESET
All bits low
Bit 0 is high; Bits 1 - 7 low
All bits low
Line Control Reg.
All bits low
MODEM Control Reg.
Line Status Reg.
All bits low
All bits low except 5, 6 high
MODEM Status Reg.
INTRPT (RCVR errs)
INTRPT (RCVR Data Ready)
INTRPT (THRE)
Bits 0 - 3 low; Bits 4 - 7 input
RESET/Read LSR
Low
RESET/Read RBR
Low
RESET/Read IIR/Write THR
Low
RCVR FIFO
RESET/
FCR1*FCR0/_FCR0
All Bits Low
XMIT FIFO
RESET/
FCR1*FCR0/_FCR0
All Bits Low
TABLE 6-6:
PIN RESET
Pin Signal
Reset Control
Reset State
TXDn
RESET
RESET
RESET
High-Z (Note 6-3)
High-Z (Note 6-3)
High-Z (Note 6-3)
nRTSx
nDTRx
Note 6-3
Serial ports 1 and 2 may be placed in the powerdown mode by clearing the associated activate bit
located at CR30 or by clearing the associated power bit located in the Power Control register at
CR22. Serial ports 3,4,5,6 (if available) may be placed in the powerdown mode by clearing the
associated activate bit located at CR30. When in the powerdown mode, the serial port outputs are
tristated. In cases where the serial port is multiplexed as an alternate function, the corresponding
output will only be tristated if the serial port is the selected alternate function.
2016-2017 Microchip Technology Inc.
DS00002121B-page 47
TABLE 6-7:
REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL
Register
Address
(Note 6-4)
Register
Symbol
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADDR = 0
DLAB = 0
Receive Buffer Register
(Read Only)
RBR
Data Bit 7
Data Bit 7
Data Bit 6
Data Bit 6
Data Bit 5
Data Bit 5
Data Bit 4
Data Bit 4
Data Bit 3
Data Bit 3
Data Bit 2
Data Bit 2
Data Bit 1
Data Bit 1
Data Bit 0
(Note 6-5)
ADDR = 0
DLAB = 0
Transmitter Holding Reg-
ister
THR
IER
Data Bit 0
(Write Only)
ADDR = 1
DLAB = 0
Interrupt Enable Register
0
0
0
0
Enable
MODEM Sta-
tus Interrupt
(EMSI)
Enable
Receiver
Enable
Transmitter
Enable
Received
Line Status Holding Reg- Data Avail-
Interrupt
(ELSI)
ister Empty
Interrupt
able Inter-
rupt (ERDAI)
(ETHREI)
ADDR = 2
ADDR = 2
ADDR = 3
ADDR = 4
ADDR = 5
Interrupt Ident. Register
(Read Only)
IIR
FIFOs
Enabled
(Note 6-9)
FIFOs
Enabled
(Note 6)
0
0
Interrupt ID
Bit (Note 6-9)
Interrupt ID
Bit
Interrupt ID “0” if Interrupt
Bit Pending
FIFO Control Register
(Write Only)
FCR
(Note 6-11)
RCVR Trig-
ger MSB
RCVR Trig-
ger LSB
Reserved
Stick Parity
0
Reserved
DMA Mode
Select
(Note 6-10)
XMIT FIFO
Reset
RCVR FIFO FIFO Enable
Reset
Line Control Register
LCR
MCR
LSR
Divisor Latch
Access Bit
(DLAB)
Set Break
0
Even Parity ParityEnable
Select (EPS)
Number of
Stop Bits
(STB)
Word Length Word Length
(PEN)
Select Bit 1
(WLS1)
Select Bit 0
(WLS0)
MODEM Control Regis-
ter
0
Loop
OUT2
(Note 6-7)
OUT1
(Note 6-7)
Request to
Send (RTS)
Data Termi-
nal Ready
(DTR)
Line Status Register
Error in
RCVR FIFO
(Note 6-9)
Transmitter
Empty
(TEMT)
Transmitter
Holding Reg-
ister (THRE)
Break Inter-
rupt (BI)
Framing
Error (FE)
Parity Error
(PE)
Overrun
Error (OE)
Data Ready
(DR)
(Note 6-6)
ADDR = 6
ADDR = 7
MODEM Status Register
MSR
SCR
Data Carrier Ring Indica-
Data Set
Ready (DSR) Send (CTS)
Clear to
Delta Data Trailing Edge
Delta Data
Set Ready
(DDSR)
Delta Clear
to Send
(DCTS)
Detect (DCD)
Bit 7
tor (RI)
Carrier
Detect
Ring Indica-
tor (TERI)
(DDCD)
Scratch Register
(Note 6-8)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TABLE 6-7:
REGISTER SUMMARY FOR AN INDIVIDUAL UART CHANNEL (CONTINUED)
Register
Address
(Note 6-4)
Register
Symbol
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADDR = 0
DLAB = 1
Divisor Latch (LS)
Divisor Latch (MS)
DDL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 9
Bit 0
Bit 8
ADDR = 1
DLAB = 1
DLM
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Note 6-4
Note 6-5
Note 6-6
Note 6-7
Note 6-8
Note 6-9
Note 6-10
Note 6-11
DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
This bit no longer has a pin associated with it.
When operating in the XT mode, this register is not available.
These bits are always zero in the non-FIFO mode.
Writing a one to this bit has no effect. DMA modes are not supported in this chip.
The UARTs FCR’s are shadowed UART FIFO Control Shadow Registers. See Section 24.0, "Runtime Register" for more details.
SCH3227/SCH3226/SCH3224/SCH3222
6.1.16
NOTES ON SERIAL PORT OPERATION
FIFO Mode Operation:
General
The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected.
6.1.16.1
TX and RX FIFO Operation
The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx FIFO. The UART
will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the Tx FIFO will again be enabled as
soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous
operation of the Tx.
The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO
is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is empty and the
CPU starts to load it. When the first byte enters the FIFO the Tx FIFO empty interrupt will transition from active to inac-
tive. Depending on the execution speed of the service routine software, the UART may be able to transfer this byte from
the FIFO to the shift register before the CPU loads another byte. If this happens, the Tx FIFO will be empty again and
typically the UART’s interrupt line would transition to the active state. This could cause a system with an interrupt control
unit to record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt. Therefore, after the
first byte has been loaded into the FIFO the UART will wait one serial character transmission time before issuing a new
Tx FIFO empty interrupt. This one character Tx interrupt delay will remain active until at least two bytes have been
loaded into the FIFO, concurrently. When the Tx FIFO empties after this condition, the Tx interrupt will be activated with-
out a one character delay.
Rx support functions and operation are quite different from those described for the transmitter. The Rx FIFO receives
data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are
enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it holds 16 of them.
It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag.
Normally, the FIFO depth and the programmable trigger levels will give the CPU ample time to empty the Rx FIFO before
an overrun occurs.
One side-effect of having a Rx FIFO is that the selected interrupt trigger level may be above the data level in the FIFO.
This could occur when data at the end of the block contains fewer bytes than the trigger level. No interrupt would be
issued to the CPU and the data would remain in the UART. To prevent the software from having to check for this situation
the chip incorporates a timeout interrupt.
The timeout interrupt is activated when there is a least one byte in the Rx FIFO, and neither the CPU nor the Rx shift
register has accessed the Rx FIFO within 4 character times of the last byte. The timeout interrupt is cleared or reset
when the CPU reads the Rx FIFO or another character enters it.
These FIFO related features allow optimization of CPU/UART transactions and are especially useful given the higher
baud rate capability (256 kbaud).
6.1.16.2
TXD2 Pin
The TXD2 signal is located on the GP53/TXD2(IRTX) pin. The operation of this pin following a power cycle is defined
in Section 6.2.1, "IR Transmit Pin," on page 51.
6.2
Infrared Interface
The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Two
IR implementations have been provided for the second UART in this chip (logical device 5), IrDA and Amplitude Shift
Keyed IR. The IR transmission can use the standard UART2 TXD2 and RXD2 pins. These can be selected through the
configuration registers.
IrDA 1.0 allows serial communication at baud rates up to 115.2 kbps. Each word is sent serially beginning with a zero
value start bit. A zero is signaled by sending a single IR pulse at the beginning of the serial bit time. A one is signaled
by sending no IR pulse during the bit time. Please refer to the AC timing for the parameters of these pulses and the IrDA
waveform.
The Amplitude Shift Keyed IR allows asynchronous serial communication at baud rates up to 19.2K Baud. Each word
is sent serially beginning with a zero value start bit. A zero is signaled by sending a 500KHz waveform for the duration
of the serial bit time. A one is signaled by sending no transmission during the bit time. Please refer to the AC timing for
the parameters of the ASK-IR waveform.
DS00002121B-page 50
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
If the Half Duplex option is chosen, there is a time-out when the direction of the transmission is changed. This time-out
starts at the last bit transferred during a transmission and blocks the receiver input until the timeout expires. If the trans-
mit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is transmitted.
If data is loaded into the transmit buffer while a character is being received, the transmission will not start until the time-
out expires after the last receive bit has been received. If the start bit of another character is received during this time-
out, the timer is restarted after the new character is received. The IR half duplex time-out is programmable via CRF2 in
Logical Device 5. This register allows the time-out to be programmed to any value between 0 and 10msec in 100usec
increments.
FIGURE 6-3:
BLOCK DIAGRAM OF THE IR COMPONENTS IN THE
SCH3227/SCH3226/SCH3224/SCH3222
ACE
Registers
COM
IR
Output
MUX
Host Interface
IrDA SIR
COM
ACE UART
Sharp ASK
IR Options Register,
Bit 6
6.2.1
IR TRANSMIT PIN
The following description describes the state of the GP53/TXD2(IRTX) pin following a power cycle.
GP53/TXD2(IRTX) Pin. This pin defaults to the GPIO input function on a VTR POR.
The GP53/TXD2(IRTX) pin will be tristate following a VCC POR, VTR POR, Soft Reset, or PCI Reset when it is config-
ured for the TXD2 (IRTX) function. It will remain tristate until the UART is powered. Once the UART is powered, the state
of the pin will be determined by the UART block. If VCC>2.4V and GP53 function is selected the pin will reflect the cur-
rent state of GP53.
Note:
External hardware should be implemented to protect the transceiver when the IRTX2 pin is tristated.
6.3
Interrupt Sharing
Multiple sharing options are available are for the SCH322x devices. Sharing an interrupt requires the following:
1. Configure the UART to be the generator to the desired IRQ.
2. Configure other shared UARTs to use No IRQ selected.
3. Set the desired share IRQ bit.
APPLICATION NOTE: If both UARTs are configured to use different IRQs and the share IRQ bit is set, then both
of the UART IRQs will assert when either UART generates an interrupt.
Table 6-8, summarizes the various IRQ sharing configurations. In this table, the following nomenclature is used:
• N/A - not applicable
• NS - port not shared
• S12 - uart 1 and uart 2 share an IRQ
• S34 - uart 3 and uart 4 share an IRQ
• S56 - uart 5 and uart 6 share an IRQ
• S1234 - UARTS 1,2,3,4 share the same IRQ
2016-2017 Microchip Technology Inc.
DS00002121B-page 51
SCH3227/SCH3226/SCH3224/SCH3222
• S1256 - UARTS 1,2,5,6 share the same IRQ
• S3456 - UARTS 3,4,5,6 share the same IRQ
• S123456 - all uarts share the same IRQ
TABLE 6-8:
SCH3227/SCH3226/SCH3224/SCH3222 IRQ SHARING SUMMARY
SP1 Mode
Reg
SP1 Mode
Reg
SP3 Mode
Reg
SP5 Mode
Reg
Device
(0xF0) Bit6 (0xF0) Bit7 (0xF0) Bit7 (0xF0) Bit7 SP1 SP2 SP3 SP4 SP5 SP6
All
SP12
SP34
SP56
Share Bit
Share Bit
Share Bit
Share Bit
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
0
1
1
0
0
1
1
NS
S12
NS
NS
S12
NS
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
NS
NS
NS
NS
S56
S56
NS
S56
S56
NS
S12
NS
S12
NS
SCH3224
S12
NS
S12
NS
NS
NS
S56
S56
S125 S125 N/A
6
N/A S125 S125
6
6
6
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
NS
S12
NS
S12
NS
S12
NS
NS
S12
NS
S12
NS
S12
NS
NS
NS
NS
NS
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
S34
S34
NS
S34
S34
NS
STRAPOPT=
0, SCH3227
/ SCH3226
NS
NS
S34
S34
S123 S123 S123 S123 N/A
4
4
4
4
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
NS
NS
NS
NS
NS
NS
NS
NS
S12
NS
S12
NS
NS
NS
S34
S34
NS
S34
S34
NS
NS
NS
S12
NS
S12
NS
NS
NS
S56
S56
S56
S56
NS
S56
S56
S56
S56
NS
S12
NS
S12
NS
NS
NS
S34
S34
NS
S34
S34
NS
S12
NS
S12
NS
SCH3222,
S12
NS
S12
NS
NS
NS
NS
NS
STRAPOPT=
1, SCH3227
/ SCH3226
S34
S34
NS
NS
S123 S123 S123 S123 NS
4
NS
4
4
4
1
1
0
1
0
0
1
1
NS
NS
NS
NS
S56
S56
S125 S125 NS
6
NS S125 S125
6
6
6
1
1
0
1
1
1
1
1
NS
NS S345 S345 S345 S345
6
6
6
6
S123 S123 S123 S123 S123 S123
456 456 456 456 456 456
DS00002121B-page 52
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
6.4
RS485 Auto Direction Control
The purpose of this function is to save the effort to deal with direction control in software. A direction control signal (usu-
ally nRTS) is used to tristate the transmitter when no other data is available, so that other nodes can use the shared
lines. It is preferred to have this function on all six serial ports.
This will affect the nRTS and nDTR signals for each serial port in the device. Each serial port will have the following
additional characteristics:
• An option register for the serial port in the runtime registers with following bits:
- An enable bit to turn on/off the direction control
- An enable bit to select which bit nRTS or nDTR, of the serial port is affected.
- A bit to select the polarity - high or low, that the selected signal is driven to when the output buffer of the cor-
responding serial port is empty or full.
• When automatic direction control is enabled, the device monitors the local output buffer for not empty and empty
conditions. If enabled, the direction control will force the nRTS or nDTR signal (selected via programming) to the
desired polarity under the empty or not empty condition. Table 6-9 summarizes the possible programming states.
• Automatic Direction Control of the serial ports is only valid when the FIFO is enabled.
• The multi-function GPIO pins do not automatically set the direction when selected as serial port pins.
• The high speed baud rates will only work if the MSB of the MS divisor is set.
TABLE 6-9:
NRTS/NDTR AUTOMATIC DIRECTION CONTROL OPTIONS
Local TX
Buffer State
Flow Count
EN Bit
NRTS/NDTR
SEL Bit
Polarity
SEL Bit
NRTS
NDTR
X
0
1
1
1
1
1
1
1
1
X
1
1
1
1
0
0
0
0
X
0
1
0
1
0
1
0
1
N/A
0
N/A
N/A
N/A
N/A
N/A
0
empty
empty
1
not empty
not empty
empty
1
0
N/A
N/A
N/A
N/A
empty
1
not empty
not empty
1
0
Note:
Note that N/A indicates the signal is not affected under these conditions and maintains normal operation.
A typical application using HW automatic direction control is shown in the following FIGURE 6-4: on page 54. In this
figure the nRTS signal is used to control direction.
2016-2017 Microchip Technology Inc.
DS00002121B-page 53
SCH3227/SCH3226/SCH3224/SCH3222
FIGURE 6-4:
HALF DUPLEX OPERATION WITH DIRECTION CONTROL
Client Device
Master Device
Tx data
Rx data
Receive
Transmit
Tx data
Rx data
Transmit
Receive
nRTS /
nDTR
nCTS /
nDCD
More detail on the programming of the autodirection control can be found in Section 24.0, "Runtime Register," on
page 213. SP12 is the option register for Serial Port 1 and 2. SP34 is the option register for Serial Port 3 and 4. SP5 is
the option register for Serial Port 5. SP6 is the option register for Serial Port 6.
6.5
Reduced Pin Serial Ports
The SCH322x family provides for two, 4 pin serial ports (UARTs 5 and 6), which have multiplexed control signals. For
each 4 pin port, there is a transmit, receive, input control and output control. The selection of the input and output control
is done via a bit in the SP5/6 option register. Figure 6-5 illustrates the how programming these bits selects the corre-
sponding control signals.
DS00002121B-page 54
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
FIGURE 6-5:
REDUCE PIN SERIAL PORT CONTROL SIGNAL SELECTION
External
Internal
Connections
Connections
1
0
nSCIN
nDCD
MUX
"0"
"1"
=11
1
MUX
nRI (default)
0
=10
1
0
DE
MUX
MUX
nCTS
nDSR
"0"
"0"
=01
1
0
MUX
=00
nRTS
1
SP5/6 Option Register
Bit[2:1]
nSCOUT
MUX
nDTR (default)
0
SP5/6 Option Register
Bit 0
For SP5, the port signals are nRTS5, nDTR5, nSCOUT5 and nSCIN5. The nSCOUT5 signal may be either nRTS5 or
nDTR5, selected via an SP5 option bit in a register.
The nSCIN5 signal may be either the nDSR5, nCTS5, nRI5 or nDCD5 signals, as selected via a bit in the SP5 option
register.
For SP6, the nSCOUT6 signal may be either nRTS6 or nDTR6, selected via SP6 option bit. The nSCIN6 signal may be
either the nDSR6, nCTS6, nRI6 or nDCD6 signals, as selected via a bit in theSP6 option register. The programming for
the SP5 and SP6 Option register is given in Section 24.0, "Runtime Register," on page 213.
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7.0
PARALLEL PORT
The SCH322x incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional
parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes.
Refer to the Configuration Registers for information on disabling, power- down, changing the base address of the par-
allel port, and selecting the mode of operation.
The parallel port also incorporates Microchip’s ChiProtect circuitry, which prevents possible damage to the parallel port
due to printer power-up.
The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their associated reg-
isters and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP
mode. The address map of the Parallel Port is shown below:
DATA PORT
BASE ADDRESS + 00H
BASE ADDRESS + 01H
BASE ADDRESS + 02H
BASE ADDRESS + 03H
BASE ADDRESS + 04H
BASE ADDRESS + 05H
BASE ADDRESS + 06H
BASE ADDRESS + 07H
STATUS PORT
CONTROL PORT
EPP ADDR PORT
EPP DATA PORT 0
EPP DATA PORT 1
EPP DATA PORT 2
EPP DATA PORT 3
The bit map of these registers is:
D0
D1
D2
PD2
D3
PD3
D4
PD4
D5
PD5
D6
PD6
D7
PD7
Note
DATA PORT PD0
PD1
0
1
1
STATUS
PORT
TMOUT
0
nERR
SLC
PD3
PD3
PD3
PD3
PD3
SLCT
IRQE
PD4
PD4
PD4
PD4
PD4
PE
nACK
nBUSY
CONTROL
PORT
STROBE AUTOFD
nINIT
PD2
PD2
PD2
PD2
PD2
PCD
PD5
PD5
PD5
PD5
PD5
0
0
1
2
2
2
2
2
EPP ADDR
PORT
PD0
PD0
PD0
PD0
PD0
PD1
PD1
PD1
PD1
PD1
PD6
PD6
PD6
PD6
PD6
PD7
PD7
PD7
PD7
PD7
EPP DATA
PORT 0
EPP DATA
PORT 1
EPP DATA
PORT 2
EPP DATA
PORT 3
Note 1: These registers are available in all modes.
2: These registers are only available in EPP mode.
TABLE 7-1:
PARALLEL PORT CONNECTOR
Pin Number Standard
Host Connector
EPP
ECP
1
83
nSTROBE
PD<0:7>
nACK
nWrite
nStrobe
2-9
10
11
12
68-75
80
PData<0:7>
Intr
PData<0:7>
nAck
79
BUSY
nWait
Busy, PeriphAck(3)
78
PE
(User Defined)
PError,
nAckReverse (3)
13
14
77
82
SLCT
nALF
(User Defined)
nDatastb
Select
nAutoFd,
HostAck(3)
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TABLE 7-1:
Host Connector
15
PARALLEL PORT CONNECTOR (CONTINUED)
Pin Number
Standard
nERROR
EPP
ECP
81
66
67
(User Defined)
nFault (1)
nPeriphRequest (3)
16
nINIT
nRESET
nInit(1)
nReverseRqst(3)
17
nSLCTIN
nAddrstrb
nSelectIn(1,3)
(1) = Compatible Mode
(3) = High Speed Mode
Note:
For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This document
is available from Microsoft.
7.1
IBM XT/AT Compatible, Bi-Directional and EPP Modes
7.1.1
DATA PORT
ADDRESS OFFSET = 00H
The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at initialization by
RESET. During a WRITE operation, the Data Register latches the contents of the internal data bus. The contents of this
register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP mode, PD0
- PD7 ports are buffered (not latched) and output to the host CPU.
7.1.2
STATUS PORT
ADDRESS OFFSET = 01H
The Status Port is located at an offset of ‘01H’ from the base address. The contents of this register are latched for the
duration of a read cycle. The bits of the Status Port are defined as follows:
Bit 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic O means
that no time out error has occurred; a logic 1 means that a time out error has been detected. This bit is cleared by a
RESET. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device 3 Configuration
Registers) is ‘0’, writing a one to this bit clears the TMOUT status bit. Writing a zero to this bit has no effect. If the TIM-
EOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device 3 Configuration Registers) is ‘1’,
the TMOUT bit is cleared on the trailing edge of a read of the EPP Status Register.
Bits 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are a low level.
Bit 3 nERR – nERROR
The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0 means an error has
been detected; a logic 1 means no error has been detected.
Bit 4 SLT - Printer Selected Status
The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is on
line; a logic 0 means it is not selected.
Bit 5 PE - Paper End
The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end; a
logic 0 indicates the presence of paper.
Bit 6 nACK - Acknowledge
The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means that the printer
has received a character and can now accept another. A logic 1 means that it is still processing the last character or has
not received the data.
Bit 7 nBUSY - nBUSY
The complement of the level on the BUSY input is read by the CPU as bit 7 of the Printer Status Register. A logic 0 in
this bit means that the printer is busy and cannot accept a new character. A logic 1 means that it is ready to accept the
next character.
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7.1.3
CONTROL PORT
ADDRESS OFFSET = 02H
The Control Port is located at an offset of ‘02H’ from the base address. The Control Register is initialized by the RESET
input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.
Bit 0 STROBE - Strobe
This bit is inverted and output onto the nSTROBE output.
Bit 1 AUTOFD - Autofeed
This bit is inverted and output onto the nAutoFd output. A logic 1 causes the printer to generate a line feed after each
line is printed. A logic 0 means no autofeed.
Bit 2 nINIT - Initiate Output
This bit is output onto the nINIT output without inversion.
Bit 3 SLCTIN - Printer Select Input
This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the
printer is not selected.
Bit 4 IRQE - Interrupt Request Enable
The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port
to the CPU. An interrupt request is generated on the IRQ port by a positive going nACK input. When the IRQE bit is
programmed low the IRQ is disabled.
Bit 5 PCD - PARALLEL CONTROL DIRECTION
Parallel Control Direction is not valid in printer mode. In printer mode, the direction is always out regardless of the state
of this bit. In bi-directional, EPP or ECP mode, a logic 0 means that the printer port is in output mode (write); a logic 1
means that the printer port is in input mode (read).
Bits 6 and 7 during a read are a low level, and cannot be written.
7.1.4
EPP ADDRESS PORT
ADDRESS OFFSET = 03H
The EPP Address Port is located at an offset of ‘03H’ from the base address. The address register is cleared at initial-
ization by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non inverting)
and output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP ADDRESS WRITE cycle to be performed,
during which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are
read. An LPC I/O read cycle causes an EPP ADDRESS READ cycle to be performed and the data output to the host
CPU, the deassertion of ADDRSTB latches the PData for the duration of the read cycle. This register is only available
in EPP mode.
7.1.5
EPP DATA PORT 0
ADDRESS OFFSET = 04H
The EPP Data Port 0 is located at an offset of ‘04H’ from the base address. The data register is cleared at initialization
by RESET. During a WRITE operation, the contents of the internal data bus DB0-DB7 are buffered (non inverting) and
output onto the PD0 - PD7 ports. An LPC I/O write cycle causes an EPP DATA WRITE cycle to be performed, during
which the data is latched for the duration of the EPP write cycle. During a READ operation, PD0 - PD7 ports are read.
An LPC I/O read cycle causes an EPP READ cycle to be performed and the data output to the host CPU, the deassertion
of DATASTB latches the PData for the duration of the read cycle. This register is only available in EPP mode.
7.1.6
EPP DATA PORT 1
ADDRESS OFFSET = 05H
The EPP Data Port 1 is located at an offset of ‘05H’ from the base address. Refer to EPP DATA PORT 0 for a description
of operation. This register is only available in EPP mode.
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7.1.7
EPP DATA PORT 2
ADDRESS OFFSET = 06H
The EPP Data Port 2 is located at an offset of ‘06H’ from the base address. Refer to EPP DATA PORT 0 for a description
of operation. This register is only available in EPP mode.
7.1.8
EPP DATA PORT 3
ADDRESS OFFSET = 07H
The EPP Data Port 3 is located at an offset of ‘07H’ from the base address. Refer to EPP DATA PORT 0 for a description
of operation. This register is only available in EPP mode.
7.1.9
EPP 1.9 OPERATION
When the EPP mode is selected in the configuration register, the standard and bi-directional modes are also available.
If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional mode,
and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled by PCD
of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to
prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to nWAIT
being deasserted (after command). If a time-out occurs, the current EPP cycle is aborted and the time-out condition is
indicated in Status bit 0.
During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always be in a write
mode and the nWRITE signal to always be asserted.
7.1.10
SOFTWARE CONSTRAINTS
Before an EPP cycle is executed, the software must ensure that the control register bit PCD is a logic “0” (i.e., a 04H or
05H should be written to the Control port). If the user leaves PCD as a logic “1”, and attempts to perform an EPP write,
the chip is unable to perform the write (because PCD is a logic “1”) and will appear to perform an EPP read on the par-
allel bus, no error is indicated.
7.1.11
EPP 1.9 WRITE
The timing for a write operation (address or data) is shown in timing diagram EPP Write Data or Address cycle. The chip
inserts wait states into the LPC I/O write cycle until it has been determined that the write cycle can complete. The write
cycle can complete under the following circumstances:
• If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then the write can
complete when nWAIT goes inactive high.
• If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the
state of nDATASTB, nWRITE or nADDRSTB. The write can complete once nWAIT is determined inactive.
Write Sequence of operation
1. The host initiates an I/O write cycle to the selected EPP register.
2. If WAIT is not asserted, the chip must wait until WAIT is asserted.
3. The chip places address or data on PData bus, clears PDIR, and asserts nWRITE.
4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE
signal is valid.
5. Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin
the termination phase of the cycle.
6.
a) The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. If it has
not already done so, the peripheral should latch the information byte now.
b) The chip latches the data from the internal data bus for the PData bus and drives the sync that indicates that
no more wait states are required followed by the TAR to complete the write cycle.
7. Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and
acknowledging the termination of the cycle.
8. Chip may modify nWRITE and nPDATA in preparation for the next cycle.
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7.1.12
EPP 1.9 READ
The timing for a read operation (data) is shown in timing diagram EPP Read Data cycle. The chip inserts wait states into
the LPC I/O read cycle until it has been determined that the read cycle can complete. The read cycle can complete under
the following circumstances:
• If the EPP bus is not ready (nWAIT is active low) when nDATASTB goes active then the read can complete when
nWAIT goes inactive high.
• If the EPP bus is ready (nWAIT is inactive high) then the chip must wait for it to go active low before changing the
state of nWRITE or before nDATASTB goes active. The read can complete once nWAIT is determined inactive.
Read Sequence of Operation
1. The host initiates an I/O read cycle to the selected EPP register.
2. If WAIT is not asserted, the chip must wait until WAIT is asserted.
3. The chip tri-states the PData bus and deasserts nWRITE.
4. Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE
signal is valid.
5. Peripheral drives PData bus valid.
6. Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the
cycle.
7.
a) The chip latches the data from the PData bus for the internal data bus and deasserts nDATASTB or nAD-
DRSTRB. This marks the beginning of the termination phase.
b) The chip drives the sync that indicates that no more wait states are required and drives valid data onto the
LAD[3:0] signals, followed by the TAR to complete the read cycle.
8. Peripheral tri-states the PData bus and asserts nWAIT, indicating to the host that the PData bus is tri-stated.
9. Chip may modify nWRITE, PDIR and nPDATA in preparation for the next cycle.
7.1.13
EPP 1.7 OPERATION
When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes are also avail-
able. If no EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the standard or bi-directional
mode, and all output signals (STROBE, AUTOFD, INIT) are as set by the SPP Control Port and direction is controlled
by PCD of the Control port.
In EPP mode, the system timing is closely coupled to the EPP timing. For this reason, a watchdog timer is required to
prevent system lockup. The timer indicates if more than 10usec have elapsed from the start of the EPP cycle to the end
of the cycle. If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0.
7.1.14
SOFTWARE CONSTRAINTS
Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero.
Also, bit D5 (PCD) is a logic “0” for an EPP write or a logic “1” for and EPP read.
7.1.15
EPP 1.7 WRITE
The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. The
chip inserts wait states into the I/O write cycle when nWAIT is active low during the EPP cycle. This can be used to
extend the cycle time. The write cycle can complete when nWAIT is inactive high.
Write Sequence of Operation
• The host sets PDIR bit in the control register to a logic “0”. This asserts nWRITE.
• The host initiates an I/O write cycle to the selected EPP register.
• The chip places address or data on PData bus.
• Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE
signal is valid.
• If nWAIT is asserted, the chip inserts wait states into I/O write cycle until the peripheral deasserts nWAIT or a time-
out occurs.
• The chip drives the final sync, deasserts nDATASTB or nADDRSTRB and latches the data from the internal data
bus for the PData bus.
• Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
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7.1.16
EPP 1.7 READ
The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. The chip inserts wait states
into the I/O read cycle when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The
read cycle can complete when nWAIT is inactive high.
Read Sequence of Operation
• The host sets PDIR bit in the control register to a logic “1”. This deasserts nWRITE and tri-states the PData bus.
• The host initiates an I/O read cycle to the selected EPP register.
• Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the nWRITE sig-
nal is valid.
• If nWAIT is asserted, the chip inserts wait states into the I/O read cycle until the peripheral deasserts nWAIT or a
time-out occurs.
• The Peripheral drives PData bus valid.
• The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of
the cycle.
• The chip drives the final sync and deasserts nDATASTB or nADDRSTRB.
• Peripheral tri-states the PData bus.
• Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
TABLE 7-2:
EPP Signal
EPP PIN DESCRIPTIONS
EPP Name Type
nWrite
EPP Description
nWRITE
PD<0:7>
INTR
O
This signal is active low. It denotes a write operation.
Bi-directional EPP byte wide address and data bus.
Address/Data
Interrupt
I/O
I
This signal is active high and positive edge triggered. (Pass through
with no inversion, Same as SPP).
nWAIT
nWait
I
This signal is active low. It is driven inactive as a positive
acknowledgement from the device that the transfer of data is
completed. It is driven active as an indication that the device is ready
for the next transfer.
nDATASTB
nRESET
nData Strobe
nReset
O
O
O
This signal is active low. It is used to denote data read or write
operation.
This signal is active low. When driven active, the EPP device is reset
to its initial operational mode.
nADDRSTB
Address Strobe
Paper End
This signal is active low. It is used to denote address read or write
operation.
PE
I
I
Same as SPP mode.
Same as SPP mode.
SLCT
Printer Selected
Status
nERR
Error
I
Same as SPP mode.
Note 1: SPP and EPP can use 1 common register.
2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct
EPP read cycles, PCD is required to be a low.
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7.2
Extended Capabilities Parallel Port
ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater
detail in the remainder of this section.
High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer Optional
single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost peripherals Maintains link
and data layer separation Permits the use of active output drivers permits the use of adaptive signal timing Peer-to-peer
capability.
7.2.1
VOCABULARY
The following terms are used in this document:
assert:
forward:
reverse:
Pword:
1
When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state.
Host to Peripheral communication.
Peripheral to Host communication
A port word; equal in size to the width of the LPC interface. For this implementation, PWord is always 8 bits.
A high level.
A low level.
0
These terms may be considered synonymous:
PeriphClk, nAck
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
nReverseRequest, nInit
nAckReverse, PError
Xflag, Select
ECPMode, nSelectln
HostClk, nStrobe
Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14,
1993. This document is available from Microsoft.
The bit map of the Extended Parallel Port registers is:
D7
D6
D5
D4
D3
D2
D1
D0
Note
data
ecpAFifo
dsr
PD7
Addr/RLE
nBusy
0
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Address or RLE field
Select nFault
ackIntEn SelectIn
2
1
1
2
2
2
nAck
0
PError
0
0
0
dcr
Direction
nInit
autofd
strobe
cFifo
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
0
0
0
1
0
0
0
0
compress intrValue
MODE
Parallel Port IRQ
Parallel Port DMA
full empty
nErrIntrEn dmaEn serviceI
ntr
Note 1: These registers are available in all modes.
2: All FIFOs use one common 16 byte FIFO.
3: The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the Configuration Reg-
isters.
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7.2.2
ECP IMPLEMENTATION STANDARD
This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC devices supporting
ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a descrip-
tion of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard,
Rev. 1.14, July 14, 1993. This document is available from Microsoft.
Description
The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT port
if ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It does not
do any “protocol” negotiation, rather it provides an automatic high burst-bandwidth channel that supports DMA for ECP
in both the forward and reverse directions.
Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum band-
width requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the standard
parallel port to improve compatibility mode transfer speed.
The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is accomplished
by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated.
Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. Hardware
support for compression is optional.
TABLE 7-3:
Name
ECP PIN DESCRIPTIONS
Type
Description
nStrobe
O
During write operations nStrobe registers data or address into the slave on the
asserting edge (handshakes with Busy).
PData 7:0
nAck
I/O
I
Contains address or data or RLE data.
Indicates valid data driven by the peripheral when asserted. This signal
handshakes with nAutoFd in reverse.
PeriphAck (Busy)
I
This signal deasserts to indicate that the peripheral can accept data. This signal
handshakes with nStrobe in the forward direction. In the reverse direction this
signal indicates whether the data lines contain ECP command information or
data. The peripheral uses this signal to automatic direction control in the forward
direction. It is an “interlocked” handshake with nStrobe. PeriphAck also provides
command information in the reverse direction.
PError
(nAckReverse)
I
Used to acknowledge a change in the direction the transfer (asserted =
forward). The peripheral drives this signal low to acknowledge
nReverseRequest. It is an “interlocked” handshake with nReverseRequest. The
host relies upon nAckReverse to determine when it is permitted to drive the data
bus.
Select
I
Indicates printer on line.
nAutoFd
(HostAck)
O
Requests a byte of data from the peripheral when asserted, handshaking with
nAck in the reverse direction. In the forward direction this signal indicates
whether the data lines contain ECP address or data. The host drives this signal
to automatic direction control in the reverse direction. It is an “interlocked”
handshake with nAck. HostAck also provides command information in the
forward phase.
nFault
(nPeriphRequest)
I
Generates an error interrupt when asserted. This signal provides a mechanism
for peer-to-peer communication. This signal is valid only in the forward direction.
During ECP Mode the peripheral is permitted (but not required) to drive this pin
low to request a reverse transfer. The request is merely a “hint” to the host; the
host has ultimate control over the transfer direction. This signal would be
typically used to generate an interrupt to the host CPU.
nInit
O
O
Sets the transfer direction (asserted = reverse, deasserted = forward). This pin
is driven low to place the channel in the reverse direction. The peripheral is only
allowed to drive the bi-directional data bus while in ECP Mode and HostAck is
low and nSelectIn is high.
nSelectIn
Always deasserted in ECP mode.
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7.2.3
REGISTER DEFINITIONS
The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported.
The additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict with standard
ISA devices. The port is equivalent to a generic parallel port interface and may be operated in that mode. The port reg-
isters vary depending on the mode field in the ecr. Table 7-4 lists these dependencies. Operation of the devices in
modes other that those specified is undefined.
TABLE 7-4:
Name
ECP REGISTER DEFINITIONS
Address (See Notes)
ECP Modes
Function
Data Register
data
+000h R/W
+000h R/W
+001h R/W
+002h R/W
+400h R/W
+400h R/W
+400h R/W
+400h R
000-001
011
All
ecpAFifo
dsr
ECP FIFO (Address)
Status Register
dcr
All
Control Register
cFifo
ecpDFifo
tFifo
010
011
110
111
111
All
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
cnfgA
cnfgB
ecr
Configuration Register A
Configuration Register B
Extended Control Register
+401h R/W
+402h R/W
Note 1: These addresses are added to the parallel port base address as selected by configuration register or jump-
ers.
2: All addresses are qualified with AEN. Refer to the AEN pin definition.
TABLE 7-5:
Mode
MODE DESCRIPTIONS
Description
000
001
010
011
100
101
110
111
SPP mode
PS/2 Parallel Port mode
Parallel Port Data FIFO mode
ECP Parallel Port mode
EPP mode (If this option is enabled in the configuration registers)
Reserved
Test mode
Configuration mode
*Refer to ECR Register Description
7.2.4
DATA AND ECPAFIFO PORT
ADDRESS OFFSET = 00H
Modes 000 and 001 (Data Port)
The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at initialization by
RESET. During a WRITE operation, the Data Register latches the contents of the data bus. The contents of this register
are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation, PD0 - PD7 ports are read
and output to the host CPU.
Mode 011 (ECP FIFO - Address/RLE)
A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP
port transmits this byte to the peripheral automatically. The operation of this register is only defined for the forward direc-
tion (direction is 0).
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7.2.5
DEVICE STATUS REGISTER (DSR)
ADDRESS OFFSET = 01H
The Status Port is located at an offset of ‘01H’ from the base address. Bits0 - 2 are not implemented as register bits,
during a read of the Printer Status Register these bits are a low level. The bits of the Status Port are defined as follows:
Bit 3 nFault
The level on the nFault input is read by the CPU as bit 3 of the Device Status Register.
Bit 4 Select
The level on the Select input is read by the CPU as bit 4 of the Device Status Register.
Bit 5 PError
The level on the PError input is read by the CPU as bit 5 of the Device Status Register. Printer Status Register.
Bit 6 nAck
The level on the nAck input is read by the CPU as bit 6 of the Device Status Register.
Bit 7 nBusy
The complement of the level on the BUSY input is read by the CPU as bit 7 of the Device Status Register.
7.2.6
DEVICE CONTROL REGISTER (DCR)
ADDRESS OFFSET = 02H
The Control Register is located at an offset of ‘02H’ from the base address. The Control Register is initialized to zero by
the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.
Bit 0 STROBE - STROBE
This bit is inverted and output onto the nSTROBE output.
Bit 1 AUTOFD - AUTOFEED
This bit is inverted and output onto the nAutoFd output. A logic 1 causes the printer to generate a line feed after each
line is printed. A logic 0 means no autofeed.
Bit 2 nINIT - INITIATE OUTPUT
This bit is output onto the nINIT output without inversion.
Bit 3 SELECTIN
This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the
printer is not selected.
Bit 4 ackIntEn - INTERRUPT REQUEST ENABLE
The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port
to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt under Operation,
Interrupts.
Bit 5 DIRECTION
If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all
other modes, Direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that
the printer port is in input mode (read).
Bits 6 and 7 during a read are a low level, and cannot be written.
cFifo (Parallel Port Data FIFO)
ADDRESS OFFSET = 400h
Mode = 010
Bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using
the standard parallel port protocol. Transfers to the FIFO are byte aligned. This mode is only defined for the forward
direction.
ecpDFifo (ECP Data FIFO)
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ADDRESS OFFSET = 400H
Mode = 011
Bytes written or DMAed from the system to this FIFO, when the direction bit is 0, are transmitted by a hardware hand-
shake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned.
Data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO when the direc-
tion bit is 1. Reads or DMAs from the FIFO will return bytes of ECP data to the system.
tFifo (Test FIFO Mode)
ADDRESS OFFSET = 400H
Mode = 110
Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not
be transmitted to the to the parallel port lines using a hardware protocol handshake. However, data in the tFIFO may be
displayed on the parallel port data lines.
The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data to a full tFIFO, the new data is
not accepted into the tFIFO. If an attempt is made to read data from an empty tFIFO, the last data byte is re-read again.
The full and empty bits must always keep track of the correct FIFO state. The tFIFO will transfer data at the maximum
ISA rate so that software may generate performance metrics.
The FIFO size and interrupt threshold can be determined by writing bytes to the FIFO and checking the full and servi-
ceIntr bits.
The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and emptying it a
byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been
reached.
The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time
until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached.
Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h,
22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as was written.
cnfgA (Configuration Register A)
ADDRESS OFFSET = 400H
Mode = 111
This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit imple-
mentation. (PWord = 1 byte)
cnfgB (Configuration Register B)
ADDRESS OFFSET = 401H
Mode = 111
Bit 7 compress
This bit is read only. During a read it is a low level. This means that this chip does not support hardware RLE compres-
sion. It does support hardware de-compression.
Bit 6 intrValue
Returns the value of the interrupt to determine possible conflicts.
Bit [5:3] Parallel Port IRQ (read-only)
to Table 7-7 on page 68.
Bits [2:0] Parallel Port DMA (read-only)
to Table 7-8 on page 68.
ecr (Extended Control Register)
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ADDRESS OFFSET = 402H
Mode = all
This register controls the extended ECP parallel port functions.
Bits 7,6,5
These bits are Read/Write and select the Mode.
Bit 4 nErrIntrEn
Read/Write (Valid only in ECP Mode)
1:
0:
Disables the interrupt generated on the asserting edge of nFault.
Enables an interrupt pulse on the high to low edge of nFault. Note that an interrupt will be generated if nFault is
asserted (interrupting) and this bit is written from a 1 to a 0. This prevents interrupts from being lost in the time
between the read of the ecr and the write of the ecr.
Bit 3 dmaEn
Read/Write
1:
0:
Enables DMA (DMA starts when serviceIntr is 0).
Disables DMA unconditionally.
Bit 2 serviceIntr
Read/Write
1:
0:
Disables DMA and all of the service interrupts.
Enables one of the following 3 cases of interrupts. Once one of the 3 service interrupts has occurred serviceIntr
bit shall be set to a 1 by hardware. It must be reset to 0 to re-enable the interrupts. Writing this bit to a 1 will not
cause an interrupt.
case dmaEn=1:
During DMA (this bit is set to a 1 when terminal count is reached).
case dmaEn=0 direction=0:
This bit shall be set to 1 whenever there are writeIntrThreshold or more bytes free in the FIFO.
case dmaEn=0 direction=1:
This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read from the FIFO.
Bit 1 full
Read only
1:
0:
The FIFO cannot accept another byte or the FIFO is completely full.
The FIFO has at least 1 free byte.
Bit 0 empty
Read only
1:
0:
The FIFO is completely empty.
The FIFO contains at least 1 byte of data.
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TABLE 7-6:
R/W
EXTENDED CONTROL REGISTER (A)
Mode
000:
001:
010:
011:
Standard Parallel Port Mode. In this mode the FIFO is reset and common drain drivers are used on the
control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output
drivers in this mode.
PS/2 Parallel Port Mode. Same as above except that direction may be used to tri-state the data lines and
reading the data register returns the value on the data lines and not the value in the data register. All
drivers have active pull-ups (push-pull).
Parallel Port FIFO Mode. This is the same as 000 except that bytes are written or DMAed to the FIFO.
FIFO data is automatically transmitted using the standard parallel port protocol. Note that this mode is
only useful when direction is 0. All drivers have active pull-ups (push-pull).
ECP Parallel Port Mode. In the forward direction (direction is 0) bytes placed into the ecpDFifo and bytes
written to the ecpAFifo are placed in a single FIFO and transmitted automatically to the peripheral using
ECP Protocol. In the reverse direction (direction is 1) bytes are moved from the ECP parallel port and
packed into bytes in the ecpDFifo. All drivers have active pull-ups (push-pull).
100:
Selects EPP Mode: In this mode, EPP is selected if the EPP supported option is selected in configuration
register L3-CRF0. All drivers have active pull-ups (push-pull).
101:
110:
Reserved
Test Mode. In this mode the FIFO may be written and read, but the data will not be transmitted on the
parallel port. All drivers have active pull-ups (push-pull).
111:
Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All
drivers have active pull-ups (push-pull).
TABLE 7-7:
EXTENDED CONTROL REGISTER (B)
IRQ Selected
Config REG B
Bits 5:3
15
110
101
100
011
010
001
111
000
14
11
10
9
7
5
All others
TABLE 7-8:
EXTENDED CONTROL REGISTER (C)
IRQ Selected
Config REG B
Bits 5:3
3
011
010
001
000
2
1
All others
7.2.7
OPERATION
Mode Switching/Software Control
Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control
(mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the
ECP port only in the data transfer phase (modes 011 or 010).
Setting the mode to 011 or 010 will cause the hardware to initiate data transfer.
If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be
switched into mode 000 or 001. The direction can only be changed in mode 001.
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Once in an extended forward mode the software should wait for the FIFO to be empty before switching back to mode
000 or 001. In this case all control signals will be deasserted before the mode switch. In an ecp reverse mode the soft-
ware waits for all the data to be read from the FIFO before changing back to mode 000 or 001. Since the automatic
hardware ecp reverse handshake only cares about the state of the FIFO it may have acquired extra data which will be
discarded. It may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. In this case the
port will deassert nAutoFd independent of the state of the transfer. The design shall not cause glitches on the handshake
signals if the software meets the constraints above.
7.2.8
ECP OPERATION
Prior to ECP operation the Host must negotiate on the parallel port to determine if the peripheral supports the ECP pro-
tocol. This is a somewhat complex negotiation carried out under program control in mode 000.
After negotiation, it is necessary to initialize some of the port bits. The following are required:
Set Direction = 0, enabling the drivers.
Set strobe = 0, causing the nStrobe signal to default to the deasserted state.
Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state.
Set mode = 011 (ECP Mode)
ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo respectively.
Note that all FIFO data transfers are byte wide and byte aligned. Address/RLE transfers are byte-wide and only allowed
in the forward direction.
The host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting
direction to 1 or 0, then setting mode = 011. When direction is 1 the hardware shall handshake for each ECP read data
byte and attempt to fill the FIFO. Bytes may then be read from the ecpDFifo as long as it is not empty.
ECP transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode
= 001, or 000.
7.2.9
TERMINATION FROM ECP MODE
Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate
from ECP Mode only in specific well-defined states. The termination can only be executed while the bus is in the forward
direction. To terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction.
7.2.10
COMMAND/DATA
ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The fea-
tures are implemented by allowing the transfer of normal 8 bit data or 8 bit commands.
When in the forward direction, normal data is transferred when HostAck is high and an 8 bit command is transferred
when HostAck is low.
The most significant bit of the command indicates whether it is a run-length count (for compression) or a channel
address.
When in the reverse direction, normal data is transferred when PeriphAck is high and an 8 bit command is transferred
when PeriphAck is low. The most significant bit of the command is always zero. Reverse channel addresses are seldom
used and may not be supported in hardware.
TABLE 7-9:
CHANNEL/DATA COMMANDS SUPPORTED IN ECP MODE
Forward Channel Commands (HostAck Low)
Reverse Channel Commands (PeripAck Low)
D7
D[6:0]
0
1
Run-Length Count (0-127) (mode 0011 0X00 only)
Channel Address (0-127)
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7.2.11
DATA COMPRESSION
The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a
peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP
mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo.
Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times
the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte the spec-
ified number of times. When a run-length count is received from a peripheral, the subsequent data byte is replicated the
specified number of times. A run-length count of zero specifies that only one byte of data is represented by the next data
byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. To prevent data
expansion, however, run-length counts of zero should be avoided.
7.2.12
PIN DEFINITION
The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-drain in mode 000 and are push-pull in all other modes.
7.2.13
LPC CONNECTIONS
The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on an I/O address
basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on a byte boundary. (The PWord
value can be obtained by reading Configuration Register A, cnfgA, described in the next section). Single byte wide trans-
fers are always possible with standard or PS/2 mode using program control of the control signals.
7.2.14
INTERRUPTS
The interrupts are enabled by serviceIntr in the ecr register.
serviceIntr = 1 Disables the DMA and all of the service interrupts.
serviceIntr = 0 Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupts gener-
ated immediately when this bit is changed from a 1 to a 0. This can occur during Programmed I/O if the
number of bytes removed or added from/to the FIFO does not cross the threshold.
An interrupt is generated when:
1. For DMA transfers: When serviceIntr is 0, dmaEn is 1 and the DMA TC cycle is received.
2. For Programmed I/O:
a) When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free bytes in the
FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are writeIntrThreshold
or more free bytes in the FIFO.
b) When serviceIntr is 0, dmaEn is 0, direction is 1 and there are readIntrThreshold or more bytes in the FIFO.
Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are readIntrThreshold or
more bytes in the FIFO.
3. When nErrIntrEn is 0 and nFault transitions from high to low or when nErrIntrEn is set from 1 to 0 and nFault is
asserted.
4. When ackIntEn is 1 and the nAck signal transitions from a low to a high.
7.2.15
FIFO OPERATION
The FIFO threshold is set in the chip configuration registers. All data transfers to or from the parallel port can proceed
in DMA or Programmed I/O (non-DMA) mode as indicated by the selected mode. The FIFO is used by selecting the
Parallel Port FIFO mode or ECP Parallel Port Mode. (FIFO test mode will be addressed separately.) After a reset, the
FIFO is disabled. Each data byte is transferred by a Programmed I/O cycle or DMA cycle depending on the selection of
DMA or Programmed I/O mode.
The following paragraphs detail the operation of the FIFO automatic direction control. In these descriptions, <threshold>
ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of
the request for both read and write cases. The host must be very responsive to the service request. This is the desired
case for use with a “fast” system. A high value of threshold (i.e. 12) is used with a “sluggish” system by affording a long
latency period after a service request, but results in more frequent service requests.
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7.2.16
DMA TRANSFERS
DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To use
the DMA transfers, the host first sets up the direction and state as in the programmed I/O case. Then it programs the
DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to 1 and serviceIntr to 0.
The ECP requests DMA transfers from the host by encoding the LDRQ# pin. The DMA will empty or fill the FIFO using
the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated
and serviceIntr is asserted, disabling DMA. In order to prevent possible blocking of refresh requests a DMA cycle shall
not be requested for more than 32 DMA cycles in a row. The FIFO is enabled directly by the host initiating a DMA cycle
for the requested channel, and addresses need not be valid. An interrupt is generated when a TC cycle is received.
(Note: The only way to properly terminate DMA transfers is with a TC cycle.)
DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to
1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. Restarting the DMA is accomplished
by enabling DMA in the host, setting dmaEn to 1, followed by setting serviceIntr to 0.
7.2.17
DMA MODE - TRANSFERS FROM THE FIFO TO THE HOST
Note:
In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even
if the chip continues to request more data from the peripheral.
The ECP requests a DMA cycle whenever there is data in the FIFO. The DMA controller must respond to the request
by reading data from the FIFO. The ECP stops requesting DMA cycles when the FIFO becomes empty or when a TC
cycle is received, indicating that no more data is required. If the ECP stops requesting DMA cycles due to the FIFO
going empty, then a DMA cycle is requested again as soon as there is one byte in the FIFO. If the ECP stops requesting
DMA cycles due to the TC cycle, then a DMA cycle is requested again when there is one byte in the FIFO, and servi-
ceIntr has been re-enabled.
7.2.18
PROGRAMMED I/O MODE OR NON-DMA MODE
The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software can determine
the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test Mode.
Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or
to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the direction and state, sets dmaEn
to 0 and serviceIntr to 0.
The ECP requests programmed I/O transfers from the host by activating the interrupt. The programmed I/O will empty
or fill the FIFO using the appropriate direction and mode.
Note:
A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same.
PROGRAMMED I/O - TRANSFERS FROM THE FIFO TO THE HOST
7.2.19
In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO.
If at this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes may be
read from the FIFO in a single burst.
readIntrThreshold =(16-<threshold>) data bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16-
<threshold>). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the FIFO). The host must
respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of
the FIFO. If at this time the FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of (16-
<threshold>) bytes may be read from the FIFO in a single burst.
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7.2.20
PROGRAMMED I/O - TRANSFERS FROM THE HOST TO THE FIFO
In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free in
the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty bit needs to be re-read.
Otherwise it may be filled with writeIntrThreshold bytes.
writeIntrThreshold
=
(16-<threshold>) free bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to <threshold>.
(If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the FIFO.) The host must
respond to the request by writing data to the FIFO. If at this time the FIFO is empty, it can be completely filled in a single
burst, otherwise a minimum of (16-<threshold>) bytes may be written to the FIFO in a single burst. This process is
repeated until the last byte is transferred into the FIFO.
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8.0
POWER MANAGEMENT
Power management capabilities are provided for the following logical devices: UART 1, UART 2 and the parallel port.
Note:
Each Logical Device may be place in powerdown mode by clearing the associated activate bit located at
CR30 or by clearing the associated power bit located in the Power Control register at CR22.
UART Power Management
Direct power management is controlled by CR22. Refer to CR22 for more information.
Parallel Port
Direct power management is controlled by CR22. Refer to CR22 for more information.
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9.0
SERIAL IRQ
The SCH3227/SCH3226/SCH3224/SCH3222 supports the serial interrupt to transmit interrupt information to the host
system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0.
9.1
Timing Diagrams For SER_IRQ Cycle
a) Start Frame timing with source sampled a low pulse on IRQ1
START FRAME
IRQ0 FRAME IRQ1 FRAME IRQ2 FRAME
SL
or
H
R
T
S
R
T
S
R
T
S
R
T
H
PCI_CLK
1
START
SER_IRQ
Drive Source
IRQ1
Host Controller
None
IRQ1
None
Note 1: H=Host Control; R=Recovery; T=Turn-Around; SL=Slave Control; S=Sample
2: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge hierarchy
in a synchronous bridge design.
b) Stop Frame Timing with Host using 17 SER_IRQ sampling period
IRQ14
FRAME
IRQ15
FRAME
IOCHCK#
FRAME
STOP FRAME
NEXT CYCLE
I 2
S
R
T
S
R
T
S
R
T
H
R
T
PCI_CLK
SER_IRQ
1
3
STOP
START
None
IRQ15
None
Host Controller
Driver
Note 1: H=Host Control; R=Recovery; T=Turn-Around; S=Sample; I=Idle
2: The next SER_IRQ cycle’s Start Frame pulse may or may not start immediately after the turn-around clock
of the Stop Frame.
3: There may be none, one or more Idle states during the Stop Frame.
4: Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode.
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9.2
SER_IRQ Cycle Control
There are two modes of operation for the SER_IRQ Start Frame
1. Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock, while the
SER_IRQ is Idle. After driving low for one clock the SER_IRQ must immediately be tri-stated without at any time
driving high. A Start Frame may not be initiated while the SER_IRQ is Active. The SER_IRQ is Idle between Stop
and Start Frames. The SER_IRQ is Active between Start and Stop Frames. This mode of operation allows the
SER_IRQ to be Idle when there are no IRQ/Data transitions which should be most of the time.
Once a Start Frame has been initiated the Host Controller will take over driving the SER_IRQ low in the next clock and
will continue driving the SER_IRQ low for a programmable period of three to seven clocks. This makes a total low pulse
width of four to eight clocks. Finally, the Host Controller will drive the SER_IRQ back high for one clock, then tri-state.
Any SER_IRQ Device (i.e., The SCH3227/SCH3226/SCH3224/SCH3222 which detects any transition on an IRQ/Data
line for which it is responsible must initiate a Start Frame in order to update the Host Controller unless the SER_IRQ is
already in an SER_IRQ Cycle and the IRQ/Data transition can be delivered in that SER_IRQ Cycle
2. Continuous (Idle) Mode: Only the Host controller can initiate a Start Frame to update IRQ/Data line information.
All other SER_IRQ agents become passive and may not initiate a Start Frame. SER_IRQ will be driven low for
four to eight clocks by Host Controller. This mode has two functions. It can be used to stop or idle the SER_IRQ
or the Host Controller can operate SER_IRQ in a continuous mode by initiating a Start Frame at the end of every
Stop Frame.
An SER_IRQ mode transition can only occur during the Stop Frame. Upon reset, SER_IRQ bus is defaulted to Contin-
uous mode, therefore only the Host controller can initiate the first Start Frame. Slaves must continuously sample the
Stop Frames pulse width to determine the next SER_IRQ Cycle’s mode.
9.3
SER_IRQ Data Frame
Once a Start Frame has been initiated, the SCH3227/SCH3226/SCH3224/SCH3222 will watch for the rising edge of the
Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase,
Recovery phase, and Turn-around phase. During the Sample phase the SCH3227/SCH3226/SCH3224/SCH3222 must
drive the SER_IRQ low, if and only if, its last detected IRQ/Data value was low. If its detected IRQ/Data value is high,
SER_IRQ must be left tri-stated. During the Recovery phase the SCH3227/SCH3226/SCH3224/SCH3222 must drive
the SER_IRQ high, if and only if, it had driven the SER_IRQ low during the previous Sample Phase. During the Turn-
around
Phase
the
SCH3227/SCH3226/SCH3224/SCH3222
must
tri-state
the
SER_IRQ.The
SCH3227/SCH3226/SCH3224/SCH3222 will drive the SER_IRQ line low at the appropriate sample point if its associ-
ated IRQ/Data line is low, regardless of which device initiated the Start Frame.
The Sample Phase for each IRQ/Data follows the low to high transition of the Start Frame pulse by a number of clocks
equal to the IRQ/Data Frame times three, minus one. (e.g. The IRQ5 Sample clock is the sixth IRQ/Data Frame, (6 x 3)
- 1 = 17th clock after the rising edge of the Start Pulse).
SER_IRQ Sampling Periods
SER_IRQ Period
Signal Sampled
# of Clocks Past Start
1
Not Used
IRQ1
2
2
5
3
nIO_SMI/IRQ2
IRQ3
8
4
11
14
17
20
23
26
29
32
35
38
5
IRQ4
6
IRQ5
7
IRQ6
8
IRQ7
9
IRQ8
10
11
12
13
IRQ9
IRQ10
IRQ11
IRQ12
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SCH3227/SCH3226/SCH3224/SCH3222
SER_IRQ Sampling Periods
SER_IRQ Period
Signal Sampled
# of Clocks Past Start
14
15
16
IRQ13
IRQ14
IRQ15
41
44
47
The SER_IRQ data frame supports IRQ2 from a logical device on Period 3, which can be used for the System Manage-
ment Interrupt (nSMI). When using Period 3 for IRQ2 the user should mask off the SMI via the SMI Enable Register.
Likewise, when using Period 3 for nSMI the user should not configure any logical devices as using IRQ2.
SER_IRQ Period 14 is used to transfer IRQ13. Logical devices 3 (Par Port), 4 (Ser Port 1), 5 (Ser Port 2), and 7 (KBD)
shall have IRQ13 as a choice for their primary interrupt.
The SMI is enabled onto the SMI frame of the Serial IRQ via bit 6 of SMI Enable Register 2 and onto the nIO_SMI pin
via bit 7 of the SMI Enable Register 2.
9.4
Stop Cycle Control
Once all IRQ/Data Frames have completed the Host Controller will terminate SER_IRQ activity by initiating a Stop
Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the SER_IRQ is low for
two or three clocks. If the Stop Frame’s low time is two clocks then the next SER_IRQ Cycle’s sampled mode is the
Quiet mode; and any SER_IRQ device may initiate a Start Frame in the second clock or more after the rising edge of
the Stop Frame’s pulse. If the Stop Frame’s low time is three clocks then the next SER_IRQ Cycle’s sampled mode is
the Continuous mode; and only the Host Controller may initiate a Start Frame in the second clock or more after the rising
edge of the Stop Frame’s pulse.
9.5
Latency
Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum Host supported
IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84S with a 25MHz PCI Bus or 2.88uS with a 33MHz PCI
Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the secondary or
tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses.
9.6
EOI/ISR Read Latency
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an
EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host
interrupt controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is to
delay EOIs and ISR Reads to the interrupt controller by the same amount as the SER_IRQ Cycle latency in order to
ensure that these events do not occur out of order.
9.7
AC/DC Specification Issue
All SER_IRQ agents must drive / sample SER_IRQ synchronously related to the rising edge of PCI bus clock. The
SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will follow PCI spec. section 4, sustained
tri-state.
9.8
Reset and Initialization
The SER_IRQ bus uses PCI_RESET# as its reset signal. The SER_IRQ pin is tri-stated by all agents while PCI_RE-
SET# is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode. The Host Controller is responsible
for starting the initial SER_IRQ Cycle to collect system’s IRQ/Data default values. The system then follows with the Con-
tinuous/Quiet mode protocol (Stop Frame pulse width) for subsequent SER_IRQ Cycles. It is Host Controller’s respon-
sibility to provide the default values to 8259’s and other system logic before the first SER_IRQ Cycle is performed. For
SER_IRQ system suspend, insertion, or removal application, the Host controller should be programmed into Continuous
(IDLE) mode first. This is to ensure SER_IRQ bus is in IDLE state before the system configuration changes.
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SCH3227/SCH3226/SCH3224/SCH3222
10.0 8042 KEYBOARD CONTROLLER DESCRIPTION
The SCH3227/SCH3226/SCH3224/SCH3222 is a Super I/O and Universal Keyboard Controller that is designed for
intelligent keyboard management in desktop computer applications. The Universal Keyboard Controller uses an 8042
microcontroller CPU core. This section concentrates on the SCH3227/SCH3226/SCH3224/SCH3222 enhancements to
the 8042. For general information about the 8042, refer to the “Hardware Description of the 8042” in the 8-Bit Embedded
Controller Handbook.
FIGURE 10-1:
SCH3227/SCH3226/SCH3224/SCH3222 KEYBOARD AND MOUSE INTERFACE
8042A
LS05
P27
P10
KDAT
KCLK
MCLK
MDAT
P26
TST0
P23
TST1
P22
P11
Keyboard and Mouse Interface
KIRQ is the Keyboard IRQ
MIRQ is the Mouse IRQ
Port 21 is used to create a GATEA20 signal from the SCH3227/SCH3226/SCH3224/SCH3222.
10.1 Keyboard Interface
The SCH3227/SCH3226/SCH3224/SCH3222 LPC interface is functionally compatible with the 8042 style host inter-
face. It consists of the D0-7 data signals; the read and write signals and the Status register, Input Data register, and
Output Data register. Table 10-1 shows how the interface decodes the control signals. In addition to the above signals,
the host interface includes keyboard and mouse IRQs.
TABLE 10-1: I/O ADDRESS MAP
Address
Command
Block
Function (See Note)
Keyboard Data Write (C/D=0)
Write
Read
Write
Read
KDATA
KDATA
KDCTL
KDCTL
0x60
Keyboard Data Read
Keyboard Command Write (C/D=1)
Keyboard Status Read
0x64
Note: These registers consist of three separate 8-bit registers. Status, Data/Command Write and Data
Read.
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Keyboard Data Write
This is an 8 bit write only register. When written, the C/D status bit of the status register is cleared to zero and the IBF
bit is set.
Keyboard Data Read
This is an 8 bit read only register. If enabled by “ENABLE FLAGS”, when read, the KIRQ output is cleared and the OBF
flag in the status register is cleared. If not enabled, the KIRQ and/or AUXOBF1 must be cleared in software.
Keyboard Command Write
This is an 8 bit write only register. When written, the C/D status bit of the status register is set to one and the IBF bit is set.
Keyboard Status Read
This is an 8 bit read only register. Refer to the description of the Status Register for more information.
CPU-to-Host Communication
The SCH3227/SCH3226/SCH3224/SCH3222 CPU can write to the Output Data register via register DBB. A write to this
register automatically sets Bit 0 (OBF) in the Status register. See Table 10-2.
TABLE 10-2: HOST INTERFACE FLAGS
8042 Instruction
OUT DBB
Host-to-CPU Communication
Flag
Set OBF, and, if enabled, the KIRQ output signal goes high
The host system can send both commands and data to the Input Data register. The CPU differentiates between com-
mands and data by reading the value of Bit 3 of the Status register. When bit 3 is “1”, the CPU interprets the register
contents as a command. When bit 3 is “0”, the CPU interprets the register contents as data. During a host write opera-
tion, bit 3 is set to “1” if SA2 = 1 or reset to “0” if SA2 = 0.
KIRQ
If “EN FLAGS” has been executed and P24 is set to a one: the OBF flag is gated onto KIRQ. The KIRQ signal can be
connected to system interrupt to signify that the SCH3227/SCH3226/SCH3224/SCH3222 CPU has written to the output
data register via “OUT DBB,A”. If P24 is set to a zero, KIRQ is forced low. On power-up, after a valid RST pulse has
been delivered to the device, KIRQ is reset to 0. KIRQ will normally reflects the status of writes “DBB”. (KIRQ is normally
selected as IRQ1 for keyboard support.)
If “EN FLAGS” has not been executed: KIRQ can be controlled by writing to P24. Writing a zero to P24 forces KIRQ low;
a high forces KIRQ high.
MIRQ
If “EN FLAGS” has been executed and P25 is set to a one:; IBF is inverted and gated onto MIRQ. The MIRQ signal can
be connected to system interrupt to signify that the SCH3227/SCH3226/SCH3224/SCH3222 CPU has read the DBB
register. If “EN FLAGS” has not been executed, MIRQ is controlled by P25, Writing a zero to P25 forces MIRQ low, a
high forces MIRQ high. (MIRQ is normally selected as IRQ12 for mouse support).
Gate A20
A general purpose P21 is used as a software controlled Gate A20 or user defined output.
8042 PINS
The 8042 functions P17, P16 and P12 are implemented as in a true 8042 part. Reference the 8042 spec for all timing.
A port signal of 0 drives the output to 0. A port signal of 1 causes the port enable signal to drive the output to 1 within
20-30nsec. After 500nsec (six 8042 clocks) the port enable goes away and the external pull-up maintains the output
signal as 1.
In 8042 mode, the pins can be programmed as open drain. When programmed in open drain mode, the port enables
do not come into play. If the port signal is 0 the output will be 0. If the port signal is 1, the output tristates: an external
pull-up can pull the pin high, and the pin can be shared. In 8042 mode, the pins cannot be programmed as input nor
inverted through the GP configuration registers.
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SCH3227/SCH3226/SCH3224/SCH3222
10.2 External Keyboard and Mouse Interface
Industry-standard PC-AT-compatible keyboards employ a two-wire, bidirectional TTL interface for data transmission.
Several sources also supply PS/2 mouse products that employ the same type of interface. To facilitate system expan-
sion, the SCH3227/SCH3226/SCH3224/SCH3222 provides four signal pins that may be used to implement this inter-
face directly for an external keyboard and mouse.
The SCH3227/SCH3226/SCH3224/SCH3222 has four high-drive, open-drain output, bidirectional port pins that can be
used for external serial interfaces, such as external keyboard and PS/2-type mouse interfaces. They are KCLK, KDAT,
MCLK, and MDAT. P26 is inverted and output as KCLK. The KCLK pin is connected to TEST0. P27 is inverted and out-
put as KDAT. The KDAT pin is connected to P10. P23 is inverted and output as MCLK. The MCLK pin is connected to
TEST1. P22 is inverted and output as MDAT. The MDAT pin is connected to P11.
Note:
External pull-ups may be required.
10.2.1
KEYBOARD/MOUSE SWAP BIT
There is a Kbd/mouse Swap bit in the Keyboard Select configuration register located at 0xF1 in Logical Device 7. This
bit can be used to swap the keyboard and mouse clock and data pins into/out of the 8042. The default value of this bit
is ‘0’ on VCC POR, VTR POR and PCI Reset.
1=internally swap the KCLK pin and the MCLK pin, and the KDAT pin and the MDAT pin into/out of the 8042.
0=do not swap the keyboard and mouse clock and data pins
10.3 Keyboard Power Management
The keyboard provides support for two power-saving modes: soft power-down mode and hard power-down mode. In
soft power-down mode, the clock to the ALU is stopped but the timer/counter and interrupts are still active. In hard power
down mode the clock to the 8042 is stopped.
Soft Power-Down Mode
This mode is entered by executing a HALT instruction. The execution of program code is halted until either RESET is
driven active or a data byte is written to the DBBIN register by a master CPU. If this mode is exited using the interrupt,
and the IBF interrupt is enabled, then program execution resumes with a CALL to the interrupt routine, otherwise the
next instruction is executed. If it is exited using RESET then a normal reset sequence is initiated and program execution
starts from program memory location 0.
Hard Power-Down Mode
This mode is entered by executing a STOP instruction. The oscillator is stopped by disabling the oscillator driver cell.
When either RESET is driven active or a data byte is written to the DBBIN register by a master CPU, this mode will be
exited (as above). However, as the oscillator cell will require an initialization time, either RESET must be held active for
sufficient time to allow the oscillator to stabilize. Program execution will resume as above.
10.4 Interrupts
The SCH3227/SCH3226/SCH3224/SCH3222 provides the two 8042 interrupts: IBF and the Timer/Counter Overflow.
10.5 Memory Configurations
The SCH3227/SCH3226/SCH3224/SCH3222 provides 2K of on-chip ROM and 256 bytes of on-chip RAM.
10.6 Register Definitions
Host I/F Data Register
The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will load the Keyboard
Data Read Buffer, set the OBF flag and set the KIRQ output if enabled. A read of this register will read the data from the
Keyboard Data or Command Write Buffer and clear the IBF flag. Refer to the KIRQ and Status register descriptions for
more information.
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Host I/F Status Register
The Status register is 8 bits wide.
Table 10-3 shows the contents of the Status register.
TABLE 10-3: STATUS REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
UD
UD
UD
UD
C/D
UD
IBF
OBF
Status Register
This register is cleared on
a
reset. This register is read-only for the Host and read/write by the
SCH3227/SCH3226/SCH3224/SCH3222 CPU.
UD Writable by SCH3227/SCH3226/SCH3224/SCH3222 CPU. These bits are user-definable.
C/D (Command Data)-This bit specifies whether the input data register contains data or a command (0 = data, 1 =
command). During a host data/command write operation, this bit is set to “1” if SA2 = 1 or reset to “0” if SA2 = 0.
IBF (Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input data register. Setting
this flag activates the SCH3227/SCH3226/SCH3224/SCH3222 CPU’s nIBF (MIRQ) interrupt if enabled. When
the SCH3227/SCH3226/SCH3224/SCH3222 CPU reads the input data register (DBB), this bit is automatically
reset and the interrupt is cleared. There is no output pin associated with this internal signal.
OBF (Output Buffer Full) - This flag is set to whenever the SCH3227/SCH3226/SCH3224/SCH3222 CPU write to the
output data register (DBB). When the host system reads the output data register, this bit is automatically reset.
10.7 External Clock Signal
The SCH3227/SCH3226/SCH3224/SCH3222 Keyboard Controller clock source is a 12 MHz clock generated from a
14.318 MHz clock. The reset pulse must last for at least 24 16 MHz clock periods. The pulse-width requirement applies
to both internally (VCC POR) and externally generated reset signals. In power-down mode, the external clock signal is
not loaded by the chip.
10.8 Default Reset Conditions
The SCH3227/SCH3226/SCH3224/SCH3222 has one source of hardware reset: an external reset via the PCI_RESET#
pin. Refer to Table 10-4 for the effect of each type of reset on the internal registers.
TABLE 10-4: RESETS
Description
Hardware Reset (PCI_RESET#)
KCLK
Low
Low
Low
Low
N/A
00H
KDAT
MCLK
MDAT
Host I/F Data Reg
Host I/F Status Reg
Note: N/A = Not Applicable
10.9 GATEA20 and Keyboard Reset
The SCH3227/SCH3226/SCH3224/SCH3222 provides two options for GateA20 and Keyboard Reset: 8042 Software
Generated GateA20 and KRESET and Port 92 Fast GateA20 and KRESET.
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SCH3227/SCH3226/SCH3224/SCH3222
10.10 Port 92 Fast GATEA20 and Keyboard Reset
Port 92 Register
This port can only be read or written if Port 92 has been enabled via bit 2 of the KRST_GA20 Register (Logical Device
7, 0xF0) set to 1.
This register is used to support the alternate reset (nALT_RST) and alternate A20 (ALT_A20) functions.
Name
Port 92
Location
92h
24h
Default Value
Attribute
Size
Read/Write
8 bits
Port 92 Register
Function
Bit
7:6
5
Reserved. Returns 00 when read
Reserved. Returns a 1 when read
Reserved. Returns a 0 when read
Reserved. Returns a 0 when read
Reserved. Returns a 1 when read
4
3
2
1
ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be driven low. Writing a
1 to this bit causes the ALT_A20 signal to be driven high.
0
Alternate System Reset. This read/write bit provides an alternate system reset function. This function
provides an alternate means to reset the system CPU to effect a mode switch from Protected Virtual
Address Mode to the Real Address Mode. This provides a faster means of reset than is provided by
the Keyboard controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause the
nALT_RST signal to pulse active (low) for a minimum of 1 µs after a delay of 500 ns. Before another
nALT_RST pulse can be generated, this bit must be written back to a 0.
NGATEA20
8042 P21
ALT_A20
System NA20M
0
0
1
1
0
1
0
1
0
1
1
1
Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program control. This signal is
AND’ed together externally with the reset signal (nKBDRST) from the keyboard controller to provide a software means
of resetting the CPU. This provides a faster means of reset than is provided by the keyboard controller. Writing a 1 to
bit 0 in the Port 92 Register causes this signal to pulse low for a minimum of 6µs, after a delay of a minimum of 14µs.
Before another nALT_RST pulse can be generated, bit 0 must be set to 0 either by a system reset of a write to Port 92.
Upon reset, this signal is driven inactive high (bit 0 in the Port 92 Register is set to 0).
If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing a 1 to bit 0 of the Port 92
Register and this pulse is AND’ed with the pulse generated from the 8042. This pulse is output on pin KRESET and its
polarity is controlled by the GPI/O polarity configuration.
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SCH3227/SCH3226/SCH3224/SCH3222
FIGURE 10-2:
GPI/O POLARITY CONFIGURATION
14us
~~
6us
8042
P20
KRST
KBDRST
KRST_GA2
Bit 2
P92
nALT_RST
Bit 0
Pulse
Gen
14us
Note: When Port 92 is
writes are ignored and
return undefined
~
~
6us
Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode compatible soft-
ware. This signal is externally OR’ed with the A20GATE signal from the keyboard controller and CPURST to control the
nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92 Register forces ALT_A20 low. ALT_A20 low drives nA20M
to the CPU low, if A20GATE from the keyboard controller is also low. Writing a 1 to bit 1 of the Port 92 Register forces
ALT_A20 high. ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE from the keyboard
controller. Upon reset, this signal is driven low.
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SCH3227/SCH3226/SCH3224/SCH3222
Latches On Keyboard and Mouse IRQs
The implementation of the latches on the keyboard and mouse interrupts is shown below.
FIGURE 10-3:
KEYBOARD LATCH
KLATCH Bit
VCC
D
KINnTew
Q
KINT
CLR
8042
RD 60
FIGURE 10-4:
MOUSE LATCH
MLATCH Bit
VCC
D
MINT
new
Q
MINT
CLR
8042
RD 60
The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Logical Device 7 at 0xF0.
These bits are defined as follows:
Bit[4]: MLATCH – Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched MINT (default),
1=MINT is the latched 8042 MINT.
Bit[3]: KLATCH – Keyboard Interrupt latch control bit. 0=KINT is the 8042 KINT ANDed with Latched KINT (default),
1=KINT is the latched 8042 KINT.
See Table 23-13, “KYBD. Logical Device 7 [Logical Device Number = 0X07],” on page 209 for a description of this reg-
ister.
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10.11 Keyboard and Mouse PME Generation
The SCH3227/SCH3226/SCH3224/SCH3222 sets the associated PME Status bits when the following conditions occur:
Keyboard Interrupt
• Mouse Interrupt
• Active Edge on Keyboard Data Signal (KDAT)
• Active Edge on Mouse Data Signal (MDAT)
These events can cause a PME to be generated if the associated PME Wake Enable register bit and the global PME_EN
bit are set. Refer to Section 13.0, "PME Support," on page 94 for more details on the PME interface logic and refer to
Section 24.0, "Runtime Register," on page 213 for details on the PME Status and Enable registers.
The keyboard interrupt and mouse interrupt PMEs can be generated when the part is powered by VCC. The keyboard
data and mouse data PMEs can be generated both when the part is powered by VCC, and when the part is powered
by VTR (VCC=0).
When using the keyboard and mouse data signals for wakeup, it may be necessary to isolate the keyboard signals
(KCLK, KDAT, MCLK, MDAT) from the 8042 prior to entering certain system sleep states. This is due to the fact that the
normal operation of the 8042 can prevent the system from entering a sleep state or trigger false PME events. The
SCH3227/SCH3226/SCH3224/SCH3222 has “isolation” bits for the keyboard and mouse signals, which allow the key-
board and mouse data signals to go into the wakeup logic but block the clock and data signals from the 8042. These
bits may be used anytime it is necessary to isolate the 8042 keyboard and mouse signals from the 8042 before entering
a system sleep state.
The bits used to isolate the keyboard and mouse signals from the 8042 are located in Logical Device 7, Register 0xF0
(KRST_GA20) and are defined below. These bits reset on VTR POR only.
Bit[6]M_ISO. Enables/disables isolation of mouse signals into 8042. Does not affect the MDAT signal to The mouse
wakeup (PME) logic.
1 = block mouse clock and data signals into 8042
0 = do not block mouse clock and data signals into 8042
Bit[5] K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect the KDAT signal to the keyboard
wakeup (PME) logic.
1 = block keyboard clock and data signals into 8042
0 = do not block keyboard clock and data signals into 8042
When the keyboard and/or mouse isolation bits are used, it may be necessary to reset the 8042 upon exiting the sleep
state. If either of the isolation bits is set prior to entering a sleep state where VCC goes inactive (S3-S5), then the 8042
must be reset upon exiting the sleep mode. Write 0x40 to global configuration register 0x2C to reset the 8042. The 8042
must then be taken out of reset by writing 0x00 to register 0x2C since the bit that resets the 8042 is not self-clearing.
Bit 6 of configuration register 0x2C is used to put the 8042 into reset - do not set any of the other bits in register 0x2C,
as this may produce undesired results.
It is not necessary to reset the 8042 if the isolation bits are used for a sleep state where VCC does not go inactive (S1,
S2).
USER’S NOTE:
Regarding External Keyboard and Mouse:
This is an application matter resulting from the behavior of the external 8042 in the keyboard.
When the external keyboard and external mouse are powered up, the KDAT and MDAT lines are driven low. This sets
the KBD bit (D3) and the MOUSE bit (D4) of the PME Wake Status Register since the KDAT and MDAT signals cannot
be isolated internal to the part. This causes an nIO_PME assertion to be generated if the keyboard and/or mouse PME
events are enabled. Note that the keyboard and mouse isolation bits only prevent the internal 8042 in the part from set-
ting these status bits.
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SCH3227/SCH3226/SCH3224/SCH3222
Case 1: Keyboard and/or Mouse Powered by VTR
The KBD and/or MOUSE status bits will be set upon a VTR POR if the keyboard and/or mouse are powered by VTR.
In this case, a nIO_PME will not be generated, since the keyboard and mouse PME enable bits are reset to zero on a
VTR POR. The BIOS software needs to clear these PME status bits after power-up.
In this case, an nIO_PME will be generated if the enable bits were set for wakeup, since the keyboard and mouse PME
enable bits are Bvat powered. Therefore, if the keyboard and mouse are powered by VTR, the enable bits for keyboard
and mouse events should be cleared prior to entering a sleep state where VTR is removed (i.e., S4 or S5) to prevent a
false PME from being generated. In this case, the keyboard and mouse should only be used as PME and/or wake events
from the power states S3 or below.
Case 2: Keyboard and/or Mouse Powered by VCC
The KBD and/or MOUSE status bits will be set upon a VCC POR if the keyboard and/or mouse are powered by VCC.
In this case, a nIO_PME and a nIO_PME will be generated if the enable bits were set for wakeup, since the keyboard
and mouse PME enable bits are VTRor Vbat powered. Therefore, if the keyboard and mouse are powered by VCC, the
enable bits for keyboard and mouse events should be cleared prior to entering a sleep state where VCC is removed
(i.e., S3) to prevent a false PME from being generated. In this case, the keyboard and mouse should only be used as
PME and/or wake events from the S0 and/or S1 states. The BIOS software needs to clear these PME status bits after
power-up.
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SCH3227/SCH3226/SCH3224/SCH3222
11.0 GENERAL PURPOSE I/O (GPIO)
The SCH322x provides a set of flexible Input/Output control functions to the system designer through the independently
programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and many of them can be indi-
vidually enabled to generate an SMI and a PME.
CAUTION: This device architecture contains registers, controlling GPIOs that may not be brought out to package pins
in some specific family members. See Table 2-1 SCH3227, Table 2-2 SCH3226, Table 2-3 SCH3224, or Table 2-4
SCH3222, for the pins that are brought out. Pins which are not brought out must not be used because they are tied to
known states internally. Do not change their configurations from their POR defaults, because doing so may cause unpre-
dictable behavior and/or excessive currents, and therefore may damage the device and/or the system.
11.1 GPIO Pins
The following pins include GPIO functionality. These pins are defined in the table below.
TABLE 11-1: GPIO PIN FUNCTIONALITY
GPIO Pin Name
GPIO
(Default Func/
VTR POR
SMI/PME
Note
PWRWELL
Alternate Funcs)
GP10
VCC
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
11-3
11-3
11-3
GP10 / RXD3
GP11
GP11 / TXD3
VTR
VTR
VTR
VTR
VTR
VCC
VTR
GP12
GP12 / nDCD3
GP13
GP13 / nRI3
PME
11-3,
11-4
GP14
GP14 / nDSR3
11-3
11-3
11-3
11-3
GP15
GP15 / nDTR3
GP16
GP16 / nCTS3
GP17
GP17 / nRTS3
KDAT/GP21
VCC
VCC
VCC
VTR
VTR
0x8C
0x8C
0x01
0x05
0x01
SMI/PME
11-1, 11-3
11-1, 11-3
11-1
KCLK/GP22
SMI/PME
GP27/nIO_SMI /P17
nFPRST / GP30
nIO_SMI/PME
11-3
GP31
GP31 / nRI4
PME
11-3,
11-4
11-5
MDAT/GP32
MCLK/GP33
VCC
VCC
VTR
0x84
0x84
0x01
SMI/PME
SMI/PME
11-1
11-3
11-1
11-3
GP34
GP34 / nDTR4
11-3
11-5
GP36/nKBDRST
GP37/A20M
VCC
VCC
VCC
VTR
VTR
0x01
0x01
0x01
0x01
0x01
-
-
GP40/DRVDEN0
GP42/nIO_PME
-
SMI
nIDE_RSTDRV / GP44
GP44 / TXD6
11-3
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TABLE 11-1: GPIO PIN FUNCTIONALITY (CONTINUED)
GPIO Pin Name
(Default Func/
Alternate Funcs)
GPIO
PWRWELL
VTR POR
SMI/PME
Note
nPCI_RST1 / GP45
VTR
0x01
0x01
0x01
11-3
GP45 / RXD6
nPCI_RST2 / GP46
GP46 / nSCIN6
VTR
VTR
PME
11-3,
11-4
nPCI_RST3 / GP47
GP47 / nSCOUT6
11-3
GP50/nRI2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VTR
VTR
VTR
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
PME
11-1
11-1
11-1
11-1
11-1
11-1
11-1
11-1
11-1
11-1
11-3
GP51/nDCD2
PME
GP52/RXD2(IRRX)
GP53/TXD2 (IRTX)
GP54/nDSR2
PME
PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
GP55/nRTS2
GP56/nCTS2
GP57/nDTR2
GP60/nLED1/WDT
GP61/nLED2/ CLKO
GP62
GP62 / nCTS4
GP63
VTR
VTR
VTR
VTR
VTR
0x01
0x01
0x01
0x01
0x01
11-3
11-3
11-3
11-3
11-3
GP63 / nDCD4
GP64
GP64 / RXD4
GP65
GP65 / TXD4
GP66
GP66 / nDCR4
GP67
GP67 / nRTS4
Note 11-1
Note 11-2
Note 11-3
These pins are inputs to VCC and VTR powered logic. The logic for the GPIO is on VCC - it is also
a wake event which goes to VTR powered logic.
This pin’s primary function (power up default function) is not GPIO function; however, the pin can be
configured a GPIO Alternate function.
Not all pins are available in all family members. Also, in some cases incorrect usage can cause
damage. See the CAUTION note at the beginning of this chapter: Section 11.0, General Purpose I/O
(GPIO).
Note 11-4
Note 11-5
The PME is for the RI signal only. Note that this may not be available for all SCH322x devices. Refer
to Table 11-2, “SCH322x General Purpose I/O Port Assignments,” on page 88 for more details.
This pin is an OD type buffer in output mode. It cannot be configured as a Push-Pull Output buffer
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11.2 Description
Each GPIO port has a 1-bit data register and an 8-bit configuration control register. The data register for each GPIO port
is represented as a bit in one of the 8-bit GPIO DATA Registers, GP1 to GP6. The bits in these registers reflect the value
of the associated GPIO pin as follows. Pin is an input: The bit is the value of the GPIO pin. Pin is an output: The value
written to the bit goes to the GPIO pin. Latched on read and write. All of the GPIO registers are located in the PME block
see Section 24.0, "Runtime Register," on page 213. The GPIO ports with their alternate functions and configuration state
register addresses are listed in Table 11-2.
TABLE 11-2: SCH322X GENERAL PURPOSE I/O PORT ASSIGNMENTS
Run-Time
ALT.
GP
GP
REG Offset
(HEX)
DEF
ALT. FUNC. 1
ALT. FUNC. 2
FUNC. 3
Data REG Data Bit
23
24
25
26
27
29
2A
2B
GPIO10
RXD3
GP1
0
1
2
3
4
5
6
7
0
1
OFFSET
4B
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
Reserved
TXD3
nDCD3
nRI3
nDSR3
nDTR3
nCTS3
nRTS3
GP2
OFFSET
4C
2C
2D
KDAT (See
Note 11-6)
GPIO21
GPIO22
KCLK (See
Note 11-6)
2
Reserved
Reserved
Reserved
GPIO27
4:3
5
6
32
SMI Output
P17 (See
Note 11-6)
7
33
34
35
nFPRST
GPIO31
GPIO30
nRI4
GP3
OFFSET
4D
0
1
2
MDAT (See
Note 11-6)
GPIO32
36
37
MCLK (See
Note 11-6)
GPIO33
nDTR4
3
GPIO34
Reserved
GPIO36
GPIO37
GPIO40
4
5
6
7
0
39
3A
3B
Keyboard Reset
Gate A20
Drive Density Select
0
GP4
OFFSET
4E
Reserved
GPIO42
Reserved
GPIO44
GPIO45
GPIO46
GPIO47
1
2
3
4
5
6
7
3D
nIO_PME
6E
6F
72
73
TXD6
RXD6
nSCIN6
nSCOUT6
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TABLE 11-2: SCH322X GENERAL PURPOSE I/O PORT ASSIGNMENTS (CONTINUED)
Run-Time
ALT.
GP
GP
REG Offset
(HEX)
DEF
ALT. FUNC. 1
ALT. FUNC. 2
FUNC. 3
Data REG Data Bit
3F
40
GPIO50
Ring Indicator 2
GP5
OFFSET
4F
0
1
GPIO51
GPIO52
GPIO53
Data Carrier Detect
2
41
42
Receive Serial Data
2
2
3
Transmit Serial Data
2
43
44
45
46
47
GPIO54
GPIO55
GPIO56
GPIO57
Data Set Ready 2
Request to Send 2
Clear to Send 2
Date Terminal Ready
nLED1
4
5
6
7
0
GPIO60
Note 11-7
WDT
CLKO
WDT
GP6
OFFSET
50
48
54
55
56
57
58
59
GPIO61
Note 11-7
nLED2
nCTS4
nDCD4
RXD4
1
2
3
4
5
6
7
GPIO62
Note 11-8
GPIO63
Note 11-8
GPIO64
Note 11-8
GPIO65
Note 11-8
TXD4
GPIO66
Note 11-8
nDSR4
nRTS4
GPIO67
Note 11-8
Note 11-6
Note 11-7
When this pin function is selected, the associated GPIO pins have bi-directional functionality.
These pins have Either Edge Triggered Interrupt (EETI) functionality. See Section 11.5, "GPIO PME
and SMI Functionality," on page 91 for more details.
Note 11-8
These pins have VID compatible inputs.
11.3 GPIO Control
Each GPIO port has an 8-bit control register that controls the behavior of the pin. These registers are defined in Section
24.0, "Runtime Register," on page 213 section of this specification.
Each GPIO port may be configured as either an input or an output. If the pin is configured as an output, it can be pro-
grammed as open-drain or push-pull. Inputs and outputs can be configured as non-inverting or inverting. Bit[0] of each
GPIO Configuration Register determines the port direction, bit[1] determines the signal polarity, and bit[7] determines
the output driver type select. The GPIO configuration register Output Type select bit[7] applies to GPIO functions and
the nSMI Alternate functions.
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The basic GPIO configuration options are summarized in Table 11-3, "GPIO Configuration Option".
TABLE 11-3: GPIO CONFIGURATION OPTION
Direction Bit
B0
Polarity Bit
B1
Selected Function
Description
GPIO
0
0
1
1
0
1
0
1
Pin is a non-inverted output.
Pin is an inverted output.
Pin is a non-inverted input.
Pin is an inverted input.
11.4 GPIO Operation
The operation of the GPIO ports is illustrated in Figure 11-1.
When a GPIO port is programmed as an input, reading it through the GPIO data register latches either the inverted or
non-inverted logic value present at the GPIO pin. Writing to a GPIO port that is programmed as an input has no effect
(Table 11-4).
When a GPIO port is programmed as an output, the logic value or the inverted logic value that has been written into the
GPIO data register is output to the GPIO pin. Reading from a GPIO port that is programmed as an output returns the
last value written to the data register (Table 11-4). When the GPIO is programmed as an output, the pin is excluded from
the PME and SMI logic.
FIGURE 11-1:
GPIO FUNCTION ILLUSTRATION
GPIO
GPIO
Configuration
Register bit-1
(Polarity)
Configuration
Register bit-0
(Input/Output)
D-TYPE
SD-bit
D
Q
GPx_nIOW
GPx_nIOR
GPIO
PIN
Transparent
0
1
Q
D
GPIO
Data Register
Bit-n
Note:
Figure 11-1 is for illustration purposes only and is not intended to suggest specific implementation details.
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TABLE 11-4: GPIO READ/WRITE BEHAVIOR
Host Operation
GPIO Input Port
GPIO Output Port
READ
LATCHED VALUE OF GPIO PIN
NO EFFECT
LAST WRITE TO GPIO DATA REGISTER
BIT PLACED IN GPIO DATA REGISTER
WRITE
11.5 GPIO PME and SMI Functionality
The SCH3227/SCH3226/SCH3224/SCH3222 provides GPIOs that can directly generate a PME. The polarity bit in the
GPIO control registers select the edge on these GPIO pins that will set the associated status bit in a PME Status. For
additional description of PME behavior see Section 13.0, "PME Support," on page 94. The default is the low-to-high
transition. In addition, the SCH3227/SCH3226/SCH3224/SCH3222 provides GPIOs that can directly generate an SMI.
The following GPIOs are dedicated wakeup GPIOs with a status and enable bit in the PME status and enable registers:
GP21-GP22,GP27, GP32-GP33 are controlled by PME_STS1, PME_STS3, PME_EN1, PME_EN3 registers.
GP50-GP57 are controlled by PME_STS5, PME_EN5 registers.
GP60, GP61 are controlled by PME_STS6, and PME_EN6 registers.
The following GPIOs can directly generate an SMI and have a status and enable bit in the SMI status and enable reg-
isters.
GP21, GP22, GP54, GP55, GP56, GP57, GP60 are controlled by SMI_STS3, and SMI_EN3 registers.
GP32, GP33, GP42, GP61 are controlled by SMI_STS4, and SMI_EN4 registers.
The following GPIOs have "either edge triggered interrupt" (EETI) input capability: GP21, GP22, GP60, GP61. These
GPIOs can generate a PME and an SMI on both a high-to-low and a low-to-high edge on the GPIO pin. These GPIOs
have a status bit in the PME_STS6 status register that is set on both edges. The corresponding bits in the PME and SMI
status registers are also set on both edges.
11.6 Either Edge Triggered Interrupts
Three GPIO pins are implemented such that they allow an interrupt (PME or SMI) to be generated on both a high-to-
low and a low-to-high edge transition, instead of one or the other as selected by the polarity bit.
The either edge triggered interrupts (EETI) function as follows: If the EETI function is selected for the GPIO pin, then
the bits that control input/output, polarity and open drain/push-pull have no effect on the function of the pin. However,
the polarity bit does affect the value of the GP bit.
A PME or SMI interrupt occurs if the PME or SMI enable bit is set for the corresponding GPIO and the EETI function is
selected on the GPIO. The PME or SMI status bits are set when the EETI pin transitions (on either edge) and are cleared
on a write of '1'. There are also status bits for the EETIs located in the PME_STSX register, which are also cleared on
a write of '1'. The MSC_STS register provides the status of all of the EETI interrupts within one register. The PME, SMI
or MSC status is valid whether or not the interrupt is enabled and whether or not the EETI function is selected for the pin.
Miscellaneous Status Register (MSC_STS) is for the either edge triggered interrupt status bits. If the EETI function is
selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding MSC status bits. Status
bits are cleared on a write of '1'. See Section 24.0, "Runtime Register," on page 213 for more information.
The configuration register for the either edge triggered interrupt status bits is defined in Section 24.0.
11.7 LED Functionality
The SCH3227/SCH3226/SCH3224/SCH3222 provides LED functionality on two GPIOs, GP60 and GP61. These pins
can be configured to turn the LED on and off and blink independent of each other through the LED1 and LED2 runtime
registers at offset 0x5D and 0x5E from the base address located in the primary base I/O address in Logical Device A.
The LED pins (GP60 and GP61) are able to control the LED while the part is under VTR power with VCC removed. In
order to control a LED while the part is under VTR power, the GPIO pin must be configured for the LED function and
either open drain or push-pull buffer type. In the case of open-drain buffer type, the pin is capable of sinking current to
control the LED. In the case of push-pull buffer type, the part will source current. The part is also able to blink the LED
under VTR power. The LED will not blink under VTR power (VCC removed) if the external 32KHz clock is not connected.
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The LED pins can drive a LED when the buffer type is configured to be push-pull and the part is powered by either VCC
or VTR, since the buffers for these pins are powered by VTR. This means they will source their specified current from
VTR even when VCC is present.
The LED control registers are defined in Section 24.0, "Runtime Register," on page 213.
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12.0 SYSTEM MANAGEMENT INTERRUPT (SMI)
The SCH322x implements a “group” nIO_SMI output pin. The System Management Interrupt is a non-maskable inter-
rupt with the highest priority level used for OS transparent power management. The nSMI group interrupt output consists
of the enabled interrupts from each of the functional blocks in the chip and many of the GPIOs and the Fan tachometer
pins. The GP27/nIO_SMI/P17 pin, when selected for the nIO_SMI function, can be programmed to be active high or
active low via the polarity bit in the GP27 register. The output buffer type of the pin can be programmed to be open-drain
or push-pull via bit 7 of the GP27 register. The nIO_SMI pin function defaults to active low, open-drain output.
The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 to 4. The nSMI output is then
enabled onto the group nIO_SMI output pin via bit[7] in the SMI Enable Register 2. The SMI output can also be enabled
onto the serial IRQ stream (IRQ2) via Bit[6] in the SMI Enable Register 2. The internal SMI can also be enabled onto
the nIO_PME pin. Bit[5] of the SMI Enable Register 2 (SMI_EN2) is used to enable the SMI output onto the nIO_PME
pin (GP42). This bit will enable the internal SMI output into the PME logic through the DEVINT_STS bit in PME_STS3.
An example logic equation for the nSMI output for SMI registers 1 and 2 is as follows:
nSMI = (EN_PINT and IRQ_PINT) or (EN_U2INT and IRQ_U2INT) or (EN_U1INT and IRQ_U1INT) or (EN_FINT and
IRQ_FINT) or (EN_MINT and IRQ_MINT) or (EN_KINT and IRQ_KINT) or (EN_IRINT and IRQ_IRINT) or (ENP12 and
IRQ_P12) or (SPEMSE_EN and SPEMSE_STS)
Note:
The prefixes EN and IRQ are used above to indicate SMI enable bit and SMI status bit respectively.
12.1 SMI Registers
The SMI event bits for the GPIOs and the Fan tachometer events are located in the SMI status and Enable registers 3-
5. The polarity of the edge used to set the status bit and generate an SMI is controlled by the polarity bit of the control
registers. For non-inverted polarity (default) the status bit is set on the low-to-high edge. If the EETI function is selected
for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding SMI status bit. Status bits for the
GPIOs are cleared on a write of ‘1’.
The SMI logic for these events is implemented such that the output of the status bit for each event is combined with the
corresponding enable bit in order to generate an SMI.
The SMI registers are accessed at an offset from PME_BLK (see Section 24.0, "Runtime Register," on page 213 for
more information).
The SMI event bits for the super I/O devices are located in the SMI status and enable register 1 and 2. All of these status
bits are cleared at the source except for IRINT, which is cleared by a read of the SMI_STS2 register; these status bits
are not cleared by a write of ‘1’. The SMI logic for these events is implemented such that each event is directly combined
with the corresponding enable bit in order to generate an SMI.
See the Section 24.0 for the definition of these registers.
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13.0 PME SUPPORT
The SCH322x offers support for power management events (PMEs), also referred to as a System Control Interrupt (SCI)
events in an ACPI system. A power management event is indicated to the chipset via the assertion of the nIO_PME
signal when in S5 or below power states.
APPLICATION NOTE: Software must properly configure the enable and status bits for the individual PME events in
the registers described below.
Table 13-1 describes the PME interface.
TABLE 13-1: PME INTERFACE
Name
nIO_PME
Buffer
Power Well
Description
(O12/OD12)
VTR
General Purpose I/O.
Power Management Event Output. This active low Power
Management Event signal allows this device to request
wakeup in S5 and below.
13.1 PME Events
All PME the events asserted on nIO_PME are listed in Table 13-2.
TABLE 13-2: PME EVENTS
Events
PME
Comment
Mouse
by IRQ
Y (from group SMI)
DATA pin edge sensitive
Specific Mouse Click
Y
Y
See Section 13.5, "Wake on
Specific Mouse Click," on
page 96 for details
Keyboard
Any Key
Specific Key
by IRQ
Y
Y
Y (from group SMI)
Power button input
Last state before Power Loss
PIO
Y
Y (from group SMI)
UART-1
by IRQ
Y (from group SMI)
Y
by nRI1 pin
UART-2
by IRQ
Y (from group SMI)
Y
by nRI2 pin
UART-3
by IRQ
Y (from group SMI)
Y
by nRI3 pin
UART-4
by IRQ
Y (from group SMI)
Y
by nRI4 pin
UART-5
by IRQ
Y (from group SMI)
Y
by nRI5 pin
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TABLE 13-2: PME EVENTS (CONTINUED)
Events
PME
Comment
UART-6
by IRQ
Y (from group SMI)
by nRI6 pin
Y
Hardware Monitor
Watch Dog Timer
GPIO, total 15 pins
Low-Battery
nHWM_INT
Y
Y
Y
Detect on VCC POR only not a
S3 wakeup either
The PME function is controlled by the PME status and enable registers in the runtime registers block, which is located
at the address programmed in configuration registers 0x60 and 0x61 in Logical.
There are four types of registers which control PME events:
1. PME Wake Status register (PME_STS1, PME_STS3, PME_STS5, PME_STS6.) provides the status of individual
wake events.
2. PME Wake Enable (PME_EN1, PME_EN3, PME_EN5, PME_EN6) provides the enable for individual wake
events.
3. PME Pin Enable Register (PME_EN,) provides an enable for the PME output pins.
4. PME Pin Status Register (PME_STS) provides the status for the PME output pins.
See Section 24.0, "Runtime Register," on page 213 for detailed register description.
The following describes the behavior to the PME status bits for each event:
Each wake source has a bit in a PME Wake Status register which indicates that a wake source has occurred. The PME
Wake Status bits are “sticky“(unless otherwise stated in bit description in Section 24.0): once a status bit is set by the
wake-up event, the bit will remains set until cleared by writing a ‘1’ to the bit.
Each PME Wake Status register has a corresponding PME Wake Enable Register.
If the corresponding bit in both in a PME Wake Status register and the PME Wake Enable Register are set then the PME
Pin Status Register bit is set. If both corresponding PME Pin Status and the PME Pin Enable Register bit are set then
the IO_PME pinIO_PME pin will asserted.
For the GPIO events, the polarity of the edge used to set the status bit and generate a PME is controlled by the polarity
bit of the GPIO control register. For non-inverted polarity (default) the status bit is set on the low-to-high edge. If the
EETI function is selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding PME
status bits. Status bits are cleared on a write of '1'.
The PME Wake registers also include status and enable bits for the HW Monitor Block.
See Section 10.11, "Keyboard and Mouse PME Generation," on page 84 for information about using the keyboard and
mouse signals to generate a PME.
13.2 Enabling SMI Events onto the PME Pin
There is a bit in the PME Status Register 3 to show the status of the internal “group” SMI signal in the PME logic (if bit
5 of the SMI_EN2 register is set). This bit, DEVINT_STS, is at bit 3 of the PME_STS3 register. When this bit is clear,
the group SMI output is inactive. When bit is set, the group SMI output is active.The corresponding Wake-up enable bit
is DEVINT_EN, is at bit 3 of the PME_EN3 register.
Bit 5 of the SMI_EN2 register must also be set. This bit is cleared on a write of '1'.
13.3 PME Function Pin Control
The GP42/nIO_PME pin, when selected for the nIO_PME function, can be programmed to be active high or active low
via the polarity bit in the GP42 register. The output buffer type of the pin can be programmed to be open-drain or push-
pull via bit 7 of the GP42 register. The nIO_PME pin function defaults to active low, open-drain output; however the
GP42/nIO_PME pin defaults to the GP42 function.
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In the SCH3227/SCH3226/SCH3224/SCH3222 the nIO_PME pin can be programmed to be an open drain, active low,
driver. The SCH3227/SCH3226/SCH3224/SCH3222 nIO_PME pin are fully isolated from other external devices that
might pull the signal low; i.e., the nIO_PME pin are capable of being driven high externally by another active device or
pull-up even when the SCH3227/SCH3226/SCH3224/SCH3222 VCC is grounded, providing VTR power is active. The
IO_PME pin driver sinks 6mA at 0.55V max (see section 4.2.1.1 DC Specifications in the "PCI Local Bus Specification,
Revision 2.2, December 18, 1998).
13.4 Wake on Specific Key Code
The SCH3227/SCH3226/SCH3224/SCH3222 Wake on Specific Key Code feature is enabled for the assertion of the
nIO_PME signal in SX power states by the SPEKEY bit in the PME_STS6 register. This bit defaults to enabled and is
Vbat powered.
At Vbat POR the Wake on Specific Key Code feature is disabled. During the first VTR POR and VCC POR the Wake
on Specific Key Code feature remains disabled. Software selects the precise Specific Key Code event (configuration)
to wake the system and then enables the feature via the SPEKEY bit in the PME_STS6 register. The system then may
go the sleep and/or have a power failure. After returning to or remaining in S5 sleep, the system will fully awake by a
Wake on Specific Key Code The Specific Key Code configuration and the enable for the nIO_PME are retained via Vbat
POR backed registers.
The SCH3227/SCH3226/SCH3224/SCH3222 Wake on Specific Key Code feature is enabled for assertion of the
nIO_PME signal when in S3 power state or below by the SPEKEY bit in the PME_EN6 register. This bit defaults to dis-
abled and is VTR powered.
13.5 Wake on Specific Mouse Click
The SPESME SELECT field in the Mouse_Specific_ Wake Register selects which mouse event is routed to the
PME_STS6 if enabled by PME_EN6. The KB_MSE_SWAP bit in the Mouse_Specific_ Wake Register can swap the
Mouse port and Keyboard interfaces internally.
The Lock bit in the Mouse_Specific_ Wake Register provides a means of changing access to read only to prevent tam-
pering with the Wake on Mouse settings. The other bits in the Mouse_Specific_ Wake Register are VBAT powered and
reset on VBAT POR; therefore, the mouse event settings are maintained through a power failure. The lock bit also con-
trols access to the DBLCLICK Register.
The DBLCLICK register contains a numeric value that determines the time interval used to check for a double mouse
click. The value is the time interval between mouse clicks. For example, if DBLCLICK is set to 0.5 seconds, you have
one half second to click twice for a double-click.
The larger the value in the DBLCLICK Register, the longer you can wait between the first and second click for the
SCH3227/SCH3226/SCH3224/SCH3222 to interpret the two clicks as a double-click mouse wake event. If the
DBLCLICK value is set to a very small value, even quick double clicks may be interpreted as two single clicks.
The DBLCLICK register has a six bit weighted sum value from 0 to 0x3Fh which provides a double click interval between
0.0859375 and 5.5 seconds. Each incremental digit has a weight of 0.0859375 seconds.
The DBLCLICK Register is VBAT powered and reset on VBAT POR; therefore, the double click setting is maintained
through a power failure. The default setting provides a 1.03125 second time interval.
DBLCLICK Writing to the DBLCLICK register shall reset the Mouse Wake-up internal logic and initialize the Mouse
Wake-up state machines.The SPEMSE_EN bit in of the CLOCKI32 configuration register at 0xF0 in Logical Device A
is used to control the “Wake on Specific Mouse Click” feature. This bit is used to turn the logic for this feature on and
off. It will disable the 32KHz clock input to the logic. The logic will draw no power when disabled. The bit is defined as
follows:
0= "Wake on Specific Mouse Click" logic is on (default)
1= "Wake on Specific Mouse Click" logic is off
The generation of a PME for this event is controlled by the PME enable bits (SPEMSE_EN bit in the PME_EN6 register
and in the SMI_EN2 register) when the logic for feature is turned on. See Section 13.5, "Wake on Specific Mouse
Click," on page 96.
APPLICATION NOTE: The Wake on Specific Mouse Click feature requires use of the M_ISO bit in the KRST_GA20
register. See Application Note 8.8 titled “Keyboard and Mouse Wake-up Functionality”.
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SCH3227/SCH3226/SCH3224/SCH3222
When using the wake on specific mouse event, it may be necessary to isolate the Mouse Port signals (MCLK, MDAT)
from the 8042 prior to entering certain system sleep states. This is due to the fact that the normal operation of the 8042
can
prevent
the
system
from
entering
a
sleep
state
or
trigger
false
PME
events.
SCH3227/SCH3226/SCH3224/SCH3222 has an “isolation” bit for the mouse signals, which allows the mouse data sig-
nals to go into the wake-up logic but block the clock and data signals from the 8042.
When the mouse isolation bit are used, it may be necessary to reset the 8042 upon exiting the sleep state. If M_SIO bit
is set prior to entering a sleep state where VCC goes inactive (S3-S5), then the 8042 must be reset upon exiting the
sleep mode. Write 0x40 to global configuration register 0x2C to reset the 8042. The 8042 must then be taken out of
reset by writing 0x00 to register 0x2C since the bit that resets the 8042 is not self-clearing. Caution: Bit 6 of configuration
register 0x2C is used to put the 8042 into reset - do not set any of the other bits in register 0x2C, as this may produce
undesired results.
2016-2017 Microchip Technology Inc.
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FIGURE 13-1:
8042 ISOLATION AND KEYBOARD AND MOUSE PORT SWAP
REPRESENTATION
ISO_
KDAT_IN
WAKE ON NON-
SPECIFC KEY
KBD
ISO_
KDAT
_IN
WAKE ON
SPEKEY
SPECIFC KEY
KB_MSE_SWAP
K_ISO
ISO_MDAT_OUT
PIN_KDAT_OUT
K
D
A
T
ISO KDAT_OUT
KDAT_OUT
ISO_
KDAT_IN
KDAT_IN
PIN_KDAT_IN
PIN_KCLK_OUT
ISO_KCLK_OUT
KCLK_OUT
K
C
L
ISO_MCLK_OUT
K
KCLK_IN
ISO_KCLK_IN
PIN_KCLK_IN
8042
ISO_KDAT_OUT
ISO MDAT_OUT
PIN_MDAT_OUT
M
D
A
T
MDAT_OUT
MDAT_IN
ISO_
MDAT_IN
PIN_MDAT_IN
ISO_
MCLK_OUT
PIN_MCLK_OUT
M
C
L
MCLK_OUT
MCLK_IN
ISO_KCLK_OUT
K
ISO_MCLK_IN
PIN_MCLK_IN
M_ISO
WAKE ON NON-
SPECIFC KEY
MOUSE
WAKE ON
SPEMSE
SPECIFC KEY
Note:
This figure is for illustration purposes only and not meant to imply specific implementation details.
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SCH3227/SCH3226/SCH3224/SCH3222
14.0 WATCHDOG TIMER
The SCH322x contains a Watchdog Timer (WDT). The Watchdog Time-out status bit may be mapped to an interrupt
through the WDT_CFG Runtime Register.
The SCH322x WDT has a programmable time-out ranging from 1 to 255 minutes with one minute resolution, or 1 to 255
seconds with 1 second resolution. The units of the WDT timeout value are selected via bit[7] of the WDT_TIMEOUT
register. The WDT time-out value is set through the WDT_VAL Runtime register. Setting the WDT_VAL register to 0x00
disables the WDT function (this is its power on default). Setting the WDT_VAL to any other non-zero value will cause
the WDT to reload and begin counting down from the value loaded. When the WDT count value reaches zero the
counter stops and sets the Watchdog time-out status bit in the WDT_CTRL Runtime register.
Note:
Regardless of the current state of the WDT, the WDT time-out status bit can be directly set or cleared by
the Host CPU.
Note 14-1
To set the WDT for time X minutes, the value of X+1 minutes must be programmed. To set the WDT
for X seconds, the value of X+1 seconds must be programmed.
Two system events can reset the WDT: a Keyboard Interrupt or a Mouse Interrupt. The effect on the WDT for each of
these system events may be individually enabled or disabled through bits in the WDT_CFG Runtime register. When a
system event is enabled through the WDT_CFG register, the occurrence of that event will cause the WDT to reload the
value stored in WDT_VAL and reset the WDT time-out status bit if set. If both system events are disabled, the WDT_VAL
register is not re-loaded.
The Watchdog Timer may be configured to generate an interrupt on the rising edge of the Time-out status bit. The WDT
interrupt is mapped to an interrupt channel through the WDT_CFG Runtime register. When mapped to an interrupt the
interrupt request pin reflects the value of the WDT time-out status bit.
The host may force a Watchdog time-out to occur by writing a "1" to bit 2 of the WDT_CTRL (Force WD Time-out) Run-
time register. Writing a "1" to this bit forces the WDT count value to zero and sets bit 0 of the WDT_CTRL (Watchdog
Status). Bit 2 of the WDT_CTRL is self-clearing.
See the Section 24.0, "Runtime Register" for description of these registers.
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15.0 PROGRAMMABLE CLOCK OUTPUT
A CLK_OUT pin is available on the SCH322x. This will output a programmable frequency between 0.5 Hz to 16 Hz, and
have the following characteristics:
• Must run when Vcc if off - could use 32Khz clock
• Accuracy is not an issue
• CLOCK_OUT register at offset 3Ch in runtime registers with the following programming:
- Options for 0.25, 0.5, 1, 2, 4, 8, or 16 Hz
APPLICATION NOTE: No attempt has been made to synchronize the clock. As a result, glitches will occur on the
clock output when different frequencies are selected.
CLOCK Output
Control Register
3C
Bit[0] Enable
1= Output Enabled
0= Disable Clock output
Bit[3:1] Frequency Select
000= 0.25 Hz
(R/W)
VTR POR = 0x00
001= 0.50 Hz
010= 1.00 Hz
011= 2.00 Hz
100= 4.00 Hz
101= 8.00 Hz
110= 16 hz
111 = reserved
Bit[7:4] Reserved
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16.0 RESET GENERATION
The SCH322x family has a Reset Generator with the following characteristics:
• output is open-drain PWRGD_OUT
• 3.3V, 3.3V VTR and 5V voltage trip monitors are ALWAYS a source for the PWRGD_OUT.
• An internal version of nTHERMTRIP signal from the HW monitor block, can be a source of PWRGD_OUT, select-
able via a bit in the RESGEN register.
• A 1.6 sec watchdog timer can be a source for PWRGD_OUT, selectable via a bit in the RESGEN register. See
Section 16.1, "Watchdog Timer for Resets on VCC_POR," on page 102 for more details.
• The output pulse width is selectable via a strap option (see Note 2-15 on page 29), between 200 msec (default) or
500 msec. This pulse is applied to PWRGD_OUT. The RESGEN strap is sampled at the deaserting edge of
PCIRST# or VCC POR. The following table summarizes the strap option programmming.
TABLE 16-1: RESGEN STRAP OPTION
RESGEN
Delay
1
0
200 msec delay (approximate) default
500 msec delay (approximate)
The programming for the RESGEN function is in the REGEN register, runtime register offset 1Dh as shown in Table 16-
2.
TABLE 16-2: RESGEN PROGRAMMING
RESGEN
1Dh
Reset Generator
Bit[0] WDT2_EN: Enable Watchdog timer Generation / Select
0= WDT Enabled - Source for PWRGD_OUT (Default)
1= WDT Disabled - Not source for PWRGD_OUT
default = 00h
(R/W)
Bit[1] ThermTrip Source Select
0 = Thermtrip not source for PWRGD_OUT ((Default)
1 = Thermtrip source for PWRGD_OUT
Bit[2] WDT2_CTL: WDT input bit
Bit[7:3] Reserved
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FIGURE 16-1:
RESET GENERATION CIRCUIT (FOR ILLUSTRATIVE PURPOSES ONLY)
Threshold
3.3VTR
Comparator
and
Reset Logic
RSMRST#
approx 140 msec Delay
RESGEN
RESGEN
Bit[2]
Bit[0]
WDT2_CTL
WDT2_EN
Threshold1
3.3VCC
WDT
(125
msec)
Comparator
VCC_PORB
and
RESET#
Reset Logic
PWRGD_OUT
Threshold2
Comparator
and
Reset Logic
Strap = 1: 200 msec Delay
Strap = 0: 500 msec Delay
(Delays are approximate)
RESET#
+5V_IN
RESGEN Bit[1]
THERMTRIP
SEL
PS_ON#
Held '1' internally if pin is not present
or is not configured for this function.
Internal THERMTRIP#
RESETB
CLKI32
Debounce
PWROK
nFPRST
PWRGD_PS
16.1 Watchdog Timer for Resets on VCC_POR
The current WDT implementation resets after a VCC_POR, and does not begin counting until after WDT2_CTL bit is
toggled. The current operation of the RESGEN watchdog timer is as follows:
1. Feature enable/disable via a bit in a control register, accessible from the LPC. When enabled, the RESGEN WDT
output is selected as a source for the PWRGD_OUT signal.
2. Watchdog input bit in a the RESGEN register, WDT2_CTL, reset to 0 via VCC_POR, accessible from the LPC.
See Table 16-3.
3. The counter is reset by VCC_POR. The counter will remain reset as long as VCC_POR is active.
4. Counter will start when the following conditions are met:
a) VCC_POR is released AND
b) The WDT2_CTL bit is toggled from 0 to 1
5. If the host toggles the WDT2_CTL bit in the RESGEN control register, then the counter is reset to 1.6 seconds
and begins to count.
6. If the host does not toggle the WDT2_CTL bit in the RESGEN register by writing a 0 followed by a 1, before the
WDT has timed out, a 100 msec pulse is output.
7. After a timeout has occurred, a new timeout cycle does not begin until the host toggles the WDT2_CTL bit in
RESGEN register, by writing a 0 followed by a 1. This causes the counter to be reset to 1.6 seconds and begins
to count again.
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TABLE 16-3: WDT OPERATION FOLLOWING VCC_POR OR WDT2_CTL WRITING
WDT2_CTL
VCC_PORB
RST_WDT2B
Counter Reset
Condition
x
0
1
x
Yes
No
Power On
0
1
State after VCC_PORB.
Counter starts Counting
0->1
1
1
Yes
Write 1 to WDT2_CTL.
Counter reset and starts
counting.
1->0
x
1
1
1
0
No
Write 0 to WDT2_CTL. No
affect - counter running.
Yes
Counter timeout under
normal conditions.
16.2 Voltage Scaling and Reset Generator Tolerances
The 5V supply is scaled internally. The input resistance is 20kohms (min). The voltage trip point is 4.45V (nominal) with
a tolerance of 0.15V (range: 4.3V-4.6V).
For the 3.3V VTR and 3.3V supplies, the voltage trip point is 2.8V (nominal) with a tolerance of ±0.1V (range: 2.7V-2.9V).
Refer to FIGURE 16-1: on page 102.
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17.0 BUFFERED PCI OUTPUTS
17.1 Buffered PCI Outputs Interface
The SCH322x family devices provide three software controlled PCIRST# outputs and one buffered IDE Reset.
Table 17-1 describes the interface.
TABLE 17-1: BUFFERED PCI OUTPUTS INTERFACE
Name
Buffer
PCI_I
Power Well
Description
PCI_RESET#
nIDE_RSTDRV
nPCIRST1
VCC
VCC
VCC
VCC
VCC
PCI Reset Input
OD4
IDE Reset Output
O8/OD8
O8/OD8
O4/OD4
Buffered PCI Reset Output
Buffered PCI Reset Output
Buffered PCI Reset Output
nPCIRST2
nPCIRST3
17.1.1
IDE RESET OUTPUT
nIDE_RSTDRV is an open drain buffered copy of PCI_RESET#. This signal requires an external 1Kpull-up to VCC
or 5V. This pin is an output only pin which floats when VCC=0. The pin function’s default state on VTR POR is the
nIDE_RST function; however the pin function can be programmed to the a GPO pin function by bit 2 in its GPIO control
register.
The nIDE_RSTDRV output has a programmable forced reset. The software control of the programmable forced reset
function is located in the GP4 GPIO Data register. When the GP44 bit (bit 4) is set, the nIDE_RSTDRV output follows
the PCI_RESET# input; this is the default state on VTR POR. When the GP44 bit is cleared, the nIDE_RSTDRV output
stays low.
See GP44 and GP4 for Runtime Register Description (Section 24.0, "Runtime Register," on page 213).
TABLE 17-2: NIDE_RSTDRV TRUTH TABLE
PCI_RESET# (Input)
nIDE_RSTDRV (Output)
0
1
0
Hi-Z
TABLE 17-3: NIDE_RSTDRV TIMING
Name
Tf
Description
MIN
TYP
MAX
15
Units
nIDE_RSTDRV high to low fall time. Measured form 90% to
10%
ns
ns
Tpropf
nIDE_RSTDRV high to low propagation time. Measured from
PCI_RESET# to nIDE_RSTDRV.
22
CO
CL
Output Capacitance
Load Capacitance
25
40
pF
pF
17.1.2
NPCIRSTX OUTPUT LOGIC
The nPCIRST1, nPCIRST2, and nPCIRST3 outputs are 3.3V balance buffer push-pull buffered copies of PCI_RESET#
input. Each pin function’s default state on VTR POR is the nPCIRSTx function; however, the pin function can be pro-
grammed to the a GPO pin (output only) function by bit 2 in the corresponding GPIO control register (GP45, GP46,
GP47).
Each nPCIRSTx output has a programmable force reset. The software control of the programmable forced reset func-
tion is located in the GP4 GPIO Data register. When the corresponding (GP45, GP46 GP47) bit in the GP4 GPIO Data
register is set, the nPCIRSTx output follows the PCI_RESET# input; this is the default state on VTR POR. When the
corresponding (GP45, GP46, GP47) bit in the GP4 GPIO Data register is cleared, the nPCIRSTx output stays low.
See GP4 for Runtime Register Description.
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When the VTR power is applied, VCC is powered down, and the GPIO control register’s contents are default, the
nPCIRSTx pin output is low.
The Figure 17-1 illustrates the nPCIRSTx function. The figure is for illustration purposes only and in not intended to sug-
gest specific implementation details.
FIGURE 17-1:
NPCIRSTX LOGIC
PCI_RESET#
PCI_I(Vcc)
This signal is 0
when VCC=0
nPCIRSTx
VTR
VTR
One Bit in the
GP4
GPIO DATA
Default = 1 on
VTR POR
Internal VCC
active high
power good
signal
Note: This figure is for illustration purposes only and not meant to imply specific implementation dertails
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18.0 POWER CONTROL FEATURES
The SCH322x family devices are able to turn on the power supply when the power button located on the PC chassis is
pressed, when the power button located on the keyboard is pressed, or when recovering from a power failure. The sig-
nals used to support these features are:
• PB_IN#
• PB_OUT#
• SLP_Sx#
• PS_ON#
Table 18-1 and Figure 18-1 describe the interface and connectivity of the following Power Control Features:
1. Front Panel Reset with Input Debounce, Power Supply Gate, and Powergood Output Signal Generation
2. AC Recovery Circuit
3. Keyboard Wake on Mouse.
4. SLP_Sx# PME wakeup
TABLE 18-1: POWER CONTROL INTERFACE
Name
Direction
Input
Description
PB_IN#
Power Button Input
Power Good Output
Power Supply On output
From south bridge
PB_OUT#
PS_ON#
Output
Output
Input
SLP_SX#
PWRGD_PS
nFPRST
Input
Power Good Input from Power Supply
Reset Input from Front Panel
Input
PWRGD_OUT
nIO_PME
Output
Output
Power Good Output – Open Drain
Power Management Event Output signal allows this device to request
wakeup.
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FIGURE 18-1:
Power Control Block Diagram
Pulse Width >
0.5 sec.
Wake On
nIO_PME Wakeup
Key-
board
Con-
Specific Key
PME_EN6
KB_PB_STS
SPEKEY
(Vbat)
troller
combina-
torial
nIO_PME
PB_IN#
logic
PME_STS6
(Sticky bits)
(VTR)
Other Sx
wake up sources
Keyboard
Controller w/
modified logic for
Keyboard Power
Button
PB_OUT# Control Logic
Wake On
Specific Key
KB_EN
PB_OUT#
PB_IN#
PB_EN
PFR_EN
Power Failure Recovery Logic
APF Bit[0]
APF Bit[1]
Pulse Width > 0.5 sec
0=Off
1=On
SET
CLR
D
Q
Q
L
Previous State2
VTR PWR_GD
Min 1 sec delay
Delay
Sampled PS_ON# Value
(battery powered)
0=OFF, 1=ON
Power Supply On Logic
SLP_Sx#
PS_ON#
Other Reset
Generator Sources
nFPRST
debounce
ckt
PWRGD_OUT
Reset
Generation
Logic
PWROK
(VTR)
PWRGD_PS
Note 1: The PS_ON# level will be latched in the Previous State bit located in the Power Recovery Register on the
falling edge of VTR PWR_GD, VCC PWR_GD, or PWR_OK, which ever comes first. If mode 1 is enabled,
this bit will be used to determine the Previous State.
2: The Previous state is equal to the Previous State bit located in the Power Recover Register, if configured
for Mode 1. If mode 2 is enabled, the Previous state is determined by one of the bits in the 8-bit shift register,
which is stored in the PS_ON register located in the Runtime Register block at 4Ah. The bit selected in mode
2 is determined by the state of the PS_ON# Previous State Select bits located in Runtime Register 53h.
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18.1 nIO_PME Pin use in Power Control
The nIO_PME signal can be used to control the state of the power supply. The nIO_PME signal will be asserted when
a PME event occurs and the PME logic is enabled. The following is a summary of the Power control PME events (See
Figure 18-1):
1. PB_IN# input signal assertion.
2. When the Wake On Specific Key Logic detects the programmed keyboard event it will generate a wake event
(KB_PB_STS).
3. Upon returning from a power failure.
Each PME wake event sets a status bit in the PME_STS6 register. If the corresponding enable bit in the PME_EN6 reg-
ister is set then the nIO_PME pin will be asserted. The enable bits in the PME_EN6 register default to set and are Vbat
powered. Refer to Section 13.0, "PME Support," on page 94 for description of the PME support for this PME event.
18.2 Front Panel Reset
The inputs, PWRGD_PS and nFPRST have hysteresis and are internally pulled to VTR through a 30uA resistor. The
nFPRST is debounced internally.
The nFPRST input has internal debounce circuitry that is valid on both edges for at least 16ms before the output is
changed. The 32.768kHz is used to meet the timing requirement. See Figure 18-2 for nFPRST debounce timing.
The actual minimum debounce time is 15.8msec
The 32.768 kHz trickle input must be connected to supply the clock signal for the nFPRST debounce circuitry. The
SCH322x has a legacy feature which is incompatible with use of the nFPRST input signal. An internal 32kHz clock
source derived from the 14MHz (VCC powered) can be selected when the external 32kHz clock is not connected.
APPLICATION NOTE: The 32.768 kHz trickle input must be connected to supply the clock signal for the nFPRST
debounce circuitry.
TABLE 18-2: INTERNAL PWROK TRUTH TABLE
Inputs
Output
nFPRST
PWRGD_PS
Internal PWROK
0
0
1
1
0
1
0
1
0
0
0
1
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FIGURE 18-2:
NFPRST DEBOUNCE TIMING
Release
Press
nFPRST
(before
debounce)
15.8msec
min
15.8msec
min
Internal nFPRST
(after debounce)
The next
nFPRST press
will be detected
starting here
18.3 A/C Power Failure Recovery Control
The Power Failure Recovery Control logic, which is powered by VTR, is used to return a system to a pre-defined state
after a power failure (VTR=0V). The Power Control Register, which is powered by Vbat, contains two bits defined as
APF (After Power Failure). These bits are used to determine if the power supply should be powered on, powered off, or
set to the previous power state before VTR was removed as shown in Table 18-3.
Power Failure Recovery registers that are required to retain their state through a power failure are powered by Vbat.
Two modes may be used to determine the previous state:
Mode 1: (Suggested if PWR_OK is selected& enabled), which is enabled when Bit[3] PS_ON# sampling is disabled,
latches the current value of the PS_ON# pin when VCC, VTR, or PWR_OK (if enabled) transition to the inactive state,
whichever comes first. This value is latched into Bit[4] Previous State Bit located in the Power Recovery Register located
at offset 49h and is used to determine the state of the PS_ON# pin when VTR becomes active.
Mode 2 is enabled when Bit[3] PS_ON# sampling is enabled. To determine the previous power state, the PS_ON# pin
is sampled every 0.5 seconds while VTR is greater than ~2.2Volts. This sample is inserted into a battery powered 8-bit
shift register. The hardware will select a bit from the shift register depending on the value of the PS_ON# Previous State
Select bits located in the Runtime Register block at offset 53h to determine the state of the PS_ON# pin when VTR
becomes active. The value in the 8-bit shift register is latched into the PS_ON Register at offset 4Ah in the Runtime
Register block after VTR power is returned to the system, but before the internal shift register is cleared and activated.
The PS_ON Register is a battery powered register that is only reset on a Vbat POR.
Note 1: In Mode 2, when VTR falls below ~2.2Volts the current value of the PS_ON# pin will be latched into Bit [4]
Previous State Bit located in the Power Recovery Register at offset 49h. This bit will not be used by hard-
ware, but may be read by software to determine the state of the PS_ON# pin when the power failure
occurred.
2: The time selected for the PS_ON# Previous State bits should be greater than or equal to the time it takes
for Resume Reset to go inactive to the time VTR is less than ~2.2 Volts.
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If a power failure occurs and the Power Supply should be in the ON state, the Power Failure Recovery logic will assert
the PB_OUT# pin active low for a minimum pulse width of 0.5sec when VTR powers on. If the Power Supply should
remain off, the Power Failure Recovery logic will have no effect on the PB_OUT# pin. The following table defines the
possible states of PB_OUT# after a power failure for each configuration of the APF bits.
TABLE 18-3: DEFINITION OF APF BITS
AFTERG3 Bit
APF[1:0]
Definition of APF Bits
PB_OUT#
(Located in ICH)
00
11
Power Supply OFF
1
––––
––––
01
10
Power Supply ON
1
1
Power Supply set to Previous
State (ON)
10
Power Supply set to Previous
State (OFF)
1
Note:
It is a requirement that the AFTERG3 bit located in the ICH controller be programmed to 1 for this AC
Recovery logic to be used.
18.3.1
PB_OUT# AND PS_ON#
The PB_OUT# and PS_ON# signals are used to control the state of the power supply.
The PB_OUT# signal will be asserted low if the PB_IN# is asserted and enabled, if the KB_IN# is asserted and enabled,
or if recovering from a power failure and the power supply should be turned on. Refer to Figure 18-1. The following is a
summary of these signals:
1. If the PB_IN# signal is enabled and asserted low, the PB_OUT# signal should be held low for as long as the
PB_IN# signal is held low.
2. If the internal KB_PB_STS# signal (see Figure 14) is asserted low, the PB_OUT# signal is held low for as long
as the KB_PB_STS# signal is held low.
3. If returning from a power failure and the power supply need to be turned on, a minimum of a ~0.5sec pulse is
asserted on the PB_OUT# pin.
Note:
This pulse width is less than 4 seconds, since a 4 second pulse width signifies a power button override
event.
The PS_ON# signal is the inverse of the SLP_Sx# input signal. This signal goes directly to the Power Supply to turn the
supply on or off.
The SCH#11X indirectly controls the PS_ON# signal by asserting the PB_OUT#. PB_OUT# will be interpreted by an
external device (i.e., ICH controller), which will use this information to control the SLP_Sx# signal.
Note:
Two modes have been added to save the state of the PS_ON# pin in the event of a power failure. This
allows the system to recover from a power failure. See Section 18.3, "A/C Power Failure Recovery Con-
trol," on page 109.
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18.3.2
POWER SUPPLY TIMING DIAGRAMS
The following diagrams show the relative timing for the I/O pins associated with the Power Control logic. These are con-
ceptual diagrams to show the flow of events.
FIGURE 18-3:
POWER SUPPLY DURING NORMAL OPERATION
PB_IN#
PB_OUT#
SLP_Sx#
PS_ON#
VCC
VTR (ON)
FIGURE 18-4:
POWER SUPPLY AFTER POWER FAILURE (RETURN TO OFF)
Power Failure
PB_IN# (high)
PB_OUT# (high)
SLP_Sx# (Low)
PS_ON# (high)
VCC(Off)
VTR
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FIGURE 18-5:
POWER SUPPLY AFTER POWER FAILURE (RETURN TO ON)
Power Failure
PB_IN#
PB_OUT#
SLP_Sx#
PS_ON#
VCC
VTR
18.4 Resume Reset Signal Generation
nRSMRST signal is the reset output for the ICH resume well. This signal is used as a power on reset signal for the ICH.
The SCH322x detects when VTR voltage raises above VTRIP and provides a delay before generating the rising edge of
nRSMRST. See Section 27.9, "Resume Reset Signal Generation," on page 275 for a detailed description of how the
nRSMRST signal is generated.
18.5 Keyboard Power Button
The SCH322x has logic to detect a keyboard make/break scan codes that may be used for wakeup (PME generation).
The scan codes are programmed in the Keyboard Scan Code Registers, located in the runtime register block, from off-
set 0x5F to 0x63 from the base address located in the primary base I/O address in Logical Device A. These registers
are powered by Vbat and are reset on a Vbat POR.
The following sections will describe the format of the keyboard data, the methods that may be used to decode the make
codes, and the methods that may be used to decode the break codes.
The Wake on Specific Key Code feature is enabled for the assertion of the nIO_PME signal when in SX power state or
below.
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18.5.1
KEYBOARD DATA FORMAT
Data transmissions from the keyboard consist of an 11-bit serial data stream. A logic 1 is sent at an active high level.
The following table shows the functions of the bits.
Bit
Function
1
2
Start bit (always 0)
Data bit 0 (least significant bit)
Data bit 1
3
4
Data bit 2
5
Data bit 3
6
Data bit 4
7
Data bit 5
8
Data bit 6
9
Data bit 7 (most significant bit)
Parity bit (odd parity)
Stop Bit (always 1)
10
11
The process to find a match for the scan code stored in the Keyboard Scan Code register meets the timing constraints
as defined by the IBM Personal System/2™ Model 50 and 60 Technical Reference, dated April 1987. The timing for the
keyboard clock and data signals are shown in Section 27.0, "Timing Diagrams," on page 260. (See Section 27.8, "Key-
board/Mouse Interface Timing," on page 274).
18.5.1.1
Method for Receiving Data is as Follows
The wake on specific key logic snoops the keyboard interface for a particular incoming scan code, which is used to wake
the system through a PME event. These scan codes may be comprised of a single byte or multiple bytes. To determine
when the first key code is being received, the wake on specific key logic begins sampling the data at the first falling edge
of the keyboard clock for the start bit. The data is sampled on each falling edge of the clock. The hardware decodes the
byte received and determines if it is valid (i.e., no parity error). Valid scan code bytes received are compared to the pro-
grammed scan code as determined by bits [3:2] SPEKEY Scan Code Runtime register located at offset 0x64. If the scan
code(s) received matches the value(s) programmed in the Keyboard Scan Code registers then a wake on specific key
status event has occurred. The wake on specific key status event is mapped to the PME and Power Button logic.
The snooping logic always checks the incoming data byte for a parity error. The hardware samples the parity bit and
checks that the 8 data bits plus the parity bit always have an odd number of 1’s (odd parity). If a parity error is detected
the state machine used to decode the incoming scan code is reset and begins looking for the first byte in the keyboard
scan code sequence.
This process is repeated until a match is found. See Section 18.5.2, "System for Decoding Scan Code Make Bytes
Received from the Keyboard," on page 114 and Section 18.5.3, "System for Decoding Scan Code Break Bytes
Received from the Keyboard," on page 115.
If the scan code received matches the programmed make code stored in the Keyboard Scan Code registers and no
parity error is detected, then it is considered a match. When a match is found and if the stop bit is 1, a PME wake event
(KB_PB_STS-See Figure 18-1) will be generated within 100usec of the falling edge of clock 10 of the last byte of the
sequence. This wake event may be used to generate the assertion of the nIO_PME signal when in SX power state or
below.
The state machine will reset and repeat the process until it is shut off by setting the SPEKEY_EN bit to ‘1’.
The SPEKEY_EN bit at bit 1 of the register at 0xF0 in Logical Device A is used to control the “wake-on-specific feature.
This bit is used to turn the logic for this feature on and off. It will disable the 32kHz clock input to the logic. The logic will
draw no power when disabled. The bit is defined as follows:
0= “Wake on specific key” logic is on (default)
1= “Wake on specific key” logic is off
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The state machine used to snoop the incoming data from the keyboard is synchronized by the clock high and low time.
If the KCLK signal remains high or low for a nominal 125usec during the transmission of a byte, a timeout event is gen-
erated causing the snooping and scan code decoding logic to be reset, such that it will look for the first byte of the make
or break scan code.
18.5.1.2
Description Of SCAN 1 and SCAN 2
SCAN 1:
Many standard keyboards (PC/XT, MFII, etc.) generate scan 1 make and break codes per key press. These codes may
be generated as a single byte or multi-byte sequences. If a single byte is generated, the make code, which is used to
indicate when a key is pressed, is a value between 0h and 7Fh. The break code, which is used to indicate when a key
is released, is equal to the make code plus 80h (i.e. 80h Break Code FFh). If a multi-byte sequence is sent it will
send E0h before the make or break.
Example of Single Byte Scan 1: Make Code = 37h, Break Code=B7h
Example of Multi-byte Scan 1: Make Code = E0h 37h, Break Code = E0h B7h.
SCAN 2:
The scan 2 make and break codes used in AT and PS/2 keyboards, which are defined by the PC 8042 Keyboard Con-
troller, use the same scan code when a key is pressed and when the key is released. A reserved release code, 0xF0,
is sent by the keyboard immediately before the key specific portion of the scan code to indicate when that the key is
released.
Example of Single Byte Scan 2: Make Code = 37h, Break Code=F0h 37h
Example of Multi-byte Scan 2: Make Code = E0h 37h, Break Code = E0h F0h 37h.
18.5.2
SYSTEM FOR DECODING SCAN CODE MAKE BYTES RECEIVED FROM THE KEYBOARD
Bit [3:2] of the SPEKEY Scan Code register is used to determine if the hardware is required to detect a single byte make
code or a multi-byte make code. Table 18-4 summarizes how single byte and multi-byte scan codes are decoded.
FIGURE 18-6:
FIGURE 18-7:
SAMPLE SINGLE-BYTE MAKE CODE
Keyboard Scan Code - Make Byte 1
37h
SAMPLE MULTI-BYTE MAKE CODE
MSB
LSB
Keyboard Scan Code - Make Byte 1
E0h
Keyboard Scan Code - Make Byte 2
37h
Note:
In multi-byte scan codes the most significant byte (MSB) will be received first.
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TABLE 18-4: DECODING KEYBOARD SCAN CODE FOR MAKE CODE
SPEKEY Scan
Number of Bytes
in Make Code
Code
Description
Bit[3]
X
Bit[2]
0
1 byte
The wake on specific key logic will compare each valid data byte received
with the Keyboard Scan Code – Make Byte 1 located in the Runtime
Register block at offset 5Fh. If the data byte received matches the value
stored in the register, a wake on specific key status event will be
generated. This wake event may be used to generate the assertion of the
nIO_PME signal.
Note:
If the value programmed in Keyboard Scan Code – Make Byte 1
is 00h it is treated as a don’t care and any valid scan code being
compared to this byte will be a match.
X
1
2 byte
The wake on specific key logic compares each valid data byte received
with the value programmed in the Keyboard Scan Code – Make Byte 1
located in the Runtime Register block at offset 5Fh. If the data byte
received matches the value stored in the register, the hardware compares
the next byte received with the value programmed in the Keyboard Scan
Code – Make Byte 2 located in the Runtime Register block at offset 60h.
If the consecutive bytes received match the programmed values, a wake
on specific key status event is generated. If the values do not match, if a
parity error occurs, or if a timeout occurs, the state machine is reset and
the process is repeated. If a specific key status event is generated then it
may be used to generate the assertion of the nIO_PME signal.
Note:
If the value programmed in Keyboard Scan Code – Make Byte 1
or Keyboard Scan Code -Make Byte2 is 00h it is treated as a
don’t care and any valid scan code being compared to this byte
will be a match.
Note 1: X’ represents a don’t care.
2: By default, any time the KCLK signal is high or low for a nominal 125usec during the transmission of a byte
the scan code decode cycle will be reset and the next byte received will be treated as the first byte received
in the scan code byte sequence.
Once a valid make code is detected the wake on specific key logic will generate a KB_PB_STS wake event (see
Figure 18-1). This wake event may be used to generate the assertion of the nIO_PME signal when in SX power state
or below.
18.5.3
SYSTEM FOR DECODING SCAN CODE BREAK BYTES RECEIVED FROM THE KEYBOARD
To accommodate different keyboards, there are three options for determining when the wake on specific key logic deas-
serts the KB_PB_STS wake event (See in Figure 18-1) going to the sticky bits. Deassertion of the KB_PB_STS inter-
nally does not deassert the PME status bit.
The Keyboard Power Button Release bits may select these KB_PB_STS options. See Section 24.0, "Runtime Register,"
on page 213. A detailed description of each option is shown below.
Option 1 (00): De-assert KB_PB_STS 0.5sec after it is asserted.
This option allows the user to program any scan code into the Keyboard Scan Code – Make Byte Register(s). When a
valid scan code is received that matches the value programmed in the Keyboard Scan Code Register(s), a 0.5sec pulse
is generated on the KB_PB_STS wake event. Regardless of the state of the SPEKEY bits, no additional wake events
will no additional wake events will occur for 0.5sec.
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FIGURE 18-8:
Keyboard Input
KB_PB_STS
OPTION 1: KB_PB_STS WAKE EVENT FIXED PULSE WIDTH
Valid Scan Code
(1 or 2 bytes)
Scan Code
Pulse Width=0.5sec
Option 2 (01): De-assert KB_PB_STS after Scan Code Not Equal Programmed Make Code
This option may be used by keyboards that emit single byte or multi-byte make codes for each key pressed. When a
valid Scan Code is received that matches the value programmed in the Keyboard Scan Code – Make Byte Register(s),
the KB_PB_STS wake event signal will be held asserted low until another valid Scan Code is received that is not equal
to the programmed make code. Regardless of the state of the SPEKEY bits, no additional wake events will no additional
wake events will occur until another valid Scan Code is received that is not equal to the programmed make code.
FIGURE 18-9:
Keyboard Input
KB_PB_STS
Option 2: Assert KB_PB_STS Wake Event Until Scan Code
Not Programmed Make Code
Valid Scan Code=
Programmed Make
Code
Valid Scan Code Not =
Programmed Make Code
Invalid Scan Code
Pulse Width
Note 1: The Valid Scan Code may be 1 or 2 bytes depending on the SPEKEY ScanCode bits in the Runtime register
at offset 64h.
2: A Valid Scan Code for single byte codes means that no parity error exists. A Valid Scan Code for Multi-byte
Scan Codes requires that no parity error exists and that the first Byte received matches the value pro-
grammed in the Keyboard Scan Code – Make Byte 1 located in the Runtime Register block at offset 5Fh.
This value is typically E0h for Scan 1 and Scan 2 type keyboards. (Example: The ACPI power scan 2 make
code is E0h, 37h) Section 18.5.1.2, "Description Of SCAN 1 and SCAN 2," on page 114.
Option 3 (10): De-assert KB_PB_STS after Scan Code Equal Break Code
This option may be used with single byte and multi-byte scan 1 and scan 2 type keyboards. The break code can be
configured for a specific break code or for any valid break code.
the KB_PB_STS wake event signal will be held asserted low until a valid break code is detected. The break code can
be configured for a specific break code or for any valid break code. Regardless of the state of the SPEKEY bits, no addi-
tional wake events will occur until another until a valid break code is detected.
Note:
Table 18-5 defines how the scan code will be decoded for the Break Code. Once a valid break code is
detected, the keyboard power button event will be de-asserted as shown in Figure 18-10.
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FIGURE 18-10:
OPTION 3: DE-ASSERT KB_PB_STS WHEN SCAN CODE EQUAL BREAK CODE.
Valid Scan Code =
Valid Scan Code=
Programmed Make
Code
Keyboard Input
Programmed Break
Code
Invalid Scan Code
Pulse Width
KB_PB_STS
Note:
The SPEKEY ScanCode bits are located in the register Keyboard PWRBTN/SPEKEY located at offset 64h.
TABLE 18-5: DECODING KEYBOARD SCAN CODE FOR BREAK CODE
SPEKEY Scan
Number of
Scan
Code
Code
Bytes in Break
Code
Description
Bit[3] Bit[2]
0
0
0
1
Scan 1 1 Byte
Scan 1 2 Bytes
The wake on specific key logic will compare each valid data byte
received with the Keyboard Scan Code – Break Byte 1 located in
the Runtime Register block at offset 61h. If the data byte received
matches the value stored in the register, the wake on specific key
status event (KB_PB_STS) will be de-asserted. Deassertion of
the KB_PB_STS internally does not deasset the PME status bit.
The wake on specific key logic will compare each valid data byte
received with the Keyboard Scan Code – Break Byte 1 located in
the Runtime Register block at offset 61h. If the data byte received
matches the value stored in the register, the next byte received
will be compared to Keyboard Scan Code – Break Byte 2 located
in the Runtime Register block at offset 62h. If this byte is a valid
scan code and it matches the value programmed, the wake on
specific key status (KB_PB_STS) will be de-asserted.
Deassertion of the KB_PB_STS internally does not deasset the
PME status bit.
If the values do not match, if a parity error occurs, or if a timeout
occurs, the state machine will be reset and repeat the process.
1
0
Scan 2 2 Bytes
The wake on specific key logic will compare each valid data byte
received with the Keyboard Scan Code – Break Byte 1 located in
the Runtime Register block at offset 61h. If the data byte received
matches the value stored in the register, the next byte received
will be compared to Keyboard Scan Code – Break Byte 2 located
in the Runtime Register block at offset 62h. If this byte is a valid
scan code and it matches the value programmed, the wake on
specific key status event (KB_PB_STS) will be de-asserted.
Deassertion of the KB_PB_STS internally does not deasset the
PME status bit.
If the values do not match, if a parity error occurs, or if a timeout
occurs, the state machine will be reset and repeat the process.
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TABLE 18-5: DECODING KEYBOARD SCAN CODE FOR BREAK CODE (CONTINUED)
SPEKEY Scan
Number of
Scan
Code
Code
Bytes in Break
Code
Description
Bit[3] Bit[2]
1
1
Scan 2 3 Bytes
The wake on specific key logic will compare each valid data byte
received with the Keyboard Scan Code – Break Byte 1 located in
the Runtime Register block at offset 61h. If the data byte received
matches the value stored in the register, the next byte received
will be compared to Keyboard Scan Code – Break Byte 2 located
in the Runtime Register block at offset 62h. If the data byte
received matches the value stored in the register, the next byte
received will be compared to Keyboard Scan Code – Break Byte
3 located in the Runtime Register block at offset 63h. If this byte
is a valid scan code and it matches the value (KB_PB_STS) will
be de-asserted. Deassertion of the KB_PB_STS internally does
not deasset the PME status bit. If the values do not match, if a
parity error occurs, or if a timeout occurs, the state machine will
be reset and repeat the process.
Note:
To de-assert wake on specific key status event (KB_PB_STS) on any valid break key the register contain-
ing the LSB of the break code should be programmed to 00h. If a Keyboard Scan Code – Break Byte reg-
ister is programmed to 00h then any valid scan code will be a match. The value 00h is treated as a Don’t
Care.
18.6 Wake on Specific Mouse Event
The device can generate SX wake events (where SX is the sleep state input) based on detection of specific Mouse but-
ton clicks on a Mouse connected to the Mouse port interface (MDAT and MCLK pins). The following specific Mouse
events can be used for wake-up events:
1. Any button click (left/right/middle) or any movement
2. Any one click of left/right/middle button
3. one click of left button
4. one click of right button
5. two times click of left button
6. two times click of right button
In addition to the Idle detection logic there is Start Bit Time-out logic which detects any time MCLK stays high for more
that 115-145us.
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19.0 LOW BATTERY DETECTION LOGIC
The low battery detection logic monitors the battery voltage to detect if this voltage drops below 2.2V and/or 1.2V. If the
device is powered by Vbat only and the battery voltage is below approximately 1.2V, a VBAT POR will occur upon a
VTR POR. If the device detects the battery voltage is below approximately 2.2V while it is powered by Vbat only or VTR
(VCC=0V) the LOW_BAT PME and SMI Status bits will be set upon a VCC POR. When the external diode voltage drop
is taken into account, these numbers become 1.5V and 2.5V, respectively.
The LOW_BAT PME event is indicated and enabled via the appropriate PME registers.
The LOW_BAT SMI event is indicated and enabled via the SMI_STS1 and SMI_EN1 registers. See the Section 24.0,
"Runtime Register," on page 213 section for a description of these registers.
The following figure illustrates external battery circuit.
FIGURE 19-1:
EXTERNAL BATTERY CIRCUIT
Battery
ICH
VBAT
SCH322x
VBATLOW~2.2V
Note that the battery voltage of 2.2V nominal is at the VBAT pin of the device, not at the source.
19.1 VBAT POR
When VBAT drops below approximately 1.2V while both VTR and VCC are off, a VBAT POR will occur upon a VTR POR.
The LOW_BAT PME and SMI Status bits is set to ‘1’ upon a VBAT POR. Since the PME enable bit is not battery backed
up and is cleared on VTR POR, the VBAT POR event is not a wakeup event. When VCC returns, if the PME or SMI
enable bit (and other associated enable bits) are set, then the corresponding event will be generated.
19.2 Low Battery
19.2.1
UNDER BATTERY POWER
If the battery voltage drops below approximately 2.2V under battery power (VTR and VCC off) then the LOW_BAT PME
and SMI Status bits will be set upon a VCC POR. This is due to the fact that the LOW_BAT event signal is only active
upon a VCC POR, and therefore the low battery event is not a wakeup event. When VCC returns, if the PME or SMI
enable bit (and other associated enable bits) are set, then a corresponding event will be generated.
19.2.2
UNDER VTR POWER
If the battery voltage drops below approximately 2.2V under VTR power (VCC off) then the LOW_BAT PME and SMI
Status bits will be set upon a VCC POR. The corresponding enable bit (and other associated enable bits) must be set
to generate a PME or an SMI.
If the PME enable bit (and other associated enable bits) were set prior to VCC going away, then the low battery event
will generate a PME when VCC becomes active again. It will not generate a PME under VTR power and will not cause
a wakeup event.
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If the SMI enable bit (and other associated enable bits) were set prior to VCC going away, then the low battery event
will generate an SMI when VCC becomes active again.
19.2.3
UNDER VCC POWER
The LOW_BAT PME and SMI bits are not set when the part is under VCC power. They are only set upon a VCC POR.
See Section 19.2.2, "Under VTR Power".
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20.0 BATTERY BACKED SECURITY KEY REGISTER
Located at the Secondary Base I/O Address of Logical Device A is a 32 byte CMOS memory register dedicated to secu-
rity key storage. This security key register is battery powered and has the option to be read protected, write protected,
and lockable. The Secondary Base I/O Address is programmable at offsets 0x62 and 0x63. See Table 20-1, "Security
Key Register Summary" is a complete list of the Security Key registers.
TABLE 20-1: SECURITY KEY REGISTER SUMMARY
Register Offset (HEX)
VBAT POR
Register
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Security Key Byte 0
Security Key Byte 1
Security Key Byte 2
Security Key Byte 3
Security Key Byte 4
Security Key Byte 5
Security Key Byte 6
Security Key Byte 7
Security Key Byte 8
Security Key Byte 9
Security Key Byte 10
Security Key Byte 11
Security Key Byte 12
Security Key Byte 13
Security Key Byte 14
Security Key Byte 15
Security Key Byte 16
Security Key Byte 17
Security Key Byte 18
Security Key Byte 19
Security Key Byte 20
Security Key Byte 21
Security Key Byte 22
Security Key Byte 23
Security Key Byte 24
Security Key Byte 25
Security Key Byte 26
Security Key Byte 27
Security Key Byte 28
Security Key Byte 29
Security Key Byte 30
Security Key Byte 31
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Access to the Security Key register block is controlled by bits [2:1] of the Security Key Control (SKC) Register located
in the Configuration Register block, Logical Device A, at offset 0xF2. The following table summarizes the function of
these bits.
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TABLE 20-2: DESCRIPTION OF SECURITY KEY CONTROL (SKC) REGISTER BITS[2:1]
Bit[2]
(Write-Lock)
Bit[1]
(Read-Lock)
Description
0
0
1
1
0
1
0
1
Security Key Bytes[31:0] are read/write registers
Security Key Bytes[31:0] are Write-Only registers
Security Key Bytes[31:0] are Read-Only registers
Security Key Bytes[31:0] are not accessible. All reads/write
access is denied.
Note:
When Bit[1] (Read-Lock) is ‘1’ all reads to this register block will return 00h.
• As an added layer of protection, bit [0] SKC Register Lock bit has been added to the Security Key Control Regis-
ter. This lock bit is used to block write access to the Write-Lock and Read-Lock bits defined in the table above.
Once this bit is set it can only be cleared by a VTR POR, VCC POR, and PCI Reset.
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21.0 TEMPERATURE MONITORING AND FAN CONTROL
The Hardware Monitoring (HWM) block contains the temperature monitoring and fan control functions. The following
sub-sections describe the HWM block features.
Note:
The SCH3222 device does not bring out these pins, and therefore the HWM block and this chapter are
irrelevant to it.
21.1 Block Diagram
FIGURE 21-1:
HWM BLOCK EMBEDDED IN SCH322X
HWM BLOCK
Analog
Remote1+
Remote1-
Remote2+
Remote2-
SIO LOGIC
Index
Data
Runtime
Reg's
(Logical
Device A)
HWM Registers
Digital
LPC
Interface
Block
LPC Interface
THERMTRIP
Monitoring Logic
PWM1
PWM2
PWM3
Fan Control &
Monitoring
TACH1
TACH2
TACH3
Interrupt
Generation Logic
nHWM_INT
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21.2 HWM Interface
The SCH322x HWM block registers are accessed through an index and data register located at offset 70h and 71h,
respectively, from the address programmed in the Base I/O Address in Logical Device A (also referred to as the Runtime
Register set).
FIGURE 21-2:
HWM REGISTER ACCESS
00h
Logical Device 0Ah
Runtime Registers
base + 70h
base + 71h
HWM_Index
HWM_Data
hwm registers
FFh
21.3 Power Supply
The HWM block is powered by standby power, HVTR, to retain the register settings during a main power (sleep) cycle.
The HWM block does not operate when VCC=0 and HVTR is on. In this case, the H/W Monitoring logic will be held in
reset and no monitoring or fan control will be provided. Following a VCC POR, the H/W monitoring logic will begin to
operate based on programmed parameters and limits.
The fan tachometer input pins are protected against floating inputs and the PWM output pins are held low when VCC=0.
Note:
The PWM pins will be forced to “spinup” (if enabled) when PWRGD_PS goes active. See “PWM Fan Speed
Control” on page 134.
21.4 Resetting the SCH322x Hardware Monitor Block
21.4.1
VTR POWER-ON RESET
All the registers in the Hardware Monitor Block, except the reading registers, reset to a default value when VTR power
is applied to the block. The default state of the register is shown in the Register Summary Table. The default state of
Reading Registers are not shown because these registers have indeterminate power on values.
Note:
Usually the first action after power up is to write limits into the Limit Registers.
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21.4.2
VCC POWER-ON RESET
The PWRGD_PS signal is used by the hardware-monitoring block to determine when a VCC POR has occurred. The
PWRGD_PS signal indicates that the VCC power supply is within operation range and the 14.318MHz clock source is
valid.
Note:
Throughout the description of the hardware monitoring block VCC POR and PWRGD_PS are used inter-
changeably, since the PWRGD_PS is used to generate a VCC POR.
All the HWM registers will retain their value through a sleep cycle unless otherwise specified. If a VCC POR is preceded
by a VTR POR the registers will be reset to their default values. The following is a list of the registers and bits that are
reset to their default values following a VCC POR.
• FANTACH1 LSB register at offset 28h
• FANTACH1 MSB register at offset 29h
• FANTACH2 LSB register at offset 2Ah
• FANTACH2 MSB register at offset 2Bh
• FANTACH3 LSB register at offset 2Ch
• FANTACH3 MSB register at offset 2Dh
• Bit[1] LOCK of the Ready/Lock/Start register at offset 40h
• Zone 1 Low Temp Limit at offset 67h
• Zone 2 Low Temp Limit at offset 68h
• Zone 3 Low Temp Limit at offset 69h
• Bit[3] TRDY of the Configuration register at offset 7Fh
• Top Temperature Remote diode 1 (Zone 1) register at offset AEh
• Top Temperature Remote diode 2 (Zone 3) register at offset AFh
• Top Temperature Ambient (Zone 2) register at offset B3h
21.4.3
SOFT RESET (INITIALIZATION)
Setting bit 7 of the Configuration Register (7Fh) performs a soft reset on all the Hardware Monitoring registers except
the reading registers. This bit is self-clearing.
21.5 Clocks
The hardware monitor logic operates on a 90kHz nominal clock frequency derived from the 14MHz clock input to the
SIO block. The 14MHz clock source is also used to derive the high PWM frequencies.
21.6 Input Monitoring
The SCH322x device’s monitoring function is started by writing a ‘1’ to the START bit in the Ready/Lock/Start Register
(0x40). Measured values from the temperature sensors are stored in Reading Registers. The values in the reading reg-
isters can be accessed via the LPC interface. These values are compared to the programmed limits in the Limit Regis-
ters. The out-of-limit and diode fault conditions are stored in the Interrupt Status Registers.
Note:
All limit and parameter registers must be set before the START bit is set to ‘1’. Once the start bit is set,
these registers become read-only.
21.7 Monitoring Modes
The Hardware Monitor Block supports two Monitoring modes: Continuous Mode and Cycle Mode. These modes are
selected using bit 1 of the Special Function Register (7Ch). The following subsections contain a description of these
monitoring modes.
The time to complete a conversion cycle depends upon the number of inputs in the conversion sequence to be mea-
sured and the amount of averaging per input, which is selected using the AVG[2:0] bits in the Special Function register
(see the Special Function Register, 7Ch).
For each mode, there are four options for the number of measurements that are averaged for each temperature reading.
These options are selected using bits[7:5] of the Special Function Register (7Ch). These bits are defined as follows:
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Bits [7:5] AVG[2:0]
The AVG[2:0] bits determine the amount of averaging for each of the measurements that are performed by the hardware
monitor before the reading registers are updated (Table 21-1). The AVG[2:0] bits are priority encoded where the most
significant bit has highest priority. For example, when the AVG2 bit is asserted, 32 averages will be performed for each
measurement before the reading registers are updated regardless of the state of the AVG[1:0] bits.
TABLE 21-1: AVG[2:0] BIT DECODER
SFTR[7:5]
Measurements per Reading
Nominal Total
Conversion Cycle Time
(MSEC)
Remote
Remote
Diode 2
AVG2
AVG1
AVG0
Ambient
Diode 1
0
0
0
1
0
0
1
X
0
1
128
16
128
16
8
1
587.4
73.4
X
X
16
16
16
32
150.8
301.5
32
32
Note:
The default for the AVG[2:0] bits is ‘010’b.
21.7.1
CONTINUOUS MONITORING MODE
In the continuous monitoring mode, the sampling and conversion process is performed continuously for each tempera-
ture reading after the Start bit is set high. The time for each temperature reading is shown above for each measurement
option.
The continuous monitoring function is started by doing a write to the Ready/Lock/Start Register, setting the START bit
(Bit 0) high. The part then performs a “round robin” sampling of the inputs, in the order shown below (see Table 21-2).
Sampling of all values occurs in a nominal 150.8 ms (default - see Table 21-2).
TABLE 21-2: ADC CONVERSION SEQUENCE
Sampling Order
Register
Remote Diode Temp Reading 1
1
2
3
Ambient Temperature reading
Remote Diode Temp Reading 2
When the continuous monitoring function is started, it cycles through each measurement in sequence, and it continu-
ously loops through the sequence approximately once every 150.8 ms (default - see Table 21-2). Each measured value
is compared to values stored in the Limit registers. When the measured value violates the programmed limit the Hard-
ware Monitor Block will set a corresponding status bit in the Interrupt Status Registers.
If auto fan option is selected, the hardware will adjust the operation of the fans accordingly.
The results of the sampling and conversions can be found in the Reading Registers and are available at any time.
21.7.2
CYCLE MONITORING MODE
In cycle monitoring mode, the part completes all sampling and conversions, then waits approximately one second to
repeat the process. It repeats the sampling and conversion process typically every 1.151 seconds (1.3 sec max - default
averaging enabled). The sampling and conversion of each temperature reading is performed once every monitoring
cycle. This is a power saving mode.
The cycle monitoring function is started by doing a write to the Ready/Lock/Start Register, setting the Start bit (Bit 0)
high. The part then performs a “round robin” sampling of the inputs, in the order shown above.
When the cycle monitoring function is started, it cycles through each measurement in sequence, and it produces a con-
verted temperature reading for each input. The state machine waits approximately one second before repeating this
process. Each measured value is compared to values stored in the Limit registers. When the measured value violates
(or is equal to) the programmed limit the Hardware Monitor Block will set a corresponding status bit in the Interrupt Status
Registers.
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If auto fan option is selected, the hardware will adjust the operation of the fans accordingly.
The results of each sampling and conversion can be found in the Reading Registers and are available at any time, how-
ever, they are only updated once per conversion cycle.
21.8 Interrupt Status Registers
The Hardware Monitor Block contains two primary interrupt status registers (ISRs):
• Interrupt Status Register 1 (41h)
• Interrupt Status Register 2 (42h)
There is also a secondary set of interrupt status registers:
• Interrupt Status Register 1 - Secondary (A5h)
• Interrupt Status Register 2 - Secondary (A6h)
Note 1: The status events in the primary set of interrupt status registers is mapped to a PME bit, an SMI bit, to Serial
IRQ (See Interrupt Event on Serial IRQ on page 130), and to the nHWM_INT pin.
2: The nHWM_INT pin is deasserted when all of the bits in the primary ISRs (41h, 42h) are cleared. The sec-
ondary ISRs do not affect the nHWM_INT pin.
3: The primary and secondary ISRs share all of the interrupt enable bits for each of the events.
These registers are used to reflect the state of all temperature and fan violation of limit error conditions and diode fault
conditions that the Hardware Monitor Block monitors.
When an error occurs during the conversion cycle, its corresponding bit is set (if enabled) in its respective interrupt sta-
tus register. The bit remains set until the register bit is written to ‘1’ by software, at which time the bit will be cleared to
‘0’ if the associated error event no longer violates the limit conditions or if the diode fault condition no longer exists. Writ-
ing ‘1’ to the register bit will not cause a bit to be cleared if the source of the status bit remains active.
These registers default to 0x00 on a VCC POR, VTR POR, and Initialization. (See Resetting the SCH322x Hardware
Monitor Block on page 124.)
The following section defines the Interrupt Enable Bits that correspond to the Interrupt Status registers listed above. Set-
ting or clearing these bits affects the operation of the Interrupt Status bits.
21.8.1
INTERRUPT ENABLE BITS
Each interrupt event can be enabled into the interrupt status registers. See the figure below for the status and enable
bits used to control the interrupt bits and nHWM_INT pin. Note that a status bit will not be set if the individual enable bit
is not set.
The following is a list of the Interrupt Enable registers:
• Interrupt Enable Register - Fan Tachs (80h)
• Interrupt Enable Register - Temp (82h)
Note:
Clearing the individual enable bits will clear the corresponding individual status bit.
Clearing the individual enable bits. There are two cases and in both cases it is not possible to change the individual
interrupt enable while the start bit is set.
1. The interrupt status bit will never be set when the individual interrupt enable is cleared. Here the interrupt status
bit will not get set when the start bit is set, regardless of whether the limits are violated during a measurement.
2. If an interrupt status bit had been set from a previous condition, clearing the start bit and then clearing the indi-
vidual interrupt enable bit will not clear the associated interrupts status bit immediately. It will be cleared when
the start bit is set, when the associated reading register is updated.
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FIGURE 21-3:
INTERRUPT CONTROL
INT1 Reg
2.5V_Error (INT1[0])
2.5V_Error
2.5V_Error_En (IER1[2])
Vccp_Error
Vccp_Error (INT1[1])
Vccp_Error_En (IER1[3])
VCC_Error
VCC_Error (INT1[2])
5V_Error (INT1[3])
VCC_Error_En (IER1[7])
5V_Error
5V_Error_En (IER1[5])
Diode 1 Limit
Diode 1 Limit (INT1[4])
Ambient Limit (INT1[5])
Diode 1_En (IER3[2])
Ambient Limit
Diode 2 Limit
+
Ambient_En (IER3[1])
Diode 2_En (IER3[3])
Diode 2 Limit (INT1[6])
INT23 (INT1[7])
INT2 Event
INT3 Event
INT2 Reg
12V_Error
12V_Error (INT2[0])
12V_Error_En (IER1[6])
PME Status
Bits in SIO
Block
TACH1 Out-of-Limit
TACH1 (INT2[2])
TACH2 (INT2[3])
TACH3 (INT2[4])
TACH1_En (IER2[1])
TACH2 Out-of-Limit
TACH2 _En (IER2[2])
TACH3 Out-of-Limit
nHWM_INT
+
+
TACH3 _En (IER2[3])
Diode 1 Fault
Diode 2 Fault
Diode 1 Fault (INT2[6])
Diode 2 Fault (INT2[7])
Diode 1_En (IER3[2])
Diode 2_En (IER3[3])
INT3 Reg
VTR_Error (INT3[0])
VTR_Error
VTR_Error_En (IER1[4])
+
Vbat_Error
Vbat_Error (INT3[1])
Vbat_Error_En (IER1[1])
From AMTA
Interrupt Logic
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Note 1: The Primary Interrupt Status registers, and the Top Temp Status register may be used to generate a HWM
Interrupt event (HWM_Event). A HWM Interrupt Event may be used to generate a PME, SMI, Serial IRQ, or
nHWM_INT event. Figure 21-3, "Interrupt Control" shows the Interrupt Status registers generating an inter-
rupt event. To see how the Top Temp Status register generates a Top_Temp_Event see FIGURE 21-14:
AMTA Interrupt Mapping on page 149.
2: The diode fault bits are not mapped directly to the nHWM_INT pin. A diode fault condition forces the diode
reading register to a value of 80h, which will generate a Diode Error condition. See section Diode Fault on
page 129.
21.8.2
DIODE FAULT
The SCH322x Chip automatically sets the associated diode fault bit to 1 when any of the following conditions occur on
the Remote Diode pins:
• The positive and negative terminal are an open circuit
• Positive terminal is connected to VCC
• Positive terminal is connected to ground
• Negative terminal is connected to VCC
• Negative terminal is connected to ground
The occurrence of a fault will cause 80h to be loaded into the associated reading register, except for the case when the
negative terminal is connected to ground. A temperature reading of 80h will cause the corresponding diode error bit to
be set. This will cause the nHWM_INT pin to become active if the individual, group (TEMP), and global enable (INTEN)
bits are set.
Note 1: The individual remote diode enable bits and the TEMP bit are located in the Interrupt Enable Register 1
(7Eh). The INTEN bit is located in bit[2] of Special Function Register (7Ch).
2: When 80h is loaded into the Remote Diode Reading Register the PWM output(s) controlled by the zone
associated with that diode input will be forced to full on. See Thermal Zones on page 132.
If the diode is disabled, the fault bit in the interrupt status register will not be set. In this case, the occurrence of a fault
will cause 00h to be loaded into the associated reading register. The limits must be programmed accordingly to prevent
unwanted fan speed changes based on this temperature reading. If the diode is disabled and a fault condition does not
exist on the diode pins, then the associated reading register will contain a “valid” reading (e.g. A reading that is not pro-
duced by a fault condition.).
21.9 Interrupt Signal
The hardware monitoring interrupt signal, which is used to indicate out-of-limit temperature, and/or fan errors, can be
generated via a dedicated pin (nHWM_INT) or through PME Status bits or SMI Status Bits located in the Runtime Reg-
ister block.
To enable temperature event and/or fan events onto the nHWM_INT pin or the PME status bits or SMI status bits, the
following group enable bits must be set:
• To enable out-of-limit temperature events set bit[0] of the Interrupt Enable - Temp register (82h) to ‘1’.
• To enable Fan tachometer error events set bit[0] of the Interrupt Enable - Fan Tachs register (80h) to ‘1’.
21.9.1
INTERRUPT PIN (NHWM_INT)
The nHWM_INT function is used as an interrupt output for out-of-limit temperature and/or fan errors.
• The nHWM_INT signal is on pin 114.
• To enable the interrupt pin to go active, set bit 2 of the Special Function Register (7Ch) to ‘1’.
Note:
If the nHWM_INT pin is not enabled the pin will be tristate if the nHWM_INT function is selected on the pin.
See FIGURE 21-3: on page 128. The following description assumes that the interrupt enable bits for all events are set
to enable the interrupt status bits to be set and no events are being masked.
If the internal or remote temperature reading violates the low or high temperature limits, nHWM_INT will be forced active
low (if all the corresponding enable bits are set: individual enable bits (D1_EN, D2_EN, and/or AMB_EN), group enable
bit (TEMP_EN) and the global enable bit (INTEN)). This pin will remain low while the Internal Temp Error bit or one or
both of the Remote Temp Error bits in Interrupt Status 1 Register is set and the corresponding enable bit(s) are set.
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The nHWM_INT pin will not become active low as a result of the remote diode fault bits becoming set. However, the
occurrence of a fault will cause 80h to be loaded into the associated reading register, which will cause the corresponding
diode error bit to be set. This will cause the nHWM_INT pin to become active if enabled.
The nHWM_INT pin can be enabled to indicate fan errors. Bit[0] of the Interrupt Enable 2 (Fan Tachs) register (80h) is
used to enable this option. This pin will remain low while the associated fan error bit in the Interrupt Status Register 2 is
set.
The nHWM_INT pin will remain low while any bit is set in any of the Interrupt Status Registers. Reading the interrupt
status registers will cause the logic to attempt to clear the status bits; however, the status bits will not clear if the interrupt
stimulus is still active. The interrupt enable bit (Special Function Register bit[2]) should be cleared by software before
reading the interrupt status registers to insure that the nHWM_INT pin will be re-asserted while an interrupt event is
active, when the INT_EN bit is written to ‘1’ again.
The nHWM_INT pin may only become active while the monitor block is operational.
21.9.2
INTERRUPT AS A PME EVENT
The hardware monitoring interrupt signal is routed to the SIO PME block. For a description of these bits see the section
defining PME events. This signal is unaffected by the nHWM_INT pin enable (INT_EN) bit (See FIGURE 21-3: Interrupt
Control on page 128.)
The THERM PME status bit is located in the PME_STS1 Runtime Register at offset 04h located in the SIO block.
When a temperature or fan tachometer event causes a status bit to be set, the THERM PME status bits will be set as
long as the corresponding group enable bit is set.
The enable bit is located in the PME_EN1 register at offset 0Ah.
21.9.3
INTERRUPT AS AN SMI EVENT
The hardware monitoring interrupt signal is routed to the SIO SMI block. For a description of these bits see the section
defining SMI events. This signal is unaffected by the nHWM_INT pin enable (INT_EN) bit (See FIGURE 21-3: Interrupt
Control on page 128.)
The THERM SMI status bit is located in the SMI_STS5 Runtime Register at offset 14h located in the SIO block.
When a temperature or fan tachometer event causes a status bit to be set, the THERM SMI status bits will be set as
long as the corresponding group enable bit is set.
The enable bit is located in the SMI_EN5 register at offset 1Ah.
The SMI is enabled onto the SERIRQ (IRQ2) via bit 6 of the SMI_EN2 register at 17h.
21.9.4
INTERRUPT EVENT ON SERIAL IRQ
The hardware monitoring interrupt signal is routed to the Serial IRQ logic. This signal is unaffected by the nHWM_INT
pin enable (INT_EN) bit (See FIGURE 21-3: Interrupt Control on page 128.)
This operation is configured via the Interrupt Select register (0x70) in Logical Device A. This register allows the selection
of any serial IRQ frame to be used for the HWM nHWM_INT interrupt (SERIRQ9 slot will be used). See Interrupt Event
on Serial IRQ on page 130.
21.10 Low Power Mode
bit The hardware monitor has two modes of operation: Monitoring and Sleep. When the START bit, located in Bit[0] of
the Ready/Lock/Start register (0x40), is set to zero the hardware monitor is in Sleep Mode. When this bit is set to one
the hardware monitor is fully functional and monitors the analog inputs to this device.
bit Sleep mode is a low power mode in which bias currents are on and the internal oscillator is on, but the A/D converter
and monitoring cycle are turned off. Serial bus communication is still possible with any register in the Hardware Monitor
Block while in this low-power mode.
Note 1: In Sleep Mode the PWM Pins are held high forcing the PWM pins to 100% duty cycle (256/256).
2: The START a bit cannot be modified when the LOCK bit is set.
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21.11 Temperature Measurement
Temperatures are measured internally by bandgap temperature sensor and externally using two sets of diode sensor
pins (for measuring two external temperatures). See subsections below.
Note:
The temperature sensing circuitry for the two remote diode sensors is calibrated for a 3904 type diode.
21.11.1 INTERNAL TEMPERATURE MEASUREMENT
Internal temperature can be measured by bandgap temperature sensor. The measurement is converted into digital for-
mat by internal ADC. This data is converted in two’s complement format since both negative and positive temperature
can be measured. This value is stored in Internal Temperature Reading register (26h) and compared to the Temperature
Limit registers (50h – 51h). If this value violates the programmed limits in the Internal High Temperature Limit register
(51h) and the Internal Low Temperature Limit register (50h) the corresponding status bit in Interrupt Status Register 1
is set.
If auto fan option is selected, the hardware will adjust the operation of the fans accordingly. See the section titled Auto
Fan Control Operating Mode on page 134.
21.11.2 EXTERNAL TEMPERATURE MEASUREMENT
The Hardware Monitor Block also provides a way to measure two external temperatures using diode sensor pins
(Remote x+ and Remote x-). The value is stored in the register (25h) for Remote1+ and Remote1- pins. The value is
stored in the Remote Temperature Reading register (27h) for Remote2+ and Remote2- pins. If these values violate the
programmed limits in the associated limit registers, then the corresponding Remote Diode 1 (D1) or Remote Diode 2
(D2) status bits will be set in the Interrupt Status Register 1.
If auto fan option is selected, the hardware will adjust the operation of the fans accordingly. See Auto Fan Control Oper-
ating Mode on page 134.
There are Remote Diode (1 or 2) Fault status bits in Interrupt Status Register 2 (42h), which, when one, indicate a short
or open-circuit on remote thermal diode inputs (Remote x+ and Remote x-). Before a remote diode conversion is
updated, the status of the remote diode is checked. In the case of a short or open-circuit on the remote thermal diode
inputs, the value in the corresponding reading register will be forced to 80h. Note that this will cause the associated
remote diode limit exceeded status bit to be set (i.e. Remote Diode x Limit Error bits (D1 and D2) are located in the
Interrupt Status 1 Register at register address 41h).
The temperature change is computed by measuring the change in Vbe at two different operating points of the diode to
which the Remote x+ and Remote x- pins are connected. But accuracy of the measurement also depends on non-ide-
ality factor of the process the diode is manufactured on.
21.11.3 TEMPERATURE DATA FORMAT
Temperature data can be read from the three temperature registers:
• Internal Temp Reading register (26h)
• Remote Diode 1 Temp Reading register (25h)
• Remote Diode 2 Temp Reading register (27h)
The following table shows several examples of the format of the temperature digital data, represented by an 8-bit, two’s
complement word with an LSB equal to 1.0 0C.
TABLE 21-3: TEMPERATURE DATA FORMAT
Temperature
Reading (DEC)
Reading (HEX)
Digital Output
-1270C
-127
81h
1000 0001
0
-50 C
-50
-25
-1
CEh
E7h
FFh
1100 1110
1110 0111
1111 1111
0
-25 C
0
-1 C
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TABLE 21-3: TEMPERATURE DATA FORMAT (CONTINUED)
Temperature
Reading (DEC)
Reading (HEX)
Digital Output
0
0 C
0
1
00h
01h
0000 0000
0000 0001
0
+1 C
0
+25 C
25
50
19h
32h
0001 1001
0011 0010
+500C
+1270C
127
128
7Fh
80h
0111 1111
1000 0000
SENSOR ERROR
21.12 Thermal Zones
Each temperature measurement input is assigned to a Thermal Zone to control the PWM outputs in Auto Fan Control
mode. These zone assignments are as follows:
• Zone 1 = Remote Diode 1 (Processor)
• Zone 2 = Ambient Temperature Sensor
• Zone 3 = Remote Diode 2
The auto fan control logic uses the zone temperature reading to control the duty cycle of the PWM outputs.
The following sections describe the various fan control and monitoring modes in the part.
21.13 Fan Control
This Fan Control device is capable of driving multiple DC fans via three PWM outputs and monitoring up to three fans
equipped with tachometer outputs in either Manual Fan Control mode or in Auto Fan Control mode. The three fan control
outputs (PWMx pins) are controlled by a Pulse Width Modulation (PWM) scheme. The three pins dedicated to monitor-
ing the operation of each fan are the FANTACH[1:3] pins. Fans equipped with Fan Tachometer outputs may be con-
nected to these pins to monitor the speed of the fan.
21.13.1 LIMIT AND CONFIGURATION REGISTERS
At power up, all the registers are reset to their default values and PWM[1:3] are set to “Fan always on Full” mode. Before
initiating the monitoring cycle for either manual or auto mode, the values in the limit and configuration registers should
be set.
The limit and configuration registers are:
• Registers 54h – 5Bh: TACHx Minimum
• Registers 5Fh – 61h: Zone x Range/FANx Frequency
• Registers 5Ch – 5Eh: PWMx Configuration
• Registers 62h 63h: PWM 1 Ramp Rate Control
• Registers 64h – 66h: PWMx Minimum Duty Cycle
• Registers 67h – 69h: Zone x Low Temp LIMIT
• Registers 6Ah – 6Ch: Zone x Temp Absolute Limit – all fans in Auto Mode are set to full
• Register 81h: TACH_PWM Association
• Registers 90h – 92h: Tachx Option Registers
• Registers 94h – 96h: PWMx Option Registers
Note 1: The START bit in Register 40h Ready/Lock/Start Register must be set to ‘1’ to start temperature monitoring
functions.
2: Setting the PWM Configuration register to Auto Mode will not take effect until after the START bit is set
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21.13.2 DEVICE SET-UP
BIOS will follow the steps listed below to configure the fan registers on this device. The registers corresponding to each
function are listed. All steps may not be necessary if default values are acceptable. Regardless of all changes made by
the BIOS to the limit and parameter registers during configuration, the SCH322x will continue to operate based on
default values until the Start bit, in the Ready/Lock/Start register, is set. Once the Start bit is set, the SCH322x will oper-
ate according to the values that were set by BIOS in the limit and parameter registers.
Following a VTR Power-on-Reset (loss of a/c power) the following steps must be taken:
1. Set limits and parameters (not necessarily in this order)
a) [5F-61h] Set PWM frequencies and Auto Fan Control Range.
b) [62-63h] Set Ramp Rate Control.
c) [5C-5Eh] Set the fan spin-up delays.
d) [5C-5Eh] Match each PWM output with a corresponding thermal zone.
e) [67-69h] Set the zone temperature low limits.
f) [6A-6Ch] Set the zone temperature absolute limits.
g) [64-66h] Set the PWM minimum duty cycle.
h) [81h] Associate a Tachometer input to a PWM output Register
i) [90-92h] Select the TACH Mode of operation (Mode 1 or Mode 2)
j) [90-92h] Set the number of edges per tach reading
k) [90-92h] Set the ignore first 3 edges of tach input bit
l) [90-92h] Set the SLOW bit if tach reading should indicated slow fan event as FFFEh and stalled fan event
as FFFFh.
m) [94-96h] Set the TACH Reading Update rate
n) [94-96h] Set the tach reading guard time (Mode 2 Only)
o) [94-96h] Set the TACH reading logic for Opportunistic Mode (Mode 2 Only)
p) [94-96h] Set the SZEN bit, which determines if the PWM output will ramp to Off or jump to Off.
q) [ABh] Set the Tach 1-3 Mode
r) [AEh, AFh, B3h] Set the Top Temperature Remote 1, 2, Ambient
s) [B4h - B6h] Min Temp Adjust Temp Remote 1-2, Min Temp Adjust Temp and Delay Amb, and Min Temp
Adjust Delay 1-2
t) [B7h] Tmin Adjust Enable
u) [C4h, C5h, C9h] THERMTRIP Temp Limit Remote 1, 2, Ambient
v) [CEh] THERMTRIP Output Enable
w) [D1h, D6h, DBh] PWM1, 2, 3 Max Duty Cycle
2. [40h] Set bit 0 (Start) to start monitoring
3. [40h] Set bit 1 (Lock) to lock the limit and parameter registers (optional).
Following a VCC Power-On-Reset (exiting sleep mode) the following steps must be taken. These steps are required for
most systems in order to prevent improper fan start-up due to the reset of the Top Temperature and zone low limit reg-
isters to their default values on active PWRGD_PS.
1. Set the ramp rate to the min value [registers 62h and 63h].
2. Clear the start bit (bit 0 of register 40h) to stop monitoring
3. Set the Top Temperature Remote 1, 2, Ambient registers [AEh, AFh, B3h] to their initial values
4. Set the zone temperature low limit registers [67-69h] to their initial values
5. Set the start bit (bit 0 of register 40h) to start monitoring
6. Set the lock bit (bit 1of register 40h) to lock the limit and parameter registers (optional)
Note:
If not locked, the ramp rate can be set to a new value at a later time if desired [registers 62h and 63h].
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21.13.3 PWM FAN SPEED CONTROL
The following description applies to PWM1, PWM2, and PWM3.
Note:
The PWM output pins are held low when VCC=0. The PWM pins will be forced to “spinup” when PWRG-
D_PS goes active. See “Spin Up” on page 137.
The PWM pin reflects a duty cycle that is determined based on 256 PWM duty cycle intervals. The minimum duty cycle
is “off”, when the pin is low, or “full on” when the pin is high for 255 intervals and low for 1 interval. The INVERT bit (bit
4 of the PWMx Configuration registers at 80h-82h) can be used to invert the PWM output, however, the default operation
(following a VCC POR) of the part is based on the PWM pin active high to turn the fans “on”. When the INVERT bit is
set, as long as power is not removed from the part, the inversion of the pin will apply thereafter.
When describing the operation of the PWMs, the terms “Full on” and “100% duty cycle” means that the PWM output will
be high for 255 clocks and low for 1 clock (INVERT bit = 0). The exception to this is during fan spin-up when the PWM
pin will be forced high for the duration of the spin-up time.
The SCH322x can control each of the PWM outputs in one of two modes:
• Manual Fan Control Operating Mode: software controls the speed of the fans by directly programming the PWM
duty cycle.
• Auto Fan Control Mode: the device automatically adjusts the duty cycle of the PWM outputs based on tempera-
ture, according to programmed parameters.
These modes are described in sections that follow.
21.13.3.1 Manual Fan Control Operating Mode (Test Mode)
When operating in Manual Fan Control Operating Mode, software controls the speed of the fans by directly program-
ming the PWM duty cycle. The operation of the fans can be monitored based on reading the temperature and tachom-
eter reading registers and/or by polling the interrupt status registers. The SCH322x offers the option of generating an
interrupt indicated by the nHWM_INT signal.
To control the PWM outputs in manual mode:
• To set the mode to operate in manual mode, write ‘111’ to bits[7:5] Zone/Mode, located in Registers 5Ch-5Eh:
PWMx Configuration.
• The speed of the fan is controlled by the duty cycle set for that PWM output. The duty cycle must be programmed
in Registers 30h-32h: Current PWM Duty
To monitor the fans:
Fans equipped with Tachometer outputs can be monitored via the FANTACHx input pins. See Section 21.14.2, "Fan
Speed Monitoring," on page 150.
If an out-of-limit condition occurs, the corresponding status bit will be set in the Interrupt Status registers. Setting this
status bit will generate an interrupt signal on the nHWM_INT pin (if enabled). Software must handle the interrupt condi-
tion and modify the operation of the device accordingly. Software can evaluate the operation of the Fan Control device
through the Temperature and Fan Tachometer Reading registers.
When in manual mode, the current PWM duty cycle registers can be written to adjust the speed of the fans, when the
start bit is set. These registers are not writable when the lock bit is set.
Note:
The PWMx Current Duty Cycle register is implemented as two separate registers: a read-only and a write-
only. When a value is written to this register in manual mode there will be a delay before the programmed
value can be read back by software. The hardware updates the read-only PWMx Current Duty Cycle reg-
ister on the beginning of a PWM cycle. If Ramp Rate Control is disabled, the delay to read back the pro-
grammed value will be from 0 seconds to 1/(PWM frequency) seconds. Typically, the delay will be
1/(2*PWM frequency) seconds.
21.13.3.2 Auto Fan Control Operating Mode
The SCH322x implements automatic fan control. In Auto Fan Mode, this device automatically adjusts the PWM duty
cycle of the PWM outputs, according to the flow chart on the following page (see FIGURE 21-4: Automatic Fan Control
Flow Diagram on page 135).
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PWM outputs are assigned to a thermal zone based on the PWMx Configuration registers (see Thermal Zones on page
132). It is possible to have more than one PWM output assigned to a thermal zone. For example, PWM outputs 2 and
3, connected to two chassis fans, may both be controlled by thermal zone 2. At any time, if the temperature of a zone
exceeds its absolute limit, all PWM outputs go to 100% duty cycle to provide maximum cooling to the system (except
those fans that are disabled or in manual mode).
It is possible to have a single fan controlled by multiple zones, turning on when either zone requires cooling based on
its individual settings.
If the start bit is one, the Auto Fan Control block will evaluate the temperature in the zones configured for each Fan in
a round robin method. The Auto Fan Control block completely evaluates the zones for all three fans in a maximum of
0.25sec.
FIGURE 21-4:
AUTOMATIC FAN CONTROL FLOW DIAGRAM
Auto Fan Mode
Initiated
End Polling
Cycle
No
End Fan Spin
Up
Begin Polling
Cycle
Yes
Spin Up
Time Elapsed?
(5C-5E)
Fan Spinning
Up?
Yes
No
Override all PWM
Temp >=
AbsLimit
(69~6B)
outputs to 100%
duty cycle except
if disabled or in
manual mode
Yes
No
Temp >= Limit
(66~68)
No
Set Fan Output to
100%
Yes
Set fan to min
PWM
Begin Fan Spin-
Up
Fan Output
At 0%?
Yes
No
Set fan speed based on
Auto Fan Range
Algorithm*
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When in Auto Fan Control Operating Mode the hardware controls the fans directly based on monitoring of temperature
and speed.
To control the fans:
• Set the minimum temperature that will turn the fans on. This value is programmed in Registers 67h-69h: Zone x
Low Temp Limit (Auto Fan Mode Only).
The speed of the fan is controlled by the duty cycle set for that device. The duty cycle for the minimum fan speed must
be programmed in Registers 64h-66h: PWMx Minimum Duty Cycle. This value corresponds to the speed of the fan when
the temperature reading is equal to the minimum temperature LIMIT setting. As the actual temperature increases and
is above the Zone LIMIT temperature and below the Absolute Temperature Limit, the PWM will be determined by a linear
function based on the Auto Fan Speed Range bits in Registers 5Fh-61h.
The maximum speed of the fan for the linear autofan function is programmed in the PWMx Max registers (0D1h, 0D6h,
0DBh). When the temperature reaches the top of the linear fan function for the sensor (Zone x Low Temp Limit plus
Temperature Range) the fan will be at the PWM maximum duty cycle.
Set the absolute temperature for each zone in Registers 6Ah-6Ch: Zone x Temp Absolute Limit (Auto Fan Mode only).
If the actual temperature is equal to or exceeds the absolute temperature in one or more of the associated zones, all
Fans operating in auto mode will be set to Full on, regardless of which zone they are operating in (except those that are
disabled or configured for Manual Mode). Note that fans can be disabled via the PWMx Configuration registers and the
absolute temperature safety feature can be disabled by writing 80h into the Zone x Temp Absolute Limit registers.
To set the mode to operate in auto mode, set Bits[7:5] Zone/Mode, located in Registers 5Ch-5Eh: PWM Configuration
Bits[7:5]=’000’ for PWM on Zone 1; Bits[7:5]=’001’ for PWM on Zone 2; Bits[7:5]=’010’ for PWM on Zone 3. If the “Hot-
test” option is chosen (101 or 110), then the PWM output is controlled by the zone that results in the highest PWM duty
cycle value.
Note 1: Software can be alerted of an out-of-limit condition by the nHWM_INT pin if an event status bit is set and
the event is enabled and the interrupt function is enabled onto the nHWM_INT pin.
2: Software can monitor the operation of the Fans through the Fan Tachometer Reading registers and by the
PWM x Current PWM duty registers. It can also monitor current temperature readings through the Tempera-
ture Limit Registers if hardware monitoring is enabled.
3: Fan control in auto mode is implemented without any input from external processor .
In auto “Zone” mode, the speed is adjusted automatically as shown in the figure below. Fans are assigned to a zone(s).
It is possible to have more than one fan assigned to a thermal zone or to have multiple zones assigned to one fan.
FIGURE 21-5: on page 137 shows the control for the auto fan algorithm. The part allows a minimum temperature to be
set, below which the fan will run at minimum speed. The minimum speed is programmed in the PWMx Minimum Duty
cycle registers (64h-66h) and may be zero. A temperature range is specified over which the part will automatically adjust
the fan speed. The fan will go to a duty cycle computed by the auto fan algorithm. As the temperature rises, the duty
cycle will increase until the fan is running at full-speed when the temperature reaches the minimum plus the range value.
The effect of this is a temperature feedback loop, which will cause the temperature to reach equilibrium between the
minimum temperature and the minimum temperature plus the range. Provided that the fan has adequate cooling capac-
ity for all environmental and power dissipation conditions, this system will maintain the temperature within acceptable
limits, while allowing the fan to run slower (and quieter) when less cooling is required.
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FIGURE 21-5:
AUTOMATIC FAN CONTROL
( F a n s t a y s o n w h e n t e m p e r a t u r e is b e lo w m in im u m t e m p . )
T e m p
T m a x
=
T m in
+
T r a n g e
T m in
T im e
P W M
D u ty
C y c le
M a x
m in
T im e
21.13.3.3 Spin Up
When a fan is being started from a stationary state (PWM duty cycle =00h), the part will cause the fan to “spin up” by
going to 100% duty cycle for a programmable amount of time to overcome the inertia of the fan (i.e., to get the fan turn-
ing). Following this spin up time, the fan will go to the duty cycle computed by the auto fan algorithm.
During spin-up, the PWM duty cycle is reported as 0%.
To limit the spin-up time and thereby reduce fan noise, the part uses feedback from the tachometers to determine when
each fan has started spinning properly. The following tachometer feedback is included into the auto fan algorithm during
spin-up.
Auto Fan operation during Spin Up:
The PWM goes to 100% duty cycle until the tachometer reading register is below the minimum limit (see Figure 21-6),
or the spin-up time expires, whichever comes first. This causes spin-up to continue until the tachometer enters the valid
count range, unless the spin up time expires. If the spin up expires before the tachometer enters the valid range, an
interrupt status bit will be set once spin-up expires. Note that more than one tachometer may be associated with a PWM,
in which case all tachometers associated with a PWM must be in the valid range for spin-up to end.
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FIGURE 21-6:
SPIN UP REDUCTION ENABLED
duty cycle = 100%
duty cycle = 0%
PWM Output
tach reading
vs. tach limit
tach reading >
tach limit
FFFFh
tach reading < tach limit
Spin Up Time
Programmed Spin Up Time
Note: When Spin Up Reduction is enabled (SUREN), the Spin Up time will be less than
or equal to the programmed time for Spin Up. Once the tachometer(s) associated with
a PWM output are operating within the programmed limits or the Spin Up time expires,
whichever comes first, the PWM output is reduced to the calculated duty cycle.
This feature defaults to enabled; it can be disabled by clearing bit 4 of the Configuration register (7Fh). If disabled, the
all fans go to 100% duty cycle for the duration of their associated spin up time. Note that the Tachometer x minimum
registers must be programmed to a value less than FFFFh in order for the spin up reduction to work properly.
Note 1: The tachometer reading register always gives the actual reading of the tachometer input.
2: No interrupt bits are set during spin-up.
21.13.3.4 Hottest Option
If the “Hottest” option is chosen (101 or 110), then the fan is controlled by the limits and parameters associated with the
zone that requires the highest PWM duty cycle value, as calculated by the auto fan algorithm.
21.13.3.5 Ramp Rate Control Logic
The Ramp Rate Control Logic, if enabled, limits the amount of change in the PWM duty cycle over a specified period of
time. This period of time is programmable in the Ramp Rate Control registers located at offsets 62h and 63h.
21.13.3.5.1
Ramp Rate Control Disabled: (default)
The Auto Fan Control logic determines the duty cycle for a particular temperature. If PWM Ramp Rate Control is dis-
abled, the PWM output will be set to this calculated duty cycle.
21.13.3.5.2
Ramp Rate Control Enabled:
If PWM Ramp Rate Control is enabled, the PWM duty cycle will Ramp up or down to the new duty cycle computed by
the auto fan control logic at the programmed Ramp Rate. The PWM Ramp Rate Control logic compares the current duty
cycle computed by the auto fan logic with the previous ramp rate duty cycle. If the current duty cycle is greater than the
previous ramp rate duty cycle the ramp rate duty cycle is incremented by ‘1’ at the programmed ramp rate until it is
greater than or equal to the current calculated duty cycle. If the current duty cycle is less than the previous ramp rate
duty cycle, the ramp rate duty cycle is decremented by ‘1’ until it is less than or equal to the current duty cycle. If the
current PWM duty cycle is equal to the calculated duty cycle the PWM output will remain unchanged.
Internally, the PWM Ramp Rate Control Logic will increment/decrement the internal PWM Duty cycle by ‘1’ at a rate
determined by the Ramp Rate Control Register (see Table 21-4). The actual duty cycle output is changed once per the
period of the PWM output, which is determined by the frequency of the PWM output. (See FIGURE 21-7: Illustration of
PWM Ramp Rate Control on page 140.)
• If the period of the PWM output is less than the step size created by the PWM Ramp Rate, the PWM output will
hold the duty cycle constant until the Ramp Rate logic increments/decrements the duty cycle by ‘1’ again. For
example, if the PWM frequency is 87.7Hz (1/87.7Hz = 11.4msec) and the PWM Step time is 206msec, the PWM
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duty cycle will be held constant for a minimum of 18 periods (206/11.4 = 18.07) until the Ramp Logic incre-
ments/decrements the actual PWM duty cycle by ‘1’.
• If the period of the PWM output is greater than the step size created by the PWM Ramp Rate, the ramp rate logic
will force the PWM output to increment/decrement the actual duty cycle in increments larger than 1/255. For
example, if the PWM frequency is 11Hz (1/11Hz = 90.9msec) and the PWM Step time is 5msec, the PWM duty
cycle output will be incremented 18 or 19 out of 255 (i.e., 90.9/5 = 18.18) until it reaches the calculated duty cycle.
Note that the step size may be less if the calculated duty cycle minus the actual duty cycle is less than 18.
Note:
The calculated PWM Duty cycle reacts immediately to a change in the temperature reading value. The tem-
perature reading value may be updated once in 105.8msec (default) (see Table 21-2, “ADC Conversion
Sequence,” on page 126). The internal PWM duty cycle generated by the Ramp Rate control logic gradu-
ally ramps up/down to the calculated duty cycle at a rate pre-determined by the value programmed in the
PWM Ramp Rate Control bits. The PWM output latches the internal duty cycle generated by the Ramp
Rate Control Block every 1/(PWM frequency) seconds to determine the actual duty cycle of the PWM out-
put pin.
PWM Output Transition from OFF to ON
When the calculated PWM Duty cycle generated by the auto fan control logic transitions from the ‘OFF’ state to the ‘ON’
state (i.e., Current PWM duty cycle>00h), the internal PWM duty cycle in the Ramp Rate Control Logic is initialized to
the calculated duty cycle without any ramp time and the PWMx Current Duty Cycle register is set to this value. The PWM
output will latch the current duty cycle value in the Ramp Rate Control block to control the PWM output.
PWM Output Transition from ON to OFF
Each PWM output has a control bit to determine if the PWM output will transition immediately to the OFF state (default)
or if it will gradually step down to Off at the programmed Ramp Rate. These control bits (SZEN) are located in the PWMx
Options registers at offsets 94h-96h.
TABLE 21-4: PWM RAMP RATE
PWM Ramp Time (sec) PWM Ramp Time (sec)
Time per
PWM Step
(PWM Step Size =
1/255)
PWM
Ramp Rate
(Hz)
(Time from 33% Duty
Cycle to 100% Duty
Cycle)
(Time from 0% Duty
Cycle to 100% Duty
Cycle)
RRx-[2:0]
000
001
010
011
100
101
110
111
35
17.6
11.8
7.0
52.53
26.52
17.595
10.455
6.63
206 msec
104 msec
69 msec
41 msec
26 msec
18 msec
10 msec
5 msec
4.85
9.62
14.49
24.39
38.46
55.56
100
4.4
3.0
4.59
1.6
2.55
0.8
1.275
200
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FIGURE 21-7:
ILLUSTRATION OF PWM RAMP RATE CONTROL
Example 1: PWM period < Ramp Rate Step Size
PWM frequency = 87.7Hz (11.4msec) & PWM Ramp Rate = 38.46Hz (26msec)
Calculate Duty Cycle
Ramping Duty Cycle
74h
70h
70h
73h
72h
74h
71h
26ms
26ms
26ms
26ms
PWM Duty Cycle
70h
71h
72h
73h
73h
74h
71h
71h
72h
73h
74h
74h
11.4ms
11.4ms
11.4ms
11.4ms
11.4ms
11.4ms
11.4ms
11.4ms
11.4ms
Example 2: PWM period > Ramp Rate Step Size
PWM frequency = 11Hz (90.9msec) & PWM Ramp Rate = 38.46Hz (26msec)
Calculate Duty Cycle
Ramping Duty Cycle
74h
70h
70h
73h
72h
74h
71h
26ms
26ms
26ms
26ms
PWM Duty Cycle
70h
74h
71h
90.9msec
Note 1: The PWM Duty Cycle latches the Ramping Duty Cycle on the rising edge of the PWM output.
2: The calculated duty cycle, ramping duty cycle, and the PWM output duty cycle are asynchronous to each
other, but are all synchronized to the internal 90kHz clock source.
It should be noted that the actual duty cycle on the pin is created by the PWM Ramp Rate Control block and latched on
the rising edge of the PWM output. Therefore, the current PWM duty cycle may lag the PWM Calculated Duty Cycle.
21.13.4 OPERATION OF PWM PIN FOLLOWING A POWER CYCLE
This device has special features to control the level and operation of the PWM pin following a Power Cycle. These fea-
tures are PWM Clamping and Forced Spinup.
21.13.4.1 PWM Clamp
The PWM pin has the option to be held low for 0 seconds or 2 seconds following a VCC POR. This feature is selectable
by a Vbat powered register bit in the SIO Runtime Register block.
Bit[7] of the DBLCLICK register at offset 5Bh is used to select the 0 or 2 second option.
This bit is defined as follows:
• BIT[3] ZERO_SPINUP
- 1 = zero delay for spin up
- 0 = delay spinup by 2 seconds (default)
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Following PWRGD_PS being asserted the PWM Pin will be held low until either the TRDY signal is asserted or the delay
counter expires, whichever comes first. The delay counter performs two functions when set to the 2 second delay option.
1. Following a VTR POR & VCC POR, the BIOS has up to 2 seconds to program the hwm registers and enable
autofan before the fans are turned on full. This is a noise reduction feature
2. Following a VCC POR only (return from sleep) the hardware requires 150.8 ms (default - see Table 21-2) to load
the temperature reading registers. The TRDY signal is used to indicate when these values have been updated.
TRDY is reset to zero on a VCC POR, which forces the Fans to be set to FFh. If the delay counter is enabled for
up to a 2 second delay, the PWMs will be held low until the reading registers are valid. Once the registers are
updated, the hardware will initiate a forced spinup (if enabled) and enter automode. See Forced Spinup on page
141.
The timing diagrams in the section titled Timing Diagrams for PWM Clamp and Forced Spinup Operation on page 142
show the effect of the 2 second PWM hold-off counter on the PWM pin.
21.13.4.2 Forced Spinup
Spinup is a feature of the auto fan control mode. Any time the PWM pin transitions from a 0% duty cycle to a non zero
duty cycle the PWM pin will be forced high for the duration of spinup or until the fan are spinning within normal operating
parameters as determined by the Tach Limit registers. See Spin Up on page 137 for a more detailed description of
spinup. This feature can also be initiated by the PWRGD_PS signal transitioning high following a main (VCC) power
cycle if the TRDY bit is set to one before the PWM Clamp is released.
Note 1: In this device, a forced spinup will be generated the first time TRDY is detected as a ‘1’ following the PWRG-
D_PS signal transitioning from low to high (if enabled). To enable this feature, set bit[3] of the PWMx Con-
figuration registers to one. These registers are located at offsets 5Ch, 5Dh, and 5Eh.
2: If the TRDY bit is ‘1’ and cleared by software after being set to and then set again while the PWRGD_PS
signal is high, the act of TRDY being asserted will not cause a forced spinup event.
• The duration of the forced spin-up time is controlled by the SPIN[2:0] bits located in the PWM x Configuration reg-
isters (5Ch - 5Eh). The forced spinup enable bit is located in Bit[3] SUENx of the PWMx Configuration registers.
Forced Spinup defaults to disabled on a VTR POR.
21.13.4.2.1
Start of Spin-up on main (VCC) power cycle
The PWM spin-up supports the scenario where the part is powered by VTR and the fans are powered by a main power
rail. If the start bit is not cleared on a main power cycle, then the PWM will remain at a level that may not start the fan
when the main supply ramps up. This spinup will force each PWM into spin-up (if enabled) when the TRDY bit goes
active.
21.13.4.2.2
Start of Spin-up on Standby (VTR) Power Cycle
The two second PWM Clamping feature may be used to delay the fans from being turned on full until the BIOS has the
opportunity to program the limit and configuration registers for the auto fan control mode. (See PWM Clamp on page
140) This is a noise reduction feature. Once the TRDY bit goes high the clamp will be released and the fans will be
forced into spinup.
Note:
If the two second PWM Clamping period expires before TRDY is asserted, the PWMs will be set to Full On.
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21.13.4.3 Timing Diagrams for PWM Clamp and Forced Spinup Operation
FIGURE 21-8:
CASE 1 SPINUP OPERATION
Case 1: Spinup Operation Following PWRGD_PS Active after VTR POR.
START bit and TRDY go high during 2 sec delay.
VTR
VCC
PWRGD_PS
PWM
Spinup
Time
Duty Cycle
PWM Clamp
Timer
START
TRDY
2 seconds
Spinup
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FIGURE 21-9:
CASE 2 SPINUP OPERATION
Case 2: Spinup Operation Following PWRGD_PS Active after VTR POR.
START bit goes high during 2 sec delay, TRDY goes high after 2 sec delay.
VTR
VCC
PWRGD_PS
PWM
Spinup
Time
FFh
Duty Cycle
PWM Clamp
2 seconds
Timer
START
TRDY
Spinup
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FIGURE 21-10:
CASE 3 SPINUP OPERATION
Case 3: Spinup Operation Following PWRGD_PS Active after VTR POR.
START bit and TRDY go high after 2 sec delay.
VTR
VCC
PWRGD_PS
PWM
Spinup
Time
FFh
Duty Cycle
PWM Clamp
Timer
2 seconds
START
TRDY
Spinup
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FIGURE 21-11:
CASE 4 SPINUP OPERATION
Case 4: Spinup Operation Following PWRGD_PS Active after VTR POR.
START bit and TRDY do not go high.
VTR
VCC
PWRGD_PS
PWM
FFh
PWMClamp
2 seconds
Timer
START
TRDY
Spinup
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FIGURE 21-12:
CASE 5 SPINUP OPERATION
Case 5: Spinup Operation Following PWRGD_PS Active after VCC POR.
START bit and TRDY high before 2 sec delay.
VTR
VCC
PWRGD_PS
PWM
Spinup
Time
Duty Cycle
Duty Cycle
PWM Clamp
Timer
START
TRDY
2 sec
2 sec
This is thetime to complete
one monitoring cycle.
Spinup
21.13.5 ACTIVE MINIMUM TEMPERATURE ADJUSTMENT (AMTA)
The AMTA operation in the SCH322x consists of a “Top Temperature” register (for each zone) that defines the upper
bound of the operating temperature for the zone. If the temperature exceeds this value, the minimum temperature (Low
Temp Limit) for the zone is adjusted down. This keeps the zone operating in the lower portion of the temperature range
of the fan control function (PWM Duty Cycle vs. Temperature), thereby limiting fan noise by preventing the fan from
going to the higher PWM duty cycles.
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21.13.5.1 Adjusting Minimum Temperature Based on Top Temperature
This describes the option for adjusting the minimum temperature based on the Top Temperature.
The AMTA option automatically adjusts the preprogrammed value for the minimum temperature and shifts the tempera-
ture range for the autofan algorithm to better suit the environment of the system, that is, to bias the operating range of
the autofan algorithm toward the low end of the temperature range.
It uses a programmed value for the “Top temperature” for the zone to shift the temperature range of the autofan algo-
rithm, and therefore the speed of the fan, toward the middle of the fan control function (PWM Duty Cycle vs. Tempera-
ture). This feature will effectively prevent the fans from going on full, thereby limiting the noise produced by the fans.
The value of the Top temperature for each zone can be programmed to be near the center of the temperature range for
the zone, or near the maximum as defined by the low temp limit plus range. The implementation of the AMTA feature is
defined as follows:
This feature can be individually enabled to operate for each zone. Each zone has a separate enable bit for this feature
(register 0B7h). Note that if the piecewise linear fan function is used, the minimum temperature for the zone (Zone x
Low Temp Limit register) is shifted down, which will result in each segment being shifted down.
This feature adjusts the minimum temperature for each zone for the autofan algorithm based on the current temperature
reading for the zone exceeding the Top temperature.
When the current temperature for the zone exceeds the Top temperature for the zone, the minimum temperature value
is reloaded with the value of the minimum temperature limit minus a programmable temperature adjustment value for
the zone, as programmed in the Min Temp Adjust registers. The temperature adjustment value is programmable for
each zone.
The zone must exceed the limits set in the associated Top Temp Zone [3:1] register for two successive monitoring cycles
in order for the minimum temperature value to be adjusted (and for the associated status bit to be set).
The new minimum temperature value is loaded into the low temp limit register for each zone (Zone x Low Temp Limit).
This will cause the temperature range of the autofan algorithm to be biased down in temperature.
Note:
When the minimum temperature for the zone is adjusted, the autofan algorithm will operate with a new fan
control function (PWM Duty Cycle vs. Temperature), which will result in a new PWM duty cycle value. The
PWM will move to the new value smoothly, so there is little audible effect when the PWM Ramp rate control
is enabled.
This process will repeat after a delay until the current temperature for the zone no longer exceeds the Top temperature
for the zone.
Once the minimum temp value is adjusted, it will not adjust again until after a programmable time delay. The delay is
programmed for each zone in the Min Temp Adjust Delay registers. The adjust times are as follows: 1, 2, 3, and 4 min-
utes.
Figure 8.5 illustrates the operation of the AMTA for one adjustment down in minimum temperature resulting from the
temperature exceeding the Top temperature. The effect on the linear fan control function (PWM Duty Cycle vs. Tem-
perature) is shown.
2016-2017 Microchip Technology Inc.
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FIGURE 21-13:
AMTA ILLUSTRATION, ADJUSTING MINIMUM TEMPERATURE
TMIN ADJUST
TOP
PWM
Duty
Cycle
Initial
Operating Range
MAX
MIN
Increasing Temp
Range
Range
Temperature
TMIN
New TMIN = TMIN – TMIN ADJUST
Note:
If the AMTA feature is not enabled for a zone, then the Top temperature register for that zone is not used.
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21.13.5.1.1
Interrupt Generation
The following figure illustrates the operation of the interrupt mapping for the AMTA feature in relation to the status bits
and enable bits.
FIGURE 21-14:
AMTA INTERRUPT MAPPING
Top Temp
Exceeded
Status Reg
Zone 3
Zone 3 Top Limit Exceeded
Zone 2 Top Limit Exceeded
Zone 1 Top Limit Exceeded
(TTE Status [2])
O
R
To INT Pin
(AND'd with
INTEN bit)
Top_Temp_Event
Zone 2
(TTE Status [1])
TOP_INT_EN
(Tmin Adjust Enable Reg [0])
Zone 1
(TTE Status [0])
TMIN_ADJ_EN1
(Tmin Adjust Enable [1])
To Zone 1-3 Low
Temp Limit Adjust
Logic
TMIN_ADJ_EN2
(Tmin Adjust Enable [2])
TMIN_ADJ_EN3
(Tmin Adjust Enable [3])
21.14 nTHERMTRIP
The nTHERMTRIP output pin can be configured to assert when any of the temperature sensors (remote
diodes 1-2, internal) is above its associated temperature limit.
The Thermtrip Enable register at offset CEh selects which reading(s) will cause the nTHERMTRIP signal to be active,
when the selected temperature(s) exceed in the associated limit registers (C4h for Remote Diode 1, C5h for Remote
diode 2, and C9h for Ambient temp) their pre-programmed limit.
An internal version of this output will also be used by the RESGEN block to generate a system reset pulse. More details
can be found in Section 16.0, "Reset Generation," on page 101.
21.14.1 NTHERMTRIP OPERATION
The nTHERMTRIP pin can be configured to assert when one of the temperature zones is above its associated nTHER-
MTRIP temperature limit (THERMTRIP Temp Limit Zone[3:1]). The Thermtrip temperature limit is a separate limit reg-
ister from the high limit used for setting the interrupt status bits for each zone.
The THERMTRIP Limit Zone[3:1] registers represent the upper temperature limit for asserting nTHERMTRIP for each
zone. These registers are defined as follows: If the monitored temperature for the zone exceeds the value set in the
associated THERMTRIP Temp Limit Zone[3:1], the corresponding bit in the THERMTRIP status register will be set. The
nTHERMTRIP pin may or may not be set depending on the state of the associated enable bits (in the THERM Output
Enable register).
Each zone may be individually enabled to assert the nTHERMTRIP pin (as an output).
The zone must exceed the limits set in the associated THERMTRIP Temp Limit Zone [3:1] register for two suc-
cessive monitoring cycles in order for the nTHERMTRIP pin to go active (and for the associated status bit to be
set).
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The following figures summarize the THERMTRIP operation in relation to the THERMTRIP status bits.
FIGURE 21-15:
NTHERMTRIP OUTPUT OPERATION
THERMTRIP
Status Reg
To
nTHERMTRIP
Pin
Zone 3 THERMTRIP Limit Exceeded
Zone 3 OUT_En
(THERMTRIP Output Enable [2])
OR
Zone 2 THERMTRIP Limit Exceeded
Zone 1 THERMTRIP Limit Exceeded
Zone 2 OUT_En
(THERMTRIP Output Enable [1])
Zone 1 OUT_En
(THERMTRIP Output Enable [0])
THERMTRIP_CTRL
(THERMTRIP Control [0])
21.14.2 FAN SPEED MONITORING
The chip monitors the speed of the fans by utilizing fan tachometer input signals from fans equipped with tachometer
outputs. The fan tachometer inputs are monitored by using the Fan Tachometer registers. These signals, as well as the
Fan Tachometer registers, are described below.
The tachometers will operate in one of two modes:
• Mode 1: Standard tachometer reading mode. This mode is used when the fan is always powered when the duty
cycle is greater than 00h.
• Mode 2: Enhanced tachometer reading mode. This mode is used when the PWM is pulsing the fan.
21.14.2.1 TACH Inputs
The tachometer inputs are implemented as digital input buffers with logic to filter out small glitches on the tach signal.
21.14.2.2 Selecting the Mode of Operation:
The mode is selected through the Mode Select bits located in the Tach Option register. This Mode Select bit is defined
as follows:
• 0=Mode 1: Standard tachometer reading mode
• 1=Mode 2: Enhanced tachometer reading mode
Default Mode of Operation:
• Mode 1
• Slow interrupt disabled (Don't force FFFEh)
• Tach interrupt enabled via enable bit
• Tach Limit = FFFFh
• Tach readings updated once a second
21.14.2.3 Mode 1 – Always Monitoring
Mode 1 is the simple case. In this mode, the Fan is always powered when it is ‘ON’ and the fan tachometer output
ALWAYS has a valid output. This mode is typically used if a linear DC Voltage control circuit drives the fan. In this mode,
the fan tachometer simply counts the number of 90kHz pulses between the programmed number of edges (default = 5
edges). The fan tachometer reading registers are continuously updated.
The counter is used to determine the period of the Fan Tachometer input pulse. The counter starts counting on the first
edge and continues counting until it detects the last edge or until it reaches FFFFh. If the programmed number of edges
is detected on or before the counter reaches FFFFh, the reading register is updated with that count value. If the counter
reaches FFFFh and no edges were detected a stalled fan event has occurred and the Tach Reading register will be set
to FFFFh. If one or more edges are detected, but less than the programmed number of edges, a slow fan event has
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occurred and the Tach Reading register will be set to either FFFEh or FFFFh depending on the state of the Slow Tach
bits located in the TACHx Options registers at offsets 90h - 93h. Software can easily compute the RPM value using the
tachometer reading value if it knows the number of edges per revolution.
Note 1: If the PWM output associated with a tach input is configured for the high frequency option then the tach input
must be configured for Mode 1.
2: Some enhanced features added to support Mode 2, are available to Mode 1 also. They are: programmable
number of tach edges and force tach reading register to FFFEh to indicate a SLOW fan.
3: Five edges or two tach pulses are generated per revolution.
4: If a tach input is left unconnected it must be configured for Mode 1.
21.14.2.4 Mode 2 – Monitor Tach input When PWM is ‘ON’
In this mode, the PWM is used to pulse the Fan motor of a 3-wire fan. 3-wire fans use the same power supply to drive
the fan motor and to drive the tachometer output logic. When the PWM is ‘ON’ the fan generates valid tach pulses. When
the PWM is not driving the Fan, the tachometer signal is not generated and the tach signal becomes indeterminate or
tristate. Therefore, Mode 2 only makes tachometer measurements when the associated PWM is driving high during an
update cycle. As a result, the Fan tachometer measurement is “synchronized” to the PWM output, such that it only looks
for tach pulses when the PWM is ‘ON’.
Note:
Any fan tachometer input may be associated with any PWM output (see Linking Fan Tachometers to PWMs
on page 155.)
During an update cycle, if an insufficient number of tachometer pulses are detected during this time period, the following
applies: If at least one edge but less than the programmed number of edges is detected, the fan is considered slow. If
no edge is detected, the fan is considered stopped.
Note 1: The interrupt status bits are set, if enabled, to indicate that a slow or stopped fan event has occurred when
the tach reading registers are greater than the tach limit registers.
2: At some duty cycles, the programmed number of edges will appear during some PWM High times, but not
all. If opportunistic mode is enabled, the tach logic will latch the count value any time it detects the pro-
grammed number of edges and reset the update counter. An interrupt will only be generated if no valid read-
ings were made during the programmed update time.
21.14.2.5 Assumptions (refer to Figure 21-16 - PWM and Tachometer Concept):
The Tachometer pulse generates 5 transitions per fan revolution (i.e., two fan tachometer periods per revolution, edges
26). One half of a revolution (one tachometer period) is equivalent to three edges (24 or 35). One quarter of a
revolution (one-half tachometer period) is equivalent to two edges. To obtain the fan speed, count the number of 90Khz
pulses that occurs between 2 edges i.e., 23, between 3 edges i.e., 24, or between 5 edges, i.e. 26 (the case of
9 edges is not shown). The time from 1-2 occurs through the guard time and is not to be used. For the discussion below,
an edge is a high-to-low or low-to-high transition (edges are numbered – refer to Figure 21-16 - PWM and Tachometer
Concept.
The Tachometer circuit begins monitoring the tach when the associated PWM output transitions high and the guard time
has expired. Each tach circuit will continue monitoring until either the “ON” time ends or the programmed number of
edges has been detected, whichever comes first.
The Fan Tachometer value may be updated every 300ms, 500ms, or 1000ms.
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FIGURE 21-16:
PWM AND TACHOMETER CONCEPT
Internal PWM
PWM “ON”
Signal
Guard time A
Window for
Valid Tach
Pulses
2
3
4
5
6
1
Tach
Pulses
Tach
Pulses
B
C
D
E
F
A
21.14.2.5.1
Fan Tachometer Options for Mode 2
• 2, 3, 5 or 9 “edges” to calculate the fan speed (Figure 21-16)
• Guard time A is programmable (8-63 clocks) to account for delays in the system (Figure 21-16)
• Suggested PWM frequencies for mode 2 are: 11.0 Hz, 14.6 Hz, 21.9 Hz, 29.3 Hz, 35.2 Hz, 44.0 Hz, 58.6 Hz,
87.7Hz
• Option to ignore first 3 tachometer edges after guard time
• Option to force tach reading register to FFFEh to indicate a slow fan.
21.14.2.6 Fan Tachometer Reading Registers:
The Tachometer Reading registers are 16 bits, unsigned. When one byte of a 16-bit register is read, the other byte
latches the current value until it is read, in order to ensure a valid reading. The order is LSB first, MSB second. The value
FFFFh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (this could be
triggered by a counter overflow). These registers are read only – a write to these registers has no effect.
Note 1: The Fan Tachometer Reading registers always return an accurate fan tachometer measurement, even
when a fan is disabled or non-functional.
2: FFFFh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (This
could be triggered by a counter overflow).
3: The Tachometer registers are read only – a write to these registers has no effect.
4: Mode 1 should be enabled and the tachometer limit register should be set to FFFFh if a tachometer input is
left unconnected.
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21.14.2.7 Programming Options for Each Tachometer Input
The features defined in this section are programmable via the TACHx Option registers located at offsets 90h-92h and
the PWMx Option registers located at offsets 94h-96h.
21.14.2.7.1
Tach Reading Update Time
In Mode 1, the Fan Tachometer Reading registers are continuously updated. In Mode 2, the fan tachometer registers
are updated every 300ms, 500msec, or 1000msec. This option is programmed via bits[1:0] in the PWMx Option register.
The PWM associated with a particular TACH(s) determines the TACH update time.
21.14.2.7.2
Programmed Number Of Tach Edges
In modes 1 & 2, the number of edges is programmable for 2, 3, 5 or 9 edges (i.e., ½ tachometer pulse, 1 tachometer
pulse, 2 tachometer pulses, 4 tachometer pulses). This option is programmed via bits[2:1] in the TachX Option register.
Note:
The “5 edges” case corresponds to two tachometer pulses, or 1 RPM for most fans. Using the other edge
options will require software to scale the values in the reading register to correspond to the count for 1
RPM.
21.14.2.7.3
Guard Time (Mode 2 Only)
The guard time is programmable from 8 to 63 clocks (90kHz). This option is programmed via bits[4:3] in the TachX
Option register.
21.14.2.7.4
Ignore first 3 tachometer edges (Mode 2 Only)
Option to ignore first 3 tachometer edges after guard time. This option is programmed for each tachometer via bits[2:0]
in the TACHx Option register. Default is do not ignore first 3 tachometer edges after guard time.
21.14.2.8 Summary of Operation for Modes 1 & 2
The following summarizes the detection cases:
• No edge occurs during the PWM ‘ON’ time: indicate this condition as a stalled fan
- The tachometer reading register contains FFFFh.
• One edge (or less than programmed number of edges) occurs during the PWM ‘ON’ time: indicate this con-
dition as a slow fan.
- If the SLOW bit is enabled, the tachometer reading register will be set to FFFEh to indicate that this is a slow
fan instead of a seized fan. Note that this operation also pertains to the case where the tachometer counter
reaches FFFFh before the programmed number of edges occurs.
- If the SLOW bit is disabled, the tachometer reading register will be set to FFFFh. In this case, no distinction is
made between a slow or seized fan.
Note:
The Slow Interrupt Enable feature (SLOW) is configured in the TACHx Options registers at offsets 90h to
93h.
• The programmed number of edges occurs:
- Mode 1: If the programmed number of edges occurs before the counter reaches FFFFh latch the tachometer
count
- Mode 2: If the programmed number of edges occurs during the PWM ‘ON’ time: latch the tachometer count
(see Note below).
Note 1: Whenever the programmed number of edges is detected, the edge detection ends and the state machine
is reset. The tachometer reading register is updated with the tachometer count value at this time. See
Detection of a Stalled Fan on page 154 for the exception to this behavior.
2: In the case where the programmed number of edges occurs during the “on”, the tachometer value is latched
when the last required edge is detected.
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21.14.2.9 Examples of Minimum RPMs Supported
The following tables show minimum RPMs that can be supported with the different parameters. The first table uses 3
edges and the second table uses 2 edges.
TABLE 21-5: MINIMUM RPM DETECTABLE USING 3 EDGES
PWM
Frequency
Pulse Width at Duty Cycle
(PWM “ON” Time)
Minimum RPM at Duty Cycle (Note 21-2)
(30/TTachPulse
)
100%
(MSEC)
25%
50%
(HZ)
(MSEC)
(MSEC)
(Note 21-1)
25%
50%
100%
87.7
58.6
44
2.85
4.27
5.68
7.1
5.7
11.36
17
10865
7175
5366
4279
3554
2648
1761
1325
5347
3554
2662
2126
1768
1319
878
2662
1774
1330
1063
885
8.53
11.36
14.2
22.64
28.3
34
35.2
29.3
21.9
14.6
11
8.53
11.42
17.12
22.73
17.06
22.83
34.25
45.45
45.48
68.23
90.55
661
440
661
332
Note 21-1
Note 21-2
100% duty cycle is 255/256
RPM=60/T , T
= T
/2. Using 3 edges for detection, T
= (PWM ”ON”
Revolution
TachPulse
Revolution
TachPulse
Time – Guard Time). Minimum RPM values shown use minimum guard time (88.88usec).
TABLE 21-6: MINIMUM RPM DETECTABLE USING 2 EDGES
PWM
Frequency
Pulse Width at Duty Cycle
(PWM “ON” Time)
Minimum RPM at Duty Cycle (Note 21-4)
(30/TTachPulse
)
100%
(MSEC)
25%
50%
(HZ)
(MSEC)
(MSEC)
(Note 21-3)
25%
50%
100%
87.7
58.6
44
2.85
4.27
5.68
7.1
5.7
11.36
17
5433
3588
2683
2139
1777
1324
881
2673
1777
1331
1063
884
1331
887
665
532
442
330
220
166
8.53
11.36
14.2
22.64
28.3
34
35.2
29.3
21.9
14.6
8.53
11.42
17.12
22.73
17.06
22.83
34.25
45.45
45.48
68.23
90.55
660
439
11
663
331
Note 21-3
100% duty cycle is 255/256
Note 21-4
RPM=60/T , T
= T
/2. Using 2 edges for detection, T
= 2*(PWM “ON”
Revolution
TachPulse
Revolution
TachPulse
Time-Guard Time). Minimum RPM values shown use minimum guard time (88.88usec).
21.14.2.10 Detection of a Stalled Fan
There is a fan failure bit (TACHx) in the interrupt status register used to indicate that a slow or stalled fan event has
occurred. If the tach reading value exceeds the value programmed in the tach limit register the interrupt status bit is set.
See Interrupt Status register 2 at offset 42h.
Note 1: The reading register will be forced to FFFFh if a stalled event occurs (i.e., stalled event =no edges detected.)
2: The reading register will be forced to either FFFFh or FFFEh if a slow fan event occurs. (i.e., slow event: 0
< #edges < programmed #edges). If the control bit, SLOW, located in the TACHx Options registers at offsets
90h - 93h, is set then FFFEh will be forced into the corresponding Tach Reading Register to indicate that
the fan is spinning slowly.
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3: The fan tachometer reading register stays at FFFFh in the event of a stalled fan. If the fan begins to spin
again, the tachometer logic will reset and latch the next valid reading into the tachometer reading register.
21.14.2.11 Fan Interrupt Status Bits
The status bits for the fan events are in Interrupt Status Register 2 (42h). These bits are set when the reading register
is above the tachometer minimum and the Interrupt Enable 2 (Fan Tachs) register bits are configured to enable Fan
Tach events. No interrupt status bits are set for fan events (even if the fan is stalled) if the associated tachometer mini-
mum is set to FFFFh (registers 54h-5Bh).
Note:
The Interrupt Enable 2 (Fan Tachs) register at offset 80h defaults to enabled for the individual tachometer
status events bits. The group Fan Tach nHWM_INT bit defaults to disabled. This bit needs to be set if Fan
Tach interrupts are to be generated on the external nHWM_INT pin.
See FIGURE 21-3: Interrupt Control on page 128.
21.14.3 LOCKED ROTOR SUPPORT FOR TACHOMETER INPUTS
All tachometer inputs support locked rotor input mode. In this mode, the tachometer input pin is not used as a tachom-
eter signal, but as a level signal. The active state of this signal (high or low) is the state that the fan’s locked rotor signal
indicates the locked condition.
The locked rotor signals that are supported are active high level and active low level. They are selectable for each
tachometer. If the pin goes to its programmed active state, the associated interrupt status bit will be set. In addition, if
properly configured, the nHWM_INT pin can be made to go active when the status bit is set.
The locked rotor input option is configured through the following bits:
• Tach1 Mode, bits[7:6] of Tach 1-3 Mode register
• Tach2 Mode, bits[5:4]of Tach 1-3 Mode register
• Tach3 Mode, bit[3:2] of Tach 1-3 Mode register
These bits are defined as follows:
• 00=normal operation (default)
• 01=locked rotor mode, active high signal
• 10=locked rotor mode, active low signal
• 11=undefined
21.14.4 LINKING FAN TACHOMETERS TO PWMS
The TACH/PWM Association Register at offset 81h is used to associate a Tachometer input with a PWM output. This
association has three purposes:
1. The auto fan control logic supports a feature called SpinUp Reduction. If SpinUp Reduction is enabled (SUREN
bit), the auto fan control logic will stop driving the PWM output high if the associated TACH input is operating
within normal parameters. (Note: SUREN bit is located in the Configuration Register at offset 7Fh)
2. To measure the tachometer input in Mode 2, the tachometer logic must know when the associated PWM is ‘ON’.
3. Inhibit fan tachometer interrupts when the associated PWM is ‘OFF’.
See the description of the PWM_TACH register. The default configuration is:
PWM1 -> FANTACH1
PWM2 -> FANTACH2
PWM3 -> FANTACH3
Note:
If a FANTACH is associated with a PWM operating in high frequency mode (see the Zonex Range/FANx
Frequency registers (5Fh-61h)) the tach monitoring logic must be configured for Mode 1 (see Bit[3] Mode
in FANTACHx Option Registers, 90h-92h).
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21.15 High Frequency PWM Options
Note:
If a fan with a tachometer output is driven by the high frequency PWM option, the tachometer must be mon-
itored in Mode 1 only.
21.15.1 PWM FREQUENCIES SUPPORTED
The SCH322x supports low frequency and high frequency PWMs. The low frequency options are 11.0Hz, 14.6Hz,
21.9Hz, 29.3Hz, 35.2Hz, 44.0Hz, 58.6Hz and 87.7Hz. The high frequency options are 15kHz, 20kHz, 25kHz and 30kHz.
All PWM frequencies are derived from the 14.318MHz clock input.
The frequency of the PWM output is determined by the Frequency Select bits[3:0]. The default PWM frequency is
25kHz.
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22.0 HARDWARE MONITORING REGISTER SET
These registers are accessed through an index and data register scheme using the HW_Reg_INDEX and HW_Reg_-
DATA registers located in the runtime register block at offset 70h and 71h from the address programmed in Logical
Device A. The Hardware Monitor Block registers are located at the indexed address shown in Table 22-1, "Register
Summary".
CAUTION: The HWM block is unsupported in the SCH3222 device. These registers, as well as the HW_Reg_INDEX
and HW_Reg_DATA registers at Runtime offsets 70h and 71h, are unsupported, and should not be accessed. Do not
attempt to change their configurations from their POR defaults, because doing so may cause unpredictable behavior
and/or excessive currents, and therefore may damage the device and/or the system.
Definition for the Lock column:
Yes = Register is made read-only when the lock bit is set; No = Register is not made read-only when the lock bit is set.
TABLE 22-1: REGISTER SUMMARY
Reg
Addr
Read/
Write
Reg Name
Bit 7
MSb
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSb
Default
Value
Lock
10h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
R/W
R
MCHP Test Register
7
RES
RES
RES
7
6
RES
RES
RES
6
5
RES
RES
RES
5
4
RES
RES
RES
4
3
RES
RES
RES
3
2
RES
RES
RES
2
1
RES
RES
RES
1
0
RES
RES
RES
0
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
No
Reserved
N/A
N/A
N/A
R
Reserved
R
Reserved
R
+2.5V
No
No
No
No
No
No
R
+1.5V Reading from Vccp pin
7
6
5
4
3
2
1
0
R
VCC
5V
7
6
5
4
3
2
1
0
R
7
6
5
4
3
2
1
0
R
12V
7
6
5
4
3
2
1
0
R
Remote Diode 1 (Zone 1) Temp
Reading
7
6
5
4
3
2
1
0
26h
27h
R
R
Internal Temp (Zone 2) Reading
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
00h
00h
No
No
Remote Diode 2 (Zone 3) Temp
Reading
28h
29h
2Ah
2Bh
2Ch
2Dh
R
R
R
R
R
R
FANTACH1 LSB
FANTACH1 MSB
FANTACH2 LSB
FANTACH2 MSB
FANTACH3 LSB
FANTACH3 MSB
7
15
7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
9
1
9
0
8
0
8
0
8
FFh
Note 22-8
No
No
No
No
No
No
FFh
Note 22-8
FFh
Note 22-8
15
7
14
6
13
5
12
4
11
3
10
2
FFh
Note 22-8
FFh
Note 22-8
15
14
13
12
11
10
FFh
Note 22-8
2Eh
2Fh
30h
R
R
Reserved
Reserved
RES
RES
7
RES
RES
6
RES
RES
5
RES
RES
4
RES
RES
3
RES
RES
2
RES
RES
1
RES
RES
0
00h
00h
N/A
No
No
R/W
Note 2
2-1
PWM1 Current Duty Cycle
Yes
Note 22- Note 2
10
00
2-1
31h
32h
R/W
Note 2
2-1
PWM2 Current Duty Cycle
PWM3 Current Duty Cycle
Reserved
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
N/A
Yes
Note 22- Note 2
10
00
2-1
R/W
Note 2
2-1
N/A
Note 22-
10
Yes
00
33-
R
RES
RES
RES
RES
RES
RES
RES
RES
00h
No
3Ch
3Dh
3Eh
3Fh
R
R
R
Device ID
Company ID
Revision
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
8Ch
5Ch
01h
No
No
No
2016-2017 Microchip Technology Inc.
DS00002121B-page 157
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 22-1: REGISTER SUMMARY (CONTINUED)
Reg
Addr
Read/
Write
Reg Name
Bit 7
MSb
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSb
Default
Value
Lock
40h
41h
42h
R/W
Note 2
2-2
Ready/Lock/Start
RES
INT23
ERR2
RES
RES
Vbat
Mon
OVRID READY LOCK START
04h
Yes
Note 2
2-2
Note 2
2-9
R/WC
Note 2
2-3
Interrupt Status Register 1
Interrupt Status Register 2
D2
AMB
RES
D1
5V
VCC
FAN-
Vccp
2.5V
12V
00h
Note 22-8
No
R/WC
Note 2
2-3
ERR1
FAN-
FAN-
RES
00h
No
TACH3 TACH2 TACH1
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
R
Reserved
2.5V Low limit
RES
RES
RES
RES
RES
3
RES
2
RES
RES
00h
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
81h
7Fh
81h
7Fh
81h
7Fh
FFh
FFh
FFh
FFh
FFh
FFh
00h
00h
62h
62h
62h
CBh
CBh
CBh
00h
No
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
No
R
7
6
5
4
1
0
R
2.5V High limit
7
6
5
4
3
2
1
0
R
Vccp Low limit
7
6
5
4
3
2
1
0
R
Vccp High limit
7
6
5
4
4
3
2
1
0
R
VCC Low limit
7
6
5
3
2
1
0
R
VCC High limit
7
6
5
4
3
2
1
0
R
5V Low limit
7
6
5
4
3
2
1
0
R
5V High limit
7
6
6
5
5
4
3
2
1
0
R
12V Low limit
7
7
4
3
2
1
0
R
12V High limit
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Remote Diode 1 Low Temp
Remote Diode 1 High Temp
Internal Diode Low Temp
Internal Diode High Temp
Remote Diode 2 Low Temp
Remote Diode 2 High Temp
FANTACH1 Minimum LSB
FANTACH1 Minimum MSB
FANTACH2 Minimum LSB
FANTACH2 Minimum MSB
FANTACH3 Minimum LSB
FANTACH3 Minimum MSB
Reserved
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
No
7
6
5
4
3
2
1
1
0
0
No
7
6
5
4
3
2
No
7
6
5
4
3
2
1
0
No
7
6
5
4
3
2
1
0
No
7
6
5
4
3
2
1
0
No
15
14
13
12
4
11
3
10
2
9
8
No
7
6
5
1
0
No
15
14
13
12
4
11
3
10
2
9
8
No
7
6
5
1
0
No
15
14
13
12
RES
RES
INV
INV
INV
RAN0
RAN0
RAN0
RES
11
RES
RES
10
RES
RES
9
8
No
RES
RES
ZON2
ZON2
ZON2
RAN3
RAN3
RAN3
RES
RES
ZON1
ZON1
ZON1
RAN2
RAN2
RAN2
RES1
RES
RES
ZON0
ZON0
ZON0
RAN1
RAN1
RAN1
RES1
RES
RES
SPIN1
SPIN1
SPIN1
FRQ1
FRQ1
FRQ1
RR1-1
RES
RES
SPIN0
SPIN0
SPIN0
FRQ0
FRQ0
FRQ0
RR1-0
No
R
Reserved
No
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM 1 Configuration
PWM 2 Configuration
PWM 3 Configuration
Zone 1 Range/PWM 1 Frequency
Zone 2 Range/PWM 2 Frequency
Zone 3 Range/PWM 3 Frequency
PWM1 Ramp Rate Control
SUEN1 SPIN2
SUEN2 SPIN2
SUEN3 SPIN2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
FRQ3
FRQ3
FRQ3
RR1E
FRQ2
FRQ2
FRQ2
RR1-2
RES1
Note 2
2-7
Note 2 Note 2
2-7
2-7
63h
64h
65h
66h
67h
R/W
R/W
R/W
R/W
R/W
PWM 2, PWM3 Ramp Rate Control
PWM 1 MINIMUM Duty Cycle
PWM 2 MINIMUM Duty Cycle
PWM 3 MINIMUM Duty Cycle
RR2E
RR2-2
RR2-1
RR2-0
RR3E
RR3-2
RR3-1
RR3-0
00h
80h
80h
80h
Yes
Yes
Yes
Yes
Yes
7
7
7
7
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
Zone 1 (Remote Diode 1) Low
Temp Limit
80h
Note 22-8
68h
69h
R/W
R/W
Zone 2 (Ambient) Low Temp Limit
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
80h
Note 22-8
Yes
Yes
Zone 3 (Remote Diode 2) Low
Temp Limit
80h
Note 22-8
6Ah
6Bh
6Ch
6Dh
6Eh
R/W
R/W
R/W
R
Zone 1 Temp Absolute Limit
Zone 2 Temp Absolute Limit
Zone 3 Temp Absolute Limit
Reserved
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
64h
64h
64h
00h
44h
Yes
Yes
Yes
No
7
6
5
4
3
2
1
0
RES
7
RES
6
RES
5
RES
4
RES
3
RES
2
RES
1
RES
0
R
MCHP Test Register
No
6Fh
R
MCHP Test Register
7
6
5
4
RES
RES
RES
RES
40h
No
DS00002121B-page 158
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 22-1: REGISTER SUMMARY (CONTINUED)
Reg
Addr
Read/
Write
Reg Name
Bit 7
MSb
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSb
Default
Value
Lock
70h
71h
72h
R
R
R
MCHP Test Register
MCHP Test Register
MCHP Test Register
TST7
TST7
TST7
TST6
TST6
TST6
TST5
TST5
TST5
TST4
TST4
TST4
TST3
TST3
TST3
TST2
TST2
TST2
TST1
TST1
TST1
TST0
TST0
TST0
N/A
N/A
N/A
No
No
No
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
R
R/W
R
MCHP Test Register
MCHP Test Register
MCHP Test Register
MCHP Test Register
MCHP Test Register
MCHP Test Register
MCHP Test Register
Reserved
RES
RES
RES
RES
RES
RES
TST7
RES
RES
AVG2
RES
RES
RES
RES
RES
RES
TST6
RES
RES
AVG1
RES
RES
RES
RES
RES
RES
TST5
RES
RES
AVG0
RES
RES
RES
RES
RES
RES
TST4
RES
RES
TST3
TST3
TST3
TST3
TST3
TST3
TST3
RES
TST2
TST2
TST2
TST2
TST2
TST2
TST2
RES
TST1
TST1
TST1
TST1
TST1
TST1
TST1
RES
TST0
TST0
TST0
TST0
TST0
TST0
TST0
RES
09h
09h
09h
09h
09h
09h
00h
00h
00h
40h
No
Yes
No
R/W
R
Yes
No
R/W
R/W
R
Yes
Yes
No
R
Reserved
RES
RES
RES
RES
No
R/W
Note 2
2-4
Special Function Register
MCHP
Note 2
2-6
MCHP INTEN
Note 2
2-6
MON-
MD
RES
Yes
Note 2
2-4
7Dh
7Eh
7Fh
R
Reserved
Interrupt Enable Voltages
Configuration
RES
VCC
INIT
RES
12V
RES
5V
RES
VTR
RES
RES
2.5V
RES
VBAT
RES
RES
VOLT
RES
00h
ECh
14h
No
Yes
Yes
R/W
R/W
VCCP
MCHP
Note 2 Note 2
2-6
MCHP
SURE
N
TRDY
Note 2
2-9
MON
_DN
com-
plete
moni-
tor
2-6
cycle
80h
R/W
Interrupt Enable (Fan Tachs)
RES
RES
RES
RES
FAN-
FAN-
FAN-
FAN-
0Eh
Yes
TACH3 TACH2 TACH1
TACH
81h
82h
R/W
R/W
TACH_PWM Association
Interrupt Enable (Temp)
RES
RES
RES
RES
T3H
RES
T3L
T2H
T2L
T1H
T1L
24h
0Eh
Yes
Yes
RES
D2EN
D1EN
AMB
TEMP
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
RWC
R
Interrupt Status Register 3
A/D Converter LSbs Reg 5
A/D Converter LSbs Reg 1
A/D Converter LSbs Reg 2
A/D Converter LSbs Reg 3
A/D Converter LSbs Reg 4
Reserved
RES
VTR.3
RD2.3
V12.3
V50.3
VCC.3
RES
RES
VTR.2
RD2.2
V12.2
V50.2
RES
VTR.1
RD2.1
V12.1
V50.1
RES
RES
RES
VBAT
VTR
00h
00h
00h
00h
00h
00h
00h
4Dh
4Dh
09h
09h
N/A
00h
04h
04h
04h
00h
0Ch
No
No
No
No
No
No
No
No
Yes
No
Yes
No
No
No
No
No
No
No
VTR.0 VBAT.3 VBAT.2 VBAT.1 VBAT.0
R
RD2.0
V12.0
V50.0
VCC.0
RES
RD1.3
AM.3
V25.3
VCP.3
RES
RD1.2
AM.2
V25.2
VCP.2
RES
RD1.1
AM.1
V25.1
VCP.1
RES
RD1.0
AM.0
V25.0
VCP.0
RES
R
R
R
VCC.2 VCC.1
R
RES
TST6
TST6
RES
RES
TST5
TST5
RES
R
MCHP Test Register
MCHP Test Register
MCHP Test Register
MCHP Test Register
MCHP Test Register
Reserved
RES
TST4
TST4
TST4
TST4
TST4
RES
TST3
TST3
TST3
TST3
TST3
RES
TST2
TST2
TST2
TST2
TST2
RES
TST1
TST1
TST1
TST1
TST1
RES
TST0
TST0
TST0
TST0
TST0
RES
R/W
R
RES
RES
R/W
R
RES
RES
RES
TST7
RES
TST6
RES
TST5
RES
R
R/W
R/W
R/W
R
FANTACH1 Option
FANTACH2 Option
FANTACH3 Option
Reserved
MCHP
MCHP
MCHP
RES
MCHP
MCHP
MCHP
RES
MCHP
MCHP
MCHP
RES
3EDG
3EDG
3EDG
RES
MODE
MODE
MODE
RES
EDG1
EDG1
EDG1
RES
EDG0
EDG0
EDG0
RES
SLOW
SLOW
SLOW
RES
R/W
PWM1 Option
RES
Note 2
2-5
RES
Note 2
2-5
OPP
GRD1
GRD0
SZEN UPDT1 UPDT0
95h
96h
R/W
R/W
PWM2 Option
PWM3 Option
RES
Note 2
2-5
RES
Note 2
2-5
OPP
OPP
GRD1
GRD1
GRD0
GRD0
SZEN UPDT1 UPDT0
0Ch
0Ch
No
No
RES
Note 2
2-5
RES
Note 2
2-5
SZEN UPDT1 UPDT0
97h
98h
99h
9Ah
R/W
R
MCHP Test Register
MCHP Test Register
VTR Reading
TST7
TST7
7
TST 6
TST 5
TST 4
TST3
TST3
3
TST2
TST2
2
TST1
TST1
1
TST0
TST0
0
5Ah
F1h
00h
00h
Yes
Yes
No
TST 6
TST 5
TST 4
R
6
6
5
5
4
4
R
VBAT Reading
7
3
2
1
0
No
9Bh
R
VTR Limit Low
7
6
5
4
3
2
1
0
00h
No
2016-2017 Microchip Technology Inc.
DS00002121B-page 159
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 22-1: REGISTER SUMMARY (CONTINUED)
Reg
Addr
Read/
Write
Reg Name
Bit 7
MSb
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSb
Default
Value
Lock
9Ch
9Dh
9Eh
9Fh
A0h
A1h
A2h
A3h
R/W
R/W
R/W
R
VTR Limit Hi
VBAT Limit Low
VBAT Limit Hi
Reserved
7
6
5
4
3
2
1
0
FFh
00h
FFh
00h
00h
00h
00h
No
No
No
No
No
No
No
Yes
7
6
5
4
3
2
1
0
RES
RES
RES
RES
TST7
RES
RES
RES
RES
TST6
RES
RES
RES
RES
TST5
RES
RES
RES
RES
TST4
RES
RES
RES
RES
TST3
RES
RES
RES
RES
TST2
RES
RES
RES
RES
TST1
RES
RES
RES
RES
TST0
R
Reserved
R
Reserved
R
Reserved
R/W
MCHP Test Register
00h
N/A
A4h
A5h
R
MCHP Test Register
TST7
TST6
D2
TST5
AMB
TST4
D1
TST3
5V
TST2
VCC
TST1
Vccp
TST0
2.5V
02h
No
No
R/WC
Interrupt Status 1 Secondary
INT23
00h
Note 22-8
A6h
R/WC
Interrupt Status 2 Secondary
ERR2
ERR1
RES
FAN-
FAN-
FAN-
RES
12V
00h
No
TACH3 TACH2 TACH1
Note 22-8
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
RWC
R
Interrupt Status 3 Secondary
Reserved
INS3
RES
RES
7
RES
RES
6
RES
RES
5
RES
RES
4
RES
RES
3
RES
RES
2
VBAT
RES
1
VTR
RES
0
00h
00h
00h
00h
00h
00h
00h
No
No
R/W
R/W
R/W
R
MCHP Test Register
MCHP Test Register
Tach 1-3 Mode
Yes
Yes
No
7
6
5
4
3
2
1
0
T1M1
RES
7
T1M0
RES
6
T2M1
RES
5
T2M0
RES
4
T3M1
RES
3
T3M0
RES
2
RES
RES
1
RES
RES
0
Reserved
No
R
MCHP Test Register
No
R/W
Top Temperature Remote Diode 1
(Zone 1)
7
6
5
4
3
2
1
0
2Dh
Note 22-8
Yes
AFh
R/W
Top Temperature Remote Diode 2
(Zone 3)
7
6
5
4
3
2
1
0
2Dh
Note 22-8
Yes
B0h
B1h
B2h
B3h
R
R
MCHP Test Register
MCHP Test Register
MCHP Test Register
RES
RES
RES
7
RES
RES
RES
6
RES
RES
RES
5
RES
RES
RES
4
RES
RES
RES
3
RES
RES
RES
2
RES
RES
RES
1
RES
RES
RES
0
00h
00h
00h
No
No
R
No
R/W
Top Temperature Ambient
(Zone 2)
2Dh
Note 22-8
Yes
B4h
B5h
R/W
R/W
Min Temp Adjust Temp RD1, RD2
R1ATP R1ATP R2ATP R2ATP
RES
RES
RES
RES
RES
RES
RES
RES
00h
Yes
Yes
1
0
1
0
Min Temp Adjust Temp and Delay
Amb
RES
RES
AMATP AMATP
AMAD1 AMAD0
00h
1
0
B6h
B7h
R/W
R/W
Min Temp Adjust Delay 1-2
Tmin Adjust Enable
R1AD1 R1AD0 R2AD1 R2AD0
RES
RES
00h
00h
Yes
Yes
RES
RES
RES
RES
RES
RES
TMIN_ TMIN_ TMIN_
ADJ_
EN2
TOP_
INT_
EN
ADJ_
EN1
ADJ_
ENA
B8h
R/WC
Top Temp Exceeded Status
RES
RES
RES
STS2
STS1
STSA
00h
No
Note 22-8
B9h
BAh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
00h
04h
No
R/W
MCHP Reserved
Yes
BBh
R
MCHP Reserved
7
6
5
4
3
2
1
0
00h
No
BCh
BDh
R
R
Reserved
RES
7
RES
6
RES
5
RES
4
RES
3
RES
2
RES
1
RES
0
00h
00h
No
No
MCHP Reserved
BEh
BFh
R
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
00h
00h
No
R/W
MCHP Reserved
Yes
C0h
C1h
R/W
R/W
MCHP Reserved
Thermtrip Control
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
00h
01h
Yes
Yes
THER-
MTRIP
_CTRL
C2h
C3h
C4h
R
R
Reserved
Reserved
RES
RES
7
RES
RES
6
RES
RES
5
RES
RES
4
RES
RES
3
RES
RES
2
RES
RES
1
RES
RES
0
00h
00h
7Fh
No
No
R/W
ThermTrip Temp Limit RD1 (Zone
1)
Yes
C5h
C6h
R/W
R
ThermTrip Temp Limit RD2 (Zone
3)
7
6
5
4
3
2
1
0
7Fh
00h
Yes
No
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
DS00002121B-page 160
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 22-1: REGISTER SUMMARY (CONTINUED)
Reg
Addr
Read/
Write
Reg Name
Bit 7
MSb
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSb
Default
Value
Lock
C7h
C8h
C9h
R
R
Reserved
Reserved
RES
RES
7
RES
RES
6
RES
RES
5
RES
RES
4
RES
RES
3
RES
RES
2
RES
RES
1
RES
RES
0
00h
00h
7Fh
No
No
R/W
ThermTrip Temp Limit Amb (Zone
2)
Yes
CAh
R/WC
ThermTrip Status
RES
RES
RES
RES
RES
RD 2
RD 1
AMB
00h
No
Note 22-8
CBh
CCh
CDh
CEh
R/W
R
ThermTrip Output Enable
Reserved
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RD 2
RES
RES
RES
RD 1
RES
RES
RES
AMB
RES
RES
RES
00h
00h
00h
00h
Yes
No
R
Reserved
No
R/W
MCHP Reserved
Yes
CF-
R/w
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
00h
No
D0h
D1h
R/W
R
PWM1 Max
Reserved
7
6
5
4
3
2
1
0
FFh
00h
Yes
No
D2h-
D5h
RES
RES
RES
RES
RES
RES
RES
RES
D6h
R/W
R
PWM2 Max
Reserved
7
6
5
4
3
2
1
0
FFh
00h
Yes
No
D7h-
DAh
RES
RES
RES
RES
RES
RES
RES
RES
DBh
R/W
R
PWM3 Max
Reserved
7
6
5
4
3
2
1
0
FFh
00h
Yes
No
DCh-
DFh
RES
RES
RES
RES
RES
RES
RES
RES
E0h
R/W
R
Enable LSbs for AutoFan
Reserved
RES
RES
7
RES
PWM3 PWM3 PWM2 PWM2 PWM1 PWM1
00h
00h
00h
00h
00h
00h
00h
00h
N/A
No
No
_n1
_n0
_n1
_n0
_n1
_n0
E1-
E8h
RES
RES
RES
RES
RES
RES
RES
E9h
EAh
EBh
ECh
EDh
EEh
FFh
R/W
R
MCHP Reserved
MCHP Reserved
MCHP Reserved
MCHP Reserved
MCHP Reserved
MCHP Reserved
MCHP Test Register
6
5
4
3
3
2
2
1
1
0
0
Yes
No
7
6
6
5
5
4
4
R
7
3
2
1
0
No
R/W
R/W
R/W
R
7
6
5
4
3
2
1
0
Yes
Yes
Yes
No
7
6
5
4
3
2
1
0
RES
TST7
RES
TST 6
RES
TST 5
RES
TST 4
RES
TST3
RES
TST2
RES
TST1
RES
TST0
Note:
MCHP Test Registers may be read/write registers. Writing these registers can cause unwanted results.
Note 22-1
Note 22-2
The PWMx Current Duty Cycle Registers are only writable when the associated fan is in manual
mode. In this case, the register is writable when the start bit is set, but not when the lock bit is set.
The Lock and Start bits in the Ready/Lock/Start register are locked by the Lock Bit. The OVRID bit
is always writable when the lock bit is set.
Note 22-3
Note 22-4
The Interrupt status register bits are cleared on a write of 1 if the corresponding event is not active.
The INTEN bit in register 7Ch is always writable, both when the start bit is set and when the lock bit
is set.
Note 22-5
Note 22-6
These Reserved bits are read/write bits. Writing these bits to a ‘1’ has no effect on the hardware.
MCHP bits may be read/write bits. Writing these bits to a value other than the default value may
cause unwanted results
Note 22-7
Note 22-8
Note 22-9
RES1 bits are defined as reads return 1, writes are ignored.
This register is reset to its default value when the PWRGD_PS signal transitions high.
This bit is reset to its default value when the PWRGD_PS signal transitions high.
Note 22-10 This register always reflects the state of the pin, unless it is in spinup. During spinup this register is
forced to 00h.
2016-2017 Microchip Technology Inc.
DS00002121B-page 161
SCH3227/SCH3226/SCH3224/SCH3222
22.1 Undefined Registers
The registers shown in the table above are the defined registers in the part. Any reads to undefined registers always
return 00h. Writes to undefined registers have no effect and do not return an error.
22.2 Defined Registers
22.2.1
REGISTER 10H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
10h
R/W
MCHP TEST
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
00h
Setting the Lock bit has no effect on this registers
This register must not be written. Writing this register may produce unexpected results.
22.2.2
REGISTERS 20-24H, 99-9AH: VOLTAGE READING
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
20h
R
R
R
R
R
R
R
2.5V Reading
Vccp Reading
VCC Reading
+5V Reading
+12V Reading
VTR Reading
Vbat Reading
7
7
7
7
7
7
7
6
6
6
6
6
6
6
5
5
5
5
5
5
5
4
4
4
4
4
4
4
3
3
3
3
3
3
3
2
2
2
2
2
2
2
1
1
1
1
1
1
1
0
0
0
0
0
0
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
21h
22h
23h
24h
99h
9Ah
The Voltage Reading registers reflect the current voltage of the voltage monitoring inputs. Voltages are presented in the
registers at ¾ full scale for the nominal voltage, meaning that at nominal voltage, each register will read C0h, except for
the Vbat input. Vbat is nominally a 3.0V input that is implemented on a +3.3V (nominal) analog input. Therefore, the
nominal reading for Vbat is AEh.
Note:
Vbat will only be monitored when the Vbat Monitoring Enable bit is set to ‘1’. Updating the Vbat register
automatically clears the Vbat Monitoring Enable bit.
TABLE 22-2: VOLTAGE VS. REGISTER READING
Register
Register
Reading at
Maximum
Voltage
Nominal
Voltage
Maximum
Voltage
Minimum Register Reading at
Input
Reading at
Voltage
Minimum Voltage
Nominal Voltage
VTR
3.3V
3.0V
C0h
AEh
4.38V
4.38V
FFh
FFh
0V
0V
00h
00h
Vbat
(Note 22-
11)
5.0V
Vccp
VCC
2.5V
12V
5.0V
1.5V
3.3V
2.5V
12.0V
C0h
C0h
C0h
C0h
C0h
6.64V
2.00V
4.38V
3.32V
16.00V
FFh
FFh
FFh
FFh
FFh
0V
0V
0V
0V
0V
00h
00h
00h
00h
00h
Note 22-11 Vbat is a nominal 3.0V input source that has been implemented on a 3.3V analog voltage monitoring
input.
The Voltage Reading registers will be updated automatically by the device with a minimum frequency of 4Hz if the aver-
age bits located in the Special Function register at offset 7Ch are set to 001. These registers are read only – a write to
these registers has no effect.
DS00002121B-page 162
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
22.2.3
REGISTERS 25-27H: TEMPERATURE READING
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
25h
R
R
R
Remote Diode 1 (Zone 1) Temp
Reading
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
N/A
N/A
N/A
26h
27h
Internal Diode (Zone 2) Temp Read-
ing
Remote Diode 2 (Zone 3) Temp
Reading
The Temperature Reading registers reflect the current temperatures of the internal and remote diodes. Remote Diode
1 Temp Reading register reports the temperature measured by the Remote1- and Remote1+ pins, Remote Diode 2
Temp Reading register reports the temperature measured by the Remote2- and Remote2+ pins, and the Internal Diode
Temp Reading register reports the temperature measured by the internal (ambient) temperature sensor. Current tem-
peratures are represented as 12 bit, 2’s complement, signed numbers in Celsius. The 8MSbs are accessible in the tem-
perature reading registers. Table 22-3 shows the conversion for the 8-bit reading value shown in these registers. The
extended precision bits for these readings are accessible in the A/D Converter LSBs Register (85h-86h). The Tempera-
ture Reading register will return a value of 80h if the remote diode pins are not implemented by the board designer or
are not functioning properly (this corresponds to the diode fault interrupt status bits). The Temperature Reading registers
will be updated automatically by the SCH322x Chip with a minimum frequency of 4Hz.
Note:
These registers are read only – a write to these registers has no effect.
Each of the temperature reading registers are mapped to a zone. Each PWM may be programmed to operate in the
auto fan control operating mode by associating a PWM with one or more zones. The following is a list of the zone asso-
ciations.
• Zone 1 is controlled by Remote Diode 1 Temp Reading
• Zone 2 is controlled by Internal Temp Reading (Ambient Temperature Sensor)
• Zone 3 is controlled by Remote Diode 2 Temp Reading
Note:
To read a 12-bit reading value, software must read in the order of MSB then LSB. If several readings are
being read at the same time, software can read all the MSB registers then the corresponding LSB registers.
For example: Read RD1 Reading, RD2 Reading, then A/D Converter LSbs Reg1, which contains the LSbs
for RD1 and RD2.
TABLE 22-3: TEMPERATURE VS. REGISTER READING
Temperature
Reading (DEC)
Reading (HEX)
-127c
-127
81h
.
.
.
.
.
.
.
.
.
-50c
-50
CEh
.
.
.
.
.
.
.
.
.
0c
0
00h
.
.
.
.
.
.
.
.
.
50c
50
32h
.
.
.
.
.
.
.
.
.
127c
127
7Fh
80h
(SENSOR ERROR)
2016-2017 Microchip Technology Inc.
DS00002121B-page 163
SCH3227/SCH3226/SCH3224/SCH3222
22.2.4
REGISTERS 28-2DH: FAN TACHOMETER READING
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
28h
R
R
R
R
R
R
FANTACH1 LSB
FANTACH1 MSB
FANTACH2 LSB
FANTACH2 MSB
FANTACH3 LSB
FANTACH3 MSB
7
15
7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
9
1
9
0
8
0
8
0
8
FFh
FFh
FFh
FFh
FFh
FFh
29h
2Ah
2Bh
15
7
14
6
13
5
12
4
11
3
10
2
2Ch
2Dh
15
14
13
12
11
10
This register is reset to its default value when PWRGD_PS is asserted.
The Fan Tachometer Reading registers contain the number of 11.111s periods (90KHz) between full fan revolutions.
Fans produce two tachometer pulses per full revolution. These registers are updated at least once every second.
This value is represented for each fan in a 16 bit, unsigned number.
The Fan Tachometer Reading registers always return an accurate fan tachometer measurement, even when a fan is
disabled or non-functional, including when the start bit=0.
When one byte of a 16-bit register is read, the other byte latches the current value until it is read, in order to ensure a
valid reading. The order is LSB first, MSB second.
FFFFh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (This could be
triggered by a counter overflow).
These registers are read only – a write to these registers has no effect.
22.2.5
REGISTERS 30-32H: CURRENT PWM DUTY
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
30h
PWM1 Current Duty Cycle
7
7
7
6
5
4
3
2
1
0
0
0
N/A
N/A
N/A
R/W
(Note 22-
12)
31h
32h
PWM2 Current Duty Cycle
PWM3 Current Duty Cycle
6
6
5
5
4
4
3
3
2
2
1
1
R/W
(Note 22-
12)
R/W
(Note 22-
12)
Note 22-12 These registers are only writable when the associated fan is in manual mode. These registers
become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
The Current PWM Duty registers store the duty cycle that the chip is currently driving the PWM signals at. At initial
power-on, the duty cycle is 100% and thus, when read, this register will return FFh. After the Ready/Lock/Start Register
Start bit is set, this register and the PWM signals are updated based on the algorithm described in the Auto Fan Control
Operating Mode section and the Ramp Rate Control logic, unless the associated fan is in manual mode – see below.
Note:
When the device is configured for Manual Mode, the Ramp Rate Control logic should be disabled.
When read, the Current PWM Duty registers return the current PWM duty cycle for the respective PWM signal.
These registers are read only – a write to these registers has no effect.
Note:
If the current PWM duty cycle registers are written while the part is not in manual mode or when the start
bit is zero, the data will be stored in internal registers that will only be active and observable when the start
bit is set and the fan is configured for manual mode. While the part is not in manual mode and the start bit
is zero, the current PWM duty cycle registers will read back FFh.
DS00002121B-page 164
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
Manual Mode (Test Mode)
In manual mode, when the start bit is set to 1 and the lock bit is 0, the current duty cycle registers are writeable to control
the PWMs.
Note:
When the lock bit is set to 1, the current duty cycle registers are Read-Only.
The PWM duty cycle is represented as follows:
TABLE 22-4: PWM DUTY VS REGISTER READING
Current Duty
Value (Decimal)
Value (HEX)
0%
0
00h
25%
50%
64
40h
80h
FFh
128
255
100%
During spin-up, the PWM duty cycle is reported as 0%.
Note 1: The PWMx Current Duty Cycle always reflects the current duty cycle on the associated PWM pin.
2: The PWMx Current Duty Cycle register is implemented as two separate registers: a read-only and a write-
only. When a value is written to this register in manual mode there will be a delay before the programmed
value can be read back by software. The hardware updates the read-only PWMx Current Duty Cycle register
on the beginning of a PWM cycle. If Ramp Rate Control is disabled, the delay to read back the programmed
value will be from 0 seconds to 1/(PWM frequency) seconds. Typically, the delay will be 1/(2*PWM fre-
quency) seconds.
22.2.6
REGISTER 3DH: DEVICE ID
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
3Dh
R
Device ID
7
6
5
4
3
2
1
0
8Ch
The Device ID register contains a unique value to allow software to identify which device has been implemented in a
given system.
22.2.7
REGISTER 3EH: COMPANY ID
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
3Eh
R
Company ID
7
6
5
4
3
2
1
0
5Ch
The company ID register contains a unique value to allow software to identify Microchip devices that been implemented
in a given system.
22.2.8
REGISTER 3FH: REVISION
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
3Fh
R
Revision
7
6
5
4
3
2
1
0
01h
The Revision register contains the current version of this device.
The register is used by application software to identify which version of the device has been implemented in the given
system. Based on this information, software can determine which registers to read from and write to. Further, application
software may use the current stepping to implement work-arounds for bugs found in a specific silicon stepping.
This register is read only – a write to this register has no effect.
2016-2017 Microchip Technology Inc.
DS00002121B-page 165
SCH3227/SCH3226/SCH3224/SCH3222
22.2.9
REGISTER 40H: READY/LOCK/START MONITORING
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
40h
R/W
Ready/Lock/Start
RES
RES
RES
RES
OVRID
READY
LOCK
Note 22
-13
START
04h
Note 22-13 This LOCK bit is cleared when PWRGD_PS is asserted.
Setting the Lock bit makes the Lock and Start bits read-only.
Bit
Name
R/W
Default
Description
0
START
R/W
0
When software writes a 1 to this bit, the SCH322x enables
monitoring and PWM output control functions based on the
limit and parameter registers. Before this bit is set, the part
does not update register values. Whenever this bit is set to
0, the monitoring and PWM output control functions are
based on the default limits and parameters, regardless of the
current values in the limit and parameter registers. The
SCH322x preserves the values currently stored in the limit
and parameter registers when this bit is set or cleared. This
bit becomes read only when the Lock bit is set.
Note 1: When this bit is 0, all fans are on full 100% duty
cycle, i.e., PWM pins are high for 255 clocks, low
for 1 clock. When this bit is 0, the part is not moni-
toring.
2: It is suggested that software clear the START bit
and exit auto fan control mode before modifying
any fan configuration registers. After clearing the
START bit, software should wait for a period of one
90kHz-10% clock (~12.5usec) before setting the
START bit back to ‘1’ to ensure the fan logic exited
auto mode when START was cleared.
1
2
LOCK
R/W
Note 22-14
0
0
Setting this bit to 1 locks specified limit and parameter
registers. Once this bit is set, limit and parameter registers
become read only and will remain locked until the device is
powered off. This register bit becomes read only once it is
set.
READY
R
The SCH322x sets this bit automatically after the part is fully
powered up, has completed the power-up-reset process, and
after all A/D converters are functioning (all bias conditions for
the A/Ds have stabilized and the A/Ds are in operational
mode). (Always reads back ‘1’.)
3
4
OVRID
R/W
R/W
0
0
If this bit is set to 1, all PWM outputs go to 100% duty cycle
regardless of whether or not the lock bit is set.
VBAT Mon
The Vbat Monitoring Enable bit determines if Vbat will be
monitored on the next available monitoring cycle.
This is a read/write bit. Writing this bit to a ‘1’ will enable the
Vbat input to be monitored on the next available monitoring
cycle. Writing this bit to a ‘0’ has no effect. This bit is cleared
on an HVTR POR or when the Vbat register is updated.
Software can poll this bit for a ‘0’ after setting it to a ‘1’ to
determine when the Vbat register has been updated.
0 = Vbat input is not being monitored (default)
1 = Vbat input is being monitored
Note:
The lock bit has no effect on this register bit.
5-7
Reserved
R
0
Reserved
Note 22-14 This bit is set by software and cleared by hardware. Writing a ‘0’ to this register has no effect.
DS00002121B-page 166
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
Note 22-15 There is a start-up time of up to 301.5ms (default - see Table 21-2, “ADC Conversion Sequence,” on
page 126) for monitoring after the start bit is set to ‘1’, during which time the reading registers are
not valid. Software can poll the TRDY bit located in the Configuration Register (7Fh) to determine
when the voltage and temperature readings are valid.The following summarizes the operation of the
part based on the Start bit:
1. If Start bit = '0' then:
a) Fans are set to Full On.
b) No temperature or fan tach monitoring is performed. The values in the reading registers will be N/A (Not
Applicable), which means these values will not be considered valid readings until the Start bit = '1'. The
exception to this is the Tachometer reading registers, which always give the actual reading on the TACH
pins.
c) No Status bits are set.
2. If Start bit = '1'
a) All fan control and monitoring will be based on the current values in the registers. There is no need to pre-
serve the default values after software has programmed these registers because no monitoring or auto fan
control will be done when Start bit = '0'.
b) Status bits may be set.
Note:
Once programmed, the register values will be saved when start bit is reset to ‘0’.
22.2.10 REGISTER 41H: INTERRUPT STATUS REGISTER 1
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
41h
R/WC
Interrupt Status 1
INT2
Note 22
-16
D2
AMB
D1
5V
VCC
Vccp
2.5V
00h
Note 22-16 This is a read-only bit. Writing ‘1’ to this bit has no effect.
Note 1: This register is reset to its default value when the PWRGD_PS signal transitions high.
2: The is a read/write-to-clear register. Bits[6:4] are cleared on a write of one if the temperature event is no
longer active. Writing a zero to these bits has no effect.
Bit[7] INT2
This bit indicates that a status bit is set in the Interrupt Status Register 2 Register. Therefore, S/W can poll this register,
and only if bit 7 is set does the other registers need to be read. This bit is cleared (set to 0) automatically by the device
if there are no bits set in the Interrupt Status Register 2.
Bits[6:0] Individual Status Bits
Bits[6:0] of the Interrupt Status Register 1 are automatically set by the device whenever the measured temperature on
Remote Diode 1, Internal Diode, or the Remote Diode 2 Temperature violates the limits set in the corresponding tem-
perature limit registers. These individual status bits remain set until the bit is written to one by software or until the indi-
vidual enable bit is cleared, even if the temperatures no longer violate the limits set in the limit registers.
• Clearing the status bits by a write of ‘1’
- The voltage status bits are cleared (set to 0) automatically by the SCH322x after they are written to one by
software, if the voltage readings no longer violate the limit set in the limit registers. See Registers 44-4Dh,
9B-9Eh: Voltage Limit Registers on page 169.
- The temperature status bits are cleared (set to 0) automatically by the SCH322x after they are written to one
by software, if the temperature readings no longer violate the limit set in the limit registers. See Registers 4E-
53h: Temperature Limit Registers on page 170.
• Clearing the status bits by clearing the individual enable bits.
- Clearing or setting the individual enable bits does not take effect unless the START bit is 1. No interrupt status
events can be generated when START=0 or when the individual enable bit is cleared. If the status bit is one
and the START bit is one then clearing the individual enable bit will immediately clear the status bit. If the sta-
tus bit is one and the START bit is zero then clearing the individual enable bit will have no effect on the status
bit until the START bit is set to one. Setting the START bit to one when the individual enable bit is zero will
2016-2017 Microchip Technology Inc.
DS00002121B-page 167
SCH3227/SCH3226/SCH3224/SCH3222
clear the status bit. Setting or clearing the START bit when the individual enable bit is one has no effect on the
status bits.
Note 1: The individual enable bits for D2, AMB, and D1 are located in the Interrupt Enable 3 (Temp) register at offset
82h.
2: Clearing the group Temp enable bit or the global INTEN enable bit has no effect on the status bits.
Bit
Name
R/W
Default
Description
0
2.5V_Error R/WC
Vccp_Error R/WC
VCC_Error R/WC
0
The SCH322x automatically sets this bit to 1 when the 2.5V input
voltage is less than or equal to the limit set in the 2.5V Low Limit
register or greater than the limit set in the 2.5V High Limit register.
1
2
3
4
0
0
0
0
The SCH322x automatically sets this bit to 1 when the Vccp input
voltage is less than or equal to the limit set in the Vccp Low Limit
register or greater than the limit set in the Vccp High Limit register.
The SCH322x automatically sets this bit to 1 when the VCC input
voltage is less than or equal to the limit set in the VCC Low Limit
register or greater than the limit set in the VCC High Limit register.
5V_Error
R/WC
R/WC
The SCH322x automatically sets this bit to 1 when the 5V input voltage
is less than or equal to the limit set in the 5V Low Limit register or
greater than the limit set in the 5V High Limit register.
Remote
Diode 1
The SCH322x automatically sets this bit to 1 when the temperature
input measured by the Remote1- and Remote1+ is less than or equal
to the limit set in the Remote Diode 1 Low Temp register or greater than
the limit set in Remote Diode 1 High Temp register.
Limit Error
5
6
7
Internal
Sensor Limit
Error
R/WC
R/WC
0
0
0
The SCH322x automatically sets this bit to 1 when the temperature
input measured by the internal temperature sensor is less than or equal
to the limit set in the Internal Low Temp register or greater than the limit
set in the Internal High Temp register.
Remote
Diode 2
Limit Error
The SCH322x automatically sets this bit to 1 when the temperature
input measured by the Remote2- and Remote2+ is less than or equal
to the limit set in the Remote Diode 2 Low Temp register or greater than
the limit set in the Remote Diode 1 High Temp register.
INT2 Event R/WC
Active
The device automatically sets this bit to 1 when a status bit is set in the
Interrupt Status Register 2.
22.2.11 REGISTER 42H: INTERRUPT STATUS REGISTER 2
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
42h
R/WC
Interrupt Status Register 2
ERR2
ERR1
RES
FAN-
FAN-
FAN-
RES
12V
00h
TACH3
TACH2
TACH1
Note 1: This register is reset to its default value when the PWRGD_PS signal transitions high.
2: This is a read/write-to-clear register. The status bits are cleared on a write of one if the event causing the
interrupt is no longer active. Writing a zero to these bits has no effect.
The Interrupt Status Register 2 bits is automatically set by the device whenever a tach reading value is above the min-
imum value set in the tachometer minimum registers or when a remote diode fault occurs. When a remote diode fault
occurs (if the start bit is set) 80h will be loaded into the associated temperature reading register, which causes the asso-
ciated diode limit error bit to be set (see Register 41h: Interrupt Status Register 1 on page 167) in addition to the diode
fault bit (ERRx). These individual status bits remain set until the bit is written to one by software or until the individual
enable bit is cleared, even if the event no longer persists.
• Clearing the status bits by a write of ‘1’
- The FANTACHx status bits are cleared (set to 0) automatically by the SCH322x after they are written to one
by software, if the FANTACHx reading register no longer violates the programmed FANTACH Limit. (See
Registers 28-2Dh: Fan Tachometer Reading on page 164 and Registers 54-59h: Fan Tachometer Low Limit
on page 171)
DS00002121B-page 168
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
- The ERRx status bits are cleared (set to 0) automatically by the SCH322x after they are written to one by soft-
ware, if the Diode Fault condition no longer exists. The remote diode fault bits do not get cleared while the
fault condition exists.
• Clearing the status bits by clearing the individual enable bits.
- Clearing or setting the individual enable bits does not take effect unless the START bit is 1. No interrupt status
events can be generated when START=0 or when the individual enable bit is cleared. If the status bit is one
and the START bit is one then clearing the individual enable bit will immediately clear the status bit. If the sta-
tus bit is one and the START bit is zero then clearing the individual enable bit will have no effect on the status
bit until the START bit is set to one. Setting the START bit to one when the individual enable bit is zero will
clear the status bit. Setting or clearing the START bit when the individual enable bit is one has no effect on the
status bits.
Note 1: The individual enable bits for FANTACH[1:3] are located in Register 80h: Interrupt Enable 2 Register on
page 181. The ERRx bits are enabled by the Remote Diode Limit error bits located in Register 82h: Interrupt
Enable 3 Register on page 182
2: Clearing the group FANTACH or Temp enable bits or the global INTEN enable bit has no effect on the status
bits.
Bit
Name
R/W
Default
Description
0
+12v_Error
R
0
The SCH322x automatically sets this bit to 1 when the 12V input
voltage is less than or equal to the limit set in the 12V Low Limit
register or greater than the limit set in the 12V High Limit register.
1
2
Reserved
R
0
0
Reserved
FANTACH1 R/WC
Slow/Stalled
The SCH322x automatically sets this bit to 1 when the FANTACH1
input reading is above the value set in the Tach1 Minimum MSB and
LSB registers.
3
4
FANTACH2 R/WC
Slow/Stalled
0
0
The SCH322x automatically sets this bit to 1 when the FANTACH2
input reading is above the value set in the Tach2 Minimum MSB and
LSB registers.
FANTACH3 R/WC
Slow/Stalled
The SCH322x automatically sets this bit to 1 when the FANTACH3
input reading is above the value set in the Tach3 Minimum MSB and
LSB registers.
5
6
Reserved
R
0
0
Reserved
Remote
Diode 1 Fault
R/WC
The SCH322x automatically sets this bit to 1 when there is either a
short or open circuit fault on the Remote1+ or Remote1- thermal diode
input pins.
If the START bit is set and a fault condition exists, the Remote Diode
1 reading register will be forced to 80h.
7
Remote
Diode 2 Fault
R/WC
0
The SCH322x automatically sets this bit to 1 when there is either a
short or open circuit fault on the Remote2+ or Remote2- thermal diode
input pins.
If the START bit is set and a fault condition exists, the Remote Diode
2 reading register will be forced to 80h.
22.2.12 REGISTERS 44-4DH, 9B-9EH: VOLTAGE LIMIT REGISTERS
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2.5V Low Limit
2.5V High Limit
Vccp Low Limit
Vccp High Limit
VCC Low Limit
VCC High Limit
5V Low Limit
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
5V High Limit
12V Low Limit
12V High Limit
2016-2017 Microchip Technology Inc.
DS00002121B-page 169
SCH3227/SCH3226/SCH3224/SCH3222
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
9Bh
9Ch
9Dh
9Eh
R/W
R/W
R/W
R/W
VTR Low Limit
VTR High Limit
Vbat Low Limit
Vbat High Limit
7
7
7
7
6
6
6
6
5
5
5
5
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
0
0
0
0
00h
FFh
00h
FFh
Setting the Lock bit has no effect on these registers.
If a voltage input either exceeds the value set in the voltage high limit register or falls below or equals the value set in
the voltage low limit register, the corresponding bit will be set automatically in the interrupt status registers (41-42h, 83h).
Voltages are presented in the registers at ¾ full scale for the nominal voltage, meaning that at nominal voltage, each
register will read C0h, except for the Vbat input. Vbat is nominally a 3.0V input that is implemented on a +3.3V (nominal)
analog input. Therefore, the nominal reading for Vbat is AEh.
Note:
Vbat will only be monitored when the Vbat Monitoring Enable bit is set to ‘1’. Updating the Vbat reading
register automatically clears the Vbat Monitoring Enable bit.
TABLE 22-5: VOLTAGE LIMITS VS. REGISTER SETTING
Register Reading
Nominal
Voltage
Maximum Register Reading at Minimum Register Reading at
Input
at Nominal
Voltage
Voltage
Maximum Voltage
Voltage
Minimum Voltage
VTR
3.3V
3.0V
C0h
AEh
4.38V
4.38V
FFh
FFh
0V
0V
00h
00h
Vbat
(Note 2
2-17)
2.5V
Vccp
VCC
5V
5.0V
2.25V
3.3V
C0h
C0h
C0h
C0h
C0h
6.64V
3.00V
4.38V
6.64V
16.00V
FFh
FFh
FFh
FFh
FFh
0V
0V
0V
0V
0V
00h
00h
00h
00h
00h
5.0V
12V
12.0V
Note 22-17 Vbat is a nominal 3.0V input source that has been implemented on a 3.3V analog voltage monitoring
input.
22.2.13 REGISTERS 4E-53H: TEMPERATURE LIMIT REGISTERS
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
4Eh
4Fh
50h
51h
52h
53h
R/W
R/W
R/W
R/W
R/W
R/W
Remote Diode 1 Low Temp
Remote Diode 1 High Temp
Ambient Low Temp
7
7
7
7
7
7
6
6
6
6
6
6
5
5
5
5
5
5
4
4
4
4
4
4
3
3
3
3
3
3
2
2
2
2
2
2
1
1
1
1
1
1
0
0
0
0
0
0
81h
7Fh
81h
7Fh
81h
7Fh
Ambient High Temp
Remote Diode 2 Low Temp
Remote Diode 2 High Temp
Setting the Lock bit has no effect on these registers.
If an external temperature input or the internal temperature sensor either exceeds the value set in the high limit register
or is less than or equal to the value set in the low limit register, the corresponding bit will be set automatically by the
SCH322x in the Interrupt Status Register 1 (41h). For example, if the temperature reading from the Remote1- and
Remote1+ inputs exceeds the Remote Diode 1 High Temp register limit setting, Bit[4] D1 of the Interrupt Status Register
1 will be set. The temperature limits in these registers are represented as 8 bit, 2’s complement, signed numbers in Cel-
sius, as shown below in Table 22-6.
DS00002121B-page 170
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SCH3227/SCH3226/SCH3224/SCH3222
TABLE 22-6: TEMPERATURE LIMITS VS. REGISTER SETTINGS
Temperature
Limit (DEC)
Limit (HEX)
-127c
-127
81h
.
.
.
.
.
.
.
.
.
-50c
-50
CEh
.
.
.
.
.
.
.
.
.
0c
0
00h
.
.
.
.
.
.
.
.
.
50c
50
32h
.
.
.
.
.
.
.
.
.
127c
127
7Fh
22.2.14 REGISTERS 54-59H: FAN TACHOMETER LOW LIMIT
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
54h
55h
56h
57h
58h
59h
R/W
R/W
R/W
R/W
R/W
R/W
FANTACH1 Minimum LSB
FANTACH1 Minimum MSB
FANTACH2 Minimum LSB
FANTACH2 Minimum MSB
FANTACH3 Minimum LSB
FANTACH3 Minimum MSB
7
15
7
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
9
1
9
0
8
0
8
0
8
FFh
FFh
FFh
FFh
FFh
FFh
15
7
14
6
13
5
12
4
11
3
10
2
15
14
13
12
11
10
Setting the Lock bit has no effect on these registers.
The Fan Tachometer Low Limit registers indicate the tachometer reading under which the corresponding bit will be set
in the Interrupt Status Register 2 register. In Auto Fan Control mode, the fan can run at high speeds (100% duty cycle),
so care should be taken in software to ensure that the limit is low enough not to cause sporadic alerts. Note that an
interrupt status event will be generated when the tachometer reading is greater than the minimum tachometer limit.
The fan tachometer will not cause a bit to be set in the interrupt status register if the current value in the associated
Current PWM Duty registers is 00h or if the PWM is disabled via the PWM Configuration Register.
Interrupts will never be generated for a fan if its tachometer minimum is set to FFFFh.
22.2.15 REGISTERS 5C-5EH: PWM CONFIGURATION
Register
Address
Read/Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
5Ch
5Dh
5Eh
R/W
R/W
R/W
PWM 1 Configuration
PWM 2 Configuration
PWM 3 Configuration
ZON2
ZON2
ZON2
ZON1
ZON1
ZON1
ZON0
ZON0
ZON0
INV
INV
INV
SUEN1
SUEN2
SUEN3
SPIN2
SPIN2
SPIN2
SPIN1
SPIN1
SPIN1
SPIN0
SPIN0
SPIN0
62h
62h
62h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
Bits [7:5] Zone/Mode
Bits [7:5] of the PWM Configuration registers associate each PWM with a temperature zone.
• When in Auto Fan Mode, the PWM will be assigned to a zone, and its PWM duty cycle will be adjusted according
to the temperature of that zone. If ‘Hottest’ option is selected (101 or 110), the PWM will be controlled by the hot-
2016-2017 Microchip Technology Inc.
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test of zones 2 and 3, or of zones 1, 2, and 3. If one of these options is selected, the PWM is controlled by the lim-
its and parameters for the zone that requires the highest PWM duty cycle, as computed by the auto fan algorithm.
• When in manual control mode, the PWMx Current Duty Cycle Registers (30h-32h) become Read/Write. It is then
possible to control the PWM outputs with software by writing to these registers. See PWMx Current Duty Cycle
Registers description.
• When the fan is disabled (100) the corresponding PWM output is driven low (or high, if inverted).
• When the fan is Full On (011) the corresponding PWM output is driven high (or low, if inverted).
Note 1: Zone 1 is controlled by Remote Diode 1 Temp Reading register
2: Zone 2 is controlled by the Ambient Reading Register.
3: Zone 3 is controlled by Remote Diode 2 Temp Reading register
TABLE 22-7: FAN ZONE SETTING
ZON[7:5]
PWM Configuration
000
001
010
011
100
101
110
111
Fan on zone 1 auto
Fan on zone 2 auto
Fan on zone 3 auto
Fan always on full
Fan disabled
Fan controlled by hottest of zones 2,3
Fan controlled by hottest of zones 1,2,3
Fan manually controlled
Bit [4] PWM Invert
Bit [4] inverts the PWM output. If set to 1, 100% duty cycle will yield an output that is low for 255 clocks and high for 1
clock. If set to 0, 100% duty cycle will yield an output that is high for 255 clocks and low for 1 clock.
Bit [3] Forced Spin-up Enable
Bit [3] enables the forced spin up option for a particular PWM. If set to 1, the forced spin-up feature is enabled for the
associated PWM. If set to 0, the forced spin-up feature is disabled for the associated PWM.
APPLICATION NOTE: This bit should always be enabled (set) to prevent fan tachometer interrupts during spinup.
Bits [2:0] Spin Up
Bits [2:0] specify the ‘spin up’ time for the fan. When a fan is being started from a stationary state, the PWM output is
held at 100% duty cycle for the time specified in the table below before scaling to a lower speed. Note that during spin-
up, the PWM pin is forced high for the duration of the spin-up time (i.e., 100% duty cycle = 256/256).
Note:
To reduce the spin-up time, this device has implemented a feature referred to as Spin Up Reduction. Spin
Up Reduction uses feedback from the tachometers to determine when each fan has started spinning prop-
erly. Spin up for a PWM will end when the tachometer reading register is below the minimum limit, or the
spin-up time expires, whichever comes first. All tachs associated with a PWM must be below min. for spin-
up to end prematurely. This feature can be disabled by clearing bit 4 (SUREN) of the Configuration register
(7Fh). If disabled, the all fans go on full for the duration of their associated spin up time. Note that the Tachx
minimum registers must be programmed to a value less than FFFFh in order for the spin-up reduction to
work properly.
DS00002121B-page 172
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SCH3227/SCH3226/SCH3224/SCH3222
TABLE 22-8: FAN SPIN-UP REGISTER
SPIN[2:0]
Spin Up Time
000
001
010
011
100
101
110
111
0 sec
100ms
250ms (default)
400ms
700ms
1000ms
2000ms
4000ms
22.2.16 REGISTERS 5F-61H: ZONE TEMPERATURE RANGE, PWM FREQUENCY
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
5Fh
60h
61h
R/W
R/W
R/W
Zone 1 Range / Fan 1 Frequency
Zone 2 Range / Fan 2 Frequency
Zone 3 Range / Fan 3 Frequency
RAN3
RAN3
RAN3
RAN2
RAN2
RAN2
RAN1
RAN1
RAN1
RAN0
RAN0
RAN0
FRQ3
FRQ3
FRQ3
FRQ2
FRQ2
FRQ2
FRQ1
FRQ1
FRQ1
FRQ0
FRQ0
FRQ0
CBh
CBh
CBh
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
In Auto Fan Mode, when the temperature for a zone is above the Low Temperature Limit (registers 67-69h) and below
the Absolute Temperature Limit (registers 6A-6Ch) the speed of a fan assigned to that zone is determined as follows by
the auto fan control logic.
When the temperature reaches the temperature value programmed in the Zone x Low Temp Limit register, the PWM
output assigned to that zone is at PWMx Minimum Duty Cycle. Between Zone x Low Temp Limit and (Zone x Low Temp
Limit + Zone x Range), the PWM duty cycle increases linearly according to the temperature as shown in the figure below.
FIGURE 22-1:
FAN ACTIVITY ABOVE FAN TEMP LIMIT
PWM Duty is linear over
this range
Below Fan Temp Limit: Fan is off or at Fan PWM
Minimum depending on bit[7:5] of register 62h
and bit 2 of register 7Fh
Temperature
Temperature LIMIT: PWM
output at MIN FAN SPEED
LIMIT+ RANGE: PWM
Output at 100% Duty
Example for PWM1 assigned to Zone 1:
• Zone 1 Low Temp Limit (Register 67h) is set to 50C (32h).
• Zone 1 Range (Register 5Fh) is set to 8C (7h)
• PWM1 Minimum Duty Cycle (Register 64h) is set to 50% (80h)
In this case, the PWM1 duty cycle will be 50% at 50C.
Since (Zone 1 Low Temp Limit) + (Zone 1 Range) = 50C + 8C = 58C, the fan controlled by PWM1 will run at 100%
duty cycle when the temperature of the Zone 1 sensor is at 58C.
2016-2017 Microchip Technology Inc.
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Since the midpoint of the fan control range is 54C, and the median duty cycle is 75% (Halfway between the PWM Min-
imum and 100%), PWM1 duty cycle would be 75% at 54C.
Above (Zone 1 Low Temp Limit) + (Zone 1 Range), the duty cycle must be 100%.
The PWM frequency bits [3:0] determine the PWM frequency for the fan. If the high frequency option is selected the
associated FANTACH inputs must be configured for Mode 1.
22.2.16.1 PWM Frequency Selection (Default =1011 bits=25kHz)
TABLE 22-9: PWM FREQUENCY SELECTION
Frequency
Frequency
Select Bits[3:0]
14.318MHz Clock Source
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
11.0 Hz
14.6 Hz
21.9 Hz
29.3 Hz
35.2 Hz
44.0 Hz
58.6 Hz
87.7 Hz
15kHz
20kHz
30kHz
25kHz (default)
Reserved
Reserved
Reserved
Reserved
22.2.16.2 Range Selection (Default =1100=32C)
TABLE 22-10: REGISTER SETTING VS. TEMPERATURE RANGE
RAN[3:0]
Range (C)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
2
2.5
3.33
4
5
6.67
8
10
13.33
16
20
26.67
32
40
53.33
80
DS00002121B-page 174
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Note:
The range numbers will be used to calculate the slope of the PWM ramp up. For the fractional entries, the
PWM will go on full when the temp reaches the next integer value e.g., for 3.33, PWM will be full on at (min.
temp + 4).
22.2.17 REGISTER 62H, 63H: PWM RAMP RATE CONTROL
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
62h
63h
R/W
R/W
PWM 1 Ramp Rate Control
RES1
RR2E
RES1
RES1
RES
RR1E
RR3E
RR1-2
RR3-2
RR1-1
RR3-1
RR1-0
RR3-0
E0h
00h
PWM 2, PWM 3 Ramp Rate
Control
RR2-2
RR2-1
RR2-0
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
RES1 bits are set to ‘1’ and are read only, writes are ignored.
Description of Ramp Rate Control bits:
If the Remote1 or Remote2 pins are connected to a processor or chipset, instantaneous temperature spikes may be
sampled by the part. The auto fan control logic calculates the PWM duty cycle for all temperature readings. If Ramp
Rate Control is disabled, the PWM output will jump or oscillate between different PWM duty cycles causing the fan to
suddenly change speeds, which creates unwanted fan noise. If enabled, the PWM Ramp Rate Control logic will prevent
the PWM output from jumping, instead the PWM will ramp up/down towards the new duty cycle at a pre-determined
ramp rate.
Ramp Rate Control
The Ramp Rate Control logic limits the amount of change to the PWM duty cycle over a period of time. This period of
time is programmable via the Ramp Rate Control bits. For a detailed description of the Ramp Rate Control bits see
Table 22-11.
Note 1: RR1E, RR2E, and RR3E enable PWM Ramp Rate Control for PWM 1, 2, and 3 respectively.
2: RR1-2, RR1-1, and RR1-0 control ramp rate time for PWM 1
3: RR2-2, RR2-1, and RR2-0 control ramp rate time for PWM 2
4: RR3-2, RR3-1, and RR3-0 control ramp rate time for PWM 3
TABLE 22-11: PWM RAMP RATE CONTROL
PWM Ramp Time
(SEC)
(Time from 33%
Duty Cycle to
100% Duty Cycle)
PWM Ramp Time
(SEC)
(Time from 0%
Duty Cycle to
100% Duty Cycle)
Time per PWM
Step
(PWM Step Size =
1/255)
PWM
Ramp Rate
(Hz)
RRx-[2:0]
000
001
010
011
100
101
110
111
35
17.6
11.8
7.0
52.53
26.52
17.595
10.455
6.63
206 msec
104 msec
69 msec
41 msec
26 msec
18 msec
10 msec
5 msec
4.85
9.62
14.49
24.39
38.46
55.56
100
4.4
3.0
4.59
1.6
2.55
0.8
1.275
200
Note:
This assumes the Ramp Rate Enable bit (RRxE) is set.
2016-2017 Microchip Technology Inc.
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22.2.18 REGISTERS 64-66H: MINIMUM PWM DUTY CYCLE
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
64h
65h
66h
R/W
R/W
R/W
PWM1 Minimum Duty Cycle
PWM2 Minimum Duty Cycle
PWM3 Minimum Duty Cycle
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
80h
80h
80h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
These registers specify the minimum duty cycle that the PWM will output when the measured temperature reaches the
Temperature LIMIT register setting in Auto Fan Control Mode.
TABLE 22-12: PWM DUTY VS. REGISTER SETTING
Minimum PWM Duty
Value (Decimal)
Value (HEX)
0%
0
00h
.
.
.
.
.
.
.
.
.
25%
64
40h
.
.
.
.
.
.
.
.
.
50%
128
80h
.
.
.
.
.
.
.
.
.
100%
255
FFh
22.2.19 REGISTERS 67-69H: ZONE LOW TEMPERATURE LIMIT
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
67h
68h
69h
R/W
R/W
R/W
Zone 1 (Remote Diode 1) Low Temp
Limit
7
7
7
6
5
4
3
2
2
2
1
0
80h
Note 22-
18
Zone 2 (Ambient) Low Temp Limit
6
6
5
5
4
4
3
3
1
1
0
0
80h
Note 22-
18
Zone 3 (Remote Diode 2) Low Temp
Limit
80h
Note 22-
18
Note 22-18 This register is reset to the default value following a VCC POR when the PWRGD_PS signal is
asserted.
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
These are the temperature limits for the individual zones. When the current temperature equals this limit, the fan will be
turned on if it is not already. When the temperature exceeds this limit, the fan speed will be increased according to the
auto fan algorithm based on the setting in the Zone x Range / PWMx Frequency register. Default = 90C=5Ah.
DS00002121B-page 176
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TABLE 22-13: TEMPERATURE LIMIT VS. REGISTER SETTING
Limit
Limit (DEC)
Limit (HEX)
-127c
-127
81h
.
.
.
.
.
.
.
.
.
-50c
-50
CEh
.
.
.
.
.
.
.
.
.
0c
0
00h
.
.
.
.
.
.
.
.
.
50c
50
32h
.
.
.
.
.
.
.
.
.
127c
127
7Fh
22.2.20 REGISTERS 6A-6CH: ABSOLUTE TEMPERATURE LIMIT
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
6Ah
6Bh
6Ch
R/W
R/W
R/W
Zone 1 Temp Absolute Limit
Zone 2 Temp Absolute Limit
Zone 3 Temp Absolute Limit
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
64h
64h
64h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
In Auto Fan mode, if any zone associated with a PWM output exceeds the temperature set in the Absolute limit register,
all PWM outputs will increase their duty cycle to 100% except those that are disabled via the PWM Configuration reg-
isters. This is a safety feature that attempts to cool the system if there is a potentially catastrophic thermal event.
If an absolute limit register set to 80h (-128c), the safety feature is disabled for the associated zone. That is, if 80h is
written into the Zone x Temp Absolute Limit Register, then regardless of the reading register for the zone, the fans will
not turn on-full based on the absolute temp condition.
Default =100c=64h.
When any fan is in auto fan mode, then if the temperature in any zone exceeds absolute limit, all fans go to full, including
any in manual mode, except those that are disabled. Therefore, even if a zone is not associated with a fan, if that zone
exceeds absolute, then all fans go to full. In this case, the absolute limit can be chosen to be 7Fh for those zones that
are not associated with a fan, so that the fans won't turn on unless the temperature hits 127 degrees.
TABLE 22-14: ABSOLUTE LIMIT VS. REGISTER SETTING
Absolute Limit
Abs Limit (DEC)
Abs Limit (HEX)
-127c
-127
81h
.
.
.
.
.
.
.
.
.
-50c
-50
CEh
.
.
.
.
.
.
.
.
.
0c
0
00h
2016-2017 Microchip Technology Inc.
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TABLE 22-14: ABSOLUTE LIMIT VS. REGISTER SETTING (CONTINUED)
Absolute Limit
Abs Limit (DEC)
Abs Limit (HEX)
.
.
.
.
.
.
.
.
.
50c
50
32h
.
.
.
.
.
.
.
.
.
127c
127
7Fh
22.2.21 REGISTERS 6D-6EH: MCHP TEST REGISTERS
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
6Dh
6Eh
R/W
R/W
MCHP Test Register
MCHP Test register
7
7
6
6
5
5
4
4
3
2
1
0
44h
40h
RES
RES
RES
RES
22.2.22 REGISTER 70-72H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
70h
71h
72h
R
R
R
MCHP Test Register
MCHP Test Register
MCHP Test Register
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
N/A
N/A
N/A
This is a read-only MCHP test register. Writing to this register has no effect.
22.2.23 REGISTER 73-78H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
TST3
TST3
TST3
TST3
TST3
TST3
TST2
TST2
TST2
TST2
TST2
TST2
TST1
TST1
TST1
TST1
TST1
TST1
TST0
TST0
TST0
TST0
TST0
TST0
09h
09h
09h
09h
09h
09h
73h
74h
75h
76h
77h
78h
R
R/W
R
MCHP Test Register
MCHP Test Register
MCHP Test Register
MCHP Test Register
MCHP Test Register
MCHP Test Register
R/W
R
R/W
These are MCHP Test registers. Writing to these registers may cause unwanted results.
22.2.24 REGISTER 79H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
79h
R/W
MCHP Test Register
TST7
TST6
TST5
TST4 TST3 TST2 TST1
TST0
00h
This is a read/write register. Writing this register may produce unwanted results.
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
22.2.25 REGISTER 7CH: SPECIAL FUNCTION REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
7Ch
R/W
Special Function
AVG2
AVG1
AVG0
MCHP
MCHP
INT_EN
MONMD
RES
E0h
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
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This register contains the following bits:
Bit[0] Reserved
Bit[1] Monitoring Mode Select
0= Continuous Monitor Mode (default)
1= Cycle Monitor Mode
Bit[2] Interrupt (nHWM_INT Pin) Enable
0= Disables nHWM_INT pin output function (default)
1= Enables nHWM_INT pin output function
Bit[3] MCHP Reserved
This is a read/write bit. Reading this bit has no effect. Writing this bit to ‘1’ may cause unwanted results.Bit [4] MCHP
Reserved
This is a read/write bit. Reading this bit has no effect. Writing this bit to ‘1’ may cause unwanted results.
Bits [7:5] AVG[2:0]
The AVG[2:0] bits determine the amount of averaging for each of the measurements that are performed by the hardware
monitor before the reading registers are updated (TABLE 22). The AVG[2:0] bits are priority encoded where the most
significant bit has highest priority. For example, when the AVG2 bit is asserted, 32 averages will be performed for each
measurement before the reading registers are updated regardless of the state of the AVG[1:0] bits.
TABLE 22-15: AVG[2:0] BIT DECODER
SFTR[7:5]
AVG1
Averages Per Reading
REM Diode 2
AVG2
AVG0
REM Diode 1
Internal Diode
0
0
0
1
0
0
1
X
0
1
128
16
128
16
8
1
X
X
16
16
16
32
32
32
Note:
The default for the AVG[2:0] bits is ‘010’b.
22.2.26 REGISTER 7EH: INTERRUPT ENABLE 1 REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
7Eh
R/W
Interrupt Enable 1 (Voltages)
VCC
12V
5V
VTR
VCCP
2.5V
VBAT
VOLT
ECh
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
This register is used to enable individual voltage error events to set the corresponding status bits in the interrupt status
registers. This register also contains the group voltage enable bit (Bit[0] VOLT), which is used to enable voltage events
to force the interrupt pin (nHWM_INT) low if interrupts are enabled (see Bit[2] INTEN of the Special Function register at
offset 7Ch).
This register contains the following bits:
Bit[0] Group interrupt Voltage Enable (VOLT)
0=Out-of-limit voltages do not affect the state of the nHWM_INT pin (default)
1=Enable out-of-limit voltages to make the nHWM_INT pin active low
Bit[1] VBAT Error Enable
Bit[2] 2.5V Error Enable
Bit[3] Vccp Error Enable
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Bit[4] VTR Error Enable
Bit[5] 5V Error Enable
Bit[6] 12V Error Enable
Bit[7] VCC Error Enable
The individual voltage error event bits are defined as follows:
0= disable
1= enable.
See FIGURE 21-3: Interrupt Control on page 128.
22.2.27 REGISTER 7FH: CONFIGURATION REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
7Fh
R/W
Configuration
INIT
MCHP
MCHP
SUREN
TRDY MON_ DN
RES
RES
10h
Note 22
-19
Note 22-19 TRDY is cleared when the PWRGD_PS signal is asserted.
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
This register contains the following bits:
Bit[0] Reserved
Bit[1] Reserved
Bit[2] MON_DN: This bit is used to detect when the monitoring cycle is completed following the START bit being set to
0. When the START bit is cleared, the hardware monitoring block always completes the monitoring cycle. 0= monitoring
cycle active, 1= monitoring cycle complete.
APPLICATION NOTE: When the START bit is 1, and the device is monitoring, this bit will toggle each time it
completes the monitoring cycle. It is intended that the user only read this bit when the START
bit is 0.
Bit[3] TRDY: Temperature Reading Ready. This bit indicates that the temperature reading registers have valid values.
This bit is used after writing the start bit to ‘1’. 0= not valid, 1=valid.
Bit[4] SUREN: Spin-up reduction enable. This bit enables the reduction of the spin-up time based on feedback from all
fan tachometers associated with each PWM. 0=disable, 1=enable (default)
Bit[5] MCHP Reserved
This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results.
Bit[5] MCHP Reserved
This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results.
Bit[6] MCHP Reserved
This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results.
Bit[7] Initialization
Setting the INIT bit to ‘1’ performs a soft reset. This bit is self-clearing. Soft Reset sets all the registers except the Read-
ing Registers to their default values.
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SCH3227/SCH3226/SCH3224/SCH3222
22.2.28 REGISTER 80H: INTERRUPT ENABLE 2 REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
80h
R/W
Interrupt Enable 2 (Fan
Tachs)
RES
RES
RES
RES
FAN-
TACH3
FAN-
TACH2
FAN-
TACH1
FAN-
TACH
1Eh
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
This register is used to enable individual fan tach error events to set the corresponding status bits in the interrupt status
registers. This register also contains the group fan tach enable bit (Bit[0] TACH), which is used to enable fan tach events
to force the interrupt pin (nHWM_INT) low if interrupts are enabled (see Bit[2] INTEN of the Special Function register at
offset 7Ch).
This register contains the following bits:
Bit[0] FANTACH (Group TACH Enable)
0= Out-of-limit tachometer readings do not affect the state of the nHWM_INT pin (default)
1= Enable out-of-limit tachometer readings to make the nHWM_INT pin active low
Bit[1] Fantach 1 Event Enable
Bit[2] Fantach 2 Event Enable
Bit[3] Fantach 3 Event Enable
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The individual fan tach error event bits are defined as follows:
0= disable
1= enable.
22.2.29 REGISTER 81H: TACH_PWM ASSOCIATION REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
81h
R/W
TACH_PWM Association
RES
RES
T3H
T3L
T2H
T2L
T1H
T1L
24h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
This register is used to associate a PWM with a tachometer input. This association is used by the fan logic to determine
when to prevent a bit from being set in the interrupt status registers.
The fan tachometer will not cause a bit to be set in the interrupt status register:
a) if the current value in Current PWM Duty registers is 00h or
b) if the fan is disabled via the Fan Configuration Register.
Note:
A bit will never be set in the interrupt status for a fan if its tachometer minimum is set to FFFFh.
See bit definition below.
Bits[1:0] Tach1. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[3:2] Tach2. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[5:4] Tach3. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[7:6] Reserved
2016-2017 Microchip Technology Inc.
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Bits[1:0], Bits[3:2], Bits[5:4], Bits[7:6]
PWM Associated With Tachx
00
01
10
11
PWM1
PWM2
PWM3
Reserved
Note 1: Any PWM that has no TACH inputs associated with it must be configured to operate in Mode 1.
2: All TACH inputs must be associated with a PWM output. If the tach is not being driven by the associated
PWM output it should be configured to operate in Mode 1 and the associated TACH interrupt must be dis-
abled.
22.2.30 REGISTER 82H: INTERRUPT ENABLE 3 REGISTER
Register
Address
Read/
Write
Bit 7
(MSb)
Bit 0
(LSb)
Default
Value
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
82h
R/W
Interrupt Enable 3 (Temp)
RES
RES
RES
RES
D2EN
D1EN
AMB
TEMP
0Eh
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
This register is used to enable individual thermal error events to set the corresponding status bits in the interrupt status
registers. This register also contains the group thermal enable bit (Bit[0] TEMP), which is used to enable thermal events
to force the interrupt pin (nHWM_INT) low if interrupts are enabled (see Bit[2] INTEN of the Special Function register at
offset 7Ch).
This register contains the following bits:
Bit[0] TEMP. Group temperature enable bit.
0= Out-of-limit temperature readings do not affect the state of the nHWM_INT pin (default)
1= Enable out-of-limit temperature readings to make the nHWM_INT pin active low
Bit[1] ZONE 2 Temperature Status Enable bit.
Bit[2] ZONE 1 Temperature Status Enable bit.
Bit[3] ZONE 3 Temperature Status Enable bit
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The individual thermal error event bits are defined as follows:
0= disable
1= enable
22.2.31 REGISTER 83H: INTERRUPT STATUS REGISTER 3
Register
Address
Read/
Write
Bit 7
(MSb)
Bit 0
(LSb)
Default
Value
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RWC1
83h
Interrupt Status 3
RES
RES
RES
RES
RES
RES
Vbat
VTR
00h
Note:
This is a read/write-to-clear register. The status bits are cleared on a write of one if the event causing the
interrupt is no longer active. Writing a zero to these bits has no effect.
The Interrupt Status Register 3 bits[1:0] are automatically set by the device whenever a voltage event occurs on the
VTR or Vbat inputs. A voltage event occurs when any of these inputs violate the limits set in the corresponding limit
registers.
DS00002121B-page 182
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This register holds a set bit until the event is cleared by software or until the individual enable bit is cleared. Once set,
the Interrupt Status Register 3 bits remain set until the individual enable bits is cleared, even if the voltage or tachometer
reading no longer violate the limits set in the limit registers. Note that clearing the group Temp, Fan, or Volt enable bits
or the global INTEN enable bit has no effect on the status bits.
Note:
The individual enable bits for VTR and Vbat are located in the Interrupt Enable 1 register at offset 7Eh.
This register is read only – a write to this register has no effect.
Bit
Name
R/W
Default
Description
0
VTR_Error
R
0
The device automatically sets this bit to 1 when the VTR input
voltage is less than or equal to the limit set in the VTR Low Limit
register or greater than the limit set in the VTR High Limit register.
1
Vbat_Error
R
0
The device automatically sets this bit to 1 when the Vbat input
voltage is less than or equal to the limit set in the Vbat Low Limit
register or greater than the limit set in the Vbat High Limit register.
2-7
Reserved
R
0
Reserved
22.2.32 REGISTERS 84H-88H: A/D CONVERTER LSBS REGISTERS
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
84h
85h
86h
87h
88h
R
R
R
R
R
A/D Converter LSbs Reg 5
A/D Converter LSbs Reg 1
A/D Converter LSbs Reg 2
A/D Converter LSbs Reg 3
A/D Converter LSbs Reg 4
VTR.3
RD2.3
V12.3
V50.3
VCC.3
VTR.2
RD2.2
V12.2
V50.2
VCC.2
VTR.1
RD2.1
V12.1
V50.1
VCC.1
VTR.0
RD2.0
V12.0
V50.0
VCC.0
VBT.3
RD1.3
AM.3
VBT.2
RD1.2
AM.2
VBT.1
RD1.1
AM.1
VBT.0
RD1.0
AM.0
N/A
N/A
N/A
N/A
N/A
V25.3
VCP.3
V25.2
VCP.2
V25.1
VCP.1
V25.0
VCP.0
There is a 10-bit Analog to Digital Converter (ADC) located in the hardware monitoring block that converts the measured
voltages into 10-bit reading values. Depending on the averaging scheme enabled (i.e., 16x averaging, 32x averaging,
etc.), the hardware monitor may take multiple readings and average them to create 12-bit reading values. The 8 MSb’s
of the reading values are placed in the Reading Registers. When the upper 8-bits located in the reading registers are
read the 4 LSb’s are latched into their respective bits in the A/D Converter LSbs Register. This give 12-bits of resolution
th
with a minimum value of 1/16 per unit measured. (i.e., Temperature Range: -127.9375 ºC < Temp < 127.9375 ºC and
Voltage Range: 0 < Voltage < 256.9375). See the DC Characteristics for the accuracy of the reading values.
The eight most significant bits of the 12-bit averaged readings are stored in Reading registers and compared with Limit
registers. The Interrupt Status Register bits are asserted if the corresponding measured value(s) on the inputs violate
their programmed limits.
22.2.33 REGISTERS 89H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
89h
R
MCHP Test Register
7
6
5
4
3
2
1
0
N/A
This is a read-only MCHP test register. Writing to this register has no effect on the hardware.
22.2.34 REGISTERS 8AH: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
8Ah
R
MCHP Test Register
RES
TST6
TST5
TST4
TST3
TST2
TST1
TST0
4Dh
22.2.35 REGISTERS 8BH: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
8Bh
R/W
MCHP Test Register
RES
TST6
TST5
TST4
TST3
TST2
TST1
TST0
4Dh
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This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
This register must not be written. Writing this register may produce unexpected results.
22.2.36 REGISTERS 8CH: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
8Ch
R
MCHP Test Register
RES
RES
RES
TST4
TST3
TST2
TST1
TST0
0Eh
22.2.37 REGISTERS 8DH: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
8Dh
R/W
MCHP Test Register
RES
RES
RES
TST4
TST3
TST2
TST1
TST0
0Eh
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
This register must not be written. Writing this register may produce unexpected results.
22.2.38 REGISTERS 8EH: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
8Eh
R
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
N/A
This register is an MCHP Test register.
22.2.39 REGISTERS 90H-92H: FANTACHX OPTION REGISTERS
Register
Address
Read/
Write
Bit 7
(MSb)
Bit 0
(LSb)
Default
Value
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
90h
R/W
R/W
R/W
FANTACH1 Option
FANTACH2 Option
FANTACH3 Option
RES
RES
RES
RES
RES
RES
RES
3EDG MODE EDG1 EDG0 SLOW 04h
3EDG MODE EDG1 EDG0 SLOW 04h
3EDG MODE EDG1 EDG0 SLOW 04h
91h
92h
RES
RES
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
Bit[0] SLOW
0= Force tach reading register to FFFFh if number of tach edges detected is greater than 0, but less than programmed
number of edges. (default)
1= Force tach reading register to FFFEh if number of tach edges detected is greater than 0, but less than programmed
number of edges.
Bit[2:1] The number of edges for tach reading:
00= 2 edges
01= 3 edges
10= 5 edges (default)
11= 9 edges
Bit[3] Tachometer Reading Mode
0= mode 1 standard (Default)
1= mode 2 enhanced.
Note 1: Unused FANTACH inputs must be configured for Mode 1.
2: Tach inputs associated with PWM outputs that are configured for high frequency mode must be configured
for Mode 1.
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Bit[4] 3 Edge Detection (Mode 2 only)
0= Don’t ignore first 3 edges (default)
1= Ignore first 3 tachometer edges after guard time
Note:
This bit has been added to support a small sampling of fans that emit irregular tach pulses when the PWM
transitions ‘ON’. Typically, the guard time is sufficient for most fans.
Bit[7:5] Reserved
22.2.40 REGISTERS 94H-96H: PWMX OPTION REGISTERS
Register
Address
Read/
Write
Register
Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
94h
95h
96h
R/W
R/W
R/W
PWM1 Option
PWM2 Option
PWM3 Option
RES
RES
RES
RES
RES
RES
OPP
OPP
OPP
GRD1
GRD1
GRD1
GRD0
GRD0
GRD0
SZEN
SZEN
SZEN
UPDT1
UPDT1
UPDT1
UPDT0
UPDT0
UPDT0
0Ch
0Ch
0Ch
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
Bits[1:0] Tachs reading registers associated with PWMx are updated: (Mode 2 only)
00= once a second (default)
01= twice a second
1x= every 300msec
Bit[2] Snap to Zero (SZEN)
This bit determines if the PWM output ramps down to OFF or if it is immediately set to zero.
0= Step Down the PWMx output to Off at the programmed Ramp Rate
1= Transition PWMx to Off immediately when the calculated duty cycle is 00h (default)
Bit[4:3] Guard time (Mode 2 only)
00= 63 clocks (90kHz clocks ~ 700usec)
01= 32 clocks (90kHz clocks ~ 356usec) (default)
10= 16 clocks (90kHz clocks ~ 178usec)
11= 8 clocks (90kHz clocks ~ 89usec)
Bit[5] Opportunistic Mode Enable
0= Opportunistic Mode Disabled. Update Tach Reading once per PWMx Update Period (see Bits[1:0] in this register)
1= Opportunistic Mode is Enabled. The tachometer reading register is updated any time a valid tachometer reading can
be made during the ‘on’ time of the PWM output signal. If a valid reading is detected prior to the Update cycle, then the
Update counter is reset.
Bit[7:6] Reserved
22.2.41 REGISTER 97H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
97h
R/W
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
5Ah
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
This is an MCHP Test Register. Writing to this register may cause unwanted results.
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22.2.42 REGISTER 98H:MCHP TEST REGISTER
Register Read/
Address Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Default
(LSb)
Value
98h
R/W
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
glitch
F1h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
22.2.43 This is an MCHP Test Register. Writing to this register may cause unwanted results.REGISTERS 99H-
9AH:VOLTAGE READING REGISTERS
See Section 22.2.2, "Registers 20-24h, 99-9Ah: Voltage Reading," on page 162.
22.2.44 REGISTERS 9B-9EH: VOLTAGE LIMIT REGISTERS
22.2.45 REGISTER A3H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
A3h
R/W
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
00h
This is an MCHP Test Register. Writing to this register may cause unwanted results.
22.2.46 REGISTER A4H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
A4h
R
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
02h
This register is an MCHP Test register.
22.2.47 REGISTER A5H: INTERRUPT STATUS REGISTER 1 - SECONDARY
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
A5h
R/WC
Interrupt Status 1 - Secondary
INT2
Note 22-
20
D2
AMB
D1
5V
VCC
Vccp
2.5V
00h
Note 22-20 This is a read-only bit. Writing ‘1’ to this bit has no effect.
Note 1: This register is reset to its default value when the PWRGD_PS signal transitions high.
2: This is a read/write-to-clear register. Bits[6:4] are cleared on a write of one if the temperature event is no
longer active. Writing a zero to these bits has no effect.
See definition of Register 41h: Interrupt Status Register 1 on page 167 for setting and clearing bits.
Note:
Only the primary status registers generate an interrupt event.
22.2.48 REGISTER A6H: INTERRUPT STATUS REGISTER 2 - SECONDARY
Register Read/W
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
Address
rite
A6h
R/WC Interrupt Status Register 2 -
Secondary
ERR2
ERR1
RES
FAN-
TACH3
FAN-
TACH2
FAN-
TACH1
RES
12V
00h
Note 1: This register is reset to its default value when the PWRGD_PS signal transitions high.
2: This is a read/write-to-clear register. The status bits in this register are cleared on a write of one if the event
causing the interrupt is no longer active. Writing a zero to these bits has no effect.
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See definition of Register 42h: Interrupt Status Register 2 on page 168 for setting and clearing bits.
Note:
Only the primary status registers generate an interrupt event.
22.2.49 REGISTER A7H: INTERRUPT STATUS REGISTER 3 - SECONDARY
Register Read/W
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
Address
rite
A7h
R/WC
Interrupt Status Register 3-
Secondary
RES
RES
RES
RES
RES
RES
VBAT
VTR
00h
Note 1: This register is reset to its default value when the PWRGD_PS signal transitions high.
2: This is a read/write-to-clear register. The status bits in this register are cleared on a write of one if the event
causing the interrupt is no longer active. Writing a zero to these bits has no effect.
See definition of Register 83h: Interrupt Status Register 3 on page 182 for setting and clearing bits.
Note:
Only the primary status registers generate an interrupt event.
22.2.50 REGISTER ABH: TACH 1-3 MODE REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
ABh
R/W
Tach 1-3 Mode
T1M1
T1M0
T2M1
T2M0
T3M1
T3M0
RES
RES
00h
The following defines the mode control bits:
• bits[7:6]: Tach1 Mode
• bits[5:4]: Tach2 Mode.
• bits[3:2]: Tach3 Mode.
• bits[1:0]: RESERVED.
For bits[7:2], these bits are defined as follows:
- 00= normal operation (default)
- 01= locked rotor mode, active high signal
- 10= locked rotor mode, active low signal
- 11= undefined.
For bits[1:0], these bits are defined as RESERVED. Writes have no affect, reads return 00.
22.2.51 REGISTER ADH: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
ADh
R
MCHP Test Register
7
6
5
4
3
2
1
0
00h
This is a read-only MCHP test register. Writing to this register has no effect.
22.2.52 REGISTERS AE-AFH, B3H: TOP TEMPERATURE LIMIT REGISTERS
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
AEh
AFh
B3h
R/W
R/W
R/W
Top Temperature Remote Diode 1
(Zone 1)
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
2Dh
2Dh
2Dh
Top Temperature Remote Diode 2
(Zone 3)
Top Temperature Ambient
(Zone 2)
Note:
These registers are reset to their default values when the powergood_ps signal transitions high.
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This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
The Top Temperature Registers define the upper bound of the operating temperature for each zone. If the temperature
of the zone exceeds this value, the minimum temperature for the zone can be configured to be adjusted down.
The Top Temperature registers are used as a comparison point for the AMTA feature, to determine if the Low Temp Limit
register for a zone should be adjusted down. The Top temp register for a zone is not used if the AMTA feature is not
enabled for the zone. The AMTA feature is enabled via the Tmin Adjust Enable register at 0B7h.
22.2.53 REGISTER B4H: MIN TEMP ADJUST TEMP RD1, RD2 (ZONES 1& 3)
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
B4h
R/W
Min Temp Adjust Temp RD1,
RD2 (Zones 1&3)
R1ATP1 R1ATP R2ATP R2ATP
RES
RES
RES
RES
00h
0
1
0
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
Bits[7:4] are used to select the temperature adjustment values that are subtracted from the Zone Low temp limit for
zones 1& 3. There is a 2-bit value for each of the remote zones that is used to program the value that is subtracted from
the low temp limit temperature register when the temperature reading for the zone reaches the Top Temperature for the
AMTA feature. The AMTA feature is enabled via the Tmin Adjust Enable register at B7h.
These bits are defined as follows: ZxATP[1:0]:
- 00= 2oC (default)
- 01= 4oC
- 10= 6oC
- 11= 8oC
Note:
The Zones are hardwired to the sensors in the following manner:
• R1ATP[1:0] = Zone 1 = Remote Diode 1
• AMATP[1:0] = Zone 2 = Ambient
• R2ATP[1:0] = Zone 3 = Remote Diode 2
22.2.54 REGISTER B5H: MIN TEMP ADJUST TEMP AND DELAY AMB (ZONE 2)
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
B5h
R/W
Min Temp Adjust Temp and
Delay (Zone 2)
RES
RES
AMATP AMATP
RES
RES
AMAD1 AMAD0
00h
1
0
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
Bits[5:4] Min Temp Adjust for Ambient Temp Sensor (Zone 2)
See Register B4h: Min Temp Adjust Temp RD1, RD2 (Zones 1& 3) on page 188 for a definition of the Min Temp Adjust
bits.
Bits[1:0] Min Temp Adjust Delay for Ambient Temp Sensor (Zone 2)
See Register B6h: Min Temp Adjust Delay RD1, RD2 (ZONE 1 & 3) Register on page 188 for a definition of the Min
Temp Delay bits.
22.2.55 REGISTER B6H: MIN TEMP ADJUST DELAY RD1, RD2 (ZONE 1 & 3) REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
B6h
R/W
Min Temp Adjust Temp and
R1 AD1
R1
R2
R2
RES
RES
RES
RES
00h
Delay RD1, RD2 (Zones 1 & 3)
AD0
AD1
AD0
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This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
Bits[7:4] are the bits to program the time delay for subsequently adjusting the low temperature limit value for zones 1&3
once an adjustment is made. These bits are defined as follows: RxAD[1:0]:
- 00= 1min (default)
- 01= 2min
- 10= 3min
- 11= 4min
Note:
The Zones are hardwired to the sensors in the following manner:
• R1AD[1:0] = Zone 1 = Remote Diode 1
• AMAD[1:0] = Zone 2 = Ambient
• R2AD[1:0] = Zone 3 = Remote Diode 2
22.2.56 REGISTER B7H: MIN TEMP ADJUST ENABLE REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
B7h
R/W
Tmin Adjust Enable
RES
RES
RES
RES
TMIN_ TMIN_ TMIN_
TOP_
INT_
EN
00h
ADJ_
EN2
ADJ_
EN1
ADJ_
ENA
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall have no
effect.
This register is used to enable the Automatic Minimum Temperature Adjustment (AMTA) feature for each zone. AMTA
allows for an adjustment of the low temp limit temperature register for each zone when the current temperature for the
zone exceeds the Top Temperature. Bits[3:1] are used to enable an adjustment of the low temp limit for each of zones
1-3.
This register also contains the bit (TOP_INT_EN) to enable an interrupt to be generated anytime the top temp for any
zone is exceeded. This interrupt is generated based on a bit in the Top Temp Exceeded status register (0B8h) being set.
Note that the INT_EN bit (register 7Ch) must also be set for an interrupt to be generated on the THERM pin.
Note:
The Zones are hardwired to the sensors in the following manner:
• TMIN_ ADJ_ EN1 = Zone 1 = Remote Diode 1
• TMIN_ ADJ_ ENA = Zone 2 = Ambient
• TMIN_ ADJ_ EN2 = Zone 3 = Remote Diode 2
22.2.57 REGISTER B8H: TOP TEMP EXCEEDED STATUS REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
B8h
R/WC
Top Temp Exceeded Status
RES
RES
RES
RES
RES
STS2
STS1
STSA
00h
Note:
Each bit in this register is cleared on a write of 1 if the event is not active.
Note:
This register is reset to its default value when the PWRGD_PS signal transitions high.
The Top Temp Exceeded Status Register bits are automatically set by the device whenever the temperature value in the
reading register for a zone exceeds the value in the Top Temperature register for the zone.
This register holds a bit set until the bit is written to 1 by software. The contents of this register are cleared (set to 0)
automatically by the device after it is written by software, if the temperature no longer exceeds the value in the Top Tem-
perature register for the zone. Once set, the Status bits remain set until written to 1, even if the if the temperature no
longer exceeds the value in the Top Temperature register for the zone.
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Note:
If a bit is set in this register, an interrupt can be generated if the TOP_INT_EN bit (register B7h) and, for
the nHWM_INT pin to go active, the INT_EN bit (7Ch) is set.
22.2.58 REGISTER BAH: MCHP RESERVED REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
BAh
R/W
MCHP Reserved
RES
RES
RES
RES
RES
RES
RES
RES
03h
This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results.
22.2.59 REGISTER BBH: MCHP RESERVED REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
BBh
R
MCHP Reserved
7
6
5
4
3
2
1
0
00h
This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results.
22.2.60 REGISTER 0BDH: MCHP RESERVED REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
BDh
R
MCHP Reserved
7
6
5
4
3
2
1
0
N/A
This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results.
22.2.61 REGISTER BFH: MCHP RESERVED REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
BFh
R/W
MCHP Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results.
22.2.62 REGISTER C0H: MCHP RESERVED REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
C0h
R/W
MCHP Reserved
RES
RES
RES
RES
RES
RES
RES
RES
00h
This is an MCHP Reserved bit. Writing this bit to a value different than the default value may cause unwanted results.
22.2.63 REGISTER C1H: MCHP RESERVED REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
C1h
R/W
Thermtrip Control
RES
RES
RES
RES
RES
RES
THERM-
TRIP_C-
TRL
RES
01h
THERMTRIP_CTRL: Bit 1 in the Thermtrip Control register. May be enabled to assert the Thermtrip# pin if programmed
limits are exceeded as indicated by the Thermtrip Status register 1=enable, 0=disable (default).
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22.2.64 REGISTERS C4-C5, C9H: THERMTRIP TEMPERATURE LIMIT ZONE REGISTERS
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
C4h
C9h
C5h
R/W
R/W
R/W
THERMTRIP Temp Limit ZONE 1
(Remote Diode 1)
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
7Fh
7Fh
7Fh
THERMTRIP Temp Limit ZONE 2
(Ambient)
THERMTRIP Temp Limit ZONE 3
(Remote Diode 2)
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
The nTHERMTRIP pin can be configured to assert when one of the temperature zones is above its associated THER-
MTRIP temperature limit (THERMTRIP Temp Limit ZONES 1-3). The THERMTRIP temperature limit is a separate limit
register from the high limit used for setting the interrupt status bits for each zone.
The THERMTRIP Temp Limit ZONE 1-3 registers represent the upper temperature limit for asserting nTHERMTRIP pin
for each zone. These registers are defined as follows:
If the monitored temperature for the zone exceeds the value set in the associated THERMTRIP Temp Limit ZONE 1-3
registers, the corresponding bit in the THERMTRIP status register will be set. The nTHERMTRIP pin may or may not
be set depending on the state of the associated enable bits (in the THERMTRIP Output Enable register).
Note:
The zone must exceed the limits set in the associated THERMTRIP Temp Limit ZONE 1-3 register for two
successive monitoring cycles in order for the nTHERMTRIP pin to go active (and for the associated status
bit to be set).
22.2.65 REGISTER CAH: THERMTRIP STATUS REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
CAh
R/WC
THERMTRIP Status
RES
RES
RES
RES
RES
RD 2
RD 1
AMB
00h
Note:
Each bit in this register is cleared on a write of 1 if the event is not active.
Note:
This register is reset to its default value when the PWRGD_PS signal transitions high.
This register holds a bit set until the bit is written to 1 by software. The contents of this register are cleared (set to 0)
automatically by the device after it is written by software, if the nTHERMTRIP pin is no longer active. Once set, the Sta-
tus bits remain set until written to 1, even if the nTHERMTRIP pin is no longer active.
Bits[2:0] THERMTRIP zone status bits (one bit per zone). A status bit is set to ‘1’ if the associated zone temp exceeds
the associated THERMTRIP Temp Limit register value.
22.2.66 REGISTER CBH: THERMTRIP OUTPUT ENABLE REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
CBh
R/W
THERMTRIP
Output Enable
RES
RES
RES
RES
RES
RD2
RD1
AMB
00h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
Bits[2:0] in THERMTRIP Output Enable register, THERMTRIP output enable bits (one bit per zone). Each zone may be
individually enabled to assert the nTHERMTRIP pin if the zone temperature reading exceeds the associated THERM-
TRIP Temp Limit register value. 1=enable, 0=disable (default).
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22.2.67 REGISTER CEH: MCHP RESERVED REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
CEh
R/W
RES
RES
RES
RES
RES
RD2
_INT_ _INT_
EN
RD1
AMB_
INT_
EN
00h
EN
22.2.68 REGISTERS D1,D6,DBH: PWM MAX SEGMENT REGISTERS
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
0D1h
0D6h
0DBh
R/W
R/W
R/W
PWM1 Max
PWM2 Max
PWM3 Max
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
FFh
FFh
FFh
These registers become read only when the Lock bit is set. Any further attempts to write to these registers shall have
no effect.
Registers 0D1h, 0D6h and 0DBh are used to program the Max PWM duty cycle for the fan function for each PWM.
22.2.69 REGISTER E0H: ENABLE LSBS FOR AUTO FAN
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
E0h
R/W
Enable LSbs for AutoFan
RES
RES
PWM3_ PWM3_ PWM2_ PWM2_ PWM1_ PWM1_
n1 n0 n1 n0 n1 n0
00h
Bits[7:6] Reserved
Bits[5:4] PWM3_n[1:0]
Bits[3:2] PWM2_n[1:0]
Bits[1:0] PWM1_n[1:0]
The PWMx_n[1:0] configuration bits allow the autofan control logic to utilize the extended resolution bits in the tempera-
ture reading. Increasing the precision reduces the programmable temperature range that can be used to control the
PWM outputs. For a description of the programmable temperature ranges see Registers 5F-61h: Zone Temperature
Range, PWM Frequency on page 173.
Note:
Increasing the precision does not limit the range of temperature readings supported. The active region for
the autofan control is bound by the Minimum Zone Limit + Range, where the Minimum Zone Limit can be
any integer value from -127 to +127 degrees.
Max Theoretical
Temperature Range
Supported
Max Programmable
Temperature Range
Supported
Degree of Resolution per
LSb Used in Autofan
PWMx_n[1:0]
00
01
10
11
1
0.5
255
128.5
80
80
0.25
64.75
53.33
Reserved
Reserved
Reserved
22.2.70 REGISTERS E1H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
8Ah
R
MCHP Test Register
RES
TST6
TST5
TST4
TST3
TST2
TST1
TST0
4Dh
DS00002121B-page 192
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
22.2.71 REGISTERS E2H: MCHP TEST REGISTER
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
8Ah
R
MCHP Test Register
RES
TST6
TST5
TST4
TST3
TST2
TST1
TST0
4Dh
22.2.72 REGISTERS E3H: MCHP TEST REGISTER
Register
Address
Read/Wri
te
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
8Ah
R
MCHP Test Register
RES
TST6
TST5
TST4
TST3
TST2
TST1
TST0
4Dh
22.2.73 REGISTER E9-EEH: MCHP TEST REGISTERS
Register
Address
Read/
Write
Register Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
E9h
EAh
EBh
ECh
EDh
EEh
R/W
R/W
R/W
R/W
R/W
R/W
MCHP Test Register
MCHP Test Register
MCHP Test Register
MCHP Test Register
MCHP Test Register
MCHP Test Register
TST7
TST7
TST7
TST7
TST7
TST7
TST6
TST6
TST6
TST6
TST6
TST6
TST5
TST5
TST5
TST5
TST5
TST5
TST4
TST4
TST4
TST4
TST4
TST4
TST3
TST3
TST3
TST3
TST3
TST3
TST2
TST2
TST2
TST2
TST2
TST2
TST1
TST1
TST1
TST1
TST1
TST1
TST0
TST0
TST0
TST0
TST0
TST0
00h
00h
00h
00h
00h
00h
These are MCHP Test Registers. Writing to these registers may cause unwanted results.
22.2.74 REGISTER FFH: MCHP TEST REGISTER
Register
Address
Read/
Write
Register
Name
Bit 7
(MSb)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSb)
Default
Value
FFh
R
MCHP Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
N/A
This register is an MCHP Test register.
2016-2017 Microchip Technology Inc.
DS00002121B-page 193
SCH3227/SCH3226/SCH3224/SCH3222
23.0 CONFIGURATION REGISTERS
The Configuration of the SCH322x is very flexible and is based on the configuration architecture implemented in typical
Plug-and-Play components. The SCH322x is designed for motherboard applications in which the resources required by
their components are known. With its flexible resource allocation architecture, the SCH322x allows the BIOS to assign
resources at POST.
SYSTEM ELEMENTS
Primary Configuration Address Decoder
After a PCI Reset or Vcc Power On Reset the SCH322x is in the Run Mode with all logical devices disabled. The logical
devices may be configured through two standard Configuration I/O Ports (INDEX and DATA) by placing the SCH322x
into Configuration Mode.
The BIOS uses these configuration ports to initialize the logical devices at POST. The INDEX and DATA ports are only
valid when the SCH322x Is in Configuration Mode.
Strap options must be added to allow four Configuration Register Base Address options: 0x002E, 0x004E, 0x162E, or
0x164E. At the deasserting edge of PCIRST# or VCC POR the nRTS1/SYSOPT0 pin is latched to determine
the configuration base address:
• 0 = Index Base I/O Address bits A[7:0]= 0x2E
• 1 = Index Base I/O Address bits A[7:0]= 0x4E
At the deasserting edge of PCIRST# or VCC POR the nDTR1/SYSOPT1 pin is latched to determine the
configuration base address:
• 0 = Index Base I/O Address bits A[15:8]= 0x16;
• 1 = Index Base I/O Address bits A[15:8]= 0x00
bit The above strap options will allow the Configuration Access Ports (CONFIG PORT, the INDEX PORT, and DATA
PORT) to be controlled by the nRTS1/SYSOPT0 and nDTR1/SYSOPT1 pins and by the Configuration Port Base
Address registers at offset 0x26 and 0x27. The configuration base address at power-up is determined by the SYSOPT
strap option. The SYSOPT strap option is latched state of the nRTS1/SYSOPT0 and nDTR1/SYSOPT1 pins at the
deasserting edge of PCIRST#. The nRTS1/SYSOPT0 pin determines the lower byte of the Base Address and the
nDTR1/SYSOPT1 pin determines the upper byte of the Base Address. The following table summarizes the Base Con-
figuration address selected by the SYSOPT strap option.
TABLE 23-1: SYSOPT STRAP OPTION CONFIGURATION ADDRESS SELECT
Default CONFIG PORT/
SYSOPT1
SYSOPT0
Data Port
Index Port Address
1
1
0
0
0
1
0
1
0x002E
0x004E
0x162E
0x164E
INDEX PORT + 1
APPLICATION NOTE: The nRTS1/SYSOPT0 and the nDTR1/SYSOPT1 pins requires external pullup/pulldown
resistors to set the default base I/O address for configuration to 0x002E, 0x004E, 0x162E,
or 0x164E.
The INDEX and DATA ports are effective only when the chip is in the Configuration State.
Note 23-1
The configuration port base address can be relocated through CR26 and CR27.
Entering the Configuration State
The device enters the Configuration State when the following Config Key is successfully written to the CONFIG PORT.
Config Key = <0x55>
Exiting the Configuration State
The device exits the Configuration State when the following Config Key is successfully written to the CONFIG PORT.
Config Key = <0xAA>
DS00002121B-page 194
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
CONFIGURATION SEQUENCE
To program the configuration registers, the following sequence must be followed:
1. Enter Configuration Mode
2. Configure the Configuration Registers
3. Exit Configuration Mode.
Enter Configuration Mode
To place the chip into the Configuration State the Config Key is sent to the chip’s CONFIG PORT. The config key consists
of 0x55 written to the CONFIG PORT. Once the configuration key is received correctly the chip enters into the Config-
uration State (The auto Config ports are enabled).
Configuration Mode
The system sets the logical device information and activates desired logical devices through the INDEX and DATA ports.
In configuration mode, the INDEX PORT is located at the CONFIG PORT address and the DATA PORT is at INDEX
PORT address + 1.
The desired configuration registers are accessed in two steps:
1. Write the index of the Logical Device Number Configuration Register (i.e., 0x07) to the INDEX PORT and then
write the number of the desired logical device to the DATA PORT
2. Write the address of the desired configuration register within the logical device to the INDEX PORT and then write
or read the configuration register through the DATA PORT.
Note:
If accessing the Global Configuration Registers, step (a) is not required.
Exit Configuration Mode
To exit the Configuration State the system writes 0xAA to the CONFIG PORT. The chip returns to the RUN State.
Note:
Only two states are defined (Run and Configuration). In the Run State the chip will always be ready to enter
the Configuration State.
Programming Example
The following is an example of a configuration program in Intel 8086 assembly language.
;----------------------------.
; ENTER CONFIGURATION MODE
|
;----------------------------‘
MOV DX,02EH
MOV AX,055H
OUT DX,AL
;----------------------------.
; CONFIGURE REGISTER CRE0,
; LOGICAL DEVICE 8
|
|
;----------------------------‘
MOV DX,02EH
MOV AL,07H
OUT DX,AL ;Point to LD# Config Reg
MOV DX,02FH
MOV AL, 08H
OUT DX,AL;Point to Logical Device 8
;
MOV DX,02EH
MOV AL,E0H
OUT DX,AL; Point to CRE0
MOV DX,02fH
MOV AL,02H
OUT DX,AL; Update CRE0
;-----------------------------.
; EXIT CONFIGURATION MODE
|
;-----------------------------‘
MOV DX,02EH
MOV AX,0AAH
OUT DX,AL
2016-2017 Microchip Technology Inc.
DS00002121B-page 195
SCH3227/SCH3226/SCH3224/SCH3222
Note 1: SOFT RESET: Bit 0 of Configuration Control register set to one.
2: All host accesses are blocked for 500µs after Vcc POR (See FIGURE 27-1: Power-Up Timing on page 260.)
23.1 Configuration Registers
CAUTION: This device contains circuits which must not be used because their pins are not brought out of the package,
and are pulled to known states internally. Any features, and especially Logical Devices, that are not listed in this docu-
ment must not be activated or accessed. Doing so may cause unpredictable behavior and/or excessive currents, and
therefore may damage the device and/or the system.
The following table summarizes the logical device allocation for the different varieties of SCH322x devices.
TABLE 23-2: SCH322X LOGICAL DEVICE SUMMARY
Logical Device
SCH3222
RESERVED
SCH3224
RESERVED
SCH3226
RESERVED
SCH3227
RESERVED
0
1
RESERVED
RESERVED
RESERVED
SERIAL PORT 1
SERIAL PORT 2
RESERVED
KEYBOARD
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
SERIAL PORT 1
SERIAL PORT 2
RESERVED
KEYBOARD
RESERVED
RESERVED
RESERVED
2
RESERVED
RESERVED
3
PARALLEL PORT
SERIAL PORT 1
SERIAL PORT 2
RESERVED
PARALLEL PORT
SERIAL PORT 1
SERIAL PORT 2
RESERVED
4
5
6
7
KEYBOARD
KEYBOARD
8
RESERVED
RESERVED
9
RESERVED
RESERVED
Ah
RUNTIME
REGISTERS
RUNTIME
REGISTERS
RUNTIME
REGISTERS
RUNTIME
REGISTERS
Bh
Ch
Dh
Eh
SERIAL PORT 3
SERIAL PORT 4
SERIAL PORT 5
SERIAL PORT 6
RESERVED
SERIAL PORT 3
SERIAL PORT 4
SERIAL PORT 3
SERIAL PORT 4
RESERVED
SERIAL PORT 5
SERIAL PORT 6
IF STRAPOPT=1
SERIAL PORTS [5/6]
ELSE RESERVED
IF STRAPOPT=1
SERIAL PORTS [5/6]
ELSE RESERVED
Fh
RESERVED
RESERVED
RESERVED
RESERVED
TABLE 23-3: CONFIGURATION REGISTER SUMMARY
Index
Type
PCI Reset VCC POR VTR POR Soft Reset
GLOBAL CONFIGURATION REGISTERS
Configuration Register
0x02
W
R
0x00
-
0x00
-
0x00
-
-
Config Control
0x03
0x07
0x20
-
Reserved – reads return 0
Logical Device Number
R/W
R
0x00
0x00
0x00
0x00
0x7D or
0x7F
0x7D or
0x7F
0x7D or
0x7F
0x7D or
0x7F
Device ID - hard wired
SCH3222 - 0x7F
SCH3224 - 0x7F
SCH3226 - 0x7D or 0x7F
SCH3227 - 0x7D or 0x7F
STRAPOPT pin selects value for
SCH3226 and SCH3227.
See this register in Table 23-4.
TEST8
0x19
0x21
R/W
R
-
0x00
0x00
-
Current Revision
Device Rev - hard wired
DS00002121B-page 196
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 23-3: CONFIGURATION REGISTER SUMMARY (CONTINUED)
Index
0x22
Type
R/W
PCI Reset VCC POR VTR POR Soft Reset
Configuration Register
Power Control
0x00
0x00
0x44
-
0x00
0x00
0x44
0x00
-
0x00
0x00
0x44
0x00
-
0x00
0x23
0x24
0x25
0x26
R/W
R/W
R/W
R/W
-
-
-
-
Reserved
OSC
TEST9
See
Table 23-1
on
Configuration Port Address Byte 0
(Low Byte)
page 194
0x27
R/W
See
-
-
-
Configuration Port Address Byte 1
(High Byte)
Table 23-1
on
page 194
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reserved
TEST
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
TEST 6
TEST 4
TEST 5
TEST 1
TEST 2
TEST 3
LOGICAL DEVICE 0 CONFIGURATION REGISTERS (RESERVED)
LOGICAL DEVICE 1 CONFIGURATION REGISTERS (RESERVED)
LOGICAL DEVICE 2 CONFIGURATION REGISTERS (RESERVED)
LOGICAL DEVICE 3 CONFIGURATION REGISTERS (PARALLEL PORT)
AVAILABLE IN SCH3227, SCH3224
RESERVED IN SCH3226, SCH3222
0x30
0x60
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Activate
Primary Base I/O Address High
Byte
0x61
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address Low
Byte
0x70
0x74
0xF0
0xF1
R/W
R/W
R/W
R/W
0x00
0x04
0x3C
0x00
0x00
0x04
0x3C
0x00
0x00
0x04
0x3C
0x00
0x00
Primary Interrupt Select
DMA Channel Select
0x04
-
-
Parallel Port Mode Register
Parallel Port Mode Register 2
LOGICAL DEVICE 4 CONFIGURATION REGISTERS (SERIAL PORT 1)
0x30
0x60
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Activate Note 23-2
Primary Base I/O Address High
Byte
0x61
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address Low
Byte
0x70
0xF0
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
-
Primary Interrupt Select
Serial Port 1 Mode Register
LOGICAL DEVICE 5 CONFIGURATION REGISTERS (SERIAL PORT 2)
0x30
0x60
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Activate Note 23-2
Primary Base I/O Address High
Byte
2016-2017 Microchip Technology Inc.
DS00002121B-page 197
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 23-3: CONFIGURATION REGISTER SUMMARY (CONTINUED)
Index
0x61
Type
R/W
PCI Reset VCC POR VTR POR Soft Reset
Configuration Register
0x00
0x00
0x00
0x00
Primary Base I/O Address Low
Byte
0x70
0xF0
0xF1
0xF2
R/W
R/W
R/W
R/W
0x00
0x00
0x02
0x03
0x00
0x00
0x02
0x03
0x00
0x00
0x02
0x03
0x00
Primary Interrupt Select
Serial Port 2 Mode Register
IR Options Register
-
-
-
IR Half Duplex Timeout
LOGICAL DEVICE 6 CONFIGURATION REGISTERS (RESERVED)
LOGICAL DEVICE 7 CONFIGURATION REGISTERS (KEYBOARD)
0x30
0x70
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Activate
Primary Interrupt Select
(Keyboard)
0x72
0xF0
R/W
R/W
0x00
0x00
0x00
0x00
Secondary Interrupt Select
(Mouse)
0x00
0x00
0x00
-
KRESET and GateA20 Select
LOGICAL DEVICE 8 CONFIGURATION REGISTERS (RESERVED)
LOGICAL DEVICE 9 CONFIGURATION REGISTERS (RESERVED)
LOGICAL DEVICE A CONFIGURATION REGISTERS (RUNTIME REGISTERS)
0x30
0x60
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Activate
Primary Base I/O Address High
Byte
0x61
0x62
0x63
R/W
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Primary Base I/O Address Low
Byte
Secondary Base I/O Address High
Byte
Secondary Base I/O Address Low
Byte
0XF0
0xF1
0XF2
R/W
-
-
0X00
0x00
0x04
-
CLOCKI32
R/W
0x00
0x04
0x00
0x04
0x00
-
RESERVED: do not write.
Security Key Control Register
RW / R
LOGICAL DEVICE B CONFIGURATION REGISTERS (SERIAL PORT 3)
AVAILABLE IN SCH3227, SCH3226, SCH3222
RESERVED IN SCH3224
0x30
0x60
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Activate Note 23-2
Primary Base I/O Address High
Byte
0x61
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address Low
Byte
0x70
0xF0
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
-
Primary Interrupt Select
Serial Port 3 Mode Register
LOGICAL DEVICE C CONFIGURATION REGISTERS (SERIAL PORT 4)
AVAILABLE IN SCH3227, SCH3226, SCH3222
RESERVED IN SCH3224
0x30
0x60
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Activate Note 23-2
Primary Base I/O Address High
Byte
0x61
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address Low
Byte
DS00002121B-page 198
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 23-3: CONFIGURATION REGISTER SUMMARY (CONTINUED)
Index
0x70
Type
R/W
PCI Reset VCC POR VTR POR Soft Reset
Configuration Register
0x00
0x00
0x00
0x00
0x00
0x00
0x00
-
Primary Interrupt Select
0xF0
R/W
Serial Port 4 Mode Register
LOGICAL DEVICE D CONFIGURATION REGISTERS (SERIAL PORT 5)
AVAILABLE IN SCH3224, SCH3222; IF STRAPOPT=1 SCH3227, SCH3226
0x30
0x60
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Activate Note 23-2
Primary Base I/O Address High
Byte
0x61
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address Low
Byte
0x70
0xF0
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
-
Primary Interrupt Select
Serial Port 5 Mode Register
LOGICAL DEVICE E CONFIGURATION REGISTERS (SERIAL PORT 6)
AVAILABLE IN SCH3224, SCH3222; IF STRAPOPT=1 SCH3227, SCH3226
0x30
0x60
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Activate Note 23-2
Primary Base I/O Address High
Byte
0x61
R/W
0x00
0x00
0x00
0x00
Primary Base I/O Address Low
Byte
0x70
0xF0
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
-
Primary Interrupt Select
Serial Port 6 Mode Register
LOGICAL DEVICE F CONFIGURATION REGISTERS (RESERVED)
Note 23-2
Serial ports 1 and 2 may be placed in the powerdown mode by clearing the associated activate bit
located at CR30 or by clearing the associated power bit located in the Power Control register at
CR22. Serial ports 3,4,5,6 (if available) may be placed in the powerdown mode by clearing the
associated activate bit located at CR30. When in the powerdown mode, the serial port outputs are
tristated. In cases where the serial port is multiplexed as an alternate function, the corresponding
output will only be tristated if the serial port is the selected alternate function.
23.1.1
GLOBAL CONFIG REGISTERS
The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS
Port for register selection. All unimplemented registers and bits ignore writes and return zero when read.
The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is then used to access the
selected register. These registers are accessible only in the Configuration Mode.
TABLE 23-4: CHIP-LEVEL (GLOBAL) CONFIGURATION REGISTERS
Register
Address
Description
CHIP (GLOBAL) CONTROL REGISTERS
0x00 - 0x01
0x02 W
Reserved - Writes are ignored, reads return 0.
Config Control
The hardware automatically clears this bit after the write, there is no
need for software to clear the bits.
Bit 0 = 1: Soft Reset. Refer to theTable 23-3, “Configuration Register
Summary,” on page 196 for the soft reset value for each register.
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
0x03 - 0x06
Reserved - Writes are ignored, reads return 0.
2016-2017 Microchip Technology Inc.
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SCH3227/SCH3226/SCH3224/SCH3222
TABLE 23-4: CHIP-LEVEL (GLOBAL) CONFIGURATION REGISTERS (CONTINUED)
Register
Address
Description
Logical Device #
0x07 R/W
A write to this register selects the current logical device. This allows
access to the control and configuration registers for each logical
device.
Default = 0x00
on VCC POR,
VTR POR,
SOFT RESET and PCI
RESET
Note:
The Activate command operates only on the selected log-
ical device.
Reserved
0x08 - 0x18,
0x1A-0x1F
Reserved - Writes are ignored, reads return 0.
CHIP-LEVEL, MCHP DEFINED
Device ID -
Hard wired
0x20 R
A read only register which provides Legacy device identification, as
follows:
Default = 0x7D or 0x7F
(see Description).
on VCC POR,
SCH3227 depends on STRAPOPT pin:
if STRAPOPT=0: 0x7D
if STRAPOPT=1: 0x7F
VTR POR,
SOFT RESET and PCI
RESET
SCH3226 depends on STRAPOPT pin:
if STRAPOPT=0: 0x7D
if STRAPOPT=1: 0x7F
SCH3224 = 0x7F
SCH3222 = 0x7F
Device Rev
0x21 R
A read only register which provides device revision information.
Bits[7:0] = current revision when read.
Hard wired
= Current Revision
Power Control
0x22 R/W
Bit[0] Reserved
Bit[1] Reserved
Default = 0x00
on VCC POR,
VTR POR,
SOFT RESET and PCI
RESET
Bit[2] Reserved
Bit[3] Parallel Port Power
Bit[4] Serial Port 1 Power
Bit[5] Serial Port 2 Power
Bit[6] Reserved
Bit[7] Reserved
0: Power Off or Disabled
1: Power On or Enabled
Reserved
0x23 R/W
0x24 R/W
Reserved. This is a read/write register. Writing to this register may
cause unwanted results.
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
OSC
Bit[0] Reserved
Bit [1] PLL Control
Default = 0x44, on on VCC
POR,
VTR POR and
PCI RESET
= 0 PLL is on (backward Compatible)
= 1 PLL is off
Bits[3:2] OSC
= 01 Osc is on, BRG clock is on.
= 10 Same as above (01) case.
= 00 Osc is on, BRG Clock Enabled.
= 11 Osc is off, BRG clock is disabled.
Bit [5:4] Reserved, set to zero
Bit [6] 16-Bit Address Qualification
= 0 12-Bit Address Qualification
= 1 16-Bit Address Qualification
Note:
For normal operation, bit 6 should be set.
Bit[7] Reserved
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TABLE 23-4: CHIP-LEVEL (GLOBAL) CONFIGURATION REGISTERS (CONTINUED)
Register
Address
Description
Configuration Address Byte
0
0x26
Bit[7:1] Configuration Address Bits [7:1]
Bit[0] = 0
(Note 23-3)
Default
Sysopt0 = 0 0x2E
Sysopt0 = 1 0x4E
on VCC POR and PCI
RESET
Configuration Address Byte
1
0x27
Bit[7:0] Configuration Address Bits [15:8]
Bits[15:21] = 0
(Note 23-3)
Default
Sysopt1 = 0 0x16
Sysopt1 = 1 0x00
n VCC POR and PCI
RESET
Default = 0x00
on VCC POR,
SOFT RESET and
PCI RESET
0x28
Bits[7:0] Reserved - Writes are ignored, reads return 0.
Note 23-3
To allow the selection of the configuration address to a user defined location, these Configuration
Address Bytes are used. There is no restriction on the address chosen, except that A0 is 0, that is,
the address must be on an even byte boundary. As soon as both bytes are changed, the configuration
space is moved to the specified location with no delay (Note: Write byte 0, then byte 1; writing CR27
changes the base address).
The configuration address is only reset to its default address upon a PCI Reset or Vcc POR.
Note:
The default configuration address is specified in Table 23-1, “SYSOPT Strap Option Configuration Address
Select,” on page 194.
23.1.2
TEST REGISTERS
The following test registers are used in the SCH322x devices.
TABLE 23-5: TEST REGISTER SUMMARY
Register
Address
Description
TEST 8
0x19 R/W
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
Default = 0x00, on VCC
POR and
VTR POR
TEST 9
0x25 R/W
0x29 R/W
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
Default = 0x00, on VCC
POR and
VTR POR
TEST
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
Default = 0x00
Note on VTR_POR BIT0/7
are reset
BIT1-6 reset on
TST_PORB from resgen
block
TEST 6
0x2A R/W
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
Default = 0x00, on VCC
POR and
VTR POR
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TABLE 23-5: TEST REGISTER SUMMARY (CONTINUED)
Register
Address
Description
TEST 4
0x2B R/W
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
Default = 0x00, on VCC
POR and
VTR POR
TEST 5
0x2C R/W
0x2D R/W
0x2E R/W
0x2F R/W
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
Default = 0x00, on VCC
POR and
VTR POR
TEST 1
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
Default = 0x00, on VCC
POR and
VTR POR
TEST 2
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
Default = 0x00, on VCC
POR and
VTR POR
TEST 3
Test Modes: Reserved for MCHP. Users should not write to this
register, may produce undesired results.
Default = 0x00, on VCC
POR and
VTR POR
23.1.2.1
Logical Device Configuration/Control Registers [0x30-0xFF]
Used to access the registers that are assigned to each logical unit. A separate set (bank) of control and configuration
registers exists for each logical device and is selected with the Logical Device # Register (0x07).
The INDEX PORT is used to select a specific logical device register. These registers are then accessed through the
DATA PORT.
The Logical Device registers are accessible only when the device is in the Configuration State. The logical register
addresses are shown in Table 23-6.
TABLE 23-6: LOGICAL DEVICE REGISTERS
Logical Device Register
Address
Description
Activate
(0x30)
Bits[7:1] Reserved, set to zero.
(Note 23-4)
Bit[0]
Default = 0x00
= 1 Activates the logical device currently selected through
the Logical Device # register.
= 0 Logical device currently selected is inactive
on VCC POR, VTR POR, PCI
RESET and
SOFT RESET
Logical Device Control
Logical Device Control
(0x31-0x37)
(0x38-0x3F)
Reserved – Writes are ignored, reads return 0.
Vendor Defined - Reserved - Writes are ignored, reads return
0.
Memory Base Address
(0x40-0x5F)
(0x60-0x6F)
Reserved – Writes are ignored, reads return 0.
I/O Base Address
(Note 23-5)
Registers 0x60 and 0x61 set the base address for the
device. If more than one base address is required, the
second base address is set by registers 0x62 and 0x63.
Refer to Table 23-7 on page 203 for the number of base
address registers used by each device.
Unused registers will ignore writes and return zero when
read.
0x60,2,... =
addr[15:8]
(see Table 23-7, “Base I/O
Range for Logical Devices,” on
page 203)
0x61,3,... =
addr[7:0]
Default = 0x00
on VCC POR, VTR POR, PCI
RESET and
SOFT RESET
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TABLE 23-6: LOGICAL DEVICE REGISTERS (CONTINUED)
Logical Device Register
Address
Description
Interrupt Select
(0x70,0x72)
0x70 is implemented for each logical device. Refer to
Interrupt Configuration Register description. Only the
keyboard controller uses Interrupt Select register 0x72.
Unused register (0x72) will ignore writes and return zero
when read. Interrupts default to edge high (ISA compatible).
Defaults:
0x70 = 0x00 or 0x06 (Note 23-6)
on VCC POR, VTR POR, PCI
RESET and
SOFT RESET
0x72 = 0x00,
on VCC POR, VTR POR, PCI
RESET and
SOFT RESET
(0x71,0x73)
(0x74,0x75)
Reserved - not implemented. These register locations ignore
writes and return zero when read.
DMA Channel Select
Only 0x74 is implemented for Parallel port. 0x75 is not
implemented and ignores writes and returns zero when read.
Refer to DMA Channel Configuration.
Default = 0x02 or 0x04
(Note 23-6)
on VCC POR, VTR POR, PCI
RESET and
SOFT RESET
32-Bit Memory Space
Configuration
(0x76-0xA8)
(0xA9-0xDF)
(0xE0-0xFE)
0xFF
Reserved - not implemented. These register locations ignore
writes and return zero when read.
Logical Device
Reserved - not implemented. These register locations ignore
writes and return zero when read.
Logical Device Configuration
Reserved
Reserved – Vendor Defined (see MCHP defined Logical
Device Configuration Registers).
Reserved
Note 23-4
A logical device will be active and powered up according to the following equation unless otherwise
specified:
DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET).
The Logical device’s Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or clears the
other.
Note 23-5
If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the Logical
Device I/O map, then read or write is not valid and is ignored.
Note 23-6
The default value of the DMA Channel Select register for logical devices 3 and 5 is 0x04.
TABLE 23-7: BASE I/O RANGE FOR LOGICAL DEVICES
Logical
Register
Index
Base I/O Range
Device
Number
Logical Device
Fixed Base Offsets
(Note 23-7)
0x00
0x01
0x02
0x03
Reserved
Reserved
Reserved
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Parallel
Port
0x60,0x61
[0x0100:0x0FFC]
ON 4 BYTE BOUNDARIES
(EPP Not supported)
or
[0x0100:0x0FF8]
ON 8 BYTE BOUNDARIES
+0 : Data/ecpAfifo
+1 : Status
+2 : Control
+400h : cfifo/ecpDfifo/tfifo/cnfgA
+401h : cnfgB
+402h : ecr
(all modes supported,
EPP is only available when
the base address is on an 8-
byte boundary)
+3 : EPP Address
+4 : EPP Data 0
+5 : EPP Data 1
+6 : EPP Data 2
+7 : EPP Data 3
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TABLE 23-7: BASE I/O RANGE FOR LOGICAL DEVICES (CONTINUED)
Logical
Register
Index
Base I/O Range
Device
Number
Logical Device
Fixed Base Offsets
(Note 23-7)
0x04
Serial Port 1
0x60,0x61
[0x0100:0x0FF8]
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
ON 8 BYTE BOUNDARIES
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
0x05
Serial Port 2
0x60,0x61
[0x0100:0x0FF8]
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
ON 8 BYTE BOUNDARIES
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
0x06
0x07
Reserved
KYBD
n/a
n/a
n/a
n/a
Not Relocatable
Fixed Base Address: 60,64
+0 : Data Register
+4 : Command/Status Reg.
0x08
0x09
0x0A
Reserved
Reserved
n/a
n/a
n/a
n/a
n/a
n/a
Runtime Register
Block
0x60,0x61
[0x0000:0x0F7F]
on 128-byte boundaries
+00 : PME Status
.
.
.
+5F : Keyboard Scan Code
(See Table 24-2 on page 216)
Security Key
Register
0x62, 0x63
0x60,0x61
[0x0000:0x0FDF
on 32-byte boundaries
+00 : Security Key Byte 0
.
.
.
+1F: Security Key Byte 31
0x0B
0x0C
0x0D
Serial Port 3
[0x0100:0x0FF8]
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
APPROPRIATE
DEVICES ONLY
SEE CAUTION IN
Section 23.1,
"Configuration
Registers"
ON 8 BYTE BOUNDARIES
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
Serial Port 4
0x60,0x61
0x60,0x61
[0x0100:0x0FF8]
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
APPROPRIATE
DEVICES ONLY
SEE CAUTION IN
Section 23.1,
"Configuration
Registers"
ON 8 BYTE BOUNDARIES
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
Serial Port 5
[0x0100:0x0FF8]
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
APPROPRIATE
DEVICES ONLY
SEE CAUTION IN
Section 23.1,
"Configuration
Registers"
ON 8 BYTE BOUNDARIES
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
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TABLE 23-7: BASE I/O RANGE FOR LOGICAL DEVICES (CONTINUED)
Logical
Register
Index
Base I/O Range
Device
Number
Logical Device
Fixed Base Offsets
(Note 23-7)
0x0E
Serial Port 6
0x60,0x61
[0x0100:0x0FF8]
+0 : RB/TB/LSB div
+1 : IER/MSB div
+2 : IIR/FCR
+3 : LCR
APPROPRIATE
DEVICES ONLY
SEE CAUTION IN
Section 23.1,
"Configuration
Registers"
ON 8 BYTE BOUNDARIES
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
Config. Port
Config. Port
0x26, 0x27
(Note 23-8)
0x0100:0x0FFE
On 2 byte boundaries
See Configuration Register
Summary and Description.
Accessed through the index and
DATA ports located at the
Configuration Port address and
the Configuration Port address
+1 respectively.
Note 23-7
Note 23-8
This chip uses address bits [A11:A0] to decode the base address of each of its logical devices. This
device performs 16 bit address qualification, therefore address bits [A15:A12] must be ‘0’.
The Configuration Port is at either 0x02E, 0x04EE (for SYSOPT=0 and SYSOPT=1) at power up and
can be relocated via CR26 and CR27.
TABLE 23-8: PRIMARY INTERRUPT SELECT REGISTER
Name
REG Index
Definition
Primary Interrupt
Select
0x70 (R/W)
Bits[3:0] selects which interrupt is used for the primary Interrupt.
0x00= no interrupt selected
0x01= IRQ1
Default=0x00 or 0x06
on VCC POR, VTR
POR,
PCI RESET and
SOFT RESET
0x02= IRQ2/nSMI
0x03= IRQ3
0x04= IRQ4
0x05= IRQ5
0x06= IRQ6
0x07= IRQ7
0x08= IRQ8
0x09= IRQ9
0x0A= IRQ10
0x0B= IRQ11
0x0C= IRQ12
0x0D= IRQ13
0x0E= IRQ14
0x0F= IRQ15
Note:
• All interrupts are edge high (except ECP/EPP)
• nSMI is active low
Note 1: An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero value AND:
- For the PP logical device by setting IRQE, bit D4 of the Control Port and in addition
- For the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr.
- For the Serial Port logical device by setting any combination of bits D0-D3 in the IER and by setting the OUT2
bit in the UART's Modem Control (MCR) Register.
- For the KYBD logical device (refer to Section 10.0, "8042 Keyboard Controller Description," on page 77).
2: IRQs are disabled if not used/selected by any Logical Device. Refer to Note 23-9 on page 206.
3: nSMI must be disabled to use IRQ2.
4: All IRQ’s are available in Serial IRQ mode.
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TABLE 23-9: DMA CHANNEL SELECT
Name
REG Index
Definition
DMA Channel Select
0x74 (R/W)
Bits[2:0] select the DMA Channel.
0x00= Reserved
0x01= DMA1
Default=0x02 or 0x04
(See notes)
on VCC POR, VTR
POR,
PCI RESET and
SOFT RESET
0x02= DMA2
0x03= DMA3
0x04-0x07= No DMA active
Note 1: A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND:
2: For the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr.
3: The DMA channel must be disabled if not used/selected by any Logical Device. Refer to Note A.
4: The default value of the DMA Channel Select register for logical device 3 and 5 is 0x04.
Note 23-9
Logical Device IRQ and DMA Operation. IRQ and DMA Enable and Disable: Any time the IRQ or
DMA channel for a logical block is disabled by a register bit in that logical block, the IRQ and/or DMA
channel must be disabled. This is in addition to the IRQ and DMA channel disabled by the
Configuration Registers (Active bit or address not valid).
Serial Ports:
Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic “0”, the serial port interrupt is disabled.
Disabling DMA Enable bit, disables DMA for UART2. Refer to the IrCC specification.
Parallel Port:
SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to “0”, IRQ is disabled.
ECP Mode:
• (DMA) dmaEn from ecr register. See table.
• IRQ - See table.
Mode
(From ECG Register)
IRQ Controlled By
DMA Controlled By
000
001
010
011
100
101
110
111
PRINTER
IRQE
IRQE
(on)
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
SPP
FIFO
ECP
(on)
EPP
IRQE
IRQE
(on)
RES
TEST
CONFIG
IRQE
Keyboard Controller: Refer to the 8042 Keyboard Controller Description on page 77 of this document.
MCHP Defined Logical Device Configuration Registers
The MCHP Specific Logical Device Configuration Registers reset to their default values only on PCI resets generated
by Vcc or VTR POR (as shown) or the PCI_RESET# signal. These registers are not affected by soft resets.
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TABLE 23-10: PARALLEL PORT, LOGICAL DEVICE 3 [LOGICAL DEVICE NUMBER = 0X03]
Name
REG Index
Definition
PP Mode Register
0xF0 R/W
Bits[2:0] Parallel Port Mode
= 100 Printer Mode (default)
Default = 0x3C
on VCC POR,
VTR POR and
PCI RESET
= 000 Standard and Bi-directional (SPP) Mode
= 001 EPP-1.9 and SPP Mode
= 101 EPP-1.7 and SPP Mode
= 010 ECP Mode
= 011 ECP and EPP-1.9 Mode
= 111 ECP and EPP-1.7 Mode
Bit[6:3] ECP FIFO Threshold
0111b (default)
Bit[7] PP Interrupt Type
Not valid when the parallel port is in the Printer Mode (100) or the
Standard & Bi-directional Mode (000).
= 1 Pulsed Low, released to high-Z.
= 0 IRQ follows nACK when parallel port in EPP Mode or [Printer,
SPP, EPP] under ECP.
IRQ level type when the parallel port is in ECP, TEST, or Centronics
FIFO Mode.
PP Mode Register 2
0xF1 R/W
Bit [3:0] Reserved. Set to zero.
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Bit [4] TIMEOUT_SELECT
= 0 TMOUT (EPP Status Reg.) cleared on write of ‘1’ to TMOUT.
= 1 TMOUT cleared on trailing edge of read of EPP Status Reg.
Bits[7:5] Reserved. Set to zero.
TABLE 23-11: SERIAL PORT 1, LOGICAL DEVICE 4 [LOGICAL DEVICE NUMBER = 0X04]
Name
REG Index
Definition
Serial Port 1
Mode Register
0xF0 R/W
Bit[0] MIDI Mode
= 0 MIDI support disabled (default)
= 1 MIDI support enabled
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Bit[1] High Speed
= 0 High Speed Disabled (default)
= 1 High Speed Enabled
Bit [3:2] Enhanced Frequency Select
= 00 Standard Mode (default)
= 01 Select 921K
= 10 Select 1.5M
= 11 Reserved
Bit[5:4] Reserved, set to zero
Bit[6] All Share IRQ
=0 Use bit 7 to determine sharing
=1 Share all serial ports on the
SCH3227/SCH3226/SCH3224/SCH3222 device.
Bit[7]: Share IRQ
=0 UARTs 1,2 use different IRQs
=1 UARTs 1,2 share a common IRQ
(Note 23-10)
Note 23-10 To properly share and IRQ:
• Configure UART1 (or UART2) to use the desired IRQ.
• Configure UART2 (or UART1) to use No IRQ selected.
• Set the share IRQ bit.
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Note:
If both UARTs are configured to use different IRQs and the share IRQ bit is set, then both of the UART IRQs
will assert when either UART generates an interrupt.
TABLE 23-12: SERIAL PORT 2. LOGICAL DEVICE 5 [LOGICAL DEVICE NUMBER = 0X05]
Name
REG Index
Definition
Serial Port 2 Mode
Register
0xF0 R/W
Bit[0] MIDI Mode
= 0 MIDI support disabled (default)
= 1 MIDI support enabled
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Bit[1] High Speed
= 0 High Speed Disabled(default)
= 1 High Speed Enabled
Bit [3:2] Enhanced Frequency Select
= 00 Standard Mode (default)
= 01 Select 921K
= 10 Select 1.5M
= 11 Reserved
Bit[4] Reserved, set to zero
Bit[5] TXD2_MODE (See Note 23-11.)
=0 TXD2 pin reflects current configuration state
=1 Override current pin configuration and force TXD2 pin tristate.
Bits[7:6] Reserved. Set to zero.
IR Option Register
0xF1 R/W
Bit[0] Receive Polarity
= 0 Active High (Default)
= 1 Active Low
Default = 0x02
on VCC POR,
VTR POR and
PCI RESET
Bit[1] Transmit Polarity
= 0 Active High
= 1 Active Low (Default)
Bit[2] Duplex Select
= 0 Full Duplex (Default)
= 1 Half Duplex
Bits[5:3] IR Mode
= 000 Standard COM Functionality (Default)
= 001 IrDA
= 010 ASK-IR
= 011 Reserved
= 1xx Reserved
Bit[6] Reserved Set to 0.
Bit[7] Reserved, write 0.
IR Half Duplex Timeout
0xF2
Bits [7:0]
These bits set the half duplex time-out for the IR port. This value is
0 to 10msec in 100usec increments.
0= blank during transmit/receive
Default = 0x03
on VCC POR,
VTR POR and
PCI RESET
1= blank during transmit/receive + 100usec
Note 23-11 The TXD2_MODE bit is a VTR powered bit that is reset on VTR POR only.
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TABLE 23-13: KYBD. LOGICAL DEVICE 7 [LOGICAL DEVICE NUMBER = 0X07]
Name
KRST_GA20
REG Index
Definition
0xF0
R/W
KRESET and GateA20 Select
Bit[7] Polarity Select for P12
= 0 P12 active low (default)
= 1 P12 active high
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Bit[6] M_ISO. Enables/disables isolation of mouse signals into 8042.
Does not affect MDAT signal to mouse wakeup (PME) logic.
1= block mouse clock and data signals into 8042
0= do not block mouse clock and data signals into 8042
Bit[5] K_ISO. Enables/disables isolation of keyboard signals into
8042. Does not affect KDAT signal to keyboard wakeup (PME) logic.
1= block keyboard clock and data signals into 8042
0= do not block keyboard clock and data signals into 8042
Bit[4] MLATCH
Bits[6:5] reset on VTR
POR only
= 0 MINT is the 8042 MINT ANDed with Latched MINT (default)
= 1 MINT is the latched 8042 MINT
Bit[3] KLATCH
= 0 KINT is the 8042 KINT ANDed with Latched KINT (default)
= 1 KINT is the latched 8042 KINT
Bit[2] Port 92 Select
= 0 Port 92 Disabled
= 1 Port 92 Enabled
Bit[1] Reserved (read/write bit)
Bit[0] Reserved (read/write bit)
2016-2017 Microchip Technology Inc.
DS00002121B-page 209
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 23-14: LOGICAL DEVICE A [LOGICAL DEVICE NUMBER = 0X0A]
Name
CLOCKI32
REG Index
Definition
0xF0
(R/W)
Bit[0] (CLK32_PRSN)
0 = 32kHz clock is connected to the CLKI32 pin (default)
1 = 32kHz clock is not connected to the CLKI32 pin (pin is grounded)
Bit[1] SPEKEY_EN. This bit is used to turn the logic for the “wake on
specific key” feature on and off. It will disable the 32kHz clock input to
the logic when turned off. The logic will draw no power when disabled.
0 = “Wake on specific key” logic is on (default)
Default = 0x00 on VTR
POR
1 = “Wake on specific key” logic is off
Bit[2] Reserved (read-only bit)
Reads return 0. Writes have no effect.
Bit[3] SPEMSE_EN
This bit is used to turn the logic for the “wake on specific mouse click”
feature on and off. It will disable the 32 Khz clock input to the logic
when turned off. The logic will draw no power when disabled.
0 = “wake on specific mouse click” logic is on (default)
1 = “wake on specific mouse click” logic is off
Bits[7:4] are reserved
Reserved Register
0xF1 R/W
0xF2
Bits[7:0] Reserved. Set to zero.
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Security Key Control
(SKC) Register
Bit[0] SKC Register Lock
This bit blocks write access to the Security Key Control Register.
0 = Security Key Control Register is a Read/Write register (default)
1 = Security Key Control Register is a Read-Only register
Bit[1] Read-Lock
R/W when
bit[0]= 0
Default=0x04 on a VTR
POR, VCC POR, PCI
Reset
This bit prevents reads from the Security Key registers located at an
offset from the Secondary Base I/O address in Logical Device A
0 = Permits read operations in the Security Key block (default)
1 = Prevents read operations in the Security Key block (Reads return
00h.)
Read-Only when
bit[0]=1
Bit[2] Write-Lock
This bit prevents writes to the Security Key registers located at an
offset from the Secondary Base I/O address in Logical Device A
0 = Permits write operations in the Security Key block
1 = Prevents write operations in the Security Key block (default)
Bit[3] Reserved
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
Note:
The registers located in Logical Device A are runtime registers.
DS00002121B-page 210
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 23-15: SERIAL PORT 3, LOGICAL DEVICE B [LOGICAL DEVICE NUMBER = 0X0B]
Name
REG Index
Definition
Serial Port 3
Mode Register
0xF0 R/W
Bit[7:0] MCHP Test Bit
Must be written with zero for proper operation.
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
SCH3224 device.
Serial Port 3
Mode Register
0xF0 R/W
Bit[0] MIDI Mode
= 0 MIDI support disabled (default)
= 1 MIDI support enabled
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Bit[1] High Speed
= 0 High Speed Disabled (default)
= 1 High Speed Enabled
SCH3227, SCH3226 and
SCH3222 devices.
Bit [3:2] Enhanced Frequency Select
= 00 Standard Mode (default)
= 01 Select 921K
= 10 Select 1.5M
= 11 Reserved
Bit[5:4] Reserved, set to zero
Bit[6] MCHP Test Bit
Must be written with zero for proper operation.
Bit[7]: Share IRQ
=0 UARTs 3,4 use different IRQs
=1 UARTs 3,4 share a common IRQ
(Note 23-10)
TABLE 23-16: SERIAL PORT 4, LOGICAL DEVICE C LOGICAL DEVICE NUMBER = 0X0C]
Name
REG Index
Definition
Serial Port 4
Mode Register
0xF0 R/W
Bit[7:0] MCHP Test Bit
Must be written with zero for proper operation.
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
SCH3224 device.
Serial Port 4
Mode Register
0xF0 R/W
Bit[0] MIDI Mode
= 0 MIDI support disabled (default)
= 1 MIDI support enabled
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Bit[1] High Speed
= 0 High Speed Disabled(default)
= 1 High Speed Enabled
SCH3227, SCH3226 and
SCH3222 devices.
Bit [3:2] Enhanced Frequency Select
= 00 Standard Mode (default)
= 01 Select 921K
= 10 Select 1.5M
= 11 Reserved
Bit[5:4] Reserved, set to zero
Bit[7:6] MCHP Test Bit
Must be written with zero for proper operation.
2016-2017 Microchip Technology Inc.
DS00002121B-page 211
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 23-17: SERIAL PORT 5, LOGICAL DEVICE D [LOGICAL DEVICE NUMBER = 0X0D]
Name
REG Index
Definition
Serial Port 5
Mode Register
0xF0 R/W
Bit[0] MIDI Mode
= 0 MIDI support disabled (default)
= 1 MIDI support enabled
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Bit[1] High Speed
= 0 High Speed Disabled (default)
= 1 High Speed Enabled
Bit [3:2] Enhanced Frequency Select
= 00 Standard Mode (default)
= 01 Select 921K
= 10 Select 1.5M
= 11 Reserved
Bit[5:4] Reserved, set to zero
Bit[6] MCHP Test Bit
Must be written with zero for proper operation.
Bit[7]: Share IRQ
=0 UARTs 5,6 use different IRQs
=1 UARTs 5,6 share a common IRQ
(Note 23-10)
TABLE 23-18: SERIAL PORT 6, LOGICAL DEVICE E LOGICAL DEVICE NUMBER = 0X0E]
Name
REG Index
Definition
Serial Port 6
Mode Register
0xF0 R/W
Bit[0] MIDI Mode
= 0 MIDI support disabled (default)
= 1 MIDI support enabled
Default = 0x00
on VCC POR,
VTR POR and
PCI RESET
Bit[1] High Speed
= 0 High Speed Disabled(default)
= 1 High Speed Enabled
Bit [3:2] Enhanced Frequency Select
= 00 Standard Mode (default)
= 01 Select 921K
= 10 Select 1.5M
= 11 Reserved
Bit[5:4] Reserved, set to zero
Bit[7:6] MCHP Test Bit
Must be written with zero for proper operation.
DS00002121B-page 212
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
24.0 RUNTIME REGISTER
CAUTION: This device architecture contains registers, controlling GPIOs or other pin features that may not be brought
out to package pins in some specific family members. See Table 2-1 SCH3227, Table 2-2 SCH3226, Table 2-3
SCH3224, or Table 2-4 SCH3222, for the pins that are brought out. Pins which are not brought out must not be used
because they are tied to known states internally. Do not change their configurations from their POR defaults, because
doing so may cause unpredictable behavior and/or excessive currents, and therefore may damage the device and/or
the system.
24.1 Runtime Register
The following registers are runtime registers in the SCH322x. They are located at the address programmed in the Base
I/O Address in Logical Device A (also referred to as the Runtime Register) at the offset shown. These registers are pow-
ered by VTR.
Table 24-1 summarizes the runtime register differences between the SCH3227/SCH3226/SCH3224/SCH3222 family
member devices. Table 24-2 gives the POR information for each of the registers. A complete description of each of the
registers is given in Section 24.2, "Runtime Register Description," on page 221.
TABLE 24-1: SCH322X RUNTIME REGISTER SUMMARY
Register Offset
SCH3222 Register
SCH3224 Register
SCH3226, SCH3227 Register
(HEX)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
PME_STS
PME_STS
PME_STS
Reserved – reads return 0
PME_EN
Reserved – reads return 0
PME_EN
Reserved – reads return 0
PME_EN
Reserved – reads return 0
PME_STS1
Reserved – reads return 0
PME_STS1
Reserved – reads return 0
PME_STS1
PME_STS3
PME_STS3
PME_STS3
PME_STS5 (Note 24-1)
PME_STS6
PME_STS5 (Note 24-1)
PME_STS6
PME_STS5 (Note 24-1)
PME_STS6 (Note 24-2)
PME_EN1
PME_EN1
PME_EN1
PME_EN3
PME_EN3
PME_EN3
PME_EN5
PME_EN5
PME_EN5
PME_EN6
PME_EN6
PME_EN6 (Note 24-2)
PME_STS7 (Note 24-3)
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
PME_EN7 (Note 24-3)
Reserved – reads return 0
SP12
PME_STS7 (Note 24-3)
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
PME_EN7 (Note 24-3)
Reserved – reads return 0
SP12
PME_STS7 (Note 24-3)
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
PME_EN7 (Note 24-3)
Reserved – reads return 0
SP12
12
13
14
15
16
17
18
19
1A
1B
Reserved – reads return 0
SMI_STS1
SP34
SP34
SMI_STS1
SMI_STS1
SMI_STS2
SMI_STS2
SMI_STS2
SMI_STS3
SMI_STS3
SMI_STS3
SMI_STS4 (Note 24-4)
SMI_EN1
SMI_STS4 (Note 24-4)
SMI_EN1
SMI_STS4 (Note 24-4)
SMI_EN1
SMI_EN2
SMI_EN2
SMI_EN2
SMI_EN3
SMI_EN3
SMI_EN3
SMI_EN4 (Note 24-4)
SMI_EN4 (Note 24-4)
SMI_EN4 (Note 24-4)
2016-2017 Microchip Technology Inc.
DS00002121B-page 213
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-1: SCH322X RUNTIME REGISTER SUMMARY (CONTINUED)
Register Offset
SCH3222 Register
SCH3224 Register
SCH3226, SCH3227 Register
(HEX)
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
MSC_STS
MSC_STS
MSC_STS
RESGEN
RESGEN
RESGEN
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UART1 FIFO Control Shadow
UART1 FIFO Control Shadow
UART2 FIFO Control Shadow
Reserved - Indeterminate
GP10 (Note 24-6)
GP11 (Note 24-6)
GP12 (Note 24-6)
GP13 (Note 24-6)
GP14 (Note 24-6)
Reserved - Indeterminate
GP15 (Note 24-6)
GP16 (Note 24-6)
GP17 (Note 24-6)
GP21
UART1 FIFO Control Shadow
UART2 FIFO Control Shadow
UART3 FIFO Control Shadow
GP10 (Note 24-6)
GP11 (Note 24-6)
GP12 (Note 24-6)
GP13 (Note 24-6)
GP14 (Note 24-6)
UART4 FIFO Control Shadow
GP15 (Note 24-6)
GP16 (Note 24-6)
GP17 (Note 24-6)
GP21
UART2 FIFO Control Shadow
UART3 FIFO Control Shadow
GP10
GP11
GP12
GP13
GP14
UART4 FIFO Control Shadow
GP15
GP16
GP17
GP21
GP22
GP22
GP22
UART5 FIFO Control Shadow
UART5 FIFO Control Shadow
If STRAPOPT=1:
UART5 FIFO Control Shadow
If STRAPOPT=0:
Reserved
2F
30
31
UART6 FIFO Control Shadow
SP5 Option
UART6 FIFO Control Shadow
SP5 Option
If STRAPOPT=1:
UART6 FIFO Control Shadow
If STRAPOPT=0:
Reserved
If STRAPOPT=1:
SP5 Option
If STRAPOPT=0:
Reserved
SP6 Option
SP6 Option
If STRAPOPT=1:
SP6 Option
If STRAPOPT=0:
Reserved
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
GP27
GP27
GP27
GP30
GP30
GP30
GP31
GP31(Note 24-6)
GP32
GP31(Note 24-6)
GP32
GP32
GP33
GP33
GP33
GP34
GP34 (Note 24-6)
Reserved
GP34 (Note 24-6)
Reserved
Reserved
GP36
GP36
GP36
GP37
GP37
GP37
GP40
GP40
GP40
CLK_OUT Register
GP42
CLK_OUT Register
GP42
CLK_OUT Register
GP42
Reserved – reads return 0
GP50
Reserved – reads return 0
GP50
Reserved – reads return 0
GP50
DS00002121B-page 214
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-1: SCH322X RUNTIME REGISTER SUMMARY (CONTINUED)
Register Offset
SCH3222 Register
SCH3224 Register
SCH3226, SCH3227 Register
(HEX)
40
41
42
43
44
45
46
47
48
49
GP51
GP52
GP53
GP54
GP55
GP56
GP57
GP60
GP61
GP51
GP52
GP53
GP54
GP55
GP56
GP57
GP60
GP61
GP51
GP52
GP53
GP54
GP55
GP56
GP57
GP60
GP61
PWR_REC
PWR_REC
Reserved – reads return 0
(Note 24-2)
4A
PS_ON Register
PS_ON Register
Reserved – reads return 0
(Note 24-2)
4B
4C
4D
4E
4F
50
51
52
53
GP1
GP1
GP1
GP2
GP2
GP2
GP3
GP3
GP3
GP4
GP4
GP4
GP5
GP5
GP5
GP6
GP6
GP6
Reserved – reads return 0
Reserved – reads return 0
PS_ON# Previous State
Reserved – reads return 0
Reserved – reads return 0
PS_ON# Previous State
Reserved – reads return 0
Reserved – reads return 0
If STRAPOPT=0:
PS_ON# Previous State
If STRAPOPT=1:
Reserved – reads return 0,
and Note 24-2 applies.
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
GP62
GP62 (Note 24-6)
GP63 (Note 24-6)
GP64(Note 24-6)
GP65(Note 24-6)
GP66(Note 24-6)
GP67 (Note 24-6)
TEST
GP62 (Note 24-6)
GP63 (Note 24-6)
GP64(Note 24-6)
GP65(Note 24-6)
GP66(Note 24-6)
GP67 (Note 24-6)
TEST
GP63
GP64
GP65
GP66
GP67
TEST
DBLCLICK
Mouse_Specific_ Wake
LED1
DBLCLICK
DBLCLICK
Mouse_Specific_ Wake
LED1
Mouse_Specific_ Wake
LED1
LED2
LED2
LED2
Keyboard Scan Code – Make
Byte 1
Keyboard Scan Code – Make
Byte 1
Keyboard Scan Code – Make
Byte 1
60
61
62
Keyboard Scan Code – Make
Byte 2
Keyboard Scan Code – Make
Byte 2
Keyboard Scan Code – Make
Byte 2
Keyboard Scan Code – Break Keyboard Scan Code – Break Keyboard Scan Code – Break
Byte 1 Byte 1 Byte 1
Keyboard Scan Code – Break Keyboard Scan Code – Break Keyboard Scan Code – Break
Byte 2 Byte 2 Byte 2
2016-2017 Microchip Technology Inc.
DS00002121B-page 215
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-1: SCH322X RUNTIME REGISTER SUMMARY (CONTINUED)
Register Offset
SCH3222 Register
SCH3224 Register
SCH3226, SCH3227 Register
(HEX)
63
Keyboard Scan Code – Break Keyboard Scan Code – Break Keyboard Scan Code – Break
Byte 3
Byte 3
Byte 3
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
Keyboard PWRBTN/SPEKEY
WDT_TIME_OUT
Keyboard PWRBTN/SPEKEY
WDT_TIME_OUT
Keyboard PWRBTN/SPEKEY
WDT_TIME_OUT
WDT_VAL
WDT_VAL
WDT_VAL
WDT_CFG
WDT_CFG
WDT_CFG
WDT_CTRL
WDT_CTRL
WDT_CTRL
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
GP45 (Note 24-7)
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
GP45 (Note 24-7)
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
GP45 (Note 24-8)
Reserved - do not write.
Reserved - do not write.
GP46 (Note 24-7)
HWM Index Register
HWM Data Register
GP46 (Note 24-7)
HWM Index Register
HWM Data Register
GP46 (Note 24-8)
GP47 (Note 24-7)
GP47 (Note 24-7)
GP47 (Note 24-8)
74-7Fh
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
TABLE 24-2: RUNTIME REGISTER POR SUMMARY
RegisterOffset
(HEX)
VCC
POR
VTR
POR
Type PCI Reset
Soft Reset Vbat POR
Register
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
R/WC
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0x00
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PME_STS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reserved – reads return 0
PME_EN
R/W
R
0x00
-
Reserved – reads return 0
PME_STS1
R/WC
R/WC
R/WC
R/WC
R/W
R/W
R/W
R/W
R/WC
R
0x00
0x00
0x00
Note 24-9
0x00)
0x00
0x00
0x00
0x00
-
PME_STS3
PME_STS5 (Note 24-1)
PME_STS6
PME_EN1
PME_EN3
PME_EN5
PME_EN6
PME_STS7
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
PME_EN7
R
-
R
-
R/W
R
0x00
0x00
0x44
0x00
RESERVED
12
13
R/W
R
SP12
RESERVED
(SCH3224)
DS00002121B-page 216
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-2: RUNTIME REGISTER POR SUMMARY (CONTINUED)
RegisterOffset
(HEX)
VCC
POR
VTR
POR
Type PCI Reset
Soft Reset Vbat POR
Register
13
R/W
-
-
0x00
-
SP34
(SCH3227, SCH3226,
SCH3222)
14
15
Note 2
4-16
-
-
-
-
Note 24-9
0x00
-
-
-
-
SMI_STS1
Note 2
4-16
SMI_STS2
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
R/WC
R/WC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
-
-
-
-
-
-
-
-
-
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x03
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SMI_STS3
-
SMI_STS4
-
SMI_EN1
-
SMI_EN2
-
SMI_EN3
-
SMI_EN4
-
MSC_STS
-
RESGEN
0x03
0x03
RESERVED
-
-
-
-
-
-
-
-
RESERVED
R
-
UART1 FIFO Control Shadow
UART2 FIFO Control Shadow
R
-
R
-
RESERVED
(SCH3224)
22
R
-
-
-
-
-
UART3 FIFO Control Shadow
(SCH3227, SCH3226,
SCH3222)
23
24
25
26
27
28
R/W
R/W
R/W
R/W
R/W
R
-
-
-
-
-
-
-
-
-
-
-
-
0x01
0x01
0x01
0x01
0x01
0x00
-
-
-
-
-
-
-
-
-
-
-
-
GP10
GP11
GP12
GP13
GP14
RESERVED
(SCH3224)
28
R
-
-
0x00
-
-
UART4 FIFO Control Shadow
(SCH3227, SCH3226,
SCH3222)
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0x01
0x01
0x01
0x8C
0x8C
0x00
0x00
0x04
0x04
0x01
0x05
0x01
0x84
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GP15
R
GP16
R
GP17
R/W
R/W
R
GP21
GP22
UART5 FIFO Control Shadow
R
UART6 FIFO Control Shadow
R/W
R/W
R/W
R/W
R/W
R/W
SP5 Option
SP6 Option
GP27
GP30
GP31
GP32
2016-2017 Microchip Technology Inc.
DS00002121B-page 217
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-2: RUNTIME REGISTER POR SUMMARY (CONTINUED)
RegisterOffset
(HEX)
VCC
POR
VTR
POR
Type PCI Reset
R/W
Soft Reset Vbat POR
Register
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0x84
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GP33
R/W
R
0x01
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GP34
Reserved
GP36
R/W
R/W
R/W
R
0x01
0x01
0x01
0x00
0x01
-
GP37
GP40
CLK_OUT Register
R/W
R
GP42
Reserved – reads return 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
0x01
GP50
GP51
GP52
GP53
GP54
GP55
GP56
GP57
GP60
GP61
Note 2 0xxxxxxxx
0xxxxxx11 -
0x00000x PWR_REC
4-11
b Note 24-
12
b
xb
Note 24-
12
(SCH3227 or SCH3226, and
STRAPOPT=0)
Note 24-
12
49
R
0xxxxxxxx
b Note 24-
12
-
0xxxxxx11 -
0x00000x RESERVED
b
xb
(SCH3222, SCH3224, or
Note 24-
12
Note 24-
12
SCH3227 / SCH3226 with
STRAPOPT=1)
4A
4A
R
R
-
-
-
-
-
-
-
-
0x00
0x00
PS_ON Register
(SCH3227 or SCH3226, and
STRAPOPT=0)
RESERVED
(SCH3222, SCH3224, or
SCH3227 / SCH3226 with
STRAPOPT=1)
4B
4C
4D
4E
4F
50
51
52
53
R/W
R/W
R/W
R/W
R/W
R/W
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0x00
0x00
0x00
0x00
0x00
0x00
-
-
-
-
-
-
-
-
-
-
-
GP1
-
GP2
-
GP3
-
GP4
-
GP5
-
GP6
-
Reserved – reads return 0
Reserved – reads return 0
R
-
-
R/W
-
0x00
PS_ON# Previous State
(SCH3227 or SCH3226, and
STRAPOPT=0)
53
R
-
-
-
-
0x00
RESERVED
(SCH3222, SCH3224, or
SCH3227 / SCH3226 with
STRAPOPT=1)
DS00002121B-page 218
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-2: RUNTIME REGISTER POR SUMMARY (CONTINUED)
RegisterOffset
(HEX)
VCC
POR
VTR
POR
Type PCI Reset
Soft Reset Vbat POR
Register
54
55
56
57
58
59
5A
5B
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0x01
-
-
GP62
R
R
R
R
R
R
0x01
0x01
0x01
0x01
0x01
-
-
-
-
-
-
-
-
-
GP63
-
GP64
-
GP65
-
GP66
-
GP67
-
TEST
Note 2
4-17
-
0x0C
DBLCLICK
5C
Note 2 Note 24-9 Note 24- Note 24-9
-
-
Mouse_Specific_ Wake
4-17
R/W
R/W
9
5D
5E
5F
-
-
-
-
0x00
0x00
-
-
-
-
-
LED1
LED2
-
-
Note 2
4-13
-
0xE0
Keyboard Scan Code – Make
Byte 1
60
61
62
63
64
Note 2
4-13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0x37
0xE0
0xF0
0x37
Keyboard Scan Code – Make
Byte 2
Note 2
4-13
Keyboard Scan Code – Break
Byte 1
Note 2
4-13
Keyboard Scan Code – Break
Byte 2
Note 2
4-13
Keyboard Scan Code – Break
Byte 3
Note 2 Note 24-9 Note 24- Note 24-9
Note 24-9 Keyboard PWRBTN/SPEKEY
4-13
R/W
R/W
R/W
R/W
9
65
66
67
68
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
-
-
-
-
-
-
-
-
WDT_TIME_OUT
WDT_VAL
WDT_CFG
WDT_CTRL
Note 2 Note 24-14
4-15
69
6A
6B
6C
6D
6E
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
Reserved – reads return 0
(SCH3227 or SCH3226, and
STRAPOPT=0)
6E
R/W
-
-
0x01
-
-
GP44
(SCH3222, SCH3224, or
SCH3227 / SCH3226 with
STRAPOPT=1)
6F
6F
R/W
R/W
-
-
-
-
0x00
0x01
-
-
-
-
GP45
(SCH3227 or SCH3226, and
STRAPOPT=0)
GP45
(SCH3222, SCH3224, or
SCH3227 / SCH3226 with
STRAPOPT=1)
2016-2017 Microchip Technology Inc.
DS00002121B-page 219
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-2: RUNTIME REGISTER POR SUMMARY (CONTINUED)
RegisterOffset
(HEX)
VCC
POR
VTR
POR
Type PCI Reset
Soft Reset Vbat POR
Register
70
71
72
R/W
-
-
-
-
-
-
0x00
-
-
-
-
HWM Index Register
(RESERVED in SCH3222)
R/W
R/W
0x00
0x00
-
-
HWM Data Register
(RESERVED in SCH3222)
GP46
(SCH3227 or SCH3226, and
STRAPOPT=0)
72
R/W
-
-
0x01
-
-
GP46
(SCH3222, SCH3224, or
SCH3227 / SCH3226 with
STRAPOPT=1)
73
73
R/W
R/W
-
-
-
-
0x00
0x01
-
-
-
-
GP47
(SCH3227 or SCH3226, and
STRAPOPT=0)
GP47
(SCH3222, SCH3224, or
SCH3227 / SCH3226 with
STRAPOPT=1)
74-7Fh
R
-
-
-
-
-
Reserved – reads return 0
Note 24-1
Bit 3 of the PME_STS5 register may be set on a VCC POR. If GP53 are configured as input, then
their corresponding PME and SMI status bits will be set on a VCC POR.
Note 24-2
Note 24-3
Note 24-4
This register does not support the Power failure recovery status.
This register supports ring indicator status bits for serial ports 3-6 if required by the particular device.
This register supports additional UART interrupt status bits for serial ports 3-6 if required by the
particular device
Note 24-5
Note 24-6
Note 24-7
Note 24-8
Note 24-9
This register supports alternate functions for serial port 3.
This register supports alternate functions for serial port 4.
This register supports alternate functions for pci reset outputs.
This register supports alternate functions for serial port 6.
See the register description for the default value.
Note 24-10 Bit[0] cannot be written to '1'. Bit[1] and Bit[7] are read-only.
Note 24-11 This register is a read/write register when bit[7]=0, except bit[4]. Bit[4] is a read-only bit. This register
is a read-only register when bit7]=1.
Note 24-12 This is a binary number. The x's denote a bit that is not affected by the reset condition.
Note 24-13 This register is read/write when Bit [7] Keyboard PWRBTN/SPEKEY Lock of the Keyboard
PWRBTN/SPEKEY register at offset 64h is set to '0' and Read-Only when Bit [7] is set to '1'.
Note 24-14 Bit 0 is not cleared by PCI RESET.
Note 24-15 This register contains some bits that are read or write only.
Note 24-16 See the register description for the bit-wise access type.
Note 24-17 This register is read/write when Bit [7] in the Mouse_Specific_ Wake Register is set to '0' and Read-
Only when Bit [7] is set to '1'.
DS00002121B-page 220
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
24.2 Runtime Register Description
The following registers are located at an offset from (PME_BLK) the address programmed into the base I/O address
register for Logical Device A.
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION
REG Offset
Name
Description
(HEX)
PME_STS
00
PME Pin Status Register
Bit[0] PME_Status
= 0 (default)
Default = 0x00
on VTR POR
(R/WC)
= 1 Autonomously Set when a wakeup event occurs that normally asserts
the nIO_PME signal. This bit is set independent of the state of the PME_EN
bit
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT RESET or PCI RESET.
Writing a “1” to PME_Status will clear it and cause the device to stop
asserting nIO_PME, in enabled. Writing a “0” to PME_Status has no effect.
PME_EN
02
PME Pin Enable Register
Bit[0] PME_En
Default = 0x00
on VTR POR
(R/W)
= 0 nIO_PME signal assertion is disabled (default)
= 1 Enables this device to assert nIO_PME signal
Bit[7:1] Reserved
PME_En is not affected by Vcc POR, SOFT RESET or PCI RESET
PME_STS1
04
PME Wake Status Register 1
This register indicates the state of the individual PME wake sources,
Default = 0x00
on VTR POR
(R/WC)
independent of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] HW_Monitor
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[5] Reserved
Bit[6] IRINT. This bit is set by a transition on the IR pin (IRRX)
Bit[7] Reserved
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
PME_STS3
05
PME Wake Status Register 3
This register indicates the state of the individual PME wake sources,
Default = 0x00
on VTR POR
(R/WC)
independent of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] WDT
Bit[1] GP21
Bit[2] GP22
Bit[3] DEVINT_STS (status of group SMI signal for PME)
Bit[4] GP27
Bit[5] GP32
Bit[6] GP33
Bit[7] Reserved
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
2016-2017 Microchip Technology Inc.
DS00002121B-page 221
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
PME_STS5
06
PME Wake Status Register 5
This register indicates the state of the individual PME wake sources,
Default = 0x00
on VTR POR
(R/WC)
independent of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Bit[0] GP50
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
PME_STS6
07
This register indicates the state of the individual PME sources, independent
of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Default = 0x00 or
0x01 on VTR POR
(R/WC)
The default will be
0x01 if there is a
LOW_BAT event
under VBAT power
only, 0x00 if the event
does not occurs.
Bit[0] LOW_BAT, Cleared by a write of ‘1’.
When the battery is removed and replaced or the if the battery voltage drops
below 1.2V under battery power, then the LOW_BAT PME status bit is set
on VTR POR. When the battery voltage drops below 2.4 volts under VTR
power (VCC=0) or under battery power only, the LOW_BAT PME status bit
is set on VCC POR. The corresponding enable bit must be set to generate
a PME. The low battery event is not a PME wakeup event.
Bit[0] will be set to ‘1’
on a VCC POR if the
battery voltage drops
below 2.4V under
VTR power (VCC=0)
or under battery
Bit[1] RESERVED.
Bit[2] GP60
Bit[3] GP61
Bit[4] SPEMSE_STS (Wake on specific mouse click)
Bit[5] SPEKEY_STS (Wake on specific key)
Bit[6] PB_STS
power only.
(SCH3227 or
SCH3226, and
STRAPOPT=0)
Bit[7] PFR_STS Power Failure Recovery Status
The PME Status register is not affected by VCC POR, SOFT RESET or PCI
RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Status
Register has no effect.
DS00002121B-page 222
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
PME_STS6
07
This register indicates the state of the individual PME sources, independent
of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
nIO_PME pin.
Default = 0x00 or
0x01 on VTR POR
(R/WC)
The default will be
0x01 if there is a
LOW_BAT event
under VBAT power
only, 0x00 if the event
does not occurs.
Bit[0] LOW_BAT, Cleared by a write of ‘1’.
When the battery is removed and replaced or the if the battery voltage drops
below 1.2V under battery power, then the LOW_BAT PME status bit is set
on VTR POR. When the battery voltage drops below 2.4 volts under VTR
power (VCC=0) or under battery power only, the LOW_BAT PME status bit
is set on VCC POR. The corresponding enable bit must be set to generate
a PME. The low battery event is not a PME wakeup event.
Bit[0] will be set to ‘1’
on a VCC POR if the
battery voltage drops
below 2.4V under
VTR power (VCC=0)
or under battery
Bit[1] RESERVED.
Bit[2] GP60
Bit[3] GP61
Bit[4] SPEMSE_STS (Wake on specific mouse click)
Bit[5] SPEKEY_STS (Wake on specific key)
Bit[6] PB_STS
power only.
(SCH3222,
SCH3224, or
SCH3227 / SCH3226
with STRAPOPT=1)
Bit[7] Reserved
The PME Status register is not affected by VCC POR, SOFT RESET or PCI
RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Status
Register has no effect.
PME_EN1
08
PME Wake Enable Register 1
This register is used to enable individual PME wake sources onto the
Default = 0x00
on VTR POR
(R/W)
nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”), if
the source asserts a wake event so that the associated status bit is “1” and
the PME_EN bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive (“0”),
the PME Wake Status register will indicate the state of the wake source but
will not assert the nIO_PME signal.
Bit[0] HW_Monitor
Bit[1] RI2
Bit[2] RI1
Bit[3] KBD
Bit[4] MOUSE
Bit[5] Reserved
Bit[6] IRINT
Bit[7] Reserved
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
PME_EN3
09
PME Wake Status Register 3
This register is used to enable individual PME wake sources onto the
Default = 0x00
on VTR POR
(R/W)
nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”), if
the source asserts a wake event so that the associated status bit is “1” and
the PME_EN bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive (“0”),
the PME Wake Status register will indicate the state of the wake source but
will not assert the nIO_PME signal.
Bit[0] WDT
Bit[1] GP21
Bit[2] GP22
Bit[3] DEVINT_EN (Enable bit for group SMI signal for PME)
Bit[4] GP27
Bit[5] GP32
Bit[6] GP33
Bit[7] Reserved
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
2016-2017 Microchip Technology Inc.
DS00002121B-page 223
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
PME_EN5
0A
PME Wake Enable Register 5
This register is used to enable individual PME wake sources onto the
Default = 0x00
on VTR POR
(R/W)
nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”), if
the source asserts a wake event so that the associated status bit is “1” and
the PME_EN bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive (“0”),
the PME Wake Status register will indicate the state of the wake source but
will not assert the nIO_PME signal.
Bit[0] GP50
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
PME_EN6
0B
PME Enable Register 6
This register is used to enable individual PME sources onto the nIO_PME
Default = 0x00 on
VTR POR
(R/W)
signal.
When the PME Enable register bit for a PME source is active (“1”), if the
source asserts a PME event and the PME_EN bit is “1”, the source will
assert the nIO_PME signal.
(SCH3227 or
SCH3226, and
STRAPOPT=0)
When the PME Enable register bit for a PME source is inactive (“0”), the
PME Status register will indicate the state of the PME source but will not
assert the nIO_PME signal.
NOTE: Bit 7 of this
register needs to be
VBAT powered
Bit[0] LOW_BAT
Bit[1] Reserved
Bit[2] GP60
Bit[3] GP61
Bit[4] SPEMSE_EN (Wake on specific mouse click)
Bit[5] SPEKEY_EN (Wake on specific key)
Bit[6] PB_EN
Bit[7] PFR_STS Power Failure Recovery Enable
The PME Enable register 6 is not affected by VCC POR, SOFT RESET or
PCI RESET.
PME_EN6
0B
PME Enable Register 6
This register is used to enable individual PME sources onto the nIO_PME
Default = 0x00 on
VTR POR
(R/W)
signal.
When the PME Enable register bit for a PME source is active (“1”), if the
source asserts a PME event and the PME_EN bit is “1”, the source will
assert the nIO_PME signal.
(SCH3222,
SCH3224, or
SCH3227 / SCH3226
with STRAPOPT=1)
When the PME Enable register bit for a PME source is inactive (“0”), the
PME Status register will indicate the state of the PME source but will not
assert the nIO_PME signal.
Bit[0] LOW_BAT
NOTE: Bit 7 of this
register needs to be
VBAT powered
Bit[1] Reserved
Bit[2] GP60
Bit[3] GP61
Bit[4] SPEMSE_EN (Wake on specific mouse click)
Bit[5] SPEKEY_EN (Wake on specific key)
Bit[6] PB_EN
Bit[7] Reserved
The PME Enable register 6 is not affected by VCC POR, SOFT RESET or
PCI RESET.
DS00002121B-page 224
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
PME_STS7
0C
PME Wake Status Register 7
This register indicates the state of the individual PME wake sources,
Default = 0x00
on VTR POR
(R/WC)
independent of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
(SCH3227 or
SCH3226, and
STRAPOPT=0)
nIO_PME pin.
Bit[0] RI3
Bit[1] RI4
Bit[2] Reserved
Bit[3] Reserved
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
PME_STS7
0C
PME Wake Status Register 7
This register indicates the state of the individual PME wake sources,
Default = 0x00
on VTR POR
(R/WC)
independent of the individual source enables or the PME_EN bit.
If the wake source has asserted a wake event, the associated PME Wake
Status bit will be a “1”. If enabled, any set bit in this register asserts the
(SCH3222,
SCH3224, or
SCH3227 / SCH3226
with STRAPOPT=1)
nIO_PME pin.
Bit[0] RI3
Bit[1] RI4
Bit[2] RI5
Bit[3] RI6
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The PME Wake Status register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake
Status Register has no effect.
PME_EN7
10
PME Wake Enable Register 1
This register is used to enable individual PME wake sources onto the
Default = 0x00
on Vbat POR
(R/W)
nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”), if
the source asserts a wake event so that the associated status bit is “1” and
(SCH3227 or
SCH3226, and
STRAPOPT=0)
the PME_EN bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive (“0”),
the PME Wake Status register will indicate the state of the wake source but
will not assert the nIO_PME signal.
Bit[0] RI3
Bit[1] RI4
Bit[2] Reserved
Bit[3] Reserved
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
2016-2017 Microchip Technology Inc.
DS00002121B-page 225
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
PME_EN7
10
PME Wake Enable Register 1
This register is used to enable individual PME wake sources onto the
Default = 0x00
on Vbat POR
(R/W)
nIO_PME wake bus.
When the PME Wake Enable register bit for a wake source is active (“1”), if
the source asserts a wake event so that the associated status bit is “1” and
(SCH3222,
SCH3224, or
SCH3227 / SCH3226
with STRAPOPT=1)
the PME_EN bit is “1”, the source will assert the nIO_PME signal.
When the PME Wake Enable register bit for a wake source is inactive (“0”),
the PME Wake Status register will indicate the state of the wake source but
will not assert the nIO_PME signal.
Bit[0] RI3
Bit[1] RI4
Bit[2] RI5
Bit[3] RI6
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] Reserved
The PME Wake Enable register is not affected by Vcc POR, SOFT RESET
or PCI RESET.
SP12 Option
0x12
SP Options for SP1 and SP2
Default = 0x44
on VTR POR
(R/W)
Bit[0] Automatic Direction Control Select SP1
1=FC on
0=FC off
Bits[1] Signal select SP1
1=nRTS control
0=nDTR control
Bits[2] Polarity SP1
0= Drive low when enabled
1= Drive 1 when enabled
Bits[3] RESERVED
Bit[4] Automatic Direction Control Select SP2
1=FC on
0=FC off
Bits[5] Signal select SP2
1=nRTS control
0=nDTR control
Bits[6] Polarity SP2
0= Drive low when enabled
1= Drive 1 when enabled
Bits[7] RESERVED
Bits[7:0] RESERVED
SP34 Option
0x13
Default = 0x44
on VTR POR
(R/W)
(SCH3224)
DS00002121B-page 226
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
SP34 Option
0x13
Bit[0] Automatic Direction Control Select SP3
1=FC on
0=FC off
Default = 0x44
on VTR POR
(R/W)
Bits[1] Signal select SP3
1=nRTS control
0=nDTR control
(All except SCH3224)
Bits[2] Polarity SP3
0= Drive low when enabled
1= Drive 1 when enabled
Bits[3] RESERVED
Bit[4] Automatic Direction Control Select SP4
1=FC on
0=FC off
Bits[5] Signal select SP4
1=nRTS control
0=nDTR control
Bits[6] Polarity SP4
0= Drive low when enabled
1= Drive 1 when enabled
Bits[7] RESERVED
SMI_STS1
14
SMI Status Register 1
This register is used to read the status of the SMI inputs.
The following bits must be cleared at their source except as shown.
Default = 0x02, or
0x03 On VTR POR. R/WC.
Bits[0] are
Bit[0] LOW_BAT. Cleared by a write of ‘1’. When the battery is removed and
The default will be
0x03 if there is a
LOW_BAT event
under VBAT power
only, or 0x02 if this
event does not occur.
Bit 0 will be set to ‘1’
on a VCC POR if the
battery voltage drops
below 2.4V under
VTR power (VCC=0)
or under battery
Bits[1:4,7] are replaced or if the battery voltage drops below 1.2V (nominal) under battery
RO.
power only (VBAT POR), then the LOW_BAT SMI status bit is set on VTR
POR. When the battery voltage drops below 2.4 volts (nominal) under VTR
power (VCC=0) or under battery power only, the LOW_BAT SMI status bit is
set on VCC POR.
Bit[1] PINT. The parallel port interrupt defaults to ‘1’ when the parallel port
activate bit is cleared. When the parallel port is activated, PINT follows the
nACK input.
Bit[2] U2INT
Bit[3] U1INT
Bit[4] FINT
Bit[5] Reserved
Bit[6] Reserved
Bit[7] WDT
power only.
Bit 1 is set to ‘1’ on
VCC POR, VTR
POR, PCI Reset and
soft reset.
SMI_STS2
15
SMI Status Register 2
This register is used to read the status of the SMI inputs.
Default = 0x00
on VTR POR
(R/W)
Bit[0] MINT. Cleared at source.
Bit[1] KINT. Cleared at source.
Bits[0,1] are
RO
Bits[2] is
Read-Clear.
Bit[2] IRINT. This bit is set by a transition on the IR pin (IRRX). Cleared by
a read of this register.
Bit[3] Reserved
Bit[4] SPEMSE_STS (Wake on specific mouse click) - Cleared by writing a
‘1’
Bit[7:5] Reserved
2016-2017 Microchip Technology Inc.
DS00002121B-page 227
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
SMI_STS3
16
SMI Status Register 3
This register is used to read the status of the SMI inputs.
Default = 0x00
on VTR POR
(R/WC)
The following bits are cleared on a write of ‘1’.
Bit[0] Reserved
Bit[1] GP21
Bit[2] GP22
Bit[3] GP54
Bit[4] GP55
Bit[5] GP56
Bit[6] GP57
Bit[7] GP60
SMI_STS4
17
SMI Status Register 4
This register is used to read the status of the SMI inputs.
Default = 0x00
on VTR POR
(Note 24-22)
(R/WC)
The following bits are cleared on a write of ‘1’.
Bit[0] RESERVED
Bit[1] RESERVED
Bit[2] GP32
(SCH3224)
Bit[3] GP33
Bit[4] U5INT
Bit[5] GP42
Bit[6] U5INT
Bit[7] GP61
SMI_STS4
17
SMI Status Register 4
This register is used to read the status of the SMI inputs.
Default = 0x00
on VTR POR
(Note 24-22)
(R/WC)
The following bits are cleared on a write of ‘1’.
Bit[0] U3INT
Bit[1] U4INT
Bit[2] GP32
(All except SCH3224)
Bit[3] GP33
Bit[4] U5INT (RESERVED if SCH3227/SCH3226 and STRAPOPT=0)
Bit[5] GP42
Bit[6] U6INT (RESERVED if SCH3227/SCH3226 and STRAPOPT=0)
Bit[7] GP61
SMI_EN1
18
SMI Enable Register 1
This register is used to enable the different interrupt sources onto the group
Default = 0x00
On VTR POR
(R/W)
nIO_SMI output.
1=Enable
0=Disable
Bit[0] EN_LOW_BAT
Bit[1] EN_PINT
Bit[2] EN_U2INT
Bit[3] EN_U1INT
Bit[4] EN_FINT
Bit[5] Reserved
Bit[6] Reserved
Bit[7] EN_WDT
SMI_EN2
19
SMI Enable Register 2
This register is used to enable the different interrupt sources onto the group
nSMI output, and the group nSMI output onto the nIO_SMI GPI/O pin, the
serial IRQ stream or into the PME Logic.
Default = 0x00
on VTR POR
(R/W)
Unless otherwise noted,
1=Enable
0=Disable
Bit[0] EN_MINT
Bit[1] EN_KINT
Bit[2] EN_IRINT
Bit[3] Reserved
Bit[4] EN_SPESME
Bit[5] EN_SMI_PME (Enable group SMI into PME logic)
Bit[6] EN_SMI_S (Enable group SMI onto serial IRQ)
Bit[7] EN_SMI (Enable group SMI onto nIO_SMI pin)
DS00002121B-page 228
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
SMI_EN3
1A
SMI Enable Register 3
This register is used to enable the different interrupt sources onto the group
Default = 0x00
on VTR POR
(R/W)
nSMI output.
1=Enable
0=Disable
Bit[0] Reserved
Bit[1] GP21
Bit[2] GP22
Bit[3] GP54
Bit[4] GP55
Bit[5] GP56
Bit[6] GP57
Bit[7] GP60
SMI_EN4
1B
SMI Enable Register 4
This register is used to enable the different interrupt sources onto the group
Default = 0x00
on VTR POR
(R/W)
nSMI output.
1=Enable
0=Disable
(SCH3224)
Bit[0] RESERVED
Bit[1] RESERVED
Bit[2] GP32
Bit[3] GP33
Bit[4] U5INT
Bit[5] GP42
Bit[6] U5INT
Bit[7] GP61
SMI_EN4
1B
SMI Enable Register 4
This register is used to enable the different interrupt sources onto the group
Default = 0x00
on VTR POR
(R/W)
nSMI output.
1=Enable
0=Disable
(All except SCH3224)
Bit[0] U3INT
Bit[1] U4INT
Bit[2] GP32
Bit[3] GP33
Bit[4] U5INT (RESERVED if SCH3227/SCH3226 and STRAPOPT=0)
Bit[5] GP42
Bit[6] U6INT (RESERVED if SCH3227/SCH3226 and STRAPOPT=0)
Bit[7] GP61
MSC_STS
1C
Miscellaneous Status Register
Bits[5:0] can be cleared by writing a 1 to their position (writing a 0 has no
effect).
Default = 0x00
on VTR POR
(R/W)
Bit[0] Either Edge Triggered Interrupt Input 0 Status. This bit is set when an
edge occurs on the GP21 pin.
Bit[1] Either Edge Triggered Interrupt Input 1 Status. This bit is set when an
edge occurs on the GP22 pin.
Bit[2] Reserved
Bit[3] Reserved
Bit[4] Either Edge Triggered Interrupt Input 4 Status. This bit is set when an
edge occurs on the GP60 pin.
Bit[5] Either Edge Triggered Interrupt Input 5 Status. This bit is set when an
edge occurs on the GP61 pin.
Bit[7:6] Reserved. This bit always returns zero.
RESGEN
1Dh
Reset Generator
Bit[0] WDT2_EN: Enable Watchdog timer Generation / Select
0= WDT Enabled - Source for PWRGD_OUT (Default)
1= WDT Disabled - Not source for PWRGD_OUT
VTR POR
default = 00h
(R/W)
Bit[1] ThermTrip Source Select
0 = Thermtrip not source for PWRGD_OUT ((Default)
1 = Thermtrip source for PWRGD_OUT
Bit[2] WDT2_CTL: WDT input bit
Bit[7:3] Reserved
2016-2017 Microchip Technology Inc.
DS00002121B-page 229
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
Reserved
1E
Bit[7:0] Reserved, do not change.
Default = 0x03 on
VCC POR, PCI Reset
and VTR POR
(R/W)
Reserved
1F
Bit[7:0] Reserved, contents undefined.
(R)
UART1 FIFO Control 20
Shadow
(R)
UART FIFO Control Shadow 1
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
UART2 FIFO Control 21
Shadow
(R)
UART FIFO Control Shadow 2
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
UART3 FIFO Control 22
Bits[7:0] RESERVED
Shadow
(R)
(SCH3224)
UART3 FIFO Control 22
Shadow
UART FIFO Control Shadow 3
Bit[0] FIFO Enable
(R)
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
(All except SCH3224)
GP10
23
General Purpose I/O bit 1.0
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Default = 0x01
on VTR POR
(R/W)
Bit[7] Output Type Select
1=Open Drain
(SCH3224)
0=Push Pull
GP10
23
General Purpose I/O bit 1.0
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= RXD3
Default = 0x01
on VTR POR
(R/W)
(All except SCH3224)
0=GP10
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP11
24
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Default = 0x01
on VTR POR
(R/W)
(SCH3224)
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
DS00002121B-page 230
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
GP11
24
General Purpose I/O bit 1.1
Default = 0x01
on VTR POR
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=TXD3
(R/W)
(All except SCH3224)
0=GP11
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP12
25
General Purpose I/O bit 1.2
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Default = 0x01
on VTR POR
(R/W)
Bit[7] Output Type Select
1=Open Drain
(SCH3224)
0=Push Pull
GP12
25
General Purpose I/O bit 1.2
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nDCD3
Default = 0x01
on VTR POR
(R/W)
(All except SCH3224)
0=GP12
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP13
26
General Purpose I/O bit 1.3
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Default = 0x01
on VTR POR
(R/W)
Bit[7] Output Type Select
1=Open Drain
(SCH3224)
0=Push Pull
GP13
26
General Purpose I/O bit 1.3
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nRI3
Default = 0x01
on VTR POR
(R/W)
(All except SCH3224)
0=GP13
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP14
27
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Default = 0x01
on VTR POR
(R/W)
Bit[7] Output Type Select
1=Open Drain
(SCH3224)
0=Push Pull
GP14
27
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nDSR3
Default = 0x01
on VTR POR
(R/W)
(All except SCH3224)
0=GP14
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
2016-2017 Microchip Technology Inc.
DS00002121B-page 231
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
UART4 FIFO Control 28
Bits[7:0] RESERVED
Shadow
(R)
(SCH3224)
UART4 FIFO Control 28
Shadow
UART FIFO Control Shadow 4
Bit[0] FIFO Enable
(R)
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
(All except SCH3224)
GP15
29
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Default = 0x01
on VTR POR
(R/W)
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
(SCH3224)
GP15
29
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nDTR3
Default = 0x01
on VTR POR
(R/W)
(All except SCH3224)
0=GP15
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP16
2A
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Default = 0x01
on VTR POR
(R/W)
Bit[7] Output Type Select
1=Open Drain
(SCH3224)
0=Push Pull
GP16
2A
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nCTS3
Default = 0x01
on VTR POR
(R/W)
(All except SCH3224)
0=GP16
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP17
2B
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Default = 0x01
on VTR POR
(R/W)
Bit[7] Output Type Select
1=Open Drain
(SCH3224)
0=Push Pull
GP17
2B
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nRTS3
Default = 0x01
on VTR POR
(R/W)
(All except SCH3224)
0=GP17
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
DS00002121B-page 232
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
GP21
Default =0x8C
on VTR POR
2C
General Purpose I/O bit 2.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[3:2] Alternate Function Select
11= KDAT (Default)
(R/W)
10=Either Edge Triggered Interrupt Input 0 (Note 24-20)
01=Reserved
00=Basic GPIO function
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull (Default)
APPLICATION NOTE: When Bits[3:2] are programmed to ‘11’ to select the
KDAT function, bit[0] should always be programmed
to ‘0’. The KDAT function will not operate properly
when bit[0] is set.
GP22
2D
General Purpose I/O bit 2.2
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[3:2] Alternate Function Select
11= KCLK (Default)
Default =0x8C
on VTR POR
(R/W)
10=Either Edge Triggered Interrupt Input 1 (Note 24-20)
01= Reserved
00=Basic GPIO function
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain (Default)
0=Push Pull
APPLICATION NOTE: When Bits[3:2] are programmed to ‘11’ to select the
KCLK function, bit[0] should always be programmed
to ‘0’. The KCLK function will not operate properly
when bit[0] is set.
UART5 FIFO Control 2E
Shadow
Bits[7:0] RESERVED
(R)
(SCH3227 or
SCH3226, and
STRAPOPT=0)
UART5 FIFO Control 2E
Shadow
UART FIFO Control Shadow 5
Bit[0] FIFO Enable
(R)
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
(SCH3222,
SCH3224, or
SCH3227 / SCH3226
with STRAPOPT=1)
UART6 FIFO Control 2F
Shadow
Bits[7:0] RESERVED
(R)
(SCH3227 or
SCH3226, and
STRAPOPT=0)
UART6 FIFO Control 2F
Shadow
Bit[0] FIFO Enable
Bit[1] RCVR FIFO Reset
Bit[2] XMIT FIFO Reset
Bit[3] DMA Mode Select
Bit[5:4] Reserved
(R)
(SCH3222,
SCH3224, or
SCH3227 / SCH3226
with STRAPOPT=1)
Bit[6] RCVR Trigger (LSB)
Bit[7] RCVR Trigger (MSB)
2016-2017 Microchip Technology Inc.
DS00002121B-page 233
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
SP5 Option
30
Bits[7:0] RESERVED
Default = 0x04
on VTR POR
(R/W)
(SCH3227 or
SCH3226, and
STRAPOPT=0)
SP5 Option
30
Bit[0] nSCOUT5 Select:
1= nRTS5
Default = 0x04
on VTR POR
(R/W)
0= nDTR5
Bit[2:1] nSCIN Select:
11= nDCD5
(SCH3222,
SCH3224, or
SCH3227 / SCH3226
with STRAPOPT=1)
10= nRI5
01= nCTS5
00= nDSR5
Bit[3] Automatic Direction Control Select
1=FC on
0=FC off
Bits[4] Signal select
1=nRTS control
0=nDTR control
Bits[5] Polarity
0= Drive low when enabled
1= Drive 1 when enabled
Bit[7:6] Reserved
SP6 Option
31
Bits[7:0] RESERVED
Default = 0x04
on VTR POR
(R/W)
(SCH3227 or
SCH3226, and
STRAPOPT=0)
SP6 Option
31
Bit[0] nSCOUT6 Select:
1= nRTS6
Default = 0x04
on VTR POR
(R/W)
0= nDTR6
Bit[2:1] nSCIN Select:
11= nDCD6
(SCH3222,
SCH3224, or
SCH3227 / SCH3226
with STRAPOPT=1)
10= nRI6
01= nCTS6
00= nDSR6
Bit[3] Automatic Direction Control Select
1=FC on
0=FC off
Bits[4] Signal select
1=nRTS control
0=nDTR control
Bits[5] Polarity
0= Drive low when enabled
1= Drive 1 when enabled
Bit[7:6] Reserved
GP27
32
General Purpose I/O bit 2.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[3:2] Alternate Function Select
11=Reserved
Default = 0x01
on VTR POR
(R/W)
10=8042 P17 function (Note 24-19)
01=nIO_SMI (Note 24-21)
00=GPIO
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
DS00002121B-page 234
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
GP30
33
General Purpose I/O bit 3.2
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nFPRST (Default)
Default = 0x05
on VTR POR
(R/W)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain (Default)
0=Push Pull
GP31
34
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Default = 0x01
on VTR POR
(R/W)
Bit[7] Output Type Select read only returns 1= Open Drain
(SCH3224)
Note:
The pin can only be an Open Drain output.
GP31
34
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nRI4
Default = 0x01
on VTR POR
(R/W)
(All except SCH3224)
0=GP31
Bits[6:3] Reserved
Bit[7] Output Type Select read only returns 1= Open Drain
Note:
The pin can only be an Open Drain output.
GP32
35
General Purpose I/O bit 3.2
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=MDAT (Default)
Default = 0x84
on VTR POR
(R/W)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain (Default)
0=Push Pull
APPLICATION NOTE: When Bit[2] are programmed to ‘1’ to select the
MDAT function, bit[0] should always be programmed
to ‘0’. The MDAT function will not operate properly
when bit[0] is set.
GP33
36
General Purpose I/O bit 3.3
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=MCLK (Default)
Default = 0x84
on VTR POR
(R/W)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain (Default)
0=Push Pull
APPLICATION NOTE: When Bit[2] are programmed to ‘1’ to select the
MCLK function, bit[0] should always be programmed
to ‘0’. The MCLK function will not operate properly
when bit[0] is set.
GP34
37
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Default = 0x01
on VTR POR
(R/W)
Bit[7] Output Type Select read only returns 1= Open Drain
(SCH3224)
Note:
The pin can only be an Open Drain output.
2016-2017 Microchip Technology Inc.
DS00002121B-page 235
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
GP34
37
General Purpose I/O bit 1.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nDTR4
Default = 0x01
on VTR POR
(R/W)
(All except SCH3224)
0=GP34
Bits[6:3] Reserved
Bit[7] Output Type Select read only returns 1= Open Drain
Note:
The pin can only be an Open Drain output.
GP36
39
General Purpose I/O bit 3.6
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= nKBDRST
Default = 0x01
on VTR POR
(R/W)
0=Basic GPIO function
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP37
3A
General Purpose I/O bit 3.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=A20M
Default = 0x01
on VTR POR
(R/W)
0=Basic GPIO function
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP40
3B
General Purpose I/O bit 4.0
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1= Reserved
Default =0x01
on VTR POR
(R/W)
0= Basic GPIO function
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
CLOCK Output
Control Register
3C
Bit[0] Enable
1= Output Enabled
0= Disable Clock output
Bit[3:1] Frequency Select
000= 0.25 Hz
(R/W)
VTR POR = 0x00
001= 0.50 Hz
010= 1.00 Hz
011= 2.00 Hz
100= 4.00 Hz
101= 8.00 Hz
110= 16 hz
111 = reserved
Bit[7:4] Reserved
DS00002121B-page 236
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
GP42
3D
General Purpose I/O bit 4.2
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nIO_PME
Default =0x01
on VTR POR
(R/W)
Note:
Configuring this pin function as output with non-inverted polarity
will give an active low output signal. The output type can be either
open drain or push-pull.
0=Basic GPIO function
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP50
3F
General Purpose I/O bit 5.0
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nRI2 (Note 24-18)
Default = 0x01
on VTR POR
(R/W)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP51
40
General Purpose I/O bit 5.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nDCD2
Default = 0x01
on VTR POR
(R/W)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP52
41
General Purpose I/O bit 5.2
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=RXD2
Default = 0x01
on VTR POR
(R/W)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP53
42
General Purpose I/O bit 5.3
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=TXD2
Default = 0x01
on VTR POR
(R/W)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
2016-2017 Microchip Technology Inc.
DS00002121B-page 237
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
GP54
43
General Purpose I/O bit 5.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nDSR2
Default = 0x01
on VTR POR
(R/W)
0=GPIO
Bit[3] RESERVED
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP55
44
General Purpose I/O bit 5.5
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nRTS2
Default = 0x01
on VTR POR
(R/W)
0=GPIO
Bit[3] RESERVED
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP56
45
General Purpose I/O bit 5.6
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nCTS2
Default = 0x01
on VTR POR
(R/W)
0=GPIO
Bit[3] RESERVED
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP57
46
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nDTR2
Default = 0x01
on VTR POR
(R/W)
0=GPIO
Bit[3] RESERVED
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP60
47
General Purpose I/O bit 6.0
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[3:2] Alternate Function Select
11=WDT
Default = 0x01
on VTR POR
(R/W)
10=Either Edge Triggered Interrupt Input 4 (Note 24-20)
01=LED1
00=GPIO
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
DS00002121B-page 238
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
GP61
48
(R/W)
General Purpose I/O bit 6.1
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[3:2] Alternate Function Select
11=CLKO - Programmable clock output as described in
10=Either Edge Triggered Interrupt Input 5 (Note 24-20)
01=LED2
Default = 0x01
on VTR POR
00=GPIO
Bits[6:4] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
PWR_REC
Power Recovery
Register
49
A/C Power Control/Recovery Register
R/W when
bit[7] =0
Bit[0] Power Button Enable
0=disabled
1=enabled (default)
Default = 0xxxxx11b (default),
on VTR POR
except for
bit[4]
Bit[1] Keyboard Power Button Enable
0=disabled
1=enabled (default)
Default =x00000xxb
on a Vbat POR
Bit[4] is a
Read-Only
Default = 0xxxxxxxb bit.
on a VCC POR and
PCI Reset
Bit[2] Power Failure Recovery Enable
0=disabled (default)
1=enabled
Read-Only
when bit[7]=1
Bit[3] PS_ON# sampling enable
Note: x indicates that
the bit is not affected
by this reset
0=Sampling is disabled (Mode 1)
1=Sampling is enabled (Mode 2)
When sampling is enabled the PS_ON# pin is sampled every 0.5 seconds
and stored in an 8-bit shift register for up to a maximum of 4 seconds.
condition.
(SCH3227 or
SCH3226, and
STRAPOPT=0)
Bit[4] Previous State Bit (This read-only bit is powered by Vbat)
(NOTE: THIS BIT IS NOT RESET ON A VTR POR)
This bit contains the state of the PS_ON# pin when VTR power is removed
from the device.
0=off (PS_ON# signal was high)
1=on (PS_ON# signal was low)
Bit[6:5] APF (After Power Failure) (These bits are powered by Vbat)
(NOTE: THIS BIT IS NOT RESET ON A VTR POR)
When VTR transitions from the OFF state to the ON state, the power
recovery logic will look at the APF bits to determine if the power supply
should be off or on. If the logic determines that the Power Supply should be
place in the ON state it will generate a pulse on the PB_OUT# pin. The auto
recovery logic does not directly control the PS_ON# pin. The PS_ON# pin
is controlled by the SLP_Sx# pin.
00=Power Supply Off
01=Power Supply On
10=Power Supply set to Previous State
11=Power Supply Off
Bit[7] Register Recovery R/W Control
This bit is used to control write access to the Power Recovery Register at
offset 49h.
0=Read/Write
1=Read-OnlyA/C Power Control/Recovery Register
2016-2017 Microchip Technology Inc.
DS00002121B-page 239
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
PWR_REC
Power Recovery
Register
49
Bits[7:0] RESERVED
Do not write to this register.
Default = 0xxxxx11b
on VTR POR
Default =x00000xxb
on a Vbat POR
Default = 0xxxxxxxb
on a VCC POR and
PCI Reset
Note: x indicates that
the bit is not affected
by this reset
condition.
(SCH3222,
SCH3224, or
SCH3227 / SCH3226
with STRAPOPT=1)
PS_ON Register
4A
PS_ON Shift Register
This 8-bit register is used to read the PS_ON sample values loaded in the
shift register in A/C Power Recovery Control - Mode 2.
default = 0x00 on a
Vbat POR
(R)
Bit[0] = PS_ON# sampled 0 - 0.5sec before power failure
Bit[1] = PS_ON# sampled 0.5 - 1.0sec before power failure
Bit[2] = PS_ON# sampled 1.0 - 1.5sec before power failure
Bit[3] = PS_ON# sampled 1.5 - 2.0sec before power failure
Bit[4] = PS_ON# sampled 2.0 - 2.5sec before power failure
Bit[5] = PS_ON# sampled 2.5 - 3.0sec before power failure
Bit[6] = PS_ON# sampled 3.0 - 3.5sec before power failure
Bit[7] = PS_ON# sampled 3.5 - 4.0sec before power failure
default = value
latched on Power
Failure on a VTR
POR
(SCH3227 or
SCH3226, and
STRAPOPT=0)
Bit definition
0=off (PS_ON# signal was high)
1=on (PS_ON# signal was low)
Note:
This register is powered by Vbat
PS_ON Register
4A
Bits[7:0] RESERVED
Note:
This register is powered by Vbat
default = 0x00 on a
Vbat POR
(R)
default = value
latched on Power
Failure on a VTR
POR
(SCH3222,
SCH3224, or
SCH3227 / SCH3226
with STRAPOPT=1)
GP1
4B
General Purpose I/O Data Register 1
Bit[0] GP10
Default = 0x00
on VTR POR
(R/W)
Bit[1] GP11
Bit[2] GP12
Bit[3] GP13
Bit[4] GP14
Bit[5] GP15
Bit[6] GP16
Bit[7] GP17
DS00002121B-page 240
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
GP2
Default = 0x00
on VTR POR
4C
General Purpose I/O Data Register 2
Bit[0] Reserved
Bit[1] GP21
(R/W)
Bit[2] GP22
Bit[3] Reserved
Bit[4] Reserved
Bit[5] Reserved
Bit[6] Reserved
Bit[7] GP27
GP3
4D
General Purpose I\O Data Register 3
Bit[0] GP30
Default = 0x00
on VTR POR
(R/W)
Bit[1] GP31
Bit[2] GP32
Bit[3] GP33
Bit[4] GP34
Bit[5] Reserved
Bit[6] GP36
Bit[7] GP37
GP4
4E
General Purpose I/O Data Register 4
Bit[0] GP40
Default = 0xF0
on VTR POR
(R/W)
Bit[1] Reserved
Bit[2] GP42
Bit[3] Reserved
Bit[4] GP44
Bit[5] GP45
Bit[6] GP46
Bit[7] GP47
GP5
4F
General Purpose I/O Data Register 5
Bit[0] GP50
Default = 0x00
on VTR POR
(R/W)
Bit[1] GP51
Bit[2] GP52
Bit[3] GP53
Bit[4] GP54
Bit[5] GP55
Bit[6] GP56
Bit[7] GP57
GP6
50
General Purpose I/O Data Register 6
Bit[0] GP60
Default = 0x00
on VTR POR
(R/W)
Bit[1] GP61
Bit[2] GP62
Bit[3] GP63
Bit[4] GP64
Bit[5] GP65
Bit[6] GP66
Bit[7] GP67
N/A
51
Bits[7:0] Reserved – reads return 0
(R)
2016-2017 Microchip Technology Inc.
DS00002121B-page 241
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
PS_ON# Previous
State Select
53
Bits[7:4] Reserved – reads return 0
(R/W)
Bit[3] MCHP Reserved, should be programmed to 0 for proper operation
Default = 0x00
on Vbat POR
Bits[2:0] PS_ON# Previous State Select
The TTL level of the PS_ON# pin is sampled every 0.5 seconds and placed
into an 8-bit shift register while VTR and VCC are on. The PS_ON# Previous
State Select bits determine which bit is used as the previous state bit
following a power failure (VTR ~2.2V).
(SCH3227 or
SCH3226, and
STRAPOPT=0)
000 = PS_ON# sampled 0 - 0.5sec before power failure
001 = PS_ON# sampled 0.5 - 1.0sec before power failure
010 = PS_ON# sampled 1.0 - 1.5sec before power failure
011 = PS_ON# sampled 1.5 - 2.0sec before power failure
100 = PS_ON# sampled 2.0 - 2.5sec before power failure
101 = PS_ON# sampled 2.5 - 3.0sec before power failure
110 = PS_ON# sampled 3.0 - 3.5sec before power failure
111 = PS_ON# sampled 3.5 - 4.0sec before power failure
PS_ON# Previous
State Select
53
Bits[7:0] RESERVED
(R/W)
Default = 0x00
on Vbat POR
(SCH3222,
SCH3224, or
SCH3227 / SCH3226
with STRAPOPT=1)
GP62
54
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Default = 0x01
on VTR POR
(R/W)
Bit[7] Output Type Select
1=Open Drain
(SCH3224)
0=Push Pull
GP62
54
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nCTS4
Default = 0x01
on VTR POR
(R/W)
(All except SCH3224)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP63
55
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Default = 0x01
on VTR POR
(R/W)
Bit[7] Output Type Select
1=Open Drain
(SCH3224)
0=Push Pull
GP63
55
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nDCD4
Default = 0x01
on VTR POR
(R/W)
(All except SCH3224)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
DS00002121B-page 242
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
GP64
56
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Default = 0x01
on VTR POR
(R/W)
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
(SCH3224)
GP64
56
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=RXD4
Default = 0x01
on VTR POR
(R/W)
(All except SCH3224)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP65
57
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Default = 0x01
on VTR POR
(R/W)
Bit[7] Output Type Select
1=Open Drain
(SCH3224)
0=Push Pull
GP65
57
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=TXD4
Default = 0x01
on VTR POR
(R/W)
(All except SCH3224)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP66
58
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Default = 0x01
on VTR POR
(R/W)
Bit[7] Output Type Select
1=Open Drain
(SCH3224)
0=Push Pull
GP66
58
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nDSR4
Default = 0x01
on VTR POR
(R/W)
(All except SCH3224)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP67
59
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Default = 0x01
on VTR POR
(R/W)
Bit[7] Output Type Select
1=Open Drain
(SCH3224)
0=Push Pull
2016-2017 Microchip Technology Inc.
DS00002121B-page 243
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
GP67
59
General Purpose I/O bit 5.7
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nRTS4
Default = 0x01
on VTR POR
(R/W)
(All except SCH3224)
0=GPIO
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
TEST
5A
Bits[0:1,5] MCHP Reserved bit. Must be written as a ‘0’.
Bits[2:4,6:7] Reserved Read only.
Default = 0x00
on VBAT POR
(R)
DBLCLICK
5B
Double Click for Specific Wake on Mouse Select Register
The DBLCLICK contains a numeric value that determines the time interval
Default = 0x0C
on VBAT POR
Bits [5:0] are used to check for a double mouse click. DBLCLICK is the time interval
R/W
when
between mouse clicks. For example, if DBLCLICK is set to 0.5 seconds, you
have one half second to click twice for a double-click.
Mouse_Specif
ic_ Wake
register- Bit
[7] is ‘0’
Bit[0:5] This field contains a six bit weighted sum value from 0 to 0x3Fh
which provides a double click interval between 0.0859375 and 5.5 seconds.
Each incremental digit has a weight of 0.0859375 seconds.
Bits [5:0] are Bit[6] Reserved - returns zero when read
Read Only
when
Bit[7] Spinup delay
Mouse_Specif 1= zero delay for spinup following VTR POR
ic_ Wake
register- Bit
[7] is ‘1’
0 = spinup delay by 2 seconds (default)
Mouse_Specific_
Wake
5C
Specific Wake on Mouse Click Control Register
Bit[0:1] MCHP Reserved bit. Must be written as a ‘0’.
R/W
Default = 00h on
VBAT POR
when Bit [7] is Bits[4:2] SPESME SELECT. These bits select which mouse event is/are
‘0’
routed to trigger a PME wake event.
000 = Any button click or any movement (left/right/middle)
001 = One click of left button.
Default = 0xxxxxxxb Read Only
on VTR POR, VCC
when Bit [7] is 010 = One click of right button.
POR, and PCI Reset ‘1’
011 = Any one click of left/right/middle button.
100 = Reserved
101 = Two times click of left button.
110 = Two times click of right button.
111 = Reserved
Note: The ‘x’
indicates bit is not
affected by reset
Bit[5] Reserved. Read only zero.
Bit[6] KB_MSE_SWAP. This bit swaps the Keyboard and Mouse Port
interfaces.
0 = The Keyboard and Mouse Ports are not swapped.
1 = The Keyboard and Mouse Ports are swapped.
Bit [7] Mouse_Specific_ Wake Lock (Note) (This bit is Reset on a VBAT
POR, VTR POR, VCC POR, and PCI Reset)
0 = Mouse_Specific_ Wake, and DBLCLICK Registers are Read/Write.
1 = Mouse_Specific_ Wake, and DBLCLICK Registers are Read Only.
LED1
5D
LED1
Bit[1:0] LED1 Control
Default = 0x00
on VTR POR
(R/W)
00=off
01=blink at 1Hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off)
10=Blink at ½ HZ rate with a 25% duty cycle (0.5 sec on, 1.5 sec off)
11=on
Bits[7:2] Reserved
DS00002121B-page 244
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
LED2
5E
(R/W)
LED2
Bit[1:0] LED2 Control
00=off
Default = 0x00
on VTR POR
01=blink at 1Hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off)
10=Blink at ½ HZ rate with a 25% duty cycle (0.5 sec on, 1.5 sec off)
11=on
Bits[7:2] Reserved
Keyboard Scan Code 5F
– Make Byte 1 (MSB)
Keyboard Scan Code
This register is used to decode the first byte received from keyboards that
generate multi-byte make codes and for single byte make codes.
(R/W)
Default = 0xE0
on Vbat POR
Bit[0] LSB of Scan Code
. . .
. . .
. . .
Bit[7] MSB of Scan Code
Note:
• The keyboard scan code registers default to the ACPI scan 2 Power
make/break codes.
(i.e., make=E0_37, break=E0_F0_37).
• Programming this register to 0x00 indicates that this register a don’t
care. Any valid scan code that is received will be a match.
Keyboard Scan Code 60
– Make Byte 2 (LSB)
Keyboard Scan Code
This register is used only for multi-byte make codes. It is used to decode
the second byte received.
(R/W)
Default = 0x37
on Vbat POR
Bit[0] LSB of Scan Code
. . .
. . .
. . .
Bit[7] MSB of Scan Code
Note:
• The keyboard scan code registers default to the ACPI scan 2 Power
make/break codes.
(i.e., make=E0_37, break=E0_F0_37).
• Programming this register to 0x00 indicates that this register a don’t
care. Any valid scan code that is received will be a match.
Keyboard Scan Code 61
– Break Byte 1 (MSB)
Keyboard Scan Code
This register is used to decode the first byte received from keyboards that
generate multi-byte make codes and for single byte break codes.
(R/W)
Default = 0xE0
on Vbat POR
Bit[0] LSB of Scan Code
. . .
. . .
. . .
Bit[7] MSB of Scan Code
Note:
• The keyboard scan code registers default to the ACPI scan 2 Power
make/break codes.
(i.e., make=E0_37, break=E0_F0_37).
• Programming this register to 0x00 indicates that this register a don’t
care. Any valid scan code that is received will be a match.
2016-2017 Microchip Technology Inc.
DS00002121B-page 245
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
Keyboard Scan Code 62
– Break Byte 2
Keyboard Scan Code
This register is used to decode the second byte received in multi-byte break
codes.
(R/W)
Default = 0xF0
on Vbat POR
Bit[0] LSB of Scan Code
. . .
. . .
. . .
Bit[7] MSB of Scan Code
Note:
• The keyboard scan code registers default to the ACPI scan 2 Power
make/break codes.
(i.e., make=E0_37, break=E0_F0_37).
• Programming this register to 0x00 indicates that this register a don’t
care. Any valid scan code that is received will be a match.
Keyboard Scan Code 63
– Break Byte 3 (LSB)
Keyboard Scan Code
This register is used to decode the third byte received in scan 2 multi-byte
break codes.
(R/W)
Default = 0x37
on Vbat POR
Bit[0] LSB of Scan Code
. . .
. . .
. . .
Bit[7] MSB of Scan Code
Note:
• The keyboard scan code registers default to the ACPI scan 2 Power
make/break codes.
(i.e., make=E0_37, break=E0_F0_37).
• Programming this register to 0x00 indicates that this register a don’t
care. Any valid scan code that is received will be a match.
Keyboard
64
Bit[0] MCHP Reserved bit. Must be written as a ‘0’.
Bit[1] MCHP Reserved bit. Must be written as a ‘0’.
PWRBTN/SPEKEY
R/W
when Bit [7] is
‘0’
Default = 6Ch on
Vbat POR
Bits[3:2] SPEKEY ScanCode. This bit is used to configure the hardware to
decode a particular type of scan code.
00 = Single Byte, Scan Code Set 1 (Ex. make=37h and break=B7h)
Default = 0xxxxxxxb Read Only
on VTR POR, VCC
when Bit [7] is 01 =Multi-Byte, Scan Code Set 1 (Ex. make = E0h, 37h and break = E0h,
POR, and PCI Reset ‘1’
B7h)
10 = Single Byte, Scan Code Set 2 (Ex. make=37h and break=F0h 37h)
11 = Multi-Byte, Scan Code Set 2 (Ex. make = E0h, 37h and break = E0h
F0h 37h) (Default)
Note: The ‘x’
indicates bit is not
affected by reset
Bits[5:4] Keyboard Power Button Release
These bits are used to determine the pulse width of the Power Button event
from the keyboard (KB_PB_STS). The wake on specific key can be
configured to generate a PME event and/or power button event. If it is used
to generate a power button event, the following bits will determine when the
KB_PB_STS event is de-asserted.
00=De-assert KB_PB_STS 0.5sec after it is asserted (default)
01=De-assert KB_PB_STS after any valid scan code NOT EQUAL to the
programmed make code.
10=De-assert KB_PB_STS when scan code received is equal to
programmed break code
11=Reserved
Bit[6] MCHP Reserved bit. Must be written as a ‘1’.
DS00002121B-page 246
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
Keyboard
PWRBTN/SPEKEY
(continued)
Bit [7] Keyboard PWRBTN/SPEKEY Lock (Note) (This bit is Reset on a Vbat
POR, VTR POR, VCC POR, and PCI Reset)
0 = Keyboard PWRBTN/SPEKEY and Keyboard Scan Code Registers are
Read/Write
1 = Keyboard PWRBTN/SPEKEY and Keyboard Scan Code Registers are
Read Only
Note:
The following registers become Read-Only when Bit [7] is ‘1’:
• Keyboard Scan Code – Make Byte 1 at offset 5Fh
• Keyboard Scan Code – Make Byte 2 at offset 60h
• Keyboard Scan Code – Break Byte 1 at offset 61h
• Keyboard Scan Code – Break Byte 2 at offset 62h
• Keyboard Scan Code – Break Byte 3 at offset 63h
• Keyboard PWRBTN/SPEKEY at offset 64h
WDT_TIME_OUT
65
Watch-dog Timeout
Bit[0] Reserved
Default = 0x00
on VCC POR, VTR
POR, and PCI Reset
(R/W)
Bit[1] Reserved
Bits[6:2] Reserved, = 00000
Bit[7] WDT Time-out Value Units Select
= 0 Minutes (default)
= 1 Seconds
WDT_VAL
66
Watch-dog Timer Time-out Value
Binary coded, units = minutes (default) or seconds, selectable via Bit[7] of
WDT_TIME_OUT register (0x52).
0x00 Time out disabled
Default = 0x00
on VCC POR, VTR
POR, and PCI Reset
(R/W)
0x01 Time-out = 1 minute (second)
.........
0xFF Time-out = 255 minutes (seconds)
WDT_CFG
67
Watch-dog timer Configuration
Bit[0] Reserved
Bit[1] Keyboard Enable
=1 WDT is reset upon a Keyboard interrupt.
=0 WDT is not affected by Keyboard interrupts.
Bit[2] Mouse Enable
Default = 0x00
on VCC POR, VTR
POR, and PCI Reset
(R/W)
=1 WDT is reset upon a Mouse interrupt.
=0 WDT is not affected by Mouse interrupts.
Bit[3] Reserved
Bits[7:4] WDT Interrupt Mapping
1111 = IRQ15
.........
0011 = IRQ3
0010 = IRQ2 (Note)
0001 = IRQ1
0000 = Disable
Note:
IRQ2 is used for generating SMI events via the serial IRQ’s
stream. The WDT should not be configured for IRQ2 if the IRQ2
slot is enabled for generating an SMI event.
2016-2017 Microchip Technology Inc.
DS00002121B-page 247
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
WDT_CTRL
68
Watch-dog timer Control
Bit[0] Watch-dog Status Bit, R/W
Default = 0x00
on VCC POR and
VTR POR
(R/W)
=1 WD timeout occurred
=0 WD timer counting
Bit[2] is
Write-Only
Bit[1] Reserved
Bit[2] Force Timeout, W
Default = 0000000xb
on PCI Reset
Note: Bit[0] is not
cleared by PCI Reset
=1 Forces WD timeout event; this bit is self-clearing
Bit[3] P20 Force Timeout Enable, R/W
= 1 Allows rising edge of P20, from the Keyboard Controller, to force the WD
timeout event. A WD timeout event may still be forced by setting the Force
Timeout Bit, bit 2.
Note:
• If the P20 signal is high when the enable bit is set a WD timeout event
will be generated.
= 0 P20 activity does not generate the WD timeout event.
• The P20 signal will remain high for a minimum of 1us and can remain
high indefinitely. Therefore, when P20 forced timeouts are enabled, a
self-clearing edge-detect circuit is used to generate a signal which is
OR’ed with the signal generated by the Force Timeout Bit.
Bit[7:4] Reserved. Set to 0
TEST
6D
Test Register.
Test Registers are reserved for MCHP. Users should not write to this register,
may produce undesired results.
Default=0x00 on Vbat (R/W)
POR
GP44
6Eh
General Purpose I/O bit 4.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=GPIO
Default = 0x80
on VTR POR
(R/W)
(SCH3227 or
SCH3226, and
STRAPOPT=0)
0=nIDE_RSTDRV (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP44
6Eh
General Purpose I/O bit 4.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=TXD6
Default = 0x01
on VTR POR
(R/W)
(SCH3222,
SCH3224, or
SCH3227 / SCH3226
with STRAPOPT=1)
0=GPIO (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP45
6Fh
General Purpose I/O bit 4.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=GPIO
Default = 0x00
on VTR POR
(R/W)
(SCH3227 or
SCH3226, and
STRAPOPT=0)
0=nPCI_RST1 (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
DS00002121B-page 248
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
GP45
6Fh
General Purpose I/O bit 4.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=RXD6
Default = 0x01
on VTR POR
(R/W)
(SCH3222,
SCH3224, or
SCH3227 / SCH3226
with STRAPOPT=1)
0=GPIO (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
HW_Reg INDEX
70
The register is used to access the registers located in the H/W Monitoring
Register block. The value in this register is the register INDEX (address),
which determines the register currently accessible.
Default=0x00
on VTR POR
(R/W)
(All except SCH3222)
HW_Reg DATA
71
This register is used to Read/Write the data in the hardware monitoring
register that is currently INDEX’d. (See the HW_Reg INDEX register at offset
60h.)
Default=0x00
on VTR POR
(R/W)
(All except SCH3222)
GP46
72h
General Purpose I/O bit 4.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=GPIO
Default = 0x00
on VTR POR
(R/W)
(SCH3227 or
SCH3226, and
STRAPOPT=0)
0=nPCI_RST2 (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP46
72h
General Purpose I/O bit 4.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nSCIN6
Default = 0x01
on VTR POR
(R/W)
(SCH3222,
SCH3224, or
SCH3227 / SCH3226
with STRAPOPT=1)
0=GPIO (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
GP47
73h
General Purpose I/O bit 4.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=GPIO
Default = 0x00
on VTR POR
(R/W)
(SCH3227 or
SCH3226, and
STRAPOPT=0)
0=nPCI_RST3 (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
2016-2017 Microchip Technology Inc.
DS00002121B-page 249
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 24-3: DETAILED RUNTIME REGISTER DESCRIPTION (CONTINUED)
REG Offset
Name
Description
(HEX)
GP47
73h
General Purpose I/O bit 4.4
Bit[0] In/Out : =1 Input, =0 Output
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nSCOUT6
Default = 0x01
on VTR POR
(R/W)
(SCH3222,
SCH3224, or
SCH3227 / SCH3226
with STRAPOPT=1)
0=GPIO (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
N/A
74-7F
(R)
Bits[7:0] Reserved – reads return 0
Note:
When selecting an alternate function for a GPIO pin, all bits in the GPIO register must be properly pro-
grammed, including in/out, polarity and output type.
Note 24-18 If this pin is used for Ring Indicator wakeup, either the nRI2 event can be enabled via bit 1 in the
PME_EN1 register or the GP50 PME event can be enabled via bit 0 in the PME_EN5 register.
Note 24-19 In order to use the P17 functions, the corresponding GPIO must be programmed for output, non-
invert, and push-pull output type.
Note 24-20 If the EETI function is selected for this GPIO then both a high-to-low and a low-to-high edge will set
the PME, SMI and MSC status bits.
Note 24-21 The nIO_SMI pin is inactive when the internal group SMI signal is inactive and when the SMI enable
bit (EN_SMI, bit 7 of the SMI_EN2 register) is '0'. When the output buffer type is OD, nIO_SMI pin
is floating when inactive; when the output buffer type is push-pull, the nIO_SMI pin is high when
inactive.
Note 24-22 Bit3 of the PME_STS5 register may be set on a VCC POR. If GP53 is configured as input, then the
corresponding PME status bits will be set on a VCC POR. These bits are R/W but have no effect on
circuit operation.
Note 24-23 These bits are R/W but have no effect on circuit operation.
DS00002121B-page 250
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
25.0 VALID POWER MODES
The following table shows the valid power states for each power supply to the device.
TABLE 25-1: VALID POWER STATES
Power Supply
Power State
S0-S2
S3
S4-S5
Vbat
On
On
On
Off (Note 25-1)
Off (Note 25-1)
Off (Note 25-1)
VTR
VCC
On
On
On
Off
On
Off
HVTR
On (HVTR=VTR)
On (HVTR=VTR)
On (HVTR=VTR)
Note 25-1
Although this is not considered normal operating mode, Vbat = Off is a valid power state. When Vbat
is off all battery backed system context will be lost.
2016-2017 Microchip Technology Inc.
DS00002121B-page 251
SCH3227/SCH3226/SCH3224/SCH3222
26.0 OPERATIONAL DESCRIPTION
26.1 Maximum Ratings
o
o
Operating Temperature Range (Industrial)............................................................................................... -40 C to +85 C
o
o
Operating Temperature Range (Commercial) ..............................................................................................0 C to +70 C
o
o
Storage Temperature Range.....................................................................................................................-55 to +150 C
Lead Temperature Range ........................................................................................Refer to JEDEC Spec. J-STD-020b
Note:
Stresses above those listed above and below could cause permanent damage to the device. This is a
stress rating only and functional operation of the device at any other condition above those indicated in the
operation sections of this specification is not implied. When powering this device from laboratory or system
power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can
result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or
off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility
exists, it is suggested that a clamp circuit be used.
26.1.1
SUPER I/O SECTION (PINS 3 TO 112)
Maximum V ...........................................................................................................................................................+5.0V
cc
Negative Voltage on any pin, with respect to Ground .............................................................................................. -0.3V
26.1.2
HARDWARE MONITORING BLOCK (PINS 1 AND 2 AND PINS 113 TO 119)
Maximum HVTR.......................................................................................................................................................+5.0V
Negative Voltage on any pin, with respect to Ground (Except analog inputs).......................................................... -0.3V
26.2 DC Electrical Characteristics
TABLE 26-1: BUFFER OPERATIONAL RATINGS
SUPER I/O BLOCK (TA INDUSTRIAL = -40OC – +85OC, VCC = +3.3 V ± 10%) OR
(TA COMMERCIAL = 0OC – +70OC, VCC = +3.3 V ± 10%)
Parameter
Symbol
MIN
TYP
MAX
Units
Comments
I Type Input Buffer
Low Input Level
TTL Levels
V
0.8
5.5
V
V
ILI
High Input Level
V
2.0
2.2
IHI
IS Type Input Buffer
Low Input Level
Schmitt Trigger
Schmitt Trigger
V
0.8
5.5
V
V
ILIS
IHIS
HYS
High Input Level
V
Schmitt Trigger Hysteresis
V
100
mV
O6 Type Buffer
Low Output Level
High Output Level
O8 Type Buffer
Low Output Level
High Output Level
I
I
= 6mA
= -3mA
V
0.4
0.4
V
V
OL
OL
OH
V
2.4
2.4
OH
I
I
= 8mA
= -4mA
V
V
V
OL
OL
OH
V
OH
DS00002121B-page 252
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 26-1: BUFFER OPERATIONAL RATINGS (CONTINUED)
SUPER I/O BLOCK (TA INDUSTRIAL = -40OC – +85OC, VCC = +3.3 V ± 10%) OR
(TA COMMERCIAL = 0OC – +70OC, VCC = +3.3 V ± 10%)
Parameter
OD4 Type Buffer
Symbol
MIN
TYP
MAX
Units
Comments
Low Output Level
High Output Level
I
= 4mA
OL
V
0.4
5.5
V
V
OL
Open Drain;
V
OH
OD8 Type Buffer
Low Output Level
High Output Level
O12 Type Buffer
Low Output Level
High Output Level
OD12 Type Buffer
Low Output Level
High Output Level
OD14 Type Buffer
Low Output Level
High Output Level
OP14 Type Buffer
Low Output Level
High Output Level
IO8 Type Buffer
Low Input Level
I
= 8mA
V
0.4
5.5
V
V
OL
OL
Open Drain;
V
OH
I
I
= 12mA
= -6mA
V
0.4
V
V
OL
OL
OH
V
2.4
OH
I
= 12mA
V
0.4
5.5
V
V
OL
OL
Open Drain;
V
OH
I
= 14mA
V
0.4
5.5
V
V
OL
OL
Open Drain;
V
OH
I
I
= 14mA
= -14mA
V
0.4
V
V
OL
OL
OH
V
2.4
OH
TTL Levels
V
0.8
5.5
0.4
V
V
V
V
ILI
IHI
OL
OH
High Input Level
Low Output Level
High Output Level
V
V
2.0
2.4
I
I
= 8mA
= -4mA
OL
OH
V
IS/O8 Type Buffer
Low Input Level
Schmitt Trigger
Schmitt Trigger
V
0.8
5.5
V
V
ILI
High Input Level
V
2.2
2.4
IHI
Schmitt Trigger Hysteresis
Low Output Level
High Output Level
V
100
mV
V
HYS
I
I
= 8mA
= -4mA
OL
V
0.4
OL
OH
V
V
OH
2016-2017 Microchip Technology Inc.
DS00002121B-page 253
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 26-1: BUFFER OPERATIONAL RATINGS (CONTINUED)
SUPER I/O BLOCK (TA INDUSTRIAL = -40OC – +85OC, VCC = +3.3 V ± 10%) OR
(TA COMMERCIAL = 0OC – +70OC, VCC = +3.3 V ± 10%)
Parameter
Symbol
MIN
TYP
MAX
Units
Comments
IO12 Type Buffer
Low Input Level
High Input Level
Low Output Level
High Output Level
TTL Levels
V
0.8
5.5
0.4
V
V
V
V
ILI
IHI
OL
OH
V
V
2.0
2.4
I
I
= 12mA
= -6mA
OL
OH
V
IOP14 Type Buffer
Low Input Level
TTL Levels
V
0.8
5.5
0.4
V
V
V
V
ILI
IHI
OL
OH
High Input Level
Low Output Level
High Output Level
V
V
2.0
2.4
I
I
= 14mA
= -14mA
OL
OH
V
IOD16 Type Buffer
Low Input Level
TTL Levels
V
0.8
5.5
0.4
V
V
V
ILI
IHI
OL
OH
High Input Level
Low Output Level
High Output Level
V
V
2.0
I
= 16mA
OL
Open Drain;
V
5.5
0.3
V
V
OD_PH Type Buffer
VOL
RLOAD is 40ohms to
1.2V
Max Output
impedance is 10ohms
PCI Type Buffers
(PCI_ICLK, PCI_I, PCI_O,
PCI_IO)
3.3V PCI 2.1 Compatible.
Leakage Current (ALL)
Input High Current
Input Low Current
(Note 26-1)
V
= V
CC
ILEAK
10
µA
µA
IN
IN
IH
V
= 0V
ILEAK
-10
IL
Backdrive
Protect/ChiProtect
(All signal pins excluding
LAD[3:0], LDRQ#, LFRAME#)
Input High Current
Input Low Current
V
V
= 0V
CC
IN
= 5.5V Max
ILEAK
10
µA
µA
IH
V
= 0V
IN
ILEAK
-10
IL
DS00002121B-page 254
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
TABLE 26-1: BUFFER OPERATIONAL RATINGS (CONTINUED)
SUPER I/O BLOCK (TA INDUSTRIAL = -40OC – +85OC, VCC = +3.3 V ± 10%) OR
(TA COMMERCIAL = 0OC – +70OC, VCC = +3.3 V ± 10%)
Parameter
5V Tolerant Pins
Symbol
MIN
TYP
MAX
Units
Comments
(All signal pins excluding
LAD[3:0], LDRQ#, LFRAME#)
Inputs and Outputs in High
Impedance State
Input High Current
Input Low Current
V
V
= 0V
CC
IN
ILEAK
10
µA
µA
IH
= 5.5V Max
ILEAK
-10
V
= 0V
IL
IN
LPC Bus Pins
(LAD[3:0], LDRQ#, LFRAME#)
V
V
V
= 0V and
= 3.3V
CC
CC
IN
Input High Current
Input Low Current
ILEAK
10
µA
IH
= 3.6V Max
ILEAK
-10
µA
IL
V
= 0V
IN
VCC Supply Current Active
I
1
mA
All outputs open, all
inputs transitioning
from/to 0V to/from
3.3V.
CC
(Note 26-2)
Trickle Supply Voltage
V
2.97
(Note 26-3)
3.3
3.0
3.63
V
TR
VTR Supply Current Active
I
20
mA
All outputs, all inputs
transitioning from/to
0V to/from 3.3V.
TR
(Note 26-2,
Note 26-4)
Battery Supply Voltage
V
2.2
3.6
V
BAT
VBAT Average Supply
Current Active
µA
All outputs open, all
inputs transitioning
to/from 0V from/to
3.0V).
VBAT Monitoring Active
I
I
1.5
BAT, AVG
BAT, AVG
VBAT Monitoring Disabled
1.0
10
VBAT Peak Supply Current
Active
VBAT Monitoring Active
I
µA
All outputs open, all
inputs transitioning
to/from 0V from/to
3.0V).
BAT, Peak
HARDWARE MONITORING BLOCK (TA = 0OC – +70OC, HVTR = +3.3 V ± 10%)
Parameter
Symbol
Min
Typ
Max
Units
Comments
Temperature-to-Digital
Converter Characteristics
o
o
o
Internal Temperature Accuracy
0 C <= T <= 70 C
A
-3
-2
±0.25
±0.25
+3
+2
C
o
o
40 C <= T <= 70 C
Resolution
o
A
C
External Diode Sensor
Accuracy
o
C
o
o
o
o
o
-5
-3
+5
+3
C
-40 C <= T <= 125 C
S
S
o
C
40 C <= T <= 100 C
o
C
Resolution
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HARDWARE MONITORING BLOCK (TA = 0OC – +70OC, HVTR = +3.3 V ± 10%)
Parameter
Symbol
Min
Typ
Max
Units
Comments
Analog-to-Digital Converter
Characteristics
Note 26-5
±2
%
Total Unadjusted Error
Differential Non-Linearity
Power Supply Sensitivity
TUE
DNL
PSS
±1
±1
LSB
%/V
sec
Total Monitoring Cycle Time
(Cycle Mode, Default
Averaging)
t
1.25
1.4
275
200
Note 26-6
Note 26-7
C(Cycle)
t
225
247
140
msec
C(Cts)
Conversion Time
(Continuous Mode, Default
Averaging)
k
Input Resistance
ADC Resolution
10 bits Note 26-10
Input Buffer (I)
(FANTACH1)
Low Input Level
High Input Level
V
0.8
V
V
ILI
V
2.0
2.0
0.8
Vcc+0.3
IHI
Input Buffer (I)
(FANTACH2-FANTACH3)
Low Input Level
High Input Level
V
0.8
5.5
V
V
ILI
V
IHI
I_VID Type Buffer
(GP62* to GP67*)
(Note 26-11)
Low Input Level
High Input Level
V
0.4
5.5
V
V
ILI
V
IHI
IOD Type Buffer
(PWM1, PWM2,
PWM3/ADDRESS ENABLE,
nHWM_INT
V
V
0.8
5.5
V
V
ILI
Low Input Level
High Input Level
Hysteresis
2.0
IHI
V
500
mV
V
HYS
Low Output Level
I
= +4.0 mA (Note 26-9)
OL
V
0.4
OL
Leakage Current
(ALL - Digital)
(Note 26-8)
Input High Current
V
V
= V
CC
IN
ILEAK
10
-10
10
µA
µA
pF
IH
Input Low Current
= 0V
IN
ILEAK
IL
Digital Input Capacitance
C
IN
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HARDWARE MONITORING BLOCK (TA = 0OC – +70OC, HVTR = +3.3 V ± 10%)
Parameter
Symbol
Min
Typ
Max
Units
Comments
HVTR Supply Current
All outputs open, all inputs
transitioning from/to 0V
to/from 3.3V.
Active Mode
I
2
µA
HTR
HARDWARE MONITORING BLOCK (TA = -40OC – +85OC, HVTR = +3.3 V ± 10%)
Parameter
Symbol
Min
Typ
Max
Units
Comments
Temperature-to-Digital
Converter Characteristics
o
o
o
Internal Temperature Accuracy
0 C <= T <= 85 C
A
-3
-2
±0.25
±0.25
+3
+3
C
o
o
40 C <= T <= 85 C
Resolution
o
A
C
External Diode Sensor
Accuracy
o
C
o
o
o
o
o
-5
-3
+5
+3
C
-40 C <= T <= 125 C
S
S
o
C
40 C <= T <= 100 C
o
C
Resolution
Analog-to-Digital Converter
Characteristics
Note 26-5
±2
%
Total Unadjusted Error
Differential Non-Linearity
Power Supply Sensitivity
TUE
DNL
PSS
±1
±2
LSB
%/V
sec
Total Monitoring Cycle Time
(Cycle Mode, Default
Averaging)
t
1.25
1.4
275
200
Note 26-6
Note 26-7
C(Cycle)
t
225
247
140
msec
C(Cts)
Conversion Time
(Continuous Mode, Default
Averaging)
k
Input Resistance
ADC Resolution
10 bits Note 26-10
Input Buffer (I)
(FANTACH1)
Low Input Level
High Input Level
V
0.8
V
V
ILI
V
2.0
2.0
0.8
Vcc+0.3
IHI
Input Buffer (I)
(FANTACH2-FANTACH3)
Low Input Level
High Input Level
V
0.8
5.5
V
V
ILI
V
IHI
I_VID Type Buffer
(GP62* to GP67*)
(Note 26-11)
Low Input Level
High Input Level
V
0.4
5.5
V
V
ILI
V
IHI
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HARDWARE MONITORING BLOCK (TA = -40OC – +85OC, HVTR = +3.3 V ± 10%)
Parameter
Symbol
Min
Typ
Max
Units
Comments
IOD Type Buffer
(PWM1, PWM2,
PWM3/ADDRESS ENABLE,
nHWM_INT
V
V
0.8
5.5
V
V
ILI
Low Input Level
High Input Level
Hysteresis
2.0
IHI
V
500
mV
V
HYS
Low Output Level
I
= +4.0 mA (Note 26-9)
V
0.4
OL
OL
Leakage Current
(ALL - Digital)
(Note 26-8)
Input High Current
V
V
= V
CC
IN
ILEAK
10
-10
10
µA
µA
pF
IH
Input Low Current
= 0V
IN
ILEAK
IL
Digital Input Capacitance
C
IN
HVTR Supply Current
All outputs open, all inputs
transitioning from/to 0V
to/from 3.3V.
Active Mode
I
2
µA
HTR
Note 1: Voltages are measured from the local ground potential, unless otherwise specified.
2: Typicals are at TA=25°C and represent most likely parametric norm.
3: The maximum allowable power dissipation at any temperature is PD = (TJmax - TA) / QJA.
4: Timing specifications are tested at the TTL logic levels, VIL=0.4V for a falling edge and VIH=2.4V for a rising
edge. TRI-STATE output voltage is forced to 1.4V.
Note 26-1
Note 26-2
All leakage currents are measured with all pins in high impedance.
These values are estimated. They will be updated after Characterization. Contact Microchip for the
latest values.
Note 26-3
Note 26-4
The minimum value given for V applies when V is active. When V is 0V, the minimum V is
TR CC CC TR
0V.
Max I
Max I
with V = 3.3V (nominal) is 10mA
CC
TRI
TRI
with V
= 0V (nominal) is 250uA
CC
Note 26-5
Note 26-6
TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC.
Total Monitoring Cycle Time for cycle mode includes a one second delay plus all temperature
conversions and all analog input voltage conversions.
Note 26-7
Note 26-8
Note 26-9
Only the nominal default case is shown in this section.
All leakage currents are measured with all pins in high impedance.
The low output level for PWM pins is actually +8.0mA.
Note 26-10 The h/w monitor analog block implements a 10-bit ADC. The output of this ADC goes to an average
block, which can be configured to accumulate the averaged value of the analog inputs. The amount
of averaging is programmable. The output of the averaging block produce a 12-bit temperature or
voltage reading value. The 8 MSbits go to the reading register and the 4 LSbits to the A/D LSb
register.
Note 26-11 Other platform components may use VID inputs and may require tighter limits.
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26.3 Capacitance Values for Pins
The input and output capacitance applies to both the Super I/O Block and the Hardware Monitoring Block digital pins.
TABLE 26-2: CAPACITANCE T = 25; FC = 1MHZ; V = 3.3V ±10%
A
CC
Limits
TYP
Parameter
Symbol
MIN
MAX
Units
Test Condition
Clock Input Capacitance
Input Capacitance
C
C
20
10
20
pF
pF
pF
IN
All pins except pin under test
tied to AC ground
IN
Output Capacitance
C
OUT
Note:
The input capacitance of a port is measured at the connector pins.
26.4 Reset Generators
TABLE 26-3: RESET GENERATORS
Supply
Trip Point
Tolerance
3.3V, 3.3V VTR
5.0V
2.8V
100 mV
150mV
4.45V
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27.0 TIMING DIAGRAMS
For the Timing Diagrams shown, the following capacitive loads are used on outputs.
Name
Capacitance Total (pF)
SER_IRQ
LAD [3:0]
LDRQ#
nDIR
50
50
50
240
240
240
240
240
240
240
240
240
240
50
nSTEP
nDS0
PD[0:7]
nSTROBE
nALF
KDAT
KCLK
MDAT
MCLK
LED1
LED2
50
TXD1
50
TXD2
50
TXD3
50
TXD4
50
TXD5
50
TXD6
50
27.1 Power Up Timing
FIGURE 27-1:
POWER-UP TIMING
t 1
t 2
V c c
t 3
A ll H o s t
A c c e s s e s
Name
Description
MIN
TYP
MAX
Units
t1
t2
t3
Vcc Slew from 2.7V to 0V
Vcc Slew from 0V to 2.7V
300
100
s
s
s
All Host Accesses After Power-up (See Note 27-1)
125
500
Note 27-1
Internal write-protection period after Vcc passes 2.7 volts on power-up.
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27.2 Input Clock Timing
FIGURE 27-2:
INPUT CLOCK TIMING
t1
CLOCKI
t2
t2
Name
t1
t2
Description
MIN
TYP
MAX
Units
Clock Cycle Time for 14.318MHZ
69.84
35
ns
ns
ns
Clock High Time/Low Time for 14.318MHz
Clock Rise Time/Fall Time (not shown)
20
5
27.3 LPC Interface Timing
FIGURE 27-3:
PCI CLOCK TIMING
t1
t4
t2
t5
t3
PCI_CLK
Name
t1
Description
MIN
30
TYP
MAX
Units
Period
33.3
nsec
nsec
nsec
nsec
nsec
t2
t3
t4
t5
High Time
Low Time
Rise Time
Fall Time
12
12
3
3
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FIGURE 27-4:
RESET TIMING
t1
PCI_RESET#
Name
t1
Description
MIN
TYP
MAX
Units
ms
PCI_RESET# width
1
FIGURE 27-5:
OUTPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS
CLK
t1
Output Delay
t2
t3
Tri-State Output
Name
t1
Description
MIN
TYP
MAX
11
Units
ns
CLK to Signal Valid Delay – Bused Signals
Float to Active Delay
2
t2
t3
2
11
28
ns
ns
Active to Float Delay
FIGURE 27-6:
INPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS
t1
t2
CLK
Inputs Valid
Input
Name
Description
MIN
TYP
MAX
Units
t1
t2
Input Set Up Time to CLK – Bused Signals
Input Hold Time from CLK
7
0
ns
ns
Note:
L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000
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FIGURE 27-7:
I/O WRITE
PCI_CLK
LFRAME#
LAD[3:0]
L1
L2
Address
Data
TAR
Sync=0110
L3
TAR
FIGURE 27-8:
I/O READ
PCI_CLK
LFRAME#
LAD[3:0]
L1
L2
Address
TAR
Sync=0110
L3
Data
TAR
Note:
L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000
FIGURE 27-9:
DMA REQUEST ASSERTION THROUGH LDRQ#
PCI_CLK
LDRQ#
Start
MSB
LSB
ACT
FIGURE 27-10:
DMA WRITE (FIRST BYTE)
PCI_CLK
LFRAME#
LAD[3:0]
Start C+D CHL Size
TAR
Sync=0101
L1
Data
TAR
Note:
L1=Sync of 0000
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FIGURE 27-11:
DMA READ (FIRST BYTE)
PCI_CLK
LFRAME#
LAD[3:0]
Start C+D CHL Size
Data
TAR
Sync=0101
L1
TAR
Note:
L1=Sync of 0000
27.4 Parallel Port Timing
FIGURE 27-12:
EPP 1.9 DATA OR ADDRESS WRITE CYCLE
t1
t2
nWRITE
t3
PD<7:0>
t4
t5
t6
t7
nDATASTB
nADDRSTB
t8
t9
nWAIT
Name
t1
Description
MIN
TYP
MAX
Units
ns
nWAIT Asserted to nWRITE Asserted (See Note 27-2)
nWAIT Asserted to nWRITE Change (See Note 27-2)
nWAIT Asserted to PDATA Invalid (See Note 27-2)
PDATA Valid to Command Asserted
60
60
0
185
t2
t3
t4
t5
t6
t7
185
ns
ns
ns
ns
ns
ns
10
5
nWRITE to Command Asserted
35
nWAIT Asserted to Command Asserted (See Note 27-2)
60
60
210
190
nWAIT Deasserted to Command Deasserted
(See Note 27-2)
t8
t9
Command Asserted to nWAIT Deasserted
Command Deasserted to nWAIT Asserted
0
0
10
s
ns
Note 27-2
nWAIT must be filtered to compensate for ringing on the parallel bus cable. nWAIT is considered to
have settled after it does not transition for a minimum of 50 nsec.
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FIGURE 27-13:
EPP 1.9 DATA OR ADDRESS READ CYCLE
t1
t3
t2
nWRITE
t4
t5
t6
PD<7:0>
t7
t8
t9
t10
DATASTB
ADDRSTB
t11
t12
nWAIT
Name
t1
Description
nWAIT Asserted to nWRITE Deasserted
MIN
TYP
MAX
185
Units
ns
0
t2
t3
t4
t5
t6
t7
t8
t9
t10
nWAIT Asserted to nWRITE Modified (Notes 1,2)
nWAIT Asserted to PDATA Hi-Z (Note 1)
Command Asserted to PDATA Valid
60
60
0
190
180
ns
ns
ns
ns
ns
ns
ns
ns
ns
Command Deasserted to PDATA Hi-Z
nWAIT Asserted to PDATA Driven (Note 1)
PDATA Hi-Z to Command Asserted
0
60
0
190
30
nWRITE Deasserted to Command
1
nWAIT Asserted to Command Asserted
0
195
180
nWAIT Deasserted to Command Deasserted
(Note 1)
60
t11
t12
PDATA Valid to nWAIT Deasserted
PDATA Hi-Z to nWAIT Asserted
0
0
ns
µs
Note 1: nWAIT is considered to have settled after it does not transition for a minimum of 50 ns.
2: When not executing a write cycle, EPP nWRITE is inactive high.
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FIGURE 27-14:
EPP 1.7 DATA OR ADDRESS WRITE CYCLE
t1
t2
nWRITE
PD<7:0>
t3
t4
nDATASTB
nADDRSTB
t5
nWAIT
Name
t1
Description
MIN
TYP
MAX
40
Units
ns
Command Deasserted to nWRITE Change
Command Deasserted to PDATA Invalid
PDATA Valid to Command Asserted
nWRITE to Command
0
t2
t3
t4
t5
50
10
5
ns
ns
ns
ns
35
35
Command Deasserted to nWAIT Deasserted
0
FIGURE 27-15:
EPP 1.7 DATA OR ADDRESS READ CYCLE
nWRITE
t1
t2
PD<7:0>
nDATASTB
nADDRSTB
nWAIT
t3
Name
t1
Description
MIN
TYP
MAX
Units
Command Asserted to PDATA Valid
0
0
0
ns
ns
ns
t2
t3
Command Deasserted to PDATA Hi-Z
Command Deasserted to nWAIT Deasserted
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27.4.1
ECP PARALLEL PORT TIMING
Parallel Port FIFO (Mode 101)
The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using DMA. The
state machine does not examine nACK and begins the next transfer based on Busy. Refer to FIGURE 27-16: on
page 268.
ECP Parallel Port Timing
The timing is designed to allow operation at approximately 2.0 Mbytes/sec over a 15ft cable. If a shorter cable is used
then the bandwidth will increase.
Forward-Idle
When the host has no data to send it keeps HostClk (nStrobe) high and the peripheral will leave PeriphClk (Busy) low.
Forward Data Transfer Phase
The interface transfers data and commands from the host to the peripheral using an interlocked PeriphAck and HostClk.
The peripheral may indicate its desire to send data to the host by asserting nPeriphRequest.
The Forward Data Transfer Phase may be entered from the Forward-Idle Phase. While in the Forward Phase the periph-
eral may asynchronously assert the nPeriphRequest (nFault) to request that the channel be reversed. When the periph-
eral is not busy it sets PeriphAck (Busy) low. The host then sets HostClk (nStrobe) low when it is prepared to send data.
The data must be stable for the specified setup time prior to the falling edge of HostClk. The peripheral then sets
PeriphAck (Busy) high to acknowledge the handshake. The host then sets HostClk (nStrobe) high. The peripheral then
accepts the data and sets PeriphAck (Busy) low, completing the transfer. This sequence is shown in FIGURE 27-17: on
page 268.
The timing is designed to provide 3 cable round-trip times for data setup if Data is driven simultaneously with HostClk
(nStrobe).
Reverse-Idle Phase
The peripheral has no data to send and keeps PeriphClk high. The host is idle and keeps HostAck low.
Reverse Data Transfer Phase
The interface transfers data and commands from the peripheral to the host using an interlocked HostAck and PeriphClk.
The Reverse Data Transfer Phase may be entered from the Reverse-Idle Phase. After the previous byte has been
accepted the host sets HostAck (nALF) low. The peripheral then sets PeriphClk (nACK) low when it has data to send.
The data must be stable for the specified setup time prior to the falling edge of PeriphClk. When the host is ready to
accept a byte it sets HostAck (nALF) high to acknowledge the handshake. The peripheral then sets PeriphClk (nACK)
high. After the host has accepted the data, it sets HostAck (nALF) low, completing the transfer. This sequence is shown
in FIGURE 27-18: on page 269.
Output Drivers
To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data,
HostAck, HostClk, PeriphAck, PeriphClk) are used in ECP Mode. Because the use of active drivers can present com-
patibility problems in Compatible Mode (the control signals, by tradition, are specified as open-drain), the drivers are
dynamically changed from open-drain to push-pull. The timing for the dynamic driver change is specified in the IEEE
1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July 14, 1993, available from Microsoft.
The dynamic driver change must be implemented properly to prevent glitching the outputs.
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FIGURE 27-16:
PARALLEL PORT FIFO TIMING
t6
t3
PD<7:0>
t1
t2
t5
nSTROBE
BUSY
t4
Name
Description
MIN
600
TYP
MAX
Units
t1
t2
t3
t4
t5
t6
PDATA Valid to nSTROBE Active
nSTROBE Active Pulse Width
ns
ns
ns
ns
ns
ns
600
450
PDATA Hold from nSTROBE Inactive (See Note 27-3)
nSTROBE Active to BUSY Active
500
BUSY Inactive to nSTROBE Active
680
80
BUSY Inactive to PDATA Invalid (See Note 27-3)
Note 27-3
The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if
another data transfer is pending. If no other data transfer is pending, the data is held indefinitely.
FIGURE 27-17:
ECP PARALLEL PORT FORWARD TIMING
t3
t4
nALF
PD<7:0>
t2
t1
t7
t8
nSTROBE
BUSY
t6
t5
t6
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Name
t1
Description
MIN
TYP
MAX
60
Units
nALF Valid to nSTROBE Asserted
PDATA Valid to nSTROBE Asserted
0
0
ns
ns
ns
t2
t3
60
BUSY Deasserted to nALF Changed
(Notes 1,2)
80
180
t4
t5
t6
t7
t8
BUSY Deasserted to PDATA Changed (Notes 1,2)
nSTROBE Asserted to Busy Asserted
80
0
180
ns
ns
ns
ns
ns
nSTROBE Deasserted to Busy Deasserted
BUSY Deasserted to nSTROBE Asserted (Notes 1,2)
BUSY Asserted to nSTROBE Deasserted (Note 2)
0
80
80
200
180
Note 1: Maximum value only applies if there is data in the FIFO waiting to be written out.
2: BUSY is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
FIGURE 27-18:
ECP PARALLEL PORT REVERSE TIMING
t2
PD<7:0>
t1
t5
t6
nACK
nALF
t4
t3
t4
Name
t1
Description
MIN
TYP
MAX
Units
PDATA Valid to nACK Asserted
0
ns
ns
ns
t2
t3
nALF Deasserted to PDATA Changed
0
nACK Asserted to nALF Deasserted
(Notes 1,2)
80
200
200
t4
t5
t6
nACK Deasserted to nALF Asserted (Note 2)
nALF Asserted to nACK Asserted
80
0
ns
ns
ns
nALF Deasserted to nACK Deasserted
0
Note 1: Maximum value only applies if there is room in the FIFO and terminal count has not been received. ECP
can stall by keeping nALF low.
2: nACK is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns.
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27.5 IR Timing
FIGURE 27-19:
IRDA RECEIVE TIMING
DATA
0
1
0
1
0
0
1
1
0
1
1
t2
t1
t2
t1
IRRX
n IRRX
Parameter
min
typ
max
units
t1 Pulse Width at 115kbaud
t1 Pulse Width at 57.6kbaud
t1 Pulse Width at 38.4kbaud
t1 Pulse Width at 19.2kbaud
t1 Pulse Width at 9.6kbaud
t1 Pulse Width at 4.8kbaud
t1 Pulse Width at 2.4kbaud
t2 Bit Time at 115kbaud
t2 Bit Time at 57.6kbaud
t2 Bit Time at 38.4kbaud
t2 Bit Time at 19.2kbaud
t2 Bit Time at 9.6kbaud
t2 Bit Time at 4.8kbaud
t2 Bit Time at 2.4kbaud
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.6
3.22
4.8
2.71
3.69
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
5.53
9.7
11.07
22.13
44.27
88.55
19.5
39
78
8.68
17.4
26
52
104
208
416
Notes:
1. Receive Pulse Detection Criteria: A received pulse is considered detected if the
received pulse is a minimum of 1.41µs.
2. IRRX: L5, CRF1 Bit 0 = 1
nIRRX: L5, CRF1 Bit 0 = 0 (default)
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FIGURE 27-20:
IRDA TRANSMIT TIMING
DATA
1
0
1
0
0
1
1
1
1
0
0
t2
t1
t2
t1
IRTX
n IRTX
min
Parameter
typ
max
units
1.41
1.41
1.41
1.41
1.41
1.41
1.41
t1
Pulse Width at 115kbaud
Pulse Width at 57.6kbaud
Pulse Width at 38.4kbaud
Pulse Width at 19.2kbaud
Pulse Width at 9.6kbaud
Pulse Width at 4.8kbaud
Pulse Width at 2.4kbaud
Bit Time at 115kbaud
Bit Time at 57.6kbaud
Bit Time at 38.4kbaud
Bit Time at 19.2kbaud
Bit Time at 9.6kbaud
1.6
3.22
4.8
2.71
3.69
µ s
µ s
µ s
µ s
µ s
µ s
µ s
µ s
µ s
µ s
µ s
µ s
µ s
µ s
t1
t1
t1
t1
t1
t1
t2
t2
t2
t2
t2
t2
t2
5.53
9.7
11.07
22.13
44.27
88.55
19.5
39
78
8.68
17.4
26
52
104
208
416
Bit Time at 4.8kbaud
Bit Time at 2.4kbaud
Notes:
1. IrDA @ 115k is HPSIR compatible.
and 48SX.
IrDA @ 2400 will allow compatibility with HP95LX
2. IRTX: L5, CRF1 Bit 1 = 1 (default)
nIRTX: L5, CRF1 Bit 1 = 0
2016-2017 Microchip Technology Inc.
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SCH3227/SCH3226/SCH3224/SCH3222
FIGURE 27-21:
AMPLITUDE SHIFT-KEYED IR RECEIVE TIMING
DATA
0
1
0
1
0
0
1
1
0
1
1
t1
t2
IRRX
n IRRX
t3
t5
t4
MIRRX
t6
nMIRRX
Parameter
min
typ
max
units
t1
t2
t3
t4
t5
t6
Modulated Output Bit Time
Off Bit Time
µ s
µ s
µ s
µ s
µ s
µ s
Modulated Output "On"
Modulated Output "Off"
Modulated Output "On"
Modulated Output "Off"
0.8
0.8
0.8
0.8
1
1
1
1
1.2
1.2
1.2
1.2
Notes:
1. IRRX: L5, CRF1 Bit 0 = 1
nIRRX: L5, CRF1 Bit 0 = 0 (default)
MIRRX, nMIRRX are the modulated outputs
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SCH3227/SCH3226/SCH3224/SCH3222
FIGURE 27-22:
AMPLITUDE SHIFT-KEYED IR TRANSMIT TIMING
DATA
0
1
0
1
0
0
1
1
0
1
1
t1
t2
IRTX
n IRTX
t3
t5
t4
t6
MIRTX
nMIRTX
Parameter
min
typ
max
units
t1
t2
t3
t4
t5
t6
Modulated Output Bit Time
Off Bit Time
µ s
µ s
µ s
µ s
µ s
µ s
Modulated Output "On"
Modulated Output "Off"
Modulated Output "On"
Modulated Output "Off"
0.8
0.8
0.8
0.8
1
1
1
1
1.2
1.2
1.2
1.2
Notes:
1. IRTX: L5, CRF1 Bit 1 = 1 (default)
nIRTX: L5, CRF1 Bit 1 = 0
MIRTX, nMIRTX are the modulated outputs
27.6 Serial IRQ Timing
FIGURE 27-23:
SETUP AND HOLD TIME
PCI_CLK
t1
t2
SER_IRQ
Name
t1
t2
Description
MIN
TYP
MAX
Units
nsec
nsec
SER_IRQ Setup Time to PCI_CLK Rising
SER_IRQ Hold Time to PCI_CLK Rising
7
0
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SCH3227/SCH3226/SCH3224/SCH3222
27.7 UART Interface Timing
FIGURE 27-24:
SERIAL PORT DATA
Data
Stop (1-2 Bits)
Data (5-8 Bits)
Start
Parity
t1
TXD1, 2
Name
t1
Description
MIN
TYP
MAX
Units
nsec
1
Serial Port Data Bit Time
t
BR
t
is 1/Baud Rate. The Baud Rate is programmed through the divisor latch registers. Baud Rates have percentage
BR
errors indicated in the “Baud Rate” table in the “Serial Port” section.
27.8 Keyboard/Mouse Interface Timing
FIGURE 27-25:
KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING
CLK
1
CLK
2
CLK
9
CLK
10
CLK
11
KCLK/
MCLK
t3 t4
t5
t2
t6
t1
KDAT/ Start Bit
MDAT
Bit 0
Bit 7
Parity Bit Stop Bit
Name
t1
Description
MIN
TYP
MAX
25
Units
µsec
Time from DATA transition to falling edge of CLOCK (Receive) 5
Time from rising edge of CLOCK to DATA transition (Receive) 5
t2
t3
t4
t5
T4-5
50
µsec
µsec
µsec
µsec
Duration of CLOCK inactive (Receive/Send)
Duration of CLOCK active (Receive/Send)
30
30
50
Time to keyboard inhibit after clock 11 to ensure the keyboard >0
does not start another transmission (Receive)
50
t6
Time from inactive to active CLOCK transition, used to time
when the auxiliary device samples DATA (Send)
5
25
µsec
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SCH3227/SCH3226/SCH3224/SCH3222
27.9 Resume Reset Signal Generation
nRSMRST signal is the reset output for the ICH resume well. This signal is used as a power on reset signal for the ICH.
SCH322x detects when VTR voltage raises above VTRIP, provides a delay before generating the rising edge of
nRSMRST. See definition of VTRIP on page 275.
This delay, tRESET_DELAY, (t1 on page 275) is nominally 350ms, starts when VTR voltage rises above the VTRIP trip
point. If the VTR voltage falls below VTRIP the during tRESET_DELAY then the following glitch protection behavior is
implemented:. When the VTR voltage rises above VTRIP, nRSMRST will remain asserted the full tRESET_DELAY after
which nRSMRST is deasserted.
On the falling edge there is minimal delay, tRESET_FALL.
Timing and voltage parameters are shown in Figure 27-26 and Table 27-1.
FIGURE 27-26:
RESUME RESET SEQUENCE
Max
Vtrip
Min
VTR (3.3V)
nRSMRST
t3
t2
t1
TABLE 27-1: RESUME RESET TIMING
Name
t1
Description
MIN
140
TYP
350
MAX
Units
msec
Notes
tRESET_DELAY: VTR active to nRSMRST
inactive
560
t2
tRESET_FALL: VTR inactive to nRSMRST
active (Glitch width allowance)
100
nsec
t3
tRESET_RISE
100
2.9
nsec
V
VTRIP
VTR low trip voltage
2.7
2.8
APPLICATION NOTE: The 5 Volt Standby power supply must power up before or simultaneous with VTR, and must
power down simultaneous with or after VTR (from ICH2 data sheet.) SCH322x does not have
a 5 Volt Standby power supply input and does not respond to incorrect 5 Volt Standby power
- VTR sequencing.
2016-2017 Microchip Technology Inc.
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27.10 PWRGD_OUT Signal Generation
FIGURE 27-27:
PWRGD_OUT TIMING VS. VOLTAGE 3.3V OR 5V DROP
RSMRST# = 1
3.3V, VTR, VCC or 5V
Voltage Trip Point
TDelay
TFD
PWRGD_OUT
Time
Symbol
Description
MIN
TYP
MAX
188ms
470ms
200ms
500ms
212ms
530ms
The delay time is from the rising voltage trip
voltage to the rising edge of PWRGD_OUT.
This delay is selected via a strapping option.
Default value is 200ms.
T
Delay
T
3s
20s
FD
For 3.3V and 5V trip points refer to Table 26-3, “Reset Generators,” on page 259.
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FIGURE 27-28:
PWG_OUT VS. PS_ON# SIGNAL NEGATION
RSMRST# = 1
PS_ON# or
Internal_THERMTRIP#
TRD
TDelay
PWRGD_OUT
Time
TYP
Symbol
Description
MIN
MAX
188ms
470ms
200ms
500ms
212ms
530ms
The delay time is from the falling edge of
PS_ON# to the rising edge of
PWRGD_OUT. This delay is selected via a
strapping option. Default value is 200ms.
T
Delay
T
15s
30s
FD
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SCH3227/SCH3226/SCH3224/SCH3222
T
D
T
D
RESETB or nFPRST
PWRGD_OUT
Time
Symbol
Description
MIN
TYP
MAX
T
0
1.6ms
2.0ms
Debounce Delay
D
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SCH3227/SCH3226/SCH3224/SCH3222
T
D
T
D
PWRGD_PS
PWRGD_OUT
Time
Symbol
Description
MIN
TYP
MAX
T
1s
10s
20s
Gate Delay
D
27.11 nLEDx Timing
FIGURE 27-29:
NLEDX TIMING
t1
t2
nLEDx
Name
Description
MIN
TYP
MAX
Units
sec
sec
2
1
t1
t2
Period
1 or 2
5.88
1.52
2
1
Blink ON Time
0
0.5
1. These Max values are due to internal Ring Oscillator. If 1Hz blink rate is selected for LED1 pin, the range will
vary from 0.33Hz to 1.0Hz. If 0.5Hz blink rate is selected for LED1 pin, the range will vary from 0.17Hz to 0.5Hz.
2. The blink rate is programmed through Bits[1:0] in LEDx register. When Bits[1:0]=00, LED is OFF. Bits[1:0]=01
indicates LED blink at 1Hz rate with a 50% duty cycle (0.5 sec ON, 0.5 sec OFF). Bits[1:0]=10 indicates LED blink
at ½ Hz rate with a 25% duty cycle (0.5 sec ON, 1.5 sec OFF). When Bits[1:0]=11, LED is ON.
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27.12 PWM Outputs
The following section shows the timing for the PWM[1:3] outputs.
FIGURE 27-30:
PWMX OUTPUT TIMING
t1
t2
FANx
TABLE 27-2: TIMING FOR PWM[1:3] OUTPUTS
Name
Description
MIN
TYP
MAX
Units
t1
PWM Period (Note 1)
- low frequency option
- high frequency option
11.4
10.7
90.9
42.7
msec
usec
t2
PWM High Time (Note 2)
0
99.6
%
Note 1: This value is programmable by the PWM frequency bits located in the FRFx registers.
2: The PWM High Time is based on a percentage of the total PWM period (min=0/256*T
, max
PWM
=255/256*T
). During Spin-up the PWM High Time can reach a 100% or Full On. (T
= t1).
PWM
PWM
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SCH3227/SCH3226/SCH3224/SCH3222
28.0 PACKAGE OUTLINES
FIGURE 28-1:
SCH3227 144-BALL WFBGA PACKAGE OUTLINE; 9 X 9 MM BODY, 0.65MM
PITCH
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SCH3227/SCH3226/SCH3224/SCH3222
FIGURE 28-2:
SCH3226, SCH3224 100-BALL WFBGA PACKAGE OUTLINE; 8 X 8 MM BODY,
0.65MM PITCH
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SCH3227/SCH3226/SCH3224/SCH3222
FIGURE 28-3:
SCH3222 84-BALL WFBGA PACKAGE OUTLINE; 7 X 7 MM BODY, 0.65MM
PITCH
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APPENDIX A: ADC VOLTAGE CONVERSION
TABLE A-1:
ANALOG-TO-DIGITAL VOLTAGE CONVERSIONS FOR HARDWARE MONITORING
BLOCK
Input Voltage
A/D Output
+5 V
Note 28-1
+3.3 V
Note 28-2
+12 V
+2.5V
1.5V
Decimal
Binary
<0.062
<0.026
<0.0172
<0.013
<0.008
0
1
2
3
4
5
6
7
8
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
0000 1000
0.062–0.125
0.125–0.188
0.188–0.250
0.250–0.313
0.313–0.375
0.375–0.438
0.438–0.500
0.500–0.563
0.026–0.052
0.052–0.078
0.078–0.104
0.104–0.130
0.130–0.156
0.156–0.182
0.182–0.208
0.208–0.234
0.017–0.034
0.034–0.052
0.052–0.069
0.069–0.086
0.086–0.103
0.103–0.120
0.120–0.138
0.138–0.155
0.013 - 0.031
0.031 - 0.039
0.039 - 0.052
0.052 - 0.065
0.065 - 0.078
0.078 - 0.091
0.091 - 0.104
0.104 - 0.117
0.008 - 0.015
0.015 - 0.024
0.024 - 0.031
0.031 - 0.039
0.039 - 0.047
0.047 - 0.055
0.055 - 0.063
0.063 - 0.071
4.000–4.063
8.000–8.063
12.000–12.063
1.666–1.692
3.330–3.560
5.000–5.026
1.100–1.117
2.200–2.217
3.300–3.317
0.833 - 0.846
1.665- 1.780
2,500 - 2.513
0.501 - 0.508
1.001 - 1.009
1.502 - 1.509
64 (1/4 Scale)
128 (1/2 Scale)
192 (3/4 Scale)
0100 0000
1000 0000
1100 0000
15.312–15.375
15.375–15.437
15.437–15.500
15.500–15.563
15.625–15.625
15.625–15.688
15.688–15.750
15.750–15.812
15.812–15.875
15.875–15.938
>15.938
6.380–6.406
6.406–6.432
6.432–6.458
6.458–6.484
6.484–6.510
6.510–6.536
6.536–6.562
6.562–6.588
6.588–6.615
6.615–6.640
>6.640
4.210–4.230
4.230–4.245
4.245–4.263
4.263–4.280
4.280–4.300
4.300–4.314
4.314–4.330
4.331–4.348
4.348–4.366
4.366–4.383
>4.383
3.190 - 3.200
3.200 - 3.216
3.216 - 3.229
3.229 - 3.242
3.242 - 3.255
3.255 - 3.268
3.268 - 3.281
3.281 - 3.294
3.294 - 3.308
3.308 - 3.320
> 3.320
1.916 - 1.925
1.925 - 1.931
1.931 - 1.948
1.948 - 1.947
1.947 - 1.957
1.957 - 1.963
1.963 - 1.970
1.970 - 1.978
1.978 - 1.987
1.987 - 1.994
> 1.994
245
246
247
248
249
250
251
252
253
254
255
1111 0101
1111 0110
1111 0111
1111 1000
1111 1001
1111 1010
1111 1011
1111 1100
1111 1101
1111 1110
1111 1111
Note 28-1
Note 28-2
The 5V input is a +5V nominal inputs. 2.5V input is a 2.5V nominal input.
The VCC, VTR, and Vbat inputs are +3.3V nominal inputs. VCC and VTR are nominal 3.3V power
supplies. Vbat is a nominal 3.0V power supply.
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SCH3227/SCH3226/SCH3224/SCH3222
APPENDIX B: EXAMPLE FAN CIRCUITS
The following figures show examples of circuitry on the board for the PWM outputs, tachometer inputs, and remote
diodes. Figure B-1 shows how the part can be used to control four fans by connecting two fans to one PWM output.
Note:
• These examples represent the minimum required components. Some designs may require additional compo-
nents.
• The SCH3222 device does not support fan control.
FIGURE B-1: FAN DRIVE CIRCUITRY FOR LOW FREQUENCY OPTION (APPLY TO PWM DRIVING
TWO FANS)
12V
3.3V
3.3V
1k
2.2k
PWMx
MMBT3904
M
10
MMBT2222
Fan1
Empty
M
10
MMBT2222
Fan2
Empty
2016-2017 Microchip Technology Inc.
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SCH3227/SCH3226/SCH3224/SCH3222
FIGURE B-2: FAN DRIVE CIRCUITRY FOR LOW FREQUENCY OPTION (APPLY TO PWM DRIVING
ONE FAN)
3.3V
12V
Fan
470
M
PWMx
0
MMBT2222
Empty
FIGURE B-3: FAN TACHOMETER CIRCUITRY (APPLY TO EACH FAN)
3.3V
10k
Tach
TACH
Input
Output
from Fan
D1
IN4148
Note: For fans controlled directly by a PWM, it is suggested to implement
the optional diode (D1) to protect the tachometer input from large voltage
spikes generated by the fan.
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SCH3227/SCH3226/SCH3224/SCH3222
FIGURE B-4: REMOTE DIODE (APPLY TO REMOTE2 LINES)
Remote Diode +
External Temperature
Sensing Diode
2.2nF
(MMBT3904)
Remote Diode -
Note 1: 2.2nF cap is optional and should be placed close to the SCH322x f used.
2: The voltage at PWM3 must be at least 2.0V to avoid triggering Address Enable.
3: The Remote Diode + and Remote Diode - tracks should be kept close together, in parallel with grounded
guard tracks on each side. Using wide tracks will help to minimize inductance and reduce noise pickup. A
10 mil track minimum width and spacing is recommended. See Figure B-5, "Suggested Minimum Track
Width and Spacing".
FIGURE B-5: SUGGESTED MINIMUM TRACK WIDTH AND SPACING
10 mil.
10 mil.
GND
10 mil.
D+
10 mil.
10 mil.
D-
10 mil.
10 mil.
GND
2016-2017 Microchip Technology Inc.
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APPENDIX C: TEST MODE
The SCH322x provides board test capability through the implementation of one XNOR chain and one XOR chain. The
XNOR chain is dedicated to the Super I/O portion and the Hardware Monitoring Block of the device.
Note:
Pins that are not brought out of the package are tied to a determinate voltage internal to the package, and
so will not affect the XNOR output, except that its initial state may differ among family members.
C.1
XNOR-Chain Test Mode Overview
XNOR-Chain test structure allows users to confirm that all pins are in contact with the motherboard during assembly
and test operations. See Figure C-1. When the chip is in the XNOR chain test mode, setting the state of any of the input
pins to the opposite of its current state will cause the output of the chain to toggle.
The XNOR-Chain test structure must be activated to perform these tests. When the XNOR-Chain is activated, the
SCH322x pin functions are disconnected from the device pins, which all become input pins except for one output pin at
the end of XNOR-Chain.
The tests that are performed when the XNOR-Chain test structure is activated require the board-level test hardware to
control the device pins and observe the results at the XNOR-Chain output pin.
FIGURE C-1: XNOR-CHAIN TEST STRUCTURE
I/O#1
I/O#2
I/O#3
I/O#n
XNor
Out
C.1.1
Board Test Mode
Board test mode can be entered as follows:
On the rising (deasserting) edge of PCI_RESET#, drive LFRAME# low and drive LAD[0] low.
Exit board test mode as follows:
On the rising (deasserting) edge of PCI_RESET#, drive either LFRAME# or LAD[0] high.
The PCI_RESET# pin is not included in the XNOR-Chain. The XNOR-Chain output pin# is TXD1. See the following sub-
sections for more details.
Pin List of XNOR Chain
All pins on the chip are inputs to the first XNOR chain, with the exception of the following:
• All power supply pins - HVTR, HVSS, VCC, VTR, and Vbat
• VSS and AVSS
• All analog inputs: Remote2-, Remote2+, Remote1-, Remote1+, VCCP_IN, +12V_IN, +5V_IN, +2.5V_IN
• TXD1 This is the chain output.
• PCI_RESET#.
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To put the chip in the first XNOR chain test mode, tie LAD0 and LFRAME# low. Then toggle PCI_RESET# from a low
to a high state. Once the chip is put into XNOR chain test mode, LAD0 and LFRAME# become part of the chain.
To exit the SIO XNOR chain test mode tie LAD0 or LFRAME# high. Then toggle PCI_RESET# from a low to a high state.
A VCC POR will also cause the XNOR chain test mode to be exited. To verify the test mode has been exited, observe
the output at TXD1. Toggling any of the input pins in the chain should not cause its state to change.
Setup of Super I/O XNOR Chain
Warning: Ensure power supply is off during setup.
• Connect the VSS, the AVSS, HVSS pins to ground.
• Connect the VCC, the VTR, and HVTR pins to 3.3V.
• Connect an oscilloscope or voltmeter to TXD1.
• All other pins should be tied to ground.
Testing
1. Turn power on.
2. With LAD0 and LFRAME# low, bring PCI_RESET# high. The chip is now in XNOR chain test mode. At this point,
all inputs to the first XNOR chain are low. The output, on TXD1 should also be low. Refer to INITIAL CONFIG on
Table C-1.
3. Bring the first pin high. The output on TXD1 should go toggle. Refer to STEP ONE in Table C-1.
4. In descending pin order, bring each input high. The output should switch states each time an input is toggled.
Continue until all inputs are high. The output on TXD1 should now be low. Refer to END CONFIG in Table C-1.
5. The current state of the chip is now represented by INITIAL CONFIG in Table C-2.
6. Each input should now be brought low, starting at pin one and continuing in ascending order. Continue until all
inputs are low. The output on TXD1 should now be low. Refer to Table C-2.
7. To exit test mode, tie LAD0 or LFRAME# high, and toggle PCI_RESET# from a low to a high state.
TABLE C-1:
TOGGLING INPUTS IN DESCENDING ORDER
LastPin
First Pin
(1 of N)
Pin N-1 Pin N-2 Pin N-3 Pin N-4
(N)
Pin ...
Output Pin
L
H
H
H
H
H
…
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H or L
Toggles
Toggles
Toggles
Toggles
Toggles
…
INITIAL CONFIG
STEP 1
H
H
H
H
…
H
H
L
L
L
L
L
STEP 2
H
H
H
…
H
H
L
L
L
L
STEP 3
H
H
…
H
H
L
L
L
STEP 4
H
…
H
H
L
L
STEP 5
…
H
H
…
L
…
Toggles
Toggles
STEP N
END CONFIG
H
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TABLE C-2:
TOGGLING INPUTS IN ASCENDING ORDER
First Pin
(1)
Next Pin
(2)
Last Pin
(N)
Pin (3)
Pin (4) PIN (5)
Pin ...
Output Pin
H
L
H
H
L
H
H
H
L
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
…
L
H
H
H
H
H
H
…
H
L
H or L
Toggles
Toggles
Toggles
Toggles
Toggles
…
INITIAL CONFIG
STEP 1
L
STEP 2
L
L
STEP 3
L
L
L
STEP 4
L
L
L
L
STEP 5
…
L
…
L
…
L
…
L
…
L
Toggles
Toggles
STEP N
L
L
L
L
L
L
END CONFIG
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SCH3227/SCH3226/SCH3224/SCH3222
APPENDIX D: DATA SHEET REVISION HISTORY
TABLE D-1:
SCH3227/SCH3226/SCH3224/SCH3222 REVISION HISTORY
Section/Figure/Entry Correction
Updated diagrams
Revision
DS00002121B (03-20-17) Figure 2-2, "SCH3226 Pin Diagram"
and Figure 2-3, "SCH3224 Pin
Diagram"
Table 2-2, "SCH3226 Summaries By Added footnote to pin TEST, indicating that a
Strap Option", Table 2-3, "SCH3224
Summary" and Table 2-4, "SCH3222
Summary"
connection to VSS is necessary.
DS00002121A (03-02-16)
Document Release
2016-2017 Microchip Technology Inc.
DS00002121B-page 291
SCH3227/SCH3226/SCH3224/SCH3222
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
-
PART NO.
Device
Examples:
XX
[XX]
[X]
-
a)
b)
SCH3227-SZ
Commercial temperature, 144-pin WFBGA,
Tray
Package
Tape and Reel
Option
Temperature
Range
SCH3227I-SZ-TR
Device:
SCH3227/SCH3226/SCH3224/SCH3222
Industrial temperature, 144-pin WFBGA, Tape
& Reel
Temperature
Range:
Blank
I
=
=
0C to +70C (Commercial)
-40C to +85C (Industrial)
Package:
SZ
SY
SX
=
=
=
144-pin WFBGA (SCH3227)
100-pin WFBGA (SCH3226. SCH3224)
84-pin WFBGA (SCH3222)
Tape and Reel
Option:
Blank = Standard packaging (tray)
TR = Tape and Reel (Note 1)
Note 1:
Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office for
package availability with the Tape and Reel
option.
DS00002121B-page 292
2016-2017 Microchip Technology Inc.
SCH3227/SCH3226/SCH3224/SCH3222
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-
tains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-
nars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-
cation” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-
ment.
Technical support is available through the web site at: http://www.microchip.com/support
2016-2017 Microchip Technology Inc.
DS00002121B-page 293
SCH3227/SCH3226/SCH3224/SCH3222
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro-
chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR,
MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,
SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision
Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard,
CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench,
MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher,
SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2016-2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 9781522414872
QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
CERTIFIEDꢀBYꢀDNVꢀ
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
== ISO/TSꢀ16949ꢀ==ꢀ
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS00002121B-page 294
2016-2017 Microchip Technology Inc.
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
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China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
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Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
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Tel: 86-756-3210040
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Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
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Tel: 852-2943-5100
Fax: 852-2401-3431
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Web Address:
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Tel: 678-957-9614
Fax: 678-957-1455
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Fax: 774-760-0088
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Germany - Heilbronn
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Tel: 86-769-8702-9880
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Fax: 60-3-6201-9859
Detroit
Novi, MI
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Italy - Milan
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Fax: 39-0331-466781
China - Nanjing
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Malaysia - Penang
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Poland - Warsaw
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Spain - Madrid
Tel: 34-91-708-08-90
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Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
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Sweden - Gothenberg
Tel: 46-31-704-60-40
San Jose, CA
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Thailand - Bangkok
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Sweden - Stockholm
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DS00002121B-page 295
2016-2017 Microchip Technology Inc.
11/07/16
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