SST25PF080B-80-4C-S2AE-T [MICROCHIP]
8 Mbit 2.3-3.6V SPI Serial Flash; 8兆位2.3-3.6V SPI串行闪存
| 型号： | SST25PF080B-80-4C-S2AE-T |
| 厂家： | 
MICROCHIP |
| 描述： | 8 Mbit 2.3-3.6V SPI Serial Flash |
| 文件： | 总32页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SST25PF080B
8 Mbit 2.3-3.6V SPI Serial Flash
Features
Product Description
• Single Voltage Read and Write Operations
- 2.3-3.6V
The 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ulti-
mately lowers total system costs. The SST25PF080B
devices are enhanced with improved operating fre-
quency and lower power consumption. SST25PF080B
SPI serial flash memories are manufactured with pro-
prietary, high-performance CMOS SuperFlash technol-
ogy. The split-gate cell design and thick-oxide tunneling
injector attain better reliability and manufacturability
compared with alternate approaches.
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
- 80 MHz (2.7-3.6V)
- 50 MHz (2.3-2.7V)
• Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
The SST25PF080B devices significantly improve per-
formance and reliability, while lowering power con-
sumption. The devices write (Program or Erase) with a
single power supply of 2.3-3.6V for SST25PF080B.
The total energy consumed is a function of the applied
voltage, current, and time of application. Since for any
given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time,
the total energy consumed during any Erase or Pro-
gram operation is less than alternative flash memory
technologies.
• Low Power Consumption:
- Active Read Current: 10 mA (typical)
- Standby Current: 5 µA (typical)
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Uniform 32 KByte overlay blocks
- Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
- Chip-Erase Time: 35 ms (typical)
- Sector-/Block-Erase Time: 18 ms (typical)
- Byte-Program Time: 7 µs (typical)
The SST25PF080B device is offered in 8-lead SOIC
(150 mils), 8-lead SOIC (200 mils), and 8-contact
WSON (6mm x 5mm). See Figure 2-1 for pin assign-
ments.
• Auto Address Increment (AAI) Programming
- Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
- Software polling the BUSY bit in Status Register
- Busy Status readout on SO pin in AAI Mode
• Hold Pin (HOLD#)
- Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
- Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
- Write protection through Block-Protection bits in
status register
• Temperature Range
- Commercial: 0°C to +70°C
• Packages Available
- 8-lead SOIC (150 mils)
- 8-lead SOIC (200 mils)
- 8-contact WSON (6mm x 5mm)
• All devices are RoHS compliant
2012 Microchip Technology Inc.
DS25134A-page 1
SST25PF080B
1.0
BLOCK DIAGRAM
SuperFlash
Memory
X - Decoder
Address
Buffers
and
Latches
Y - Decoder
I/O Buffers
and
Control Logic
Data Latches
Serial Interface
25137 B1.0
CE# SCK SI SO WP# HOLD#
FIGURE 1-1:
FUNCTIONAL BLOCK DIAGRAM
DS25134A-page 2
2012 Microchip Technology Inc.
SST25PF080B
2.0
PIN DESCRIPTION
1
2
3
4
8
7
6
5
CE#
SO
V
DD
1
2
3
4
8
7
6
5
CE#
SO
V
DD
HOLD#
SCK
SI
HOLD#
SCK
SI
Top View
Top View
WP#
WP#
V
SS
V
SS
25137 08-soic S2A P1.0
25137 08-wson QA P2.0
8-lead SOIC
8-contact WSON
FIGURE 2-1:
TABLE 2-1:
PIN ASSIGNMENTS
PIN DESCRIPTION
Functions
To provide the timing of the serial interface.
Symbol Pin Name
SCK
Serial Clock
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY#
pin. See “Hardware End-of-Write Detection” on page 9 for details.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for
the duration of any command sequence.
WP#
Write Protect
Hold
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD#
To temporarily stop serial communication with SPI flash memory without resetting
the device.
VDD
VSS
Power Supply
Ground
To provide power supply voltage: 2.3-3.6V for SST25PF080B
2012 Microchip Technology Inc.
DS25134A-page 3
SST25PF080B
used to select the device, and data is accessed through
the Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK).
3.0
MEMORY ORGANIZATION
The SST25PF080B SuperFlash memory array is orga-
nized in uniform 4 KByte erasable sectors with 32
KByte overlay blocks and 64 KByte overlay erasable
blocks.
The SST25PF080B supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 4-1, is the
state of the SCK signal when the bus master is in
Standby mode and no data is being transferred. The
SCK signal is low for Mode 0 and SCK signal is high for
Mode 3. For both modes, the Serial Data In (SI) is sam-
pled at the rising edge of the SCK clock signal and the
Serial Data Output (SO) is driven after the falling edge
of the SCK clock signal.
4.0
DEVICE OPERATION
The SST25PF080B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI
bus consist of four control lines; Chip Enable (CE#) is
CE#
MODE 3
MODE 3
MODE 0
MODE 0
SCK
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SI
DON'T CARE
MSB
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
25137 SPIprot.0
FIGURE 4-1:
SPI PROTOCOL
4.1
Hold Operation
The HOLD# pin is used to pause a serial sequence
underway with the SPI flash memory without resetting
the clocking sequence. To activate the HOLD# mode,
CE# must be in active low state. The HOLD# mode
begins when the SCK active low state coincides with
the falling edge of the HOLD# signal. The HOLD mode
ends when the HOLD# signal’s rising edge coincides
with the SCK active low state.
low state, then the device exits in Hold mode when the
SCK next reaches the active low state. See Figure 4-2
for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition,the
device returns to Standby mode. As long as HOLD#
signal is low, the memory remains in the Hold condition.
To resume communication with the device, HOLD#
must be driven active high, and CE# must be driven
active low. See Figure 5-3 for Hold timing.
If the falling edge of the HOLD# signal does not coin-
cide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the
active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active
SCK
HOLD#
Active
Hold
Active
Hold
Active
25137 HoldCond.0
FIGURE 4-2:
HOLD CONDITION WAVEFORM
DS25134A-page 4
2012 Microchip Technology Inc.
SST25PF080B
4.2.1
WRITE PROTECT PIN (WP#)
4.2
Write Protection
The Write Protect (WP#) pin enables the lock-down
function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-
Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 4-1). When WP# is
high, the lock-down function of the BPL bit is disabled.
SST25PF080B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-
down function of the status register. The Block-Protec-
tion bits (BP2, BP1, BP0, and BPL) in the status regis-
ter provide Write protection to the memory array and
the status register. See Table 4-3 for the Block-Protec-
tion description.
TABLE 4-1:
WP#
CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION
BPL
1
Execute WRSR Instruction
Not Allowed
L
L
0
Allowed
H
X
Allowed
The factory-programmed portion of the Security ID can
never be programmed, and none of the Security ID can
be erased.
4.3
Security ID
SST25PF080B offers a 256-bit Security ID (Sec ID)
feature. The Security ID space is divided into two parts
– one factory-programmed, 64-bit segment and one
user-programmable 192-bit segment. The factory-pro-
grammed segment is programmed at Microchip with a
unique number and cannot be changed. The user-pro-
grammable segment is left unprogrammed for the cus-
tomer to program as desired.
4.4
Status Register
The software status register provides status on
whether the flash memory array is available for any
Read or Write operation, whether the device is Write
enabled, and the state of the Memory Write protection.
During an internal Erase or Program operation, the sta-
tus register may be read only to determine the comple-
tion of an operation in progress. Table 4-2 describes
the function of each bit in the software status register.
Use the Program SID command to program the Secu-
rity ID using the address shown in Table 4-5. Once pro-
grammed, the Security ID can be locked using the
Lockout SID command. This prevents any future write
to the Security ID.
TABLE 4-2:
SOFTWARE STATUS REGISTER
Default at
Bit
Name
Function
Power-up
Read/Write
0
BUSY
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
1
WEL
1 = Device is memory Write enabled
0
R
0 = Device is not memory Write enabled
2
3
4
5
BP0
BP1
BP2
SEC1
Indicates current level of block write protection
Indicates current level of block write protection
Indicates current level of block write protection
1
1
R/W
R/W
R/W
R
1
Security ID status
0 or 1
1 = Security ID space locked
0 = Security ID space not locked
6
7
AAI
Auto Address Increment Programming status
1 = AII programming mode
0 = Byte-Program mode
0
0
R
BPL
1 = BP2, BP1, BP0 are read-only bits
0 = BP2, BP1, BP0 are readable/writable
R/W
1. The Security ID status will always be ‘1’ at power-up after a successful execution of the Lockout SID instruction; otherwise,
the default at power-up is ‘0’.
2012 Microchip Technology Inc.
DS25134A-page 5
SST25PF080B
4.4.1
BUSY
4.4.3
AUTO ADDRESS INCREMENT (AAI)
The Busy bit determines whether there is an internal
Erase or Program operation in progress. A “1” for the
Busy bit indicates the device is busy with an operation
in progress. A “0” indicates the device is ready for the
next valid operation.
The Auto Address Increment Programming-Status bit
provides status on whether the device is in AAI pro-
gramming mode or Byte-Program mode. The default at
power up is Byte-Program mode.
4.4.4
SECURITY ID STATUS (SEC)
4.4.2
WRITE ENABLE LATCH (WEL)
The Security ID Status (SEC) bit indicates when the
Security ID space is locked to prevent a Write com-
mand. The SEC is ‘1’ after the host issues a Lockout
SID command. Once the host issues a Lockout SID
command, the SEC can never be reset to ‘0’.
The Write-Enable-Latch bit indicates the status of the
internal memory Write Enable Latch. If the Write-
Enable-Latch bit is set to “1”, it indicates the device is
Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept
any memory Write (Program/Erase) commands. The
Write-Enable-Latch bit is automatically reset under the
following conditions:
4.4.5
BLOCK PROTECTION (BP2, BP1,
BP0)
The Block-Protection (BP2, BP1, BP0) bits define the
size of the memory area, as defined in Table 4-3, to be
software protected against any memory Write (Pro-
gram or Erase) operation. The Write-Status-Register
(WRSR) instruction is used to program the BP2, BP1
and BP0 bits as long as WP# is high or the Block-Pro-
tect-Lock (BPL) bit is 0. Chip-Erase can only be exe-
cuted if Block-Protection bits are all 0. After power-up,
BP2, BP1 and BP0 are set to 1.
• Power-up
• Write-Disable (WRDI) instruction completion
• Byte-Program instruction completion
• Auto Address Increment (AAI) programming is
completed or reached its highest unprotected
memory address
• Sector-Erase instruction completion
• Block-Erase instruction completion
• Chip-Erase instruction completion
• Write-Status-Register instruction completion
• Program SID instruction completion
• Lockout SID instruction completion
4.4.6
BLOCK PROTECTION LOCK-DOWN
(BPL)
WP# pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents
any further alteration of the BPL, BP2, BP1, and BP0
bits. When the WP# pin is driven high (VIH), the BPL bit
has no effect and its value is “Don’t Care”. After power-
up, the BPL bit is reset to 0.
1
TABLE 4-3:
SOFTWARE STATUS REGISTER BLOCK PROTECTION FOR SST25PF080B
Status Register Bit2
Protected Memory Address
8 Mbit
Protection Level
None
BP2
BP1
0
BP0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
None
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
All Blocks
All Blocks
0
F0000H-FFFFFH
E0000H-FFFFFH
C0000H-FFFFFH
80000H-FFFFFH
00000H-FFFFFH
00000H-FFFFFH
00000H-FFFFFH
1
1
0
0
1
1
1. X = Don’t Care (RESERVED) default is ‘0’
2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected)
DS25134A-page 6
2012 Microchip Technology Inc.
SST25PF080B
4.5
Instructions
Instructions are used to read, write (Erase and Pro-
gram), and configure the SST25PF080B. The instruc-
tion bus cycles are 8 bits each for commands (Op
Code), data, and addresses. Prior to executing any
Byte-Program, Auto Address Increment (AAI) program-
ming, Sector-Erase, Block-Erase, Write-Status-Regis-
ter, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The com-
plete list of instructions is provided in Table 4-4. All
instructions are synchronized off a high to low transition
of CE#. Inputs will be accepted on the rising edge of
SCK starting with the most significant bit. CE# must be
driven low before an instruction is entered and must be
driven high after the last bit of the instruction has been
shifted in (except for Read, Read-ID, and Read-Status-
Register instructions). Any low to high transition on
CE#, before receiving the last bit of an instruction bus
cycle, will terminate the instruction in progress and
return the device to standby mode. Instruction com-
mands (Op Code), addresses, and data are all input
from the most significant bit (MSB) first.
TABLE 4-4:
DEVICE OPERATION INSTRUCTIONS
Address Dummy
Data
Instruction
Read
Description
Op Code Cycle1
0000 0011b (03H)
Cycle(s)2 Cycle(s) Cycle(s)
Read Memory
3
3
3
0
1
0
1 to ∞
1 to ∞
0
High-Speed Read
4 KByte Sector-Erase3 Erase 4 KByte of
Read Memory at higher speed 0000 1011b (0BH)
0010 0000b (20H)
0101 0010b (52H)
1101 1000b (D8H)
memory array
32 KByte Block-Erase4 Erase 32 KByte block
of memory array
64 KByte Block-Erase5 Erase 64 KByte block
3
3
0
0
0
0
0
0
0
of memory array
Chip-Erase
Erase Full Memory Array
To Program One Data Byte
0110 0000b (60H) or
1100 0111b (C7H)
Byte-Program
AAI-Word-Program6
0000 0010b (02H)
1010 1101b (ADH)
3
3
0
0
1
Auto Address Increment
Programming
2 to ∞
RDSR7
EWSR
WRSR
WREN
WRDI
Read-Status-Register
Enable-Write-Status-Register
Write-Status-Register
Write-Enable
0000 0101b (05H)
0101b 0000b (50H)
0000 0001b (01H)
0000 0110b (06H)
0000 0100b (04H)
0
0
0
0
0
3
0
0
0
0
0
0
1 to ∞
0
1
0
Write-Disable
0
RDID8
Read-ID
1001 0000b (90H) or
1010 1011b (ABH)
1 to ∞
JEDEC-ID
EBSY
JEDEC ID Read
1001 1111b (9FH)
0111 0000b (70H)
0
0
0
0
3 to ∞
Enable SO to output RY/BY#
status during AAI programming
0
DBSY
Disable SO to output RY/BY#
status during AAI programming
1000 0000b (80H)
0
0
0
Read SID
Read Security ID
1000 1000b (88H)
1
1
0
1
0
0
1 to 32
Program SID9
Lockout SID9
Program User Security ID area 1010 0101b (A5H)
Lockout Security ID Programming 1000 0101b (85H)
1
0
1. One bus cycle is eight clock periods.
2. Address bits above the most significant bit of each density can be VIL or VIH
.
3. 4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
4. 32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.
5. 64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data
to be programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be pro-
grammed into the initial address [A23-A1] with A0=1.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
2012 Microchip Technology Inc.
DS25134A-page 7
SST25PF080B
8. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s ID
and Device ID output stream is continuous until terminated by a low-to-high transition on CE#.
9. Requires a prior WREN command.
is reached, the address pointer will automatically incre-
ment to the beginning (wrap-around) of the address
space. Once the data from address location 1FFFFFH
has been read, the next output will be from address
location 000000H.
4.5.1
READ (33/25 MHZ)
The Read instruction, 03H, supports up to 33 MHz (2.7-
3.6V operation) or 25 MHz (2.3-2.7V operation) Read.
The device outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low to high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
The Read instruction is initiated by executing an 8-bit
command, 03H, followed by address bits [A23-A0].
CE# must remain active low for the duration of the
Read cycle. See Figure 4-3 for the Read sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
39
40
47 48
55 56
63 64
70
24
32
SCK
MODE 0
03
ADD.
MSB
HIGH IMPEDANCE
ADD.
ADD.
SI
MSB
N
N+1
N+2
N+3
N+4
D
OUT
D
D
D
D
SO
OUT
OUT
OUT
OUT
MSB
25137 ReadSeq_0.0
FIGURE 4-3:
READ SEQUENCE
through all addresses until terminated by a low to high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically incre-
ment to the beginning (wrap-around) of the address
space. Once the data from address location FFFFFH
has been read, the next output will be from address
location 00000H.
4.5.2 HIGH-SPEED-READ (80/50 MHZ)
The High-Speed-Read instruction supporting up to 80
MHz (2.7-3.6V operation) or 50 MHz (2.3-2.7V opera-
tion) Read is initiated by executing an 8-bit command,
0BH, followed by address bits [A23-A0] and a dummy
byte. CE# must remain active low for the duration of the
High-Speed-Read cycle. See Figure 4-4 for the High-
Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read
instruction outputs the data starting from the specified
address location. The data output stream is continuous
CE#
MODE 3
MODE 0
0
1
2
3
4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
SCK
0B
ADD.
MSB
HIGH IMPEDANCE
ADD.
ADD.
X
SI
MSB
N
N+1
N+2
N+3
N+4
D
D
D
D
D
OUT
SO
OUT
OUT
OUT
OUT
MSB
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V or V
)
IH
IL
25137 HSRdSeq.0
FIGURE 4-4:
HIGH-SPEED-READ SEQUENCE
DS25134A-page 8
2012 Microchip Technology Inc.
SST25PF080B
The Byte-Program instruction is initiated by executing
4.5.3
BYTE-PROGRAM
an 8-bit command, 02H, followed by address bits [A23
-
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte
must be in the erased state (FFH) when initiating a Pro-
gram operation. A Byte-Program instruction applied to a
protected memory area will be ignored.
A0]. Following the address, the data is input in order
from MSB (bit 7) to LSB (bit 0). CE# must be driven
high before the instruction is executed. The user may
poll the Busy bit in the software status register or wait
TBP for the completion of the internal self-timed Byte-
Program operation. See Figure 4-5 for the Byte-Pro-
gram sequence.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active
low for the duration of the Byte-Program instruction.
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
39
24
32
SCK
MODE 0
02
ADD.
ADD.
ADD.
D
IN
SI
MSB
MSB LSB
MSB
SO
HIGH IMPEDANCE
25137 ByteProg.0
FIGURE 4-5:
4.5.4
BYTE-PROGRAM SEQUENCE
device indicates it is no longer busy, data for the next
two sequential addresses may be programmed, fol-
lowed by the next two, and so on.
AUTO ADDRESS INCREMENT (AAI)
WORD-PROGRAM
The AAI program instruction allows multiple bytes of
data to be programmed without re-issuing the next
sequential address location. This feature decreases
total programming time when multiple bytes or entire
memory array is to be programmed. An AAI Word pro-
gram instruction pointing to a protected memory area
will be ignored. The selected address range must be in
the erased state (FFH) when initiating an AAI Word
Program operation. While within AAI Word Program-
ming sequence, only the following instructions are
valid: for software end-of-write detection—AAI Word
(ADH), WRDI (04H), and RDSR (05H); for hardware
end-of-write detection—AAI Word (ADH) and WRDI
(04H). There are three options to determine the com-
pletion of each AAI Word program cycle: hardware
detection by reading the Serial Output, software detec-
tion by polling the BUSY bit in the software status reg-
ister, or wait TBP. Refer to“End-of-Write Detection” for
details.
When programming the last desired word, or the high-
est unprotected memory address, check the busy sta-
tus using either the hardware or software (RDSR
instruction) method to check for program completion.
Once programming is complete, use the applicable
method to terminate AAI. If the device is in Software
End-of-Write Detection mode, execute the Write-Dis-
able (WRDI) instruction, 04H. If the device is in AAI
Hardware End-of-Write Detection mode, execute the
Write-Disable (WRDI) instruction, 04H, followed by the
8-bit DBSY command, 80H. There is no wrap mode
during AAI programming once the highest unprotected
memory address is reached. See Figures 4-8 and 4-9
for the AAI Word programming sequence.
4.5.5
END-OF-WRITE DETECTION
There are three methods to determine completion of a
program cycle during AAI Word programming: hard-
ware detection by reading the Serial Output, software
detection by polling the BUSY bit in the Software Status
Register, or wait TBP. The Hardware End-of-Write
detection method is described in the section below.
Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. Initiate the AAI Word
Program instruction by executing an 8-bit command,
ADH, followed by address bits [A23-A0]. Following the
addresses, two bytes of data are input sequentially,
each one from MSB (Bit 7) to LSB (Bit 0). The first byte
4.5.6
HARDWARE END-OF-WRITE
DETECTION
of data (D0) is programmed into the initial address [A23
-
A1] with A0=0, the second byte of Data (D1) is pro-
grammed into the initial address [A23-A1] with A0=1.
CE# must be driven high before executing the AAI
Word Program instruction. Check the BUSY status
before entering the next valid command. Once the
The Hardware End-of-Write detection method elimi-
nates the overhead of polling the Busy bit in the Soft-
ware Status Register during an AAI Word program
operation. The 8-bit command, 70H, configures the
Serial Output (SO) pin to indicate Flash Busy status
during AAI Word programming. (see Figure 4-6) The 8-
2012 Microchip Technology Inc.
DS25134A-page 9
SST25PF080B
bit command, 70H, must be executed prior to initiating
an AAI Word-Program instruction. Once an internal
programming operation begins, asserting CE# will
immediately drive the status of the internal flash status
on the SO pin. A ‘0’ indicates the device is busy and a
‘1’ indicates the device is ready for the next instruction.
De-asserting CE# will return the SO pin to tri-state.
While in AAI and Hardware End-of-Write detection
mode, the only valid instructions are AAI Word (ADH)
and WRDI (04H).
To exit AAI Hardware End-of-Write detection, first exe-
cute WRDI instruction, 04H, to reset the Write-Enable-
Latch bit (WEL=0) and AAI bit. Then execute the 8-bit
DBSY command, 80H, to disable RY/BY# status during
the AAI command. See Figures 4-7 and 4-8.
CE#
MODE 3
0
1
2
3
4 5 6 7
SCK
MODE 0
SI
70
MSB
SO
HIGH IMPEDANCE
25137 EnableSO.0
FIGURE 4-6:
ENABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
CE#
MODE 3
0
1
2
3
4 5 6 7
SCK
MODE 0
SI
80
MSB
SO
HIGH IMPEDANCE
25137 DisableSO.0
FIGURE 4-7:
DISABLE SO AS HARDWARE RY/BY# DURING AAI PROGRAMMING
DS25134A-page 10
2012 Microchip Technology Inc.
SST25PF080B
CE#
0
7
0
7
0
7
8
15 16 23 24 31 32 39 40 47
0
7
8
15 16 23
MODE 3
SCKMODE 0
AD
SI
WREN
A
A
A
D0
D1
AD
D2
D3
EBSY
Load AAI command, Address, 2 bytes data
SO
Check for Flash Busy Status to load next valid1 command
CE# cont.
0
7
8
15 16 23
0
7
0
7
0
7
8
15
SCK cont.
SI cont.
D
n-1
D
n
WRDI
RDSR
AD
DBSY
Last 2
Data Bytes
WRDI followed by DBSY
to exit AAI Mode
D
OUT
SO cont.
Check for Flash Busy Status to load next valid1 command
Note: 1. Valid commands during AAI programming: AAI command or WRDI command
2. User must configure the SO pin to output Flash Busy status during AAI programming
25137 AAI.HW.3
FIGURE 4-8:
AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH
HARDWARE END-OF-WRITE DETECTION
Wait T or poll Software Status
BP
register to load next valid1 command
CE#
0
7
8
15 16 23 24 31 32 39 40 47
0
7
8
15 16 23
0
7
8
15 16 23
0
7
0
7
8
15
MODE 3
SCK MODE 0
SI
D
n-1
D
n
WRDI
RDSR
AD
A
A
A
D0
D1
AD
D2
D3
AD
Last 2
Data Bytes
WRDI to exit
AAI Mode
Load AAI command, Address, 2 bytes data
SO
Note: 1. Valid commands during AAI programming: AAI command, RDSR command, or WRDI command
D
OUT
25137 AAI.SW.3
FIGURE 4-9:
AUTO ADDRESS INCREMENT (AAI) WORD-PROGRAM SEQUENCE WITH
SOFTWARE END-OF-WRITE DETECTION
2012 Microchip Technology Inc.
DS25134A-page 11
SST25PF080B
bits [A23-A0]. Address bits [AMS-A12] (AMS = Most Sig-
nificant address) are used to determine the sector
address (SAX), remaining address bits canbeVIL or VIH.
CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software
status register or wait TSE for the completion of the
internal self-timed Sector-Erase cycle. See Figure 4-10
for the Sector-Erase sequence.
4.5.7
4-KBYTE SECTOR-ERASE
The Sector-Erase instruction clears all bits in the
selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must
remain active low for the duration of any command
sequence. The Sector-Erase instruction is initiated by
executing an 8-bit command, 20H, followed by address
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
24
SCK
MODE 0
SI
20
ADD.
ADD.
ADD.
MSB
MSB
SO
HIGH IMPEDANCE
25137 SecErase.0
FIGURE 4-10:
SECTOR-ERASE SEQUENCE
nificant Address) are used to determine block address
(BAX), remaining address bits can be VIL or VIH. CE#
must be driven high before the instruction is executed. The
64-KByte Block-Erase instruction is initiated by executing an
8-bit command D8H, followed by address bits [A23-A0].
Address bits [AMS-A16] are used to determine block address
(BAX), remaining address bits can be VIL or VIH. CE# must
be driven high before the instruction is executed. The user
may poll the Busy bit in the software status register or wait
TBE for the completion of the internal self-timed 32-
KByte Block-Erase or 64-KByte Block-Erase cycles.
See Figures 4-11 and 4-12 for the 32-KByte Block-
Erase and 64-KByte Block-Erase sequences.
4.5.8
32-KBYTE AND 64-KBYTE BLOCK-
ERASE
The 32-KByte Block-Erase instruction clears all bits in
the selected 32 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be
ignored. The 64-KByte Block-Erase instruction clears all bits
in the selected 64 KByte block to FFH. A Block-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must remain
active low for the duration of any command sequence.
The 32-KByte Block-Erase instruction is initiated by
executing an 8-bit command, 52H, followed by address
bits [A23-A0]. Address bits [AMS-A15] (AMS = Most Sig-
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
24
SCK
MODE 0
SI
52
ADDR
ADDR ADDR
MSB
MSB
SO
HIGH IMPEDANCE
25137 32KBklEr.0
FIGURE 4-11:
32-KBYTE BLOCK-ERASE SEQUENCE
DS25134A-page 12
2012 Microchip Technology Inc.
SST25PF080B
CE#
SCK
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
15 16
23
31
24
SI
D8
ADDR
ADDR ADDR
MSB
MSB
SO
HIGH IMPEDANCE
25137 63KBlkEr.0
FIGURE 4-12:
64-KBYTE BLOCK-ERASE SEQUENCE
instruction is initiated by executing an 8-bit command,
60H or C7H. CE# must be driven high before the instruction
is executed. The user may poll the Busy bit in the software
status register or wait TCE for the completion of the
internal self-timed Chip-Erase cycle. See Figure 4-13
for the Chip-Erase sequence.
4.5.9
CHIP-ERASE
The Chip-Erase instruction clears all bits in the device
to FFH. A Chip-Erase instruction will be ignored if any
of the memory area is protected. Prior to any Write oper-
ation, the Write-Enable (WREN) instruction must be exe-
cuted. CE# must remain active low for the duration of
the Chip-Erase instruction sequence. The Chip-Erase
CE#
MODE 3
0
1 2 3 4 5 6 7
SCK
MODE 0
SI
60 or C7
MSB
SO
HIGH IMPEDANCE
25137 ChEr.0
FIGURE 4-13:
CHIP-ERASE SEQUENCE
4.6
Read Security ID
4.7
Lockout Security ID
To execute a Read SID operation, the host drives CE#
low, sends the Read Security ID command cycle (88H),
one address cycle, and then one dummy cycle. Each
cycle is eight clock periods long, most significant bit
first.
The Lockout SID instruction prevents any future
changes to the Security ID. To execute a Lockout SID,
the host drives CE# low, sends the Lockout SID com-
mand cycle (85H), then drives CE# high. Each cycle is
eight clocks long, most significant bit first. Poll the
BUSY bit in the software status register, or wait TPSID
for the completion of the Lockout SID operation.
,
After the dummy cycle, the device outputs data on the
falling edge of the SCK signal starting from the speci-
fied address location. The data output stream is contin-
uous through all SID addresses until terminated by a
low-to-high transition on CE#. The internal address
pointer automatically increments until the last SID
address is reached, then outputs 00H until CE# goes
high.
2012 Microchip Technology Inc.
DS25134A-page 13
SST25PF080B
4.8
Program Security ID
The Program SID instruction programs a byte of data in
the user-programmable, Security ID space. Security ID
addresses 08h-1FH are the user-programmable loca-
tions. The device ignores a Program Security ID
instruction pointing to an invalid or protected address,
see Table 4-5. Prior to the program operation, execute
WREN.
To execute a Program SID operation, the host drives
CE# low, sends the Program SID command cycle
(A5H), one address cycle, the data to be programmed,
then drives CE# high. Each cycle is eight clocks long,
most significant bit first. To determine the completion of
the internal, self-timed Program SID operation, poll the
BUSY bit in the software status register, or wait TPSID
for the completion of the internal self-timed Program
SID operation.
TABLE 4-5:
PROGRAM SECURITY ID
Program Security ID
Pre-Programmed at factory
User Programmable
Address Range
00H – 07H
08H – 1FH
properly received by the device. CE# must be driven
low before the RDSR instruction is entered and remain
low until the status data is read. Read-Status-Register
is continuous with ongoing clock cycles until it is termi-
nated by a low to high transition of the CE#. See Figure
4-14 for the RDSR instruction sequence.
4.8.1
READ-STATUS-REGISTER (RDSR)
The Read-Status-Register (RDSR) instruction allows
reading of the status register. The status register may
be read at any time even during a Write (Program/
Erase) operation. When a Write operation is in prog-
ress, the Busy bit may be checked before sending any
new commands to assure that the new commands are
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK
SI
05
HIGH IMPEDANCE
MSB
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
Status
Register Out
25137 RDSRseq.0
FIGURE 4-14:
READ-STATUS-REGISTER (RDSR) SEQUENCE
DS25134A-page 14
2012 Microchip Technology Inc.
SST25PF080B
execution of the Write-Status-Register (WRSR) instruc-
tion; however, the Write-Enable-Latch bit in the Status
Register will be cleared upon the rising edge CE# of the
WRSR instruction. CE# must be driven high before the
WREN instruction is executed.
4.8.2
WRITE-ENABLE (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit in the Status Register to 1 allowing
Write operations to occur. The WREN instruction must
be executed prior to any Write (Program/Erase) opera-
tion. The WREN instruction may also be used to allow
CE#
MODE 3
0
1 2 3 4 5 6 7
SCK
MODE 0
06
SI
MSB
SO
HIGH IMPEDANCE
25137 WREN.0
FIGURE 4-15:
WRITE ENABLE (WREN) SEQUENCE
ress. Any program operation in progress may continue
up to TBP after executing the WRDI instruction. CE#
must be driven high before the WRDI instruction is exe-
cuted.
4.8.3
WRITE-DISABLE (WRDI)
The Write-Disable (WRDI) instruction resets the Write-
Enable-Latch bit and AAI bit to 0 disabling any new
Write operations from occurring. The WRDI instruction
will not terminate any programming operation in prog-
CE#
MODE 3
0
1
2
3
4 5 6 7
SCK
MODE 0
SI
04
MSB
SO
HIGH IMPEDANCE
25137 WRDI.0
FIGURE 4-16:
WRITE DISABLE (WRDI) SEQUENCE
be driven low before the EWSR instruction is entered
and must be driven high before the EWSR instruction
is executed.
4.8.4 ENABLE-WRITE-STATUS-
REGISTER (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction
and opens the status register for alteration. The Write-
Status-Register instruction must be executed immedi-
ately after the execution of the Enable-Write-Status-
Register instruction. This two-step instruction
sequence of the EWSR instruction followed by the
WRSR instruction works like SDP (software data pro-
tection) command structure which prevents any acci-
dental alteration of the status register values. CE# must
2012 Microchip Technology Inc.
DS25134A-page 15
SST25PF080B
reset from “1” to “0”. When WP# is high, the lock-down
function of the BPL bit is disabled and the BPL, BP0,
BP1, and BP2 bits in the status register can all be
changed. As long as BPL bit is set to 0 or WP# pin is
driven high (VIH) prior to the low-to-high transition of the
CE# pin at the end of the WRSR instruction, the bits in
the status register can all be altered by the WRSR
instruction. In this case, a single WRSR instruction can
set the BPL bit to “1” to lock down the status register as
well as altering the BP0, BP1, and BP2 bits at the same
time. See Table 4-1 for a summary description of WP#
and BPL functions.
4.8.5
WRITE-STATUS-REGISTER (WRSR)
The Write-Status-Register instruction writes new val-
ues to the BP2, BP1, BP0, and BPL bits of the status
register. CE# must be driven low before the command
sequence of the WRSR instruction is entered and
driven high before the WRSR instruction is executed.
See Figure 4-17 for EWSR or WREN and WRSR
instruction sequences.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to “1”.
When the WP# is low, the BPL bit can only be set from
“0” to “1” to lock-down the status register, but cannot be
CE#
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
MODE 3
MODE 0
MODE 3
MODE 0
SCK
STATUS
REGISTER IN
SI
50 or 06
01
7 6 5 4 3 2 1 0
MSB
MSB
MSB
HIGH IMPEDANCE
SO
25137 EWSR.0
FIGURE 4-17:
ENABLE-WRITE-STATUS-REGISTER (EWSR) OR WRITE-ENABLE (WREN) AND
WRITE-STATUS-REGISTER (WRSR) SEQUENCE
DS25134A-page 16
2012 Microchip Technology Inc.
SST25PF080B
out on the SO pin. Byte 1, BFH, identifies the manufac-
turer as Microchip. Byte 2, 25H, identifies the memory
type as SPI Serial Flash. Byte 3, 8EH, identifies the
device as SST25PF080B. The instruction sequence is
shown in Figure 4-18. The JEDEC Read ID instruction
is terminated by a low to high transition on CE# at any
time during data output.
4.8.6
JEDEC READ-ID
The JEDEC Read-ID instruction identifies the device as
SST25PF080B and the manufacturer as Microchip.
The device information can be read from executing the
8-bit command, 9FH. Following the JEDEC Read-ID
instruction, the 8-bit manufacturer’s ID, BFH, is output
from the device. After that, a 16-bit device ID is shifted
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCK
SI
9F
HIGH IMPEDANCE
SO
25
8E
BF
MSB
MSB
25137 JEDECID.1
FIGURE 4-18:
TABLE 4-6:
JEDEC READ-ID SEQUENCE
JEDEC READ-ID DATA
Device ID
Manufacturer’s ID
Memory Type
Byte 2
Memory Capacity
Byte 3
Byte1
BFH
25H
8EH
2012 Microchip Technology Inc.
DS25134A-page 17
SST25PF080B
A0]. Following the Read-ID instruction, the manufac-
turer’s ID is located in address 00000H and the device
ID is located in address 00001H. Once the device is in
Read-ID mode, the manufacturer’s and device ID out-
put data toggles between address 00000H and 00001H
until terminated by a low to high transition on CE#.
4.8.7
READ-ID (RDID)
The Read-ID instruction (RDID) identifies the devices
as SST25PF080B and manufacturer as Microchip. This
command is backward compatible and should be used
as default device identification when multiple versions
of SPI Serial Flash devices are used in a design. The
device information can be read from executing an 8-bit
Refer to Tables 4-6 and 4-7 for device identification
data.
command, 90H or ABH, followed by address bits [A23
-
CE#
MODE 3
MODE 0
0
1
2
3
4
5
6
7
8
15 16
23
31
39
40
47 48
55 56
63
24
32
SCK
90 or AB
00
00
ADD1
SI
MSB
MSB
HIGH
IMPEDANCE
HIGH IMPEDANCE
Device ID
Device ID
BF
BF
SO
MSB
Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#.
Device ID = 8EH for SST25PF080B
1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.
25137 RdID.0
FIGURE 4-19:
TABLE 4-7:
READ-ID SEQUENCE
PRODUCT IDENTIFICATION
Address
Data
Manufacturer’s ID
Device ID
00000H
BFH
SST25PF080B
00001H
8EH
DS25134A-page 18
2012 Microchip Technology Inc.
SST25PF080B
5.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maxi-
mum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these conditions or conditions greater than those defined in the operational
sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may
affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V +0.5V
DD
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . .-2.0V to V +2.0V
DD
Package Power Dissipation Capability (T = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
A
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
1
Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
1
TABLE 5-1:
OPERATING RANGE
TABLE 5-2:
AC CONDITIONS OF TEST
Range
Ambient Temp
VDD
Input Rise/Fall Time
Output Load
Commercial
0°C to +70°C
2.3-3.6V
5ns
CL = 30 pF
1. See Figures 5-5 and 5-6
TABLE 5-3:
DC OPERATING CHARACTERISTICS
Limits
Symbol Parameter
Min
Max Units Test Conditions
IDDR
IDDR3
IDDW
ISB
Read Current
12
20
30
20
1
mA
mA
mA
µA
µA
µA
V
CE#=0.1 VDD/0.9 VDD@33 MHz, SO=open
CE#=0.1 VDD/0.9 VDD@80 MHz, SO=open
CE#=VDD
Read Current
Program and Erase Current
Standby Current
CE#=VDD, VIN=VDD or VSS
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Output High Voltage
ILO
1
VIL
0.7
VIH
0.7 VDD
VDD-0.2
V
VDD=VDD Max
VOL
VOL2
VOH
0.2
0.4
V
IOL=100 µA, VDD=VDD Min
IOL=1.6 mA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
V
V
TABLE 5-4:
CAPACITANCE (TA = 25°C, F=1 MHZ, OTHER PINS OPEN)
Parameter
Description
Test Condition
Maximum
12 pF
1
COUT
Output Pin Capacitance
Input Capacitance
VOUT = 0V
VIN = 0V
1
CIN
6 pF
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2012 Microchip Technology Inc.
DS25134A-page 19
SST25PF080B
TABLE 5-5:
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 5-6:
AC OPERATING CHARACTERISTICS, 2.3-2.7V
25 MHz
50 MHz
Symbol
Parameter
Serial Clock Frequency
Serial Clock High Time
Serial Clock Low Time
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CE# Active Setup Time
CE# Active Hold Time
CE# Not Active Setup Time
CE# Not Active Hold Time
CE# High Time
Min
Max
Min
Max
Units
MHz
ns
1
FCLK
25
50
TSCKH
TSCKL
18
18
0.1
0.1
5
9
9
ns
2
TSCKR
0.1
0.1
5
V/ns
V/ns
ns
TSCKF
3
TCES
3
TCEH
5
5
ns
3
TCHS
5
5
ns
3
TCHH
5
5
ns
TCPH
TCHZ
TCLZ
TDS
50
50
ns
CE# High to High-Z Output
SCK Low to Low-Z Output
Data In Setup Time
15
7
ns
0
2
4
5
5
5
5
0
2
4
5
5
5
5
ns
ns
TDH
Data In Hold Time
ns
THLS
THHS
THLH
THHH
THZ
HOLD# Low Setup Time
HOLD# High Setup Time
HOLD# Low Hold Time
HOLD# High Hold Time
HOLD# Low to High-Z Output
HOLD# High to Low-Z Output
Output Hold from SCK Change
Output Valid from SCK
Sector-Erase
ns
ns
ns
ns
7
7
7
7
ns
TLZ
ns
TOH
TV
0
0
ns
12
25
25
50
10
10
8
ns
TSE
25
25
50
10
10
ms
ms
ms
µs
TBE
Block-Erase
TSCE
TBP
Chip-Erase
Byte-Program
TPSID
Program Security ID
µs
1. Maximum clock frequency for Read Instruction, 03H, is 25 MHz
2. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements
3. Relative to SCK.
DS25134A-page 20
2012 Microchip Technology Inc.
SST25PF080B
TABLE 5-7:
AC OPERATING CHARACTERISTICS, 2.7-3.6V
33 MHz
80 MHz
Symbol
Parameter
Serial Clock Frequency
Serial Clock High Time
Min
Max
Min
Max
Units
MHz
ns
1
FCLK
33
80
TSCKH
TSCKL
TSCKR
TSCKF
13
13
0.1
0.1
5
6
6
Serial Clock Low Time
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
CE# Active Setup Time
CE# Active Hold Time
CE# Not Active Setup Time
CE# Not Active Hold Time
CE# High Time
ns
2
0.1
0.1
5
V/ns
V/ns
ns
3
TCES
3
TCEH
5
5
ns
3
TCHS
5
5
ns
3
TCHH
5
5
ns
TCPH
TCHZ
TCLZ
TDS
50
50
ns
CE# High to High-Z Output
SCK Low to Low-Z Output
Data In Setup Time
7
7
ns
0
2
4
5
5
5
5
0
2
4
5
5
5
5
ns
ns
TDH
Data In Hold Time
ns
THLS
THHS
THLH
THHH
THZ
HOLD# Low Setup Time
HOLD# High Setup Time
HOLD# Low Hold Time
HOLD# High Hold Time
HOLD# Low to High-Z Output
HOLD# High to Low-Z Output
Output Hold from SCK Change
Output Valid from SCK
Sector-Erase
ns
ns
ns
ns
7
7
7
7
ns
TLZ
ns
TOH
TV
0
0
ns
10
25
25
50
10
10
6
ns
TSE
25
25
50
10
10
ms
ms
ms
µs
TBE
Block-Erase
TSCE
TBP
Chip-Erase
Byte-Program
TPSID
Program Security ID
µs
1. Maximum clock frequency for Read Instruction, 03H, is 33 MHz
2. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements
3. Relative to SCK.
T
CPH
CE#
T
T
CES
T
T
CHS
CHH
T
SCKF
CEH
SCK
T
SCKR
T
T
DS
DH
MSB
LSB
SI
SO
HIGH-Z
HIGH-Z
25137 SerIn.0
FIGURE 5-1:
SERIAL INPUT TIMING DIAGRAM
2012 Microchip Technology Inc.
DS25134A-page 21
SST25PF080B
CE#
T
SCKL
T
SCKH
SCK
T
OH
T
T
CHZ
CLZ
SO
SI
MSB
LSB
T
V
25137 SerOut.0
FIGURE 5-2:
SERIAL OUTPUT TIMING DIAGRAM
CE#
SCK
T
T
T
HLS
HHS
HHH
T
HLH
T
HZ
T
LZ
SO
SI
HOLD#
25137 Hold.0
FIGURE 5-3:
HOLD TIMING DIAGRAM
DS25134A-page 22
2012 Microchip Technology Inc.
SST25PF080B
5.1
Power-Up Specifications
All functionalities and DC specifications are specified
for a VDD ramp rate of greater than 1V per 100 ms (0V
- 3.0V in less than 300 ms). See Table 5-8 and Figure
5-4 for more information.
TABLE 5-8:
RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
µs
1
TPU-READ
VDD Min to Read Operation
VDD Min to Write Operation
100
100
1
TPU-WRITE
µs
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
V
DD
V
Max
Min
DD
Chip selection is not allowed.
Commands may not be accepted or properly
interpreted by the device.
V
DD
TPU-READ
TPU-WRITE
Device fully accessible
Time
25137 PwrUp.0
FIGURE 5-4:
POWER-UP TIMING DIAGRAM
2012 Microchip Technology Inc.
DS25134A-page 23
SST25PF080B
V
IHT
V
V
HT
HT
INPUT
REFERENCE POINTS
OUTPUT
V
V
LT
LT
V
ILT
25137 IORef.0
AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measurement
reference points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and fall times (10%
↔ 90%) are <5 ns.
Note: VHT - VHIGH Test
V
LT - VLOW Test
VIHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
V
FIGURE 5-5:
AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
25137 TstLd.0
FIGURE 5-6:
A TEST LOAD EXAMPLE
DS25134A-page 24
2012 Microchip Technology Inc.
SST25PF080B
6.0
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
XX
XXX
X
Valid Combinations:
PART NO.
Device
XX
SST25PF080B-80-4C-QAE
SST25PF080B-80-4C-QAE-T
SST25PF080B-80-4C-SAE
SST25PF080B-80-4C-SAE-T
SST25PF080B-80-4C-S2AE
SST25PF080B-80-4C-S2AE-T
Operating
Frequency
Package
Tape/Reel
Indicator
Endurance/
Temperature
Device:
SST25PF080B
80
= 8 Mbit, 2.3-3.6V, Serial Peripheral Inter-
face flash memory
Operating
= 80 MHz
Frequency:
Endurance:
Temperature:
Package:
4
= 10,000 cycles
= 0°C to +70°C
C
QAE
SAE
S2AE
= WSON (6mm x 5mm Body), 8-contact
= SOIC (150 mil Body), 8-lead
= SOIC (200 mil Body), 8-lead
Tape and
T
= Tape and Reel
Reel Flag:
2012 Microchip Technology Inc.
DS25134A-page 25
SST25PF080B
7.0
PACKAGING DIAGRAMS
Pin #1
Identifier
SIDE VIEW
TOP VIEW
7°
4 places
0.51
0.33
5.0
4.8
1.27 BSC
END VIEW
45°
7°
4 places
0.25
0.10
4.00
3.80
1.75
1.35
0.25
0.19
0°
6.20
5.80
8°
1.27
0.40
Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
08-soic-5x6-SA-8
1mm
4. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
FIGURE 7-1:
8-LEAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) 150 MIL BODY WIDTH
PACKAGE CODE: SA
DS25134A-page 26
2012 Microchip Technology Inc.
SST25PF080B
Pin #1
Identifier
TOP VIEW
SIDE VIEW
0.50
0.35
5.40
5.15
1.27 BSC
0.25
0.05
END VIEW
5.40
5.15
2.16
1.75
8.10
7.70
0°
0.25
0.19
8°
0.80
0.50
Note: 1. All linear dimensions are in millimeters (max/min).
08-soic-EIAJ-S2A-3
2. Coplanarity: 0.1 mm
3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
1mm
FIGURE 7-2:
8-LEAD SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) 200 MIL BODY WIDTH
PACKAGE CODE: S2A
2012 Microchip Technology Inc.
DS25134A-page 27
SST25PF080B
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Pin #1
0.2
Pin #1
Corner
1.27 BSC
4.0
5.00 ± 0.10
0.076
0.48
0.35
3.4
0.70
0.50
0.05 Max
6.00 ± 0.10
0.80
0.70
CROSS SECTION
Note: 1. All linear dimensions are in millimeters (max/min).
2. Untoleranced dimensions (shown with box surround)
are nominal target dimensions.
0.80
0.70
3. The external paddle is electrically connected to the
1mm
die back-side and possibly to certain V
leads.
SS
This paddle can be soldered to the PC board;
it is suggested to connect this paddle to the V
8-wson-5x6-QA-9.0
of the unit.
SS
Connection of this paddle to any other voltage potential can
result in shorts and/or electrical malfunction of the device.
FIGURE 7-3:
8-CONTACT VERY-VERY-THIN SMALL OUTLINE NO-LEAD (WSON)
PACKAGE CODE: QA
DS25134A-page 28
2012 Microchip Technology Inc.
SST25PF080B
TABLE 7-1:
Revision
A
REVISION HISTORY
Description
Date
Dec 2012
•
Initial release of data sheet
2012 Microchip Technology Inc.
DS25134A-page 29
SST25PF080B
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
CUSTOMER SUPPORT
• General Technical Support – Frequently Asked
Questions (FAQs), technical support requests,
online discussion groups, Microchip consultant
program member listing
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
CUSTOMER CHANGE NOTIFICATION
SERVICE
DS25134A-page 30
2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2012, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-719-1
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2012 Microchip Technology Inc.
DS25134A-page 31
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
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Tel: 91-20-2566-1512
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Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
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Tel: 49-89-627-144-0
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Tel: 81-66-152-7160
Fax: 81-66-152-9310
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Chengdu
Tel: 86-28-8665-5511
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Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
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Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Korea - Seoul
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
UK - Wokingham
Tel: 44-118-921-5869
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Cleveland
China - Hong Kong SAR
Tel: 852-2401-1200
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Tel: 216-447-0464
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Tel: 63-2-634-9065
Fax: 63-2-634-9069
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Farmington Hills, MI
Tel: 248-538-2250
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Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
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Tel: 65-6334-8870
Fax: 65-6334-8850
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
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Tel: 86-24-2334-2829
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Taiwan - Hsin Chu
Tel: 886-3-5778-366
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Tel: 886-7-536-4818
Fax: 886-7-330-9305
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Tel: 949-462-9523
Fax: 949-462-9608
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
2012 Microchip Technology Inc.
DS25134A-page 32
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