SST39VF1682-70-4C-B3KE [MICROCHIP]
2M X 8 FLASH 2.7V PROM, 70 ns, PBGA48, 6 X 8 MM, 0.80 MM PITCH, LEAD FREE, MO-210AB-1, TFBGA-48;
| 型号： | SST39VF1682-70-4C-B3KE |
| 厂家： | 
MICROCHIP |
| 描述： | 2M X 8 FLASH 2.7V PROM, 70 ns, PBGA48, 6 X 8 MM, 0.80 MM PITCH, LEAD FREE, MO-210AB-1, TFBGA-48 可编程只读存储器 内存集成电路 |
| 文件： | 总34页 (文件大小：460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 Mbit (x8) Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
The SST39VF1681 / SST39VF1682 are 2M x8 CMOS Multi-Purpose Flash Plus
(MPF+) manufactured with SST proprietary, high performance CMOS Super-
Flash® technology. The split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared with alternate approaches.
The SST39VF1681 / SST39VF1682 write (Program or Erase) with a 2.7-3.6V
power supply. These devices conforms to JEDEC standard pinouts for x8 memo-
ries.
Features
• Organized as 2M x8
• Security-ID Feature
– SST: 128 bits; User: 128 bits
• Single Voltage Read and Write Operations
• Fast Read Access Time:
– 2.7-3.6V
– 70 ns
• Superior Reliability
• Latched Address and Data
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Fast Erase and Byte-Program:
• Low Power Consumption (typical values at 5 MHz)
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Byte-Program Time: 7 µs (typical)
– Active Current: 9 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• Hardware Block-Protection/WP# Input Pin
• Automatic Write Timing
– Top Block-Protection (top 64 KByte)
– Internal VPP Generation
for SST39VF1682
• End-of-Write Detection
– Bottom Block-Protection (bottom 64 KByte)
for SST39VF1681
– Toggle Bits
– Data# Polling
• Sector-Erase Capability
• CMOS I/O Compatibility
– Uniform 4 KByte sectors
• Block-Erase Capability
• JEDEC Standard
– Uniform 64 KByte blocks
– Flash EEPROM Pinouts and Command sets
• Chip-Erase Capability
• Packages Available
– 48-ball TFBGA (6mm x 8mm)
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
– 48-lead TSOP (12mm x 20mm)
• All devices are RoHS compliant
www.microchip.com
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Product Description
The SST39VF168x devices are 2M x8 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST’s
proprietary, high performance CMOS SuperFlash® technology. The split-gate cell design and thick-oxide
tunneling injector attain better reliability and manufacturability compared with alternate approaches. The
SST39VF168x write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC
standard pinouts for x8 memories.
Featuring high performance Byte-Program, the SST39VF168x devices provide a typical Byte-Program
time of 7 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program
operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protec-
tion schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices
are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater
than 100 years.
The SST39VF168x devices are suited for applications that require convenient and economical updat-
ing of program, configuration, or data memory. For all system applications, they significantly improve
performance and reliability, while lowering power consumption. They inherently use less energy during
Erase and Program than alternative flash technologies. The total energy consumed is a function of the
applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter erase time, the total energy consumed dur-
ing any Erase or Program operation is less than alternative flash technologies. These devices also
improve flexibility while lowering the cost for program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro-
gram times increase with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the SST39VF168x are offered in both 48-ball TFBGA
and 48-lead TSOP packages. See Figures 2 and 3 for pin assignments.
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
2
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Block Diagram
SuperFlash
Memory
X-Decoder
Memory Address
Address Buffer Latches
Y-Decoder
CE#
OE#
WE#
I/O Buffers and Data Latches
Control Logic
WP#
RESET#
DQ - DQ
7
0
1243 B1.0
Figure 1: SST39VF1681 / SST39VF1682 Block Diagram
Pin Description
TOP VIEW (balls facing down)
6
5
4
3
2
1
A14 A13 A15 A16 A17 NC
A10 A9 A11 A12 DQ7 NC
WE# RST# NC A20 DQ5 NC
NC WP# A19 NC DQ2 NC
A0
NC DQ6
DQ4
V
SS
V
DD
NC DQ3
NC DQ1
A8 A18 A7
A6 DQ0 NC
A4
A5
A3
A2
A1 CE# OE# V
SS
A
B
C
D
E F G H
Figure 2: Pin Assignments for 48-lead TFBGA
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
3
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
A17
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
A15
A14
A13
A12
A11
A10
A9
A20
NC
WE#
RST#
NC
WP#
NC
A19
A18
A8
A7
A6
A5
A4
V
A0
SS
DQ7
NC
DQ6
NC
DQ5
NC
DQ4
Standard Pinout
Top View
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
NC
DD
Die Up
DQ3
NC
DQ2
NC
DQ1
NC
DQ0
OE#
V
SS
CE#
A1
A3
A2
1243 48-tsop P2.0
Figure 3: Pin Assignments for 48-lead TSOP
Table 1: Pin Description
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses.
During Sector-Erase AMS-A12 address lines will select the sector.
During Block-Erase AMS-A16 address lines will select the block.
DQ7-DQ0
WP#
Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
Write Protect
To protect the top/bottom boot block from Erase/Program operation when
grounded.
RST#
CE#
OE#
WE#
VDD
Reset
To reset and return the device to Read mode.
To activate the device when CE# is low.
To gate the data output buffers.
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
To control the Write operations.
To provide power supply voltage: 2.7-3.6V
VSS
NC
No Connection
Unconnected pins.
T1.1 25040
1. AMS = Most significant address
AMS = A20 for SST39VF1681/1682
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
4
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
The SST39VF168x also have the Auto Low Power mode which puts the device in a near standby
mode after data has been accessed with a valid Read operation. This reduces the IDD active read cur-
rent from typically 9 mA to typically 3 µA. The Auto Low Power mode reduces the typical IDD active
read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode
with any address transition or control signal transition used to initiate another Read cycle, with no
access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with
CE# held steadily low, until the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF168x is controlled by CE# and OE#, both have to be low for the system
to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected
and only standby power is consumed. OE# is the output control and is used to gate data from the output
pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle tim-
ing diagram for further details (Figure 4).
Byte-Program Operation
The SST39VF168x are programmed on a byte-by-byte basis. Before programming, the sector where
the byte exists must be fully erased. The Program operation is accomplished in three steps. The first
step is the three-byte load sequence for Software Data Protection. The second step is to load byte
address and byte data. During the Byte-Program operation, the addresses are latched on the falling
edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE#
or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after
the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initi-
ated, will be completed within 10 µs. See Figures 5 and 6 for WE# and CE# controlled Program opera-
tion timing diagrams and Figure 20 for flowcharts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform
additional tasks. Any commands issued during the internal Program operation are ignored. During the
command sequence, WP# should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The SST39VF168x offer both Sector-Erase and Block-Erase mode. The sector
architecture is based on uniform sector size of 4 KByte. The Block-Erase mode is based on uniform
block size of 64 KByte. The Sector-Erase operation is initiated by executing a six-byte command
sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The Block-
Erase operation is initiated by executing a six-byte command sequence with Block-Erase command
(30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling
edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth
WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase opera-
tion can be determined using either Data# Polling or Toggle Bit methods. See Figures 10 and 11 for
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
5
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
timing waveforms and Figure 24 for the flowchart. Any commands issued during the Sector- or Block-
Erase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the protected
block will be ignored. During the command sequence, WP# should be statically held high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing
data to be read from any memory location, or program data into any sector/block that is not suspended
for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-
Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the
Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address location within erase-suspended sectors/
blocks will output DQ2 toggling and DQ6 at “1”. While in Erase-Suspend mode, a Byte-Program opera-
tion is allowed except for the sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase
Resume command. The operation is executed by issuing one byte command sequence with Erase Resume com-
mand (30H) at any address in the last Byte sequence.
Chip-Erase Operation
The SST39VF168x provide a Chip-Erase operation, which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase command
(10H) at address AAAH in the last byte sequence. The Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Poll-
ing. See Table 6 for the command sequence, Figure 10 for timing diagram, and Figure 24 for the flowchart.
Any commands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-
Erase will be ignored. During the command sequence, WP# should be statically held high or low.
Write Operation Status Detection
The SST39VF168x provide two software means to detect the completion of a Write (Program or
Erase) cycle, in order to optimize the system write cycle time. The software detection includes two sta-
tus bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after
the rising edge of WE#, which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the sys-
tem may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In
order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop
to read the accessed location an additional two (2) times. If both reads are valid, then the device has com-
pleted the Write cycle, otherwise the rejection is valid.
Data# Polling (DQ7)
When the SST39VF168x are in the internal Program operation, any attempt to read DQ7 will produce the
complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that
even though DQ7 may have valid data immediately following the completion of an internal Write operation, the
remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent succes-
sive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will pro-
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
6
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
duce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid
after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase,
the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling tim-
ing diagram and Figure 21 for a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce
alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation
is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector-
, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ6 will be set to “1” if a Read operation is attempted on an Erase-Suspended Sector/Block. If Pro-
gram operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle.
An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check
whether a particular sector is being actively erased or erase-suspended. Table 2 shows detailed status
bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of
Write operation. See Figure 8 for Toggle Bit timing diagram and Figure 21 for a flowchart.
Table 2: Write Operation Status
Status
DQ7
DQ7#
0
DQ6
Toggle
Toggle
1
DQ2
No Toggle
Toggle
Toggle
Data
Normal Operation
Standard Program
Standard Erase
Erase-Suspend Mode
Read from Erase Suspended Sector/Block
Read from Non- Erase Suspended Sector/Block
Program
1
Data
DQ7#
Data
Toggle
N/A
T2.0 25040
Note: DQ7 and DQ2 require a valid address when reading status information.
Data Protection
The SST39VF168x provide both hardware and software features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-
vents inadvertent writes during power-up or power-down.
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
7
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Hardware Block Protection
The SST39VF1682 supports top hardware block protection, which protects the top 64 KByte block of
the device. The SST39VF1681 supports bottom hardware block protection, which protects the bottom
64 KByte block of the device. The Boot Block address ranges are described in Table 3. Program and
Erase operations are prevented on the 64 KByte when WP# is low. If WP# is left floating, it is internally
held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase opera-
tions on that block.
Table 3: Boot Block Address Ranges
Product
Address Range
000000H-00FFFFH
1F0000H-1FFFFFH
Bottom Boot Block
SST39VF1681
Top Boot Block
SST39VF1682
T3.1 25040
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the device to read array data. When the RST#
pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When
no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST#
is driven high before a valid Read can take place (see Figure 16).
The Erase or Program operation that has been interrupted needs to be re-initiated after the device
resumes normal operation mode to ensure data integrity.
Software Data Protection (SDP)
The SST39VF168x provide the JEDEC approved Software Data Protection scheme for all data altera-
tion operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-
byte sequence. The three-byte load sequence is used to initiate the Program operation, providing opti-
mal protection from inadvertent Write operations, e.g., during the system power-up or power-down.
Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the
Software Data Protection permanently enabled. See Table 6 for the specific software command codes.
During SDP command sequence, invalid commands will abort the device to Read mode within TRC.
Common Flash Memory Interface (CFI)
The SST39VF168x also contain the CFI information to describe the characteristics of the device. In order to
enter the CFI Query mode, the system must write three-byte sequence, same as product ID entry command
with 98H (CFI Query command) to address AAAH in the last byte sequence. Once the device enters the CFI
Query mode, the system can read CFI data at the addresses given in Tables 7 through 9. The system must write
the CFI Exit command to return to Read mode from the CFI Query mode.
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
8
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Product Identification
The Product Identification mode identifies the devices as the SST39VF1681 and SST39VF1682, and manu-
facturer as SST. Users may use the software Product Identification operation to identify the part (i.e., using
the device ID) when using multiple manufacturers in the same socket. For details, see Table 6 for software
operation, Figure 12 for the software ID Entry and Read timing diagram, and Figure 22 for the software ID
Entry command sequence flowchart.
Table 4: Product Identification
Address
Data
Manufacturer’s ID
Device ID
0000H
BFH
SST39VF1681
SST39VF1682
0001H
0001H
C8H
C9H
T4.1 25040
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited.
Exit is accomplished by issuing the software ID Exit command sequence, which returns the device to
the Read mode. This command may also be used to reset the device to the Read mode after any inad-
vertent transient condition that apparently causes the device to behave abnormally, e.g., not read cor-
rectly. Please note that the software ID Exit/CFI Exit command is ignored during an internal Program or
Erase operation. See Table 6 for software command codes, Figure 14 for timing waveform, and Figures
22 and 23 for flowcharts.
Security ID
The SST39VF168x devices offer a 256-bit Security ID space which is divided into two 128-bit seg-
ments. The first segment is programmed and locked at SST with a random 128-bit number. The user
segment is left un-programmed for the customer to program as desired.
To program the user segment of the Security ID, the user must use the Security ID Byte-Program com-
mand. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this
is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any
future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec
ID segment can be erased.
The Security ID space can be queried by executing a three-byte command sequence with Enter-Sec-
ID command (88H) at address AAAH in the last byte sequence. Execute the Exit-Sec-ID command to
exit this mode. Refer to Table 6 for more details.
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
9
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Operations
Table 5: Operation Modes Selection
Mode
CE#
VIL
OE#
VIL
WE# DQ
Address
AIN
Read
VIH
VIL
VIL
DOUT
Program
Erase
VIL
VIH
VIH
DIN
X1
AIN
VIL
Sector or block address,
XXH for Chip-Erase
Standby
VIH
X
X
VIL
X
X
X
High Z
X
X
X
Write Inhibit
High Z/ DOUT
High Z/ DOUT
X
VIH
Product Identification
Software Mode
VIL
VIL
VIH
See Table 6
T5.0 25040
1. X can be VIL or VIH, but no other value.
Table 6: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
3rd Bus
4th Bus
5th Bus
Write Cycle Write Cycle
6th Bus
Write Cycle Write Cycle Write Cycle
Addr1 Data Addr1 Data Addr1 Data Addr1 Data Addr1 Data Addr1 Data
AAAH AAH 555H 55H AAAH A0H Data
BA2
Byte-Program
Sector-Erase
Block-Erase
3
AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SAX
AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H BAX
50H
30H
3
Chip-Erase
AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H
Erase-Suspend
Erase-Resume
Query Sec ID4
XXXXH B0H
XXXXH 30H
AAAH AAH 555H 55H AAAH 88H
BA5
Data
User Security ID
Byte-Program
AAAH AAH 555H 55H AAAH A5H
AAAH AAH 555H 55H AAAH 85H XXH5 00H
AAAH AAH 555H 55H AAAH 90H
User Security ID
Program Lock-Out
Software ID
Entry6,7
CFI Query Entry
AAAH AAH 555H 55H AAAH 98H
AAAH AAH 555H 55H AAAH F0H
Software ID Exit8,9
/CFI Exit/Sec ID
Exit
Software ID Exit8,9
/CFI Exit/Sec ID
Exit
XXH
F0H
T6.1 25040
1. Address format A11-A0 (Hex).
Addresses A20-A12 can be VIL or VIH, but no other value, for Command sequence for SST39VF1681/1682.
2. BA = Program Byte Address
3. SAX for Sector-Erase; uses AMS-A12 address lines
BAX, for Block-Erase; uses AMS-A16 address lines
AMS = Most significant address
AMS = A20 for SST39VF1681/1682
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
10
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
4. With AMS-A5 = 0; Sec ID is read with A4-A0,
SST ID is read with A4 = 0 (Address range = 00000H to 0000FH),
User ID is read with A4 = 1 (Address range = 00010H to 0001FH).
Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
5. Valid Byte Addresses for Sec ID are from 000000H-00000FH and 000020H-00002FH.
6. The device does not remain in Software Product ID Mode if powered down.
7. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0,
SST39VF1681 Device ID = C8H, is read with A0 = 1,
SST39VF1682 Device ID = C9H, is read with A0 = 1,
A
MS = Most significant address
AMS = A20 for SST39VF1681/1682
8. Both Software ID Exit operations are equivalent
9. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1)
using the Sec ID mode again (the programmed “0” bits cannot be reversed to “1”).
Table 7: CFI Query Identification String1
Address
10H
11H
12H
13H
14H
15H
16H
17H
Data
51H
52H
59H
01H
07H
00H
00H
00H
00H
00H
00H
Data
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
18H
19H
1AH
T7.1 25040
1. Refer to CFI publication 100 for more details.
Table 8: System Interface Information
Address
Data
Data
1BH
27H
VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH
36H
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
00H
00H
03H
00H
04H
05H
01H
00H
01H
01H
VPP min. (00H = no VPP pin)
VPP max. (00H = no VPP pin)
Typical time out for Byte-Program 2N µs (23 = 8 µs)
Typical time out for min. size buffer program 2N µs (00H = not supported)
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
Typical time out for Chip-Erase 2N ms (25 = 32 ms)
Maximum time out for Byte-Program 2N times typical (21 x 23 = 16 µs)
Maximum time out for buffer program 2N times typical
Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms)
T8.1 25040
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
11
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Table 9: Device Geometry Information
Address
Data
15H
00H
00H
00H
00H
02H
FFH
01H
10H
00H
1FH
00H
00H
01H
Data
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
Flash Device Interface description; 00H = x8-only asynchronous interface
Maximum number of byte in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 511 + 1 = 512 sectors (01FF = 511
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 31 + 1 = 32 blocks (1F = 31)
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T9.1 25040
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
12
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating con-
ditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
Table 10:Operating Range
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
2.7-3.6V
2.7-3.6V
-40°C to +85°C
T10.1 25040
Table 11:AC Conditions of Test1
Input Rise/Fall Time
Output Load
5ns
CL = 30 pF
T11.1 25040
1. See Figures 18 and 19
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
13
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Table 12:DC Operating Characteristics VDD = 2.7-3.6V1
Limits
Max
Symbol Parameter
Min
Units
Test Conditions
IDD
Power Supply Current
Address input=VILT/VIHT2, at f=5 MHz,
VDD=VDD Max
Read3
18
mA
CE#=VIL, OE#=WE#=VIH, all I/Os
open
Program and Erase
Standby VDD Current
Auto Low Power
35
20
20
mA
µA
µA
CE#=WE#=VIL, OE#=VIH
CE#=VIHC, VDD=VDD Max
ISB
IALP
CE#=VILC, VDD=VDD Max
All inputs=VSS or VDD, WE#=VIHC
ILI
Input Leakage Current
1
µA
µA
VIN=GND to VDD, VDD=VDD Max
ILIW
Input Leakage Current
on WP# pin and RST#
10
WP#=GND to VDD or RST#=GND to
VDD
ILO
Output Leakage Current
Input Low Voltage
10
0.8
0.3
µA
V
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
VIL
VILC
VIH
Input Low Voltage (CMOS)
Input High Voltage
V
VDD=VDD Max
0.7VDD
V
VDD=VDD Max
VIHC
VOL
VOH
Input High Voltage (CMOS)
Output Low Voltage
VDD-0.3
V
VDD=VDD Max
0.2
V
IOL=100 µA, VDD=VDD Min
Output High Voltage
VDD-0.2
V
IOH=-100 µA, VDD=VDD Min
T12.8 25040
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 3V. Not 100% tested.
2. See Figure 18
3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.
Table 13:Recommended System Power-up Timings
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Program/Erase Operation
1
TPU-WRITE
100
µs
T13.0 25040
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 14:Capacitance (Ta = 25°C, f=1 MHz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
12 pF
1
CI/O
I/O Pin Capacitance
Input Capacitance
1
CIN
VIN = 0V
6 pF
T14.0 25040
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
14
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Table 15:Reliability Characteristics
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Cycles
Years
mA
Test Method
1,2
NEND
10,000
100
JEDEC Standard A117
JEDEC Standard A103
1
TDR
1
ILTH
100 + IDD
JEDEC Standard 78
T15.2 25040
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would
result in a higher minimum specification.
AC Characteristics
Table 16:Read Cycle Timing Parameters VDD = 2.7-3.6V
SST39VF168x-70
Symbol
TRC
Parameter
Min
Max
Units
ns
Read Cycle Time
70
TCE
Chip Enable Access Time
Address Access Time
70
70
35
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
RST# Pulse Width
ns
1
TCLZ
0
0
ns
1
TOLZ
ns
1
TCHZ
20
20
ns
1
TOHZ
ns
1
TOH
0
ns
1
TRP
500
50
ns
1
TRHR
RST# High before Read
RST# Pin Low to Read Mode
ns
1,2
TRY
20
µs
T16.1 25040
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
15
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Table 17:Program/Erase Cycle Timing Parameters
Symbol Parameter
Min
Max
Units
µs
TBP
Byte-Program Time
10
TAS
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
0
30
0
ns
TAH
ns
TCS
ns
TCH
TOES
TOEH
TCP
0
ns
0
ns
10
40
40
30
30
30
0
ns
ns
TWP
TWPH
WE# Pulse Width
ns
1
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
ns
1
TCPH
TDS
ns
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
ns
TSE
25
25
50
ms
ms
TBE
Block-Erase
TSCE
Chip-Erase
ms
T17.0 25040
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
16
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
T
T
AA
RC
ADDRESS A
MS-0
T
CE
CE#
T
OE
OE#
WE#
T
T
OHZ
OLZ
V
IH
T
T
CHZ
OH
T
CLZ
HIGH-Z
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
1243 F02.0
Note: AMS = Most Significant Address
AMS = A20 for SST39VF168x
Figure 4: Read Cycle Timing Diagram
INTERNAL PROGRAM OPERATION STARTS
T
BP
AAA
555
AAA
ADDR
ADDRESS A
MS-0
WE#
T
AH
T
DH
T
WP
T
T
AS
DS
T
WPH
OE#
CE#
T
CH
T
CS
DQ
7-0
AA
SW0
55
A0
DATA
BYTE
SW1
SW2
1243 F03.2
(ADDR/DATA)
Note: AMS = Most Significant Address
AMS = A20 for SST39VF168x
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 5: WE# Controlled Program Cycle Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
17
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
T
BP
AAA
555
AAA
ADDR
ADDRESS A
MS-0
CE#
T
AH
T
DH
T
CP
T
T
AS
DS
T
CPH
OE#
WE#
T
CH
T
CS
DQ
7-0
AA
SW0
55
A0
DATA
SW1
SW2
BYTE
1243 F04.2
(ADDR/DATA)
Note: AMS = Most Significant Address
AMS = A20 for SST39VF168x
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 6: CE# Controlled Program Cycle Timing Diagram
ADDRESS A
MS-0
CE#
OE#
T
CE
T
T
OES
OEH
T
OE
WE#
DQ
DATA
DATA#
DATA#
DATA
7
1243 F05.1
Note: AMS = Most Significant Address
AMS = A20 for SST39VF168x
Figure 7: Data# Polling Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
18
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
ADDRESS A
MS-0
T
CE
CE#
T
T
OES
OEH
T
OE
OE#
WE#
DQ and DQ
6
2
TWO READ CYCLES
WITH SAME OUTPUTS
1243 F06.1
Note: AMS = Most Significant Address
AMS = A20 for SST39VF168x
Figure 8: Toggle Bits Timing Diagram
T
SIX-BYTE CODE FOR CHIP-ERASE
AAA AAA 555
SCE
AAA
555
AAA
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
AA
55
SW1
80
SW2
AA
SW3
55
SW4
10
SW5
DQ
7-0
SW0
1243 F07.1
Note: This device also supports CE# controlled Chip-Erase operation.
The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 17.)
AMS = Most Significant Address
A
MS = A20 for SST39VF168x
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 9: WE# Controlled Chip-Erase Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
19
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
T
SIX-BYTE CODE FOR BLOCK-ERASE
AAA AAA 555
BE
AAA
555
BA
X
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
AA
SW0
55
SW1
80
SW2
AA
SW3
55
SW4
30
SW5
DQ
7-0
1243 F08.1
Note: This device also supports CE# controlled Chip-Erase operation.
The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 17.)
BAX = Block Address
AMS = Most Significant Address
AMS = A20 for SST39VF168x
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 10:WE# Controlled Block-Erase Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
20
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
T
SIX-BYTE CODE FOR SECTOR-ERASE
AAA AAA 555
SE
AAA
555
SA
X
ADDRESS A
MS-0
CE#
OE#
WE#
T
WP
DQ
7-0
AA
55
SW1
80
SW2
AA
SW3
55
SW4
50
SW5
SW0
1243 F9.1
Note: This device also supports CE# controlled Chip-Erase operation.
The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 17.)
SAX = Sector Address
AMS = Most Significant Address
AMS = A20 for SST39VF168x
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 11:WE# Controlled Sector-Erase Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
21
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
AAA
555
AAA
0000
0001
MS-0
CE#
OE#
T
T
IDA
WP
WE#
T
WPH
T
AA
BF
DQ
7-0
AA
55
SW1
90
Device ID
SW0
SW2
1243 F10.1
Note: Device ID - See Table 4 on page 9
AMS = Most Significant Address
AMS = A20 for SST39VF168x
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 12:Software ID Entry and Read
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS A
AAA
555
AAA
MS-0
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
T
AA
AA
SW0
55
98
DQ
7-0
SW1
SW2
1243 F11.2
Note: AMS = Most Significant Address
AMS = A20 for SST39VF168x
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 13:CFI Query Entry and Read
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
22
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
ADDRESS A
MS-0
AAA
555
AAA
DQ
AA
55
F0
7-0
T
IDA
CE#
OE#
WE#
T
WP
T
WHP
1243 F12.2
SW0
SW1
SW2
Note: AMS = Most Significant Address
AMS = A20 for SST39VF168x
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 14:Software ID Exit/CFI Exit
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS A
AAA
555
AAA
MS-0
CE#
OE#
T
IDA
T
WP
WE#
T
WPH
T
AA
AA
SW0
55
88
DQ
7-0
SW1
SW2
1243 F13.1
Note: AMS = Most Significant Address
AMS = A20 for SST39VF168x
WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.
X can be VIL or VIH, but no other value.
Figure 15:Sec ID Entry
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
23
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
T
RP
RST#
CE#/OE#
T
RHR
1243 F14.0
Figure 16:RST# Timing Diagram (When no internal operation is in progress)
T
RP
RST#
T
RY
CE#/OE#
End-of-Write Detection
(Toggle-Bit)
1243 F15.0
Figure 17:RST# Timing Diagram (During Program or Erase operation)
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
24
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
1243 F16.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Mea-
surement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input
rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
Figure 18:AC Input/Output Reference Waveforms
TO TESTER
TO DUT
CL
1243 F17.0
Figure 19:A Test Load Example
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
25
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Start
Load data: AAH
Address: AAAH
Load data: 55H
Address: 555H
Load data: A0H
Address: AAAH
Load Word
Address/Word
Data
Wait for end of
Program (T
Data# Polling
,
BP
bit, or Toggle bit
operation)
Program
Completed
1243 F18.0
X can be V or V , but no other value
IL IH
Figure 20:Byte-Program Algorithm
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
26
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read DQ
7
Read word
Wait T
,
BP
T
T
SCE, SE
or T
BE
Read same
word
Is DQ =
7
No
true data
Program/Erase
Completed
Yes
No
Does DQ
match
Program/Erase
Completed
6
Yes
Program/Erase
Completed
1243 F19.0
Figure 21:Wait Options
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
27
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
CFI Query Entry
Command Sequence
Sec ID Query Entry
Command Sequence
Software Product ID Entry
Command Sequence
Load data: AAH
Address: AAAH
Load data: AAH
Address: AAAH
Load data: AAH
Address: AAAH
Load data: 55H
Address: 555H
Load data: 55H
Address: 555H
Load data: 55H
Address: 555H
Load data: 98H
Address: AAAH
Load data: 88H
Address: AAAH
Load data: 90H
Address: 5555H
Wait T
Wait T
Wait T
IDA
IDA
IDA
Read CFI data
Read Sec ID
Read Software ID
X can be V or V , but no other value
IL IH
1243 F20.0
Figure 22:Software ID/CFI Entry Command Flowcharts
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
28
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Software ID Exit/CFI Exit/Sec ID Exit
Command Sequence
Load data: AAH
Address: AAAH
Load data: F0H
Address: XXH
Load data: 55H
Address: 555H
Wait T
IDA
Load data: F0H
Address: AAAH
Return to normal
operation
Wait T
IDA
Return to normal
operation
X can be V or V but no other value
IL
IH,
1243 F21.0
Figure 23:Software ID/CFI Exit Command Flowcharts
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
29
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: AAH
Address: AAAH
Load data: AAH
Address: AAAH
Load data: AAH
Address: AAAH
Load data: 55H
Address: 555H
Load data: 55H
Address: 555H
Load data: 55H
Address: 555H
Load data: 80H
Address: AAAH
Load data: 80H
Address: AAAH
Load data: 80H
Address: AAAH
Load data: AAH
Address: AAAH
Load data: AAH
Address: AAAH
Load data: AAH
Address: AAAH
Load data: 55H
Address: 555H
Load data: 55H
Address: 555H
Load data: 55H
Address: 555H
Load data: 10H
Address: AAAH
Load data: 50H
Load data: 30H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
1243 F22.0
X can be V or V , but no other value
IL IH
Figure 24:Erase Command Sequence
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
30
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Product Ordering Information
SST 39 VF 1681
-
70
-
4C
-
B3KE
-
XX XX XXXX
-
XX
-
XX
XXXX
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 leads
Package Type
B3 = TFBGA (6mm x 8mm, 0.8mm pitch)
E = TSOP (type1, die up, 12mm x 20mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Hardware Block Protection
1 = Bottom Boot-Block
2 = Top Boot-Block
Device Density
168 = 16 Mbit
Voltage
V = 2.7-3.6V
Product Series
39 = Multi-Purpose Flash
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
Valid Combinations for SST39VF1681
SST39VF1681-70-4C-EKE
SST39VF1681-70-4C-B3KE
SST39VF1681-70-4I-EKE
SST39VF1681-70-4I-B3KE
Valid Combinations for SST39VF1682
SST39VF1682-70-4C-EKE
SST39VF1682-70-4C-B3KE
SST39VF1682-70-4I-EKE
SST39VF1682-70-4I-B3KE
Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
31
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Packaging Diagrams
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
12.20
11.80
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0°- 5°
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
1mm
48-tsop-EK-8
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
Figure 25:48-lead Thin Small Outline Package (TSOP) 12mm x 20mm
SST Package Code: EK
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
32
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
TOP VIEW
8.00 0.10
BOTTOM VIEW
5.60
0.45 0.05
0.80
(48X)
6
5
6
5
4
3
2
1
4.00
4
3
6.00 0.10
2
1
0.80
A
B C D E F G H
H
G F E D C B A
A1 CORNER
A1 CORNER
1.10 0.10
SIDE VIEW
0.12
SEATING PLANE
1mm
0.35 0.05
Note:
1. Complies with JEDEC Publication 95, MO-210, variant AB-1 , although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm ( 0.05 mm)
48-tfbga-B3K-6x8-450mic-5
Figure 26:48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm
SST Package Code: B3K
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
33
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
A Microchip Technology Company
Data Sheet
Table 18:Revision History
Number
00
Description
Date
May 2003
Sep 2003
Oct 2003
•
•
•
•
•
•
•
•
Initial release
01
Change product number from 166x to 168x
Added B3K package and associated MPNs (See page 31)
Removed 90 ns Commercial temperature for the EK and EKE packages
2004 Data Book
02
03
A
Nov 2003
May 2011
Updated B3K package diagram
Updated document status to “Data Sheet.”
Removed all 90ns information. Edited “Features” on page 1, “Product
Ordering Information” on page 31, and Table 16 on page 15.
•
•
•
•
Updated TIDA information in Table 17 on page 16
Applied new document format
Released document under the letter revision system
Updated spec number from S71243 to DS25040
ISBN:978-1-61341-202-2
© 2011 Silicon Storage Technology, Inc–a Microchip Technology Company. All rights reserved.
SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Tech-
nology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and
registered trademarks mentioned herein are the property of their respective owners.
Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current
package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.
Memory sizes denote raw storage capacity; actual usable capacity may be less.
SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of
Sale.
For sales office(s) location and information, please see www.microchip.com.
Silicon Storage Technology, Inc.
A Microchip Technology Company
www.microchip.com
©2011 Silicon Storage Technology, Inc.
DS25040A
05/11
34
相关型号：
SST39VF1682-70-4I-EKE
2M X 8 FLASH 2.7V PROM, 70 ns, PDSO48, 12 X 20 MM, LEAD FREE, MO-142DD, TSOP1-48
MICROCHIP
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