SY88083LMG [MICROCHIP]
ATM/SONET/SDH SUPPORT CIRCUIT, QCC16;
| 型号： | SY88083LMG |
| 厂家： | 
MICROCHIP |
| 描述： | ATM/SONET/SDH SUPPORT CIRCUIT, QCC16 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总15页 (文件大小：932K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SY88083L
1G to 12.5G Limiting Post Amplifier with
Digital Offset Correction
Revision 1.0
Features
General Description
• Multi-rate operation from 1.0625Gbps to 12.5Gbps
The SY88083L limiting post amplifier is designed for use in
fiber-optic receivers for continuous mode, multi-rate
applications from 1Gbps to 12.5Gbps.
• Selectable digital offset correction for internal offset
compensation in the high-speed data path
• Wide differential input range (10mVPP to 1800mVPP)
• Wide SD de-assert or LOS assert threshold range
− 4.5mVPP to 30mVPP
− 4dB typical electrical hysteresis
• Fast SD assert and LOS de-assert times
− 1µs typical; 2µs maximum
The SY88083L contains a high-bandwidth, high-sensitivity
input stage with user-programmable, wide-range SD
assert/LOS de-assert threshold levels, which enables
optimized system reach. Typically, 4dB of electrical
hysteresis is provided to minimize LOS or SD chattering
caused by noisy input signals. A logic level control pin is
provided to enable user selection of an open-collector,
TTL-compatible LOS or SD status indication signal with an
external 5kΩ to 10kΩ pull-up resistor.
• Selectable LOS or SD status signal indicator
• TTL-compatible JAM input with internal pull-up
• Low-noise CML data inputs with integrated 50Ω
The SY88083L provides faster SD assert and LOS de-
assert times than typical continuous mode devices over
the entire differential input voltage range of 10mVPP to
1800mVPP.
termination impedance to internal reference VREF
• Low-noise CML data outputs with integrated 50Ω
termination impedance
− 30ps typical rise/fall times
The SY88083L input stage also provides a user-selectable
digital offset correction (DOC) function to automatically
compensate for internal device offsets in the high-speed
data path.
• Wide range power supply: 3.3V ±10%
• Industrial temperature range: −40°C to +85°C
• Available in a tiny 3mm × 3mm QFN package
The SY88083L provides integrated 50Ω input and output
impedances to optimize the high-speed signal paths and
reduce component count. A TTL-compatible JAM input is
provided to enable a SQUELCH function by feeding back
the LOS or SD signal. The JAM input disables only the
post amplifier output.
Applications
• 10G/8G Fibre Channel
• 10Gigabit Ethernet
• OTN equipment
• SONET OC192; SDH STM64
• WDM/DWDM systems
The SY88083L operates from a single +3.3V power
supply, over temperatures ranging from –40°C to +85°C.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Markets
• Fibre Channel storage area networks
• Datacom/Enterprise
• High-performance computing
• Telecom
• Wireless base stations
.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
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SY88083L
Typical Application Circuit
Ordering Information
Part Number
Package Type
Operating Range
Industrial
Package Marking
Lead Finish
SY88083LMG
SY88083LMG TR(1)
3mm × 3mm QFN-16
3mm × 3mm QFN-16
083L with Pb-Free bar-line indicator
083L with Pb-Free bar-line indicator
NiPdAu Pb-Free
NiPdAu Pb-Free
Industrial
Note:
1. Tape and reel.
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SY88083L
Pin Configuration
16-Pin 3mm × 3mm QFN
(Top View)
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SY88083L
Pin Description
Pin Number
Pin Name
Pin Type
Pin Function
Negative Supply Negative Supply Rail. Connect to the PCB negative power supply plane that is
1
GND
Rail
also connected to the ePad.
Differential Noninverting Data Input. LVPECL/CML compatible. AC-coupled
with 100nF (high-frequency, low-ESR capacitor is recommended).
High-Speed
Data Input
2
RXIN+
Internally terminated with 50Ω to VCC – 0.9V. AC-coupled only.
Differential Inverting Data Input. LVPECL/CML-compatible. AC-coupled with
100nF (high-frequency, low-ESR capacitor is recommended).
High-Speed
Data Input
3
4
RXIN−
Internally terminated by 50Ω to VCC – 0.9V. AC-coupled only.
Negative Supply Negative Supply Rail. Connect to the PCB negative power supply plane that is
GND
Rail
also connected to the ePad.
5
6
NC
NC
No Connect
No Connect
No Connect. Do not connect to logic circuits or power supply rails.
No Connect. Do not connect to logic circuits or power supply rails.
Output Status Indicator. Loss-of-signal (LOS) or signal detect (SD) open
collector output externally terminated with 5kΩ to 10kΩ resistor to VCC. TTL
compatible.
Open Collector
Logic Output
LOS = High when RXIN± amplitude falls below the threshold set at the
SD/LOSLVL pin.
7
8
SD/LOS
SD = Low when RXIN± amplitude falls below the threshold set at the
SD/LOSLVL pin.
Analog control input. Sets the trigger threshold for the LOS or SD status
indicator signals.
If SD/LOS_SEL = High (LOS selected), connect a resistor from the
SD/LOSLVL pin (loss of signal threshold level) to VCC to adjust the
LOS_Assert threshold for the RXIN± data inputs.
SD/LOSLVL
Analog Input
If SD/LOS_SEL = Low (SD selected), connect a resistor from the SD/LOSLVL
pin (signal detect threshold level) to VCC to adjust the SD_De-assert threshold
for the RXIN± data inputs.
Positive Supply Positive power supply input. Bypass with a 0.1µF capacitor in parallel with a
9, 12
10
VCC
Rail
0.01µF low-ESR capacitor to GND as close as possible to the VCC pin.
High-Speed
Data Output
Differential inverting data output. CML compatible and internally terminated by
50Ω to VCC. Can be AC- or DC-coupled to downstream devices.
RXOUT−
RXOUT+
TEST
High-Speed
Data Output
Differential noninverting data output. CML compatible and internally
terminated by 50Ω to VCC. Can be AC- or DC-coupled to downstream devices.
11
Factory test pin. For factory use only. Do not connect to logic circuits or power
supply rails.
13
Test Pin
Input control signal. TTL-compatible logic input signal to select LOS or SD as
the output signal. Internal ~18kΩ pull-up to VCC
.
Logic Level
Input
14
15
SD/LOS_SEL
Default = High (NC): LOS selected – normal operation
LOS/SD_SEL = Low: SD selected and JAM operation is inverted
Input control signal. TTL-compatible input signal that enables or disables the
RXOUT± output signals. Internal 27kΩ pull-up resistor to VCC. Can be
connected to SD/LOS to form a SQUELCH function.
Logic Level
Input
When SD/LOS_SEL = High
JAM
Default = High and RXOUT± outputs are disabled.
Low = RXOUT± outputs are enabled
Operation is inverted when SD/LOS_SEL = Low and SD is selected.
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Pin Description (Continued)
Pin Number
Pin Name
Pin Type
Pin Function
Input Control Signal. TTL-compatible logic input signal that enables or
disables the digital offset correction (DOC) circuit.
Default:
DOC_EN = High = Enable with internal 18kΩ pull-up to VCC if not connected to
an external logic low or high signal.
Logic Level
Input
16
DOC_EN
DOC_EN = Low disables the digital offset correction function.
Toggling the DOC_EN signal from high to low to high will cause a reset of the
DOC circuitry and initiate a new DOC routine to lock in new DOC values.
Note: Digital offset correction is not applied to large input signals.
Exposed Thermal Pad. Must be soldered to PCB plane connected to the
negative supply rail. The recommended via array is needed to remove heat
from the device.
Negative Supply
Rail
ePad
GND
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SY88083L
Absolute Maximum Ratings(2)
Operating Ratings(3)
Supply Voltage (VCC)......................................... 0V to +4.0V
Input Voltage (RXIN±) .............................. VCC – 1.5V to VCC
CML Output Voltage (VOUT)……....VCC − 1.0V to VCC + 0.5V
JAM Voltage ........................................................... 0 to VCC
SD/LOSLVL Voltage ................................ VCC – 1.3V to VCC
Lead Temperature (soldering, 20s)............................ 260°C
Storage Temperature (Ts) .........................–65°C to +150°C
Supply Voltage (VCC).................................... +3.0V to +3.6V
Ambient Temperature (TA)..........................–40°C to +85°C
Junction Temperature (TJ) ........................–40°C to +120°C
Package Thermal Resistance(4)
QFN (θJA) Still-Air...............................................60°C/W
QFN (ψJB)...........................................................33°C/W
DC Electrical Characteristics
VCC = 3.0 to 3.6V; TA = –40°C to +85°C, typical values at VCC = 3.3V, TA = 25°C.
Symbol
ICC
Parameter
Condition
Min.
Typ.
Max.
75
Units
mA
V
Power Supply Current
SD or LOS Threshold Voltage
Note 5
60
SD/LOSLVL
VCC
VCC − 1.3
RXOUT±
High Voltage
VOH
VCC
V
VCC − 0.020 VCC − 0.005
RXOUT±
Low Voltage
VOL
V
mV
Ω
VCC − 0.400 VCC − 0.350 VCC − 0.300
VOS_DOC_ON
Z0
Differential Output Offset
Digital Offset Correction = ON
±10
Single-Ended Output
Impedance
45
45
50
50
55
55
Single-Ended Input
Impedance
ZI
Ω
Notes:
2. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this datasheet. Exposure to absolute maximum ratings conditions may affect
device reliability.
3. The datasheet limits are not guaranteed if the device is operated beyond the recommended operating conditions.
4. Package thermal resistance assumes that the exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. ψJB and
θ
JA assumes still air and a 4-layer PCB, unless otherwise stated. It also assumes that the recommended via pattern and via sizes on the PCB are
used.
5. DOC is enabled, outputs RXOUT± are loaded with external 50Ω loads, and the outputs are enabled.
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SY88083L
TTL DC Electrical Characteristics
VCC = 3.0 to 3.6V; TA = –40°C to +85°C, typical values at VCC = 3.3V, TA = 25°C.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
JAM, DOC_EN, SD/LOS_SEL
Input High Voltage
VIH
2.0
V
JAM, DOC_EN, SD/LOS_SEL
Input Low Voltage
VIL
IIH
IIL
0.8
V
V
IN = 2.7V
20
JAM, DOC_EN, SD/LOS_SEL
Input High Current
µA
mA
VIN = VCC
100
JAM, DOC_EN, SD/LOS_SEL
Input Low Current
VIN = 0.4V
−0.3
VOH
VOL
SD or LOS Output High Level
SD or LOS Output Low Level
Sourcing 100µA
Sinking 2mA
2.4
V
V
0.4
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SY88083L
AC Electrical Characteristics
VCC = 3.3V ±10%, TA = –40°C to +85°C. Typical values at VCC = 3.3V, TA = 25°C; RLOAD = 50Ω to VCC
.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Output Rise/Fall Time
(20% to 80%)
tr, tf
Note 6
30
45
ps
Deterministic
Note 7
10
1
tJITTER
ps
Random
Note 8
VID
Differential Input Voltage Swing
Differential Output Voltage Swing
Note 10. See Figure 1.
Note 6
10
1800
800
mVPP
mVPP
VOD
600
700
1
tLOS_D; tLOS_A
tSD_D; tSD_A
LOS De-assert, LOS Assert Time
SD De-assert, SD Assert Time
Note 11
2
us
LOSAM_10k
LOSDM_10k
HYSM_10k
LOSAH1_1k
LOSDH1_1k
HYSH1_1k
LOSAH2_100
LOSDH2_100
HYSH2_100
AV(Diff)_063C
S21_063C
Medium LOS Assert Level
Medium LOS De-assert Level
Medium LOS Hysteresis
High1 LOS Assert Level
High1 LOS De-assert Level
High1 LOS Hysteresis
High2 LOS Assert Level
High2 LOS De-assert Level
High2 LOS Hysteresis
Differential Voltage Gain
Single-Ended Small-Signal Gain
DOC Delay Time
RLOSLVL = 10kΩ, Note 9
RLOSLVL = 10kΩ, Note 9
RLOSLVL = 10kΩ, Note 12
RLOSLVL = 1kΩ, Note 9
RLOSLVL = 1kΩ, Note 9
RLOSLVL = 1kΩ, Note 12
RLOSLVL = 100Ω, Note 9
RLOSLVL = 100Ω, Note 9
RLOSLVL = 100Ω, Note 12
4.5
7.3
mVPP
mVPP
dB
2
2
4.1
6
6
6
18.6
28.3
3.6
mVPP
mVPP
dB
29.7
44.6
3.5
mVPP
mVPP
dB
2
44
dB
32
38
dB
tDOC_DELAY
tDOC_LOCK
Note:
6. Amplifier is in limiting mode. Input is a 200MHz square wave.
7. Deterministic jitter is measured using 10Gbps K28.5 pattern, VID = 20mVPP
8. Random jitter is measured using 10Gbps K28.7 pattern, VID = 20mVPP
15
µs
DOC Lock Time
150
µs
.
.
9. See “Typical Operating Characteristics” for a graph showing how to choose a particular RLOSLVL for a particular LOS assert and its associated de-
assert amplitude.
10. Differential input swing amplitude for data rates up to 12.5Gbps
11. In real world applications, the LOS de-assert/assert time can be strongly influenced by the RC time constant of the AC-coupling capacitor and the
50Ω input termination. To keep this time low, use a decoupling capacitor with the lowest value that is allowed by the data rate and the number of
consecutive identical bits in the application (typical values are in the range of 0.001µF to 0.1µF).
12. This specification defines electrical hysteresis as 20log (LOS de-assert/LOS assert). The ratio between optical hysteresis and electrical hysteresis is
found to vary between 1.5 and 2, depending on the level of received optical power and ROSA characteristics.
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SY88083L
Typical Operating Characteristics
VCC = 3.3V, TA = 25°C, RLOAD = 50Ω to VCC, unless otherwise stated.
LOS Hysteresis
VID(LOS Assert) and
vs. LOSLVL Resistor
VID(LOS De-Assert) vs. RSD/LOSLVL
100
10
1
6.00
5.00
4.00
3.00
2.00
1.00
0.00
10
100
1000
10000
100000
10
100
1000
10000
100000
SD/LOSLVL Resistor (Ω)
SD/LOSLVL Resistor (Ω)
20 ps/div,
Typical 10.3G Output with 10mVPP Input Signal
20 ps/div,
Typical 12.5G Output with 10mVPP Input Signal
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SY88083L
Functional Block Diagram
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SY88083L
SD/LOSLVL and de-asserts low otherwise. LOS can be
fed back to the JAM input to perform the SQUELCH
function and to maintain output stability under a LOS
condition. JAM de-asserts the true output signal low
without removing the input signals. Typically, 4dB LOS
hysteresis is provided to prevent chattering.
Functional Description
The SY88083L is a high-sensitivity, high-bandwidth
limiting post amplifier. It operates from a single +3.3V
power supply across the entire industrial temperature
range of –40°C to +85°C.
Signals with data rates from 1.0625Gbps to 12.5Gbps
and amplitudes as small as 10mVPP are supported.
Figure 1 shows the allowed input voltage swing.
When SD/LOS_SEL is used to select the SD output on
the SD/LOS pin, SD is asserted when the differential
input signal amplitude exceeds the level set by the
SD/LOSLVL resistor. The JAM operation is inverted when
SD is selected.
RXIN+
RXIN-
900 (mV)
VIS (mV)
5 (mV)
Signal Detect/Loss-of-Signal Level Setting
A programmable SD/LOS level set pin (SD/LOSLVL) sets
the threshold of the input amplitude detection.
Connecting an external resistor between VCC and
SD/LOSLVL sets the threshold voltage. This voltage
ranges from VCC to VCC − 1.3V. The external resistor
creates a voltage divider between VCC and VCC − 1.3V, as
shown in Figure 5.
1800 (mVPP
)
(RXIN+) –
(RXIN-)
VID (mVPP
)
Hysteresis
10 (mVPP
)
The SY88083L provides typically 4dB LOS electrical
hysteresis, which is defined as 20log (VINLOS_De-Assert
÷
VINLOS_Assert). Because the relationship of the voltage
output of the ROSA to optical power at its input is linear,
the optical hysteresis is typically half of the electrical
hysteresis reported in the datasheet. In practice the ratio
between electrical and optical hysteresis is found to be
between 1.5 and 1.8. Thus, 4dB electrical hysteresis
corresponds to an optical hysteresis within the range of
2dB to 2.4dB.
Figure 1. VIS and VID Definition
The SY88083L has a selectable SD or LOS status output
signal that can be fed back to the JAM input to perform
the SQUELCH function for output stability if there is no
signal at the input. SD/LOSLVL sets the sensitivity of the
input amplitude detection.
The SY88083L has a user-selectable, integrated digital
offset correction function to cancel internally generated
output offsets.
Digital Offset Correction (DOC)
The digital offset correction (DOC) circuit compensates
for the inherent offsets found in high-gain amplifier
circuits and minimizes the offset seen at the outputs.
DOC is a user-selectable feature using the DOC_EN pin
as defined in the “Pin Description” table.
Input Amplifier/Buffer
Figure 2 shows a simplified schematic of the input stage.
The high sensitivity of the input amplifier allows signals
as small as 10mVPP to be detected and amplified. The
input amplifier allows input signals as large as 1800mVPP.
Input small signals are amplified with a typical 44dB
differential voltage gain.
Conventional analog offset compensation techniques
may be susceptible to drift from long continuous identical
digit (CID) patterns. They can also add additional cost
due to the extra DAC and manufacturing setup time
needed to optimize each individual module. The
SY88083L avoids both of these issues and provides a
performance/cost optimized solution.
Output Buffer
The SY88083L CML output buffer is designed to drive
50Ω impedance transmission lines and is internally
terminated with 50Ω to VCC. Figure 3 shows a simplified
schematic of the output stage.
The DOC circuitry automatically detects any internal
device offsets and locks the correction values but does
not apply offset correction to large input signals.
Signal Detect/Loss-of-Signal (SD/LOS)
The DOC is enabled by default unless DOC_EN is pulled
low by an external logic level signal. It can be reset by
toggling the DOC_EN pin high-to-low-to-high. The DOC
reset routine typically completes in 200µs.
The
SY88083L
generates
a
user-selectable
(SD/LOS_SEL pin) signal detect (SD) or loss-of-signal
(LOS) open-collector TTL output, as shown in Figure 4.
LOS is used to determine whether the input amplitude is
too small to be considered as a valid input. LOS asserts
high if the input amplitude falls below the threshold set by
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Functional Circuit Structures
Figure 2. Input Structure
Figure 3. Output Structure
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SY88083L
Functional Circuit Structures (Continued)
Figure 4. SD/LOS Output Structure
Figure 5. SD/LOSLVL Setting Circuit
Related Product and Support Documentation
Document Number
Title
Application Note Link
Notes on Sensitivity and Hysteresis
in Micrel Post Amplifiers
www.micrel.com/_PDF/HBW/App-Notes/an-45.pdf
AN-45
SY88073L/SY88083L Evaluation
Board
SY88073L_83L_EB
http://www.micrel.com/_PDF/Eval-Board/SY88073L_83L_EB.pdf
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SY88083L
Package Information(12)
16-Pin (3mm × 3mm) QFN-16
Note:
13. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
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SY88083L
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical
implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2013 Micrel, Incorporated.
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