SY89251VMITR [MICROCHIP]
LINE RECEIVER, PDSO8, 2 X 2 MM, MLF-8;
| 型号： | SY89251VMITR |
| 厂家： | 
MICROCHIP |
| 描述： | LINE RECEIVER, PDSO8, 2 X 2 MM, MLF-8 光电二极管 接口集成电路 |
| 文件： | 总7页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SY89251V
Enhanced Differential Receiver
General Description
Features
The SY89251V is a differential PECL/ECL receiver/buffer
in a space saving (2mm x 2mm) DFN package. The device
is functionally equivalent to the SY100EL16VC, except for
an active HIGH enable pin and a 70% smaller footprint. It
is also equivalent to the SY89250V, except for an active
• 3.3V and 5V power supply options
• 250ps propagation delay
• Very high voltage gain
• Ideal for pulse amplifier and limiting amplifier
applications
HIGH enable pin. It provides a V
output for either
BB
• Data synchronous enable/disable (EN) on QHG and
/QHG provides for complete glitchless gating of the
outputs
single-ended application or as a DC bias for AC-coupling
to the device.
The SY89251V provides an EN input which is
synchronized with the data input (D) signal in a way that
• Ideal for gating timing signals
provides glitchless gating of the Q
and /Q
outputs.
• Complete solution for high quality, high frequency
HG
HG
crystal oscillator applications
When the EN signal is HIGH, the input is passed to the
outputs and the data output equals the data input. When
the data input is HIGH and the EN goes LOW, it will force
• Available in an ultra-small 8-pin (2mm x 2mm)
DFN package
the Q
LOW and the /Q
HIGH on the next negative
HG
HG
Applications
transition of the data input. If the data input is LOW when
the EN goes LOW, the next data transition to a HIGH is
• Oscillator modules
ignored and Q
remains LOW and /Q
remains HIGH.
HG
HG
The next positive transition of the data input is not passed
on to the data outputs under these conditions. The Q
HG
and /Q
outputs remain in their disabled state as long as
HG
the EN input is held LOW. The EN input has no influence
on the /Q output and the data input is passed on (inverted)
to this output whether EN is HIGH or LOW. This
configuration is ideal for crystal oscillator applications,
where the oscillator can be free running and gated on and
off synchronously without adding extra counts to the
output.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
___________________________________________________________________________________________________________
Block Diagram
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
M9999-060410-A
hbwhelp@micrel.com or (408) 955-1690
June 2010
Micrel, Inc.
SY89251V
Ordering Information(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead
Finish
SY89251VMI
DFN-8
DFN-8
DFN-8
Industrial
Industrial
Industrial
251
251
Sn-Pb
Sn-Pb
SY89251VMITR(2)
SY89251VMG
251 with
Pb-Free bar-line indicator
Pb-Free
NiPdAu
SY89251VMGTR(2)
DFN-8
Industrial
251 with
Pb-Free bar-line indicator
Pb-Free
NiPdAu
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only.
2. Tape and Reel.
Truth Table
Pin Configuration
EN
0
QHG Output
Logic Low
Data
1
8-Pin DFN
(Ultra-Small Outline)
Pin Description
Pin Number
Pin Name
Type
100k
100k
Pin Function
Single-Ended PECL/ECL Feedback Output.
1
2
/Q
D
Single-Ended PECL/ECL Input: The signal input includes an internal 75kΩ pull-
down resistor. If input is left open, Q output will default to LOW.
3
4
VBB
EN
Reference
Output
Voltage
Bias Voltage: VCC–1.3V. Used as reference voltage when AC-coupling to the D
input. Max sink/source current is ±0.5mA.
Enable Input EN Input which is synchronized with data input (D) signal in a way that provides
glitchless gating of QHG and /QHG outputs. Includes internal 75kΩ pull-up resistor.
Default is HIGH.
5
VEE
Exposed Pad
Negative
Power
Negative Power Supply: VEE and exposed pad must be tied to most negative
supply. For PECL/LVPECL connect to ground.
Supply
6, 7
8
/QHG, QHG
VCC
100k
Differential PECL/ECL Output: QHG defaults to LOW and /QHG defaults to HIGH
if D input is left open. See “Output Interface Applications” section for
recommendations on terminations.
Positive
Power
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close
to VCC pin as possible.
Supply
M9999-060410-A
hbwhelp@micrel.com or (408) 955-1690
June 2010
2
Micrel, Inc.
SY89251V
Absolute Maximum Ratings(1)
Operating Ratings(2)
Power Supply Voltage (VCC)......................... –0.5V to +6.0V
Power Supply Voltage |VCC–VEE|............. 3.3V ±10% or 5V ±10%
ECL Input Voltage (VIN)..............................0V to V +0.5V
Ambient Temperature (TA)..........................–40°C to +85°C
CC
(3)
Voltage Applied to Output at HIGH State
Package Thermal Resistance,
(VOUT) ........................................................ –0.5V to V
...........................................................
CC
DFN (θ ) Still-Air
93°C/W
JA
Output Current (IOUT
)
DFN (ψ ) ...........................................................60°C/W
JB
Continuous ............................................................50mA
Surge………………………………………………..100mA
Lead Temperature (soldering, 20 sec.)...................... 260°C
Storage Temperature (T ) ........................–65°C to +150°C
S
DC Electrical Characteristics(4)
TA = –40°C to +85°C, unless noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
VEE
Power Supply
|VCC–VEE
|VCC–VEE
|
|
3.0
4.5
3.3
5.0
3.6
5.5
V
V
IEE
IIL
Power Supply Current
Input Low Current
46
mA
µA
V
EN
-150
VBB
Output Reference Voltage
VCC –1.38
VCC –1.32
VCC –1.26
DC Electrical Characteristics(4)
VCC = +3.3V ±10% or +5V ±10% and VEE = 0V; VCC = 0V and VEE = –3.3V ±10% or –5V ±10%; TA = –40°C to +85°C;
unless noted.
Symbol
VOH
VOL
Parameter
Condition
Note 4
Min
Typ
Max
Units
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Minimum Input Swing
Input HIGH Current
Input LOW Current
VCC–1.085
VCC–1.830
VCC–1.165
VCC–1.810
150
VCC–0.880
VCC–1.555
VCC–0.880
VCC–1.475
Note 4
V
VIH
V
VIL
V
VPP
mV
µA
µA
IIH
D
D
150
IIL
0.5
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
4. Output loaded with 50Ω to VCC–2V.
M9999-060410-A
hbwhelp@micrel.com or (408) 955-1690
June 2010
3
Micrel, Inc.
SY89251V
AC Electrical Characteristics
VEE = VEE (min) to VEE (max); VCC = GND; TA = –40°C to +85°C; unless noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
tpd
Propagation Delay to:
/Q Output
D (Diff)
D (SE)
380
430
ps
ps
QHG, /QHG Output
D (Diff)
D (SE)
730
780
ps
ps
tS
Set-Up Time
EN
EN
150
150
ps
ps
ps
mV
V
tH
Hold Time
tSKEW
VPP
VCMR
tr, tf
Duty Cycle Skew
Minimum Input Swing
Common Mode Range
(Diff) Note 5
5
20
Note 6
150
-1.3
100
Note 7
-0.4
350
Output /Q and QHG, /QHG
Rise/Fall Times
At full output swing
225
ps
(20% to 80%)
Notes:
5. Duty cycle skew is the difference between a tpd propagation delay through a device.
6. Minimum input swing for which AC parameters are guaranteed. The device has a DC gain of ≈ 40 to Q, /Q outputs and a DC gain of ≈ 200 or higher
to /QHG, QHG outputs.
7. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the
specified range and the peak-to-peak voltage lies between VPP(min) and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in
the spec table assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR(min) will be fixed at 3.3V – |VCMR(min)|.
Timing Diagram
M9999-060410-A
hbwhelp@micrel.com or (408) 955-1690
June 2010
4
Micrel, Inc.
SY89251V
Output Interface Applications
Figure 1b. Three Resistor “Y” Termination
Figure 1a. Parallel Thevenin-Equivalent Termination
Figure 1c. Terminating Unused I/O
M9999-060410-A
hbwhelp@micrel.com or (408) 955-1690
June 2010
5
Micrel, Inc.
SY89251V
Package Information
8-Pin Ultra-Small EPAD-DFN
M9999-060410-A
hbwhelp@micrel.com or (408) 955-1690
June 2010
6
Micrel, Inc.
SY89251V
PCB Thermal Consideration for 8-Pin DFN Package
Package Notes:
1. Packaging meets Leve 2 qualification.
2. All pasrts are dry-packaged before shipment.
3. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its
use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant
into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2009 Micrel, Incorporated.
M9999-060410-A
hbwhelp@micrel.com or (408) 955-1690
June 2010
7
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