SY89429AZH-TR [MICROCHIP]
PLL FREQUENCY SYNTHESIZER, 25MHz, PDSO28;
| 型号： | SY89429AZH-TR |
| 厂家： | 
MICROCHIP |
| 描述： | PLL FREQUENCY SYNTHESIZER, 25MHz, PDSO28 光电二极管 |
| 文件： | 总9页 (文件大小：494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Edge®
PROGRAMMABLE
FREQUENCY SYNTHESIZER
(25MHz to 400MHz)
SY89429A
FEATURES
n Improved jitter performance over SY89429
n 25MHz to 400MHz differential PECL outputs
n ±25ps peak-to-peak output jitter
n Minimal frequency over-shoot
n Synthesized architecture
Precision Edge®
DESCRIPTION
The SY89429A is a general purpose, synthesized clock
source targeting applications that require both serial and
parallel interfaces. Its internal VCO will operate over a range
offrequenciesfrom400MHzto800MHz.ThedifferentialPECL
output can be configured to be the VCO frequency divided by
2, 4, 8 or 16. With the output configured to divide the VCO
frequencyby2, andwitha16MHzexternalquartzcrystalused
to provide the reference frequency, the output frequency can
be specified in 1MHz steps.
n Serial 3 wire interface
n Parallel interface for power-on
n Internal quartz reference oscillator driven by quartz
crystal or PECL source
n PECL output can operate with either +3.3V or +5V
VCC_OUT power supply
nꢀ Externalꢀloopꢀfilterꢀoptimizesꢀperformance/cost
n Applications note (AN-06) for ease of design-ins
n Available in PLCC and SOIC 28-pin packages
PIN CONFIGURATION
M[0]
M[1]
M[2]
M[3]
M[4]
M[5]
M[6]
M[7]
M[8]
1
2
3
4
5
6
7
8
9
28 /P_LOAD
27 VCC1
24 23 22 21 20 19
25
26 XTAL2
S_CLOCK
S_DATA
26
27
28
1
18
17
16
15
14
13
12
N[1]
N[0]
M[8
M[7
M[6
M[5
M[4
25 XTAL1
S_LOAD
24 LOOP_REF
23 LOOP_FILTER
22 VCC_QUIET
21 S_LOAD
20 S_DATA
19 S_CLOCK
18 VCC_OUT
17 FOUT
PLCC
TOP VIEW
VCC_QUIET
LOOP_FILTER
LOOP_REF
XTAL1
2
SOIC
TOP VIEW
3
4
5
6
7
8
9
10 11
N[0] 10
N[1] 11
GND (TTL) 12
TEST 13
16 /FOUT
VCC (TTL) 14
15 GND
APPLICATIONS
n Workstations
n Advanced communications
n High end consumer
n High-performance computing
n RISC CPU clock
n Graphics pixel clock
n Test equipment
n Other high-performance processor-based
applications
Precision Edge is a registered trademark of Micrel, Inc.
Rev.: K
Amendment: /0
1
Issue Date: July 2009
Precision Edge®
SY89429A
Micrel, Inc.
BLOCK DIAGRAM
+5.0V
PLL
FREF
PHASE DETECTOR
÷ 8
10-25MHz
Fundamental
Crystal
VCO
PECL
OSC
÷ M
÷ N
FOUT
TEST
or
PECL
Source
400 – 800
MHz
INTERFACE
LOGIC
3 WIRE
INTERFACE
SERIAL
PARALLEL
CONFIG. INFO
DETAILED BLOCK DIAGRAM
+5.0V
+5.0V
6, 21
2
3
1
LOOP_RE F
LOOP_FILTER
VCC_QUIE T
VCC1
FRE F
PHASE DETECTOR
÷ 8
400-800
MHz
VCO
+5.0V
25
VCC_OUT
10–25MHz
Fundamental
Crystal
T110
4
5
1
0
XTAL1
24
or
FOU
23
9-BIT ÷ M
COUNTER
÷ N
(2,4,8,16)
OSC
PECL
S ource
FOU
XTAL2
L = LATCH
H = Transparent
7
6
5
4
3
2
FOUT ÷ 4 —
S _CLOCK ÷ M
LATCH
LATCH
—
28
7
S _LOAD
LOW —
FOUT —
÷ M —
LATCH
20
TES
P_LOAD
0
1
0
1
FRE F—
HIGH—
1
0
27
26
9-BIT S R
3-BIT S R
S _DATA
2-BIT S R
S _CLOCK
19,22
8 -> 16
17,18
9
2
N[1:0]
NOTE:
Pin numbers reference PLCC pinout.
2
Precision Edge®
SY89429A
Micrel, Inc.
PIN DESCRIPTIONS
INPUTS
OUTPUTS
XTAL1, XTAL2
FOUT, FOUT
These pins form an oscillator when connected to an external These differential positive-referenced ECL signals (PECL)
crystal. Thecrystalisseriesresonant. Alternatively,thesepins are the output of the synthesizer.
can be driven with 100K PECL level by an external source.
TEST
S_LOAD
The function of this TTL output is determined by the serial
This TTLpin loads the configuration latches with the contents configuration bits T[2:0].
of the shift registers. The latches will be transparent when this
signal is HIGH; thus, the register data must be stable on the POWER
HIGH-to-LOW transition of S_LOAD for proper operation.
VCC1
S_DATA
Thisisthepositivesupplyforthechipandisnormallyconnected
This TTL pin is the input to the serial configuration shift to +5.0V.
registers.
VCC_OUT
S_CLOCK
This is the positive reference for the PECLoutputs, FOUTand
FOUT. It is constrained to be less than or equal to VCC1.
This TTLpin clocks the serial configuration shift registers. On
the rising edge of this signal, data from S_DATA is sampled.
VCC_QUIET
P_LOAD
This is the positive supply for the PLLand should be as noise-
free as possible for low-jitter operation.
This TTLpin loads the configuration latches with the contents
of the parallel inputs. The latches will be transparent when
this signal is LOW; thus, the parallel data must be stable on
the LOW-to-HIGH transition of P_LOAD for proper operation.
GND
These pins are the negative supply for the chip and are
normally all connected to ground.
M[8:0]
OTHER
These TTL pins are used to configure the PLL loop divider.
They are sampled on the LOW-to-HIGH transition of P_LOAD.
M[8] is the MSB, M[0] is the LSB. The binary count on the M
pins equates to the divide-by value for the PLL.
LOOP_FILTER
This is an analog I/O pin that provides the loop filter for the
PLL.
N[1:0]
LOOP_REF
These TTL pins are used to configure the output divider
modulus. They are sampled on the LOW-to-HIGH transition
of P_LOAD.
This is an analog I/O pin that provides a reference voltage
for the PLL.
N[1:0]
0 0
Output Division
2
4
0 1
1 0
8
1 1
16
3
Precision Edge®
SY89429A
Micrel, Inc.
WITH 16MHZ INPUT
VCO Frequency
256
M8
0
128
M7
1
64
M6
1
32
M5
0
16
M4
0
8
M3
1
1
1
1
•
4
M2
0
0
0
0
•
2
M1
0
0
1
1
•
1
M0
0
1
0
1
•
(MHz)
400
402
404
406
•
M Count
200
201
202
203
•
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
794
796
798
800
397
398
399
400
1
1
0
0
0
1
1
1
0
1
1
1
0
0
1
1
0
1
0
1
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VCC
Parameter
Power Supply Voltage
Value
Unit
–0.5 to +7.0
–0.5 to +7.0
V
V
VI
Input Voltage
IOUT
Output Source
Continuous
Surge
50
100
mA
Tstore
TA
Storage Temperature
Operating Temperature
–65 to +150
–0 to +75
°C
°C
NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at
conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods
may affect device reliability.
FUNCTIONAL DESCRIPTION
The internal oscillator uses the external quartz crystal as the in 50ý. The positive reference for the output driver is provided by
basis of its frequency reference. The output of the reference a dedicated power pin (VCC_OUT) to reduce noise and provide
oscillator is divided by eight before being sent to the phase application flexibility.
detector. With a 16MHz crystal, this provides a reference
frequency of 2MHz.
The configuration logic has two sections: serial and parallel.
The parallel interface uses the values at the M[8:0] and N[1:0]
TheVCOwithinthePLLoperatesoverarangeof400–800MHz. inputs to configure the internal counters. Normally upon system
Its output is scaled by a divider that is configured by either the reset, the P_LOAD input is held LOW until sometime after power
serial or parallel interfaces. The output of this loop divider is also becomes valid. With S_LOAD held LOW, on the LOW-to-HIGH
applied to the phase detector.
transitionofP_LOAD,theparallelinputsarecaptured. Theparallel
The phase detector and loop filter force the VCO output interface has priority over the serial interface. Internal pull-up
frequency to be M times the reference frequency by adjusting resistors are provided on the M[8:0] and N[1:0] inputs to reduce
the VCO control voltage. Note that for some values of M (either component count.
too high or too low) the PLL will not achieve loop lock. External
loop filter components are utilized to allow for optimal phase register scheme. The register shifts once per rising edge of the
jitter performance. S_CLOCK input. The serial input S_DATA must meet set-up and
The serial interface logic is implemented with a 14-bit shift
TheoutputoftheVCOisalsopassedthroughanoutputdivider hold timing as specified in the AC parameters section of this
before being sent to the PECL output driver. The output divider data sheet. With P_LOAD held HIGH, the configuration latches
is configured through either the serial or the parallel interfaces will capture the value in the shift register on the HIGH-to-LOW
and can provide one of four divider ratios (2, 4, 8 or 16). This edge of the S_LOAD input. See the programming section for more
divider extends the performance of the part while providing a information.
50% duty cycle.
The TEST output reflects various internal node values and is
The output driver is driven differentially from the output divider controlled by the T[2:0] bits in the serial data stream. See the
and is capable of driving a pair of transmission lines terminated programming section for more information.
4
Precision Edge®
SY89429A
Micrel, Inc.
PROGRAMMING INTERFACE
Programming the device is accomplished by properly
The TEST output provides visibility for one of several
configuring the internal dividers to produce the desired internal nodes (as determined by the T[1:0] bits in the serial
frequency at the outputs. The output frequency can be configuration stream). It is not configurable through the
represented by this formula:
parallel interface. Although it is possible to select the node
that represents FOUT, the TTL output may not be able to
toggle fast enough for some of the higher output frequencies.
The T2, T1, T0 configuration latches are preset to 000 when
P_LOAD is low, so that the FOUT outputs are as jitter-free as
possible. The serial configuration port can be used to select
one of the alternate functions for this pin.
&84!,
-
.
&/54 ꢀ
8
ꢁ ꢃ
ꢂ
Where FXTAL is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that it is
possible to select values of M such that the PLL is unable to
achieve loop lock. To avoid this, always make sure that M is
selected to be 200 M 400 for a 16MHz input reference.
M[8:0]and N[1:0]arenormallyspecifiedonceatpower-on,
throughtheparallelinterface,andthenpossiblyagainthrough
the serial interface. This approach allows the designer to
bring up the application at one frequency and then change or
fine-tune the clock, as the ability to control the serial interface
becomes available. To minimize transients in the frequency
domain, the output should be varied in the smallest step size
possible.
The Test register is loaded with the first three bits, the N
register with the next two and the M register with the final eight
bits of the data stream on the S_DATA input. For each register
the most significant bit is loaded first (T2, N1 and M8).
When T[2:0] is set to 100 the SY89429A is placed in PLL
bypass mode. In this mode the S_CLOCK input is fed directly
into the M and N dividers. The N divider drives the FOUT
differential pair and the M counter drives the TEST output
pin. In this mode the S_CLOCK input could be used for low
speed board level functional test or debug. Bypassing the
PLL and driving FOUT directly gives the user more control
on the test clocks sent through the clock tree (See detailed
BlockDiagram). BecausetheS_CLOCK isaTTLleveltheinput
frequency is limited to 250MHz or less.This means the fastest
the FOUT pin can be toggled via the S_CLOCK is 125MHz as
the minimum divide ratio of the N counter is 2. Note that the
M counter output on the TEST output will not be a 50% duty
cycle due to the way the divider is implemented.
T2 T1 T0
TEST
Data Out – Last Bit SR
HIGH
ꢀ FOUTꢀ/ꢀFOUTꢀ
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FVCO ÷ N
FVCO ÷ N
FVCO ÷ N
FVCO ÷ N
FVCO ÷ N
FVCO ÷ N
S_CLOCK ÷ N
FVCO ÷ N
FREF
M Counter Output
FOUT
LOW
S_CLOCK ÷ M
FOUT ÷ 4
S_ CLOCK
S_ DATA
T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0
Last
Bit
First
Bit
S_ LOAD
M[ 8 :0 ]
N[1 :0 ]
M,N
P_ LOAD
Input S_DATA to M0 then M1, then M2, etc., as indicated above.
5
Precision Edge®
SY89429A
Micrel, Inc.
100H ECL DC ELECTRICAL CHARACTERISTICS
VCC1 = VCC_QUIET = VCC_TTL = +5.0V ±5%; VCC_OUT = +3.3V to +5.0V ±5%; TA = 0°C to +75°C
Symbol
VOH
Parameter
Output HIGH Voltage
Output LOW Voltage
Min.
Max.
Unit
V
Condition
VCC_OUT –1.075
VCC_OUT –1.860
VCC_OUT –0.830
VCC_OUT –1.570
50ý to VCC_OUT –2V
50ý to VCC_OUT –2V
VOL
V
TTL DC ELECTRICAL CHARACTERISTICS
VCC1 = VCC_QUIET = VCC_TTL = +5.0V ±5%; VCC_OUT = +3.3V to +5.0V ±5%; TA = 0°C to +75°C
T A = 0°C TA = +25°C TA = +75°C
Symbol
VIH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Input Clamp Voltage
Output HIGH Voltage
Output LOW Voltage
Output Short Circuit Current
Supply Current
Min.
Max.
—
Min.
2.0
—
Max.
—
Min.
2.0
—
Max.
—
Unit
Condition
—
2.0
—
—
—
—
—
—
V
V
VIL
0.8
0.8
0.8
—
IIH
50
—
50
—
50
µA
mA
V
VIN = 2.7V
VIN = 0.5V
IIN = –12mA
IOH = –2.0mA
IOL = 8mA
VOUT = 0V
—
IIL
–0.6
–1.2
2.5
—
–0.6
–1.2
2.5
—
–0.6
–1.2
2.5
VIK
—
—
VOH
VOL
IOS
—
—
V
0.5
—
0.5
—
0.5
V
–80 (Typ.)
–80 (Typ.)
–80 (Typ.)
mA
mA
ICC1
—
225
—
225
—
225
Typical % of ICC1
VCC1
91%
91%
91%
VCC_OUT
VCC_QUIET
VCC_TTL
4.5%
2.25%
2.25%
4.5%
2.25%
2.25%
4.5%
2.25%
2.25%
AC ELECTRICAL CHARACTERISTICS
VCC1 = VCC_QUIET = VCC_TTL = +5.0V ±5%; VCC_OUT = +3.3V to +5.0V ±5%; TA = 0°C to +75°C
TA = 0°C TA = +25°C TA = +75°C
Min. Max. Min. Max. Min. Max. Unit
Symbol
Parameter
Condition
fMAXI
Maximum Input Frequency(1)
S_CLOCK
Xtal Oscillator
—
10
10
25
—
10
10
25
—
10
10
25
MHz
Fundamental
Cyrstal
fMAXO
Maximum Output Frequency VCO (Internal)
FOUT
400
25
800
400
400
25
800
400
400
25
800 MHz
400
tLOCK
tjitter
tS
Maximum PLL Lock Time
—
—
20
10
±25
—
—
—
20
10
±25
—
—
—
20
10
±25
—
ms
ps
ns
Cycle-to-Cycle Jitter (Peak-toPeak)
Test output static
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
—
—
20
20
—
—
20
20
—
—
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
—
—
—
20
20
20
—
—
—
20
20
20
—
—
—
ns
ns
tpw(MIN)
tDC
Minimum Pulse Width
FOUT Duty Cycle
S_LOAD
P_LOAD
50
50
—
—
50
50
—
—
50
50
—
—
45
55
45
55
45
55
%
tr
tf
Output Rise/Fall
20% to 80%
FOUT
300
800
300
800
300
800
ps
NOTE:
1. 10MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at high frequencies when used as a test clock in
TEST_MODE 6.
6
Precision Edge®
SY89429A
Micrel, Inc.
TIMING DIAGRAM
S
_DATA
S
_CLOCK
t
HOLD
t
SET-UP
S
_LOAD
t
SET-UP
M[8:0]
N[1:0]
/P
_LOAD
t
HOLD
t
SET-UP
PRODUCT ORDERING CODE
Package
Operating
Range
Package
Marking
Lead
Finish
Part Number
SY89429AJC
SY89429AJCTR
SY89429AJZ
Type
J28-1
J28-1
J28-1
Commercial
Commercial
Industrial
SY89429A
SY89429A
Sn-Pb
Sn-Pb
SY89429A with
Pb-Free
Pb-Free bar-line indicator
Matte-Sn
SY89429AJZTR
J28-1
Industrial
SY89429A with
Pb-Free
Pb-Free bar-line indicator
Matte-Sn
SY89429AZC
SY89429AZCTR
SY89429AZH
Z28-1
Z28-1
Z28-1
Commercial
Commercial
Industrial
SY89429A
SY89429A
Sn-Pb
Sn-Pb
SY89429A with
Pb-Free bar-line indicator
Pb-Free
NiPdAu
SY89429AZHTR
Z28-1
Industrial
SY89429A with
Pb-Free bar-line indicator
Pb-Free
NiPdAu
7
Precision Edge®
SY89429A
Micrel, Inc.
28 LEAD SOIC .300" WIDE (Z28-1)
8
Precision Edge®
SY89429A
Micrel, Inc.
28 LEAD PLCC (J28-1)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
t e l + 1 (408) 944-0800 f a x + 1 (408) 944-0970 w e b http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2003 Micrel, Incorporated.
9
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