SY89467UHY [MICROCHIP]
Precision LVPECL 1:20 Fanout with 2:1 MUX and Internal Termination with Fail-Safe Input;
| 型号： | SY89467UHY |
| 厂家： | 
MICROCHIP |
| 描述： | Precision LVPECL 1:20 Fanout with 2:1 MUX and Internal Termination with Fail-Safe Input |
| 文件： | 总15页 (文件大小：558K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SY89467U
Precision LVPECL 1:20 Fanout with 2:1 MUX
and Internal Termination with Fail-Safe Input
General Description
Precision Edge®
The SY89467U is a 2.5/3.3V, 1:20 LVPECL fanout
buffer with a 2:1 differential input multiplexer (MUX).
A unique Fail-Safe Input (FSI) protection prevents
metastable output conditions when the selected
input clock fails to a DC voltage (when voltage
between the pins of the differential input drops
significantly below 100mV).
Features
• Selects between two inputs, and provides 20
precision LVPECL copies
• Fail-Safe Input
– Prevents outputs from oscillating when input is
invalid
The differential input includes Micrel’s unique, 3-pin
internal termination architecture that can interface to
any differential signal (AC- or DC-coupled) as small
as 100mV (200mVPP) without any level shifting or
termination resistor networks in the signal path. The
outputs are 800mV, LVPECL with fast rise/fall times
guaranteed to be less than 270ps.
• Guaranteed AC performance over temperature and
supply voltage:
– DC-to >1.5 GHz throughput
– < 1200ps Propagation Delay (In-to-Q)
– 270ps Rise/Fall times
• Ultra-low jitter design:
– <1psRMS random jitter
The SY89467U operates from a 2.5V ±5% or 3.3V
±10% supply and is guaranteed over the full
industrial temperature range of –40°C to +85°C. The
SY89467U is part of Micrel’s high-speed, Precision
Edge® product line.
– <1psRMS cycle-to-cycle jitter
– <10psPP total jitter (clock)
– <0.7psRMS MUX crosstalk induced jitter
• Unique, patented MUX input isolation design
minimizes adjacent channel crosstalk
All support documentation can be found on Micrel’s
web site at: www.micrel.com.
• Unique patented internal termination and VT pin
accepts DC- and AC-coupled inputs (CML, PECL,
LVDS)
Functional Block Diagram
• Wide input voltage range: VCC to GND
• 2.5V ±5% or 3.3V ±10% supply voltage
• -40°C to +85°C industrial temperature range
• Available in 64-pin TQFP package
Applications
• Fail-safe clock protection
• SONET clock distribution
• Backplane distribution
Markets
• LAN/WAN
• Enterprise servers
• ATE
• Test and measurement
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
April 2008
Micrel, Inc.
SY89467U
Ordering Information(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead
Finish
SY89467UHY with
Pb-Free bar-line Indicator
Matte-Sn
Pb-Free
SY89467UHY
T64-1
Industrial
Industrial
SY89467UHY with
Pb-Free bar-line Indicator
Matte-Sn
Pb-Free
SY89467UHYTR(2)
T64-1
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals Only.
2. Tape and Reel.
Pin Configuration
64-Pin EPAD-TQFP (T64-1)
April 2008
2
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY89467U
Pin Description
Pin Number
Pin Name
Pin Function
1, 16, 23, 33
41, 48, 58
Positive Power Supply: Bypass with 0.1µF||0.01µF low ESR capacitors as close to the VCC
pins as possible.
VCC
64, 63
62, 61
60, 59
57, 56
55, 54
53, 52
51, 50
47, 46
45, 44
43, 42
39, 38
37, 36
35, 34
31, 30
29, 28
27, 26
25, 24
22, 21
20, 19
18, 17
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
Q5, /Q5
Q6, /Q6
Q7, /Q7
Q8, /Q8
LVPECL Differential Output Pairs: Differential buffered output copies of the selected input
signal. The output swing is typically 800mV. Unused output pairs may be left floating with no
impact on jitter. See “LVPECL Output Termination” subsection. Normally terminated with 50Ω
to VCC-2V. These differential LVPECL outputs are a logic function of the IN0, IN1, and SEL
inputs. See “Truth Table” below.
Q9, /Q9
Q10, /Q10
Q11, /Q11
Q12, /Q12
Q13, /Q13
Q14, /Q14
Q15, /Q15
Q16, /Q16
Q17, /Q17
Q18, /Q18
Q19, /Q19
Reference Voltage: These outputs bias to VCC–1.2V. They are used for AC-coupling inputs IN
and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01µF low
ESR capacitor to VCC. Due to limited drive capability, each VREF-AC pin is only intended to
drive its respective VT pin. Maximum sink/source current is ±0.5mA. See “Input Interface
Applications” subsection.
VREF-AC0
VREF-AC1
4, 13
5, 12
Input Termination Center-Tap: Each side of a differential input pair terminates to the VT pin.
The VT pin provides a center-tap for each input (IN, /IN) to a termination network for
maximum interface flexibility. See “Input Interface Applications” subsection.
VT0, VT1
Differential Inputs: These input pairs are the differential signal inputs to the device. These
inputs accept AC- or DC-coupled signals as small as 100mV. The input pairs internally
terminate to a VT pin through 50Ω. This allows a wide input voltage range from VCC to
GND. See Figure 3a, Simplified Differential Input Stage for details. Note that when these
inputs are left in an open state, the FSI feature will override this input state and provide a
valid state at the output. See “Functional Description” subsection.
6, 7
10, 11
IN0, /IN0
IN1, /IN1
GND,
Exposed
Pad
2, 3, 14, 15,
32, 40, 49
Ground. Exposed pad must be connected to a ground plane that is the same potential as the
ground pins.
Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q19 outputs. It is
internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left
open. When disabled, Q goes LOW and /Q goes HIGH. OE being synchronous, outputs will
be enabled/disabled following a rising and a falling edge of the input clock. VTH = VCC/2.
9
OE
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will
default to logic HIGH state if left open. VTH = VCC/2.
8
SEL
Truth Table
Inputs
Outputs
IN0
0
/IN0
1
IN1
X
/IN1
X
SEL
Q
/Q
1
0
0
1
1
0
1
0
1
1
0
X
X
0
X
X
0
1
1
X
X
1
0
0
April 2008
3
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY89467U
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC) ..........................–0.5V to +4.0V
Input Voltage (VIN) ..................................–0.5V to VCC
LVPECL Output Current (IOUT)....................................
Continuous................................................. 50mA
Surge........................................................ 100mA
Current (VT)
Supply Voltage (VCC).................. +2.375V to +2.625V
......................................................+3.0V to +3.6V
Ambient Temperature (TA)……………-40°C to +85°C
(3)
Package Thermal Resistance
TQFP (θ JA)
Still-Air ..................................................... 35°C/W
TQFP (ψ JB)
Source or sink on VT pin........................ ±100mA
Input Current
Junction-to-Board.................................... 21°C/W
Source or sink current on (IN, /IN) ........... ±50mA
Current (VREF
)
(4)
Source/Sink Current on VREF-AC ........... ±0.5mA
Maximum Operating Junction Temperature.....125°C
Lead Temperature (soldering, 20 sec.) ..........+260°C
Storage Temperature (Ts)..................–65°C to 150°C
DC Electrical Characteristics(5)
TA = –40°C to +85°C, unless otherwise stated.
Symbol Parameter
Condition
Min
Typ
Max
Units
VCC
Power Supply
2.375
3.0
2.5
3.3
2.625
3.6
V
V
ICC
Power Supply Current
No load, max VCC
120
50
165
55
mA
RIN
Input Resistance
(IN-to-VT)
45
90
0.1
0
Ω
RDIFF_IN
VIH
Differential Input Resistance
(IN-to-/IN)
100
110
VCC
Ω
V
Input High Voltage
(IN, /IN)
VIL
Input Low Voltage
(IN, /IN)
VIH–0.1
1.0
V
VIN
Input Voltage Swing
(IN, /IN)
See Figure 2a. Note 6.
See Figure 2b.
0.1
0.2
V
VDIFF_IN
VIN_FSI
Differential Input Voltage Swing
|IN-/IN|
V
Input Voltage Threshold that
Triggers FSI
30
100
mV
VREF-AC
VT_IN
Output Reference Voltage
Voltage from Input to VT
IVREF-AC = + 0.5mA
VCC–1.3
VCC–1.2
VCC–1.1
1.28
V
V
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. θJA and
ψJB values are determined for a 4-layer board in still air unless otherwise stated.
4. Due to limited drive capability use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6.
VIN (max) is specified when VT is floating.
April 2008
4
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY89467U
LVPECL Outputs DC Electrical Characteristics(7)
VCC = 2.5V ±5% or 3.3V ±10%; RL = 50Ω to VCC-2V; TA = –40°C to + 85°C, unless otherwise stated.
Symbol
VOH
Parameter
Condition
Q, /Q
Min
VCC-1.145
VCC-1.945
550
Typ
Max
Units
Output HIGH Voltage
Output LOW Voltage
Output Voltage Swing
Differential Output Voltage Swing
VCC-0.895
VCC-1.695
950
V
VOL
Q, /Q
VOUT
See Figure 2a.
See Figure 2b.
800
mV
mV
VDIFF_OUT
1100
1600
1900
LVTTL/CMOS DC Electrical Characteristics(7)
VCC = 2.5V ±5% or 3.3V ±10%;TA = –40°C to + 85°C, unless otherwise stated.
Symbol
VIH
Parameter
Condition
Min
Typ
Max
Units
V
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
2.0
VIL
0.8
30
V
IIH
-125
-300
µA
µA
IIL
Note:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
April 2008
5
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY89467U
AC Electrical Characteristics(8)
VCC = 2.5V ±5% or 3.3V ±10%; RL = 50Ω to VCC-2V; Input tr/tf < 300ps; TA = –40°C to + 85°C, unless otherwise
stated.
Symbol Parameter
fMAX Maximum Operating Frequency
Condition
Min
1.5
1.0
Typ
2.0
1.5
Max
Units
GHz
GHz
VOUT ≥ 200mV, VIN ≥ 200mV
VOUT ≥ 200mV, VIN ≥ 100mV
tpd
Differential Propagation Delay
IN-to-Q
IN-to-Q
SEL-to-Q
100mV < VIN ≤ 200mV, Note 9
200mV < VIN ≤ 800mV, Note 9
VTH = VCC/2
600
500
350
300
800
850
750
600
1200
1100
850
ps
ps
ps
ps
ps
ps
ps
ps
tS OE
tH OE
tSKEW
Set-up Time
OE-to-IN Note 10
IN-to-OE Note 10
Hold Time
Output-to-Output Skew
Input-to-Input Skew
Part-to-Part Skew
Clock
Note 11
Note 12
Note 13
15
5
35
20
300
tJITTER
Random Jitter
Note 14
Note 15
Note 16
Note 17
1
1
psRMS
psRMS
psPP
psRMS
ps
Cycle-to-Cycle Jitter
Total Jitter
10
0.7
250
55
55
Crosstalk-Induced Jitter
tr, tf
Output Rise/Fall Time (20% to 80%) At full output swing.
110
45
170
Duty Cycle
VIN > 200mV
%
100mV < VIN ≤ 200mV
45
%
Notes:
8. High-frequency AC-parameters are guaranteed by design and characterization.
9. Propagation delay is measured with input tr, tf ≤ 300ps (20% to 80%). The propagation delay is a function of the rise and fall times at IN.
See “Typical Operating Characteristics” for details.
10. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous
applications, set-up and hold do not apply.
11. Output-to-Output skew is measured between two different outputs under identical transitions.
12. Input-to-Input skew is the time difference between the two inputs to one output, under identical input transitions.
13. Part-to-Part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs.
14. Random Jitter is measured with a K28.7 character pattern, measured at <fMAX
.
15. Cycle-to-Cycle Jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the
output signal.
16. Total Jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 1012 output edges will deviate by more
than the specified peak-to-peak jitter value.
17. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each
other at the inputs.
April 2008
6
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY89467U
Functional Description
Clock Select (SEL)
Input Clock Failure Case
SEL is an asynchronous TTL/CMOS compatible input
that selects one of the two input signals. An internal
25kΩ pull-up resistor defaults the input to logic HIGH if
left open. Input switching threshold is VCC/2. Refer to
Figure 1a.
If the input clock fails to a floating, static, or extremely
low signal swing such that the voltage across the input
pair is significantly less than 100mV, FSI function will
eliminate a metastable condition and latch the outputs
to the last valid state. No ringing and no undetermined
state will occur at the output under these conditions.
The output recovers to normal operation once the
input signal returns to a valid state with a typical swing
greater than 30mV.
Fail-Safe Input (FSI)
The input includes a special failsafe circuit to sense
the amplitude of the input signal and to latch the
outputs when there is no input signal present, or when
the amplitude of the input signal drops sufficiently
below 100mVPK, typically 30mVPK. Maximum
frequency of the SY89467U is limited by the FSI
function. Refer to Figure 1b.
Note that the FSI function will not prevent duty cycle
distortion in case of a slowly deteriorating (but still
toggling) input signal. Due to the FSI function, the
propagation delay will depend on the rise and fall time
of the input signal and on its amplitude.
Output Enable (OE)
OE is a synchronous TTL/CMOS compatible input that
enables/disables the outputs based upon the input to
this pin. The enable function is synchronous so that
the clock outputs will be enabled or disabled following
a rising and a falling edge of the input clock. Refer to
Figure 1c. Internal 25kΩ pull-up resistor defaults the
input to logic HIGH if left open. Input switching
threshold is VCC/2.
April 2008
7
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY89467U
Timing Diagrams
Figure 1a. SEL-to-Q Delay
Figure 1b. Fail-Safe Feature
April 2008
8
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY89467U
Figure 1c. Enable Output Timing Diagram
Figure 1d. Propagation Delay
Figure 1e. Setup and Hold Time
April 2008
9
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY89467U
Typical Operating Characteristics
VCC = 3.3V, GND = 0V, VIN = 200mV, RL = 50Ω to VCC–2V; TA = 25°C, unless otherwise stated.
April 2008
10
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY89467U
Functional Characteristics
VCC = 3.3V, GND = 0V, VIN = 100mV, RL = 50Ω to VCC-2V; TA = 25°C, unless otherwise stated.
April 2008
11
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY89467U
Single-Ended and Differential Swings
Figure 2b. Differential Voltage Swing
Figure 2a. Single-Ended Voltage Swing
Input and Output Stages
Figure 3b. Simplified Differential Output Stage
Figure 3a. Simplified Differential Input Stage
April 2008
12
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY89467U
Input Interface Applications
Option: may connect VT to VCC
Figure 4c. CML Interface
(DC-Coupled)
Figure 4a. LVPECL Interface
(DC-Coupled)
Figure 4b. LVPECL Interface
(AC-Coupled)
Figure 4d. CML Interface
(AC-Coupled)
Figure 4e. LVDS Interface
(DC-Coupled)
April 2008
13
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY89467U
PECL Output Interface Applications
PECL has a high input impedance, a very low output
impedance (open emitter), and a small signal swing
which results in low EMI. PECL is ideal for driving
50ohm
and
100ohm-controlled
impedance
transmission lines. There are several techniques for
terminating the PECL output: parallel termination-
thevenin equivalent, parallel termination (3-resistor),
and AC-coupled termination. Unused output pairs
may be left floating. However, single-ended outputs
must be terminated or balanced.
Figure 5b. Parallel Termination
(3-Resistor)
Figure 5a. Parallel Termination-Thevenin
Equivalent
Related Product and Support Documentation
Part Number
Function
Data Sheet Link
SY89468U
Precision LVDS 1:20 Fanout MUX with 2:1
MUX and internal termination with Fail Safe
Input
http://www.micrel.com/_PDF/HBW/sy89467u.pdf#page=2
MLF® Application Note
www.amkor.com/products/notes_papers/MLFAppNote.pdf
www.micrel.com/product-info/products/solutions.shtml
HBW Solutions New Products and Applications
April 2008
14
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY89467U
Package Information
64-Pin EPAD-TQFP (T64-1)
Packages Notes:
1. Package meets Level 2 Moisture Sensitivity Classification.
2. All parts are dry-packed before shipment.
3. Exposed pad must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel
for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for
surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant
injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk
and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2007 Micrel, Inc.
April 2008
15
M9999-040808-C
hbwhelp@micrel.com or (408) 955-1690
相关型号：
SY89467UHYTR
89467 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64, LEAD FREE, TQFP-64
MICROCHIP
SY89468U
Precision LVDS 1:20 Fanout with 2:1 MUX and Internal Termination with Fail-Safe Input
MICREL
SY89468UHY
Precision LVDS 1:20 Fanout with 2:1 MUX and Internal Termination with Fail-Safe Input
MICREL
SY89468UHYTR
Precision LVDS 1:20 Fanout with 2:1 MUX and Internal Termination with Fail-Safe Input
MICREL
SY89468UMY
89468 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
MICROCHIP
SY89468UMY-TR
89468 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64
MICROCHIP
SY89468UMYTR
89468 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64, LEAD FREE, TQFP-64
MICROCHIP
©2020 ICPDF网 联系我们和版权申明