SY89468UMYTR [MICROCHIP]
89468 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64, LEAD FREE, TQFP-64;
| 型号： | SY89468UMYTR |
| 厂家： | 
MICROCHIP |
| 描述： | 89468 SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP64, LEAD FREE, TQFP-64 驱动 输出元件 |
| 文件： | 总15页 (文件大小：560K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SY89468U
Precision LVDS 1:20 Fanout with 2:1 MUX
and Internal Termination with Fail-Safe Input
General Description
Precision Edge®
The SY89468U is a 2.5V, 1:20 LVDS fanout buffer
with a 2:1 differential input multiplexer (MUX). A
unique Fail-Safe Input (FSI) protection prevents
metastable output conditions when the selected
input clock fails to a DC voltage (voltage between
the pins of the differential input drops significantly
below 100mV).
Features
• Selects between two inputs, and provides 20
precision LVDS copies
• Fail-Safe Input
– Prevents outputs from oscillating when input is
invalid
The differential input includes Micrel’s unique, 3-pin
internal termination architecture that can interface to
any differential signal (AC- or DC-coupled) as small
as 100mV (200mVPP) without any level shifting or
termination resistor networks in the signal path. The
outputs are LVDS compatible with very fast rise/fall
times guaranteed to be less than 270ps.
• Guaranteed AC performance over temperature and
supply voltage:
– DC to >1.5GHz throughput
– < 1200ps Propagation Delay (In-to-Q)
– < 270ps Rise/Fall times
• Ultra-low jitter design:
The SY89468U operates from a 2.5V ±5% supply
and is guaranteed over the full industrial
temperature range of –40°C to +85°C. The
SY89468U is part of Micrel’s high-speed, Precision
Edge® product line.
– <1psRMS random jitter
– <1psRMS cycle-to-cycle jitter
– <10psPP total jitter (clock)
– <0.7psRMS MUX crosstalk induced jitter
• Unique, patented MUX input isolation design
All support documentation can be found on Micrel’s
web site at: www.micrel.com.
minimizes adjacent channel crosstalk
• Unique, patented internal termination and VT pin
accepts DC- and AC-coupled inputs (CML, PECL,
LVDS)
Functional Block Diagram
• Wide input voltage range VCC to GND
• 2.5V ±5% supply voltage
• -40°C to +85°C industrial temperature range
• Available in 64-pin TQFP package
Applications
• Fail-safe clock protection
• Ultra-low jitter LVDS clock or data distribution
• Rack-based Telecom/Datacom
Markets
• LAN/WAN
• Enterprise servers
• ATE
• Test and measurement
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
M9999-012208-B
hbwhelp@micrel.com or (408) 955-1690
January 2008
Micrel, Inc.
SY89468U
Ordering Information(1)
Part Number
Package
Type
Operating
Range
Package Marking
Lead
Finish
SY89468UMY with
Pb-Free bar-line Indicator
Matte-Sn
Pb-Free
SY89468UMY
T64-1
Industrial
Industrial
SY89468UMY with
Pb-Free bar-line Indicator
Matte-Sn
Pb-Free
SY89468UMYTR(2)
T64-1
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals Only.
2. Tape and Reel.
Pin Configuration
64-Pin EPAD-TQFP (T64-1)
January 2008
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SY89468U
Pin Description
Pin Number
Pin Name
Pin Function
Positive Power Supply: Bypass with 0.1µF||0.01µF low ESR capacitors as close to the VCC
pins as possible.
1, 16, 23, 33
41, 48, 58
VCC
64, 63
62, 61
60, 59
57, 56
55, 54
53, 52
51, 50
47, 46
45, 44
43, 42
39, 38
37, 36
35, 34
31, 30
29, 28
27, 26
25, 24
22, 21
20, 19
18, 17
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
Q5, /Q5
Q6, /Q6
Q7, /Q7
Q8, /Q8
Differential Output Pairs: The output swing is typically 325mV. Used and unused outputs
must be terminated with 100Ω across the pair (Q, /Q). These differential LVDS outputs are a
logic function of the IN0, IN1, and SEL inputs. See “Truth Table” below.
Q9, /Q9
Q10, /Q10
Q11, /Q11
Q12, /Q12
Q13, /Q13
Q14, /Q14
Q15, /Q15
Q16, /Q16
Q17, /Q17
Q18, /Q18
Q19, /Q19
Reference Voltage: These outputs bias to VCC–1.2V. They are used for AC-coupling inputs
IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01µF low
ESR capacitor to VCC. Due to limited drive capability, each VREF-AC pin is only intended to
drive its respective VT pin. Maximum sink/source current is ±0.5mA. See “Input Interface
Applications” subsection.
VREF-AC0
VREF-AC1
4, 13
5, 12
Input Termination Center-Tap: Each side of a differential input pair terminates to the VT pin.
The VT pin provides a center-tap for each input (IN, /IN) to a termination network for
maximum interface flexibility. See “Input Interface Applications” subsection.
VT0, VT1
Differential Inputs: These input pairs are the differential signal inputs to the device. These
inputs accept AC- or DC-coupled signals as small as 100mV. The input pairs internally
terminate to a VT pin through 50Ω. Each input has level shifting resistors of 3.72kΩ to VCC.
This allows a wide input voltage range from VCC to GND. See Figure 3, Simplified
Differential Input Stage for details. Note that when these inputs are left in an open state, the
FSI feature will override this input state and provide a valid state at the output. See
“Functional Description” subsection.
6, 7
10, 11
IN0, /IN0
IN1, /IN1
2, 3, 14, 15,
32, 40, 49
GND,
Ground. Exposed pad must be connected to a ground plane that is the same potential as
Exposed Pad the ground pins.
Single-Ended Input: This TTL/CMOS input disables and enables the Q0-Q19 outputs. It is
internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left
open. When disabled, Q goes LOW and /Q goes HIGH. OE being synchronous, outputs will
be enabled/disabled following a rising and a falling edge of the input clock. VTH = VCC/2.
9
OE
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the
multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will
default to logic HIGH state if left open. VTH = VCC/2.
8
SEL
Truth Table
Inputs
Outputs
IN0
0
/IN0
1
IN1
X
/IN1
X
SEL
Q
/Q
1
0
0
1
1
0
1
0
1
1
0
X
X
0
X
X
0
1
1
X
X
1
0
0
January 2008
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SY89468U
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC) ..........................–0.5V to +4.0V
Input Voltage (VIN) ..................................–0.5V to VCC
LVDS Output Current (IOUT)…………………….±10mA
Current (VT)
Source or sink on VT pin........................ ±100mA
Input Current
Supply Voltage (VCC).................. +2.375V to +2.625V
Ambient Temperature (TA)……………-40°C to +85°C
(3)
Package Thermal Resistance
TQFP (θ JA)
Still-Air ..................................................... 35°C/W
TQFP (ψ JB)
Source or sink current on (IN, /IN) ........... ±50mA
Junction-to-Board.................................... 21°C/W
Current (VREF
)
(4)
Source/Sink Current on VREF-AC ........... ±0.5mA
Maximum operating Junction Temperature….. 125°C
Lead Temperature (soldering, 20 sec.) ..........+260°C
Storage Temperature (Ts)..................–65°C to 150°C
DC Electrical Characteristics(5)
TA = –40°C to +85°C, unless otherwise stated.
Symbol Parameter
Condition
Min
Typ
Max
Units
VCC
Power Supply
2.375
2.5
2.625
V
ICC
Power Supply Current
No load, max VCC
260
50
365
55
mA
RIN
Input Resistance
(IN-to-VT)
45
90
0.1
0
Ω
RDIFF_IN
VIH
Differential Input Resistance
(IN-to-/IN)
100
110
VCC
Ω
V
Input High Voltage
(IN, /IN)
VIL
Input Low Voltage
(IN, /IN)
VIH–0.1
1.0
V
VIN
Input Voltage Swing
(IN, /IN)
See Figure 2a. Note 6.
See Figure 2b.
0.1
0.2
V
VDIFF_IN
VIN_FSI
Differential Input Voltage Swing
|IN-/IN|
V
Input Voltage Threshold that
Triggers FSI
30
100
mV
VREF-AC
VT_IN
Output Reference Voltage
Voltage from Input to VT
IVREF-AC = + 0.5mA
VCC–1.3
VCC–1.2
VCC–1.1
1.28
V
V
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. θJA and
ψJB values are determined for a 4-layer board in still air unless otherwise stated.
4. Due to limited drive capability use for input of the same package only.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6.
VIN (max) is specified when VT is floating.
January 2008
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SY89468U
LVDS Outputs DC Electrical Characteristics(7)
VCC = +2.5V ±5%, RL = 100ꢀ across the outputs; TA = –40°C to +85°C, unless otherwise stated.
Symbol
VOUT
Parameter
Condition
Min
250
Typ
325
650
1.20
Max
Units
mV
Output Voltage Swing (Q, /Q)
Differential Output Voltage Swing |Q – /Q|
Output Common Mode Voltage (Q, /Q)
See Figure 2a
See Figure 2b
See Figure 5a
VDIFF_OUT
VOCM
500
mV
1.125
–50
1.275
+50
V
Change in Common Mode Voltage (Q, /Q) See Figure 5b
mV
∆VOCM
LVTTL/CMOS DC Electrical Characteristics(7)
VCC = 2.5V ±5%; TA = –40°C to + 85°C, unless otherwise stated.
Symbol
VIH
Parameter
Condition
Min
Typ
Max
Units
V
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
2.0
VIL
0.8
30
V
IIH
-125
-300
µA
µA
IIL
Note:
7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
January 2008
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SY89468U
AC Electrical Characteristics(8)
VCC = +2.5V ±5%, RL = 100ꢀ across the outputs; TA = –40°C to +85°C, unless otherwise stated.
Symbol Parameter
Condition
Min
Typ
Max
Units
VOUT ≥ 200mV
1.0
1.5
GHz
tpd
Differential Propagation Delay
IN-to-Q
100mV ≤ VIN ≤ 200mV, Note 9
200mV ≤ VIN ≤ 800mV, Note 9
VTH = VCC/2
600
500
350
300
800
810
720
580
1200
1100
850
ps
ps
ps
ps
ps
ps
ps
ps
IN-to-Q
SEL-to-Q
tS OE
tH OE
tSKEW
Set-up Time
OE-to-IN Note 10
Hold Time
IN-to-OE Note 10
Note 11
Output-to-Output Skew
Input-to-Input Skew
Part-to-Part Skew
Clock
15
5
40
25
Note 12
Note 13
300
tJITTER
Random Jitter
Cycle-to-Cycle Jitter
Total Jitter
Note 14
Note 15
Note 16
Note 17
1
1
psRMS
psRMS
psPP
psRMS
ps
10
0.7
270
53
55
Crosstalk-Induced Jitter
tr, tf
Output Rise/Fall Time (20% to 80%)
Duty Cycle
At full output swing.
VIN > 200mV
90
47
45
%
100mV ≤ VIN ≤ 200mV
%
Notes:
8. High-frequency AC-parameters are guaranteed by design and characterization.
9. Propagation delay is measured with input tr, tf ≤ 300ps (20% to 80%). The propagation delay is a function of the rise and fall times at IN.
See “Typical Operating Characteristics” for details.
10. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous
applications, set-up and hold do not apply.
11. Output-to-Output skew is measured between two different outputs under identical transitions.
12. Input-to-Input skew is the time difference between the two inputs to one output, under identical input transitions.
13. Part-to-Part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at
the respective inputs.
14. Random Jitter is measured with a K28.7 character pattern, measured at <fMAX
.
15. Cycle-to-Cycle Jitter definition: the variation of periods between adjacent cycles, Tn – Tn-1 where T is the time between rising edges of the
output signal.
16. Total Jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 1012 output edges will deviate by more
than the specified peak-to-peak jitter value.
17. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each
other at the inputs.
January 2008
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SY89468U
Functional Description
Clock Select (SEL)
SEL is an asynchronous TTL/CMOS compatible input
that selects one of the two input signals. An internal
25kꢀ pull-up resistor defaults the input to logic HIGH if
left open. Input switching threshold is VCC/2. Refer to
Figure 1a.
function will eliminate a metastable condition and latch
the outputs to the last valid state. No ringing and no
undetermined state will occur at the output under
these conditions. The output recovers to normal
operation once the input signal returns to a valid state
with a typical swing greater than 30mV.
Fail-Safe Input (FSI)
Note that the FSI function will not prevent duty cycle
distortion in case of a slowly deteriorating (but still
toggling) input signal. Due to the FSI function, the
propagation delay will depend on the rise and fall time
of the input signal and on its amplitude.
The input includes a special fail-safe circuit to sense
the amplitude of the input signal and to latch the
outputs when there is no input signal present or when
the amplitude of the input signal drops sufficiently
below 100mVPK, typically 30mVPK. Refer to Figure 1b.
Output Enable (OE)
Input Clock Failure Case
OE is a synchronous TTL/CMOS-compatible input
that enables/disables the outputs based upon the
input to this pin. The enable function is synchronous
so that the clock outputs will be enabled or disabled
following a rising and a falling edge of the input clock.
Refer to Figure 1c. Internal 25kꢀ pull-up resistor
defaults the input to logic HIGH if left open. Input
switching threshold is VCC/2.
If the input clock fails to a floating, static, or extremely
low signal swing such that the voltage across the input
pair is significantly less than 100mV, FSI
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SY89468U
Timing Diagrams
Figure 1a. SEL-to-Q Delay
Figure 1b. Fail-Safe Feature
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SY89468U
Figure 1c. Enable Output Timing Diagram
Figure 1d. Propagation Delay
Figure 1e. Setup and Hold Time
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SY89468U
Typical Operating Characteristics
VCC = 2.5V, GND = 0V, VIN = 200mV, RL = 100ꢀ across the outputs; TA = 25°C, unless otherwise stated.
January 2008
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SY89468U
Functional Characteristics
VCC = 2.5V, GND = 0V, VIN = 200mV, RL = 100ꢀ across the outputs; TA = 25°C, unless otherwise stated.
January 2008
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SY89468U
Single-Ended and Differential Swings
Figure 2b. Differential Voltage Swing
Figure 2a. Single-Ended Voltage Swing
Input Stage
Figure 3. Simplified Differential Input Stage
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SY89468U
Input Interface Applications
Option: may connect VT to VCC
Figure 4b. LVPECL Interface
(AC-Coupled)
Figure 4c. CML Interface
(DC-Coupled)
Figure 4a. LVPECL Interface
(DC-Coupled)
Figure 4d. CML Interface
(AC-Coupled)
Figure 4e. LVDS Interface
(DC-Coupled)
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SY89468U
LVDS Output Interface Applications
LVDS specifies a small swing of 325mV typical, on a
nominal 1.2V common mode above ground. The
common mode voltage has tight limits to permit large
variations in the ground between an LVDS driver and
receiver. Also, change in common mode voltage, as a
function of data input, is kept to a minimum, to keep
EMI low.
Figure 5b. LVDS Common Mode Measurement
Figure 5a. LVDS Differential Measurement
Related Product and Support Documentation
Part Number
Function
Data Sheet Link
SY89467U
Precision LVPECL 1:20 Fanout MUX with 2:1
MUX and internal termination with Fail Safe
Input
http://www.micrel.com/_PDF/HBW/sy89467u.pdf
MLF® Application Note
www.amkor.com/products/notes_papers/MLFAppNote.pdf
www.micrel.com/product-info/products/solutions.shtml
HBW
Solutions
New Products and Applications
January 2008
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Micrel, Inc.
SY89468U
Package Information
64-Pin EPAD-TQFP (T64-1)
Packages Notes:
1. Package meets Level 2 Moisture Sensitivity Classification.
2. All parts are dry-packed before shipment.
3. Exposed pad must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel
for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a
product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended
for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant
injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk
and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
© 2007 Micrel, Inc.
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