T555714-PP [MICROCHIP]
Telecom Circuit;
| 型号： | T555714-PP |
| 厂家： | 
MICROCHIP |
| 描述： | Telecom Circuit 电信 电信集成电路 |
| 文件： | 总29页 (文件大小：506K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Contactless Read/Write Data Transmission
• Radio Frequency fRF from 100 kHz to 150 kHz
• e5550 Binary Compatible or T5557 Extended Mode
• Small Size, Configurable for ISO/IEC 11784/785 Compatibility
• 75 pF On-chip Resonant Capacitor (Mask Option)
• 7 x 32-bit EEPROM Data Memory Including 32-bit Password
• Separate 64-bit memory for Traceability Data
• 32-bit Configuration Register in EEPROM to Setup:
– Data Rate
- RF/2 to RF/128, Binary Selectable or
- Fixed e5550 Data Rates
– Modulation/Coding
- FSK, PSK, Manchester, Biphase, NRZ
– Other Options
- Password Mode
- Max Block Feature
- Answer-On-Request (AOR) Mode
- Inverse Data Output
Multifunctional
330-bit
Read/Write
RF-Identification
IC
- Direct Access Mode
- Sequence Terminator(s)
- Write Protection (Through Lock-bit per Block)
- Fast Write Method (5 kbps versus 2 kbps)
- OTP Functionality
T5557
- POR Delay up to 67 ms
Description
ꢀ
The T5557 is a contactless R/W IDentification IC (IDIC ) for applications in the
125 kHz frequency range. A single coil, connected to the chip, serves as the IC’s
power supply and bi-directional communication interface. The antenna and chip
together form a transponder or tag.
The on-chip 330-bit EEPROM (10 blocks, 33 bits each) can be read and written block-
wise from a reader. Block 0 is reserved for setting the operation modes of the T5557
tag. Block 7 may contain a password to prevent unauthorized writing.
ꢁ
Data is transmitted from the IDIC using load modulation. This is achieved by damping
the RF field with a resistive load between the two terminals Coil 1 and Coil 2. The IC
receives and decodes 100% amplitude modulated (OOK) pulse interval encoded bit
streams from the base station or reader.
System Block Diagram
Figure 1. RFID System Using T5557 Tag
Transponder
Power
Reader
or
Base station
Memory
*
Data
T5557
Mask option
*
Rev. 4517C–RFID–10/02
T5557 –
Figure 2. Block Diagram
Building Blocks
POR
Modulator
Coil 1
Mode register
Memory
*
(330 bit EEPROM)
Controller
Test logic
Input register
HV generator
Coil 2
* Mask option
Analog Front End (AFE)
The AFE includes all circuits which are directly connected to the coil. It generates the
IC’s power supply and handles the bi-directional data communication with the reader. It
consists of the following blocks:
•
•
•
•
•
Rectifier to generate a DC supply voltage from the AC coil voltage
Clock extractor
Switchable load between Coil 1/Coil 2 for data transmission from tag to the reader
Field gap detector for data transmission from the base station to the tag
ESD protection circuitry
Data-rate Generator
The data rate is binary programmable to operate at any data rate between RF/2 and
RF/128 or equal to any of the fixed e5550/e5551 and T5554 bitrates (RF/8, RF/16,
RF/32, RF/40, RF/50, RF/64, RF/100 and RF/128).
Write Decoder
HV Generator
DC Supply
This function decodes the write gaps and verifies the validity of the data stream
according to the Atmel e555x write method (pulse interval encoding).
This on-chip charge pump circuit generates the high voltage required for programming
of the EEPROM.
Power is externally supplied to the IDIC via the two coil connections. The IC rectifies and
regulates this RF source and uses it to generate its supply voltage.
2
T5557
4517C–RFID–10/02
T5557
Power-On Reset (POR)
This circuit delays the IDIC functionality until an acceptable voltage threshold has been
reached.
Clock Extraction
Controller
The clock extraction circuit uses the external RF signal as its internal clock source.
The control-logic module executes the following functions:
•
Load-mode register with configuration data from EEPROM block 0 after power-on
and also during reading
•
•
•
Control memory access (read, write)
Handle write data transmission and write error modes
The first two bits of the reader to tag data stream are the opcode, e.g., write, direct
access or reset
•
In password mode, the 32 bits received after the opcode are compared with the
password stored in memory block 7
Mode Register
The mode register stores the configuration data from the EEPROM block 0. It is
continually refreshed at the start of every block read and (re-)loaded after any POR
event or reset command. On delivery the mode register is preprogrammed with the
value ‘0014 8000’h which corresponds to continuous read of block 0, Manchester
coded, RF/64.
Figure 3. Block 0 Configuration Mapping – e5550 Compatibility Mode
L
1 2 3
4
0
5 6 7
8
0
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
0
1
1
0
0
0
0
0
0
0
0
0
0
Safer Key
Data
Modulation
PSK-
CF
MAX-
Note 1), 2)
Bit Rate
BLOCK
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
RF/2
RF/4
RF/8
Res.
RF/8
RF/16
RF/32
RF/40
RF/50
RF/64
0 Unlocked
1 Locked
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
Direct
PSK1
PSK2
PSK3
FSK1
FSK2
FSK1a
FSK2a
RF/100 1
RF/128
1
Manchester
Biphase('50)
Reserved
1) If Master Key = 6 then test mode write commands are ignored
2) If Master Key <> 6 or 9 then extended function mode is disabled
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4517C–RFID–10/02
Modulator
The modulator consists of data encoders for the following basic types of modulation:
Table 1. Types of e5550-compatible Modulation Modes
Mode
Direct Data Output
FSK/8-/5
FSK1a (1)
FSK2a (1)
FSK1 (1)
FSK2 (1)
PSK1 (2)
PSK2 (2)
PSK3 (2)
Manchester
Biphase
NRZ
‘0’ = rf/8;
‘0’ = rf/8;
‘0’ = rf/5;
‘0’ = rf/10;
‘1’ = rf/5
‘1’ = rf/10
‘1’ = rf/8
1’ = rf/8
FSK/8-/10
FSK/5-/8
FSK/10-/8
Phase change when input changes
Phase change on bit clock if input high
Phase change on rising edge of input
‘0’ = falling edge, ‘1’ = rising edge
‘1’ creates an additional mid-bit change
‘1’ = damping on, ‘0’ = damping off
Notes: 1. A common multiple of bitrate and FSK frequencies is recommended.
2. In PSK mode the selected data rate has to be an integer multiple of the PSK
sub-carrier frequency.
Memory
The memory is a 330-bit EEPROM, which is arranged in 10 blocks of 33 bits each. All 33
bits of a block, including the lock bit, are programmed simultaneously.
Block 0 of page 0 contains the mode/configuration data, which is not transmitted during
regular-read operations. Block 7 of page 0 may be used as a write protection password.
Bit 0 of every block is the lock bit for that block. Once locked, the block (including the
lock bit itself) is not re-programmable through the RF field again.
Blocks 1 and 2 of page 1 contain traceability data and are transmitted with the modula-
tion parameters defined in the configuration register after the opcode ’11’ is issued by
the reader (see Figure 11). These tracebility data blocks are programmed and locked by
Atmel.
Figure 4. Memory Map
0 1
32
Block 2
Block 1
1
1
Traceability data
Traceability data
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
L
L
L
L
L
L
L
L
User data or password
User data
User data
User data
User data
User data
User data
Configuration data
32 bits
Not transmitted
4
T5557
4517C–RFID–10/02
T5557
Traceability Data
Structure
Blocks 1 and 2 of page 1 contain the traceability data and are programmed and locked
by Atmel during production testing. The most significant byte of block 1 is fixed to
‘E0’hex, the allocation class (ACL) as defined in ISO/IEC 15963-1. The second byte is
therefore defined as the manufacturer’s ID of Atmel (= ‘15’hex). The following 8 bits are
used as IC reference byte (ICR - Bits 47 to 40). The 3 most significant bits define the IC
and/or foundry version of the T5557. The lower 5 bits are by default reset (=00) as the
Atmel standard value. Other values may be assigned on request to high volume custom-
ers as tag issuer identification.
The lower 40 bits of the data encode the traceability information of Atmel and conform to
a unique numbering system. These 40 data bits are divided in two sub-groups, a 5-digit
lot ID number, the binary wafer number (5 bit) concatenated with the sequential die
number per wafer.
Figure 5. T5557 Traceability Data Structure
Traceability
12
' 557 '
20
31
32
1
1
...
12 13 ... 18 19
wafer #
...
die on wafer #
MSN LotID
Block 2
Block 1
LotID
ACL
...
MFC
...
ICR
...
8
9
16 17
24 25
...
32
' 41 '
8
Example:
' E0 '
' 15 '
' 00 '
ACL
MFC
ICR
Allocation class as defined in ISO/IEC 15963-1 = E0h
Manufacturer code of Atmel Corporation as defined in ISO/IEC 7816-6 = 15h
IC reference of silicon and/or tag manufacturer
Top 3 bits define IC revision
Lower 5 bits may contain a customer ID code on request
Manufacturer serial number consists of:
5-digit lot number, e.g., ’38765’
MSN
LotID
DPW
20 bits encoded as sequential die per wafer number (with top 5 bits = wafer#)
Operating the T5557
Initialization and
POR Delay
The Power-On-Reset (POR) circuit remains active until an adequate voltage threshold
has been reached. This in turn triggers the default start-up delay sequence. During this
configuration period of about 192 field clocks, the T5557 is initialized with the configura-
tion data stored in EEPROM block 0. During initialization of the configuration block 0, all
T55570x variants the load damping is active permanently (see Figure 10). The T55571x
types (without damping option) achieve a longer read range based on the lower activa-
tion field strength.
If the POR-delay bit is reset, no additional delay is observed after the configuration
period. Tag modulation in regular-read mode will be observed about 3 ms after entering
the RF field. If the POR delay bit is set, the T5557 remains in a permanent damping
state until 8190 internal field clocks have elapsed.
T
INIT = (192 + 8190 P POR delay) PꢀTC Wꢀ67 ms ; TC = 8 µs at 125 kHz
5
4517C–RFID–10/02
Any field gap occurring during this initialization phase will restart the complete
sequence. After this initialization time the T5557 enters regular-read mode and modula-
tion starts automatically using the parameters defined in the configuration register.
Tag to Reader
Communication
During normal operation, the data stored within the EEPROM is cycled and the Coil 1,
Coil 2 terminals are load modulated. This resistive load modulation can be detected at
the reader module.
Regular-read Mode
In regular-read mode data from the memory is transmitted serially, starting with block 1,
bit 1, up to the last block (e.g., 7), bit 32. The last block which will be read is defined by
the mode parameter field MAXBLK in EEPROM block 0. When the data block
addressed by MAXBLK has been read, data transmission restarts with block 1, bit 1.
The user may limit the cyclic datastream in regular-read mode by setting the MAXBLK
between 0 and 7 (representing each of the 8 data blocks). If set to 7, blocks 1 through 7
can be read. If set to 1, only block 1 is transmitted continously. If set to 0, the contents of
the configuration block (normally not transmitted) can be read. In the case of MAXBLK =
0 or 1, regular-read mode can not be distinguished from block-read mode.
Figure 6. Examples for Different MAXBLK Settings
Block 1
Loading block 0
Block 4
Block 5
Block 1
Block 2
Block 2
Block 1
MAXBLK = 5
MAXBLK = 2
MAXBLK = 0
0
Block 1
Block 2
Block 1
0
Loading block 0
Block 0
Block 0
Block 0
Block 0
Block 0
0
Loading block 0
Every time the T5557 enters regular- or block-read mode, the first bit transmitted is a
logical ‘0’. The data stream starts with block 1, bit 1, continues through MAXBLK, bit 32,
and cycles continuously if in regular-read mode .
Note:
This behavior is different from the original e555x and helps to decode PSK-modulated
data.
Block-read Mode
With the direct access command, the addressed block is repetitively read only. This
mode is called block-read mode. Direct access is entered by transmitting the page
access opcode (‘10’ or ‘11’), a single ‘0’ bit and the requested 3-bit block address when
the tag is in normal mode.
In password mode (PWD bit set), the direct access to a single block needs the valid
32-bit password to be transmitted after the page access opcode whereas a ‘0’ bit and
the 3-bit block address follow afterwards. In case the transmitted password does not
match with the contents of block 7, the T5557 tag returns to the regular-read mode.
Note:
A direct access to block 0 of page 1 will read the configuration data of block 0, page 0.
A direct access to bock 3 .. 7 of page 1 reads all data bits as zero.
e5550 Sequence
Terminator
The sequence terminator ST is a special damping pattern which is inserted before the
first block and may be used to synchronize the reader. This e5550-compatible sequence
terminator consists of 4 bit periods with underlaying data values of ‘1’. During the sec-
ond and the fourth bit period, modulation is switched off (Manchester encoding –
switched on). Biphase modulated data blocks need fixed leading and trailing bits in com-
bination with the sequence terminator to be identified reliable.
6
T5557
4517C–RFID–10/02
T5557
The sequence terminator may be individually enabled by setting of mode bit 29
(ST = ‘1’) in the e5550-compatibility mode (X-mode = ‘0’).
In the regular-read mode, the sequence terminator is inserted at the start of each
MAXBLK-limited read data stream.
In block-read mode – after any block-write or direct access command – or if MAXBLK
was set to 0 or 1, the sequence terminator is inserted before the transmission of the
selected block.
Especially this behavior is different to former e5550 – compatible ICs (T5551, T5554).
Figure 7. Read Data Stream with Sequence Terminator
No terminator
Block 1
Block 2
MAXBLK
Block 1
Block 2
Regular read mode
Sequence terminator
Sequence terminator
Block 1
Block 2
MAXBLK
Block 1
Block 2
ST = on
Figure 8. e5550-compatible Sequence Terminator Waveforms
Bit period
Last bit
Data '1'
Data '1'
Data '1'
Data '1'
Sequence
First Bit
Modulation
off (on)
Modulation
off (on)
Waveforms per different modulation types
bit '1' or '0'
VCoil
PP
Manchester
FSK
Sequence terminator not suitable for Biphase or PSK modulation
Reader to Tag
Communication
Data is written to the tag by interrupting the RF field with short field gaps (on-off keying)
in accordance with the e5550 write method. The time between two gaps encodes the
‘0/1’ information to be transmitted (pulse interval encoding). The duration of the gaps is
usually 50 µs to 150 µs. The time between two gaps is nominally 24 field clocks for a ‘0’
and 54 field clocks for a ‘1’. When there is no gap for more than 64 field clocks after a
previous gap, the T5557 exits the write mode. The tag starts with the command execu-
tion if the correct number of bits were received. If there is a failure detected the T5557
does not continue and will enter regular-read mode.
Start Gap
The initial gap is referred to as the start gap. This triggers the reader to tag communica-
tion. During this mode of operation, the receive damping is permanently enabled to ease
gap detection. The start gap may need to be longer than subsequent gaps in order to be
detected reliably.
7
4517C–RFID–10/02
A start gap will be accepted at any time after the mode register has been loaded
(O 3 ms). A single gap will not change the previously selected page (by former opcode
‘10’ or ‘11’).
Figure 9. Start of Reader to Tag Communication
Read mode
Write mode
d1
d0
S
gap
W
gap
Table 2. Write Data Decoding Scheme
Parameters
Start gap
Remark
Symbol
Sgap
Wgap
d0
Min.
Max.
50
Unit
FC
FC
FC
FC
10
8
Write gap
Normal write mode
‘0’ data
30
16
48
31
Write data in normal mode
‘1’ data
d1
63
Write Data Protocol
The T5557 expects to receive a dual bit opcode as the first two bits of a reader com-
mand sequence. There are three valid opcodes:
•
The opcodes ‘10’ and ‘11’ precede all block write and direct access operations for
page 0 and page 1
•
•
The RESET opcode ‘00’ initiates a POR cycle
The opcode ‘01’ precedes all test mode write operations. Any test mode access is
ignored after master key (bits 1..4) in block 0 has been set to ‘6’. Any further
modifications of the master key are prohibited by setting the lock bit of block 0 or the
OTP bit.
Writing has to follow these rules:
•
•
•
Standard write needs the opcode, the lock bit, 32 data bits and the 3-bit address
(38 bits total)
Protected write (PWD bit set) requires a valid 32-bit password between opcode and
data, address bits
For the AOR wake-up command an opcode and a valid password are necessary to
select and activate a specific tag
Note:
The data bits are read in the same order as written.
If the transmitted command sequence is invalid, the T5557 enters regular-read mode
with the previously selected page (by former opcode ‘10’ or ‘11’).
8
T5557
4517C–RFID–10/02
T5557
Figure 10. Complete Writing Sequence
Read mode
Write mode
Read mode
Block
address
T55571x
Programming
Opcode
Block data
T555701
Start gap
Lock bit
Block 0 loading
POR
Figure 11. T5557 Command Formats
Opcode
1p *
1p *
10
1
Data
32
2
Addr
0
Standard write
L
1
Password
Password
Password
32
1
Data
32
2
Addr
0
Protected write
L
0
1
32
32
AOR (wake-up command)
Direct access (PWD = 1)
Direct access (PWD = 0)
Page 0/1 regular read
Reset command
1p *
1p *
1p *
1
2
Addr 0
0
2 Addr 0
* p = page selector
00
Password
When password mode is active (PWD = 1), the first 32 bits after the opcode are
regarded as the password. They are compared bit by bit with the contents of block 7,
starting at bit 1. If the comparison fails, the T5557 will not program the memory, instead
it will restart in regular-read mode once the command transmission is finished.
Note:
In password mode, MAXBLK should be set to a value below 7 to prevent the password
from being transmitted by the T5557.
Each transmission of the direct access command (two opcode bits, 32 bits password, ‘0’
bit plus 3 address bits = 38 bits) needs about 18 ms. Testing all possible combinations
(about 4.3 billion) takes about two years.
Answer-On-Request
(AOR) Mode
When the AOR bit is set, the T5557 does not start modulation in the regular-read mode
after loading configuration block 0. The tag waits for a valid AOR data stream (“wake-up
command”) from the reader before modulation is enabled. The wake-up command con-
sists of the opcode (‘10‘) followed by a valid password. The selected tag will remain
active until the RF field is turned off or a new command with a different password is
transmitted which may address another tag in the RF field.
9
4517C–RFID–10/02
Table 3. T5557 — Modes of Operation
PWD
AOR
Behavior of Tag after Reset Command or POR
De-activate Function
Answer-On-Request (AOR) mode:
SꢀModulation starts after wake-up with a matching password
SꢀProgramming needs valid password
Command with non-matching password
deactivates the selected tag
1
1
Password mode:
1
0
0
SꢀModulation in regular-read mode starts after reset
SꢀProgramming and direct access needs valid password
Normal mode:
SꢀModulation in regular-read mode starts after reset
SꢀProgramming and direct access without password
--
Figure 12. Answer-On-Request (AOR) Mode
T55571x
T555701
Modulation
VCoil 1- Coil2
No modulation
because AOR = 1
Loading block 0
POR
AOR wake-up command (with valid PWD)
Figure 13. Coil Voltage after Programming of a Memory Block
VCoil 1- Coil 2
POR/
Read programmed
memory block
or
5.6 ms
Read block 1..MAXBLK
(Regular-read mode)
Write data to tag
Programming and
data verification
(Block-read mode)
single
gap
10
T5557
4517C–RFID–10/02
T5557
Figure 14. Anticollision Procedure Using AOR Mode
Reader
Tag
init tags with
AOR = '1' , PWD = '1'
Field OFF => ON
POWER ON RESET
read configuration
wait for tw > 2.5ms
enter AOR mode
wait for OPCODE + PWD
=> "wake up command"
"Select a single tag"
send OPCODE + PWD
=> "wake up command"
Receive damping ON
NO
Password correct ?
YES
send block 1...MAXBLK
decode data
NO
all tags read ?
YES
EXIT
11
4517C–RFID–10/02
Programming
When all necessary information has been received by the T5557, programming may
proceed. There is a clock delay between the end of the writing sequence and the start of
programming.
Typical programming time is 5.6 ms. This cycle includes a data verification read to grant
secure and correct programming. After programming was executed successfully, the
T5557 enters block-read mode transmitting the block just programmed (see Figure 13).
Note:
This timing and behavior is different from the e555x-family predecessors.
Error Handling
Several error conditions can be detected to ensure that only valid bits are programmed
into the EEPROM. There are two error types, which lead to two different actions.
Errors During Writing
The following detectable errors could occur during writing data into the T5557:
•
•
•
Wrong number of field clocks between two gaps (i.e., not a valid ‘1’ or ‘0’ pulse
stream)
Password mode is activated and the password does not match the contents of
block 7
The number of bits received in the command sequence is incorrect
Valid bit counts accepted by the T5557 are:
Password write
70 bits (PWD = 1)
38 bits (PWD = 0)
34 bits (PWD = 1)
38 bits (PWD = 1)
6 bits (PWD = 0)
2 bits
Standard write
AOR wake up
Direct access with PWD
Direct access
Reset command
Page 0/1 regular-read
2 bits
If any of these erroneous conditions were detected, the T5557 enters regular-read
mode, starting with block 1 of the page defined in the command sequence.
Errors Before/During
Programming
If the command sequence was received successfully, the following error could still
prevent programming:
•
•
The lock bit of the addressed block is set already
In case of a locked block, programming mode will not be entered. The T5557 reverts
to block-read mode continuously transmitting the currently addressed block.
If the command sequence is validated and the addressed block is not write protected,
the new data will be programmed into the EEPROM memory. The new state of the block
write protection bit (lock bit) will be programmed at the same time accordingly.
Each programming cycle consists of 4 consecutive steps: erase block, erase verification
(data = ‘0’), programming, write verification (corresponding data bits = ‘1’).
•
If a data verification error is detected after an executed data block programming, the
tag will stop modulation (modulation defeat) until a new command is transmitted.
12
T5557
4517C–RFID–10/02
T5557
Figure 15. T5557 Functional Diagram
Power-on reset
* p = page selector
AOR = 1
Setup modes
AOR mode
AOR = 0
Regular-read mode
addr = 1 .. maxblk
Page 0 or 1
Page 0
Block-read mode
gap
Start
Gap
addr = current
gap
command mode
Direct access OP (1p)*
OP (1p)*
Command decode
OP(11..)
single gap
Modulation defeat
Page 1
Page 0
OP(10..)
OP(00)
OP(01)
Write
OP(1p)*
Reset
Test-mode
to page 0
if master key <> 6
Write
fail
fail
fail
data = old
data = old
data = old
Number of bits
Password check
Lock bit check
Data verification failed
ok
data = new
Program & Verify
T5557 in Extended
Mode (X-mode)
In general, the block 0 setting of the master key (bits 1 to 4) to the value ‘6’ or ‘9’
together with the X-mode bit will enable the extended mode functions.
•
•
Master key = ‘9’: Test mode access and extended mode are both enabled.
Master key = ‘6’: Any test mode access will be denied but the extended mode is still
enabled.
Any other master key setting will prevent the activation of the T5557 extended mode
options, even when the X-mode bit is set.
Binary Bit-rate Generator In extended mode the data rate is binary programmable to operate at any data rate
between RF/2 and RF/128 as given in the formula below.
Data rate = RF/(2n+2)
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4517C–RFID–10/02
OTP Functionality
If the OTP bit is set to ‘1’, all memory blocks are write protected and behave as if all lock
bits are set to 1. If the master key is set to ‘6’ additionally, the T5557 mode of operation
is locked forever (= OTP functionality).
If the master key is set to ‘9’, the test-mode access allows the re-configuration of the tag
again.
Figure 16. Block 0 — Configuration Map in Extended Mode (X-mode)
L
1
1
2
0
3 4
5
0
6
0
7 8 9 10 11 12 13 14 15 16 17 18 19 2021 22 23 2425 26 27 2829 30 31 32
0
1
0
0
1
n5 n4 n3 n2 n1 n0
Master Key
Modulation
PSK-
CF
MAX-
Note 1), 2)
BLOCK
Data Bit Rate
0
0
1
1
0
1
0
1
RF/2
RF/4
RF/8
Res.
RF/(2n+2)
Direct
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
PSK1
PSK2
PSK3
FSK1
FSK2
0
1
Unlocked
Locked
Manchester
Biphase ('50) 1
Biphase ('57) 1
1) If Master Key = 6 and bit 15 set, then test-mode access is disabled and extended mode is active
2) If Master Key = 9 and bit 15 set, then extended mode is enabled
Table 4. T5557 Types of Modulation in Extended Mode
Mode
Direct Data Output Encoding
Inverse Data Output Encoding
FSK1 (1)
FSK/5-/8
‘0’ = RF/5;
‘1’ = RF/8
FSK/8-/5
‘0’ = RF/8;
‘1’ = RF/5
(= FSK1a)
(= FSK2a)
FSK2 (1)
FSK/10-/8
‘0’ = RF/10; ‘1’ = RF/8
FSK/8-/10 ‘0’ = RF/8;
‘1’ = RF/10
PSK1 (2)
Phase change when input changes
Phase change on bit clock if input high
Phase change on rising edge of input
‘0’ = falling edge, ‘1’= rising edge on mid-bit
‘1’ creates an additional mid-bit change
‘0’ creates an additional mid-bit change
‘1’= damping on, ‘0’= damping off
Phase change when input changes
Phase change on bit clock if input low
Phase change on falling edge of input
‘1’ = falling edge, ‘1’= rising edge on mid-bit
‘0’ creates an additional mid-bit change
‘1’ creates an additional mid-bit change
‘0’= damping on, ‘1’= damping off
PSK2 (2)
PSK3 (2)
Manchester
Biphase 1 (’50)
Biphase 2 (’57)
NRZ
Notes: 1. A common multiple of bitrate and FSK frequencies is recommended.
2. In PSK mode the selected data rate has to be an integer multiple of the PSK sub-carrier frequency.
14
T5557
4517C–RFID–10/02
T5557
Sequence Start Marker
Figure 17. T5557 Sequence Start Marker in Extended Mode
Sequence Start Marker
10
10
Block n
Block 1
01
Block n
10
Block n
01
Block n
10
Block n
01
10
Block-read mode
Block 2
MAXBLK 01
Block 1
Block 2
MAXBLK
Regular-read mode
The T5557 sequence start marker is a special damping pattern, which may be used to
synchronize the reader. The sequence start marker consists of two bits (‘01’ or ‘10’)
which are inserted as header before the first block to be transmitted if the bit 29 in
extended mode ist set. At the start of a new block sequence, the value of the two bits is
inverted.
Inverse Data Output
The T5557 supports in its extended mode (X-mode) an inverse data output option. If
inverse data is enabled, the modulator as shown in figure 18 works on inverted data
(see Table 4). This function is supported for all basic types of encoding.
Figure 18. Data Encoder for Inverse Data Output
PSK1
PSK2
PSK3
Intern out
data
D
Direct/NRZ
Data output
XOR
Sync
Mux
FSK1
FSK2
Data clock
CLK
R
Manchester
Biphase
Inverse data output
Modulator
Fast Write
In the optional fast write mode the time between two gaps is nominally 12 field clocks for
a ‘0’ and 27 field clocks for a ‘1’. When there is no gap for more than 32 field clocks after
a previous gap, the T5557 will exit the write mode. Please refer to Table 5 and Figure 8.
Table 5. Fast Write Data Decoding Schemes
Parameters
Remark
–
Symbol
Sgap
Wngap
Wfgap
d0
Min.
10
8
Max.
50
Unit
FC
FC
FC
FC
FC
FC
FC
Start gap
Normal write mode
Fast write mode
‘0’ data
30
Write gap
8
20
16
48
8
31
Write data in
normal mode
‘1’ data
d1
63
‘0’ data
d0
15
Write data in fast
mode
‘1’ data
d1
24
31
15
4517C–RFID–10/02
Figure 19. Example of Manchester Coding with Data
Figure 20. Example of Biphase Coding with Data Rate
Rate RF/16
RF/16
16
T5557
4517C–RFID–10/02
T5557
Figure 21. Example: FSK1a Coding with Data Rate
Figure 22. Example of PSK1 Coding with Data Rate
RF/16
RF/40, Subcarrier f0 = RF/8, f1 = RF/5
17
4517C–RFID–10/02
Figure 23. Example of PSK2 Coding with Data Rate
Figure 24. Example of PSK3 Coding with Data Rate
RF/16
RF/16
18
T5557
4517C–RFID–10/02
T5557
Absolute Maximum Ratings
Parameters
Symbol
Value
Unit
Maximum DC current into Coil 1/Coil 2
Icoil
20
mA
Maximum AC current into Coil 1/Coil 2
f = 125 kHz
Icoil p
Ptot
20
mA
mW
V
Power dissipation (dice)
(free-air condition, time of application: 1 s)
100
Electrostatic discharge maximum to
MIL-Standard 883 C method 3015
Vmax
4000
Operating ambient temperature range
Tamb
Tstg
-40 to +85
°C
°C
Storage temperature range (data retention reduced)
-40 to +150
Electrical Characteristics
Tamb = +25°C; fcoil = 125 kHz; unless otherwise specified
No.
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Type*
1
RF frequency range
fRF
100
125
150
kHz
T
amb = 25°C (1)
2.1
2.2
2.3
3.1
3.2
1.5
2
3
4
ꢁA
ꢁA
ꢁA
V
T
Q
Q
Q
Q
(see Figure 24)
Supply current
Read – full temperature
range
(without current
consumed by the
external LC tank circuit)
IDD
Programming full
temperature range
25
3.6
40
POR threshold
(50 mV hysteresis)
3.2
4.0
Vclamp
Coil voltage (AC supply)
Read mode and write
command (2)
Program EEPROM (2)
Vcoil pp
6
8
V
3.3
4
Vclamp
3
V
Q
Q
Start-up time
V
coil pp = 6 V
tstartup
Vclamp
2.5
ms
10 mA current into
Coil 1/2
5
Clamp voltage
17
23
V
T
6.1
6.2
6.3
Vcoilpp = 6 V on test circuit
generator and
V mod pp
I mod pp
4.2
600
-6
4.8
V
T
T
modulation ON (3)
Modulation parameters
400
ꢁA
Thermal stability
Vmod/Tamb
mV/°C
Q
*) Type means: T: directly or indirectly tested during production; Q: guaranteed based on initial product qualification data
Notes: 1. IDD measurement setup R = 100 k; VCLK = Vcoil = 5 V: EEPROM programmed to 00 ... 000 (erase all); chip in modulation
defeat. IDD = (VOUTmax - VCLK)/R
2. Current into Coil 1/Coil 2 is limited to 10 mA. The damping circuitry has the same structure as the e5550. The damping
characteristics are defined by the internally limited supply voltage (= minimum AC coil voltage)
3. Vmod measurement setup: R = 2.3 k; VCLK = 3 V; setup with modulation enabled (see Figure 25).
4. Since EEPROM performance is influenced by assembly processes, Atmel confirms the parameters for DOW (tested dice
on uncutted wafer) delivery.
5. The tolerance of the on-chip resonance capacitor Cr is ±10% at 3ꢂ over whole production. The capacitor tolerance is
±3% at 3ꢂꢀon a wafer basis.
6. The tolerance of the microcodule resonance capacitor Cr is ±5% at 3ꢂ over whole production.
19
4517C–RFID–10/02
Electrical Characteristics
Tamb = +25°C; fcoil = 125 kHz; unless otherwise specified
No.
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Type*
From last command gap
to re-enter read mode
(64 + 648 internal clocks)
Erase all / Write all (4)
Top = 55 LC (4)
Top = 150 LC (4)
Top = 250 LC (4)
Mask option(5)
7
Programming time
Endurance
Tprog
5
5.7
6
ms
T
8
ncycle
tretention
tretention
tretention
Cr
100000
10
Cycles
Years
hrs
Q
9.1
9.2
9.3
10
20
50
Data retention
96
T
Q
T
24
hrs
Resonance capacitor
70
78
86
pF
Cr
Capacitance tolerance
Tamb
11.1
313.5
330
346.5
pF
T
Microdule capacitor
parameters
11.2
11.3
Temperature coefficient
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
*) Type means: T: directly or indirectly tested during production; Q: guaranteed based on initial product qualification data
Notes: 1. IDD measurement setup R = 100 k; VCLK = Vcoil = 5 V: EEPROM programmed to 00 ... 000 (erase all); chip in modulation
defeat. IDD = (VOUTmax - VCLK)/R
2. Current into Coil 1/Coil 2 is limited to 10 mA. The damping circuitry has the same structure as the e5550. The damping
characteristics are defined by the internally limited supply voltage (= minimum AC coil voltage)
3. Vmod measurement setup: R = 2.3 k; VCLK = 3 V; setup with modulation enabled (see Figure 25).
4. Since EEPROM performance is influenced by assembly processes, Atmel confirms the parameters for DOW (tested dice
on uncutted wafer) delivery.
5. The tolerance of the on-chip resonance capacitor Cr is ±10% at 3ꢂ over whole production. The capacitor tolerance is
±3% at 3ꢂꢀon a wafer basis.
6. The tolerance of the microcodule resonance capacitor Cr is ±5% at 3ꢂ over whole production.
Figure 25. Measurement Setup for IDD and Vmod
R
BAT68
-
Coil 1
T5557
Coil 2
750
750
VOUTmax
+
Substrate
V CLK
BAT68
20
T5557
4517C–RFID–10/02
T5557
Ordering Information (2)
x x x
T 5 5 5 7 a b M c c -
Package
- DDW
- DDT
Drawing
- Dice on wafer, 6" un-sawn wafer, thickness 300 µm
- Dice in Tray (waffle pack), thickness 300 µm
- Dice on solder bumped wafer, thickness 390 µm
Sn63Pb37 on 5 µm Ni/Au, height 70 µm
- SO8 Package
- DBW
see Figure 27
see Figure 28
see Figure 31
see Figure 29
see Figure 33
- TAS
- PAE
- PP
- MOA2 Micro-Module
- Plastic Transponder
(1)
Customer ID
- Atmel standard (corresponds to “00")
M01
11
- Customer ’X’ unique ID code (1)
- 2 Pads without on-chip C
see Figure 26
see Figure 27
see Figure 27
see Figure 29
see Figure 26
13
- 4 Pads without on-chip C
14
- 4 Pads with on-chip 75 pF
15
- Micro - Module with 330 pF
01
- 2 Pads without C; Damping during initialisation
Notes: 1. Unique customer ID code programming according to Figure 5 is linked to a minimum order quantity of 1 Mio parts per year.
2. For available order codes refer to Atmel Sales/Marketing.
Ordering Examples
(Recommended)
T555711-DDW Tested dice on unsawn 6” wafer, thickness 300 ꢀm, no on-chip
capacitor, no damping during POR initialisation;
especially for ISO 11784/785 and access control applications
21
4517C–RFID–10/02
Package Information
Figure 26. 2 Pad Layout for Wire Bonding
Dimensions in µm
124
994
149.5
87
125
C2
497
22
T5557
4517C–RFID–10/02
T5557
Figure 27. 4 Pad Flip-chip Version with 70 µm Solder Bumps
Dimensions in µm
124
994
97
60
157
107
100
97
C2
497
Figure 28. Solder bump on NiAu
PbSn
70µm
Ni
Passivation
AL bondpad
23
4517C–RFID–10/02
Figure 29. MOA2 Micromodule
24
T5557
4517C–RFID–10/02
T5557
Figure 30. Shipping Reel
41,4 to
Ø329,6
max 43,0
120° (3x)
R1,14
Ø13
2,3
Ø171
Ø175
16,7
2
2,2
25
4517C–RFID–10/02
Figure 31. SO8 Package
Package SO8
Dimensions in mm
5.2
4.8
5.00
4.85
3.7
1.4
0.25
0.2
0.4
3.8
0.10
1.27
6.15
5.85
3.81
8
5
technical drawings
according to DIN
specifications
1
4
Figure 32. Pinning SO8
Coil 2
NC
1
2
3
4
8
7
6
5
Coil 1
NC
NC
NC
NC
NC
26
T5557
4517C–RFID–10/02
T5557
Figure 33. Plastic Transponder
Dimensions in mm
27
4517C–RFID–10/02
Operating Characteristics Plastic Transponder
Tamb = 25°C, fres = 125 kHz unless otherwise specified; For all other parameters please refer to IC characteristics
No. Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
mH
pF
Typ
Inductance
L
C
4.0
Capacitor
386.1
120
390
125
13
393.9
130
Resonance frequency
Hpp = 20 A/m
fres
QLC
kHz
Quality factor
Q
Assembly temperature t < 5 min
Magnetic Field Strength (H)
Tass
175
°C
Max. field strength where
No influence to other
Hpp not
4
A/m
T
transponder does not modulate
transponders in the field
Tamb = -40LC
Hpp -40
Hpp 25
Hpp 85
Hpp
30
18
17
50
A/m
A/m
A/m
A/m
A/m
Q
T
Field strength for operation
T
amb = 25LC
amb = 85LC
Tamb = 25LC
T
Q
T
Programming mode
Maximum field strength
Hpp max
600
Q
Modulation Range (see also H-DV curve)
Modulation range
Hpp = 20 A/m
pp = 30 A/m
Hpp = 50 A/m
Hpp = 100 A/m
DV
4.0
6.0
8.0
8.0
V
H
28
T5557
4517C–RFID–10/02
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© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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4517C–RFID–10/02
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