T5753C-6AQJ-66 [MICROCHIP]
IC TX UHF ASK/FSK 8TSSOP;
| 型号： | T5753C-6AQJ-66 |
| 厂家： | 
MICROCHIP |
| 描述： | IC TX UHF ASK/FSK 8TSSOP 电信 光电二极管 电信集成电路 |
| 文件： | 总13页 (文件大小：633K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
T5753C
UHF ASK/FSK Transmitter
DATASHEET
Features
● Integrated PLL loop filter
● ESD protection also at ANT1/ANT2
(3kV HBM/150V MM; Except pin 2: 3kV HBM/100V MM)
● High output power (8.0dBm) with low supply current (9.0mA)
● Modulation scheme ASK/FSK
● FSK modulation is achieved by connecting an additional capacitor between the
XTAL load capacitor and the open drain output of the modulating microcontroller
● Easy to design-in due to excellent isolation of the PLL from the PA and power
supply
● Single Li-cell for power supply
● Supply voltage 2.0V to 4.0V in the temperature range of –40°C to +85°C/125°C
● Package TSSOP8L
● Single-ended antenna output with high efficient power amplifier
● CLK output for clocking the microcontroller
● One-chip solution with minimum external circuitry
● 125°C operation for tire pressure systems
4510L-RKE-03/14
1.
Description
The Atmel® T5753C is a PLL transmitter IC which has been developed for the demands of RF low-cost transmission
systems at data rates up to 32kBaud. The transmitting frequency range is 310MHz to 350MHz. It can be used in both FSK
and ASK systems.
Figure 1-1. System Block Diagram
UHF ASK/FSK
Remote control transmitter
UHF ASK/FSK
Remote control receiver
1 Li cell
Keys
T5753C
U3741B/
U3745B/
T5743/
1 to 3 Micro-
controller
Demod
IF Amp
Control
T5744
Encoder
ATARx9x
PLL
Antenna Antenna
XTO
VCO
LNA
PLL
XTO
LNA
VCO
2
T5753C [DATASHEET]
4510L–RKE–03/14
2.
Pin Configuration
Figure 2-1. Pinning TSSOP8L
T5753C
CLK
PA_ENABLE
ANT2
1
8
7
6
5
ENABLE
GND
VS
2
3
4
ANT1
XTAL
Table 2-1. Pin Description
Pin
Symbol
Function
Configuration
VS
Clock output signal for
microcontroller
The clock output frequency is set by
the crystal to fXTAL/4
100Ω
100Ω
CLK
1
CLK
PA_ENABLE
50kΩ
UREF = 1.1V
Switches on power amplifier, used
for ASK modulation
2
PA_ENABLE
20μA
ANT1
3
4
ANT2
ANT1
Emitter of antenna output stage
Open collector antenna output
ANT2
T5753C [DATASHEET]
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4510L–RKE–03/14
Table 2-1. Pin Description (Continued)
Pin
Symbol
Function
Configuration
VS
VS
1.5kΩ
1.2kΩ
5
XTAL
Connection for crystal
XTAL
182μA
6
7
VS
Supply voltage
Ground
See ESD protection circuitry (see Figure 4-5 on page 8)
See ESD protection circuitry (see Figure 4-5 on page 8)
GND
200kΩ
ENABLE
8
ENABLE
Enable input
Figure 2-2. Block Diagram
T5753C
Power up/down
f
CLK
ENABLE
4
1
8
7
f
32
PA_ENABLE
GND
2
PDF
CP
ANT2
VS
3
4
6
5
LF
ANT1
PA
VCO
XTO
XTAL
PLL
4
T5753C [DATASHEET]
4510L–RKE–03/14
3.
General Description
This fully integrated PLL transmitter allows particularly simple, low-cost RF miniature transmitters to be assembled. The
VCO is locked to 32 fXTAL hence a 9.8438MHz crystal is needed for a 315MHz transmitter. All other PLL and VCO peripheral
elements are integrated.
The XTO is a series resonance oscillator so that only one capacitor together with a crystal connected in series to GND are
needed as external elements.
The crystal oscillator together with the PLL needs typically < 3 ms until the PLL is locked and the CLK output is stable. There
is a wait time of ≥ 3ms until the CLK is used for the microcontroller and the PA is switched on.
The power amplifier is an open-collector output delivering a current pulse which is nearly independent from the load
impedance. The delivered output power is hence controllable via the connected load impedance.
This output configuration enables a simple matching to any kind of antenna or to 50Ω. A high power efficiency of
η= Pout/(IS,PA VS) of 40% for the power amplifier results when an optimized load impedance of ZLoad = (255 + j192)Ω is used
at 3V supply voltage.
4.
Functional Description
If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming only a very small amount of current so
that a lithium cell used as power supply can work for several years.
With ENABLE = H the XTO, PLL and the CLK driver are switched on. If PA_ENABLE remains L only the PLL and the XTO is
running and the CLK signal is delivered to the microcontroller. The VCO locks to 32 times the XTO frequency.
With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver and the power amplifier are on. With PA_ENABLE the
power amplifier can be switched on and off, which is used to perform the ASK modulation.
4.1
4.2
ASK Transmission
The Atmel® T5753C is activated by ENABLE = H. PA_ENABLE must remain L for typically ≥ 3 ms, then the CLK signal can
be taken to clock the microcontroller and the output power can be modulated by means of pin PA_ENABLE. After
transmission PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The Atmel T5753C is
switched back to standby mode with ENABLE = L.
FSK Transmission
The Atmel T5753C is activated by ENABLE = H. PA_ENABLE must remain L for typically ≥ 3ms, then the CLK signal can be
taken to clock the microcontroller and the power amplifier is switched on with PA_ENABLE = H. The chip is then ready for
FSK modulation. The microcontroller starts to switch on and off the capacitor between the XTAL load capacitor and GND
with an open-drain output port, thus changing the reference frequency of the PLL. If the switch is closed, the output
frequency is lower than if the switch is open. After transmission PA_ENABLE is switched to L and the microcontroller
switches back to internal clocking. The Atmel T5753C is switched back to standby mode with ENABLE = L.
The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the following tolerances are
considered.
Figure 4-1. Tolerances of Frequency Modulation
VS
CStray1
CStray2
LM
C4
XTAL
CM
RS
C0
Crystal equivalent circuit
C5
CSwitch
Using C4 = 8.2pF ±5%, C5 = 10pF ±5%, a switch port with CSwitch = 3pF ±10%, stray capacitances on each side of the crystal
of CStray1 = CStray2 = 1pF ±10%, a parallel capacitance of the crystal of C0 = 3.2pF ±10% and a crystal with CM = 13fF ±10%,
an FSK deviation of ±21.5kHz typical with worst case tolerances of ±16.25kHz to ±28.01kHz results.
T5753C [DATASHEET]
5
4510L–RKE–03/14
4.3
CLK Output
An output CLK signal is provided for a connected microcontroller, the delivered signal is CMOS compatible if the load
capacitance is lower than 10pF.
4.3.1 Clock Pulse Take-over
The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel®’s ATARx9x has the special feature of
starting with an integrated RC-oscillator to switch on the Atmel T5753C with ENABLE = H, and after 3 ms to assume the
clock signal of the transmission IC, so that the message can be sent with crystal accuracy.
4.3.2 Output Matching and Power Setting
The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load
impedance of ZLoad,opt = (255 + j192)Ω. There must be a low resistive path to VS to deliver the DC current.
The delivered current pulse of the power amplifier is 9 mA and the maximum output power is delivered to a resistive load of
400Ω if the 1.0pF output capacitance of the power amplifier is compensated by the load impedance.
An optimum load impedance of:
Z
Load = 400Ω || j/(2 × π 1.0pF) = (255 + j192)Ωthus results for the maximum output power of 8dBm.
The load impedance is defined as the impedance seen from the Atmel T5753C’s ANT1, ANT2 into the matching network. Do
not confuse this large signal load impedance with a small signal input impedance delivered as input characteristic of RF
amplifiers and measured from the application into the IC instead of from the IC into the application for a power amplifier.
Less output power is achieved by lowering the real parallel part of 400Ω where the parallel imaginary part should be kept
constant.
Output power measurement can be done with the circuit of Figure 4-2. Note that the component values must be changed to
compensate the individual board parasitics until the Atmel T5753C has the right load impedance ZLoad,opt = (255 + j192)Ω.
Also the damping of the cable used to measure the output power must be calibrated out.
Figure 4-2. Output Power Measurement at f = 315MHz
VS
C1
1nF
L1 56nH
C2
3.3pF
Power
meter
Z = 50Ω
ANT1
ZLopt
Rin
50Ω
ANT2
Note:
For 345MHz C2 has to be changed to 2.7pF
4.4
Application Circuit
For the blocking of the supply voltage a capacitor value of C3 = 68nF/X7R is recommended (see Figure 4-3 on page 7 and
Figure 4-4 on page 8). C1 and C2 are used to match the loop antenna to the power amplifier where C1 typically is 22pF/NP0
and C2 is 10.8pF/NP0 (18pF + 27pF in series); for C2 two capacitors in series should be used to achieve a better tolerance
value and to have the possibility to realize the ZLoad,opt by using standard valued capacitors.
C1 forms together with the pins of Atmel T5753C and the PCB board wires a series resonance loop that suppresses the 1st
harmonic, hence the position of C1 on the PCB is important. Normally the best suppression is achieved when C1 is placed as
close as possible to the pins ANT1 and ANT2.
The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop antenna is too high.
L1 ([50nH to 100nH) can be printed on PCB. C4 should be selected that the XTO runs on the load resonance frequency of
the crystal. Normally, a value of 12pF results for a 15pF load-capacitance crystal.
6
T5753C [DATASHEET]
4510L–RKE–03/14
Figure 4-3. ASK Application Circuit
S1
VDD
VSS
BPXY
BPXY
BPXY
OSC1
ATARx9x
VS
1
S2
20
BPXY
7
T5753C
Power up/down
CLK
ENABLE
f
4
1
2
8
7
f
32
PA_ENABLE
GND
PDF
CP
C3
C2
ANT2
VS
3
4
6
5
VS
Loop
Antenna
LF
C1
ANT1
XTAL
XTAL
PA
VCO
XTO
PLL
L1
C4
VS
T5753C [DATASHEET]
7
4510L–RKE–03/14
Figure 4-4. FSK Application Circuit
S1
VDD
BPXY
ATARx9x
VS
1
20
18
S2
VSS
BPXY
BPXY
OSC1
BP42/T2O
BPXY
7
T5753C
Power up/down
CLK
ENABLE
f
4
1
2
8
7
f
32
PA_ENABLE
GND
PDF
CP
C3
C2
ANT2
VS
3
4
6
5
Loop
Antenna
LF
VS
C1
C5
XTAL
ANT1
XTAL
PA
VCO
XTO
PLL
L1
C4
VS
Figure 4-5. ESD Protection Circuit
VS
ANT1
ANT2
CLK
PA_ENABLE
XTAL
ENABLE
GND
8
T5753C [DATASHEET]
4510L–RKE–03/14
5.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Minimum
Maximum
Unit
V
Supply voltage
VS
5
100
Power dissipation
Junction temperature
Storage temperature
Ambient temperature
Input voltage
Ptot
mW
°C
°C
°C
V
Tj
Tstg
150
–55
–55
–0.3
125
Tamb
125
(VS + 0.3)(1)
VmaxPA_ENABLE
Note:
1. If VS + 0.3 is higher than 3.7V, the maximum voltage will be reduced to 3.7V.
6.
Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient
RthJA
170
K/W
7.
Electrical Characteristics
VS = 2.0V to 4.0V, Tamb = –40°C to 125°C unless otherwise specified.
Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7).
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Power down,
VENABLE < 0.25V, –40°C to 85°C
VPA-ENABLE < 0.25V, –40°C to +125°C
VPA-ENABLE < 0.25V, 25°C
(100% correlation tested)
350
7
nA
µA
nA
Supply current
IS_Off
< 10
Power up, PA off, VS = 3V,
VENABLE > 1.7V, VPA-ENABLE < 0.25V
Supply current
Supply current
Output power
IS
3.7
9
4.8
11.6
10.5
mA
mA
Power up, VS = 3.0V,
IS_Transmit
PRef
VENABLE > 1.7V, VPA-ENABLE > 1.7V
VS = 3.0V, Tamb = 25°C,
f = 315MHz, ZLoad = (255 + j192)Ω
6.0
8.0
dBm
Tamb = –40°C to +85°C,
VS = 3.0V
VS = 2.0V
Output power variation for the full
temperature range
ΔPRef
ΔPRef
–1.5
–4.0
dB
dB
Tamb = –40°C to +125°C,
Output power variation for the full VS = 3.0V
ΔPRef
ΔPRef
–2.0
–4.5
dB
dB
temperature range
VS = 2.0V,
Out = PRef + ΔPRef
P
Achievable output-power range
Selectable by load impedance
POut_typ
0
8.0
dBm
fCLK = f0/128
Load capacitance at pin CLK = 10pF
fO ±1 × fCLK
fO ±4 × fCLK
Spurious emission
–55
–52
dBc
dBc
other spurious are lower
Note:
1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V.
T5753C [DATASHEET]
9
4510L–RKE–03/14
7.
Electrical Characteristics (Continued)
VS = 2.0V to 4.0V, Tamb = –40°C to 125°C unless otherwise specified.
Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7).
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
fXTO = f0/32
fXTAL = resonant frequency of the XTAL,
CM ≤ 10fF, load capacitance selected
accordingly
Oscillator frequency XTO
(= phase comparator frequency)
fXTO
Tamb = –40°C to +85°C,
Tamb = –40°C to +125°C
–30
–40
fXTAL
+30
+40
ppm
ppm
PLL loop bandwidth
250
–116
–86
kHz
Referred to fPC = fXT0,
25kHz distance to carrier
Phase noise of phase comparator
In loop phase noise PLL
Phase noise VCO
–110
–80
dBc/Hz
dBc/Hz
25kHz distance to carrier
at 1MHz
at 36MHz
–94
–125
–90
–121
dBc/Hz
dBc/Hz
Frequency range of VCO
fVCO
310
350
MHz
Clock output frequency (CMOS
microcontroller compatible)
f0/128
MHz
V0h
V0l
V
V
Voltage swing at pin CLK
CLoad ≤ 10pF
VS × 0.8
VS × 0.2
Series resonance R of the crystal
Capacitive load at pin XT0
Rs
110
7
Ω
pF
Duty cycle of the modulation signal =
50%
FSK modulation frequency rate
ASK modulation frequency rate
0
0
32
kHz
kHz
Duty cycle of the modulation signal =
50%
32
Low level input voltage
High level input voltage
Input current high
VIl
VIh
IIn
0.25
V
V
µA
ENABLE input
1.7
1.7
20
Low level input voltage
High level input voltage
Input current high
VIl
VIh
IIn
0.25
V
V
µA
(1)
PA_ENABLE input
VS
5
Note:
1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V.
10
T5753C [DATASHEET]
4510L–RKE–03/14
8.
Ordering Information
Extended Type Number
Package
TSSOP8L
TSSOP8L
Remarks
T5753C-6AQJ
T5753C-6APJ
Taped and reeled, Marking: 573C, Pb-free
Taped and reeled, Marking: 573C, small reel, Pb-free
Note:
1. J = –40°C to +125°C + lead-free
9.
Package Information
Dimensions in mm
3
0.1
3
0.1
+0.06
3.8 0.3
4.9 0.1
0.31-0.07
0.65 nom.
3 x 0.65 = 1.95 nom.
8
5
4
technical drawings
according to DIN
specifications
1
03/15/04
REV.
TITLE
DRAWING NO.
GPC
Package Drawing Contact:
packagedrawings@atmel.com
Package: TSSOP 8L
6.543-5083.01-4
2
T5753C [DATASHEET]
11
4510L–RKE–03/14
10. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
History
• T5753 in T5753C on all pages substituted
4510L-RKE-03/14
4510K-RKE-01/13
4510J-RKE-12/08
• Section 8 “Ordering Information” on page 11 updated
• Section “Features” on page 1 changed
• Section 8 “Ordering Information” on page 11 updated
• Put datasheet in the newest template
• Section 4.3.1 “Clock Pulse Take-over” on page 5 updated
• Put datasheet in the newest template
4510I-RKE-02/07
4510H-RKE-09/05
• Pb-free Logo on page 1 deleted
• Pb-free Logo on page 1 added
• Put datasheet in the newest template
• Section 1 “Description” on page 1 updated
4510G-RKE-02/05
4510F-RKE-02/05
• Figure title Figure 4-2 on page 6 updated
• Table “Electrical Characteristics” on pages 9 to 10 updated
• Table “Ordering Information” on page 11 updated
• Table “Absolute Maximum Ratings” (page 8): row “Input voltage” added
• Table “Absolute Maximum Ratings” (page 8): table note 1 added
• Table “Electrical Characteristics” (page 10): row “PA_ENABLE input” updated
• Table “Electrical Characteristics” (page 10): table note 1 added
• Table “Ordering Information” (page 11): Remarks updated
12
T5753C [DATASHEET]
4510L–RKE–03/14
X
X X X X
X
Atmel Corporation
1600 Technology Drive, San Jose, CA 95110 USA
T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
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© 2014 Atmel Corporation. / Rev.: Rev.: 4510L–RKE–03/14
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