TC8020K6-G-M937 [MICROCHIP]
MOSFET 6N/6P-CH 200V 56VQFN;
| 型号： | TC8020K6-G-M937 |
| 厂家： | 
MICROCHIP |
| 描述： | MOSFET 6N/6P-CH 200V 56VQFN 开关 晶体管 |
| 文件： | 总8页 (文件大小：644K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Supertex inc.
TC8020
Six Pair, N- and P-Channel
Enhancement-Mode MOSFET
Features
General Description
► High voltage, vertical DMOS technology
► Integrated gate-to-source resistor
► Integrated gate-to-source Zener diode
► Typical peak output +/-3.5A at 50V
► Low threshold, low on-resistance
► Low input & output capacitance
► Fast switching speeds
The Supertex TC8020 consists of six pairs of high voltage,
low threshold N- and P-channel MOSFETs in a 56-lead QFN
package. All MOSFETs have integrated gate-to-source resistors
and gate-to-source Zener diode clamps which are desired for
high voltage pulser applications. The complimentary, high-speed,
high voltage, gate-clamped N- and P-channel MOSFET pairs
utilize an advanced vertical DMOS structure and Supertex’s well-
proven silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities of bipolar
transistors and with the high input impedance and positive
temperature coefficient inherent in MOS devices.
► Electrically isolated N- and P-MOSFET pairs
Applications
► High voltage pulsers
► Amplifiers
► Buffers
► Piezoelectric transducer drivers
► General purpose line drivers
► Logic level interfaces
Characteristic of all MOS structures, this device is free from
thermal runaway and thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input and output capacitance, and fast switching
speeds are desired.
Typical Application
VPP2
VPP1
+3.3V
+12V
+12V
+12V
VLL/EN
AVDD
VDD1
VDD2
SP6 SP3 SP5 SP2 SP4
SP1
OP1A
ON1A
OP2A
ON2A
OP3A
ON3A
OP1B
ON2A
OP2B
ON2B
OP3B
ON3B
GP1
GN1
GP2
GN2
GP3
GN3
GP4
GN4
GP5
GN5
GP6
GN6
DP1
DN1
DP2
DN2
DP3
DN3
DP4
DN4
DP5
DN5
DP6
DN6
10nF
10nF
10nF
10nF
TX(A)
SELA
POSA
NEGA
POSB
NEGB
SELB
1.8 to 3.3V
CMOS
Input Logic
MD1715
TC8020
10nF
10nF
10nF
10nF
TX(B)
AGND GND AVSS(SUB)
VSS
PAD SN6 SN3 SN5 SN2 SN4 SN1
-12V
-12V
VNN2
VNN1
Supertex inc.
Doc.# DSFP-TC8020
C091112
www.supertex.com
TC8020
Ordering Information
Product Summary
BVDSS/BVDGS
RDS(ON)
(max) (Ω)
Part Number
Package Option
Packing
(V)
TC8020K6-G
-G indicates package is RoHS compliant (‘Green’)
56-Lead QFN (8x8)
250/Tray
N-Channel
P-Channel
N-Channel
8.0
P-Channel
200
-200
9.5
Pin Configuration
56
1
Absolute Maximum Ratings
Parameter
Value
Drain-to-source voltage
BVDSS
BVDGS
Drain-to-gate voltage
Operating and storage temperature
-55°C to +150°C
Absolute Maximum Ratings are those values beyond which damage to
the device may occur. Functional operation under these conditions is not
implied. Continuous operation of the device at the absolute rating level
may affect device reliability. All voltages are referenced to device ground.
*
Distance of 1.6mm from case for 10 seconds.
Thermal Characteristics
56-Lead QFN (K6)
Package
θja
Top View
56-Lead QFN (K6)
27OC/W
Note:
Package Marking
1.0oz, 4-layer, 3”x4” PCB
L = Lot Number
TC8020K6
LLLLLLLLL
YYWW
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
AAA CCC
= “Green” Packaging
Package may or may not include the following marks: Si or
56-Lead QFN (K6)
Supertex inc.
Doc.# DSFP-TC8020
C091112
www.supertex.com
2
TC8020
N-Channel Electrical Characteristics (TA = 25°C unless otherwise specified)
Sym
BVDSS
VGS(th)
Parameter
Min
200
1.0
-
Typ
Max
Units Conditions
Drain-to-source breakdown voltage
Gate threshold voltage
-
-
-
-
-
-
-
V
V
VGS = 0V, ID = 1.0mA
VGS = VDS, ID = 1.0mA
2.4
-4.5
26
ΔVGS(th) Change in VGS(th) with temperature
mV/OC VGS = VDS, ID = 1.0mA
RGS
Gate-to-source shunt resistor
Gate-to-source Zener voltage
5.0
13.2
-
KΩ
V
IGS = 100µA
VZGS
25
IGS = 2.0mA
10.0
µA
VDS = Max rating, VGS = 0V
IDSS
Zero gate voltage drain current
On-state drain current
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
-
-
1.0
mA
A
1.2
1.8
3.2
6.0
5.3
-
-
-
VGS = 4.5V, VDS = 25V
VGS = 10V, VDS = 25V
VGS = 4.5V, ID = 150mA
VGS = 10V, ID = 1.0A
ID(ON)
2.0
-
9.0
8.0
1.0
-
RDS(ON) Static drain-to-source on-state resistance
Ω
-
ΔRDS(ON) Change in RDS(ON) with temperature
-
%/OC VGS = 10V, ID =1.0A
GFS
CISS
COSS
CRSS
td(ON)
tr
Forward transconductance
Input capacitance
400
-
mmho VDS = 25V, ID = 500mA
-
-
-
-
-
-
-
-
-
50
18
7.0
-
-
VGS = 0V,
VDS = 25V,
f = 1.0MHz
Common source output capacitance
Reverse transfer capacitance
Turn-on delay time
-
pF
ns
-
10
15
20
15
1.8
-
VDD =25V,
ID = 500mA,
RGEN = 25Ω
Rise time
-
td(OFF)
tf
Turn-off delay time
-
Fall time
-
VSD
Diode forward voltage drop
Reverse recovery time
-
V
VGS = 0V, ISD = 500mA
VGS = 0V, ISD = 500mA
trr
300
ns
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
N-Channel Switching Waveforms and Test Circuit
10V
90%
VDD
RL
Input
10%
Pulse
0V
Generator
OUTPUT
D.U.T
t(ON)
td(ON)
t(OFF)
RGEN
tr
tf
td(OFF)
VDD
10%
10%
90%
Input
Output
90%
0V
Supertex inc.
Doc.# DSFP-TC8020
C091112
www.supertex.com
3
TC8020
P-Channel Electrical Characteristics (TA = 25°C unless otherwise specified)
Sym
BVDSS
VGS(th)
Parameter
Min
-200
-1.0
-
Typ
Max
Units Conditions
Drain-to-source breakdown voltage
Gate threshold voltage
-
-
-
-
-
-
-
V
V
VGS = 0V, ID = -1.0mA
VGS = VDS, ID = -1.0mA
-2.4
4.5
26
ΔVGS(th) Change in VGS(th) with temperature
mV/OC VGS = VDS, ID = -1.0mA
RGS
Gate-to-source shunt resistor
Gate-to-source Zener voltage
5.0
-13.2
-
KΩ
V
IGS = -100µA
VZGS
-24.0
-10
IGS = -2.0mA
µA
VDS = Max rating, VGS = 0V
IDSS
Zero gate voltage drain current
On-state drain current
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
-
-
-1.0
mA
A
-0.80
-2.00
-1.25
-
-
VGS = -4.5V, VDS = -25V
VGS = -10V, VDS = -25V
VGS = -4.5V, ID = -150mA
VGS = -10V, ID = -1.0A
VGS = -10V, ID =-1.0A
ID(ON)
-2.80
7.0
10
9.5
1.0
-
RDS(ON) Static drain-to-source on-state resistance
Ω
-
6.5
ΔRDS(ON) Change in RDS(ON) with temperature
-
-
-
%/OC
GFS
CISS
COSS
CRSS
td(ON)
tr
Forward transconductance
Input capacitance
400
mmho VDS = -25V, ID = -500mA
-
-
-
-
-
-
-
-
-
55
20
8.0
-
-
VGS = 0V,
VDS = -25V,
f = 1.0MHz
Common source output capacitance
Reverse transfer capacitance
Turn-on delay time
-
pF
ns
-
10
15
20
15
-1.8
-
VDD = -25V,
ID = -1.0A,
RGEN = 25Ω
Rise time
-
td(OFF)
tf
Turn-off delay time
-
Fall time
-
VSD
Diode forward voltage drop
Reverse recovery time
-
V
VGS = 0V, ISD = -500mA
VGS = 0V, ISD = -500mA
trr
300
ns
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
P-Channel Switching Waveforms and Test Circuit
0V
10%
Pulse
Generator
Input
-10V
90%
RGEN
D.U.T
t(ON)
td(ON)
t(OFF)
Input
tr
tf
td(OFF)
90% 90%
10%
Output
0V
Output
RL
VDD
10%
VDD
Supertex inc.
Doc.# DSFP-TC8020
C091112
www.supertex.com
4
TC8020
Test Circuit
+12V
VDD1
+12V
VDD2
+12V
AVDD
VPP1
SP1
VDD2
OP1
ON1
GP1
GN1
DP1
DN1
VDD2
VNN1
SN1
SP2
High Speed
Gate Buffers
VPP2
VLL/EN
VDD1
OP2
ON2
GP2
GN2
Control
DP2
DN2
SEL
POS
NEG
Logic
and
Level
VDD1
100Ω
Translation
VNN2
SN2
SP3
GND
High Speed
Gate Buffers
GP3
GN3
OP3
ON3
DP3
DN3
VSS
VDD1
SN3
MD1715
1 OF 2-CH
TC8020
6 of 12-FETs
PAD
GND
PAD AVSS
VSS
-12V
-12V
Supertex inc.
Doc.# DSFP-TC8020
C091112
www.supertex.com
5
TC8020
Circuit Pin Layout
GN1
GN2
NC
DN1
DP1
DN2
TX(A)
SELA
POSA
ON3A
GND
GND
OP3A
VSS
GN3
GP3
NC
DP2
DN3
DP3
NEGA
VLL/EN
AVDD
SN3
SN6
NC
SP3
SP6
MD1715
TC8020
AGND
GND
OP3B
VSS
AVSS
SELB
POSB
NEGB
DN6
DP6
DN5
GP6
GN6
NC
ON3B
GND
TX(B)
DP5
GN5
GN4
DN4
DP4
Pin Description
Pin
Function
Description
GN1
GN2
NC
1
Gate of N-MOSFET 1
Gate of N-MOSFET 2
No Connection
2
3
GN3
GP3
NC
4
Gate of N-MOSFET 3
Gate of P-MOSFET 3
No Connection
5
6
7
SN3
SN6
NC
Source of N-MOSFET 3
Source of N-MOSFET 6
No Connection
8
9
10
11
12
13
14
15
16
17
18
GP6
GN6
NC
Gate of P-MOSFET 6
Gate of N-MOSFET 6
No Connection
GN5
GN4
GP5
GP4
NC
Gate of N-MOSFET 5
Gate of N-MOSFET 4
Gate of P-MOSFET 5
Gate of P-MOSFET 4
No Connection
SN5
Source of N-MOSFET 5
Supertex inc.
Doc.# DSFP-TC8020
C091112
www.supertex.com
6
TC8020
Pin Description (cont.)
Pin
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Function
Description
NC
No Connection
SN4
NC
Source of N-MOSFET 4
No Connection
VSUB
NC
Die attachment substrate, must be grounded externally.
No Connection
SP4
NC
Source of P-MOSFET 4
No Connection
SP5
NC
Source of P-MOSFET 5
No Connection
NC
No Connection
DP4
DN4
DP5
DN5
DP6
DN6
SP6
SP3
DP3
DN3
DP2
DN2
DP1
DN1
NC
Drain of P-MOSFET 4
Drain of N-MOSFET 4
Drain of P-MOSFET 5
Drain of N-MOSFET 5
Drain of P-MOSFET 6
Drain of N-MOSFET 6
Source of P-MOSFET 6
Source of P-MOSFET 3
Drain of P-MOSFET 3
Drain of N-MOSFET 3
Drain of P-MOSFET 2
Drain of N-MOSFET 2
Drain of P-MOSFET 1
Drain of N-MOSFET 1
No Connection
NC
No Connection
SP2
NC
Source of P-MOSFET 2
No Connection
SP1
NC
Source of P-MOSFET 1
No Connection
VSUB
NC
Die attachment substrate, must be grounded externally.
No Connection
SN1
NC
Source of N-MOSFET 1
No Connection
SN2
NC
Source of N-MOSFET 2
No Connection
GP1
GP2
Gate of P-MOSFET 1
Gate of P-MOSFET 2
Note:
Thermal Pad must be grounded externally.
Supertex inc.
Doc.# DSFP-TC8020
C091112
www.supertex.com
7
TC8020
56-Lead QFN Package Outline (K6)
8.00x8.00mm body, 1.00mm height (max), 0.50mm pitch
D2
D
56
56
1
1
Note 1
(Index Area
D/2 x E/2)
Note 1
(Index Area
D/2 x E/2)
e
b
E
E2
View B
Bottom View
Top View
Note 3
θ
L
A3
A
Seating
Plane
L1
Note 2
A1
Side View
View B
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.
Symbol
A
A1
A3
b
D
D2
E
E2
e
L
L1
0.00
-
θ
0O
-
MIN
NOM
MAX
0.80
0.90
1.00
0.00
0.02
0.05
0.18
0.25
0.30
7.85*
2.75
7.85*
2.75
0.30
0.40
0.50
Dimension
(mm)
0.20
REF
0.50
BSC
8.00
5.70
8.00
5.70
8.15* 6.70† 8.15* 6.70†
0.15
14O
JEDEC Registration MO-220, Variation VLLD-2, Issue K, June 2006.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings are not to scale.
Supertex Doc.#: DSPD-56QFNK68X8P050, Version A031010.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2012 Supertex inc.All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
Doc.# DSFP-TC8020
C091112
8
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