USB3503/GL [MICROCHIP]
Bus Controller;
MICROCHIP 
USB3503
USB 2.0 HSIC High-Speed Hub Controller Optimized
for Portable Applications
• USB Port ESD Protection (DP/DM)
Features
- ±15kV (air and contact discharge)
• Integrated USB 2.0 Compatible 3-Port Hub.
• HSIC Upstream Port
- IEC 61000-4-2 level 4 ESD protection without
external devices
• Advanced power saving features
- 1 A Typical Standby Current
• 25-pin WLCS (1.97mm x 1.97mm Wafer Level
Chip Scale) Package - 0.4mm ball pitch
- Port goes into power saving state when no
devices are connected downstream
• 32-pin SQFN (5.0 mm x 5.0 mm) Package
- Port is shutdown when port is disabled.
- Digital core shut down in Standby Mode
Applications
The USB3503 is targeted for applications where more
than one USB port is required. As mobile devices add
more features and the systems become more complex
it is necessary to have more than one USB port to take
communicate with the internal and peripheral devices.
• Supports either Single-TT or Multi-TT configura-
tions for Full-Speed and Low-Speed connections.
• Enhanced configuration options available through
serial I2C Slave Port
- VID/PID/DID
• Mobile Phones
- String Descriptors
• Tablet Computers
- Configuration options for Hub.
• Ultra Mobile PCs
• Internal Default configuration option when serial
I2C host not available.
• MultiTRAKTM
• Digital Still Cameras
• Digital Video Camcorders
• Gaming Consoles
• PDAs
- Dedicated Transaction Translator per port.
• PortMap
• Portable Media Players
• GPS Personal Navigation Devices
• Media Players/Viewers
- Configurable port mapping and disable
sequencing.
• PortSwap
- Configurable differential intra-pair signal
swapping.
• PHYBoostTM
- Programmable USB transceiver drive
strength for recovering signal integrity
• VariSenseTM
- Programmable USB receiver sensitivity
• flexPWR® Technology
- Low current design ideal for battery powered
applications
• Internal supply switching provides low power
modes
• External 12, 19.2, 24, 25, 26, 27, 38.4, or 52 MHz
clock input
• Internal 3.3V & 1.2V Voltage Regulators for single
supply operation.
- External VBAT and 1.8V dual supply input
option
• Internal Short Circuit protection of USB differential
signal pins.
2011-2020 Microchip Technology Inc.
DS00001584C-page 1
USB3503
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
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DS00001584C-page 2
2011-2020 Microchip Technology Inc.
USB3503
Table of Contents
1.0 General Description ........................................................................................................................................................................ 4
2.0 Acronyms and Definitions ............................................................................................................................................................... 6
3.0 USB3503 Pin Definitions ................................................................................................................................................................. 7
4.0 Modes of Operation ...................................................................................................................................................................... 15
5.0 Configuration Options ................................................................................................................................................................... 19
6.0 Serial Slave Interface .................................................................................................................................................................... 36
7.0 USB Descriptors ........................................................................................................................................................................... 39
8.0 Battery Charging ........................................................................................................................................................................... 48
9.0 Integrated Power Regulators ........................................................................................................................................................ 50
10.0 Specifications .............................................................................................................................................................................. 51
11.0 Application Reference ................................................................................................................................................................. 59
12.0 Package Outlines, Tape & Reel Drawings, Package Marking .................................................................................................... 62
Appendix A: Data sheet Revision History ........................................................................................................................................... 70
The Microchip Web Site ...................................................................................................................................................................... 71
Customer Change Notification Service ............................................................................................................................................... 71
Customer Support ............................................................................................................................................................................... 71
USB3503 25-WLCSP Product Identification System .......................................................................................................................... 72
USB3503 32-SQFN Product Identification System ............................................................................................................................. 72
2011-2020 Microchip Technology Inc.
DS00001584C-page 3
USB3503
1.0
GENERAL DESCRIPTION
The USB3503 is a low-power, USB 2.0 hub controller with HSIC upstream connectivity and three USB 2.0 downtream
ports. The USB3503 operates as a hi-speed hub and supports low-speed, full-speed, and hi-speed downstream devices
on all of the enabled downstream ports.
The USB3503 has been specifically optimized for mobile embedded applications. The pin-count has been reduced by
optimizing the USB3503 for mobile battery-powered embedded systems where power consumption, small package
size, and minimal BOM are critical design requirements. Standby mode power has been minimized. Instead of a dedi-
cated crystal, reference clock inputs are aligned to mobile applications. Flexible integrated power regulators ease inte-
gration into battery powered devices. All required resistors on the USB ports are integrated into the hub. This includes
all series termination resistors on D+ and D– pins and all required pull-down resistors on D+ and D– pins.
The USB3503 includes programmable features such as:
MultiTRAKTM Technology, which utilizes a dedicated Transaction Translator (TT) per port to maintain consistent full-
speed data throughput regardless of the number of active downstream connections. MultiTRAKTM outperforms conven-
tional USB 2.0 hubs with a single TT in USB full-speed data transfers.
PortMap, which provides flexible port mapping and disable sequences. The downstream ports of a USB3503 hub can
be reordered or disabled in any sequence to support multiple platform designs with minimum effort. For any port that is
disabled, the USB3503 hub controllers automatically reorder the remaining ports to match the USB host controller’s port
numbering scheme.
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB signal drive
strength in the downstream port transceivers. PHYBoost attempts to restore USB sig-
nal integrity in a compromised system environment. The graphic on the right shows
an example of Hi-Speed USB eye diagrams before and after PHYBoost signal integ-
rity restoration.
VariSense, which controls the USB receiver sensitivity enabling programmable lev-
els of USB signal receive sensitivity. This capability allows operation in a sub-optimal
system environment, such as when a captive USB cable is used.
1.1
Customer Selectable Features
A default configuration is available in the USB3503 following a reset. This configuration may be sufficient for most appli-
cations. The USB3503 hub may also be configured by an external microcontroller. When using the microcontroller inter-
face, the hub appears as an I2C slave device.
The USB3503 hub supports customer selectable features including:
• Optional customer configuration via I2C.
• Supports compound devices on a port-by-port basis.
• Customizable vendor ID, product ID, and device ID.
• Configurable downstream port power-on time reported to the host.
• Supports indication of the maximum current that the hub consumes from the USB upstream port.
• Supports Indication of the maximum current required for the hub controller.
• Configurable as a either a Self-Powered or Bus-Powered Hub
• Supports custom string descriptors (up to 30 characters):
- Product string
- Manufacturer string
- Serial number string
• When available, I2C configurable options for default configuration may include:
- Downstream ports as non-removable ports
- Downstream ports as disabled ports
- USB signal drive strength
- USB receiver sensitivity
- USB differential pair pin location
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2011-2020 Microchip Technology Inc.
USB3503
1.1.1
BLOCK DIAGRAM
FIGURE 1-1:
USB3503 BLOCK DIAGRAM
Upstream HSIC
To I2C Master
Port
VBAT
VDD_CORE_REG
VDD12_BYP
SDA SCL INT_N
RESET_N
VDD33_BYP
Serial
Interface
Mode
Control
3.3V Reg
1.2V Reg
Upstream
HSIC
-
Standby
Hub Mode
SIE
Controller
Repeater
TT #1
TT #2
TT #3
Port Controller
Routing & Port Re-Ordering Logic
PHY#3
PHY#2
PHY#1
PLL
USB Data
Downstream
USB Data
Downstream
REF_CLK HUB_CONNECT
USB Data
Downstream
2011-2020 Microchip Technology Inc.
DS00001584C-page 5
USB3503
2.0
2.1
ACRONYMS AND DEFINITIONS
Acronyms
EP:
FS:
Endpoint
Full-Speed
HS:
I2C:
LS:
Hi-Speed
Inter-Integrated Circuit1
Low-Speed
HSIC: High-Speed Inter-Chip
2.2
Reference Documents
1. USB Engineering Change Notice dated December 29th, 2004, UNICODE UTF-16LE For String Descriptors.
2. Universal Serial Bus Specification, Revision 2.0, Dated April 27th, 2000.
3. Battery Charging Specification, Revision 1.1, Release Candidate 10, Dated Sept. 22, 2008
4. High-Speed Inter-Chip USB Electrical Specification, Version 1.0, Dated Sept. 23, 2007
1. I2C is a registered trademark of Philips Corporation.
DS00001584C-page 6
2011-2020 Microchip Technology Inc.
USB3503
3.0
3.1
USB3503 PIN DEFINITIONS
Pin Configuration
Figure 3-1 details the 25-ball WLCSP package. Figure 3-2 details the 32-pin SQFN package pin configuration. Signal
definitions are provided in Section 3.2.
FIGURE 3-1:
USB3503 25-BALL WLCSP PACKAGE
1
2
3
4
5
A
B
C
D
E
TOP VIEW
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DS00001584C-page 7
USB3503
FIGURE 3-2:
USB3503 32-PIN SQFN PACKAGE
P
M
P
M
P
M
D
_
1
D
_
1
D
_
2
D
_
2
D
_
3
D
_
3
N
D
B
S
U
N
D
B
S
U
N
D
B
S
U
N
D
B
S
U
N
D
B
S
U
N
D
B
S
U
C
N
C
N
4
2
3
2
2
2
1
2
0
2
9
1
8
1
7
1
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VBAT
VDD33_BYP
NC
STROBE
DATA
NC
VDD_CORE_REG
REFCLK
VDD12_BYP
RESET_N
VDD12_BYP
REF_SEL0
REF_SEL1
USB3503
RBIAS
e3
NC
VDD33_BYP
1
2
3
4
5
6
7
8
T
L
C
S
P
Y
N
_
C
N
R
N
_
N
I
A
D
S
C
E
N
N
W
P
T
T
S
C
B
_
2
1
O
R
P
O
C
_
D
D
V
B
U
H
Note: Exposed pad (VSS) on bottom of package must be connected to ground.
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2011-2020 Microchip Technology Inc.
USB3503
3.2
Signal Definitions
WLCSP
Ball
SQFN
Pin
Name
Description
E2
E1
A5
C4
B4
A1
B1
C2
D2
C1
D1
E5
D5
E3
B5
C5
D4
E4
B3
A4
D3
A2
B2
A3
C3
-
15
16
32
4
DATA
STROBE
Upstream HSIC DATA pin of the USB Interface
Upstream HSIC STROBE pin of the USB Interface
3.3 V Regulator Bypass
VDD33_BYP
PRTPWR
OCS_N
Port Power Control Output
Over Current Sense Input
1
24
23
22
21
20
19
8
USBDN1_DP
USBDN1_DM
USBDN2_DP
USBDN2_DM
USBDN3_DP
USBDN3_DM
SCL
USB downstream Port 1 D+ data pin
USB downstream Port 1 D- data pin
USB downstream Port 2 D+ data pin
USB downstream Port 2 D- data pin
USB downstream Port 3 D+ data pin
USB downstream Port 3 D- data pin
I2C clock input
7
SDA
I2C bi-directional data pin
12
2
RESET_N
HUB_CONNECT
INT_N
Active low reset signal
Hub Connect
5
Active low interrupt signal
9
REF_SEL1
REF_SEL0
REFCLK
Reference Clock Select 1 input
Reference Clock Select 0 input
Reference Clock input
10
29
30
6,11,13
26
25
28
e-pad
RBIAS
Bias Resistor pin
VDD12_BYP
VDD33_BYP
VBAT
1.2 V Regulator
3.3 V Regulator
Voltage input from the battery supply
Power supply input to 1.2V regulator for digital logic core
Ground
VDD_CORE_REG
VSS
3,14,17,
18,27,31
NC
No connect
2011-2020 Microchip Technology Inc.
DS00001584C-page 9
USB3503
3.3
Pin Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional groups according to
their associated interface.
The terms assertion and negation are used. This is done to avoid confusion when working with a mixture of “active low”
and “active high” signal. The term “assert”, or “assertion” indicates that a signal is active, independent of whether that
level is represented by a high or low voltage. The term “negate”, or “negation” indicates that a signal is inactive.
3.3.1
PIN DEFINITION
TABLE 3-1:
PIN DESCRIPTIONS
Name
Symbol
Type
Description
UPSTREAM HIGH SPEED INTER-CHIP INTERFACE
HSIC Clock/Strobe
HSIC Data
STROBE
DATA
I/O
I/O
HSIC Upstream Hub Strobe pin
HSIC Upstream Hub Data pin
High-Speed USB Data
&
Port Disable Strap Option
USBDN_DP[2:1]
&
USBDN_DM[2:1]
A-I/O
These pins connect to the downstream USB
peripheral devices attached to the hub’s ports
Downstream Port Disable Strap option:
This pin will be sampled at RESET_N negation to
determine if the port is disabled.
Both USB data pins for the corresponding port
must be tied to VDD33_BYP to disable the
associated downstream port.
HS USB Data
USBDN_DP[3]
&
A-I/O
These pins connect to the downstream USB
peripheral devices attached to the hub’s ports.
USBDN_DM[3]
There is no downstream Port Disable Strap
option on these ports.
SERIAL PORT INTERFACE
Serial Data
Serial Clock
Interrupt
SDA
I/OD
I
I2C Serial Data
SCL
Serial Clock (SCL)
INT_N
OD
Interrupt
The function of this pin is determined by the
setting in the CFGP.INTSUSP configuration
register.
When CFGP.INTSUSP = 0 (General Interrupt)
A transition from high to low identifies when one of
the interrupt enabled status registers has been
updated.
SOC must update the Serial Port Interrupt Status
Register to reset the interrupt pin high.
When CFGP.INTSUSP = 1 (Suspend Interrupt)
Indicates USB state of the hub.
‘Asserted’ low = Unconfigured or configured and in
USB Suspend
‘Negated’ high = Hub is configured, and is active
(i.e., not in suspend)
If unused, this pin must be tied to VDD33_BYP.
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2011-2020 Microchip Technology Inc.
USB3503
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Name
Over Current Sense
Symbol
Type
Description
OCS_N
I
Over Current Sense - Input from external current
monitor indicating an over-current condition on
port 3 or on ganged supply.
Negated High = No over current fault detected
Asserted Low = Over Current Fault Reported
Port Power
PRTPWR
OD
Port Power Control- Enables power to USB
peripheral devices downstream on port 3 or on
ganged supply.
Asserted High = External Device should provide
power for port(s).
Negated Low = External Device should disable
power to port(s).
MISC
Reference Clock Input
Reference Clock Select
REFCLK
I
I
Reference clock input.
REF_SEL[1:0]
The reference select input must be set to
correspond to the frequency applied to the
REFCLK input. The customer should tie these pins
to ground or VDD33_BYP. This input is latched
during HUB.Init stage.
Selects input reference clock frequency per
Table 3-3.
RESET Input
USB Transceiver Bias
Hub Connect
RESET_N
RBIAS
I
A-I/O
I
This active low signal is used by the system to
reset the chip and hold the chip in low power
STANDBY MODE.
A 12.0k (+/- 1%) resistor is attached from ground
to this pin to set the transceiver’s internal bias
settings.
HUB_CONNECT
Hub will transition to the Hub Communication
Stage when this pin is asserted high. It can be
used in three different ways:
Tied to Ground - Hub will not transition to the Hub
Communication Stage until connect_n bit of the
SP_ILOCK register is negated.
Tied to VDD33_BYP - Hub will automatically
transition to the Hub Communication Stage
regardless of the setting of the connect_n bit and
without pausing for the SOC to reference status
registers.
Transition from low to high - Hub will transition to
the Hub Communication Stage after this pin
transitions from low to high. HUB_CONNECT
should never be driven high when USB3503 is in
Standby Mode.
2011-2020 Microchip Technology Inc.
DS00001584C-page 11
USB3503
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Type
Description
POWER
1.2V VDD Power
3.3V VDD Power
VDD12_BYP
Power 1.2 V Regulator. A 1.0 F (<1 ESR) capacitor
to ground is required for regulator stability. The
capacitor should be placed as close as possible to
the USB3503.
VDD33_BYP
Power 3.3V Regulator. A 4.7F (<1 ESR) capacitor to
ground is required for regulator stability. The
capacitor should be placed as close as possible to
the USB3503.
Core Power Supply Input
VDD_CORE_REG
Power Power supply to 1.2V regulator.
This power pin should be connected to
VDD33_BYP for single supply applications.
Refer to Section 9.0 “Integrated Power
Regulators” for power supply configuration
options.
Battery Power Supply Input
VBAT
VSS
Power Battery power supply.
Refer to Section 9.0 “Integrated Power
Regulators” for power supply configuration
options.
VSS
Ground Ground
3.3.2
I/O TYPE DESCRIPTIONS
TABLE 3-2:
USB3503 I/O TYPE DESCRIPTIONS
Description
I/O Type
I
Digital Input.
OD
Digital Output. Open Drain.
Digital Input or Output.
Analog Input or Output.
DC input or Output.
Ground.
I/O
A-I/O
Power
Ground
3.3.3
REFERENCE CLOCK
The REFCLK input is can be driven with a square wave from 0 V to VDD33_BYP. The USB3503 only uses the positive
edge of the clock. The duty cycle is not critical.
The USB3503 is tolerant to jitter on the reference clock. The REFCLK jitter should be limited to a peak to peak jitter of
less than 1 ns over a 10 s time interval. If this level of jitter is exceeded the USB3503 high speed eye diagram may be
degraded.
To select the REFCLK input frequency, the REF_SEL pins must be set according to Table 3-3 and Table 3-4. To select
the primary REFCLK frequencies defined in Table 3-3, INT_N must be sampled high during the Hub.Init stage. If the
INT_N pin is not used, the INT_N pin should be tied to VDD33_BYP. To select the secondary REFCLK frequencies
defined in Table 3-4, INT_N must be sampled low during the Hub.Init stage. If the INT_N pin is not used, the INT_N pin
should be tied to ground. Since the INT_N pin is open-drain during normal function, selecting the secondary REFCLK
frequencies requires that the INT_N pin be driven low from an external source during Hub.Init and then, after startup,
that external source must turn into an input to receive the INT_N signal.
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2011-2020 Microchip Technology Inc.
USB3503
TABLE 3-3:
USB3503 PRIMARY REFERENCE CLOCK FREQUENCIES
Frequency (MHz)
REF_SEL[1:0]
‘00’
‘01’
‘10’
‘11’
38.4
26.0
19.2
12.0
TABLE 3-4:
USB3503 SECONDARY REFERENCE CLOCK FREQUENCIES
Frequency (MHz)
REF_SEL[1:0]
‘00’
‘01’
‘10’
‘11’
24.0
27.0
25.0
50.0
3.3.4
INTERRUPT
The general interrupt pin (INT_N) is intended to communicate a condition change within the hub. The conditions that
may cause an interrupt are captured within a register mapped to the serial port (Register E8h: Serial Port Interrupt Status
- INT_STATUS). The conditions that cause the interrupt to assert can be controlled through use of an interrupt mask
register (Register E9h: Serial Port Interrupt Mask - INT_MASK).
The general interrupt and all interrupt conditions are functionally latched and event driven. Once the interrupt or any of
the conditions have asserted, the status bit will remain asserted until the SOC negates the bit using the serial port. The
bits will then remain negated until a new event condition occurs. The latching nature of the register causes the status to
remain even if the condition that caused the interrupt ceases to be active. The event driven nature of the register causes
the interrupt to only occur when a new event occurs- when a condition is removed and then is applied again.
The function of the interrupt and the associated status and masking registers are illustrated in Figure 3-3. Registers &
Register bits shown in the figure are defined in Table 5-2, “Serial Interface Registers,” on page 19.
FIGURE 3-3:
INT_N OPERATION
Suspended OR
NOT Configured
INT_STATUS<4:0>
Hub in USB Suspend Mode
(SuspInd)
SET
S
R
Q
Q
<4>
CLR
Hub Configured by USB Host
(HubConf)
SET
CLR
S
R
Q
Q
INT_N
<3>
<2>
<1>
<0>
INT_STATUS <7>
Port Power Register Updated
(PrtPwr)
SET
CLR
S
R
Q
Q
SET
S
Q
SET
CLR
CLR
S
R
Q
Q
R
Q
Reserved
Reserved
SET
CLR
S
R
Q
Q
SE
T
D
Q
Q
CLR
CFGP.INTSUSP
SET
CLR
D
Q
Q
INT_MASK
SCL/SDA
Serial Port
Write Logic
2011-2020 Microchip Technology Inc.
DS00001584C-page 13
USB3503
Figure 3-3 also shows an alternate configuration option (CFGP.INTSUSP) for a suspend interrupt. This option allows
the user to change the behavior of the INT_N pin to become a direct level indication of configuration and suspend status.
When selected, the INT_N indicates that the entire hub has entered the USB suspend state.
Note:
Because INT_N is driven low when active, care must be taken when selecting the external pullup resistor
value for this open drain output. A sufficiently large resistor must be selected to insure suspend current
requirements can be satisfied for the system.
DS00001584C-page 14
2011-2020 Microchip Technology Inc.
USB3503
4.0
MODES OF OPERATION
The USB3503 provides two modes of operation - Standby Mode and Hub Mode - which balance power consumption
with functionality. The operating mode of the USB3503 is selected by setting values on primary inputs according to the
table below.
TABLE 4-1:
CONTROLLING MODES OF OPERATION
Resulting Mode
RESET_N
Input
Summary
0
Standby
Hub
Lowest Power Mode – no function other than monitoring RESET_N
input to move to higher states. All regulators are powered off.
1
Full Feature Mode - Operates as a configurable USB hub. Power
consumption based on how many ports are active, at what speeds
they are running and amount of data transferred.
4.1
Operational Mode Flowchart
The flowchart in Figure 4-1 shows the modes of operation. It also shows how the USB3503 traverses through the Hub
mode stages (shown in bold.) The flow of control is dictated by control register bits shown in Italics as well as other
events such as availability of reference clock. Refer to Section 5.3, "Serial Interface Register Definitions," on page 21
for the detailed definition of the control register bits. In this specification register bits are referenced using the syntax
<Register>.<RegisterBit>. A summary of all registers can be found in Table 5-2, “Serial Interface Registers,” on
page 19.
The remaining sections in this chapter provide more detail on each stage and mode of operation.
2011-2020 Microchip Technology Inc.
DS00001584C-page 15
USB3503
FIGURE 4-1:
MODES OF OPERATION FLOWCHART
Legend
Standby
Mode
Start
(SOC Set Pin RESET_N=0)
Hub Mode
Hub Initialization Stage
Core Regulator Enabled
Power-On-Reset
PLL Synchronization
Hub Wait RefClk Stage
Wait for Pin
HUB_CONNECT=1
OR I2C bit
N
SP_ILOCK.connect_n=0
REF_CLK available
Y
Hub Connect Stage
Wait for
REF_CLK
Host Enumerates and
Configures Hub
Hub Configuration Stage
Host Initiates Data Transfers
to Downstream Devices
1
SP_ILOCK.
config_n
0
Systemto
power down
HSIC I/F
N
Timeout or
I2C Write
I2C Write
SP_ILOCK.
config_n=1
Y
Wait for
Timeout
I2C bit
SP_ILOCK.config_n=0
SOC Set Pin RESET_N=0
Hub Communication Stage
(USB Traffic)
DS00001584C-page 16
2011-2020 Microchip Technology Inc.
USB3503
4.2
Standby Mode
Standby Mode provides a very low power state for maximum power efficiency when no signaling is required. This is the
lowest power state. In Standby Mode all internal regulators are powered off, the PLL is not running, and core logic is
powered down in order to reduce power. Because core logic is powered off, no configuration settings are retained in this
mode and must be re-initialized after RESET_N is negated high.
4.2.1
EXTERNAL HARDWARE RESET_N
A valid hardware reset is defined as an assertion of RESET_N low for a minimum of 100us after all power supplies are
within operating range. While reset is asserted, the Hub (and its associated external circuitry) enters STANDBY MODE
and consumes extremely low current as defined in Table 10-5 and Table 10-6.
Assertion of RESET_N (external pin) causes the following:
• All downstream ports are disabled.
• All transactions immediately terminate; no states are saved.
• All internal registers return to the default state.
• The PLL is halted.
After RESET_N is negated high in the Hub.Init stage, the Hub reads customer-specific data from the ROM.
4.3
Hub Mode
Hub Mode provides functions of configuration and high speed USB hub operation including connection and communi-
cation. Upon entering Hub Mode and initializing internal logic, the device passes through several sequential stages
based on a fixed time interval.
4.3.1
HUB INITIALIZATION STAGE (HUB.INIT)
The first stage is the initialization stage and occurs when Hub mode is entered based on the conditions in Table 4-1. In
this stage the 1.2V regulator is enabled and stabilizes, internal logic is reset, and the PLL locks if a valid REFCLK is
supplied. Configuration registers are initialized to their default state and REF_SEL[1:0] input values are latched. The
USB3503 will complete initialization and automatically enter the next stage after Thubinit. Because the digital logic within
the device is not yet stable, no communication with the device using the serial port is possible. Configuration registers
are initialized to their default state.
4.3.2
HUB WAIT REFCLK STAGE (HUB.WAITREF)
During this stage the serial port is not functional.
If the reference clock is provided before entering hub mode, the USB3503 will transition to the Hub Configuration stage
without pausing in the Hub Wait RefClk stage. Otherwise, the USB3503 will transition to the Hub configuration stage
once a valid reference clock is supplied and the PLL has locked.
4.3.3
HUB CONFIGURATION STAGE (HUB.CONFIG)
In this stage, the SOC has an opportunity to control the configuration of the USB3503 and modify any of the default
configuration settings specified in the integrated ROM. These settings include USB device descriptors, port electrical
settings such as PHY BOOST, and control features. The SOC implements the changes using the serial slave port inter-
face to write configuration & control registers.
See Section 5.3.29, "Register E7h: Serial Port Interlock Control - SP_ILOCK," on page 29 for definition of SP_ILOCK
register and how it controls progress through hub stages. If the SP_ILOCK.config_n bit has its default asserted low and
the bit is not written by the serial port, then the USB3503 completes configuration without any I2C intervention.
If the SP_ILOCK.config_n bit has its default negated high or the SOC negates the bit high using the serial port during
Thubconfig, the USB3503 will remain in the Hub Configuration Stage indefinitely. This will allow the SOC to update other
configuration and control registers without any remaining time-out restrictions. Once the SP_ILOCK.config_n bit is
asserted low by the SOC the device will transition to the next stage.
2011-2020 Microchip Technology Inc.
DS00001584C-page 17
USB3503
4.3.4
HUB CONNECT STAGE (HUB.CONNECT)
Next, the USB3503 enters the Hub Connect Stage. See Section 5.3.32, "Register EEh: Configure Portable Hub - CFGP,"
on page 31 and Section 5.3.29, "Register E7h: Serial Port Interlock Control - SP_ILOCK," on page 29 for definition of
control registers which affect how the device transitions through the hub stages.
By using the appropriate controls, the USB3503 can be set to immediately transition, or instead to remain in the Hub
Connect Stage indefinitely until one of the SOC handshake events occur. When set to wait on the handshake, the SOC
may read or update any of the serial port registers. Once the SOC finishes accessing registers and is ready for USB
communication to start, it can perform one of the selected handshakes which that cause the USB3503 to connect within
T
hubconnect and transition to the Hub Communication Stage.
4.3.5
HUB COMMUNICATION STAGE (HUB.COM)
Once it exits the Hub Connect Stage, the USB3503 enters Hub Communication Stage. In this stage full USB operation
is supported under control of the USB Host on the upstream port. The USB3503 will remain in the Hub Communication
Stage until the operating mode is changed by the system asserting RESET_N low.
While in the Hub Communication Stage, communication over the serial port is no longer supported and the resulting
behavior of the serial port if accessed is undefined. In order to re-enable the serial port interface, the device must exit
Hub Communication Stage. Exiting this stage is only possible by entering Standby mode.
4.3.6
HUB MODE TIMING DIAGRAM
The following timing diagram shows the progression through the stages of Hub Mode and the associated timing param-
eters.
FIGURE 4-2:
TIMING DIAGRAM FOR HUB STAGES
RESET_N
T_HUBINIT
T_HUBCONFIG
T_HUBCONNECT
Hub.Connect
Device
Mode.Stage
Standby
Hub.Init
Hub.Config
Hub.Com
The following table lists the timing parameters associated with the stages of the Hub Mode.
TABLE 4-2:
TIMING PARAMETERS FOR HUB STAGES
Characteristic
Symbol
MIN
TYP
MAX
Units
Conditions
Hub Initialization
Time
THUBINIT
3
4
ms
Hub Configuration
Time-out
THUBCONFIG
94
0
95
1
96
10
ms
us
Hub Connect Time
THUBCONNECT
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2011-2020 Microchip Technology Inc.
USB3503
5.0
5.1
CONFIGURATION OPTIONS
Hub Configuration Options
The Hub supports a number of features (some are mutually exclusive), and must be configured in order to correctly func-
tion when attached to a USB host controller. There are two principal ways to configure the hub: by writing to configuration
registers using the serial slave port, or by internal default settings. Any configuration registers which are not written by
the serial slave retain their default settings.
5.1.1
MULTI/SINGLE TT
The USB 2.0 Hub is fully specification compliant to the Universal Serial Bus Specification Revision 2.0 April 27,2000
(12/7/2000 and 5/28/2002 Errata). Please reference Chapter 11 (Hub Specification) for general details regarding Hub
operation and functionality.
For performance reasons, the Hub provides 1 Transaction Translator (TT) per port (defined as Multi-TT configuration),
and each TT has 1512 bytes of periodic buffer space and 272 Bytes of non- periodic buffer space (divided into 4 non-
periodic buffers per TT), for a total of 1784 bytes of buffer space for each Transaction Translator.
When configured as a Single-TT Hub (required by USB 2.0 Specification), the Single Transaction Translator will have
1512 bytes of periodic buffer space and 272 bytes of non-periodic buffer space (divided into 4 non-periodic buffers per
TT), for a total of 1784 bytes of buffer space for the entire Transaction Translator. Each Transaction Translator’s buf-
fer is divided as shown in Table 5-1, "Transaction Translator Buffer Chart".
TABLE 5-1:
TRANSACTION TRANSLATOR BUFFER CHART
Periodic Start-Split Descriptors
256 Bytes
752 Bytes
128 Bytes
376 Bytes
16 Bytes
Periodic Start-Split Data
Periodic Complete-Split Descriptors
Periodic Complete-Split Data
Non-Periodic Descriptors
Non-Periodic Data
256 Bytes
1784 Bytes
Total for each Transaction Translator
5.2
Default Serial Interface Register Memory Map
The Serial Interface Registers are used to customize the USB3503 for specific applications. Reserved registers or
reserved bits within a defined register should not be written to non-default values or undefined behavior may result.
TABLE 5-2:
REG
SERIAL INTERFACE REGISTERS
Register Name
R/W
Abbreviation
Section
ADDR
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VID LSB
VID MSB
VIDL
VIDM
PIDL
5.3.1, page 21
5.3.2, page 21
5.3.3, page 21
5.3.4, page 21
5.3.5, page 21
5.3.6, page 21
5.3.7, page 22
5.3.8, page 23
5.3.9, page 23
5.3.10, page 24
5.3.11, page 24
5.3.12, page 25
5.3.13, page 25
PID LSB
PID MSB
PIDM
DIDL
DID LSB
DID MSB
DIDM
CFG1
CFG2
CFG3
NRD
Config Data Byte 1
Config Data Byte 2
Config Data Byte 3
Non-Removable Devices
Port Disable (Self)
Port Disable (Bus)
Max Power (Self)
PDS
PDB
MAXPS
2011-2020 Microchip Technology Inc.
DS00001584C-page 19
USB3503
TABLE 5-2:
REG
SERIAL INTERFACE REGISTERS (CONTINUED)
R/W
Register Name
Abbreviation
Section
ADDR
0Dh
0Eh
R/W
Max Power (Bus)
MAXPB
HCMCS
HCMCB
PWRT
5.3.14, page 25
5.3.15, page 26
5.3.16, page 26
5.3.17, page 26
5.3.18, page 26
5.3.19, page 26
5.3.20, page 26
5.3.21, page 27
5.3.22, page 27
5.3.23, page 27
5.3.24, page 27
5.3.25, page 27
5.3.26, page 28
R/W Hub Controller Max Current (Self)
R/W Hub Controller Max Current (Bus)
0Fh
10h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Power-on Time
LANG_ID_H
11h
LANGIDH
LANGIDL
MFRSL
PRDSL
SERSL
MANSTR
PRDSTR
SERSTR
BC_EN
N/A
12h
LANG_ID_L
13h
MFR_STR_LEN
PRD_STR_LEN
SER_STR_LEN
MFR_STR
14h
15h
16h-53h
54h-91h
PROD_STR
92h-CFh R/W
SER_STR
D0h
D1-E1h
E2h
R/W
R/W
R/W
R/W
R
Downstream Battery Charging
Reserved
Reserved
N/A
E3-E4h
E5h
Reserved
N/A
Port Power Status
Over Current Sense Control
Serial Port Interlock Control
Serial Port Interrupt Status
Serial Port Interrupt Mask
Reserved
PRTPWR
OCS
5.3.27, page 28
5.3.28, page 29
5.3.29, page 29
5.3.30, page 30
5.3.31, page 31
E6h
R/W
R/W
R/W
R/W
R/W
E7h
SP_ILOCK
INT_STATUS
INT_MASK
N/A
E8h
E9h
EAh-
EDh
EEh
EFh-F3h
F4h
R/W
R
Configure Portable Hub
Reserved
CFGP
N/A
5.3.32, page 31
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Varisense_Up3
Varisense_21
Boost_Up3
VSNSUP3
VSNS21
BSTUP3
N/A
5.3.33, page 32
5.3.34, page 32
5.3.35, page 32
F5h
F6h
F7h
Reserved
F8h
Boost_21
BST21
N/A
5.3.36, page 33
F9h
Reserved
FAh
Port Swap
PRTSP
PRTR12
PRTR34
N/A
5.3.37, page 33
5.3.38, page 34
5.3.39, page 35
FBh
FCh
FDh
FEh
FFh
Port Remap 12
Port Remap 34
Reserved
Reserved
I2C Status/Command
N/A
STCD
5.3.40, page 35
DS00001584C-page 20
2011-2020 Microchip Technology Inc.
USB3503
5.3
Serial Interface Register Definitions
5.3.1
REGISTER 00H: VENDOR ID (LSB) - VIDL
Default = 0x24h - Corresponds to Vendor ID.
Bit Number
Bit Name
Description
7:0
VID_LSB
Least Significant Byte of the Vendor ID. This is a 16-bit value that uniquely
identifies the Vendor of the user device (assigned by USB-Interface Forum).
This field is set by the customer using the serial interface options.
5.3.2
REGISTER 01H: VENDOR ID (MSB) - VIDM
Default = 0x04h - Corresponds to Vendor ID.
Bit Number
Bit Name
Description
7:0
VID_MSB
Most Significant Byte of the Vendor ID. This is a 16-bit value that uniquely
identifies the Vendor of the user device (assigned by USB-Interface Forum).
This field is set by the customer using serial interface options.
5.3.3
REGISTER 02H: PRODUCT ID (LSB) - PIDL
Default = 0x03h - Corresponds to USB part number for 3-port device.
Bit Number
Bit Name
Description
7:0
PID_LSB
Least Significant Byte of the Product ID. This is a 16-bit value that the Vendor
can assign that uniquely identifies this particular product (assigned by
customer). This field is set by the customer using the serial interface options.
5.3.4
REGISTER 03H: PRODUCT ID (MSB) - PIDM
Default = 0x35h Corresponds to 3503 device.
Bit Number
Bit Name
Description
7:0
PID_MSB
Most Significant Byte of the Product ID. This is a 16-bit value that the Vendor
can assign that uniquely identifies this particular product (assigned by
customer). This field is set by the customer using the serial interface options.
5.3.5
REGISTER 04H: DEVICE ID (LSB) - DIDL
Default = 0xA0h
Bit Number
Bit Name
Description
7:0
DID_LSB
Least Significant Byte of the Device ID. This is a 16-bit device release number
in BCD format (assigned by customer). This field is set by the customer using
the serial interface options.
5.3.6
REGISTER 05H: DEVICE ID (MSB) - DIDM
Default = 0xA1h
Bit Number
Bit Name
Description
7:0
DID_MSB
Most Significant Byte of the Device ID. This is a 16-bit device release number
in BCD format (assigned by customer). This field is set by the customer using
the serial interface options.
2011-2020 Microchip Technology Inc.
DS00001584C-page 21
USB3503
5.3.7
REGISTER 06H: CONFIG_BYTE_1 - CFG1
Default = 0x98h - Corresponds to Self Powered, Ganged Port Power
Bit Number
Bit Name
Description
7
SELF_BUS_PW Self or Bus Power: Selects between Self- and Bus-Powered operation.
R
The Hub is either Self-Powered or Bus-Powered.
When configured as a Bus-Powered device, the Hub consumes less than
100mA of current prior to being configured. After configuration, the Bus-
Powered Hub (along with all associated hub circuitry, any embedded devices if
part of a compound device, and 100mA per externally available downstream
port) must consume no more than 500mA of upstream VBUS current. The
current consumption is system dependent, and the customer must ensure that
the USB 2.0 specifications are not violated.
When configured as a Self-Powered device, <1mA of upstream VBUS current
is consumed and all ports are available, with each port being capable of
sourcing 500mA of current.
This field is set by the customer using the serial interface options.
0 = Bus-Powered operation.
1 = Self-Powered operation.
6
5
4
Reserved
Reserved
Reserved
Reserved
MTT_ENABLE Multi-TT enable: Enables one transaction translator per port operation.
Selects between a mode where only one transaction translator is available for
all ports (Single-TT), or each port gets a dedicated transaction translator (Multi-
TT) {Note: The host may force Single-TT mode only}.
0 = single TT for all ports.
1 = one TT per port (multiple TT’s supported)
3
Reserved
Reserved
2:1
CURRENT_SN Over Current Sense: Selects current sensing on a port-by-port basis, all ports
S
ganged, or none (only for bus-powered hubs) The ability to support current
sensing on a port or ganged basis is hardware implementation dependent.
00 = Ganged sensing (all ports together).
01 = Individual port-by-port.
1x = Over current sensing not supported. (must only be used with Bus-
Powered configurations!)
0
PORT_PWR
Port Power Switching: Enables power switching on all ports simultaneously
(ganged), or port power is individually switched on and off on a port- by-port
basis (individual). The ability to support power enabling on a port or ganged
basis is hardware implementation dependent.
0 = Ganged switching (all ports together)
1 = Individual port-by-port switching.
DS00001584C-page 22
2011-2020 Microchip Technology Inc.
USB3503
5.3.8
REGISTER 07H: CONFIGURATION DATA BYTE 2 - CFG2
Default = 0x20h - Not a Compound Device
Bit Number
Bit Name
Description
7:4
Reserved
Reserved
3
COMPOUND Compound Device: Allows the customer to indicate that the Hub is part of a
compound (see the USB Specification for definition) device. The applicable
port(s) must also be defined as having a “Non-Removable Device”.
0 = No.
1 = Yes, Hub is part of a compound device.
2:0
Reserved
Reserved
5.3.9
REGISTER 08H: CONFIGURATION DATA BYTE 3 - CFG3
Default = 0x03h
Bit Number
Bit Name
Description
7:4
3
Reserved
Reserved
PRTMAP_EN Port Re-Mapping enable: Selects the method used by the hub to assign port
numbers and disable ports
‘0’ = Standard Mode. The following registers are used to define which ports are
enabled, and the ports are mapped as Port “n” on the hub is reported as Port
‘n’ to the host, unless one of the ports is disabled, then the higher numbered
ports are remapped in order to report contiguous port numbers to the host.
Section 5.3.11 Register 0A
Section 5.3.12 Register 0B
‘1’ = Port Re-Map mode. The mode enables remapping via the registers defined
below.
Section 5.3.38 Register FB
Section 5.3.39 Register FC
2:1
0
Reserved
Reserved
STRING_EN Enables String Descriptor Support
‘0’ = String Support Disabled
‘1’ = String Support Enabled
2011-2020 Microchip Technology Inc.
DS00001584C-page 23
USB3503
5.3.10
REGISTER 09H: NON-REMOVABLE DEVICE - NRD
Default = 0x00h
Bit Number
Bit Name
Description
7:0
NR_DEVICE Non-Removable Device: Indicates which port(s) include non- removable
devices.
‘0’ = port is removable
‘1’ = port is non- removable.
Informs the Host if one of the active physical ports has a permanent device that
is undetachable from the Hub. (Note: The device must provide its own
descriptor data.)
Bit 7= Reserved
Bit 6= Reserved
Bit 5= Reserved
Bit 4= Reserved
Bit 3= Port 3 non-removable.
Bit 2= Port 2 non-removable.
Bit 1= Port 1 non removable.
Bit 0= Reserved
5.3.11
REGISTER 0AH: PORT DISABLE FOR SELF POWERED OPERATION - PDS
Default = 0x00h
Bit Number
Bit Name
Description
7:0
PORT_DIS_SP Port Disable, Self-Powered: Disables 1 or more ports.
‘0’ = port is available
‘1’ = port is disabled.
During Self-Powered operation and PRTMAP_EN = ‘0’, this selects the ports
which will be permanently disabled, and are not available to be enabled or
enumerated by a Host Controller. The ports can be disabled in any order, the
internal logic will automatically report the correct number of enabled ports to the
USB Host, and will reorder the active ports in order to ensure proper function.
Bit 7= Reserved
Bit 6= Reserved
Bit 5= Reserved
Bit 4= Reserved
Bit 3= Port 3 Disable.
Bit 2= Port 2 Disable.
Bit 1= Port 1 Disable.
Bit 0= Reserved
DS00001584C-page 24
2011-2020 Microchip Technology Inc.
USB3503
5.3.12
REGISTER 0BH: PORT DISABLE FOR BUS POWERED OPERATION - PDB
Default = 0x00h
Bit Number
Bit Name
Description
7:0
PORT_DIS_BP Port Disable, Bus-Powered: Disables 1 or more ports.
‘0’ = port is available
‘1’ = port is disabled.
During Bus-Powered operation and PRTMAP_EN = ‘0’, this selects the ports
which will be permanently disabled, and are not available to be enabled or
enumerated by a Host Controller. The ports can be disabled in any order, the
internal logic will automatically report the correct number of enabled ports to the
USB Host, and will reorder the active ports in order to ensure proper function.
Bit 7= Reserved
Bit 6= Reserved
Bit 5= Reserved
Bit 4= Reserved
Bit 3= Port 3 Disable.
Bit 2= Port 2 Disable.
Bit 1= Port 1 Disable.
Bit 0= Reserved
5.3.13
REGISTER 0CH: MAX POWER FOR SELF POWERED OPERATION - MAXPS
Default = 0x01h
Bit Number
Bit Name
Description
7:0
MAX_PWR_SP Max Power Self_Powered: Value in 2mA increments that the Hub consumes
from an upstream port when operating as a self-powered hub. This value
includes the hub silicon along with the combined power consumption (from
VBUS) of all associated circuitry on the board. This value also includes the
power consumption of a permanently attached peripheral if the hub is
configured as a compound device, and the embedded peripheral reports 0mA
in its descriptors.
Example: A value of 8mA would be written to this register as 0x04h
Note: The USB 2.0 Specification does not permit this value to exceed 100mA
5.3.14
REGISTER 0DH: MAX POWER FOR BUS POWERED OPERATION - MAXPB
Default = 0xFAh- Corresponds to 500mA.
Bit Number
Bit Name
Description
7:0
MAX_PWR_BP Max Power Bus_Powered: Value in 2mA increments that the Hub consumes
from an upstream port when operating as a bus-powered hub. This value
includes the hub silicon along with the combined power consumption (from
VBUS) of all associated circuitry on the board. This value also includes the
power consumption of a permanently attached peripheral if the hub is
configured as a compound device, and the embedded peripheral reports 0mA
in its descriptors.
Example: A value of 8mA would be written to this register as 0x04h
2011-2020 Microchip Technology Inc.
DS00001584C-page 25
USB3503
5.3.15
REGISTER 0EH: HUB CONTROLLER MAX CURRENT FOR SELF POWERED OPERATION -
HCMCS
Default = 0x02h Corresponds to 2mA.
Bit Number
Bit Name
Description
7:0
HC_MAX_C_SP Hub Controller Max Current Self-Powered: Value in 1mA increments that the
Hub consumes from an upstream port when operating as a self- powered hub.
This value includes the hub silicon along with the combined power consumption
(from VBUS) of all associated circuitry on the board. This value does NOT
include the power consumption of a permanently attached peripheral if the hub
is configured as a compound device.
Example: A value of 8mA would be written to this register as 0x08h
Note: The USB 2.0 Specification does not permit this value to exceed 100mA
5.3.16
REGISTER 0FH: HUB CONTROLLER MAX CURRENT FOR BUS POWERED OPERATION -
HCMCB
Default = 0x64h- Corresponds to 100mA.
Bit Number
Bit Name
Description
7:0
HC_MAX_C_BP Hub Controller Max Current Bus-Powered: Value in 1mA increments that the
Hub consumes from an upstream port when operating as a bus- powered hub.
Example: A value of 8mA would be written to this register as 0x08h
5.3.17
REGISTER 10H: POWER-ON TIME - PWRT
Default = 0x00h - Corresponds to 0ms. Required for a hub with no power switches
Bit Number
Bit Name
Description
7:0
POWER_ON_TI Power On Time: The length of time that is takes (in 2 ms intervals) from the
ME
time the host initiated power-on sequence begins on a port until power is good
on that port. System software uses this value to determine how long to wait
before accessing a powered-on port. Setting affects only the hub descriptor field
“PwrOn2PwrGood” see Section 7.4, "Class-Specific Hub Descriptor," on
page 45.
Note:
This register represents time from when a host sends a SetPortFeature(PORT_POWER) request to the
time power is supplied through an external switch to a downstream port. It should be set to 0 if no power
switch is used- for instance within a compound device.
5.3.18
REGISTER 11H: LANGUAGE ID HIGH - LANGIDH
Default = 0x04h - Corresponds to US English code 0x0409h
Bit Number
Bit Name
Description
7:0
LANG_ID_H
USB LANGUAGE ID (Upper 8 bits of a 16 bit ID field)
5.3.19
REGISTER 12H: LANGUAGE ID LOW - LANGIDL
Default = 0x09h - Corresponds to US English code 0x0409h
Bit Number
Bit Name
Description
7:0
LANG_ID_L
USB LANGUAGE ID (lower 8 bits of a 16 bit ID field)
5.3.20
REGISTER 13H: MANUFACTURER STRING LENGTH - MFRSL
Default = 0x00h
Bit Number
Bit Name
Description
7:0
MFR_STR_LEN Manufacturer String Length
DS00001584C-page 26
2011-2020 Microchip Technology Inc.
USB3503
5.3.21
REGISTER 14H: PRODUCT STRING LENGTH - PRDSL
Default = 0x00h
Bit Number
Bit Name
Description
7:0
PRD_STR_LEN Product String Length
5.3.22
REGISTER 15H: SERIAL STRING LENGTH - SERSL
Default = 0x00h
Bit Number
Bit Name
Description
7:0
SER_STR_LEN Serial String Length
5.3.23
REGISTER 16H-53H: MANUFACTURER STRING - MANSTR
Default = 0x00h
Bit Number
Bit Name
Description
7:0
MFR_STR
Manufacturer String, UNICODE UTF-16LE per USB 2.0 Specification
Note: The String consists of individual 16 Bit UNICODE UTF-16LE characters.
The Characters will be stored starting with the LSB at the least
significant address and the MSB at the next 8-bit location (subsequent
characters must be stored in sequential contiguous address in the
same LSB, MSB manner). Please pay careful attention to the Byte
ordering or your selected programming tools.
5.3.24
REGISTER 54H-91H: PRODUCT STRING - PRDSTR
Default = 0x00h
Bit Number
Bit Name
Description
7:0
PRD_STR
Product String, UNICODE UTF-16LE per USB 2.0 Specification
Note: The String consists of individual 16 Bit UNICODE UTF-16LE characters.
The Characters will be stored starting with the LSB at the least
significant address and the MSB at the next 8-bit location (subsequent
characters must be stored in sequential contiguous address in the
same LSB, MSB manner). Please pay careful attention to the Byte
ordering or your selected programming tools.
5.3.25
REGISTER 92H-CFH: SERIAL STRING - SERSTR
Default = 0x00h
Bit Number
Bit Name
Description
7:0
SER_STR
Serial String, UNICODE UTF-16LE per USB 2.0 Specification
Note: The String consists of individual 16 Bit UNICODE UTF-16LE characters.
The Characters will be stored starting with the LSB at the least
significant address and the MSB at the next 8-bit location (subsequent
characters must be stored in sequential contiguous address in the
same LSB, MSB manner). Please pay careful attention to the Byte
ordering or your selected programming tools.
2011-2020 Microchip Technology Inc.
DS00001584C-page 27
USB3503
5.3.26
REGISTER D0: DOWNSTREAM BATTERY CHARGING ENABLE - BC_EN
Default = 0x00h
Bit Number
Bit Name
Description
7:0
BC_EN
Battery Charging Enable: Enables the battery charging feature for the
corresponding downstream port.
‘0’ = Downstream Battery Charging support is not enabled.
‘1’ = Downstream Battery charging support is enabled
Bit 7= Reserved
Bit 6= Reserved
Bit 5= Reserved
Bit 4= Reserved
Bit 3= Port 3 Battery Charging Enable.
Bit 2= Port 2 Battery Charging Enable.
Bit 1= Port 1 Battery Charging Enable.
Bit 0= Reserved
5.3.27
REGISTER E5H: PORT POWER STATUS - PRTPWR
Default = 0x00h
Bit Number
Bit Name
Description
7:4
3:1
Reserved
Reserved.
PRTPWR[3:1] Read Only.
Optional status to SOC indicating that power to the downstream port was
enabled by the USB Host for the specified port. Not required for an embedded
application.
This is a read-only status bit. Actual control over port power is implemented by
the USB Host, OCS register and Downstream Battery Charging logic if enabled.
See Section 8.1.2, "Special Behavior of PRTPWR Register," on page 48 for
more information.
0 = USB Host has not enabled port to be powered or in downstream battery
charging and corresponding OCS bit has been set.
1 = USB Host has enabled port to be powered
0
Reserved
Reserved.
DS00001584C-page 28
2011-2020 Microchip Technology Inc.
USB3503
5.3.28
REGISTER E6H: OVER CURRENT SENSE CONTROL - OCS
Default = 0x00h
Bit Number
Bit Name
Description
7:4
3
Reserved
OCS[3]
Reserved. {Note: Software must never write a ‘1’ to these bits}
When SP_ILOCK.OcsPinSel = 1
Register Bit is reserved. Setting bit has no effect on HUB operation, instead
OCS_N device pin controls over current condition reporting.
When SP_ILOCK.OcsPinSel = 0
Optional control from SOC on indicating external current monitor indicating an
over-current condition on port 3 for HUB status reporting to USB host. Also
resets corresponding PRTPWR status register bit. Not required for an
embedded application.
0 = No Over Current Condition
1 = Over Current Condition
2:1
OCS[2:1]
Reserved
Optional control from SOC on indicating external current monitor indicating an
over-current condition on the specified port for HUB status reporting to USB
host. Also resets corresponding PRTPWR status register bit. Not required for
an embedded application.
0 = No Over Current Condition
1 = Over Current Condition
0
Reserved.
5.3.29
REGISTER E7H: SERIAL PORT INTERLOCK CONTROL - SP_ILOCK
Default=0x32h - Corresponds to OCS_N/PRT_PWR pins & pausing to connect until write from I2C
Bit Number
Bit Name
Description
7:6
Reserved
Reserved
5
4
OcsPinSel
1= OCS device pin will assume role as an active low Over Current Sense input
0= OCS device pin disabled, register control established
PrtPwrPinSel 1=PRTPWR device pin will assume role as an active high Port Power Switch
Control output
0=PRTPWR device pin disabled, register control established
3:2
1
Reserved
connect_n
Reserved
The SOC can utilize this bit to control when the hub attempts to connect to the
upstream host.
1 = Device will remain in Hub Mode.Connect Stage indefinitely until bit is
cleared by the SOC.
0 = Device will transition to the Hub Mode.Communication Stage after this bit
is asserted low by default or through a serial port write.
2011-2020 Microchip Technology Inc.
DS00001584C-page 29
USB3503
Bit Number
Bit Name
config_n
Description
0
If the SOC intends to update the default configuration using the serial port, this
register should be the first register updated by the SOC. In this way the timing
dependency between configuration and device operation can be minimized- the
SOC is only required to write to Serial Port Interlock Register within Thubconfig
and not all the registers it is attempting to configure.
Once all registers have been written for the desired configuration, the SOC
must clear this bit to ‘0’ for the device to resume normal operation using the
new configuration.
It may be desirable for the device to initiate autonomous operation with no SOC
intervention at all. This is why the default setting is to allow the device to initiate
automatic operation if the SOC does not intervene by writing the interlock
register within the allotted configuration timeout.
1 = Device will remain in Hub Mode.Configuration Stage indefinitely, and allow
SOC to write through the serial port to set any desired configuration.
0 = Device will transition out of Hub.Configuration Stage immediately after this
bit is asserted low through a serial port write. (A default low assertion results in
transition after a timeout.)
5.3.30
REGISTER E8H: SERIAL PORT INTERRUPT STATUS - INT_STATUS
Default = 0x00h
Bit Number
Bit Name
Description
7
Interrupt
Read:
1 = INT_N pin has been asserted low due to unmasked interrupt
0 = INT_N pin has not been asserted low due to unmasked interrupt
Write:
1 = No Effect – INT_N pin and register retains its current value
0 = Negate INT_N pin high
6:5
4
Reserved
Reserved
HubSuspInt
Read:
1 = Hub has entered USB suspend
0 = Hub has not entered USB suspend since last HubSuspInt reset
Write:
1 = No Effect
0 = Negate HubSuspInt status low
3
2
HubCfgInt
PrtPwrInt
Reserved
Read:
1 = Hub has been configured by USB Host
0 = Hub has not been configured by USB Host since last HubConfInt reset
Write:
1 = No Effect
0 = Negate HubConfInt status low
Read:
1 = Port Power register has been updated
0 = Port Power register has not been updated since last PrtPwrInt reset
Write:
1 = No Effect
0 = Negate PrtPwrInt status low
1:0
Reserved
DS00001584C-page 30
2011-2020 Microchip Technology Inc.
USB3503
5.3.31
REGISTER E9H: SERIAL PORT INTERRUPT MASK - INT_MASK
Default = 0x00h
Bit Number
Bit Name
Description
7:5
Reserved
Reserved
4
3
2
HubSuspMask 1 = INT_N pin is asserted low when Hub enters suspend
0 = INT_N pin is not affected by Hub entering suspend
HubCfgMask 1 = INT_N pin is asserted low when Hub configured by USB Host
0 = INT_N pin is not affected by Hub configuration event
PrtPwrMask
1 = INT_N pin is asserted low when Port Power register has been updated by
USB Host
0 = INT_N pin is not affected by Port Power register
1:0
Reserved
Reserved
5.3.32
REGISTER EEH: CONFIGURE PORTABLE HUB - CFGP
Default = 0x00h - Corresponds to 95ms startup & Phone RefClks available
Bit Number
Bit Name
Description
7
ClkSusp
(Read/Write)
1 = Force device to run internal clock even during USB suspend (will cause
device to violate USB suspend current limit - intended for test or self-powered
applications which require use of serial port during USB session.)
0 = Allow device to gate off its internal clocks during suspend mode in order to
meet USB suspend current requirements.
6
IntSusp
(Read/Write)
1 = INT_N pin function is a level sensitive USB suspend interrupt indication.
Allows system to adjust current consumption to comply with USB specification
limits when hub is in the USB suspend state.
0 = INT_N pin function retains event sensitive role of a general serial port
interrupt.
See Section 3.3.4, "Interrupt," on page 13 for more information.
5:4
CfgTout
(Read Only)
Specifies timeout value for allowing SOC to configure the device. Corresponds
to the Thubconfig parameter. See Section TABLE 4-2:, "Timing Parameters for
Hub Stages".
‘00’ = 95ms - Use to meet legacy 100ms connect timing
Reserved
3
Reserved
Reserved
2:0
Reserved
2011-2020 Microchip Technology Inc.
DS00001584C-page 31
USB3503
5.3.33
REGISTER F4H: VARISENSE_UP3 - VSNSUP3
Default = 0x00h
Bit Number
Bit Name
Description
7:3
2:0
Reserved
Reserved
DN3_SQUELC These two bits control the Squelch setting of the downstream port 3.
H
‘000’ = Nominal value
‘001’ = 90% of Nominal value
‘010’ = 80% of Nominal value
‘011’ = 70% of Nominal value
‘100’ = 60% of Nominal value
‘101’ = 50% of Nominal value
‘110’ = 120% of Nominal value
‘111’ = 110% of Nominal value
5.3.34
REGISTER F5H: VARISENSE_21 - VSNS21
Default = 0x00h
Bit Number
Bit Name
Description
7
Reserved
Reserved
6:4
DN2_SQUELC These two bits control the Squelch setting of the downstream port 2.
H
‘000’ = Nominal value
‘001’ = 90% of Nominal value
‘010’ = 80% of Nominal value
‘011’ = 70% of Nominal value
‘100’ = 60% of Nominal value
‘101’ = 50% of Nominal value
‘110’ = 120% of Nominal value
‘111’ = 110% of Nominal value
3
Reserved
Reserved
2:0
DN1_SQUELC These three bits control the Squelch setting of the downstream port 1.
H
‘000’ = Nominal value
‘001’ = 90% of Nominal value
‘010’ = 80% of Nominal value
‘011’ = 70% of Nominal value
‘100’ = 60% of Nominal value
‘101’ = 50% of Nominal value
‘110’ = 120% of Nominal value
‘111’ = 110% of Nominal value
5.3.35
REGISTER F6H: BOOST_UP3 - BSTUP3
Default = 0x30h
Bit Number
Bit Name
Description
7:3
2:0
Reserved
Reserved
BOOST_IOUT_ USB electrical signaling drive strength Boost Bit for Downstream Port ‘3’.
3
Boosts USB High Speed Current.
3’b000: Nominal
3’b001: -5%
3’b010: +10%
3’b011: +5%
3’b100: +20%
3’b101: +15%
3’b110: +30%
3’b111: +25%
DS00001584C-page 32
2011-2020 Microchip Technology Inc.
USB3503
5.3.36
REGISTER F8H: BOOST_21 - BST21
Default = 0x00h
Bit Number
Bit Name
Description
7
Reserved
Reserved
6:4
BOOST_IOUT_ USB electrical signaling drive strength Boost Bit for Downstream Port ‘2’.
2
Boosts USB High Speed Current.
3’b000: Nominal
3’b001: -5%
3’b010: +10%
3’b011: +5%
3’b100: +20%
3’b101: +15%
3’b110: +30%
3’b111: +25%
3
Reserved
Reserved
2:0
BOOST_IOUT_ USB electrical signaling drive strength Boost Bit for Downstream Port ‘1’.
1
Boosts USB High Speed Current.
3’b000: Nominal
3’b001: -5%
3’b010: +10%
3’b011: +5%
3’b100: +20%
3’b101: +15%
3’b110: +30%
3’b111: +25%
5.3.37
REGISTER FAH: PORT SWAP - PRTSP
Default = 0x00h
Bit Number
Bit Name
Description
7:0
PRTSP
Port Swap: Swaps the Upstream HSIC and Downstream USB DP and DM Pins
for ease of board routing to devices and connectors.
‘0’ = USB D+ functionality is associated with the DP pin and D- functionality is
associated with the DM pin.
‘1’ = USB D+ functionality is associated with the DM pin and D- functionality is
associated with the DP pin.
Bit 7= Reserved
Bit 6= Reserved
Bit 5= Reserved
Bit 4= Reserved
Bit 3= Port 3 DP/DM Swap.
Bit 2= Port 2 DP/DM Swap.
Bit 1= Port 1 DP/DM Swap.
Bit 0= Reserved
2011-2020 Microchip Technology Inc.
DS00001584C-page 33
USB3503
5.3.38
REGISTER FBH: PORT REMAP 12 - PRTR12
Default = 0x21h - Physical Port is mapped to the corresponding logical port.
Bit Number
Bit Name
Description
Port remap register for ports 1 & 2.
7:0
PRTR12
When a hub is enumerated by a USB Host Controller, the hub is only permitted
to report how many ports it has, the hub is not permitted to select a numerical
range or assignment. The Host Controller will number the downstream ports of
the hub starting with the number ‘1’, up to the number of ports that the hub
reported having.
The host’s port number is referred to as “Logical Port Number” and the physical
port on the hub is the Physical Port Number”. When remapping mode is
enabled (see PRTMAP_EN in Section 5.3.9) the hub’s downstream port
numbers can be remapped to different logical port numbers (assigned by the
host.)
Note: the customer must ensure that Contiguous Logical Port Numbers are
used, starting from #1 up to the maximum number of enabled ports, this
ensures that the hub’s ports are numbered in accordance with the way a Host
will communicate with the ports.
Bit [7:4] = ‘0000’ Physical Port 2 is Disabled
‘0001’ Physical Port 2 is mapped to Logical Port 1
‘0010’ Physical Port 2 is mapped to Logical Port 2
‘0011’ Physical Port 2 is mapped to Logical Port 3
‘0100’ Reserved, will default to ‘0000’ value
‘0101’ Reserved, will default to ‘0000’ value
to
‘1111’
Bit [3:0] = ‘0000’ Physical Port 1 is Disabled
‘0001’ Physical Port 1 is mapped to Logical Port 1
‘0010’ Physical Port 1 is mapped to Logical Port 2
‘0011’ Physical Port 1 is mapped to Logical Port 3
‘0100’ Reserved, will default to ‘0000’ value
‘0101’ Reserved, will default to ‘0000’ value
to
‘1111’
DS00001584C-page 34
2011-2020 Microchip Technology Inc.
USB3503
5.3.39
REGISTER FCH: PORT REMAP 34 - PRTR34
Default = 0x03h - Physical port is mapped to corresponding logical port.
Bit Number
Bit Name
Description
7:0
PRTR34
Port remap register for ports 3.
When a hub is enumerated by a USB Host Controller, the hub is only permitted
to report how many ports it has, the hub is not permitted to select a numerical
range or assignment. The Host Controller will number the downstream ports of
the hub starting with the number ‘1’, up to the number of ports that the hub
reported having.
The host’s port number is referred to as “Logical Port Number” and the physical
port on the hub is the Physical Port Number”. When remapping mode is enabled
(see PRTMAP_EN in Section 5.3.9) the hub’s downstream port numbers can be
remapped to different logical port numbers (assigned by the host).
Note: the customer must ensure that Contiguous Logical Port Numbers are
used, starting from #1 up to the maximum number of enabled ports, this ensures
that the hub’s ports are numbered in accordance with the way a Host will
communicate with the ports.
Bit [7:4] = ‘0000’ Reserved – software must not write ‘1’ to any of these bits.
‘0001’ Reserved, will default to ‘0000’ value
to
‘1111’
Bit [3:0] = ‘0000’ Physical Port 3 is Disabled
‘0001’ Physical Port 3 is mapped to Logical Port 1
‘0010’ Physical Port 3 is mapped to Logical Port 2
‘0011’ Physical Port 3 is mapped to Logical Port 3
‘0100’ Reserved, will default to ‘0000’ value Physical Port 3 is
mapped to Logical Port 4
‘0101’ Reserved, will default to ‘0000’ value
to
‘1111’
5.3.40
REGISTER FFH: STATUS/COMMAND - STCD
Default = 0x00h
Bit Number
Bit Name
Description
7:2
1
Reserved
RESET
Reserved {Note: Software must never write a ‘1’ to these bits}
Reset the Serial Interface and internal memory registers in address
range 00h-E1h and EFh-FFh back to RESET_N assertion default
settings. {Note: During this reset, this bit is automatically cleared to its
default value of 0.}
0 = Normal Run/Idle State.
1 = Force a reset of the registers to their default state.
0
CONFIG_PROTECT Protect the Configuration
0 = serial slave interface is active.
1 = The internal configuration memory (address range 00h-E1h and EFh-
FFh) is “write-protected” to prevent unintentional data corruption.
{Note 1: This bit is write once and is only cleared by assertion of the
external RESET_N pin.}
2011-2020 Microchip Technology Inc.
DS00001584C-page 35
USB3503
6.0
SERIAL SLAVE INTERFACE
6.1
Overview
The serial slave interface on USB3503 is implemented as I2C. It is a standard I2C slave interface that operates at the
standard (100Kbps), fast (400Kbps), and the fast mode plus (1Mbps) modes.
The USB3503 I2C slave interface address is 0x08h.
REFCLK must be running for I2C to operate. The register map is outlined in section Section 5.3.
The I2C Slave Base Address is 0x08. The interrupt pin INT_N is used to communicate status changes on selected
events that are mapped into the Serial Port Interrupt Status Register. INT_N is asserted low whenever an unmasked bit
is set in the Serial Port Interrupt Status Register. SOC must update the Serial Port Interrupt Status Register to negate
the interrupt high.
The SOC can mask events to not cause the interrupt pin to transition by updating the Serial Port Interrupt Mask Register.
The status events will still be captured in the status register even if the interrupt pin is not asserted. The serial port has
limited speed and latency capability so events mapped into the serial ports and its interrupt are not expected to be
latency critical.
6.2
Interconnecting the USB3503 to an I2C Master
FIGURE 6-1:
I2C CONNECTIONS
SOC
VDD
SCL
SCL
SDA
INT
SDA
INT
I2C
MASTER
CONTROLLER
USB3503
Note 6-1
The largest pullup values which meet the customer application should be selected in order to
minimize power consumption. Pullup values must also have low enough resistance to support the
desired i2C operating speed with the expected total capacitance in the application. Typical
applications are expected to use pullup values between 220Ω and 2.7kΩ for operation at 1MHz on
SCL and SDA. Larger pullup resistors may be acceptable for operation at 400KHz or 100KHz.
DS00001584C-page 36
2011-2020 Microchip Technology Inc.
USB3503
6.3
I2C Message format
6.3.1
SEQUENTIAL ACCESS WRITES
The I2C interface will support sequential writing of the register address space of the USB3503. This mode is useful for
configuring contiguous blocks of registers. Please see section on SOC interface for address definitions. Figure 6-2
shows the format of the sequential write operation. Where color is visible in the figure, blue indicates signaling from the
I2C master, and gray indicates signaling from the USB3503 slave:
FIGURE 6-2:
I2C SEQUENTIAL ACCESS WRITE FORMAT
S
7-Bit Slave Address
0
A
xxxxxxxx
A
nnnnnnnn
A
...
nnnnnnnn
A
P
Register
Address
(bits 7-0)
Data value for
XXXXXX
Data value for
XXXXXX + y
In this operation, following the 7-bit slave address, an 8-bit register address is written indicating the start address for
sequential write operation. Every data access after that is a data write to a data register where the register address incre-
ments after each access and ACK from the slave must occur. Sequential write access is terminated by a Stop condition.
6.3.2
SEQUENTIAL ACCESS READS
The I2C interface will support direct reading of the USB3503 registers. In order to read one or more register addresses,
the starting address must be set by using a write sequence followed by a read. The read register interface supports
auto-increment mode. The master should send a NACK instead of an ACK when the last byte has been transferred.
In this operation, following the 7-bit slave address, 8-bit register address is written indicating the start address for
sequential read operation to be followed. In the read sequence, every data access is a data read from a data register
where the register address increments after each access. Write sequence can end with optional Stop (P). If so the Read
sequence must start with a Start (S) otherwise it must start with Repeated Start (Sr).
Figure 6-3 shows the format of the read operation. Where color is visible in the figure, blue and gold indicate signaling
from the I2C master, and gray indicates signaling from the USB3503 slave.
FIGURE 6-3:
SEQUENTIAL ACCESS READ FORMAT
O
c
p
e
r w i s
t i o
n
m
a
l . I f
p
h
e
r e
v
a
s
e
e
n
t ,
t a r t ( S ) ,
t a r t ( S r )
N e x t
a
o
c
s
s
u
s
t
a
S
t h
e
e
R
e
p
t
S
S
7
- B i t
S
l a
v
e
A
d
d
r e
s
s
0
A
x
x
x
x
x
x
x
x
A
P
R
A
e g i s t e r
d
d
r e
7
s s
( b i t s
- 0 )
If p re v io u s w rit e s e ttin g u p
R e g is t e r a d d r e s s e n d e d w ith
S t o p ( P ) , o t h e r w is e it w ill b e
R e p e a te d S ta r t ( S r )
a
S
7 -B it S la v e A d d re s s
1
A C K
n
n
n
n
n
n
n
n
A C K
n
n
n
n
n
n
n
n
A C K
...
n
n
n
n
n
n
n
n
N A C K
P
R e g is t e r v a lu e
f o r x x x x x x x x
R e g is te r v a lu e
fo r x x x x x x x x
R e g is t e r v a lu e
fo r x x x x x x x x
+
1
+
y
2011-2020 Microchip Technology Inc.
DS00001584C-page 37
USB3503
6.3.3
I2C TIMING
Below is the timing diagram and timing specifications for the different I2C modes that the USB3503 supports.
FIGURE 6-4:
I2C TIMING DIAGRAM
I2C_DATA
t
t
LOW
BUF
t
t
t
HD;STA
R
F
2
I C_CLK
t
HD;STA
t
SU;STO
t
t
t
t
SU;STA
HD;DAT
HIGH
SU;DAT
FIGURE 6-5:
I2C TIMING SPECIFICATIONS
Standard-Mode
Fast-Mode
Fast-Mode Plus
Symbol
Parameter
Unit
MIN
MAX
MIN
MAX
MIN
MAX
fSCL
tHD;STA
tLOW
SCL clock
frequency
0
100
0
400
0
1000
KHz
μs
Hold time
START condition
4
0.6
1.3
0.6
0.6
0.26
0.5
LOW period of the
SCL clock
4.7
4
μs
tHIGH
HIGH period of the
SCL clock
0.26
0.26
μs
tSU;STA
Set-up time for a
repeated START
condition
4.7
μs
tHD;DAT
tSU;DAT
tR
DATA hold time
0
0
0
ns
ns
ns
DATA set-up time
250
100
50
Rise time of both
SDA and SCL
signals
1000
300
300
300
120
120
tF
Fall time of both
SCL and SDA lines
ns
μs
μs
tSU;STO
Set-up time for a
STOP condition
4
0.6
1.3
0.26
0.5
tBUF
Bus free time
between a STOP
and START
4.7
condition
DS00001584C-page 38
2011-2020 Microchip Technology Inc.
USB3503
7.0
USB DESCRIPTORS
A customer can indirectly affect which descriptors are reported via one of two methods. The two methods are: Internal
Default ROM Configuration, or direct load through the serial port interface.
The Hub will not electrically attach to the USB until after it has loaded valid data for all user- defined descriptor fields
(either through Internal Default ROM, or serial port).
7.1
USB Bus Reset
In response to the upstream port signaling a reset to the Hub, the Hub does the following:
Note 7-1 The Hub does not propagate the upstream USB reset to downstream devices.
• Sets default address to 0.
• Sets configuration to: Unconfigured.
• Negates PRTPWR[3:1] register for all downstream ports.
• Clears all TT buffers.
• Moves device from suspended to active (if suspended).
• Complies with Section 11.10 of the USB 2.0 Specification for behavior after completion of the reset sequence.
The Host then configures the Hub and the Hub's downstream port devices in accordance with the USB Specification.
7.2
Hub Attached as a High-Speed Device (Customer-Configured for Single-TT Support
Only)
The following tables provide descriptor information for Customer-Configured Single-TT-Only Hubs attached for use with
High-Speed devices.
7.2.1
STANDARD DEVICE DESCRIPTOR
The following table provides device descriptor values for High-Speed operation.
TABLE 7-1:
Offset
DEVICE DESCRIPTOR
Field
Size
Value
Description
Size of this Descriptor.
0
1
2
4
5
6
7
8
Length
DescriptorType
USB
1
1
2
1
1
1
1
2
12h
01h
Device Descriptor Type.
0200h
09h
USB Specification Release Number.
Class code assigned by USB-IF for Hubs.
Class code assigned by USB-IF for Hubs.
Protocol Code.
DeviceClass
DeviceSubClass
DeviceProtocol
MaxPacketSize0
Vendor
00h
01h
40h
64-byte packet size.
user/
Vendor ID; Customer value defined in ROM or serial port
default load.
10
12
14
Product
Device
2
2
1
user/
default port load.
Product ID; Customer value defined in ROM or serial
user/
default load
Device ID; Customer value defined in ROM or serial port
Manufacturer
xxh
If STRING_EN =0 Optional string is not supported, and
xx = 00.
If STRING_EN = 1, String support is enabled, and
xx = 01
15
Product
1
yyh
If STRING_EN =0 Optional string is not supported, and
yy = 00.
If STRING_EN = 1, String support is enabled, and
yy = 02
2011-2020 Microchip Technology Inc.
DS00001584C-page 39
USB3503
TABLE 7-1:
Offset
DEVICE DESCRIPTOR (CONTINUED)
Field
Size
Value
Description
16
SerialNumber
1
zzh
If STRING_EN =0 Optional string is not supported, and
zz = 00.
If STRING_EN = 1, String support is enabled, and
zz = 03
17
NumConfigurations
1
01h
Supports 1 configuration.
7.2.2
CONFIGURATION DESCRIPTOR
The following table provides configuration descriptor values for High-Speed, Single-TT-Only operation.
TABLE 7-2:
OFFSET
CONFIGURATION DESCRIPTOR (HIGH-SPEED, SINGLE-TT ONLY)
FIELD
SIZE
VALUE
DESCRIPTION
Size of this Descriptor.
0
1
2
Length
1
1
2
09h
02h
DescriptorType
TotalLength
Configuration Descriptor Type.
yyyyh
Total combined length of all descriptors for this
configuration (configuration, interface, endpoint, and
class- or vendor-specific).
yyyyh = 0019h
4
5
NumInterfaces
1
1
01h
Number of interfaces supported by this configuration.
ConfigurationValue
01H
Value to use as an argument to the SetConfiguration()
request to select this configuration.
6
7
Configuration
Attributes
1
1
00h
Index of string descriptor describing this configuration
(string not supported).
user/
signal
Configuration characteristics: Communicates the
capabilities of the hub regarding Remote Wake-up
capability, and also reports the self-power status. In all
cases, the value reported to the host always indicates
that the hub supports Remote Wakeup.
The value reported to the host is dependant upon the
SELF_BUS_PWR bit (CONFIG_BYTE_1)
= A0h for Bus-Powered (SELF_BUS_PWR = 0).
= E0h for Self-Powered (SELF_BUS_PWR = 1).
All other values are reserved.
8
MaxPower
1
user
Maximum Power Consumption of the Hub from VBUS
when fully operational. This value includes all support
circuitry associated with the hub (including an attached
“embedded” peripheral if hub is part of a compound
device), and is in 2mA increments. The Hub supports
Self-Powered and Bus-Powered operation. The
SELF_BUS_PWR bit (CONFIG_BYTE_1) is used to
determine which of the values below are reported. The
value reported to the host must coincide with the current
operating mode, and will be determined by the following
rules.
The value that is reported to the host will be:
‘MAX_PWR_BP’ if SELF_BUS_PWR = ‘0’
‘MAX_PWR_SP’ if SELF_BUS_PWR = ‘1’
In all cases the reported value is sourced from the MAX
POWER data field (for Self or Bus power) that was
loaded by Internal Default, or serial port configuration.
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USB3503
7.2.3
INTERFACE DESCRIPTOR (SINGLE-TT)
The following table provides interface descriptor values for High-Speed, Single-TT operation.
TABLE 7-3:
Offset
INTERFACE DESCRIPTOR (HIGH-SPEED, SINGLE-TT)
Field
Size
Value
Description
Size of this Descriptor.
0
1
2
3
Length
1
1
1
1
09h
04h
00h
00h
DescriptorType
InterfaceNumber
AlternateSetting
Interface Descriptor Type.
Number of this interface.
Value used to select this alternate setting for the
interface.
4
NumEndpoints
1
01h
Number of endpoints used by this interface (not including
endpoint 0).
5
6
7
8
InterfaceClass
InterfaceSubclass
InterfaceProtocol
Interface
1
1
1
1
09h
00h
00h
00h
Hub class code.
Subclass code.
Single-TT.
Index of the string descriptor describing this interface
(strings not supported).
7.2.4
ENDPOINT DESCRIPTOR (SINGLE-TT)
The following table provides endpoint descriptor values for Single-TT operation.
TABLE 7-4:
Offset
ENDPOINT DESCRIPTOR (FOR STATUS CHANGE ENDPOINT, SINGLE-TT)
Field
Size
Value
Description
Size of this Descriptor.
0
1
2
3
Length
1
1
1
1
07h
05h
81h
03h
DescriptorType
EndpointAddress
Attributes
Endpoint Descriptor Type.
The address of the endpoint on the USB device.
Describes the endpoint’s attributes. (interrupt only, no
synchronization, data endpoint).
4
6
MaxPacketSize
Interval
2
1
0001h Maximum packet size for this endpoint.
0Ch
Interval for polling endpoint for data transfers (Maximum
Possible).
7.3
Hub Attached as a High-Speed Device (Customer-Configured as Multi-TT Capable)
The following tables provide descriptor information for Customer-Configured Multi-TT High-Speed devices.
7.3.1
STANDARD DEVICE DESCRIPTOR
The following table provides device descriptor values for High-Speed operation.
TABLE 7-5:
Offset
DEVICE DESCRIPTOR (HIGH-SPEED)
Field
Size
Value
Description
0
1
2
4
5
6
7
8
Length
DescriptorType
USB
1
1
2
1
1
1
1
2
12
Size of this Descriptor
Device Descriptor Type.
01h
0200h USB Specification Release Number.
DeviceClass
DeviceSubClass
DeviceProtocol
MaxPacketSize0
Vendor
09h
00h
02h
40h
user
Class code assigned by USB-IF for Hubs.
Class code assigned by USB-IF for Hubs.
Protocol code (Multi-TTs).
64-byte packet size.
Vendor ID; Customer value defined in ROM or serial port
load.
10
Product
2
user
Product ID; Customer value defined in ROM or serial port
load.
2011-2020 Microchip Technology Inc.
DS00001584C-page 41
USB3503
TABLE 7-5:
Offset
DEVICE DESCRIPTOR (HIGH-SPEED) (CONTINUED)
Field
Size
Value
Description
12
Device
2
user
Device ID; Customer value defined in ROM or serial port
load.
14
15
16
17
Manufacturer
Product
1
1
1
1
xxh
yyh
zzh
01h
If STRING_EN =0 Optional string is not supported, and xx
= 00.
If STRING_EN = 1, String support is enabled, and
xx = 01
If STRING_EN =0 Optional string is not supported, and yy
= 00.
If STRING_EN = 1, String support is enabled, and
yy = 02
SerialNumber
NumConfigurations
If STRING_EN =0 Optional string is not supported, and zz
= 00.
If STRING_EN = 1, String support is enabled, and
zz = 03
Supports 1 configuration.
7.3.2
CONFIGURATION DESCRIPTOR
The following table provides configuration descriptor values for High-Speed operation.
TABLE 7-6:
Offset
CONFIGURATION DESCRIPTOR (HIGH-SPEED)
Field
Size
Value
Description
Size of this Descriptor.
0
1
2
Length
1
1
2
09h
02h
DescriptorType
TotalLength
Configuration Descriptor Type.
yyyyh
Total combined length of all descriptors for this
configuration (configuration, interface, endpoint, and
class- or vendor-specific).
yyyyh = 0029h.
4
5
NumInterfaces
1
1
01h
01H
Number of Interface supported by this configuration.
ConfigurationValue
Value to use as an argument to the SetConfiguration()
request to select this configuration.
6
7
Configuration
Attributes
1
1
00h
Index of string descriptor describing this configuration
(String not supported).
user/
signal
Configuration characteristics: Communicates the
capabilities of the hub regarding Remote Wake-up
capability, and also reports the self-power status. In all
cases, the value reported to the host always indicates
that the hub supports Remote Wakeup.
The value reported to the host is dependant upon the
SELF_BUS_PWR bit (CONFIG_BYTE_1)
= A0h for Bus-Powered (SELF_BUS_PWR = 0).
= E0h for Self-Powered (SELF_BUS_PWR = 1).
All other values are reserved.
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USB3503
TABLE 7-6:
CONFIGURATION DESCRIPTOR (HIGH-SPEED) (CONTINUED)
Offset
Field
Size
Value
Description
8
MaxPower
1
user
Maximum Power Consumption of the Hub from VBUS
when fully operational. This value includes all support
circuitry associated with the hub (including an attached
“embedded” peripheral if hub is part of a compound
device), and is in 2mA increments. The Hub supports
Self-Powered and Bus-Powered operation. The
SELF_BUS_PWR bit (CONFIG_BYTE_1) is used to
determine which of the values below are reported. The
value reported to the host must coincide with the current
operating mode, and will be determined by the following
rules.
The value that is reported to the host will be:
‘MAX_PWR_BP’ if SELF_BUS_PWR = ‘0’
‘MAX_PWR_SP’ if SELF_BUS_PWR = ‘1’
In all cases the reported value is sourced from the MAX
POWER data field (for Self or Bus power) that was
loaded by Internal Default, or serial port configuration.
7.3.3
INTERFACE DESCRIPTOR (SINGLE-TT)
The following table provides interface descriptor values for High-Speed Single-TT operation.
TABLE 7-7:
Offset
INTERFACE DESCRIPTOR (HIGH-SPEED, SINGLE-TT)
Field
Size
Value
Description
Size of this Descriptor.
0
1
2
3
4
Length
1
1
1
1
1
09h
04h
00h
00h
01h
DescriptorType
InterfaceNumber
AlternateSetting
NumEndpoints
Interface Descriptor Type.
Number of this interface.
Value used to select this alternate setting for the interface.
Number of endpoints used by this interface (not including
endpoint 0).
5
6
7
8
InterfaceClass
InterfaceSubclass
InterfaceProtocol
Interface
1
1
1
1
09h
00h
01h
00h
Hub class code.
Subclass code
Single-TT.
Index of the string descriptor describing this interface
(strings not supported).
7.3.4
ENDPOINT DESCRIPTOR (SINGLE-TT)
The following table provides endpoint descriptor values for Single-TT operation.
TABLE 7-8:
Offset
ENDPOINT DESCRIPTOR (FOR STATUS CHANGE ENDPOINT, SINGLE-TT)
Field
Size
Value
Description
Size of this Descriptor.
0
1
2
3
Length
1
1
1
1
07h
05h
81h
03h
DescriptorType
EndpointAddress
Attributes
Endpoint Descriptor Type.
The address of the endpoint on the USB device.
Describes the endpoint’s attributes. (interrupt only, no
synchronization, data endpoint).
4
6
MaxPacketSize
Interval
2
1
0001h Maximum packet size for this endpoint.
0Ch
Interval for polling endpoint for data transfers (Maximum
Possible).
2011-2020 Microchip Technology Inc.
DS00001584C-page 43
USB3503
7.3.5
INTERFACE DESCRIPTOR (MULTI-TT)
The following table provides interface descriptor values for High-Speed Multi-TT operation.
TABLE 7-9:
Offset
INTERFACE DESCRIPTOR (MULTI-TT, HIGH-SPEED)
Field
Size
Value
Description
Size of this Descriptor.
0
1
2
3
Length
1
1
1
1
09h
04h
00h
01h
DescriptorType
InterfaceNumber
AlternateSetting
Interface Descriptor Type.
Number of this interface.
Value used to select this alternate setting for the
interface.
4
NumEndpoints
1
01h
Number of endpoints used by this interface (not including
endpoint 0).
5
6
7
8
InterfaceClass
InterfaceSubclass
InterfaceProtocol
Interface
1
1
1
1
09h
00h
02h
00h
Hub class code.
Subclass code.
Multiple-TTs.
Index of the string descriptor describing this interface
(strings not supported).
7.3.6
ENDPOINT DESCRIPTOR (MULTI-TT)
The following table provides endpoint descriptor values for Multi-TT operation.
TABLE 7-10: ENDPOINT DESCRIPTOR (FOR STATUS CHANGE ENDPOINT, MULTI-TT)
Offset
Field
Size
Value
Description
Size of this Descriptor.
0
1
2
3
Length
1
1
1
1
07h
05h
81h
03h
DescriptorType
EndpointAddress
Attributes
Endpoint Descriptor Type.
The address of the endpoint on the USB device.
Describes the endpoint’s attributes. (interrupt only, no
synchronization, data endpoint).
4
6
MaxPacketSize
Interval
2
1
0001h Maximum packet size for this endpoint.
0Ch
Interval for polling endpoint for data transfers (Maximum
Possible).
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USB3503
7.4
Class-Specific Hub Descriptor
The following table provides class-specific Hub descriptor values.
Note:
The Hub must respond to Hub Class Descriptor type 29h (the USB 1.1 and USB 2.0 value) and 00h
(the USB 1.0 value).
TABLE 7-11: CLASS-SPECIFIC HUB DESCRIPTOR
Offset
Field
Size
Value
Description
0
1
2
Length
DescriptorType
NbrPorts
1
1
1
09h
29h
user
Size of this Descriptor.
Hub Descriptor Type.
Number of downstream facing ports this Hub supports.
See Section 11.23.2.1 of the USB Specification for
additional details regarding the use of this field.
The value reported is implementation dependent, and is
derived from the value defined during Internal Default, or
serial port load. The PORT_DIS_SP field defines the
ports that are permanently disabled when in Self-
Powered operation, and the PORT_DIS_BP field defines
the ports that are permanently disabled when in Bus-
Powered operation.
Internal logic will subtract the number of ports which are
disabled, from the total number available (which is 3),
and will report the remainder as the number of ports
supported. The value reported to the host must coincide
with the current operating mode, and will be determined
by the following rules.
The field used to determine the value that is reported to
the host will be:
‘PORT_DIS_BP’ if SELF_BUS_PWR = ‘0’
‘PORT_DIS_SP’ if SELF_BUS_PWR = ‘1’
3
HubCharacteristics
2
user
Defines support for Logical power switching mode,
Compound Device support, Over-current protection, TT
Think Time, and Port Indicator support, See Section
11.23.2.1 in the USB Specification for additional details
regarding the use of this field.
The values delivered to a host are all derived from values
defined during Internal Default, or serial port load, and
are assigned as follows:
D1:0 = ‘00’b if PORT_PWR = ‘0’
D1:0 = ‘01’b if PORT_PWR = ‘1’
D2 = ‘COMPOUND’
D4:3 = ‘CURRENT_SNS’
D6:5 = ‘00’b for 8FS (max) bit times of TT think time.
D7 = hardcoded to ‘0’ (no Port Indicator Support)
D15:8 = ‘00000000’b
2011-2020 Microchip Technology Inc.
DS00001584C-page 45
USB3503
TABLE 7-11: CLASS-SPECIFIC HUB DESCRIPTOR (CONTINUED)
Offset
Field
Size
Value
Description
5
PwrOn2PwrGood
1
user
Time (in 2 ms intervals) from the time the power-on
sequence begins on a port until power is good on that
port. See Section 11.23.2.1 in the USB Specification.
The value contained in the ‘POWER_ON_TIME’ field is
directly reported to the host, and is determined by
Internal Default, or serial port load.
6
HubContrCurrent
1
user
Maximum current requirements of the Hub Controller
electronics in 1 mA increments. See Section 11.23.2.1 in
the USB Specification for additional details on the use of
this field.
This field reports the maximum current that only the hub
consumes from upstream VBUS when fully operational.
This value includes all support circuitry associated with
the hub (but does not include the current consumption of
any permanently attached peripherals if the hub is part of
a compound device).
The Hub supports Self-Powered and Bus-Powered
operation. The SELF_BUS_PWR bit (CONFIG_BYTE_1)
defined in Section 5.3.7, "Register 06h:
CONFIG_BYTE_1 - CFG1," on page 22 is used to
determine which of the stored values are reported. The
value reported to the host must coincide with the current
operating mode, and will be determined by the following
rules.
The value that is reported to the host will be:
‘HC_MAX_C_BP’ if SELF_BUS_PWR = ‘0’
‘HC_MAX_C_SP’ if SELF_BUS_PWR = ‘1’
‘HC_MAX_C_BP/SP’ are defined in Section 5.3.15, and
Section 5.3.16, "Register 0Fh: Hub Controller Max
Current For Bus Powered Operation - HCMCB," on
page 26. In all cases the reported value is sourced from
the Hub Controller Max Current data field (for Self or Bus
power) that was determined by Internal Default, or serial
port load.
7
8
DeviceRemovable
PortPwrCtrlMask
1
1
user
FFh
Indicates if port has a removable device attached. See
Section 11.23.2.1 in the USB Specification.
The value contained in the ‘NR_DEVICE’ field is directly
reported to the host, and is determined by Internal
Default, or serial port load.
Field for backwards USB 1.0 compatibility.
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USB3503
7.5
String Descriptors
The USB3503 supports a 30 Character Manufacturer String Descriptor, a 30 Character Product String and a 30 charac-
ter Serial String.
7.5.1
STRING DESCRIPTOR ZERO (SPECIFIES LANGUAGES SUPPORTED)
TABLE 7-12: STRING DESCRIPTOR ZERO
Offset
Field
Size
Value
Description
0
1
2
Length
DescriptorType
LANGID
1
1
2
04h
03h
Size of this Descriptor.
String Descriptor Type.
xxxxh
Language ID code from LANG_ID_H and LANG_ID_L
registers
7.5.2
STRING DESCRIPTOR 1 (MANUFACTURER STRING)
TABLE 7-13: STRING DESCRIPTOR 1, MANUFACTURER STRING
Offset
Field
Size
Value
Description
0
Length
1
yyh
Size of this Descriptor. The yy value is created by taking
the MFR_STR_LEN{bytes} + 2{bytes}
1
2
DescriptorType
String
1
03h
String Descriptor Type.
Manufacturer String
N
string
The string is located in the MFR_STR register and the
size (N) is held in the MFR_STR_LEN register
7.5.3
STRING DESCRIPTOR 2 (PRODUCT STRING)
TABLE 7-14: STRING DESCRIPTOR 2, PRODUCT STRING
Offset
Field
Size
Value
Description
0
Length
1
yyh
Size of this Descriptor. The yy value is created by taking
the PRD_STR_LEN{bytes} + 2{bytes}
1
2
DescriptorType
String
1
03h
String Descriptor Type.
Product String
N
string
The string is located in the PROD_STR register and the
size (N) is held in the PRD_STR_LEN register
7.5.4
STRING DESCRIPTOR 3 (SERIAL STRING)
TABLE 7-15: STRING DESCRIPTOR 3, SERIAL STRING
Offset
Field
Size
Value
Description
0
Length
1
yyh
Size of this Descriptor. The yy value is created by taking
the SER_STR_LEN{bytes} + 2{bytes}
1
2
DescriptorType
String
1
03h
String Descriptor Type.
Serial String
N
string
The string is located in the SER_STR register and the
size (N) is held in the SER_STR_LEN register
2011-2020 Microchip Technology Inc.
DS00001584C-page 47
USB3503
8.0
8.1
BATTERY CHARGING
Downstream Port Battery Charging Support
The USB3503 can configure any of the downstream ports to support battery charger handshake.
The Hub’s role in downstream battery charging is to provide an acknowledge to a device’s query as to if the hub system
supports USB battery charging. The hub silicon does not provide any current or power FETs or any such thing to actually
charge the device. Those components would need to be provided as external components in the final Hub board design.
FIGURE 8-1:
BATTERY CHARGING EXTERNAL POWER SUPPLY
INT
DC Power
USB3503
(Serial Mapped
Register)
SCL
SDA
SOC
PRTPWR
VBUS
If the final Hub board design provides an external supply capable of supplying current per the battery charging specifi-
cation, the hub can be configured to indicate the presence of such a supply to the device. This indication is on a per/port
basis. i.e. the board can configure two ports to support battery charging (thru high current power FET’s) and leave the
other port as a standard USB port.
8.1.1
USB BATTERY CHARGING
In the terminology of the USB battery charging specification, if the port is configured to support battery charging, the
downstream port is a “Charging Host Port”. All AC/DC characteristics will comply with only this type. If the port is not
configured to support battery charging, the port is a “Standard Host Port”. AC/DC characteristics comply with the USB
2.0 specification.
Adownstream port will only behave as a “Charging Host Port” or a “Standard Host Port”. The port will not switch between
“Charging Host Port” or Standard Host Port” at any time after initial power-up and configuration.
8.1.2
SPECIAL BEHAVIOR OF PRTPWR REGISTER
The USB Battery charging specification does not address system issues. It only defines a low level protocol for a device
and host (or hub) to communicate a simple question and optional answer.
Device queries if the host to which it is connected supports battery charging.
The host will respond that it does support battery charging or does not respond at all. There is no negative response.
(A lack of response is taken as a negative response)
When ports are configured for downstream battery charging, the corresponding PRTPWR setting will be controlled by
downstream battery charging logic instead of the normal hub logic.
PRTPWR setting will assert after initial hub customer configuration (Internal default/Serial register writes). PRTPWR will
remain asserted and under the control of the battery charge logic until one of two events.
1. An overcurrent is detected on the corresponding OCS_N pin. In this case, PRTPWR setting will negate. The only
way to re-enable the PRTPWR setting from this state is to RESET the USB3503.
2. The hub enters Hub.Communication stage, connects on its upstream port and is enumerated by a USB host. In
this case, control over the PRTPWR setting reverts back to the hub logic inside the USB3503 and the normal
USB behavior applies. In this case, the host must enable PRTPWR.
Since the enumeration process for a hub sets the PORT_POWER feature for all downstream ports, this information can
be used to switch control over the PRTPWR setting between the battery charge logic and the hub logic.
• When the Hub PORT_POWER feature is ‘1’, the hub logic controls the PRTPWR setting.
• When the Hub PORT_POWER feature is ‘0’, the battery charging logic controls the PRTPWR setting.
DS00001584C-page 48
2011-2020 Microchip Technology Inc.
USB3503
No matter which controller is controlling the PRTPWR setting, an overcurrent event will always negate PRTPWR setting.
8.1.3
BATTERY CHARGING CONFIGURATION
Configuration of ports to support battery charging is done through serial port configuration load.
Register D0: Downstream Battery Charging Enable - BC_EN is allocated for Battery Charging support. The register,
starting from Bit 1, enables Battery charging for each down stream port when asserted. Bit 1 represents port 1 and so
on. Each port with battery charging enabled asserts the corresponding PRTPWR register bit.
2011-2020 Microchip Technology Inc.
DS00001584C-page 49
USB3503
9.0
9.1
INTEGRATED POWER REGULATORS
Overview
The integrated power regulators are designed to provide significant flexibility to the system in providing power to the
USB3503. Several different configurations are allowed in order to align the USB3503 power structure to the supplies
available in the system.
9.1.1
3.3V REGULATOR
The USB3503 has an integrated regulator to convert from VBAT to 3.3V.
9.1.2
1.2V REGULATOR
The USB3503 has an integrated regulator to convert from a variable voltage input on VDD_CORE_REG to 1.2V. The
1.2V regulator shall be tolerant to the presence of low voltage (~0V) on the VDD_CORE_REG pin in order to support
system power solutions where a 1.8V supply is not always present in low power states.
The 1.2V regulator shall support an input voltage range consistent with a 1.8V input in order to reduce power consump-
tion in systems which provide multiple power supply levels. In addition the 1.2V regulator shall support an input voltage
up to 3.3V for systems which provide only a single power supply. The device will support operation where the 3.3V reg-
ulator output can drive the 1.2V regulator input such that VBAT is the only required supply.
9.2
Power Configurations
The USB3503 support operation with no back current when power is connected in each of the following configurations.
9.2.1
SINGLE SUPPLY CONFIGURATIONS
VBAT Only
9.2.1.1
bit VBAT should be tied to the VBAT system supply. VDD33_BYP regulator output and VDD_CORE_REG should be
tied together on the board. In this configuration the 3.3V regulator will be active, and the 3.3V to 1.2V regulator will be
active.
9.2.1.2
3.3V Only
VBAT should be tied to the 3.3V system supply. VDD33_BYP and VDD_CORE_REG pins should be tied together on
the board. In this configuration, the 3.3V regulator will operate in dropout. The 1.2V regulator will be active.
9.2.2
DOUBLE SUPPLY CONFIGURATIONS
VBAT + 1.8V
9.2.2.1
VBAT should be tied to the VBAT system supply. VDD33_BYP regulator output requires external capacitor.
VDD_CORE_REG should be tied to the 1.8V system supply. In this configuration, the 3.3V regulator and the 1.2V reg-
ulator will be active.
9.2.2.2
3.3V + 1.8V
VBAT should be tied to the 3.3V system supply. VDD33_BYP should be connected to the 3.3V external capacitor.
VDD_CORE_REG should be tied to the 1.8v system supply. In this configuration the 3.3V regulator will operate in drop-
out. The 1.2V regulator will be active.
9.3
Regulator Control Signals
The regulators are controlled by RESET_N. When RESET_N is brought high the VDD33 regulator will turn on. When
RESET_N is brought low the VDD33 regulator will turn off.
DS00001584C-page 50
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USB3503
10.0 SPECIFICATIONS
10.1 Absolute Maximum Ratings
TABLE 10-1: ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Conditions
MIN
MAX
Units
VBAT
VBAT
VDD_CORE_REG
VDD33_BYP
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
0
5.5
4.6
4.6
4.6
3.6
5.5
70
V
V
V
V
V
V
C
C
C
C
VDD_CORE_REG
VDD33
Maximum IO Voltage to Ground VIO
REFCLK Voltage
VMAX_REFCLK
Voltage on USB+ and USB- pins VMAX_USB
Operating Temperature
Operating Temperature
Storage Temperature
Junction Temperature
TMAX_OP
TMAX_OP
TMAX_STG
TJMAX
Commercial
Industrial
-40
-55
85
150
125
Note 1: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2: This is a stress rating only and functional operation of the device at any other condition above those indi-
cated in the operation sections of this specification is not implied.
3: When powering this device from laboratory or system power supplies, it is important that the Absolute Max-
imum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on
their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line
may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit be used.
10.2 Recommended Operating Conditions
TABLE 10-2: RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Conditions
MIN
TYP
MAX
Units
VBAT
VBAT
2.9
1.6
5.5
2.0
V
V
V
V
V
VDD_CORE_REG
VDD_CORE_REG
Input Voltage (DP, DM)
VDD_CORE_REG
VDD_CORE_REG
VIUSB
Note 10-1
1.8
3.3
Note 10-2
3.0
3.6
-0.3
-0.3
5.5
Input Voltage (STROBE,
DATA)
VIHSIC
1.2
1.8
1.32
Input Voltage on I/O Pins
Voltage on REFCLK
Ambient Temperature
Ambient Temperature
VI
-0.3
-0.3
0
3.6
3.6
70
V
V
C
C
VREFCLK
TA
Commercial
Industrial
TA
-40
85
Note 10-1
Note 10-2
Applicable only when VDD_CORE_REG is supplied from external power supply.
Applicable only when VDD_CORE_REG is tied to VDD33_BYP.
2011-2020 Microchip Technology Inc.
DS00001584C-page 51
USB3503
TABLE 10-3: 25-BALL WLCSP PACKAGE THERMAL PARAMETERS
Parameter
Symbol
Value
Units
°C/W
°C/W
°C/W
Comments
37.3
Measured in still air
34.9
33.9
Airflow 1 m/s
Thermal Resistance Junction to Ambient
JA
Airflow 2.5 m/s
Thermal Resistance Junction to Bottom of Case
Thermal Resistance Junction to Top of Case
JT
JC
0.4
°C/W
°C/W
Measured in still air
-
25.7
TABLE 10-4: 32-PIN SQFN PACKAGE THERMAL PARAMETERS
Parameter
Symbol
Value
Units
°C/W
°C/W
°C/W
Comments
44
Measured in still air
39
35
Airflow 1 m/s
Thermal Resistance Junction to Ambient
JA
Airflow 2.5 m/s
Thermal Resistance Junction to Bottom of Case
Thermal Resistance Junction to Top of Case
JT
JC
0.6
6.3
°C/W
°C/W
Measured in still air
-
10.3 Operating Current
The following conditions are assumed unless otherwise specified:
VBAT = 3.0 to 5.5V; VDD_CORE = 1.6 to 2.0V; VSS = 0V;
TA = 0C to +70C (Commercial), -40C to +85C (Industrial)
TABLE 10-5: OPERATING CURRENT (DUAL SUPPLY)
Parameter
Symbol
IVBAT(HS)
Conditions
MIN
TYP
MAX
Units
mA
High Speed USB Operation
with Upstream HSIC
Active USB Transfer
RESET_N = 1
3 Downstream Ports
Active
55
29
65
33
68
38
ICORE(HS)
mA
High Speed USB Operation
with Upstream HSIC
IVBAT(HS)
ICORE(HS)
Active USB Transfer
RESET_N = 1
2 Downstream Ports
Active, 1 Port Disabled
33
26
43
28
45
35
mA
mA
High Speed USB Operation
with Upstream HSIC
IVBAT(HS)
ICORE(HS)
Active USB Transfer
RESET_N = 1
1 Downstream Port
Active, 2 Ports Disabled
19
22
23
24
25
30
mA
mA
High Speed USB Operation
with Upstream HSIC
IVBAT(HS)
ICORE(HS)
High Speed Idle
RESET_N = 1
3 Downstream Ports
Enabled, No USB Data
Transfer
20
24
21
25
23
29
mA
mA
High Speed USB Operation
with Upstream HSIC
IVBAT(HS)
ICORE(HS)
High Speed Idle
RESET_N = 1
1Downstream Port
Enabled, No USB Data
Transfer
12
19
13
20
14
23
mA
mA
Unconfigured
(High Speed)
IVBAT(UNCONF)
ICORE(UNCONF)
RESET_N = 1
7
8
10
22
mA
mA
17
18
DS00001584C-page 52
2011-2020 Microchip Technology Inc.
USB3503
TABLE 10-5: OPERATING CURRENT (DUAL SUPPLY) (CONTINUED)
Parameter
STANDBY Mode
Symbol
Conditions
MIN
TYP
MAX
Units
A
IVBAT(STDBY)
ICORE(STDBY)
IVBAT(STDBY)
ICORE(STDBY)
IVBAT(SPND)
ICORE(SPND)
IVBAT(SPND)
ICORE(SPND)
RESET_N = 0
Commercial Temp
0
0
0.4
0
2.5
0.5
3.9
0.9
110
765
125
A
A
A
A
A
A
STANDBY Mode
SUSPEND Mode
SUSPEND Mode
RESET_N = 0
Industrial Temp
0
0.6
0
0
USB Suspend
Commercial Temp
65
125
65
125
73
165
73
165
USB Suspend
Industrial Temp
1050 A
The following conditions are assumed unless otherwise specified:
VBAT = 3.0 to 5.5V; VSS = 0V; TA = 0C to +70C (Commercial), -40C to +85C (Industrial)
TABLE 10-6: OPERATING CURRENT (SINGLE SUPPLY)
Parameter
Symbol
IVBAT(HS)
Conditions
MIN
TYP
MAX
Units
High Speed USB Operation
with Upstream HSIC
Active USB Transfer
RESET_N = 1
3 Downstream Ports
Active
88
98
110
mA
mA
mA
mA
High Speed USB Operation
with Upstream HSIC
IVBAT(HS)
IVBAT(HS)
IVBAT(HS)
Active USB Transfer
RESET_N = 1
2 Downstream Ports
Active, 1 Port Disabled
69
45
47
72
48
50
80
55
53
High Speed USB Operation
with Upstream HSIC
Active USB Transfer
RESET_N = 1
1 Downstream Port
Active, 2 Ports Disabled
High Speed USB Operation
with Upstream HSIC
High Speed Idle
RESET_N = 1
3 Downstream Ports
Enabled, No USB Data
Transfer
High Speed USB Operation
with Upstream HSIC
IVBAT(HS)
High Speed Idle
RESET_N = 1
1Downstream Port
Enabled, No USB Data
Transfer
34
35
36
mA
Unconfigured
(High Speed)
IVBAT(UNCONF)
IVBAT(STDBY)
IVBAT(STDBY)
IVBAT(SPND)
IVBAT(SPND)
RESET_N = 1
28
0
29
0.6
0.6
250
250
30
2.6
3.1
925
mA
A
A
A
STANDBY Mode
STANDBY Mode
SUSPEND Mode
SUSPEND Mode
RESET_N = 0
Commercial Temp
RESET_N = 0
Industrial Temp
0
USB Suspend
Commercial Temp
215
215
USB Suspend
Industrial Temp
1330 A
2011-2020 Microchip Technology Inc.
DS00001584C-page 53
USB3503
10.4 DC Characteristics: Digital I/O Pins
Note:
TA = -40˚C to 85˚C
TABLE 10-7: DIGITAL I/O CHARACTERISTICS
Parameter
Symbol
VIL
Conditions
MIN
TYP
MAX
Units
Low-Level Input Voltage
Low-Level Input Voltage
High-Level Input Voltage
Note 10-1
Note 10-2
-0.3
-0.3
1.25
0.42
0.34
V
V
V
VIL
VIH
VDD33_BYP+
0.3V
Low-Level Input Voltage
VIL_RST
VIH_RST
-0.3
1.0
0.38
V
V
RESET
High-Level Input Voltage
RESET
VDD33_BYP+
0.3V
Low-Level Input Voltage OSC VIL_OSC
-0.3
0.8
0.55
V
V
High-Level Input Voltage
VIH_OSC
VIL_REF
VIH_REF
CIN
VDD33_BYP+
0.3V
OSC
Low-Level Input Voltage
REFCLK
-0.3
1.4
0.5
V
V
High-Level Input Voltage
REFCLK
VDD33_BYP+
0.3V
Clock Input Capacitance
2
pF
V
REFCLK
Low-Level Output Voltage
VOL
@ IOL=12mA
sink current
0.4
Pin Capacitance
Cpin
IO
2
20
24
pF
Output Current Capability
12
20
mA
Note 10-1
For I2C interface using pullups to less than 2.1V.
For I2C interface using pullups to greater than 2.1V.
Note 10-2
DS00001584C-page 54
2011-2020 Microchip Technology Inc.
USB3503
10.5 DC Characteristics: Analog I/O Pins
TABLE 10-8: DC CHARACTERISTICS: ANALOG I/O PINS (DP/DM)
Parameter
Symbol
Conditions
MIN
TYP
MAX
Units
LS/FS FUNCTIONALITY
Input levels
Differential Receiver Input
Sensitivity
VDIFS
VCMFS
VILSE
| V(DP) - V(DM) |
0.2
V
V
V
V
V
Differential Receiver
Common-Mode Voltage
0.8
2.5
Single-Ended Receiver Low
Level Input Voltage
0.8
Single-Ended Receiver High
Level Input Voltage
VIHSE
2.0
Single-Ended Receiver
Hysteresis
VHYSSE
0.050
0.150
Output Levels
Low Level Output Voltage
VFSOL
VFSOH
Pull-up resistor on DP;
0.3
3.6
V
V
RL = 1.5kΩ to VDD33_BYP
High Level Output Voltage
Pull-down resistor on DP,
DM;
RL = 15kΩ to GND
2.8
Termination
Driver Output Impedance for
HS
ZHSDRV
Steady state drive
40.5
45
49.5
20
Ω
Input Impedance
ZINP
RPD
RX, RPU, RPD disabled
Note 10-3
1.0
MΩ
kΩ
Pull-dn Resistor Impedance
HS FUNCTIONALITY
Input levels
14.25
16.9
HS Differential Input Sensitivity VDIHS
| V(DP) - V(DM) |
100
-50
mV
mV
HS Data Signaling Common
Mode Voltage Range
VCMHS
VHSSQ
VHSDSC
500
150
625
HS Squelch Detection
Threshold (Differential)
100
525
mV
mV
HS Disconnect Threshold
Output Levels
High Speed Low Level
Output Voltage (DP/DM
referenced to GND)
VHSOL
VHSOH
VOLHS
45Ω load
45Ω load
45Ω load
-10
360
-10
10
mV
mV
mV
High Speed High Level
Output Voltage (DP/DM
referenced to GND)
440
10
High Speed IDLE Level
Output Voltage (DP/DM
referenced to GND)
Leakage Current
OFF-State Leakage Current
Port Capacitance
ILZ
±10
10
A
Transceiver Input Capacitance CIN
Note 10-3
Pin to GND
5
pF
The resistor value follows the 27% Resistor ECN published by the USB-IF.
2011-2020 Microchip Technology Inc.
DS00001584C-page 55
USB3503
10.6 Dynamic Characteristics: Digital I/O Pins
TABLE 10-9: DYNAMIC CHARACTERISTICS: DIGITAL I/O PINS (RESET_N)
Parameter
Symbol
Conditions
RESET_N = ‘0’
MIN
TYP
MAX
Units
ms
Minimum Active Low Pulse on TRESET
RESET_N
1
10.7 Dynamic Characteristics: Analog I/O Pins
TABLE 10-10: DYNAMIC CHARACTERISTICS: ANALOG I/O PINS (DP/DM)
Parameter
Symbol
Conditions
MIN
TYP
MAX
Units
FS Output Driver Timing
FS Rise Time
TFR
CL = 50pF; 10 to 90% of
4
4
20
ns
|VOH - VOL
|
FS Fall Time
TFF
CL = 50pF; 10 to 90% of
|VOH - VOL
20
ns
V
|
Output Signal Crossover
Voltage
VCRS
TFRFM
Excluding the first transition 1.3
from IDLE state
2.0
Differential Rise/Fall Time
Matching
Excluding the first transition 90
from IDLE state
111.1
%
LS Output Driver Timing
LS Rise Time
TLR
CL = 50-600pF;
10 to 90% of
75
75
300
300
125
ns
ns
%
|VOH - VOL
|
LS Fall Time
TLF
CL = 50-600pF;
10 to 90% of
|VOH - VOL
|
Differential Rise/Fall Time
Matching
TLRFM
Excluding the first transition 80
from IDLE state
HS Output Driver Timing
Differential Rise Time
Differential Fall Time
THSR
THSF
500
500
ps
ps
Driver Waveform
Requirements
Eye pattern of Template 1
in USB 2.0 specification
High Speed Mode Timing
Receiver Waveform
Requirements
Eye pattern of Template 4
in USB 2.0 specification
Data Source Jitter and
Receiver Jitter Tolerance
Eye pattern of Template 4
in USB 2.0 specification
10.8 Regulator Output Voltages and Capacitor Requirement
TABLE 10-11: REGULATOR OUTPUT VOLTAGES AND CAPACITOR REQUIREMENT
Parameter
Symbol
VDD33
Conditions
MIN
TYP
MAX
Units
Regulator Output Voltage
Regulator Capacitor
Capacitor ESR
5.5V > VBAT > 2.9V
2.8
4.7
3.3
3.6
V
CBYP33
CESR33
VDD12
F
Ω
1
Regulator Output Voltage
Regulator Capacitor
Capacitor ESR
3.6V > VDD33 > 2.8V
1.1
1.0
1.2
1.3
V
CBYP12
CESR12
F
Ω
1
DS00001584C-page 56
2011-2020 Microchip Technology Inc.
USB3503
10.9 ESD and Latch-Up Performance
TABLE 10-12: ESD AND LATCH-UP PERFORMANCE
Parameter
Conditions
MIN
TYP
MAX
Units
Comments
ESD PERFORMANCE
Human Body Model
±5
kV
Device
System
EN/IEC 61000-4-2 Contact
Discharge
±15
kV
3rd party system test
System
EN/IEC 61000-4-2 Air-gap
Discharge
±15
kV
3rd party system test
LATCH-UP PERFORMANCE
All Pins
EIA/JESD 78, Class II
150
mA
10.10 ESD Performance
The USB3503 is protected from ESD strikes. By eliminating the requirement for external ESD protection devices, board
space is conserved, and the board manufacturer is enabled to reduce cost. The advanced ESD structures integrated
into the USB3503 protect the device whether or not it is powered up.
10.10.1 HUMAN BODY MODEL (HBM) PERFORMANCE
HBM testing verifies the ability to withstand the ESD strikes like those that occur during handling and manufacturing,
and is done without power applied to the IC. To pass the test, the device must have no change in operation or perfor-
mance due to the event. All pins on the USB3503 provide ±5 kV HBM protection, as shown in Table 10-12.
10.10.2 EN 61000-4-2 PERFORMANCE
The EN 61000-4-2 ESD specification is an international standard that addresses system-level immunity to ESD strikes
while the end equipment is operational. In contrast, the HBM ESD tests are performed at the device level with the device
powered down.
Microchip contracts with Independent laboratories to test the USB3503 to EN 61000-4-2 in a working system. Reports
are available upon request. Please contact your representative, and request information on 3rd party ESD test results.
The reports show that systems designed with the USB3503 can safely provide the ESD performance without additional
board level protection.
In addition to defining the ESD tests, EN 61000-4-2 also categorizes the impact to equipment operation when the strike
occurs (ESD Result Classification). Both air discharge and contact discharge test techniques for applying stress condi-
tions are defined by the EN 61000-4-2 ESD document.
10.10.3 AIR DISCHARGE
To perform this test, a charged electrode is moved close to the system being tested until a spark is generated. This test
is difficult to reproduce because the discharge is influenced by such factors as humidity, the speed of approach of the
electrode, and construction of the test equipment.
10.10.4 CONTACT DISCHARGE
The uncharged electrode first contacts the pin to prepare this test, and then the probe tip is energized. This yields more
repeatable results, and is the preferred test method. The independent test laboratories contracted by Microchip provide
test results for both types of discharge methods.
2011-2020 Microchip Technology Inc.
DS00001584C-page 57
USB3503
10.11 AC Specifications
10.11.1 REFCLK
External Clock:50% duty cycle ± 10%, ± 350ppm, Jitter < 100ps rms.
10.11.2 SERIAL INTERFACE
The Hub conforms to AC specifications as set forth in the I2C Specification for Slave-Only devices.
10.11.3 USB 2.0
The Hub conforms to all voltage, power, and timing characteristics and specifications as set forth in the USB 2.0 Spec-
ification. Please refer to the USB 2.0 Specification which is available from the www.usb.org web site.
10.11.4 USB 2.0 HSIC
The upstream port of the HSIC Hub conforms to all voltage, power, and timing characteristics and specifications as set
forth in the High-Speed Inter-Chip USB Electrical Specification Version 1.0. Please refer to the USB 2.0 HSIC Specifi-
cation which is available from the www.usb.org web site.
DS00001584C-page 58
2011-2020 Microchip Technology Inc.
USB3503
11.0 APPLICATION REFERENCE
11.1 Application Diagram
The USB3503 requires several external components to function and insure compliance with the USB 2.0 specification.
TABLE 11-1: COMPONENT VALUES IN APPLICATION DIAGRAMS
Reference
Value
Description
Notes
Designator
CVDD12BYP
CVDD33BYP
COUT
1.0 F
4.7 F
0.1 F
12.0k
Capacitor to ground for regulator stability. Place as close to the
USB3503 as possible
Capacitor to ground for regulator stability. Place as close to the
USB3503 as possible
Bypass capacitor to ground.
Place as close to the
USB3503 as possible
Series resistor to establish reference
voltage used by analog circuits.
Place as close to the
USB3503 as possible
RBIAS
10k or 1k
Pull-up for I2C bus. 10k for 100kHz or
RPU1
RPU2
400kHz operation. 1k for 1MHz operation.
10k (or greater)
Pull-up for open-drain outputs
TABLE 11-2: CAPACITANCE VALUES AT VBUS OF USB CONNECTOR
Port
MIN Value
MAX Value
Downstream
120F
2011-2020 Microchip Technology Inc.
DS00001584C-page 59
USB3503
FIGURE 11-1:
INTERNAL CHIP-TO-CHIP INTERFACE
Port 1 Disabled
USB3503A-1
VDD33_BYP
LTE
USBDN1_DP
Baseband
Processor
DATA
USBDN1_DM
USBDN2_DP
USBDN2_DM
STROBE
REFCLK
USBDN3_DP
USBDN3_DM
3G
Baseband
Processor
RESET_N
HUB_CONNECT
OCS_N
PORT_PWR
OCS_N tied to VDD33_BYP
when unused.
VDD_INTN
RBIAS
RBIAS
RPU2
Applications
Processor
INT_N
VDD_I2C
VBAT
SCL
SDA
VBAT
COUT
+1.8V
RPU1
RPU1
VDD_CORE_REG
VDD33_BYP
COUT
REF_SEL1
REF_SEL0
Connect pins to
either
VDD33_BYP or
GND.
VDD33_BYP
VDD12_BYP
CVDD33BYP
CVDD12BYP
VSS
Note 1: While RESET_N is driven low, all other inputs from Applications Processor should also be driven low in
order to minimize current draw.
2: To disable a downstream port, tie DP and DM to VDD33_BYP pin of the USB3503.
DS00001584C-page 60
2011-2020 Microchip Technology Inc.
USB3503
FIGURE 11-2:
INTERNAL CHIP-TO-CHIP INTERFACE WITH EMBEDDED HOST PORT
LTE
Baseband
Processor
USB3503A-1
3G
Baseband
Processor
USBDN1_DP
DATA
USBDN1_DM
USBDN2_DP
USBDN2_DM
STROBE
Embedded
Host Port
REFCLK
USBDN3_DP
USBDN3_DM
DP
DM
VBUS
GND
RESET_N
HUB_CONNECT
OCS_N
PORT_PWR
FAULT
VDD_INTN
+5V
EN
VBUS
RBIAS
RBIAS
+5V
RPU2
Applications
Processor
INT_N
VDD_I2C
VBAT
SCL
SDA
VBAT
COUT
+1.8V
RPU1
RPU1
VDD_CORE_REG
VDD33_BYP
COUT
REF_SEL1
REF_SEL0
Connect pins to
either
VDD33_BYP or
GND.
VDD33_BYP
VDD12_BYP
CVDD33BYP
CVDD12BYP
VSS
2011-2020 Microchip Technology Inc.
DS00001584C-page 61
USB3503
12.0 PACKAGE OUTLINES, TAPE & REEL DRAWINGS, PACKAGE MARKING
12.1 25-Ball WLCSP
FIGURE 12-1:
25-BALL WLCSP, 1.97X1.97MM BODY, 0.4MM PITCH PACKAGE DRAWING
DS00001584C-page 62
2011-2020 Microchip Technology Inc.
USB3503
FIGURE 12-2:
25-BALL WLCSP TAPE AND REEL
2011-2020 Microchip Technology Inc.
DS00001584C-page 63
USB3503
FIGURE 12-3:
25-BALL WLCSP REEL DIMENSIONS
DS00001584C-page 64
2011-2020 Microchip Technology Inc.
USB3503
FIGURE 12-4:
25-BALL WLCSP TAPE SECTIONS
FIGURE 12-5:
25-BALL WLCSP REFLOW PROFILE AND CRITICAL PARAMETERS FOR ROHS
COMPLIANT (SNAGCU) SOLDER
2011-2020 Microchip Technology Inc.
DS00001584C-page 65
USB3503
FIGURE 12-6:
25-BALL WLCSP PACKAGE MARKING
Note:
The Device # Code for the USB3503 is “05”.
DS00001584C-page 66
2011-2020 Microchip Technology Inc.
USB3503
12.2 32-Pin SQFN
FIGURE 12-7:
32-PIN SQFN (5.0MM X 5.0MM) PACKAGE
2011-2020 Microchip Technology Inc.
DS00001584C-page 67
USB3503
FIGURE 12-8:
RECOMMENDED PCB LAND PATTERN
FIGURE 12-9:
TAPING DIMENSIONS AND PART ORIENTATION
Ø1.5+0.1/-0.0
4.0
CARRIER TAPE
2.0 0.05
0.ꢀ0 0.05
A
1.75
5.5 0.05
12.0 0.ꢀ
5.25x5.25
+0.1/-0.0
Ø1.5 MIN
9.2 0.1
A
1.10
8.0
COVER TAPE
SECTION: A-A
FEED DIRECTION
QFN-5x5mm Body: TAPE DIMENSIONS AND PART ORIENTATION
UNIT: MM
DS00001584C-page 68
2011-2020 Microchip Technology Inc.
USB3503
FIGURE 12-10:
REEL DIMENSIONS
FIGURE 12-11:
TAPE LENGTH AND PART QUANTITY
Note:
Standard reel size is 4,000 pieces per reel.
2011-2020 Microchip Technology Inc.
DS00001584C-page 69
USB3503
APPENDIX A: DATA SHEET REVISION HISTORY
TABLE A-1:
REVISION HISTORY
REVISION LEVEL
DS00001584C (02-17-20)
SECTION/FIGURE/ENTRY
CORRECTION
Table 10-1, "Absolute
Maximum Ratings"
Added junction temperature information.
Table 10-3, "25-BALL
WLCSP PACKAGE
Added package thermal parameters tables.
THERMAL PARAMETERS",
Table 10-4, "32-PIN SQFN
PACKAGE THERMAL
PARAMETERS"
DS00001584B (03-18-15)
Section 10.6, "Dynamic
Characteristics: Digital I/O
Pins," on page 56
Changed RESET_N minimum active low pulse from
100s to 1ms.
FIGURE 12-6: 25-Ball
WLCSP Package Marking
on page 66
Added note under figure: “Note: The Device # Code
for the USB3503 is “05”.”
DS00001584A replaces the previous SMSC version 1.2.
Rev. 1.2 (08-22-13)
Rev. 1.1 (02-07-13)
Rev. 1.1 (12-19-11)
All
Added 32-SQFN pinout and package information
Document co-branded: Microchip logo added, company disclaimer modified.
Table 4-2, "Timing
Parameters for Hub Stages"
Removed the second sentence in the Standby Sum-
mary:
“All port interfaces are high impedance”
Removed second bullet:
Section 4.2.1, "External
Hardware RESET_N"
“The USB data pins will be in a high-impedance
state.”
Table 3-4, "USB3503
Secondary Reference Clock
Frequencies"
Changed Frequency values in TABLE 3-4: as fol-
lows:
01 = 27.0MHz
10 = 25.0MHz
Rev. 1.0 (10-24-11)
Document release
DS00001584C-page 70
2011-2020 Microchip Technology Inc.
USB3503
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-
tains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-
nars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-
cation” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-
ment.
Technical support is available through the web site at: http://www.microchip.com/support
2011-2020 Microchip Technology Inc.
DS00001584C-page 71
USB3503
USB3503 25-WLCSP PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X](1)
X
/XX
XXX
PART NO.
Device
Examples:
Temperature Package Pattern
Range
Tape and Reel
Option
a)
USB3503A-1-GL-TR
0C to 70C temperature range,
25-Ball WLCSP, 3000 piece reel
b)
USB3503Ai-1-GL-TR:
-40C to 85C temperature range,
25-Ball WLCSP, 3000 piece reel
Device:
USB3503
Tape and Reel
Option:
Blank
T
=
=
Standard packaging (tube or tray)
Tape and Reel(1)
Temperature
Range:
i
=
=
-40C to +85C (Industrial)
0C to +70C (Commercial)
Blank
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This identi-
fier is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
Package:
GL
=
WLCSP
USB3503 32-SQFN PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X](1)
X
/XX
XXX
PART NO.
Device
Examples:
Temperature Package Pattern
Range
Tape and Reel
Option
a)
USB3503/ML
0C t 70C temperature range,
32-Pin SQFN, tray
b)
USB3503-i/ML
-40C to 85C temperature range,
32-Pin SQFN, tray
Device:
USB3503
c)
d)
USB3503T/ML
- 0C to 70C temperature range,
32-Pin SQFN, 5000 piece reel
Tape and Reel
Option:
Blank
T
=
=
Standard packaging (tube or tray)
Tape and Reel(1)
USB3503T-i/ML
-40C to 85C temperature range,
32-Pin SQFN, 5000 piece reel
Temperature
Range:
i
=
=
-40C to +85C (Industrial)
0C to +70C (Commercial)
Blank
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This identi-
fier is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
Package:
ML
=
SQFN
DS00001584C-page 72
2011-2020 Microchip Technology Inc.
USB3503
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro-
chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch,
MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo,
PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero,
motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux,
TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the
U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain,
Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher,
SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in
other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2011-2020, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 9781522456292
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2011-2020 Microchip Technology Inc.
DS00001584C-page 73
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Australia - Sydney
Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Beijing
Tel: 86-10-8569-7000
India - New Delhi
Tel: 91-11-4160-8631
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8665-5511
India - Pune
Tel: 91-20-4121-0141
Finland - Espoo
Tel: 358-9-4520-820
China - Chongqing
Tel: 86-23-8980-9588
Japan - Osaka
Tel: 81-6-6152-7160
Web Address:
www.microchip.com
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Dongguan
Tel: 86-769-8702-9880
Japan - Tokyo
Tel: 81-3-6880- 3770
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Guangzhou
Tel: 86-20-8755-8029
Korea - Daegu
Tel: 82-53-744-4301
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Tel: 49-8931-9700
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Tel: 86-571-8792-8115
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Tel: 512-257-3370
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Tel: 49-721-625370
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Philippines - Manila
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Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Tel: 86-532-8502-7355
Tel: 63-2-634-9065
Chicago
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Tel: 630-285-0071
Fax: 630-285-0075
China - Shanghai
Tel: 86-21-3326-8000
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Germany - Rosenheim
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China - Shenyang
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Dallas
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Tel: 972-818-7423
Fax: 972-818-2924
Israel - Ra’anana
Tel: 972-9-744-7705
China - Shenzhen
Tel: 86-755-8864-2200
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Suzhou
Tel: 86-186-6233-1526
Taiwan - Taipei
Tel: 886-2-2508-8600
Detroit
Novi, MI
Tel: 248-848-4000
China - Wuhan
Tel: 86-27-5980-5300
Thailand - Bangkok
Tel: 66-2-694-1351
Italy - Padova
Tel: 39-049-7625286
Houston, TX
Tel: 281-894-5983
China - Xian
Tel: 86-29-8833-7252
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
China - Xiamen
Tel: 86-592-2388138
Norway - Trondheim
Tel: 47-7288-4388
China - Zhuhai
Tel: 86-756-3210040
Poland - Warsaw
Tel: 48-22-3325737
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Raleigh, NC
Tel: 919-844-7510
Sweden - Gothenberg
Tel: 46-31-704-60-40
New York, NY
Tel: 631-435-6000
Sweden - Stockholm
Tel: 46-8-5090-4654
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
05/14/19
2011-2020 Microchip Technology Inc.
DS00001584C-page 74
相关型号：
USB3503AI-1-GL-TR
UNIVERSAL SERIAL BUS CONTROLLER, PBGA25, 1.97 X 1.97 MM, 0.40 MM PITCH, ROHS COMPLIANT, WLCSP-25
MICROCHIP
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