VSC8512XJG-02 [MICROCHIP]
Ethernet Transceiver;
| 型号： | VSC8512XJG-02 |
| 厂家： | 
MICROCHIP |
| 描述： | Ethernet Transceiver 以太网：16GBASE-T 电信 电信集成电路 |
| 文件： | 总141页 (文件大小：1080K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VSC8512-02 Datasheet
12-Port 10/100/1000BASE-T PHY with SGMII and QSGMII
MAC
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of
its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the
application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have
been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any
performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all
performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not
rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to
independently determine suitability of any products and to test and verify the same. The information provided by Microsemi
hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely
with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP
rights, whether with regard to such information itself or anything described by such information. Information provided in this
document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
Microsemi Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Within the USA: +1 (800) 713-4113
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Fax: +1 (949) 215-4996
Email: sales.support@microsemi.com
www.microsemi.com
About Microsemi
©2018 Microsemi, a wholly owned
subsidiary of Microchip Technology Inc. All
rights reserved. Microsemi and the
Microsemi logo are registered trademarks of
Microsemi Corporation. All other trademarks
and service marks are the property of their
respective owners.
Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of
semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets.
Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and
ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's
standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication
solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and
midspans; as well as custom design capabilities and services. Learn more at www.microsemi.com.
VMDS-10396. 4.3 11/18
Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
1.5
Revision 4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Revision 4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Revision 4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1
Register and Bit Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2
SerDes MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2.1
4.2.2
4.2.3
SerDes MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SGMII MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
QSGMII MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.3
SerDes Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3.1
4.3.2
4.3.3
4.3.4
QSGMII to 1000BASE-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
QSGMII to 100BASE-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
QSGMII to SGMII Protocol Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Unidirectional Transport for Fiber Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.4
4.5
PHY Addressing and Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.4.1
4.4.2
PHY Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SerDes Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Cat5 Twisted Pair Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
Voltage-Mode Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Cat5 Autonegotiation and Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1000BASE-T Forced Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Automatic Crossover and Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Manual HP Auto-MDIX Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Link Speed Downshift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.6
4.7
Automatic Media-Sense Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7.1
4.7.2
4.7.3
Configuring the REFCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Single-Ended REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Differential REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8
Ethernet Inline Powered Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
IEEE 802.3af PoE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.9
4.10
ActiPHY Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.10.1 Low Power State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.10.2 Link Partner Wake-Up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.10.3 Normal Operating State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11
Media Recovered Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11.1 Clock Selection Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11.2 Clock Output Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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4.12
4.13
Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.12.1 SMI Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.12.2 SMI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.13.1 LED Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.13.2 Extended LED Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.13.3 LED Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.13.4 Basic Serial LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.13.5 Enhanced Serial LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.13.6 LED Port Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.14
4.15
Fast Link Failure Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Integrated I2C Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.15.1 Read/Write Access Using the I2C MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.16
4.17
GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Testing Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.17.1 Ethernet Packet Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.17.2 CRC Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.17.3 Far-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.17.4 Near-End Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.17.5 Connector Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.17.6 SerDes Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.17.7 VeriPHY Cable Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.17.8 JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.17.9 JTAG Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.17.10 Boundary Scan Register Cell Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.17.11 JTAG Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.18
4.19
100FX Halt Code Transmission and Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1
IEEE Standard and Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Mode Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Autonegotiation Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Link Partner Autonegotiation Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Autonegotiation Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Transmit Autonegotiation Next Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Autonegotiation Link Partner Next Page Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1000BASE-T Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.1.10 1000BASE-T Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1.11 MMD Access Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.1.12 MMD Address or Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.1.13 1000BASE-T Status Extension 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.1.14 100BASE-TX Status Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.1.15 1000BASE-T Status Extension 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.1.16 Bypass Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.1.17 Error Counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.1.18 Error Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.1.19 Error Counter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.1.20 Extended Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.2
Extended PHY Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Extended PHY Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Device Auxiliary Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
LED Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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5.2.6
5.2.7
LED Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Extended Page Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3
Extended Page 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
SerDes Media Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Cu Media CRC Good Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Extended Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
ActiPHY Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PoE and Miscellaneous Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
VeriPHY Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
VeriPHY Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
VeriPHY Control 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Ethernet Packet Generator Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3.10 Ethernet Packet Generator Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.4
5.5
Extended Page 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.4.1
5.4.2
Cu PMD Transmit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
EEE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Extended Page 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.5.7
5.5.8
5.5.9
MAC SerDes PCS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
MAC SerDes PCS Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
MAC SerDes Clause 37 Advertised Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
MAC SerDes Clause 37 Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
MAC SerDes Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Media SerDes Transmit Good Packet Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Media SerDes Transmit CRC Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Media SerDes PCS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Media SerDes PCS Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.5.10 Media SerDes Clause 37 Advertised Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.5.11 Media SerDes Clause 37 Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.5.12 Media SerDes Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.5.13 Fiber Media CRC Good Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.5.14 Fiber Media CRC Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.6
General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
5.6.8
5.6.9
SIGDET/LED vs. GPIO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
COMA_MODE and CLK_SQUELCH_IN Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
GPIO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
GPIO Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
GPIO Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Global Command and SerDes Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
MAC Mode and Fast Link Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I2C MUX Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I2C MUX Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.6.10 I2C MUX Data Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.6.11 Recovered Clock 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.6.12 Recovered Clock 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.6.13 Enhanced LED Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.6.14 Global Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.7
Clause 45 Registers to Support Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.7.1
5.7.2
5.7.3
5.7.4
5.7.5
PCS Status 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
EEE Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
EEE Wake Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
EEE Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
EEE Link Partner Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.1
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.1.1
6.1.2
VDD_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Internal Pull-Up or Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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6.1.3
6.1.4
6.1.5
6.1.6
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Enhanced SerDes Interface (QSGMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
SerDes Interface (SGMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.2
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Recovered Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
SerDes Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
SerDes Driver Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
SerDes Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SerDes Receiver Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Enhanced SerDes Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Enhanced SerDes Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Enhanced Serial LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.2.10 Enhanced SerDes Driver Jitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.2.11 Enhanced SerDes Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.2.12 Enhanced SerDes Receiver Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.2.13 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.2.14 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.2.15 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.2.16 Serial LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.2.17 Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3
6.4
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.1
Pin Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.2
Pins by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
LED and Multi/General Purpose Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
MAC SerDes/QSGMII Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
No Connect and Reserved Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Serial Management Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Twisted Pair Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.3
7.4
Pins by Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Pins by Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
8 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
8.1
8.2
8.3
Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
9 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
10BASE-T mode unable to re-establish link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Link status for 100BASE-FX operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Software script for link performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
10BASE-T signal amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Clause 45 register 7.60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Clause 45 register 3.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Clause 45 register 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Clause 45 register address post-increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
QSGMII Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
SGMII Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SerDes MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
QSGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Cat5 Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Low Power Idle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Automatic Media-Sense Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 V CMOS Single-Ended REFCLK Input Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 V CMOS Single-Ended REFCLK Input Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC-Coupling Required for REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Inline Powered Ethernet Switch Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ActiPHY State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SMI Read Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SMI Write Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MDINT Configured as an Open-Drain (Active-Low) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MDINT Configured as an Open-Source (Active-High) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
I2C MUX with SFP Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I2C MUX Read and Write Register Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Far-End Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Near-End Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Connector Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Data Loops of the SerDes Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Test Access Port and Boundary Scan Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Register Space Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SGMII DC Transmit Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SGMII DC Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SGMII DC Driver Output Impedance Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SGMII DC Input Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
QSGMII Transient Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Enhanced Serial LED Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
JTAG Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Test Circuit for TDO Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
SMI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Serial LED Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Pin Diagram, Left . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Pin Diagram, Right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
vii
Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PHY Address Range Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SerDes Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supported MDI Pair Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AMS Media Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
REFCLK Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LED Mode and Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Extended LED Mode and Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LED Serial Stream Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
IDCODE JTAG Device Identification Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
USERCODE JTAG Device Identification Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
JTAG Interface Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
IEEE 802.3 Standard Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Mode Control, Address 0 (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Mode Status, Address 1 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Identifier 1, Address 2 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Identifier 2, Address 3 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Device Autonegotiation Advertisement, Address 4 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Autonegotiation Link Partner Ability, Address 5 (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Autonegotiation Expansion, Address 6 (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Autonegotiation Next Page Transmit, Address 7 (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Autonegotiation LP Next Page Receive, Address 8 (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1000BASE-T Control, Address 9 (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1000BASE-T Status, Address 10 (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MMD EEE Access, Address 13 (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MMD Address or Data Register, Address 14 (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1000BASE-T Status Extension 1, Address 15 (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
100BASE-TX Status Extension, Address 16 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1000BASE-T Status Extension 2, Address 17 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Bypass Control, Address 18 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Extended Control and Status, Address 19 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Extended Control and Status, Address 20 (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Extended Control and Status, Address 21 (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Extended Control and Status, Address 22 (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Extended PHY Control 1, Address 23 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Extended PHY Control 2, Address 24 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Interrupt Mask, Address 25 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Interrupt Status, Address 26 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Auxiliary Control and Status, Address 28 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
LED Mode Select, Address 29 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
LED Behavior, Address 30 (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Extended/GPIO Page Access, Address 31 (0x1F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Extended Registers Page 1 Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SerDes Media Control, Address 16E1 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Cu Media CRC Good Counter, Address 18E1 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Extended Mode Control, Address 19E1 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Extended PHY Control 3, Address 20E1 (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Extended PHY Control 4, Address 23E1 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
VeriPHY Control 1, Address 24E1 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
VeriPHY Control 2, Address 25E1 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
VeriPHY Control 3, Address 26E1 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
VeriPHY Control 3 Fault Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Table 49
Table 50
Table 51
Table 52
Table 53
Table 54
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
viii
Table 55
Table 56
Table 57
Table 58
Table 59
Table 60
Table 61
Table 62
Table 63
Table 64
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 74
Table 75
Table 76
Table 77
Table 78
Table 79
Table 80
Table 81
Table 82
Table 83
Table 84
Table 85
Table 86
Table 87
Table 88
Table 89
Table 90
Table 91
Table 92
Table 93
Table 94
Table 95
Table 96
Table 97
Table 98
Table 99
Table 100
Table 101
Table 102
Table 103
Table 104
Table 105
Table 106
Table 107
Table 108
Table 109
Table 110
Table 111
Table 112
Table 113
EPG Control 1, Address 29E1 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
EPG Control 2, Address 30E1 (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Extended Registers Page 2 Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Cu PMD Transmit Control, Address 16E2 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
EEE Control, Address 17E2 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Extended Registers Page 3 Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
MAC SerDes PCS Control, Address 16E3 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
MAC SerDes PCS Status, Address 17E3 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
MAC SerDes Cl37 Advertised Ability, Address 18E3 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
MAC SerDes Cl37 LP Ability, Address 19E3 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
MAC SerDes Status, Address 20E3 (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Media SerDes Tx Good Packet Counter, Address 21E3 (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Media SerDes Tx CRC Error Counter, Address 22E3 (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Media SerDes PCS Control, Address 23E3 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Media SerDes PCS Status, Address 24E3 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Media SerDes Cl37 Advertised Ability, Address 25E3 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
MAC SerDes Cl37 LP Ability, Address 26E3 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Media SerDes Status, Address 27E3 (0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Fiber Media CRC Good Counter, Address 28E3 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Fiber Media CRC Error Counter, Address 29E3 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
General Purpose Registers Page Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SIGDET/LED vs. GPIO Control, Address 13G (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
COMA_MODE and CLK_SQUELCH_IN Control, Address 14G (0x0E) . . . . . . . . . . . . . . . . . . . . . 72
GPIO Input, Address 15G (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
GPIO Output, Address 16G (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
GPIO Input/Output Configuration, Address 17G (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Global Command and SerDes Configuration, Address 18G (0x12) . . . . . . . . . . . . . . . . . . . . . . . . 73
MAC Mode and Fast Link Configuration, Address 19G (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I2C MUX Control 1, Address 20G (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I2C MUX Interface Status and Control, Address 21G (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
I2C MUX Data Read/Write, Address 22G (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Recovered Clock 0 Control, Address 23G (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Recovered Clock 1 Control, Address 24G (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Enhanced LED Control, Address 25G (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Global Interrupt Status, Address 29G (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Clause 45 Registers Page Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
PCS Status 1, Address 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
EEE Capability, Address 3.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
EEE Wake Error Counter, Address 3.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
EEE Advertisement, Address 7.60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
EEE Advertisement, Address 7.61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
VDD_IO DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Internal Pull-Up or Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Reference Clock DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Enhanced SerDes Driver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Enhanced SerDes Receiver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SerDes Driver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SerDes Receiver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
QSGMII to 1000BASE-T Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
QSGMII to 1000BASE-X Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
QSGMII to 100BASE-FX Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
SGMII to 1000BASE-T Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Reference Clock AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Recovered Clock AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
SerDes Output AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
SerDes Driver Jitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
SerDes Input AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SerDes Receiver Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Enhanced SerDes Outputs AC Specifications, SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Table 114
Table 115
Table 116
Table 117
Table 118
Table 119
Table 120
Table 121
Table 122
Table 123
Table 124
Table 125
Table 126
Table 127
Table 128
Table 129
Table 130
Table 131
Table 132
Table 133
Table 134
Table 135
Table 136
Enhanced SerDes Outputs AC Specifications, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Enhanced Serial LEDs AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Enhanced SerDes Driver Jitter Characteristics, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Enhanced SerDes Input AC Specifications, SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Enhanced SerDes Inputs AC Specifications, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Enhanced SerDes Receiver Jitter Tolerance, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
JTAG Interface AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SMI Interface AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
NRESET Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Serial LEDs AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Pin Type Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
LED, Multipurpose, and GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
MAC SerDes Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
No Connect and Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Serial Management Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Twisted Pair Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Thermal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
x
Revision History
1
Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
1.1
1.2
Revision 4.3
Revision 4.3 of this datasheet was published in September 2014. In revision 4.3 of the document, the
package drawing was updated to reflect two top views, which represent one of two packages customers
can expect to receive. The maximum package height was changed to 2.44 mm. For more information,
see Figure 40, page 127.
Revision 4.2
Revision 4.2 of this datasheet was published in May 2014. The following is a summary of the changes
made to the datasheet:
•
•
Information about the device SerDes MAC and the device media interface was updated. Neither the
integrated SerDes media access controller (MAC) or the enhanced SerDes media interface of the
device include internal AC-decoupling capacitors; external capacitors must be used.
Information about AC-coupling, which is required when using a differential reference clock
(REFCLK) input, was added.
•
•
Information about the typical input impedance for a differential REFCLK signal (RI) was added.
The order of the information in the Pins by Function section was changed to match the alphabetical
sort in the Pins spreadsheet attached to this document.
•
•
“LED and Multipurpose Pins,” in the Pins by Function section, was changed to “LED and
Multi/General Purpose Input and Output Pins” to more accurately describe the functionality of the
pins.
The names of pins V3 and W3 were changed. The name of V3 was changed to
PHY0_LED0/BASIC_SLED_DATA to accurately reflect its function as a source of basic serial LED
data. The name of W3 was changed to PHY8_LED1/GPIO_13 to accurately reflect that it does not
provide basic serial LED data.
•
•
The description of the following pins was changed from “Reserved” to “No Connect”: AA23, AA24,
AA25, AA26, AB23, AB24, AB25, AB26, AC23, AC24, AC25, AC26, AD24, AD25, AD26, AE25, C5,
R23, R24, R25, R26, T23, T24, T25, T26, U23, U24, U25, U26, V23, V24, V25, V26, W23, W24,
W25, W26, Y23, Y24, Y25, Y26. This change does not effect the functionality of these pins or the
device.
Information about pin C18 was corrected. C18 must not be left floating/unconnected. It should be
connected to VDD_IO for correct functioning of fiber media ports.
1.3
1.4
Revision 4.1
Revision 4.1 of this datasheet was published in January 2013. In revision 4.1 of the document, the
VSC8512-03 part number was added to reflect the availability of a device with an extended operating
temperature range of –40 °C ambient to 125 °C junction.
Revision 4.0
Revision 4.0 of this datasheet was published in October 2012. In revision 4.0 of the document, errata
items, which were previously published in the VSC8512-02 Errata revision 1.0 as open issues, are now
reconciled in the datasheet. Now that the information is available in the datasheet, the previously
published errata document no longer applies, and it has been removed from the Microsemi Web site.
1.5
Revision 2.0
•
Revision 2.0 of this datasheet was published in September 2012. This was the first publication of the
document.
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
1
Introduction
2
Introduction
This document consists of descriptions and specifications for both functional and physical aspects of the
VSC8512-02 12-port 10/100/1000BASE-T PHY device with four dual media ports for the Ethernet market
segment.
In addition to datasheets, the Microsemi Web site offers an extensive library of documentation, support
files, and application materials specific to each device. The address of the Microsemi Web site is
www.microsemi.com.
2.1
Register and Bit Conventions
This document refers to registers by their address and bit number in decimal notation. A range of bits is
indicated with a colon. For example, a reference to address 26, bits 15 through 14 is shown as 26.15:14.
A register with an E and a number attached (example 27E1) means it is a register contained within
extended register page number 1. A register with a G attached (example 13G) means it is a GPIO page
register.
Bit numbering follows the IEEE standard with bit 15 being the most significant bit and bit 0 being the least
significant bit.
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Overview
3
Overview
The VSC8512-02 is a low-power 12-port Gigabit Ethernet transceiver with four SerDes interfaces for
quad-port dual media capability. It also includes an integrated quad port I2C multiplexer (MUX) to control
SFPs or PoE modules. It has a low electromagnetic interference (EMI) line driver and integrated line side
termination resistors that conserve both power and printed circuit board (PCB) space.
Microsemi’s mixed signal and digital signal processing (DSP) architecture is a key operational feature of
the VSC8512-02, assuring robust performance even under less-than-favorable environmental
conditions. It supports both half-duplex and full duplex 10BASE-T, 100BASE-TX, and 1000BASE-T
communication speeds over Category 5 (Cat5) unshielded twisted pair (UTP) cable at distances greater
than 100 m, displaying excellent tolerance to NEXT, FEXT, echo, and other types of ambient
environmental and system electronic noise. This device also supports four dual media ports and can
support up to four 100BASE-FX, 1000BASE-X, and/or triple-speed copper SFPs on ports 8 through 11 of
the VSC8512-02.
The following illustrations show a high-level, general view of typical VSC8512-02 applications.
Figure 1 • QSGMII Application Diagram
QSGMII
1.0 V
2.5 V
QSGMII Ethernet MAC
QSGMII Ethernet MAC
12× RJ-45
and Magnetics
VSC8512
8 ports copper media
4 ports dual media
(copper or fiber)
SerDes
QSGMII MAC interface
4 SFPs
QSGMII Ethernet MAC
SCL/SDA
Figure 2 • SGMII Application Diagram
1.0 V
2.5 V
SGMII
VSC8512
12 ports copper media
SGMII MAC interface
12× SGMII Ethernet
MACs
12× RJ-45
and Magnetics
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
3
Overview
3.1
Key Features
This section lists the main features and benefits of the VSC8512-02 device.
Low Power
•
Low power consumption of approximately 425 mW per port in 1000BASE-T mode, 200 mW per port
in 100BASE-TX mode, 225 mW per port in 10BASE-T mode, and less than 115 mW per port in
100BASE-FX and 1000BASE-X modes
•
•
•
ActiPHY™ link down power savings
PerfectReach™ smart cable reach algorithm
IEEE 802.3az Energy Efficient Ethernet idle power savings
Wide Range of Support
•
Compliant with IEEE 802.3 (10BASE-T, 100BASE-TX, 1000BASE-T, 100BASE-FX, and
1000BASE-X) specifications
•
•
•
Support for IEEE 802.3ah unidirectional transport for 100BASE-FX and 1000BASE-X fiber media
Support for >16 kB jumbo frames in all speeds with programmable synchronization FIFOs
Supports Cisco SGMII v1.9, Cisco QSGMII v1.3 and 1000BASE-X MACs, IEEE 1149.1 JTAG
boundary scan, and IEEE 1149.6 AC-JTAG
•
•
Support for applications that need to meet 2 kV CDE, IEC 61000-4-2 at 8 kV
Available in a low-cost, 672-pin BGA package with a 27 mm × 27 mm body size for low-power,
fanless applications
Flexibility
•
VeriPHY® cable diagnostics suite provides extensive network cable information such as cable
length, termination status, and open/short fault location
•
•
Patented, low EMI line driver with integrated line side termination resistors
Two programmable direct-drive LEDs per port with adjustable brightness levels using register
controls; bi-color LED support using both LED pins
•
•
Serial LED interface option
Extensive test features including near end, far end, copper media connector, SerDes MAC/media
loopback, and Ethernet packet generator with CRC error counter to decrease time-to-market
3.2
Block Diagram
The following illustration shows the primary functional blocks of the VSC8512-02 device.
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
4
Overview
Figure 3 • Block Diagram
P[11:0]_D0P
P[11:0]_D0N
P[11:0]_D1P
P[11:0]_D1N
P[11:0]_D2P
P[11:0]_D2N
P[11:0]_D3P
P[11:0]_D3N
10/100/
1000BASE-T
PCS
10/100/
1000BASE-T
PMA
MDI
Twisted Pair
Interface
RCVRD_CLK0
RCVRD_CLK1
FAST_LINK_STATUS
CLK_SQUELCH_IN
Sync
Ethernet
SERDES[7:0]_TXP
SERDES[7:0]_TXN
(1)
1000BASE-X
PCS
1000BASE-X
PMA
SERDES[7:0]_RXP
SERDES[7:0]_RXN
SERDES[7:0]_TXP
SERDES[7:0]_TXN
SERDES_E[3:0]_TXP
SERDES_E[3:0]_TXN
SERDES[7:0]_RXP
SERDES[7:0]_RXN
MDI
SerDes
Interface
and
SERDES_E[3:0]_RXP
SERDES_E[3:0]_RXN
100BASE-FX
PCS
100BASE-FX
PMA
SFP[3:0]_SD
I2C Mux
SFP_SERIALDATA
SFP_SERIALCLK[3:0]
10/100/1000BASE-T SFP Data Path
REFCLK_P
REFCLK_N
COMA_MODE
NRESET
Management
and
Control Interface
(MIIM)
REFCLK_SEL[2:0]
REF_FILT_[2:0]
REF_REXT_[2:0]
SERDES_REXT_[1:0]
PLL and Analog
LED Interface
JTAG
MDC
MDIO
MDINT
PHY[11:0]_LED[1:0]
1. Pin shared with PHY4_LED1
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Functional Descriptions
4
Functional Descriptions
This section provides detailed information about the functionality of the VSC8512-02 device, available
configurations, operational features, and testing functionality. It includes descriptions of the various
device interfaces and their configuration. With the information in this section, the device setup
parameters can be determined for configuring the VSC8512-02 part for use in a particular application.
4.1
Operating Modes
The following table lists the operating modes of the VSC8512-02 device.
Table 1 •
Operating Modes
Operating Mode
Supported Media
Notes
SerDes MAC-to-Cat5 Link
Partner
1000BASE-T only
See Figure 2, page 3.
SGMII MAC-to-Cat5 Link
Partner
10/100/1000BASE-T
10/100/1000BASE-T
See Figure 2, page 3.
See Figure 1, page 3.
QSGMII MAC-to-Cat5 Link
Partner
QSGMII MAC-to-1000BASE-X 1000BASE-X
Link Partner
See Figure 1, page 3. Ports 8–11
only.
QSGMII MAC-to-100BASE-FX 100BASE-FX
Link Partner
See Figure 1, page 3. Ports 8–11
only.
QSGMII MAC-to-
SFP/Fiber (1000BASE-X, See Figure 1, page 3. Ports 8–11
SGMII/1000BASE-X
10/100/1000BASE-T Cu
SFP)
only (SGMII/1000BASE-X protocol
transfer).
QSGMII MAC-to-AMS and
1000BASE-X SerDes
1000BASE-X,
10/100/1000BASE-T
See Figure 1, page 3.
QSGMII MAC-to-AMS and
100BASE-FX SerDes
100BASE-FX,
10/100/1000BASE-T
See Figure 1, page 3.
QSGMII MAC-to-AMS and
SGMII/1000BASE-X
SFP/Fiber (1000BASE-X, See Figure 1, page 3.
10/100/1000BASE-T,
1000BASE-X,
SGMII/1000BASE-X protocol
transfer on ports 8–11 when
configured for SerDes media
operation.
10/100/1000BASE-T Cu
SFP)
4.2
SerDes MAC Interface
The VSC8512-02 SerDes MAC interface performs data serialization and deserialization functions using
an integrated SerDes block. The interface operates in the following modes: 1000BASE-X mode, SGMII
mode, and QSGMII mode. The SerDes and Enhanced SerDes blocks include integrated termination
resistors. Register 19G is a global register and only needs to be set once to configure the device. The
other register bits are configured on a per-port basis and the operation either needs to be repeated for
each port, or a broadcast write needs to be used by setting register 22, bit 0 to configure all the ports
simultaneously.
4.2.1
SerDes MAC
When connected to a SerDes MAC compliant to 1000BASE-X, the VSC8512-02 device provides data
throughput at a rate of 1000 Mbps only; 10 Mbps and 100 Mbps rates are not supported. To configure the
device for SerDes MAC mode, set register 19G, bits 15:14 = 01, and register 23, bit 12 = 1. The device
also supports 1000BASE-X Clause 37 MAC-side autonegotiation, and is enabled through register 16E3,
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
6
Functional Descriptions
bit 7. To configure the rest of the device for 1000 Mbps only operation, select 1000BASE-T only by
disabling the 10BASE-T/100BASE-TX advertisements in register 4.
Figure 4 • SerDes MAC Interface
0.1 µF
0.1 µF
TxP
TxN
RxP
100 Ω
RxN
SerDes MAC
PHY Port_n
TxP
100 Ω
TxN
0.1 µF
0.1 µF
RxP
RxN
100 Ω
4.2.2
SGMII MAC
When configured to detect and switch between 10BASE-T, 100BASE-T, and 1000BASE-T data rates, the
VSC8512-02 device can be connected to an SGMII-compatible MAC. To configure the device for SGMII
MAC mode, set register 19G, bits 15:14 = 01 and register 23, bit 12 = 0. This device also supports SGMII
MAC-side autonegotiation and is enabled through register 16E3, bit 7.
Figure 5 • SGMII MAC Interface
0.1 µF
0.1 µF
TxP
RxP
100 Ω
RxN
TxN
SGMII MAC
PHY Port_n
TxP
100 Ω
TxN
0.1 µF
0.1 µF
RxP
RxN
100 Ω
4.2.3
QSGMII MAC
The VSC8512-02 device supports a QSGMII MAC to convey four ports of network data and port speed
between 10BASE-T, 100BASE-T, and 1000BASE-T data rates and operates in both half-duplex and full-
duplex at all port speeds. The MAC interface protocol for each port within QSGMII can either be
1000BASE-X or SGMII, if the QSGMII MAC that the VSC8512-02 is connecting to supports this
functionality. To configure the device for QSGMII MAC mode, set register 19G, bits 15:14 = 00 or 10. This
device also supports SGMII MAC-side autonegotiation on each individual port and is enabled through
register 16E3, bit 7, of that port.
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
7
Functional Descriptions
Figure 6 • QSGMII MAC Interface
0.1 µF
SERDES_E_RxP
100 Ω
TxP
PHY
Port_n
PHY
Port_n-1
TxN
0.1 µF
0.1 µF
SERDES_E_RxN
QSGMII MAC
PHY
Port_n-2
SERDES_E_TxP
RxP
PHY
Port_n-3
100 Ω
100 Ω
RxN
0.1 µF
SERDES_E_TxN
4.3
SerDes Media Interface
The VSC8512-02 device SerDes media interface performs data serialization and deserialization
functions using an integrated SerDes block in the SerDes media interface. The interface operates at
1.25 Gbps speed, providing full-duplex and half-duplex for 10/100/1000 Mbps bandwidth that can
connect directly to 100BASE-FX/1000BASE-X-compliant optical devices as well as to
10/100/1000BASE-T copper SFP devices. The interface also provides support for unidirectional
transport as defined in IEEE 802.3-2008, Clause 66. The interface has the following SerDes operating
modes:
•
•
•
QSGMII to 1000BASE-X
QSGMII to 100BASE-FX
QSGMII to SGMII/1000BASE-X SGMII/1000BASE-X protocol transfer
The SerDes media block includes an integrated termination resistor.
A software reset through register 0, bit 15 is required when changing operating modes between
100BASE-FX and 1000BASE-X.
4.3.1
QSGMII to 1000BASE-X
The 1000BASE-X SerDes media in QSGMII mode supports IEEE 802.3 Clause 36 and Clause 37, which
describe 1000BASE-X fiber autonegotiation. In this mode, control and status of the SerDes media is
displayed in the VSC8512-02 device registers 0 through 15 in a manner similar to what is described in
IEEE 802.3 Clause 28. In this mode, connected copper SFPs can only operate at 1000BASE-T speed. A
link in this mode is established using autonegotiation (enabled or disabled) between the PHY and the link
partner. To configure the PHY in this mode, set register 23, bits 10:8 = 010. To configure 1000BASE-X
autonegotiation for this mode, set register 0, bit 12. Setting this mode and configurations can be
performed individually on each of the four ports. Ethernet packet generator (EPG), cyclical redundancy
check (CRC) counters, and loopback modes are supported in 1000BASE-X mode.
4.3.2
4.3.3
QSGMII to 100BASE-FX
The VSC8512-02 supports 100BASE-FX communication speed for connecting to fiber modules such as
GBICs and SFPs. This capability is facilitated by using the connections on the SerDes pins when
connected to a MAC through QSGMII only. Ethernet packet generator (EPG), cyclical redundancy check
(CRC) counters, and loopback modes are supported in the 100BASE-FX mode. Setting this mode and
configurations can be performed individually on each of the four ports. To configure the PHY in this
mode, set register 23, bits 10:8 = 011.
QSGMII to SGMII Protocol Conversion
QSGMII to SGMII (protocol transfer) mode is a feature that links a fiber module or triple speed
10/100/1000-T copper SFP to the QSGMII MAC through the VSC8512-02 device. SGMII can be
converted to QSGMII with protocol conversion using this mode.
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
8
Functional Descriptions
To configure the PHY in this mode, set register 23, bits 10:8 = 001. To establish the link, assert the
SFP[3:0]_SD pins.
All relevant LED modes are supported except for collision, duplex, and autonegotiation fault. The triple-
speed copper SFP’s link status and data type plugged into the port can be indicated by the PHY’s LEDs.
Setting this particular mode and configuration can be performed individually on each of the four ports
within a QSGMII grouping.
4.3.4
Unidirectional Transport for Fiber Media
The VSC8512-02 device supports 802.3ah for unidirectional transport across its 1000BASE-X and
100BASE-FX fiber media. This feature enables transmission across fiber media, regardless of whether
the PHY has determined that a valid link has been established (register 1, bit 2). The only valid operating
modes for unidirectional fiber mode are 100BASE-FX or 1000BASE-X fiber media.
To enable this feature, set register 0, bit 5 to 1. For status of the unidirectional ability, read register 1,
bit 7.
Note: Automatic media-sensing does not work with this feature. In addition, because unidirectional fiber media
must have autonegotiation disabled, SGMII autonegotiation must also be disabled (register 16E3, bit 7 =
0).
4.4
PHY Addressing and Port Mapping
This section contains information about PHY addressing and port mapping.
4.4.1
PHY Addressing
The VSC8512-02 includes two external PHY address pins to allow control of multiple PHY devices on a
system board that are sharing a common management bus. Based on the settings of these two address
control pins, the internal PHYs in the VSC8512-02 device take on the address ranges as shown in the
following table.
Table 2 •
PHY Address Range Selection
PHYADD4
PHYADD3
Internal PHY Addresses
0
0
1
1
0
1
0
1
0–11
12–23
4–15
20–31
4.4.2
SerDes Port Mapping
The VSC8512-02 includes eight 1.25 GHz SerDes macros and four 5 GHz enhanced SerDes macros.
Depending on the configuration, some of the SerDes macros are configured as either
1000BASE-X/100BASE-FX SerDes media interfaces or SGMII MAC interfaces. Also, based on
configuration, the enhanced SerDes macros are configured as either QSGMII MAC interfaces or SGMII
MAC interfaces. The following table shows the different operating modes based on the settings of
register 19G, bits 15:14.
Table 3 •
Operating Modes
Mode
19G[15:14] Operating Mode
Mode 0 00
Mode 1 01
Mode 2 10
QSGMII to CAT5 mode
SGMII to CAT5 mode
QSGMII to CAT5 and fiber media mode
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Functional Descriptions
The following table shows the SerDes port mapping in the modes of operation shown in the previous
table.
Table 4 •
SerDes Port Mapping
Interface Pins
Mode 0
Mode 1
SGMII0
SGMII0
Mode 2
SERDES_E0_TXP, SERDES_E0_TXN
SERDES_E0_RXP, SERDES_E0_RXN
SERDES_E1_TXP, SERDES_E1_TXN QSGMII0 SGMII3
SERDES_E1_RXP, SERDES_E1_RXN QSGMII0 SGMII3
SERDES_E2_TXP, SERDES_E2_TXN QSGMII1 SGMII6
SERDES_E2_RXP, SERDES_E2_RXN QSGMII1 SGMII6
SERDES_E3_TXP, SERDES_E3_TXN QSGMII2 SGMII9
SERDES_E3_RXP, SERDES_E3_RXN QSGMII2 SGMII9
QSGMII0
QSGMII0
QSGMII1
QSGMII1
QSGMII2
QSGMII2
SERDES0_TXP, SERDES0_TXN
SERDES0_RXP, SERDES0_RXN
SERDES1_TXP, SERDES1_TXN
SERDES1_RXP, SERDES1_RXN
SERDES2_TXP, SERDES2_TXN
SERDES2_RXP, SERDES2_RXN
SERDES3_TXP, SERDES3_TXN
SERDES3_RXP, SERDES3_RXN
SERDES4_TXP, SERDES4_TXN
SERDES4_RXP, SERDES4_RXN
SERDES5_TXP, SERDES5_TXN
SERDES5_RXP, SERDES5_RXN
SERDES6_TXP, SERDES6_TXN
SERDES6_RXP, SERDES6_RXN
SERDES7_TXP, SERDES7_TXN
SERDES7_RXP, SERDES7_RXN
SGMII1
SGMII1
SGMII2
SGMII2
SGMII4
SGMII4
SGMII5
SGMII5
SGMII7
SGMII7
SGMII8
SGMII8
SGMII10
SGMII10
SGMII11
SGMII11
FIBER11
FIBER11
FIBER10
FIBER10
FIBER9
FIBER9
FIBER8
FIBER8
4.5
Cat5 Twisted Pair Media Interface
The VSC8512-02 twisted pair interface is compliant with IEEE 802.3-2008 and the IEEE 802.3az
standard for Energy Efficient Ethernet.
4.5.1
Voltage-Mode Line Driver
Unlike many other gigabit PHYs, the VSC8512-02 uses a patented voltage-mode line driver that allows it
to fully integrate the series termination resistors, which are required to connect the PHY’s Cat5 interface
to an external 1:1 transformer. Also, the interface does not require the user to place an external voltage
on the center tap of the magnetic. The following illustration shows the connections.
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Functional Descriptions
Figure 7 • Cat5 Media Interface
PHY Port_n
RJ-45
Transformer
TXVPA_n
1
2
3
6
4
5
7
8
A+
A–
0.1 µF
0.1 µF
0.1 µF
0.1 µF
TXVNA_n
TXVPB_n
TXVNB_n
B+
B–
C+
C–
D+
D–
TXVPC_n
TXVNC_n
TXVPD_n
TXVND_n
75 Ω
75 Ω
75 Ω
75 Ω
1000 pF,
2 kV
4.5.2
Cat5 Autonegotiation and Parallel Detection
The VSC8512-02 supports twisted pair autonegotiation, as defined by IEEE 802.3-2008 Clause 28 and
IEEE 802.3az. The autonegotiation process evaluates the advertised capabilities of the local PHY and its
link partner to determine the best possible operating mode. In particular, autonegotiation can determine
speed, duplex configuration, and master or slave operating modes for 1000BASE-TX. Autonegotiation
also enables a connected MAC to communicate with its link partner MAC through the VSC8512-02 using
optional next pages, which set attributes that may not otherwise be defined by the IEEE standard.
If the Cat5 link partner does not support autonegotiation, the VSC8512-02 automatically uses parallel
detection to select the appropriate link speed.
Autonegotiation is disabled by clearing register 0, bit 12. If autonegotiation is disabled, the state of
register bits 0.6, 0.13, and 0.8 determine the device operating speed and duplex mode. Note that while
10BASE-T and 100BASE-T do not require autonegotiation, Clause 40 has defined 1000BASE-T to
require autonegotiation.
4.5.3
4.5.4
1000BASE-T Forced Mode Support
VSC8512-02 provides support for a 1000BASE-T forced test mode. In this mode, the PHY can be forced
into 1000BASE-T mode and does not require manual setting of master/slave at the two ends of the link.
This mode is for test purposes only, and should not be used in normal operation. To configure a PHY in
this mode, set register 17E2, bit 5 = 1 and register 0, bits 6 and 13 = 10.
Automatic Crossover and Polarity Detection
For trouble-free configuration and management of Ethernet links, the VSC8512-02 includes a robust
automatic crossover detection feature for all three speeds on the twisted-pair interface (10BASE-T,
100BASE-T, and 1000BASE-T). Known as HP Auto-MDIX, the function is fully compliant with Clause 40
of IEEE 802.3-2008.
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Functional Descriptions
Additionally, the device detects and corrects polarity errors on all MDI pairs — a useful capability that
exceeds the requirements of the standard.
Both HP Auto-MDIX detection and polarity correction are enabled in the device by default. Default
settings can be changed using device register bits 18.5:4. Status bits for each of these functions are
located in register 28.
Note: The VSC8512-02 can be configured to perform HP Auto-MDIX, even when autonegotiation is disabled
and the link is forced into 10/100 speeds. To enable this feature, set register 18.7 to 0. To disable the
feature, set register 0.12 to 0.
The HP Auto-MDIX algorithm successfully detects, corrects, and operates with any of the MDI wiring pair
combinations listed in the following table.
Table 5 •
Supported MDI Pair Combinations
1, 2
A
3, 6
B
4, 5
C
7, 8
D
Mode
Normal MDI
B
A
D
C
Normal MDI-X
A
B
D
C
Normal MDI with pair swap on C and D pair
Normal MDI-X with pair swap on C and D pair
B
A
C
D
4.5.5
4.5.6
Manual HP Auto-MDIX Setting
As an alternative to HP Auto-MDIX detection, the PHY can be forced to be MDI or MDI-X using
register 19E1, bits 3:2. Setting these bits to 10 forces MDI and setting 11 forces MDI-X. Leaving the
bits 00 enables the HP Auto-MDIX setting to be based on register 18, bits 7 and 5.
Link Speed Downshift
For operation in cabling environments that are incompatible with 1000BASE-T, the VSC8512-02 provides
an automatic link speed downshift option. When enabled, the device automatically changes its
1000BASE-T autonegotiation advertisement to the next slower speed after a set number of failed
attempts at 1000BASE-T. No reset is required to get out of this state if a subsequent link partner with
1000BASE-T support is connected. This feature is useful in setting up in networks using older cable
installations that include only pairs A and B, and not pairs C and D.
To configure and monitor link speed downshifting, set register 20E1, bits 4:1. For more information, see
Table 49, page 59.
4.5.7
Energy Efficient Ethernet
The VSC8512-02 supports the IEEE 802.3az Energy Efficient Ethernet standard that is currently in
development. This new standard provides a method for reducing power consumption on an Ethernet link
during times of low utilization. It uses low power idles (LPI) to achieve this objective.
Figure 8 • Low Power Idle Operation
Active
Low-Power Idle
Active
Quiet
Quiet
Quiet
Ts
Tq
Tr
Using LPI, the usage model for the link is to transmit data as fast as possible and then return to a low
power idle state. Energy is saved on the link by cycling between active and low power idle states. During
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Functional Descriptions
LPI, power is reduced by turning off unused circuits and using this method, energy use scales with
bandwidth utilization.
The VSC8512-02 uses LPI to optimize power dissipation in 100BASE-TX and 1000BASE-T modes of
operation. In addition, the IEEE 802.3az standard defines a 10BASE-Te mode that reduces transmit
signal amplitude from 5 Vp-p to ~3.3 Vp-p. This mode reduces power consumption in 10 Mbps link speed
and fully interoperates with legacy 10BASE-T compliant PHYs over 100 m Cat5 cable or better.
To configure the VSC8512-02 in 10BASE-Te mode, set register 17E2.15 to 1 for each port. Additional
Energy Efficient Ethernet features are controlled through Clause 45 registers. For more information, see
Clause 45 Registers to Support Energy Efficient Ethernet, page 79.
4.6
Automatic Media-Sense Interface Mode
Automatic media-sense (AMS) mode automatically sets the media interface to Cat5 mode or SerDes
mode. The active media mode chosen is based on the automatic media-sense preferences set in the
device register 23, bit 11. The following illustration shows a block diagram of AMS functionality on ports 8
through 11 of the VSC8512-02 device.
Figure 9 • Automatic Media-Sense Block Diagram
PHY port_n
Cat5
MAC
SGMII /
Serial MAC
Auto Sense
Logic
TD
RD
SerDes
SIGDET
Fiber Optic
Module
When both SerDes and Cat5 media interfaces attempt to establish a link, the preferred media interface
overrides a link-up of the non-preferred media interface. For example, if the preference is set for SerDes
mode and Cat5 media establishes a link, then Cat5 becomes the active media interface. However, after
the SerDes media interface establishes a link, the Cat5 interface drops its link because the preference
was set for SerDes mode. In this scenario, the SerDes preference determines the active media source
until the SerDes link is lost. Also, Cat5 media cannot link up unless there is no SerDes media link
established. The following table shows the possible link conditions based on preference settings.
Table 6 •
AMS Media Preferences
Cat5 Linked,
SerDes Linked,
Both Cat5 and
Preference Cat5 Linked,
SerDes Linked,
SerDes Attempts to Cat5 Attempts to SerDesAttempt to
Setting
SerDes
Cat5
Fiber Not Linked Cat5 Not Linked Link
Link
Link
Cat5
Cat5
SerDes
SerDes
SerDes
Cat5
SerDes
Cat5
SerDes
Cat5
The status of the media mode selected by the AMS can be read from device register 20E1, bits 7:6. It
indicates whether copper media, SerDes media, or no media is selected. Each PHY has four automatic
media-sense modes. The difference between the modes is based on the SerDes media modes:
•
•
•
QSGMII MAC to AMS and 1000BASE-X SerDes
QSGMII MAC to AMS and 100BASE-FX SerDes
QSGMII MAC to AMS and SGMII (protocol transfer)
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Functional Descriptions
For more information about SerDes media mode functionality with AMS enabled, see SerDes Media
Interface, page 8.
4.7
Reference Clock
The device reference clock can be a 25 MHz, 125 MHz, or 156.25 MHz clock signal. It can be either a
differential reference clock or a single-ended clock. However, 25 MHz single-ended operation is not
recommended when using QSGMII due to the jitter specification requirements of this interface. For more
information, see Reference Clock, page 82.
4.7.1
Configuring the REFCLK
There are three REFCLK_SEL pins to configure the REFCLK speed. The following table shows the
functionality and associated REFCLK frequency.
Table 7 •
REFCLK Frequency Selection
REFCLK_SEL2 REFCLK_SEL1 REFCLK_SEL0 REFCLK Frequency
0
0
1
0
0
0
0
1
0
125 MHz
156.25 MHz
25 MHz
4.7.2
Single-Ended REFCLK Input
To use a single-ended REFCLK, an external resistor network is required. The purpose of the network is
to limit the amplitude and to adjust the center of the swing. The configurations for a single-ended
REFCLK are shown in the following illustrations.
Figure 10 • 2.5 V CMOS Single-Ended REFCLK Input Resistor Network
220 Ω
REFCLK_P
REFCLK_N
2.5 V
CMOS
VDD_A
910 Ω
VSS
Figure 11 • 3.3 V CMOS Single-Ended REFCLK Input Resistor Network
270 Ω
REFCLK_P
REFCLK_N
3.3 V
CMOS
VDD_A
430 Ω
VSS
4.7.3
Differential REFCLK Input
AC-coupling is required when using a differential REFCLK. Differential clocks must be capacitively
coupled and LVDS-compliant. The following illustration shows the configuration.
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Functional Descriptions
Figure 12 • AC-Coupling Required for REFCLK Input
REFCLK_P
PHY Equivalent
Termination Circuit
0.1 µF
50 Ω
50 Ω
VTT (Internal Voltage)
REFCLK_N
0.1 µF
4.8
Ethernet Inline Powered Devices
The VSC8512-02 can detect legacy inline powered devices in Ethernet network applications. Inline
powered detection capability is useful in systems that enable IP phones and other devices (such as
wireless access points) to receive power directly from their Ethernet cable, similar to office digital phones
receiving power from a private branch exchange (PBX) office switch over telephone cabling. This type of
setup eliminates the need for an external power supply and enables the inline powered device to remain
active during a power outage, assuming that the Ethernet switch is connected to an uninterrupted power
supply, battery, back-up power generator, or other uninterruptable power source.
For more information about legacy inline powered device detection, visit the Cisco Web site at
www.cisco.com. The following illustration shows an example of an inline powered Ethernet switch
application.
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Functional Descriptions
Figure 13 • Inline Powered Ethernet Switch Diagram
Gigabit Switch
Processor
Control
SMI
SGMII
Interface
Inline,
Power-Over-Ethernet
(PoE)
PHY_port0
PHY_port1
PHY_portn
Power Supply
Transformer
Transformer
Transformer
RJ-45
I/F
RJ-45
I/F
RJ-45
I/F
Cat5
Link
Partner
Link
Partner
Link
Partner
The following procedure describes the process that an Ethernet switch must perform to process inline
power requests made by a link partner (LP) that is, in turn, capable of receiving inline power:
1. Enable the inline powered device detection mode on each VSC8512-02 PHY using its serial
management interface. Set register bit 23E1.10 to 1.
2. Ensure that the VSC8512-02 autonegotiation enable bit (register 0.12) is also set to 1. In the
application, the device sends a special fast link pulse (FLP) signal to the LP. Reading register
bit 23E1.9:8 returns 00 during the search for devices that require power over Ethernet (PoE).
3. The VSC8512-02 PHY monitors its inputs for the FLP signal looped back by the LP. An LP capable
of receiving PoE loops back the FLP pulses when the LP is in a powered down state. This is
reported when VSC8512-02 register bit 23E1.9:8 reads back 01. It can also be verified as an inline
power detection interrupt by reading VSC8512-02 register bit 26.9, which should be a 1, and which
is subsequently cleared and the interrupt de-asserted after the read. If an LP device does not loop
back the FLP after a specific time, VSC8512-02 register bit 23E1.9:8 automatically resets to 10.
4. If the VSC8512-02 PHY reports that the LP requires PoE, the Ethernet switch must enable inline
power on this port, externally of the PHY.
5. The PHY automatically disables inline powered device detection if the VSC8512-02 register
bits 23E1.9:8 automatically resets to 10, and then automatically changes to its normal
autonegotiation process. A link is then auto-negotiated and established when the link status bit is set
(register bit 1.2 is set to 1).
6. In the event of a link failure (indicated when VSC8512-02 register bit 1.2 reads 0), the inline power
should be disabled to the inline powered device external to the PHY. The VSC8512-02 PHY disables
its normal autonegotiation process and re-enables its inline powered device detection mode.
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Functional Descriptions
4.9
IEEE 802.3af PoE Support
The VSC8512-02 is compatible with switch designs that are intended for use in systems that supply
power to data terminal equipment (DTE) by means of the MDI or twisted pair cable, as described in
IEEE 802.3af Clause 33.
4.10 ActiPHY Power Management
In addition to the IEEE-specified power-down control bit (device register bit 0.11), the device also
includes an ActiPHY power management mode for each PHY. This mode enables support for power-
sensitive applications. It utilizes a signal-detect function that monitors the media interface for the
presence of a link to determine when to automatically power-down the PHY. The PHY wakes up at a
programmable interval and attempts to wake up the link partner PHY by sending a burst of FLP over
copper media.
The ActiPHY power management mode in the VSC8512-02 is enabled on a per-port basis during normal
operation at any time by setting register bit 28.6 to 1.
The following operating states are possible when ActiPHY mode is enabled:
•
•
•
Low power state
LP wake-up state
Normal operating state (link-up state)
The VSC8512-02 switches between the low power state and LP wake-up state at a programmable rate
(the default is two seconds) until signal energy has been detected on the media interface pins. When
signal energy is detected, the PHY enters the normal operating state. If the PHY is in its normal operating
state and the link fails, the PHY returns to the low power state after the expiration of the link status time-
out timer. After reset, the PHY enters the low power state.
When autonegotiation is enabled in the PHY, the ActiPHY state machine operates as described. If
autonegotiation is disabled and the link is forced to use 10BASE-T or 100BASE-TX modes while the
PHY is in its low power state, the PHY continues to transition between the low power and LP wake-up
states until signal energy is detected on the media pins. At that time, the PHY transitions to the normal
operating state and stays in that state even when the link is dropped. If autonegotiation is disabled while
the PHY is in the normal operation state, the PHY stays in that state when the link is dropped and does
not transition back to the low power state.
The following illustration shows the relationship between ActiPHY states and timers.
Figure 14 • ActiPHY State Diagram
Low Power State
Signal Energy Detected on
Media
FLP Burst or
Clause 37 Restart
Signal Sent
Sleep Timer Expires
Timeout Timer Expires and
Auto-negotiation Enabled
Normal
Operation State
LP Wake-up
State
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Functional Descriptions
4.10.1 Low Power State
In the low power state, all major digital blocks are powered down. However, the following functionality is
provided:
•
•
SMI interface (MDC, MDIO, and MDINT pins)
CLKOUT
In this state, the PHY monitors the media interface pins for signal energy. The PHY comes out of low
power state and transitions to the normal operating state when signal energy is detected on the media.
This happens when the PHY is connected to one of the following:
•
•
Autonegotiation-capable link partner
Another PHY in enhanced ActiPHY LP wake-up state
In the absence of signal energy on the media pins, the PHY periodically transitions from low-power state
to LP wake-up state, based on the programmable sleep timer (register bits 20E1.14:13). The actual sleep
time duration is randomized from –80 ms to 60 ms to avoid two linked PHYs in ActiPHY mode entering a
lock-up state during operation.
4.10.2 Link Partner Wake-Up State
In the link partner wake-up state, the PHY attempts to wake up the link partner. Up to three complete FLP
bursts are sent on alternating pairs A and B of the Cat5 media for a duration based on the wake-up timer,
which is set using register bits 20E1.12:11.
In this state, the following functionality is provided:
•
•
SMI interface (MDC, MDIO, and MDINT pins)
CLKOUT
After sending signal energy on the relevant media, the PHY returns to the low power state.
4.10.3 Normal Operating State
In the normal operating state, the PHY establishes a link with a link partner. When the media is
unplugged or the link partner is powered down, the PHY waits for the duration of the programmable link
status time-out timer, which is set using register bit 28.7 and bit 28.2. It then enters the low power state.
4.11
Media Recovered Clock Outputs
For Synchronous Ethernet applications, the VSC8512-02 includes two recovered clock output pins,
RCVRD_CLK0 and RCVRD_CLK1, that are controlled by registers 23G and 24G, respectively. These
pins are synchronized to the clock of the active media link.
To enable recovered clock output, set register 23G or 24G, bit 15, to 1. By default, the recovered clock
output pins are disabled and held low, including when NRESET is asserted. Registers 23G and 24G also
control the PHY port for clock output, the clock source, the clock frequency (either 25 MHz or 125 MHz),
and squelch conditions.
4.11.1 Clock Selection Settings
On each pin, the recovered clock supports the following sources, as set by registers 23G or 24G, bits 2:0:
•
Fiber SerDes media
•
•
Copper media
Copper transmitter TCLK output (RCVRD_CLK0 only)
Note: When using the automatic media-sense feature, the recovered clock output cannot automatically change
between each active media. Changing the media source must be managed through the recovered clock
register settings.
Note: The 10BASE-T mode and 1000BASE-T master mode are not effective for Synchronous Ethernet clock
recovery. For 10BASE-T mode, the receiver does not produce a reliable continuous clock source. For
1000BASE-T master mode, the clock is based on the VSC8512-02 REFCLK input, which is a local clock.
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Functional Descriptions
4.11.2 Clock Output Squelch
Under certain conditions, the PHY outputs a clock based on the REFCLK pin, such as when there is no
link present or during autonegotiation. To prevent an undesirable clock from appearing on the recovered
clock pins, the VSC8512-02 squelches, or inhibits, the clock output based on any of the following criteria:
•
•
No link is detected (the link status register 1, bit 2 = 0).
The link is found to be unstable using the fast link failure detection feature (FAST_LINK_STATUS pin
is asserted high when enabled).
•
•
The active link is in 10BASE-T or in 1000BASE-T master mode. These modes produce unreliable
recovered clock sources.
CLK_SQUELCH_IN is enabled to squelch the clock.
Use registers 23G or 24G, bits 5:4 to configure the clock squelch criteria. These registers can also
disable the squelch feature. The CLK_SQUELCH_IN pin functionality is controlled by register bit 14G.14.
When this bit is set to 1, the CLK_SQUELCH_IN pin also controls the squelching of the clock. When
enabled, both RCVRD_CLK0 and RCVRD_CLK1 are squelched when the CLK_SQUELCH_IN pin is
high.
4.12 Serial Management Interface
The VSC8512-02 device includes an IEEE 802.3-compliant serial management interface (SMI) that is
affected by use of its MDC and MDIO pins. The SMI provides access to device control and status
registers. The register set that controls the SMI consists of 32 16-bit registers, including all required
IEEE-specified registers. Also, there are additional pages of registers accessible using device
register 31.
Energy Efficient Ethernet control registers are available through the SMI using Clause 45 registers and
Clause 22 register access in registers 13 through 14. For more information, see Table 27, page 46 and
Table 90, page 79.
The SMI is a synchronous serial interface with input data to the VSC8512-02 on the MDIO pin that is
clocked on the rising edge of the MDC pin. The output data is sent on the MDIO pin on the rising edge of
the MDC signal. The interface can be clocked at a rate from 0 MHz to 12.5 MHz, depending on the total
load on MDIO. An external 2-kΩ pull-up resistor is required on the MDIO pin.
4.12.1 SMI Frames
Data is transferred over the SMI using 32-bit frames with an optional, arbitrary-length preamble. Before
the first frame can be sent, at least two clock pulses on MDC must be provided with the MDIO signal at
logic one to initialize the SMI state machine. The following illustrations show the SMI frame format for
read and write operations.
Figure 15 • SMI Read Frame
Station manager drives MDIO
PHY drives MDIO
MDC
MDIO
Z
Z
1
0
1
1
0
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
Z
0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z
Z
Preamble
(optional)
Register Data
from PHY
Register Address
to PHY
Idle
SFD Read
PHY Address
TA
Idle
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Functional Descriptions
Figure 16 • SMI Write Frame
Station manager drives MDIO (PHY tri-states MDIO during the entire sequence)
MDC
MDIO
Z
Z
1
0
1
0
1
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
1
0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z
Z
Preamble
(optional)
Register Data
from PHY
Register Address
to PHY
Idle
SFD Write
PHY Address
TA
Idle
The following list provides additional information about the terms used in the SMI read and write timing
diagrams.
4.12.1.1 Idle
During idle, the MDIO node goes to a high-impedance state. This allows an external pull-up resistor to
pull the MDIO node up to a logical 1 state. Because the idle mode should not contain any transitions on
MDIO, the number of bits is undefined during idle.
4.12.1.2 Preamble
By default, preambles are not expected or required. The preamble is a string of ones. If it exists, the
preamble must be at least one bit; otherwise, it can be of an arbitrary length.
4.12.1.3 Start of Frame (SFD)
A pattern of 01 indicates the start of frame. If the pattern is not 01, all following bits are ignored until the
next preamble pattern is detected.
4.12.1.4 Read or Write Opcode
A pattern of 10 indicates a read. A 01 pattern indicates a write. If the bits are not either 01 or 10, all
following bits are ignored until the next preamble pattern is detected.
4.12.1.5 PHY Address
The particular VSC8512-02 responds to a message frame only when the received PHY address matches
its physical address. The physical address is 5 bits long (4:0).
4.12.1.6 Register Address
The next five bits are the register address.
4.12.1.7 Turnaround
The two bits used to avoid signal contention when a read operation is performed on the MDIO are called
the turnaround (TA) bits. During read operations, the VSC8512-02 drives the second TA bit, a logical 0.
4.12.1.8 Data
The 16-bits read from or written to the device are considered the data or data stream. When data is read
from a PHY, it is valid at the output from one rising edge of MDC to the next rising edge of MDC. When
data is written to the PHY, it must be valid around the rising edge of MDC.
4.12.1.9 Idle
The sequence is repeated.
4.12.2 SMI Interrupt
The SMI includes an output interrupt signal, MDINT, for signaling the station manager when certain
events occur in the VSC8512-02.
The MDINT pin can be configured for open-drain (active-low) by tying the pin to a pull-up resistor and to
VDDIO. The following illustration shows this configuration.
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Functional Descriptions
Figure 17 • MDINT Configured as an Open-Drain (Active-Low) Pin
External Pull-up
Resistor at the
VDDIO
Station Manager
for Open-drain
(Active-low Mode)
PHY_n
Interrupt Pin Enable
MDINT
MDINT
(to the Station
Manager)
(Register 25.15)
Interrupt Pin Status
(Register 26.15)
Alternatively, the MDINT pin can be configured for open-source (active-high) by tying the pin to a pull-
down resistor and to VSS. The following illustration shows this configuration.
Figure 18 • MDINT Configured as an Open-Source (Active-High) Pin
VDDIO
Interrupt Pin Enable
(Register 25.15)
MDINT
(to the Station
Manager)
MDINT
Interrupt Pin Status
(Register 26.15)
External Pull-down
at the Station
PHY_n
Manager
For Open-source
(Active-high Mode)
When a PHY generates an interrupt, the MDINT pin is asserted (driven high or low, depending on resistor
connection) if the interrupt pin enable bit (MII register 25.15) is set.
4.13 LED Interface
The VSC8512-02 outputs two LED signals per port, LED0 and LED1, through direct-drive signal outputs,
or four LED signals per port (LED0, LED1, LED2, and LED3) through an enhanced serial LED mode. For
more information, see Enhanced Serial LED Mode, page 25. The polarity of the LED outputs is
programmable and can be changed through register 17E2.13:10. The default polarity is active low.
Basic serial LED mode is also supported, in which all possible signals that can be displayed on LEDs are
sent out on the serial LED stream for further processing by an external programmable device. For more
information, see “Basic Serial LED Mode,” .
The PHY[11:8]_LED1 pins are multipurpose pins and can be configured to serve as LED input pins. For
more information, see Table 76, page 71.
4.13.1 LED Modes
Each LED pin can be configured to display different status information that can be selected by setting the
LED mode in register 29. The modes listed in the following table are equivalent to the setting used in
register 29 to configure each LED pin. The default LED state is active low and can be changed by
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Functional Descriptions
modifying the value in register 17E2, bits 13:10. The blink/pulse-stretch is dependent on the LED
behavior setting in register 30.
Table 8 •
LED Mode and Function Summary
Mode Function Name
LED State and Description
0
1
2
3
4
Link/Activity
1 = No link in any speed on any media interface.
0 = Valid link at any speed on any media interface.
Blink or pulse-stretch = Valid link at any speed on any media
interface with activity present.
Link1000/Activity
Link100/Activity
Link10/Activity
1 = No link in 1000BASE-T or 1000BASE-X.
0 = Valid 1000BASE-T or 1000BASE-X.
Blink or pulse-stretch = Valid 1000BASE-T or 1000BASE-X link
with activity present.
1 = No link in 100BASE-TX or 100BASE-FX.
0 = Valid 100BASE-TX or 100BASE-FX.
Blink or pulse-stretch = Valid 100BASE-TX or 100BASE-FX link
with activity present.
1 = No link in 10BASE-T.
0 = Valid 10BASE-T link.
Blink or pulse-stretch = Valid 10BASE-T link with activity
present.
Link100/1000/Activity
1 = No link in 100BASE-TX, 100BASE-FX, 1000BASE-X, or
1000BASE-T.
0 = Valid 100BASE-TX, 100BASE-FX, 1000BASE-X, or
1000BASE-T link.
Blink or pulse-stretch = Valid 100BASE-TX, 100BASE-FX,
1000BASE-X, or 1000BASE-T link with activity present.
5
6
7
8
Link10/1000/Activity
Link10/100/Activity
1 = No link in 10BASE-T, 1000BASE-X, or 1000BASE-T.
0 = Valid 10BASE-T, 1000BASE-X, or 1000BASE-T link.
Blink or pulse-stretch = Valid 10BASE-T, 1000BASE-X, or
1000BASE-T link with activity present.
1 = No link in 10BASE-T, 100BASE-FX, or 100BASE-TX.
0 = Valid 10BASE-T 100BASE-FX, or 100BASE-TX, link.
Blink or pulse-stretch = Valid 10BASE-T, 100BASE-FX, or
100BASE-TX link with activity present.
Link100BASE-FX/1000 1 = No link in 100BASE-FX or 1000BASE-X.
BASE-X/Activity
0 = Valid 100BASE-FX or 1000BASE-X link.
Blink or pulse-stretch = Valid 100BASE-FX or 1000BASE-X link
with activity present.
Duplex/Collision
1 = Link established in half-duplex mode, or no link established.
0 = Link established in full-duplex mode.
Blink or pulse-stretch = Link established in half-duplex mode but
collisions are present.
9
Collision
Activity
1 = No collision detected.
Blink or pulse-stretch = Collision detected.
10
1 = No activity present.
Blink or pulse-stretch = Activity present (becomes TX activity
present if register bit 30.14 is set to 1).
11
100BASE-FX/1000BAS 1 = No 100BASE-FX or 1000BASE-X activity present.
E-X Fiber Activity
Blink or pulse-stretch = 100BASE-FX or 1000BASE-X activity
present (becomes RX activity present if register bit 30.14 is set
to 1).
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Functional Descriptions
Table 8 •
LED Mode and Function Summary (continued)
Mode Function Name
LED State and Description
12
Autonegotiation Fault
1 = No autonegotiation fault present.
0 = Autonegotiation fault occurred.
13
Serial Mode
Serial stream = See Basic Serial LED Mode, page 24. Only
relevant on PHY port 0 and reserved in others.
14
15
Force LED Off
Force LED On
1 = De-asserts the LED(1)
0 = Asserts the LED(1)
.
.
1. Setting this mode suppresses LED blinking after reset.
4.13.2 Extended LED Modes
In addition to the LED modes in register 29, there are also additional LED modes that are enabled on
PHY[11:8]_LED1 whenever the corresponding register 19E1, bits 15 to 12 are set to 1. Each of these bits
enables extended modes on a specific LED pin and these extended modes are shown in the following
table. For example, LED0 = mode 17 means that register 19E1 bit 12 = 1 and register 29 bits 3 to 0 =
0001.
Table 9 •
Extended LED Mode and Function Summary
Mode Function Name
LED State and Description
16
17
18
19
Link1000BASE-X Activity 1 = No link in 1000BASE-X.
0 = Valid 1000BASE-X link.
Link100BASE-FX Activity 1 = No link in 100BASE-FX.
0 = Valid 100BASE-FX link.
1000BASE-X Activity
1 = No 1000BASE-X activity present.
Blink or pulse-stretch = 1000BASE-X activity present.
100BASE-FX Activity
1 = No 100BASE-FX activity present.
Blink or pulse-stretch = 100BASE-FX activity present.
20
21
22
Force LED Off
Force LED On
Fast Link Fail
1 = De-asserts the LED.
0 = Asserts the LED. LED pulsing is disabled in this mode.
1 = Enable Fast Link Fail on LED0 pin
0 = Disable
4.13.3 LED Behavior
Several LED behaviors can be programmed into the VSC8512-02. Use the settings in register 30 and
19E1 to program LED behavior, which includes the following:
4.13.3.1 LED Combine
Enables an LED to display the status for a combination of primary and secondary modes. This can be
enabled or disabled for each LED pin. For example, a copper link running in 1000BASE-T mode and
activity present can be displayed with one LED by configuring an LED pin to Link1000/Activity mode. The
LED asserts when linked to a 1000BASE-T partner and also blinks or performs pulse-stretch when
activity is either transmitted by the PHY or received by the Link Partner. When disabled, the combine
feature only provides status of the selected primary function. In this example, only Link1000 asserts the
LED, and the secondary mode, activity, does not display if the combine feature is disabled.
4.13.3.2 LED Blink or Pulse-Stretch
This behavior is used for activity and collision indication. This can be uniquely configured for each LED
pin. Activity and collision events can occur randomly and intermittently throughout the link-up period.
Blink is a 50% duty cycle oscillation of asserting and de-asserting an LED pin. Pulse-stretch guarantees
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Functional Descriptions
that an LED is asserted and de-asserted for a specific period of time when activity is either present or not
present. These rates can also be configured using a register setting.
4.13.3.3 Rate of LED Blink or Pulse-Stretch
This behavior controls the LED blink rate or pulse-stretch length when blink/pulse-stretch is enabled on
an LED pin. The blink rate, which alternates between a high and low voltage level at a 50% duty cycle,
can be set to 2.5 Hz, 5 Hz, 10 Hz, or 20 Hz. For pulse-stretch, the rate can be set to 50 ms, 100 ms,
200 ms, or 400 ms. The blink rate selection for PHY0 globally sets the rate used for all LED pins on all
PHY ports.
4.13.3.4 LED Pulsing Enable
To provide additional power savings, the LEDs (when asserted) can be pulsed at 5 kHz, 20% duty cycle.
4.13.3.5 LED Blink After Reset
The LEDs will blink for one second after power-up and after any time all resets have been de-asserted.
This can be disabled through register 19E1, bit 11 = 0.
4.13.3.6 Fiber LED Disable
This bit controls whether the LEDs indicate the fiber and copper status (default) or the copper status only.
4.13.3.7 Pulse Programmable Control
These bits add the ability to width and frequency of LED pulses. This feature facilities power reduction
options.
4.13.3.8 Fast Link Failure
For more information about this feature, see Fast Link Failure Indication, page 25.
4.13.4 Basic Serial LED Mode
Optionally, the VSC8512-02 can be configured so that access to all its LED signals is available through
two pins. This option is enabled by setting LED0 on PHY0 to serial LED mode. When serial LED mode is
enabled on PHY0, the PHY0_LED0 pin becomes the basic serial data pin, and the PHY0_LED1 pin
becomes the serial clock pin. All other LED pins can still be configured normally. The serial LED mode
clocks the 144 LED status bits on the rising edge of the serial clock.
The LED behavior settings can also be used in serial LED mode. The controls are used on a per-PHY
basis, where the LED combine and LED blink or pulse-stretch setting of LED0_n for each PHY is used to
control the behavior of each bit of the serial LED stream for each corresponding PHY. To configure LED
behavior, set device register 30.
The serial bitstream outputs, 1 through 144, of each LED signal are shown in the following table
beginning with PHY port 0 and ending with PHY port 11. The individual signals can be clocked in the
order shown.
Table 10 • LED Serial Stream Order
PHY0
PHY1
PHYx
PHY11
Bit 1. Link/Activity
Bit 2. Link1000/Activity
Bit 3. Link100/Activity
Bit 4. Link10/Activity
Bit 5. Fiber Link/Activity
Bit 6. Duplex/Collision
Bit 7. Collision
Bit 13. Link/Activity
Bit 14. Link1000/Activity
Bit 15. Link100/Activity
Bit 16. Link10/Activity
Bit 17. Fiber Link/Activity
Bit 18. Duplex/Collision
Bit 19. Collision
Bit [X]. Link/Activity
Bit [X]. Link1000/Activity
Bit [X]. Link100/Activity
Bit [X]. Link10/Activity
Bit [X]. Fiber Link/Activity
Bit [X]. Duplex/Collision
Bit [X]. Collision
Bit 133. Link/Activity
Bit 134. Link1000/Activity
Bit 135. Link100/Activity
Bit 136. Link10/Activity
Bit 137. Fiber Link/Activity
Bit 138. Duplex/Collision
Bit 139. Collision
Bit 8. Activity
Bit 20. Activity
Bit [X]. Activity
Bit 140. Activity
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Functional Descriptions
Table 10 • LED Serial Stream Order (continued)
PHY0
PHY1
PHYx
PHY11
Bit 9. Fiber Activity
Bit 10. TX Activity
Bit 11. RX Activity
Bit 21. Fiber Activity
Bit 22. TX Activity
Bit 23. RX Activity
Bit [X]. Fiber Activity
Bit [X]. TX Activity
Bit [X]. RX Activity
Bit 141. Fiber Activity
Bit 142. TX Activity
Bit 143. RX Activity
Bit 144. Autonegotiation Fault
Bit 12. Autonegotiation
Fault
Bit 24. Autonegotiation
Fault
Bit [X]. Autonegotiation
Fault
4.13.5 Enhanced Serial LED Mode
VSC8512-02 can be configured to output up to four LED signals per port on a serial stream that can be
de-serialized externally to drive LEDs on the system board. This functionality is controlled by setting
register 25G, bits 7:1. In this mode, the serial LED_DATA is shifted out on the falling edge of LED_CLK
and is latched in the external serial to parallel converter on the rising edge of LED_CLK. The falling edge
of LED_LD signal can be used to shift the data from the shift register in the converter to the parallel
output drive register. If a separate parallel output drive register is not used in the external serial to parallel
converter, then the LEDs will blink at a high frequency as the data bits are being shifted through which
may be undesirable. The LED_PULSE signal provides a 5 kHz pulse stream whose duty cycle can be
modulated to turn on/off LEDs at a high rate. This signal can be tied to the output enable signal of the
serial to parallel converter to provide the LED dimming functionality to save energy.
4.13.6 LED Port Swapping
For additional hardware configurations, the VSC8512-02 can have its LED port order swapped. This is a
useful feature to help simplify PCB layout design. Register 25G bit 0 controls the LED port swapping
mode.
4.14 Fast Link Failure Indication
To aid Synchronous Ethernet applications, the VSC8512-02 can indicate the onset of a link failure in less
than 1 ms. By comparison, the IEEE 802.3 standard establishes a delay of up to 750 ms before
indicating that a 1000BASE-T link is no longer present. A fast link failure indication is critical to support
ports used in a synchronization timing link application. The fast link failure indication works for all copper
and fiber media speeds. The FAST_LINK_STATUS pin provides the external hardware notification of this
event.
Note: For all links except 1000BASE-T, the fast link failure indication matches the link status register
(address 1, bit 2). For 1000BASE-T links, the link failure is based on a circuit that analyzes the integrity of
the link, and at the indication of failure, will assert.
4.15 Integrated I2C Multiplexer
The VSC8512-02 includes an integrated quad I2C multiplexer (MUX), eliminating the need for an
external two-wire serial device for the control and status of SFP or PoE modules. There are five I2C
controller pins: four clocks and one shared data pin. Each SFP or PoE connects to the corresponding
SFP_SERIALCLK0 or PHY[5:7]_LED1 pins (configured as SFP_SERIALCLK[3:0], respectively), and
shares the SFP_SERIALDATA device pin (configured as I2C_SDA), as shown in the following
illustration. For SFP modules, VSC8512-02 can also provide control for the MODULE_DETECT and
TX_DIS module pins using the multipurpose LED/GPIO pins.
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Functional Descriptions
Figure 19 • I2C MUX with SFP Control and Status
SDA
SCL
SFP0
SFP1
SFP2
SFP3
Management
Interface
SDA
SCL
MDC
MDIO
Integrated I2C
Mux
SDA
SCL
I2C_SCL_0
I2C_SCL_1
I2C_SCL_2
I2C_SCL_3
I2C_SDA
SDA
SCL
PHY
4.15.1 Read/Write Access Using the I2C MUX
Using the integrated I2C MUX, the VSC8512-02 device can read and write to an SFP or PoE module
through the SCL and SDA pins. If the ability is required to write to the slave I2C device, refer to the
device’s specific datasheet for more information.
Note: The VSC8512-02 device does not automatically increment the I2C address. Each desired address must
be intentionally set.
Main control of the integrated I2C MUX is available through register 20G. The I2C MUX pins are enabled
or disabled using register 20G bits 3:0. Register 20G bits 15:9 set the I2C device address (the default is
0xA0). Using register 20G bits 5:4, the two-wire serial frequency can be changed from 100 kHz to other
speeds, such as 50 kHz, 100 kHz (the default), 400 kHz, and 2 MHz. Registers 21G and 22G provide
status and control of the read/write process. The following illustration shows the read and write register
flow.
Figure 20 • I2C MUX Read and Write Register Flow
Start
21G.15 = 0
Wait for
Ready
21G.9 = 1
Read Data = 22G.15:8
21G.15 = 1
Read or Write
Read SFP Data
21G.15 = 1
21G.11:10 = PHY port to Write
21G.7:0 = Address to Write
21G.8 = 1
Write
SFP
Data
Wait for
Ready
22G.7:0 = Data to Write
21G.15 = 0
21G.11:10 = PHY port to Read
21G.7:0 = Address to Read
21G.8 = 1
21G.9 = 1
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Functional Descriptions
To read a value from a specific address of the I2C slave device:
1. Read the VSC8512-02 device register 21G bit 15, and ensure that it is set.
2. Write the PHY port address to be read to register 21G bits 11:10.
3. Write the I2C address to be read to register 21G bits 7:0.
4. Set both register 21G bits 8 and 9 to 1.
5. When register 21G bit 15 changes to 1, read the 8-bit data value found at register 22G bits 15:8.
This is the contents of the address just read by the PHY.
To write a value to a specific address of the I2C slave device:
1. Read the VSC8512-02 device register 21G bit 15 and ensure that it is set.
2. Write the PHY port address to be written to register 21G bits 11:10.
3. Write the address to be written to register 21G bits 7:0.
4. Set register 21 bit 8 to 0.
5. Set register 22G bits 7:0 with the 8-bit value to be written to the slave device.
6. Set register 21G bit 9 to 1.
To avoid collisions during read and write transactions on the I2C serial bus, always wait until register 21G
bit 15 changes to 1 before performing another I2C read or write operation.
4.16 GPIO Pins
The VSC8512-02 provides 30 multiplexed multipurpose pins. For more information about the available
GPIO pins, see LED and Multi/General Purpose Input and Output Pins, page 101, and for information
about configuring them, see General Purpose Registers, page 70.
4.17 Testing Features
The VSC8512-02 device includes several testing features designed to facilitate performing system-level
debugging and in-system production testing. This section describes the available features.
4.17.1 Ethernet Packet Generator
The Ethernet packet generator (EPG) can be used at each of the 10/100/1000BASE-T speed settings for
copper Cat5 media and fiber media to isolate problems between the MAC and the VSC8512-02, or
between a locally connected PHY and its remote link partner. Enabling the EPG feature effectively
disables all MAC interface transmit pins and selects the EPG as the source for all data transmitted onto
the twisted pair interface. This feature is not used when the SerDes media is set to pass-through mode.
Important The EPG is intended for use with laboratory or in-system testing equipment only. Do not use
the EPG testing feature when the VSC8512-02 is connected to a live network.
To enable the VSC8512-02 EPG feature, set the device register bit 29E1.15 to 1.
When the EPG is enabled, packet loss occurs during transmission of packets from the MAC to the PHY.
However, the PHY receive output pins to the MAC are still active when the EPG is enabled. If it is
necessary to disable the MAC receive pins as well, set the register bit 0.10 to 1.
When the device register bit 29E1.14 is set to 1, the PHY begins transmitting Ethernet packets based on
the settings in registers 29E1 and 30E1. These registers set:
•
•
•
•
•
•
Source and destination addresses for each packet
Packet size
Inter-packet gap
FCS state
Transmit duration
Payload pattern
If register bit 29E1.13 is set to 0, register bit 29E1.14 is cleared automatically after 30,000,000 packets
are transmitted.
4.17.2 CRC Counters
Two sets of cyclical redundancy check (CRC) counters are available in all PHYs in VSC8512-02 to
monitor traffic on the copper and SerDes interfaces.
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Functional Descriptions
The device CRC counters operate in 100BASE-FX/1000BASE-X over SerDes mode and
10/100/1000BASE-T mode as follows:
•
After receiving a packet on the media interface, register bit 15 in register 18E1 or register 28E3 is set
and cleared after being read.
•
•
The packet then is counted by either the good CRC counter or the bad CRC counter.
Both CRC counters are also automatically cleared when read.
The good CRC counter’s highest value is 9,999 packets. After this value is reached, the counter clears
on the 10,000th packet and continues to count additional packets beyond that value. The bad CRC
counter stops counting when it reaches its maximum counter limit of 255 packets.
4.17.2.1 Copper Interface CRC Counters
Two separate CRC counters are available and reside between the copper interface PCSs and SerDes
MAC interface. There is a 14-bit good CRC counter available through register bits 18E1.13:0 and a
separate 8-bit bad CRC counter available in register bits 23E1.7:0.
4.17.2.2 SerDes Interface CRC Counters
Two separate CRC counters are available and reside between the SerDes media interface PCSs and
SerDes MAC interface. There is a 14-bit good CRC counter available through register bits 28E3.13:0 and
a separate 8-bit bad CRC counter available in register bits 29E3.7:0.
4.17.3 Far-End Loopback
The far-end loopback testing feature is enabled by setting register bit 23.3 to 1. When enabled, it forces
incoming data from a link partner on the current media interface, into the MAC interface of the PHY, to be
retransmitted back to the link partner on the media interface as shown in the following illustration. In
addition, the incoming data also appears on the receive data pins of the MAC interface. Data present on
the transmit data pins of the MAC interface is ignored when using this testing feature.
Figure 21 • Far-End Loopback Diagram
PHY_port_n
RX
RXD
TXD
Link Partner
MAC
TX
Cat5
4.17.4 Near-End Loopback
When the near-end loopback testing feature is enabled, transmitted data (TXD) is looped back in the
PCS block onto the receive data signals (RXD), as shown in the following illustration. When using this
testing feature, no data is transmitted over the network. To enable near-end loopback, set the device
register bit 0.14 to 1.
Figure 22 • Near-End Loopback Diagram
PHY_port_n
RX
RXD
TXD
Link Partner
MAC
TX
Cat5
4.17.5 Connector Loopback
The connector loopback testing feature allows the twisted pair interface to be looped back externally.
When using this feature, the PHY must be connected to a loopback connector or a loopback cable.
Pair A should be connected to pair B, and pair C to pair D, as shown in the following illustration. The
connector loopback feature functions at all available interface speeds.
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Functional Descriptions
Figure 23 • Connector Loopback Diagram
A
B
RXD
TXD
Cat5
PHY_port_n
MAC
C
D
When using the connector loopback testing feature, the device autonegotiation, speed, and duplex
configuration is set using device registers 0, 4, and 9. For 1000BASE-T connector loopback, the
following additional writes are required. Execute the additional writes in the following order:
1. Enable the 1000BASE-T connector loopback. Set register bit 24.0 to 1.
2. Disable pair swap correction. Set register bit 18.5 to 1.
4.17.6 SerDes Loopbacks
For test purposes, the SerDes and enhanced SerDes macro interfaces provide several data loops. The
following illustration shows the SerDes loopbacks.
Figure 24 • Data Loops of the SerDes Macro
n bit IF
n bit IF
SLIVER
Digital interface, configuration, and control logic
including synchronous Ethernet clock tree
D Q
Facility Loop
HS-ref. clock
HS-ref. clock
RC-PLL
DES
SER
n:1
1:n
Equipment-Loop
Input-Loop
OB
Analog Service Modules
IB
(BIAS, clk tree buffers, ESD
protection,
)
Pad-Loop
RX
TX
4.17.6.1 SGMII Mode
When the MAC interface is configured in SGMII mode, write the following 16-bit value to register 18G:
Bits 15:12 0x9
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Functional Descriptions
Bits 11:8: Port address (0x0 to 0xb)
Bits 7:4: Loopback type
Bits 3:0: 0x2
where loopback type is:
0x0: No loopback
0x1: Pad loopback
0x2: Input loopback
0x4: Facility loopback
0x8: Equipment loopback
4.17.6.2 QSGMII Mode
When the MAC interface is configured in QSGMII mode, the configuration command is the same as
SGMII mode, except that the port addresses (bits 11:8) are:
0xC: Enhanced SerDes macro for ports 0–3
0xD: Enhanced SerDes macro for ports 4–7
0xE: Enhanced SerDes macro for ports 8-11
Note: Loopback configuration affects all four ports associated with a QSGMII. Individual port loopback within a
QSGMII is not possible.
4.17.6.3 Fiber Media Port Mode
When the SerDes is configured as a fiber media port, write the following 16-bit value to register 18G:
Bits 15:12: 0x8
Bits 11:8: Port address
Bits 7:4: Loopback type
Bits 3:0: 0x2
where port address is:
0x1: Fiber8 port
0x2: Fiber9 port
0x4: Fiber10 port
0x8: Fiber11 port
Port addresses for fiber media SerDes can be OR’ed together to address multiple ports using a single
command. Bit 18G.15 will be cleared when the internal configuration is complete.
4.17.6.4 Facility Loop
The recovered and de-multiplexer deserializer data output is looped back to the serializer data input and
replaces the data delivered by the digital core. This test loop provides the possibility to test the complete
analog macro data path from outside including input buffer, clock and data recovery, serialization and
output buffer. The data received by the input buffer must be transmitted by the output buffer after some
delay.
Additional configuration of the SerDes and Enhanced SerDes macros is required for facility loopback
mode. When entering facility loopback mode, the set = 1 option should be run; when exiting facility
loopback mode, the set = 0 option should be run.
For SerDes macro configurations, the following software script must be executed after running the
command to enable/disable facility loopback mode.
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PhyWrite(PhyBaseAddr, 31, 0x0010);
PhyWrite(PhyBaseAddr, 18, 0x8s03);
// where "s" is the physical address of the SerDes macro
PhyWrite(PhyBaseAddr, 18, 0xd7d3);
PhyWrite(PhyBaseAddr, 18, 0x8007);
tmp1 = PhyRead(PhyBaseAddr, 18);
tmp2 = tmp1 & 0x0ff0;
if (set)
tmp3 = tmp2 | 0x0010;
else
tmp3 = tmp2 & 0x0fe0;
tmp4 = tmp3 | 0x8006;
PhyWrite(PhyBaseAddr, 18, tmp4);
if (SGMII)
PhyWrite(PhyBaseAddr, 18, 0x9p40);
// where "p" is the logical address of the SGMII interface
else
PhyWrite(PhyBaseAddr, 18, 0x8p40);
// where "p" is the logical address of the Fiber media interface
PhyBaseAddr is the base address of the internal PHYs and is equal to 0, 12, 4, or 20 based on the value
of the PHYADDR4 and PHYADDR3 pins. For more information, see Table 2, page 9.
The value of s is 0–7 and corresponds to the physical address of the SerDes macro. For SerDes SGMII
MAC interface configuration, the value of p is 1, 2, 4, 5, 7, 8, 10, or 11 and is the logical address of the
SGMII lane that corresponds to the SerDes macro with physical address s. For SerDes Fiber Media
interface configuration, the value of p is 8–11 and is the logical address of the Fiber Media lane that
corresponds to the SerDes macro with physical address s. For more information about address mapping,
see Table 4, page 10.
For Enhanced SerDes macro configurations, the following software script must be executed after running
the command to enable/disable facility loopback mode.
PhyWrite(PhyBaseAddr, 31, 0x0010);
PhyWrite(PhyBaseAddr, 18, 0x8s13);
// where "s" is the physical address of the SerDes macro
PhyWrite(PhyBaseAddr, 18, 0xd7d3);
PhyWrite(PhyBaseAddr, 18, 0x8007);
tmp1 = PhyRead(PhyBaseAddr, 18);
tmp2 = tmp1 & 0x0ff0;
if (set)
tmp3 = tmp2 | 0x0100;
else
tmp3 = tmp2 & 0x0ef0;
tmp4 = tmp3 | 0x8006;
PhyWrite(PhyBaseAddr, 18, tmp4);
PhyWrite(PhyBaseAddr, 18, 0x9p40);
// where "p" is the logical address of the SGMII or QSGMII interface
PhyBaseAddr is the base address of the internal PHYs and is equal to 0, 12, 4, or 20 based on the value
of the PHYADD4 and PHYADD3 pins. For more information, see Table 2, page 9.
The value of s is 0–3 and corresponds to the physical address of the enhanced SerDes macro. For
enhanced SerDes SGMII MAC interface configuration, the value of p is 0, 3, 6, or 9 and is the logical
address of the SGMII lane that corresponds to the enhanced SerDes macro with physical address s. For
enhanced SerDes QSGMII MAC interface configuration, the value of p is 0–2 and is the logical address
of the QSGMII lane that corresponds to the enhanced SerDes macro with physical address s. For more
information about address mapping, see Table 4, page 10.
4.17.6.4.1 Equipment Loop
The 1-bit data stream at the serializer output is looped back to the deserializer and replaces the received
data stream from the input buffer. This test loop provides the possibility to verify the digital data path
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Functional Descriptions
internally. The transmit data goes through the serialization, the clock and data recovery and
deserialization before the data is fed back to the digital core.
4.17.6.4.2 Input Loop
The received 1-bit data stream of the input buffer is looped back asynchronously to the output buffer. This
test loop provides the possibility to the test only the analog parts of the SGMII interface because only the
input and output buffer are part of this loop.
4.17.6.4.3 Pad Loop
The 1-bit data stream at the output buffer output is looped back to the input buffer input and added to the
differential pad signal. Therefore, the input pad should not be driven when the output loop is activated.
The test loop provides a means to test the complete SGMII macro data path, including the input and
output buffers.
4.17.7 VeriPHY Cable Diagnostics
The VSC8512-02 includes a comprehensive suite of cable diagnostic functions that are available using
SMI reads and writes. These functions enable a variety of cable operating conditions and status to be
accessed and checked. The VeriPHY suite has the ability to identify the cable length and operating
conditions and to isolate a variety of common faults that can occur on the Cat5 twisted pair cabling.
Note: If a link is established on the twisted pair interface in the 1000BASE-T mode, VeriPHY can run without
disrupting the link or disrupting any data transfer. However, if a link is established in 100BASE-TX or
10BASE-T, VeriPHY causes the link to drop while the diagnostics are running. After diagnostics are
finished, the link is re-established.
The following diagnostic functions are part of the VeriPHY suite:
•
•
•
Detecting coupling between cable pairs
Detecting cable pair termination
Determining cable length
4.17.7.1 Coupling Between Cable Pairs
Shorted wires, improper termination, or high crosstalk resulting from an incorrect wire map can cause
error conditions, such as anomalous coupling between cable pairs. These conditions can prevent the
device from establishing a link in any speed.
4.17.7.2 Cable Pair Termination
Proper termination of Cat5 cable requires a 100 Ω differential impedance between the positive and
negative cable terminals. IEEE 802.3 allows for a termination of 115 Ω maximum and 85 Ω minimum. If
the termination falls outside of this range, it is reported by the VeriPHY diagnostics as an anomalous
termination. The diagnostics can also determine the presence of an open or shorted cable pair.
4.17.7.3 Cable Length
When the Cat5 cable in an installation is properly terminated, VeriPHY reports the approximate cable
length in meters.
4.17.7.4 Mean Square Error Noise
The average absolute error can be read out when either a 100BASE-TX or 1000BASE-T link is
established. In the case of 1000BASE-T link, there are four average absolute error terms, one for each
twisted-pair over which signal is received. Use the following script to read average absolute error for
100BASE-TX:
PhyWrite( <phy>, 31, 0x52b5 );
PhyWrite( <phy>, 16, 0xa3c0 );
PhyRead( <phy>, 16 );
tmp17 = PhyRead( <phy>, 17 );
tmp18 = PhyRead( <phy>, 18 );
mse = (tmp18 << 4) | (tmp17 >> 12);
PhyWrite( <phy>, 31, 0 );
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Functional Descriptions
The returned average absolute error is in units of 1/2048 and can be found in the mse variable.
PhyWrite( <phy>, 31, 0x52b5 );
PhyWrite( <phy>, 16, 0xa3c0 );
PhyRead( <phy>, 16 );
tmp17 = PhyRead( <phy>, 17 );
tmp18 = PhyRead( <phy>, 18 );
mseA = (tmp18 << 4) | (tmp17 >> 12);
mseB = tmp17 & 0x0fff;
PhyWrite( <phy>, 16, 0xa3c2 );
PhyRead( <phy>, 16 );
tmp17 = PhyRead( <phy>, 17 );
tmp18 = PhyRead( <phy>, 18 );
mseC = (tmp18 << 4) | (tmp17 >> 12);
mseD = tmp17 & 0x0fff;
PhyWrite( <phy>, 31, 0 );
The returned average absolute error is in units of 1/2048 and can be found in the mseA, mseB, mseC,
and mseD variables for each twisted pair.
4.17.8 JTAG Boundary Scan
The VSC8512-02 supports the test access port (TAP) and boundary scan architecture described in
IEEE 1149.1. The device includes an IEEE 1149.1-compliant test interface, referred to as a JTAG TAP
interface.
The JTAG boundary scan logic on the VSC8512-02, accessed using its TAP interface, consists of a
boundary scan register and other logic control blocks. The TAP controller includes all IEEE-required
signals (TMS, TCK, TDI, and TDO), in addition to the optional asynchronous reset signal NTRST. The
following illustration shows the TAP and boundary scan architecture.
Figure 25 • Test Access Port and Boundary Scan Architecture
Boundary Scan
Register
Device Identification
Register
Bypass Register
TDO
MUX,
DFF
Control
Instruction Register,
Instruction Decode
Control
TDI
TMS
Control
Select
Test Access Port
Controller
NTRST
TCK
TDO Enable
After a TAP reset, the device identification register is serially connected between TDI and TDO by
default. The TAP instruction register is loaded either from a shift register when a new instruction is shifted
in, or, if there is no new instruction in the shift register, a default value of 6’b100100 (IDCODE) is loaded.
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Functional Descriptions
Using this method, there is always a valid code in the instruction register, and the problem of toggling
instruction bits during a shift is avoided. Unused codes are mapped to the BYPASS instruction.
4.17.9 JTAG Instruction Codes
The VSC8512-02 supports the following instruction codes:
4.17.9.1 EXTEST
Allows tests of the off-chip circuitry and board-level interconnections by sampling input pins and loading
data onto output pins. Outputs are driven by the contents of the boundary-scan cells, which have to be
updated with valid values, with the PRELOAD instruction, prior to the EXTEST instruction.
4.17.9.2 SAMPLE/PRELOAD
Allows a snapshot of inputs and outputs during normal system operation to be taken and examined. It
also allows data values to be loaded into the boundary-scan cells prior to the selection of other boundary-
scan test instructions.
4.17.9.3 IDCODE
Provides the version number (bits 31:28), device family ID (bits 27:12), and the manufacturer identity
(bits 11:1) to be serially read from the device.
The following table provides information about the meaning of IDCODE binary values stored in the
device JTAG registers.
Table 11 • IDCODE JTAG Device Identification Register Descriptions
Description Device Version Family ID
Bit field 31–28 27–12
Manufacturing Identity
LSB
11–1
0
1
Binary value 0000
1011 0000 0000 0001 000 0111 0100
4.17.9.4 USERCODE
Provides the version number (bits 31:28), part number (bits 27:12), and the manufacturer identity
(bits 11:1) to be serially read from the device. The following table provides information about the meaning
of USERCODE binary values stored in the device JTAG registers.
Table 12 • USERCODE JTAG Device Identification Register Descriptions
Description Device Version Model Number
Bit field 31–28 27–12
Binary value 0010
Manufacturing Identity
LSB
11–1
0
1
1000 0101 0001 0010 000 0111 0100
4.17.9.5 CLAMP
Allows the state of the signals driven from the component pins to be determined from the boundary scan
register while the bypass register is selected as the serial path between TDI and TDO. While the CLAMP
instruction is selected, the signals driven from the component pins do not change.
4.17.9.6 HIGHZ
Places the component in a state in which all of its system logic outputs are placed in a high-impedance
state. In this state, an in-circuit test system can drive signals onto the connections normally driven by a
component output without incurring a risk of damage to the component. This makes it possible to use a
board where not all of the components are compatible with the IEEE 1149.1 standard.
4.17.9.7 BYPASS
The bypass register contains a single shift-register stage and is used to provide a minimum-length serial
path (one TCK clock period) between TDI and TDO to bypass the device when no test operation is
required.
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Functional Descriptions
The following table provides information about the location and IEEE compliance of the JTAG instruction
codes used in the VSC8512-02. Instructions not explicitly listed in the table are reserved. For more
information about these IEEE specifications, visit the IEEE Web site at www.IEEE.org.
Table 13 • JTAG Interface Instruction Codes
Register
Instruction
Code
Selected Register
Width
IEEE 1149.1 IEEE 1149.6
Mandatory
EXTEST
6'b000000 Boundary-Scan
161
SAMPLE/PREL 6'b000001 Boundary-Scan
OAD
161
Mandatory
IDCODE
USERCODE
CLAMP
6'b100100 Device Identification
6'b100101 Device Identification
6'b000010 Bypass Register
6'b000101 Bypass Register
6'b111111 Bypass Register
32
32
1
Optional
Optional
Optional
Optional
Mandatory
Mandatory
HIGHZ
1
BYPASS
1
EXTEST_PULS 6'b000011 Boundary-Scan Register 161
E
EXTEST_TRAI 6'b000100 Boundary-Scan Register 161
N
Mandatory
4.17.10 Boundary Scan Register Cell Order
All inputs and outputs are observed in the boundary scan register cells. All outputs are additionally driven
by the contents of boundary scan register cells. Bidirectional pins have all three related boundary scan
register cells: input, output, and control.
The complete boundary scan cell order is available as a BSDL file format on the Microsemi Web site at
www.microsemi.com.
4.17.11 JTAG Boundary Scan Interface
The IEEE 1149.6 AC-JTAG solution integrated on all SerDes ports of the VSC8512-02 extends the
capability of IEEE 1149.1 boundary scan for robust board-level testing. This interface is backward-
compatible to the IEEE 1149.1 standard.
4.18 100FX Halt Code Transmission and Reception
The VSC8512-02 device supports transmission and reception of halt code words in 100BASE-FX mode.
There are three separate scripts provided to initiate transmission of halt code words, stop transmission of
halt code words and detect reception of halt code words. Use the following scripts to implement each of
these functions:
Sending the HALT codeword:
PhyWrite( <phy>, 31, 0x52b5 );
PhyWrite( <phy>, 16, 0xac82 );
reg18 = PhyRead( <phy>, 18 );
reg18 = (reg18 & 0xf0) | 0x0c;
PhyWrite( <phy>, 18, reg18 );
PhyWrite( <phy>, 17, 0xe739 );
PhyWrite( <phy>, 16, 0x8c82 );
PhyWrite< <phy>, 16, 0xbe80 );
reg17 = PhyRead( <phy>, 17 );
reg18 = PhyRead( <phy>, 18 );
reg17 = reg17 | 0x0040;
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Functional Descriptions
PhyWrite( <phy>, 18, reg18 );
PhyWrite( <phy>, 17, reg17 );
PhyWrite( <phy>, 16, 0x9e80 );
PhyWrite( <phy>, 31, 0 );
Stop sending the HALT codeword:
PhyWrite( <phy>, 31, 0x52b5 );
PhyWrite< <phy>, 16, 0xbe80 );
reg17 = PhyRead( <phy>, 17 );
reg18 = PhyRead( <phy>, 18 );
reg17 = reg17 & ~0x0040;
PhyWrite( <phy>, 18, reg18 );
PhyWrite( <phy>, 17, reg17 );
PhyWrite( <phy>, 16, 0x9e80 );
PhyWrite( <phy>, 31, 0 );
Detecting if the HALT codeword is being sent by the link partner:
long patternset[5] = {
0xce739,
0xe739c,
0x739ce,
0x39ce7,
0x9ce73
};
Turning on the pattern checker:
PhyWrite( <phy>, 31, 0x52b5 );
PhyWrite( <phy>, 16, 0xbe80 );
reg18 = PhyRead( <phy>, 18 );
reg17 = PhyRead( <phy>, 17 );
reg17 = reg17 | 4;
PhyWrite( <phy>, 18, reg18 );
PhyWrite( <phy>, 17, reg17 );
PhyWrite( <phy>, 16, 0x9e80 );
Sweeping through all 5 pattern shifts looking for a match:
for (i = 0, matchfailed = 1; i < 5 && matchfailed; ++i) {
PhyWrite( <phy>, 16, 0xac84 );
reg18 = PhyRead( <phy>, 18 );
reg18 = (reg18 & 0xf0) | (patternset[i] >> 16)
PhyWrite( <phy>, 18, reg18 );
PhyWrite( <phy>, 17, patternset[i] & 0xffff );
PhyWrite( <phy>, 16, 0x8c84 );
PhyWrite( <phy>, 16, 0xbe84 ); // Dummy read to clear latched mismatch
PhyWrite( <phy>, 16, 0xbe84 ); // Read pattern check failure status
matchfailed = PhyRead( <phy>, 17 ) & 1; // Extract pattern check failure status
}
Turning off the pattern checker:
PhyWrite( <phy>, 16, 0xbe80 );
reg18 = PhyRead( <phy>, 18 );
reg17 = PhyRead( <phy>, 17 );
reg17 = reg17 & ~4;
PhyWrite( <phy>, 18, reg18 );
PhyWrite( <phy>, 17, reg17 );
PhyWrite( <phy>, 16, 0x9e80 );
PhyWrite( <phy>, 31, 0 );
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Functional Descriptions
HALT_codeword_detected = !matchfailed;
4.19 Configuration
The VSC8512-02 can be configured by setting internal memory registers using the management
interface.
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Registers
5
Registers
This section provides information about how to configure the VSC8512-02 using its internal memory
registers and the management interface.
The VSC8512-02 uses several different types of registers:
•
•
•
•
IEEE Clause 22 device registers with addresses from 0 to 31
Three pages of extended registers with addresses from 16E1–30E1, 16E2–30E2, and 16E3–30E3
General-purpose registers with addresses from 0G to 30G
IEEE Clause 45 devices registers accessible through the Clause 22 registers 13 and 14 to support
IEEE 802.3az Energy Efficient Ethernet registers
The following illustration shows the relationship between the device registers and their address spaces.
Figure 26 • Register Space Diagram
0
1
2
3
.
0G
1G
2G
3G
.
.
.
Clause 45
Registers
IEEE 802.3
Standard
.
Registers
.
13
14
15
.
.
15G
General Purpose
Registers
16
17
18
19
.
.
.
16E1
17E1
18E1
19E1
.
.
.
16E2
17E2
18E2
19E2
.
.
.
16E3
17E3
18E3
19E3
.
.
.
16G
17G
18G
19G
.
.
.
Extended
Registers 1
Extended
Registers 2
Extended
Registers 3
Main Registers
.
.
.
.
.
.
.
.
.
.
30
30E1
30E2
30E3
30G
31
0x0000
0x0010
0x0001
0x0002
0x0003
•
•
Reserved Registers—For main registers 16–31, extended registers 16E1–30E1, 16E2–30E2,
16E3–30E3, and general purpose registers 0G–30G, any bits marked as Reserved should be
processed as read-only and their states as undefined.
Reserved Bits—In writing to registers with reserved bits, use a read-modify-then-write technique,
where the entire register is read but only the intended bits to be changed are modified. Reserved bits
cannot be changed and their read state cannot be considered static or unchanging.
5.1
IEEE Standard and Main Registers
In the VSC8512-02, the page space of the standard registers consists of the IEEE standard registers and
the Microsemi standard registers. The following table lists the names of the registers associated with the
addresses as dictated by the IEEE standard.
Table 14 • IEEE 802.3 Standard Registers
Address Name
0
1
2
3
4
5
6
Mode Control
Mode Status
PHY Identifier 1
PHY Identifier 2
Autonegotiation Advertisement
Autonegotiation Link Partner Ability
Autonegotiation Expansion
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Registers
Table 14 • IEEE 802.3 Standard Registers (continued)
Address Name
7
Autonegotiation Next-Page Transmit
Autonegotiation Link Partner Next-Page Receive
1000BASE-T Control
8
9
10
1000BASE-T Status
11–12
13
Reserved
Clause 45 access registers from IEEE 802.3
Table 22-6 and 22.24.3.11-12 and Annex 22D
14
15
Clause 45 access registers from IEEE 802.3
Table 22-6 and 22.24.3.11-12 and Annex 22D
1000BASE-T Status Extension 1
The following table lists the names of the registers in the main page space of the device. These registers
are accessible only when register address 31 is set to 0x0000.
Table 15 • Main Registers
Address Name
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
100BASE-TX Status Extension 1
1000BASE-T Status Extension 2
Bypass Control
Error Counter 1
Error Counter 2
Error Counter 3
Extended Control and Status
Extended PHY Control 1
Extended PHY Control 2
Interrupt Mask
Interrupt Status
Reserved
Auxiliary Control and Status
LED Mode Select
LED Behavior
Extended Register Page Access
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Registers
5.1.1
Mode Control
The device register at memory address 0 controls several aspects of VSC8512-02 functionality. The
following table shows the available bit settings in this register and what they control.
Table 16 • Mode Control, Address 0 (0x00)
Bit
Name
Access Description
R/W Self-clearing. Restores all serial
Default
15
Software reset
0
management interface (SMI) registers to
default state, except for sticky and
super-sticky bits.
1: Reset asserted.
0: Reset de-asserted. Wait [X] after setting
this bit to initiate another SMI register
access.
14
Loopback
R/W
1: Loopback enabled.
0: Loopback disabled.
When loop back is enabled, the device
functions at the current speed setting and
with the current duplex mode setting (bits 6,
8, and 13 of this register).
0
0
13
12
Forced speed selection R/W
LSB
Least significant bit. MSB is bit 6.
00: 10 Mbps.
01: 100 Mbps.
10: 1000 Mbps.
11: Reserved.
Autonegotiation enable R/W
1: Autonegotiation enabled.
0: Autonegotiation disabled.
1
0
11
10
Power-down
Isolate
R/W
R/W
1: Power-down enabled.
1: Disable MAC interface outputs and ignore 0
MAC interface inputs.
9
8
Restart autonegotiation R/W
Self-clearing bit.
1: Restart autonegotiation on media
interface.
0
Duplex
R/W
R/W
1: Full-duplex.
0: Half-duplex.
0
7
6
Collision test enable
1: Collision test enabled.
0
Forced speed selection R/W
MSB
Most significant bit. LSB is bit 13.
00: 10 Mbps.
10
01: 100 Mbps.
10: 1000 Mbps.
11: Reserved.
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Table 16 • Mode Control, Address 0 (0x00) (continued)
Bit
Name
Access Description
R/W When bit 0.12 = 1 or bit 0.8 = 0, this bit is
Default
5
Unidirectional enable
0
ignored. When bit 0.12 = 0 and bit 0.8 = 1,
the behavior is as follows:
1: Enable transmit from media independent
interface regardless of whether the PHY has
determined that a valid link has been
established.
0: Enable transmit from media independent
interface only when the PHY has determined
that a valid link has been established
Note: This bit is only applicable in
100BASE-FX and
1000BASE-X fiber media
modes for ports 8-11.
4:0
Reserved
RO
Reserved.
00000
5.1.2
Mode Status
The register at address 1 in the device main registers space allows you to read the currently enabled
mode setting. The following table shows possible readouts of this register.
Table 17 • Mode Status, Address 1 (0x01)
Bit Name
Access Description
Default
15 100BASE-T4 capability
RO
1: 100BASE-T4 capable.
0
1
1
1
1
0
0
1
14 100BASE-TX FDX capability RO
13 100BASE-TX HDX capability RO
1: 100BASE-TX FDX capable.
1: 100BASE-TX HDX capable.
1: 10BASE-T FDX capable.
1: 10BASE-T HDX capable.
1: 100BASE-T2 FDX capable.
1: 100BASE-T2 HDX capable.
12 10BASE-T FDX capability
11 10BASE-T HDX capability
RO
RO
10 100BASE-T2 FDX capability RO
9
8
100BASE-T2 HDX capability RO
Extended status enable
RO
1: Extended status information present in
register 15.
7
Unidirectional ability
RO
1: PHY able to transmit from media
independent interface regardless of
whether the PHY has determined that a
valid link has been established.
0: PHY able to transmit from media
independent interface only when the PHY
has determined that a valid link has been
established.
1
Note: This bit is only applicable to
100BASE-FX and
1000BASE-X fiber media
modes.
6
5
Preamble suppression
capability
RO
RO
1: MF preamble can be suppressed.
0: MF required.
1
0
Autonegotiation complete
1: Autonegotiation complete.
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Registers
Table 17 • Mode Status, Address 1 (0x01) (continued)
Bit Name
Remote fault
Access Description
Default
4
RO
Latches high.
0
1: Far-end fault detected.
3
2
Autonegotiation capability
Link status
RO
RO
1: Autonegotiation capable.
1
0
Latches low.
1: Link is up.
1
0
Jabber detect
RO
RO
Latches high.
1: Jabber condition detected.
0
1
Extended capability
1: Extended register capable.
5.1.3
Device Identification
All 16 bits in both register 2 and register 3 in the VSC8512-02 are used to provide information associated
with aspects of the device identification. The following tables list the expected readouts.
Table 18 • Identifier 1, Address 2 (0x02)
Bit Name
Access Description
RO OUI most significant bits (3:18)
Default
15:0 Organizationally unique identifier
(OUI)
0×0007
Table 19 • Identifier 2, Address 3 (0x03)
Bit
Name
Access Description
Default
15:10 OUI
RO
RO
OUI least significant bits (19:24)
VSC8512-02 (0x2e)
000001
101110
9:4
3:0
Microsemi model
number
Device revision number RO
0011
5.1.4
Autonegotiation Advertisement
The bits in address 4 in the main registers space control the VSC8512-02 ability to notify other devices of
the status of its autonegotiation feature. The following table shows the available settings and readouts.
Table 20 • Device Autonegotiation Advertisement, Address 4 (0x04)
Bit Name
Access Description
Default
15 Next page transmission request R/W
1: Request enabled
0
0
0
0
0
0
0
1
1
1
1
14 Reserved
RO
Reserved
13 Transmit remote fault
12 Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1: Enabled
Reserved
11 Advertise asymmetric pause
10 Advertise symmetric pause
1: Advertises asymmetric pause
1: Advertises symmetric pause
1: Advertises 100BASE-T4
1: Advertise 100BASE-TX FDX
1: Advertises 100BASE-TX HDX
1: Advertises 10BASE-T FDX
1: Advertises 10BASE-T HDX
9
8
7
6
5
Advertise100BASE-T4
Advertise100BASE-TX FDX
Advertise100BASE-TX HDX
Advertise10BASE-T FDX
Advertise10BASE-T HDX
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Registers
Table 20 • Device Autonegotiation Advertisement, Address 4 (0x04) (continued)
Bit Name
Access Description
Default
4:0 Advertise selector
R/W
00001
5.1.5
Link Partner Autonegotiation Capability
The bits in main register 5 can be used to determine if the Cat5 link partner (LP) used with the
VSC8512-02 is compatible with the autonegotiation functionality.
Table 21 • Autonegotiation Link Partner Ability, Address 5 (0x05)
Bit Name
Access Description
Default
15 LP next page transmission request RO
1: Requested
0
14 LP acknowledge
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
1: Acknowledge
0
13 LP remote fault
1: Remote fault
0
12 Reserved
Reserved
0
11 LP advertise asymmetric pause
10 LP advertise symmetric pause
1: Capable of asymmetric pause
1: Capable of symmetric pause
1: Capable of 100BASE-T4
1: Capable of 100BASE-TX FDX
1: Capable of 100BASE-TX HDX
1: Capable of 10BASE-T FDX
1: Capable of 10BASE-T HDX
0
0
9
8
7
6
5
LP advertise 100BASE-T4
0
LP advertise 100BASE-TX FDX
LP advertise 100BASE-TX HDX
LP advertise 10BASE-T FDX
LP advertise 10BASE-T HDX
0
0
0
0
4:0 LP advertise selector
00000
5.1.6
Autonegotiation Expansion
The bits in main register 6 work together with those in register 5 to indicate the status of the LP
autonegotiation functioning. The following table shows the available settings and readouts.
Table 22 • Autonegotiation Expansion, Address 6 (0x06)
Bit
Name
Access Description
Default
All zeros
0
15:5 Reserved
RO
RO
Reserved.
4
Parallel detection fault
LP next page capable
This bit latches high.
1: Parallel detection fault.
3
2
1
RO
1: LP is next page capable.
0
1
0
Local PHY next page capable RO
Page received RO
1: Local PHY is next page capable.
This bit latches low.
1: New page is received.
0
LP is autonegotiation capable RO
1: LP is capable of autonegotiation.
0
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Registers
5.1.7
Transmit Autonegotiation Next Page
The settings in register 7 in the main registers space provide information about the number of pages in
an autonegotiation sequence. The following table shows the settings available.
Table 23 • Autonegotiation Next Page Transmit, Address 7 (0x07)
Bit
15
14
13
Name
Access Description
Default
Next page
Reserved
Message page
R/W
RO
1: More pages follow
0
0
1
Reserved
R/W
1: Message page
0: Unformatted page
12
11
Acknowledge 2
Toggle
R/W
RO
1: Complies with request
0: Cannot comply with request
0
1: Previous transmitted LCW = 0
0: Previous transmitted LCW = 1
0
10:0 Message/unformatted code R/W
00000000001
5.1.8
Autonegotiation Link Partner Next Page Receive
The bits in register 8 of the main register space work together with register 7 to determine certain aspects
of the LP autonegotiation. The following table shows the possible readouts.
Table 24 • Autonegotiation LP Next Page Receive, Address 8 (0x08)
Bit
15
14
13
Name
Access Description
Default
LP next page
Acknowledge
LP message page
RO
RO
RO
1: More pages follow
0
0
0
1: LP acknowledge
1: Message page
0: Unformatted page
12
11
LP acknowledge 2
LP toggle
RO
RO
1: LP complies with request
0
0
1: Previous transmitted LCW = 0
0: Previous transmitted LCW = 1
10:0 LP message/unformatted code RO
All zeros
5.1.9
1000BASE-T Control
The VSC8512-02’s 1000BASE-T functionality is controlled by the bits in register 9 of the main register
space. The following table shows the settings and readouts available.
Table 25 • 1000BASE-T Control, Address 9 (0x09)
Bit
Name
Access Description
Default
15:13 Transmitter test
mode
R/W
000: Normal.
000
001: Mode 1: Transmit waveform test.
010: Mode 2: Transmit jitter test as master.
011: Mode 3: Transmit jitter test as slave.
100: Mode 4: Transmitter distortion test.
101–111: Reserved
12
Master/slavemanual R/W
configuration
1: Master/slave manual configuration enabled.
0
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Registers
Table 25 • 1000BASE-T Control, Address 9 (0x09) (continued)
Bit
Name
Access Description
Default
11
Master/slave value R/W
This register is only valid when bit 9.12 is set to
1.
0
1: Configure PHY as master during negotiation.
0: Configure PHY as slave during negotiation.
10
9
Port type
R/W
R/W
1: Multi-port device.
0: Single-port device.
1
1000BASE-T FDX
capability
1: PHY is 1000BASE-T FDX capable.
1: PHY is 1000BASE-T HDX capable.
Reserved.
1
8
1000BASE-T HDX R/W
capability
1
7:0
Reserved
R/W
0x00
Note: Transmitter test mode (bits 15:13) operates in the manner described in IEEE 802.3 section 40.6.1.1.2.
When using any of the transmitter test modes, the automatic media-sense feature must be disabled. For
more information, see Extended PHY Control 2, page 51.
5.1.10 1000BASE-T Status
The bits in register 10 of the main register space can be read to obtain the status of the 1000BASE-T
communications enabled in the device. The following table shows the readouts.
Table 26 • 1000BASE-T Status, Address 10 (0x0A)
Bit Name
Access Description
Default
15 Master/slave
RO
RO
This bit latches high.
1: Master/slave configuration fault detected.
0: No master/slave configuration fault detected.
0
configuration fault
14 Master/slave
configuration
resolution
1: Local PHY configuration resolved to master.
0: Local PHY configuration resolved to slave.
1
13 Local receiver status RO
1: Local receiver is operating normally.
1: Remote receiver OK.
0
0
12 Remote receiver
status
RO
RO
RO
11 LP 1000BASE-T
FDX capability
1: LP 1000BASE-T FDX capable.
1: LP 1000BASE-T HDX capable.
0
0
10 LP 1000BASE-T
HDX capability
9:8 Reserved
RO
RO
Reserved.
00
7:0 Idle error count
Self-clearing register.
0x00
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Registers
5.1.11 MMD Access Control Register
The bits in register 13 of the main register space are a window to the EEE registers as defined in
IEEE 802.3az Clause 45.
Table 27 • MMD EEE Access, Address 13 (0x0D)
Bit
Name
Access Description
15:14 Function R/W
00: Address
01: Data, no post increment
10: Data, post increment for read and write
11: Data, post increment for write only
13:5
4:0
Reserved R/W
DVAD R/W
Reserved
Device address as defined in IEEE 802.3az table 45-1
5.1.12 MMD Address or Data Register
The bits in register 14 of the main register space are a window to the EEE registers as defined in
IEEE 802.3az Clause 45.
Table 28 • MMD Address or Data Register, Address 14 (0x0E)
Bit
Name
Access Description
15:0 Register Address/Data R/W
If register 13.15:14 = 2'b00, address of register of the
device that is specified by 13.4:0. Otherwise, the data to
be written to or read from the register.
5.1.13 1000BASE-T Status Extension 1
Register 15 provides additional information about the operation of the device 1000BASE-T
communications. The following table shows the readouts available.
Table 29 • 1000BASE-T Status Extension 1, Address 15 (0x0F)
Bit
15
14
13
12
Name
Access Description
Default
1000BASE-X FDX capability RO
1000BASE-X HDX capability RO
1000BASE-T FDX capability RO
1000BASE-T HDX capability RO
1: PHY is 1000BASE-X FDX capable
1: PHY is 1000BASE-X HDX capable
1: PHY is 1000BASE-T FDX capable
1: PHY is 1000BASE-T HDX capable
Reserved
0
0
1
1
11:0 Reserved
RO
0x000
5.1.14 100BASE-TX Status Extension
Register 16 in the main registers page space of the VSC8512-02 provides additional information about
the status of the device’s 100BASE-TX operation.
Table 30 • 100BASE-TX Status Extension, Address 16 (0x10)
Bit Name
Access Description
Default
15 100BASE-TX Descrambler
14 100BASE-TX lock error
RO
RO
1: Descrambler locked.
0
0
Self-clearing bit.
1: Lock error detected.
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Registers
Table 30 • 100BASE-TX Status Extension, Address 16 (0x10) (continued)
Bit Name
Access Description
Default
13 100BASE-TX disconnect state
RO
Self-clearing bit.
0
1: PHY 100BASE-TX link disconnect
detected.
12 100BASE-TX current link status RO
1: PHY 100BASE-TX link active.
0
0
11 100BASE-TX receive error
RO
RO
RO
Self-clearing bit.
1: Receive error detected.
10 100BASE-TX transmit error
Self-clearing bit.
1: Transmit error detected.
0
0
9
8
100BASE-TX SSD error
100BASE-TX ESD error
Self-clearing bit.
1: Start-of-stream delimiter error
detected.
RO
RO
Self-clearing bit.
1: End-of-stream delimiter error
detected.
0
7:0 Reserved
Reserved
5.1.15 1000BASE-T Status Extension 2
The second status extension register is at address 17 in the device main registers space. It provides
information about another set of parameters associated with 1000BASE-T communications. For
information about the first status extension register, see Table 29, page 46.
Table 31 • 1000BASE-T Status Extension 2, Address 17 (0x11)
Bit Name
Access Description
Default
15 1000BASE-T descrambler
14 1000BASE-T lock error
RO
RO
1: Descrambler locked.
0
0
Self-clearing bit.
1: Lock error detected.
13 1000BASE-T disconnect state
RO
Self-clearing bit.
0
1: PHY 1000BASE-T link disconnect
detected.
12 1000BASE-T current link status RO
1: PHY 1000BASE-T link active.
0
0
11 1000BASE-T receive error
RO
RO
RO
Self-clearing bit.
1: Receive error detected.
10 1000BASE-T transmit error
Self-clearing bit.
1: Transmit error detected.
0
0
9
8
1000BASE-T SSD error
1000BASE-T ESD error
Self-clearing bit.
1: Start-of-stream delimiter error
detected.
RO
Self-clearing bit.
0
1: End-of-stream delimiter error
detected.
7
6
5
1000BASE-T carrier extension
error
RO
RO
RO
Self-clearing bit.
1: Carrier extension error detected.
0
0
0
Non-compliant BCM5400
detected
1: Non-compliant BCM5400 link
partner detected.
MDI crossover error
1: MDI crossover error was detected.
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Registers
Table 31 • 1000BASE-T Status Extension 2, Address 17 (0x11) (continued)
Bit Name
Access Description
RO Reserved
Default
4:0 Reserved
5.1.16 Bypass Control
The bits in this register control aspects of functionality in effect when the device is disabled for the
purpose of traffic bypass. The following table shows the settings available.
Table 32 • Bypass Control, Address 18 (0x12)
Bit Name
Access Description
Default
15 Transmit disable
14 4B5B encoder/decoder
13 Scrambler
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
1: PHY transmitter disabled.
0
0
0
0
0
0
0
1: Bypass 4B/5B encoder/decoder.
1: Bypass scrambler.
12 De-scrambler
11 PCS receive
10 PCS transmit
1: Bypass de-scrambler.
1: Bypass PCS receiver.
1: Bypass PSC transmit.
1: Bypass Link Fail Inhibit (LFI) timer.
Reserved.
9
8
7
LFI timer
Reserved
HP Auto-MDIX at forced
10/100
R/W
Sticky bit.
1
0
0
1: Disable HP Auto-MDIX at forced 10/100
speeds.
6
5
Non-compliant BCM5400 R/W
detect disable
Sticky bit.
1: Disable non-compliant BCM5400
detection.
Disable pair swap
correction (HP Auto-MDIX
when autonegotiation
enabled)
R/W
Sticky bit.
1: Disable the automatic pair swap correction.
4
3
Disable polarity correction R/W
Sticky bit.
0
1
1: Disable polarity inversion correction on
each subchannel.
Parallel detect control
R/W
Sticky bit.
1: Do not ignore advertised ability.
0: Ignore advertised ability.
2
1
Pulse shaping filter
R/W
R/W
1: Disable pulse shaping filter
0
0
Disable automatic
1000BASE-T next page
exchange
Sticky bit.
1: Disable automatic 1000BASE-T next page
exchanges.
0
Reserved
RO
Reserved.
Note: If bit 18.1 is set to 1 in this register, automatic exchange of next pages is disabled, and control is returned
to the user through the SMI after the base page is exchanged. The user then must send the correct
sequence of next pages to the link partner, determine the common capabilities, and force the device into
the correct configuration following the successful exchange of pages.
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Registers
5.1.17 Error Counter 1
The bits in register 19 provide an error counter. The following table shows the settings available.
Table 33 • Extended Control and Status, Address 19 (0x13)
Bit
15:8 Reserved
7:0 100/1000BASE-TX
receive error counter
Name
Access Description
Default
RO
RO
Reserved.
8-bit counter that saturates when it reaches
255. These bits are self-clearing when read.
0x00
5.1.18 Error Counter 2
The bits in register 20 provide an error counter. The following table shows the settings available.
Table 34 • Extended Control and Status, Address 20 (0x14)
Bit
15:8 Reserved
7:0 100/1000BASE-TX
false carrier counter
Name
Access Description
Default
RO
RO
Reserved.
8-bit counter that saturates when it reaches
255. These bits are self-clearing when read.
0x00
5.1.19 Error Counter 3
The bits in register 21 provide an error counter. The following table shows the settings available.
Table 35 • Extended Control and Status, Address 21 (0x15)
Bit
15:8 Reserved
7:0 Copper media link
disconnect counter
Name
Access Description
Default
RO
RO
Reserved.
8-bit counter that saturates when it reaches 255. 0x00
These bits are self-clearing when read.
5.1.20 Extended Control and Status
The bits in register 22 provide additional device control and readouts. The following table shows the
settings available.
Table 36 • Extended Control and Status, Address 22 (0x16)
Bit
Name
Access Description
Default
15
Force 10BASE-T link high R/W
Sticky bit.
0
1: Bypass link integrity test.
0: Enable link integrity test.
14
13
12
Jabber detect disable
Disable 10BASE-T echo
Disable SQE mode
R/W
R/W
R/W
Sticky bit.
1: Disable jabber detect.
0
1
1
Sticky bit.
1: Disable 10BASE-T echo.
Sticky bit.
1: Disable SQE mode.
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Registers
Table 36 • Extended Control and Status, Address 22 (0x16) (continued)
Bit
Name
Access Description
Default
11:10 10BASE-T squelch control R/W
Sticky bit.
00
00: Normal squelch.
01: Low squelch.
10: High squelch.
11: Reserved.
9
8
7
Sticky reset enable
EOF Error
R/W
RO
Super-sticky bit.
1: Enabled.
1
0
0
0
This bit is self-clearing.
1: EOF error detected.
10BASE-T disconnect state RO
This bit is self-clearing.
1: 10BASE-T link disconnect detected.
6
10BASE-T link status
Reserved
RO
RO
1: 10BASE-T link active.
Reserved.
5:1
0
SMI broadcast write
R/W
Sticky bit.
0
1: Enabled.
The following information applies to the extended control and status bits:
•
•
When bit 22.15 is set, the link integrity state machine is bypassed and the PHY is forced into a link
pass status.
When bits 22.11:10 are set to 00, the squelch threshold levels are based on the IEEE standard for
10BASE-T. When set to 01, the squelch level is decreased, which can improve the bit error rate
performance on long loops. When set to 10, the squelch level is increased and can improve the bit
error rate in high-noise environments.
•
•
When bit 22.9 is set, all sticky register bits retain their values during a software reset. Clearing this
bit causes all sticky register bits to change to their default values upon software reset. Super-sticky
bits retain their values upon software reset regardless of the setting of bit 22.9.
When bit 22.0 is set, if a write to any PHY register (registers 0–31, including extended registers), the
same write is broadcast to all PHYs. For example, if bit 22.0 is set to 1 and a write to PHY0 is
executed (register 0 is set to 0x1040), all PHYs’ register 0s are set to 0x1040. Disabling this bit
restores normal PHY write operation. Reads are still possible when this bit is set, but the value that
is read corresponds only to the particular PHY being addressed.
5.2
Extended PHY Control 1
The following table shows the settings available.
Table 37 • Extended PHY Control 1, Address 23 (0x17)
Bit
Name
Access Description
Default
110
15:13 Reserved
RO
Reserved.
12
11
MAC interface
mode
R/W
Super-sticky bit.
0: SGMII
1: 1000BASE-X
0
Note: Register 19G.15:14 = 01 for this
selection to be valid.
AMS preference R/W
Super-sticky bit.
0
1: Cat5 copper preferred
0: SerDes fiber/SFP preferred
Note: Register 19G.15:14 = 10 for this
selection to be valid.
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Registers
Table 37 • Extended PHY Control 1, Address 23 (0x17) (continued)
Bit
Name
Access Description
Default
10:8
Media operating R/W
mode
Super-sticky bits.
000: Cat5 copper only.
000
001: SerDes fiber/SFP protocol transfer mode only.
010: 1000BASE-X fiber/SFP media only with
autonegotiation performed by the PHY.
011: 100BASE-FX fiber/SFP on the fiber media pins
only.
101: Automatic media-sense (AMS) with Cat5
media or SerDes fiber/SFP protocol transfer mode.
110: AMS with Cat5 media or 1000BASE-X
fiber/SFP media with autonegotiation performed by
PHY.
111: AMS with Cat5 media or 100BASE-FX
fiber/SFP media.
100: AMS.
Note: Register 19G.15:14 = 10 for the any of
the fiber media selections to be valid.
7:6
Force AMS
override
R/W
RO
00: Normal AMS selection
00
01: Force AMS to select SerDes media only
10: Force AMS to select copper media only
11: Reserved
Note: Register 19G.15:14 = 10 for this
selection to be valid.
5:4
3
Reserved
Reserved.
Far-endloopback R/W
mode
1: Enabled.
0
2:0
Reserved
RO
Reserved.
Note: After configuring bits 13:8 of the extended PHY control register set 1, a software reset (register 0, bit 15)
must be written to change the device operating mode. On read, these bits only indicate the actual
operating mode and not the pending operating mode setting before a software reset has taken place.
5.2.1
Extended PHY Control 2
The second set of extended controls is located in register 24 in the main register space for the device.
The following table shows the settings and readouts available.
Table 38 • Extended PHY Control 2, Address 24 (0x18)
Bit
Name
Access Description
Default
15:13 100BASE-TX edge rate R/W
control
Sticky bit.
000
011: +5 Edge rate (slowest).
010: +4 Edge rate.
001: +3 Edge rate.
000: +2 Edge rate.
111: +1 Edge rate.
110: Default edge rate.
101: –1 Edge rate.
100: –2 Edge rate (fastest).
12
PICMG 2.16 reduced
power mode
R/W
RO
Sticky bit.
1: Enabled.
0
11:6
Reserved
Reserved.
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Registers
Table 38 • Extended PHY Control 2, Address 24 (0x18) (continued)
Bit
Name
Access Description
Default
5:4
Jumbo packet mode
R/W
Sticky bit.
00
00: Normal IEEE 1.5 kB packet length.
01: 9 kB jumbo packet length (12 kB with
60 ppm or better reference clock).
10: 12 kB jumbo packet length (16 kB with
70 ppm or better reference clock).
11: Reserved.
3:1
0
Reserved
RO
Reserved.
1000BASE-Tconnector R/W
loopback
1: Enabled.
0
Note: When bits 5:4 are set to jumbo packet mode, the default maximum packet values are based on 100 ppm
driven reference clock to the device. Controlling the ppm offset between the MAC and the PHY as
specified in the bit description results in a higher jumbo packet length.
5.2.2
Interrupt Mask
These bits control the device interrupt mask. The following table shows the settings available.
Table 39 • Interrupt Mask, Address 25 (0x19)
Bit Name
Access Description
Default
15 MDINT interrupt status enable
R/W
R/W
R/W
R/W
R/W
R/W
Sticky bit.
1: Enabled.
0
14 Speed state change mask
13 Link state change mask
12 FDX state change mask
11 Autonegotiation error mask
10 Autonegotiation complete mask
Sticky bit.
1: Enabled.
0
0
0
0
0
0
0
0
0
0
0
0
Sticky bit.
1: Enabled.
Sticky bit.
1: Enabled.
Sticky bit.
1: Enabled.
Sticky bit.
1: Enabled.
9
8
7
6
5
4
3
Inline powered device (PoE) detect mask R/W
Sticky bit.
1: Enabled.
Symbol error interrupt mask
R/W
R/W
R/W
R/W
R/W
R/W
Sticky bit.
1: Enabled.
Fast link failure interrupt mask
TX FIFO over/underflow interrupt mask
RX FIFO over/underflow interrupt mask
AMS media changed mask
Sticky bit.
1: Enabled.
Sticky bit.
1: Enabled.
Sticky bit.
1: Enabled.
Sticky bit.
1: Enabled.
False-carrier interrupt mask
Sticky bit.
1: Enabled.
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Registers
Table 39 • Interrupt Mask, Address 25 (0x19) (continued)
Bit Name Access Description
Default
2
1
0
Link speed downshift detect mask
R/W
R/W
R/W
Sticky bit.
1: Enabled.
0
Master/Slave resolution error mask
RX_ER interrupt mask
Sticky bit.
1: Enabled.
0
0
Sticky bit.
1: Enabled.
Note: When bit 25.15 is set, the MDINT pin is enabled. When enabled, the state of this pin reflects the state of
bit 26.15. Clearing this bit only inhibits the MDINT pin from being asserted. Also, before enabling this bit,
read register 26 to clear any previously inactive interrupts pending that will cause bit 25.15 to be set.
5.2.3
Interrupt Status
The status of interrupts already written to the device are available for reading from register 26 in the main
registers space. The following table shows the expected readouts.
Table 40 • Interrupt Status, Address 26 (0x1A)
Bit Name
Access Description
Default
15 Interrupt status
RO
RO
RO
RO
RO
RO
RO
RO
RO
Self-clearing bit.
1: Interrupt pending.
0
14 Speed state change status
13 Link state change status
12 FDX state change status
11 Autonegotiation error status
10 Autonegotiation complete status
Self-clearing bit.
1: Interrupt pending.
0
0
0
0
0
0
0
0
0
0
0
0
0
Self-clearing bit.
1: Interrupt pending.
Self-clearing bit.
1: Interrupt pending.
Self-clearing bit.
1: Interrupt pending.
Self-clearing bit.
1: Interrupt pending.
9
8
7
6
5
4
3
2
Inline powered device detect status
Symbol error status
Self-clearing bit.
1: Interrupt pending.
Self-clearing bit.
1: Interrupt pending.
Fast link failure detect status
Self-clearing bit.
1: Interrupt pending.
TX FIFO over/underflow detect status RO
RX FIFO over/underflow detect status RO
Self-clearing bit.
1: Interrupt pending.
Self-clearing bit.
1: Interrupt pending.
AMS media changed mask
RO
RO
RO
Self-clearing bit.
1: Interrupt pending.
False-carrier interrupt status
Link speed downshift detect status
Self-clearing bit.
1: Interrupt pending.
Self-clearing bit.
1: Interrupt pending.
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Registers
Table 40 • Interrupt Status, Address 26 (0x1A) (continued)
Bit Name Access Description
Default
1
Master/Slave resolution error status
RO
Self-clearing bit.
0
1: Interrupt pending.
0
RX_ER interrupt status
RO
Self-clearing bit.
0
1: Interrupt pending.
The following information applies to the interrupt status bits:
•
All set bits in this register are cleared after being read (self-clearing). If bit 26.15 is set, the cause of
the interrupt can be read by reading bits 26.14:0.
•
•
•
For bits 26.14 and 26.12, bit 0.12 must be set for this interrupt to assert.
For bit 26.2, bits 4.8:5 must be set for this interrupt to assert.
For bit 26.0, this interrupt will not occur when RX_ER is used for carrier-extension decoding of a link
partner’s data transmission.
5.2.4
Device Auxiliary Control and Status
Register 28 provides control and status information for several device functions not controlled or
monitored by other device registers. The following table shows the settings available and the expected
readouts.
Table 41 • Auxiliary Control and Status, Address 28 (0x1C)
Bit Name
Access Description
Default
15 Autonegotiation complete RO
Duplicate of bit 1.5.
0
0
0
14 Autonegotiation disabled
RO
RO
Inverted duplicate of bit 0.12.
13 HP Auto-MDIX crossover
indication
1: HP Auto-MDIX crossover performed
internally.
12 CD pair swap
RO
RO
RO
RO
RO
1: CD pairs are swapped.
1: Polarity swap on pair A.
1: Polarity swap on pair B.
1: Polarity swap on pair C.
1: Polarity swap on pair D.
0
0
0
0
0
0
11 A polarity inversion
10 B polarity inversion
9
8
7
C polarity inversion
D polarity inversion
ActiPHY link status time-out R/W
control [1]
Sticky bit. Bits 7 and 2 are part of the
ActiPHY Link Status time-out control. Bit 7 is
the MSB.
00: 1 second.
01: 2 seconds.
10: 3 seconds.
11: 4 seconds.
6
5
ActiPHY mode enable
FDX status
R/W
RO
RO
Sticky bit.
1: Enabled.
0
1: Full-duplex.
0: Half-duplex.
00
0
4:3 Speed status
00: Speed is 10BASE-T.
01: Speed is 100BASE-TX or 100BASE-FX.
10: Speed is 1000BASE-T or 1000BASE-X.
11: Reserved.
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Table 41 • Auxiliary Control and Status, Address 28 (0x1C) (continued)
Bit Name
ActiPHY link status time-out R/W
control [0]
Access Description
Default
2
Sticky bit. Bits 7 and 2 are part of the
ActiPHY Link Status time-out control. Bit 7 is
the MSB.
1
00: 1 second.
01: 2 seconds.
10: 3 seconds.
11: 4 seconds.
1:0 Media mode status
RO
00: No media selected.
01: Copper media selected.
10: SerDes media selected.
11: Reserved.
00
5.2.5
LED Mode Select
The device LED outputs are controlled using the bits in register 29 of the main register space. The
following table shows the information needed to access the functionality of each of the outputs. For more
information about LED modes, see Table 8, page 22. For information about enabling the extended LED
mode bits in Register 19E1 bits 13 to 12, see Table 9, page 23.
Table 42 • LED Mode Select, Address 29 (0x1D)
Bit
Name
Access Description
Default
15:12 LED3 mode select R/W
Sticky bit. Select from LED modes 0–15. 1000
11:8
7:4
LED2 mode select R/W
LED1 mode select R/W
LED0 mode select R/W
Sticky bit. Select from LED modes 0–15. 0000
Sticky bit. Select from LED modes 0–15. 0010
Sticky bit. Select from LED modes 0–15. 0001
3:0
5.2.6
LED Behavior
The bits in register 30 control and enable you to read the status of the pulse or blink rate of the device
LEDs. The following table shows the settings you can write to the register or read from the register.
Table 43 • LED Behavior, Address 30 (0x1E)
Bit
15:13 Reserved
12 LED pulsing enable R/W
Name
Access Description
Default
RO
Reserved.
Sticky bit.
0
0: Normal operation.
1: LEDs pulse with a 5 kHz, programmable duty
cycle when active.
11:10 LED blink/pulse-
stretch rate
R/W
Sticky bit.
01
00: 2.5 Hz blink rate/400 ms pulse-stretch.
01: 5 Hz blink rate/200 ms pulse-stretch.
10: 10 Hz blink rate/100 ms pulse-stretch.
11: 20 Hz blink rate/50 ms pulse-stretch. The
blink rate selection for PHY0 globally sets the
rate used for all LED pins on all PHY ports.
9:7
6
Reserved
RO
Reserved.
LED1 pulse-
R/W
Sticky bit.
0
stretch/blink select
1: Pulse-stretch.
0: Blink.
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Registers
Table 43 • LED Behavior, Address 30 (0x1E) (continued)
Bit
Name
Access Description
Default
5
LED0 pulse-
R/W
Sticky bit.
0
stretch/blink select
1: Pulse-stretch.
0: Blink.
4:2
1
Reserved
RO
Reserved.
LED1 combine
feature disable
R/W
Sticky bit.
0: Combine enabled (link/activity,
duplex/collision).
0
0
1: Disable combination (link only, duplex only).
0
LED0 combine
feature disable
R/W
Sticky bit.
0: Combine enabled (link/activity,
duplex/collision).
1: Disable combination (link only, duplex only).
Note: Bits 30.11:10 are active only in port 0 and affect the behavior of LEDs for all the ports.
5.2.7
Extended Page Access
To provide functionality beyond the IEEE 802.3-specified registers and main device registers, the
VSC8512-02 includes an extended set of registers that provide an additional 15 register spaces.
The register at address 31 controls the access to the extended registers for the VSC8512-02. Accessing
the GPIO page register space is similar to accessing the extended page registers. The following table
shows the settings available.
Table 44 • Extended/GPIO Page Access, Address 31 (0x1F)
Bit
Name
Access Description
Default
15:0 Extended/GPIO page R/W
register access
0x0000: Register 16–30 accesses main register 0x0000
space. Writing 0x0000 to register 31 restores the
main register access.
0x0001: Register 16–30 accesses extended
register space 1
0x0002: Register 16–30 accesses extended
register space 2
0x0003: Register 16–30 accesses extended
register space 3
0x0010: Register 0–30 accesses GPIO register
space
5.3
Extended Page 1 Registers
To access the extended page 1 registers (16E1–30E1), enable extended register access by writing
0x0001 to register 31. Writing 0x0000 to register 31 restores the main register access.
When extended page 1 register access is enabled, reads and writes to registers 16–30 affect the
extended registers 16E1–30E1 instead of those same registers in the IEEE-specified register space.
Registers 0–15 are not affected by the state of the extended page register access.
Table 45 • Extended Registers Page 1 Space
Address
16E1
Name
SerDes Media Control
Reserved
17E1
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Table 45 • Extended Registers Page 1 Space (continued)
Address
18E1
Name
Cu Media CRC Good Counter
19E1
Extended Mode Control (SerDes loopback and SIGDET
control)
20E1
Extended PHY Control 3 (ActiPHY)
21E1–22E1 Reserved
23E1
24E1
25E1
26E1
Extended PHY Control 4 (PoE and CRC error counter)
VeriPHY 1
VeriPHY 2
VeriPHY 3
27E1–28E1 Reserved
29E1
30E1
Ethernet Packet Generator (EPG) Control 1
EPG Control 2
5.3.1
SerDes Media Control
Register 16E1 controls some functions of the SerDes media interface on ports 8-11. These settings are
only valid for those ports. The following table shows the setting available in this register.
Table 46 • SerDes Media Control, Address 16E1 (0x10)
Bit Name Access Description
Default
15:14 Transmit remote fault
R/W
RO
Remote fault indication sent to link partner
(LP)
00
13:12 Link partner (LP)
remote fault
Remote fault bits sent by LP during
autonegotiation
00
1
11:10 Reserved
RO
Reserved
9
Allow 1000BASE-X
link-up
R/W
Sticky bit.
1: Allow 1000BASE-X fiber media link-up
capability
0: Suppress 1000BASE-X fiber media link-up
capability
8
Allow 100BASE-FX
link-up
R/W
RO
Sticky bit.
1
0
1: Allow 100BASE-FX fiber media link-up
capability
0: Suppress 100BASE-FX fiber media link-up
capability
7
6
Reserved
Reserved
Far end fault detected RO
in 100BASE-FX
Self-clearing bit.
1: Far end fault in 100BASE-FX detected
5:0
Reserved
RO
Reserved
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5.3.2
Cu Media CRC Good Counter
Register 18E1 makes it possible to read the contents of the CRC good counter for packets that are
received on the Cu media interface; the number of CRC routines that have executed successfully. The
following table shows the expected readouts.
Table 47 • Cu Media CRC Good Counter, Address 18E1 (0x12)
Bit
Name
Access Description
Default
15
Packet since last read
RO
Self-clearing bit.
0
1: Packet received since last read.
14
Reserved
RO
RO
Reserved.
13:0 Cu Media CRC good counter
contents
Self-clearing counter containing the 0x0000
number of packets with valid CRCs
modulo 10,000. This counter does
not saturate and will roll over to 0 on
the next good packet received after
9,999.
5.3.3
Extended Mode Control
Register 19E1 controls the extended LED and other chip modes. The following table shows the settings
available.
Table 48 • Extended Mode Control, Address 19E1 (0x13)
Bit
15
14
13
12
11
Name
Access Description
Default
LED3 Extended Mode
LED2 Extended Mode
LED1 Extended Mode
LED0 Extended Mode
R/W
R/W
R/W
R/W
R/W
1: See Extended LED Modes, page 23.
0
0
0
0
0
1: See Extended LED Modes, page 23.
1: See Extended LED Modes, page 23.
1: See Extended LED Modes, page 23.
LED Reset Blink
Suppress
1: Blink LEDs after COMA_MODE is
deasserted.
0: Suppress LED blink after COMA_MODE
is deasserted.
10:4
3:2
Reserved
RO
Reserved
0
Force MDI crossover
R/W
00: Normal HP Auto-MDIX operation.
01: Reserved.
00
10: Copper media forced to MDI.
11: Copper media forced MDI-X.
1
0
Reserved
RO
Reserved
SFP[3:0]_SD pin polarity R/W
1: Active low.
0: Active high.
0
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5.3.4
ActiPHY Control
Register 20E1 controls the device ActiPHY sleep timer, its wake-up timer, the frequency of the CLKOUT
signal, and its link speed downshifting feature. The following table shows the settings available.
Table 49 • Extended PHY Control 3, Address 20E1 (0x14)
Bit
Name
Access Description
Default
15
Disable carrier
extension
R/W
1: Disable carrier extension in SGMII-
1000BASE-T copper links.
1
14:13 ActiPHY sleep timer
R/W
Sticky bit.
01
00: 1 second.
01: 2 seconds.
10: 3 seconds.
11: 4 seconds.
12:11 ActiPHY wake-up
timer
R/W
RO
Sticky bit.
00
00: 160 ms.
01: 400 ms.
10: 800 ms.
11: 2 seconds.
10
9
Reserved
Reserved
PHY address reversal R/W
1: Enabled
Address
00
8
Reserved
RO
RO
Valid only on PHY0.
7:6
Media mode status
00: No media selected.
01: Copper media selected.
10: SerDes media selected.
11: Reserved.
5
Enable 10BASE-T no R/W
preamble mode
Sticky bit.
0
1: 10BASE-T will assert RX_DV indication
when data is presented to the receiver even
without a preamble preceding it.
4
Enable link speed
auto-downshift feature
R/W
R/W
Sticky bit.
0
1: Enable auto link speed downshift from
1000BASE-T.
3:2
Link speed auto
downshift control
Sticky bit.
01
00: Downshift after 2 failed 1000BASE-T
autonegotiation attempts.
01: Downshift after 3 failed 1000BASE-T
autonegotiation attempts.
10: Downshift after 4 failed 1000BASE-T
autonegotiation attempts.
11: Downshift after 5 failed 1000BASE-T
autonegotiation attempts.
1
0
Link speed auto
downshift status
RO
RO
0: No downshift.
1: Downshift is required or has occurred.
0
Reserved
Reserved
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5.3.5
PoE and Miscellaneous Functionality
The register at address 23E1 controls various aspects of inline powering and the CRC error counter in
the VSC8512-02.
Table 50 • Extended PHY Control 4, Address 23E1 (0x17)
Bit
Name
Access Description
Default
15:11 PHY address
RO
PHY address; latched on reset.
10
Inline powered device
R/W
Sticky bit.
0
detection
1: Enabled.
9:8
Inline powered device
detection status
RO
RO
Only valid when bit 10 is set.
00: Searching for devices.
01: Device found; requires inline power.
10: Device found; does not require inline
power.
00
11: Reserved.
7:0
Cu Media CRC error
counter
Self-clearing bit.
0x00
RC error counter for packets received on the
Cu media interface. The value saturates at
0xFF and subsequently clears when read
and restarts count.
5.3.6
VeriPHY Control 1
Register 24E1 in the extended register space provides control over the device VeriPHY diagnostics
features. There are three separate VeriPHY control registers. The following table shows the settings
available and describes the expected readouts.
Table 51 • VeriPHY Control 1, Address 24E1 (0x18)
Bit
Name
Access Description
Default
15
VeriPHY trigger
R/W
RO
Self-clearing bit.
0
1: Triggers the VeriPHY algorithm and clears
when VeriPHY has completed. Settings in
registers 24E–26E become valid after this bit
clears.
14
VeriPHY valid
1: VeriPHY results in registers 24E–26E are
valid.
0
13:8 Pair A (1, 2) distance RO
Loop length or distance to anomaly for pair A (1, 0x00
2).
7:6
5:0
Reserved
RO
Reserved.
Pair B (3, 6) distance RO
Loop length or distance to anomaly for pair B (3, 0x00
6).
Note: The resolution of the 6-bit length field is 3 meters.
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Registers
5.3.7
VeriPHY Control 2
The register at address 25E1 consists of the second of the three device registers that provide control
over VeriPHY diagnostics features. The following table shows the expected readouts.
Table 52 • VeriPHY Control 2, Address 25E1 (0x19)
Bit
Name
Access Description
RO Reserved
Pair C (4, 5) distance RO
Default
15:14 Reserved
13:8
Loop length or distance to anomaly for pair C 0x00
(4, 5)
7:6
5:0
Reserved
RO
Reserved
Pair D (7, 8) distance RO
Loop length or distance to anomaly for pair D 0x00
(7, 8)
Note: The resolution of the 6-bit length field is 3 meters.
5.3.8
VeriPHY Control 3
The register at address 26E1 consists of the third of the three device registers that provide control over
VeriPHY diagnostics features. Specifically, this register provides information about the termination status
(fault condition) for all four link partner pairs. The following table shows the expected readouts.
Table 53 • VeriPHY Control 3, Address 26E1 (0x1A)
Bit
Name
Access Description
Default
0x00
15:12 Pair A (1, 2) termination status RO
Termination fault for pair A (1, 2)
Termination fault for pair B (3, 4)
Termination fault for pair C (4, 5)
Termination fault for pair D (7, 8)
11:8
7:4
Pair B (3, 6) termination status RO
Pair C (4, 5) termination status RO
Pair D (7, 8) termination status RO
0x00
0x00
3:0
0x00
The following table shows the meanings for the various fault codes.
Table 54 • VeriPHY Control 3 Fault Codes
Code Denotes
0000 Correctly terminated pair
0001 Open pair
0010 Shorted pair
0100 Abnormal termination
1000 Cross-pair short to pair A
1001 Cross-pair short to pair B
1010 Cross-pair short to pair C
1011 Cross-pair short to pair D
1100 Abnormal cross-pair coupling with pair A
1101 Abnormal cross-pair coupling with pair B
1110 Abnormal cross-pair coupling with pair C
1111 Abnormal cross-pair coupling with pair D
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5.3.9
Ethernet Packet Generator Control 1
The EPG control register provides access to and control of various aspects of the EPG testing feature.
There are two separate EPG control registers. The following table shows the settings available in the first
register.
Table 55 • EPG Control 1, Address 29E1 (0x1D)
Bit
15
14
13
Name
Access Description
Default
EPG enable
EPG run or stop
R/W
R/W
1: Enable EPG
1: Run EPG
0
0
0
Transmission duration R/W
1: Continuous (sends in 10,000-packet
increments)
0: Send 30,000,000 packets and stop
12:11 Packet length
R/W
00: 125 bytes
0
01: 64 bytes
10: 1518 bytes
11: 10,000 bytes (jumbo packet)
10
9:6
5:2
1
Inter-packet gap
Destination address
Source address
Payload type
R/W
R/W
R/W
R/W
R/W
1: 8,192 ns
0: 96 ns
0
Lowest nibble of the 6-byte destination
address
0001
0000
0
Lowest nibble of the 6-byte destination
address
1: Randomly generated payload pattern
0: Fixed based on payload pattern
0
Bad frame check
sequence (FCS)
generation
1: Generate packets with bad FCS
0: Generate packets with good FCS
0
The following information applies to the EPG control number 1:
•
•
Do not run the EPG when the VSC8512-02 is connected to a live network.
Bit 29E1.13 (continuous EPG mode control): When enabled, this mode causes the device to send
continuous packets. When disabled, the device continues to send packets only until it reaches the
next 10,000-packet increment mark. It then ceases to send packets.
•
•
•
The 6-byte destination address in bits 9:6 is assigned one of 16 addresses in the range of 0xFF FF
FF FF FF F0 through 0xFF FF FF FF FF FF.
The 6-byte source address in bits 5:2 is assigned one of 16 addresses in the range of 0xFF FF FF
FF FF F0 through 0xFF FF FF FF FF FF.
If any of bits 13:0 are changed while the EPG is running (bit 14 is set to 1), bit 14 must be cleared
and then set back to 1 for the change to take effect and to restart the EPG.
5.3.10 Ethernet Packet Generator Control 2
Register 30E1 consists of the second set of bits that provide access to and control over the various
aspects of the EPG testing feature. The following table shows the settings available.
Table 56 • EPG Control 2, Address 30E1 (0x1E)
Bit
Name
Access Description
Data pattern repeated in the payload of packets 0x00
generated by the EPG
Default
15:0 EPG packet payload R/W
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Note: If any of bits 15:0 in this register are changed while the EPG is running (bit 14 of register 29E1 is set to
1), that bit (29E1.14) must first be cleared and then set back to 1 for the change to take effect and to
restart the EPG.
5.4
Extended Page 2 Registers
To access the extended page 2 registers (16E2–30E2), enable extended register access by writing
0x0002 to register 31. For more information, see Table 44, page 56.
When extended page 2 register access is enabled, reads and writes to registers 16–30 affect the
extended registers 16E2–30E2 instead of those same registers in the IEEE-specified register space.
Registers 0–15 are not affected by the state of the extended page register access.
Writing 0x0000 to register 31 restores the main register access.
The following table lists the addresses and register names in the extended register page 2 space. These
registers are accessible only when the device register 31 is set to 0x0002.
Table 57 • Extended Registers Page 2 Space
Address
16E2
Name
Cu PMD Transmit Control
EEE Control
17E2
18E2–30E2 Reserved
5.4.1
Cu PMD Transmit Control
The register at address 16E2 consists of the bits that provide control over the amplitude settings for the
transmit side Cu PMD interface. These bits provide the ability to make small adjustments in the signal
amplitude to compensate for minor variations in the magnetics from different vendors. Extreme caution
must be exercised when changing these settings from the default values as they have a direct impact on
the signal quality. Changing these settings also affects the linearity and harmonic distortion of the
transmitted signals. Contact Microsemi for further help with changing these values.
Table 58 • Cu PMD Transmit Control, Address 16E2 (0x10)
Bit
Name
Access Description
Default
15:12 1000BASE-T signal R/W
amplitude trim
Change 1000BASE-T 0000
signal amplitude
11:8
100BASE-TX signal R/W
amplitude trim
Change 100BASE-TX 0010
signal amplitude
7:4
10BASE-T signal
amplitude trim
R/W
Change 10BASE-T
signal amplitude
1111
3:0
10BASE-Te signal
amplitude trim
R/W
Change 10BASE-Te 0000
signal amplitude
5.4.2
EEE Control
The register at address 17E2 consists of the bits that provide additional control over the chip behavior in
Energy Efficient Ethernet (IEEE 802.3az) mode for debug and to allow interoperation with legacy MACs
that do not support IEEE 802.3az.
Table 59 • EEE Control, Address 17E2 (0x11)
Bit
Name
Access Description
R/W Enable Energy Efficient (IEEE 802.3az)
10BASE-Te operating mode.
Default
15
Enable 10BASE-Te
0
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Registers
Table 59 • EEE Control, Address 17E2 (0x11) (continued)
Bit
Name
Access Description
Default
14
Enable LED in fiber
unidirectional mode
R/W
1: Enable LED functions in fiber unidirectional
mode.
0
13:10 Invert LED polarity
R/W
Invert polarity of LED[3:0] signals. Default is to 0000
drive an active low signal on the LED pins. This
also applies to enhanced serial LED mode. For
more information, see Enhanced Serial LED
Mode, page 25.
9:6
5
Reserved
R/O
Reserved.
Enable 1000BASE-T R/W
force mode
1: Enable 1000BASE-T force mode to allow
PHY to link up in 1000BASE-T mode without
forcing master/slave when register 0, bits 6 and
13 are set to 2'b10.
0
0
4
Force transmit LPI
R/W
1: Enable the EPG to transmit LPI on the MDI
instead of normal idles when receiving normal
idles from the MAC.
0: Transmit idles being received from the MAC.
3
2
1
0
Inhibit 100BASE-TX R/W
transmit EEE LPI
1: Disable transmission of EEE LPI on transmit 0
path MDI in 100BASE-TX mode when receiving
LPI from MAC.
Inhibit 100BASE-TX R/W
receive EEE LPI
1: Disable transmission of EEE LPI on receive
path MAC interface in 100BASE-TX mode
when receiving LPI from the MDI.
0
Inhibit 1000BASE-T R/W
transmit EEE LPI
1: Disable transmission of EEE LPI on transmit 0
path MDI in 1000BASE-T mode when receiving
LPI from MAC.
Inhibit 1000BASE-T R/W
receive EEE LPI
1: Disable transmission of EEE LPI on receive
path MAC interface in 1000BASE-T mode when
receiving LPI from the MDI.
0
5.5
Extended Page 3 Registers
To access the extended page 3 registers (16E3–30E3), enable extended register access by writing
0x0003 to register 31. For more information, see Table 44, page 56.
When extended page 3 register access is enabled, reads and writes to registers 16–30 affect the
extended registers 16E3–30E3 instead of those same registers in the IEEE-specified register space.
Registers 0–15 are not affected by the state of the extended page register access.
Writing 0x0000 to register 31 restores the main register access.
The following table lists the addresses and register names in the extended register page 3 space. These
registers are accessible only when the device register 31 is set to 0x0003.
Table 60 • Extended Registers Page 3 Space
Address
16E3
Name
MAC SerDes PCS Control
MAC SerDes PCS Status
MAC SerDes Clause 37 Advertised Ability
MAC SerDes Clause 37 Link Partner Ability
MAC SerDes Status
17E3
18E3
19E3
20E3
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Table 60 • Extended Registers Page 3 Space (continued)
Address
21E3
22E3
23E3
24E3
25E3
26E3
27E3
28E3
29E3
30E3
Name
Media SerDes Transmit Good Packet Counter
Media SerDes Transmit CRC Error Counter
Media SerDes PCS Control
Media SerDes PCS Status
Media SerDes Clause 37 Advertised Ability
Media SerDes Clause 37 Link Partner Ability
Media SerDes status
Fiber Media CRC Good Counter
Fiber Media CRC Error Counter
Reserved
5.5.1
MAC SerDes PCS Control
The register at address 16E3 consists of the bits that provide access to and control over MAC SerDes
PCS block. The following table shows the settings available.
Table 61 • MAC SerDes PCS Control, Address 16E3 (0x10)
Bit
Name
Access Description
Default
15
MAC interface disable
R/W
R/W
Sticky bit.
1: 1000BASE-X MAC interface disable
when media link down.
0
14
13
MAC interface restart
Sticky bit.
0
0
1: 1000BASE-X MAC interface restart on
media link change.
MAC interface PD enable R/W
Sticky bit.
1: MAC interface autonegotiation parallel
detect enable.
12
11
MAC interface
autonegotiation restart
R/W
R/W
R/W
Self-clearing bit.
1: Restart MAC interface autonegotiation.
0
Force advertised ability
1: Force 16-bit advertised ability from
register 18E3.
0
10:8 SGMII preamble control
000 = No effect on the start of packet.
001 = If both the first two nibbles of the
10/100 packet are not 0x5, a byte of 0x55
must be prefixed to the output, otherwise
there will be no effect on the start of packet.
010 = If both the first two nibbles of the
10/100 packet are not 0x5, a byte of 0x55
must be prefixed to the output. An
additional byte of 0x55 must be prefixed to
the output if the next two nibbles are also
not 0x5.
001
011–111 = Reserved.
7
6
MAC SerDes
autonegotiation enable
R/W
1: MAC SerDes ANEG enable.
0
SerDes polarity at input of R/W
MAC
1: Invert polarity of signal received at input 0
of MAC.
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Table 61 • MAC SerDes PCS Control, Address 16E3 (0x10) (continued)
Bit
Name
Access Description
Default
5
SerDes polarity at output of R/W
MAC
1: Invert polarity of signal at output of MAC.
4
3
Fast link status enable
R/W
1: Use fast link fail indication as link status 0
indication to MAC SerDes
0: Use normal link status indication to MAC
SerDes
Unidirectional enable
R/W
1: Enable transmit on MAC interface
regardless of whether the PHY has
determined that a valid link has been
established.
0
0: Enable transmit on MAC interface only
when the PHY has determined that a valid
link has been established.
2:0
Reserved
RO
Reserved.
5.5.2
MAC SerDes PCS Status
The register at address 17E3 consists of the bits that provide status from the MAC SerDes PCS block.
The following table shows the settings available.
Table 62 • MAC SerDes PCS Status, Address 17E3 (0x11)
Bit
Name
Access Description
15:13 Reserved
RO
RO
RO
Reserved
12
11
SGMII alignment error
1: SGMII alignment error occurred
MAC interface LP
1: MAC interface link partner autonegotiation restart
request occurred
autonegotiation restart
10
Reserved
RO
RO
Reserved
9:8
MAC remote fault
01, 10, and 11: Remote fault detected from MAC
00: No remote fault detected from MAC
7
6
Asymmetric pause
advertisement
RO
RO
RO
1: Asymmetric pause advertised by MAC
Symmetric pause
advertisement
1: Symmetric pause advertised by MAC
5
4
3
Full duplex advertisement
1: Full duplex advertised by MAC
1: Half duplex advertised by MAC
Half duplex advertisement RO
MAC interface LP
autonegotiation capable
RO
1: MAC interface link partner autonegotiation
capable
2
1
MAC interface link status
RO
RO
1: MAC interface link status connected
MAC interface
1: MAC interface autonegotiation complete
autonegotiation complete
0
MAC interface PCS signal RO
detect
1: MAC interface PCS signal detect present
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5.5.3
MAC SerDes Clause 37 Advertised Ability
The register at address 18E3 consists of the bits that provide access to and control over MAC SerDes
Clause 37 advertised ability. The following table shows the settings available.
Table 63 • MAC SerDes Cl37 Advertised Ability, Address 18E3 (0x12)
Bit Name Access Description
Default
15:0 MAC SerDes
advertised ability
R/W
Current configuration code word being advertised 0x0000
(this register is read/write if 16E3.11 = 1)
5.5.4
5.5.5
MAC SerDes Clause 37 Link Partner Ability
The register at address 19E3 consists of the bits that provide status of the MAC SerDes link partner’s
Clause 37 advertised ability. The following table shows the settings available.
Table 64 • MAC SerDes Cl37 LP Ability, Address 19E3 (0x13)
Bit
Name
Access Description
15:0 MAC SerDes LP ability RO
Last configuration code word received from link partner
MAC SerDes Status
The register at address 20E3 consists of the bits that provide access to MAC SerDes status. The
following table shows the settings available.
Table 65 • MAC SerDes Status, Address 20E3 (0x14)
Bit
Name
Access Description
15
K28.5 comma realignment RO
Self-clearing bit.
1: a K28.5 comma re-alignment has occurred
14
SerDes signal detect
RO
RO
Self-clearing bit. Sticky bit.
1: SerDes signal detection occurred
13:0 Reserved
Reserved
5.5.6
Media SerDes Transmit Good Packet Counter
The register at address 21E3 consists of the bits that provide status of the media SerDes transmit good
packet counter. The following table shows the settings available.
Table 66 • Media SerDes Tx Good Packet Counter, Address 21E3 (0x15)
Bit
15
14
Name
Access Description
Tx good packet counter active RO
1: Transmit good packet counter active
Reserved
Reserved
RO
RO
13:0 Tx good packet count
Transmit good packet count modulo 10000
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5.5.7
Media SerDes Transmit CRC Error Counter
The register at address 22E3 consists of the bits that provide status of the media SerDes transmit packet
count that had a CRC error. The following table shows the settings available.
Table 67 • Media SerDes Tx CRC Error Counter, Address 22E3 (0x16)
Bit
15:8 Reserved
7:0 Tx CRC packet count RO
Name
Access Description
RO
Reserved
Transmit CRC packet count (saturates at 255)
5.5.8
Media SerDes PCS Control
The register at address 23E3 consists of the bits that provide access to and control over Media SerDes
PCS control. The following table shows the settings available.
Table 68 • Media SerDes PCS Control, Address 23E3 (0x17)
Bit
Name
Access Description
Default
15:14 Reserved
RO
Reserved
13
Media interface
R/W
Sticky bit.
0
autonegotiation parallel-
detection
1: SerDes media autonegotiation parallel
detect enabled
12
11
Reserved
RO
Reserved
Force advertised ability R/W
1: Force 16-bit advertised ability from
register 25E3.15:0
0
10:0
Reserved RO
Reserved
5.5.9
Media SerDes PCS Status
The register at address 24E3 consists of the bits that provide status of the Media SerDes PCS block. The
following table shows the settings available.
Table 69 • Media SerDes PCS Status, Address 24E3 (0x18)
Bit
Name
Access Description
15:12 Reserved
RO
RO
Reserved
11
Media interface link partner
1: Media interface link partner
autonegotiation restart request
occurred
autonegotiation restart
10
Reserved
RO
RO
Reserved
9:8
Remote fault detected
01, 10, 11: Remote fault detected from
link partner
7
6
5
4
Link partner asymmetric pause
Link partner symmetric pause
RO
RO
RO
RO
1: Asymmetric pause advertised by
link partner
1: Symmetric pause advertised by link
partner
Link partner full duplex
advertisement
1: Full duplex advertised by link
partner
Link partner half duplex
advertisement
1: Half duplex advertised by link
partner
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Table 69 • Media SerDes PCS Status, Address 24E3 (0x18) (continued)
Bit
Name
Access Description
3
Link partner autonegotiation
capable
RO
1: Media interface link partner
autonegotiation capable
2
1
Media interface link status
RO
1: Media interface link status
Media interface autonegotiation RO
complete
1: Media interface autonegotiation
complete
0
Media interface signal detect
RO
1: Media interface signal detect
5.5.10 Media SerDes Clause 37 Advertised Ability
The register at address 25E3 consists of the bits that provide access to and control over Media SerDes
Clause 37 advertised ability. The following table shows the settings available.
Table 70 • Media SerDes Cl37 Advertised Ability, Address 25E3 (0x19)
Bit
Name
Access Description
Default
15:0 Media SerDes advertised R/W
ability
Current configuration code word being
advertised. This register is read/write if
23E3.11 = 1.
0x0000
5.5.11 Media SerDes Clause 37 Link Partner Ability
The register at address 26E3 consists of the bits that provide status of the media SerDes link partner’s
Clause 37 advertised ability. The following table shows the settings available.
Table 71 • MAC SerDes Cl37 LP Ability, Address 26E3 (0x1A)
Bit
Name
Access Description
15:0 Media SerDes LP ability RO
Last configuration code word received from
link partner
5.5.12 Media SerDes Status
The register at address 27E3 consists of the bits that provide access to Media SerDes status. The
following table shows the settings available.
Table 72 • Media SerDes Status, Address 27E3 (0x1B)
Bit
Name
Access Description
15
K28.5 comma realignment RO
Self-clearing bit.
1: K28.5 comma re-alignment has occurred
14
Signal detect
RO
RO
Self-clearing bit. Sticky bit.
1: SerDes media signal detect
13:0 Reserved
Reserved
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5.5.13 Fiber Media CRC Good Counter
Register 28E3 makes it possible to read the contents of the CRC good counter for packets that are
received on the Fiber media interface; the number of CRC routines that have executed successfully. The
following table shows the expected readouts.
Table 73 • Fiber Media CRC Good Counter, Address 28E3 (0x1C)
Bit
Name
Access Description
Default
15
Packet since last read RO
Self-clearing bit.
0
1: Packet received since last read.
14
Reserved
RO
Reserved.
13:0 Fiber media CRC good RO
counter contents
Self-clearing bit. Counter containing the
number of packets with valid CRCs. This
counter does not saturate and will roll over.
0x000
5.5.14 Fiber Media CRC Error Counter
Register 29E3 makes it possible to read the contents of the CRC error counter for packets that are
received on the Fiber media interface. The following table shows the expected readouts.
Table 74 • Fiber Media CRC Error Counter, Address 29E3 (0x1D)
Bit
15:8 Reserved
7:0 Fiber Media CRC error counter RO
Name
Access Description
Default
RO Reserved.
Self-clearing bit. CRC error counter for 0x00
packets received on the Fiber media
interface. The value saturates at 0xFF
and subsequently clears when read
and restarts count.
5.6
General Purpose Registers
Accessing the General Purpose register space is similar to accessing the extended page registers. Set
register 31 to 0x0010. This sets all 32 registers to the general purpose register space.
To restore main register page access, write 0x0000 to register 31.
The following table lists the addresses and register names in the general purpose register page space.
These registers are accessible only when the device register 31 is set to 0x0010.
Table 75 • General Purpose Registers Page Space
Address Name
0G–12G Reserved
13G
14G
15G
16G
17G
18G
19G
20G
SIGDET/LED vs. GPIO Control
COMA_MODE and CLK_SQUELCH_IN Control
GPIO Input
GPIO Output
GPIO Output Enable
Global Command and SerDes Configuration
MAC Mode and Fast Link Configuration
I2C MUX Control 1
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Table 75 • General Purpose Registers Page Space (continued)
Address Name
21G
22G
23G
24G
25G
I2C MUX Control 2
I2C MUX Data Read/Write
Recovered Clock 0 Control
Recovered Clock 1 Control
Enhanced LED Control
26G–28G Reserved
29G
30G
Global Interrupt Status
Reserved
5.6.1
SIGDET/LED vs. GPIO Control
The SIGDET/LED control register configures the multipurpose pins to be either signal detect pins for
each fiber media port, or to be general purpose I/O pins. It also controls LED1 pins for PHYs 8, 9, 10, and
11 to be either LED1 pins or GPIO pins. The following table shows the values that can be written.
Table 76 • SIGDET/LED vs. GPIO Control, Address 13G (0x0D)
Bit
Name
Access Description
Default
15:14 GPIO_16 control R/W
13:12 GPIO_15 control R/W
11:10 GPIO_14 control R/W
00: LED1 operation for PHY11
01, 10: Reserved
11: GPIO controlled by MII registers 15G–17G
00
00: LED1 operation for PHY10
01, 10: Reserved
11: GPIO controlled by MII registers 15G–17G
00
00
00
00
00
00
00
00: LED1 operation for PHY9
01, 10: Reserved
11: GPIO controlled by MII registers 15G–17G
9:8
7:6
5:4
3:2
1:0
GPIO_13 control R/W
SFP3_SD control R/W
SFP2_SD control R/W
SFP1_SD control R/W
SFP0_SD control R/W
00: LED1 operation for PHY8
01, 10: Reserved
11: GPIO controlled by MII registers 15G–17G
00: SIGDET operation
01, 10: Reserved
11: GPIO controlled by MII registers 15G–17G
00: SIGDET operation
01, 10: Reserved
11: GPIO controlled by MII registers 15G–17G
00: SIGDET operation
01, 10: Reserved
11: GPIO controlled by MII registers 15G–17G
00: SIGDET operation
01, 10: Reserved
11: GPIO controlled by MII registers 15G–17G
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5.6.2
COMA_MODE and CLK_SQUELCH_IN Control
Register 14G configures the functionality of the COMA_MODE and CLK_SQUELCH_IN input pins.
Table 77 • COMA_MODE and CLK_SQUELCH_IN Control, Address 14G (0x0E)
Bit
15
14
Name
Access Description
Default
Reserved
RO
Reserved
Clock squelch input enable R/W
Configure PHY4_LED1 pin as
CLK_SQUELCH_IN and enable clock
squelch control from that pin
0
13
12
COMA_MODE output
enable (active low)
R/W
1: COMA_MODE pin is an input
0: COMA_MODE pin is an output
1
0
COMA_MODE output data R/W
Value to output on the COMA_MODE pin
when it is configured as an output
11
10
COMA_MODE input data RO
Tri-state enable for I2C bus R/W
Data read from the COMA_MODE pin
1: Tri-state I2C bus output signals instead 0
of driving them high. This allows those
signals to be pulled above VDDIO using
an external pull-up resistor.
0: Drive I2C bus output signals to high and
low values as appropriate
9
Tri-state enable for LEDs R/W
1: Tri-state LED output signals instead of
driving them high. This allows those
signals to be pulled above VDDIO using
an external pull-up resistor.
0
0: Drive LED bus output signals to high
and low values as appropriate.
8:0
Reserved
RO
Reserved.
0
5.6.3
5.6.4
GPIO Input
The input register contains information about the input to the device GPIO pins. Read from this register to
access the data on the device GPIO pins. The following table shows the readout you can expect.
Table 78 • GPIO Input, Address 15G (0x0F)
Bit
15:8 Reserved
7:0 GPIO input RO
Name
Access Description
Default
RO
Reserved
Data read from the SFP[3:0]_SD and
GPIO[16:13] pins
GPIO Output
The output register allows you to access and control the output from the device GPIO pins. The following
table shows the values you can write.
Table 79 • GPIO Output, Address 16G (0x10)
Bit
15:8 Reserved
7:0 GPIO output R/W
Name
Access Description
Default
RO Reserved
Data written to the SFP[3:0]_SD and 0x00
GPIO[16:13] pins
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5.6.5
GPIO Pin Configuration
Register 17G in the GPIO register space controls whether a particular GPIO pin functions as an input or
an output. The following table shows the settings available.
Table 80 • GPIO Input/Output Configuration, Address 17G (0x11)
Bit
Name
Access Description
Default
15:8 Reserved
RO
Reserved
7:0
SFP[3:0]_SD and GPIO[16:13] pin R/W
input or output enable
1: Pin is configured as an output.
0: Pin is configured as an input.
0x00
5.6.6
Global Command and SerDes Configuration
Register 18G is a command window. Bit 15 tells the internal processor to execute the command. When
bit 15 is cleared the command has completed. Software needs to wait until bit 15 = 0 before proceeding
with the next PHY register access. The following table lists the values to write to register 18G to execute
the various commands.
Table 81 • Global Command and SerDes Configuration, Address 18G (0x12)
Command
Value
Enable 12 PHYs MAC SGMII
0x80B0
0x80A0
0x8F81(1)
0x8F91(1)
Enable 12 PHYs MAC QSGMII
Enable 4 PHYs (PHY8 to PHY11) media 1000BASE-X
Enable 4 PHYs (PHY8 to PHY11) media 100BASE-FX
1. The “F” in the command has a bit representing each of the four PHYs. To exclude a PHY from the
configuration, set its bit to 0. For example, the configuration of PHY 3 and PHY 2 to 1000BASE-X
would be 1100 or a “C” and the command would be 0x8CC1.
5.6.7
MAC Mode and Fast Link Configuration
Register 19G controls the MAC interface mode and the selection of the source PHY for the fast link
failure indication. The following table shows the settings available for the FAST_LINK_STATUS pin.
Table 82 • MAC Mode and Fast Link Configuration, Address 19G (0x13)
Bit Name Access Description
Default
15:14 MAC interface mode select R/W
for all PHYs in the
Select MAC interface mode
00: QSGMII to CAT5 mode
01: SGMII to CAT5 mode
10: QSGMII to CAT5 and Fiber mode
11: Reserved
00
VSC8512-02
13:4
Reserved
RO
Reserved
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Registers
Table 82 • MAC Mode and Fast Link Configuration, Address 19G (0x13) (continued)
Bit
Name
Access Description
Default
3:0
Fast link failure port setting R/W
0000: PHY0
0xF
0001: PHY1
0010: PHY2
0011: PHY3
0100: PHY4
0101: PHY5
0110: PHY6
0111: PHY7
1000: PHY8
1001: PHY9
1010: PHY10
1011: PHY11
1100–1111: Output disabled
5.6.8
I2C MUX Control 1
The following table shows the settings available to control the integrated I2C MUX.
Table 83 • I2C MUX Control 1, Address 20G (0x14)
Bit
Name
Access Description
Default
15:9 I2C device address
R/W
Top 7 bits of the 8-bit address sent out on the 0xA0
two wire serial stream. The bottom bit is the
read/write signal, which is controlled by
register 21G, bit 8. SFPs use 0xA0.
8:6
5:4
Reserved
RO
Reserved.
I2C SCL clock frequency R/W
00: 50 kHz
01: 100 kHz
10: 400 kHz
11: 2 MHz
01
3
2
1
0
I2C MUX port 3 enable
I2C MUX port 2 enable
I2C MUX port 1 enable
I2C MUX port 0 enable
R/W
R/W
R/W
R/W
1: Enabled.
0: I2C disabled. Becomes PHY5_LED1 pin.
0
0
0
0
1: Enabled.
0: I2C disabled. Becomes PHY6_LED1 pin.
1: Enabled.
0: I2C disabled. Becomes PHY7_LED1 pin.
0: SFP_SERIALCLK0
1: ESLED_CLK
5.6.9
I2C MUX Control 2
Register 21G is used to control the I2C MUX for status and control of I2C slave devices.
Table 84 • I2C MUX Interface Status and Control, Address 21G (0x15)
Bit
Name
Access Description
Default
15
I2C MUX ready
RO
RO
R/W
1: I2C MUX is ready for read or write.
14:12 Reserved
Reserved
11:10 PHY port Address
Specific VSC8512-02 PHY port being
addressed.
00
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Registers
Table 84 • I2C MUX Interface Status and Control, Address 21G (0x15) (continued)
Bit
Name
Access Description
Default
9
Enable I2C MUX access R/W
Self-clearing bit.
0
1: Execute read or write through the I2C
MUX based on the settings of register bit
21G.8.
8
I2C MUX read or write R/W
1: Read from I2C MUX.
0: Write to I2C MUX.
1
7:0
I2C MUX address
R/W
Sets the address of the I2C MUX used to
direct read or write operations.
0x00
5.6.10 I2C MUX Data Read/Write
Register 22G in the extended register space enables access to the I2C MUX.
Table 85 • I2C MUX Data Read/Write, Address 22G (0x16)
Bit
Name
Access Description
Default
15:8 I2C MUX read data RO
Eight-bit data read from I2C MUX; requires
setting both register 21G.9 and 21G.8 to 1.
7:0
I2C MUX write data R/W
Eight-bit data to be written to I2C MUX.
0x00
5.6.11 Recovered Clock 0 Control
Register 23G in the extended register space controls the functionality of the recovered clock 0 output
signal.
Table 86 • Recovered Clock 0 Control, Address 23G (0x17)
Bit
Name
Access Description
Default
15
Enable
R/W
1: Enable recovered clock 0 output
0
RCVRD_CLK[0]
0: Disable recovered clock 0 output
14:11 Clock source
select
R/W
Select bits for source PHY for recovered clock:
0000: PHY0
0000
0001: PHY1
0010: PHY2
0011: PHY3
0100: PHY4
0101: PHY5
0110: PHY6
0111: PHY7
1000: PHY8
1001: PHY9
1010: PHY10
1011: PHY11
1100–1111: Reserved
10:8
7:6
Clock frequency R/W
select
Select output clock frequency:
000: 25 MHz output clock
001: 125 MHz output clock
010: 31.25 MHz output clock
011–111: Reserved
000
Reserved
RO
Reserved.
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Registers
Table 86 • Recovered Clock 0 Control, Address 23G (0x17) (continued)
Bit
Name
Access Description
R/W Select clock squelch level
Default
5:4
Clock squelch
level
00: Automatically squelch clock to low when the link
is not up, is unstable, is up in a mode that does not
support the generation of a recovered clock
(1000BASE-T master or 10BASE-T), or is up in EEE
mode (100BASE-TX or 1000BASE-T slave).
01: Same as 00 except that the clock is also
generated in 1000BASE-T master and 10BASE-T
link-up modes. This mode also generates a
recovered clock output in EEE mode during
reception of LP_IDLE.
10: Squelch only when the link is not up.
11: Disable clock squelch.
Note: A clock from the SerDes or Cu PHY
will be output on the recovered clock
output in this mode when the link is
down.
3
Reserved
RO
Reserved.
2:0
Clock selection R/W
for specified PHY
000: Serial media recovered clock (only valid for
PHYs 8, 9, 10, and 11 that support dual-media
functionality)
000
001: Copper PHY recovered clock
010: Copper PHY transmitter TCLK
011–111: Reserved
5.6.12 Recovered Clock 1 Control
Register 24G in the extended register space controls the functionality of the recovered clock 1 output
signal.
Table 87 • Recovered Clock 1 Control, Address 24G (0x18)
Bit
Name
Access Description
Default
15
Enable
R/W
Enable recovered clock 1 output
0
RCVRD_CLK[1]
14:11 Clock source
select
R/W
Select bits for source PHY for recovered clock:
0000: PHY0
0000
0001: PHY1
0010: PHY2
0011: PHY3
0100: PHY4
0101: PHY5
0110: PHY6
0111: PHY7
1000: PHY8
1001: PHY9
1010: PHY10
1011: PHY11
1100–1111: Reserved
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Table 87 • Recovered Clock 1 Control, Address 24G (0x18) (continued)
Bit
Name
Access Description
Default
10:8
Clock frequency
select
R/W
Select output clock frequency:
000
000: 25 MHz output clock
001: 125 MHz output clock
010: 31.25 MHz output clock
011–111: Reserved
7:6
5:4
Reserved
RO
Reserved.
Clock squelch
level
R/W
Select clock squelch level:
00: Automatically squelch clock to low when the
link is not up, is unstable, is up in a mode that does
not support the generation of a recovered clock
(1000BASE-T master or 10BASE-T), or is up in
EEE mode (100BASE-TX or 1000BASE-T slave).
01: Same as 00 except that the clock is also
generated in 1000BASE-T master and 10BASE-T
link-up modes. This mode also generates a
recovered clock output in EEE mode during
reception of LP_IDLE
10: Squelch only when the link is not up
11: Disable clock squelch.
Note: A clock from the SerDes or Cu PHY
will be output on the recovered clock
output in this mode when the link is
down.
3
Reserved
RO
Reserved
2:0
Clock selection for R/W
specified PHY
000: Serial media recovered clock (only valid for
PHYs 8, 9, 10, and 11 that support dual-media
functionality).
000
001: Copper PHY recovered clock
010–111: Reserved.
5.6.13 Enhanced LED Control
The following table contains the bits to control advanced functionality of the parallel and serial LED
signals.
Table 88 • Enhanced LED Control, Address 25G (0x19)
Bit
Name
Access Description
Default
15:8 LED pulsing duty cycle R/W
control
Programmable control for LED pulsing duty
cycle when bit 30.12 is set to 1. Valid settings
are between 0 and 198. A setting of 0
corresponds to a 0.5% duty cycle and 198
corresponds to a 99.5% duty cycle.
Intermediate values change the duty cycle in
0.5% increments
00
7
Serial LED output 2
enable
R/W
Enable the serial LED output functionality for
GPIO_5, GPIO_6, GPIO_7, and GPIO_8 pins
1: Pins function as serial LED outputs
0: Pins retain their normal function
0
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Table 88 • Enhanced LED Control, Address 25G (0x19) (continued)
Bit
Name
Access Description
R/W Enable the serial LED output functionality for
Default
6
Serial LED output 1
enable
0
GPIO_[3:0] pins
1: Pins function as serial LED outputs
0: Pins retain their normal function
5:3
Serial LED frame rate R/W
selection
Select frame rate of serial LED stream
000: 2500 Hz frame rate
001: 1000 Hz frame rate
010: 500 Hz frame rate
011: 250 Hz frame rate
100: 200 Hz frame rate
101: 125 Hz frame rate
110: 40 Hz frame rate
111: Output basic serial LED stream.
See Table 10, page 24.
2:1
Serial LED select
LED port swapping
R/W
R/W
Select which LEDs from each PHY to enable on 00
the serial stream
00: Enable all 4 LEDs of each PHY
01: Enable LEDs 2, 1 and 0 of each PHY
10: Enable LEDs 1 and 0 of each PHY
11: Enable LED 0 of each PHY
0
See LED Port Swapping, page 25.
5.6.14 Global Interrupt Status
The following table contains the interrupt status from the various sources to indicate which one caused
that last interrupt on the pin.
Table 89 • Global Interrupt Status, Address 29G (0x1D)
Bit
Name
Access Description
15:12 Reserved
RO
RO
Reserved
11
10
9
PHY11 interrupt source(1)
PHY11 interrupt source indication
0: PHY caused the interrupt
1: PHY did not cause an interrupt
PHY10 interrupt source(1)
PHY9 interrupt source(1)
PHY8 interrupt source(1)
PHY7 interrupt source(1)
PHY6 interrupt source(1)
RO
RO
RO
RO
RO
PHY10 interrupt source indication
0: PHY caused the interrupt
1: PHY did not cause an interrupt
PHY9 interrupt source indication
0: PHY caused the interrupt
1: PHY did not cause an interrupt
8
PHY8 interrupt source indication
0: PHY caused the interrupt
1: PHY did not cause an interrupt
7
PHY7 interrupt source indication
0: PHY caused the interrupt
1: PHY did not cause an interrupt
6
PHY6 interrupt source indication
0: PHY caused the interrupt
1: PHY did not cause an interrupt
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Table 89 • Global Interrupt Status, Address 29G (0x1D) (continued)
Bit
Name
Access Description
5
PHY5 interrupt source(1)
RO
RO
RO
RO
RO
RO
PHY5 interrupt source indication
0: PHY caused the interrupt
1: PHY did not cause an interrupt
4
3
2
1
0
PHY4 interrupt source(1)
PHY3 interrupt source(1)
PHY2 interrupt source(1)
PHY1 interrupt source(1)
PHY0 interrupt source(1)
PHY4 interrupt source indication
0: PHY caused the interrupt
1: PHY did not cause an interrupt
PHY3 interrupt source indication
0: PHY caused the interrupt
1: PHY did not cause an interrupt
PHY2 interrupt source indication
0: PHY caused the interrupt
1: PHY did not cause an interrupt
PHY1 interrupt source indication
0: PHY caused the interrupt
1: PHY did not cause an interrupt
PHY0 interrupt source indication
0: PHY caused the interrupt
1: PHY did not cause an interrupt
1. This bit is set to 1 when the corresponding PHY’s Interrupt Status register 26 (0x1A) is read.
5.7
Clause 45 Registers to Support Energy Efficient Ethernet
This section describes the Clause 45 registers that are required to support Energy Efficient Ethernet.
Access to these registers is through the IEEE standard registers 13 and 14 (MMD access control and
MMD data or address registers) as described in section 4.2.11 and 4.2.12.
The following table lists the addresses and register names in the Clause 45 register page space.
Table 90 • Clause 45 Registers Page Space
Address Name
3.1
PCS Status 1
3.20
3.22
7.60
7.61
EEE Capability
EEE Wake Error Counter
EEE Advertisement
EEE Link Partner Advertisement
5.7.1
PCS Status 1
The bits in the PCS Status 1 register provide a status of the EEE operation from the PCS for the link that
is currently active.
Table 91 • PCS Status 1, Address 3.1
Bit
15:12 Reserved
11 Tx LPI received
Name
Access Description
RO Reserved
RO/LH 1: Tx PCS has received LPI
0: LPI not received
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Registers
Table 91 • PCS Status 1, Address 3.1 (continued)
Bit
Name
Access Description
10
Rx LPI received
RO/LH 1: Rx PCS has received LPI
0: LPI not received
9
8
Tx LPI indication
Rx LPI indication
Reserved
RO
RO
RO
1: Tx PCS is currently receiving LPI
0: PCS is not currently receiving LPI
1: Rx PCS is currently receiving LPI
0: PCS is not currently receiving LPI
7:3
2
Reserved
PCS receive link status RO
1: PCS receive link up
0: PCS receive link down
1:0
Reserved RO
Reserved
5.7.2
EEE Capability
This register is used to indicate the capability of the PCS to support EEE functions for each PHY type.
The following table shows the bit assignments for the EEE capability register.
Table 92 • EEE Capability, Address 3.20
Bit
Name
Access Description
15:3 Reserved
RO
1000BASE-T EEE RO
Reserved
2
1
0
1: EEE is supported for 1000BASE-T
0: EEE is not supported for 1000BASE-T
100BASE-TX
EEE
RO
RO
1: EEE is supported for 100BASE-TX
0: EEE is not supported for 100BASE-TX
Reserved
Reserved
5.7.3
5.7.4
EEE Wake Error Counter
This register is used by PHY types that support EEE to count wake time faults where the PHY fails to
complete its normal wake sequence within the time required for the specific PHY type. The definition of
the fault event to be counted is defined for each PHY and can occur during a refresh or a wakeup as
defined by the PHY. This 16-bit counter is reset to all zeros when the EEE wake error counter is read or
when the PHY undergoes hardware or software reset.
Table 93 • EEE Wake Error Counter, Address 3.22
Bit
Name
Access Description
15:0 Wake error counter RO
Count of wake time faults for a PHY
EEE Advertisement
This register defines the EEE advertisement that is sent in the unformatted next page following a EEE
technology message code. The following table shows the bit assignments for the EEE advertisement
register.
Table 94 • EEE Advertisement, Address 7.60
Bit
Name
Access Description
RO Reserved
Default
15:3 Reserved
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Registers
Table 94 • EEE Advertisement, Address 7.60 (continued)
Bit
Name
Access Description
Default
2
1000BASE-T EEE R/W
1: Advertise that the 1000BASE-T has EEE
0
capability
0: Do not advertise that the 1000BASE-T has EEE
capability
1
0
100BASE-TX
EEE
R/W
RO
1: Advertise that the 100BASE-TX has EEE
capability
0: Do not advertise that the 100BASE-TX has EEE
capability
0
Reserved
Reserved
5.7.5
EEE Link Partner Advertisement
All the bits in the EEE LP Advertisement register are read only. A write to the EEE LP advertisement
register has no effect. When the AN process has been completed, this register will reflect the contents of
the link partner’s EEE advertisement register. The following table shows the bit assignments for the EEE
advertisement register.
Table 95 • EEE Advertisement, Address 7.61
Bit
Name
Access Description
15:3 Reserved
RO
1000BASE-T EEE RO
Reserved
2
1
0
1: Link partner is advertising EEE capability for 1000BASE-T
0: Link partner is not advertising EEE capability for
1000BASE-T
100BASE-TX
EEE
RO
RO
1: Link partner is advertising EEE capability for 100BASE-TX
0: Link partner is not advertising EEE capability for
100BASE-TX
Reserved
Reserved
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Electrical Specifications
6
Electrical Specifications
This section provides the DC characteristics, AC characteristics, recommended operating conditions,
and stress ratings for the VSC8512-02 device.
6.1
DC Characteristics
This section contains the DC specifications for the VSC8512-02 device.
6.1.1
VDD_IO
The following table shows the DC specifications for the pins referenced to VDD_IO. The specifications
listed in the following table are valid only when VDD = 1.0 V, VDD_VS = 1.0 V, VDD_AL = 1.0 V, or
VDD_AH = 2.5 V.
Table 96 • VDD_IO DC Characteristics
Parameter
Symbol
VOH
Minimum Maximum Unit Condition
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input leakage current
2.0
2.8
0.4
3.0
0.7
32
32
6
V
IOH = –1.0 mA
IOL = 1.0 mA
VOL
–0.3
1.85
–0.3
–32
–32
V
VIH
V
VIL
V
IILEAK
µA
µA
mA
Internal resistor included
Internal resistor included
Output leakage current IOLEAK
Output low current drive IOL
strength
Output high current drive IOH
strength
–6
mA
6.1.2
Internal Pull-Up or Pull-Down Resistors
Internal pull-up or pull-down resistors are specified in the following table. For more information about
signals with internal pull-up or pull-down resistors, see Pins by Function, page 100Pins by Function,
page 72.
All internal pull-up resistors are connected to their respective I/O supply.
Table 97 • Internal Pull-Up or Pull-Down Resistors
Parameter
Symbol Minimum Typical Maximum Unit
Internal pull-up resistor, GPIO pins
Internal pull-up resistor, all other pins
Internal pull-down resistor
RPU
RPU
RPD
33
96
96
53
90
kΩ
kΩ
kΩ
120
120
144
144
6.1.3
Reference Clock
The following table shows the DC specifications for a differential reference clock input signal.
Table 98 • Reference Clock DC Characteristics
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Input voltage range
VIP,VIN
–25
1260
mV
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Electrical Specifications
Table 98 • Reference Clock DC Characteristics (continued)
Parameter
Symbol
Minimum
150(1)
0
Typical
Maximum
1000
Unit
mV
mV
Ω
Input differential voltage
VID
Input common-mode voltage VICM
Differential input impedance RI
1200(2)
100
1. To meet jitter specifications, the minimum input differential voltage must be 400 mV. When using a single-
ended clock input, the REFCLK_P low voltage must be less than VDDA – 200 mV, and the high voltage
level must be greater than VDDA + 200 mV.
2. The maximum common-mode voltage is provided without a differential signal. The common-mode voltage
is only limited by the maximum and minimum input voltage range and by the differential amplitude of the
input signal.
6.1.4
Enhanced SerDes Interface (QSGMII)
All DC specifications for the enhanced SerDes interface are compliant with QSGMII Specification
Revision 1.3 and meet or exceed the requirements in the standard. They are also compliant with OIF-
CEI-02.0 requirements where applicable.
The enhanced SerDes interface supports the following operating modes: SGMII, QSGMII, and SFP. The
values in the following table apply to the modes specified in the condition column.
Table 99 • Enhanced SerDes Driver DC Specifications
Parameter
Symbol Minimum Maximum Unit Condition
Output differential peak voltage,
SFP and QSGMII modes
|VODp
|
250
400
mV VDD_VS = 1.0 V
RL = 100 Ω ±1%
maximum drive
Output differential peak voltage,
SGMII mode(1)
|VODp
RO
|
150
40
400
140
mV VDD_VS = 1.0 V
RL = 100 Ω ±1%
DC output impedance,
single-ended, SGMII mode
Ω
VC = 1.0 V
See Figure 29,
page 85
RO mismatch between A and B,
SGMII mode(2)
∆RO
10
%
VC = 1.0 V
See Figure 29,
page 85
Change in |VOD| between 0 and 1, ∆|VOD
|
25
25
40
mV
RL = 100 Ω ±1%
SGMII mode
Change in VOS between 0 and 1, ∆VOS
SGMII mode
mV RL = 100 Ω ±1%
Output current, drivers shorted to |IOSA|,
mA
ground, SGMII and QSGMII
modes
|IOSB
|
Output current, drivers shorted
together, SGMII and QSGMII
modes
|IOSAB
|
12
mA
1. Voltage is adjustable in 64 steps.
2. Matching of reflection coefficients. For more information about test methods, see IEEE Std 1596.3-1996.
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Electrical Specifications
The following table lists the DC specifications for the enhanced SerDes receiver.
Table 100 • Enhanced SerDes Receiver DC Specifications
Parameter
Symbol Minimum Typical Maximum Unit
(1)
Input voltage range, VIA or VIB
VI
–0.25
100
0
1.2
V
Input differential peak-to-peak voltage
Input common-mode voltage
|VID|
VICM
RI
1600
1200
120
mV
mV
Ω
Receiver differential input impedance
80
100
1. QSGMII DC input sensitivity is less than 400 mV.
6.1.5
SerDes Interface (SGMII)
The SerDes output drivers are designed to operate in SGMII/LVDS mode. The SGMII/LVDS mode meets
or exceeds the DC requirements of Serial-GMII Specification Revision 1.9 (ENG-46158), unless
otherwise noted. The following table lists the DC specifications for the SGMII driver. The values are valid
for all configurations, unless stated otherwise.
Table 101 • SerDes Driver DC Specifications
Parameter
Symbol Minimum Maximum Unit Condition
Output high voltage, VOA or VOB
Output low voltage, VOA or VOB
VOH
VOL
1250
mV RL = 100 Ω ±1%
mV RL = 100 Ω ±1%
0
Output differential peak voltage(1) |VOD
|
150
400
400
580
140
mV VDD_VS = 1.0 V
RL = 100 Ω ±1%
Output differential peak voltage,
SGMII mode(1)
|VOD
VOS
RO
|
150
420
40
mV VDD_VS = 1.0 V
RL = 100 Ω ±1%
Output offset voltage(2)
mV VDD_VS = 1.0 V
RL = 100 Ω ±1%
DC output impedance,
Ω
VC = 1.0 V
See Figure 29,
page 85
single-ended, SGMII mode
RO mismatch between A and B,
SGMII mode(3)
∆RO
10
%
VC = 1.0 V
See Figure 29,
page 85
Change in |VOD| between 0 and 1, ∆|VOD
|
25
25
40
12
mV
RL = 100 Ω ±1%
SGMII mode
Change in VOS between 0 and 1, ∆VOS
SGMII mode
mV RL = 100 Ω ±1%
Output current, driver shorted to
GND, SGMII mode
|IOSA|,
|IOSB
mA
mA
|
Output current, drivers shorted
together, SGMII mode
|IOSAB|
1. Voltage is adjustable in 14 steps.
2. Requires AC-coupling for SGMII compliance.
3. Matching of reflection coefficients. For more information about test methods, see IEEE Std 1596.3-1996.
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Electrical Specifications
Figure 27 • SGMII DC Transmit Test Circuit
VOA
VOD = VOA – VOB
100 Ω ±1%
VOS = ½ (VOA + VOB
)
VOB
Figure 28 • SGMII DC Definitions
VOA
VOB
GND
VOD
0 V differential
∆|VOD
|
|VOD
|
0 V differential
VOS
∆VOS
GND
∆|VOD| = | |VOAH – VOBL| – |VOBH – VOAL| |
∆VOS = | ½(VOAH + VOBL) – ½(VOAL + VOBH) |
Figure 29 • SGMII DC Driver Output Impedance Test Circuit
VOA
50 Ω ±0.1%
+
–
0 and 1
VC
VOB
50 Ω ±0.1%
The following table lists the DC specifications for the SGMII receivers.
Table 102 • SerDes Receiver DC Specifications
Parameter
Symbol Minimum Maximum Unit Condition
Input voltage range, VIA or VIB
VI
–25
100
1250
2000
mV
mV
Input differential peak-to-peak
voltage
|VID|
Input common-mode voltage(1) VICM
0
VDD_A
mV Without any
(2)
differential signal
(internally
AC-coupled)
Receiver differential input
impedance
RI
80
25
120
Ω
Input differential hysteresis,
SGMII mode
VHYST
mV
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Electrical Specifications
1. SGMII compliancy requires external AC-coupling. When interfacing with specific Microsemi devices, DC-
coupling is possible. For more information, contact your local Microsemi sales representative.
2. The maximum common-mode voltage is provided without a differential signal, because the input is
internally AC-coupled. The common-mode voltage is only limited by the maximum and minimum input
voltage range and the input signal’s differential amplitude.
Figure 30 • SGMII DC Input Definitions
VIA
VID = VIA – VIB
VIC = ½ (VIA + VIB)
VIB
6.1.6
Current Consumption
Current consumption is determined under the following operating conditions:
•
•
•
•
QSGMII to 1000BASE-T mode
QSGMII to 1000BASE-X dual media mode
QSGMII to 100BASE-FX dual media mode
SGMII to 1000BASE-T mode
The typical current consumption values in QSGMII to 1000BASE-T mode are based on nominal voltages
with the MAC interface operating in QSGMII mode, and all media side ports operating in 1000BASE-T
with full-duplex enabled. Data traffic is a 64-bit random data pattern at 100% utilization.
Table 103 • QSGMII to 1000BASE-T Current Consumption
Parameter
Symbol Typical Maximum Unit
Worst-case power consumption PD
6.75
W
A
A
A
A
A
A
Current with VDD at 1.0 V
IVDD
IVDD_A
1.15
0.18
Current with VDD_A at 1.0 V
Current with VDD_AH at 2.5 V
Current with VDD_AL at 1.0 V
Current with VDD_IO at 2.5 V
Current with VDD_VS at 1.0 V
IVDD_AH 1.37
IVDD_AL 0.19
IVDD_IO 0.06
IVDD_VS 0.09
The typical current consumption values in QSGMII to 1000BASE-X dual media mode are based on
nominal voltages with the MAC interface operating in QSGMII mode, 8 media side ports operating in
1000BASE-T with full-duplex enabled and 4 dual media ports operating in 1000BASE-X mode. Data
traffic is a 64-bit random data pattern at 100% utilization.
Table 104 • QSGMII to 1000BASE-X Current Consumption
Parameter
Symbol Typical Maximum Unit
Worst-case power consumption PD
5.25
W
A
A
A
A
A
Current with VDD at 1.0 V
Current with VDD_A at 1.0 V
Current with VDD_AH at 2.5 V
Current with VDD_AL at 1.0 V
Current with VDD_IO at 2.5 V
IVDD
IVDD_A
0.95
0.2
IVDD_AH 0.93
IVDD_AL 0.16
IVDD_IO 0.06
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Electrical Specifications
Table 104 • QSGMII to 1000BASE-X Current Consumption (continued)
Parameter
Current with VDD_VS at 1.0 V
Symbol Typical Maximum Unit
IVDD_VS 0.13
A
The typical current consumption values in QSGMII to 100BASE-FX dual media mode are based on
nominal voltages with the MAC interface operating in QSGMII mode, 8 media side ports operating in
1000BASE-T with full-duplex enabled, and 4 dual media ports operating in 100BASE-FX mode. Data
traffic is a 64-bit random data pattern at 100% utilization.
Table 105 • QSGMII to 100BASE-FX Current Consumption
Parameter
Symbol Typical Maximum Unit
Worst-case power consumption PD
5.25
W
A
A
A
A
A
A
Current with VDD at 1.0 V
IVDD
IVDD_A
0.95
0.2
Current with VDD_A at 1.0 V
Current with VDD_AH at 2.5 V
Current with VDD_AL at 1.0 V
Current with VDD_IO at 2.5 V
Current with VDD_VS at 1.0 V
IVDD_AH 0.93
IVDD_AL 0.16
IVDD_IO 0.06
IVDD_VS 0.13
The typical current consumption values in SGMII to 1000BASE-T mode are based on nominal voltages
with the MAC interface operating in SGMII mode and all media side ports operating in 1000BASE-T with
full-duplex enabled. Data traffic is a 64-bit random data pattern at 100% utilization.
Table 106 • SGMII to 1000BASE-T Current Consumption
Parameter
Symbol Typical Maximum Unit
Worst-case power consumption PD
6.85
W
A
A
A
A
A
A
Current with VDD at 1.0 V
IVDD
IVDD_A
1.18
0.25
Current with VDD_A at 1.0 V
Current with VDD_AH at 2.5 V
Current with VDD_AL at 1.0 V
Current with VDD_IO at 2.5 V
Current with VDD_VS at 1.0 V
IVDD_AH 1.37
IVDD_AL 0.19
IVDD_IO 0.06
IVDD_VS 0.19
6.2
AC Characteristics
This section provides the AC specifications for the VSC8512-02 device.
6.2.1
Reference Clock
To meet QSGMII jitter generation requirements, Microsemi requires the use of a differential reference
clock source. Use of a 25 MHz single-ended reference clock is not recommended. However, to
implement a QSGMII chip interconnect using a 25 MHz single-ended reference clock and achieve error-
free data transfer on that interface, use an Ethernet switch with higher jitter tolerance than specified in
the standard, such as Microsemi VSC742x family of products. For more information about QSGMII
interoperability when using a 25 MHz single-ended reference clock, contact your Microsemi
representative.
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Electrical Specifications
The following table shows the AC specifications for a differential reference clock input. Performance is
guaranteed for 156.25 MHz and 125 MHz differential clocks only, however 25 MHz and single-ended
clocks are also supported.
Table 107 • Reference Clock AC Characteristics
Parameter
Symbol Minimum Typical Maximum Unit Condition
Reference clock frequency,
REFCLK_SEL[2:0] = 100
ƒ
ƒ
ƒ
–100 ppm 25.00
100 ppm
MHz
MHz
MHz
Reference clock frequency,
REFCLK_SEL[2:0] = 000
–100 ppm 125.00 100 ppm
–100 ppm 156.25 100 ppm
Reference clock frequency,
REFCLK_SEL[2:0] = 001
Duty cycle
DC
40
50
60
%
Rise time and fall time
tR, tF
1.5
ns
20% to 80%
threshold
REFCLK input RMS jitter,
bandwidth from 12 kHz to
500 kHz
20
4
ps
ps
ps
ps
dB
dB
REFCLK input RMS jitter,
bandwidth from 500 kHz to
15 MHz
REFCLK input RMS jitter,
bandwidth from 15 MHz to
40 MHz
20
100
0.3
3
REFCLK input RMS jitter,
bandwidth from 40 MHz to
80 MHz
Jitter gain from REFCLK to
SerDes output, bandwidth
from 0 MHz to 0.1 MHz
Jitter gain from REFCLK to
SerDes output, bandwidth
from 0.1 MHz to 7 MHz
Jitter gain from REFCLK to
SerDes output, bandwidth
greater than 7 MHz
3 –20 × log dB
(ƒ/7 MHz)
6.2.2
Recovered Clock Outputs
The following table shows the AC specifications for the RCVRD_CLK1 and RCVRD_CLK0 outputs.
Table 108 • Recovered Clock AC Characteristics
Parameter
Symbol
Minimum Typical Maximum Unit Condition
Recovered clock
frequency, registers 23G
or 24G bits 10:8 = 001
ƒ
125.00
31.25
MHz
Recovered clock
ƒ
MHz
frequency, registers 23G
or 24G bits 10:8 = 010
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Electrical Specifications
Table 108 • Recovered Clock AC Characteristics (continued)
Parameter
Symbol
Minimum Typical Maximum Unit Condition
Recovered clock
frequency, registers 23G
or 24G bits 10:8 = 000
ƒ
25.00
50
MHz
Duty cycle
DC
40
60
%
Clock rise and fall time, tR, tF
20% to 80%
1.5
ns
Measured at 50%
threshold
Peak-to-peak jitter,
copper media interface
JPPCLK_C
200
200
ps
ps
Jitter bandwidth
from 12 kHz to
10 MHz
u
Peak-to-peak jitter, fiber JPPCLK_Fi
media interface
Jitter bandwidth
from 10 kHz to
80 MHz
6.2.3
SerDes Outputs
The values listed in the following table are valid for all configurations, unless otherwise noted.
Table 109 • SerDes Output AC Specifications
Parameter
OD ringing compared to VS,
Symbol Minimum
Maximum Unit Condition
V
VRING
±10
200
30
%
RL = 100 Ω ±1%
SGMII mode
VOD rise time and fall time,
SGMII mode
tR, tF
100
ps
20% to 80% of VS
RL = 100 Ω ±1%
Differential peak-to-peak output VOD
voltage
mV
dB
dB
dB
ps
Tx disabled
Differential output return loss, RLO_DIFF ≥10
50 MHz to 625 MHz
RL = 100 Ω ±1%
RL = 100 Ω ±1%
Differential output return loss, RLO_DIFF 10–10 × log
625 MHz to 1250 MHz
(ƒ/625 MHz)
Common-mode return loss,
50 MHz to 625 MHz
RLOCM
tSKEW
6
Intrapair skew, SGMII mode
20
6.2.4
SerDes Driver Jitter
The following table lists the jitter characteristics for the SerDes output driver.
Table 110 • SerDes Driver Jitter Characteristics
Parameter
Symbol Maximum Unit Condition
Total jitter
TJO
192
80
ps
ps
Measured according to IEEE 802.3.38.5.
Measured according to IEEE 802.3.38.5.
Deterministic jitter DJO
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Electrical Specifications
6.2.5
SerDes Inputs
The following table lists the AC specifications for the SerDes inputs.
Table 111 • SerDes Input AC Specifications
Parameter
Maximum
Unit Condition
dB RL = 100 Ω ±1%
Differential input return loss, ≥10
50 MHz to 625 MHz
Differential input return loss, 10–10 × log (ƒ/625 MHz) dB
625 MHz to 1250 MHz
RL = 100 Ω ±1%
6.2.6
SerDes Receiver Jitter Tolerance
The following table lists jitter tolerances for the SerDes receiver.
Table 112 • SerDes Receiver Jitter Tolerance
Parameter
Symbol Minimum Unit Condition
Total jitter tolerance, greater than 637 kHz, TJTI
SFP mode
600
370
1.4
ps
ps
ns
ns
ns
Measured according to
IEEE 802.3 38.6.8
Deterministic jitter tolerance, greater than DJTI
637 kHz, SFP mode
Measured according to
IEEE 802.3 38.6.8
Cycle distortion jitter tolerance, 100BASE- JTCD
FX mode
Measured according to
ISO/IEC 9314-3:1990
Data-dependent jitter tolerance, 100BASE- DDJ
FX mode
2.2
Measured according to
ISO/IEC 9314-3:1990
Random peak-to-peak jitter tolerance,
100BASE-FX mode
RJT
2.27
Measured according to
ISO/IEC 9314-3:1990
6.2.7
Enhanced SerDes Interface
All AC specifications for the enhanced SerDes interface are compliant with QSGMII Specification
Revision 1.3 and meet or exceed the requirements in the standard. They are also compliant with the OIF-
CEI-02.0 requirements where applicable.
The enhanced SerDes interface supports the following modes of operation: SGMII, QSGMII, and SFP.
The values in the tables in the following sections apply to the modes listed in the condition column and
are based on the test circuit shown in Figure 27, page 85. The transmit and receive eye specifications
relate to the eye diagrams shown in the following illustration, with the compliance load as defined in the
test circuit.
Figure 31 • QSGMII Transient Parameters
Transmitter Eye Mask
Receiver Eye Mask
T_Y2
T_Y1
0
R_Y2
R_Y1
0
–T_Y1
–T_Y2
–R_Y1
–R_Y2
0
T_X1
T_X2
1–T_X2 1–T_X1
1.0
0
R_X1
0.5
1–R_X1
1.0
Time (UI)
Time (UI)
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Electrical Specifications
6.2.8
Enhanced SerDes Outputs
The following table provides the AC specifications for the enhanced SerDes outputs in SGMII mode.
Table 113 • Enhanced SerDes Outputs AC Specifications, SGMII Mode
Parameter
Symbol Minimum
Maximum Unit Condition
Unit interval, 1.25G mode
VOD ringing compared to VS
VOD rise time and fall time
UI
800 ps
VRING
±10
200
%
RL = 100 Ω ±1%
tR, tF
100
ps
20% to 80% of VS
RL = 100 Ω ±1%
Differential peak-to-peak output VOD
voltage
30
mV Tx disabled
Differential output return loss, RLO_DIFF ≥10
dB
dB
dB
ps
RL = 100 Ω ±1%
RL = 100 Ω ±1%
50 MHz to 625 MHz
Differential output return loss, RLO_DIFF 10–10 × log
625 MHz to 1250 MHz
(ƒ/625 MHz)
Common-mode return loss,
50 MHz to 625 MHz
RLOCM
tSKEW
6
Intrapair skew
20
The following table provides the AC specifications for the enhanced SerDes outputs in QSGMII mode.
Table 114 • Enhanced SerDes Outputs AC Specifications, QSGMII Mode
Parameter
Symbol Minimum
Maximum Unit Condition
Unit interval, 5G
UI
200 ps
VOD rise time and fall time tR, tF
30
96
30
ps
20% to 80% of VS
RL = 100 Ω ±1%
Differential peak-to-peak
output voltage
VOD
mV Tx disabled
Differential output return
loss, 100 MHz to 2.5 GHz
RLO_DIFF
8
dB
dB
RL = 100 Ω ±1%
RL = 100 Ω ±1%
Differential output return
loss, 2.5 GHz to 5 GHz
RLO_DIFF 8 dB – 16.6 log
(ƒ/2.5 GHz)
Eye mask X1
Eye mask X2
Eye mask Y1
Eye mask Y2
T_X1
T_X2
0.15
0.4
UI
UI
T_Y1
T_Y2
200
mV
mV
450
6.2.9
Enhanced Serial LEDs
This section contains the AC specifications for the enhanced serial LEDs. The duty cycle of the
LED_PULSE signal is programmable and can be varied from 0.5% to 99.5%.
Table 115 • Enhanced Serial LEDs AC Characteristics
Parameter
Symbol Minimum Maximum Unit
LED_CLK cycle time
tCYC
255
257
ns
µs
Pause between LED_DATA bit sequences tPAUSE
387.712
24987
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Electrical Specifications
Table 115 • Enhanced Serial LEDs AC Characteristics (continued)
Parameter
Symbol Minimum Maximum Unit
LED_CLK to LED_DATA
LED_CLK to LED_LD
LED_LD pulse width
LED_PULSE cycle time
tCO
127
255
127
199
129
257
129
201
ns
ns
ns
µs
tCL
tLW
tPULSE
Figure 32 • Enhanced Serial LED Timing
tcyc
tpause
LED_CLK
tcl
tco
Bit 1
LED_DATA
Bit 2
Bit X
Bit 1
Bit 2
tlw
LED_LD
tpulse
LED_PULSE
6.2.10 Enhanced SerDes Driver Jitter Characteristics
The following table lists the jitter characteristics for the enhanced SerDes driver in QSGMII mode. For
information about jitter characteristics for the enhanced SerDes driver in SGMII mode, see Table 110,
page 89.
Table 116 • Enhanced SerDes Driver Jitter Characteristics, QSGMII Mode
Parameter
Symbol Maximum Unit Condition
Total output jitter
TJO
60
ps
Measured according to
IEEE 802.3.38.5.
Deterministic output jitter
DJO
10
ps
Measured according to
IEEE 802.3.38.5.
6.2.11 Enhanced SerDes Inputs
The following table lists the AC specifications for the enhanced SerDes inputs in SGMII mode.
Table 117 • Enhanced SerDes Input AC Specifications, SGMII Mode
Parameter
Symbol Minimum Unit Condition
Unit interval, 1.25G
UI
ps
800 ps
Differential input return loss,
50 MHz to 625 MHz
RLI_DIFF 10
dB
RL = 100 Ω ±1%
Common-mode input return loss, RLICM
50 MHz to 625 MHz
6
dB
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Electrical Specifications
The following table lists the AC specifications for the enhanced SerDes inputs in QSGMII mode.
Table 118 • Enhanced SerDes Inputs AC Specifications, QSGMII Mode
Parameter
Symbol Minimum
Maximum Unit Condition
Unit interval, 5G
UI
200 ps
Differential input return loss, RLI_DIFF
100 MHz to 2.5 GHz
8
dB
dB
dB
RL = 100 Ω ±1%
Differential input return loss, RLI_DIFF 8 dB – 16.6 log
2.5 GHz to 5 GHz
RL = 100 Ω ±1%
(ƒ/2.5 GHz)
Common-mode input return RLICM
loss, 100 MHz to 2.5 GHz
6
Eye mask X1
Eye mask Y1
Eye mask Y2
R_X1
R_Y1
R_Y2
0.3
50
UI
mV
mV
450
6.2.12 Enhanced SerDes Receiver Jitter Tolerance
The following table lists the jitter tolerance for the enhanced SerDes receiver in QSGMII mode. For
information about jitter tolerance for the enhanced SerDes receiver in SGMII mode, see Table 112,
page 90.
Table 119 • Enhanced SerDes Receiver Jitter Tolerance, QSGMII Mode
Parameter
Symbol Maximum Unit Condition
Bounded high-probability jitter(1)
BHPJ
90
ps
92 ps peak-to-peak random
jitter and 38 ps sinusoidal jitter
(SJHF).
Sinusoidal jitter, maximum
Sinusoidal jitter, high frequency
Total jitter tolerance
SJMAX
SJHF
TJTI
1000
10
ps
ps
ps
120
92 ps peak-to-peak random
jitter and 38 ps sinusoidal jitter
(SJHF).
1. This is the sum of uncorrelated bounded high probability jitter (0.15 UI), and correlated bounded high
probability jitter (0.30 UI). Uncorrelated bounded high probability jitter is distribution where the value of the
jitter shows no correlation to any signal level being transmitted, formally defined as deterministic jitter (DJ).
Correlated bounded high probability jitter is jitter distribution where the value of the jitter shows a strong
correlation to the signal level being transmitted.
6.2.13 JTAG Interface
This section provides the AC specifications for the JTAG interface. The specifications meet or exceed the
requirements of IEEE 1149.1-2001. The JTAG receive signal requirements are requested at the pin of
the device. The JTAG_TRST signal is asynchronous to the clock, and does not have a setup or hold time
requirement.
Table 120 • JTAG Interface AC Specifications
Parameter
Symbol Minimum Maximum Unit Condition
TCK frequency
TCK cycle time
TCK high time
ƒ
10
MHz
ns
tC
100
40
tW(CH)
ns
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Electrical Specifications
Table 120 • JTAG Interface AC Specifications (continued)
Parameter
Symbol Minimum Maximum Unit Condition
TCK low time
tW(CL)
tSU
40
10
10
ns
ns
ns
ns
ns
Setup time to TCK rising
Hold time from TCK rising tH
TDO valid after TCK falling tV(C)
28
30
CL = 10 pF
CL = 0 pF
TDO hold time from TCK
falling
tH(TDO)
0
TDO disable time(1)
tDIS
ns
ns
See Figure 34, page 94.
nTRST time low
tW(TL)
30
1. The pin begins to float when a 300 mV change from the actual VOH/VOL level occurs.
Figure 33 • JTAG Interface Timing Diagram
tC
TCK
tW(CH)
tW(CL)
TDI
TMS
tSU
tH
tV(C)
TDO
See definition.
tH(TDO)
tDIS
nTRST
tW(TL)
Figure 34 • Test Circuit for TDO Disable Time
3.3 V
500 Ω
From output under test
5 pF
500 Ω
6.2.14 Serial Management Interface
This section contains the AC specifications for the serial management interface (SMI).
Table 121 • SMI Interface AC Characteristics
Parameter
Symbol Minimum Typical Maximum Unit Condition
ƒCLK 0.488 20.83 MHz
MDC frequency(1)
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Electrical Specifications
Table 121 • SMI Interface AC Characteristics (continued)
Parameter
Symbol Minimum Typical Maximum Unit Condition
MDC cycle time
MDC time high
MDC time low
tCYC
tWH
tWL
48
20
20
10
2048
ns
ns
ns
ns
CL = 50 pF
CL = 50 pF
MDIO setup time to MDC tSU
on write
MDIO hold time to MDC
on write
tH
tR
tR
10
ns
ns
ns
MDC rise time,
MDC = 0: 1 MHz
100
MDC rise time,
MDC = 1 MHz:
ƒCLK maximum
tCYC
×
10%(1)
MDC fall time,
MDC = 0: 1 MHz
tF
tF
100
ns
ns
MDC fall time,
MDC = 1 MHz:
ƒCLK maximum
tCYC
×
10%(1)
MDC to MDIO valid
tCO
10
300
ns
Time-dependant
on the value of
the external pull-
up resistor on the
MDIO pin
1. For ƒCLK greater than 1 MHz, the minimum rise time and fall time is in relation to the frequency of the MDC
clock period. For example, if ƒCLK is 2 MHz, the minimum clock rise time and fall time is 50 ns.
Figure 35 • SMI Interface Timing
tWH
tWL
MDC
tCYC
tSU
tH
MDIO
(write)
Data
tCO
MDIO
(read)
Data
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Electrical Specifications
6.2.15 Reset Timing
This section contains the AC specifications that apply to device reset functionality. The signal applied to
the NRESET input must comply with the specifications listed in the following table.
Table 122 • NRESET Timing Specifications
Parameter
Symbol Minimum Maximum Unit
NRESET assertion time after power supplies tW
and clock stabilize
2
ms
Recovery time from reset inactive to device tREC
fully active
105
ms
NRESET pulse width
tW(RL)
tWAIT
100
105
ns
Wait time between NRESET de-assert and
access of the SMI interface
ms
Figure 36 • Reset Timing
tcyc
tpause
LED_CLK
tco
LED_DATA
Bit 1
Bit 2
Bit X
Bit 1
6.2.16 Serial LEDs
This section contains the AC specifications for the serial LEDs.
Table 123 • Serial LEDs AC Characteristics
Parameter
Symbol Minimum Maximum Unit
LED_CLK cycle time
tCYC
1
µs
ms
ns
Pause between LED bit sequences tPAUSE
LED_CLK to LED_DATA tCO
25
1
Figure 37 • Serial LED Timing
tcyc
tpause
LED_CLK
tco
LED_DATA
Bit 1
Bit 2
Bit X
Bit 1
6.2.17 Power Supply Sequencing
During power on and off, VDD_A and VDD_VS must never be more than 300 mV above VDD. VDD_VS must
be powered, even if the associated interface is not used. These power supplies must not remain at
ground or left floating.
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Electrical Specifications
There are no sequencing requirements for VDD_AL, VDD_AH, or VDD_IO. These power supplies can
remain at ground or left floating if not used.
The NRESET and JTAG_nTRST inputs must be held low until all power supply voltages
have reached their recommended operating condition values.
6.3
Operating Conditions
The following table shows the recommended operating conditions for the device.
Table 124 • Recommended Operating Conditions
Parameter
Symbol Minimum Typical Maximum Unit
Power supply voltage for VDD
Power supply voltage for VDD_A
Power supply voltage for VDD_AH
Power supply voltage for VDD_AL
Power supply voltage for VDD_IO
Power supply voltage for VDD_VS
VSC8512-02 operating temperature(1)
VSC8512-03 operating temperature(1)
VDD
0.95
0.95
1.00
1.00
2.50
1.00
2.50
1.00
1.05
1.05
2.62
1.05
2.62
1.05
125
V
V
V
V
V
V
VDD_A
VDD_AH 2.38
VDD_AL 0.95
VDD_IO
2.38
VDD_VS 0.95
T
T
0
°C
°C
–40
125
1. Minimum specification is ambient temperature, and the maximum is junction temperature.
6.4
Stress Ratings
This section contains the stress ratings for the VSC8512-02 device.
Warning Stresses listed in the following table may be applied to devices one at a time without causing
permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these
values for extended periods may affect device reliability.
Table 125 • Stress Ratings
Parameter
Symbol
VDD
Minimum Maximum Unit
Power supply voltage for core supply
–0.3
–0.3
1.10
1.32
V
V
Power supply voltage for SerDes and Enhanced
SerDes interfaces
VDD_VS
Power supply voltage for analog circuits in twisted pair VDD_AL
interface
–0.3
–0.3
–0.3
1.10
2.75
2.75
V
V
V
Power supply voltage for analog circuits in twisted pair VDD_AH
interface
Power supply voltage for MIIM, PI, and miscellaneous VDD_IO
I/O
Input voltage for GPIO and logic input pins
3.3
V
Storage temperature
TS
–55
125
250
1750
°C
V
Electrostatic discharge voltage, charged device model VESD_CDM –250
Electrostatic discharge voltage, human body model VESD_HBM –1750
V
Warning This device can be damaged by electrostatic discharge (ESD) voltage. Microsemi
recommends that all integrated circuits be handled with appropriate precautions. Failure to observe
proper handling and installation procedures may adversely affect reliability of the device.
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Electrical Specifications
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
98
Pin Descriptions
7
Pin Descriptions
The VSC8512-02 device has 672 pins, which are described in this section.
The pin information is also provided as an attached Microsoft Excel file, so that you can copy it
electronically. In Adobe Reader, double-click the attachment icon.
7.1
Pin Diagrams
The following illustrations show the pin diagrams for the VSC8512-02 device.
Figure 38 • Pin Diagram, Left
1
2
3
4
5
6
7
8
9
10
11
12
13
A
B
P8_D0P
P8_D1P
P8_D2P
P8_D3P
P7_D0P
P7_D1P
P7_D2P
P7_D3P
P6_D0P
P6_D1P
P6_D2P
P6_D3P
VSS_1
P9_D3P
P9_D2P
P9_D1P
P9_D0P
P10_D3P
P10_D2P
P10_D1P
P10_D0P
P11_D3P
P11_D2P
P11_D1P
P8_D0N
P9_D3N
P9_D2N
P9_D1N
P9_D0N
P10_D3N
P10_D2N
P10_D1N
P10_D0N
P11_D3N
P11_D2N
P11_D1N
P11_D0N
MDINT
P8_D1N
P8_D2N
NRESET
P8_D3N
P7_D0N
VSS
P7_D1N
P7_D2N
P7_D3N
P6_D0N
P6_D1N
P6_D2N
P6_D3N
COMA_MODE
NO CONNECT
RESERVED_3
RESERVED_29
RESERVED_4
REFCLK_SEL0
REFCLK_SEL1
C
PHYADD3 PHYADD4
RESERVED_205
RESERVED_216
RESERVED_218
RESERVED_206 RESERVED_207 RESERVED_208 RESERVED_209 RESERVED_248
RESERVED_211 RESERVED_13
D
VDD_AH_1 VDD_AH_2
VDD_AH_4
REF_REXT_1
VDD_AH_10 VDD_AH_11
VDD_AH_20 VDD_AH_21
E
VDD_AH_7 VDD_AH_8 VDD_IO_1 VDD_IO_2 VDD_AH_9 VDD_AL_1 VDD_AL_2
RESERVED_219
RESERVED_247
RESERVED_246
VDD_AH_17 VDD_AH_18
VDD_AH_19
VDD_3
F
VDD_IO_5 VDD_AH_3
VDD_AL_5 VDD_AL_6
RESERVED_15
VDD_AL_10
VDD_AL_9
G
VSS_3
VSS_7
VSS_4
VDD_1
VDD_2
VDD_4
VDD_5
RESERVED_14
H
J
VSS_8
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
RESERVED_240 RESERVED_241 RESERVED_242 RESERVED_243 RESERVED_244 RESERVED_245
VDD_AH_27 VDD_AH_28 VDD_AL_13 VDD_AL_14 VDD_AL_15
REF_REXT_2
VDD_AL_19 VDD_AL_20 VDD_AL_21
VSS_11
K
VSS_12
VSS_27
VSS_41
VSS_56
VSS_72
VSS_86
VSS_98
VSS_112
VDD_51
VDD_67
REFCLK_P
REFCLK_N
VSS_131
VSS_13
VSS_28
VSS_42
VSS_57
VSS_73
VSS_87
VSS_99
VSS_113
VDD_52
VSS_14
VSS_29
VSS_43
VSS_58
VSS_74
VSS_88
VSS_100
VSS_114
VDD_53
VSS_15
VSS_30
VSS_44
VSS_59
VSS_75
VSS_89
VSS_101
VSS_115
VDD_54
VSS_16
VSS_31
VSS_45
VSS_60
VSS_76
VSS_90
VSS_102
VSS_116
VDD_55
VDD_71
VSS_126
VSS_145
VSS_135
VSS_17
VSS_32
VSS_46
VSS_61
VSS_77
VSS_91
VSS_103
VSS_117
VDD_56
REF_FILT_2
L
VSS_25
VSS_26
VDD_25
VDD_29
VDD_33
VDD_26
VDD_30
VDD_34
VDD_38
VDD_42
VDD_46
VSS_111
VDD_50
VDD_AH_31 VDD_AH_32 VDD_AH_33
M
N
P
VSS_53
VSS_71
VSS_54
VSS_55
RESERVED_24
P11_D0P
VDD_IO_7 VDD_37
VDD_IO_8 VDD_41
FAST_LINK_STATUS
SFP3_SD
/
GPIO_29
PHY11_LED0
R
PHY10_LED0
T
PHY9_LED0 PHY8_LED0 PHY7_LED0 VDD_IO_9 VDD_45
VDD_IO_10
U
PHY6_LED0 PHY5_LED0 PHY4_LED0 PHY3_LED0
VSS_110
VDD_49
PHY0_LED0
/ BASIC_SLED_DATA
PHY11_LED1
/ GPIO_16
VDD_IO_11
VDD_IO_12
VDD_IO_13
VDD_IO_14
VDD_IO_15
V
PHY2_LED0 PHY1_LED0
PHY10_LED1
/
GPIO_15
PHY9_LED1
/
GPIO_14
PHY8_LED1
/
GPIO_13
PHY7_LED1 / SFP_SERIALCLK1
W
Y
VDD_65
VDD_66
VDD_68
VDD_69
VDD_70
VDD_72
PHY6_LED1
/ SFP_SERIALCLK2 PHY5_LED1 / SFP_SERIALCLK3 PHY4_LED1 / CLK_SQUELCH_IN PHY3_LED1 / ESLED1_PULSE
SERDES7_TXP
SERDES6_TXP
SERDES_E3_TXP
SERDES5_TXP
SERDES4_TXP
SERDES_E2_TXP
PH Y0_LED 1 / ESLED 1_CLK / BASIC_SLED _CLK
PHY2_LED1
/ ESLED1_DO PHY1_LED1 / ESLED1_LD
SFP2_SD
/
GPIO_4
SERDES7_TXN
SERDES6_TXN
SERDES_E3_TXN
SERDES5_TXN
SERDES4_TXN
SERDES_E2_TXN
AA
AB
AC
AD
SFP1_SD
/
ESLED0_PULSE
/
GPIO_3
SFP0_SD
/
ESLED0_DO
/
GPIO_2
SFP_SERIALCLK0
/
ESLED0_CLK
SFP_SERIALDATA
/ ESLED0_LD
VSS_129
VSS_130
VSS_132
VSS_133
VSS_134
VSS_136
RESERVED_27 RESERVED_28
RESERVED_25 RESERVED_26
RCVRD_CLK0
VDD_IO_16 VDD_IO_17
VDD_IO_18
VSS_148
VDD_A_1 VDD_A_2 VDD_A_3 VDD_A_4 VDD_A_5 VDD_A_6 VDD_A_7 VDD_A_8
RCVRD_CLK1
VSS_149 VDD_VS_1 VDD_VS_2 VDD_VS_3 VDD_VS_4 VDD_VS_5 VDD_VS_6 VDD_VS_7 VDD_VS_8
SERDES7_RXP
SERDES6_RXP
RESERVED_22
SERDES_E3_RXP
SERDES5_RXP
SERDES4_RXP
SERDES_E2_RXP
SERDES_E2_RXN
VDD_IO_19
MDIO
AE VSS_151
VSS_163
MDC
VSS_152
VSS_158
VSS_153
VSS_159
SERDES7_RXN SERDES6_RXN RESERVED_23 SERDES_E3_RXN SERDES5_RXN SERDES4_RXN
VDD_IO_20
AF
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Pin Descriptions
Figure 39 • Pin Diagram, Right
14
15
16
17
18
19
20
21
22
23
24
25
26
P5_D0P
P5_D1P
P5_D2P
P5_D3P
P4_D0P
P4_D1P
P4_D2P
P4_D3P
P3_D0P
P3_D1P
P3_D2P
P3_D3P
A
B
P5_D0N
P5_D1N
P5_D2N
P5_D3N
P4_D0N
P4_D1N
P4_D2N
P4_D3N
P3_D0N
P3_D1N
P3_D2N
P3_D3N
P2_D0N
P2_D1N
P2_D2N
P2_D3N
P1_D0N
P1_D1N
P1_D2N
P1_D3N
P0_D0N
P0_D1N
P0_D2N
VSS_2
P2_D0P
P2_D1P
P2_D2P
P2_D3P
P1_D0P
P1_D1P
P1_D2P
P1_D3P
P0_D0P
P0_D1P
P0_D2P
REFCLK_SEL2
RESERVED_8
RESERVED_7
RESERVED_6
RESERVED_5 RESERVED_201 RESERVED_202 RESERVED_203 THERMDC_VSS
RESERVED_204
THERMDA
C
RESERVED_12 RESERVED_212
RESERVED_213 RESERVED_214 RESERVED_215
JTAG_TRST
VDD_AH_5 JTAG_CLK JTAG_DI
JTAG_DO JTAG_TMS
VDD_AH_14
D
RESERVED_217
REF_FILT_1 VDD_AH_12 VDD_AH_13
VDD_AH_15 VDD_AH_16
VDD_AL_3 VDD_AL_4
VDD_AL_7 VDD_AL_8
VDD_AL_11 VDD_AL_12
VDD_IO_3 VDD_IO_4
VDD_AH_6 VDD_IO_6
E
RESERVED_220
RESERVED_221
VDD_AH_22 VDD_AH_23
VDD_AH_24
VDD_8
VDD_AH_25 VDD_AH_26
F
RESERVED_223
RESERVED_10
VDD_6
VDD_7
VDD_9
VDD_10
VDD_24
VSS_5
VSS_9
VSS_6
G
RESERVED_225
RESERVED_11
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VSS_10
H
J
RESERVED_232 RESERVED_233 RESERVED_234 RESERVED_235 RESERVED_236 RESERVED_237
VDD_AL_16 VDD_AL_17 VDD_AL_18 VDD_AH_29 VDD_AH_30
REF_REXT_0
VDD_AL_22 VDD_AL_23 VDD_AL_24
VSS_24
VSS_18
VSS_33
VSS_47
VSS_62
VSS_78
VSS_92
VSS_104
VSS_118
VDD_57
VSS_19
VSS_34
VSS_48
VSS_63
VSS_79
VSS_93
VSS_105
VSS_119
VDD_58
VSS_20
VSS_35
VSS_49
VSS_64
VSS_80
VSS_94
VSS_106
VSS_120
VDD_59
VDD_75
VSS_127
VSS_146
VSS_139
VSS_21
VSS_36
VSS_50
VSS_65
VSS_81
VSS_95
VSS_107
VSS_121
VDD_60
VSS_22
VSS_37
VSS_51
VSS_66
VSS_82
VSS_96
VSS_108
VSS_122
VDD_61
VSS_23
VSS_38
VSS_52
VSS_67
VSS_83
VSS_97
VSS_109
VSS_123
VDD_62
K
REF_FILT_0
VDD_27
VDD_31
VDD_35
VDD_39
VDD_43
VDD_47
VSS_124
VDD_63
VDD_79
VSS_128
VSS_147
VSS_143
VDD_28
VDD_32
VDD_36
VDD_40
VDD_44
VDD_48
VSS_125
VDD_64
VSS_39
VSS_40
L
VDD_AH_34 VDD_AH_35 VDD_AH_36
M
N
P
VSS_68
VSS_69
VSS_70
VDD_IODDR_1
VSS_84
VSS_85
P0_D3N
P0_D3P
VDD_IODDR_2
VDD_IODDR_3
VDD_IODDR_4
VDD_IODDR_5
VDD_IODDR_6
VDD_IODDR_7
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
R
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
VDD_IODDR_11
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
VDD_IODDR_12
VDD_IODDR_14
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
VDD_IODDR_13
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
T
U
V
VDD_73
VDD_74
VDD_76
VDD_77
VDD_78
VDD_80
W
Y
SERDES3_TXP
SERDES2_TXP
SERDES_E1_TXP
SERDES1_TXP
SERDES0_TXP
SERDES_E0_TXP
SERDES3_TXN SERDES2_TXN
SERDES_E1_TXN
SERDES1_TXN
SERDES0_TXN
SERDES_E0_TXN VDD_IODDR_8
AA
AB
AC
AD
VDD_IODDR_9
VSS_137
VSS_138
VSS_140
VSS_141
VSS_142
VSS_144
VDD_IODDR_10
VDD_A_9 VDD_A_10 VDD_A_11 VDD_A_12 VDD_A_13 VDD_A_14 VDD_A_15 VDD_A_16
VDD_VS_10 VDD_VS_11 VDD_VS_12 VDD_VS_13 VDD_VS_14 VDD_VS_15 VDD_VS_16
VDD_VS_9
VSS_150
SERDES3_RXP
SERDES2_RXP
SERDES_E1_RXP
SERDES1_RXP
SERDES0_RXP
SERDES_E0_RXP
SERDES_E0_RXN
SERDES_REXT_0
VSS_154
VSS_160
VSS_155
VSS_161
VSS_156
VSS_162
VSS_157 AE
SERDES3_RXN SERDES2_RXN
SERDES_E1_RXN SERDES1_RXN SERDES0_RXN
SERDES_REXT_1
AF
7.2
Pins by Function
This section contains the functional pin descriptions for the VSC8512-02 device. The following table lists
the definitions for the pin type symbols.
Table 126 • Pin Type Symbol Definitions
Symbol Pin Type
Description
3V
3.3 V-tolerant pin.
Analog bias pin.
ABIAS
ADIFF
I
Analog bias
Analog differential Analog differential signal pair.
Input
Input without on-chip pull-up or pull-down resistor.
I/O
Bidirectional
No connect
Output
Bidirectional input or output signal.
No connect pins must be left floating.
Output signal.
NC
O
OD
OS
PD
Open drain
Open source
Pull-down
Open drain output.
Open source output.
On-chip pull-down resistor to VSS.
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
100
Pin Descriptions
Table 126 • Pin Type Symbol Definitions (continued)
Symbol Pin Type
Description
PU
ST
Pull-up
On-chip pull-up resistor to VDD_IO.
Input has Schmitt-trigger circuitry.
Schmitt-trigger
7.2.1
JTAG Pins
The following table shows the functional pins for the JTAG interface.
Table 127 • JTAG Pins
Name
Pin
Type
Description
JTAG_CLK
JTAG_DI
JTAG_DO
JTAG_TMS
D17
D18
D19
D20
I, PU, ST, 3V JTAG clock pin
I, PU, ST, 3V JTAG data input pin
O
JTAG data output pin
I, PU, ST, 3V JTAG test mode select pin
I, PU, ST, 3V JTAG reset pin
JTAG_TRST D21
7.2.2
LED and Multi/General Purpose Input and Output Pins
The following table lists the descriptions for the multifunction LED pins, the multipurpose pins, and the
general purpose input/output (GPIO) pins. For more information about configuring these pins, see LED
Interface, page 21, and Table 93, page 80.
Table 128 • LED, Multipurpose, and GPIO Pins
Name
Pin
Type
Description
PHY[1:11]_LED0
V2, V1, U4,
U3, U2, U1,
T4, T3, T2,
R4
I/O, PU, 3V
LED direct-drive output
PHY0_LED0 / BASIC_SLED_DATA V3
I/O, PU, 3V
I/O, PU, 3V
LED direct-drive output
Basic serial LED data
PHY0_LED1 / ESLED1_CLK /
BASIC_SLED_CLK
AA3
LED direct-drive output
Enhanced serial LED clock
Basic serial LED clock
PHY1_LED1 / ESLED1_LD
AA2
AA1
Y4
I/O, PU, 3V
I/O, PU, 3V
I/O, PU, 3V
I/O, PU, 3V
I/O, PU, 3V
I/O, PU, 3V
I/O, PU, 3V
LED direct-drive output
Enhanced serial LED load
PHY2_LED1 / ESLED1_DO
LED direct-drive output
Enhanced serial LED data
PHY3_LED1 / ESLED1_PULSE
PHY4_LED1 / CLK_SQUELCH_IN
PHY5_LED1 / SFP_SERIALCLK3
PHY6_LED1 / SFP_SERIALCLK2
PHY7_LED1 / SFP_SERIALCLK1
LED direct-drive output
Enhanced serial LED pulse
Y3
LED direct-drive output
Clock squelch input
Y2
LED direct-drive output
SFP serial clock
Y1
LED direct-drive output
SFP serial clock
W4
LED direct-drive output
SFP serial clock
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
101
Pin Descriptions
Table 128 • LED, Multipurpose, and GPIO Pins (continued)
Name
Pin
Type
Description
PHY8_LED1 / GPIO_13
W3
I/O, PU, 3V
LED direct-drive output
General purpose I/O
PHY9_LED1 / GPIO_14
PHY10_LED1 / GPIO_15
PHY11_LED1 / GPIO_16
W2
W1
V4
I/O, PU, 3V
I/O, PU, 3V
I/O, PU, 3V
I/O, PU, 3V
I/O, PU, 3V
I/O, PU, 3V
LED direct-drive output
General purpose I/O
LED direct-drive output
General purpose I/O
LED direct-drive output
General purpose I/O
SFP_SERIALCLK0 / ESLED0_CLK AB4
SFP serial clock
Enhanced serial LED clock
SFP_SERIALDATA / ESLED0_LD
SFP0_SD / ESLED0_DO / GPIO_2
AB3
AB2
SFP serial data
Enhanced serial LED load
SFP Signal Detect
Enhanced serial LED data
General purpose I/O
SFP1_SD / ESLED0_PULSE /
GPIO_3
AB1
I/O, PU, 3V
SFP Signal Detect
Enhanced serial LED pulse
General purpose I/O
SFP2_SD / GPIO_4
SFP3_SD / GPIO_29
AA4
R3
I/O, PU, 3V
I/O, PU, 3V
SFP Signal Detect
General purpose I/O
SFP Signal Detect
General purpose I/O
7.2.3
MAC SerDes/QSGMII Interface Pins
The following table shows the functional pins for the MAC SerDes/QSGMII interface.
Table 129 • MAC SerDes Interface Pins
Name
Pin
Type
Description
SERDES_E[0:3]_RXN AF21, AF17, AF13, AF9
SERDES_E[0:3]_RXP AE21, AE17, AE13, AE9
SERDES_E[0:3]_TXN AA21, AA17, AA13, AA9
SERDES_E[0:3]_TXP Y21, Y17, Y13, Y9
SERDES_REXT_[0:1] AE22, AF22
ADIFF Enhanced SerDes receive
negative polarity pins
ADIFF Enhanced SerDes receive
positive polarity pins
ADIFF Enhanced SerDes transmit
negative polarity pins
ADIFF Enhanced SerDes transmit
positive polarity pins
ABIAS SerDes bias pins
SERDES[0:7]_RXN
SERDES[0:7]_RXP
SERDES[0:7]_TXN
SERDES[0:7]_TXP
AF19, AF18, AF15, AF14,
AF11, AF10, AF7, AF6
ADIFF SerDes receive negative
polarity pins
AE19, AE18, AE15, AE14,
AE11, AE10, AE7, AE6
ADIFF SerDes receive positive
polarity pins
AA19, AA18, AA15, AA14,
AA11, AA10, AA7, AA6
ADIFF SerDes transmit negative
polarity pins
Y19, Y18, Y15, Y14,
Y11, Y10, Y7, Y6
ADIFF SerDes transmit positive
polarity pins
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
102
Pin Descriptions
7.2.4
Miscellaneous Pins
The following table shows the miscellaneous pins.
Table 130 • Miscellaneous Pins
Name
Pin
Type
I/O
Description
FAST_LINK_STATUS
PHYADD[3:4]
RCVRD_CLK[0:1]
R1
Fast link failure indication.
PHY address range select.
C7, C8
AE2, AD3
I, PD
O
Recovered clock frequency select.
These pins are not active when
NRESET is asserted. Clock outputs
can be enabled or disabled using
registers 23G and 24G. When
disabled, the pin is held low.
000: 25 MHz output clock
001: 125 MHz output clock
010: 31.25 MHz output clock
REFCLK_N
REFCLK_P
AA8
Y8
I, ADIFF Reference clock input. The input can
be either differential or single-ended.
In differential mode, REFCLK_P is the
true part of the differential signal, and
REFCLK_N is the complement part of
the differential signal. In single-ended
mode, REFCLK_P is used as single-
ended LVTTL input, and the
REFCLK_N should be pulled to
VDD_A. Required applied frequency
depends on REFCLK_SEL[2:0] input
state.
REFCLK_SEL[0:2]
C12, C13, C14
I, PD
Reference clock frequency select.
0: Connect to pull-down or leave
floating.
1: Connect to pull-up to VDD_IO.
000: 125 MHz (default).
001: 156.25 MHz.
100: 25 MHz.
RESERVED_5
C18
I/O
Connect to VDD_IO for correct
functioning of fiber media ports.
THERMDA
C23
C22
A
A
Thermal diode anode.
Thermal diode cathode.
THERMDC_VSS
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
103
Pin Descriptions
7.2.5
No Connect and Reserved Pins
The following table lists the reserved pins. Not all of the pins are labeled “reserved,” but all pins listed
should not be connected.
Table 131 • No Connect and Reserved
Name
Pin
Type Description
NO CONNECT
AA23, AA24, AA25, AA26, AB23, AB24,
AB25, AB26, AC23, AC24, AC25, AC26,
AD24, AD25, AD26, AE25, C5, R23, R24,
R25, R26, T23, T24, T25, T26, U23, U24,
U25, U26, V23, V24, V25, V26, W23, W24,
W25, W26, Y23, Y24, Y25, Y26
NC
Reserved. Leave
unconnected.
RESERVED_[3:4]
RESERVED_[6:8]
RESERVED_[10:15]
RESERVED_[22:29]
C9, C11
NC
NC
NC
NC
NC
Reserved. Leave
unconnected.
C17, C16, C15
Reserved. Leave
unconnected.
G23, H23, D14, D13, H4, G4
AE8, AF8, P4, AD1, AD2, AC1, AC2, C10
Reserved. Leave
unconnected.
Reserved. Leave
unconnected.
RESERVED_[201:209] C19, C20, C21, C24, D3, D6, D7, D8, D9
Reserved. Leave
unconnected.
RESERVED_[211:221] D12, D15, D22, D23, D24, E3, E24, F3, F13, NC
F14, F24
Reserved. Leave
unconnected.
RESERVED_223
G14
NC
NC
NC
NC
Reserved. Leave
unconnected.
RESERVED_225
H14
Reserved. Leave
unconnected.
RESERVED_[232:237] J14, J15, J16, J17, J18, J19
Reserved. Leave
unconnected.
RESERVED_[240:248] J8, J9, J10, J11, J12, J13, H13, G13, D10
Reserved. Leave
unconnected.0
7.2.6
Power Supply Pins
The following table lists the power supply pins. All power supply pins must be connected to their
respective voltage input, even though certain pin functions may not be used for a specific application.
Table 132 • Power Supply Pins
Name
Pin
Type Description
VDD_[1:80]
G6, G7, G8, G11, G12, G15, G16, G19, G20, 1.0V Connect to 1.0 V
G21, H6, H7, H8, H9, H10, H11, H12, H15,
H16, H17, H18, H19, H20, H21, L6, L7, L20,
L21, M6, M7, M20, M21, N6, N7, N20, N21,
P6, P7, P20, P21, R6, R7, R20, R21, T6, T7,
T20, T21, V6, V7, V8, V9, V10, V11, V12,
V13, V14, V15, V16, V17, V18, V19, V20,
V21, W6, W7, W8, W9, W10, W11, W12,
W13, W14, W15, W16, W17, W18, W19,
W20, W21
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
104
Pin Descriptions
Table 132 • Power Supply Pins (continued)
Name
Pin
Type Description
VDD_A_[1:16]
AC6, AC7, AC8, AC9, AC10, AC11, AC12,
AC13, AC14, AC15, AC16, AC17, AC18,
AC19, AC20, AC21
1.0V Analog SerDes 1.0 V
VDD_AH_[1:36]
D4, D5, D11, D16, E4, E5, E8, E11, E12,
E15, E16, E19, E22, E23, F4, F5, F7, F8,
F11, F12, F15, F16, F19, F20, F22, F23, J3,
J4, J23, J24, M3, M4, M5, M22, M23, M24
2.5V Analog 2.5 V
VDD_AL_[1:24]
VDD_IO_[1:20]
E9, E10, E17, E18, F9, F10, F17, F18, G9, 1.0V Analog 1.0 V
G10, G17, G18, J5, J6, J7, J20, J21, J22,
K5, K6, K7, K20, K21, K22
E6, E7, E20, E21, F6, F21, P5, R5, T5, U5, 2.5V Connect to 2.5 V
V5, W5, Y5, AA5, AB5, AC4, AC5, AD4,
AE3, AF2
VDD_IODDR_[1:14] P22, R22, T22, U22, V22, W22, Y22, AA22, 0V
Ground
AB22, AC22, AD23, AE24, AF25, AF24
VDD_VS_[1:16]
AD6, AD7, AD8, AD9, AD10, AD11, AD12,
AD13, AD14, AD15, AD16, AD17, AD18,
AD19, AD20, AD21
1.0V Analog SerDes 1.0 V
VSS
C6
0V
0V
Ground
Ground
VSS_[1:163]
B1, B26, G3, G5, G22, G24, H3, H5, H22,
H24, K3, K8, K9, K10, K11, K12, K13, K14,
K15, K16, K17, K18, K19, K24, L3, L5, L8,
L9, L10, L11, L12, L13, L14, L15, L16, L17,
L18, L19, L22, L24, M8, M9, M10, M11, M12,
M13, M14, M15, M16, M17, M18, M19, N3,
N4, N5, N8, N9, N10, N11, N12, N13, N14,
N15, N16, N17, N18, N19, N22, N23, N24,
P3, P8, P9, P10, P11, P12, P13, P14, P15,
P16, P17, P18, P19, P23, P24, R8, R9, R10,
R11, R12, R13, R14, R15, R16, R17, R18,
R19, T8, T9, T10, T11, T12, T13, T14, T15,
T16, T17, T18, T19, U6, U7, U8, U9, U10,
U11, U12, U13, U14, U15, U16, U17, U18,
U19, U20, U21, Y12, Y16, Y20, AB6, AB7,
AB8, AB9, AB10, AB11, AB12, AB13, AB14,
AB15, AB16, AB17, AB18, AB19, AB20,
AB21, AA12, AA16, AA20, AC3, AD5, AD22,
AE1, AE5, AE12, AE16, AE20, AE23, AE26,
AF5, AF12, AF16, AF20, AF23, AE4
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
105
Pin Descriptions
7.2.7
Serial Management Interface Pins
The following table shows the functional pins for the serial management interface.
Table 133 • Serial Management Interface Pins
Name
Pin
Type
Description
COMA_MOD C3
E
I/O, PU, ST, 3V When this pin is asserted high, all PHYs are held in a
powered down state. When this pin is deasserted low, all
PHYs are powered up and resume normal operation.
This signal is also used to synchronize the operation of
multiple chips on the same PCB to provide visual
synchronization for LEDs driven from the separate chips.
MDC
AF4
I
Management data clock pin.
Management interrupt signal.
Management data input/output pin.
Device reset pin, active low.
MDINT
MDIO
R2
I/O, OS, OD
I/O, OD
I, PD, ST, 3V
AF3
C4
nRESET
7.2.8
Twisted Pair Interface Pins
The following table shows the functional pins for the twisted pair interface.
Table 134 • Twisted Pair Interface Pins
Name
Pin
Type
Description
P0_D[0:3]N
P0_D[0:3]P
P[0:11]_D0N
L25, M25, N25, P25 ADIFF Connects to RJ45 Pin 2 through a magnetic.
L26, M26, N26, P26 ADIFF Connects to RJ45 Pin 1 through a magnetic.
L25, G25, C25, B22, ADIFF Connects to RJ45 Pin 2 through a magnetic.
B18, B14, B10, B6,
B2, F2, K2, P2
P[0:11]_D0P
P[0:11]_D1N
P[0:11]_D1P
P[0:11]_D2N
P[0:11]_D2P
P[0:11]_D3N
P[0:11}_D3P
L26, G26, C26, A22, ADIFF Connects to RJ45 Pin 1 through a magnetic.
A18, A14, A10, A6,
A2, F1, K1, P1
M25, H25, D25, B23, ADIFF Connects to RJ45 Pin 6 through a magnetic.
B19, B15, B11, B7,
B3, E2, J2, N2
M26, H26, D26, A23, ADIFF Connects to RJ45 Pin 3 through a magnetic.
A19, A15, A11, A7,
A3, E1, J1, N1
N25, J25, E25, B24, ADIFF Connects to RJ45 Pin 5 through a magnetic.
B20, B16, B12, B8,
B4, D2, H2, M2
N26 J26, E26, A24, ADIFF Connects to RJ45 Pin 4 through a magnetic.
A20, A16, A12, A8,
A4, D1, H1, M1
P25, K25, F25, B25, ADIFF Connect to RJ45 pin 8 through a magnetic.
B21, B17, B13, B9,
B5, C2, G2, L2
P26, K26, F26, A25, ADIFF Connects to RJ45 pin 7 through a magnetic.
A21, A17, A13, A9,
A5, C1, G1, L1
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
106
Pin Descriptions
Table 134 • Twisted Pair Interface Pins (continued)
Name Pin Type Description
REF_FILT_[2:0] 18, 148, 193
ABIAS Copper media reference filter pins. Connect
each of these pins to one external 1 µF
capacitor each and then all going to ground.
REF_REXT_[2:0] 19, 149, 194
ABIAS Copper media reference external pins.
Connect each of these pins to one external
2.0 kΩ (1%) resistor each and then all going to
ground.
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
107
12-Port 10/100/1000BASE-T PHY with QSGMII MAC
7.3
Pins by Number
This section provides a numeric list of the VSC8512-02 pins.
AA13 SERDES_E2_TXN
AA14 SERDES3_TXN
AA15 SERDES2_TXN
AA16 VSS_146
A2
P8_D0P
P8_D1P
P8_D2P
P8_D3P
P7_D0P
P7_D1P
P7_D2P
P7_D3P
P6_D0P
P6_D1P
P6_D2P
P6_D3P
P5_D0P
P5_D1P
P5_D2P
P5_D3P
P4_D0P
P4_D1P
P4_D2P
P4_D3P
P3_D0P
P3_D1P
P3_D2P
P3_D3P
PHY2_LED1 / ESLED1_DO
A3
AA17 SERDES_E1_TXN
AA18 SERDES1_TXN
AA19 SERDES0_TXN
AA20 VSS_147
A4
A5
A6
A7
AA21 SERDES_E0_TXN
AA22 VDD_IODDR_8
AA23 NO CONNECT
AA24 NO CONNECT
AA25 NO CONNECT
AA26 NO CONNECT
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
SFP1_SD / ESLED0_PULSE /
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
SFP0_SD / ESLED0_DO / GPIO_2
SFP_SERIALDATA / ESLED0_LD
SFP_SERIALCLK0 / ESLED0_CLK
VDD_IO_15
VSS_129
VSS_130
VSS_131
VSS_132
AB10 VSS_133
AB11 VSS_134
AB12 VSS_135
AB13 VSS_136
AB14 VSS_137
AB15 VSS_138
AB16 VSS_139
AB17 VSS_140
AB18 VSS_141
AB19 VSS_142
AB20 VSS_143
AB21 VSS_144
AB22 VDD_IODDR_9
AB23 NO CONNECT
AB24 NO CONNECT
PHY1_LED1 / ESLED1_LD
PHY0_LED1 / ESLED1_CLK / BASIC_SLED_CLK
SFP2_SD / GPIO_4
VDD_IO_14
SERDES7_TXN
SERDES6_TXN
REFCLK_N
SERDES_E3_TXN
AA10 SERDES5_TXN
AA11 SERDES4_TXN
AA12 VSS_145
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
108
Pins by number (continued)
AB25 NO CONNECT
AB26 NO CONNECT
AD11 VDD_VS_6
AD12 VDD_VS_7
AD13 VDD_VS_8
AD14 VDD_VS_9
AD15 VDD_VS_10
AD16 VDD_VS_11
AD17 VDD_VS_12
AD18 VDD_VS_13
AD19 VDD_VS_14
AD20 VDD_VS_15
AD21 VDD_VS_16
AD22 VSS_150
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
RESERVED_27
RESERVED_28
VSS_148
VDD_IO_16
VDD_IO_17
VDD_A_1
VDD_A_2
VDD_A_3
VDD_A_4
AC10 VDD_A_5
AC11 VDD_A_6
AD23 VDD_IODDR_11
AD24 NO CONNECT
AD25 NO CONNECT
AD26 NO CONNECT
AC12 VDD_A_7
AC13 VDD_A_8
AC14 VDD_A_9
AC15 VDD_A_10
AC16 VDD_A_11
AC17 VDD_A_12
AC18 VDD_A_13
AC19 VDD_A_14
AC20 VDD_A_15
AC21 VDD_A_16
AC22 VDD_IODDR_10
AC23 NO CONNECT
AC24 NO CONNECT
AC25 NO CONNECT
AC26 NO CONNECT
AD1 RESERVED_25
AD2 RESERVED_26
AD3 RCVRD_CLK1
AD4 VDD_IO_18
AD5 VSS_149
AE1
AE2
AE3
AE4
AE5
AE6
AE7
AE8
AE9
VSS_151
RCVRD_CLK0
VDD_IO_19
VSS_163
VSS_152
SERDES7_RXP
SERDES6_RXP
RESERVED_22
SERDES_E3_RXP
AE10 SERDES5_RXP
AE11 SERDES4_RXP
AE12 VSS_153
AE13 SERDES_E2_RXP
AE14 SERDES3_RXP
AE15 SERDES2_RXP
AE16 VSS_154
AE17 SERDES_E1_RXP
AE18 SERDES1_RXP
AE19 SERDES0_RXP
AE20 VSS_155
AD6 VDD_VS_1
AD7 VDD_VS_2
AD8 VDD_VS_3
AD9 VDD_VS_4
AD10 VDD_VS_5
AE21 SERDES_E0_RXP
AE22 SERDES_REXT_0
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
109
Pins by number (continued)
AE23 VSS_156
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C1
P6_D1N
AE24 VDD_IODDR_12
AE25 NO CONNECT
AE26 VSS_157
P6_D2N
P6_D3N
P5_D0N
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
VDD_IO_20
MDIO
P5_D1N
P5_D2N
MDC
P5_D3N
VSS_158
P4_D0N
SERDES7_RXN
SERDES6_RXN
RESERVED_23
SERDES_E3_RXN
P4_D1N
P4_D2N
P4_D3N
P3_D0N
AF10 SERDES5_RXN
AF11 SERDES4_RXN
AF12 VSS_159
P3_D1N
P3_D2N
P3_D3N
AF13 SERDES_E2_RXN
AF14 SERDES3_RXN
AF15 SERDES2_RXN
AF16 VSS_160
VSS_2
P9_D3P
C2
P9_D3N
C3
COMA_MODE
NRESET
AF17 SERDES_E1_RXN
AF18 SERDES1_RXN
AF19 SERDES0_RXN
AF20 VSS_161
C4
C5
NO CONNECT
VSS
C6
C7
PHYADD3
PHYADD4
RESERVED_3
RESERVED_29
RESERVED_4
REFCLK_SEL0
REFCLK_SEL1
REFCLK_SEL2
RESERVED_8
RESERVED_7
RESERVED_6
RESERVED_5
RESERVED_201
RESERVED_202
RESERVED_203
THERMDC_VSS
AF21 SERDES_E0_RXN
AF22 SERDES_REXT_1
AF23 VSS_162
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
AF24 VDD_IODDR_14
AF25 VDD_IODDR_13
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
VSS_1
P8_D0N
P8_D1N
P8_D2N
P8_D3N
P7_D0N
P7_D1N
P7_D2N
P7_D3N
P6_D0N
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
110
Pins by number (continued)
C23
C24
C25
C26
D1
THERMDA
E9
VDD_AL_1
VDD_AL_2
VDD_AH_10
VDD_AH_11
REF_REXT_1
REF_FILT_1
VDD_AH_12
VDD_AH_13
VDD_AL_3
VDD_AL_4
VDD_AH_14
VDD_IO_3
RESERVED_204
P2_D0N
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
F1
P2_D0P
P9_D2P
D2
P9_D2N
D3
RESERVED_205
VDD_AH_1
VDD_AH_2
RESERVED_206
RESERVED_207
RESERVED_208
RESERVED_209
RESERVED_248
VDD_AH_4
RESERVED_211
RESERVED_13
RESERVED_12
RESERVED_212
VDD_AH_5
JTAG_CLK
D4
D5
D6
D7
D8
D9
VDD_IO_4
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
E1
VDD_AH_15
VDD_AH_16
RESERVED_217
P2_D2N
P2_D2P
P9_D0P
F2
P9_D0N
F3
RESERVED_218
VDD_AH_17
VDD_AH_18
VDD_IO_5
JTAG_DI
F4
JTAG_DO
F5
JTAG_TMS
F6
JTAG_TRST
RESERVED_213
RESERVED_214
RESERVED_215
P2_D1N
F7
VDD_AH_3
VDD_AH_19
VDD_AL_5
VDD_AL_6
VDD_AH_20
VDD_AH_21
RESERVED_219
RESERVED_220
VDD_AH_22
VDD_AH_23
VDD_AL_7
VDD_AL_8
VDD_AH_24
VDD_AH_6
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
P2_D1P
P9_D1P
E2
P9_D1N
E3
RESERVED_216
VDD_AH_7
VDD_AH_8
VDD_IO_1
E4
E5
E6
E7
VDD_IO_2
E8
VDD_AH_9
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
111
Pins by number (continued)
F21
F22
F23
F24
F25
F26
G1
VDD_IO_6
H7
VDD_12
VDD_AH_25
VDD_AH_26
RESERVED_221
P2_D3N
H8
VDD_13
H9
VDD_14
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
J1
VDD_15
VDD_16
P2_D3P
VDD_17
P10_D3P
P10_D3N
VSS_3
RESERVED_246
RESERVED_225
VDD_18
G2
G3
G4
RESERVED_15
VSS_4
VDD_19
G5
VDD_20
G6
VDD_1
VDD_21
G7
VDD_2
VDD_22
G8
VDD_3
VDD_23
G9
VDD_AL_9
VDD_AL_10
VDD_4
VDD_24
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
H1
VSS_9
RESERVED_11
VSS_10
VDD_5
RESERVED_247
RESERVED_223
VDD_6
P1_D1N
P1_D1P
P10_D1P
VDD_7
J2
P10_D1N
VDD_AL_11
VDD_AL_12
VDD_8
J3
VDD_AH_27
VDD_AH_28
VDD_AL_13
VDD_AL_14
VDD_AL_15
RESERVED_240
RESERVED_241
RESERVED_242
RESERVED_243
RESERVED_244
RESERVED_245
RESERVED_232
RESERVED_233
RESERVED_234
RESERVED_235
RESERVED_236
J4
J5
VDD_9
J6
VDD_10
J7
VSS_5
J8
RESERVED_10
VSS_6
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
P1_D0N
P1_D0P
P10_D2P
P10_D2N
VSS_7
H2
H3
H4
RESERVED_14
VSS_8
H5
H6
VDD_11
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
112
Pins by number (continued)
J19
J20
J21
J22
J23
J24
J25
J26
K1
RESERVED_237
L5
VSS_26
VDD_25
VDD_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VDD_27
VDD_28
VSS_39
REF_FILT_0
VSS_40
P0_D0N
P0_D0P
VDD_AL_16
VDD_AL_17
VDD_AL_18
VDD_AH_29
VDD_AH_30
P1_D2N
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
M1
M2
M3
M4
M5
M6
M7
M8
M9
P1_D2P
P10_D0P
P10_D0N
VSS_11
K2
K3
K4
REF_REXT_2
VDD_AL_19
VDD_AL_20
VDD_AL_21
VSS_12
K5
K6
K7
K8
K9
VSS_13
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
L1
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
P11_D2P
P11_D2N
VDD_AH_31
VDD_AH_32
VDD_AH_33
VDD_29
VDD_30
VSS_41
VSS_42
VSS_20
VSS_21
VSS_22
VSS_23
VDD_AL_22
VDD_AL_23
VDD_AL_24
REF_REXT_0
VSS_24
M10 VSS_43
M11 VSS_44
M12 VSS_45
M13 VSS_46
M14 VSS_47
M15 VSS_48
M16 VSS_49
P1_D3N
P1_D3P
P11_D3P
P11_D3N
VSS_25
L2
L3
L4
REF_FILT_2
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
113
Pins by number (continued)
M17 VSS_50
M18 VSS_51
M19 VSS_52
M20 VDD_31
M21 VDD_32
P3
VSS_71
P4
RESERVED_24
VDD_IO_7
VDD_37
P5
P6
P7
VDD_38
M22 VDD_AH_34
M23 VDD_AH_35
M24 VDD_AH_36
M25 P0_D1N
P8
VSS_72
P9
VSS_73
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
R1
VSS_74
VSS_75
M26 P0_D1P
VSS_76
N1
P11_D1P
P11_D1N
VSS_53
VSS_54
VSS_55
VDD_33
VDD_34
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VDD_35
VDD_36
VSS_68
VSS_69
VSS_70
P0_D2N
P0_D2P
P11_D0P
P11_D0N
VSS_77
N2
VSS_78
N3
VSS_79
N4
VSS_80
N5
VSS_81
N6
VSS_82
N7
VSS_83
N8
VDD_39
N9
VDD_40
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
P1
VDD_IODDR_1
VSS_84
VSS_85
P0_D3N
P0_D3P
FAST_LINK_STATUS
MDINT
R2
R3
SFP3_SD / GPIO_29
PHY11_LED0
VDD_IO_8
VDD_41
R4
R5
R6
R7
VDD_42
R8
VSS_86
R9
VSS_87
R10
R11
R12
R13
R14
VSS_88
VSS_89
VSS_90
VSS_91
P2
VSS_92
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
114
Pins by number (continued)
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
T1
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VDD_43
VDD_44
U1
PHY6_LED0
PHY5_LED0
PHY4_LED0
PHY3_LED0
VDD_IO_10
VSS_110
U2
U3
U4
U5
U6
U7
VSS_111
VDD_IODDR_2
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
PHY10_LED0
PHY9_LED0
PHY8_LED0
PHY7_LED0
VDD_IO_9
VDD_45
U8
VSS_112
U9
VSS_113
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
V1
VSS_114
VSS_115
VSS_116
VSS_117
T2
VSS_118
T3
VSS_119
T4
VSS_120
T5
VSS_121
T6
VSS_122
T7
VDD_46
VSS_123
T8
VSS_98
VSS_124
T9
VSS_99
VSS_125
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
VSS_100
VDD_IODDR_4
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
PHY2_LED0
PHY1_LED0
PHY0_LED0 / BASIC_SLED_DATA
PHY11_LED1 / GPIO_16
VDD_IO_11
VDD_49
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
V2
VSS_107
V3
VSS_108
V4
VSS_109
V5
VDD_47
V6
VDD_48
V7
VDD_50
VDD_IODDR_3
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
V8
VDD_51
V9
VDD_52
V10
V11
V12
VDD_53
VDD_54
VDD_55
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
115
Pins by number (continued)
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
W1
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
W25 NO CONNECT
W26 NO CONNECT
PHY6_LED1 / SFP_SERIALCLK2
Y1
PHY5_LED1 / SFP_SERIALCLK3
PHY4_LED1 / CLK_SQUELCH_IN
PHY3_LED1 / ESLED1_PULSE
VDD_IO_13
Y2
Y3
Y4
Y5
Y6
SERDES7_TXP
SERDES6_TXP
REFCLK_P
Y7
VDD_IODDR_5
NO CONNECT
Y8
Y9
SERDES_E3_TXP
SERDES5_TXP
SERDES4_TXP
VSS_126
NO CONNECT
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
NO CONNECT
NO CONNECT
PHY10_LED1 / GPIO_15
PHY9_LED1 / GPIO_14
PHY8_LED1 / GPIO_13
PHY7_LED1 / SFP_SERIALCLK1
VDD_IO_12
SERDES_E2_TXP
SERDES3_TXP
SERDES2_TXP
VSS_127
W2
W3
W4
W5
SERDES_E1_TXP
SERDES1_TXP
SERDES0_TXP
VSS_128
W6
VDD_65
W7
VDD_66
W8
VDD_67
W9
VDD_68
SERDES_E0_TXP
VDD_IODDR_7
NO CONNECT
W10 VDD_69
W11 VDD_70
W12 VDD_71
W13 VDD_72
W14 VDD_73
W15 VDD_74
W16 VDD_75
W17 VDD_76
W18 VDD_77
W19 VDD_78
W20 VDD_79
W21 VDD_80
W22 VDD_IODDR_6
W23 NO CONNECT
W24 NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
116
12-Port 10/100/1000BASE-T PHY with QSGMII MAC
7.4
Pins by Name
This section provides an alphabetical list of the VSC8512-02 pins.
NO CONNECT
NO CONNECT
U24
U25
U26
V23
V24
V25
V26
W23
W24
W25
W26
Y23
Y24
Y25
Y26
C4
NO CONNECT
C3
COMA_MODE
NO CONNECT
FAST_LINK_STATUS
JTAG_CLK
R1
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NRESET
D17
D18
D19
D20
D21
AF4
JTAG_DI
JTAG_DO
JTAG_TMS
JTAG_TRST
MDC
MDINT
R2
MDIO
AF3
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
NO CONNECT
AA23
AA24
AA25
AA26
AB23
AB24
AB25
AB26
AC23
AC24
AC25
AC26
AD24
AD25
AD26
AE25
C5
P0_D0N
L25
L26
M25
M26
N25
N26
P25
P26
G25
G26
H25
H26
J25
J26
K25
K26
K2
P0_D0P
P0_D1N
P0_D1P
P0_D2N
P0_D2P
P0_D3N
P0_D3P
P1_D0N
P1_D0P
P1_D1N
P1_D1P
P1_D2N
P1_D2P
R23
P1_D3N
R24
P1_D3P
R25
P10_D0N
P10_D0P
R26
K1
T23
P10_D1N
P10_D1P
J2
T24
J1
T25
P10_D2N
P10_D2P
H2
T26
H1
U23
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
117
Pins by name (continued)
P10_D3N
P10_D3P
P11_D0N
P11_D0P
P11_D1N
P11_D1P
P11_D2N
P11_D2P
P11_D3N
P11_D3P
P2_D0N
P2_D0P
P2_D1N
P2_D1P
P2_D2N
P2_D2P
P2_D3N
P2_D3P
P3_D0N
P3_D0P
P3_D1N
P3_D1P
P3_D2N
P3_D2P
P3_D3N
P3_D3P
P4_D0N
P4_D0P
P4_D1N
P4_D1P
P4_D2N
P4_D2P
P4_D3N
P4_D3P
P5_D0N
P5_D0P
P5_D1N
P5_D1P
G2
P5_D2N
B16
A16
B17
A17
B10
A10
B11
A11
B12
A12
B13
A13
B6
G1
P5_D2P
P2
P5_D3N
P1
P5_D3P
N2
P6_D0N
N1
P6_D0P
M2
P6_D1N
M1
P6_D1P
L2
P6_D2N
L1
P6_D2P
C25
C26
D25
D26
E25
E26
F25
F26
B22
A22
B23
A23
B24
A24
B25
A25
B18
A18
B19
A19
B20
A20
B21
A21
B14
A14
B15
A15
P6_D3N
P6_D3P
P7_D0N
P7_D0P
A6
P7_D1N
B7
P7_D1P
A7
P7_D2N
B8
P7_D2P
A8
P7_D3N
B9
P7_D3P
A9
P8_D0N
B2
P8_D0P
A2
P8_D1N
B3
P8_D1P
A3
P8_D2N
B4
P8_D2P
A4
P8_D3N
B5
P8_D3P
A5
P9_D0N
F2
P9_D0P
F1
P9_D1N
E2
P9_D1P
E1
P9_D2N
D2
D1
C2
P9_D2P
P9_D3N
P9_D3P
C1
PHY0_LED0 / BASIC_SLED_DATA
PHY0_LED1 / ESLED1_CLK / BASIC_SLED_CLK
V3
AA3
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
118
Pins by name (continued)
PHY1_LED0
V2
RESERVED_4
C11
C18
C17
C16
C15
G23
H23
D14
D13
H4
PHY1_LED1 / ESLED1_LD
PHY10_LED0
AA2
T1
RESERVED_5
RESERVED_6
PHY10_LED1 / GPIO_15
PHY11_LED0
W1
R4
RESERVED_7
RESERVED_8
PHY11_LED1 / GPIO_16
PHY2_LED0
V4
RESERVED_10
RESERVED_11
RESERVED_12
RESERVED_13
RESERVED_14
RESERVED_15
RESERVED_22
RESERVED_23
RESERVED_24
RESERVED_25
RESERVED_26
RESERVED_27
RESERVED_28
RESERVED_29
RESERVED_211
RESERVED_212
RESERVED_213
RESERVED_214
RESERVED_215
RESERVED_216
RESERVED_217
RESERVED_218
RESERVED_219
RESERVED_220
RESERVED_221
RESERVED_223
RESERVED_225
RESERVED_232
RESERVED_233
RESERVED_234
RESERVED_235
RESERVED_236
RESERVED_237
V1
PHY2_LED1 / ESLED1_DO
PHY3_LED0
AA1
U4
PHY3_LED1 / ESLED1_PULSE
PHY4_LED0
Y4
U3
G4
PHY4_LED1 / CLK_SQUELCH_IN
PHY5_LED0
Y3
AE8
AF8
P4
U2
PHY5_LED1 / SFP_SERIALCLK3
PHY6_LED0
Y2
U1
AD1
AD2
AC1
AC2
C10
D12
D15
D22
D23
D24
E3
PHY6_LED1 / SFP_SERIALCLK2
PHY7_LED0
Y1
T4
PHY7_LED1 / SFP_SERIALCLK1
PHY8_LED0
W4
T3
PHY8_LED1 / GPIO_13
PHY9_LED0
W3
T2
PHY9_LED1 / GPIO_14
PHYADD3
W2
C7
PHYADD4
C8
RCVRD_CLK0
AE2
AD3
L23
E14
L4
RCVRD_CLK1
E24
F3
REF_FILT_0
REF_FILT_1
F13
F14
F24
G14
H14
J14
J15
J16
J17
J18
J19
REF_FILT_2
REF_REXT_0
K23
E13
K4
REF_REXT_1
REF_REXT_2
REFCLK_N
AA8
Y8
REFCLK_P
REFCLK_SEL0
C12
C13
C14
C9
REFCLK_SEL1
REFCLK_SEL2
RESERVED_3
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
119
Pins by name (continued)
RESERVED_240
RESERVED_241
RESERVED_242
RESERVED_243
RESERVED_244
RESERVED_245
RESERVED_246
RESERVED_247
RESERVED_248
RESERVED_201
RESERVED_202
RESERVED_203
RESERVED_204
RESERVED_205
RESERVED_206
RESERVED_207
RESERVED_208
RESERVED_209
SERDES_E0_RXN
SERDES_E0_RXP
SERDES_E0_TXN
SERDES_E0_TXP
SERDES_E1_RXN
SERDES_E1_RXP
SERDES_E1_TXN
SERDES_E1_TXP
SERDES_E2_RXN
SERDES_E2_RXP
SERDES_E2_TXN
SERDES_E2_TXP
SERDES_E3_RXN
SERDES_E3_RXP
SERDES_E3_TXN
SERDES_E3_TXP
SERDES_REXT_0
SERDES_REXT_1
SERDES0_RXN
J8
SERDES0_TXN
AA19
Y19
J9
SERDES0_TXP
J10
SERDES1_RXN
SERDES1_RXP
AF18
AE18
AA18
Y18
J11
J12
SERDES1_TXN
J13
SERDES1_TXP
H13
G13
D10
C19
C20
C21
C24
D3
SERDES2_RXN
SERDES2_RXP
AF15
AE15
AA15
Y15
SERDES2_TXN
SERDES2_TXP
SERDES3_RXN
SERDES3_RXP
AF14
AE14
AA14
Y14
SERDES3_TXN
SERDES3_TXP
D6
SERDES4_RXN
SERDES4_RXP
AF11
AE11
AA11
Y11
D7
D8
SERDES4_TXN
D9
SERDES4_TXP
AF21
AE21
AA21
Y21
AF17
AE17
AA17
Y17
AF13
AE13
AA13
Y13
AF9
AE9
AA9
Y9
SERDES5_RXN
SERDES5_RXP
AF10
AE10
AA10
Y10
SERDES5_TXN
SERDES5_TXP
SERDES6_RXN
SERDES6_RXP
AF7
AE7
SERDES6_TXN
AA7
Y7
SERDES6_TXP
SERDES7_RXN
SERDES7_RXP
AF6
AE6
SERDES7_TXN
AA6
Y6
SERDES7_TXP
SFP_SERIALCLK0 / ESLED0_CLK
SFP_SERIALDATA / ESLED0_LD
SFP0_SD / ESLED0_DO / GPIO_2
SFP1_SD / ESLED0_PULSE / GPIO_3
SFP2_SD / GPIO_4
SFP3_SD / GPIO_29
THERMDA
AB4
AB3
AB2
AB1
AA4
R3
AE22
AF22
AF19
AE19
C23
C22
SERDES0_RXP
THERMDC_VSS
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
120
Pins by name (continued)
VDD_1
G6
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
P20
P21
R6
VDD_2
G7
VDD_3
G8
VDD_4
G11
G12
G15
G16
G19
G20
G21
H6
R7
VDD_5
R20
R21
T6
VDD_6
VDD_7
VDD_8
T7
VDD_9
T20
T21
V6
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
H7
V7
H8
V8
H9
V9
H10
H11
H12
H15
H16
H17
H18
H19
H20
H21
L6
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
W6
L7
L20
L21
M6
W7
W8
M7
W9
M20
M21
N6
W10
W11
W12
W13
W14
W15
W16
W17
N7
N20
N21
P6
P7
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
121
Pins by name (continued)
VDD_77
W18
W19
W20
W21
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
D4
VDD_AH_19
VDD_AH_20
VDD_AH_21
VDD_AH_22
VDD_AH_23
VDD_AH_24
VDD_AH_25
VDD_AH_26
VDD_AH_27
VDD_AH_28
VDD_AH_29
VDD_AH_30
VDD_AH_31
VDD_AH_32
VDD_AH_33
VDD_AH_34
VDD_AH_35
VDD_AH_36
VDD_AL_1
F8
VDD_78
F11
F12
F15
F16
F19
F22
F23
J3
VDD_79
VDD_80
VDD_A_1
VDD_A_2
VDD_A_3
VDD_A_4
VDD_A_5
VDD_A_6
J4
VDD_A_7
J23
J24
M3
VDD_A_8
VDD_A_9
VDD_A_10
VDD_A_11
VDD_A_12
VDD_A_13
VDD_A_14
VDD_A_15
VDD_A_16
VDD_AH_1
VDD_AH_2
VDD_AH_3
VDD_AH_4
VDD_AH_5
VDD_AH_6
VDD_AH_7
VDD_AH_8
VDD_AH_9
VDD_AH_10
VDD_AH_11
VDD_AH_12
VDD_AH_13
VDD_AH_14
VDD_AH_15
VDD_AH_16
VDD_AH_17
VDD_AH_18
M4
M5
M22
M23
M24
E9
VDD_AL_2
E10
E17
E18
F9
VDD_AL_3
D5
VDD_AL_4
F7
VDD_AL_5
D11
D16
F20
VDD_AL_6
F10
F17
F18
G9
VDD_AL_7
VDD_AL_8
E4
VDD_AL_9
E5
VDD_AL_10
VDD_AL_11
VDD_AL_12
VDD_AL_13
VDD_AL_14
VDD_AL_15
VDD_AL_16
VDD_AL_17
VDD_AL_18
VDD_AL_19
VDD_AL_20
G10
G17
G18
J5
E8
E11
E12
E15
E16
E19
E22
E23
F4
J6
J7
J20
J21
J22
K5
F5
K6
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
122
Pins by name (continued)
VDD_AL_21
VDD_AL_22
VDD_AL_23
VDD_AL_24
VDD_IO_1
K7
VDD_VS_1
VDD_VS_2
VDD_VS_3
VDD_VS_4
VDD_VS_5
VDD_VS_6
VDD_VS_7
VDD_VS_8
VDD_VS_9
VDD_VS_10
VDD_VS_11
VDD_VS_12
VDD_VS_13
VDD_VS_14
VDD_VS_15
VDD_VS_16
VSS
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
C6
K20
K21
K22
E6
VDD_IO_2
E7
VDD_IO_3
E20
E21
F6
VDD_IO_4
VDD_IO_5
VDD_IO_6
F21
P5
VDD_IO_7
VDD_IO_8
R5
VDD_IO_9
T5
VDD_IO_10
VDD_IO_11
VDD_IO_12
VDD_IO_13
VDD_IO_14
VDD_IO_15
VDD_IO_16
VDD_IO_17
VDD_IO_18
VDD_IO_19
VDD_IO_20
VDD_IODDR_1
VDD_IODDR_2
VDD_IODDR_3
VDD_IODDR_4
VDD_IODDR_5
VDD_IODDR_6
VDD_IODDR_7
VDD_IODDR_8
VDD_IODDR_9
VDD_IODDR_10
VDD_IODDR_11
VDD_IODDR_12
VDD_IODDR_13
VDD_IODDR_14
U5
V5
W5
Y5
AA5
AB5
AC4
AC5
AD4
AE3
AF2
P22
R22
T22
U22
V22
W22
Y22
AA22
AB22
AC22
AD23
AE24
AF25
AF24
VSS_1
B1
VSS_2
B26
G3
VSS_3
VSS_4
G5
VSS_5
G22
G24
H3
VSS_6
VSS_7
VSS_8
H5
VSS_9
H22
H24
K3
VSS_10
VSS_11
VSS_12
K8
VSS_13
K9
VSS_14
K10
K11
K12
K13
K14
K15
K16
K17
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
123
Pins by name (continued)
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
K18
K19
K24
L3
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
N12
N13
N14
N15
N16
N17
N18
N19
N22
N23
N24
P3
L5
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L22
L24
M8
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P23
P24
R8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
N3
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
N4
N5
N8
N9
N10
N11
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
124
Pins by name (continued)
VSS_98
T8
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
AA16
AA20
AC3
AD5
AD22
AE1
VSS_99
T9
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
Y12
AE5
AE12
AE16
AE20
AE23
AE26
AF5
AF12
AF16
AF20
AF23
AE4
T10
Y16
T11
Y20
T12
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AA12
T13
T14
T15
T16
T17
T18
T19
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
125
Package Information
8
Package Information
VSC8512XJG-02 and VSC8512XJG-03 are packaged in a lead-free (Pb-free), 672-pin, thermally
enhanced, plastic ball grid array (BGA) with a 27 mm × 27 mm body size, 1 mm pin pitch, and 2.44 mm
maximum height.
Lead-free products from Microsemi comply with the temperatures and profiles defined in the joint IPC
and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.
This section provides the package drawing, thermal specifications, and moisture sensitivity rating for the
device.
8.1
Package Drawing
The following illustration shows the package drawing for the device. The drawing contains two top views,
a bottom view, a side view, a detail view, dimensions, tolerances, and notes. The top views reflect one of
two packages customers can expect to receive.
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
126
Package Information
Figure 40 • Package Drawing
Top View 1
Bottom View
Pin A1 corner
Pin A1 corner
Ø 1.00 (3×) REF
1
2
3
4
5
6
7
8
9 1012121314151617181920212223242526
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
A
B
C
C
D
D
E
F
E
F
e
G
G
H
H
J
J
K
K
L
L
M
N
M
N
P
P
R
R
T
T
U
U
V
V
W
Y
W
Y
AA
AB
AC
AD
AE
AF
AA
AB
AC
AD
AE
AF
e
4.00 Ref,
45° (4×)
Y
E1
E
Y
Ø 19.00 – 20.00
24.00
X
X
0.20 (4×)
Top View 2
Side View
Pin A1 corner
1.17 Ref
30°
Detail A
R0.25 Typ
1
2
3
4
5
6
7
8
9 1012121314151617181920212223242526
A
B
C
D
E
F
0.56 Ref
2.
3.
Ø b
G
H
J
K
L
M
N
Seating plane
Ø 0.10 M
Ø 0.25 M
Z
Z
X
Y
P
R
T
U
V
W
Y
Detail A
AA
AB
AC
AD
AE
AF
0.35 Z
0.20 Z
0.25 C
1.65 Ref,
45° (4×)
Y
Ø 2.5
Ø 19.80
25.70
Z
A1
A
X
Dimensions and Tolerances
Reference Minimum Nominal Maximum
Notes
2.44
0.60
A
A1
D
2.10
0.40
2.23
0.50
1. All dimensions and tolerances are in millimeters (mm).
2. Primary datum Z and seating plane are defined by the spherical
crowns of the solder balls.
27.00
27.00
25.00
25.00
1.00
E
3. Dimension is measured at the maximum solder ball diameter,
parallel to primary datum C.
D1
E1
e
4. Radial true position is represented by typical values.
5. Top view 1 and top view 2 reflect one of two packages customers
can expect to receive.
3.
0.70
b
0.50
0.60
8.2
Thermal Specifications
Thermal specifications for this device are based on the JEDEC JESD51 family of documents. These
documents are available on the JEDEC Web site at www.jedec.org. The thermal specifications are
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
127
Package Information
modeled using a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p
PCB). For more information about the thermal measurement method used for this device, see the
JESD51-1 standard.
Table 135 • Thermal Resistances
Symbol
θJCtop
θJB
°C/W
3.27
6.03
12.14
9.42
8
Parameter
Die junction to package case top
Die junction to printed circuit board
Die junction to ambient
θJA
θ
JMA at 1 m/s
JMA at 2 m/s
Die junction to moving air measured at an air speed of 1 m/s
Die junction to moving air measured at an air speed of 2 m/s
θ
To achieve results similar to the modeled thermal measurements, the guidelines for board design
described in the JESD51 family of publications must be applied. For information about applications using
BGA packages, see the following:
•
•
JESD51-2A, Integrated Circuits Thermal Test Method Environmental Conditions, Natural Convection
(Still Air)
JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions, Forced Convection
(Moving Air)
•
•
JESD51-8, Integrated Circuit Thermal Test Method Environmental Conditions, Junction-to-Board
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
8.3
Moisture Sensitivity
This device is rated moisture sensitivity level 4 as specified in the joint IPC and JEDEC standard
IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
128
Design Considerations
9
Design Considerations
This section provides information about the design considerations for the VSC8512-02 device.
9.1
10BASE-T mode unable to re-establish link
10BASE-T mode is unable to re-establish link with the following devices if the link drops while sending
data: SparX-III™ and Caracal™ family of switches, VSC8512-02, VSC8522-02, VSC8522-12, VSC8504,
VSC8552, VSC8572, and VSC8574. No issue is observed for other link partner devices. The probability
of this error occurring is low except in a test environment.
The workaround is to contact Microsemi for the current API software release.
This item was previously published in the VSC8512-02 Errata revision 1.0 as EA100054.
9.2
Link status for 100BASE-FX operation
SerDes media link status bit in register 24E3, bit 2 only reflects the status when the media type is
1000BASE-X. This bit is always 0 when the media type is 100BASE-FX.
The workaround is to verify that register 28, bits 1:0 media operating mode status is 10 for fiber media,
register 28, bits 4:3 speed status is 01 for 100BASE-FX, and register 16, bit 12 link status is 1 for
100BASE-FX mode.
This item was previously published in the VSC8512-02 Errata revision 1.0 as EA100055.
9.3
9.4
Software script for link performance
Software script is required for improved link performance. PHY ports may exhibit suboptimal
performance. Contact Microsemi for a script to be applied during system initialization.
This item was previously published in the VSC8512-02 Errata revision 1.0 as EA100034.
10BASE-T signal amplitude
10BASE-T signal amplitude can be lower than the minimum specified in IEEE 802.3 paragraph
14.3.1.2.1 (2.2 V) at low supply voltages. This issue is not estimated to present any system level impact.
Performance is not impaired with cables up to 130 m with various link partners.
This item was previously published in the VSC8512-02 Errata revision 1.0 as EA100036.
9.5
9.6
Clause 45 register 7.60
Clause 45, register 7.60, bit 10 reads back as a logic 1. This is a reserved bit in the standard and should
be ignored by software.
This item was previously published in the VSC8512-02 Errata revision 1.0 as EA100037.
Clause 45 register 3.22
Clause 45, register 3.22 is cleared upon read only when extended page access register (register 31) is
set to 0. This register cannot be read when page access register is set to a value other than 0.
The workaround is to set the extended page access register to 0 before accessing clause 45, register
3.22.
This item was previously published in the VSC8512-02 Errata revision 1.0 as EA100038.
9.7
Clause 45 register 3.1
Clause 45, register 3.1, Rx and Tx LPI received bits are cleared upon read only when extended page
access register (register 31) is set to 0.
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Design Considerations
The workaround is to set the extended page access register to 0 before accessing clause 45, register
3.1.
This item was previously published in the VSC8512-02 Errata revision 1.0 as EA100039.
9.8
Clause 45 register address post-increment
Clause 45 register address post-increment only works when reading registers and only when the
extended page access register (register 31) is set to 0. The estimated impact is low, as there are very few
Clause 45 registers in a Gigabit PHY, and they can be addressed individually.
The workaround is to access Clause 45 registers individually.
This item was previously published in the VSC8512-02 Errata revision 1.0 as EA100040.
VMDS-10396 VSC8512-02 Datasheet Revision 4.3
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Ordering Information
10 Ordering Information
The VSC8512 device is offered with two operating temperature ranges. The range for VSC8512-02 is
0 °C ambient to 125 °C junction, and the range for VSC8512-03 is
–40 °C ambient to 125 °C junction.
VSC8512XJG-02 and VSC8512XJG-03 are packaged in a lead-free (Pb-free), 672-pin, thermally
enhanced, plastic ball grid array (BGA) with a 27 mm × 27 mm body size, 1 mm pin pitch, and 2.44 mm
maximum height.
Lead-free products from Microsemi comply with the temperatures and profiles defined in the joint IPC
and JEDEC standard IPC/JEDEC J-STD-020. For more information, see the IPC and JEDEC standard.
The following table lists the ordering information for the device.
Table 136 • Ordering Information
Part Order Number Description
VSC8512XJG-02
Lead-free, 672-pin, thermally enhanced, plastic BGA with a
27 mm × 27 mm body size, 1 mm pin pitch, and 2.44 mm maximum height.
The operating temperature is 0 °C ambient to 125 °C junction.
VSC8512XJG-03
Lead-free, 672-pin, thermally enhanced, plastic BGA with a
27 mm × 27 mm body size, 1 mm pin pitch, and 2.44 mm maximum height.
The operating temperature is –40 °C ambient to 125 °C junction.
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