ZL40264LDF1 [MICROCHIP]
Clock Driver;
| 型号： | ZL40264LDF1 |
| 厂家： | 
MICROCHIP |
| 描述： | Clock Driver 驱动 逻辑集成电路 |
| 文件： | 总26页 (文件大小：916K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
ZL40264
Four output ultra-low additive phase noise PCIe Gen 1 to 5,
and UPI/QPI fanout buffer
Ordering Information
Features
ZL40264LDG1
ZL40264LDF1
20 pin QFN
20 pin QFN
Trays
Tape and Reel
• One differential input which accepts any
differential format.
Package size: 4 x 4 mm
• Four differential HCSL outputs
-40 C to +85 C
• Ultra-low additive jitter: 32fs (in 12kHz to 20MHz
integration band at 400MHz clock frequency)
Applications
• Supports clock frequencies from 0 to 400MHz
•
•
•
•
•
•
•
PCI Express generation 1/2/3/4/5 clock distribution
UPI/QPI clock distribution
• Supports 2.5V or 3.3V power supplies for HCSL
outputs
Low jitter clock trees
• Embedded Low Drop Out (LDO) Voltage regulator
Logic translation
provides superior Power Supply Noise Rejection
Clock and data signal restoration
High performance microprocessor clock distribution
Test Equipment
• Maximum output to output skew of 50ps
• Individual Output Enable pin for each differential
pair.
• Transfers Spread-Spectrum without attenuation
OE[3:0]_b
OUT0_p
OUT0_n
OUT1_p
OUT1_n
IN_p
IN_n
OUT2_p
OUT2_n
ZL40264
OUT3_p
OUT3_n
Figure 1. Functional Block Diagram
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Data Sheet
ZL40264
Table of Contents
Features.....................................................................................................................................1
Applications................................................................................................................................1
Table of Contents ......................................................................................................................2
Pin Diagram ...............................................................................................................................5
Pin Descriptions.........................................................................................................................6
Functional Description ...............................................................................................................7
Clock Inputs ...............................................................................................................................7
Clock Outputs ..........................................................................................................................10
Termination of unused outputs ................................................................................................11
Power Consumption ................................................................................................................11
Power Supply Filtering.............................................................................................................11
Power Supplies and Power-up Sequence...............................................................................12
Device Control .........................................................................................................................12
Typical phase noise performance............................................................................................13
AC and DC Electrical Characteristics......................................................................................14
Absolute Maximum Ratings.....................................................................................................14
Recommended Operating Conditions .....................................................................................14
Package Outline ......................................................................................................................24
Change history:........................................................................................................................25
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Data Sheet
ZL40264
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Functional Block Diagram........................................................................................................................................... 1
Pin Diagram ................................................................................................................................................................ 5
Input driven by source terminated HCSL..................................................................................................................... 7
Input driven by receiver terminated HCSL .................................................................................................................. 8
Input driven by AC coupled LVPECL output................................................................................................................. 8
Input driven by AC coupled LVDS ................................................................................................................................ 8
Input driven by a single ended output ........................................................................................................................ 9
Source terminated HCSL ........................................................................................................................................... 10
Receiver terminated HCSL......................................................................................................................................... 10
Power Supply Filtering .............................................................................................................................................. 12
100MHz HCSL Phase Noise ...................................................................................................................................... 13
133MHz HCSL Phase Noise ....................................................................................................................................... 13
400MHz HCSL Phase Noise ....................................................................................................................................... 13
Single-Ended Measurement Points for Absolute Cross Point and Swing .................................................................. 21
Single-Ended Measurement Points for Delta Cross Point ......................................................................................... 21
Single-Ended Measurement Points for Rise and Fall Time Matching ....................................................................... 21
Differential Measurement Points for Rise and Fall Time .......................................................................................... 22
Differential Measurement Points for Ringback ........................................................................................................ 22
Test Circuit ................................................................................................................................................................ 22
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Data Sheet
ZL40264
List of Tables
Table 1 Pin Descriptions................................................................................................................................................................................. 6
Table 2 Absolute Maximum Ratings*........................................................................................................................................................... 14
Table 3 Recommended Operating Conditions* ............................................................................................................................................ 14
Table 4 Current consumption ....................................................................................................................................................................... 15
Table 5 Input Characteristics* ...................................................................................................................................................................... 15
Table 6 Power Supply Rejection Ratio for VDD = VDDO = 3.3V* .................................................................................................................. 15
Table 7 Power Supply Rejection Ratio for VDD = VDDO = 2.5V* .................................................................................................................. 16
Table 8 HCSL Outputs for VDDO = 3.3V* ...................................................................................................................................................... 17
Table 9 HCSL (PCIe) Jitter Performance for VDDO = 3.3V............................................................................................................................. 18
Table 10 HCSL Outputs for VDDO = 2.5V* .................................................................................................................................................... 19
Table 11 HCSL (PCIe) Jitter Performance for VDDO = 2.5V ........................................................................................................................... 20
Table 12 4x4mm QFN Package Thermal Properties ..................................................................................................................................... 23
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Data Sheet
ZL40264
Pin Diagram
The device is packaged in a 4x4mm 20-pin QFN.
Pin#1
Corner
20
19
18
17
16
1
2
3
4
5
15
14
13
12
11
VDD
GND
VDDO
GND
OE3_b
OE1_b
OUT1_p
OUT1_n
Exposed GND Pad 2.125 x 2.125 mm
OUT3_n
OUT3_p
6
7
8
9
10
Figure 2. Pin Diagram
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Data Sheet
ZL40264
Pin Descriptions
All device inputs and outputs are HCSL unless described otherwise. The I/O column uses the following symbols: I –
input, IPU – input with 300k internal pull-up resistor, IPD – input with 300k internal pull-down resistor, IAPU – input with
31k internal pull-up resistor, IAPD – input with 30k internal pull-down resistor, IAPU/APD – input biased to VDD/2 with
60k internal pull-up and pull-down resistors (30 k equivalent), O – output, I/O – Input/Output pin, NC-No connect
pin, P – power supply pin.
Table 1 Pin Descriptions
#
Name
I/O
Description
Input Reference
IAPD
IAPU/APD
IAPD
IN_p
IN_n
20
19
Input Differential or Single Ended Reference
Input frequency range 0Hz to 400MHz.
IAPU/APD
Non-inverting inputs (_p) are pulled down with internal 30k pull-down resistors.
Inverting inputs (_n) are pulled up and pulled down with 60k internal resistors (30k
equivalent) to keep inverting input voltages at VDD/2 when inverting inputs are left
floating (device fed with a single ended reference).
Output Clocks
O
Ultra-Low Additive Jitter Differential HCSL Outputs 0 to 3
17
16
12
11
9
8
5
4
OUT0_p
OUT0_n
OUT1_p
OUT1_n
OUT2_p
OUT2_n
OUT3_p
OUT3_n
Output frequency range 0 to 400MHz
Control
IPD
18
13
10
3
OE0_b
OE1_b
OE2_b
OE3_b
Output Enable. Logic level on these pins enables/disables corresponding outputs.
OEn_b
OUTn_p/n
Active
0
1
High-Z (outputs p/n will be low/low because of 50Ω shunt
resistors—see recommended output termination)
Power and Ground
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Data Sheet
ZL40264
1
VDD
P
Positive Supply Voltage. Connect to 3.3V or 2.5V supply.
6
15
VDDO
GND
P
P
P
Positive Supply Voltage for Differential Outputs Connect 3.3V or 2.5V power
supply. VDDO does not have to be connected to the same voltage level as VDD.
2
7
14
Ground Connect to the ground
Ground. Connect to the ground
E-Pad
GND
Functional Description
The ZL40264 is an ultra-low additive jitter, low power 1 to 4 HCSL fanout buffer.
The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature
range -40°C to +85°C.
Clock Inputs
The following blocks diagram shows how to terminate different signals fed to the ZL40264 inputs.
Figure 3 and Figure 4 show how to terminate the input when driven from an HCSL driver.
The input buffer in ZL40264 in a native HCSL receiver so other differential formats need to be AC coupled as shown
in Figure 5 and Figure 6 for LVPECL and LVDS signals respectively.
Figure 7 shows how to terminate a single ended output such as LVCMOS. Ideally, resistors R1 and R2 should be
100 each and Ro + Rs should be 50 so that the transmission line is terminated at both ends with characteristic
impedance. If the driving strength of the output driver is not sufficient to drive low impedance, the value of series
resistor RS should be increased. This will reduce the voltage swing at the input but this should be fine as long as the
input voltage swing requirement is not violated (Table 5). The source resistors of Rs = 270 could be used for
standard LVCMOS driver. This will provide 516mV of voltage swing for 3.3V LVCMOS driver with load current of
(3.3V/2) *(1/(270 + 50)) = 5.16mA.
For optimum performance both differential input pins (_p and _n) need to be DC biased to the same voltage. Hence,
the ratio R1/R2 should be equal to the ratio R3/R4.
VDD
ꢂꢂ
Z0 = 50
ꢂꢂ
Z0 = 50
MSCC Device
HCSL Output
ꢀꢁ
ꢀꢁ
Figure 3. Input driven by source terminated HCSL
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Data Sheet
ZL40264
VDD
ꢂꢂ
ꢂꢂ
Z0 = 50
Z0 = 50
MSCC Device
HCSL Output
ꢀꢁ
ꢀꢁ
Figure 4. Input driven by receiver terminated HCSL
VDD
VDD
VDD
R1
R2
VDD
R1
R2
10 nF
10 nF
Z0 = 50
Z0 = 50
LVPECL
ꢃꢁꢁ
ꢃꢁꢁ
MSCC Device
R1
R2
VDD
3.3V
2.5V
442
332
56
59
Figure 5. Input driven by AC coupled LVPECL output
VDD
VDD
VDD
R1
R1
VDD
10 nF
10 nF
Z0 = 50
Zꢁ ꢅ ꢀꢁ
ꢄꢁꢁ
LVDS
MSCC Device
VDD
R1
R2
R2
R2
20 k 2.55 k
20 k 3.48 k
3.3V
2.5V
Figure 6. Input driven by AC coupled LVDS
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Data Sheet
ZL40264
Vdd
Vdd
Vdd
Vdd
Optional AC coupling
capacitor
R3
R1
R2
0.1 µF
Rs
Ro
Z0 = 50
Ro + Rs= Z0
VDD
R3
R4
R1
R2
442
332
56
59
1.27 k
1.78 k
3.3V
2.5V
10 k
10 k
MSCC Device
0.1 µF
R4
R1/R2 =R3/R4
Rs = ꢃꢆꢁ ꢀfor standard LVCMOS output
Figure 7. Input driven by a single ended output
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Data Sheet
ZL40264
Clock Outputs
Differential HCSL outputs should be terminated as shown in Figure 8 or Figure 9.
VDD
ꢂꢂ
Z0 = 50
ꢂꢂ
Z0 = 50
HCSL Input
MSCC Device
ꢀꢁ
ꢀꢁ
Figure 8. Source terminated HCSL
VDD
ꢂꢂ
ꢂꢂ
Z0 = 50
Z0 = 50
HCSL Input
MSCC Device
ꢀꢁ
ꢀꢁ
Figure 9. Receiver terminated HCSL
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Data Sheet
ZL40264
Termination of unused outputs
Unused outputs should be left unconnected.
Power Consumption
The device total power consumption can be calculated as:
PT = PS + PC + PO_DIFF
Where:
Core power consumed by the input
buffer. The static current (IS) is
specified in Table 4.
PS = VDD IS
PC = VDDO IDD_CM
Common output power shared
among four outputs. The current
IDD_CM is specified in Table 4.
PO_DIF = VDDO IDD_HCSL N
Output power where output current
per output (IDD_HCSL) is specified in
Table 4.
N is number of enabled outputs.
Power dissipated inside the device can be calculated by subtracting power dissipated in termination/biasing resistors
from the power consumption:
PD = PT – N PHCSL
Where:
PHCSL = (VSW / 50Ω)2 (50Ω + 33Ω)
VSW is voltage swing of HCSL output. 50Ω is
termination resistance and 33Ω is series resistance
of the HCSL output.
Power Supply Filtering
Each power pin (VDD and VDDO) should be decoupled with 0.1µF capacitor with minimum equivalent series
resistance (ESR) and minimum series inductance (ESL). For example, 0402 X5R Ceramic Capacitors with 6.3V
minimum rating could be used. These capacitors should be placed as close as possible to the power pins. To reduce
the power noise from adjacent digital components on the board each power supply could optionally be further
insulated with low resistance ferrite bead with 10µF and 1µF capacitors. Following figure shows the standard and
optional decoupling method.
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Data Sheet
ZL40264
Standard Decoupling
Optional Decoupling
VDDO
VDDO
0.1uF
0.1uF
VDDO
0.1uF
VDDO
VDD
0.1uF
0.1uF
Board Supply
10uF
Ferrite Bead
1uF
VDD
Board Supply
1uF
0.1uF
Figure 10.
Power Supply Filtering
Power Supplies and Power-up Sequence
The device has two different power supplies: VDD and VDDO which should always be connected to the same voltage
supply. Voltages supported by each of these power supplies are specified in Table 3.
VDD and VDDO should always be turned on and off at the same time.
Device Control
ZL40264 outputs are controlled via OE[3:0]_b pins. When an OE_b pin is low the corresponding outputs will be active
and when this pin is high the output will be high-Z. When the output driver is in high-Z mode, the output pins will be
pulled low via external 50Ω HCSL termination resistors.
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Data Sheet
ZL40264
Typical phase noise performance
The following plots show typical phase noise performance for 100 MHz, 133 MHz and 400 MHz clocks respectively.
Figure 11.
100MHz HCSL Phase Noise
Figure 12.
133MHz HCSL Phase Noise
Figure 13.
400MHz HCSL Phase Noise
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Data Sheet
ZL40264
AC and DC Electrical Characteristics
Absolute Maximum Ratings
Table 2 Absolute Maximum Ratings*
Parameter
Supply voltage (3.3V)
Sym.
VDD /VDDO
VDD /VDDO
TST
Min.
-0.5
-0.5
-55
Typ.
Max.
4.6
Units
V
Notes
1
2
3
Supply voltage (2.5V)
Storage temperature
3.5
V
125
°C
* Exceeding these values may cause permanent damage
* Functional operation under these conditions is not implied
* Voltages are with respect to ground (GND) unless otherwise stated
Recommended Operating Conditions
Table 3 Recommended Operating Conditions*
Characteristics
Sym.
VDD /VDDO
VDD /VDDO
TA
Min.
3.135
2.375
-40
Typ.
3.30
2.50
25
Max.
3.465
2.625
85
Units Notes
1
2
5
6
Supply voltage 3.3V
Supply voltage 2.5V
V
V
Operating temperature
Input voltage
°C
V
VDD-IN
- 0.3
VDD + 0.3
* Voltages are with respect to ground (GND) unless otherwise stated
* The device core supports two power supply modes (3.3V and 2.5V)
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Data Sheet
ZL40264
Table 4 Current consumption
Characteristics
Core device current
Sym.
Is_3.3V
Min.
Typ.
49
Max.
53
Units
mA
Notes
VDD= 3.3V+5%
VDD = 2.5V+5%
VDDO= 3.3V+5%
VDDO= 2.5V+5%
VDDO= 3.3V+5%
VDDO= 2.5V+5%
1
2
3
Is_2.5V
48
53
mA
IDD_CM_3.3V
IDD_CM_2.5V
IDD_HCSL_3.3V
IDD_HCSL_2.5V
5.24
4.72
14.92
14.61
5.82
5.32
17.18
16.62
mA
Common output current
mA
mA
Current dissipation per HCSL output
mA
Table 5 Input Characteristics*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
CMOS high-level input voltage for control inputs
CMOS high-level input voltage for control inputs
CMOS low-level input voltage for control inputs
VCIH_3.3V
0.7 *
VDD
V
1a
VDD = 3.3V
VCIH_2.5V
0.8 *
VDD
V
1b
2
VDD = 2.5V
VCIL
IIL
0.32 * VDD
50
V
CMOS input leakage current for control inputs (includes current due
to pull down resistors)
-25
µA
VI = VDD or 0
V
3
4
Differential input common mode voltage for IN_p/n
Differential input voltage for IN_p/n
VCM
VID
0.1
0.2
0.8
V
V
VDD + 0.3
5
Differential input leakage current for IN_p/n (includes
current due to pull-up and pull-down resistors)
IIL
-150
150
µA
VI = 2V or 0V
6
7
8
9
VSI
VSIC
VSID
-0.3
0.1
0.3
2.7
0.8
1.3
V
V
VDD = 3.3V
or 2.5V
Single ended input voltage for IN_p
VDD = 3.3V
or 2.5V
Single ended input common mode voltage IN_p
Single ended input voltage swing for IN_p
V
VDD = 3.3V
or 2.5V
10 Input frequency (differential)
11 Input duty cycle
fIN
dc
0
400
MHz
35%
0.6
65%
13 Input slew rate
slew
RPU/RPD
RPD
2
V/ns
kΩ
14 Input pull-up/ pull-down resistance
15 Input pull-down resistance for IN_p
16 Control input (OE_b) pull-down resistance
60
30
kΩ
RPDOE
300
kΩ
* Values are over Recommended Operating Conditions
* Values are over all two power supply modes (VDD = 3.3V and VDD = 2.5V)
(1) low frequency only
Table 6 Power Supply Rejection Ratio for VDD = VDDO = 3.3V*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
-80.7
fIN = 100 MHz
fIN = 133 MHz
fIN = 400 MHz
1
PSRR for HCSL output
PSRRHCSL
-76.4
-66.5
dBc
* Values are over Recommended Operating Conditions
* Noise injected to VDD/VDDO power supply with frequency 100 kHz and amplitude 100 mVpp
* PSRR is measured as amplitude of 100 kHz spur in dBc on the output clock phase noise plot
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Data Sheet
ZL40264
Table 7 Power Supply Rejection Ratio for VDD = VDDO = 2.5V*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
-73.5
fIN = 100 MHz
fIN = 133 MHz
fIN = 400 MHz
3
PSRR for HCSL output
PSRRHCSL
-69.8
-61.2
dBc
* Values are over Recommended Operating Conditions
* Noise injected to VDD/VDDO power supply with frequency 100 kHz and amplitude 100 mVpp
* PSRR is measured as amplitude of 100 kHz spur in dBc on the output clock phase noise plot
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Data Sheet
ZL40264
Table 8 HCSL Outputs for VDDO = 3.3V*
Parameter
Sym.
Rise_rate
Fall_rate
VIH
Min.
1.3
Typ.
1.7
Max.
2
Units
V/ns
V/ns
V
Notes
(2), (3)
1
2
3
4
5
6
7
8
9
Rising edge rate
Falling edge rate
1.3
1.7
2
(2), (3)
Differential High Voltage
0.6
0.9
(2)
Differential Low Voltage
VIL
-0.9
0.6
-0.6
0.85
0.01
0.38
0.061
0.809
V
(2)
Single ended high voltage
Single ended low voltage
VSIH
0.74
0
V
DC Measurement
DC Measurement
(1), (4), (5)
(1), (4), (9)
(2), (11)
VSIL
-0.01
0.26
0.039
0.534
4.6
V
Absolute Crossing Voltage
Variation of VCROSS over all rising clock edges
Ring back voltage margin
VCROSS
∆VCROSS
VRB
0.32
0.050
0.674
V
V
V
10 Time before VRB is allowed
11 Cycle-to-cycle additive jitter
tSTABLE
ns
(2), (11)
6.5
8.1
ps
peak to
peak
TJCC
(2)
12 Absolute Maximum voltage
VMAX
VMIN
0.92
(1), (7)
(1), (8)
(2)
13 Absolute Minimum voltage
-0.05
48
14 Output Duty-Cycle (when input has 50% duty-cycle)
15 Rising to falling edge matching
Duty_cycle
r/f match
50
52
15
51
%
%
(1), (12)
49
49
0
50
50
DC Measurement
(1), (13)
16 Clock Source DC impedance (CK)
17 Clock Source DC impedance (CK#)
ZC-DC_CK
Ω
Ω
51
DC Measurement
(1), (13)
ZC-DC_CK#
18 Output frequency
FMAX
tOOSK
tDOOSK
tIOD
400
50
129
1
MHz
ps
19 Output to output skew
20 Device to device output skew
21 Input to output delay
22 Output enable time
23 Output disable time
ps
0.75
0.84
ns
tEN
3
cycles
cycles
tDIS
3
* Values are over Recommended Operating Conditions
(1) Measurement taken from single ended waveform
(2) Measurement taken from differential waveform.
(3) Measured from -150 mV to +150 mV on the differential waveform (derived from CK minus CK#) The signal must be monotonic through the
measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing. See Figure 17
(4) Measured at crossing point where the instantaneous voltage value of the rising edge of CK equals the falling edge of CK# . See Figure 14
(5) Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this
measurement. See Figure 14.
(6) This requirement, from PCI Express Base Specification, Revision 4.0 is applicable only to clock generators and not to buffers. A clock buffer is a transparent
device whose output clock period follows the input clock period.
(7) Defined as the maximum instantaneous voltage including overshoot. See Figure 14.
(8) Defined as the minimum instantaneous voltage including undershoot. See Figure 14.
(9) Defined as the total variation of all crossing voltages of Rising CK and Falling CK# This is the maximum allowed variance in VCROSS for any particular
system. See Figure 15.
(10) The PPM requirement from PCIe Express Base Specification, Revision 4.0 is related to clock generation devices. This requirement is not applicable to buffers
because buffer’s output frequency accuracy is identical to the frequency accuracy of the source driving the buffer.
(11) TSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after20 rising/falling edges before it is allowed to droop
back into the VRB ±100 mV differential range. See Figure 18.
(12) Matching applies to rising edge rate for CKx and falling edge rate for CK#x. It is measured using a ±75 mV window centered on the median cros point where
CKx rising meets CK#x falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The
Rise Edge Rate of CKx should be compared to the Fall Edge Rate of CK#x the maximum allowed difference should not exceed 20% of the slowest edge rate.
See Figure 16.
(13) Clock DC impedance tolerance depends only on the tolerance of external 50Ω shunt resistors used in HCSL. The test used resistors with +/-1% tolerance.
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Data Sheet
ZL40264
Table 9 HCSL (PCIe) Jitter Performance for VDDO = 3.3V
Parameter
Sym.
Min.
Typ.
Max.
Units
Notes
1
2
Additive Jitter as per PCIe 1.0 (1.5MHz to 22MHz)
TjPCIe_1.0
1.2
1.45
ps pk-pk
Input clock: 100 MHz
Additive Jitter as per PCIe 2.0 high band (1.5MHz to
50MHz)
TjPCIe_2.0_high
134
163
fs RMS
Input clock: 100 MHz
Additive Jitter as per PCIe 2.0 low band (10kHz to
1.5MHz)
3
4
5
TjPCIe_2.0_low
TjPCIe_2.0_mid
TjPCIe_3.0
31
105
33
48
130
41
fs RMS
fs RMS
fs RMS
Input clock: 100 MHz
Input clock: 100 MHz
Input clock: 100 MHz
Additive Jitter as per PCIe 2.0 mid band (5MHz to 16MHz)
Additive Jitter as per PCIe 3.0 (PLL_BW = 2 to 5MHz,
CDR = 10MHz)
Additive Jitter as per PCIe 4.0 (PLL_BW = 2 to 5MHz,
CDR = 10MHz)
6
TjPCIe_4.0
33
13
41
16
fs RMS
fs RMS
Input clock: 100 MHz
Input clock: 100 MHz
Additive Jitter as per PCIe 5.0 (PLL_BW = 0.5 to 1.8MHz,
CDR for 32 GT/s CC)
7
8
TjPCIe_5.0
TjQPI
Additive jitter as per Intel QPI 9.6Gbps
61
87
75
106
68
fs RMS
fs RMS
fs RMS
fs RMS
fs RMS
fs RMS
fs RMS
dBc/Hz
dBc/Hz
dBc/Hz
Input clock: 100 MHz
Input clock: 100 MHz
Input clock: 133 MHz
Input clock: 400 MHz
Input clock: 100 MHz
Input clock: 133 MHz
Input clock: 400 MHz
Input clock: 100 MHz
Input clock: 133 MHz
Input clock: 400 MHz
9
Additive RMS jitter in 1MHz to 20MHz band
Tj_1M_20M
Tj_12k_20M
NF
56
26
34
91
112
75
10 Additive RMS jitter in 12kHz to 20MHz band
60
32
48
-161
-162
-160
-159
-161
-157
11 Noise floor
* Values are over Recommended Operating Conditions
ZL40264
June 2019
© 2019 Microsemi Corporation
18
Data Sheet
ZL40264
Table 10 HCSL Outputs for VDDO = 2.5V*
Parameter
Sym.
Rise_rate
Fall_rate
VIH
Min.
1.3
Typ.
1.6
Max.
1.9
Units
V/ns
V/ns
V
Notes
(2), (3)
1
2
3
4
5
6
7
8
9
Rising edge rate
Falling edge rate
1.3
1.6
1.9
(2), (3)
Differential High Voltage
0.6
0.9
(2)
Differential Low Voltage
VIL
-0.9
0.58
-0.01
0.25
0.04
0.514
4.6
-0.6
0.84
0.01
0.37
0.06
0.791
V
(2)
Single ended high voltage
Single ended low voltage
VSIH
0.71
0
V
DC Measurement
DC Measurement
(1), (4), (5)
(1), (4), (9)
(2), (11)
VSIL
V
Absolute Crossing Voltage
Variation of VCROSS over all rising clock edges
Ring back voltage margin
VCROSS
∆VCROSS
VRB
0.31
0.05
0.660
V
V
V
10 Time before VRB is allowed
11 Additive Cycle-to-cycle jitter
tSTABLE
ns
(2), (11)
5.5
7.1
ps
peak to
peak
TJCC
(2)
12 Absolute Maximum voltage
VMAX
VMIN
0.90
(1), (7)
(1), (8)
(2)
13 Absolute Minimum voltage
-0.05
48
14 Output Duty-Cycle (when input has 50% duty-cycle)
15 Rising to falling edge matching
Duty_cycle
r/f match
50
52
15
51
%
%
(1), (12)
49
49
0
50
50
DC Measurement
(1), (13)
16 Clock Source DC impedance (CK)
17 Clock Source DC impedance (CK#)
ZC-DC_CK
Ω
Ω
51
DC Measurement
(1), (13)
ZC-DC_CK#
18 Output frequency
FMAX
tOOSK
tDOOSK
tIOD
400
50
129
1
MHz
ps
19 Output to output skew
20 Device to device output skew
21 Input to output delay
22 Output enable time
23 Output disable time
ps
0.75
0.85
ns
tEN
3
cycles
cycles
tDIS
3
* Values are over Recommended Operating Conditions
(1) Measurement taken from single ended waveform
(2) Measurement taken from differential waveform.
(3) Measured from -150 mV to +150 mV on the differential waveform (derived from CK minus CK#) The signal must be monotonic through the
measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing. See Figure 17
(4) Measured at crossing point where the instantaneous voltage value of the rising edge of CK equals the falling edge of CK# . See Figure 14
(5) Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this
measurement. See Figure 14.
(6) This requirement, from PCI Express Base Specification, Revision 4.0 is applicable only to clock generators and not to buffers. A clock buffer is a transparent
device whose output clock period follows the input clock period.
(7) Defined as the maximum instantaneous voltage including overshoot. See Figure 14.
(8) Defined as the minimum instantaneous voltage including undershoot. See Figure 14.
(9) Defined as the total variation of all crossing voltages of Rising CK and Falling CK# This is the maximum allowed variance in VCROSS for any particular
system. See Figure 15.
(10) The PPM requirement from PCIe Express Base Specification, Revision 4.0 is related to clock generation devices. This requirement is not applicable to buffers
because buffer’s output frequency accuracy is identical to the frequency accuracy of the source driving the buffer.
(11) TSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after20 rising/falling edges before it is allowed to droop
back into the VRB ±100 mV differential range. See Figure 18.
(12) Matching applies to rising edge rate for CKx and falling edge rate for CK#x. It is measured using a ±75 mV window centered on the median cros point where
CKx rising meets CK#x falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The
Rise Edge Rate of CKx should be compared to the Fall Edge Rate of CK#x the maximum allowed difference should not exceed 20% of the slowest edge rate.
See Figure 16.
(13) Clock DC impedance tolerance depends only on the tolerance of external 50Ω shunt resistors used in HCSL. The test used resistors with +/-1% tolerance.
ZL40264
June 2019
© 2019 Microsemi Corporation
19
Data Sheet
ZL40264
Table 11 HCSL (PCIe) Jitter Performance for VDDO = 2.5V
Parameter
Sym.
Min.
Typ.
Max.
Units
Notes
1
2
Additive Jitter as per PCIe 1.0 (1.5MHz to 22MHz)
TjPCIe_1.0
1.03
1.27
ps pk-pk
Input clock: 100MHz
Additive Jitter as per PCIe 2.0 high band (1.5MHz to
50MHz)
TjPCIe_2.0_high
TjPCIe_2.0_low
TjPCIe_2.0_mid
TjPCIe_3.0
115
28
91
29
29
11
143
46
fs RMS
fs RMS
fs RMS
fs RMS
fs RMS
fs RMS
Input clock: 100MHz
Input clock: 100MHz
Input clock: 100MHz
Input clock: 100MHz
Input clock: 100MHz
Input clock: 100MHz
Additive Jitter as per PCIe 2.0 low band (10kHz to
1.5MHz)
3
4
5
6
Additive Jitter as per PCIe 2.0 mid band (5MHz to
16MHz)
113
36
Additive Jitter as per PCIe 3.0 (PLL_BW = 2 to 5MHz,
CDR = 10MHz)
Additive Jitter as per PCIe 4.0 (PLL_BW = 2 to 5MHz,
CDR = 10MHz)
TjPCIe_4.0
36
Additive Jitter as per PCIe 5.0 (PLL_BW = 0.5 to
1.8MHz, CDR for 32 GT/s CC)
7
8
TjPCIe_4.0
TjQPI
14
Additive jitter as per Intel QPI 9.6Gbps
53
75
67
94
fs RMS
fs RMS
fs RMS
fs RMS
fs RMS
fs RMS
fs RMS
dBc/Hz
dBc/Hz
dBc/Hz
Input clock: 100MHz
Input clock: 100 MHz
Input clock: 133 MHz
Input clock: 400 MHz
Input clock: 100 MHz
Input clock: 133 MHz
Input clock: 400 MHz
Input clock: 100 MHz
Input clock: 133 MHz
Input clock: 400 MHz
9
Additive RMS jitter in 1MHz to 20MHz band
Tj_1M_20M
Tj_12k_20M
NF
51
64
26
33
79
99
10 Additive RMS jitter in 12kHz to 20MHz band
55
68
32
47
-162
-163
-160
-159
-161
-158
11 Noise floor
* Values are over Recommended Operating Conditions
ZL40264
June 2019
© 2019 Microsemi Corporation
20
Data Sheet
ZL40264
Vmax = 1.15V
OUTx_n
Vcross_max = 550mV
Vcross_min = 250mV
OUTx_p
Vmax = -0.3V
Figure 14.
Single-Ended Measurement Points for Absolute Cross Point and Swing
OUTx_n
Vcross_delta = 250mV
OUTx_p
Figure 15.
Single-Ended Measurement Points for Delta Cross Point
tfall
OUTx_n
Vcross_median + 75mV
Vcross_median
Vcross_median
Vcross_median – 75mV
OUTx_p
trise
Rise/fall match = MIN[|trise – tfall|/trise,|trise – tfall|/tfall]*100%
Figure 16.
Single-Ended Measurement Points for Rise and Fall Time Matching
ZL40264
June 2019
© 2019 Microsemi Corporation
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Data Sheet
ZL40264
OUTx_p -OUTx_n
slew_rise = 0.3V/trise_edge_rate [V/ns]
slew_fall = 0.3V/tfall_edge_rate [V/ns]
Figure 17.
Differential Measurement Points for Rise and Fall Time
OUTx_p - OUTx_n
Figure 18.
Differential Measurement Points for Ringback
15 dB loss at 4 GHz
Refclk Margins
CK
DUT
CK#
Differential PCB trace
ZDIFF = ꢄꢁꢁ ±10%
2 pF 5%
2 pF 5%
Figure 19.
Test Circuit
ZL40264
June 2019
© 2019 Microsemi Corporation
22
Data Sheet
ZL40264
Table 12 4x4mm QFN Package Thermal Properties
Parameter
Maximum Ambient Temperature
Symbol
Conditions
Value
Units
TA
TJMAX
85
125
34
28.9
27.0
15.4
25.9
8.1
C
C
Maximum Junction Temperature
still air
1m/s airflow
2.5m/s airflow
Junction to Ambient Thermal Resistance(1)
JA
C/W
Junction to Board Thermal Resistance
Junction to Case Thermal Resistance
Junction to Pad Thermal Resistance(2)
JB
JC
JP
C/W
C/W
C/W
Still air
Still air
Junction to Top-Center Thermal Characterization Parameter
1.0
C/W
JT
(1)
(2)
Theta-JA (JA) is the thermal resistance from junction to ambient when the package is mounted on a 4-layer JEDEC standard test board and dissipating
maximum power
Theta-JP (JP) is the thermal resistance from junction to the center exposed pad on the bottom of the package)
ZL40264
June 2019
© 2019 Microsemi Corporation
23
Data Sheet
ZL40264
Package Outline
ZL40264
June 2019
© 2019 Microsemi Corporation
24
Data Sheet
ZL40264
Change history:
June 2019 revision-Initial release
ZL40264
June 2019
© 2019 Microsemi Corporation
25
Data Sheet
ZL40264
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and
system solutions for aerospace & defense, communications, data center and industrial markets.
Products include high-performance and radiation-hardened analog mixed-signal integrated
circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization
devices and precise time solutions, setting the world's standard for time; voice processing
devices; RF solutions; discrete components; enterprise storage and communication solutions,
security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-
Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is
headquartered in Aliso Viejo, California, and has approximately 4,800 employees globally.
Learn more at www.microsemi.com.
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One Enterprise, Aliso Viejo,
CA 92656 USA
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability
whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and
any other products sold by Microsemi have been subject to limited testing and should not be used in
conjunction with mission-critical equipment or applications. Any performance specifications are believed to
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ZL40264
June 2019
26
© 2019 Microsemi Corporation
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