MT16VDDF6464HG-265 [MICRON]
SMALL-OUTLINE DDR SDRAM DIMM; 小外形的DDR SDRAM DIMM
| 型号： | MT16VDDF6464HG-265 |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | SMALL-OUTLINE DDR SDRAM DIMM |
| 文件： | 总31页 (文件大小：552K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512MB, 1GB (x64)
200-PIN DDR SODIMM
MT16VDDF6464H – 512MB
MT16VDDF12864H – 1GB
SMALL-OUTLINE
ꢀ
DDR SDRAM DIMM
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/moduleds
Features
Figure 1: 200-Pin SODIMM (MO-224)
•
200-pin, small-outline, dual in-line memory
module (SODIMM)
512MB Module
•
•
Fast data transfer rates: PC1600, PC2100, and PC2700
Utilizes 200 MT/s, 266 MT/s, or 333 MT/s DDR
SDRAM components
•
•
•
•
•
•
512MB (64 Meg x 64), 1GB (128 Meg x 64)
VDD = VDDQ = +2.5V
VDDSPD = +2.3V to +3.6V
2.5V I/O (SSTL_2 compatible)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
1GB Module
•
•
Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
•
•
•
•
•
•
•
•
•
Differential clock inputs CK and CK#
Four internal device banks for concurrent operation
Programmable burst lengths: 2, 4, or 8
Auto precharge option
Auto Refresh and Self Refresh Modes
7.8125µs maximum average periodic refresh interval
Serial Presence Detect (SPD) with EEPROM
Programmable READ CAS latency
Gold edge contacts
OPTIONS
MARKING
•
Package
G
Y
200-pin SODIMM (standard)
200-pin SODIMM (lead-free)1
•
Frequency/CAS Latency2
167 MHz (333 MT/s) CL = 2.5
133 MHz (266 MT/s) CL = 2
133 MHz (266 MT/s) CL = 2
133 MHz (266 MT/s) CL = 2.5
100 MHz (200 MT/s) CL = 2
-335
-262
-26A
-265
-202
NOTE: 1. Contact factory for availability of lead-free prod-
ucts.
2. CL = CAS (READ) latency.
Table 1:
Address Table
512MB
1GB
8K
8K
Refresh Count
8K (A0–A12)
4 (BA0, BA1)
32 Meg x 8
1K (A0–A9)
2 (S0#, S1#)
8K (A0–A12)
4 (BA0, BA1)
64 Meg x 8
Device Row Addressing
Device Bank Addressing
Device Configuration
2K (A0–A9, A11)
2 (S0#, S1#)
Device Column Addressing
Module Rank Addressing
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
1
©2003 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 2:
Part Numbers and Timing Parameters
LATENCY
PART NUMBER
MODULE
DENSITY
CONFIGURATION
TRANSFER MEMORY CLOCK/
RATE
DATA BIT RATE
(CL - tRCD - tRP)
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
512MB
1GB
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
6ns/333 MT/s
6ns/333 MT/s
2.5-3-3
2.5-3-3
2-2-2
MT16VDDF6464HG-335__
MT16VDDF6464HY-335__
MT16VDDF6464HG-262__
MT16VDDF6464HY-262__
MT16VDDF6464HG-26A__
MT16VDDF6464HY-26A__
MT16VDDF6464HG-265__
MT16VDDF6464HY-265__
MT16VDDF6464HG-202__
MT16VDDF6464HY-202__
MT16VDDF12864HG-335__
MT16VDDF12864HY-335__
MT16VDDF12864HG-262__
MT16VDDF12864HY-262__
MT16VDDF12864HG-26A__
MT16VDDF12864HY-26A__
MT16VDDF12864HG-265__
MT16VDDF12864HY-265__
MT16VDDF12864HG-202__
MT16VDDF12864HY-202__
NOTE:
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
6ns/333 MT/s
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2.5-3-3
2.5-3-3
2-2-2
1GB
6ns/333 MT/s
1GB
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
1GB
2-2-2
1GB
2-3-3
1GB
2-3-3
1GB
2.5-3-3
2.5-3-3
2-2-2
1GB
1GB
1GB
2-2-2
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current Revision codes. Example: MT16VDDF6464HG-265A1.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2
512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 3:
Pin Assignment
(200-Pin SODIMM Front)
Table 4:
Pin Assignment
(200-Pin SODIMM Back)
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
VREF
VSS
51
VSS
101
A9
VSS
A7
151 DQ42
153 DQ43
2
VREF
VSS
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
VSS
102
A8
VSS
A6
152 DQ46
154 DQ47
3
53 DQ19 103
55 DQ24 105
4
DQ23 104
DQ28 106
5
DQ0
DQ1
VDD
155
157
159
161
VDD
VDD
VSS
6
DQ4
DQ5
VDD
156
VDD
7
57
VDD
107
A5
8
VDD
108
A4
158 CK1#
9
59 DQ25 109
A3
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
DQ29 110
DM3 112
A2
160
162
CK1
VSS
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
DQS0
DQ2
VSS
61
63
DQS3 111
113
A1
VSS
DM0
DQ6
VSS
A0
VSS
VDD
A10
BA0
WE#
S0#
NC
163 DQ48
165 DQ49
VSS
114
VDD
BA1
164 DQ52
166 DQ53
65 DQ26 115
67 DQ27 117
DQ30 116
DQ3
DQ8
VDD
167
VDD
DQ7
DQ12
VDD
DQ31 118 RAS# 168
VDD
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
VDD
119
169 DQS6
171 DQ50
VDD
DNU
DNU
VSS
120 CAS# 170 DM6
DNU 121
DNU 123
122
124
126
S1#
NC
VSS
172 DQ54
174
176 DQ55
DQ9
DQS1
VSS
173
VSS
DQ13
DM1
VSS
VSS
VSS
125
VSS
175 DQ51
DNU 127 DQ32 177 DQ56
DNU 129 DQ33 179
131 181 DQ57
DNU 133 DQS4 183 DQS7
DNU
DNU
VDD
DNU
DNU
VSS
128 DQ36 178 DQ60
130 DQ37 180
132 182 DQ61
134 DM4 184 DM7
136 DQ38 186
138 188 DQ62
140 DQ39 190 DQ63
DQ10
DQ11
VDD
VDD
DQ14
DQ15
VDD
VDD
VDD
VDD
VDD
CK0
NC
VSS
135 DQ34 185
VSS
VDD
VSS
CK0#
VSS
137 187 DQ58
VSS
VSS
VSS
DNU 139 DQ35 189 DQ59
VSS
VSS
DQ16
DQ17
VDD
DNU 141 DQ40 191
143 193
CKE1 145 DQ41 195
VDD
SDA
SCL
DQ20
DQ21
VDD
VDD
VDD
142 DQ44 192
144 194
VDD
SA0
SA1
SA2
VSS
VDD
VDD
VDD
CKE0 146 DQ45 196
DQS2
DQ18
NC
147 DQS5 197 VDDSPD
149 VSS 199 NC
DM2
NC
148 DM5 198
A12
DQ22 100
A11
150
VSS
200
Figure 2: Module Layout
Front View
Front View
U17
U1
U2
U3
U4
U5
U6
U1
U5
U2
U6
U3
U7
U4
U8
U7
U8
U17
PIN 1
(all odd pins)
PIN 199
U14
PIN 1
(all odd pins)
PIN 199
Back View
Back View
U9
U10
U11
U12
U13
U9
U10
U14
U11
U15
U12
U16
U13
U15
U16
PIN 200
(all even pins)
PIN 2
PIN 200
(all even pins)
PIN 2
Indicates a VDD or VDDQ pin
Indicates a VSS pin
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
3
512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
118, 119, 120
WE#,
CAS#,RAS#
Input
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
35, 37, 158, 160
95, 96
CK0, CK0#
CK1, CK1#
Input
Input
Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the
positive edge of CK, and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.
CKE0, CKE1
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any device bank). CKE is synchronous for
POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE
is asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after VDD is applied and
until CKE is first brought HIGH. After CKE is brought HIGH, it
becomes an SSTL_2 input only.
121, 122
116, 117
S0#, S1#
Input
Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
BA0, BA1
A0-A12
Input
Input
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
99, 100, 101, 102, 105,106,
107, 108, 109, 110, 111, 112,
115
Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for
READ/WRITE commands, to select one location out of the
memory array in the respective device bank. A10 sampled
during a PRECHARGE command determines whether the
PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0, BA1) or all device banks (A10 HIGH). The
address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
1, 2
195
VREF
Input
Input
SSTL_2 reference voltage.
SCL
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
194, 196, 198
193
SA0-SA2
SDA
Input
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Input/
Output
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.
12, 26, 48, 62, 134, 148, 170,
184
DM0-DM7
Input
Data Write Mask. DM LOW allows WRITE operation. DM HIGH
blocks WRITE operation. DM lines do not affect READ
operation.
09005aef80a646bc
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
4
©2003 Micron Technology, Inc.
512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 5:
Pin Descriptions (Continued)
Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
11, 25, 47, 61, 133, 147, 169,
183
DQS0-DQS7
Input/
Output
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
5, 6, 7, 8, 13, 14, 17, 18, 19,
20, 23, 24, 29, 30, 31, 32, 41,
42, 43, 44, 49, 50, 53, 54, 55,
56, 59, 60, 65, 66, 67, 68, 127,
128, 129, 130, 135, 136, 139,
140, 141, 142, 145, 146, 151,
152, 153, 154, 163, 164, 165,
166, 171, 172, 175, 176, 177,
178, 181, 182, 187, 188, 189,
190
DQ0-DQ63
Input/
Output
Data I/Os: Data bus.
9, 10, 21, 22, 33, 34, 36, 45,
46, 57, 58, 69, 70, 81, 82, 92,
93, 94, 113, 114, 131, 132,
143, 144, 155, 156, 157, 167,
168, 179, 180, 191, 192
VDD
VSS
Supply
Supply
Power Supply: +2.5V 0.2V.
3, 4, 15, 16, 27, 28, 38, 39, 40,
51, 52, 63, 64, 75, 76, 87, 88,
90, 103, 104, 125, 126, 137,
138, 149, 150, 159, 161, 162,
173, 174, 185, 186, 200
Ground.
197
VDDSPD
NC
Supply
—
Serial EEPROM positive power supply: +2.3V to +3.6V
No Connect: These pins should be left unconnected.
85, 97, 98, 123, 124, 199
71, 72, 73, 74, 77, 78, 79, 80,
83, 84, 86, 89, 91
DNU
—
Do Not Use: These pins are not connected on this module, but
are assigned pins on other modules in this product family.
09005aef80a646bc
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
5
©2003 Micron Technology, Inc.
512MB, 1GB (x64)
200-PIN DDR SODIMM
Figure 3: Functional Block Diagram – 512MB
S1#
S0#
DQS0
DM0
DQS1
DM1
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U1
U14
U7
U16
DQS3
DM3
DQS2
DM2
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U2
U13
U3
U12
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS5
DM5
DQS4
DM4
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U4
U11
U5
U10
DQ
DQ
DQ
DQ
DQS7
DM7
DQS6
DM6
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U8
U15
U6
U9
120
120
BA0, BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
BA0, BA1
A0-A12
CK0
CK0#
DDR SDRAMs U1, U2, U3, U7
U12, U13, U14, U16
RAS#
CAS#
CAS#: DDR SDRAMs
CK1
CK1#
CKE0: DDR SDRAMs U1-U8
CKE1: DDR SDRAMs U9-U16
WE#: DDR SDRAMs
CKE0
CKE1
WE#
DDR SDRAMs U4, U5, U6, U8
U9, U10, U11, U15
CK2
CK2#
120Ω
VDDSPD
SPD/EEPROM
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
VDD
VREF
SERIAL PD
SCL
WP
U17
A0 A1 A2
SDA
VSS
SA0 SA1 SA2
DDR SDRAMs: MT46V32M8S2FD
DDR SDRAMs: MT46V64M8S2FD
NOTE:
1. All resistor values are 22ꢀ unless otherwise specified.
2. Per industry standard, Micron utilizes various component speed grades as
referenced in the Module Part Numbering Guide at www.micron.com/
numberguide.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
6
512MB, 1GB (x64)
200-PIN DDR SODIMM
Figure 4: Functional Block Diagram – 1GB
S1#
S0#
DQS0
DM0
DQS1
DM1
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U1
U12
U5
U16
DQS3
DM3
DQS2
DM2
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U2
U11
U6
U15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS5
DM5
DQS4
DM4
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U3
U10
U7
U14
DQ
DQ
DQ
DQ
DQS7
DM7
DQS6
DM6
DM CS# DQS
DM CS# DQS
DM CS# DQS
DM CS# DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U4
U9
U8
U13
120
BA0, BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
BA0, BA1
A0-A12
DDR SDRAMs
U1, U2, U3, U7
U12, U13, U14, U16
CK2
CK2#
CK0
CK0#
120Ω
RAS#
CAS#
120
SERIAL PD
CAS#: DDR SDRAMs
DDR SDRAMs
U4, U5, U6, U8
U9, U10, U11, U15
SCL
WP
U17
A0 A1 A2
CK1
CK1#
SDA
CKE0: DDR SDRAMs U1-U8
CKE0
CKE1
WE#
CKE1: DDR SDRAMs U9-U16
WE#: DDR SDRAMs
SA0 SA1 SA2
VDDSPD
SPD/EEPROM
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
VDD
VREF
VSS
DDR SDRAMs: MT46V32M8S2FD
DDR SDRAMs: MT46V64M8S2FD
NOTE:
1. All resistor values are 22ꢀ unless otherwise specified.
2. Per industry standard, Micron utilizes various component speed grades as
referenced in the Module Part Numbering Guide at www.micron.com/
numberguide.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
7
512MB, 1GB (x64)
200-PIN DDR SODIMM
General Description
The MT16VDDF6464H and MT16VDDF12864H are
high-speed CMOS, dynamic random-access, 512MB
and 1GB memory modules organized in a x64 configu-
ration. These modules use internally configured quad-
bank DRAM devices.
high effective bandwidth by hiding row precharge and
activation time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible. For more
information regarding DDR SDRAM operation, refer to
the 256Mb or 512Mb DDR SDRAM data sheets.
DDR SDRAM modules use a double data rate archi-
tecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the DDR SDRAM module effectively
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corre-
sponding n-bit wide, one-half-clock-cycle data trans-
fers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.
DDR SDRAM modules operate from a differential
clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to DDR SDRAM modules
are burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select devices bank; A0–A12 select
device row). The address bits registered coincident
with the READ or WRITE command are used to select
the device bank and the starting device column loca-
tion for the burst access.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-
detect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I2C bus
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect.
Mode Register Definition
The mode register is used to define the specific
mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in
Figure 5, Mode Register Definition Diagram, on page 9.
The mode register is programmed via the MODE REG-
ISTER SET command (with BA0 = 0 and BA1 = 0) and
will retain the stored information until it is pro-
grammed again or the device loses power (except for
bit A8, which is self-clearing).
Reprogramming the mode register will not alter the
contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.
Mode register bits A0–A2 specify the burst length,
A3 specifies the type of burst (sequential or inter-
leaved), A4–A6 specify the CAS latency, and A7–A12
specify the operating mode.
DDR SDRAM modules provides for programmable
read or write burst lengths of 2, 4, or 8 locations. An
auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.
As with standard SDR SDRAM modules, the pipe-
lined, multibank architecture of DDR SDRAM modules
allows for concurrent operation, thereby providing
09005aef80a646bc
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
8
512MB, 1GB (x64)
200-PIN DDR SODIMM
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Burst Length
Read and write accesses to the DDR SDRAM are
burst oriented, with the burst length being program-
mable, as shown in Figure 5, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
Figure 5: Mode Register Definition
Diagram
A8
A6 A5 A4
A1
A0
Address Bus
A10
A7
A3 A2
BA0 A12 A11
A9
BA1
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
14 13
11
9
8
6
5
4
1
12
10
7
3
2
0
Mode Register (Mx)
0* 0*
Operating Mode
CAS Latency BT Burst Length
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–Ai when the burst length is set to two,
by A2–Ai when the burst length is set to four and by
A3–Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration. See Note 5 of Table 6, Burst Definition
Table, on page 10, for Ai values). The remaining (least
significant) address bit(s) is (are) used to select the
starting location within the block. The programmed
burst length applies to both read and write bursts.
* M14 and M13 (BA1 and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
Burst Length
M2 M1 M0
M3 = 0
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4
8
Reserved
Reserved
Reserved
Reserved
Burst Type
Sequential
Interleaved
M3
0
1
Burst Type
CAS Latency
Reserved
Reserved
2
M6 M5 M4
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 10.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
2.5
Reserved
Read Latency
M13 M12 M11 M10 M9 M8 M7
M6-M0
Valid
Valid
-
Operating Mode
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 6, CAS
Latency Diagram, on page 10.
0
0
-
0
0
-
0
0
-
0
0
-
0
0
-
0
1
-
0
0
-
Normal Operation
Normal Operation/Reset DLL
All other states reserved
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. The CAS
Latency Table indicates the operating frequencies at
which each CAS latency setting can be used.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
9
512MB, 1GB (x64)
200-PIN DDR SODIMM
Figure 6: CAS Latency Diagram
Table 6:
Burst Definition Table
T0
T1
T2
T2n
T3
T3n
ORDER OF ACCESSES WITHIN
A BURST
CK#
CK
STARTING
COLUMN
ADDRESS
BURST
LENGTH
TYPE =
TYPE =
COMMAND
READ
NOP
NOP
NOP
SEQUENTIAL INTERLEAVED
CL = 2
A0
2
4
DQS
DQ
0
1
0-1
1-0
0-1
1-0
A1 A0
T0
T1
T2
T2n
T3
T3n
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
CK#
CK
COMMAND
READ
NOP
NOP
NOP
CL = 2.5
A2 A1 A0
DQS
DQ
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
8
Burst Length = 4 in the cases shown
Shown with nominal AC, DQSCK, and DQSQ
t
t
t
TRANSITIONING DATA DON T CARE
Operating Mode
NOTE:
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7–A12
each set to zero, and bits A0–A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9–A12 each set
to zero, bit A8 set to one, and bits A0–A6 set to the
desired values. Although not required by the Micron
device, JEDEC specifications recommend when a
LOAD MODE REGISTER command is issued to reset
the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
1. For a burst length of two, A1-Ai select the two-data-ele-
ment block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai select the four-data-
element block; A0-A1 select the first access within the
block.
3. For a burst length of eight, A3-Ai select the eight-data-
element block; A0-A2 select the first access within the
block.
4. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
5. i = 9 (512MB);
i = 9,11 (1GB)
All other combinations of values for A7–A12 are
reserved for future use and/or test modes. Test modes
and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.
Table 7:
CAS Latency (CL) Table
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHZ)
Extended Mode Register
SPEED
CL = 2
CL = 2.5
The extended mode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 7, Extended Mode Register
Definition Diagram, on page 11. The extended mode
register is programmed via the LOAD MODE REGIS-
TER command to the mode register (with BA0 = 1 and
-335
-262
-26A
-265
-202
75 ? f ? 133
75 ? f ? 133
75 ? f ? 133
75 ? f ? 100
75 ? f ? 100
75 ? f ? 167
75 ? f ? 133
75 ? f ? 133
75 ? f ? 133
75 ? f ? 125
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
10
512MB, 1GB (x64)
200-PIN DDR SODIMM
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/ BA1 both LOW) to reset the DLL.
Figure 7: Extended Mode Register
Definition Diagram
A8
A6 A5 A4
A1
A0
Address Bus
BA1
A10
A7
A3 A2
BA0 A12 A11
A9
The extended mode register must be loaded when
all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either of
these requirements could result in unspecified opera-
tion.
14 13
11
9
8
6
5
4
1
12
10
7
3
2
0
Extended Mode
Register (Ex)
1
1
0
1
Operating Mode
DS DLL
DLL
E0
0
Enable
Disable
1
DLL Enable/Disable
The DLL must be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.
Drive Strength
Normal
E1
0
1
Reduced
E22
0
E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3
E1, E0
Valid
–
Operating Mode
Reserved
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
–
Reserved
NOTE:
1. BA1 and BA0 (E14 and E13) must be “0, 1” to select the
Extended Mode Register (vs. the base Mode Register).
2. The QFC# option is not supported.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
11
512MB, 1GB (x64)
200-PIN DDR SODIMM
Commands
The Truth Tables below provides a general reference
of available commands. For a more detailed descrip-
tion of commands and operations, refer to the 256Mb
or 512Mb DDR SDRAM component data sheet.
Table 8:
Commands Truth Table
CKE is HIGH for all commands shown except SELF REFRESH
NAME (FUNCTION)
CS# RAS# CAS# WE#
ADDR
NOTES
H
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
1
1
DESELECT (NOP)
NO OPERATION (NOP)
Bank/Row
Bank/Col
Bank/Col
X
2
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
H
H
H
L
3
L
3
H
H
L
L
4
L
Code
5
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
L
H
L
X
6, 7
8
L
L
Op-Code
NOTE:
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A12 provide device row address.
3. BA0–BA1 provide device bank address; A0–A9 (512MB) or A0–A9, A11 (1GB) provide device column address; A10 HIGH
enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
bursts with auto precharge enabled and for WRITE bursts.
5. A10 LOW: BA0-BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–
BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls device row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0
= 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0–A12 provide the op-code
to be written to the selected mode register.
Table 9:
DM Operation Truth Table
Used to mask write data; provided coincident with the corresponding data
NAME (FUNCTION)
DM
DQS
L
Valid
X
WRITE Enable
WRITE Inhibit
H
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DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
12
512MB, 1GB (x64)
200-PIN DDR SODIMM
Absolute Maximum Ratings
Stresses greater than those listed may cause perma-
nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Voltage on VDD Supply
Operating Temperature
Relative to VSS. . . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on VDDQ Supply
Relative to VSS . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on VREF and Inputs
TA (ambient) . . . . . . . . . . . . . . . . . . . . .. 0°C to +70°C
Storage Temperature (plastic) . . . . . .-55°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 16W
Short Circuit Output Current. . . . . . . . . . . . . . . 50mA
Relative to VSS. . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on I/O Pins
Relative to VSS. . . . . . . . . . . . . -0.5V to VDDQ +0.5V
Table 10: DC Electrical Characteristics and Operating Conditions
Notes: 1–5, 14; notes appear on pages 20–23; 0°Cꢀ? TA ? +70°C
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS NOTES
Supply Voltage
VDD
VDDQ
VREF
2.3
2.3
2.7
2.7
V
V
V
32, 36
32, 36, 39
6, 39
I/O Supply Voltage
I/O Reference Voltage
0.49ꢀPꢀ
0.51ꢀPꢀ
VDDQ
VDDQ
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VTT
VREF - 0.04 VREF + 0.04
V
V
V
7, 39
25
VIH(DC)
VIH(DC)
VREF + 0.15
-0.3
VDD + 0.3
VREF - 0.15
25
INPUT LEAKAGE CURRENT Any input
0V ? VIN ? VDD, VREF pin 0V ? VIN ?ꢀ1.35V
(All other pins not under test = 0V)
Command/Address,
RAS#, CAS#, WE#
-32
-16
-4
32
16
4
II
S#, CKE, CK, CK#
DM
µA
µA
47
47
IOZ
-10
10
OUTPUT LEAKAGE CURRENT
DQ, DQS
(DQs are disabled; 0V ? VOUT ?ꢀVDDQ)
IOH
IOL
-16.8
16.8
–
–
mA
mA
OUTPUT LEVELS
High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
)
33, 34
Table 11: AC Input Operating Conditions
Notes: 1–5, 14; notes appear on pages 20–23; 0°Cꢀ? TA ? +70°C; VDD = VDDQ = +2.5V 0.2V
UNIT
S
PARAMETER/CONDITION
SYMBOL
MIN
MAX
NOTES
VIH(AC)
VIL(AC)
VREF + 0.310
–
–
V
V
V
12, 25, 35
12, 25, 35
6
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
I/O Reference Voltage
VREF - 0.310
0.49 P VDDQ
VREF(AC)
0.49 P VDDQ
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
13
512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 12: IDD Specifications and Conditions – 512MB
Notes: 1–5, 8, 10, 12, 48; DDR SDRAM devices only; notes appear on pages 20–23; 0°Cꢀ? TA ? +70°C; VDD, VDDQ = +2.5V 0.2V
MAX
-26A/-
265
UNIT NOTE
PARAMETER/CONDITION
SYM
-335
-262
-202
S
S
a
IDD0
1,032
1,032
872
992
mA 20, 42
OPERATING CURRENT: One device bank; Active-
Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and
DQS inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
a
IDD1
1,392
1,312
1,192
1,272
mA 20, 42
OPERATING CURRENT: One device bank; Active-Read-
Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN);
IOUT = 0mA; Address and control inputs changing once
per clock cycle
b
IDD2P
IDD2F
64
64
64
64
mA 21, 28,
44
PRECHARGE POWER-DOWN STANDBY CURRENT: All
device banks idle; Power-down mode; tCK = tCK (MIN);
CKE = (LOW)
b
800
720
720
720
mA
45
IDLE STANDBY CURRENT: CS# = HIGH; All device banks
are idle; tCK = tCK (MIN); CKE = HIGH; Address and other
control inputs changing once per clock cycle. VIN = VREF
for DQ, DQS, and DM
b
b
IDD3P
480
960
400
800
400
800
480
800
mA 21, 28,
44
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode; tCK = tCK (MIN);
CKE = LOW
IDD3N
mA
41
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One device bank active; tRC = tRAS (MAX); tCK = tCK
(MIN); DQ, DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing once per
clock cycle
a
IDD4R
1,432
1,272
1,232
1,112
1,232
1,122
1,432
1,552
mA 20, 42
OPERATING CURRENT: Burst = 2; Reads; Continuous
burst; One device bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); IOUT =
0mA
a
IDD4W
mA
20
OPERATING CURRENT: Burst = 2; Writes; Continuous
burst; One device bank active; Address and control
inputs changing once per clock cycle; tCK = tCK (MIN); DQ,
DM, and DQS inputs changing twice per clock cycle
b
tRC = tRFC
IDD5
4,080
96
3,760
96
3,760
96
3,920
96
mA 20, 44
mA 24, 44
AUTO REFRESH BURST CURRENT:
(MIN) tRFC =
7.8125µs
IDD5A
b
b
SELF REFRESH CURRENT: CKE ? 0.2V
IDD6
IDD7
64
64
64
64
mA
9
a
3,272
2,832
2,832
2,952
mA 20, 43
OPERATING CURRENT: Four device bank interleaving
READs (Burst = 4) with auto precharge, tRC = minimum
tRC allowed; tCK = tCK (MIN); Address and control inputs
change only during Active READ, or WRITE commands
NOTE:
a - Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode.
b - Value calculated reflects all module ranks in this operating condition.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
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©2003 Micron Technology, Inc.
14
512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 13: IDD Specifications and Conditions – 1GB
Notes: 1–5, 8, 10, 12, 48; DDR SDRAM devices only; notes appear on pages 20–23; 0°Cꢀ? TA ? +70°C; VDD, VDDQ = +2.5V 0.2V
MAX
-26A/-
265
UNIT NOTE
PARAMETER/CONDITION
SYM
-335
-262
-202
S
S
1,080
1,080
960
960
mA 20, 42
OPERATING CURRENT: One device bank; Active-
IDD0
Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and
DQS inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
1,320
1,320
1,200
1,200
mA 20, 42
OPERATING CURRENT: One device bank; Active-Read-
IDD1
Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN);
IOUT = 0mA; Address and control inputs changing once
per clock cycle
80
80
80
80
mA 21, 28,
44
PRECHARGE POWER-DOWN STANDBY CURRENT: All
device banks idle; Power-down mode; tCK = tCK (MIN);
CKE = (LOW)
IDD2P
720
720
640
640
mA
45
IDLE STANDBY CURRENT: CS# = HIGH; All device banks IDD2F
are idle; tCK = tCK (MIN); CKE = HIGH; Address and other
control inputs changing once per clock cycle. VIN = VREF
for DQ, DQS, and DM
560
720
560
720
480
640
480
640
mA 21, 28,
44
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode; tCK = tCK (MIN);
CKE = LOW
IDD3P
IDD3N
mA
41
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One device bank active; tRC = tRAS (MAX); tCK = tCK
(MIN); DQ, DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing once per
clock cycle
1,360
1,280
4,640
1,360
1,280
4,640
1,200
1,120
4,480
1,200
1,120
4,480
mA 20, 42
OPERATING CURRENT: Burst = 2; Reads; Continuous
burst; One device bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); IOUT =
0mA
IDD4R
mA
20
OPERATING CURRENT: Burst = 2; Writes; Continuous
burst; One device bank active; Address and control
inputs changing once per clock cycle; tCK = tCK (MIN); DQ,
DM, and DQS inputs changing twice per clock cycle
IDD4W
tRC = tRFC (MIN)
mA 20, 44
mA 24, 44
AUTO REFRESH BURST CURRENT:
IDD5
tRC = 7.8125µs
160
80
160
80
160
80
160
80
IDD5A
mA
9
SELF REFRESH CURRENT: CKE ? 0.2V
IDD6
IDD7
3,280
3,240
2,840
2,840
mA 20, 43
OPERATING CURRENT: Four device bank interleaving
READs (Burst = 4) with auto precharge, tRC = minimum
tRC allowed; tCK = tCK (MIN); Address and control inputs
change only during Active READ, or WRITE commands
NOTE:
a - Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode.
b - Value calculated reflects all module ranks in this operating condition.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
15
512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 14: Capacitance
Note: 11; notes appear notes appear on pages 20–23
PARAMETER
SYMBOL
MIN MAX
UNITS
CIO
CI1
CI2
7
9
pF
pF
pF
Input/Output Capacitance: DQ, DQS,DM
24
12
40
20
Input Capacitance: Command and Address, RAS#, CAS#, WE#
Input Capacitance:CK, CK#, CKE, S#
Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (-335, -262)
Notes: 1–5, 12–15, 29, 40; notes appear on pages 20–23; 0°Cꢀ? TA ? +70°C; VDD = VDDQ = +2.5V 0.2V
AC CHARACTERISTICS
-335
MAX
-262
MAX
PARAMETER
SYMBOL MIN
MIN
-0.75
0.45
0.45
7.5
UNITS NOTES
tAC
tCH
tCL
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
-0.70
0.45
0.45
6
+0.70
0.55
0.55
13
+0.75
0.55
0.55
13
ns
tCK
26
tCK
26
tCK (2.5)
tCK (2)
tDH
CL=2.5
CL=2
ns
ns
ns
ns
ns
ns
40, 46
40, 46
23, 27
23, 27
27
7.5
13
7.5
13
0.45
0.45
1.75
-0.60
0.35
0.35
0.5
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
tDS
0.5
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
1.75
-0.75
0.35
0.35
+0.60
+0.75
tCK
tCK
DQS input low pulse width
0.4
0.5
ns
22, 23
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
tCK
tCK
tCK
0.75
0.20
0.20
1.25
0.75
0.20
0.20
1.25
tDSH
tHP
tCH,tCL
+0.70
tCH,tCL
+0.75
ns
8
tHZ
ns
ns
ns
16, 37
16, 38
12
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
tLZ
tIHF
-0.70
0.75
-0.75
0.90
tISF
tIHS
tISS
0.75
0.8
0.90
1
ns
ns
ns
12
12
12
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
0.8
1
tIPW
tMRD
tQH
tQHS
tRAS
tRAP
2.2
12
2.2
15
ns
ns
ns
ns
ns
ns
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
tHP -tQHS
tHP -tQHS
22, 23
31
0.75
0.75
42
18
70,000
40
15
120,000
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
16
512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (-335, -262) (Continued)
Notes: 1–5, 12–15, 29, 40; notes appear on pages 20–23; 0°Cꢀ? TA ? +70°C; VDD = VDDQ = +2.5V 0.2V
AC CHARACTERISTICS
-335
MAX
-262
MAX
PARAMETER
SYMBOL MIN
MIN
60
UNITS NOTES
tRC
60
ns
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
tRFC
tRCD
tRP
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
72
18
18
0.9
0.4
12
0.25
0
75
ns
ns
ns
44
37
15
15
tCK
1.1
0.6
0.9
0.4
15
1.1
0.6
tCK
DQS read postamble
ns
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
tCK
ns
0.25
0
18, 19
17
DQS write preamble setup time
DQS write postamble
tCK
ns
0.4
15
1
0.6
0.4
15
0.6
Write recovery time
tWTR
tCK
ns
1
Internal WRITE to READ command delay
Data valid output window
tQH -tDQSQ
70.3
tQH -tDQSQ
70.3
NA
22
21
21
tREFC
tREFI
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
µs
µs
ns
ns
7.8
7.8
tVTD
0
0
tXSNR
tXSRD
75
75
tCK
200
200
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (-26A, -265, -202)
Notes: 1–5, 12–15, 29, 40; notes appear on pages 20–23; 0°Cꢀ? TA ? +70°C; VDD = VDDQ = +2.5V 0.2V
AC CHARACTERISTICS
-26A
-265
-202
PARAMETER
SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES
tAC
tCH
tCL
-0.75 +0.75 -0.75 +0.75 -0.8 +0.8
ns
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
tCK
tCK
ns
0.45
0.45
7.5
0.55
0.55
13
0.45
0.45
7.5
0.55 0.45 0.55
0.55 0.45 0.55
26
26
tCK (2.5)
tCK (2)
tDH
13
13
8
13
13
40, 46
40, 46
23, 27
23, 27
27
CL=2.5
CL=2
7.5
13
10
10
0.6
0.6
2
ns
ns
ns
ns
ns
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
0.5
0.5
tDS
0.5
0.5
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
1.75
1.75
-0.75 +0.75 -0.75 +0.75 -0.8 +0.8
tCK
tCK
0.35
0.35
0.35
0.35
0.35
0.35
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group,
per access
0.5
0.5
0.6
ns
22, 23
tDQSS
tDSS
tDSH
tHP
tHZ
tLZ
tCK
tCK
tCK
0.75
0.20
0.20
1.25
0.75
0.20
0.20
1.25 0.75 1.25
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
0.20
0.20
tCH,tCL
+0.75
tCH,tCL
+0.75
tCH,tCL
+0.8
ns
8
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
ns
ns
ns
16, 37
16, 38
12
-0.75
0.90
-0.75
0.90
-0.8
tIHF
1.1
Address and control input hold time (fast slew
rate)
tISF
tIHS
tISS
.900
1
0.90
1
1.1
1.1
1.1
ns
ns
ns
12
12
12
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
1
1
Address and control input setup time (slow slew
rate)
tIPW
2.2
2.2
2.2
ns
Address and Control input pulse width (for each
input)
tMRD
tQH
LOAD MODE REGISTER command cycle time
15
15
16
ns
ns
tHP -tQHS
0.75
tHP -tQHS
0.75
tHP -tQHS
1
22, 23
31
DQ-DQS hold, DQS to first DQ to go non-valid,
per access
tQHS
tRAS
tRAP
tRC
Data hold skew factor
ns
40 120,000 40 120,000 40 120,000 ns
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
20
65
20
65
20
70
ns
ns
ACTIVE to ACTIVE/AUTO REFRESH command
period
tRFC
tRCD
tRP
75
20
20
75
20
20
80
20
20
ns
ns
ns
44
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18
512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC
Operating Conditions (-26A, -265, -202) (Continued)
Notes: 1–5, 12–15, 29, 40; notes appear on pages 20–23; 0°Cꢀ? TA ? +70°C; VDD = VDDQ = +2.5V 0.2V
AC CHARACTERISTICS
-26A
-265
-202
PARAMETER
SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
tCK
tCK
ns
0.9
0.4
15
0.25
0
1.1
0.6
0.9
0.4
15
0.25
0
1.1
0.6
0.9
0.4
15
0.25
0
1.1
0.6
37
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
tCK
ns
DQS write preamble setup time
DQS write postamble
18, 19
17
tCK
ns
0.4
15
1
0.6
0.4
15
1
0.6
0.4
15
1
0.6
Write recovery time
tWTR
NA
tCK
ns
Internal WRITE to READ command delay
Data valid output window
tQH -tDQSQ
70.3
tQH -tDQSQ tQH - tDQSQ
22
21
21
tREFC
tREFI
tVTD
tXSNR
tXSRD
70.3
70.3
µs
µs
ns
ns
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
7.8
7.8
7.8
0
0
0
75
75
80
tCK
200
200
200
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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512MB, 1GB (x64)
200-PIN DDR SODIMM
Notes
1. All voltages referenced to VSS.
25°C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) TA
2. Tests for AC timing, IDD, and electrical AC and DC
characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.
= 0.2V. DM input is grouped with I/O pins, reflect-
ing the fact that they are matched in loading.
12. Command/Address input slew rate = 0.5V/ns. For
-262, -26A, and -265 with slew rates 1V/ns and
t
t
faster, IS and IH are reduced to 900ps; for -335,
they are reduced to 750ps. If the slew rate is less
3. Outputs measured with equivalent load:
t
VTT
than 0.5 V/ns, timing must be derated: IS has an
additional 50ps per each 100mV/ns reduction in
50
Ω
t
slew rate from the 500mV/ns, while IH remains
constant. If the slew rate exceeds 4.5V/ns, func-
tionality is uncertain.
Reference
Output
Point
(VOUT
)
30pF
13. The CK/CK# input reference level (for timing ref-
erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is VREF.
4. AC timing and IDD tests may use a VIL-to-VIH
swing of up to 1.5V in the test environment, but
input timing is still referenced to VREF (or to the
crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between VIL(AC)
and VIH(AC).
14. Inputs are not recognized as valid until VREF stabi-
lizes. Exception: during the period before VREF
stabilizes, CKE ? 0.3 x VDDQ is recognized as LOW.
15. The output timing reference level, as measured at
the timing reference point indicated in Note 3, is
VTT.
t
16. tHZ and LZ transitions occur in the same access
5. The AC and DC input level specifications are as
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6. VREF is expected to equal VDDQ/2 of the transmit-
ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on VREF may not exceed 2 percent of the
DC value. Thus, from VDDQ/2, VREF is allowed
25mV for DC error and an additional 25mV for
AC noise. This measurement is to be taken at the
nearest VREF bypass capacitor.
7. VTT is not applied directly to the device. VTT is a
system supply for signal termination resistors, is
expected to be set equal to VREF and must track
variations in the DC level of VREF.
8. IDD is dependent on output loading and cycle
rates. Specified values are obtained with mini-
mum cycle time at CL = 2 for -262, -26A, and -202,
CL = 2.5 for-335 and -265 with the outputs open.
9. Enables on-chip refresh and address counters.
10. IDD specifications are tested after the device is
properly initialized, and is averaged at the defined
cycle rate.
time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).
17. The intent of the Don’t Care state after completion
of the postamble is the DQS-driven signal should
either be high, low, or high-Z and that any signal
transition within the input switching region must
follow valid input requirements. That is, if DQS
transitions high (above VIH DC (MIN) then it must
t
not transition low (below VIH DC) prior to DQSH
(MIN).
18. This is not a device limit. The device will operate
with a negative value, but system performance
could be degraded due to bus turnaround.
19. It is recommended that DQS be valid (HIGH or
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on tDQSS.
t
20. MIN (tRC or RFC) for IDD measurements is the
smallest multiple of tCK that meets the minimum
t
absolute Value for the respective parameter. RAS
11. This parameter is sampled. VDD = +2.5V 0.2V,
VDDQ = +2.5V 0.2V, VREF = VSS, f = 100 MHz, =
(MAX) for IDD measurements is the largest multi-
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
20
512MB, 1GB (x64)
200-PIN DDR SODIMM
ple of tCK that meets the maximum absolute
value for tRAS.
21. The refresh period 64ms. This equates to an aver-
age refresh rate of 7.8125µs. However, an AUTO
REFRESH command must be asserted at least
once every 70.3µs; burst refreshing or posting by
the DRAM controller greater than eight refresh
cycles is not allowed.
25. To maintain a valid level, the transitioning edge of
the input must:
a. Sustain a constant slew rate from the current
AC level through to the target AC level, VIL(AC)
or VIH(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
maintain at least the target DC level, VIL(DC)
or VIH(DC).
22. The valid data window is derived by achieving
26. JEDEC specifies CK and CK# input slew rate must
be O 1V/ns (2V/ns differentially).
other specifications: tHP (tCK/2), tDQSQ, and tQH
(tQH = tHP - tQHS). The data valid window derates
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55. Functionality is uncertain when
operating beyond a 45/55 ratio. Figure 8, Derating
Data Valid Window, shows derating curves for
duty cycles ranging between 50/50 and 45/55.
23. Each byte lane has a corresponding DQS.
27. DQ and DM input slew rates must not deviate
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
t
must be derated: 50ps must be added to DS and
tDH for each 100mv/ns reduction in slew rate. If
slew rate exceeds 4V/ns, functionality is uncer-
tain.
28. VDD must not vary more than 4 percent if CKE is
not active while any bank is active.
29. The clock is allowed up to 150ps of jitter. Each
timing parameter is allowed to vary by the same
amount.
24. This limit is actually a nominal value and does not
result in a fail value. CKE is HIGH during
REFRESH command period (tRFC [MIN]) else
CKE is LOW (i.e., during standby).
Figure 8: Derating Data Valid Window
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
3.750
3.700
3.650
3.600
3.550
3.400
3.500
3.450
3.350
3.300
3.400
3.350
3.300
3.250
3.200
3.150
3.250
3.100
3.050
NA -335
3.000
2.950
t
-262/-26A/-265 @ CK = 10ns
-202 @ CK = 10ns
-262/-26A/-265 @ CK = 7.5ns
-202 @ CK = 8ns
2.900
t
t
t
2.500
2.463
2.425
2.388
2.350
2.313
2.275
2.238
2.200
2.163
2.125
50/50
49.5/50.5
49/51
48.5/52.5
48/52
47.5/53.5
47/53
46.5/54.5
46/54
45.5/55.5
45/55
Clock Duty Cycle
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
21
512MB, 1GB (x64)
200-PIN DDR SODIMM
t
t
30. tHP min is the lesser of CL minimum and CH
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
f. The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
31. READs and WRITEs with auto precharge are not
allowed to be issued until tRAS(MIN) can be satis-
fied prior to the internal precharge command
being issued.
34. The voltage levels used are derived from a mini-
mum VDD level and the referenced test load. In
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
35. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a
pulse widthꢀ? 3ns and the pulse width can not be
greater than 1/3 of the cycle rate. VIL undershoot:
VIL (MIN) = -1.5V for a pulse width ?ꢀ 3ns and the
pulse width can not be greater than 1/3 of the
cycle rate.
32. Any positive glitch must be less than 1/3 of the
clock and not more than +400mV or 2.9V, which-
ever is less. Any negative glitch must be less than
1/3 of the clock cycle and not exceed either -
300mV or 2.2V, whichever is more positive.
33. Normal Output Drive Curves:
a. The full variation in driver pull-down current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 9,
Pull-Down Characteristics.
b. The variation in driver pull-down current
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 9, Pull-Down Characteristics.
c. The full variation in driver pull-up current
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 10,
Pull-Up Characteristics.
d. The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
10, Pull-Up Characteristics.
e. The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
36. VDD and VDDQ must track each other.
37. This maximum value is derived from the refer-
enced test load. In practice, the values obtained
in a typical terminated design may reflect up to
t
t
310ps less for HZ(MAX) and the last DVW. HZ
t
t
(MAX) will prevail over DQSCK (MAX) + RPST
(MAX) condition. tLZ (MIN) will prevail over
tDQSCK (MIN) + tRPRE (MAX) condition.
38. For slew rates greater than 1V/ns the (LZ) transi-
tion will start about 310ps earlier.
39. During Initialization, VDDQ, VTT, and VREF must
be equal to or less than VDD + 0.3V. Alternatively,
VTT may be 1.35V maximum during power up,
even if VDD/VDDQ are 0.0V, provided a minimum
of 42ꢁ of series resistance is used between the VTT
supply and the input pin.
40. The current Micron part operates below the slow-
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
Figure 9: Pull-Down Characteristics
Figure 10: Pull-Up Characteristics
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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512MB, 1GB (x64)
200-PIN DDR SODIMM
41. For -265, -26A, -262 and -335, IDD3N is specified to
be 35mA at 100 MHz.
42. Random addressing changing and 50 percent of
data changing at every transfer.
similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are similar,
IDD2F is “worst case.”
43. Random addressing changing and 100 percent of
data changing at every transfer.
44. CKE must be active (high) during the entire time a
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
46. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
47. Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
tREF later.
48. When an input signal is HIGH or LOW, it is
defined as a steady state logic HIGH or LOW.
45. IDD2N specifies the DQ, DQS, and DM to be
driven to a valid high or low logic level. IDD2Q is
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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512MB, 1GB (x64)
200-PIN DDR SODIMM
SPD Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shown in Figure 11, Data Validity, and Figure 12, Defi-
nition of Start and Stop).
SPD Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shwon in Fig-
ure 13, Acknowledge Response From Receiver).
SPD Start Condition
The SPD device will always respond with an
acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
SPD Stop Condition
All communications are terminated by a stop condi-
tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.
Figure 11: Data Validity
Figure 12: Definition of Start and Stop
SCL
SCL
SDA
SDA
DATA STABLE
DATA
CHANGE
DATA STABLE
START
BIT
STOP
BIT
Figure 13: Acknowledge Response From Receiver
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 17: EEPROM Device Select Code
Most significant bit (b7) is sent first.
DEVICE TYPE IDENTIFIER
CHIP ENABLE
RW
B0
SELECT CODE
b7
b6
b5
b4
b3
b2
b1
Memory Area Select Code (two arrays)
Protection Register Select Code
1
0
0
1
1
1
0
0
SA2
SA2
SA1
SA1
SA0
SA0
RW
RW
Table 18: EEPROM Operating Modes
MODE
RW BIT
WC
BYTES INITIAL SEQUENCE
1
0
1
1
0
0
VIH or VIL
VIH or VIL
VIH or VIL
VIH or VIL
VIL
1
1
Current Address Read
Random Address Read
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
1
O 1
1
Sequential Read
Byte Write
VIL
? 16
Page Write
START, Device Select, RW = ‘0’
Figure 14: SPD EEPROM Timing Diagram
t
t
t
F
HIGH
R
t
LOW
SCL
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
SDA IN
t
t
t
DH
AA
BUF
SDA OUT
UNDEFINED
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 19: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
VDDSPD
VIH
VIL
2.3
3.6
V
V
SUPPLY VOLTAGE
VDD Pꢀ0.7 VDD + 0.5
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
-1
–
VDD Pꢀ0.3
V
VOL
ILI
0.4
10
10
30
2
V
OUTPUT LOW VOLTAGE: IOUT = 3mA
–
µA
µA
µA
mA
INPUT LEAKAGE CURRENT: VIN = GND to VDD
OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD
STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VDD or VSS
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
ILO
–
ISB
–
ICC
–
Table 20: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V TO +3.6V
PARAMETER/CONDITION
SYMBOL
MIN MAX UNITS
NOTES
tAA
tBUF
0.2
1.3
0.9
µs
µs
1
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
tDH
200
ns
tF
300
ns
2
SDA and SCL fall time
tHD:DAT
tHD:STA
tHIGH
tI
tLOW
tR
fSCL
tSU:DAT
tSU:STA
tSU:STO
tWRC
0
µs
Data-in hold time
0.6
0.6
µs
Start condition hold time
Clock HIGH period
µs
50
ns
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
1.3
µs
0.3
µs
2
SDA and SCL rise time
400
KHz
ns
SCL clock frequency
100
0.6
0.6
Data-in setup time
µs
3
4
Start condition setup time
Stop condition setup time
WRITE cycle time
µs
10
ms
NOTE:
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising
edge of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 21: Serial Presence-Detect Matrix
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 29
BYTE
DESCRIPTION
ENTRY (VERSION)
MT16VDDF6464H MT16VDDF12864H
0
1
2
3
4
5
6
7
8
9
128
80
08
07
0D
0A
02
40
00
04
80
08
07
0D
0B
02
40
00
04
Number of Bytes Used by Micron
Total Number of Bytes in SPD Device
Fundamental Memory Type
256
SDRAM DDR
13
Number of Rows Addresses on Assembly
Number of Column Addresses on Assembly
Number of Physical Ranks on DIMM
Module Data With
11, 12
2
64
0
Module Data With (Continued)
Moduel Voltage Interface Levels
SDRAM Cycle Time, (tCK), CAS Latency = 2.5
(See note 1)
SSTL 2.5V
6ns (-335)
7ns (-262/-26A)
7.5ns( -265)
8ns (-202)
60
70
75
80
60
70
75
80
SDRAM Access From Clock,(tAC),
CAS Latency = 2.5
10
0.7ns (-335)
0.75ns (-262/-26A/-265)
0.8ns (-202)
70
75
80
70
75
80
11
12
13
14
15
Non-ECC
7.8µs/SELF
x8
00
82
08
00
01
00
82
08
00
01
Module Configuration Type
Refresh Rate/Type
SDRAM Device Width (Primary SDRAM)
Error-checking SDRAM Data Width
Non-ECC
1 clock
Minimum Clock Delay, Back-to-Back Random
Column Access
16
17
18
19
20
21
22
23
Burst Lengths Supported
Number of Banks on SDRAM Device
CAS Latencies Supported
CS Latency
2, 4, 8
0E
04
0C
01
02
20
C0
0E
04
0C
01
02
20
C0
4
2, 2.5
0
WE Latency
1
SDRAM Module Attributes
SDRAM Device Attributes: General
SDRAM Cycle Time, (tCK), CAS Latency = 2
(See note 1)
Unbuffered/Diff. Clock
Fast/Concurrent AP
7.5ns (-335/-262/-26A)
10ns (-265/-202)
75
A0
75
A0
SDRAM Access From CK, (tAC), CAS Latency = 2
24
0.7ns (-335)
0.75ns (-262/-26A/-265)
0.8ns (-202)
70
75
80
70
75
80
SDRAM Cycle Time, (tCK), CAS Latency = 1.5
SDRAM Access From CK, (tAC),
CAS Latency = 1.5
25
26
N/A
00
00
N/A
00
00
Minimum Row Precharge Time, (tRP)
27
18ns (-335)
15ns (-262)
20ns (-26A/-265/-202)
48
3C
50
48
3C
50
Minimum Row to Row Active, (tRRD)
Minimum RAS# to CAS# Delay, (tRCD)
28
29
12ns (-335)
15 ns (-262/-26A/-265/-202)
30
3C
30
3C
18ns (-335)
15ns (-262)
20ns (-26A/-265/-202)
48
3C
50
48
3C
50
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 21: Serial Presence-Detect Matrix (Continued)
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 29
BYTE
DESCRIPTION
ENTRY (VERSION)
MT16VDDF6464H MT16VDDF12864H
Minimum RAS# Pulse Width, (tRAS)
(See note 2)
30
42ns (-335)
45ns (-262/-26A/-265)
40ns (-202)
2A
2D
28
2A
2D
28
31
32
256MB, 512MB
40
80
Module Rank Density
Address and Command Setup Time, (tIS)
(See note 3)
0.8ns (-335)
1ns (-262/-26A/-265)
1.1ns (-202)
80
A0
B0
80
A0
B0
Address and Command Hold Time, (tIH)
(See note 3)
33
34
35
0.8ns (-335)
1ns (-262/-26A/-265)
1.1ns (-202)
80
A0
B0
80
A0
B0
Data/ Data Mask Input Setup Time, (tDS)
0.45ns (-335)
0.5ns (-262/-26A/-265)
0.6ns (-202)
45
50
60
45
50
60
Data/ Data Mask Input Hold Time, (tDH)
0.45ns (-335)
0.5ns (-262/-26A/-265)
0.6ns (-202)
45
50
60
45
50
60
36-40 Reserved
41
00
00
Minimum Active Auto Refresh Time (tRC)
60ns (-335/-262)
65ns (-26A/-265)
70ns (-202)
3C
41
46
3C
41
46
42
72ns (-335)
75ns (-262/-26A/-265)
80ns (-202)
48
4B
50
48
4B
50
Minimum Auto Refresh to Active/Auto Refresh
Command Period, (tRFC)
SDRAM Device Max Cycle Time (tCKMAX)
43
44
12ns (-335)
13ns (-262/-26A/-265/-202)
30
34
30
34
0.40ns (-335)
0.5ns (-262/-26A/-265)
0.6ns (-202)
28
32
3C
28
32
3C
SDRAM Device Max DQS-DQ Skew Time
(tDQSQ)
45
SDRAM Device Max Read Data Hold Skew
Factor (tQHS)
0.5ns (-335)
0.75ns (-26A/-265)
1.0ns (-202)
50
75
A0
50
75
A0
46
47
00
01
00
10
00
01
00
10
Reserved
DIMM Height
Reserved
48–61
62
Release 1.0
SPD Revision
Checksum for Bytes 0-62
63
-335
-262
-26A
-265
-202
30
BB
E8
18
B3
5F
FC
29
59
F4
64
65-71
72
MICRON
2C
00
2C
00
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code (Continued)
Manufacturing Location
01–12
01–0C
01–0D
73-90
91
Variable Data
01-09
Variable Data
01-09
Module Part Number (ASCII)
PCB Identification Code
1-9
0
92
00
00
Identification Code (Continued)
Year of Manufacture in BCD
93
Variable Data
Variable Data
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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512MB, 1GB (x64)
200-PIN DDR SODIMM
Table 21: Serial Presence-Detect Matrix (Continued)
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 29
BYTE
DESCRIPTION
ENTRY (VERSION)
MT16VDDF6464H MT16VDDF12864H
94
Variable Data
Variable Data
–
Variable Data
Variable Data
–
Week of Manufacture in BCD
Module Serial Number
95-98
99-127
Manufacturer-Specific Data (RSVD)
NOTE:
1. Device latencies used for SPD values.
2. The value of tRAS used for -262/-26A/-265 modules is calculated from tRC - tRP. Actual device spec value is 40 ns.
3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is
represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-
mum slew rate is met.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
29
512MB, 1GB (x64)
200-PIN DDR SODIMM
Figure 15: 200-PIN SODIMM Dimensions – 512MB
FRONT VIEW
0.150 (3.80)
MAX
2.666 (67.72)
2.656 (67.45)
0.079 (2.00) R
(2X)
U1
U2
U3
U4
U5
U6
1.255 (31.88)
1.245 (31.62)
0.071 (1.80)
(2X)
U7
U8
0.787 (20.00)
TYP
U17
0.236 (6.00)
0.096 (2.44)
0.043 (1.10)
0.035 (0.90)
0.079 (2.00)
0.039 (.99)
TYP
0.018 (.46)
TYP
0.024 (.61)
TYP
PIN 199
PIN 1
2.504 (63.60)
TYP
BACK VIEW
U9
U10
U11
U12
U13
U14
U15
U16
PIN 200
PIN 2
NOTE:
MAX
MIN
All dimensions are in inches (millimeters)
or typical where noted.
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
30
512MB, 1GB (x64)
200-PIN DDR SODIMM
Figure 16: 200-PIN SODIMM Dimensions – 1GB
FRONT VIEW
0.150 (3.80)
MAX
2.666 (67.72)
2.656 (67.45)
U17
0.079 (2.00) R
(2X)
U1
U5
U2
U6
U3
U4
U8
1.255 (31.88)
1.245 (31.62)
0.071 (1.80)
(2X)
U7
0.787 (20.00)
TYP
0.236 (6.00)
0.096 (2.44)
0.043 (1.10)
0.035 (0.90)
0.079 (2.00)
0.039 (.99)
TYP
0.018 (.46)
TYP
0.024 (.61)
TYP
PIN 199
PIN 1
2.504 (63.60)
TYP
BACK VIEW
U9
U10
U14
U11
U12
U16
U13
U15
PIN 200
PIN 2
NOTE:
MAX
MIN
All dimensions are in inches (millimeters)
or typical where noted.
Data Sheet Designation
Released (No Mark): This data sheet contains mini-
mum and maximum limits specified over the complete
power supply and temperature range for production
devices. Although considered final, these specifica-
tions are subject to change, as further product devel-
opment and data characterization sometimes occur.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
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DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice..
©2003 Micron Technology, Inc
31
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