MT28F322D20FH-805TET

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

MT28F322D20

MT28F322D18

FLASH MEMORY

Low Voltage, Extended Temperature

0.18µm Process Technology

FEATURES

• Flexible dual-bank architecture

– Support for true concurrent operation with zero

latency

BALL ASSIGNMENT

58-Ball FBGA

– Read bank a during program bank b and vice versa

– Read bank a during erase bank b and vice versa

• Basic configuration:

1

2

3

4

5

6

7

8

Seventy-one erasable blocks

– Bank a (8Mb for data storage)

– Bank b (24Mb for program storage)

• V^CC, VCCQ, VPP voltages

A11

A8

V

SS

V

CC

V

PP

A18

A6

A4

A

B

C

D

E

A12

A13

A15

A9

A20

CLK

ADV#

A16

RST#

WE#

DQ12

DQ2

A17

A19

WP#

DQ1

DQ9

A5

A7

A3

A2

A10

– 1.70V (MIN), 1.90V (MAX) V^CC, VCCQ

(MT28F322D18 only)

WAIT#

DQ6

A14

A1

– 1.80V VCC, VCCQ (MIN); 2.20V VCC (MAX)and 2.25V

V^CCQ (MAX) (MT28F322D20 only)

– 0.9V (TYP) VPP (in-system PROGRAM/ERASE)

– 12V 5ꢀ (ꢁV) VPP tolerant (factory programming

compatibility)

V

CCQ

DQ15

DQ14

CE#

DQ0

DQ8

A0

DQ4

DQ13

DQ5

V

SS

DQ10

DQ3

OE#

F

DQ11

DQ7

V

SSQ

VCCQ

VSSQ

G

VCC

• Random access time: 70ns/80ns @ 1.70V V^CC

• Burst Mode read access (MT28F322D20)

– MAX clock rate: 54 Mꢁz (^tCLK = 18.5ns)

– Burst latency: 70ns @ 1.80V VCC and 54 Mꢁz

– ^tACLK: 17ns @ 1.80V VCC and 54 Mꢁz

• Page Mode read access¹

Top View

(Ball Down)

NOTE: See page 7 for Ball Description Table.

– Eight-word page

See page 43 for mechanical drawing.

– Interpage read access: 70ns/80ns @ 1.80V

– Intrapage read access: 30ns @ 1.80V

• Low power consumption (V^CC= 2.20V)

– Asynchronous READ < 15mA (MAX)

– Standby < 50µA

– Automatic power saving feature (APS)

• Enhanced write and erase suspend options

– ERASE-SUSPEND-to-READ within same bank

– PROGRAM-SUSPEND-to-READ within same bank

– ERASE-SUSPEND-to-PROGRAM within same bank

• Dual 64-bit chip protection registers for security

purposes

OPTIONS

MARKING

• Timing

70ns access

80ns access

• Frequency

54 MHz

40 MHz

No burst operation

• Boot Block Configuration

Top

Bottom

• Package

58-ball FBGA (8 x 7 ball grid)

• Operating Temperature Range

Extended (-40ºC to +85ºC)

-70

-80

5²

4

None

T

B

• Cross-compatible command support

– Extended command set

– Common flash interface

• PROGRAM/ERASE cycle

FH

ET

– 100,000 WRITE/ERASE cycles per block

NOTE: 1. Data based on MT28F322D20 device.

2. A “5” in the part mark represents two different

frequencies: 54 Mꢁz (MT28F322D20) or 52 Mꢁz

(MT28F322D18)

Part Number Example:

MT28F322D20FH-804 BET

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

1

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

GENERAL DESCRIPTION

The MT28F322D20 and MT28F322D18 are high-

performance, high-density, nonvolatile Flash memory

solutions that can significantly improve system perfor-

mance. This new architecture features a two-memory-

bank configuration that supports dual-bank operation

with no latency.

PleaserefertotheMicronWebsite(www.micron.com/

flash) for the latest data sheet.

ARCHITECTURE AND MEMORY

ORGANIZATION

The Flash devices contain two separate banks of

memory (bank a and bank b) for simultaneous READ and

WRITEoperationsandareavailableinthefollowingbank

segmentation configuration:

A high-performance bus interface allows a fast burst

or page mode data transfer; a conventional asynchro-

nous bus interface is provided as well.

The devices allow soft protection for blocks, as read-

only, by configuring soft protection registers with dedi-

cated command sequences. For security purposes, two

64-bit chip protection registers are provided.

The embedded WORD WRITE and BLOCK ERASE

functions are fully automated by an on-chip write state

machine (WSM). Two on-chip status registers, one for

each of the two memory partitions, can be used to moni-

tor the WSM status and to determine the progress of the

program/erase task.

The erase/program suspend functionality allows

compatibility with existing EEPROM emulation software

packages.

The devices are manufactured using 0.18µm process

technology.

• Bank a is one-fourth of the memory containing

8 x 4K-word parameter blocks, while the remainder

of bank a is split into 15 x 32K-word blocks.

• Bank b represents three-fourths of the memory, is

equallysectored,andcontains48x32K-wordblocks.

Figures 2 and 3 show the bottom and top memory

organizations.

DEVICE MARKING

Due to the size of the package, Micron’s standard part

number is not printed on the top of each device. Instead,

an abbreviated device mark comprised of a five-digit

alphanumericcodeisused.Theabbreviateddevicemarks

are cross referenced to the Micron part numbers in

Table 1.

Table 1

Cross Reference for Abbreviated Device Marks

PRODUCT

MARKING

SAMPLE

MARKING

MECHANICAL

SAMPLE MARKING

PART NUMBER

MT28F322D20FH-705TET

MT28F322D20FH-705 BET

MT28F322D20FH-804TET

MT28F322D20FH-804 BET

MT28F322D18FH-705TET

MT28F322D18FH-705 BET

MT28F322D18FH-804TET

MT28F322D18FH-804 BET

FW546

FW547

FW548

FW549

FW558

FW559

FW543

FW542

FX546

FX547

FX548

FX549

FX558

FX559

FX543

FX542

FY546

FY547

FY548

FY549

FY558

FY559

FY543

FY542

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

PART NUMBERING INFORMATION

Micron’s low-power devices are available with sev-

eral different combinations of features (see Figure 1).

Valid combinations of features and their corresponding

part numbers are listed in Table 2.

Figure 1

Part Number Chart

MT 28F 322 D20FH-80 4 B ET

Micron Technology

Operating Temperature Range

ET = Extended (-40ºC to +85ºC)

Flash Family

Boot Block Starting Address

B = Bottom boot

28F = Dual-Supply Flash

T = Top boot

Density/Organization/Banks

322 = 32Mb (2,048K x 16)

bank a = 1/4; bank b = 3/4

Burst Mode Frequency

Blank = None

4 = 40 MHz

5 = 54 MHz (MT28F322D20) or

52 MHz (MT28F322D18)

Read Mode Operation

D = Asynchronous/Page/Burst Read

Access Time

-70 = 70ns

-80 = 80ns

Operating Voltage Range

18 = 1.70V–1.90V

20 = 1.80V–2.20V VCC

20 = 1.80V–2.25V VCC

Q

Package Code

FH = 58-ball FBGA (8 x 7 grid)

Table 2

Valid Part Number Combinations

BOOT BLOCK

STARTING

ADDRESS

BURST

OPERATING

ACCESS

TIME (ns)

FREQUENCY TEMPERATURE

PART NUMBER

(MHz)

RANGE

MT28F322D20FH-705 BET

MT28F322D20FH-705 TET

MT28F322D20FH-804 BET

MT28F322D20FH-804 TET

MT28F322D18FH-705 BET

MT28F322D18FH-705 TET

MT28F322D18FH-804 BET

MT28F322D18FH-804 TET

70

80

70

80

Bottom

Top

Bottom

Top

Bottom

Top

Bottom

Top

54

40

52

40

-40^oC to +85^oC

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

3

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

FUNCTIONAL BLOCK DIAGRAM

PR Lock

Query

Query/OTP

OTP

DQ0–DQ15

Manufacturer’s ID

Device ID

Block Lock

RCR

X DEC

Bank 1 Blocks

Data Input

Buffer

Y/Z DEC

Y/Z Gating/Sensing

Data

Register

ID Reg.

RST#

CE#

Status

Reg.

CSM

WE#

OE#

Program/

Erase

Pump Voltage

Generators

DQ0–DQ15

WSM

Output

Multiplexer

Output

Buffer

I/O Logic

Address

Input

Buffer

A0–A20

Address

CNT WSM

WAIT#

Address

Multiplexer

Y/Z DEC

X DEC

Y/Z Gating/Sensing

Bank 2 Blocks

ADV#

CLK

Address Latch

BSM

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

Figure 2

Bottom Boot Block Device

Bank b = 24Mb

Block Size

Bank a = 8Mb

Block Size

Block

Address Range

(x16)

1F8000h-1FFFFFh

Block

Address Range

(x16)

078000h-07FFFFh

(K-bytes/K-words)

64/32

(K-bytes/K-words)

64/32

8/4

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

1F0000h-1F7FFFh

1E8000h-1EFFFFh

1E0000h-1E7FFFh

1D8000h-1DFFFFh

1D0000h-1D7FFFh

1C8000h-1CFFFFh

1C0000h-1C7FFFh

1B8000h-1BFFFFh

1B0000h-1B7FFFh

1A8000h-1AFFFFh

1A0000h-1A7FFFh

198000h-19FFFFh

190000h-197FFFh

188000h-18FFFFh

180000h-187FFFh

178000h-17FFFFh

170000h-177FFFh

168000h-16FFFFh

160000h-167FFFh

158000h-15FFFFh

150000h-157FFFh

148000h-14FFFFh

140000h-147FFFh

138000h-13FFFFh

130000h-137FFFh

128000h-12FFFFh

120000h-127FFFh

118000h-11FFFFh

110000h-117FFFh

108000h-10FFFFh

100000h-107FFFh

0F8000h-0FFFFFh

0F0000h-0F7FFFh

0E8000h-0EFFFFh

0E0000h-0E7FFFh

0D8000h-0DFFFFh

0D0000h-0D7FFFh

0C8000h-0CFFFFh

0C0000h-0C7FFFh

0B8000h-0BFFFFh

0B0000h-0B7FFFh

0A8000h-0AFFFFh

0A0000h-0A7FFFh

098000h-097FFFh

090000h-097FFFh

088000h-087FFFh

080000h-087FFFh

070000h-077FFFh

068000h-067FFFh

060000h-067FFFh

058000h-05FFFFh

050000h-057FFFh

048000h-04FFFFh

040000h-047FFFh

038000h-03FFFFh

030000h-037FFFh

028000h-02FFFFh

020000h-027FFFh

018000h-01FFFFh

010000h-017FFFh

008000h-00FFFFh

007000h-007FFFh

006000h-006FFFh

005000h-005FFFh

004000h-004FFFh

003000h-003FFFh

002000h-002FFFh

001000h-001FFFh

000000h-000FFFh

8/4

0

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

5

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

Figure 3

Top Boot Block Device

Bank a = 8Mb

Block Size

(K-bytes/K-words)

8/4

Bank b = 24Mb

Block Size

Block

Address Range

(x16)

1FF000h-1FFFFFh

Block

Address Range

(x16)

178000h-17FFFFh

(K-bytes/K-words)

64/32

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8/4

64/32

1FE000h-1FEFFFh

1FD000h-1FDFFFh

1FC000h-1FCFFFh

1FB000h-1FBFFFh

1FA000h-1FAFFFh

1F9000h-1F9FFFh

1F8000h-1F8FFFh

1F0000h-1F7FFFh

1E8000h-1EFFFFh

1E0000h-1E7FFFh

1D8000h-1DFFFFh

1D0000h-1D7FFFh

1C8000h-1CFFFFh

1C0000h-1C7FFFh

1B8000h-1BFFFFh

1B0000h-1B7FFFh

1A8000h-1AFFFFh

1A0000h-1A7FFFh

198000h-19FFFFh

190000h-197FFFh

188000h-18FFFFh

180000h-187FFFh

170000h-177FFFh

168000h-16FFFFh

160000h-167FFFh

158000h-15FFFFh

150000h-157FFFh

148000h-14FFFFh

140000h-147FFFh

138000h-13FFFFh

130000h-137FFFh

128000h-12FFFFh

120000h-127FFFh

118000h-11FFFFh

110000h-117FFFh

108000h-10FFFFh

100000h-107FFFh

0F8000h-0FFFFFh

0F0000h-0F7FFFh

0E8000h-0EFFFFh

0E0000h-0E7FFFh

0D8000h-0DFFFFh

0D0000h-0D7FFFh

0C8000h-0CFFFFh

0C0000h-0C7FFFh

0B8000h-0BFFFFh

0B0000h-0B7FFFh

0A8000h-0AFFFFh

0A0000h-0A7FFFh

098000h-09FFFFh

090000h-097FFFh

088000h-08FFFFh

080000h-087FFFh

078000h-07FFFFh

070000h-077FFFh

068000h-06FFFFh

060000h-067FFFh

058000h-05FFFFh

050000h-057FFFh

048000h-04FFFFh

040000h-047FFFh

038000h-03FFFFh

030000h-037FFFh

028000h-02FFFFh

020000h-027FFFh

018000h-01FFFFh

010000h-017FFFh

008000h-00FFFFh

000000h-007FFFh

8

7

6

5

4

3

2

1

0

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

6

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

BALL DESCRIPTIONS

58-BALL FBGA

NUMBERS

SYMBOL

TYPE

DESCRIPTION

E8, D8, C8, B8,

A8, B7, A7, C7,

A2, B2, C2, A1,

B1, C1, D2, D1,

D4, B6, A6, C6,

B3

A0–A20

Input

Address Inputs: Inputs for the addresses during READ and WRITE

operations. Addresses are internally latched during READ and WRITE

cycles.

B4

CLK

Input

Clock: Synchronizes the Flash memory to the system operating frequency

during synchronous burst mode READ operations. When configured for

synchronous burst mode READs, address is latched on the first rising (or

falling, depending upon the read configuration register setting) CLK edge

when ADV# is active or upon a rising ADV# edge, whichever occurs first.

CLK is ignored during asynchronous access READ and WRITE operations

and during READ PAGE ACCESS operations.¹

C4

ADV#

Input

Address Valid: Indicates that a valid address is present on the address

inputs. Addresses are latched on the rising edge of ADV# during READ

and WRITE operations. ADV# may be tied active during asynchronous

READ and WRITE operations.¹

A5

VPP

Program/Erase Enable: [0.9V–1.95V or 11.4V–12.6V] Operates as input at

logic levels to control complete device protection. Provides factory

programming compatibility when driven to 11.4V–12.6V.

E7

F8

C5

CE#

OE#

WE#

Input

Chip Enable: Activates the device when LOW. When CE# is HIGH, the

device is disabled and goes into standby power mode.

Output Enable: Enables the output buffers when LOW. When OE# is

HIGH, the output buffers are disabled.

Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW,

the cycle is either a WRITE to the command state machine (CSM) or to the

memory array.

B5

RST#

Input

Reset: When RST# is a logic LOW, the device is in reset mode, which drives

the outputs to High-Z and resets the write state machine. When RST# is at

logic HIGH, the device is in standard operation. When RST# transitions

from logic LOW to logic HIGH, the device resets all blocks to locked and

defaults to the read array mode.

D6

WP#

Input

Write Protect: Controls the lock down function of the flexible locking

feature.

F7, E6, E5, G5, DQ0–DQ15

E4, G3, E3, G1,

G7, F6, F5, F4,

Input/

Output

Data Inputs/Outputs: Inputs array data on the second CE# and WE#

cycle during PROGRAM command. Inputs commands to the command

user interface when CE# and WE# are active. DQ0–DQ15 output data

when CE# and OE# are active.

D5, F3, F2, E2

D3

WAIT#

Output

Wait: Provides data valid feedback during continuous burst read access.

The signal is gated by OE# and CE#. This signal is always kept at a valid

logic level.

NOTE: 1. The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. The

WAIT# signal can be ignored when operating in asynchronous or page mode, as it is always held at logic “1” or “0,”

depending on the RCR8 setting (see Table 8).

(continued on next page)

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

7

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

BALL DESCRIPTIONS (continued)

58-BALL FBGA

NUMBERS

SYMBOL

TYPE

DESCRIPTION

A4, G4

VCC

Supply

Device Power Supply: [1.70V–1.90V (MT28F322D18) or 1.80V–2.20V

(MT28F322D20)] Supplies power for device operation.

E1, G6

VCC

Q

Supply

I/O Power Supply: [1.70V–1.90V (MT28F322D18) or 1.80V–2.25V

(MT28F322D20)] Supplies power for input/output buffers.

G2, G8

A3, F1

C3, D7

V

SS

Q

Supply

–

I/O Ground. Do not float any ground ball.

Do not float any ground ball.

V

SS

–

Contact ball is not physically present.

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

8

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

COMMAND STATE MACHINE (CSM)

Commands are issued to the command state ma-

chine (CSM) using standard microprocessor write tim-

ings. The CSM acts as an interface between external

microprocessors and the internal write state machine

(WSM). The available commands are listed in Table 3,

their definitions are given in Table 4, and their descrip-

tions in Table 5. Program and erase algorithms are

automated by an on-chip WSM. (For more specific

information about the CSM transition states, see Micron

technical note TN-28-33, “Command State Machine De-

scription and Command Definition.”

Once a valid PROGRAM/ERASE command is entered,

the WSM executes the appropriate algorithm, which gen-

erates the necessary timing signals to control the device

internallytoaccomplishtherequestedoperation. Acom-

mand is valid only if the exact sequence of WRITEs is

completed. After the WSM completes its task, the WSM

statusbit(SR7)(seeTable7)issettoalogicꢁIGꢁlevel(1),

allowing the CSM to respond to the full command set

again.

CE#, ADV#, and OE# must be at a logic LOW level (VIL),

and WE# and RST# must be at logic ꢁIGꢁ (VIꢁ).

Table6illustratesthebusoperationsforallthemodes:

write, read, reset, standby, and output disable.

When the device is powered up, internal reset cir-

cuitry initializes the chip to a read array mode of opera-

tion. Changing the mode of operation requires that a

command code be entered into the CSM. For each one of

the two memory partitions, an on-chip status register is

available. These two registers allow the progress of the

various operations that can take place on a memory bank

to be monitored. One of the two status registers is inter-

rogated by entering a READ STATUS REGISTER com-

mandontotheCSM(cycle1),specifyinganaddresswithin

the memory partition boundary, and reading the register

data on I/Os DQ0–DQ7 (cycle 2). Status register bits SR0-

SR7 correspond to DQ0–DQ7 (see Table 7).

COMMAND DEFINITION

Once a specific command code has been entered, the

WSM executes an internal algorithm, generating the nec-

essary timing signals to program, erase, and verify data.

See Table 4 for the CSM command definitions and data

for each of the bus cycles.

OPERATIONS

Device operations are selected by entering a standard

JEDEC 8-bit command code with conventional micro-

processor timings into an on-chip CSM through I/Os

DQ0–DQ7. The number of bus cycles required to activate

a command is typically one or two. The first operation is

always a WRITE. Control signals CE#, ADV#, and WE#

must be at a logic LOW level (V^IL), and OE# and RST#

must be at logic ꢁIGꢁ (VIꢁ). The second operation, when

needed, can be a WRITE or a READ depending upon the

command. During a READ operation, control signals

STATUS REGISTER

The status register allows the user to determine

whether the state of a PROGRAM/ERASE operation is

pending or complete. The status register is monitored by

toggling OE# and CE# and reading the resulting status

codeonI/OsDQ0–DQ7.Thehigh-orderI/Os(DQ8–DQ15)

Table 3

Command State Machine Codes For Device Mode Selection

COMMAND DQ0–DQ7

CODE ON DEVICE MODE

40h/10h

20h

Program setup/alternate program setup

Block erase setup

50h

Clear status register

60h

Protection configuration setup

Set read configuration register

Read status register

60h

70h

90h

Read protection configuration register

Read query

98h

B0h

C0h

D0h

FFh

Program/erase suspend

Protection register program/lock

Program/erase resume – erase confirm

Read array

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

9

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

are set to 00h internally, so only the low-order I/Os

(DQ0–DQ7) need to be interpreted. Address lines select

the status register pertinent to the selected memory

partition.

Register data is updated and latched on the falling

edge of ADV# or rising (falling) CLK when ADV# is LOW

during synchronous burst mode or on the falling edge of

OE# or CE#, whichever occurs last. Latching the data

prevents errors from occurring if the register input

changes during a status register monitoring.

The status register provides the internal state of the

WSM to the external microprocessor. During periods

when the WSM is active, the status register can be polled

to determine the WSM status. Table 7 defines the status

register bits.

After monitoring the status register during a PRO-

GRAM/ERASE operation, the data appearing on

DQ0–DQ7 remains as status register data until a new

command is issued to the CSM. To return the device to

other modes of operation, a new command must be

issued to the CSM.

COMMAND STATE MACHINE

OPERATIONS

The CSM decodes instructions for read array, read

protection configuration register, read query, read status

register, clear status register, program, erase, erase sus-

pend, erase resume, program suspend, program resume,

lock block, unlock block and lock down block, chip pro-

tection program, and set read configuration register. The

8-bit command code is input to the device on DQ0–DQ7

(see Table 3 for CSM codes and Table 4 for command

definitions). During a PROGRAM or ERASE cycle, the

CSM informs the WSM that a PROGRAM or ERASE cycle

has been requested.

During a PROGRAM cycle, the WSM controls the pro-

gram sequences and the CSM responds to a PROGRAM

SUSPEND command only.

Table 4

Command Definitions

FIRST BUS CYCLE

SECOND BUS CYCLE

1

COMMAND

READ ARRAY

READ PROTECTION CONFIGURATION REGISTER

READ STATUS REGISTER

CLEAR STATUS REGISTER

READ QUERY

OPERATION ADDRESS

DATA

FFh

90h

70h

50h

98h

20h

40h/10h

B0h

D0h

60h

C0h

60h

OPERATION ADDRESS

DATA

WRITE

WA

IA

READ

IA

X

ID

SRD

BA

QA

BA

WA

BA

PA

READ

WRITE

QA

BA

WA

QD

D0h

WD

BLOCK ERASE SETUP

PROGRAM SETUP/ALTERNATE PROGRAM SETUP

PROGRAM/ERASE SUSPEND

PROGRAM/ERASE RESUME – ERASE CONFIRM

LOCK BLOCK

UNLOCK BLOCK

LOCK DOWN BLOCK

PROTECTION REGISTER PROGRAM

PROTECTION REGISTER LOCK

SET READ CONFIGURATION REGISTER

WRITE

BA

PA

LPA

RCD

01h

D0h

2Fh

PD

LPA

RCD

FFFDh

03h

NOTE: 1. BA: Address within the block

IA: Identification code address

ID: Identification code data

LPA: Lock protection register address

PA: Protection register address

PD: Data to be written at the location PA

QA: Query code address

QD: Query code data

RCD: Data to be written in the read configuration register

SRD: Data read from the status register

WA: Word address of memory location to be written, or read

WD: Data to be written at the location WA

X:

“Don’t Care”

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2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

Table 5

Command Descriptions

CODE DEVICE MODE

10h Alt. Program Setup

20h Erase Setup

BUS CYCLE

First

DESCRIPTION

Operates the same as PROGRAM SETUP command

First

Prepares the CSM for the ERASE CONFIRM command. If the next

command is not an ERASE CONFIRM command, the command will be

ignored, and the bank will go to read status mode and wait for

another command.

40h Program Setup

First

A two-cycle command: The first cycle prepares for a PROGRAM

operation, and the second cycle latches addresses and data and

initiates the WSM to execute the program algorithm. The flash outputs

status register data on the rising edge of ADV#, or on the rising clock

edge when ADV# is LOW during synchronous burst mode, or on the

falling edge of OE# or CE#, whichever occurs first.

50h Clear Status

Register

First

The WSM can set the block lock status (SR1), VPP status (SR3), program

status (SR4), and erase status (SR5) bits in the status register to “1,” but

it cannot clear them to “0.” Issuing this command clears those bits to

“0.”

60h Protection

Configuration

Setup

Prepares the CSM for changes to the block locking status. If the next

command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK DOWN

the command will be ignored, and the device will go to read status

mode.

Set Read

Configuration

Register

First

Puts the device into the set read configuration mode so that it will

be possible to set the option bits related to burst read mode.

70h Read Status

Register

This command places the device into a read status register mode.

Reading the device will output the contents of the status register for

the addressed bank. The device will automatically enter this mode for

the addressed bank after a PROGRAM or ERASE operation has been

initiated.

90h Read Protection

Configuration

First

Puts the device into the read protection configuration mode so that

reading the device will output the manufacturer/device codes, block

lock status, protection register, or protection register lock status.

98h Read Query

First

Puts the device into the read query mode so that reading the device

will output common flash interface information.

B0h Program/Erase

Suspend

Issuing this command will suspend the currently executing PROGRAM/

ERASE operation. The status register will indicate when the

operation has been successfully suspended by setting either the

program suspend (SR2) or erase suspend (SR6), and the WSM status bit

(SR7) to a “1” (ready). The WSM will continue to idle in the suspend

state, regardless of the state of all input control signals except RST#,

which will immediately shut down the WSM and the remainder of the

chip if RST# is driven to VIL.

C0h Program Device

Protection Register

First

Writes a specific code into the device protection register.

Lock Device

Locks the device protection register; data can no longer be changed.

Protection Register

(continued on next page)

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11

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

Table 5

Command Descriptions (continued)

CODE DEVICE MODE

BUS CYCLE

DESCRIPTION

D0h Erase Confirm

Second

If the previous command was an ERASE SETUP command, then the

CSM will close the address and data latches, and it will begin erasing

the block indicated on the address pins. During programming/erase,

the device will respond only to the READ STATUS REGISTER, PROGRAM

SUSPEND, or ERASE SUSPEND commands. It will output status register

data on the rising edge of ADV#, or on the rising clock edge when

ADV# is LOW during synchronous burst mode, or on the falling edge

of OE# or CE#, whichever occurs last.

Program/Erase

Resume

First

If a PROGRAM or ERASE operation was previously suspended, this

command will resume the operation.

FFh Read Array

01h Lock Block

First

During read array mode, array data will be output on the data bus.

Second

If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM will latch the address and lock the block indicated on the

address bus.

03h Read Configuration Second

Register Data

If the previous command was SET READ CONFIGURATION REGISTER,

the configuration bits presented on the address bus will be stored into

the read configuration register.

2Fh Lock Down

Second

If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM will latch the address and lock down the block indicated on

the address bus.

D0h Unlock Block

If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM will latch the address and unlock the block indicated on the

address bus. If the block had been previously set to lock down, this

operation will have no effect.

00h Invalid/Reserved

Unassigned command that should not be used.

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ASYNC/PAGE/BURST FLASH MEMORY

DuringanERASEcycle,theCSMrespondstoanERASE

SUSPEND command only. When the WSM has com-

pleted its task, the WSM status bit (SR7) is set to a logic

ꢁIGꢁ level and the CSM responds to the full command

set. The CSM stays in the current command state until

the microprocessor issues another command.

The WSM successfully initiates an ERASE or PRO-

GRAM operation only when VPP is within its correct volt-

age range.

ister, the protection register, and PR lock status. Two bus

cycles are required for this operation: the chip identifica-

tion data is read by entering the command code 90h on

DQ0–DQ7 to the bank containing address 00h and the

identification code address on the address lines. Control

signals CE#, ADV#, and OE# must be at a logic LOW level

(V^IL), and WE# and RST# must be at a logic ꢁIGꢁ level

(VIꢁ) to read data from the protection configuration reg-

ister. Data is available on DQ0–DQ15. After data is read

from the protection configuration register, the READ

ARRAY command, FFh, must be issued to the bank con-

tainingaddress00hpriortoissuingothercommands. See

Table 12 for further details.

CLEAR STATUS REGISTER

The internal circuitry can set, but not clear, the block

lock status bit (SR1), the V^PPstatus bit (SR3), the program

status bit (SR4), and the erase status bit (SR5) of the status

register. The CLEAR STATUS REGISTER command (50h)

allows the external microprocessor to clear these status

bits and synchronize to the internal operations. When

the status bits are cleared, the device returns to the read

array mode.

READ QUERY

Thereadquerymodeoutputscommonflashinterface

(CFI) data when the device is read (see Table 16). Two bus

cycles are required for this operation. It is possible to

access the query by writing the read query command

code 98h on DQ0–DQ7 to the bank containing address

0h. Control signals CE#, ADV#, and OE# must be at a logic

LOW level (VIL) and WE# and RST# must be at a logic

ꢁIGꢁlevel(V^Iꢁ)toreaddatafromthequery. TheCFIdata

structure contains information such as block size, den-

sity, command set, and electrical specifications. To re-

turn to read array mode, write the read array command

code FFh on DQ0–DQ7.

READ OPERATIONS

The following READ operations are available: READ

ARRAY, READ PROTECTION CONFIGURATION REGIS-

TER, READ QUERY and READ STATUS REGISTER.

READ ARRAY

The array is read by entering the command code FFh

on DQ0–DQ7. Control signals CE#, ADV#, and OE# must

be at a logic LOW level (V^IL) and WE# and RST# must be

at a logic ꢁIGꢁ level (V^Iꢁ) to read data from the array.

Data is available on DQ0–DQ15. Any valid address within

any of the blocks selects that address and allows data to

be read from that address. Upon initial power-up or

device reset, the device defaults to the read array mode.

READ STATUS REGISTER

The status register is read by entering the command

code 70h on DQ0–DQ7. Two bus cycles are required for

this operation: one to enter the command code and a

second to read the status register. The address for both

cycles must be in the same partition. In a READ cycle, the

address is latched on the rising edge of the ADV# signal.

Registerdataisupdatedandlatchedonthefallingedgeof

ADV# or rising (falling) CLK when ADV# is LOW during

burst mode, or on the falling edge of OE# or CE#, which-

ever occurs last.

READ PROTECTION CONFIGURATION DATA

The read protection configuration mode outputs five

types of information: the manufacturer/device identi-

fier, the block locking status, the read configuration reg-

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2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

Table 6

Bus Operations

MODE

RST#

CE#

ADV#

OE#

WE#

ADDRESS DQ0–DQ15

Read (array, status registers,

device identification register, or

query)

V^IH

VIL

VIH

X

DOUT

Standby

Output disable

Reset

VIH

VIL

VIH

X

High-Z

DIN

X

Write

VIH

VIL

VIH

VIL

Table 7

Status Register Bit Definitions

WSMS

ESS

ES

PS

VPPS

PSS

BLS

R

7

6

5

4

3

2

1

0

STATUS

BIT # STATUS REGISTER BIT

DESCRIPTION

WRITE STATE MACHINE STATUS (WSMS) Check write state machine bit first to determine word

SR7

1 = Ready

0 = Busy

program or block erase completion, before checking program

or erase status bits.

SR6

ERASE SUSPEND STATUS (ESS)

1 = BLOCK ERASE Suspended

0 = BLOCK ERASE in

When ERASE SUSPEND is issued, WSM halts execution and

sets both WSMS and ESS bits to “1.” ESS bit remains set to “1”

until an ERASE RESUME command is issued.

Progress/Completed

SR5

SR4

SR3

ERASE STATUS (ES)

1 = Error in Block Erasure

0 = Successful BLOCK ERASE

When this bit is set to “1,” WSM has applied the maximum

number of erase pulses to the block and is still unable to

verify successful block erasure.

PROGRAM STATUS (PS)

1 = Error in PROGRAM

0 = Successful PROGRAM

When this bit is set to “1,” WSM has attempted but failed to

program a word.

VPP STATUS (VPPS)

1 = VPP Low Detect, Operation

Abort

The VPP status bit does not provide continuous indication of

the VPP level. The WSM interrogates the VPP level only after

the program or erase command sequences have been entered

and informs the system if VPP < 0.9V. The VPP level is also

checked before the PROGRAM/ERASE is verified by the WSM.

0 = VPP = OK

SR2

SR1

PROGRAM SUSPEND STATUS (PSS)

1 = PROGRAM Suspended

0 = PROGRAM in Progress/Completed

When PROGRAM SUSPEND is issued, WSM halts execution and

sets both WSMS and PSS bits to “1.” PSS bit remains set to “1”

until a PROGRAM RESUME command is issued.

BLOCK LOCK STATUS (BLS)

If a PROGRAM or ERASE operation is attempted to one of the

locked blocks, this is set by the WSM. The operation specified

is aborted and the device is returned to read status mode.

1 = PROGRAM/ERASE Attempted on a

Locked Block; Operation Aborted

0 = No Operation to Locked Blocks

SR0

RESERVED FOR FUTURE ENHANCEMENT This bit is reserved for future use.

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2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

PROGRAMMING OPERATIONS

There are two CSM commands for programming:

PROGRAM SETUP and ALTERNATE PROGRAM SETUP

(see Table 3).

Block erasure inside the memory array sets all bits

within the address block to logic 1s. Erase is accom-

plished only by blocks; data at single address locations

within the array cannot be erased individually. The block

to be erased is selected by using any valid address within

that block. Block erasure is initiated by a command se-

quence to the CSM: BLOCK ERASE SETUP (20h) followed

by BLOCK ERASE CONFIRM (D0h) (see Figure 6). A two-

command erase sequence protects against accidental

erasure of memory contents.

WhentheBLOCKERASECONFIRMcommandiscom-

plete, the WSM automatically executes a sequence of

events to complete the block erasure. During this se-

quence, the block is programmed with logic 0s, data is

verified, all bits in the block are erased to logic 1 state, and

finally verification is performed to ensure that all bits are

correctly erased. The ERASE operation may be moni-

tored through the status register (see the Status Register

section).

During the execution of an ERASE operation, the

ERASE SUSPEND command (B0h) can be entered to di-

rect the WSM to suspend the ERASE operation. Once the

WSM has reached the suspend state, it allows the CSM to

respond only to the READ ARRAY, READ STATUS REGIS-

TER, READ QUERY, READ CꢁIP PROTECTION CON-

FIGURATION, PROGRAM SETUP, PROGRAM RESUME,

ERASERESUMEandLOCKSETUP(seetheBlockLocking

section). During the ERASE SUSPEND operation, array

data must be read from a block other than the one being

erased. To resume the ERASE operation, an ERASE RE-

SUME command (D0h) must be issued to cause the CSM

to clear the suspend state previously set (see Figure 7). It

is also possible to suspend an ERASE in any bank and

initiate a WRITE to another block in the same bank. After

the completion of a WRITE, an ERASE can be resumed by

writing an ERASE RESUME command.

After the desired command code is entered (10h or

40h command code on DQ0–DQ7), the WSM takes over

and correctly sequences the device to complete the PRO-

GRAM operation. Monitoring of the WRITE operation is

possible through the status register (see the Status Regis-

ter section). During this time, the CSM responds only to

a PROGRAM SUSPEND command until the PROGRAM

operationhasbeencompleted, afterwhichallcommands

to the CSM become valid again. The PROGRAM opera-

tion can be suspended by issuing a PROGRAM SUSPEND

command (B0h). Once the WSM has reached the sus-

pend state, it allows the CSM to respond only to READ

ARRAY, READ STATUS REGISTER, READ PROTECTION

CONFIGURATION, READ QUERY, PROGRAM SETUP, or

PROGRAM RESUME. During the PROGRAM SUSPEND

operation, array data should be read from an address

other than the one being programmed. To resume the

PROGRAM operation, a PROGRAM RESUME command

(D0h) must be issued to cause the CSM to clear the

suspend state previously set (see Figure 4 for program-

ming operation and Figure 5 for program suspend and

program resume).

Taking RST# to V^ILduring programming aborts the

PROGRAM operation. During programming, VPP must

remain in the appropriate V^PPvoltage range as shown in

the recommended operating conditions table.

ERASE OPERATIONS

An ERASE operation must be used to initialize all bits

in an array block to “1s.” After BLOCK ERASE CONFIRM

is issued, the CSM responds only to an ERASE SUSPEND

command until the WSM completes its task.

2 Meg x 16 Async/Page/Burst Flash Memory

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2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

Figure 4

Automated Word Programming

Flowchart

BUS

OPERATION COMMAND COMMENTS

WRITE

PROGRAM

SETUP

Data = 40h or 10h

Addr = Address of word to be

programmed

Start

WRITE

DATA

Data = Word to be

programmed

Issue PROGRAM SETUP

Command and

Addr = Address of word to be

programmed

Word Address

READ

Status register data

Toggle OE# or CE# to

update status register.

Issue Word Address

and Word Data

Standby

Check SR7

1 = Ready, 0 = Busy

PROGRAM

SUSPEND Loop

Read Status Register

Bits

Repeat for subsequent words.

Write FFh after the last word programming operation

to reset the device to read array mode.

NO

PROGRAM

SUSPEND?

SR7 = 1?

YES

Full Status Register

1

Check (optional)

Word Program

Completed

BUS

FULL STATUS REGISTER CHECK FLOW

OPERATION COMMAND COMMENTS

Read Status Register

Bits

Standby

Check SR1

1 = Detect locked block

2

Check SR3

1 = Detect VPP LOW

NO

PROGRAM Attempted

on a Locked Block

SR1 = 0?

YES

3

Check SR4

1 = Word program error

NO

V

PP Range Error

SR3 = 0?

YES

Word Program Failed

SR4 = 0?

YES

Word Program Passed

NOTE: 1. Full status register check can be done after each word or after a sequence of words.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.

3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation

attempts.

2 Meg x 16 Async/Page/Burst Flash Memory

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16

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

Figure 5

PROGRAM SUSPEND/

BUS

OPERATION COMMAND COMMENTS

PROGRAM RESUME Flowchart

WRITE

READ

PROGRAM

SUSPEND

Data = B0h

Status register data

Toggle OE# or CE# to update

status register.

Start

Standby

WRITE

READ

Check SR7

1 = Ready

Issue PROGRAM

SUSPEND Command

Check SR2

1 = Suspended

READ

ARRAY

Data = FFh

Read Status Register

Bits

Read data from block other

than that being programmed

WRITE

PROGRAM

RESUME

Data = D0h

NO

SR7 = 1?

YES

NO

SR2 = 1?

PROGRAM

Complete

YES

Issue READ ARRAY

Command

NO

Finished

Reading

?

YES

Issue PROGRAM

RESUME Command

PROGRAM Resumed

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2 MEG x 16

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Figure 6

BLOCK ERASE Flowchart

BUS

OPERATION COMMAND COMMENTS

WRITE

READ

WRITE

ERASE

SETUP

Data = 20h

Block Addr = Address

within block to be erased

Start

ERASE

Data = D0h

Block Addr = Address

within block to be erased

Issue ERASE SETUP

Command and

Block Address

Status register data

Toggle OE# or CE# to

update status register.

Issue BLOCK ERASE

CONFIRM Command

and Block Address

Standby

Check SR7

1 = Ready, 0 = Busy

ERASE

SUSPEND Loop

Read Status Register

Repeat for subsequent blocks.

Write FFh after the last BLOCK ERASE operation to

reset the device to read array mode.

Bits

NO

ERASE

NO

SR 7 = 1?

SUSPEND?

YES

Full Status Register

1

Check (optional)

BLOCK ERASE

Completed

BUS

OPERATION COMMAND COMMENTS

FULL STATUS REGISTER CHECK FLOW

Standby

Check SR1

1 = Detect locked block

Check SR3²

1 = Detect VPP block

Read Status Register

Bits

Check SR5³

NO

ERASE Attempted

on a Locked Block

1 = BLOCK ERASE error

SR1 = 0?

YES

NO

VPP Range Error

SR3 = 0?

YES

NO

BLOCK ERASE Failed

SR5 = 0?

YES

BLOCK ERASE Passed

NOTE: 1. Full status register check can be done after each block or after a sequence of blocks.

2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.

3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full

status is checked.

2 Meg x 16 Async/Page/Burst Flash Memory

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2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

Figure 7

ERASE SUSPEND/ERASE RESUME

Flowchart

BUS

OPERATION COMMAND COMMENTS

WRITE

ERASE

SUSPEND

Data = B0h

Start

READ

Status register data

Toggle OE# or CE# to

update status register.

Issue ERASE

SUSPEND Command

Standby

WRITE

READ

Check SR7

1 = Ready

Check SR6

1 = Suspended

Read Status Register

Bits

READ

ARRAY

Data = FFh

Read data from block

other than that being

erased.

NO

SR7 = 1?

WRITE

ERASE

Data = D0h

RESUME

YES

NO

SR6 = 1?

ERASE

Complete

YES

PROGRAM

READ or

PROGRAM?

READ

Issue READ ARRAY

Command

PROGRAM

Loop

(Note 1)

READ or

PROGRAM

Complete?

NO

YES

Issue ERASE

RESUME Command

2

ERASE Continued

NOTE: 1. See Word Programming Flowchart for complete programming procedure.

2. See BLOCK ERASE Flowchart for complete erasure procedure.

2 Meg x 16 Async/Page/Burst Flash Memory

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2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

READ-WHILE-WRITE/ERASE

CONCURRENCY

It is possible for the device to read from one bank

while erasing/writing to another bank. Once a bank en-

ters the WRITE/ERASE operation, the other bank auto-

matically enters read array mode. For example, during a

READCONCURRENCYoperation, ifaPROGRAM/ERASE

command is issued in bank a, then bank a changes to the

read status mode and bank b defaults to the read array

mode. The device will read from bank b if the latched

address resides in bank b (see Figure 8). Similarly, if a

PROGRAM/ERASE command is issued in bank b, then

bank b changes to read status mode and bank a defaults

to read array mode. When returning to bank a, the device

will read PROGRAM/ERASE status if the latched address

resides in bank a. A correct bank address must be

specified to read status register after returning from con-

current read in the other bank.

provides the read mode (burst, synchronous, or asyn-

chronous), burstorder, latencycounter, andburstlength.

After executing this command, the device returns to read

array mode.

READ CONFIGURATION

The device supports three read configurations: asyn-

chronous, synchronousburstmode, andpagemode. The

bit RCR15 (see Table 9) in the read configuration register

setsthereadconfiguration. Asynchronousrandommode

is the default read mode.

At power-up, the RCR is set to BBCFh.

Status registers and the device identification register

support asynchronous and single synchronous READ

operations only.

When reading the CFI or the chip protection register,

concurrent operation is not allowed on the top boot

device. Concurrent READ of the CFI or the chip protec-

tion register is only allowed when a PROGRAM or ERASE

operation is performed on bank b on the bottom boot

device. For a bottom boot device, reading of the CFI table

or the chip protection register is only allowed if bank b is

in read array mode. For a top boot device, reading of the

CFI table or the chip protection register is only allowed if

bank a is in read array mode.

Figure 8

READ-While-WRITE Concurrency

Bank a

Bank b

1 - Erasing/writing to bank a

2 - Erasing in bank a can be

suspended, and a WRITE to

another block in bank a

can be initiated.

1 - Reading from bank b

3 - After the WRITE in that block

is complete, an ERASE can

be resumed by writing an

ERASE RESUME command.

READ CONFIGURATION REGISTER (RCR)

MODE

1 - Reading bank a

1 - Erasing/writing to bank b

2 - Erasing in bank b can be

suspended, and a WRITE to

another block in bank b

can be initiated.

3 - After the WRITE in that block

is complete, an ERASE can

be resumed by writing an

ERASE RESUME command.

The SET READ CONFIGURATION REGISTER com-

mand is a WRITE operation to the read configuration

register(RCR). Itisatwo-cyclecommandsequence. Read

configurationsetupiswritten, followedbyasecondwrite

that specifies the data to be written to the read configura-

tion register. The data is placed on the address bus

A0–A15, and it is latched on the rising edge of ADV#, CE#,

or WE#, whichever occurs first. The read configuration

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2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

Table 8

Read Configuration Register

RM

R

LC2

LC1

LC0

R

HDO

WC

15

14

13

12

11

10

9

8

BS

CC

R

BW

BL2

BL1

BL0

7

6

5

4

3

2

1

0

BIT #

DESCRIPTION

FUNCTION

15

Read Mode (RM)

0 = Synchronous Burst Access Mode

1 = Asynchronous/Page Access Mode (Default)

14

Reserved

Default = 0

13-11

Latency Counter (LC)

Sets the number of clock cycles before valid data out:

000 = Code 0 - reserved

001 = Code 1 - reserved

010 = Code 2

011 = Code 3

100 = Code 4

101 = Code 5 - reserved

110 = Code 6 - reserved

111 = Code 7 - reserved (Default)

10

9

Reserved

Default = 0

Hold Data Out (HDO)

Sets the data output configuration:

0 = Hold data for one clock

1 = Hold data for two clocks (Default)

8

7

Wait Configuration (WC)

Burst Sequence (BS)

Controls the behavior of the WAIT# output signal:

0 = WAIT# asserted during delay

1 = WAIT# asserted one data cycle before delay (Default)

Specifies the order in which data is addressed in synchronous burst

mode:

0 = Interleaved

1 = Linear (Default)

6

Clock Configuration (CC)

Defines the clock edge on which the BURST operation starts and

data is referenced:

0 = Falling edge

1 = Rising edge (Default)

5-4

3

Reserved

Default = 0

Burst Wrap (BW)

0 = Burst wraps within the burst length

1 = Burst no wrap (Default)

2-0

Burst Length (BL)

Sets the number of words the device will output in burst mode:

001 = 4 words

010 = 8 words

111 = Continuous burst (Default)

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

21

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

LATENCY COUNTER

The latency counter provides the number of clocks

that must elapse after ADV# is set active before data will

be available. This value depends on the input clock fre-

quency. See Table 9 for the specific input clock frequency

configuration code. See Figure 9 also.

Table 9

Clock Frequency vs. First Access Latency

MAX

LATENCY

CLK CYCLES

SYNC

ACCESS

TIME (ns)

FREQUENCY PERIOD CONFIGURATION FOR FIRST

(MHz)

-705

(ns)

COUNTER

DATA

20

50

33

2

3

4

3

4

5

150

132

92.5

30

54¹

18.5

-804

20

30

40

50

33

25

2

3

4

3

4

5

150

132

125

NOTE: 1. Maximum frequency for the MT28F322D18FH-705 device is 52 MHz.

Figure 9

Latency Counter

V_IH

V_IL

CLK

V_IH

A0–A20

VALID

ADDRESS

V_IL

V_IH

ADV#

DQ0–DQ15

V_IL

Code 2

V_OH

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

V_{O L}

Code 3

Code 4

V_OH

V_{O L}

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

V_OH

V_{O L}

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

UNDEFINED

Figure 10

Hold Data Output Configuration

Figure 11

Wired OR WAIT# Configuration

Wired OR

CLK

WAIT#

READY#

BurstCPU/

Wait State Logic

Hold

Data

1 CLK

MT28F322D18

DQ0–DQ15

Bus data

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

DQ0–DQ15

DATA

.

Hold

Data

2 CLK

VALID

OUTPUT

VALID

OUTPUT

.

WAIT#

MT28F322D18

DQ0–DQ15

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

22

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

HOLD DATA OUTPUT CONFIGURATION

The hold data output configuration specifies for how

many clocks data will be held valid. (See Figure 10.)

A Flash controller (CPU) is able to use this output

signal to drive banks of the devices. An internal 1MΩ

pull-up resistor holds WAIT# = 1 and allows wired OR’ing

multiple bank configurations, as shown in Figure 11.

WAIT# CONFIGURATION

The wait configuration bit, RCR8, sets the behavior of

the WAIT# output signal. The WAIT# signal can be active

during an output delay or one data cycle before delay

when continuous burst length is enabled. WAIT# = 1

indicates valid data when RCR8 = 0. WAIT# = 0 indicates

invalid data when RCR8 = 0. The setting of wait before or

wait during RCR8 will depend on the system and CPU

characteristic. If RCR3 = 1 (no wrap mode), then WAIT#

can also be enabled in a four- or eight-word burst if the

no-wrap burst crosses the first eight-word boundary.

BURST SEQUENCE

The burst sequence specifies the address order of the

data in synchronous burst mode. It can be programmed

as either linear or interleaved burst order. Continuous

burst length only supports linear burst order. See Table

10 for more details.

Table 10

Sequence and Burst Length

STARTING

NO

4-WORD

BURST LENGTH

8-WORD

BURST LENGTH

CONTINUOUS

BURST

ADDRESS

WRAP WRAP

.

(DEC)

0

RCR3

LINEAR

INTERLEAVED

0-1-2-3

LINEAR

INTERLEAVED

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

...

LINEAR

0-1-2-3-4-5-6-…

1-2-3-4-5-6-7-…

2-3-4-5-6-7-8-…

3-4-5-6-7-8-9-…

4-5-6-7-8-9-10-…

5-6-7-8-9-10-11-…

6-7-8-9-10-11-12-…

6-7-8-9-10-11-12-13-…

...

0

...

0

...

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

...

1

1-0-3-2

2

3

4

5

6

7

...

14

15

...

0

1

2

3

4

2-3-0-1

3-2-1-0

...

14-15-16-17-18-19-20-..

15-16-17-18-19-20-21-..

...

1

...

1

...

0-1-2-3

1-2-3-4

2-3-4-5

3-4-5-6

NA

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-8

2-3-4-5-6-7-8-9

3-4-5-6-7-8-9-10

4-5-6-7-8-9-10-11

5-6-7-8-9-10-11-12

6-7-8-9-10-11-12-13

7-8-9-10-11-12-13-14

...

NA

...

0-1-2-3-4-5-6-…

1-2-3-4-5-6-7-…

2-3-4-5-6-7-8-…

3-4-5-6-7-8-9-…

4-5-6-7-8-9-10-…

5-6-7-8-9-10-11…

6-7-8-9-10-11-12…

7-8-9-10-11-12-13…

...

5

6

7

...

14

15

…

...

14-15-16-17-18-19-20-…

15-16-17-18-19-20-21-…

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

23

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

CLOCK CONFIGURATION

The clock configuration configures the starting burst

cycle, outputdata, andWAIT#signaltobeassertedonthe

rising or falling edge of the clock.

is the maximum delay, equal to the latency counter

setting.

The delay happens only once during a continuous

burst access. If the burst never crosses an eight-word

boundary, the WAIT# is not asserted. The WAIT# informs

the system if this output delay occurs.

BURST WRAP

The burst wrap option, RCR3, signals if a four- or an

eight-word linear burst access wraps within the burst

length or whether it crosses the eight-word boundary. In

wrap mode (RCR3 = 0) the four- or eight-word access will

wrap within the four or eight words, respectively. In no-

wrap mode (RCR3 = 1), the device operates similarly to a

continuous burst. For example, in a four-word burst, no-

wrap mode, the possible linear burst sequences that do

not assert WAIT# are:

WAIT# SIGNAL IN BURST MODE

In the continuous burst mode or in the four- or eight-

word burst mode with no wrap (RCR3 = 1), the output

WAIT# informs the system when data is valid. When

WAIT# is asserted during delay (RCR8 = 0), WAIT# = 1

indicates valid data, and WAIT# = 0 indicates invalid

data. If RCR8 = 0, WAIT# is asserted on the same cycle on

whichthedelayoccurs. IfRCR8=1, WAIT#isassertedone

cycle before the delay occurs.

0-1-2-3

1-2-3-4

2-3-4-5

3-4-5-6

4-5-6-7

8-9-10-11

9-10-11-12

10-11-12-13

11-12-13-14

12-13-14-15

BLOCK LOCKING

The Flash devices provide a flexible locking scheme

that allows each block to be individually locked or un-

locked with no latency.

The devices offer two-level protection for the blocks.

The first level allows software-only control of block lock-

ing (for data, which needs to be changed frequently),

while the second level requires hardware interaction be-

forelockingcanbechanged(codewhichdoesnotrequire

frequent updates).

Control signals WP#, DQ1, and DQ0 define the state

of a block; for example, state [001] means WP# = 0, DQ1 =

0 and DQ0 = 1.

The worst-case delay is seen at the end of the eight-

word boundary: 7-8-9-10 and 15-16-17-18. In a four-

word burst, wrap mode, no WAIT# is asserted, and the

possible wrap sequences are:

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

4-5-6-7

5-6-7-4

6-7-4-5

7-4-5-6

8-9-10-11

9-10-11-8

etc.

When the continuous burst option is selected, the inter-

nal address wraps to 000000h if the device is read past the

last address.

Table 11 defines all of the possible locking states.

BURST LENGTH

NOTE: All blocks are software-locked upon comple-

The burst length defines the number of words the

deviceoutputs. Thedevicesupportsaburstlengthoffour

or eight words. The device can also be set in continuous

burst mode. In this mode the device linearly outputs data

until the internal burst counter reaches the end of the

burstable address space. RCR2 sets the burst length.

tion of a power-up sequence.

LOCKED STATE

After a power-up sequence completion, or after a

resetsequence,allblocksarelocked(states[001]or[101]).

This means full protection from alteration. Any PRO-

GRAM or ERASE operations attempted on a locked block

will return an error on bit SR1 of the status register. The

status of a locked block can be changed to unlocked or

lock down using the appropriate software commands.

Writing the lock command sequence, 60h followed by

01h, can lock an unlocked block.

CONTINUOUS BURST LENGTH

During continuous burst mode operation, the Flash

memory may have an output delay when the burst se-

quence crosses the first eight-word boundary. Also, in

four- or eight-word bursts with the burst wrap set to no

wrap (RCR3 = 1), the Flash memory may have an output

delay when the burst sequence crosses the first eight-

word boundary. The starting address dictates whether or

not a delay occurs. If the starting address is aligned with

an eight-word boundary, the delay is not seen. For a four-

word burst, if the starting address is aligned with a four-

word boundary, a delay is not seen. If the starting address

is at the end of an eight-word boundary, the output delay

UNLOCKED STATE

Unlocked blocks (states [000], [100], [110]) can be

programmed or erased. All unlocked blocks return to the

locked state when the device is reset or powered down.

An unlocked block can be locked or locked down using

the appropriate software command sequence, 60h fol-

lowed by D0h (see Table 4).

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

24

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

LOCKED DOWN STATE

Blocks that are locked down (state [011]) are pro-

tected from PROGRAM and ERASE operations, but their

protectionstatuscannotbechangedusingsoftwarecom-

mands alone. A locked or unlocked block can be locked

down by writing the lock down command sequence, 60h

followed by 2Fh. Locked down blocks revert to the locked

state when the device is reset or powered down.

UNLOCK command. It is also automatically set when

entering lock down. DQ1 indicates lock down status and

is set by the LOCK DOWN command. It can only be

cleared by reset or power-down, not by software. Table

11 shows the locking state transition scheme. The READ

ARRAY command, FFh, must be issued to the bank con-

taining address 00h prior to issuing other commands.

The LOCK DOWN function is dependent on the WP#

input. When WP# = 0, blocks in lock down [011] are

protected from program, erase, and lock status changes.

When WP# = 1, the lock down function is disabled ([111]),

and locked down blocks can be individually unlocked by

a software command to the [110] state, where they can be

erased and programmed. These blocks can then be

relocked [111] and unlocked [110] as desired while WP#

remains ꢁIGꢁ. When WP# goes LOW, blocks that were

previously locked down return to the locked down state

[011] regardless of any changes made while WP# was

ꢁIGꢁ. Device reset or power-down resets all locks, in-

cluding those in lock down, to locked state (see Table 12).

LOCKING OPERATIONS DURING ERASE SUSPEND

Changes to block lock status can be performed during

an ERASE SUSPEND by using the standard locking com-

mand sequences to unlock, lock, or lock down. This is

useful in the case when another block needs to be up-

dated while an ERASE operation is in progress.

To change block locking during an ERASE operation,

first write the ERASE SUSPEND command (B0h), then

check the status register until it indicates that the ERASE

operation has been suspended. Next, write the desired

lock command sequence to block lock, and the lock sta-

tus will be changed. After completing any desired LOCK,

READ, or PROGRAM operations, resume the ERASE op-

eration with the ERASE RESUME command (D0h).

If a block is locked or locked down during an

ERASE SUSPEND operation on the same block, the lock-

ing status bits will be changed immediately. Then, when

the ERASE is resumed, the ERASE operation will com-

plete.

READING A BLOCK’S LOCK STATUS

The lock status of every block can be read in the read

deviceidentificationmode. Toenter this mode, write 90h

to the bank containing address 00h. Subsequent READs

at block address +00002 will output the lock status of that

block. The lowest two outputs, DQ0 and DQ1, represent

the lock status. DQ0 indicates the block lock/unlock sta-

tus and is set by the LOCK command and cleared by the

A locking operation cannot be performed during a

PROGRAM SUSPEND.

Table 11

Block Locking State Transition

ERASE/PROG

ALLOWED

LOCK

DOWN

WP#

DQ1

DQ0

NAME

Unlocked

LOCK

UNLOCK

No Change

To [000]

0

1

0

1

0

1

0

1

0

1

0

Yes

No

To [001]

To [011]

No Change

To [111]

Locked (Default)

Lock Down

Unlocked

No Change

To [101]

No

No Change

To [100]

Yes

No

Locked

No Change

To [111]

Lock Down

Disabled

Yes

No Change

1

Lock Down

Disabled

No

No Change

To [110]

No Change

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

25

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

CHIP PROTECTION REGISTER

unprogrammed. After DQ1 of the PR lock register is

programmed, nofurtherprogrammingisallowedonPR2.

The programming sequence is similar to array program-

ming except that the PROTECTION REGISTER PRO-

GRAMMING SETUP command (C0h) is issued instead of

an ARRAY PROGRAMMING SETUP command (40h), fol-

lowed by the data to be programmed at addresses 85h–

88h.

A 128-bit chip protection register can be used to fulfill

the security considerations in the system (preventing the

device substitution).

The 128-bit security area is divided into two 64-bit

segments. The first 64 bits are programmed at the manu-

facturing site with a unique 64-bit unchangeable num-

ber. The other segment is left blank for customers to

program as desired. (See Figure 12).

To program the PR lock bit for PR2 (to prevent further

programming), use the above sequence on address 80h,

with data of FFFDh (DQ1 = 0).

READING THE CHIP PROTECTION REGISTER

The chip protection register is read in the device iden-

tification mode. To enter this mode, load the 90h com-

mand to the bank containing address 00h. Once in this

mode, READ cycles from addresses shown in Table 12

retrieve the specified information. To return to the read

array mode, write the READ ARRAY command (FFh). The

READ ARRAY command, FFh, must be issued to the bank

containingaddress00hpriortoissuingothercommands.

Figure 12

Protection Register Memory Map

88h

4 Words

User-Programmed

PROGRAMMING THE CHIP PROTECTION REGISTER

The first 64 bits (PR1) of the protection register (ad-

dresses 81h–84h) are programmed with a unique identi-

fier at the factory. DQ0 of the PR lock register (address

80h) is programmed to a “0” state, locking the first 64 bits

and preventing any further programming.

The second 64 bits (PR2) is a user area (addresses 85h–

88h), where the user can program any information into

this area as long as DQ1 of the PR lock register remains

85h

84h

4 Words

Factory-Programmed

81h

80h

PR Lock

0

Table 12

Chip Configuration Addressing

1

ITEM

ADDRESS²

00000h

DATA

Manufacturer Code (x16)

002Ch

Device Code

00001h

Top boot configuration

Bottom boot configuration

44B4h

44B5h

·

Block Lock Configuration

XX002h

Lock

Block is unlocked

Block is locked

Block is locked down

DQ0 = 0

DQ0 = 1

DQ1 = 1

·

Read Configuration Register

Chip Protection Register Lock

Chip Protection Register 1

Chip Protection Register 2

00005h

80h

RCR

PR Lock

81h–84h

85h–88h

Factory Data

User Data

NOTE: 1. Other locations within the configuration address space are reserved by

Micron for future use.

2. “XX” specifies the block address of lock configuration.

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

26

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

2. If one bank is in program or erase mode and the

application starts burst access in that bank, then the

status register data is returned. The internal address

counter is incremented at every clock pulse.

ASYNCHRONOUS READ MODE

The asynchronous read mode is the default read con-

figuration state. To use the device in an asynchronous-

only application, ADV# and CLK must be tied to V^SSand

WAIT# should be floated.

3. If burst is started in one bank and the bank boundary

is crossed, and the other bank is in program or erase

mode, then the status register data is returned as the

first location of the bank. If the application keeps

clocking, the internal address counter gets

incremented at every clock cycle. If bank end is

crossed, then data from the other bank is returned as

shown in Figure 13.

Toggling the address lines from A0 to A20, the access

is purely random (^tAA).

The ADV# signal needs to be toggled to latch the

address, the CE# signal needs to go LOW, and the OE#

signal needs to go LOW. In this case the data is placed on

the data bus and the processor is ready to receive the

data.

SYNCHRONOUS BURST READ MODE

The burst read mode is used to achieve a faster data

rate than is possible with asynchronous read mode. The

rising edge of the clock CLK is used to latch the address

with CE# and ADV# LOW (see timing diagram: Single

Synchronous READ Operation). The burst read configu-

ration is set in the read configuration register, where

frequency, data output, WAIT# signal, burst sequence,

clock, and burst length are configured setting the related

bits.

Figure 13

Bank Boundary Wrapping

(Bottom Boot Example)

Bank a start address

0 00000h

All blocks in both banks are burstable.

The BURST READ works across the bank boundary in

the following way:

Bank a

Bank a end address

Bank b start address

0 7FFFFh

0 80000h

bank boundary

Bank b

1. In READ operation there is no bank boundary as far as

burst access is concerned. If, for example, burst starts

in bank a, the application can keep clocking until

bank boundary is reached and then read from bank b.

If the application keeps clocking beyond bank b last

location, then the internal counter restarts from bank

a first address. (See Figure 13.)

Bank b end address

1 FFFFFh

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

27

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

ASYNCHRONOUS PAGE READ MODE

After power-up or reset, the device operates in page

mode over the whole memory array. The page size can be

customized at the factory to four or eight words as re-

quired; but if no specification is made, the normal size is

eight words. The initial portion of the page mode cycle is

the same as the asynchronous access cycle. ꢁolding CE#

LOW and toggling addresses A0–A2 allows random ac-

cess of other words in the page.

STANDBY MODE

ICC supplycurrentisreducedbyapplyingalogicꢁIGꢁ

level on CE# and RST# to enter the standby mode. In the

standby mode, the outputs are ꢁigh-Z. Applying a CMOS

logic ꢁIGꢁ level on CE# and RST# reduces the current to

I^CC4 (MAX). If the device is deselected during an ERASE

operation or during programming, the device continues

to draw current until the operation is complete.

AUTOMATIC POWER SAVE MODE (APS)

Substantial power savings are realized during periods

when the array is not being read and the device is in the

active mode. During this time the device switches to the

automatic power save mode. When the device switches

to this mode, I^CCis reduced to a level comparable to ICC4.

Further power savings can be realized by applying a logic

ꢁIGꢁ level to CE# to place the device in standby mode.

The low level of power is maintained until another opera-

tion is initiated. In this mode, the I/Os retain the data

from the last memory address read until a new address is

read. This mode is entered automatically if no address or

control signals toggle.

VPP/VCC PROGRAM AND ERASE

VOLTAGES

The Flash devices provide in-system programming

and erase with VPP in the 0.9V–2.2V range (VPP1). The 12V

VPP (VPP2) mode programming is offered for compatibil-

ity with existing programming equipment.

The device can withstand 100,000 WRITE/ERASE op-

erationswhenVPP =VPP1 or100WRITE/ERASEoperations

and 10 cumulative hours when V^PP= VPP2.

In addition to the flexible block locking, the VPP

programmingvoltagecanbeheldLOWforabsolutehard-

ware write protection of all blocks in the Flash device.

When V^PPis below VPPLK, any PROGRAM or ERASE opera-

tion will result in an error, prompting the corresponding

status register bit (SR3) to be set.

DuringWRITEandERASEoperations,theWSMmoni-

tors the V^PPvoltage level. WRITE/ERASE operations are

allowed only when VPP is within the ranges specified in

Table 13.

When V^CCis below VLKO or VPP is below VPPLK, any

WRITE/ERASE operation will be prevented.

DEVICE RESET

To correctly reset the Flash devices, the RST# signal

must be asserted (RST# = VIL) for a minimum of ^tRP. After

reset, the devices can be accessed for a READ operation

with a delayed access time of ^tRWꢁ from the rising edge

ofRST#. ThecircuitryusedforgeneratingtheRST#signal

needs to be common with the rest of the system reset to

ensure that correct system initialization occurs. Please

refer to the timing diagram for further details.

POWER-UP SEQUENCE

Table 13

VPP Range (V)

The following power-up sequence is recommended

to properly initialize internal chip operations:

• Atpower-up, RST#shouldbekeptatVIL for2µsafter

VCC reaches VCC (MIN).

MIN

0.9

MAX

2.25

12.6

• VCCQ should not come up before VCC.

In System (VPP1)

In Factory (VPP2)

• VPP should be kept atVIL to maximize data integrity.

When the power-up sequence is completed, RST#

should be brought to VIꢁ. To ensure a proper power-up,

the rise time of RST (10ꢀ–90ꢀ) should be < 10µs.

11.4

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

28

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

*Stresses greater than those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the de-

vice. This is a stress rating only and functional operation

of the device at these or any other conditions above those

indicated in the operational sections of this specification

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

**Maximum DC voltage on VPP may overshoot to +13.5V

for periods < 20ns.

ABSOLUTE MAXIMUM RATINGS*

Voltage to Any Ball Except VCC and VPP

with Respect to VSS ........................ -0.5V to +2.45V

V^PPVoltage (for BLOCK ERASE and PROGRAM

with Respect to V^SS) .................... -0.5V to +13.5V**

V^CCand VCCQ Supply Voltage

with Respect to V^SS........................ -0.3V to +2.45V

Output Short Circuit Current ................................ 100mA

Operating Temperature Range ................ -40^oC to +85^oC

Storage Temperature Range .................. -55^oC to +125^oC

Soldering Cycle ............................................. 260^oC for 10s

RECOMMENDED OPERATING CONDITIONS

PARAMETER

SYMBOL

MIN

-40

1.80

1.70

1.80

1.70

0.9

MAX

+85

UNITS

^oC

NOTES

Operating temperature

^tA

VCC supply voltage (MT28F322D20)

VCC supply voltage (MT28F322D18)

I/O supply voltage (MT28F322D20)

I/O supply voltage (MT28F322D18)

VPP voltage

VCC

2.20

V

VCC

1.90

V

VCCQ

VPP1

VPP2

2.25

V

1.90

2.25

V

VPP in-factory programming voltage

Block erase cycling (VPP = VPP1)

Block erase cycling (VPP = VPP2)

11.4

–

12.6

V

100,000

100

Cycles

–

1

NOTE: 1. VPP = VPP2 is a maximum of 10 cumulative hours.

Figure 14

AC Input/Output Reference Waveform

VCC

V

CC/2

VCCQ/2

Input

Test Points

Output

VSS

AC test inputs are driven at VCC for a logic 1 and VSS for a logic 0. Input timing begins at VCC/2, and output timing ends

at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns.

Figure 15

Output Load Circuit

VCC

14.5K

I/O

30pF

VSS

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

29

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

CAPACITANCE

(T_A= +25ºC; f = 1 MHz)

PARAMETER/CONDITION

Input Capacitance

SYMBOL

TYP

7

MAX

12

UNITS

pF

C

Output Capacitance

COUT

9

12

pF

1

DC CHARACTERISTICS

PARAMETER

SYMBOL

VIL

MIN

MAX

UNITS NOTES

Input Low Voltage

Input High Voltage

0

0.4

V

2

VIH

VCCQ - 0.4V

–

VCCQ

0.10

Output Low Voltage

IOL = 100µA

VOL

Output High Voltage

IOH = -100µA

VOH

VCCQ - 0.1V

–

V

VPP Lockout Voltage

VPPLK

VPP1

VPP2

VLKO

IL

–

0.9

11.4

1

0.4

2.2

12.6

–

V

VPP During PROGRAM/ERASE Operations

V

VCC Program/Erase Lock Voltage

Input Leakage Current

V

–

1

µA

mA

µA

mA

µA

mA

Output Leakage Current

IOZ

–

1

VCC Asynchronous Random Read, 70ns cycle

VCC Page Mode Read Current, 70ns/30ns cycle

VCC Burst Mode Read Current , 18.5ns cycle

VCC Standby Current

ICC1

ICC2

ICC3

ICC4

ICC5

ICC6

ICC7

ICC8

ICC9

IPP1

–

15

5

3, 4

4

–

10

50

55

65

50

80

–

VCC Program Current

–

VCC Erase Current

–

VCC Erase Suspend Current

–

5

VCC Program Suspend Current

Read-While-Write Current

–

VPP Current

(Read, Standby, Erase Suspend, Program Suspend)

V^PP≤ VCC

VPP ≥ VCC

–

1

200

µA

NOTE: 1. All currents are in RMS unless otherwise noted.

2. VIL may decrease to -0.4V and VIH may increase to VCCQ + 0.3V for durations not to exceed 20ns.

3. APS mode reduces ICC to approximately ICC4 levels.

4. Test conditions: Vcc = VCC (MAX), CE# = VIL, OE# = VIH. All other inputs = VIH or VIL.

5. ICC7 and ICC8 values are valid when the device is deselected. Any READ operation performed while in suspend mode

will have an additional current draw of suspend current (ICC7 or ICC8).

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

30

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

1

ASYNCHRONOUS READ CYCLE TIMING REQUIREMENTS

MT28F322D20 (V^CC= 1.80V–2.25V) and MT28F322D18 (VCC = 1.70V–1.90V)

-70

-80

PARAMETER

SYMBOL

MIN

10

MAX

MIN

10

MAX

UNITS

ns

t

Address setup to ADV# HIGH

CE# LOW to ADV# HIGH

READ cycle time

Address to output delay

CE# LOW to output delay

ADV# LOW to output delay

ADV# pulse width LOW

ADV# pulse width HIGH

Address hold from ADV# HIGH

Page address access

OE# LOW to output delay

RST# HIGH to output delay

CE# or OE# HIGH to output High-Z

Output hold from address, CE# or OE# change

AVS

t

CVS

RC

AA

t

70

80

t

ACE

t

AADV

t

VP

VPH

AVH

APA

10

3

10

3

t

30

25

200

15

30

200

25

t

AOE

t

RWH

t

OD

OH

t

0

NOTE: 1. See Figures 15 and 16 for timing requirements and load configuration.

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

31

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

1

BURST READ CYCLE TIMING REQUIREMENTS

(MT28F322D20)

-705

-804

PARAMETER

CLK period

SYMBOL

MIN

18.5

5

MAX

MIN

25

7.5

MAX

UNITS

ns

t

CLK

t

CLK HIGH (LOW) time

CLK fall (rise) time

Address valid setup to CLK

ADV# LOW setup to CLK

CE# LOW setup to CLK

CLK to output delay

Output hold from CLK

Address hold from CLK

CLK to WAIT# delay

KP

t

KHKL

AKS

3

5

t

7

9

7

13

t

VKS

CKS

t

ACLK

KOH

AKH

KHTL

15

20

t

3.5

10

5

10

t

ns

t

CE# HIGH between subsequent synchronous READs

CBPH

20

1

BURST READ CYCLE TIMING REQUIREMENTS

(MT28F322D18)

-705

-804

PARAMETER

CLK period

SYMBOL

MIN

19.2

5

MAX

MIN

25

7.5

MAX

UNITS

ns

t

CLK

t

CLK HIGH (LOW) time

CLK fall (rise) time

Address valid setup to CLK

ADV# LOW setup to CLK

CE# LOW setup to CLK

CLK to output delay

Output hold from CLK

Address hold from CLK

CLK to WAIT# delay

KP

t

KHKL

AKS

3

5

t

7

9

7

13

t

VKS

CKS

t

ACLK

17

15

20

t

KOH

AKH

KHTL

3.5

10

5

10

t

ns

t

CE# HIGH between subsequent synchronous READs

CBPH

20

NOTE: 1. See Figures 15 and 16 for timing requirements and load configuration.

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

32

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

WRITE CYCLE TIMING REQUIREMENTS

-70/-80

PARAMETER

SYMBOL

MIN

150

0

50

10

50

10

0

1.5

3

30

100

0

200

50

0

MAX

UNITS

ns

t

HIGH recovery to WE# going LOW

CE# setup to WE# going LOW

Write pulse width

RS

CS

t

WP

VP

DS

AS

t

ADV# pulse width

t

Data setup to WE# going HIGH

Address setup to WE# going HIGH

ADV# setup to WE# going HIGH

Address setup to ADV# going HIGH

CE# hold from WE# HIGH

Data hold from WE# HIGH

Address hold from WE# HIGH

Address hold from ADV# going HIGH

Write pulse width HIGH

t

VS

t

AVS

CH

DH

AH

t

AVH

t

WPH

t

RST# pulse width

RP

t

WP# setup to WE# going HIGH

VPP setup to WE# going HIGH

Write recovery before READ

WP# hold from valid SRD

VPP hold from valid SRD

RHS

VPS

t

WOS

RHH

t

VPPH

0

t

WE# HIGH to data valid

WB

AA + 50

ERASE AND PROGRAM TIMING REQUIREMENTS

-70/-80

PARAMETER

TYP

40

320

8

0.3

0.5

5

MAX

800

6,400

UNITS

4KW block program time

32KW block program time

Word program time

4KW block erase time

32KW block erase time

Program suspend latency

Erase suspend latency

Chip programming time (APA)

ms

µs

s

10,000

6

10

20

s

µs

s

5

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

33

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

SINGLE ASYNCHRONOUS READ OPERATION

V_IH

V_IL

A0–A20

VALID ADDRESS

t

AA

RC

t

OD

V_IH

V_IL

ADV#

CE#

V_IH

V_IL

t

ACE

V_IH

V_IL

OE#

t

OH

V_IH

V_IL

WE#

V_OH

V_OL

WAIT#

t

AOE

V_OH

V_OL

High-Z

VALID OUTPUT

DQ0–DQ15

RST#

t

RWH

V_IH

V_IL

UNDEFINED

READ TIMING PARAMETERS

MT28F322D20 (VCC = 1.80V–2.25V)

MT28F322D18 (VCC = 1.70V–1.90V)

-70

-80

-70

-80

SYMBOL

MIN

MAX

70

MIN

MAX

80

UNITS

ns

SYMBOL

MIN

MAX

200

15

MIN

MAX

200

25

UNITS

ns

t

AA

RWH

t

ACE

70

80

ns

OD

ns

t

AOE

25

30

ns

OH

0

ns

t

RC

70

80

ns

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

34

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

ASYNCHRONOUS PAGE MODE READ OPERATION

V_IH

V_IL

A3–A20

A0–A2

VALID ADDRESS

t

RC

V_IH

V_IL

VALID

ADDRESS

VALID

ADDRESS

VALID

ADDRESS

VALID ADDRESS

AA

V_IH

V_IL

ADV#

CE#

t

OD

V_IH

V_IL

t

ACE

V_IH

V_IL

OE#

WE#

V_IH

V_IL

V_OH

V_OL

WAIT#

t

AOE

APA

OH

V_OH

V_OL

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

High-Z

DQ0–DQ15

RST#

t

RWH

V_IH

V_IL

UNDEFINED

READ TIMING PARAMETERS

MT28F322D20 (VCC = 1.80V–2.25V)

MT28F322D18 (VCC = 1.70V–1.90V)

-70

-80

-70

-80

SYMBOL

MIN

MAX

70

MIN

MAX

80

UNITS

ns

SYMBOL

MIN

MAX

70

MIN

MAX

80

UNITS

ns

t

AA

RC

t

ACE

70

80

ns

RWH

OD

OH

200

15

200

25

ns

t

APA

30

ns

t

AOE

25

30

ns

0

ns

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

35

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

SINGLE SYNCHRONOUS READ OPERATION

V_IH

V_IL

CLK

t

AKS

AKH

V_IH

V_IL

A0–A20

VALID

ADDRESS

t

AA

t

AVH

t

V_IH

V_IL

VPH

ADV#

t

AADV

t

VP

t

VKS

OD

V_IH

V_IL

CE#

t

ACE

t

CVS

t

CKS

V_IH

V_IL

OE#

V_IH

V_IL

WE#

V_OH

V_OL

WAIT#

t

KOH

OH

AOE

V_OH

V_{O L}

VALID

OUTPUT

DQ0–DQ15

High-Z

t

ACLK

UNDEFINED

READ TIMING PARAMETERS

MT28F322D20 (VCC = 1.80V–2.25V)

READ TIMING PARAMETERS

MT28F322D18 (VCC = 1.70V–1.90V)

-705

-804

-705

-804

SYMBOL

MIN

MAX

MIN

7

MAX

UNITS

ns

SYMBOL

MIN

MAX

MIN

7

MAX

UNITS

ns

t

AKS

7

9

AKS

7

9

t

VKS

7

ns

VKS

7

ns

t

CKS

13

ns

CKS

13

ns

t

ACLK

15

20

ns

ACLK

17

20

ns

t

KOH

3

5

ns

KOH

3

5

ns

t

AKH

10

ns

AKH

10

ns

t

CVS

ns

CVS

ns

t

AA

70

80

ns

AA

70

80

ns

t

ACE

ns

ACE

ns

t

AADV

ns

AADV

ns

t

VP

10

3

10

3

ns

VP

10

3

10

3

ns

t

VPH

ns

VPH

ns

t

AVH

ns

AVH

ns

t

AOE

25

15

30

25

ns

AOE

25

15

30

25

ns

t

OD

ns

OD

ns

t

OH

0

ns

OH

0

ns

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

36

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

4-WORD SYNCHRONOUS BURST OPERATION

V_IH

V_IL

CLK

t

AKS

AKH

V_IH

V_IL

A0–A20

VALID

ADDRESS

t

AA

t

AVH

t

V_IH

V_IL

VPH

ADV#

t

AADV

t

VP

t

VKS

OD

V_IH

V_IL

CE#

t

ACE

t

CVS

t

CKS

V_IH

V_IL

OE#

V_IH

V_IL

WE#

V_OH

V_OL

V_OH

WAIT#

t

KOH

OH

AOE

t

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

DQ0–DQ15

High-Z

V_{O L}

ACLK

UNDEFINED

READ TIMING PARAMETERS

MT28F322D20 (VCC = 1.80V–2.25V)

READ TIMING PARAMETERS

MT28F322D18 (VCC = 1.70V–1.90V)

-705

-804

-705

-804

SYMBOL

MIN

MAX

MIN

7

MAX

UNITS

ns

SYMBOL

MIN

MAX

MIN

7

MAX

UNITS

ns

t

AKS

7

9

AKS

7

9

t

VKS

7

ns

VKS

7

ns

t

CKS

13

ns

CKS

13

ns

t

ACLK

15

20

ns

ACLK

17

20

ns

t

KOH

3

5

ns

KOH

3

5

ns

t

AKH

10

ns

AKH

10

ns

t

CVS

ns

CVS

ns

t

AA

70

80

ns

AA

70

80

ns

t

ACE

ns

ACE

ns

t

AADV

ns

AADV

ns

t

VP

10

3

10

3

ns

VP

10

3

10

3

ns

t

VPH

ns

VPH

ns

t

AVH

ns

AVH

ns

t

AOE

25

15

30

25

ns

AOE

25

15

30

25

ns

t

OD

ns

OD

ns

t

OH

0

ns

OH

0

ns

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

37

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

CONTINUOUS BURST READ

SHOWING AN OUTPUT DELAY WITH RCR8 = 0(1)

V_IH

V_IL

CLK

t

KP

t

CLK

t

KHKL

V_IH

V_IL

A0–A20

ADV#

V_IH

V_IL

V_IH

V_IL

CE#

V_IH

V_IL

OE#

V_IH

V_IL

WE#

t

KHTL

V_OH

V_OL

WAIT#

DQ0–DQ15

V_OH

V_{O L}

VALID

OUTPUT

VALID

OUTPUT

INVALID

OUTPUT

VALID

OUTPUT

VALID

OUTPUT

t

KOH

ACLK

UNDEFINED

READ TIMING PARAMETERS

MT28F322D20 (VCC = 1.80V–2.25V)

READ TIMING PARAMETERS

MT28F322D18 (VCC = 1.70V–1.90V)

-705

-804

-705

-804

SYMBOL

MIN

18.5

5

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

19.2

5

MAX

MIN

25

MAX

UNITS

ns

t

CLK

25

CLK

t

KP

7.5

ns

KP

7.5

ns

t

KHKL

3

5

ns

KHKL

3

5

ns

t

ACLK

15

20

ns

ACLK

17

20

ns

t

KOH

3.5

5

ns

KOH

3.5

5

ns

t

KHTL

15

20

ns

KHTL

15

20

ns

t

NOTE: 1. CLK = 19.2ns (MIN) for the MT28F322D18 device.

t

2. ACLK = 17ns (MAX) for the MT28F322D18 device.

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

38

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

TWO-CYCLE PROGRAMMING/ERASE OPERATION

V_IH

V_IL

A0–A20

VALID ADDRESS

t

VALID ADDRESS

t

AVS

AVH

AS

AH

t

VPH

V_IH

V_IL

ADV#

CE#

t

VP

VS

V_IH

V_IL

t

WOS

CS

t

CH

V_IH

V_IL

t

WPH

OE#

t

WP

V_IH

V_IL

V_IH

V_IL

WE#

t

CMD

WB

CMD/

DATA

CMD/

DATA

High-Z

STATUS

DQ0–DQ15

t

RS

t

DS

t

CH

V_IH

t

RST#

WP#

RHH

RHS

V_IL

V_IH

V_IL

t

VPPH

VPS

V_IPPH

V_IPPLK

V_IL

VPP

UNDEFINED

WRITE TIMING PARAMETERS

-70/-80

SYMBOL

MIN

150

0

MAX

UNITS

ns

SYMBOL

MIN

1.5

3

MAX

UNITS

ns

t

RS

AH

t

CS

ns

AVH

WPH

VPH

RHS

VPS

ns

t

WP

70

10

70

10

0

ns

30

10

0

ns

t

VP

ns

t

DS

ns

t

AS

ns

200

50

0

ns

t

VS

ns

WOS

RHH

VPPH

WB

ns

t

AVS

ns

t

CH

ns

0

ns

t

DH

0

ns

AA + 50

ns

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

39

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

RESET OPERATION

V_IH

V_IL

CE#

V_IH

V_IL

RST#

t

RP

V_IH

V_IL

OE#

V_OH

V_OL

DQ0–DQ15

t

RWH

READ AND WRITE TIMING PARAMETERS

-70/-80

1.80V–2.25V

1.70V–1.90V

SYMBOL

MIN

MAX

200

MIN

MAX

200

UNITS

ns

t

RWH

t

RP

100

ns

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

40

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

Table 15

CFI

OFFSET

00

DATA

2Ch

DESCRIPTION

Manufacturer code

01

B4h

Top boot block device code

B5h

Bottom boot block device code

Reserved

02 – 0F

reserved

10, 11 0051, 0052 “QR”

12 0059 “Y”

13, 14 0003, 0000 Primary OEM command set

15, 16 0039, 0000 Address for primary extended table

17, 18 0000, 0000 Alternate OEM command set

19, 1A 0000, 0000 Address for OEM extended table

1B

1C

1D

1E

1F

0017

0022

00B4

00C6

0003

0000

VCC MIN for Erase/Write; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD

VCC MAX for Erase/Write; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD

VPP MIN for Erase/Write; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD

VPP MAX for Erase/Write; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD

Typical timeout for single byte/word program, 2ⁿµs, 0000 = not supported

20

Typical timeout for maximum size multiple byte/word program, 2ⁿµs, 0000 = not

supported

21

22

23

24

0009

0000

000C

0000

Typical timeout for individual block erase, 2ⁿms, 0000 = not supported

Typical timeout for full chip erase, 2ⁿms, 0000 = not supported

Maximum timeout for single byte/word program, 2ⁿµs, 0000 = not supported

Maximum timeout for maximum size multiple byte/word program, 2ⁿµs, 0000 = not

supported

25

26

27

28

29

0003

0000

0016

0001

0000

Maximum timeout for individual block erase, 2ⁿms, 0000 = not supported

Maximum timeout for full chip erase, 2ⁿms, 0000 = not supported

Device size, 2ⁿbytes

Bus Interface x16 = 1

Flash device interface description 0000 = async

2A, 2B 0000, 0000 Maximum number of bytes in multi-byte program or page, 2ⁿ

2C 0003 Number of erase block regions within device (4K words and 32K words)

2D, 2E 002F, 0000 Top boot block device erase block region information 1, 8 blocks …

0007, 0000 Bottom boot block device erase block region information 1, 8 blocks …

2F, 30 0000, 0001 Top boot block device …..of 8KB

0020, 0000 Bottom boot block device …..of 8KB

31, 32 000E, 0000 Top boot block 15 blocks of ….

000E, 0000 Bottom boot block 15 blocks of ….

33, 34 0000, 0001 ……64KB

35, 36 0007, 0000 Top boot block device …..48 blocks of

002F, 0000 Bottom boot block device …..48 blocks of

(continued on next page)

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

41

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

Table 15

CFI (continued)

OFFSET

DATA

DESCRIPTION

37, 38 0020, 0000 Top boot block device ……64KB

0000, 0001 Bottom boot block device ……64KB

39, 3A 0050, 0052 “PR”

3B

3C

3D

0049

0030

0031

“I”

Major version number, ASCII

Minor version number, ASCII

3E

3F

40

41

00E6

0003

0000

Optional Feature and Command Support

Bit 0 Chip erase supported no = 0

Bit 1 Suspend erase supported = yes = 1

Bit 2 Suspend program supported = yes = 1

Bit 3 Chip lock/unlock supported = no = 0

Bit 4 Queued erase supported = no = 0

Bit 5 Instant individual block locking supported = yes = 1

Bit 6 Protection bits supported = yes = 1

Bit 7 Page mode read supported = yes = 1

Bit 8 Synchronous read supported = no = 0

Bit 9 Simultaneous operation supported = yes = 1

42

0001

Program supported after erase suspend = yes

43, 44 0003, 0000 Bit 0 block lock status active = yes; Bit 1 block lock down active = yes

45

46

47

0018

00C0

0001

VCC supply optimum, 00 = not supported, Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD

VPP supply optimum, 00 = not supported, Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD

Number of protection register fields in JEDEC ID space

48, 49 0080, 0000 Lock bytes LOW address, lock bytes HIGH address

4A, 4B 0003, 0003 2ⁿfactory programmed bytes, 2ⁿuser programmable bytes

4C

0003

Background Operation

0000 = Not used

0001 = 4% block split

0002 = 12% block split

0003 = 25% block split

0004 = 50% block split

4D

0072

Burst Mode Type

0000 = No burst mode

00x1 = 4 words MAX

00x2 = 8 words MAX

00x3 = 16 words MAX

001x = Linear burst, and/or

002x = Interleaved burst, and/or

004x = Continuous burst

4E

4F

0002

0000

Page Mode Type

0000 = No page mode

0001 = 4-word page

0002 = 8-word page

0003 = 16-word page

0004 = 32-word page

Not used

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

42

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

58-BALL FBGA

0.80 0.075

SEATING PLANE

.10 C

C

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or

62% Sn, 36% Pb, 2% Ag

SOLDER BALL PAD: Ø .27mm

BALL A8

0.35 TYP

58X

Ø

7.00 0.10

5.25

0.75

TYP

SUBSTRATE: PLASTIC LAMINATE

SOLDER BALL DIAMETER

REFERS TO POST REFLOW

CONDITION. THE

PRE-REFLOW DIAMETER

IS Ø 0.33

BALL #1 ID

ENCAPSULATION MATERIAL: EPOXY NOVOLAC

BALL #1 ID

BALL A1

0.75

TYP

6.00 0.05

C

L

12.00 .10

4.50

2.25 0.05

1.50 (4X)

C

L

SUPPORT BALLS

(4X)

1.20 MAX

2.625 0.05 3.50 0.05

NOTE: 1. All dimensions in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

DATA SHEET DESIGNATION

No Mark:

This data sheet contains minimum and maximum limits specified over the complete power supply and

temperature range for production devices. Although considered final, these specifications are subject

to change, as further product development and data characterization sometimes occur.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc.

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

43

2 MEG x 16

ASYNC/PAGE/BURST FLASH MEMORY

REVISION HISTORY

Rev. 4 .................................................................................................................................................................................... 7/02

•

Removed PRELIMINARY DESIGNATION

Updated Status Register section

Updated command descriptions

Updated Read-While-Write/EraseConcurrency section

Updated timing diagrams

Changed interpage read access voltage from 1.70V to 1.80V

Changed intrapage read access voltage from 1.90V to 2.20V

Rev. 3, PRELIMINARY ........................................................................................................................................................ 3/02

• Added Note 4 to DC Characteristics table

Rev. 2, PRELIMINARY ........................................................................................................................................................ 1/02

• Added -70 and -80 speed grades for the MT28F322D18

• Removed -90 speed grade

• Updated DC Characteristics Table

• Updated CFI Table

• Updated ^tAꢁ and ^tRWꢁ specifications

• Changed data sheet from Advance to Preliminary

Original document, Rev. 1, ADVANCE ............................................................................................................................ 7/01

2 Meg x 16 Async/Page/Burst Flash Memory

MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02

Micron Technology, Inc., reserves the right to change products or specifications without notice.

44


型号：	MT28F322D20FH-805TET
厂家：	MICRON TECHNOLOGY
描述：	FLASH MEMORY FL灰内存
文件：	总44页 (文件大小：519K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT28F322D20FH-805TET [MICRON]

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