MT28F800B3WG-9T_技术文档

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

FLASH MEMORY

MT28F008B3

MT28F800B3

3V Only, Dual Supply (Smart 3)

FEATURES

• Eleven erase blocks:

40-Pin TSOP Type I 48-Pin TSOP Type I

16KB/8K-word boot block (protected)

Two 8KB/4K-word parameter blocks

Eight main memory blocks

• Smart 3 technology (B3):

3.3V ±0.3V V^CC

3.3V ±0.3V VPP application programming

5V ±10% VPP application/production programming¹

• Compatible with 0.3µm Smart 3 device

• Advanced 0.18µm CMOS floating-gate process

• Address access time: 90ns

• 100,000 ERASE cycles

• Industry-standard pinouts

44-Pin SOP

• Inputs and outputs are fully TTL-compatible

• Automated write and erase algorithm

• Two-cycle WRITE/ERASE sequence

• TSOP, SOP and FBGA packaging options

•

Byte- or word-wide READ and WRITE

(MT28F800B3):

1 Meg x 8/512K x 16

OPTIONS

• Timing

MARKING

90ns access

-9

GENERAL DESCRIPTION

• Configurations

1 Meg x 8

The MT28F008B3 (x8) and MT28F800B3 (x16/x8) are

low-voltage, nonvolatile, electrically block-erasable (flash),

programmable memory devices containing 8,388,608 bits

organized as 524,288 words (16 bits) or 1,048,576 bytes (8

bits). Writing and erasing the device is done with a VPP

voltage of either 3.3V or 5V, while all operations are

performed with a 3.3V VCC. Due to process technology

advances, 5V VPP is optimal for application and production

programming. These devices are fabricated with Micron’s

advanced 0.18µm CMOS floating-gate process.

MT28F008B3

MT28F800B3

512K x 16/1 Meg x 8

• Boot Block Starting Word Address

Top (7FFFFh)

T

B

Bottom (00000h)

• Operating Temperature Range

Commercial (0ºC to +70ºC)

Extended (-40ºC to +85ºC)

None

ET

• Packages

The MT28F008B3 and MT28F800B3 are organized

into eleven separately erasable blocks. To ensure that

critical firmware is protected from accidental erasure or

overwrite, the devices feature a hardware-protected

boot block. This block may be used to store code imple-

mented in low-level system recovery. The remaining

blocks vary in density and are written and erased with

no additional security measures.

40-pin TSOP Type I (MT28F008B3)

48-pin TSOP Type I (MT28F800B3)

44-pin SOP (MT28F800B3)

VG

WG

SG

NOTE:

1. This generation of devices does not support 12V VPP

production programming; however, 5V VPP application

production programming can be used with no loss of

performance.

Part Number Example:

Refer to Micron’s Web site (www.micron.com/flash)

for the latest data sheet.

MT28F800B3WG-9 BET

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

1

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

PIN ASSIGNMENT (Top View)

48-Pin TSOP Type I

44-Pin SOP

A15

A14

A13

A12

A11

A10

A9

A8

NC

WE#

RP#

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V

PP

1

44

RP#

WE#

A8

A18

A17

A7

2

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

V

SS

3

DQ15/(A - 1)

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

4

A9

A6

5

A10

A11

A12

A13

A14

A15

A16

BYTE#

A5

6

A4

7

A3

8

A2

9

V

CC

A1

10

11

12

13

14

15

16

17

18

19

20

21

22

VPP

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

WP#

NC

A18

A17

A7

A6

A5

A4

A3

A0

CE#

V

SS

VSS

OE#

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

DQ15/(A - 1)

DQ7

DQ14

DQ6

VSS

CE#

A0

A2

A1

DQ13

DQ5

DQ12

DQ4

ORDERNUMBERANDPARTMARKING

MT28F800B3WG-9B

V

CC

MT28F800B3WG-9T

MT28F800B3WG-9BET

MT28F800B3WG-9TET

ORDERNUMBERANDPARTMARKING

MT28F800B3SG-9B

MT28F800B3SG-9T

MT28F800B3SG-9BET

MT28F800B3SG-9TET

40-Pin TSOP Type I

A16

A15

A14

A13

A12

A11

A9

A8

WE#

RP#

1

2

3

4

5

6

7

8

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

A17

VSS

NC

A19

A10

DQ7

DQ6

DQ5

DQ4

9

10

11

12

13

14

15

16

17

18

19

20

VCC

VPP

VCC

WP#

A18

A7

A6

A5

A4

A3

A2

A1

NC

DQ3

DQ2

DQ1

DQ0

OE#

VSS

CE#

A0

ORDERNUMBERANDPARTMARKING

MT28F008B3VG-9B

MT28F008B3VG-9T

MT28F008B3VG-9BET

MT28F008B3VG-9TET

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

2

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

PIN DESCRIPTIONS

44-PIN SOP 40-PIN TSOP 48-PIN TSOP

NUMBERS

SYMBOL

TYPE

DESCRIPTION

43

9

11

WE#

Input Write Enable: Determines if a given cycle is a WRITE cycle. If

WE# is LOW, the cycle is either a WRITE to the command

execution logic (CEL) or to the memory array.

–

12

14

WP#

Input Write Protect: Unlocks the boot block when HIGH if V^PP

=

VPPH

1

(3.3V) or VPPH (5V) and RP# = VIH during a WRITE or

2

ERASE. Does not affect WRITE or ERASE operation on other

blocks.

12

44

22

10

26

12

CE#

RP#

Input Chip Enable: Activates the device when LOW. When CE# is

HIGH, the device is disabled and goes into standby power

mode.

Input Reset/Power-Down: When LOW, RP# clears the status register,

sets the internal state machine (ISM) to the array read mode

and places the device in deep power-down mode. All inputs,

including CE#, are “Don’t Care,” and all outputs are High-Z.

RP# unlocks the boot block and overrides the condition of

WP# when at V^HH(12V), and must be held at VIH during all

other modes of operation.

14

33

24

–

28

47

OE#

Input Output Enable: Enables data output buffers when LOW.

When OE# is HIGH, the output buffers are disabled.

BYTE#

Input Byte Enable: If BYTE# = HIGH, the upper byte is active through

DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are High-Z, and all

data is accessed through DQ0–DQ7. DQ15/(A - 1) becomes the

least significant address input.

11, 10, 9, 8, 21, 20, 19, 18, 25, 24, 23,

7, 6, 5, 4, 42, 17, 16, 15, 14, 22, 21, 20,

41, 40, 39, 8, 7, 36, 6, 5, 19, 18, 8, 7,

38, 37, 36, 4, 3, 2, 1, 40, 6, 5, 4, 3, 2,

A0–A18/

(A19)

Input Address Inputs: Select a unique 16-bit word or 8-bit byte. The

DQ15/(A - 1) input becomes the lowest order address when

BYTE# = LOW (MT28F800B3) to allow for a selection of an 8-

bit byte from the 1,048,576 available.

35, 34, 3, 2

13, 37

1, 48, 17, 16

31

–

45

DQ15/

(A - 1)

Input/ Data I/O: MSB of data when BYTE# = HIGH. Address Input: LSB

Output of address input when BYTE# = LOW during READ or WRITE

operation.

15, 17, 19,

21, 24, 26,

28, 30

25, 26, 27,

28, 32, 33,

34, 35

29, 31, 33,

35, 38, 40,

42, 44

DQ0–

DQ7

Input/ Data I/Os: Data output pins during any READ operation or

Output data input pins during a WRITE. These pins are used to input

commands to the CEL.

16, 18, 20,

22, 25, 27,

29

–

30, 32, 34,

36, 39, 41,

43

DQ8–

DQ14

Input/ Data I/Os: Data output pins during any READ operation or

Output data input pins during a WRITE when BYTE# = HIGH. These

pins are High-Z when BYTE# is LOW.

1

11

13

V

PP

Supply Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM

until completion of the WRITE or ERASE, VPP must be at VPPH

1

(3.3V) or VPPH2 (5V). VPP = “Don’t Care” during all other

operations.

23

13, 32

–

30, 31

23, 39

29, 38

37

V

CC

Supply Power Supply: +3.3V ±0.3V.

Supply Ground.

27, 46

9, 10, 15

V

SS

NC

–

NoConnect:Thesepinsmaybedrivenorleftunconnected.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

4

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

1

TRUTH TABLE (MT28F800B3)

FUNCTION

RP#

H

CE#

H

OE#

X

WE# WP# BYTE# A0

A9

X

V

PP

DQ0–DQ7 DQ8–DQ14 DQ15/A - 1

High-Z High-Z High-Z

Standby

RESET

READ

X

L

X

READ (word mode)

READ (byte mode)

Output Disable

H

L

H

X

H

L

X

Data-Out Data-Out Data-Out

Data-Out High-Z

A-1

H

X

High-Z High-Z High-Z

WRITE/ERASE (EXCEPT BOOT BLOCK)²

ERASE SETUP

ERASE CONFIRM³

H

L

H

L

X

H

L

X

20h

D0h

X

VPPH

WRITE SETUP

X

10h/40h

WRITE (word mode)⁴

WRITE (byte mode)⁴

READ ARRAY⁵

VPPH Data-In Data-In Data-In

VPPH Data-In

X

A-1

X

FFh

WRITE/ERASE (BOOT BLOCK)^{2, 7}

ERASE SETUP

ERASE CONFIRM³

ERASE CONFIRM^{3, 6}

H

L

H

L

X

H

X

H

X

H

X

H

L

X

20h

D0h

X

VHH

V

PPH

X

H

V

D0h

WRITE SETUP

10h/40h

WRITE (word mode)⁴

WRITE (word mode)^{4, 6}

WRITE (byte mode)⁴

WRITE (byte mode)^{4, 6}

READ ARRAY⁵

VHH

V

PPH Data-In Data-In Data-In

H

VHH

PPH Data-In

X

A-1

X

H

L

X

FFh

DEVICE IDENTIFICATION^{8, 9}

Manufacturer Compatibility

(word mode)¹⁰

H

L

H

X

H

L

V

ID

X

89h

00h

–

Manufacturer Compatibility

(byte mode)

High-Z

X

Device (word mode, top boot)¹⁰

Device (byte mode, top boot)

Device (word mode, bottom boot)¹⁰

Device (byte mode, bottom boot)

H

L

H

X

H

L

H

V

ID

X

9Ch

9Dh

88h

High-Z

88h

–

X

–

H

L

High-Z

X

NOTE: 1. L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH (“Don’t Care”).

2. VPPH = VPPH1 = 3.3V or VPPH2 = 5V.

3. Operation must be preceded by ERASE SETUP command.

4. Operation must be preceded by WRITE SETUP command.

5. The READ ARRAY command must be issued before reading the array after writing or erasing.

6. When WP# = VIH, RP# may be at VIH or VHH.

7. VHH = 12V.

8. VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.

9. A1–A8, A10–A18 = VIL.

10. Value reflects DQ8–DQ15.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

5

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

1

TRUTH TABLE (MT28F008B3)

FUNCTION

Standby

RP#

H

CE#

H

OE#

X

WE#

X

WP#

X

A0

X

A9

X

VPP

X

DQ0–DQ7

High-Z

RESET

L

X

High-Z

READ

H

L

H

X

Data-Out

High-Z

Output Disable

H

WRITE/ERASE (EXCEPT BOOT BLOCK)²

ERASE SETUP

ERASE CONFIRM³

H

L

H

L

X

VPPH

X

20h

D0h

WRITE SETUP

WRITE⁴

READ ARRAY⁵

10h/40h

Data-In

FFh

VPPH

X

WRITE/ERASE (BOOT BLOCK)^{2, 7}

ERASE SETUP

H

VHH

H

L

H

L

X

H

X

H

X

20h

D0h

ERASE CONFIRM³

ERASE CONFIRM^{3, 6}

WRITE SETUP

WRITE⁴

WRITE^{4, 6}

VPPH

X

D0h

H

10h/40h

Data-In

FFh

VHH

H

VPPH

X

READ ARRAY⁵

H

DEVICE IDENTIFICATION^{8, 9}

Manufacturer Compatibility

Device (top boot)

Device (bottom boot)

H

L

H

X

L

VID

X

89h

98h

99h

H

NOTE: 1. L = VIL, H = VIH, X = VIL or VIH.

2. VPPH = VPPH1 = 3.3V or VPPH2 = 5V.

3. Operation must be preceded by ERASE SETUP command.

4. Operation must be preceded by WRITE SETUP command.

5. The READ ARRAY command must be issued before reading the array after writing or erasing.

6. When WP# = VIH, RP# may be at VIH or VHH.

7. VHH = 12V.

8. VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.

9. A1–A8, A10–A19 = VIL.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

6

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

FUNCTIONALDESCRIPTION

The MT28F800B3 and MT28F008B3 Flash devices in-

corporate a number of features ideally suited for system

firmware. The memory array is segmented into indi-

vidual erase blocks. Each block may be erased without

affecting data stored in other blocks. These memory

blocks are read, written and erased with commands to

the command execution logic (CEL). The CEL controls

the operation of the internal state machine (ISM), which

completelycontrolsallWRITE,BLOCKERASEandVERIFY

operations. TheISMprotectseachmemorylocationfrom

over-erasure and optimizes each memory location for

maximum data retention. In addition, the ISM greatly

simplifies the control necessary for writing the device in-

system or in an external programmer.

HARDWARE-PROTECTED BOOT BLOCK

This block of the memory array can be erased or

written only when the RP# pin is taken to VHH or when the

WP# pin is brought HIGH. (The WP# pin does not apply to

the SOP package.) This provides additional security for

the core firmware during in-system firmware updates

should an unintentional power fluctuation or system

resetoccur. TheMT28F800B3andMT28F008B3areavail-

able with the boot block starting at the bottom of the

address space (“B” suffix) and the top of the address

space (“T” suffix).

SELECTABLE BUS SIZE (MT28F800B3)

The MT28F800B3 allows selection of an 8-bit

(1 Meg x 8) or 16-bit (512K x 16) data bus for reading and

writing the memory. The BYTE# pin is used to select the

bus width. In the x16 configuration, control data is read

or written only on the lower eight bits (DQ0–DQ7).

Data written to the memory array utilizes all active

data pins for the selected configuration. When the x8

configuration is selected, data is written in byte form;

when the x16 configuration is selected, data is written in

word form.

The Functional Description provides detailed infor-

mation on the operation of the MT28F800B3 and

MT28F008B3 and is organized into these sections:

•

Overview

Memory Architecture

Output (READ) Operations

Input Operations

Command Set

ISM Status Register

Command Execution

Error Handling

WRITE/ERASE Cycle Endurance

Power Usage

Power-Up

INTERNAL STATE MACHINE (ISM)

BLOCK ERASE and BYTE/WORD WRITE timing are

simplified with an ISM that controls all erase and write

algorithmsinthememoryarray. TheISMensuresprotec-

tion against overerasure and optimizes write margin to

each cell.

During WRITE operations, the ISM automatically in-

crements and monitors WRITE attempts, verifies write

margin on each memory cell and updates the ISM status

register. When BLOCK ERASE is performed, the ISM au-

tomatically overwrites the entire addressed block (elimi-

nates overerasure), increments and monitors ERASE at-

tempts, and sets bits in the ISM status register.

OVERVIEW

SMART 3 TECHNOLOGY (B3)

Smart 3 operation allows maximum flexibility for in-

system READ, WRITE and ERASE operations. WRITE and

ERASE operations may be executed with a V^PPvoltage of

3.3V or 5V. Due to process technology advances, 5V VPP is

optimal for application and production programming.

ISM STATUS REGISTER

ELEVEN INDEPENDENTLY ERASABLE MEMORY

BLOCKS

The ISM status register enables an external processor

tomonitorthestatusoftheISMduringWRITEandERASE

operations. Twobitsofthe8-bitstatusregisteraresetand

cleared entirely by the ISM. These bits indicate whether

theISMisbusywithanERASEorWRITEtaskandwhenan

ERASE has been suspended. Additional error informa-

tion is set in three other bits: V^PPstatus, write status and

erase status.

TheMT28F800B3andMT28F008B3areorganizedinto

eleven independently erasable memory blocks that al-

low portions of the memory to be erased without affect-

ing the rest of the memory data. A special boot block is

hardware-protected against inadvertent erasure or writ-

ing by requiring either a super-voltage on the RP# pin or

driving the WP# pin HIGH. (The WP# pin does not apply

to the SOP package.) One of these two conditions must

exist along with the V^PPvoltage (3.3V or 5V) on the VPP pin

before a WRITE or ERASE is performed on the boot

block. The remaining blocks require that only the VPP

voltage be present on the VPP pin before writing or

erasing.

COMMAND EXECUTION LOGIC (CEL)

The CEL receives and interprets commands to the

device. These commands control the operation of the

ISM and the read path (i.e., memory array, ID register or

status register). Commands may be issued to the CEL

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

7

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

while the ISM is active. However, there are restrictions

on what commands are allowed in this condition. See

the Command Execution section for more detail.

tion is block-oriented. All READ and WRITE operations

are done on a random-access basis.

The boot block is protected from unintentional ERASE

or WRITE with a hardware protection circuit which re-

quires that a super-voltage be applied to RP# or that the

WP# pin be driven HIGH before erasure is commenced.

The boot block is intended for the core firmware required

for basic system functionality. The remaining ten blocks

do not require that either of these two conditions be met

before WRITE or ERASE operations.

DEEP POWER-DOWN MODE

To allow for maximum power conservation, the

MT28F800B3 and MT28F008B3 feature a very low cur-

rent, deep power-down mode. To enter this mode, the

RP# pin is taken to V^SS±0.2V. In this mode, the current

draw is a maximum of 8µA at 3.3V V^CC. Entering deep

power-down also clears the status register and sets the

ISM to the read array mode.

BOOT BLOCK

The hardware-protected boot block provides extra

security for the most sensitive portions of the firmware.

This 16KB block may only be erased or written when the

RP#pinisatthespecifiedbootblockunlockvoltage(V^HH)

of 12V or when the WP# pin is HIGH. During a WRITE or

ERASE of the boot block, the RP# pin must be held at V^HH

or the WP# pin held HIGH until the WRITE or ERASE is

completed. (The WP# pin does not apply to the SOP

package.) The V^PPpin must be at VPPH (3.3V or 5V) when

the boot block is written to or erased.

MEMORY ARCHITECTURE

The MT28F800B3 and MT28F008B3 memory array

architecture is designed to allow sections to be erased

without disturbing the rest of the array. The array is

divided into eleven addressable blocks that vary in size

andareindependentlyerasable. Whenblocksratherthan

the entire array are erased, total device endurance is

enhanced, as is system flexibility. Only the ERASE func-

Figure 1

Memory Address Maps

WORD ADDRESS

BYTE ADDRESS

WORD ADDRESS

BYTE ADDRESS

7FFFFh

FFFFFh

7FFFFh

FFFFFh

16KB Boot Block

128KB Main Block

96KB Main Block

70000h

6FFFFh

E0000h

DFFFFh

7E000h

7DFFFh

7D000h

7CFFFh

7C000h

7BFFFh

FC000h

FBFFFh

FA000h

F9FFFh

F8000h

F7FFFh

8KB Parameter Block

60000h

5FFFFh

C0000h

BFFFFh

96KB Main Block

128KB Main Block

50000h

4FFFFh

A0000h

9FFFFh

70000h

6FFFFh

E0000h

DFFFFh

40000h

3FFFFh

80000h

7FFFFh

60000h

5FFFFh

C0000h

BFFFFh

30000h

2FFFFh

60000h

5FFFFh

50000h

4FFFFh

A0000h

9FFFFh

20000h

1FFFFh

40000h

3FFFFh

40000h

3FFFFh

80000h

7FFFFh

10000h

0FFFFh

20000h

1FFFFh

30000h

2FFFFh

60000h

5FFFFh

04000h

03FFFh

03000h

02FFFh

02000h

01FFFh

08000h

07FFFh

06000h

05FFFh

04000h

03FFFh

20000h

1FFFFh

40000h

3FFFFh

8KB Parameter Block

10000h

0FFFFh

20000h

1FFFFh

16KB Boot Block

00000h

Bottom Boot

MT28F008B3/800B3xx-xxB

Top Boot

MT28F008B3/800B3xx-xxT

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

8

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

The MT28F800B3 and MT28F008B3 are available in

STATUS REGISTER

two configurations and top or bottom boot block. The top

boot block version supports processors of the x86 variety.

The bottom boot block version is intended for 680X0 and

RISC applications. Figure 1 illustrates the memory ad-

dress maps associated with these two versions.

Performing a READ of the status register requires

the same input sequencing as a READ of the array

except that the address inputs are “Don’t Care.” The

status register contents are always output on DQ0–

DQ7, regardless of the condition of BYTE# on the

MT28F800B3. DQ8–DQ15 are LOW when BYTE# is

HIGH, and DQ8–DQ14 are High-Z when BYTE# is LOW.

Data from the status register is latched on the falling

edge of OE# or CE#, whichever occurs last. If the con-

tents of the status register change during a READ of the

status register, either OE# or CE# may be toggled while

the other is held LOW to update the output.

PARAMETER BLOCKS

The two 8KB parameter blocks store less sensitive and

more frequently changing system parameters and also

may store configuration or diagnostic coding. These

blocks are enabled for erasure when the V^PPpin is at VPPH.

No super-voltage unlock or WP# control is required.

Following a WRITE or ERASE, the device automati-

cally enters the status register read mode. In addition, a

READ during a WRITE or ERASE produces the status

register contents on DQ0–DQ7. When the device is in the

erase suspend mode, a READ operation produces the

status register contents until another command is is-

sued. In certain other modes, READ STATUS REGISTER

may be given to return to the status register read mode.

All commands and their operations are described in the

Command Set and Command Execution sections.

MAIN MEMORY BLOCKS

The eight remaining blocks are general-purpose

memory blocks and do not require a super-voltage on

RP# or WP# control to be erased or written. These blocks

are intended for code storage, ROM-resident applica-

tions or operating systems that require in-system update

capability.

OUTPUT (READ) OPERATIONS

The MT28F800B3 and MT28F008B3 feature three dif-

ferenttypesofREADs. Dependingonthecurrentmodeof

the device, a READ operation produces data from the

memory array, status register or device identification

register. In each of these three cases, the WE#, CE# and

OE# inputs are controlled in a similar manner. Moving

between modes to perform a specific READ is described

in the Command Execution section.

IDENTIFICATION REGISTER

A READ of the two 8-bit device identification registers

requires the same input sequencing as a READ of the

array. WE# must be HIGH, and OE# and CE# must be

LOW. However, ID register data is output only on DQ0–

DQ7, regardless of the condition of BYTE# on the

MT28F800B3. A0 is used to decode between the two bytes

of the device ID register; all other address inputs are

“Don’t Care.” When A0 is LOW, the manufacturer com-

patibility ID is output, and when A0 is HIGH, the device

ID is output. DQ8–DQ15 are High-Z when BYTE# is LOW.

When BYTE# is HIGH, DQ8–DQ15 are 00h when the

manufacturer compatibility ID is read and 88h when the

device ID is read.

To get to the identification register read mode, READ

IDENTIFICATION may be issued while the device is in

certainothermodes. Inaddition, theidentificationregis-

ter read mode can be reached by applying a super-volt-

age (V^ID) to the A9 pin. Using this method, the ID register

can be read while the device is in any mode. When A9 is

returned to VIL or VIH, the device returns to the previous

mode.

MEMORY ARRAY

To read the memory array, WE# must be HIGH, and

OE# and CE# must be LOW. Valid data is output on the

DQ pins when these conditions have been met, and a

valid address is given. Valid data remains on the DQ pins

untiltheaddresschanges, oruntilOE#orCE#goesHIGH,

whichever occurs first. The DQ pins continue to output

new data after each address transition as long as OE# and

CE# remain LOW.

The MT28F800B3 features selectable bus widths.

When the memory array is accessed as a 512K x 16, BYTE#

is HIGH, and data is output on DQ0–DQ15. To access the

memory array as a 1 Meg x 8, BYTE# must be LOW, DQ8–

DQ14 must be High-Z, and all data must be output on

DQ0–DQ7. The DQ15/(A - 1) pin becomes the lowest

order address input so that 1,048,576 locations can be

read.

INPUT OPERATIONS

The DQ pins are used either to input data to the array

or to input a command to the CEL. A command input

issues an 8-bit command to the CEL to control the mode

of operation of the device. A WRITE is used to input

data to the memory array. The following section de-

After power-up or RESET, the device is automatically

in the array read mode. All commands and their opera-

tions are covered in the Command Set and Command

Execution sections.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

9

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

scribes both types of inputs. More information describ-

RP# pin be at VHH or WP# be HIGH. A0–A18 (A19) pro-

vide the address to be written, while the data to be

written to the array is input on the DQ pins. The data

and addresses are latched on the rising edge of CE#

(CE#-controlled) or WE# (WE#-controlled), whichever

occurs first. A WRITE must be preceded by a WRITE

SETUP command. Details on how to input data to the

array are described in the Write Sequence section.

Selectable bus sizing applies to WRITEs as it does to

READs on the MT28F800B3. When BYTE# is LOW (byte

mode), data is input on DQ0–DQ7, DQ8–DQ14 are High-

Z, and DQ15 becomes the lowest order address input.

WhenBYTE#isHIGH(wordmode), dataisinputonDQ0–

DQ15.

ing how to use the two types of inputs to write or erase

the device is provided in the Command Execution sec-

tion.

COMMANDS

To perform a command input, OE# must be HIGH,

and CE# and WE# must be LOW. Addresses are “Don’t

Care” but must be held stable, except during an ERASE

CONFIRM (described in a later section). The 8-bit com-

mandisinputonDQ0–DQ7, whileDQ8–DQ15are“Don’t

Care” on the MT28F800B3. The command is latched on

the rising edge of CE# (CE#-controlled) or WE# (WE#-

controlled), whichever occurs first. The condition of

BYTE# on the MT28F800B3 has no effect on a com-

mand input.

COMMAND SET

To simplify writing of the memory blocks, the

MT28F800B3 and MT28F008B3 incorporate an ISM that

controls all internal algorithms for writing and erasing

the floating gate memory cells. An 8-bit command set is

used to control the device. Details on how to sequence

commands are provided in the Command Execution

section. Table 1 lists the valid commands.

MEMORY ARRAY

A WRITE to the memory array sets the desired bits to

logic 0s but cannot change a given bit to a logic 1 from a

logic 0. Setting any bits to a logic 1 requires that the entire

blockbeerased. ToperformaWRITE, OE#mustbeHIGH,

CE# and WE# must be LOW, and V^PPmust be set to VPPH1

or VPPH2. Writing to the boot block also requires that the

Table 1

Command Set

COMMAND

HEX CODE DESCRIPTION

RESERVED

00h

This command and all unlisted commands are invalid and should not

be called. These commands are reserved to allow for future feature

enhancements.

READ ARRAY

FFh

90h

Must be issued after any other command cycle before the array can be

read. It is not necessary to issue this command after power-up or RESET.

IDENTIFY DEVICE

Allows the device and manufacturer compatibility ID to be read. A0 is

used to decode between the manufacturer compatibility ID (A0 = LOW)

and device ID (A0 = HIGH).

READ STATUS REGISTER

70h

Allows the status register to be read. Please refer to Table 2 for more

information on the status register bits.

CLEAR STATUS REGISTER

ERASE SETUP

50h

20h

Clears status register bits 3-5, which cannot be cleared by the ISM.

The first command given in the two-cycle ERASE sequence. The ERASE is

not completed unless followed by ERASE CONFIRM.

ERASE CONFIRM/RESUME

D0h

The second command given in the two-cycle ERASE sequence. Must follow

an ERASE SETUP command to be valid. Also used during an ERASE

SUSPEND to resume the ERASE.

WRITE SETUP

40h or

10h

The first command given in the two-cycle WRITE sequence. The write

data and address are given in the following cycle to complete the WRITE.

ERASE SUSPEND

B0h

Requests a halt of the ERASE and puts the device into the erase suspend

mode. When the device is in this mode, only READ STATUS REGISTER,

READ ARRAY and ERASE RESUME commands may be executed.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

10

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

ISMSTATUSREGISTER

The 8-bit ISM status register (see Table 2) is polled

to check for WRITE or ERASE completion or any related

errors. During or following a WRITE, ERASE or ERASE

SUSPEND, a READ operation outputs the status register

contents on DQ0–DQ7 without prior command. While

the status register contents are read, the outputs are not

be updated if there is a change in the ISM status unless

OE# or CE# is toggled. If the device is not in the write,

erase, erase suspend or status register read mode, READ

STATUS REGISTER (70h) can be issued to view the status

register contents.

All of the defined bits are set by the ISM, but only

the ISM and erase suspend status bits are reset by the

ISM. The erase, write and V^PPstatus bits must be cleared

using CLEAR STATUS REGISTER. If the VPP status bit

(SR3) is set, the CEL does not allow further WRITE or

ERASE operations until the status register is cleared.

This enables the user to choose when to poll and clear

the status register. For example, the host system may

perform multiple BYTE WRITE operations before check-

ing the status register instead of checking after each

individual WRITE. Asserting the RP# signal or power-

ing down the device also clears the status register.

Table 2

Status Register Bit Definitions

ISMS

ESS

ES

WS

VPPS

R

7

6

5

4

3

2–0

STATUS

BIT #

STATUS REGISTER BIT

DESCRIPTION

SR7

SR6

SR5

SR4

SR3

ISM STATUS (ISMS)

1 = Ready

0 = Busy

The ISMS bit displays the active status of the state machine during

WRITE or BLOCK ERASE operations. The controlling logic polls this

bit to determine when the erase and write status bits are valid.

ERASE SUSPEND STATUS (ESS)

1 = ERASE suspended

0 = ERASE in progress/completed

Issuing an ERASE SUSPEND places the ISM in the suspend mode

and sets this and the ISMS bit to “1.” The ESS bit remains “1”

until an ERASE RESUME is issued.

ERASE STATUS (ES)

1 = BLOCK ERASE error

0 = Successful BLOCK ERASE

ES is set to “1” after the maximum number of ERASE cycles is

executed by the ISM without a successful verify. ES is only cleared

by a CLEAR STATUS REGISTER command or after a RESET.

WRITE STATUS (WS)

1 = WORD/BYTE WRITE error

0 = Successful WORD/BYTE WRITE by a CLEAR STATUS REGISTER command or after a RESET.

WS is set to “1” after the maximum number of WRITE cycles is

executed by the ISM without a successful verify. WS is only cleared

VPP STATUS (VPPS)

1 = No VPP voltage detected

0 = VPP present

VPPS detects the presence of a VPP voltage. It does not monitor VPP

continuously, nor does it indicate a valid VPP voltage. The VPP pin

is sampled for 3.3V or 5V after WRITE or ERASE CONFIRM is given.

VPPS must be cleared by CLEAR STATUS REGISTER or by a RESET.

SR0-2

RESERVED

Reserved for future use.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

11

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

COMMAND EXECUTION

Commands are issued to bring the device into differ-

entoperationalmodes. Eachmodeallowsspecificopera-

tions to be performed. Several modes require a sequence

of commands to be written before they are reached. The

following section describes the properties of each mode,

and Table 3 lists all command sequences required to

perform the desired operation.

WRITE SEQUENCE

Two consecutive cycles are needed to input data to

the array. WRITE SETUP (40h or 10h) is given in the first

cycle. The next cycle is the WRITE, during which the write

address and data are issued and V^PPis brought to VPPH.

Writing to the boot block also requires that the RP# pin be

brought to V^HHor the WP# pin be brought HIGH at the

same time VPP is brought to VPPH. The ISM now begins to

write the word or byte. V^PPmust be held at VPPH until the

WRITE is completed (SR7 = 1).

While the ISM executes the WRITE, the ISM status bit

(SR7) is at 0, and the device does not respond to any

commands. Any READ operation produces the status

register contents on DQ0–DQ7. When the ISM status bit

(SR7) is set to a logic 1, the WRITE has been completed,

and the device goes into the status register read mode

until another command is given.

READ ARRAY

The array read mode is the initial state of the device

upon power-up and after a RESET. If the device is in any

other mode, READ ARRAY (FFh) must be given to return

to the array read mode. Unlike the WRITE SETUP com-

mand (40h), READ ARRAY does not need to be given

before each individual READ access.

IDENTIFY DEVICE

IDENTIFY DEVICE (90h) may be written to the CEL to

enter the identify device mode. While the device is in this

mode, anyREADproducesthedeviceidentificationwhen

A0 is HIGH and the manufacturer compatibility identifi-

cation when A0 is LOW. The device remains in this mode

until another command is given.

After the ISM has initiated the WRITE, it cannot be

aborted except by a RESET or by powering down the part.

Doing either during a WRITE corrupts the data being

written. If only the WRITE SETUP command has been

given, the WRITE may be nullified by performing a null

WRITE. To execute a null WRITE, FFh must be written

Table 3

Command Sequences

BUS

CYCLES

FIRST

CYCLE

SECOND

CYCLE

COMMANDS

REQ’D OPERATION ADDRESS DATA OPERATIONADDRESS DATA NOTES

READ ARRAY

1

3

2

1

2

WRITE

X

FFh

90h

70h

50h

20h

B0h

40h

10h

1

2, 3

4

IDENTIFY DEVICE

READ

IA

X

ID

READ STATUS REGISTER

CLEAR STATUS REGISTER

ERASE SETUP/CONFIRM

ERASE SUSPEND/RESUME

WRITE SETUP/WRITE

SRD

WRITE

BA

X

D0h

WD

5, 6

WA

6, 7

ALTERNATE WORD/BYTE

WRITE

NOTE: 1. Must follow WRITE or ERASE CONFIRM commands to the CEL in order to enable Flash array READ cycles.

2. IA = Identify Address: 00h for manufacturer compatibility ID; 01h for device ID.

3. ID = Identify Data.

4. SRD = Status Register Data.

5. BA = Block Address (A12–A19).

6. Addresses are “Don’t Care” in first cycle but must be held stable.

7. WA = Address to be written; WD = Data to be written to WA.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

12

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

when BYTE# is LOW, or FFFFh must be written when

that either the RP# pin be set to VHH or the WP# pin be

held HIGH at the same time VPP is set to VPPH.

BYTE# is HIGH. When the ISM status bit (SR7) has been

set, the device is in the status register read mode until

another command is issued.

ERASE SUSPENSION

The only command that may be issued while an

ERASE is in progress is ERASE SUSPEND. This com-

mand enables other commands to be executed while

pausing the ERASE in progress. When the device has

reached the erase suspend mode, the erase suspend

status bit (SR6) and ISM status bit (SR7) are set. The

device may now be given a READ ARRAY, ERASE RE-

SUME or READ STATUS REGISTER command. After

READ ARRAY has been issued, any location not within

the block being erased may be read. If ERASE RESUME

is issued before SR6 has been set, the device immedi-

ately proceeds with the ERASE in progress.

ERASE SEQUENCE

Executing an ERASE sequence sets all bits within a

block to logic 1. The command sequence necessary to

execute an ERASE is similar to that of a WRITE. To pro-

vide added security against accidental block erasure,

two consecutive command cycles are required to initiate

an ERASE of a block. In the first cycle, addresses are

“Don’t Care,” and ERASE SETUP (20h) is given. In the

second cycle, V^PPmust be brought to VPPH, an address

within the block to be erased must be issued, and ERASE

CONFIRM(D0h)mustbegiven. Ifacommandotherthan

ERASE CONFIRM is given, the write and erase status bits

(SR4 and SR5) are set, and the device is in the status

register read mode.

After the ERASE CONFIRM (D0h) is issued, the ISM

starts the ERASE of the addressed block. Any READ

operation outputs the status register contents on DQ0–

DQ7. V^PPmust be held at VPPH until the ERASE is com-

pleted (SR7 = 1). When the ERASE is completed, the

device is in the status register read mode until another

command is issued. Erasing the boot block also requires

ERROR HANDLING

After the ISM status bit (SR7) has been set, the VPP

(SR3), write (SR4) and erase (SR5) status bits may be

checked. If one or a combination of these three bits has

been set, an error has occurred. The ISM cannot reset

these three bits. To clear these bits, CLEAR STATUS REG-

ISTER (50h) must be given. If the V^PPstatus bit (SR3) is set,

further WRITE or ERASE operations cannot resume until

the status register is cleared. Table 4 lists the combina-

tion of errors.

Table 4

Status Register Error Code Description

1

STATUS BITS

SR4

SR5

0

SR3

0

ERROR DESCRIPTION

0

1

0

1

No errors

0

1

VPP voltage error

0

WRITE error

0

1

WRITE error, VPP voltage not valid at time of WRITE

ERASE error

1

0

1

ERASE error, VPP voltage not valid at time of ERASE CONFIRM

Command sequencing error or WRITE/ERASE error

1

0

1

Command sequencing error, VPP voltage error, with WRITE and ERASE errors

NOTE: 1. SR3-SR5 must be cleared using CLEAR STATUS REGISTER.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

13

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

WRITE/ERASE CYCLE ENDURANCE

POWER-UP

The MT28F800B3 and MT28F008B3 are designed and

fabricated to meet advanced firmware storage require-

ments. To ensure this level of reliability, V^PPmust be at

3.3V ±0.3V or 5V ±10% during WRITE or ERASE cycles.

Due to process technology advances, 5V VPP is optimal

for application and production programming.

The likelihood of unwanted WRITE or ERASE opera-

tions is minimized because two consecutive cycles are

required to execute either operation. However, to reset

the ISM and to provide additional protection while V^CCis

ramping, one of the following conditions must be met:

•

RP# must be held LOW until V^CCis at valid

functional level; or

•

CE# or WE# may be held HIGH and

RP# must be toggled from V^CC-GND-VCC.

POWER USAGE

The MT28F800B3 and MT28F008B3 offer several

power-saving features that may be utilized in the array

read mode to conserve power. Deep power-down mode

is enabled by bringing RP# LOW. Current draw (I^CC) in

this mode is a maximum of 8µA at 3.3V VCC. When CE# is

HIGH, the device enters standby mode. In this mode,

maximum ICC current is 100µA at 3.3V VCC. If CE# is

brought HIGH during aWRITEor ERASE, the ISM contin-

ues to operate, and the device consumes the respective

active power until the WRITE or ERASE is completed.

After a power-up or RESET, the status register is reset,

and the device enters the array read mode.

Figure 2

Power-Up/Reset Timing Diagram

RP#

Note 1

VCC

(3.3V)

t

AA

Address

VALID

Data

t

RWH

UNDEFINED

NOTE: 1. VCC must be within the valid operating range before RP#

goes HIGH.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

14

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

SELF-TIMED WRITE SEQUENCE

COMPLETE WRITE STATUS-CHECK

SEQUENCE

1

(WORD OR BYTE WRITE)

Start (WRITE completed)

Start

NO

4, 5

SR3 = 0?

YES

V

^PPError

WRITE 40h or 10h

5

SR4 = 0?

YES

BYTE/WORD WRITE Error

VPP = 3.3V or 5V

WRITE Successful

WRITE Word or Byte

Address/Data

STATUS REGISTER

READ

NO

SR7 = 1?

YES

2

Complete Status

Check (optional)

3

WRITE Complete

NOTE: 1. Sequence may be repeated for additional BYTE or WORD WRITEs.

2. Complete status check is not required. However, if SR3 = 1, further WRITEs are inhibited until the status register is

cleared.

3. Device will be in status register read mode. To return to the array read mode, the FFh command must be issued.

4. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE

or ERASE operations are allowed by the CEL.

5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

15

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

1

SELF-TIMED BLOCK ERASE SEQUENCE

COMPLETE BLOCK ERASE

STATUS-CHECK SEQUENCE

Start (ERASE completed)

Start

NO

YES

NO

5, 6

SR3 = 0?

YES

VPP Error

WRITE 20h

VPP = 3.3V or 5V

6

SR4, 5 = 1?

NO

Command Sequence Error

WRITE D0h,

Block Address

6

SR5 = 0?

BLOCK ERASE Error

YES

STATUS REGISTER

READ

ERASE Successful

NO

SR7 = 1?

YES

Suspend ERASE?

YES

4

2

Suspend

Sequence

Complete Status

Check (optional)

ERASE Resumed

3

ERASE Complete

NOTE: 1. Sequence may be repeated to erase additional blocks.

2. Complete status check is not required. However, if SR3 = 1, further ERASEs are inhibited until the status register is

cleared.

3. To return to the array read mode, the FFh command must be issued.

4. Refer to the ERASE SUSPEND flowchart for more information.

5. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE

or ERASE operations are allowed by the CEL.

6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

16

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

ERASE SUSPEND/RESUME SEQUENCE

Start (ERASE in progress)

WRITE B0h

(ERASE SUSPEND)

VPP = 3.3V or 5V

STATUS REGISTER

READ

NO

SR7 = 1?

YES

SR6 = 1?

YES

ERASE Completed

WRITE FFh

(READ ARRAY)

Done

NO

Reading?

YES

WRITE D0h

(ERASE RESUME)

Resume ERASE

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

17

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

*Stresses greater than those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the de-

vice. This is a stress rating only, and functional operation

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC Supply

Relative to VSS ..................................... -0.5V to +4V**

Input Voltage Relative to V^SS.................... -0.5V to +4V**

VPP Voltage Relative to VSS ........................ -0.5V to +5.5V^†

RP# or A9 Pin Voltage

of the device at these or any other conditions above those

indicated in the operational sections of this specification

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

**V^CC, input and I/O pins may transition to -2V for <20ns

and VCC + 2V for <20ns.

Relative to V^SS................................ -0.5V to +12.6V^††

Temperature Under Bias .......................... -10ºC to +80ºC

Storage Temperature (plastic) ............... -55ºC to +125ºC

Power Dissipation ......................................................... 1W

^†Voltage may pulse to -2V for <20ns and 7V for <20ns.

^††Voltage may pulse to -2V for <20ns and 14V for <20ns.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC READ

OPERATING CONDITIONS

Commercial Temperature (0ºC ≤ T_A≤ +70ºC) and Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

PARAMETER/CONDITION

SYMBOL

VCC

MIN

3

MAX

3.6

UNITS NOTES

3.3V Supply Voltage

V

1

Input High (Logic 1) Voltage, all inputs

Input Low (Logic 0) Voltage, all inputs

Device Identification Voltage, A9

V^PPSupply Voltage

VIH

2.4

-0.5

10

VCC + 0.5

0.8

VIL

VID

12.6

VPP

-0.5

5.5

DC OPERATING CHARACTERISTICS

Commercial Temperature (0ºC ≤ T_A≤ +70ºC) and Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS NOTES

OUTPUT VOLTAGE LEVELS

VOH

VCC - 0.2

–

V

Output High Voltage (IOH = -100µA)

Output Low Voltage (IOL = 2mA)

1

VOL

IL

–

-1

–

0.45

1

V

INPUT LEAKAGE CURRENT

Any input (0V ≤ VIN ≤ VCC);

All other pins not under test = 0V

µA

INPUT LEAKAGE CURRENT: A9 INPUT

(10V ≤ A9 ≤ 12V = VID)

IID

500

10

INPUT LEAKAGE CURRENT: RP# INPUT

(10V ≤ RP# ≤ 12V = VHH)

IHH

IOZ

–

OUTPUT LEAKAGE CURRENT

-10

(DOUT is disabled; 0V ≤ VOUT ≤ VCC)

NOTE: 1. All voltages referenced to VSS.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

18

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

CAPACITANCE

(T_A= 25ºC; f = 1 MHz)

PARAMETER/CONDITION

Input Capacitance

SYMBOL MAX

UNITS NOTES

CI

9

pF

Output Capacitance

CO

12

1

READ AND STANDBY CURRENT DRAIN

Commercial Temperature (0ºC ≤ T_A≤ +70ºC) and Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

PARAMETER/CONDITION

SYMBOL

MAX

UNITS NOTES

READ CURRENT: WORD-WIDE

(CE# ≤ 0.2V; OE# V^CC- 0.2V; f = 5 MHz;

ICC1

15

mA

2, 3

Other inputs ≤ 0.2V or VCC - 0.2V; RP# VCC - 0.2V)

READ CURRENT: BYTE-WIDE

(CE# ≤ 0.2V; OE# VCC - 0.2V; f = 5 MHz;

Other inputs ≤ 0.2V or VCC - 0.2V; RP# = VCC - 0.2V)

ICC2

ICC3

15

2

STANDBY CURRENT: TTL INPUT LEVELS

VCC power supply standby current

(CE# = RP# = VIH; Other inputs = VIL or VIH)

STANDBY CURRENT: CMOS INPUT LEVELS

V^CCpower supply standby current

(CE# = RP# = VCC - 0.2V)

ICC4

ICC6

IPP1

IPP2

100

8

µA

DEEP POWER-DOWN CURRENT: VCC SUPPLY

(RP# = VSS ±0.2V)

STANDBY OR READ CURRENT: VPP SUPPLY

(VPP ≤ 5.5V)

±15

5

DEEP POWER-DOWN CURRENT: VPP SUPPLY

(RP# = VSS ±0.2V)

NOTE: 1. VCC = MAX VCC during ICC tests.

2. ICC is dependent on cycle rates.

3. ICC is dependent on output loading. Specified values are obtained with the outputs open.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

19

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

READTIMINGPARAMETERS

ELECTRICALCHARACTERISTICSANDRECOMMENDEDACOPERATINGCONDITIONS

Commercial Temperature (0ºC ≤ T_A≤ +70ºC) and Extended Temperature (-40ºC ≤ T_A≤ +85ºC); VCC = +3.3V ±0.3V

1

ACCHARACTERISTICS

-9/-9 ET

PARAMETER

READ cycle time

Access time from CE#

Access time from OE#

Access time from address

RP# HIGH to output valid delay

OE# or CE# HIGH to output in High-Z

Output hold time from OE#, CE# or address change

RP# LOW pulse width

SYMBOL

MIN

90

MAX

UNITS NOTES

ns

t

RC

ACE

AOE

AA

t

90

40

90

1,000

25

ns

2

t

RWH

t

OD

OH

t

0

150

t

RP

NOTE: 1. Measurements tested under AC Test Conditions.

t

2. OE# may be delayed by ACE minus AOE after CE# falls before ACE is affected.

AC TEST CONDITIONS

Input pulse levels ...................................................... 0V to 3V

Input rise and fall times ................................................ <10ns

Input timing reference level ........................................... 1.5V

Output timing reference level ........................................ 1.5V

Output load ................................... 1 TTL gate and C^L= 50pF

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

20

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

1

WORD-WIDE READ CYCLE

V_IH

V_IL

A0–A18/(A19)

VALID ADDRESS

t

RC

t

AA

V_IH

V_IL

CE#

t

ACE

V_IH

V_IL

OE#

V_IH

V_IL

WE#

t

OD

t

AOE

OH

V_IH

V_IL

VALID DATA

DQ0–DQ15

t

RWH

V_IH

RP#

V

IL

DON’T CARE

UNDEFINED

TIMING PARAMETERS

Commercial Temperature (0ºC ≤ T_A≤ +70ºC)

Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

-9/-9 ET

SYMBOL

MIN

MAX UNITS

SYMBOL

MIN

MAX UNITS

t

RC

90

ns

RWH

1,000

25

ns

t

ACE

90

40

90

ns

OD

t

AOE

OH

0

t

AA

NOTE: 1. BYTE# = HIGH (MT28F800B3 only).

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

21

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

1

BYTE-WIDE READ CYCLE

V_IH

V_IL

A0–A18/(A19)

VALID ADDRESS

t

RC

t

AA

V_IH

V_IL

CE#

t

ACE

V_IH

V_IL

OE#

V_IH

V_IL

WE#

t

OD

t

AOE

OH

V_IH

V_IL

VALID DATA

DQ0–DQ7

V_IH

V_IL

HIGH-Z

DQ8–DQ14

t

RWH

V_IH

V_IL

RP#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

Commercial Temperature (0ºC ≤ T_A≤ +70ºC)

Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

-9/-9 ET

SYMBOL

MIN

90

MAX UNITS

SYMBOL

MIN

MAX UNITS

t

RC

ns

RWH

1,000

25

ns

t

ACE

90

40

90

ns

OD

t

AOE

OH

0

t

AA

NOTE: 1. BYTE# = LOW (MT28F800B3 only).

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

22

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

1

RECOMMENDED DC WRITE/ERASE CONDITIONS

Commercial Temperature (0ºC ≤ T_A≤ +70ºC) and Extended Temperature (-40ºC ≤ T_A≤ +85ºC); VCC = +3.3V ±0.3V

PARAMETER/CONDITION

SYMBOL MIN MAX UNITS NOTES

VPP WRITE/ERASE lockout voltage

VPP voltage during WRITE/ERASE operation

Boot block unlock voltage

VPPLK

VPPH1

VPPH2

VHH

–

1.5

3.6

5.5

12.6

–

V

2

3

3.0

4.5

10

2

VCC WRITE/ERASE lockout voltage

VLKO

4

WRITE/ERASE CURRENT DRAIN

Commercial Temperature (0ºC ≤ T_A≤ +70ºC) and Extended Temperature (-40ºC - T_A- +85ºC); VCC = +3.3V ±0.3V

3.3V VPP 5V VPP

PARAMETER/CONDITION

SYMBOL MAX

MAX UNITS NOTES

WORD WRITE CURRENT: VCC SUPPLY

WORD WRITE CURRENT: VPP SUPPLY

BYTE WRITE CURRENT: VCC SUPPLY

BYTE WRITE CURRENT: VPP SUPPLY

ERASE CURRENT: VCC SUPPLY

ICC7

IPP3

ICC8

IPP4

ICC9

IPP5

ICC10

20

25

8

20

25

30

10

mA

5

6

ERASE CURRENT: VPP SUPPLY

ERASE SUSPEND CURRENT: VCC SUPPLY

(ERASE suspended)

7

ERASE SUSPEND CURRENT: V^PPSUPPLY

(ERASE suspended)

IPP6

200

µA

NOTE: 1. WRITE operations are tested at VPP voltages equal to or less than the previous ERASE.

2. Absolute WRITE/ERASE protection when V^PP≤ VPPLK.

3. When 3.3V VCC and VPP are used, VCC cannot exceed VPP by more than 500mV during WRITE and ERASE operations.

4. All currents are in RMS unless otherwise noted.

5. Applies to MT28F800B3 only.

6. Applies to MT28F008B3 and MT28F800B3 with BYTE# = LOW.

7. Parameter is specified when device is not accessed. Actual current draw will be I^CC10 plus read current if a READ is

executed while the device is in erase suspend mode.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

23

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

SPEED-DEPENDENTWRITE/ERASEACTIMINGCHARACTERISTICSAND

RECOMMENDED AC OPERATING CONDITIONS:

WE# (CE#)-CONTROLLED WRITES

Commercial Temperature (0ºC ≤ T_A≤ +70ºC) and Extended Temperature (-40ºC ≤ T_A≤ +85ºC); VCC = +3.3V ±0.3V

ACCHARACTERISTICS

-9/-9 ET

PARAMETER

WRITE cycle time

WE# (CE#) HIGH pulse width

WE# (CE#) pulse width

SYMBOL

MIN

MAX

UNITS NOTES

t

WC

90

20

50

0

50

0

ns

t

WPH ( CPH)

t

WP ( CP)

t

Address setup time to WE# (CE#) HIGH

Address hold time from WE# (CE#) HIGH

Data setup time to WE# (CE#) HIGH

Data hold time from WE# (CE#) HIGH

CE# (WE#) setup time to WE# (CE#) LOW

CE# (WE#) hold time from WE# (CE#) HIGH

VPP setup time to WE# (CE#) HIGH

RP# HIGH to WE# (CE#) LOW delay

RP# at VHH or WP# HIGH setup time to WE# (CE#) HIGH

WRITE duration (WORD or BYTE WRITE)

Boot BLOCK ERASE duration

AS

AH

DS

DH

t

CS ( WS)

t

CH ( WH)

0

t

VPS1

VPS2

RS

RHS

WED1

WED2

WED3

WED4

200

100

1,000

100

2

100

500

200

0

ns

µs

ms

ns

1

2

t

3

5

4

5

3

6

t

Parameter BLOCK ERASE duration

Main BLOCK ERASE duration

t

WE# (CE#) HIGH to busy status (SR7 = 0)

VPP hold time from status data valid

RP# at VHH or WP# HIGH hold time from status data valid

Boot block relock delay time

WB

VPH

RHH

REL

t

0

t

100

WORD/BYTE WRITE AND ERASE DURATION CHARACTERISTICS

3.3V VPP

5V VPP

PARAMETER

TYP MAX TYP MAX UNITS NOTES

Boot/parameter BLOCK ERASE time

Main BLOCK ERASE time

0.5

2.8

1.5

7

14

–

0.4

1.5

1

7

14

–

s

7

Main BLOCK WRITE time (byte mode)

Main BLOCK WRITE time (word mode)

7, 8, 9

–

1

–

NOTE: 1. Measured with VPP = VPPH1 = 3.3V.

2. Measured with VPP = VPPH2 = 5V.

3. RP# should be held at VHH or WP# held HIGH until boot block WRITE or ERASE is complete.

t

4. Polling status register before WB is met may falsely indicate WRITE or ERASE completion.

5. WRITE/ERASE times are measured to valid status register data (SR7 = 1).

t

6. REL is required to relock boot block after WRITE or ERASE to boot block.

7. Typical values measured at T = +25ºC.

A

8. Assumes no system overhead.

9. Typical WRITE times use checkerboard data pattern.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

24

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

WRITE/ERASE CYCLE

WE#-CONTROLLEDWRITE/ERASE

V_IH

V_IL

A0–A18/(A19)

Note 1

AIN

t

AH

t

AH

AS

V_IH

V_IL

CE#

OE#

t

CH

CS

V_IH

V_IL

t

WC

t

WP

t

WED1/2/3/4

WPH

V_IH

V_IL

t

WB

WE#

t

DH

t

DS

V_IH

V_IL

DQ0–DQ7/

Status

(SR7=0)

CMD

in

CMD/

Data-in

Status

(SR7=1)

CMD

in

DQ0–DQ15 ²

t

RS

RHS

RHH

V_HH

[Unlock boot block]

V_IH

RP# ³

V_IL

[Unlock boot block]

V_IH

WP# ³

V_IL

t

VPS1

t

VPS2

VPH

[5V VPP]

V_PPH2

V_PPH1

[3.3V VPP]

VPP

V_IL

WRITE or ERASE (block)

address asserted, and

WRITE data or ERASE

CONFIRM issued

WRITE or ERASE

executed, status register

checked for completion

Command for next

operation issued

WRITE SETUP or

ERASE SETUP input

DON’T CARE

TIMING PARAMETERS

Commercial Temperature (0ºC ≤ T_A≤ +70ºC)

Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

-9/-9 ET

SYMBOL

MIN

90

20

50

0

MAX UNITS

SYMBOL

MIN

MAX UNITS

t

WC

ns

VPS2

100

1,000

100

2

ns

µs

ms

ns

t

WPH

RS

t

WP

RHS

t

AS

WED1

t

AH

WED2

100

500

200

0

t

DS

50

0

WED3

t

DH

WED4

t

CS

0

WB

t

CH

0

VPH

t

VPS1

200

RHH

0

NOTE: 1. Address inputs are “Don’t Care” but must be held stable.

2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit.

3. Either RP# at VHH or WP# HIGH unlocks the boot block.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

25

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

WRITE/ERASE CYCLE

CE#-CONTROLLEDWRITE/ERASE

V_IH

V_IL

A0–A18/(A19)

Note 1

AIN

t

AH

t

AH

AS

V_IH

V_IL

WE#

OE#

t

WH

WS

V_IH

V_IL

t

WC

t

CP

t

WED1/2/3/4

CPH

V_IH

V_IL

CE#

t

WB

t

DH

t

DH

t

DS

V_IH

V_IL

Status

(SR7=0)

CMD

in

CMD/

Data-in

Status

(SR7=1)

CMD

in

DQ0–DQ7/

DQ0–DQ15 ²

t

RS

RHS

RHH

V_HH

[Unlock boot block]

V_IH

RP# ³

V_IL

[Unlock boot block]

V_IH

WP# ³

V_IL

t

VPS1

t

VPS2

VPH

[5V VPP]

V_PPH2

V_PPH1

[3.3V VPP]

VPP

V_IL

WRITE or ERASE (block)

address asserted, and

WRITE data or ERASE

CONFIRM issued

WRITE or ERASE

executed, status register

checked for completion

Command for next

operation issued

WRITE SETUP or

ERASE SETUP input

DON’T CARE

TIMING PARAMETERS

Commercial Temperature (0ºC ≤ T_A≤ +70ºC)

Extended Temperature (-40ºC ≤ T_A≤ +85ºC)

-9/-9 ET

SYMBOL

MIN

90

20

50

0

MAX UNITS

SYMBOL

MIN

MAX UNITS

t

WC

ns

VPS2

100

1,000

100

2

ns

µs

ms

ns

t

CPH

RS

t

CP

RHS

t

AS

WED1

t

AH

WED2

100

500

200

0

t

DS

50

0

WED3

t

DH

WED4

t

WS

0

WB

t

WH

0

VPH

t

VPS1

200

RHH

0

NOTE: 1. Address inputs are “Don’t Care” but must be held stable.

2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit.

3. Either RP# at VHH or WP# HIGH unlocks the boot block.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

26

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

40-PIN PLASTIC TSOP I

(10mm x 20mm)

.795 (20.20)

.780 (19.80)

.727 (18.47)

.721 (18.31)

.0197 (0.50)

TYP

.010 (0.25)

1

40

PIN #1 INDEX

.397 (10.08)

.391 (9.93)

.010 (0.25)

.006 (0.15)

20

21

.010 (0.25)

.004 (0.10)

.007 (0.18)

.005 (0.13)

GAGE

PLANE

.047 (1.20)

MAX

SEE DETAIL A

.008 (0.20)

.002 (0.05)

.024 (0.60)

.016 (0.40)

.0315 (0.80)

DETAIL A

MAX

NOTE: 1. All dimensions in inches (millimeters)

or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

27

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

48-PIN PLASTIC TSOP I

(12mm x 20mm)

.795 (20.20)

.780 (19.80)

.727 (18.47)

.721 (18.31)

.0197 (0.50)

TYP

.010 (0.25)

48

1

PIN #1 INDEX

.475 (12.07)

.469 (11.91)

.010 (0.25)

.006 (0.15)

24

25

.010 (0.25)

.004 (0.10)

.007 (0.18)

.005 (0.12)

SEE DETAIL A

GAGE

PLANE

.047 (1.20) MAX

.008 (0.20)

.002 (0.05)

.024 (0.60)

.016 (0.40)

.0315 (0.80)

DETAIL A

MAX

MIN

NOTE: 1. All dimensions in inches (millimeters)

or typical where noted.

2. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

28

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

1

44-PINPLASTICSOP

(600 mil)

1.113 (28.27)

1.107 (28.12)

.007 (0.18)

.020 (0.50)

.005 (0.13)

.050 (1.27)

TYP

.015 (0.38)

.643 (16.34)

.620 (15.74)

.499 (12.68)

.493 (12.52)

PIN #1 INDEX

.030 (0.76)

SEE DETAIL A

.004 (0.10)

.016 (0.40)

.010 (0.25)

.106 (2.70) MAX

GAGE PLANE

.010 (0.25)

.0315 (0.80)

DETAIL A

(ROTATED 90 CW)

.066 (1.72)

NOTE: 1. Notrecommendedfornewdesigns.

MAX

MIN

2. All dimensions in inches (millimeters)

or typical where noted.

3. Package width and length do not include mold protrusion; allowable mold protrusion is .01” per side.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail:prodmktg@micron.com,Internet:http://www.micron.com,CustomerCommentLine:800-932-4992

The Micron logo and the M logo are trademarks of Micron Technology, Inc.

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

29

8Mb

SMART 3 BOOT BLOCK FLASH MEMORY

REVISION HISTORY

Rev. 3, Pub. 10/01 ................................................................................................................................................... 10/01

• Updated input capacitance spec

• Changed access time to 90ns

Rev. 2 ......................................................................................................................................................................................... 3/01

• Changed to 0.18µm process

• 12V V^PPno longer supported

• 10V ≤ V^HH≤ 12V

• VOH ≤ VCC - 0.2V

t

• RWH changed to 1µs from 800ns

t

• AH changed to 10ns from 0ns

• AC test output load CL changed to 50pF

• Typical main BLOCK ERASE time changed to 1.5s from 1s

• Typical main BLOCK WRITE time (byte mode) changed to 1s from 0.5s

• Typical main BLOCK WRITE time (word mode) changed to 1s from 0.5s

• MT28F800B3 only available in WG and SG packages

• MT28F008B3 only available in VG package

• Added 80ns access time for commercial and extended temperature ranges

8MbSmart3BootBlockFlashMemory

Q10_3.p65 – Rev. 3, Pub. 10/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

30


型号：	MT28F800B3WG-9T
厂家：	MICRON TECHNOLOGY
描述：	FLASH MEMORY FL灰内存内存集成电路光电二极管
文件：	总30页 (文件大小：413K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT28F800B3WG-9T [MICRON]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E