MT36LSDT25672G-13E [MICRON]
Synchronous DRAM Module;
| 型号： | MT36LSDT25672G-13E |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | Synchronous DRAM Module 动态存储器 |
| 文件： | 总30页 (文件大小：1002K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Fe a t u re s
Syn ch ro n o u s DRAM Mo d u le
MT36LSDT12872 – 1GB
MT36LSDT25672 – 2GB
For the latest data sheet, refer to Micron’s Web site: www.micron.com/products/modules
Fig u re 1:
168-Pin DIMM (MO-161)
Fe a t u re s
• 168-pin, dual in-line memory module (DIMM)
• PC100- and PC133-compliant
Standard 1.70in. (43.18mm)
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• Utilizes 125 MHz and 133 MHz SDRAM
components
• Supports ECC error detection and correction
• 1GB (128 Meg x 72) and 2GB (256 Meg x 72)
• Single +3.3V power supply
Low-Profile 1.20in. (30.48mm)
• Fully synchronous; all signals registered on positive
edge of PLL clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
• Auto refresh mode
• Self refresh mode: 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Serial presence-detect (SPD)
Op t io n s
• Package
168-pin DIMM (standard)
168-pin DIMM (lead-free)
• Frequency/ CAS Latency2
133 MHz/ CL = 2
Ma rkin g
G
1
Y
-13E
-133
• Gold edge contacts
133 MHz/ CL = 3
• PCB
Ta b le 1:
Tim in g Pa ra m e t e rs
Standard 1.70in (43.18mm)
See note on page 2
CL = CAS (READ) latency
Low-Profile 1.20in. (30.48mm) See note on page 2
Acce ss Tim e
Mo d u le
Ma rkin g
Se t u p
Ho ld
Tim e
Notes: 1. Contact Micron for product availability.
2. Registered mode adds one clock cycle to CL.
Clo ck
CL = 2 CL = 3 Tim e
-13E
-133
133 MHz
133 MHz
5.4ns
–
–
1.5
1.5
0.8
0.8
5.4ns
Ta b le 2:
Ad d re ss Ta b le
Pa ra m e t e r
1GB
2GB
8K
8K
Refresh Count
Device Banks
4 (BA0, BA1)
4 (BA0, BA1)
256Mb (64 Meg x 4)
8K (A0–A12)
512Mb (128 Meg x 4)
8K (A0–A12)
Device Configuration
Row Addressing
2K (A0–A9, A11)
4K (A0–A9, A11, A12)
2 (S0#, S2#; S1#, S3#)
Column Addressing
Module Ranks
2 (S0#, S2#; S1#, S3#)
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
1
Products and specifications discussed herein are subject to change by Micron without notice.
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Fe a t u re s
Ta b le 3:
Pa rt Nu m b e rs
Pa rt Nu m b e r
Mo d u le De n sit y
Co n fig u ra t io n
Syst e m Bu s Sp e e d
1GB
1GB
1GB
1GB
2GB
2GB
2GB
2GB
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
MT36LSDT12872G-13E__
MT36LSDT12872Y-13E__
MT36LSDT12872G-133__
MT36LSDT12872Y-133__
MT36LSDT25672G-13E__
MT36LSDT25672Y-13E__
MT36LSDT25672G-133__
MT36LSDT25672Y-133__
Note:
The designators for component and PCB revision are the last two characters of each part
number. Consult factory for current revision codes. Example: MT36LSDT12872G-133B1.
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Pin Assig n m e n t s a n d De scrip t io n s
Pin Assig n m e n t s a n d De scrip t io n s
Ta b le 4: Pin Assig n m e n t
168-Pin DIMM Fro n t
168-Pin DIMM Ba ck
Pin Sym b o l Pin Sym b o l Pin Sym b o l Pin Sym b o l Pin Sym b o l Pin Sym b o l Pin Sym b o l Pin Sym b o l
1
2
VSS
DQ0
DQ1
DQ2
DQ3
VDD
22
23
24
25
26
27
CB1
VSS
43
44
45
VSS
NC
S2#
64
65
66
VSS
DQ21
DQ22
DQ23
VSS
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
VSS
106
107
108
109
110
111
CB5
VSS
127
128
129
VSS
CKE0
S3#
148
149
150
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ53
DQ54
DQ55
VSS
3
NC
NC
4
NC
46 DQMB2 67
47 DQMB3 68
NC
130 DQMB6 151
131 DQMB7 152
5
VDD
WE#
VDD
CAS#
6
48
NC
VDD
NC
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DQ24
DQ25
DQ26
DQ27
VDD
132
NC
VDD
NC
153
154
155
156
157
158
159
DQ56
DQ57
DQ58
DQ59
VDD
7
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
28 DQMB0 49
29 DQMB1 50
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
112 DQMB4 133
113 DQMB5 134
8
9
30
31
32
33
34
35
36
37
38
39
40
41
42
S0#
NC
VSS
A0
51
52
53
54
55
56
57
58
59
60
61
62
63
NC
114
115
116
117
118
119
120
121
122
123
124
125
126
S1#
RAS#
VSS
A1
135
136
137
138
NC
10
11
12
13
14
15
16
17
18
19
20
21
CB2
CB6
CB7
VSS
CB3
DQ28
DQ29
DQ30
DQ31
VSS
DQ60
DQ61
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
A2
DQ16
DQ17
DQ18
DQ19
VDD
DQ20
NC
DQ41
DQ42
DQ43
A3
139 DQ48 160 DQ62
140 DQ49 161 DQ63
A4
A5
A6
A7
141 DQ50
142 DQ51
162
163
164
165
166
167
VSS
CK3
NC
A8
CK2
100 DQ44
101 DQ45
A9
A10
BA1
VDD
VDD
CK0
NC
BA0
A11
VDD
CK1
A12
143
VDD
NC
102
VDD
144 DQ52
SA0
SA1
SA2
VDD
DQ14
DQ15
CB0
SDA
103 DQ46
104 DQ47
145
146
147
NC
NC
NC
SCL
CKE1
VDD
105
CB4
REGE 168
Fig u re 2:
168-Pin DIMM Pin Lo ca t io n s
Standard PCB
Front View
Low Profile PCB
Front View
U6
U7
U8
U9
U1
U2
U3
U4
U5
U12
U1
U2
U4
U5
U7
U9
U3
U6
U8
U11
U10
U12
U10
U11
U14
U14
PIN 41
PIN 84
PIN 41
PIN 84
PIN 1
PIN 1
Back View
Back View
U20
U21
U22
U23
U15
U16
U17
U18
U19
U16
U17
U18
U20
U21
U22
U15
U19
U23
U24
U24
PIN 85
PIN 168
PIN125
PIN 168
PIN 85
PIN125
Indicates a VDD or VDDQ pin
Indicates a VSS pin
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
3
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Pin Assig n m e n t s a n d De scrip t io n s
Ta b le 5:
Pin De scrip t io n s
Pin numbers may not correlate with symbol order; refer to Table 4 on page 3 for more information
Pin Nu m b e rs
Sym b o l
Typ e
De scrip t io n
27, 111, 115
42, 79, 125, 163
128
RAS#, CAS#, WE# Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
CK0–CK3
CKE0
Input
Input
Clock: CK0 is distributed through an on-board PLL to all
devices. CK1–CK3 are terminated.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the
CK0 signal. Deactivating the clock provides POWER-DOWN
and SELF REFRESH operation (all device banks idle) or CLOCK
SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-down and
self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CK,
are disabled during power-down and self refresh modes,
providing low standby power.
30, 45, 114, 129
S0#–S3#
Input
Input
Chip select: S# enable (registered LOW) and disable (registered
HIGH) the command decoder. All commands are masked when
S# are registered HIGH. S# are considered part of the
command code.
28, 29, 46, 47, 112, 113, 130, DQMB0–DQMB7
131
Input/Output mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
39, 122
BA0, BA1
A0–A12
Input
Input
Bank address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
33–38, 117–121, 123, 126
Address inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.
83
165–167
147
SCL
SA0–SA2
REGE
Input
Input
Input
Serial clock for presence-detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect address inputs: These pins are used to
configure the presence-detect device.
Register enable: REGE permits the DIMM to operate in
“buffered” mode (LOW) or “registered” mode (HIGH).
2–5, 7–11, 13–17, 19–20,
55–58, 60, 65–67, 69–72,
74–77, 86–89, 91–95, 97–101,
103–104, 139–142, 144,
DQ0–DQ63
Input/
Output
Data I/Os: Data bus.
149–151, 153–156, 158–161
21, 22, 52, 53, 105, 106, 136,
137
CB0–CB7
SDA
Input/
Output
Check bits.
82
Input/
Output
Serial presence-detect data: SDA is a bidirectional pin used to
transfer addresses and data into and data out of the presence-
detect portion of the module.
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
4
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Fu n ct io n a l Blo ck Dia g ra m
Ta b le 5:
Pin De scrip t io n s (Co n t in u e d )
Pin numbers may not correlate with symbol order; refer to Table 4 on page 3 for more information
Pin Nu m b e rs
Sym b o l
Typ e
De scrip t io n
Power supply: +3.3V ±0.3V.
6, 18, 26, 40, 41, 49, 59, 73, 84,
90, 102, 110, 124, 133, 143,
157, 168
VDD
Supply
1, 12, 23, 32, 43, 54, 64, 68, 78,
85, 96, 107, 116, 127, 138, 148,
152, 162
VSS
NC
Supply
–
Ground.
24, 25, 31, 44, 48 50, 51 61, 62,
63, 80, 81, 108, 109, 132, 134,
135, 145, 146, 164
Not connected: Listed pins are not connected on these
modules.
Fu n ct io n a l Blo ck Dia g ra m
All resistor values are 10Ω unless otherwise specified.
‘t’ indicates top portion of stacked SDRAM. ‘b’ indicates bottom portion of stacked
SDRAM.
Per industry standard, Micron modules utilize various component speed grades, as ref-
erenced in the module part number guide at www.micron.com/ support/ number-
ing.html.
Standard modules use the following SDRAM devices: MT48LC64M4A2TG (1GB);
MT48LC128M4A2TG (2GB). Lead-free modules use the following SDRAM devices:
MT48LC64M4A2P (1GB); MT48LC128M4A2P (2GB).
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
5
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Fu n ct io n a l Blo ck Dia g ra m
Fig u re 3:
Fu n ct io n a l Blo ck Dia g ra m
RS0#
RS1#
RDQMB0
RDQMB4
DQM CS#
DQM CS#
DQ
DQ U1b
DQ
DQM CS#
DQ
DQM CS#
DQ
DQ0
DQ1
DQ2
DQ3
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
U1t
DQ
DQ
DQ
DQ
DQ
DQ
U23t
U23b
DQ
DQM CS#
DQ
DQM CS#
DQ
DQ U2b
DQ
DQM CS#
DQ
DQM CS#
DQ
DQ4
DQ5
DQ6
DQ7
DQ36
DQ37
DQ38
DQ39
DQ
DQ
DQ
U2t
DQ
DQ
DQ
DQ
DQ
DQ
U22t
U22b
DQ
RDQMB1
RDQMB5
DQM CS#
DQ
DQM CS#
DQ
DQ U3b
DQ
DQM CS#
DQ
DQM CS#
DQ
DQ8
DQ9
DQ10
DQ11
DQ40
DQ41
DQ42
DQ43
DQ
DQ
DQ
U3t
DQ
DQ
DQ
DQ
DQ
DQ
U21t
U21b
DQ
DQM CS#
DQ
DQ U4b
DQ
DQM CS#
DQ
DQM CS#
DQ
DQM CS#
DQ
DQ12
DQ13
DQ14
DQ15
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
U4t
DQ
DQ
DQ
DQ
DQ
DQ
U20b
U20t
DQ
DQM CS#
DQ
DQM CS#
DQ
DQ U5b
DQ
DQM
DQM
DQ
DQ U19b
DQ
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U5t
U19t
CS#
DQ
DQ
CS#
RS2#
RS3#
RDQMB2
RDQMB6
DQM CS#
DQ
DQM CS#
DQ
DQ U6b
DQ
DQM CS#
DQ
DQ U18b
DQ
DQM CS#
DQ
DQ16
DQ17
DQ18
DQ19
DQ48
DQ49
DQ50
DQ51
DQ
DQ
DQ
U6t
U18t
DQ
DQ
DQ
DQ
DQ
DQM CS#
DQ
DQM CS#
DQ
DQ U7b
DQ
DQM CS#
DQ
DQ U17b
DQ
DQM CS#
DQ
DQ20
DQ21
DQ22
DQ23
DQ52
DQ53
DQ54
DQ55
DQ
DQ
DQ
U7t
U17t
DQ
DQ
DQ
DQ
DQ
RDQMB3
RDQMB7
DQM CS#
DQ
DQM CS#
DQ
DQ U8b
DQ
DQM CS#
DQ
DQ U16b
DQ
DQM CS#
DQ
DQ24
DQ25
DQ26
DQ27
DQ56
DQ57
DQ58
DQ59
DQ
DQ
DQ
U8t
U16t
DQ
DQ
DQ
DQ
DQ
DQM CS#
DQ
DQM CS#
DQ
DQ U9b
DQ
DQM CS#
DQ
DQ U15b
DQ
DQM CS#
DQ
DQ28
DQ29
DQ30
DQ31
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
U9t
U15t
DQ
DQ
DQ
DQ
DQ
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
REGISTER x 3
U10, U11, U24
SPD
U14
U12
PLL
RAS#
CAS#
R
E
G
I
RRAS#: SDRAMs
RCAS#: SDRAMs
RWE#: SDRAMs
RCKE0: SDRAMs
RCKE1: SDRAMs
RA0-RA12: SDRAMs
SCL
WP
SDA
CK0
A0 A1 A2
WE#
SA0 SA1 SA2
12pF
CKE0
CKE0
CKE1
S
T
E
R
S
A0-A12
BA0,BA1
S0#, S2#
S1#, S3#
VDD
VSS
SDRAMs
SDRAMs
CK1-CK3
RBA0, RBA1: SDRAMs
12pF
RS0#, RS2#: Module Rank0
RS1#, RS3#: Module Rank1
RDQMB0 - RDQMB7: SDRAMs
DQMB0 - DQMB7
10K
U41
VDD
REGE
CK0
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
6
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Ge n e ra l De scrip t io n
Ge n e ra l De scrip t io n
The MT36LSDT12872 and MT36LSDT25672 are high-speed CMOS, dynamic random-
access, 1GB and 2GB memory modules organized in x72 (ECC) configurations. SDRAM
modules use internally configured quad-bank SDRAM devices with a synchronous inter-
face (all signals are registered on the positive edge of clock signal CK).
Read and write accesses to SDRAM modules are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1
select the device bank; A0–A12, select the device row). The address bits registered coinci-
dent with the READ or WRITE command are used to select the starting column location
for the burst access.
SDRAM modules provide for programmable read or write burst lengths of 1, 2, 4, or 8
locations, or full page, with a burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
SDRAM modules use an internal pipelined architecture to achieve high-speed opera-
tion. Precharging one device bank while accessing one of the other three device banks
will hide the PRECHARGE cycles and provide seamless, high-speed, random-access
operation.
SDRAM modules are designed to operate in 3.3V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving, power-down mode. All inputs and
outputs are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic column-
address generation, the ability to interleave between device banks in order to hide pre-
charge time, and the capability to randomly change column addresses on each clock
cycle during a burst access. For more inform ation regarding SDRAM operation, refer to
the 256Mb or 512Mb SDRAM component data sheets.
PLL a n d Re g ist e r Op e ra t io n
These modules can be operated in either registered mode (REGE pin HIGH), where the
control/ address input signals are latched in the register on one rising clock edge and
sent to the SDRAM devices on the following rising clock edge (data access is delayed by
one clock), or in buffered mode (REGE pin LOW) where the input signals pass through
the register/ buffer to the SDRAM devices on the same clock.
A phase-lock loop (PLL) on the modules is used to redrive the clock to the SDRAM
devices to minimize system clock loading. (CK0 is connected to the PLL, and CK1, CK2,
and CK3 are terminated.)
Se ria l Pre se n ce -De t e ct Op e ra t io n
These modules incorporate serial presence-detect (SPD). The SPD function is imple-
mented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes.
The first 128 bytes can be programmed by Micron to identify the module type and vari-
ous SDRAM organizations and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/ WRITE operations between the
2
master (system logic) and the slave EEPROM device (DIMM) occur via a standard I C
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/ EEPROM addresses. Write protect (WP) is tied to ground on
the module, permanently disabling hardware write protect.
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
7
©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
In it ia liza t io n
In it ia liza t io n
SDRAMs must be powered up and initialized in a predefined manner. Operational pro-
cedures other than those specified may result in undefined operation. Once power is
applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is
defined as a signal cycling within timing constraints specified for the clock pin), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands should be
applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All device
banks must then be precharged, thereby placing the device in the all device banks idle
state.
Once in the idle state, two auto refresh cycles must be performed. After the auto refresh
cycles are complete, the SDRAM is ready for mode register programming. Because the
mode register will power up in an unknown state, it should be loaded prior to applying
any operational command.
Mo d e Re g ist e r De fin it io n
The mode register is used to define the specific mode of operation of the SDRAM. This
definition includes the selection of a burst length, a burst type, a CAS latency, an operat-
ing mode and a write burst mode, as shown in Figure 4 on page 9. The mode register is
programmed via the LOAD MODE REGISTER command and will retain the stored infor-
mation until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst
(sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the oper-
ating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future
use. Address A12 (M12) is undefined but should be driven LOW during loading of the
mode register.
The mode register must be loaded when all device banks are idle, and the controller
must wait the specified time before initiating the subsequent operation. Violating either
of these requirements will result in unspecified operation.
Bu rst Le n g t h
Read and write accesses to the SDRAM are burst oriented, with the burst length being
programmable, as shown in Figure 4 on page 9. The burst length determines the maxi-
mum number of column locations that can be accessed for a given READ or WRITE
command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and
the interleaved burst types, and a full-page burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST TERMINATE command to gener-
ate arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached, as shown in
Table 6 on page 10. The block is uniquely selected by A1–Ai when BL = 2; A2–Ai when
BL = 4; and by A3–Ai when BL = 8. See Note 8 of Table 6 on page 10 for Ai values. The
remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if the boundary is reached, as
shown in Table 6 on page 10.
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©2002 Micron Technology, Inc. All rights reserved.
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Mo d e Re g ist e r De fin it io n
Fig u re 4:
Mo d e Re g ist e r De fin it io n Dia g ra m
A12 A11
A8
A6 A5 A4
A1
Address Bus
A10
A7
A3 A2
A0
A9
12
11
9
8
6
5
4
1
10
7
3
2
0
Mode Register (Mx)
Reserved
WB Op Mode
CAS Latency
BT
Burst Length
Program
M12, M11, M10 = “0, 0,0”
to ensure compatibility
with future devices.
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Burst Type
M3
0
Sequential
Interleaved
1
CAS Latency
M6 M5 M4
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
Reserved
Reserved
Reserved
Reserved
M8
M7
0
M6-M0
Defined
-
Operating Mode
0
-
Standard Operation
All other states reserved
-
Write Burst Mode
M9
0
1
Programmed Burst Length
Single Location Access
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9
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Mo d e Re g ist e r De fin it io n
Ta b le 6: Bu rst De fin it io n Ta b le
Ord e r o f Acce sse s Wit h in a Bu rst
St a rt in g Co lu m n
Bu rst Le n g t h
Ad d re ss
Typ e = Se q u e n t ia l
Typ e = In t e rle a ve d
A0
0
2
0-1
1-0
0-1
1-0
1
A1
0
0
A0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
4
1
1
0
1
1
A2
0
A1
0
A0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not supported
0
0
1
0
1
0
0
1
1
8
1
0
0
1
0
1
1
1
0
1
1
1
Full Page
(y)
n = i
Cn, Cn+1, Cn+2, Cn+3,
Cn+4..., ...Cn-1, Cn...
(location 0-y)
Notes: 1. For full-page accesses: y = 2,048 (1GB); y= 4,096 (2GB).
2. For BL = 2, i will select the block of two burst; A0 selects the starting column within the
block.
3. For BL = 4, i will select the block of four burst; A0–A1 select the starting column within the
block.
4. For BL = 8, i will select the block of eight burst; A0–A2 select the starting column within
the block.
5. For a full-page burst, the full row is selected and i will select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the follow-
ing access wraps within the block.
7. For BL = 1, i will select the unique column to be accessed, and mode register bit M3 is
ignored.
8. Ai = A0–A9, A11 for 1GB;
Ai = A0–A9, A11, A12 for 2GB.
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10
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Mo d e Re g ist e r De fin it io n
Fig u re 5:
CAS La t e n cy Dia g ra m
T0
T1
T2
T3
CLK
COMMAND
READ
NOP
t
NOP
t
LZ
OH
DOUT
DQ
t
AC
CAS latency = 2
T0
T1
T2
T3
T4
CLK
COMMAND
READ
NOP
NOP
NOP
t
t
LZ
OH
DOUT
DQ
t
AC
CAS latency = 3
DON’T CARE
UNDEFINED
Bu rst Typ e
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type
and the starting column address, as shown in Table 6 on page 10.
CAS La t e n cy
The CAS latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first piece of output data. The latency can be set to two
or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQ will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a read command is registered at T0
and the latency is programmed to two clocks, the DQ will start driving after T1 and the
data will be valid by T2, as shown in the Figure 5 on page 11. Table 7 on page 12, indi-
cates the operating frequencies at which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Mo d e Re g ist e r De fin it io n
Op e ra t in g Mo d e
Writ e Bu rst Mo d e
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use and/ or test modes. The pro-
grammed burst length applies to both read and write bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
When M9 = 0, the burst length programmed via M0–M2 applies to both read and write
bursts; when M9 = 1, the programmed burst length applies to read bursts, but write
accesses are single-location (non burst) accesses.
Ta b le 7: CAS La t e n cy Ta b le
Registered mode adds one clock cycle to CAS latency
Allo w a b le Op e ra t in g Clo ck Fre q u e n cy (MHz)
Sp e e d
CAS La t e n cy = 2
CAS La t e n cy = 3
-13E
-133
≤ 133
≤ 100
≤ 143
≤ 133
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12
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Co m m a n d s
Co m m a n d s
Table 8 provides a quick reference of available commands. This is followed by a written
description of each command. For a more detailed description of commands and opera-
tions refer to the 256Mb or 512Mb SDRAM component data sheets.
Ta b le 8:
SDRAM Co m m a n d a n d DQMB Op e ra t io n Tru t h Ta b le
CKE is HIGH for all commands shown except Self Refresh
Na m e (Fu n ct io n )
CS# RAS# CAS# WE# DQMB
ADDR
DQs No t e s
H
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
X
X
X
COMMAND INHIBIT (NOP)
X
NO OPERATION (NOP)
X
Bank/Row
Bank/Col
X
X
1
2
2
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
H
H
H
L
L/H7
L/H7
X
L
Bank/Col Valid
H
H
L
L
X
Code
X
Active
L
X
X
X
3
PRECHARGE (Deactivate row in bank or banks)
L
H
X
4, 5
AUTO REFRESH or SELF REFRESH (Enter self refresh
mode)
L
–
–
L
–
–
L
–
–
L
–
–
X
L
Op-Code
X
6
7
7
LOAD MODE REGISTER
–
–
Active
High-Z
Write Enable/Output Enable
Write Inhibit/Output High-Z
H
Notes: 1. A0–A12 provide device row address. BA0, BA1 determine which device bank is made
active.
2. A0–A9, A11 (1GB) or 0–A9, A11, A12 (2GB) provide device column address; A10 HIGH
enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto pre-
charge feature; BA0, BA1 determine which device bank is being read from or written to.
3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: both
device banks are precharged and BA0, BA1 are “Don’t Care.”
4. This command is Auto Refresh if CKE is HIGH, Self Refresh if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
except for CKE.
6. A0–A12 define the op-code written to the Mode Register, and should be driven low.
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
delay).
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Ab so lu t e Ma xim u m Ra t in g s
Ab so lu t e Ma xim u m Ra t in g s
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
Fig u re 6:
Pa ra m e t e r
Ab so lu t e Ma xim u m DC Ra t in g s
Min
Ma x
Un it s
-1
-1
+4.6
+4.6
+65
V
V
Voltage on VDD supply relative to Vss
Voltage on inputs, NC or I/O pins relative to Vss
Operating temperature TOPR (commercial - ambient)
Storage temperature (plastic)
0
°C
°C
-55
+150
DC Op e ra t in g Sp e cifica t io n s
Ta b le 9:
DC Ele ct rica l Ch a ra ct e rist ics a n d Op e ra t in g Co n d it io n s
Notes: 1, 5, 6; notes appear on page 19; VDD = VDDQ = +3.3V ±0.3V
Pa ra m e t e r/Co n d it io n
Sym b o l
Min
Ma x
Un it s No t e s
VDD, VDDQ
VIH
3
2
3.6
V
Supply voltage
VDD + 0.3
0.8
V
V
22
22
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
VIL
-0.3
Input leakage current: Any input: 0V ≤ VIN ≤ VDD
(All other pins not under test = 0V)
Command and
address, CKE
-20
20
II
µA
µA
33
33
-10
-5
10
5
CK, DQMB, S#
DQ
IOZ
Output leakage current: DQs are disabled;
0V ≤ VIN ≤ VDD
VOH
VOL
2.4
–
–
V
V
Output levels: Output high voltage (IOUT = -4mA)
Output low voltage (IOUT = 4mA)
0.4
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
DC Op e ra t in g Sp e cifica t io n s
Ta b le 10:
IDD Sp e cifica t io n s a n d Co n d it io n s – 1GB
SDRAM components only; Notes: 1, 5, 6, 11, 13; notes appear on page 19; VDD = VDDQ = +3.3V ±0.3V
Ma x
Pa ra m e t e r/Co n d it io n
Sym b o l
-13E
-133
Un it s
No t e s
a
IDD1
2,466
2,286
mA
3, 18, 19,
30
Operating current: Active mode; Burst = 2; READ or WRITE;
t
tRC = RC (MIN)
b
IDD2
72
72
mA
mA
mA
30
Standby current: Power-Down mode; All device banks idle;
CKE = LOW
a
IDD3
756
756
3, 12, 19,
30
Standby current: Active mode; CKE = HIGH; CS# = HIGH;
t
All device banks active after RCD met; No accesses in progress
a
IDD4
2,466
2,466
3, 18, 19,
30
Operating current: Burst mode; Continuous burst; READ or WRITE; All
device banks active
b
Auto refresh current
tRFC = RFC (MIN)
t
IDD5
10,260
126
9,720
126
mA
mA
3, 12
b
CS# = HIGH; CKE = HIGH
tRFC = 7.8125µs
IDD6
18, 19,
30, 31
b
IDD7
90
90
mA
4
Self refresh current: CKE ≤ 0.2V
Note:
a - Value calculated as one module rank in this operating condition, and all other module
ranks in power-down mode.
b - Value calculated reflects all module ranks in this operating condition.
Ta b le 11:
IDD Sp e cifica t io n s a n d Co n d it io n s – 2GB
SDRAM components only; Notes: 1, 5, 6, 11, 13; notes appear on page 19; VDD = VDDQ = +3.3V ±0.3V
Ma x
Pa ra m e t e r/Co n d it io n
Sym b o l
-13E
-133
Un it s
No t e s
a
IDD1
3,906
3,636
mA
3, 18,
19, 30
Operating current: Active mode; Burst = 2; READ or WRITE;
t
tRC = RC (MIN)
b
IDD2
72
72
mA
mA
mA
30
Standby current: Power-Down Mode; All device banks idle;
CKE = LOW
a
IDD3
1,476
3,276
1,476
3,276
3, 12,
19, 30
Standby current: Active Mode; CKE = HIGH; CS# = HIGH;
t
All device banks active after RCD met; No accesses in progress
a
IDD4
3, 18,
Operating current: Burst mode; Continuous burst; READ or WRITE; All
19, 30
device banks active
b
t
Auto refresh current
tRFC = RFC (MIN)
IDD5
14,400
360
13,320
360
mA
mA
3, 12
b
CS# = HIGH; CKE = HIGH
tRFC = 7.8125µs
IDD6
18, 19,
30, 31
b
IDD7
216
216
mA
4
Self refresh current: CKE ≤ 0.2V
Note:
a - Value calculated as one module rank in this operating condition, and all other module
ranks in power-down mode.
b - Value calculated reflects all module ranks in this operating condition.
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Ca p a cit a n ce
Ca p a cit a n ce
Ta b le 12: Ca p a cit a n ce
Note: 2; notes appear on page 19
Pa ra m e t e r
Sym b o l
Min
Typ
Ma x
Un it s
CI1
CI2
CI2
CI4
CIO
–
–
–
–
8
8
16
14
5
–
–
–
pF
pF
pF
pF
pF
Input capacitance: Address and command
Input capacitance: CKE
Input capacitance: CK
Input capacitance: S#, DQMB
Input/Output capacitance: DQ
–
12
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
AC Op e ra t in g Sp e cifica t io n s
AC Op e ra t in g Sp e cifica t io n s
Ta b le 13:
SDRAM Co m p o n e n t Ele ct rica l Ch a ra ct e rist ics a n d Re co m m e n d e d AC Op e ra t in g
Co n d it io n s
Notes: 5, 6, 8, 9, 11, 31; notes appear on page 19
AC Ch a ra ct e rist ic
-13E
-133
Pa ra m e t e r
Sym
Min
Ma x
Min
Ma x
Un it s
No t e s
tAC(3)
tAC(2)
tAH
tAS
tCH
5.4
5.4
5.4
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
27
Access time from CLK (pos. edge)
CL= 3
CL= 2
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
tCL
tCK(3)
tCK(2)
tCKH
tCKS
tCMH
tCMS
tDH
23
23
CL= 3
7.5
0.8
1.5
0.8
1.5
0.8
1.5
CL = 2
0.8
1.5
0.8
1.5
0.8
1.5
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
tDS
Data-in setup time
tHZ(3)
tHZ(2)
tLZ
5.4
5.4
5.4
6
10
10
Data-out High-Z time
CL = 3
CL = 2
1
3
1
3
Data-out Low-Z time
tOH
Data-out hold time (load)
Data-out hold time (no load)
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE command period
ACTIVE-to-READ or WRITE delay
Refresh period
tOHN
tRAS
tRC
tRCD
tREF
tRFC
tRP
1.8
37
60
15
1.8
44
66
20
28
29
120,000
64
120,000
64
66
15
14
66
20
15
Auto refresh period
PRECHARGE command period
tRRD
tT
ACTIVE bank a to ACTIVE bank b command
Transition time
0.3
1.2
0.3
1.2
7
1 CLK + 7ns
1 CLK + 7.5ns
24
25
20
WRITE recovery time
tWR
tXSR
14
67
15
75
Exit SELF REFRESH-to-ACTIVE command
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
AC Op e ra t in g Sp e cifica t io n s
Ta b le 14:
Pa ra m e t e r
AC Fu n ct io n a l Ch a ra ct e rist ics
Notes: 5, 6, 7, 8, 9, 11, 31; notes appear on page 19
Sym b o l
-13E
-133
Un it s
No t e s
tCCD
tCKED
tPED
tDQD
tDQM
tDQZ
tDWD
tDAL
tDPL
tBDL
tCDL
tRDL
1
1
1
0
0
2
0
4
2
1
1
2
2
3
2
1
1
1
0
0
2
0
5
2
1
1
2
2
3
2
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
17
14, 34
14, 34
17, 34
17, 34
17, 34
17, 34
15, 21, 34
16, 21, 34
17, 34
17, 34
16, 21, 34
26
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data High-Z during READs
WRITE command to input data delay
Data-in to ACTIVE command
Data-in to PRECHARGE command
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
LOAD MODE REGISTER command to ACTIVE or REFRESH command
tMRD
tROH(3)
tROH(2)
17, 34
17, 34
Data-out to High-Z from PRECHARGE command
CL= 3
CL = 2
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©2002 Micron Technology, Inc. All rights reserved.
18
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
No t e s
No t e s
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD = VDDQ = +3.3V ±0.3V; f = 1 MHz, T = 25°C; pin under
A
test biased at 1.4V.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range is ensured; (0°C ≤ T ≤ 55°C).
A
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be pow-
ered up simultaneously. Vss and VSSQ must be at same potential.) The two AUTO
t
REFRESH command wake-ups should be repeated any time the REF refresh require-
ment is exceeded.
t
7. AC characteristics assume T = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
sit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
Q
50pF
t
10. HZ defines the time at which the output achieves the open circuit condition; it is not
t
a reference to VOH or VOL. The last valid data element will meet OH before going
High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3.0V, using a measurement reference
level of 1.5V. If the input transition time is longer than 1ns, then the timing is mea-
sured from VIL (MAX) and VIH (MIN) and no longer at the 1.5V midpoint. CLK should
always be referenced to crossover. Refer to Micron Technical Note TN-48-09.
12. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
t
14. Timing actually specified by CKS; clock(s) specified as a reference only at minimum
cycle rate.
t
t
15. Timing actually specified by WR + RP; clock(s) specified as a reference only at mini-
mum cycle rate.
t
16. Timing actually specified by WR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any
timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
t
21. Based on CK = 7.5ns for -133 and -13E.
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SD36C128_256x72G.fm - Rev. E 6/05 EN
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©2002 Micron Technology, Inc. All rights reserved.
19
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
No t e s
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for
a pulse width ≤ 3ns for all inputs except A12. VIH overshoot for pin A12 is limited to
VDDQ + 1V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one
third of the cycle rate.
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge
t
states (READ, WRITE, including WR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
t
24. Auto precharge mode only. The precharge timing budget ( RP) begins 7ns for -13E;
and 7.5ns for -133 after the first clock delay, after the last WRITE is executed.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
t
27. AC for -133/ -13E at CL = 3 with no load is 4.6ns and is guaranteed by design.
28. Parameter guaranteed by design.
t
t
29. For -133, CL = 3 and CK = 7.5ns; for -13E, CL = 2 and CK = 7.5ns.
t
30. CKE is HIGH during refresh com mand period RFC (MIN) else CKE is LOW. The IDD6
limit is actually a nominal value and does not result in a fail value.
31. Refer to component data sheet for timing waveforms.
t
32. The value for RAS used in -13E speed grade modules is calculated from
t
t
RC - RP = 45ns.
33. Leakage number reflects the worst case leakage possible through the module pin, not
what each memory device contributes.
34. This AC timing function will show an extra clock cycle when in registered mode.
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SD36C128_256x72G.fm - Rev. E 6/05 EN
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©2002 Micron Technology, Inc. All rights reserved.
20
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Tim in g Re q u ire m e n t s a n d Sw it ch in g Ch a ra ct e rist ics
Tim in g Re q u ire m e n t s a n d Sw it ch in g Ch a ra ct e rist ics
Ta b le 15:
Re g ist e r Tim in g Re q u ire m e n t s a n d Sw it ch in g Ch a ra ct e rist ics
0°C ≤ TA ≤ 55°C
VDD = +3.3V ±0.3V
Re g ist e r
Sym b o l
Pa ra m e t e r
Co n d it io n
Min
Ma x
Un it s
fclock
tpd1
Clock frequency
150
1.4
240
3.5
MHz
ns
Propagation delay, single rank
(CK to Output)
50pF to GND and
50 Ohms to Vtt
SSTL
bit pattern by
JESD82-2
tpd2
propagation delay, dual rank
(CK to output)
30pF to GND and
0.7
2.4
ns
50Ω to VTT
tw
tsu
th
Pulse duration
Setup time
Hold time
CK, HIGH or LOW
Data before CK HIGH
Data after CK HIGH
3.3
.75
.75
–
–
–
ns
ns
ns
Ta b le 16:
Pa ra m e t e r
PLL Clo ck Drive r Tim in g Re q u ire m e n t s An d Sw it ch in g Ch a ra ct e rist ics
0°C ≤ TA ≤ 55°C
VDD = +3.3V ±0.3V
Sym b o l
Min
Ma x
Un it s
No t e s
fCK
tDC
tJITCC
50
44
-75
-150
–
140
55
MHz
%
Operating clock frequency
Input duty cycle
75
ps
Cycle to cycle jitter
Static phase offset
SSC induced skew
t
∅
150
150
150
ps
tSSC
tSKO
ps
1, 2
–
ps
Output to output skew
Notes: 1. SSC = Spread Spectrum Clock. the use of SSC synthesizers on the system motherboard will
reduce EMI.
2. Skew is defined as the total clock skew between any two outputs and is therefore speci-
fied as a maximum only.
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SD36C128_256x72G.fm - Rev. E 6/05 EN
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©2002 Micron Technology, Inc. All rights reserved.
21
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Tim in g Re q u ire m e n t s a n d Sw it ch in g Ch a ra ct e rist ics
Fig u re 7:
Co m p o n e n t Ca se Te m p e ra t u re vs. Airflo w
100
90
80
70
60
50
40
30
20
Ambient Temperature = 25º C
Tmax- memory stress software
Tave- memory stress software
Tave- 3D gaming software
Minimum Air Flow
Air Flow (meters/sec)
Notes: 1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM)
across all modules when installed in a system.
2. The component case temperature measurements shown above are obtained experimen-
tally. The system used for experimental purposes is a dual-processor 600 MHz work station,
fully loaded with four MT36LSDT12872G modules. Case temperatures charted represent
worst-case component locations on modules installed in the internal slots of the system.
3. Temperature versus air speed data is obtained by performing experiments with the system
motherboard removed from its case and mounted in a Eiffel-type low air speed wind tun-
nel. Peripheral devices installed on the system motherboard for testing are the processor(s)
and video card, all other peripheral devices are mounted outside of the wind tunnel test
chamber.
4. The memory diagnostic software used for determining worst-case component tempera-
tures is a memory diagnostic software application developed for internal use by Micron
Technology, Inc.
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SD36C128_256x72G.fm - Rev. E 6/05 EN
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©2002 Micron Technology, Inc. All rights reserved.
22
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Se ria l Pre se n ce De t e ct
Se ria l Pre se n ce De t e ct
SPD Clo ck a n d Da t a Co n ve n t io n s
Data states on the SDA line can change only during SCL LOW. SDA state changes during
SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 8,
and Figure 9 on page 24).
SPD St a rt Co n d it io n
All commands are preceded by the start condition, which is a HIGH-to-LOW transition
of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any command until this condition
has been met.
SPD St o p Co n d it io n
SPD Ackn o w le d g e
All communications are terminated by a stop condition, which is a LOW-to-HIGH tran-
sition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device
into standby power mode.
Acknowledge is a software convention used to indicate successful data transfers. The
transmitting device, either master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Figure 10 on page 24).
The SPD device will always respond with an acknowledge after recognition of a start
condition and its slave address. If both the device and a WRITE operation have been
selected, the SPD device will respond with an acknowledge after the receipt of each sub-
sequent eight bit word. In the read mode the SPD device will transmit eight bits of data,
release the SDA line and monitor the line for an acknowledge. If an acknowledge is
detected and no stop condition is generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the slave will terminate further data
transmissions and await the stop condition to return to standby power mode.
Fig u re 8:
Da t a Va lid it y
SCL
SDA
Data stable
Data
Data stable
change
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©2002 Micron Technology, Inc. All rights reserved.
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1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Se ria l Pre se n ce De t e ct
Fig u re 9:
De fin it io n o f St a rt a n d St o p
SCL
SDA
Start
bit
Stop
bit
Fig u re 10: Ackn o w le d g e Re sp o n se Fro m Re ce ive r
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
Ta b le 17:
EEPROM De vice Se le ct Co d e
The most significant bit (b7) is sent first
De vice Typ e Id e n t ifie r
Ch ip En a b le
RW
b 0
Se le ct Co d e
b 7
b 6
b 5
b 4
b 3
b 2
b 1
1
0
0
1
1
1
0
0
SA2
SA2
SA1
SA1
SA0
SA0
RW
RW
Memory area select code (two arrays)
Protection register select code
Ta b le 18:
Mo d e
EEPROM Op e ra t in g Mo d e s
RW Bit
WC
BYTES
In it ia l Se q u e n ce
1
0
1
1
0
0
VIH or VIL
VIH or VIL
VIH or VIL
VIH or VIL
VIL
1
1
Current address read
Random address read
Start, device select, RW = 1
Start, device select, RW = 0, address
Restart, device select, RW = 1
≥ 1
1
Sequential read
Byte write
Similar to current or random address read
Start, device select, RW = 0
VIL
≤ 16
Page write
Start, device select, RW = 0
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SD36C128_256x72G.fm - Rev. E 6/05 EN
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©2002 Micron Technology, Inc. All rights reserved.
24
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Se ria l Pre se n ce De t e ct
Fig u re 11: SPD EEPROM Tim in g Dia g ra m
t
t
t
F
HIGH
R
t
LOW
SCL
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
SDA IN
t
t
t
DH
AA
BUF
SDA OUT
UNDEFINED
Ta b le 19:
Se ria l Pre se n ce -De t e ct EEPROM DC Op e ra t in g Co n d it io n s
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
Pa ra m e t e r/Co n d it io n
Sym b o l
Min
Ma x
Un it s
VDD
VIH
3
3.6
V
V
Supply voltage
VDD x 0.7 VDD + 0.5
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
VIL
-1
–
VDD x 0.3
V
VOL
0.4
10
10
30
3
V
Output low voltage: IOUT = 3mA
ILI
-10
-10
–
µA
µA
µA
mA
mA
Input leakage current: VIN = GND to VDD
Output leakage current: VOUT = GND to VDD
Standby current: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD
Power supply current: SCL clock frequency = 100 KHz
ILO
ICCS
ICC Write
ICC Read
–
–
1
Ta b le 20:
Se ria l Pre se n ce -De t e ct EEPROM AC Op e ra t in g Co n d it io n s
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
Pa ra m e t e r/Co n d it io n
Sym b o l
Min
Ma x
Un it s
No t e s
tAA
tBUF
tDH
0.2
1.3
0.9
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
1
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
200
tF
300
50
2
SDA and SCL fall time
tHD:DAT
tHD:STA
tHIGH
tI
tLOW
tR
fSCL
tSU:DAT
tSU:STA
0
Data-in hold time
0.6
0.6
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
1.3
0.3
2
3
SDA and SCL rise time
400
SCL clock frequency
100
0.6
Data-in setup time
Start condition setup time
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SD36C128_256x72G.fm - Rev. E 6/05 EN
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©2002 Micron Technology, Inc. All rights reserved.
25
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Se ria l Pre se n ce De t e ct
Ta b le 20:
Se ria l Pre se n ce -De t e ct EEPROM AC Op e ra t in g Co n d it io n s
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
Pa ra m e t e r/Co n d it io n
Sym b o l
Min
Ma x
Un it s
No t e s
tSU:STO
tWRC
0.6
µs
Stop condition setup time
WRITE cycle time
10
ms
4
Notes: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between
SCL=1 and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal erase/program cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to
pull-up resistor, and the EEPROM does not respond to its slave address.
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SD36C128_256x72G.fm - Rev. E 6/05 EN
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©2002 Micron Technology, Inc. All rights reserved.
26
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Se ria l Pre se n ce De t e ct
Ta b le 21:
Se ria l Pre se n ce -De t e ct Ma t rix
“1”/”0”: Serial data, “driven to HIGH”/”driven to LOW”; VDD = +3.3V ±0.3V
En t ry
(Ve rsio n )
Byt e De scrip t io n
MT36LSDT12872 MT36LSDT25672
0
1
2
3
4
5
6
7
8
9
128
256
80
08
04
0D
0B
02
48
00
01
80
08
04
0D
0C
02
48
00
01
Number of bytes used by Micron
Total number of SPD memory bytes
Memory type
SDRAM
13
Number of row addresses
Number of column addresses
Number of module ranks
Module data width
11 or 12
2
72
0
Module data width (continued)
Module voltage interface levels
LVTTL
t
7ns (-13E)
7.5ns (-133)
70
75
70
75
SDRAM cycle time, CK (CAS latency = 3)
t
10
11
12
13
14
15
5.4ns (-13E/-133)
54
02
82
04
04
01
54
02
82
04
04
01
SDRAM access from clock, AC (CAS latency = 3)
ECC
Module configuration type
Refresh rate/type
7.81µs/SELF
4
4
1
SDRAM width (primary SDRAM)
Error-checking SDRAM data width
Minimum clock delay from back-to-back random
column addresses,tCCD
16
17
18
19
20
21
22
23
1, 2, 4, 8, PAGE
8F
04
06
01
01
1F
0E
75
8F
04
06
01
01
1F
0E
75
Burst lengths supported
Number of banks on SDRAM device
CAS latencies supported
CS latency
4
2, 3
0
0
WE latency
-13E/-133
0E
SDRAM module attributes
SDRAM device attributes: General
t
7.5ns (-13E)
SDRAM cycle time, CK
(CAS latency = 2)
t
24
25
26
27
28
29
30
5.4ns (-13E)
54
00
00
54
00
00
SDRAM access from clock, AC
(CAS latency = 2)
t
–
–
SDRAM cycle time, CK
(CAS latency = 1)
t
SDRAM access from clock, AC
(CAS latency = 1)
t
15ns (-13E)
20ns (-133)
0F
14
0F
14
Minimum row precharge time, RP
t
14ns (-13E)
15ns (-133)
0E
0F
0E
0F
Minimum row active to row active, RRD
Minimum RAS# to CAS# delay, tRCD
15ns (-13E)
20ns (-133)
0F
14
0F
14
t
45ns (-13E)
44ns (-133)
2D
2C
2D
2C
Minimum RAS# pulse width, RAS (See note 1)
31
32
33
34
512MB / 1GB
1.5ns (-13E/-133)
0.8ns (-13E/-133)
1.5ns (-13E/-133)
80
15
08
15
01
15
08
15
Module rank density
t
t
Command and address setup time, AS, CMS
t
t
Command and address hold time, AH, CMH
t
Data signal input setup time, DS
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
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©2002 Micron Technology, Inc. All rights reserved.
27
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Se ria l Pre se n ce De t e ct
Ta b le 21:
Se ria l Pre se n ce -De t e ct Ma t rix (Co n t in u e d )
“1”/”0”: Serial data, “driven to HIGH”/”driven to LOW”; VDD = +3.3V ±0.3V
En t ry
(Ve rsio n )
Byt e De scrip t io n
MT36LSDT12872 MT36LSDT25672
Data signal input hold time, tDH
Reserved
35
0.8ns (-13E/-133)
08
00
08
00
36–40
41
t
66ns (-13E)
71ns (-133)
3C
42
3C
42
Device minimum active/auto-refresh time, RC
42–61
62
00
02
00
02
Reserved
REV. 2.0
SPD revision
63
-13E
-133
22
6E
A4
F0
Checksum for bytes 0–62
64
65–71
72
MICRON
2C
2C
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code (continued)
Manufacturing location
FF
01–09
FF
01–09
1–9
73–90
91
Variable Data
01–0C
Variable Data
01–0C
Module part number (ASCII)
PCB identification code
1–12
0
92
00
00
Identification code (continued)
Year of manufacture in BCD
Week of manufacture in BCD
Module serial number
93
Variable Data
Variable Data
Variable Data
–
Variable Data
Variable Data
Variable Data
–
94
95–98
99–125
126
Manufacturer-Specific data (RSVD)
System frequency
100 MHz
64
64
(-13E/-133)
127
8F
8F
SDRAM component and clock detail
t
t
Notes: 1. The value of RAS used for the -13E module is calculated from RC - tRP. Actual device spec-
ification value is 37ns.
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SD36C128_256x72G.fm - Rev. E 6/05 EN
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©2002 Micron Technology, Inc. All rights reserved.
28
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Mo d u le Dim e n sio n s
Mo d u le Dim e n sio n s
Fig u re 12: 168-Pin DIMM Dim e n sio n s – St a n d a rd PCB
0.320 (8.13)
MAX
FRONT VIEW
5.256 (133.50)
5.244 (133.20)
U6
U7
U8
U9
U1
U2
U3
U4
U5
0.079 (2.00) R
(2X)
1.705 (43.31)
1.695 (43.05)
U12
U10
U11
0.700 (17.78)
TYP.
0.118 (3.00)
(2X)
U14
0.118 (3.00) TYP.
0.054 (1.37)
0.046 (1.17)
0.250 (6.35) TYP.
PIN 1
0.039 (1.00) R(2X)
PIN 84
0.118 (3.00)
TYP.
0.040 (1.02)
TYP.
0.050 (1.27)
TYP.
4.550 (115.57)
BACK VIEW
U20
U21
U22
U23
U15
U16
U17
U18
U19
U24
0.128 (3.25)
0.118 (3.00)
(2X)
1.661 (42.18)
2.625 (66.68)
PIN 168
PIN 85
MAX
MIN
Note:All dimensions in inches (millimeters);
or typical where noted.
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SD36C128_256x72G.fm - Rev. E 6/05 EN
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©2002 Micron Technology, Inc. All rights reserved.
29
1GB, 2GB: (x72, ECC, DR) 168-Pin SDRAM RDIMM
Mo d u le Dim e n sio n s
Fig u re 13: 168-Pin DIMM Dim e n sio n s – Lo w -Pro file
0.254 (6.45)
MAX
FRONT VIEW
5.256 (133.50)
5.244 (133.20)
U12
0.079 (2.00) R
(2X)
U1
U2
U4
U5
U7
U9
U3
U6
U8
U11
1.206 (30.63)
1.194 (30.33)
0.118 (3.00)
(2X)
U10
0.700 (17.78)
U14
0.118 (3.00)
0.054 (1.37)
0.046 (1.17)
0.250 (6.35)
PIN 1
0.039 (1.00) R(2X)
PIN 84
0.040 (1.02)
0.050 (1.27)
0.118 (3.00)
4.550 (115.57)
BACK VIEW
U16
U17
U18
U20
U21
U22
U15
U19
U23
U24
0.128 (3.25)
0.118 (3.00)
(2X)
1.661 (42.18)
2.625 (66.68)
PIN 168
PIN 85
MAX
MIN
Note:All dimensions in inches (millimeters);
or typical where noted.
®
8000 S. Fe d e ra l Wa y, P.O. Bo x 6, Bo ise , ID 83707-0006, Te l: 208-368-3900
p ro d m kt g @m icro n .co m w w w .m icro n .co m Cu st o m e r Co m m e n t Lin e : 800-932-4992
Micro n , t h e M lo g o , a n d t h e Micro n lo g o a re t ra d e m a rks o f Micro n Te ch n o lo g y, In c.
All o t h e r t ra d e m a rks a re t h e p ro p e rt y o f t h e ir re sp e ct ive o w n e rs.
Th is d a t a sh e e t co n t a in s m in im u m a n d m a xim u m lim it s sp e cifie d o ve r t h e co m p le t e p o w e r su p p ly a n d t e m p e ra t u re ra n g e
fo r p ro d u ct io n d e vice s. Alt h o u g h co n sid e re d fin a l, t h e se sp e cifica t io n s a re su b je ct t o ch a n g e , a s fu rt h e r p ro d u ct
d e ve lo p m e n t a n d d a t a ch a ra ct e riza t io n so m e t im e s o ccu r.
PDF: 09005aef80b1835d/Source: 09005aef80b18348
SD36C128_256x72G.fm - Rev. E 6/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
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