MT47H64M8B6-25ELDTR [MICRON]

512Mb: x4, x8, x16 DDR2 SDRAM; 512MB ： X4，X8 ， X16 DDR2 SDRAM


型号：	MT47H64M8B6-25ELDTR
厂家：	MICRON TECHNOLOGY
描述：	512Mb: x4, x8, x16 DDR2 SDRAM 512MB ： X4，X8 ， X16 DDR2 SDRAM 动态存储器双倍数据速率
文件：	总133页 (文件大小：2131K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

512Mb: x4, x8, x16 DDR2 SDRAM

Features

DDR2 SDRAM

MT47H128M4 – 32 Meg x 4 x 4 banks

MT47H64M8 – 16 Meg x 8 x 4 banks

MT47H32M16 – 8 Meg x 16 x 4 banks

Options¹

Marking

Features

• Configuration

• V_DD= 1.8V ±±.1V, V_DDQ= 1.8V ±±.1V

• JEDEC-standard 1.8V I/O (SSTL_18-compatible)

• Differential data strobe (DQS, DQS#) option

• 4n-bit prefetch architecture

– 128 Meg x 4 (32 Meg x 4 x 4 banks)

– 64 Meg x 8 (16 Meg x 8 x 4 banks)

– 32 Meg x 16 (8 Meg x 16 x 4 banks)

• FBGA package (Pb-free) – x16

– 84-ball FBGA (8mm x 12.5mm) Rev. F, G

• FBGA package (Pb-free) – x4, x8

– 6±-ball FBGA (8mm x 1±mm) Rev. F, G

• FBGA package (lead solder) – x16

– 84-ball FBGA (8mm x 12.5mm) Rev. F, G

• FBGA package (lead solder) – x4, x8

– 6±-ball FBGA (8mm x 1±mm) Rev. F, G

• Timing – cycle time

– 1.875ns @ CL = 7 (DDR2-1±66)

– 2.5ns @ CL = 5 (DDR2-8±±)

– 2.5ns @ CL = 6 (DDR2-8±±)

– 3.±ns @ CL = 4 (DDR2-667)

– 3.±ns @ CL = 5 (DDR2-667)

– 3.75ns @ CL = 4 (DDR2-533)

• Self refresh

128M4

64M8

32M16

• Duplicate output strobe (RDQS) option for x8

• DLL to align DQ and DQS transitions with CK

• 4 internal banks for concurrent operation

• Programmable CAS latency (CL)

• Posted CAS additive latency (AL)

• WRITE latency = READ latency - 1 ^tCK

• Selectable burst lengths: 4 or 8

-187E

-25E

-25

-3E

-3

• Adjustable data-output drive strength

• 64ms, 8192-cycle refresh

• On-die termination (ODT)

• Industrial temperature (IT) option

• Automotive temperature (AT) option

• RoHS-compliant

-37E

– Standard

– Low-power

None

• Supports JEDEC clock jitter specification

• Operating temperature

– Commercial (±°C ≤ T_C≤ +85°C)

– Industrial (–4±°C ≤ T_C≤ +95°C;

–4±°C ≤ T_A≤ +85°C)

– Automotive (–4±°C ≤ T_C, T_A≤ +1±5°C)

• Revision

None

:F/:G

1. Not all options listed can be combined to

define an offered product. Use the Part

Catalog Search on www.micron.com for

product offerings and availability.

Note:

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512MbDDR2.pdf - Rev. T 2/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

512Mb: x4, x8, x16 DDR2 SDRAM

Features

Table 1: Key Timing Parameters

Data Rate (MT/s)

Speed Grade

CL = 3

400

CL = 4

533

CL = 5

800

667

n/a

CL = 6

800

n/a

CL = 7

1066

n/a

^tRC (ns)

-187E

-25E

-25

400

533

400

533

n/a

-3E

400

667

n/a

-3

400

533

n/a

-37E

400

533

n/a

Table 2: Addressing

Parameter

128 Meg x 4

32 Meg x 4 x 4 banks

64 Meg x 8

32 Meg x 16

Configuration

Refresh count

Row address

Bank address

Column address

16 Meg x 8 x 4 banks

8 Meg x 16 x 4 banks

A[13:0] (16K)

BA[1:0] (4)

A[13:0] (16K)

BA[1:0] (4)

A[9:0] (1K)

A[12:0] (8K)

BA[1:0] (4)

A[9:0] (1K)

A[11, 9:0] (2K)

Figure 1: 512Mb DDR2 Part Numbers

Example Part Number:

MT47H128M4HR-25E :G

MT47H

Configuration

Package

Speed

Revision

:F/:G Revision

Low power

Configuration

128 Meg x 4

64 Meg x 8

32 Meg x 16

128M4

64M8

32M16

IT Industrial temperature

AT Automotive temperature

Package

Pb-free

Speed Grade

-37E

-3

CK = 3.75ns, CL = 4

CK = 3ns, CL = 5

CK = 3ns, CL = 4

CK = 2.5ns, CL = 6

CK = 2.5ns, CL = 5

84-ball 8mm x 12.5mm FBGA

60-ball 8mm x 10mm FBGA

Lead Solder

-3E

-25

84-ball 8mm x 12.5mm FBGA

60-ball 8mm x 10mm FBGA

-25E

-187E

CK = 1.875ns, CL = 7

1. Not all speeds and configurations are available in all packages.

Note:

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16 DDR2 SDRAM

Features

FBGA Part Number System

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the

part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:

http://www.micron.com.

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512Mb: x4, x8, x16 DDR2 SDRAM

Features

Contents

State Diagram .................................................................................................................................................. 9

Functional Description ................................................................................................................................... 1±

Industrial Temperature ............................................................................................................................... 1±

Automotive Temperature ............................................................................................................................ 11

General Notes ............................................................................................................................................ 11

Functional Block Diagrams ............................................................................................................................. 12

Ball Assignments and Descriptions ................................................................................................................. 14

Packaging ...................................................................................................................................................... 18

Package Dimensions ................................................................................................................................... 18

FBGA Package Capacitance ......................................................................................................................... 2±

Electrical Specifications – Absolute Ratings ..................................................................................................... 21

Temperature and Thermal Impedance ........................................................................................................ 21

Electrical Specifications – I_DDParameters ........................................................................................................ 24

I_DDSpecifications and Conditions ............................................................................................................... 24

_DD7Conditions .......................................................................................................................................... 24

AC Timing Operating Specifications ................................................................................................................ 31

AC and DC Operating Conditions .................................................................................................................... 43

ODT DC Electrical Characteristics ................................................................................................................... 44

Input Electrical Characteristics and Operating Conditions ............................................................................... 45

Output Electrical Characteristics and Operating Conditions ............................................................................. 48

Output Driver Characteristics ......................................................................................................................... 5±

Power and Ground Clamp Characteristics ....................................................................................................... 54

AC Overshoot/Undershoot Specification ......................................................................................................... 55

Input Slew Rate Derating ................................................................................................................................ 57

Commands .................................................................................................................................................... 7±

Truth Tables ............................................................................................................................................... 7±

DESELECT ................................................................................................................................................. 74

NO OPERATION (NOP) ............................................................................................................................... 75

LOAD MODE (LM) ...................................................................................................................................... 75

ACTIVATE .................................................................................................................................................. 75

READ ......................................................................................................................................................... 75

WRITE ....................................................................................................................................................... 75

PRECHARGE .............................................................................................................................................. 76

REFRESH ................................................................................................................................................... 76

SELF REFRESH ........................................................................................................................................... 76

Mode Register (MR) ........................................................................................................................................ 76

Burst Length .............................................................................................................................................. 77

Burst Type .................................................................................................................................................. 78

Operating Mode ......................................................................................................................................... 78

DLL RESET ................................................................................................................................................. 78

Write Recovery ........................................................................................................................................... 79

Power-Down Mode ..................................................................................................................................... 79

CAS Latency (CL) ........................................................................................................................................ 8±

Extended Mode Register (EMR) ....................................................................................................................... 81

DLL Enable/Disable ................................................................................................................................... 82

Output Drive Strength ................................................................................................................................ 82

DQS# Enable/Disable ................................................................................................................................. 82

RDQS Enable/Disable ................................................................................................................................. 82

Output Enable/Disable ............................................................................................................................... 82

On-Die Termination (ODT) ......................................................................................................................... 83

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512Mb: x4, x8, x16 DDR2 SDRAM

Features

Off-Chip Driver (OCD) Impedance Calibration ............................................................................................ 83

Posted CAS Additive Latency (AL) ................................................................................................................ 83

Extended Mode Register 2 (EMR2) ................................................................................................................... 85

Extended Mode Register 3 (EMR3) ................................................................................................................... 86

Initialization .................................................................................................................................................. 87

ACTIVATE ...................................................................................................................................................... 9±

READ ............................................................................................................................................................. 92

READ with Precharge .................................................................................................................................. 96

READ with Auto Precharge .......................................................................................................................... 98

WRITE .......................................................................................................................................................... 1±3

PRECHARGE ................................................................................................................................................. 113

REFRESH ...................................................................................................................................................... 114

SELF REFRESH .............................................................................................................................................. 115

Power-Down Mode ........................................................................................................................................ 117

Precharge Power-Down Clock Frequency Change ........................................................................................... 124

Reset ............................................................................................................................................................. 125

CKE Low Anytime ...................................................................................................................................... 125

ODT Timing .................................................................................................................................................. 127

MRS Command to ODT Update Delay ........................................................................................................ 129

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512Mb: x4, x8, x16 DDR2 SDRAM

Features

List of Figures

Figure 1: 512Mb DDR2 Part Numbers ............................................................................................................... 2

Figure 2: Simplified State Diagram ................................................................................................................... 9

Figure 3: 128 Meg x 4 Functional Block Diagram ............................................................................................. 12

Figure 4: 64 Meg x 8 Functional Block Diagram ............................................................................................... 13

Figure 5: 32 Meg x 16 Functional Block Diagram ............................................................................................. 13

Figure 6: 6±-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 14

Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) ............................................................................... 15

Figure 8: 84-Ball FBGA (8mm x 12.5mm) – x16 ................................................................................................ 18

Figure 9: 6±-Ball FBGA (8mm x 1±mm) – x4, x8 ............................................................................................... 19

Figure 1±: Example Temperature Test Point Location ...................................................................................... 22

Figure 11: Single-Ended Input Signal Levels ................................................................................................... 45

Figure 12: Differential Input Signal Levels ...................................................................................................... 46

Figure 13: Differential Output Signal Levels .................................................................................................... 48

Figure 14: Output Slew Rate Load .................................................................................................................. 49

Figure 15: Full Strength Pull-Down Characteristics ......................................................................................... 5±

Figure 16: Full Strength Pull-Up Characteristics .............................................................................................. 51

Figure 17: Reduced Strength Pull-Down Characteristics .................................................................................. 52

Figure 18: Reduced Strength Pull-Up Characteristics ...................................................................................... 53

Figure 19: Input Clamp Characteristics .......................................................................................................... 54

Figure 2±: Overshoot ..................................................................................................................................... 55

Figure 21: Undershoot ................................................................................................................................... 55

Figure 22: Nominal Slew Rate for ^tIS ............................................................................................................... 6±

Figure 23: Tangent Line for ^tIS ........................................................................................................................ 6±

Figure 24: Nominal Slew Rate for ^tIH .............................................................................................................. 61

Figure 25: Tangent Line for ^tIH ....................................................................................................................... 61

Figure 26: Nominal Slew Rate for ^tDS ............................................................................................................. 66

Figure 27: Tangent Line for ^tDS ...................................................................................................................... 66

Figure 28: Nominal Slew Rate for ^tDH ............................................................................................................. 67

Figure 29: Tangent Line for ^tDH ..................................................................................................................... 67

Figure 3±: AC Input Test Signal Waveform Command/Address Balls ................................................................ 68

Figure 31: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ............................................ 68

Figure 32: AC Input Test Signal Waveform for Data with DQS (Single-Ended) ................................................... 69

Figure 33: AC Input Test Signal Waveform (Differential) .................................................................................. 69

Figure 34: MR Definition ............................................................................................................................... 77

Figure 35: CL ................................................................................................................................................. 8±

Figure 36: EMR Definition ............................................................................................................................. 81

Figure 37: READ Latency ............................................................................................................................... 84

Figure 38: WRITE Latency .............................................................................................................................. 84

Figure 39: EMR2 Definition ........................................................................................................................... 85

Figure 4±: EMR3 Definition ........................................................................................................................... 86

Figure 41: DDR2 Power-Up and Initialization ................................................................................................. 87

Figure 42: Example: Meeting ^tRRD (MIN) and ^tRCD (MIN) .............................................................................. 9±

Figure 43: Multibank Activate Restriction ....................................................................................................... 91

Figure 44: READ Latency ............................................................................................................................... 93

Figure 45: Consecutive READ Bursts .............................................................................................................. 94

Figure 46: Nonconsecutive READ Bursts ........................................................................................................ 95

Figure 47: READ Interrupted by READ ............................................................................................................ 96

Figure 48: READ-to-WRITE ............................................................................................................................ 96

Figure 49: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 97

Figure 5±: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 97

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512Mb: x4, x8, x16 DDR2 SDRAM

Features

Figure 51: Bank Read – Without Auto Precharge .............................................................................................. 99

Figure 52: Bank Read – with Auto Precharge .................................................................................................. 1±±

Figure 53: x4, x8 Data Output Timing – ^tDQSQ, ^tQH, and Data Valid Window .................................................. 1±1

Figure 54: x16 Data Output Timing – ^tDQSQ, ^tQH, and Data Valid Window ..................................................... 1±2

Figure 55: Data Output Timing – ^tAC and ^tDQSCK ......................................................................................... 1±3

Figure 56: Write Burst ................................................................................................................................... 1±5

Figure 57: Consecutive WRITE-to-WRITE ...................................................................................................... 1±6

Figure 58: Nonconsecutive WRITE-to-WRITE ................................................................................................ 1±6

Figure 59: WRITE Interrupted by WRITE ....................................................................................................... 1±7

Figure 6±: WRITE-to-READ ........................................................................................................................... 1±8

Figure 61: WRITE-to-PRECHARGE ................................................................................................................ 1±9

Figure 62: Bank Write – Without Auto Precharge ............................................................................................ 11±

Figure 63: Bank Write – with Auto Precharge .................................................................................................. 111

Figure 64: WRITE – DM Operation ................................................................................................................ 112

Figure 65: Data Input Timing ........................................................................................................................ 113

Figure 66: Refresh Mode ............................................................................................................................... 114

Figure 67: Self Refresh .................................................................................................................................. 116

Figure 68: Power-Down ................................................................................................................................ 118

Figure 69: READ-to-Power-Down or Self Refresh Entry .................................................................................. 12±

Figure 7±: READ with Auto Precharge-to-Power-Down or Self Refresh Entry ................................................... 12±

Figure 71: WRITE-to-Power-Down or Self Refresh Entry ................................................................................. 121

Figure 72: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry .................................................. 121

Figure 73: REFRESH Command-to-Power-Down Entry .................................................................................. 122

Figure 74: ACTIVATE Command-to-Power-Down Entry ................................................................................. 122

Figure 75: PRECHARGE Command-to-Power-Down Entry ............................................................................. 123

Figure 76: LOAD MODE Command-to-Power-Down Entry ............................................................................. 123

Figure 77: Input Clock Frequency Change During Precharge Power-Down Mode ............................................ 124

Figure 78: RESET Function ........................................................................................................................... 126

Figure 79: ODT Timing for Entering and Exiting Power-Down Mode ............................................................... 128

Figure 8±: Timing for MRS Command to ODT Update Delay .......................................................................... 129

Figure 81: ODT Timing for Active or Fast-Exit Power-Down Mode .................................................................. 129

Figure 82: ODT Timing for Slow-Exit or Precharge Power-Down Modes .......................................................... 13±

Figure 83: ODT Turn-Off Timings When Entering Power-Down Mode ............................................................ 13±

Figure 84: ODT Turn-On Timing When Entering Power-Down Mode .............................................................. 131

Figure 85: ODT Turn-Off Timing When Exiting Power-Down Mode ................................................................ 132

Figure 86: ODT Turn-On Timing When Exiting Power-Down Mode ................................................................. 133

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512MbDDR2.pdf - Rev. T 2/12 EN

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512Mb: x4, x8, x16 DDR2 SDRAM

Features

List of Tables

Table 1: Key Timing Parameters ....................................................................................................................... 2

Table 2: Addressing ......................................................................................................................................... 2

Table 3: FBGA 84-Ball – x16 and 6±-Ball – x4, x8 Descriptions .......................................................................... 16

Table 4: Input Capacitance ............................................................................................................................ 2±

Table 5: Absolute Maximum DC Ratings ......................................................................................................... 21

Table 6: Temperature Limits .......................................................................................................................... 22

Table 7: Thermal Impedance ......................................................................................................................... 22

Table 8: General I_DDParameters ..................................................................................................................... 24

Table 9: I_DD7Timing Patterns (4-Bank Interleave READ Operation) ................................................................. 24

Table 1±: DDR2 I_DDSpecifications and Conditions (Die Revision F) ................................................................. 25

Table 11: DDR2 I_DDSpecifications and Conditions (Die Revision G) ................................................................ 28

Table 12: AC Operating Specifications and Conditions .................................................................................... 31

Table 13: Recommended DC Operating Conditions (SSTL_18) ........................................................................ 43

Table 14: ODT DC Electrical Characteristics ................................................................................................... 44

Table 15: Input DC Logic Levels ..................................................................................................................... 45

Table 16: Input AC Logic Levels ...................................................................................................................... 45

Table 17: Differential Input Logic Levels ......................................................................................................... 46

Table 18: Differential AC Output Parameters ................................................................................................... 48

Table 19: Output DC Current Drive ................................................................................................................ 48

Table 2±: Output Characteristics .................................................................................................................... 49

Table 21: Full Strength Pull-Down Current (mA) ............................................................................................. 5±

Table 22: Full Strength Pull-Up Current (mA) .................................................................................................. 51

Table 23: Reduced Strength Pull-Down Current (mA) ...................................................................................... 52

Table 24: Reduced Strength Pull-Up Current (mA) .......................................................................................... 53

Table 25: Input Clamp Characteristics ............................................................................................................ 54

Table 26: Address and Control Balls ................................................................................................................ 55

Table 27: Clock, Data, Strobe, and Mask Balls ................................................................................................. 55

Table 28: AC Input Test Conditions ................................................................................................................ 55

Table 29: DDR2-4±±/533 Setup and Hold Time Derating Values (^tIS and ^tIH) .................................................... 58

Table 3±: DDR2-667/8±±/1±66 Setup and Hold Time Derating Values (^tIS and ^tIH) ........................................... 59

Table 31: DDR2-4±±/533 ^tDS, ^tDH Derating Values with Differential Strobe ...................................................... 62

Table 32: DDR2-667/8±±/1±66 ^tDS, ^tDH Derating Values with Differential Strobe ............................................. 63

Table 33: Single-Ended DQS Slew Rate Derating Values Using DS_band ^tDH_b................................................... 64

Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V_REF) at DDR2-667 ...................................... 64

Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V_REF) at DDR2-533 ...................................... 65

Table 36: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V_REF) at DDR2-4±± ...................................... 65

Table 37: Truth Table – DDR2 Commands ...................................................................................................... 7±

Table 38: Truth Table – Current State Bank n – Command to Bank n ................................................................ 71

Table 39: Truth Table – Current State Bank n – Command to Bank m ............................................................... 73

Table 4±: Minimum Delay with Auto Precharge Enabled ................................................................................. 74

Table 41: Burst Definition .............................................................................................................................. 78

Table 42: READ Using Concurrent Auto Precharge .......................................................................................... 98

Table 43: WRITE Using Concurrent Auto Precharge ....................................................................................... 1±4

Table 44: Truth Table – CKE .......................................................................................................................... 119

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512Mb: x4, x8, x16 DDR2 SDRAM

State Diagram

Figure 2: Simplified State Diagram

CKE_L

Initialization

sequence

OCD

default

Self

refreshing

PRE

Idle

all banks

precharged

Setting

MRS

EMRS

(E)MRS

REFRESH

Refreshing

Precharge

power-

down

CKE_L

Automatic Sequence

Command Sequence

ACT

ACT = ACTIVATE

CKE_H = CKE HIGH, exit power-down or self refresh

CKE_L = CKE LOW, enter power-down

(E)MRS = (Extended) mode register set

PRE = PRECHARGE

CKE_L

Activating

PRE_A = PRECHARGE ALL

READ = READ

READ A = READ with auto precharge

REFRESH = REFRESH

Active

power-

down

SR = SELF REFRESH

WRITE = WRITE

WRITE A = WRITE with auto precharge

Bank

active

WRITE

READ

Writing

Reading

READ

WRITE

READ A

WRITE A

Writing

with

auto

Reading

with

auto

PRE, PRE_A

Precharging

precharge

1. This diagram provides the basic command flow. It is not comprehensive and does not

identify all timing requirements or possible command restrictions such as multibank in-

teraction, power down, entry/exit, etc.

Note:

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16 DDR2 SDRAM

Functional Description

The DDR2 SDRAM uses a double data rate architecture to achieve high-speed opera-

tion. The double data rate architecture is essentially a 4n-prefetch architecture, with an

interface designed to transfer two data words per clock cycle at the I/O balls. A single

READ or WRITE operation for the DDR2 SDRAM effectively consists of a single 4n-bit-

wide, two-clock-cycle data transfer at the internal DRAM core and four corresponding

n-bit-wide, one-half-clock-cycle data transfers at the I/O balls.

A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for

use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM

during READs and by the memory controller during WRITEs. DQS is edge-aligned with

data for READs and center-aligned with data for WRITEs. The x16 offering has two data

strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS,

UDQS#).

The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK

going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-

mands (address and control signals) are registered at every positive edge of CK. Input

data is registered on both edges of DQS, and output data is referenced to both edges of

DQS as well as to both edges of CK.

Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a se-

lected location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVATE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with

the ACTIVATE command are used to select the bank and row to be accessed. The ad-

dress bits registered coincident with the READ or WRITE command are used to select

the bank and the starting column location for the burst access.

The DDR2 SDRAM provides for programmable read or write burst lengths of four or

eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another

read or a burst write of eight with another write. An auto precharge function may be en-

abled to provide a self-timed row precharge that is initiated at the end of the burst ac-

cess.

As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM

enables concurrent operation, thereby providing high, effective bandwidth by hiding

row precharge and activation time.

A self refresh mode is provided, along with a power-saving, power-down mode.

All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength

outputs are SSTL_18-compatible.

Industrial Temperature

The industrial temperature (IT) option, if offered, has two simultaneous requirements:

ambient temperature surrounding the device cannot be less than –4±°C or greater than

85°C, and the case temperature cannot be less than –4±°C or greater than 95°C. JEDEC

specifications require the refresh rate to double when T_Cexceeds 85°C; this also requires

use of the high-temperature self refresh option. Additionally, ODT resistance, input/

output impedance and I_DDvalues must be derated when T_Cis < ±°C or > 85°C.

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16 DDR2 SDRAM

Functional Description

Automotive Temperature

The automotive temperature (AT) option, if offered, has two simultaneous require-

ments: ambient temperature surrounding the device cannot be less than –4±°C or great-

er than 1±5°C, and the case temperature cannot be less than –4±°C or greater than

1±5°C. JEDEC specifications require the refresh rate to double when T_Cexceeds 85°C;

this also requires use of the high-temperature self refresh option. Additionally, ODT re-

sistance the input/output impedance and I_DDvalues must be derated when T_Cis < ±°C

or > 85°C.

General Notes

• The functionality and the timing specifications discussed in this data sheet are for the

DLL-enabled mode of operation.

• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ

term is to be interpreted as any and all DQ collectively, unless specifically stated oth-

erwise. Additionally, the x16 is divided into 2 bytes: the lower byte and the upper byte.

For the lower byte (DQ[7:±]), DM refers to LDM and DQS refers to LDQS. For the up-

per byte (DQ[15:8]), DM refers to UDM and DQS refers to UDQS.

• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be

used, use the lower byte for data transfers and terminate the upper byte as noted:

– Connect UDQS to ground via 1kΩ* resistor

– Connect UDQS# to V_DDvia 1kΩ* resistor

– Connect UDM to V_DDvia 1kΩ* resistor

– Connect DQ[15:8] individually to either V_SSor V_DDvia 1kΩ* resistors, or float

DQ[15:8].

*If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT.

• Complete functionality is described throughout the document, and any page or dia-

gram may have been simplified to convey a topic and may not be inclusive of all re-

quirements.

• Any specific requirement takes precedence over a general statement.

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512MbDDR2.pdf - Rev. T 2/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16 DDR2 SDRAM

Functional Block Diagrams

The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory. It is inter-

nally configured as a multibank DRAM.

Figure 3: 128 Meg x 4 Functional Block Diagram

ODT

Control

logic

CKE

CK#

CS#

RAS#

CAS#

WE#

ODT control

VddQ

Bank3

Bank2

Bank1

sw1 sw2 sw3

Bank3

Bank2

Bank1

Bank0

row-

COL0, COL1

CK, CK#

DLL

Refresh

counter

Bank0

sw1 sw2 sw3

Mode

Row-

address

MUX

Read

latch

registers

MUX

address

latch and

decoder

DQ0–DQ3

Memory

array

(16,384 x 512 x 16)

16,384

Data

DRVRS

DQS

generator

DQS, DQS#

Sense amplifiers

8,192

Input

sw1 sw2 sw3

registers

I/O gating

DM mask logic

DQS, DQS#

Address

A0–A13,

BA0, BA1

Bank

control

logic

Write

FIFO

Mask

512

(x16)

and

RCVRS

drivers

internal

CK, CK#

Column

decoder

CK out

CK in

sw1 sw2 sw3

Column-

address

counter/

latch

Data

COL0, COL1

VssQ

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512Mb: x4, x8, x16 DDR2 SDRAM

Functional Block Diagrams

Figure 4: 64 Meg x 8 Functional Block Diagram

ODT

Control

logic

CKE

CK#

CS#

RAS#

CAS#

WE#

ODT control

VddQ

Bank 3

Bank 2

Bank 1

CK, CK#

DLL

sw1 sw2 sw3

Bank 3

Bank 2

COL0, COL1

Bank 1

Refresh

counter

Bank 0

row-

sw1 sw2 sw3

Mode

Row-

address

MUX

Read

latch

registers

MUX

address

latch and

decoder

DRVRS

DQ0–DQ7

Memory

array

(16,384 x 256 x 32)

16,384

Data

DQS

generator

DQS, DQS#

Sense amplifiers

8,192

Input

sw1 sw2 sw3

registers

I/O gating

DM mask logic

DQS, DQS#

RDQS#

Address

A0–A13,

BA0, BA1

Bank

control

logic

Write

FIFO

and

Mask

256

RCVRS

(x32)

drivers

internal

CK, CK#

Column

decoder

CK out

CK in

sw1 sw2 sw3

Column-

address

counter/

latch

RDQS

Data

COL0, COL1

VssQ

Figure 5: 32 Meg x 16 Functional Block Diagram

ODT

CKE

Control

Logic

CK#

CS#

RAS#

CAS#

WE#

VddQ

ODT control

CK, CK#

DLL

COL0, COL1

MUX

sw1 sw2 sw3

Bank 3

Bank 2

Bank 3

Bank 2

Bank 1

Bank 0

Bank 1

Refresh

counter

sw1 sw2 sw3

Mode

Read

latch

Bank 0

DRVRS

registers

Row-

address

MUX

row-

Data

DQ0–DQ15

Address

latch and

decoder

8,192

Memory

array

(8,192 x 256 x 64)

DQS

generator

UDQS, UDQS#

LDQS, LDQS#

Sense amplifiers

Input

registers

16,384

sw1 sw2 sw3

UDQS, UDQS#

LDQS, LDQS#

I/O gating

DM mask logic

A0–A12,

BA0, BA1

Bank

control

logic

Address

Write

FIFO

Mask

256

(x64)

RCVRS

and

drivers

Internal

CK, CK#

Column

decoder

sw1 sw2 sw3

CK out

CK in

Column-

address

counter/

latch

UDM, LDM

Data

COL0, COL1

VssQ

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Ball Assignments and Descriptions

Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View)

V_DD

NF, RDQS#/NU V_SS

V_SSQDQS#/NU

V_DDQ

NF, DQ7

V_DDQ

NF, DQ6

V_DDQ

V_SSQDM, DM/RDQS

DQS

V_DDQ

DQ2

V_SSDL

RAS#

CAS#

V_SSQ

DQ0

V_SSQ

DQ1

V_SSQ

V_REF

CKE

BA0

A10

V_DDQ

DQ3

V_SS

NF, DQ4

V_DDL

NF, DQ5

V_DD

WE#

BA1

CK#

CS#

ODT

RFU

V_DD

V_SS

A11

RFU

V_SS

V_DD

A12

RFU

A13

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Ball Assignments and Descriptions

Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View)

V_DD

DQ14

V_DDQ

DQ12

V_DD

V_SSQ

DQ9

V_SSQ

V_SS

UDM

V_DDQ

DQ11

V_SS

V_SSQUDQS#/NU

V_DDQ

DQ15

V_DDQ

DQ13

V_DDQ

DQ7

UDQS

V_DDQ

DQ10

V_SSQ

DQ8

V_SSQ

V_SSQLDQS#/NU

DQ6

V_SSQ

DQ1

V_SSQ

V_REF

CKE

BA0

A10

LDM

V_DDQ

DQ3

V_SS

LDQS

V_DDQ

DQ2

V_SSDL

RAS#

CAS#

V_SSQ

DQ0

V_SSQ

V_DDQ

DQ4

V_DDQ

DQ5

V_DDL

V_DD

WE#

BA1

CK#

CS#

ODT

RFU

V_DD

V_SS

A11

V_SS

V_DD

A12

RFU

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Ball Assignments and Descriptions

Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions

Symbol

Type

Description

A[12:0] (x16)

A[13:0] (x4, x8)

Input

Address inputs: Provide the row address for ACTIVATE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out

of the memory array in the respective bank. A10 sampled during a PRECHARGE com-

mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected

by BA[1:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a

LOAD MODE command.

BA0, BA1

CK, CK#

CKE

Input

Bank address inputs: BA[1:0] define to which bank an ACTIVATE, READ, WRITE, or PRE-

CHARGE command is being applied. BA[1:0] define which mode register including MR,

EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.

Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of CK#. Output

data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.

Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates

clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is

dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides

precharge power-down and SELF REFRESH operations (all banks idle), or ACTIVATE pow-

er-down (row active in any bank). CKE is synchronous for power-down entry, power-

down exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF RE-

FRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during POWER-

DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an

SSTL_18 input but will detect a LVCMOS LOW level once V_DDis applied during first pow-

er-up. After V_REFhas become stable during the power-on and initialization sequence, it

must be maintained for proper operation of the CKE receiver. For proper SELF-REFRESH

operation, V_REFmust be maintained.

CS#

Input

Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when CS# is registered high. CS# provides for exter-

nal bank selection on systems with multiple ranks. CS# is considered part of the com-

mand code.

LDM, UDM, DM

Input data mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on

both edges of DQS. Although DM balls are input-only, the DM loading is designed to

match that of DQ and DQS balls. LDM is DM for lower byte DQ[7:0] and UDM is DM for

upper byte DQ[15:8].

ODT

Input

On-die termination: ODT (registered HIGH) enables termination resistance internal to

the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls:

DQ[15:0], LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ[7:0], DQS, DQS#,

RDQS, RDQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input

will be ignored if disabled via the LOAD MODE command.

RAS#, CAS#, WE#

Input

I/O

Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being

entered.

DQ[15:0] (x16)

DQ[3:0] (x4)

DQ[7:0] (x8)

Data input/output: Bidirectional data bus for 32 Meg x 16.

Bidirectional data bus for 128 Meg x 4.

Bidirectional data bus for 64 Meg x 8.

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Ball Assignments and Descriptions

Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions (Continued)

Symbol

Type

Description

DQS, DQS#

I/O

Data strobe: Output with read data, input with write data for source synchronous oper-

ation. Edge-aligned with read data, center-aligned with write data. DQS# is only used

when differential data strobe mode is enabled via the LOAD MODE command.

LDQS, LDQS#

UDQS, UDQS#

RDQS, RDQS#

I/O

Data strobe for lower byte: Output with read data, input with write data for source

synchronous operation. Edge-aligned with read data, center-aligned with write data.

LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE

command.

Data strobe for upper byte: Output with read data, input with write data for source

synchronous operation. Edge-aligned with read data, center-aligned with write data.

UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE

command.

Output

Redundant data strobe: For 64 Meg x 8 only. RDQS is enabled/disabled via the load

mode command to the extended mode register (EMR). When RDQS is enabled, RDQS is

output with read data only and is ignored during write data. When RDQS is disabled, ball

B3 becomes data mask (see DM ball). RDQS# is only used when RDQS is enabled and dif-

ferential data strobe mode is enabled.

V_DD

V_DDQ

V_DDL

V_REF

V_SS

Supply

–

Power supply: 1.8V 0.1V.

DQ power supply: 1.8V 0.1V. Isolated on the device for improved noise immunity.

DLL power supply: 1.8V 0.1V.

SSTL_18 reference voltage (V_DDQ/2).

Ground.

V_SSDL

V_SSQ

DLL ground: Isolated on the device from V_SSand V_SSQ.

DQ ground: Isolated on the device for improved noise immunity.

No connect: These balls should be left unconnected.

–

No function: x8: these balls are used as DQ[7:4]; x4: they are no function.

–

Not used: If EMR(E10) = 0: x16, A8 = UDQS# and E8 = LDQS#; x8, A2 = RDQS# and A8 =

DQS#; x4, A2 = NU and A8 = NU. If EMR(E10) = 1: x16, A8 = NU and E8 = NU; x8, A2 = NU

and A8 = NU; x4, A2 = NU and A8 = NU.

RFU

–

Reserved for future use: Bank address BA2, row address bits A13 (x16 only), A14, and

A15.

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Packaging

Package Dimensions

Figure 8: 84-Ball FBGA (8mm x 12.5mm) – x16

0.8 0.05

0.155

Seating

plane

1.8 CTR

0.12 A

Nonconductive overmold

84X Ø0.45

Solder ball material:

SAC305 (96.5% Sn,

3% Ag, 0.5% Cu).

Dimensions apply to

solder balls post-reflow

on Ø0.35 SMD

ball pads.

Ball A1 ID

11.2 CTR

12.5 0.1

0.8 TYP

1.2 MAX

0.25 MIN

0.8

TYP

6.4 CTR

8 0.1

1. All dimensions are in millimeters.

Notes:

2. Solder ball material for this package is also available as leaded eutectic (62% Sn, 36%

Pb, 2% Ag).

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Packaging

Figure 9: 60-Ball FBGA (8mm x 10mm) – x4, x8

0.8 0.05

0.155

Seating

Plane

1.8 CTR

0.12 A

Nonconductive overmold

60X Ø0.45

Solder ball material:

SAC305 (96.5% Sn,

3% Ag, 0.5% Cu).

Dimensions apply to

solder balls post-reflow

on Ø0.35 SMD ball

pads.

Ball A1 ID

9 8 7

3 2 1

8 CTR

10 0.1

0.8 TYP

6.4 CTR

8 0.1

1. All dimensions are in millimeters.

1.2 MAX

0.25 MIN

Notes:

2. Solder ball material for this package is also available as leaded eutectic (62% Sn, 36%

Pb, 2% Ag).

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Packaging

FBGA Package Capacitance

Table 4: Input Capacitance

Parameter

Symbol

C_CK

Min

1.0

–

Max

2.0

Units

Notes

Input capacitance: CK, CK#

Delta input capacitance: CK, CK#

C_DCK

C_I

0.25

2.0

2, 3

1, 4

Input capacitance: Address balls, bank address

balls, CS#, RAS#, CAS#, WE#, CKE, ODT

1.0

Delta input capacitance: Address balls, bank

address balls, CS#, RAS#, CAS#, WE#, CKE, ODT

C_DI

–

0.25

2, 3

Input/output capacitance: DQ, DQS, DM, NF

C_IO

2.5

–

4.0

0.5

1, 5

2, 3

Delta input/output capacitance: DQ, DQS, DM,

C_DIO

1. This parameter is sampled. V_DD= 1.8V 0.1V, V_DDQ= 1.8V 0.1V, V_REF= V_SS, f = 100 MHz,

T_C= 25°C, V_OUT(DC)= V_DDQ/2, V_OUT(peak-to-peak) = 0.1V. DM input is grouped with I/O

balls, reflecting the fact that they are matched in loading.

Notes:

2. The capacitance per ball group will not differ by more than this maximum amount for

any given device.

3. ΔC are not pass/fail parameters; they are targets.

4. Reduce MAX limit by 0.25pF for -25 and -25E speed devices.

5. Reduce MAX limit by 0.5pF for -3, -3E, -5E, -25, -25E, and -37E speed devices.

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Electrical Specifications – Absolute Ratings

Stresses greater than those listed may cause permanent damage to the device. This is a

stress rating only, and functional operation of the device at these or any other condi-

tions oustide those indicated in the operational sections of this specification is not im-

plied. Exposure to absolute maximum rating conditions for extended periods may affect

reliability.

Table 5: Absolute Maximum DC Ratings

Parameter

Symbol

V_DD

Min

–1.0

–0.5

–5

Max

2.3

Units

Notes

V_DDsupply voltage relative to V_SS

V_DDQsupply voltage relative to V_SSQ

V_DDLsupply voltage relative to V_SSL

Voltage on any ball relative to V_SS

1, 2

V_DDQ

V_DDL

V_IN, V_OUT

I_I

Input leakage current; any input 0V ≤ V_IN≤ V_DD

;

μA

all other balls not under test = 0V

Output leakage current; 0V ≤ V_OUT≤ V_DDQ; DQ

I_OZ

–5

μA

and ODT disabled

V_REFleakage current; V_REF= valid V_REFlevel

I_VREF

–2

μA

1. V_DD, V_DDQ, and V_DDLmust be within 300mV of each other at all times; this is not re-

quired when power is ramping down.

Notes:

2. V_REF≤ 0.6 x V_DDQ; however, V_REFmay be ≥ V_DDQprovided that V_REF≤ 300mV.

3. Voltage on any I/O may not exceed voltage on V_DDQ

Temperature and Thermal Impedance

It is imperative that the DDR2 SDRAM device’s temperature specifications, shown in

Table 6 (page 22), be maintained in order to ensure the junction temperature is in the

proper operating range to meet data sheet specifications. An important step in main-

taining the proper junction temperature is using the device’s thermal impedances cor-

rectly. The thermal impedances are listed in Table 7 (page 22) for the applicable and

available die revision and packages.

Incorrectly using thermal impedances can produce significant errors. Read Micron

technical note TN-±±-±8, “Thermal Applications,” prior to using the thermal impedan-

ces listed in Table 7. For designs that are expected to last several years and require the

flexibility to use several DRAM die shrinks, consider using final target theta values (rath-

er than existing values) to account for increased thermal impedances from the die size

reduction.

The DDR2 SDRAM device’s safe junction temperature range can be maintained when

the T_Cspecification is not exceeded. In applications where the device’s ambient tem-

perature is too high, use of forced air and/or heat sinks may be required in order to sat-

isfy the case temperature specifications.

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Electrical Specifications – Absolute Ratings

Table 6: Temperature Limits

Parameter

Symbol

T_STG

T_C

Min

–55

Max

150

Units

°C

Notes

Storage temperature

Operating temperature: commercial

Operating temperature: industrial

°C

2, 3

T_C

–40

°C

2, 3 , 4

4, 5

T_A

°C

Operating temperature: automotive

T_C

105

°C

2, 3, 4

4, 5

T_A

°C

1. MAX storage case temperature T_STGis measured in the center of the package, as shown

in Figure 10. This case temperature limit is allowed to be exceeded briefly during pack-

age reflow, as noted in Micron technical note TN-00-15, “Recommended Soldering Pa-

rameters.”

Notes:

2. MAX operating case temperature T_Cis measured in the center of the package, as shown

in Figure 10.

3. Device functionality is not guaranteed if the device exceeds maximum T_Cduring

operation.

4. Both temperature specifications must be satisfied.

5. Operating ambient temperature surrounding the package.

Figure 10: Example Temperature Test Point Location

Test point

Length (L)

0.5 (L)

0.5 (W)

Width (W)

Lmm x Wmm FBGA

Table 7: Thermal Impedance

Θ JA (°C/W)

Die Revision Package Substrate Airflow = 0m/s Airflow = 1m/s Airflow = 2m/s Θ JB (°C/W) Θ JC (°C/W)

F¹

60-ball

2-layer

4-layer

2-layer

4-layer

71.4

53.6

65.8

50.0

54.1

44.5

50.4

41.3

47.5

40.5

44.3

37.7

33.7

33.5

30.7

30.5

5.5

84-ball

4.1

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Electrical Specifications – Absolute Ratings

Table 7: Thermal Impedance (Continued)

Θ JA (°C/W)

Die Revision Package Substrate Airflow = 0m/s Airflow = 1m/s Airflow = 2m/s Θ JB (°C/W) Θ JC (°C/W)

G¹

60-ball

84-ball

2-layer

4-layer

2-layer

4-layer

94.2

76.4

88.8

71.4

76.5

66.9

71.3

62.1

70.1

63.1

65.6

58.7

57.3

56.5

52.5

52.0

6.1

6.0

1. Thermal resistance data is based on a number of samples from multiple lots and should

be viewed as a typical number.

Note:

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Electrical Specifications – I_DDParameters

I_DDSpecifications and Conditions

Table 8: General I_DDParameters

I_DDParameters

CL (I_DD

^tRCD (I_DD

^tRC (I_DD

^tRRD (I_DD) - x4/x8 (1KB)

^tRRD (I_DD) - x16 (2KB)

-187E

-25E

-25

-3E

-3

-37E

-5E

Units

^tCK

)

13.125

58.125

7.5

12.5

57.5

7.5

)

7.5

^tCK (I_DD

^tRAS MIN (I_DD

^tRAS MAX (I_DD

^tRP (I_DD

^tRFC (I_DD- 256Mb)

^tRFC (I_DD- 512Mb)

^tRFC (I_DD- 1Gb)

)

1.875

2.5

3.75

)

70,000

13.125

70,000

12.5

70,000

)

105

127.5

197.5

105

127.5

197.5

105

127.5

197.5

105

127.5

197.5

105

127.5

197.5

105

127.5

197.5

127.5

197.5

^tRFC (I_DD- 2Gb)

^tFAW (I_DD) - x4/x8 (1KB)

^tFAW (I_DD) - x16 (2KB)

Defined by pattern in on page

I_DD7Conditions

The detailed timings are shown below for I_DD7. Where general I_DDparameters in the

General Parameters Table conflict with pattern requirements in the I_DD7Timing Pat-

terns Table, then the I_DD7timing patterns requirements take precedence.

Table 9: I_DD7Timing Patterns (4-Bank Interleave READ Operation)

Speed Grade

I_DD7Timing Patterns

Timing patterns for 4-bank x4/x8/x16 devices

-5E

A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D

-37E

-3

A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D

A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D

A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D

-3E

-25

A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D

A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D

A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D D

-25E

-187E

1. A = active; RA = read auto precharge; D = deselect.

Notes:

2. All banks are being interleaved at ^tRC (I_DD) without violating ^tRRD (I_DD) using a BL = 4.

3. Control and address bus inputs are stable during DESELECTs.

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Electrical Specifications – I_DDParameters

Table 10: DDR2 I_DDSpecifications and Conditions (Die Revision F)

Notes: 1–7 apply to the entire table

-25E/

-25

Parameter/Condition

Symbol Configuration

-3E/-3

-37E

-5E

Units

Operating one bank active-precharge

current: ^tCK = ^tCK (I_DD), ^tRC = ^tRC (I_DD),

^tRAS = ^tRAS MIN (I_DD); CKE is HIGH, CS# is

HIGH between valid commands; address bus

inputs are switching; Data bus inputs are

switching

I_DD0

x4, x8

x16

100

135

120

110

Operating one bank active-read-pre-

charge current: I_OUT= 0mA; BL = 4, CL = CL

(I_DD), AL = 0; ^tCK = ^tCK (I_DD), ^tRC = ^tRC (I_DD),

^tRAS = ^tRAS MIN (I_DD), ^tRCD = ^tRCD (I_DD); CKE

is HIGH, CS# is HIGH between valid com-

mands; address bus inputs are switching; Da-

ta pattern is same as I_DD4W

I_DD1

x4, x8

x16

115

165

105

150

135

130

Precharge power-down current: All banks

idle; ^tCK = ^tCK (I_DD); CKE is LOW; Other con-

trol and address bus inputs are stable; Data

bus inputs are floating

I_DD2P

I_DD2Q

I_DD2N

x4, x8, x16

Precharge quiet standby current: All

banks idle; ^tCK = ^tCK (I_DD); CKE is HIGH, CS# is

HIGH; Other control and address bus inputs

are stable; Data bus inputs are floating

x4, x8

x16

Precharge standby current: All banks idle;

^tCK = ^tCK (I_DD); CKE is HIGH, CS# is HIGH;

Other control and address bus inputs are

switching; Data bus inputs are switching

x4, x8

x16

Active power-down current: All banks

open; ^tCK = ^tCK (I_DD); CKE is LOW; Other con-

trol and address bus inputs are stable; Data

bus inputs are floating

I_DD3Pf

I_DD3Ps

I_DD3N

Fast PDN exit

MR12 = 0

Slow PDN exit

MR12 = 1

Active standby current: All banks open;

^tCK = ^tCK (I_DD), ^tRAS = ^tRAS MAX (I_DD), ^tRP =

^tRP (I_DD); CKE is HIGH, CS# is HIGH between

valid commands; Other control and address

bus inputs are switching; Data bus inputs are

switching

x4, x8

x16

Operating burst write current: All banks

open, continuous burst writes; BL = 4, CL =

CL (I_DD), AL = 0; ^tCK = ^tCK (I_DD), ^tRAS = ^tRAS

MAX (I_DD), ^tRP = ^tRP (I_DD); CKE is HIGH, CS# is

HIGH between valid commands; address bus

inputs are switching; Data bus inputs are

switching

I_DD4W

x4, x8

x16

195

295

170

250

140

205

115

160

PDF: 09005aef82f1e6e2

512MbDDR2.pdf - Rev. T 2/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – I_DDParameters

Table 10: DDR2 I_DDSpecifications and Conditions (Die Revision F) (Continued)

Notes: 1–7 apply to the entire table

-25E/

-25

Parameter/Condition

Symbol Configuration

-3E/-3

180

-37E

145

195

-5E

115

155

Units

Operating burst read current: All banks

open, continuous burst reads, I_OUT= 0mA; BL

= 4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK (I_DD),

^tRAS = ^tRAS MAX (I_DD), ^tRP = ^tRP (I_DD); CKE is

HIGH, CS# is HIGH between valid commands;

address bus inputs are switching; Data bus

inputs are switching

I_DD4R

x4, x8

x16

205

275

235

Burst refresh current: ^tCK = ^tCK (I_DD); re-

fresh command at every ^tRFC (I_DD) interval;

CKE is HIGH, CS# is HIGH between valid com-

mands; Other control and address bus inputs

are switching; Data bus inputs are switching

I_DD5

x4, x8

x16

230

180

185

170

175

165

170

Self refresh current: CK and CK# at 0V;

CKE ≤ 0.2V; Other control and address bus in-

puts are floating; Data bus inputs are float-

ing

I_DD6

x4, x8, x16

I_DD6L

Operating bank interleave read current:

All bank interleaving reads, I_OUT= 0mA; BL =

4, CL = CL (I_DD), AL = ^tRCD (I_DD) - 1 x ^tCK (I_DD);

^tCK = ^tCK (I_DD), ^tRC = ^tRC (I_DD), ^tRRD = ^tRRD

(I_DD), ^tRCD = ^tRCD (I_DD); CKE is HIGH, CS# is

HIGH between valid commands; address bus

inputs are stable during deselects; Data bus

inputs are switching; See I_DD7Conditions

(page 24) for details

I_DD7

x4, x8

x16

300

370

240

350

225

340

220

340

1. I_DDspecifications are tested after the device is properly initialized. 0°C ≤ T_C≤ +85°C.

2. V_DD= 1.8V 0.1V, V_DDQ= 1.8V 0.1V, V_DDL= 1.8V 0.1V, V_REF= V_DDQ/2.

3. I_DDparameters are specified with ODT disabled.

Notes:

4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and

UDQS#. I_DDvalues must be met with all combinations of EMR bits 10 and 11.

5. Definitions for I_DDconditions:

LOW

V_IN≤ V_IL(AC)max

HIGH

Stable

V_IN≥ V_IH(AC)min

Inputs stable at a HIGH or LOW level

Floating Inputs at V_REF= V_DDQ/2

Switching Inputs changing between HIGH and LOW every other clock cycle (once per

two clocks) for address and control signals

Switching Inputs changing between HIGH and LOW every other data transfer (once

per clock) for DQ signals, not including masks or strobes

6. I_DD1, I_DD4R, and I_DD7require A12 in EMR1 to be enabled during testing.

7. The following I_DDvalues must be derated (I_DDlimits increase) on IT-option or on AT-op-

tion devices when operated outside of the range 0°C ≤ T_C≤ 85°C:

PDF: 09005aef82f1e6e2

512MbDDR2.pdf - Rev. T 2/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – I_DDParameters

When

I_DD2Pand I_DD3P(SLOW)must be derated by 4%; I_DD4Rand I_DD5Wmust be derat-

T_C≤ 0°C ed by 2%; and I_DD6and I_DD7must be derated by 7%

When I_DD0, I_DD1, I_DD2N, I_DD2Q, I_DD3N, I_DD3P(FAST), I_DD4R, I_DD4W, and I_DD5Wmust be de-

T_C≥ 85°C rated by 2%; I_DD2Pmust be derated by 20%; I_DD3Pslow must be derated by

30%; and I_DD6must be derated by 80% (I_DD6will increase by this amount if

T_C< 85°C and the 2X refresh option is still enabled)

PDF: 09005aef82f1e6e2

512MbDDR2.pdf - Rev. T 2/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – I_DDParameters

Table 11: DDR2 I_DDSpecifications and Conditions (Die Revision G)

Notes: 1–7 apply to the entire table

Configura-

tion

-25E/

-25

Parameter/Condition

Symbol

-187E

-3E/-3

-37E

-5E

Units

Operating one bank active-pre-

charge current: ^tCK = ^tCK (I_DD), ^tRC =

^tRC (I_DD), ^tRAS = ^tRAS MIN (I_DD); CKE is

HIGH, CS# is HIGH between valid com-

mands; address bus inputs are switch-

ing; Data bus inputs are switching

I_DD0

x4, x8

x16

Operating one bank active-read-

precharge current: I_OUT= 0mA; BL =

4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK (I_DD),

^tRC = ^tRC (I_DD), ^tRAS = ^tRAS MIN (I_DD),

^tRCD = ^tRCD (I_DD); CKE is HIGH, CS# is

HIGH between valid commands; ad-

dress bus inputs are switching; Data

pattern is same as I_DD4W

I_DD1

x4, x8

x16

100

Precharge power-down current:

All banks idle; ^tCK = ^tCK (I_DD); CKE is

LOW; Other control and address bus

inputs are stable; Data bus inputs are

floating

I_DD2P

I_DD2Q

I_DD2N

x4, x8, x16

Precharge quiet standby current:

All banks idle; ^tCK = ^tCK (I_DD); CKE is

HIGH, CS# is HIGH; Other control and

address bus inputs are stable; Data

bus inputs are floating

x4, x8

x16

Precharge standby current: All

banks idle; ^tCK = ^tCK (I_DD); CKE is

HIGH, CS# is HIGH; Other control and

address bus inputs are switching; Da-

ta bus inputs are switching

x4, x8

x16

Active power-down current: All

banks open; ^tCK = ^tCK (I_DD); CKE is

LOW; Other control and address bus

inputs are stable; Data bus inputs are

floating

I_DD3PfFast PDN exit

MR12 = 0

I_DD3PsSlow PDN exit

MR12 = 1

Active standby current: All banks

open; ^tCK = ^tCK (I_DD), ^tRAS = ^tRAS

MAX (I_DD), ^tRP = ^tRP (I_DD); CKE is

HIGH, CS# is HIGH between valid com-

mands; Other control and address bus

inputs are switching; Data bus inputs

are switching

I_DD3N

x4, x8

x16

PDF: 09005aef82f1e6e2

512MbDDR2.pdf - Rev. T 2/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – I_DDParameters

Table 11: DDR2 I_DDSpecifications and Conditions (Die Revision G) (Continued)

Notes: 1–7 apply to the entire table

Configura-

tion

-25E/

-25

Parameter/Condition

Symbol

-187E

145

-3E/-3

115

-37E

-5E

Units

Operating burst write current: All

banks open, continuous burst writes;

BL = 4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK

(I_DD), ^tRAS = ^tRAS MAX (I_DD), ^tRP = ^tRP

(I_DD); CKE is HIGH, CS# is HIGH be-

tween valid commands; address bus

inputs are switching; Data bus inputs

are switching

I_DD4W

x4, x8

x16

125

160

185

135

120

105

Operating burst read current: All

banks open, continuous burst reads,

I_DD4R

x4, x8

x16

140

180

120

150

110

125

110

_OUT= 0mA; BL = 4, CL = CL (I_DD), AL =

0; ^tCK = ^tCK (I_DD),

^tRAS = ^tRAS MAX (I_DD), ^tRP = ^tRP (I_DD);

CKE is HIGH, CS# is HIGH between val-

id commands; address bus inputs are

switching; Data bus inputs are switch-

ing

Burst refresh current: ^tCK = ^tCK

(I_DD); refresh command at every ^tRFC

(I_DD) interval; CKE is HIGH, CS# is

HIGH between valid commands; Oth-

er control and address bus inputs are

switching; Data bus inputs are switch-

ing

I_DD5

x4, x8

x16

105

110

100

Self refresh current: CK and CK# at

0V; CKE ≤ 0.2V; Other control and ad-

dress bus inputs are floating; Data

bus inputs are floating

I_DD6

x4, x8, x16

I_DD6L

Operating bank interleave read

current: All bank interleaving reads,

I_DD7

x4, x8

x16

160

225

150

215

140

200

135

195

130

190

I_OUT= 0mA; BL = 4, CL = CL (I_DD), AL =

^tRCD (I_DD) - 1 x ^tCK (I_DD); ^tCK = ^tCK

(I_DD), ^tRC = ^tRC (I_DD), ^tRRD = ^tRRD

(I_DD), ^tRCD = ^tRCD (I_DD); CKE is HIGH,

CS# is HIGH between valid commands;

address bus inputs are stable during

deselects; Data bus inputs are switch-

ing; See I_DD7Conditions (page 24) for

details

1. I_DDspecifications are tested after the device is properly initialized. 0°C ≤ T_C≤ +85°C.

2. V_DD= +1.8V 0.1V, V_DDQ= +1.8V 0.1V, V_DDL= +1.8V 0.1V, V_REF= V_DDQ/2.

3. I_DDparameters are specified with ODT disabled.

Notes:

4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and

UDQS#. I_DDvalues must be met with all combinations of EMR bits 10 and 11.

PDF: 09005aef82f1e6e2

512MbDDR2.pdf - Rev. T 2/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

512Mb: x4, x8, x16 DDR2 SDRAM

Electrical Specifications – I_DDParameters

5. Definitions for I_DDconditions:

LOW

V_IN≤ V_IL(AC)max

V_IN≥ V_IH(AC)min

Inputs stable at a HIGH or LOW level

HIGH

Stable

Floating Inputs at V_REF= V_DDQ/2

Switching Inputs changing between HIGH and LOW every other clock cycle (once per

two clocks) for address and control signals

Switching Inputs changing between HIGH and LOW every other data transfer (once

per clock) for DQ signals, not including masks or strobes

6. I_DD1, I_DD4R, and I_DD7require A12 in EMR1 to be enabled during testing.

7. The following I_DDvalues must be derated (I_DDlimits increase) on IT-option or on AT-op-

tion devices when operated outside of the range 0°C ≤ T_C≤ 85°C:

When

T_C≤ 0°C ed by 2%; and I_DD6and I_DD7must be derated by 7%

When I_DD0, I_DD1, I_DD2N, I_DD2Q, I_DD3N, I_DD3P(FAST), I_DD4R, I_DD4W, and I_DD5Wmust be de-

I_DD2Pand I_DD3P(SLOW)must be derated by 4%; I_DD4Rand I_DD5Wmust be derat-

T_C≥ 85°C rated by 2%; I_DD2Pmust be derated by 20%; I_DD3Pslow must be derated by

30%; and I_DD6must be derated by 80% (I_DD6will increase by this amount if

T_C< 85°C and the 2X refresh option is still enabled)

PDF: 09005aef82f1e6e2

512MbDDR2.pdf - Rev. T 2/12 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

AC Timing Operating Specifications

Table 12: AC Operating Specifications and Conditions

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;

V_DDQ= 1.8V 0.1V, V_DD= 1.8V 0.1V

AC Characteristics

-187E

-25E

-25

-3E

-3

-37E

-5E

Parameter

Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes

Clock

cycle time

CL = 7 ^tCK (avg) 1.875

CL = 6 ^tCK (avg) 2.5

CL = 5 ^tCK (avg) 2.5

CL = 4 ^tCK (avg) 3.75

CL = 3 ^tCK (avg) 5.0

^tCH (avg) 0.48

8.0

–

6, 7, 8,

2.5

3.75

5.0

8.0

2.5

3.0

3.75

5.0

8.0

–

8.0

3.0

5.0

8.0

3.0

3.75

5.0

8.0

–

8.0

3.75

5.0

8.0

5.0

8.0

CK high-level

width

CK low-level width ^tCL (avg) 0.48

0.52

0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 ^tCK

0.52

0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 ^tCK

Half clock period

^tHP

MIN = lesser of ^tCH and ^tCL

MAX = n/a

Absolute ^tCK

^tCK (abs)

^tCH (abs)

^tCL (abs)

MIN = ^tCK (AVG) MIN + ^tJITper (MIN)

MAX = ^tCK (AVG) MAX + ^tJITper (MAX)

Absolute CK

high-level width

MIN = ^tCK (AVG) MIN × ^tCH (AVG) MIN + ^tJITdty (MIN)

MAX = ^tCK (AVG) MAX × ^tCH (AVG) MAX + ^tJITdty (MAX)

MIN = ^tCK (AVG) MIN × ^tCL (AVG) MIN + ^tJITdty (MIN)

MAX = ^tCK (AVG) MAX × ^tCL (AVG) MAX + ^tJITdty (MAX)

Absolute CK

low-level width

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;

V_DDQ= 1.8V 0.1V, V_DD= 1.8V 0.1V

AC Characteristics

-187E

-25E

-25

-3E

-3

-37E

-5E

Parameter

Period jitter

Half period

Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes

^tJITper

^tJITdty

^tJITcc

^tERR_2per–132

^tERR_3per–157

^tERR_4per–175

^tERR_5per–188

–90

–75

–100 100 –100 100 –125 125 –125 125 –125 125 –125 125

–100 100 –100 100 –125 125 –125 125 –125 125 –150 150

Cycle to cycle

180

200

250

Cumulative error,

2 cycles

132

157

175

188

250

425

300

–150 150 –150 150 –175 175 –175 175 –175 175 –175 175

–175 175 –175 175 –225 225 –225 225 –225 225 –225 225

–200 200 –200 200 –250 250 –250 250 –250 250 –250 250

–300 300 –300 300 –350 350 –350 350 –350 350 –350 350

–450 450 –450 450 –450 450 –450 450 –450 450 –450 450

–350 350 –350 350 –400 400 –400 400 –450 450 –500 500

Cumulative error,

3 cycles

Cumulative error,

4 cycles

Cumulative error,

5 cycles

15, 16

Cumulative error,

6–10 cycles

^tERR_6–

10per

^tERR_11–

50per

–250

–425

Cumulative error,

11–50 cycles

DQS output access ^tDQSCK –300

time from CK/CK#

DQS read pream-

ble

^tRPRE

^tRPST

^tLZ₁

MIN = 0.9 × ^tCK

MAX = 1.1 × ^tCK

MIN = 0.4 × ^tCK

MAX = 0.6 × ^tCK

MIN = ^tAC (MIN)

MAX = ^tAC (MAX)

^tCK 17, 18,

19, 20

DQS read

postamble

CK/CK# to DQS

Low-Z

19, 21,

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;

V_DDQ= 1.8V 0.1V, V_DD= 1.8V 0.1V

AC Characteristics

-187E

-25E

-25

-3E

-3

-37E

-5E

Parameter

Symbol Min

Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes

DQS rising edge to

CK rising edge

^tDQSS

MIN = –0.25 × ^tCK

MAX = 0.25 × ^tCK

MIN = 0.35 × ^tCK

MAX = n/a

MIN = 0.35 × ^tCK

MAX = n/a

MIN = 0.2 × ^tCK

MAX = n/a

^tCK

DQS input-high

pulse width

^tDQSH

^tDQSL

^tDSS

DQS input-low

pulse width

DQS falling to CK

rising: setup time

DQS falling from

CK rising:

^tDSH

MIN = 0.2 × ^tCK

MAX = n/a

hold time

Write preamble

setup time

^tWPRES

^tWPRE

^tWPST

–

MIN = 0

MAX = n/a

MIN = 0.35 × ^tCK

MAX = n/a

MIN = 0.4 × ^tCK

MAX = 0.6 × ^tCK

23, 24

DQS write

preamble

^tCK

DQS write

postamble

^tCK 18, 25

^tCK

WRITE command

to first DQS

transition

MIN = WL - ^tDQSS

MAX = WL + ^tDQSS

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;

V_DDQ= 1.8V 0.1V, V_DD= 1.8V 0.1V

AC Characteristics

-187E

-25E

-25

-3E

-3

-37E

-5E

Parameter

Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes

DQ output access

time from CK/CK#

^tAC

–350

–

350

175

–400 400 –400 400 –450 450 –450 450 –500 500 –600 600

DQS–DQ skew,

DQS to last DQ

valid, per group,

per access

^tDQSQ

–

200

–

200

–

240

–

240

–

300

–

350

26, 27

DQ hold from next

DQS strobe

^tQHS

^tQH

–

250

–

300

–

300

–

340

–

340

–

400

–

450

DQ–DQS hold, DQS

to first DQ not val-

MIN = ^tHP - ^tQHS

MAX = n/a

26, 27,

CK/CK# to DQ, DQS

High-Z

^tHZ

^tLZ₂

MIN = n/a

19, 21,

MAX = ^tAC (MAX)

CK/CK# to DQ

Low-Z

MIN = 2 × ^tAC (MIN)

MAX = ^tAC (MAX)

MIN = ^tQH - ^tDQSQ

MAX = n/a

19, 21,

Data valid output

window

DVW

^tDSb

^tDHb

^tDSa

^tDHa

^tDIPW

26, 27

DQ and DM input

setup time to DQS

–

100

175

300

–

100

175

300

–

100

225

350

–

150

275

400

–

26, 30,

DQ and DM input

hold time to DQS

125

250

125

250

26, 30,

DQ and DM input

setup time to DQS

200

26, 30,

DQ and DM input

hold time to DQS

26, 30,

DQ and DM input

pulse width

MIN = 0.35 × ^tCK

MAX = n/a

^tCK 18, 32

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;

V_DDQ= 1.8V 0.1V, V_DD= 1.8V 0.1V

AC Characteristics

-187E

-25E

-25

-3E

-3

-37E

-5E

Parameter

Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes

Input setup time

Input hold time

Input setup time

Input hold time

Input pulse width

^tISb

^tIHb

^tISa

^tIHa

^tIPW

^tRC

125

200

325

0.6

–

175

250

375

0.6

–

175

250

375

0.6

–

200

275

400

0.6

–

200

275

400

0.6

–

250

375

500

0.6

–

350

475

600

0.6

–

31, 33

^tCK 18, 32

ACTIVATE-to-

ACTIVATE delay,

same bank

18, 34,

ACTIVATE-to-READ

or WRITE delay

^tRCD

^tRAS

13.125

–

12.5

–

ACTIVATE-to-

PRECHARGE delay

70K

18, 34,

PRECHARGE period

^tRP

^tRPA

13.125

–

12.5

–

18, 36

PRE-

<1Gb

CHARGE

ALL period

≥1Gb

17.5

18.75

ACTIVATE x4, x8

^tRRD

7.5

–

7.5

–

7.5

–

7.5

–

7.5

–

7.5

–

7.5

–

18, 37

-to-

x16

ACTIVATE

delay

different

bank

4-bank

activate

period

(≥1Gb)

x4, x8

x16

^tFAW

–

37.5

–

37.5

–

37.5

–

37.5

–

18, 38

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;

V_DDQ= 1.8V 0.1V, V_DD= 1.8V 0.1V

AC Characteristics

-187E

-25E

-25

-3E

-3

-37E

-5E

Parameter

Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes

Internal READ-to-

PRECHARGE delay

^tRTP

^tCCD

^tWR

7.5

–

7.5

–

7.5

–

7.5

–

7.5

–

7.5

–

7.5

–

^tCK

18, 37,

CAS#-to-CAS#

delay

18, 37

Write recovery

time

Write AP recovery

+ precharge time

^tDAL

^tWTR

^tMRD

^tRFC

^tWR +

^tRP

^tWR +

^tRP

^tWR +

^tRP

^tWR +

^tRP

^tWR +

^tRP

^tWR +

^tRP

^tWR +

^tRP

Internal WRITE-to-

READ delay

7.5

18, 37

LOAD MODE cycle

time

^tCK

REFRESH- 256Mb

105

–

105

–

105

–

105

–

105

–

105

–

105

–

18, 41

to-

ACTIVATE

or to

-REFRESH

interval

512Mb

1Gb

127.5

195

127.5

195

127.5

195

127.5

195

127.5

195

127.5

195

127.5

195

2Gb

Average periodic

refresh

(commercial)

^tREFI

^tREFI_IT

^tREFI_AT

^tDELAY

–

7.8

3.9

–

7.8

3.9

–

7.8

3.9

–

7.8

3.9

–

7.8

3.9

–

7.8

3.9

–

7.8

3.9

μs

18, 41

Average periodic

refresh

(industrial)

Average periodic

refresh

(automotive)

CKE LOW to CK,

CK# uncertainty

MIN limit = ^tIS + ^tCK + ^tIH

MAX limit = n/a

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;

V_DDQ= 1.8V 0.1V, V_DD= 1.8V 0.1V

AC Characteristics

-187E

-25E

-25

-3E

-3

-37E

-5E

Parameter

Symbol Min

Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes

Exit SELF REFRESH

to nonREAD

command

^tXSNR

MIN limit = ^tRFC (MIN) + 10

MAX limit = n/a

Exit SELF REFRESH

to READ command

^tXSRD

^tISXR

MIN limit = 200

MAX limit = n/a

MIN limit = ^tIS

^tCK

33, 43

Exit SELF REFRESH

timing reference

Exit active MR12 ^tXARD

MAX limit = n/a

–

^tCK

power-

down to

READ

= 0

MR12

= 1

10 -

8 - AL

7 - AL

–

7 - AL

6 - AL

command

Exit precharge

power-down and

active power-down

to any

^tXP

–

^tCK

nonREAD

command

CKE MIN

^tCKE

MIN = 3

^tCK 18, 44

HIGH/LOW time

MAX = n/a

Table 12: AC Operating Specifications and Conditions (Continued)

Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;

V_DDQ= 1.8V 0.1V, V_DD= 1.8V 0.1V

AC Characteristics

-187E

-25E

-25

-3E

-3

-37E

-5E

Parameter

Symbol Min Max Min Max Min Max Min Max Min Max Min Max Min Max Units Notes

ODT to power-

down entry latency

^tANPD

^tAXPD

–

^tCK

ODT power-down

exit latency

ODT turn-on delay ^tAOND

ODT turn-off delay ^tAOFD

2.5

^tCK 18, 45

ODT turn-on

^tAON

^tAC

MIN = ^tAC (MIN)

MAX = ^tAC (MAX) + 700

MIN = ^tAC (MIN)

MAX = ^tAC (MAX) + 1000

19, 46

(MIN) (MAX) MAX = ^tAC (MAX) + 600

2575

ODT turn-off

^tAOF

MIN = ^tAC (MIN)

47, 48

MAX = ^tAC (MAX) + 600

ODT turn-on

(power-down

mode)

^tAONPD

^tAC

2 ×

MIN = ^tAC (MIN) + 2000

MAX = 2 × ^tCK + ^tAC (MAX) + 1000

(MIN) ^tCK +

+ 2000 ^tAC

(MAX)

1000

ODT turn-off

(power-down

mode)

^tAOFPD

^tMOD

MIN = ^tAC (MIN) + 2000

MAX = 2.5 × ^tCK + ^tAC (MAX) + 1000

ODT enable from

MRS command

MIN = 12

MAX = n/a

18, 50

1. All voltages are referenced to V_SS.

Notes:

2. Tests for AC timing, I_DD, and electrical AC and DC characteristics may be conducted at nominal reference/supply

voltage levels, but the related specifications and the operation of the device are warranted for the full voltage

range specified. ODT is disabled for all measurements that are not ODT-specific.

3. Outputs measured with equivalent load (see Figure 14 (page 49)).

4. AC timing and I_DDtests may use a V_IL-to-V_IHswing of up to 1.0V in the test environment, and parameter specifica-

tions are guaranteed for the specified AC input levels under normal use conditions. The slew rate for the input

signals used to test the device is 1.0 V/ns for signals in the range between V_IL(AC)and V_IH(AC). Slew rates other than

1.0 V/ns may require the timing parameters to be derated as specified.

5. The AC and DC input level specifications are as defined in the SSTL_18 standard (that is, the receiver will effective-

ly switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal

does not ring back above [below] the DC input LOW [HIGH] level).

6. CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measured differentially).

7. Operating frequency is only allowed to change during self refresh mode (see Figure 77 (page 124)), precharge

power-down mode, or system reset condition (see Reset (page 125)). SSC allows for small deviations in operating

frequency, provided the SSC guidelines are satisfied.

8. The clock’s ^tCK (AVG) is the average clock over any 200 consecutive clocks and ^tCK (AVG) MIN is the smallest clock

rate allowed (except for a deviation due to allowed clock jitter). Input clock jitter is allowed provided it does not

exceed values specified. Also, the jitter must be of a random Gaussian distribution in nature.

9. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate

spread spectrum at a sweep rate in the range 8–60 kHz with an additional one percent ^tCK (AVG); however, the

spread spectrum may not use a clock rate below ^tCK (AVG) MIN or above ^tCK (AVG) MAX.

10. MIN (^tCL, ^tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time driven to the

device. The clock’s half period must also be of a Gaussian distribution; ^tCH (AVG) and ^tCL (AVG) must be met with

or without clock jitter and with or without duty cycle jitter. ^tCH (AVG) and ^tCL (AVG) are the average of any 200

consecutive CK falling edges. ^tCH limits may be exceeded if the duty cycle jitter is small enough that the absolute

half period limits (^tCH [ABS], ^tCL [ABS]) are not violated.

11. ^tHP (MIN) is the lesser of ^tCL and ^tCH actually applied to the device CK and CK# inputs; thus, ^tHP (MIN) ≥ the lesser

of ^tCL (ABS) MIN and ^tCH (ABS) MIN.

12. The period jitter (^tJITper) is the maximum deviation in the clock period from the average or nominal clock allowed

in either the positive or negative direction. JEDEC specifies tighter jitter numbers during DLL locking time. During

DLL lock time, the jitter values should be 20 percent less those than noted in the table (DLL locked).

13. The half-period jitter (^tJITdty) applies to either the high pulse of clock or the low pulse of clock; however, the two

cumulatively can not exceed ^tJITper.

14. The cycle-to-cycle jitter (^tJITcc) is the amount the clock period can deviate from one cycle to the next. JEDEC speci-

fies tighter jitter numbers during DLL locking time. During DLL lock time, the jitter values should be 20 percent

less than those noted in the table (DLL locked).

15. The cumulative jitter error (^tERR_nper), where n is 2, 3, 4, 5, 6–10, or 11–50 is the amount of clock time allowed to

consecutively accumulate away from the average clock over any number of clock cycles.

16. JEDEC specifies using ^tERR_6–10perwhen derating clock-related output timing (see notes 19 and 48). Micron requires

less derating by allowing ^tERR_5perto be used.

17. This parameter is not referenced to a specific voltage level but is specified when the device output is no longer

driving (^tRPST) or beginning to drive (^tRPRE).

18. The inputs to the DRAM must be aligned to the associated clock, that is, the actual clock that latches it in. Howev-

er, the input timing (in ns) references to the ^tCK (AVG) when determining the required number of clocks. The fol-

lowing input parameters are determined by taking the specified percentage times the ^tCK (AVG) rather than ^tCK:

^tIPW, ^tDIPW, ^tDQSS, ^tDQSH, ^tDQSL, ^tDSS, ^tDSH, ^tWPST, and ^tWPRE.

19. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by

the actual jitter error when input clock jitter is present; this will result in each parameter becoming larger. The

following parameters are required to be derated by subtracting ^tERR_5per(MAX): ^tAC (MIN), ^tDQSCK (MIN), ^tLZ_DQS

(MIN), ^tLZ_DQ(MIN), ^tAON (MIN); while the following parameters are required to be derated by subtracting

^tERR_5per(MIN): ^tAC (MAX), ^tDQSCK (MAX), ^tHZ (MAX), ^tLZ_DQS(MAX), ^tLZ_DQ(MAX), ^tAON (MAX). The parameter

^tRPRE (MIN) is derated by subtracting ^tJITper (MAX), while ^tRPRE (MAX), is derated by subtracting ^tJITper (MIN).

The parameter ^tRPST (MIN) is derated by subtracting ^tJITdty (MAX), while ^tRPST (MAX), is derated by subtracting

^tJITdty (MIN). Output timings that require ^tERR_5perderating can be observed to have offsets relative to the clock;

however, the total window will not degrade.

20. When DQS is used single-ended, the minimum limit is reduced by 100ps.

21. ^tHZ and ^tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not

referenced to a specific voltage level, but specify when the device output is no longer driving (^tHZ) or begins driv-

ing (^tLZ).

22. ^tLZ (MIN) will prevail over a ^tDQSCK (MIN) + ^tRPRE (MAX) condition.

23. This is not a device limit. The device will operate with a negative value, but system performance could be degra-

ded due to bus turnaround.

24. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS go-

ing from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous

WRITE was in progress, DQS could be HIGH during this time, depending on ^tDQSS.

25. The intent of the “Don’t Care” state after completion of the postamble is that the DQS-driven signal should either

be HIGH, LOW, or High-Z, and that any signal transition within the input switching region must follow valid input

requirements. That is, if DQS transitions HIGH (above V_IH[DC]min), then it must not transition LOW (below V_IH[DC]

)

prior to ^tDQSH (MIN).

26. Referenced to each output group: x4 = DQS with DQ[3:0]; x8 = DQS with DQ[7:0]; x16 = LDQS with DQ[7:0]; and

UDQS with DQ[15:8].

27. The data valid window is derived by achieving other specifications: ^tHP (^tCK/2), ^tDQSQ, and ^tQH (^tQH = ^tHP - ^tQHS).

The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can

be derived.

28. ^tQH = ^tHP - ^tQHS; the worst case ^tQH would be the lesser of ^tCL (ABS) MAX or ^tCH (ABS) MAX times ^tCK (ABS) MIN

- ^tQHS. Minimizing the amount of ^tCH (AVG) offset and value of ^tJITdty will provide a larger ^tQH, which in turn

will provide a larger valid data out window.

29. This maximum value is derived from the referenced test load. ^tHZ (MAX) will prevail over ^tDQSCK (MAX) + ^tRPST

(MAX) condition.

30. The values listed are for the differential DQS strobe (DQS and DQS#) with a differential slew rate of 2 V/ns (1 V/ns

for each signal). There are two sets of values listed: ^tDS_a, ^tDH_aand ^tDS_b, ^tDH_b. The ^tDS_a, ^tDH_avalues (for reference

only) are equivalent to the baseline values of ^tDS_b, ^tDH_bat V_REFwhen the slew rate is 2 V/ns, differentially. The

baseline values, ^tDS_b, ^tDH_b, are the JEDEC-defined values, referenced from the logic trip points. ^tDS_bis referenced

from V_IH(AC)for a rising signal and V_IL(AC)for a falling signal, while ^tDH_bis referenced from V_IL(DC)for a rising sig-

nal and V_IH(DC)for a falling signal. If the differential DQS slew rate is not equal to 2 V/ns, then the baseline values

must be derated by adding the values from Table 31 (page 62) and Table 32 (page 63). If the DQS differential

strobe feature is not enabled, then the DQS strobe is single-ended and the baseline values must be derated using

Table 33 (page 64). Single-ended DQS data timing is referenced at DQS crossing V_REF. The correct timing values

for a single-ended DQS strobe are listed in Table 34 (page 64)–Table 36 (page 65) on Table 34 (page 64),

Table 35 (page 65), and Table 36 (page 65); listed values are already derated for slew rate variations and con-

verted from baseline values to V_REFvalues.

31. V_IL/V_IHDDR2 overshoot/undershoot. See AC Overshoot/Undershoot Specification (page 55).

32. For each input signal—not the group collectively.

33. There are two sets of values listed for command/address: ^tIS_a, ^tIH_aand ^tIS_b, ^tIH_b. The ^tIS_a, ^tIH_avalues (for reference

only) are equivalent to the baseline values of ^tIS_b, ^tIH_bat V_REFwhen the slew rate is 1 V/ns. The baseline values,

^tIS_b, ^tIH_b, are the JEDEC-defined values, referenced from the logic trip points. ^tIS_bis referenced from V_IH(AC)for a

rising signal and V_IL(AC)for a falling signal, while ^tIH_bis referenced from V_IL(DC)for a rising signal and V_IH(DC)for a

falling signal. If the command/address slew rate is not equal to 1 V/ns, then the baseline values must be derated

by adding the values from Table 29 (page 58) and Table 30 (page 59).

34. This is applicable to READ cycles only. WRITE cycles generally require additional time due to ^tWR during auto pre-

charge.

35. READs and WRITEs with auto precharge are allowed to be issued before ^tRAS (MIN) is satisfied because ^tRAS lock-

out feature is supported in DDR2 SDRAM.

36. When a single-bank PRECHARGE command is issued, ^tRP timing applies. ^tRPA timing applies when the PRE-

CHARGE (ALL) command is issued, regardless of the number of banks open. For 8-bank devices (≥1Gb), ^tRPA (MIN)

= ^tRP (MIN) + ^tCK (AVG) (Table 12 (page 31) lists ^tRP [MIN] + ^tCK [AVG] MIN).

37. This parameter has a two clock minimum requirement at any ^tCK.

38. The ^tFAW (MIN) parameter applies to all 8-bank DDR2 devices. No more than four bank-ACTIVATE commands may

be issued in a given ^tFAW (MIN) period. ^tRRD (MIN) restriction still applies.

39. The minimum internal READ-to-PRECHARGE time. This is the time from which the last 4-bit prefetch begins to

when the PRECHARGE command can be issued. A 4-bit prefetch is when the READ command internally latches the

READ so that data will output CL later. This parameter is only applicable when ^tRTP/(2 × ^tCK) > 1, such as frequen-

cies faster than 533 MHz when ^tRTP = 7.5ns. If ^tRTP/(2 × ^tCK) ≤ 1, then equation AL + BL/2 applies. ^tRAS (MIN) has

to be satisfied as well. The DDR2 SDRAM will automatically delay the internal PRECHARGE command until ^tRAS

(MIN) has been satisfied.

40. ^tDAL = (nWR) + (^tRP/^tCK). Each of these terms, if not already an integer, should be rounded up to the next integer.

^tCK refers to the application clock period; nWR refers to the ^tWR parameter stored in the MR9–MR11. For exam-

ple, -37E at ^tCK = 3.75ns with ^tWR programmed to four clocks would have ^tDAL = 4 + (15ns/3.75ns) clocks =

4 + (4) clocks = 8 clocks.

41. The refresh period is 64ms (commercial) or 32ms (industrial and automotive). This equates to an average refresh

rate of 7.8125μs (commercial) or 3.9607μs (industrial and automotive). To ensure all rows of all banks are properly

refreshed, 8192 REFRESH commands must be issued every 64ms (commercial) or 32ms (industrial and automotive).

The JEDEC ^tRFC MAX of 70,000ns is not required as bursting of AUTO REFRESH commands is allowed.

42. ^tDELAY is calculated from ^tIS + ^tCK + ^tIH so that CKE registration LOW is guaranteed prior to CK, CK# being re-

moved in a system RESET condition (see Reset (page 125)).

43. ^tISXR is equal to ^tIS and is used for CKE setup time during self refresh exit, as shown in Figure 67 (page 116).

44. ^tCKE (MIN) of three clocks means CKE must be registered on three consecutive positive clock edges. CKE must re-

main at the valid input level the entire time it takes to achieve the three clocks of registration. Thus, after any

CKE transition, CKE may not transition from its valid level during the time period of ^tIS + 2 × ^tCK + ^tIH.

45. The half-clock of ^tAOFD’s 2.5 ^tCK assumes a 50/50 clock duty cycle. This half-clock value must be derated by the

amount of half-clock duty cycle error. For example, if the clock duty cycle was 47/53, ^tAOFD would actually be 2.5 -

0.03, or 2.47, for ^tAOF (MIN) and 2.5 + 0.03, or 2.53, for ^tAOF (MAX).

46. ODT turn-on time ^tAON (MIN) is when the device leaves High-Z and ODT resistance begins to turn on. ODT turn-

on time ^tAON (MAX) is when the ODT resistance is fully on. Both are measured from ^tAOND.

47. ODT turn-off time ^tAOF (MIN) is when the device starts to turn off ODT resistance. ODT turn off time ^tAOF (MAX)

is when the bus is in High-Z. Both are measured from ^tAOFD.

48. Half-clock output parameters must be derated by the actual ^tERR_5perand ^tJITdty when input clock jitter is present;

this will result in each parameter becoming larger. The parameter ^tAOF (MIN) is required to be derated by sub-

tracting both ^tERR_5per(MAX) and ^tJITdty (MAX). The parameter ^tAOF (MAX) is required to be derated by subtract-

ing both ^tERR_5per(MIN) and ^tJITdty (MIN).

49. The -187E maximum limit is 2 × ^tCK + ^tAC (MAX) + 1000 but it will likely be 3 x ^tCK + ^tAC (MAX) + 1000 in the

future.

50. Should use 8 ^tCK for backward compatibility.

51. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row ad-

dress may result in reduction of the product lifetime.

512Mb: x4, x8, x16 DDR2 SDRAM

AC and DC Operating Conditions

Table 13: Recommended DC Operating Conditions (SSTL_18)

All voltages referenced to V_SS

Parameter

Symbol

V_DD

Min

1.7

Nom

1.8

Max

1.9

Units Notes

Supply voltage

1, 2

2, 3

V_DDLsupply voltage

I/O supply voltage

I/O reference voltage

I/O termination voltage (system)

V_DDL

1.7

1.8

1.9

V_DDQ

V_REF(DC)

V_TT

1.7

1.8

1.9

0.49 × V_DDQ

V_REF(DC)- 40

0.50 × V_DDQ

V_REF(DC)

0.51 × V_DDQ

V_REF(DC)+ 40

1. V_DDand V_DDQmust track each other. V_DDQmust be ≤ V_DD

Notes:

2. V_SSQ= V_SSL= V_SS.

3. V_DDQtracks with V_DD; V_DDLtracks with V_DD

4. V_REFis expected to equal V_DDQ/2 of the transmitting device and to track variations in the

DC level of the same. Peak-to-peak noise (noncommon mode) on V_REFmay not exceed

1 percent of the DC value. Peak-to-peak AC noise on V_REFmay not exceed 2 percent

of V_REF(DC). This measurement is to be taken at the nearest V_REFbypass capacitor.

5. V_TTis not applied directly to the device. V_TTis a system supply for signal termination re-

sistors, is expected to be set equal to V_REF, and must track variations in the DC level of

V_REF

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512Mb: x4, x8, x16 DDR2 SDRAM

ODT DC Electrical Characteristics

Table 14: ODT DC Electrical Characteristics

All voltages are referenced to V_SS

Parameter

Symbol

Min

Nom

Max

Units

Notes

R_TTeffective impedance value for 75Ω setting

R_TT1(EFF)

1, 2

EMR (A6, A2) = 0, 1

_TTeffective impedance value for 150Ω setting

EMR (A6, A2) = 1, 0

_TTeffective impedance value for 50Ω setting

R_TT2(EFF)

R_TT3(EFF)

ΔVM

120

150

–

180

1, 2

EMR (A6, A2) = 1, 1

Deviation of VM with respect to V_DDQ/2

–6

1. R_TT1(EFF)and R_TT2(EFF)are determined by separately applying V_IH(AC)and V_IL(DC)to the ball

being tested, and then measuring current, I(V_IH[AC]), and I(V_IL[AC]), respectively.

Notes:

2. Minimum IT and AT device values are derated by six percent less when the devices oper-

ate between –40°C and 0°C (T_C).

3. Measure voltage (VM) at tested ball with no load.

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512Mb: x4, x8, x16 DDR2 SDRAM

Input Electrical Characteristics and Operating Conditions

Table 15: Input DC Logic Levels

All voltages are referenced to V_SS

Parameter

Symbol

V_IH(DC)

V_IL(DC)

Min

V_REF(DC)+ 125

–300

Max

Units

Input high (logic 1) voltage

Input low (logic 0) voltage

V_DDQ

V_REF(DC)- 125

1. V_DDQ+ 300mV allowed provided 1.9V is not exceeded.

Note:

Table 16: Input AC Logic Levels

All voltages are referenced to V_SS

Parameter

Symbol

V_IH(AC)

V_IL(AC)

Min

V_REF(DC)+ 250

V_REF(DC)+ 200

–300

Max

Units

Input high (logic 1) voltage (-37E/-5E)

V_DDQ

Input high (logic 1) voltage (-187E/-25E/-25/-3E/-3)

Input low (logic 0) voltage (-37E/-5E)

V_REF(DC)- 250

V_REF(DC)- 200

Input low (logic 0) voltage (-187E/-25E/-25/-3E/-3)

V_IL(AC)

–300

1. Refer to AC Overshoot/Undershoot Specification (page 55).

Note:

Figure 11: Single-Ended Input Signal Levels

1,150mV

V_IH(AC)

1,025mV

V_IH(DC)

936mV

918mV

900mV

882mV

864mV

V_REF+ AC noise

V_REF+ DC error

V_REF- DC error

V_REF- AC noise

775mV

V_IL(DC)

650mV

V_IL(AC)

1. Numbers in diagram reflect nominal DDR2-400/DDR2-533 values.

Note:

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512Mb: x4, x8, x16 DDR2 SDRAM

Input Electrical Characteristics and Operating Conditions

Table 17: Differential Input Logic Levels

All voltages referenced to V_SS

Parameter

Symbol

V_IN(DC)

V_ID(DC)

V_ID(AC)

V_IX(AC)

V_MP(DC)

Min

Max

V_DDQ

Units Notes

DC input signal voltage

–300

1, 6

2, 6

3, 6

DC differential input voltage

AC differential input voltage

AC differential cross-point voltage

Input midpoint voltage

250

500

V_DDQ

0.50 × V_DDQ- 175

850

0.50 × V_DDQ+ 175

950

1. V_IN(DC)specifies the allowable DC execution of each input of differential pair such as CK,

CK#, DQS, DQS#, LDQS, LDQS#, UDQS, UDQS#, and RDQS, RDQS#.

Notes:

2. V_ID(DC)specifies the input differential voltage |V_TR- V_CP| required for switching, where

_TRis the true input (such as CK, DQS, LDQS, UDQS) level and V_CPis the complementary

input (such as CK#, DQS#, LDQS#, UDQS#) level. The minimum value is equal to V_IH(DC)

_IL(DC). Differential input signal levels are shown in Figure 12.

3. V_ID(AC)specifies the input differential voltage |V_TR- V_CP| required for switching, where

_TRis the true input (such as CK, DQS, LDQS, UDQS, RDQS) level and V_CPis the comple-

mentary input (such as CK#, DQS#, LDQS#, UDQS#, RDQS#) level. The minimum value is

equal to V_IH(AC)- V_IL(AC), as shown in Table 16 (page 45).

4. The typical value of V_IX(AC)is expected to be about 0.5 × V_DDQof the transmitting device

and V_IX(AC)is expected to track variations in V_DDQ. V_IX(AC)indicates the voltage at which

differential input signals must cross, as shown in Figure 12.

5. V_MP(DC)specifies the input differential common mode voltage (V_TR+ V_CP)/2 where V_TRis

the true input (CK, DQS) level and V_CPis the complementary input (CK#, DQS#). V_MP(DC)

is expected to be approximately 0.5 × V_DDQ

6. V_DDQ+ 300mV allowed provided 1.9V is not exceeded.

Figure 12: Differential Input Signal Levels

2.1V

IN(DC)max

= 1.8V

DDQ

1.075V

0.9V

ID(DC)

IX(AC)

MP(DC)

ID(AC)

0.725V

–0.30V

IN(DC)min

1. TR and CP may not be more positive than V_DDQ+ 0.3V or more negative than V_SS- 0.3V.

Notes:

2. TR represents the CK, DQS, RDQS, LDQS, and UDQS signals; CP represents CK#, DQS#,

RDQS#, LDQS#, and UDQS# signals.

3. This provides a minimum of 850mV to a maximum of 950mV and is expected to be

_DDQ/2.

4. TR and CP must cross in this region.

5. TR and CP must meet at least V_ID(DC)minwhen static and is centered around V_MP(DC)

6. TR and CP must have a minimum 500mV peak-to-peak swing.

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Input Electrical Characteristics and Operating Conditions

7. Numbers in diagram reflect nominal values (V_DDQ= 1.8V).

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Output Electrical Characteristics and Operating Conditions

Table 18: Differential AC Output Parameters

Parameter

Symbol

V_OX(AC)

Vswing

Min

0.50 × V_DDQ- 125

1.0

Max

Units Notes

AC differential cross-point voltage

AC differential voltage swing

0.50 × V_DDQ+ 125

–

1. The typical value of V_OX(AC)is expected to be about 0.5 × V_DDQof the transmitting de-

vice and V_OX(AC)is expected to track variations in V_DDQ. V_OX(AC)indicates the voltage at

which differential output signals must cross.

Note:

Figure 13: Differential Output Signal Levels

V_DDQ

V_TR

Crossing point

V_OX

Vswing

V_CP

V_SSQ

Table 19: Output DC Current Drive

Parameter

Symbol

I_OH

I_OL

Value

–13.4

13.4

Units

Notes

1, 2, 4

2, 3, 4

Output MIN source DC current

Output MIN sink DC current

1. For I_OH(DC); V_DDQ= 1.7V, V_OUT= 1,420mV. (V_OUT- V_DDQ)/I_OHmust be less than 21Ω for val-

Notes:

ues of V_OUTbetween V_DDQand V_DDQ- 280mV.

2. For I_OL(DC); V_DDQ= 1.7V, V_OUT= 280mV. V_OUT/I_OLmust be less than 21Ω for values of V_OUT

between 0V and 280mV.

3. The DC value of V_REFapplied to the receiving device is set to V_TT.

4. The values of I_OH(DC)and I_OL(DC)are based on the conditions given in Notes 1 and 2. They

are used to test device drive current capability to ensure V_IH,minplus a noise margin and

V_IL,maxminus a noise margin are delivered to an SSTL_18 receiver. The actual current val-

ues are derived by shifting the desired driver operating point (see output IV curves)

along a 21Ω load line to define a convenient driver current for measurement.

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Output Electrical Characteristics and Operating Conditions

Table 20: Output Characteristics

Parameter

Min

Nom

Max

Units

Notes

1, 2

Output impedance

Pull-up and pull-down mismatch

Output slew rate

See Output Driver Characteristics (page 50)

–

1, 2, 3

1, 4, 5, 6

1.5

V/ns

1. Absolute specifications: 0°C ≤ T_C≤ +85°C; V_DDQ= 1.8V 0.1V, V_DD= 1.8V 0.1V.

2. Impedance measurement conditions for output source DC current: V_DDQ= 1.7V;

Notes:

_OUT= 1420mV; (V_OUT- V_DDQ)/I_OHmust be less than 23.4Ω for values of V_OUTbetween

V_DDQand V_DDQ- 280mV. The impedance measurement condition for output sink DC cur-

rent: V_DDQ= 1.7V; V_OUT= 280mV; V_OUT/I_OLmust be less than 23.4Ω for values of V_OUT

between 0V and 280mV.

3. Mismatch is an absolute value between pull-up and pull-down; both are measured at

the same temperature and voltage.

4. Output slew rate for falling and rising edges is measured between V_TT- 250mV and

V_TT+ 250mV for single-ended signals. For differential signals (DQS, DQS#), output slew

rate is measured between DQS - DQS# = –500mV and DQS# - DQS = 500mV. Output slew

rate is guaranteed by design but is not necessarily tested on each device.

5. The absolute value of the slew rate as measured from V_IL(DC)maxto V_IH(DC)minis equal to

or greater than the slew rate as measured from V_IL(AC)maxto V_IH(AC)min. This is guaran-

teed by design and characterization.

6. IT and AT devices require an additional 0.4 V/ns in the MAX limit when T_Cis between –

40°C and 0°C.

Figure 14: Output Slew Rate Load

= V

DDQ

25ȍ

Reference

point

Output

)

OUT

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Output Driver Characteristics

Figure 15: Full Strength Pull-Down Characteristics

120

100

0.0

0.5

1.0

V_OUT(V)

1.5

Table 21: Full Strength Pull-Down Current (mA)

Voltage (V)

0.0

Min

Nom

0.00

Max

0.00

4.30

0.1

5.63

7.95

0.2

8.60

11.30

16.52

22.19

27.59

32.39

36.45

40.38

44.01

47.01

49.63

51.71

53.32

54.9

15.90

23.85

31.80

39.75

47.70

55.55

62.95

69.55

75.35

80.35

84.55

87.95

90.70

93.00

95.05

97.05

99.05

101.05

0.3

12.90

16.90

20.40

23.28

25.44

26.79

27.67

28.38

28.96

29.46

29.90

30.29

30.65

30.98

31.31

31.64

31.96

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

56.03

57.07

58.16

59.27

60.35

1.6

1.7

1.8

1.9

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Output Driver Characteristics

Figure 16: Full Strength Pull-Up Characteristics

–20

–40

–60

–80

–100

–120

0.5

1.0

1.5

V_DDQ- V_OUT(V)

Table 22: Full Strength Pull-Up Current (mA)

Voltage (V)

0.0

Min

Nom

0.00

Max

0.00

0.1

–4.30

–5.63

–7.95

0.2

–8.60

–11.30

–16.52

–22.19

–27.59

–32.39

–36.45

–40.38

–44.01

–47.01

–49.63

–51.71

–53.32

–54.90

–56.03

–57.07

–58.16

–59.27

–60.35

–15.90

–23.85

–31.80

–39.75

–47.70

–55.55

–62.95

–69.55

–75.35

–80.35

–84.55

–87.95

–90.70

–93.00

–95.05

–97.05

–99.05

–101.05

0.3

–12.90

–16.90

–20.40

–23.28

–25.44

–26.79

–27.67

–28.38

–28.96

–29.46

–29.90

–30.29

–30.65

–30.98

–31.31

–31.64

–31.96

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

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Output Driver Characteristics

Figure 17: Reduced Strength Pull-Down Characteristics

0.0

0.5

1.0

_OUT(V)

1.5

Table 23: Reduced Strength Pull-Down Current (mA)

Voltage (V)

0.0

Min

0.00

Nom

0.00

Max

0.00

0.1

1.72

2.98

4.77

0.2

3.44

5.99

9.54

0.3

5.16

8.75

14.31

19.08

23.85

28.62

33.33

37.77

41.73

45.21

48.21

50.73

52.77

54.42

55.80

57.03

58.23

59.43

60.63

0.4

6.76

11.76

14.62

17.17

19.32

21.40

23.32

24.92

26.30

27.41

28.26

29.10

29.70

30.25

30.82

31.41

31.98

0.5

8.16

0.6

9.31

0.7

10.18

10.72

11.07

11.35

11.58

11.78

11.96

12.12

12.26

12.39

12.52

12.66

12.78

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

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Output Driver Characteristics

Figure 18: Reduced Strength Pull-Up Characteristics

–10

–20

–30

–40

–50

–60

–70

0.0

0.5

1.0

1.5

_DDQ- V_OUT(V)

Table 24: Reduced Strength Pull-Up Current (mA)

Voltage (V)

0.0

Min

Nom

0.00

Max

0.00

0.1

–1.72

–2.98

–4.77

0.2

–3.44

–5.99

–9.54

0.3

–5.16

–8.75

–14.31

–19.08

–23.85

–28.62

–33.33

–37.77

–41.73

–45.21

–48.21

–50.73

–52.77

–54.42

–55.8

0.4

–6.76

–11.76

–14.62

–17.17

–19.32

–21.40

–23.32

–24.92

–26.30

–27.41

–28.26

–29.10

–29.69

–30.25

–30.82

–31.42

–31.98

0.5

–8.16

0.6

–9.31

0.7

–10.18

–10.72

–11.07

–11.35

–11.58

–11.78

–11.96

–12.12

–12.26

–12.39

–12.52

–12.66

–12.78

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

–57.03

–58.23

–59.43

–60.63

1.7

1.8

1.9

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Power and Ground Clamp Characteristics

Power and ground clamps are provided on the following input-only balls: Address balls,

bank address balls, CS#, RAS#, CAS#, WE#, ODT, and CKE.

Table 25: Input Clamp Characteristics

Minimum Power Clamp Current

(mA)

Minimum Ground Clamp Current

(mA)

Voltage Across Clamp (V)

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

0.0

0.1

1.0

2.5

4.7

6.8

9.1

11.0

13.5

16.0

18.2

21.0

11.0

13.5

16.0

18.2

21.0

Figure 19: Input Clamp Characteristics

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8

Voltage Across Clamp (V)

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AC Overshoot/Undershoot Specification

Table 26: Address and Control Balls

Applies to address balls, bank address balls, CS#, RAS#, CAS#, WE#, CKE, and ODT

Specification

-3/-3E

Parameter

-187E

-25/-25E

-37E

-5E

Maximum peak amplitude allowed for overshoot area

(see Figure 20)

0.50V

Maximum peak amplitude allowed for undershoot area

(see Figure 21)

0.50V

Maximum overshoot area above V_DD(see Figure 20)

Maximum undershoot area below V_SS(see Figure 21)

0.5 Vns

0.66 Vns

0.80 Vns 1.00 Vns 1.33 Vns

Table 27: Clock, Data, Strobe, and Mask Balls

Applies to DQ, DQS, DQS#, RDQS, RDQS#, UDQS, UDQS#, LDQS, LDQS#, DM, UDM, and LDM

Specification

-3/-3E

Parameter

-187E

-25/-25E

-37E

-5E

Maximum peak amplitude allowed for overshoot area

(see Figure 20)

0.50V

Maximum peak amplitude allowed for undershoot area

(see Figure 21)

0.50V

Maximum overshoot area above V_DDQ(see Figure 20)

Maximum undershoot area below V_SSQ(see Figure 21)

0.19 Vns

0.23 Vns

0.28 Vns 0.38 Vns

Figure 20: Overshoot

Maximum amplitude

Overshoot area

DD DDQ

SS SSQ

Time (ns)

Figure 21: Undershoot

SS SSQ

Undershoot area

Maximum amplitude

Time (ns)

Table 28: AC Input Test Conditions

Parameter

Symbol

Min

Max

Units

Notes

Input setup timing measurement reference level address

balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT,

DM, UDM, LDM, and CKE

V_RS

See Note 2

1, 2, 3, 4

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AC Overshoot/Undershoot Specification

Table 28: AC Input Test Conditions (Continued)

Parameter

Symbol

Min

Max

Units

Notes

Input hold timing measurement reference level address

balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT,

DM, UDM, LDM, and CKE

V_RH

See Note 5

1, 3, 4, 5

Input timing measurement reference level (single-ended)

DQS for x4, x8; UDQS, LDQS for x16

V_REF(DC)

V_RD

V_DDQ× 0.49 V_DDQ× 0.51

V_IX(AC)

1, 3, 4, 6

Input timing measurement reference level (differential)

CK, CK# for x4, x8, x16; DQS, DQS# for x4, x8; RDQS,

RDQS# for x8; UDQS, UDQS#, LDQS, LDQS# for x16

1, 3, 7, 8, 9

1. All voltages referenced to V_SS.

2. Input waveform setup timing (^tIS_b) is referenced from the input signal crossing at the

_IH(AC)level for a rising signal and V_IL(AC)for a falling signal applied to the device under

Notes:

test, as shown in Figure 30 (page 68).

3. See Input Slew Rate Derating (page 57).

4. The slew rate for single-ended inputs is measured from DC level to AC level, V_IL(DC)to

V_IH(AC)on the rising edge and V_IL(AC)to V_IH(DC)on the falling edge. For signals referenced

to V_REF, the valid intersection is where the “tangent” line intersects V_REF, as shown in

Figure 23 (page 60), Figure 25 (page 61), Figure 27 (page 66), and Figure 29

(page 67).

5. Input waveform hold (^tIH_b) timing is referenced from the input signal crossing at the

V_IL(DC)level for a rising signal and V_IH(DC)for a falling signal applied to the device under

test, as shown in Figure 30 (page 68).

6. Input waveform setup timing (^tDS) and hold timing (^tDH) for single-ended data strobe is

referenced from the crossing of DQS, UDQS, or LDQS through the Vref level applied to

the device under test, as shown in Figure 32 (page 69).

7. Input waveform setup timing (^tDS) and hold timing (^tDH) when differential data strobe

is enabled is referenced from the cross-point of DQS/DQS#, UDQS/UDQS#, or LDQS/

LDQS#, as shown in Figure 31 (page 68).

8. Input waveform timing is referenced to the crossing point level (V_IX) of two input signals

(V_TRand V_CP) applied to the device under test, where V_TRis the true input signal and V_CP

is the complementary input signal, as shown in Figure 33 (page 69).

9. The slew rate for differentially ended inputs is measured from twice the DC level to

twice the AC level: 2 × V_IL(DC)to 2 × V_IH(AC)on the rising edge and 2 × V_IL(AC)to 2 ×

V_IH(DC)on the falling edge. For example, the CK/CK# would be –250mV to 500mV for CK

rising edge and would be 250mV to –500mV for CK falling edge.

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Input Slew Rate Derating

For all input signals, the total ^tIS (setup time) and ^tIH (hold time) required is calculated

by adding the data sheet ^tIS (base) and ^tIH (base) value to the Δ^tIS and Δ^tIH derating

value, respectively. Example: ^tIS (total setup time) = ^tIS (base) + Δ^tIS.

^tIS, the nominal slew rate for a rising signal, is defined as the slew rate between the last

crossing of V_REF(DC)and the first crossing of V_IH(AC)min. Setup nominal slew rate (^tIS) for

a falling signal is defined as the slew rate between the last crossing of V_REF(DC)and the

first crossing of V_IL(AC)max

If the actual signal is always earlier than the nominal slew rate line between shaded

“V_REF(DC)to AC region,” use the nominal slew rate for the derating value (Figure 22

(page 6±)).

If the actual signal is later than the nominal slew rate line anywhere between the shaded

“V_REF(DC)to AC region,” the slew rate of a tangent line to the actual signal from the AC

level to DC level is used for the derating value (see Figure 23 (page 6±)).

^tIH, the nominal slew rate for a rising signal, is defined as the slew rate between the last

crossing of V_IL(DC)maxand the first crossing of V_REF(DC). ^tIH, nominal slew rate for a fall-

ing signal, is defined as the slew rate between the last crossing of V_IH(DC)minand the first

crossing of V_REF(DC)

If the actual signal is always later than the nominal slew rate line between shaded “DC

to V_REF(DC)region,” use the nominal slew rate for the derating value (Figure 24

(page 61)).

If the actual signal is earlier than the nominal slew rate line anywhere between shaded

“DC to V_REF(DC)region,” the slew rate of a tangent line to the actual signal from the DC

level to V_REF(DC)level is used for the derating value (Figure 25 (page 61)).

Although the total setup time might be negative for slow slew rates (a valid input signal

will not have reached V_IH[AC]/V_IL[AC]at the time of the rising clock transition), a valid in-

put signal is still required to complete the transition and reach V_IH(AC)/V_IL(AC)

For slew rates in between the values listed in Table 29 (page 58) and Table 3±

(page 59), the derating values may obtained by linear interpolation.

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Input Slew Rate Derating

Table 29: DDR2-400/533 Setup and Hold Time Derating Values (^tIS and ^tIH)

CK, CK# Differential Slew Rate

2.0 V/ns 1.5 V/ns 1.0 V/ns

Command/Address Slew Rate (V/ns)

Δ^tIS

187

179

167

150

125

Δ^tIH

Δ^tIS

Δ^tIH

124

119

113

105

Δ^tIS

247

239

227

210

185

143

Δ^tIH

154

149

143

135

105

Units

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.25

0.2

0.15

0.1

217

209

197

180

155

113

–11

–14

–31

–54

–83

–125

–188

–292

–375

–500

–708

–1125

–25

–1

–43

–13

–37

–80

–145

–255

–320

–495

–770

–1420

–24

–53

–95

–158

–262

–345

–470

–678

–1095

–67

–7

–23

–65

–128

–232

–315

–440

–648

–1065

–110

–175

–285

–350

–525

–800

–1450

–50

–115

–225

–290

–465

–740

–1390

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Input Slew Rate Derating

Table 30: DDR2-667/800/1066 Setup and Hold Time Derating Values (^tIS and ^tIH)

Command/

Address Slew

Rate (V/ns)

CK, CK# Differential Slew Rate

2.0 V/ns

1.5 V/ns

1.0 V/ns

Δ^tIS

150

143

133

120

100

Δ^tIH

Δ^tIS

180

173

163

150

160

Δ^tIH

124

119

113

105

Δ^tIS

210

203

193

180

160

127

Δ^tIH

154

149

143

135

105

Units

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.25

0.2

0.15

0.1

–5

–14

–31

–54

–83

–125

–188

–292

–375

–500

–708

–13

–22

–34

–60

–100

–168

–200

–325

–517

–1000

–1

–24

–53

–95

–158

–262

–345

–470

–678

–1095

–4

–23

–65

–128

–232

–315

–440

–648

–1065

–30

–70

–138

–170

–295

–487

–970

–40

–108

–140

–265

–457

–940

–1125

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Input Slew Rate Derating

Figure 22: Nominal Slew Rate for ^tIS

CK#

DDQ

IH(AC)min

to AC

region

REF

IH(DC)min

Nominal

slew rate

REF(DC)

Nominal

slew rate

IL(DC)max

V_REFto AC

region

IL(AC)max

ǻTF

ǻTR

_(DC)- V_IL(AC)max

V_IH(AC)min- V

REF(DC)

Setup slew rate

rising signal

REF

Setup slew rate

falling signal

ǻTF

ǻTR

Figure 23: Tangent Line for ^tIS

CK#

DDQ

IH(AC)min

_REFto AC

region

Nominal

line

IH(DC)min

Tangent

line

REF(DC)

Tangent

line

IL(DC)max

Nominal

line

_REFto AC

region

IL(AC)max

ǻTF

ǻTR

Tangent line (V_IH[AC]min- V_REF[DC]

)

Setup slew rate

rising signal

ǻTR

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Input Slew Rate Derating

Figure 24: Nominal Slew Rate for ^tIH

CK#

DDQ

IH(AC)min

IH(DC)min

DC to V

REF

region

Nominal

slew rate

REF(DC)

Nominal

slew rate

DC to V

REF

region

IL(DC)max

IL(AC)max

ǻTF

ǻTR

Figure 25: Tangent Line for ^tIH

CK#

V_DDQ

V_IH(AC)min

Nominal

line

V_IH(DC)min

DC to V

REF

region

Tangent

line

V_REF(DC)

Tangent

line

Nominal

line

DC to V

REF

region

V_IL(DC)max

V_IL(AC)max

V_SS

ǻTR

ǻTF

Tangent line (V_REF[DC]- V_IL[DC]max

)

Tangent line (V_IH[DC]min- V_REF[DC])

Hold slew rate

rising signal

Hold slew rate

falling signal

ǻTR

ǻTF

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Input Slew Rate Derating

Table 31: DDR2-400/533 ^tDS, ^tDH Derating Values with Differential Strobe

All units are shown in picoseconds

DQS, DQS# Differential Slew Rate

1.8 V/ns 1.6 V/ns 1.4 V/ns

Slew

Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.2 V/ns

1.0 V/ns

0.8 V/ns

(V/ns) ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

125

–

–2

–

–1

–7

–

–11 –14 –11 –14

–7

–

–25 –31 –13 –19

–6

–

–31 –42 –19 –30

–18

–7

–

–43 –59 –31 –47 –19 –35

–23

–11

–

–74 –89 –62 –77 –50 –65 –38 –53

–127 –140 –115 –128 –103 –116

–

1. For all input signals, the total ^tDS and ^tDH required is calculated by adding the data

sheet value to the derating value listed in Table 31.

Notes:

2. ^tDS nominal slew rate for a rising signal is defined as the slew rate between the last

crossing of V_REF(DC)and the first crossing of V_IH(AC)min. ^tDS nominal slew rate for a falling

signal is defined as the slew rate between the last crossing of V_REF(DC)and the first cross-

ing of V_IL(AC)max. If the actual signal is always earlier than the nominal slew rate line be-

tween the shaded “V_REF(DC)to AC region,” use the nominal slew rate for the derating

value (see Figure 26 (page 66)). If the actual signal is later than the nominal slew rate

line anywhere between the shaded “V_REF(DC)to AC region,” the slew rate of a tangent

line to the actual signal from the AC level to DC level is used for the derating value (see

Figure 27 (page 66)).

3. ^tDH nominal slew rate for a rising signal is defined as the slew rate between the last

crossing of V_IL(DC)maxand the first crossing of V_REF(DC). ^tDH nominal slew rate for a falling

signal is defined as the slew rate between the last crossing of V_IH(DC)minand the first

crossing of V_REF(DC). If the actual signal is always later than the nominal slew rate line

between the shaded “DC level to V_REF(DC)region,” use the nominal slew rate for the de-

rating value (see Figure 28 (page 67)). If the actual signal is earlier than the nominal

slew rate line anywhere between shaded “DC to V_REF(DC)region,” the slew rate of a tan-

gent line to the actual signal from the DC level to V_REF(DC)level is used for the derating

value (see Figure 29 (page 67)).

4. Although the total setup time might be negative for slow slew rates (a valid input signal

will not have reached V_IH[AC]/V_IL[AC]at the time of the rising clock transition), a valid in-

put signal is still required to complete the transition and reach V_IH(AC)/V_IL(AC)

5. For slew rates between the values listed in this table, the derating values may be ob-

tained by linear interpolation.

6. These values are typically not subject to production test. They are verified by design and

characterization.

7. Single-ended DQS requires special derating. The values in Table 33 (page 64) are the

DQS single-ended slew rate derating with DQS referenced at V_REFand DQ referenced at

the logic levels ^tDS_band ^tDH_b. Converting the derated base values from DQ referenced

to the AC/DC trip points to DQ referenced to V_REFis listed in Table 35 (page 65) and

Table 36 (page 65). Table 35 provides the V_REF-based fully derated values for the DQ

(^tDS_aand ^tDH_a) for DDR2-533. Table 36 provides the V_REF-based fully derated values for

the DQ (^tDS_aand ^tDH_a) for DDR2-400.

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Input Slew Rate Derating

Table 32: DDR2-667/800/1066 ^tDS, ^tDH Derating Values with Differential Strobe

All units are shown in picoseconds

DQS, DQS# Differential Slew Rate

1.8 V/ns 1.6 V/ns 1.4 V/ns

Slew

Rate

2.8 V/ns

2.4 V/ns

2.0 V/ns

1.2 V/ns

1.0 V/ns

0.8 V/ns

(V/ns) ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

100

112

124

136

103

148 111 160 123 172 135

115

127 102 139 114

–5

–14

–5

–14

–5

–14

–2

–13 –31 –13 –31 –13 –31

–1

–19

–7

–22 –54 –22 –54 –22 –54 –10 –42

–30

–18

–47

–6

–34 –83 –34 –83 –34 –83 –22 –71 –10 –59

–35

–23

–65

–11

–53

–60 –125 –60 –125 –60 –125 –48 –113 –36 –101 –24 –89 –12 –77

0.4 –100 –188 –100 –188 –100 –188 –88 –176 –76 –164 –64 –152 –52 –140 –40 –128 –28 –116

1. For all input signals the total ^tDS and ^tDH required is calculated by adding the data

Notes:

sheet value to the derating value listed in Table 32.

2. ^tDS nominal slew rate for a rising signal is defined as the slew rate between the last

crossing of V_REF(DC)and the first crossing of V_IH(AC)min. ^tDS nominal slew rate for a falling

signal is defined as the slew rate between the last crossing of V_REF(DC)and the first cross-

ing of V_IL(AC)max. If the actual signal is always earlier than the nominal slew rate line be-

tween the shaded “V_REF(DC)to AC region,” use the nominal slew rate for the derating

value (see Figure 26 (page 66)). If the actual signal is later than the nominal slew rate

line anywhere between shaded “V_REF(DC)to AC region,” the slew rate of a tangent line

to the actual signal from the AC level to DC level is used for the derating value (see Fig-

ure 27 (page 66)).

3. ^tDH nominal slew rate for a rising signal is defined as the slew rate between the last

crossing of V_IL(DC)maxand the first crossing of V_REF(DC). ^tDH nominal slew rate for a falling

signal is defined as the slew rate between the last crossing of V_IH(DC)minand the first

crossing of V_REF(DC). If the actual signal is always later than the nominal slew rate line

between the shaded “DC level to V_REF(DC)region,” use the nominal slew rate for the de-

rating value (see Figure 28 (page 67)). If the actual signal is earlier than the nominal

slew rate line anywhere between the shaded “DC to V_REF(DC)region,” the slew rate of a

tangent line to the actual signal from the DC level to V_REF(DC)level is used for the derat-

ing value (see Figure 29 (page 67)).

4. Although the total setup time might be negative for slow slew rates (a valid input signal

will not have reached V_IH[AC]/V_IL[AC]at the time of the rising clock transition), a valid in-

put signal is still required to complete the transition and reach V_IH(AC)/V_IL(AC)

5. For slew rates between the values listed in this table, the derating values may be ob-

tained by linear interpolation.

6. These values are typically not subject to production test. They are verified by design and

characterization.

7. Single-ended DQS requires special derating. The values in Table 33 (page 64) are the

DQS single-ended slew rate derating with DQS referenced at V_REFand DQ referenced at

the logic levels ^tDS_band ^tDH_b. Converting the derated base values from DQ referenced

to the AC/DC trip points to DQ referenced to V_REFis listed in Table 34 (page 64). Ta-

ble 34 provides the V_REF-based fully derated values for the DQ (^tDS_aand ^tDH_a) for

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Input Slew Rate Derating

DDR2-667. It is not advised to operate DDR2-800 and DDR2-1066 devices with single-

ended DQS; however, Table 33 would be used with the base values.

Table 33: Single-Ended DQS Slew Rate Derating Values Using ^tDS_band ^tDH_b

Reference points indicated in bold; Derating values are to be used with base ^tDS_b- and ^tDH_b--specified values

DQS Single-Ended Slew Rate Derated (at V_REF

1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns

)

2.0 V/ns

1.8 V/ns

0.6 V/ns

0.4 V/ns

DQ (V/ns)

^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH

2.0

1.5

1.0

130 53 130 53 130 53 130 53 130 53 145 48 155 45 165 41 175 38

32 112 27 122 24 132 20 142 17

30 –10 30 –10 30 –10 30 –10 30 –10

25 –24 25 –24 25 –24 25 –24 25 –24

55 –18 65 –22 75 –25

50 –32 60 –36 70 –39

45 –15

0.9

0.8

0.7

0.6

0.5

0.4

40 –29

17 –41 17 –41 17 –41 17 –41 17 –41 32 –46 42 –49 52 –53 61 –56

–64

–64 20 –69 30 –72 40 –75 50 –79

–93 –98 18 –102 28 –105 38 –108

–147 17 –150

–78 –198 –78 –198 –78 –198 –78 –198 –78 –198 –63 –203 –53 –206 –43 –210 –33 –213

–7

–93

–7

–93

–7

–93

–7

–93

–7

–28 –135 –28 –135 –28 –135 –28 –135 –28 –135 –13 –140 –3 –143

Table 34: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V_REF) at DDR2-667

Reference points indicated in bold

DQS Single-Ended Slew Rate Derated (at V_REF

1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns

DQ (V/ns) ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH

)

2.0 V/ns

1.8 V/ns

0.6 V/ns

0.4 V/ns

2.0

1.5

1.0

330 291 330 291 330 291 330 291 330 291 345 286 355 282 365 29 375 276

330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 279 375 275

330 290 330 290 330 290 330 290 330 290

347 290 347 290 347 290 347 290 347 290

355 282 365 278 375 275

372 282 382 278 392 275

345 285

0.9

0.8

0.7

0.6

0.5

0.4

362 285

367 290 367 290 367 290 367 290 367 290 382 285 392 282 402 278 412 275

391 290 391 290 391 290 391 290 391 290 406 285 416 281 426 278 436 275

426 290 426 290 426 290 426 290 426 290 441 285 451 282 461 278 471 275

472 290 472 290 472 290 472 290 472 290 487 285 497 282 507 278 517 275

522 289 522 289 522 289 522 289 522 289 537 284 547 281 557 278 567 274

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Input Slew Rate Derating

Table 35: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V_REF) at DDR2-533

Reference points indicated in bold

DQS Single-Ended Slew Rate Derated (at V_REF

1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns

DQ (V/ns) ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH

)

2.0 V/ns

1.8 V/ns

0.6 V/ns

0.4 V/ns

2.0

1.5

1.0

355 341 355 341 355 341 355 341 355 341 370 336 380 332 390 329 400 326

364 340 364 340 364 340 364 340 364 340 379 335 389 332 399 329 409 325

380 340 380 340 380 340 380 340 380 340

402 340 402 340 402 340 402 340 402 340

405 332 415 328 425 325

427 332 437 328 447 325

395 335

0.9

0.8

0.7

0.6

0.5

0.4

417 335

429 340 429 340 429 340 429 340 429 340 444 335 454 332 464 328 474 325

463 340 463 340 463 340 463 340 463 340 478 335 488 331 498 328 508 325

510 340 510 340 510 340 510 340 510 340 525 335 535 332 545 328 555 325

572 340 572 340 572 340 572 340 572 340 587 335 597 332 607 328 617 325

647 339 647 339 647 339 647 339 647 339 662 334 672 331 682 328 692 324

Table 36: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at V_REF) at DDR2-400

Reference points indicated in bold

DQS Single-Ended Slew Rate Derated (at V_REF

1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns

DQ (V/ns) ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH ^tDS ^tDH

)

2.0 V/ns

1.8 V/ns

0.6 V/ns

0.4 V/ns

2.0

1.5

1.0

405 391 405 391 405 391 405 391 405 391 420 386 430 382 440 379 450 376

414 390 414 390 414 390 414 390 414 390 429 385 439 382 449 379 459 375

430 390 430 390 430 390 430 390 430 390

452 390 452 390 452 390 452 390 452 390

455 382 465 378 475 375

477 382 487 378 497 375

445 385

0.9

0.8

0.7

0.6

0.5

0.4

467 385

479 390 479 390 479 390 479 390 479 390 494 385 504 382 514 378 524 375

513 390 513 390 513 390 513 390 513 390 528 385 538 381 548 378 558 375

560 390 560 390 560 390 560 390 560 390 575 385 585 382 595 378 605 375

622 390 622 390 622 390 622 390 622 390 637 385 647 382 657 378 667 375

697 389 697 389 697 389 697 389 697 389 712 384 722 381 732 378 742 374

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Input Slew Rate Derating

Figure 26: Nominal Slew Rate for ^tDS

DQS

DQS#

V_DDQ

V_IH(AC)min

V_REFto AC

region

V_IH(DC)min

Nominal

slew rate

V_REF(DC)

Nominal

slew rate

V_IL(DC)max

_REFto AC

region

V_IL(AC)max

V_SS

ǻTF

ǻTR

V_REF(DC)- V_IL(AC)max

V_IH(AC)min

V_REF(DC)

Setup slew rate

falling signal

Setup slew rate

rising signal

ǻTF

ǻTR

1. DQS, DQS# signals must be monotonic between V_IL(DC)maxand V_IH(DC)min

Note:

Figure 27: Tangent Line for ^tDS

DQS

DQS#

DDQ

IH(AC)min

Nominal

line

V_REFto AC

region

IH(DC)min

Tangent line

REF(DC)

Tangent line

IL(DC)max

IL(AC)max

Nominal line

V_REFto AC

region

ǻTR

ǻTF

Tangent line (V

- V )

IL[AC]max

Tangent line (V

- V

)

REF[DC]

IH[AC]min

Setup slew rate

falling signal

Setup slew rate

rising signal

ǻTF

ǻTR

1. DQS, DQS# signals must be monotonic between V_IL(DC)maxand V_IH(DC)min

Note:

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Input Slew Rate Derating

Figure 28: Nominal Slew Rate for ^tDH

DQS

DQS#

V_DDQ

V_IH(AC)min

V_IH(DC)min

DC to V_REF

region

Nominal

slew rate

V_REF(DC)

Nominal

slew rate

DC to V_REF

region

V_IL(DC)max

V_IL(AC)max

V_SS

ǻTF

ǻTR

Hold slew rate

V_REF(DC)

V_IL(DC)max

V_IH(DC)min

V_REF(DC)

Hold slew rate

rising signal

falling signal

1. DQS, DQS# signals must be monotonic between V_IL(DC)maxand V_IH(DC)min

Note:

Figure 29: Tangent Line for ^tDH

DQS

DQS#

V_DDQ

V_IH(AC)min

Nominal

line

V_IH(DC)min

DC to V_REF

region

Tangent

line

V_REF(DC)

Tangent

line

DC to V_REF

region

Nominal

line

V_IL(DC)max

V_IL(AC)max

V_SS

ǻTF

ǻTR

Tangent line (V_REF[DC]- V_IL[DC]max

)

Tangent line (V_IH[DC]min- V_REF[DC]

)

Hold slew rate

rising signal

Hold slew rate

falling signal

ǻTR

ǻTF

1. DQS, DQS# signals must be monotonic between V_IL(DC)maxand V_IH(DC)min

Note:

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Input Slew Rate Derating

Figure 30: AC Input Test Signal Waveform Command/Address Balls

CK#

Logic levels

DDQ

IH(AC)min

IH(DC)min

REF(DC)

IL(DC)min

IL(AC)min

SSQ

levels

REF

Figure 31: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential)

DQS#

DQS

Logic levels

DDQ

IH(AC)min

IH(DC)min

REF(DC)

VIL(DC)max

VIL(AC)max

SSQ

levels

REF

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Input Slew Rate Derating

Figure 32: AC Input Test Signal Waveform for Data with DQS (Single-Ended)

REF

DQS

Logic levels

V_DDQ

V_IH(AC)min

V_IH(DC)min

V_REF(DC)

V_IL(DC)max

V_IL(AC)max

V_SSQ

levels

REF

Figure 33: AC Input Test Signal Waveform (Differential)

DDQ

Crossing point

Vswing

SSQ

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Commands

Truth Tables

The following tables provide a quick reference of available DDR2 SDRAM commands,

including CKE power-down modes and bank-to-bank commands.

Table 37: Truth Table – DDR2 Commands

Notes: 1–3 apply to the entire table

CKE

Previous Current

BA2–

Function

Cycle

CS# RAS# CAS# WE#

BA0 An–A11 A10 A9–A0 Notes

LOAD MODE

REFRESH

OP code

4, 6

SELF REFRESH entry

SELF REFRESH exit

4, 7

Single bank

PRECHARGE

All banks PRECHARGE

Bank ACTIVATE

WRITE

Row address

Column

address

Column 4, 5, 6,

address

Column 4, 5, 6,

address

Column 4, 5, 6,

address

Column 4, 5, 6,

WRITE with auto

precharge

Column

address

READ

Column

address

READ with auto

precharge

Column

address

NO OPERATION

Device DESELECT

Power-down entry

Power-down exit

1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at

the rising edge of the clock.

Notes:

2. The state of ODT does not affect the states described in this table. The ODT function is

not available during self refresh. See ODT Timing (page 127) for details.

3. “X” means “H or L” (but a defined logic level) for valid I_DDmeasurements.

4. BA2 is only applicable for densities ≥1Gb.

5. An n is the most significant address bit for a given density and configuration. Some larg-

er address bits may be “Don’t Care” during column addressing, depending on density

and configuration.

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Commands

6. Bank addresses (BA) determine which bank is to be operated upon. BA during a LOAD

MODE command selects which mode register is programmed.

7. SELF REFRESH exit is asynchronous.

8. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See Figure 47

(page 96) and Figure 59 (page 107) for other restrictions and details.

9. The power-down mode does not perform any REFRESH operations. The duration of

power-down is limited by the refresh requirements outlined in the AC parametric sec-

tion.

Table 38: Truth Table – Current State Bank n – Command to Bank n

Notes: 1–6 apply to the entire table

Current

State

CS#

RAS#

CAS#

WE#

Command/Action

DESELECT (NOP/continue previous operation)

NO OPERATION (NOP/continue previous operation)

ACTIVATE (select and activate row)

REFRESH

Notes

Any

Idle

LOAD MODE

Row active

READ (select column and start READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE (deactivate row in bank or banks)

READ (select column and start new READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE (start PRECHARGE)

Read (auto

precharge

disabled)

8, 10

Write

READ (select column and start READ burst)

WRITE (select column and start new WRITE burst)

PRECHARGE (start PRECHARGE)

(auto pre-

charge disa-

bled)

1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after ^tXSNR has been

Notes:

met (if the previous state was self refresh).

2. This table is bank-specific, except where noted (the current state is for a specific bank

and the commands shown are those allowed to be issued to that bank when in that

state). Exceptions are covered in the notes below.

3. Current state definitions:

The bank has been precharged, ^tRP has been met, and any READ burst is com-

plete.

Idle:

Row

A row in the bank has been activated, and ^tRCD has been met. No data bursts/

active: accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled and has not yet

terminated.

Write: A WRITE burst has been initiated with auto precharge disabled and has not yet

terminated.

4. The following states must not be interrupted by a command issued to the same bank.

Issue DESELECT or NOP commands, or allowable commands to the other bank, on any

clock edge occurring during these states. Allowable commands to the other bank are

determined by its current state and this table, and according to Table 39 (page 73).

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Commands

Precharge:

Starts with registration of a PRECHARGE command and ends when

^tRP is met. After ^tRP is met, the bank will be in the idle state.

Read with auto Starts with registration of a READ command with auto precharge

precharge

enabled:

enabled and ends when ^tRP has been met. After ^tRP is met, the

bank will be in the idle state.

Row activate:

Starts with registration of an ACTIVATE command and ends when

^tRCD is met. After ^tRCD is met, the bank will be in the row active

state.

Write with auto Starts with registration of a WRITE command with auto precharge

precharge

enabled:

enabled and ends when ^tRP has been met. After ^tRP is met, the

bank will be in the idle state.

5. The following states must not be interrupted by any executable command (DESELECT or

NOP commands must be applied on each positive clock edge during these states):

Refresh:

Starts with registration of a REFRESH command and ends when ^tRFC is

met. After ^tRFC is met, the DDR2 SDRAM will be in the all banks idle

state.

Accessing

mode

Starts with registration of the LOAD MODE command and ends when

^tMRD has been met. After ^tMRD is met, the DDR2 SDRAM will be in the

all banks idle state.

Precharge

all:

Starts with registration of a PRECHARGE ALL command and ends when

^tRP is met. After ^tRP is met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle and bursts are not in progress.

8. READs or WRITEs listed in the Command/Action column include READs or WRITEs with

auto precharge enabled and READs or WRITEs with auto precharge disabled.

9. May or may not be bank-specific; if multiple banks are to be precharged, each must be

in a valid state for precharging.

10. A WRITE command may be applied after the completion of the READ burst.

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Commands

Table 39: Truth Table – Current State Bank n – Command to Bank m

Notes: 1–6 apply to the entire table

Current State

CS#

RAS# CAS# WE#

Command/Action

DESELECT (NOP/continue previous operation)

NO OPERATION (NOP/continue previous operation)

Any command otherwise allowed to bank m

ACTIVATE (select and activate row)

READ (select column and start READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE

Notes

Any

Idle

Row

active, active,

or precharge

Read (auto

precharge

disabled)

ACTIVATE (select and activate row)

READ (select column and start new READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE

7, 8

Write (auto

precharge

disabled)

ACTIVATE (select and activate row)

READ (select column and start READ burst)

WRITE (select column and start new WRITE burst)

PRECHARGE

7, 9, 10

Read (with

auto

precharge)

ACTIVATE (select and activate row)

READ (select column and start new READ burst)

WRITE (select column and start WRITE burst)

PRECHARGE

7, 8

Write (with

auto

precharge)

ACTIVATE (select and activate row)

READ (select column and start READ burst)

WRITE (select column and start new WRITE burst)

PRECHARGE

7, 10

1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after ^tXSNR has been

Notes:

met (if the previous state was self refresh).

2. This table describes an alternate bank operation, except where noted (the current state

is for bank n and the commands shown are those allowed to be issued to bank m, as-

suming that bank m is in such a state that the given command is allowable). Exceptions

are covered in the notes below.

3. Current state definitions:

Idle:

The bank has been precharged, ^tRP has been met, and any READ

burst is complete.

Row active:

Read:

A row in the bank has been activated and ^tRCD has been met.

No data bursts/accesses and no register accesses are in progress.

A READ burst has been initiated with auto precharge disabled

and has not yet terminated.

Write:

A WRITE burst has been initiated with auto precharge disabled

and has not yet terminated.

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Commands

READ with auto

The READ with auto precharge enabled or WRITE with auto pre-

precharge enabled/ charge enabled states can each be broken into two parts: the ac-

WRITE with auto cess period and the precharge period. For READ with auto pre-

precharge enabled: charge, the precharge period is defined as if the same burst was

executed with auto precharge disabled and then followed with

the earliest possible PRECHARGE command that still accesses all

of the data in the burst. For WRITE with auto precharge, the pre-

charge period begins when ^tWR ends, with ^tWR measured as if

auto precharge was disabled. The access period starts with regis-

tration of the command and ends where the precharge period

(or ^tRP) begins. This device supports concurrent auto precharge

such that when a READ with auto precharge is enabled or a

WRITE with auto precharge is enabled, any command to other

banks is allowed, as long as that command does not interrupt

the read or write data transfer already in process. In either case,

all other related limitations apply (contention between read da-

ta and write data must be avoided).

The minimum delay from a READ or WRITE command with auto precharge enabled to

a command to a different bank is summarized in Table 40 (page 74).

4. REFRESH and LOAD MODE commands may only be issued when all banks are idle.

5. Not used.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with

auto precharge enabled and READs or WRITEs with auto precharge disabled.

8. A WRITE command may be applied after the completion of the READ burst.

9. Requires appropriate DM.

10. The number of clock cycles required to meet ^tWTR is either two or ^tWTR/^tCK, whichever

is greater.

Table 40: Minimum Delay with Auto Precharge Enabled

Minimum Delay

From Command (Bank n)

To Command (Bank m)

READ or READ with auto precharge

WRITE or WRITE with auto precharge

PRECHARGE or ACTIVATE

(with Concurrent Auto Precharge) Units

WRITE with auto precharge

(CL - 1) + (BL/2) + ^tWTR

^tCK

(BL/2)

(BL/2) + 2

READ with auto precharge

READ or READ with auto precharge

WRITE or WRITE with auto precharge

PRECHARGE or ACTIVATE

DESELECT

The DESELECT function (CS# HIGH) prevents new commands from being executed by

the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in

progress are not affected. DESELECT is also referred to as COMMAND INHIBIT.

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Commands

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to

perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This prevents unwanted

commands from being registered during idle or wait states. Operations already in pro-

gress are not affected.

LOAD MODE (LM)

ACTIVATE

The mode registers are loaded via bank address and address inputs. The bank address

balls determine which mode register will be programmed. See Mode Register (MR)

(page 76). The LM command can only be issued when all banks are idle, and a subse-

quent executable command cannot be issued until ^tMRD is met.

The ACTIVATE command is used to open (or activate) a row in a particular bank for a

subsequent access. The value on the bank address inputs determines the bank, and the

address inputs select the row. This row remains active (or open) for accesses until a pre-

charge command is issued to that bank. A precharge command must be issued before

opening a different row in the same bank.

READ

The READ command is used to initiate a burst read access to an active row. The value

on the bank address inputs determine the bank, and the address provided on address

inputs A±–Ai (where Ai is the most significant column address bit for a given configura-

tion) selects the starting column location. The value on input A1± determines whether

or not auto precharge is used. If auto precharge is selected, the row being accessed will

be precharged at the end of the read burst; if auto precharge is not selected, the row will

remain open for subsequent accesses.

DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command

to be issued prior to ^tRCD (MIN) by delaying the actual registration of the READ/WRITE

command to the internal device by AL clock cycles.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value

on the bank select inputs selects the bank, and the address provided on inputs A±–Ai

(where Ai is the most significant column address bit for a given configuration) selects

the starting column location. The value on input A1± determines whether or not auto

precharge is used. If auto precharge is selected, the row being accessed will be pre-

charged at the end of the WRITE burst; if auto precharge is not selected, the row will

remain open for subsequent accesses.

DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command

to be issued prior to ^tRCD (MIN) by delaying the actual registration of the READ/WRITE

command to the internal device by AL clock cycles.

Input data appearing on the DQ is written to the memory array subject to the DM input

logic level appearing coincident with the data. If a given DM signal is registered LOW,

the corresponding data will be written to memory; if the DM signal is registered HIGH,

the corresponding data inputs will be ignored, and a WRITE will not be executed to that

byte/column location (see Figure 64 (page 112)).

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Mode Register (MR)

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or

the open row in all banks. The bank(s) will be available for a subsequent row activation

a specified time (^tRP) after the PRECHARGE command is issued, except in the case of

concurrent auto precharge, where a READ or WRITE command to a different bank is al-

lowed as long as it does not interrupt the data transfer in the current bank and does not

violate any other timing parameters. After a bank has been precharged, it is in the idle

state and must be activated prior to any READ or WRITE commands being issued to

that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle

state) or if the previously open row is already in the process of precharging. However,

the precharge period will be determined by the last PRECHARGE command issued to

the bank.

REFRESH

REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to

CAS#-before-RAS# (CBR) REFRESH. All banks must be in the idle mode prior to issuing

a REFRESH command. This command is nonpersistent, so it must be issued each time

a refresh is required. The addressing is generated by the internal refresh controller. This

makes the address bits a “Don’t Care” during a REFRESH command.

SELF REFRESH

The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if

the rest of the system is powered down. When in the self refresh mode, the DDR2

SDRAM retains data without external clocking. All power supply inputs (including Vref)

must be maintained at valid levels upon entry/exit and during SELF REFRESH opera-

tion.

The SELF REFRESH command is initiated like a REFRESH command except CKE is

LOW. The DLL is automatically disabled upon entering self refresh and is automatically

enabled upon exiting self refresh.

Mode Register (MR)

The mode register is used to define the specific mode of operation of the DDR2 SDRAM.

This definition includes the selection of a burst length, burst type, CAS latency, operat-

ing mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 34

(page 77). Contents of the mode register can be altered by re-executing the LOAD

MODE (LM) command. If the user chooses to modify only a subset of the MR variables,

all variables must be programmed when the command is issued.

The MR is programmed via the LM command and will retain the stored information un-

til it is programmed again or until the device loses power (except for bit M8, which is

self-clearing). Reprogramming the mode register will not alter the contents of the mem-

ory array, provided it is performed correctly.

The LM command can only be issued (or reissued) when all banks are in the precharged

state (idle state) and no bursts are in progress. The controller must wait the specified

time ^tMRD before initiating any subsequent operations such as an ACTIVATE com-

mand. Violating either of these requirements will result in an unspecified operation.

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Mode Register (MR)

Burst Length

Burst length is defined by bits M±–M2, as shown in Figure 34. Read and write accesses

to the DDR2 SDRAM are burst-oriented, with the burst length being programmable to

either four or eight. The burst length determines the maximum number of column loca-

tions that can be accessed for a given READ or WRITE command.

When a READ or WRITE command is issued, a block of columns equal to the burst

length is effectively selected. All accesses for that burst take place within this block,

meaning that the burst will wrap within the block if a boundary is reached. The block is

uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most

significant column address bit for a given configuration). The remaining (least signifi-

cant) address bit(s) is (are) used to select the starting location within the block. The pro-

grammed burst length applies to both read and write bursts.

Figure 34: MR Definition

BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

16 15 14

12 11 10

PD WR

Mode Register (Mx)

DLL TM CAS# Latency BT Burst Length

M2 M1 M0

Burst Length

M12 PD Mode

Mode

Normal

Test

Fast exit

(normal)

Reserved

Slow exit

(low power)

DLL Reset

Reserved

Yes

Write Recovery

M11 M10 M9

Reserved

Burst Type

Sequential

Interleaved

CAS Latency (CL)

M6 M5 M4

Reserved

M15 M14

Mode Register Definition

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

1. M16 (BA2) is only applicable for densities ≥1Gb, reserved for future use, and must be

Notes:

programmed to “0.”

2. Mode bits (Mn) with corresponding address balls (An) greater than M12 (A12) are re-

served for future use and must be programmed to “0.”

3. Not all listed WR and CL options are supported in any individual speed grade.

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Mode Register (MR)

Burst Type

Accesses within a given burst may be programmed to be either sequential or inter-

leaved. The burst type is selected via bit M3, as shown in Figure 34. The ordering of ac-

cesses within a burst is determined by the burst length, the burst type, and the starting

column address, as shown in Table 41. DDR2 SDRAM supports 4-bit burst mode and 8-

bit burst mode only. For 8-bit burst mode, full interleaved address ordering is suppor-

ted; however, sequential address ordering is nibble-based.

Table 41: Burst Definition

Burst Length

Starting Column Address

Order of Accesses Within a Burst

(A2, A1, A0)

Burst Type = Sequential

Burst Type = Interleaved

0, 1, 2, 3

0 0

0 1

0, 1, 2, 3

1, 2, 3, 0

1, 0, 3, 2

1 0

2, 3, 0, 1

1 1

3, 0, 1, 2

3, 2, 1, 0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 0, 5, 6, 7, 4

2, 3, 0, 1, 6, 7, 4, 5

3, 0, 1, 2, 7, 4, 5, 6

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 4, 1, 2, 3, 0

6, 7, 4, 5, 2, 3, 0, 1

7, 4, 5, 6, 3, 0, 1, 2

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

Operating Mode

DLL RESET

The normal operating mode is selected by issuing a command with bit M7 set to “±,”

and all other bits set to the desired values, as shown in Figure 34 (page 77). When bit M7

is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1”

places the DDR2 SDRAM into a test mode that is only used by the manufacturer and

should not be used. No operation or functionality is guaranteed if M7 bit is “1.”

DLL RESET is defined by bit M8, as shown in Figure 34. Programming bit M8 to “1” will

activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to a

value of “±” after the DLL RESET function has been issued.

Anytime the DLL RESET function is used, 2±± clock cycles must occur before a READ

command can be issued to allow time for the internal clock to be synchronized with the

external clock. Failing to wait for synchronization to occur may result in a violation of

the ^tAC or ^tDQSCK parameters.

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Mode Register (MR)

Write Recovery

Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 34 (page 77).

The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera-

tion. During WRITE with auto precharge operation, the DDR2 SDRAM delays the inter-

nal auto precharge operation by WR clocks (programmed in bits M9–M11) from the last

data burst. An example of WRITE with auto precharge is shown in Figure 63 (page 111).

WR values of 2, 3, 4, 5, 6, 7, or 8 clocks may be used for programming bits M9–M11. The

user is required to program the value of WR, which is calculated by dividing WR (in

nanoseconds) by ^tCK (in nanoseconds) and rounding up a noninteger value to the next

integer; WR (cycles) = WR (ns)/^tCK (ns). Reserved states should not be used as an un-

known operation or incompatibility with future versions may result.

Power-Down Mode

Active power-down (PD) mode is defined by bit M12, as shown in Figure 34. PD mode

enables the user to determine the active power-down mode, which determines per-

formance versus power savings. PD mode bit M12 does not apply to precharge PD

mode.

When bit M12 = ±, standard active PD mode, or “fast-exit” active PD mode, is enabled.

The ^tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to

be enabled and running during this mode.

When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is en-

abled. The ^tXARDS parameter is used for slow-exit active PD exit timing. The DLL can

be enabled but “frozen” during active PD mode because the exit-to-READ command

timing is relaxed. The power difference expected between I_DD3Pnormal and I_DD3Plow-

power mode is defined in the DDR2 I_DDSpecifications and Conditions table.

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Mode Register (MR)

CAS Latency (CL)

The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 34 (page 77). CL is

the delay, in clock cycles, between the registration of a READ command and the availa-

bility of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending

on the speed grade option being used.

DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be

used as an unknown operation otherwise incompatibility with future versions may re-

sult.

DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This fea-

ture allows the READ command to be issued prior to ^tRCD (MIN) by delaying the inter-

nal command to the DDR2 SDRAM by AL clocks. The AL feature is described in further

detail in Posted CAS Additive Latency (AL) (page 83).

Examples of CL = 3 and CL = 4 are shown in Figure 35; both assume AL = ±. If a READ

command is registered at clock edge n, and the CL is m clocks, the data will be available

nominally coincident with clock edge n + m (this assumes AL = ±).

Figure 35: CL

CK#

READ

NOP

Command

DQS, DQS#

n + 1

n + 2

n + 3

CL = 3 (AL = 0)

CK#

READ

NOP

Command

DQS, DQS#

n + 1

n + 2

n + 3

CL = 4 (AL = 0)

Transitioning data

Don’t care

1. BL = 4.

2. Posted CAS# additive latency (AL) = 0.

3. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.

Notes:

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Extended Mode Register (EMR)

The extended mode register controls functions beyond those controlled by the mode

die termination (ODT), posted AL, off-chip driver impedance calibration (OCD), DQS#

enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These func-

tions are controlled via the bits shown in Figure 36. The EMR is programmed via the LM

command and will retain the stored information until it is programmed again or the de-

vice loses power. Reprogramming the EMR will not alter the contents of the memory ar-

ray, provided it is performed correctly.

The EMR must be loaded when all banks are idle and no bursts are in progress, and the

controller must wait the specified time ^tMRD before initiating any subsequent opera-

tion. Violating either of these requirements could result in an unspecified operation.

Figure 36: EMR Definition

BA2 BA1 BA0 An A12

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus

Extended mode

16 15 14

12 11 10

Out

MRS

R_TT

OCD Program

Posted CAS# R_TTODS DLL

RDQS DQS#

Outputs

Enabled

Disabled

DLL Enable

E12

E6 E2

_TT(Nominal)

Enable (normal)

Disable (test/debug)

_TTdisabled

E11 RDQS Enable

150

Output Drive Strength

Full

Yes

Reduced

E10 DQS# Enable

Posted CAS# Additive Latency (AL)

E5 E4 E3

Enable

Disable

E9 E8 E7 OCD Operation

OCD exit

Reserved

Enable OCD defaults

Mode Register Set

E15 E14

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

1. E16 (BA2) is only applicable for densities ≥1Gb, reserved for future use, and must be pro-

Notes:

grammed to 0.

2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-

served for future use and must be programmed to 0.

3. Not all listed AL options are supported in any individual speed grade.

4. As detailed in the Initialization section notes, during initialization of the OCD operation,

all three bits must be set to 1 for the OCD default state, then set to 0 before initializa-

tion is finished.

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Extended Mode Register (EMR)

DLL Enable/Disable

The DLL may be enabled or disabled by programming bit E± during the LM command,

as shown in Figure 36 (page 81). These specifications are applicable when the DLL is en-

abled for normal operation. DLL enable is required during power-up initialization and

upon returning to normal operation after having disabled the DLL for the purpose of

debugging or evaluation. Enabling the DLL should always be followed by resetting the

DLL using the LM command.

The DLL is automatically disabled when entering SELF REFRESH operation and is auto-

matically re-enabled and reset upon exit of SELF REFRESH operation.

Anytime the DLL is enabled (and subsequently reset), 2±± clock cycles must occur be-

fore a READ command can be issued to allow time for the internal clock to synchronize

with the external clock. Failing to wait for synchronization to occur may result in a vio-

lation of the ^tAC or ^tDQSCK parameters.

Anytime the DLL is disabled and the device is operated below 25 MHz, any AUTO RE-

FRESH command should be followed by a PRECHARGE ALL command.

Output Drive Strength

The output drive strength is defined by bit E1, as shown in Figure 36. The normal drive

strength for all outputs is specified to be SSTL_18. Programming bit E1 = ± selects nor-

mal (full strength) drive strength for all outputs. Selecting a reduced drive strength op-

tion (E1 = 1) will reduce all outputs to approximately 45 to 6± percent of the SSTL_18

drive strength. This option is intended for the support of lighter load and/or point-to-

point environments.

DQS# Enable/Disable

The DQS# ball is enabled by bit E1±. When E1± = ±, DQS# is the complement of the dif-

ferential data strobe pair DQS/DQS#. When disabled (E1± = 1), DQS is used in a single-

ended mode and the DQS# ball is disabled. When disabled, DQS# should be left float-

ing; however, it may be tied to ground via a 2±Ω to 1±kΩ resistor. This function is also

used to enable/disable RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled (E1± =

±), then both DQS# and RDQS# will be enabled.

RDQS Enable/Disable

The RDQS ball is enabled by bit E11, as shown in Figure 36. This feature is only applica-

ble to the x8 configuration. When enabled (E11 = 1), RDQS is identical in function and

timing to data strobe DQS during a READ. During a WRITE operation, RDQS is ignored

by the DDR2 SDRAM.

Output Enable/Disable

The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 36. When ena-

bled (E12 = ±), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) function normally. When

disabled (E12 = 1), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) are disabled, thus re-

moving output buffer current. The output disable feature is intended to be used during

I_DDcharacterization of read current.

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Extended Mode Register (EMR)

On-Die Termination (ODT)

ODT effective resistance, R_TT(EFF), is defined by bits E2 and E6 of the EMR, as shown in

Figure 36 (page 81). The ODT feature is designed to improve signal integrity of the

memory channel by allowing the DDR2 SDRAM controller to independently turn on/off

ODT for any or all devices. R_TTeffective resistance values of 5±ΩꢀꢁꢂꢃΩ, and 15±Ω are se-

lectable and apply to each DQ, DQS/DQS#, RDQS/RDQS#, UDQS/UDQS#, LDQS/

LDQS#, DM, and UDM/LDM signal. Bits (E6, E2) determine what ODT resistance is en-

abled by turning on/off sw1, sw2, or sw3. The ODT effective resistance value is selected

by enabling switch sw1, which enables all R1 values that are 15±Ω each, enabling an ef-

fective resistance of 75Ω (R_{TT2 [EFF]}= R2/2). Similarly, if sw2 is enabled, all R2 values that

are 3±±Ω each, enable an effective ODT resistance of 15±Ω (R_TT2[EFF]= R2/2). Switch sw3

enables R1 values of 1±±Ω, enabling effective resistance of 5±Ω. Reserved states should

not be used, as an unknown operation or incompatibility with future versions may re-

sult.

The ODT control ball is used to determine when R_TT(EFF)is turned on and off, assuming

ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input

ball are only used during active, active power-down (both fast-exit and slow-exit

modes), and precharge power-down modes of operation.

ODT must be turned off prior to entering self refresh mode. During power-up and initi-

alization of the DDR2 SDRAM, ODT should be disabled until the EMR command is is-

sued. This will enable the ODT feature, at which point the ODT ball will determine the

R_TT(EFF)value. Anytime the EMR enables the ODT function, ODT may not be driven

HIGH until eight clocks after the EMR has been enabled (see Figure 79 (page 128) for

ODT timing diagrams).

Off-Chip Driver (OCD) Impedance Calibration

The OFF-CHIP DRIVER function is an optional DDR2 JEDEC feature not supported by

Micron and thereby must be set to the default state. Enabling OCD beyond the default

settings will alter the I/O drive characteristics and the timing and output I/O specifica-

tions will no longer be valid (see Initialization section for proper setting of OCD de-

faults).

Posted CAS Additive Latency (AL)

Posted CAS additive latency (AL) is supported to make the command and data bus effi-

cient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as

shown in Figure 36. Bits E3–E5 allow the user to program the DDR2 SDRAM with an AL

of ±, 1, 2, 3, 4, 5, or 6 clocks. Reserved states should not be used as an unknown opera-

tion or incompatibility with future versions may result.

In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued

prior to ^tRCD (MIN) with the requirement that AL ≤ ^tRCD (MIN). A typical application

using this feature would set AL = ^tRCD (MIN) - 1 × ^tCK. The READ or WRITE command

is held for the time of the AL before it is issued internally to the DDR2 SDRAM device.

RL is controlled by the sum of AL and CL; RL = AL + CL. WRITE latency (WL) is equal to

RL minus one clock; WL = AL + CL - 1 × CK. An example of RL is shown in Figure 37

(page 84). An example of a WL is shown in Figure 38 (page 84).

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Extended Mode Register (EMR)

Figure 37: READ Latency

CK#

Command

DQS, DQS#

ACTIVE n

READ n

NOP

RCD (MIN)

n + 1

n + 3

n + 2

AL = 2

CL = 3

RL = 5

Transitioning Data

Don’t Care

1. BL = 4.

Notes:

2. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.

3. RL = AL + CL = 5.

Figure 38: WRITE Latency

CK#

ACTIVE n

WRITE n

NOP

Command

RCD (MIN)

DQS, DQS#

AL = 2

CL - 1 = 2

n + 1

n + 2

n + 3

WL = AL + CL - 1 = 4

Transitioning Data

Don’t Care

1. BL = 4.

2. CL = 3.

Notes:

3. WL = AL + CL - 1 = 4.

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Extended Mode Register 2 (EMR2)

The extended mode register 2 (EMR2) controls functions beyond those controlled by

the mode register. Currently all bits in EMR2 are reserved, except for E7, which is used

in commercial or high-temperature operations, as shown in Figure 39. The EMR2 is pro-

grammed via the LM command and will retain the stored information until it is pro-

grammed again or until the device loses power. Reprogramming the EMR will not alter

the contents of the memory array, provided it is performed correctly.

Bit E7 (A7) must be programmed as 1 to provide a faster refresh rate on IT and AT devi-

ces if T_Cexceeds 85°C.

EMR2 must be loaded when all banks are idle and no bursts are in progress, and the

controller must wait the specified time ^tMRD before initiating any subsequent opera-

tion. Violating either of these requirements could result in an unspecified operation.

Figure 39: EMR2 Definition

BA2

BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address bus

Extended mode

16 15 14

12 11 10

SRT

MRS

E15 E14

Mode Register Set

Mode register (MR)

SRT Enable

1X refresh rate (0°C to 85°C)

2X refresh rate (>85°C)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

1. E16 (BA2) is only applicable for densities ≥1Gb, reserved for future use, and must be pro-

Notes:

grammed to 0.

2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-

served for future use and must be programmed to 0.

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Extended Mode Register 3 (EMR3)

The extended mode register 3 (EMR3) controls functions beyond those controlled by

the mode register. Currently all bits in EMR3 are reserved, as shown in Figure 4±. The

EMR3 is programmed via the LM command and will retain the stored information until

it is programmed again or until the device loses power. Reprogramming the EMR will

not alter the contents of the memory array, provided it is performed correctly.

EMR3 must be loaded when all banks are idle and no bursts are in progress, and the

controller must wait the specified time ^tMRD before initiating any subsequent opera-

tion. Violating either of these requirements could result in an unspecified operation.

Figure 40: EMR3 Definition

BA2

BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus

Extended mode

16 15 14

MRS

12 11 10

E15 E14

Mode Register Set

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

1. E16 (BA2) is only applicable for densities ≥1Gb, is reserved for future use, and must be

Notes:

programmed to 0.

2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-

served for future use and must be programmed to 0.

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Initialization

Figure 41: DDR2 Power-Up and Initialization

DDR2 SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in unde-

fined operation. Figure 41 illustrates, and the notes outline, the sequence required for power-up and initialization.

DDL

DDQ

VTD

REF

Tk0

Tl0

Tm0

Tg0

Th0

Ti0

Tj0

Te0

Tf0

Tc0

Td0

Tb0

Ta0

CK#

LVCMOS

low level

SSTL_18

low level

CKE

ODT

Valid

REF

Command

PRE

REF

NOP

Address

Code

A10 = 1

Code

A10 = 1

Valid

High-Z

DQS

Rtt

MRD

T = 400ns (MIN)

T = 200μs (MIN)

RPA

MRD

RPA

RFC

6HHꢀQR WHꢀꢁꢂ

RFC

MRD

Power-up:

V_DDand stable

clock (CK, CK#)

EMR(2)

EMR(3)

EMR

MR without

DLL RESET

EMR with

OCD default

EMR with

OCD exit

200 cycles of CK are required before a READ command can be issued

Normal

operation

MR with

DLL RESET

Indicates a Break in

Time Scale

Don’t care

512Mb: x4, x8, x16 DDR2 SDRAM

Initialization

1. Applying power; if CKE is maintained below 0.2 × V_DDQ, outputs remain disabled. To

guarantee R_TT(ODT resistance) is off, V_REFmust be valid and a low level must be applied

to the ODT ball (all other inputs may be undefined; I/Os and outputs must be less than

Notes:

_DDQduring voltage ramp time to avoid DDR2 SDRAM device latch-up). V_TTis not ap-

plied directly to the device; however, ^tVTD should be ≥0 to avoid device latch-up. At

least one of the following two sets of conditions (A or B) must be met to obtain a stable

supply state (stable supply defined as V_DD, V_DDL, V_DDQ, V_REF, and V_TTare between their

minimum and maximum values as stated in Table 13 (page 43)):

A. Single power source: The V_DDvoltage ramp from 300mV to V_DD,minmust take no lon-

ger than 200ms; during the V_DDvoltage ramp, |V_DD- V_DDQ| ≤ 0.3V. Once supply voltage

ramping is complete (when V_DDQcrosses V_DD,min), Table 13 specifications apply.

• V_DD, V_DDL, and V_DDQare driven from a single power converter output

• V_TTis limited to 0.95V MAX

• V_REFtracks V_DDQ/2; V_REFmust be within 0.3V with respect to V_DDQ/2 during supply

ramp time; does not need to be satisfied when ramping power down

• V_DDQ≥ V_REFat all times

B. Multiple power sources: V_DD≥ V_DDL≥ V_DDQmust be maintained during supply voltage

ramping, for both AC and DC levels, until supply voltage ramping completes (V_DDQ

crosses V_DD,min). Once supply voltage ramping is complete, Table 13 specifications apply.

• Apply V_DDand V_DDLbefore or at the same time as V_DDQ; V_DD/V_DDLvoltage ramp time

must be ≤ 200ms from when V_DDramps from 300mV to V_DD,min

• Apply V_DDQbefore or at the same time as V_TT; the V_DDQvoltage ramp time from when

_DD,minis achieved to when V_DDQ,minis achieved must be ≤ 500ms; while V_DDis ramp-

ing, current can be supplied from V_DDthrough the device to V_DDQ

• V_REFmust track V_DDQ/2; V_REFmust be within 0.3V with respect to V_DDQ/2 during sup-

ply ramp time; V_DDQ≥ V_REFmust be met at all times; does not need to be satisfied

when ramping power down

• Apply V_TT; the V_TTvoltage ramp time from when V_DDQ,minis achieved to when V_TT,min

is achieved must be no greater than 500ms

2. CKE requires LVCMOS input levels prior to state T0 to ensure DQs are High-Z during de-

vice power-up prior to V_REFbeing stable. After state T0, CKE is required to have SSTL_18

input levels. Once CKE transitions to a high level, it must stay HIGH for the duration of

the initialization sequence.

3. For a minimum of 200μs after stable power and clock (CK, CK#), apply NOP or DESELECT

commands, then take CKE HIGH.

4. Wait a minimum of 400ns then issue a PRECHARGE ALL command.

5. Issue a LOAD MODE command to the EMR(2). To issue an EMR(2) command, provide

LOW to BA0, and provide HIGH to BA1; set register E7 to “0” or “1” to select appropri-

ate self refresh rate; remaining EMR(2) bits must be “0” (see Extended Mode Register 2

(EMR2) (page 85) for all EMR(2) requirements).

6. Issue a LOAD MODE command to the EMR(3). To issue an EMR(3) command, provide

HIGH to BA0 and BA1; remaining EMR(3) bits must be “0.” Extended Mode Register 3

(EMR3) for all EMR(3) requirements.

7. Issue a LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE com-

mand, provide LOW to BA1 and A0; provide HIGH to BA0; bits E7, E8, and E9 can be set

to “0” or “1;” Micron recommends setting them to “0;” remaining EMR bits must be

“0.” Extended Mode Register (EMR) (page 81) for all EMR requirements.

8. Issue a LOAD MODE command to the MR for DLL RESET. 200 cycles of clock input is re-

quired to lock the DLL. To issue a DLL RESET, provide HIGH to A8 and provide LOW to

BA1 and BA0; CKE must be HIGH the entire time the DLL is resetting; remaining MR bits

must be “0.” Mode Register (MR) (page 76) for all MR requirements.

9. Issue PRECHARGE ALL command.

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Initialization

10. Issue two or more REFRESH commands.

11. Issue a LOAD MODE command to the MR with LOW to A8 to initialize device operation

(that is, to program operating parameters without resetting the DLL). To access the MR,

set BA0 and BA1 LOW; remaining MR bits must be set to desired settings. Mode Register

(MR) (page 76) for all MR requirements.

12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8,

and E9 to “1,” and then setting all other desired parameters. To access the EMR, set BA0

HIGH and BA1 LOW (see Extended Mode Register (EMR) (page 81) for all EMR require-

ments.

13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and

E9 to “0,” and then setting all other desired parameters. To access the extended mode

registers, EMR, set BA0 HIGH and BA1 LOW for all EMR requirements.

14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles af-

ter the DLL RESET at Tf0.

15. DM represents DM for the x4, x8 configurations and UDM, LDM for the x16 configura-

tion; DQS represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# for the ap-

propriate configuration (x4, x8, x16); DQ represents DQ[3:0] for x4, DQ[7:0] for x8 and

DQ[15:0] for x16.

16. A10 = PRECHARGE ALL, CODE = desired values for mode registers (bank addresses are

required to be decoded).

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ACTIVATE

Before any READ or WRITE commands can be issued to a bank within the DDR2

SDRAM, a row in that bank must be opened (activated), even when additive latency is

used. This is accomplished via the ACTIVATE command, which selects both the bank

and the row to be activated.

After a row is opened with an ACTIVATE command, a READ or WRITE command may

be issued to that row subject to the ^tRCD specification. ^tRCD (MIN) should be divided

by the clock period and rounded up to the next whole number to determine the earliest

clock edge after the ACTIVATE command on which a READ or WRITE command can be

entered. The same procedure is used to convert other specification limits from time

units to clock cycles. For example, a ^tRCD (MIN) specification of 2±ns with a 266 MHz

clock (^tCK = 3.75ns) results in 5.3 clocks, rounded up to 6. This is shown in Figure 42,

which covers any case where 5 < ^tRCD (MIN)/^tCK ≤ 6. Figure 42 also shows the case for

^tRRD where 2 < ^tRRD (MIN)/^tCK ≤ 3.

Figure 42: Example: Meeting ^tRRD (MIN) and ^tRCD (MIN)

CK#

Command

ACT

Row

NOP

ACT

Row

NOP

Row

NOP

RD/WR

Col

Address

Bank x

Bank y

Bank z

Bank y

Bank address

RRD

RCD

Don’t Care

A subsequent ACTIVATE command to a different row in the same bank can only be is-

sued after the previous active row has been closed (precharged). The minimum time in-

terval between successive ACTIVATE commands to the same bank is defined by ^tRC.

A subsequent ACTIVATE command to another bank can be issued while the first bank is

being accessed, which results in a reduction of total row-access overhead. The mini-

mum time interval between successive ACTIVATE commands to different banks is de-

fined by ^tRRD.

DDR2 devices with 8 banks (1Gb or larger) have an additional requirement: ^tFAW. This

requires no more than four ACTIVATE commands may be issued in any given ^tFAW

(MIN) period, as shown in Figure 43 (page 91).

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ACTIVATE

Figure 43: Multibank Activate Restriction

T10

CK#

Command

ACT

Row

READ

ACT

Row

NOP

ACT

Row

READ

Col

ACT

READ

ACT

Row

READ

NOP

Col

Row

Col

Address

Bank address

Bank a

Bank b

Bank c

Bank d

Bank e

RRD (MIN)

FAW (MIN)

Don’t Care

1. DDR2-533 (-37E, x4 or x8), ^tCK = 3.75ns, BL = 4, AL = 3, CL = 4, ^tRRD (MIN) = 7.5ns,

^tFAW (MIN) = 37.5ns.

Note:

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READ

READ bursts are initiated with a READ command. The starting column and bank ad-

dresses are provided with the READ command, and auto precharge is either enabled or

disabled for that burst access. If auto precharge is enabled, the row being accessed is

automatically precharged at the completion of the burst. If auto precharge is disabled,

the row will be left open after the completion of the burst.

During READ bursts, the valid data-out element from the starting column address will

be available READ latency (RL) clocks later. RL is defined as the sum of AL and CL:

RL = AL + CL. The value for AL and CL are programmable via the MR and EMR com-

mands, respectively. Each subsequent data-out element will be valid nominally at the

next positive or negative clock edge (at the next crossing of CK and CK#). Figure 44

(page 93) shows examples of RL based on different AL and CL settings.

DQS/DQS# is driven by the DDR2 SDRAM along with output data. The initial LOW state

on DQS and the HIGH state on DQS# are known as the read preamble (^tRPRE). The

LOW state on DQS and the HIGH state on DQS# coincident with the last data-out ele-

ment are known as the read postamble (^tRPST).

Upon completion of a burst, assuming no other commands have been initiated, the DQ

will go High-Z. A detailed explanation of ^tDQSQ (valid data-out skew), ^tQH (data-out

window hold), and the valid data window are depicted in Figure 53 (page 1±1) and Fig-

ure 54 (page 1±2). A detailed explanation of ^tDQSCK (DQS transition skew to CK) and

^tAC (data-out transition skew to CK) is shown in Figure 55 (page 1±3).

Data from any READ burst may be concatenated with data from a subsequent READ

command to provide a continuous flow of data. The first data element from the new

burst follows the last element of a completed burst. The new READ command should be

issued x cycles after the first READ command, where x equals BL/2 cycles (see Figure 45

(page 94)).

Nonconsecutive read data is illustrated in Figure 46 (page 95). Full-speed random read

accesses within a page (or pages) can be performed. DDR2 SDRAM supports the use of

concurrent auto precharge timing (see Table 42 (page 98)).

DDR2 SDRAM does not allow interrupting or truncating of any READ burst using BL = 4

operations. Once the BL = 4 READ command is registered, it must be allowed to com-

plete the entire READ burst. However, a READ (with auto precharge disabled) using BL =

8 operation may be interrupted and truncated only by another READ burst as long as

the interruption occurs on a 4-bit boundary due to the 4n prefetch architecture of

DDR2 SDRAM. As shown in Figure 47 (page 96), READ burst BL = 8 operations may

not be interrupted or truncated with any other command except another READ com-

mand.

Data from any READ burst must be completed before a subsequent WRITE burst is al-

lowed. An example of a READ burst followed by a WRITE burst is shown in Figure 48

(page 96). The ^tDQSS (NOM) case is shown (^tDQSS [MIN] and ^tDQSS [MAX] are de-

fined in Figure 56 (page 1±5)).

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READ

Figure 44: READ Latency

T3n

T4n

CK#

Command

READ

NOP

Bank a,

Col n

Address

RL = 3 (AL = 0, CL = 3)

DQS, DQS#

T4n

T5n

CK#

Command

READ

NOP

Bank a,

Col n

Address

AL = 1

CL = 3

RL = 4 (AL = 1 + CL = 3)

DQS, DQS#

NOP

T3n

T4n

CK#

Command

READ

NOP

Bank a,

Col n

Address

RL = 4 (AL = 0, CL = 4)

DQS, DQS#

Transitioning Data

Don’t Care

1. DO n = data-out from column n.

Notes:

2. BL = 4.

3. Three subsequent elements of data-out appear in the programmed order following

DO n.

4. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.

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READ

Figure 45: Consecutive READ Bursts

T5n

T6n

NOP

CCD

T3n

T4n

CK#

Command

Address

READ

NOP

Bank,

Col n

Bank,

Col b

RL = 3

DQS, DQS#

T2n

T5n

T6n

T3n

T4n

CK#

Command

Address

READ

NOP

READ

NOP

Bank,

Col n

Bank,

Col b

CCD

RL = 4

DQS, DQS#

Transitioning Data

Don’t Care

1. DO n (or b) = data-out from column n (or column b).

Notes:

2. BL = 4.

3. Three subsequent elements of data-out appear in the programmed order following

DO n.

4. Three subsequent elements of data-out appear in the programmed order following

DO b.

5. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.

6. Example applies only when READ commands are issued to same device.

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READ

Figure 46: Nonconsecutive READ Bursts

T3 T3n T4 T4n T5

T6 T6n T7 T7n T8

CK#

Command

READ

NOP

READ

NOP

Bank,

Col n

Bank,

Col b

Address

CL = 3

DQS, DQS#

T4 T4n T5 T5n T6

T7 T7n T8

CK#

Command

READ

NOP

READ

NOP

Bank,

Col n

Bank,

Col b

Address

CL = 4

DQS, DQS#

Transitioning Data

Don’t Care

1. DO n (or b) = data-out from column n (or column b).

Notes:

2. BL = 4.

3. Three subsequent elements of data-out appear in the programmed order following

DO n.

4. Three subsequent elements of data-out appear in the programmed order following

DO b.

5. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.

6. Example applies when READ commands are issued to different devices or nonconsecu-

tive READs.

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READ

Figure 47: READ Interrupted by READ

CK#

NOP

Command

Valid

READ

Valid

Address

A10

Valid

DQS, DQS#

CL = 3 (AL = 0)

CCD

CL = 3 (AL = 0)

Transitioning Data

Don’t Care

1. BL = 8 required; auto precharge must be disabled (A10 = LOW).

Notes:

2. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be is-

sued to banks used for READs at T0 and T2.

3. Interrupting READ command must be issued exactly 2 × ^tCK from previous READ.

4. READ command can be issued to any valid bank and row address (READ command at T0

and T2 can be either same bank or different bank).

5. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the in-

terrupting READ command.

6. Example shown uses AL = 0; CL = 3, BL = 8, shown with nominal ^tAC, ^tDQSCK, and

^tDQSQ.

Figure 48: READ-to-WRITE

T10

T11

CK#

Command

ACT n

READ n

NOP

WRITE

NOP

DQS, DQS#

RCD = 3

WL = RL - 1 = 4

n + 1

n + 2

n + 3

n + 1

n + 3

n + 2

AL = 2

CL = 3

RL = 5

Transitioning Data

Don’t Care

1. BL = 4; CL = 3; AL = 2.

2. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.

Notes:

READ with Precharge

A READ burst may be followed by a PRECHARGE command to the same bank, provided

auto precharge is not activated. The minimum READ-to-PRECHARGE command spac-

ing to the same bank has two requirements that must be satisfied: AL + BL/2 clocks and

^tRTP. ^tRTP is the minimum time from the rising clock edge that initiates the last 4-bit

prefetch of a READ command to the PRECHARGE command. For BL = 4, this is the time

from the actual READ (AL after the READ command) to PRECHARGE command. For

BL = 8, this is the time from AL + 2 × CK after the READ-to-PRECHARGE command. Fol-

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READ

lowing the PRECHARGE command, a subsequent command to the same bank cannot

be issued until ^tRP is met. However, part of the row precharge time is hidden during the

access of the last data elements.

Examples of READ-to-PRECHARGE for BL = 4 are shown in Figure 49 and in Figure 5±

for BL = 8. The delay from READ-to-PRECHARGE period to the same bank is AL + BL/2 -

2CK + MAX (^tRTP/^tCK or 2 × CK) where MAX means the larger of the two.

Figure 49: READ-to-PRECHARGE – BL = 4

4-bit

prefetch

CK#

Command

READ

NOP

PRE

NOP

ACT

NOP

AL + BL/2 - 2CK + MAX ( RTP/ CK or 2CK)

Address

A10

Bank a

Valid

Bank a

Valid

AL = 1

CL = 3

DQS, DQS#

RTP (MIN)

RAS (MIN)

RP (MIN)

RC (MIN)

Transitioning Data

Don’t Care

1. RL = 4 (AL = 1, CL = 3); BL = 4.

Notes:

2. ^tRTP ≥ 2 clocks.

3. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.

Figure 50: READ-to-PRECHARGE – BL = 8

First 4-bit

prefetch

Second 4-bit

prefetch

CK#

Command READ

NOP

PRE

NOP

ACT

AL + BL/2 - 2CK + MAX ( RTP/ CK or 2CK)

Address

A10

Bank a

Valid

Bank a

Valid

AL = 1

CL = 3

DQS, DQS#

RP (MIN)

RTP (MIN)

RAS (MIN)

RC (MIN)

Transitioning Data

Don’t Care

1. RL = 4 (AL = 1, CL = 3); BL = 8.

Notes:

2. ^tRTP ≥ 2 clocks.

3. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.

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READ

READ with Auto Precharge

If A1± is high when a READ command is issued, the READ with auto precharge function

is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising clock

edge that is AL + (BL/2) cycles later than the read with auto precharge command provi-

ded ^tRAS (MIN) and ^tRTP are satisfied. If ^tRAS (MIN) is not satisfied at this rising clock

edge, the start point of the auto precharge operation will be delayed until ^tRAS (MIN) is

satisfied. If ^tRTP (MIN) is not satisfied at this rising clock edge, the start point of the au-

to precharge operation will be delayed until ^tRTP (MIN) is satisfied. When the internal

precharge is pushed out by ^tRTP, ^tRP starts at the point where the internal precharge

happens (not at the next rising clock edge after this event).

When BL = 4, the minimum time from READ with auto precharge to the next ACTIVATE

command is AL + (^tRTP + ^tRP)/^tCK. When BL = 8, the minimum time from READ with

auto precharge to the next ACTIVATE command is AL + 2 clocks + (^tRTP + ^tRP)/^tCK. The

term (^tRTP + ^tRP)/^tCK is always rounded up to the next integer. A general purpose equa-

tion can also be used: AL + BL/2 - 2CK + (^tRTP + ^tRP)/^tCK. In any event, the internal pre-

charge does not start earlier than two clocks after the last 4-bit prefetch.

READ with auto precharge command may be applied to one bank while another bank is

operational. This is referred to as concurrent auto precharge operation, as noted in Ta-

ble 42. Examples of READ with precharge and READ with auto precharge with applica-

ble timing requirements are shown in Figure 51 (page 99) and Figure 52 (page 1±±),

respectively.

Table 42: READ Using Concurrent Auto Precharge

Minimum Delay

From Command (Bank n)

To Command (Bank m)

READ or READ with auto precharge

WRITE or WRITE with auto precharge

PRECHARGE or ACTIVATE

(with Concurrent Auto Precharge) Units

READ with auto precharge

BL/2

(BL/2) + 2

^tCK

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READ

Figure 51: Bank Read – Without Auto Precharge

T7n

T8n

CK#

CKE

NOP

Command

ACT

PRE

ACT

NOP

READ

Col n

NOP

RTP

Address

A10

All banks

One bank

Bank address

Bank x

CL = 3

RCD

RAS

DQSCK (MIN)

Case 1: AC (MIN) and DQSCK (MIN)

RPST

RPRE

DQS, DQS#

LZ (MIN)

AC (MIN)

HZ (MIN)

DQSCK (MAX)

Case 2: AC (MAX) and DQSCK (MAX)

RPST

RPRE

DQS, DQS#

LZ (MAX)

AC (MAX)

HZ (MAX)

LZ (MIN)

Transitioning Data

Don’t Care

1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

Notes:

2. BL = 4 and AL = 0 in the case shown.

3. The PRECHARGE command can only be applied at T6 if ^tRAS (MIN) is met.

4. READ-to-PRECHARGE = AL + BL/2 - 2CK + MAX (^tRTP/^tCK or 2CK).

5. Disable auto precharge.

6. “Don’t Care” if A10 is HIGH at T5.

7. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,

but to when the device begins to drive or no longer drives, respectively.

8. DO n = data-out from column n; subsequent elements are applied in the programmed

order.

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READ

Figure 52: Bank Read – with Auto Precharge

T7n

T8n

CK#

CKE

2,3

READ

NOP

Command

NOP

ACT

NOP

Address

A10

Col n

Bank address

Bank x

AL = 1

CL = 3

RTP

RCD

RAS

DQSCK (MIN)

RPST

Case 1: AC (MIN) and DQSCK (MIN)

RPRE

DQS, DQS#

LZ (MIN)

HZ (MIN)

AC (MIN)

DQSCK (MAX)

Case 2: AC (MAX) and DQSCK (MAX)

RPST

RPRE

DQS, DQS#

LZ (MAX)

HZ (MAX)

LZ (MAX)

AC (MAX)

4-bit

prefetch

Internal

precharge

Transitioning Data

Don’t Care

1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

Notes:

2. BL = 4, RL = 4 (AL = 1, CL = 3) in the case shown.

3. The DDR2 SDRAM internally delays auto precharge until both ^tRAS (MIN) and ^tRTP (MIN)

have been satisfied.

4. Enable auto precharge.

5. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,

but to when the device begins to drive or no longer drives, respectively.

6. DO n = data-out from column n; subsequent elements are applied in the programmed

order.

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READ

Figure 53: x4, x8 Data Output Timing – ^tDQSQ, ^tQH, and Data Valid Window

T2n

T3n

CK#

DQSQ

DQS#

DQS

DQ (last data valid)

DQ (first data no longer valid)

QHS

DQ (last data valid)

T2n

T3n

DQ (first data no longer valid)

T3n

All DQs and DQS collectively

T2n

T3n

Earliest signal transition

Latest signal transition

Data

valid

window

Data

valid

window

Data

valid

window

valid

window

1. ^tHP is the lesser of ^tCL or ^tCH clock transitions collectively when a bank is active.

2. ^tDQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS

transitions, and ends with the last valid transition of DQ.

Notes:

3. DQ transitioning after the DQS transition defines the ^tDQSQ window. DQS transitions at

T2 and at T2n are “early DQS,” at T3 are “nominal DQS,” and at T3n are “late DQS.”

4. DQ0, DQ1, DQ2, DQ3 for x4 or DQ[7:0] for x8.

5. ^tQH is derived from ^tHP: ^tQH = ^tHP - ^tQHS.

6. The data valid window is derived for each DQS transition and is defined as ^tQH - ^tDQSQ.

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READ

Figure 54: x16 Data Output Timing – ^tDQSQ, ^tQH, and Data Valid Window

T2n

T3n

CK#

DQSQ

LDSQ#

LDQS

DQ (last data valid)

DQ (first data no longer valid)

QHS

DQ (last data valid)

T2n

T3n

DQ (first data no longer valid)

T3n

DQ0–DQ7 and LDQS collectively

T2n

Data valid

window

Data valid

window

Data valid

window

Data valid

window

DQSQ

UDQS#

UDQS

DQ (last data valid)

DQ (first data no longer valid)

QHS

DQ (last data valid)

DQ (first data no longer valid)

DQ8–DQ15 and UDQS collectively

T2n

T3n

T2n

T3n

Data valid

window

Data valid

window

Data valid

window

Data valid

window

1. ^tHP is the lesser of ^tCL or ^tCH clock transitions collectively when a bank is active.

2. ^tDQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS

transitions, and ends with the last valid transition of DQ.

Notes:

3. DQ transitioning after the DQS transitions define the ^tDQSQ window. LDQS defines the

lower byte, and UDQS defines the upper byte.

4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.

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WRITE

5. ^tQH is derived from ^tHP: ^tQH = ^tHP - ^tQHS.

6. The data valid window is derived for each DQS transition and is ^tQH - ^tDQSQ.

7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.

Figure 55: Data Output Timing – ^tAC and ^tDQSCK

T3n

T4n

T5n

T6n

CK#

HZ (MAX)

DQSCK (MAX)

DQSCK (MIN)

LZ (MIN)

RPST

RPRE

DQS#/DQS or

LDQS#/LDQS/UDQ#/UDQS

DQ (last data valid)

DQ (first data valid)

T3n

T4n

T5n

T6n

T4n

All DQs collectively

T3n

T5n

T6n

HZ (MAX)

LZ (MIN)

AC (MIN)

AC (MAX)

1. READ command with CL = 3, AL = 0 issued at T0.

Notes:

2. ^tDQSCK is the DQS output window relative to CK and is the long-term component of

DQS skew.

3. DQ transitioning after DQS transitions define ^tDQSQ window.

4. All DQ must transition by ^tDQSQ after DQS transitions, regardless of ^tAC.

5. ^tAC is the DQ output window relative to CK and is the “long term” component of DQ

skew.

6. ^tLZ (MIN) and ^tAC (MIN) are the first valid signal transitions.

7. ^tHZ (MAX) and ^tAC (MAX) are the latest valid signal transitions.

8. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,

but to when the device begins to drive or no longer drives, respectively.

WRITE

WRITE bursts are initiated with a WRITE command. DDR2 SDRAM uses WL equal to RL

minus one clock cycle (WL = RL - 1CK) (see READ (page 75)). The starting column and

bank addresses are provided with the WRITE command, and auto precharge is either

enabled or disabled for that access. If auto precharge is enabled, the row being accessed

is precharged at the completion of the burst.

Note:

For the WRITE commands used in the following illustrations, auto precharge is disa-

bled.

During WRITE bursts, the first valid data-in element will be registered on the first rising

edge of DQS following the WRITE command, and subsequent data elements will be reg-

istered on successive edges of DQS. The LOW state on DQS between the WRITE com-

mand and the first rising edge is known as the write preamble; the LOW state on DQS

following the last data-in element is known as the write postamble.

The time between the WRITE command and the first rising DQS edge is WL ± ^tDQSS.

Subsequent DQS positive rising edges are timed, relative to the associated clock edge, as

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WRITE

±^tDQSS. ^tDQSS is specified with a relatively wide range (25% of one clock cycle). All of

the WRITE diagrams show the nominal case, and where the two extreme cases (^tDQSS

[MIN] and ^tDQSS [MAX]) might not be intuitive, they have also been included. Figure 56

(page 1±5) shows the nominal case and the extremes of ^tDQSS for BL = 4. Upon com-

pletion of a burst, assuming no other commands have been initiated, the DQ will re-

main High-Z and any additional input data will be ignored.

Data for any WRITE burst may be concatenated with a subsequent WRITE command to

provide continuous flow of input data. The first data element from the new burst is ap-

plied after the last element of a completed burst. The new WRITE command should be

issued x cycles after the first WRITE command, where x equals BL/2.

Figure 57 (page 1±6) shows concatenated bursts of BL = 4 and how full-speed random

write accesses within a page or pages can be performed. An example of nonconsecutive

WRITEs is shown in Figure 58 (page 1±6). DDR2 SDRAM supports concurrent auto pre-

charge options, as shown in Table 43.

DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4

operation. Once the BL = 4 WRITE command is registered, it must be allowed to com-

plete the entire WRITE burst cycle. However, a WRITE BL = 8 operation (with auto pre-

charge disabled) might be interrupted and truncated only by another WRITE burst as

long as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architecture

of DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or truncated

with any command except another WRITE command, as shown in Figure 59

(page 1±7).

Data for any WRITE burst may be followed by a subsequent READ command. To follow

a WRITE, WTR should be met, as shown in Figure 6± (page 1±8). The number of clock

cycles required to meet ^tWTR is either 2 or ^tWTR/^tCK, whichever is greater. Data for any

WRITE burst may be followed by a subsequent PRECHARGE command. ^tWR must be

met, as shown in Figure 61 (page 1±9). ^tWR starts at the end of the data burst, regardless

of the data mask condition.

Table 43: WRITE Using Concurrent Auto Precharge

From Command

To Command

Minimum Delay

(Bank n)

(Bank m)

(with Concurrent Auto Precharge) Units

WRITE with auto precharge

READ or READ with auto precharge

WRITE or WRITE with auto precharge

PRECHARGE or ACTIVATE

(CL - 1) + (BL/2) + ^tWTR

^tCK

(BL/2)

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WRITE

Figure 56: Write Burst

T2n

T3n

CK#

Command

Address

WRITE

NOP

Bank a,

Col b

DQSS

DQSS (NOM)

DQS, DQS#

DQSS

WL - DQSS

DQSS (MIN)

DQS, DQS#

DQSS

WL + DQSS

DQSS (MAX)

DQS, DQS#

Transitioning Data

Don’t Care

1. Subsequent rising DQS signals must align to the clock within ^tDQSS.

Notes:

2. DI b = data-in for column b.

3. Three subsequent elements of data-in are applied in the programmed order following

DI b.

4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.

5. A10 is LOW with the WRITE command (auto precharge is disabled).

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WRITE

Figure 57: Consecutive WRITE-to-WRITE

T1n

T2n

T3n

T4n

T5n

CK#

Command

WRITE

NOP

CCD

WRITE

NOP

WL = 2

Bank,

Col b

Bank,

Col n

Address

WL ^tDQSS

DQSS (NOM)

DQS, DQS#

Transitioning Data

Don’t Care

1. Subsequent rising DQS signals must align to the clock within ^tDQSS.

Notes:

2. DI b, etc. = data-in for column b, etc.

3. Three subsequent elements of data-in are applied in the programmed order following

DI b.

4. Three subsequent elements of data-in are applied in the programmed order following

DI n.

5. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.

6. Each WRITE command may be to any bank.

Figure 58: Nonconsecutive WRITE-to-WRITE

T2n

T3n

T4n

T5n

T6n

CK#

Command

WRITE

NOP

WRITE

NOP

WL = 2

Bank,

Col b

Bank,

Col n

Address

DQSS

DQSS (NOM)

DQS, DQS#

Transitioning Data

Don’t Care

1. Subsequent rising DQS signals must align to the clock within ^tDQSS.

Notes:

2. DI b (or n), etc. = data-in for column b (or column n).

3. Three subsequent elements of data-in are applied in the programmed order following

DI b.

4. Three subsequent elements of data-in are applied in the programmed order following

DI n.

5. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.

6. Each WRITE command may be to any bank.

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WRITE

Figure 59: WRITE Interrupted by WRITE

CK#

Valid

WRITE

Command

NOP

Valid

Address

A10

Valid

DQS, DQS#

a + 1

a + 2

a + 3

b + 1

b + 2

b + 3

b + 4

b + 5

b + 6

b + 7

WL = 3

2-clock requirement

WL = 3

Transitioning Data

Don’t Care

1. BL = 8 required and auto precharge must be disabled (A10 = LOW).

Notes:

2. The NOP or COMMAND INHIBIT commands are valid. The PRECHARGE command cannot

be issued to banks used for WRITEs at T0 and T2.

3. The interrupting WRITE command must be issued exactly 2 × ^tCK from previous WRITE.

4. The earliest WRITE-to-PRECHARGE timing for WRITE at T0 is WL + BL/2 + ^tWR where ^tWR

starts with T7 and not T5 (because BL = 8 from MR and not the truncated length).

5. The WRITE command can be issued to any valid bank and row address (WRITE command

at T0 and T2 can be either same bank or different bank).

6. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the in-

terrupting WRITE command.

7. Subsequent rising DQS signals must align to the clock within ^tDQSS.

8. Example shown uses AL = 0; CL = 4, BL = 8.

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WRITE

Figure 60: WRITE-to-READ

T2n

T3n

T9n

CK#

Command

WRITE

NOP

READ

NOP

WTR

Bank a,

Col b

Bank a,

Col n

Address

DQSS

DQSS (NOM)

CL = 3

DQS, DQS#

WL - DQSS

DQSS (MIN)

DQS, DQS#

WL + DQSS

DQSS (MAX)

DQS, DQS#

Transitioning Data

Don’t Care

1. ^tWTR is required for any READ following a WRITE to the same device, but it is not re-

quired between module ranks.

Notes:

2. Subsequent rising DQS signals must align to the clock within ^tDQSS.

3. DI b = data-in for column b; DO n = data-out from column n.

4. BL = 4, AL = 0, CL = 3; thus, WL = 2.

5. One subsequent element of data-in is applied in the programmed order following DI b.

6. ^tWTR is referenced from the first positive CK edge after the last data-in pair.

7. A10 is LOW with the WRITE command (auto precharge is disabled).

8. The number of clock cycles required to meet ^tWTR is either 2 or ^tWTR/^tCK, whichever is

greater.

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WRITE

Figure 61: WRITE-to-PRECHARGE

T2n

T3n

CK#

Command

WRITE

NOP

PRE

Bank a,

Col b

Bank,

Address

(a or all)

DQSS (NOM)

WL + DQSS

DQS#

DQS

DQSS (MIN)

WL - DQSS

DQS#

DQS

DQSS (MAX)

WL + DQSS

DQS#

DQS

Transitioning Data

Don’t Care

1. Subsequent rising DQS signals must align to the clock within ^tDQSS.

Notes:

2. DI b = data-in for column b.

3. Three subsequent elements of data-in are applied in the programmed order following

DI b.

4. BL = 4, CL = 3, AL = 0; thus, WL = 2.

5. ^tWR is referenced from the first positive CK edge after the last data-in pair.

6. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE

and WRITE commands may be to different banks, in which case ^tWR is not required and

the PRECHARGE command could be applied earlier.

7. A10 is LOW with the WRITE command (auto precharge is disabled).

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WRITE

Figure 62: Bank Write – Without Auto Precharge

T5n

T6n

CK#

CKE

NOP

Command

ACT

NOP

PRE

NOP

WRITE

Col n

NOP

Address

A10

All banks

One bank

Bank select

Bank x

RCD

WL = 2

RAS

WL DQSS (NOM)

DQS, DQS#

DQSL DQSH WPST

WPRE

Transitioning Data

Don’t Care

1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

Notes:

2. BL = 4 and AL = 0 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A10 is HIGH at T9.

5. Subsequent rising DQS signals must align to the clock within ^tDQSS.

6. DI n = data-in for column n; subsequent elements are applied in the programmed order.

7. ^tDSH is applicable during ^tDQSS (MIN) and is referenced from CK T5 or T6.

8. ^tDSS is applicable during ^tDQSS (MAX) and is referenced from CK T6 or T7.

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WRITE

Figure 63: Bank Write – with Auto Precharge

T5n

T6n

CK#

CKE

NOP

Command

NOP

ACT

NOP

WRITE

NOP

Col n

Address

A10

Bank select

Bank x

RCD

WL = 2

RAS

WL DQSS (NOM)

DQS, DQS#

DQSL DQSH WPST

WPRE

Transitioning Data

Don’t Care

1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

Notes:

2. BL = 4 and AL = 0 in the case shown.

3. Enable auto precharge.

4. WR is programmed via MR9–MR11 and is calculated by dividing ^tWR (in ns) by ^tCK and

rounding up to the next integer value.

5. Subsequent rising DQS signals must align to the clock within ^tDQSS.

6. DI n = data-in from column n; subsequent elements are applied in the programmed or-

der.

7. ^tDSH is applicable during ^tDQSS (MIN) and is referenced from CK T5 or T6.

8. ^tDSS is applicable during ^tDQSS (MAX) and is referenced from CK T6 or T7.

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WRITE

Figure 64: WRITE – DM Operation

T10

T11

T6 T6n T7 T7n T8

CK#

CKE

NOP

Command

ACT

PRE

NOP

WRITE

Col n

NOP

AL = 1

WL = 2

Address

All banks

One bank

A10

Bank select

Bank x

RCD

RPA

RAS

WL DQSS (NOM)

DQS, DQS#

DQSL DQSH WPST

WPRE

Transitioning Data

Don’t Care

1. NOP commands are shown for ease of illustration; other commands may be valid at

these times.

Notes:

2. BL = 4, AL = 1, and WL = 2 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A10 is HIGH at T11.

5. ^tWR starts at the end of the data burst regardless of the data mask condition.

6. Subsequent rising DQS signals must align to the clock within ^tDQSS.

7. DI n = data-in for column n; subsequent elements are applied in the programmed order.

8. ^tDSH is applicable during ^tDQSS (MIN) and is referenced from CK T6 or T7.

9. ^tDSS is applicable during ^tDQSS (MAX) and is referenced from CK T7 or T8.

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PRECHARGE

Figure 65: Data Input Timing

T1n

T2n

T3n

CK#

DSS

WL - DQSS (NOM)

DSH

DSS

DSH

DQS

DQS#

WPST

DQSL

DQSH

WPRE

Transitioning Data

Don’t Care

1. ^tDSH (MIN) generally occurs during ^tDQSS (MIN).

2. ^tDSS (MIN) generally occurs during ^tDQSS (MAX).

Notes:

3. Subsequent rising DQS signals must align to the clock within ^tDQSS.

4. WRITE command issued at T0.

5. For x16, LDQS controls the lower byte and UDQS controls the upper byte.

6. WRITE command with WL = 2 (CL = 3, AL = 0) issued at T0.

PRECHARGE

Precharge can be initiated by either a manual PRECHARGE command or by an autopre-

charge in conjunction with either a READ or WRITE command. Precharge will deacti-

vate the open row in a particular bank or the open row in all banks. The PRECHARGE

operation is shown in the previous READ and WRITE operation sections.

During a manual PRECHARGE command, the A1± input determines whether one or all

banks are to be precharged. In the case where only one bank is to be precharged, bank

address inputs determine the bank to be precharged. When all banks are to be pre-

charged, the bank address inputs are treated as “Don’t Care.”

Once a bank has been precharged, it is in the idle state and must be activated prior to

any READ or WRITE commands being issued to that bank. When a single-bank PRE-

CHARGE command is issued, ^tRP timing applies. When the PRECHARGE (ALL) com-

mand is issued, ^tRPA timing applies, regardless of the number of banks opened.

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REFRESH

The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average in-

terval of 7.8125μs (MAX) and all rows in all banks must be refreshed at least once every

64ms. The refresh period begins when the REFRESH command is registered and ends

^tRFC (MIN) later. The average interval must be reduced to 3.9μs (MAX) when T_Cexceeds

85°C.

Figure 66: Refresh Mode

Ta0

Ta1

Tb0

Tb1

Tb2

CK#

CKE

NOP

Command

NOP

PRE

NOP

REF

NOP

REF

NOP

ACT

Address

A10

All banks

One bank

Bank(s)³

Bank

DQS, DQS#

RFC (MIN)

RFC

Indicates a break in

time scale

Don’t Care

1. NOP commands are shown for ease of illustration; other valid commands may be possi-

ble at these times. CKE must be active during clock positive transitions.

Notes:

2. The second REFRESH is not required and is only shown as an example of two back-to-

back REFRESH commands.

3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is

active (must precharge all active banks).

4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.

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SELF REFRESH

The SELF REFRESH command is initiated when CKE is LOW. The differential clock

should remain stable and meet ^tCKE specifications at least 1 × ^tCK after entering self re-

fresh mode. The procedure for exiting self refresh requires a sequence of commands.

First, the differential clock must be stable and meet ^tCK specifications at least 1 × ^tCK

prior to CKE going back to HIGH. Once CKE is HIGH (^tCKE [MIN] has been satisfied

with three clock registrations), the DDR2 SDRAM must have NOP or DESELECT com-

mands issued for ^tXSNR. A simple algorithm for meeting both refresh and DLL require-

ments is used to apply NOP or DESELECT commands for 2±± clock cycles before apply-

ing any other command.

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SELF REFRESH

Figure 67: Self Refresh

Tb0

Tc0

Td0

Ta0

Ta1

Ta2

CK#

ISXR

CKE

Valid

Command

NOP

REF

NOP

Valid

ODT

AOFD/ AOFPD

Address

Valid

DQS#, DQS

2, 5, 10

XSNR

CKE (MIN)

XSRD

Enter self refresh

mode (synchronous)

Exit self refresh

mode (asynchronous)

Indicates a break in

time scale

Don’t Care

1. Clock must be stable and meeting ^tCK specifications at least 1 × ^tCK after entering self

refresh mode and at least 1 × ^tCK prior to exiting self refresh mode.

Notes:

2. Self refresh exit is asynchronous; however, ^tXSNR and ^tXSRD timing starts at the first ris-

ing clock edge where CKE HIGH satisfies ^tISXR.

3. CKE must stay HIGH until ^tXSRD is met; however, if self refresh is being re-entered, CKE

may go back LOW after ^tXSNR is satisfied.

4. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0,

which allows any nonREAD command.

5. ^tXSNR is required before any nonREAD command can be applied.

6. ODT must be disabled and R_TToff (^tAOFD and ^tAOFPD have been satisfied) prior to en-

tering self refresh at state T1.

7. ^tXSRD (200 cycles of CK) is required before a READ command can be applied at state

Td0.

8. Device must be in the all banks idle state prior to entering self refresh mode.

9. After self refresh has been entered, ^tCKE (MIN) must be satisfied prior to exiting self re-

fresh.

10. Upon exiting SELF REFRESH, ODT must remain LOW until ^tXSRD is satisfied.

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Power-Down Mode

DDR2 SDRAM supports multiple power-down modes that allow significant power sav-

ings over normal operating modes. CKE is used to enter and exit different power-down

modes. Power-down entry and exit timings are shown in Figure 68 (page 118). Detailed

power-down entry conditions are shown in Figure 69 (page 12±)–Figure 76 (page 123).

Table 44 (page 119) is the CKE Truth Table.

DDR2 SDRAM requires CKE to be registered HIGH (active) at all times that an access is

in progress—from the issuing of a READ or WRITE command until completion of the

burst. Thus, a clock suspend is not supported. For READs, a burst completion is defined

when the read postamble is satisfied; for WRITEs, a burst completion is defined when

the write postamble and ^tWR (WRITE-to-PRECHARGE command) or ^tWTR (WRITE-to-

READ command) are satisfied, as shown in Figure 71 (page 121) and Figure 72

(page 121) on Figure 72 (page 121). The number of clock cycles required to meet ^tWTR

is either two or ^tWTR/^tCK, whichever is greater.

Power-down mode (see Figure 68 (page 118)) is entered when CKE is registered low co-

incident with an NOP or DESELECT command. CKE is not allowed to go LOW during a

mode register or extended mode register command time, or while a READ or WRITE op-

eration is in progress. If power-down occurs when all banks are idle, this mode is refer-

red to as precharge power-down. If power-down occurs when there is a row active in

any bank, this mode is referred to as active power-down. Entering power-down deacti-

vates the input and output buffers, excluding CK, CK#, ODT, and CKE. For maximum

power savings, the DLL is frozen during precharge power-down. Exiting active power-

down requires the device to be at the same voltage and frequency as when it entered

power-down. Exiting precharge power-down requires the device to be at the same volt-

age as when it entered power-down; however, the clock frequency is allowed to change

(see Precharge Power-Down Clock Frequency Change (page 124)).

The maximum duration for either active or precharge power-down is limited by the re-

fresh requirements of the device ^tRFC (MAX). The minimum duration for power-down

entry and exit is limited by the ^tCKE (MIN) parameter. The following must be main-

tained while in power-down mode: CKE LOW, a stable clock signal, and stable power

supply signals at the inputs of the DDR2 SDRAM. All other input signals are “Don’t

Care” except ODT. Detailed ODT timing diagrams for different power-down modes are

shown in Figure 81 (page 129)–Figure 86 (page 133).

The power-down state is synchronously exited when CKE is registered HIGH (in con-

junction with a NOP or DESELECT command), as shown in Figure 68 (page 118).

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Power-Down Mode

Figure 68: Power-Down

CK#

Command

CKE

NOP

Valid

CKE (MIN)

Address

Valid

3 t 4

XP , XARD

XARDS

DQS, DQS#

Enter

Exit

power-down

mode

power-down

mode

Don’t Care

1. If this command is a PRECHARGE (or if the device is already in the idle state), then the

power-down mode shown is precharge power-down. If this command is an ACTIVATE

(or if at least one row is already active), then the power-down mode shown is active

power-down.

Notes:

2. ^tCKE (MIN) of three clocks means CKE must be registered on three consecutive positive

clock edges. CKE must remain at the valid input level the entire time it takes to achieve

the three clocks of registration. Thus, after any CKE transition, CKE may not transition

from its valid level during the time period of ^tIS + 2 × ^tCK + ^tIH. CKE must not transition

during its ^tIS and ^tIH window.

3. ^tXP timing is used for exit precharge power-down and active power-down to any non-

READ command.

4. ^tXARD timing is used for exit active power-down to READ command if fast exit is selec-

ted via MR (bit 12 = 0).

5. ^tXARDS timing is used for exit active power-down to READ command if slow exit is se-

lected via MR (bit 12 = 1).

6. No column accesses are allowed to be in progress at the time power-down is entered. If

the DLL was not in a locked state when CKE went LOW, the DLL must be reset after exit-

ing power-down mode for proper READ operation.

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Power-Down Mode

Table 44: Truth Table – CKE

Notes 1–4 apply to the entire table

CKE

Command (n)

Previous Cycle

Current

Cycle (n)

CS#, RAS#, CAS#,

WE#

Current State

(n - 1)

Action (n)

Notes

5, 6

Power-down

Maintain power-down

Power-down exit

Maintain self refresh

Self refresh exit

DESELECT or NOP

7, 8

Self refresh

DESELECT or NOP

7, 9, 10

7, 8, 11, 12

Bank(s) active

All banks idle

DESELECT or NOP Active power-down en-

try

DESELECT or NOP Precharge power-down

entry

7, 8, 11

Refresh

Self refresh entry

10, 12, 13

Shown in Table 37 (page 70)

1. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the

Notes:

previous clock edge.

2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n.

3. Command (n) is the command registered at clock edge n, and action (n) is a result of

command (n).

4. The state of ODT does not affect the states described in this table. The ODT function is

not available during self refresh (see ODT Timing (page 127) for more details and spe-

cific restrictions).

5. Power-down modes do not perform any REFRESH operations. The duration of power-

down mode is therefore limited by the refresh requirements.

6. “X” means “Don’t Care” (including floating around V_REF) in self refresh and power-

down. However, ODT must be driven high or low in power-down if the ODT function is

enabled via EMR.

7. All states and sequences not shown are illegal or reserved unless explicitly described

elsewhere in this document.

8. Valid commands for power-down entry and exit are NOP and DESELECT only.

9. On self refresh exit, DESELECT or NOP commands must be issued on every clock edge oc-

curring during the ^tXSNR period. READ commands may be issued only after ^tXSRD (200

clocks) is satisfied.

10. Valid commands for self refresh exit are NOP and DESELECT only.

11. Power-down and self refresh can not be entered while READ or WRITE operations,

LOAD MODE operations, or PRECHARGE operations are in progress. See SELF REFRESH

(page 115) and SELF REFRESH (page 76) for a list of detailed restrictions.

12. Minimum CKE high time is ^tCKE = 3 × ^tCK. Minimum CKE LOW time is ^tCKE = 3 × ^tCK.

This requires a minimum of 3 clock cycles of registration.

13. Self refresh mode can only be entered from the all banks idle state.

14. Must be a legal command, as defined in Table 37 (page 70).

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Power-Down Mode

Figure 69: READ-to-Power-Down or Self Refresh Entry

CK#

Command

READ

NOP

Valid

NOP

CKE (MIN)

CKE

Address

Valid

A10

DQS, DQS#

RL = 3

Power-down or

self refresh entry

Transitioning Data

Don’t Care

1. In the example shown, READ burst completes at T5; earliest power-down or self refresh

entry is at T6.

Notes:

2. Power-down or self refresh entry may occur after the READ burst completes.

Figure 70: READ with Auto Precharge-to-Power-Down or Self Refresh Entry

CK#

Command

NOP

READ

NOP

Valid

CKE (MIN)

CKE

Valid

Address

A10

DQS, DQS#

RL = 3

Power-down or

self refresh entry

Transitioning Data

Don’t Care

1. In the example shown, READ burst completes at T5; earliest power-down or self refresh

entry is at T6.

Notes:

2. Power-down or self refresh entry may occur after the READ burst completes.

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Power-Down Mode

Figure 71: WRITE-to-Power-Down or Self Refresh Entry

CK#

Command

WRITE

NOP

Valid

NOP

CKE (MIN)

CKE

Address

Valid

A10

DQS, DQS#

WL = 3

WTR

Power-down or

self refresh entry

Transitioning Data

Don’t Care

1. Power-down or self refresh entry may occur after the WRITE burst completes.

Note:

Figure 72: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry

Ta0

Ta1

Ta2

CK#

Command

WRITE

NOP

Valid

NOP

Valid

CKE (MIN)

CKE

Address

Valid

A10

DQS, DQS#

WL = 3

Power-down or

self refresh entry

Indicates a break in

time scale

Transitioning Data

Don’t Care

1. Internal PRECHARGE occurs at Ta0 when WR has completed; power-down entry may oc-

cur 1 x ^tCK later at Ta1, prior to ^tRP being satisfied.

Notes:

2. WR is programmed through MR9–MR11 and represents (^tWR [MIN] ns/^tCK) rounded up

to next integer ^tCK.

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Power-Down Mode

Figure 73: REFRESH Command-to-Power-Down Entry

CK#

Valid

REFRESH

NOP

Command

CKE (MIN)

CKE

1 x CK

Power-down

entry

Don’t Care

1. The earliest precharge power-down entry may occur is at T2, which is 1 × ^tCK after the

Note:

REFRESH command. Precharge power-down entry occurs prior to ^tRFC (MIN) being satis-

fied.

Figure 74: ACTIVATE Command-to-Power-Down Entry

CK#

Valid

ACT

NOP

Command

VALID

Address

CKE (MIN)

CKE

Power-down

entry

Don’t Care

1. The earliest active power-down entry may occur is at T2, which is 1 × ^tCK after the ACTI-

VATE command. Active power-down entry occurs prior to ^tRCD (MIN) being satisfied.

Note:

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Power-Down Mode

Figure 75: PRECHARGE Command-to-Power-Down Entry

CK#

Valid

PRE

NOP

Command

Valid

Address

A10

All banks

Single bank

^tCKE (MIN)

CKE

1 x ^tCK

Power-down

entry

Don’t Care

1. The earliest precharge power-down entry may occur is at T2, which is 1 × ^tCK after the

PRECHARGE command. Precharge power-down entry occurs prior to ^tRP (MIN) being sat-

isfied.

Note:

Figure 76: LOAD MODE Command-to-Power-Down Entry

CK#

Command

Valid

NOP

Address

Valid

CKE (MIN)

CKE

MRD

Power-down

entry

Don’t Care

1. Valid address for LM command includes MR, EMR, EMR(2), and EMR(3) registers.

2. All banks must be in the precharged state and ^tRP met prior to issuing LM command.

3. The earliest precharge power-down entry is at T3, which is after ^tMRD is satisfied.

Notes:

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Precharge Power-Down Clock Frequency Change

When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off

and CKE must be at a logic LOW level. A minimum of two differential clock cycles must

pass after CKE goes LOW before clock frequency may change. The device input clock

frequency is allowed to change only within minimum and maximum operating fre-

quencies specified for the particular speed grade. During input clock frequency change,

ODT and CKE must be held at stable LOW levels. When the input clock frequency is

changed, new stable clocks must be provided to the device before precharge power-

down may be exited, and DLL must be reset via MR after precharge power-down exit.

Depending on the new clock frequency, additional LM commands might be required to

adjust the CL, WR, AL, and so forth. Depending on the new clock frequency, an addi-

tional LM command might be required to appropriately set the WR MR9, MR1±, MR11.

During the DLL relock period of 2±± cycles, ODT must remain off. After the DLL lock

time, the DRAM is ready to operate with a new clock frequency.

Figure 77: Input Clock Frequency Change During Precharge Power-Down Mode

Previous clock frequency

T1 T2

New clock frequency

Ta2

Ta4

Ta1

Ta3

Tb0

Ta0

CK#

2 x CK (MIN)

1 x CK (MIN)

CKE (MIN)

CKE

CKE (MIN)

Command

NOP

Valid

Address

Valid

DLL RESET

ODT

High-Z

DQS, DQS#

Enter precharge

power-down mode

Frequency

change

Exit precharge

power-down mode

200 x CK

Indicates a break in

time scale

Don’t Care

1. A minimum of 2 × ^tCK is required after entering precharge power-down prior to chang-

ing clock frequencies.

Notes:

2. When the new clock frequency has changed and is stable, a minimum of 1 × ^tCK is re-

quired prior to exiting precharge power-down.

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Reset

3. Minimum CKE high time is ^tCKE = 3 × ^tCK. Minimum CKE LOW time is ^tCKE = 3 × ^tCK.

This requires a minimum of three clock cycles of registration.

4. If this command is a PRECHARGE (or if the device is already in the idle state), then the

power-down mode shown is precharge power-down, which is required prior to the clock

frequency change.

Reset

CKE Low Anytime

DDR2 SDRAM applications may go into a reset state anytime during normal operation.

If an application enters a reset condition, CKE is used to ensure the DDR2 SDRAM de-

vice resumes normal operation after reinitializing. All data will be lost during a reset

condition; however, the DDR2 SDRAM device will continue to operate properly if the

following conditions outlined in this section are satisfied.

The reset condition defined here assumes all supply voltages (V_DD, V_DDQ, V_DDL, and

V_REF) are stable and meet all DC specifications prior to, during, and after the RESET op-

eration. All other input balls of the DDR2 SDRAM device are a “Don’t Care” during RE-

SET with the exception of CKE.

If CKE asynchronously drops LOW during any valid operation (including a READ or

WRITE burst), the memory controller must satisfy the timing parameter ^tDELAY before

turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM be-

fore CKE is raised HIGH, at which time the normal initialization sequence must occur

(see Initialization). The DDR2 SDRAM device is now ready for normal operation after

the initialization sequence. Figure 78 (page 126) shows the proper sequence for a RE-

SET operation.

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Reset

Figure 78: RESET Function

Tb0

Ta0

CK#

CKE (MIN)

DELAY

CKE

ODT

Command

READ

Col n

READ

Col n

PRE

NOP

Address

A10

All banks

Bank address

Bank a

Bank b

ꢃ

High-Z

DQS

High-Z

System

RESET

RPA

T = 400ns (MIN)

Start of normal

initialization

sequence

Indicates a break in

time scale

Unknown

Transitioning Data

Don’t Care

1. V_DD, V_DDL, V_DDQ, V_TT, and V_REFmust be valid at all times.

2. Either NOP or DESELECT command may be applied.

Notes:

3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS

represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, and RDQS# for the appropri-

ate configuration (x4, x8, x16).

4. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the

completion of the burst.

5. Initialization timing is shown in Figure 41 (page 87).

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ODT Timing

Once a 12ns delay (^tMOD) has been satisfied, and after the ODT function has been ena-

bled via the EMR LOAD MODE command, ODT can be accessed under two timing cate-

gories. ODT will operate either in synchronous mode or asynchronous mode, depend-

ing on the state of CKE. ODT can switch anytime except during self refresh mode and a

few clocks after being enabled via EMR, as shown in Figure 79 (page 128).

There are two timing categories for ODT—turn-on and turn-off. During active mode

(CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW,

MR[12 = ±]), ^tAOND, ^tAON, ^tAOFD, and ^tAOF timing parameters are applied, as shown in

Figure 81 (page 129).

During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1)

and precharge power-down mode (all banks/rows precharged and idle, CKE LOW),

^tAONPD and ^tAOFPD timing parameters are applied, as shown in Figure 82 (page 13±).

ODT turn-off timing, prior to entering any power-down mode, is determined by the pa-

rameter ^tANPD (MIN), as shown in Figure 83 (page 13±). At state T2, the ODT HIGH sig-

nal satisfies ^tANPD (MIN) prior to entering power-down mode at T5. When ANPD

(MIN) is satisfied, ^tAOFD and ^tAOF timing parameters apply. Figure 83 (page 13±) also

shows the example where ^tANPD (MIN) is not satisfied because ODT HIGH does not oc-

cur until state T3. When ANPD (MIN) is not satisfied, ^tAOFPD timing parameters apply.

ODT turn-on timing prior to entering any power-down mode is determined by the pa-

rameter ^tANPD, as shown in Figure 84 (page 131). At state T2, the ODT HIGH signal sat-

isfies ^tANPD (MIN) prior to entering power-down mode at T5. When ANPD (MIN) is

satisfied, ^tAOND and ^tAON timing parameters apply. Figure 84 (page 131) also shows

the example where ^tANPD (MIN) is not satisfied because ODT HIGH does not occur un-

til state T3. When ANPD (MIN) is not satisfied, ^tAONPD timing parameters apply.

ODT turn-off timing after exiting any power-down mode is determined by the parame-

ter ^tAXPD (MIN), as shown in Figure 85 (page 132). At state Ta1, the ODT LOW signal

satisfies ^tAXPD (MIN) after exiting power-down mode at state T1. When AXPD (MIN) is

satisfied, ^tAOFD and ^tAOF timing parameters apply. Figure 85 (page 132) also shows the

example where ^tAXPD (MIN) is not satisfied because ODT LOW occurs at state Ta±.

When ^tAXPD (MIN) is not satisfied, ^tAOFPD timing parameters apply.

ODT turn-on timing after exiting either slow-exit power-down mode or precharge pow-

er-down mode is determined by the parameter ^tAXPD (MIN), as shown in Figure 86

(page 133). At state Ta1, the ODT HIGH signal satisfies ^tAXPD (MIN) after exiting pow-

er-down mode at state T1. When AXPD (MIN) is satisfied, ^tAOND and ^tAON timing pa-

rameters apply. Figure 86 (page 133) also shows the example where ^tAXPD (MIN) is not

satisfied because ODT HIGH occurs at state Ta±. When AXPD (MIN) is not satisfied,

^tAONPD timing parameters apply.

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ODT Timing

Figure 79: ODT Timing for Entering and Exiting Power-Down Mode

Synchronous

Synchronous or

Asynchronous

Synchronous

ANPD (3 CKs)

First CKE latched LOW

AXPD (8 CKs)

First CKE latched HIGH

CKE

Any mode except

self refresh mode

Any mode except

self refresh mode

Active power-down fast (synchronous)

Active power-down slow (asynchronous)

Precharge power-down (asynchronous)

Applicable modes

AOND/ AOFD

AOND/ AOFD (synchronous)

AONPD/ AOFPD (asynchronous)

Applicable timing parameters

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ODT Timing

MRS Command to ODT Update Delay

During normal operation, the value of the effective termination resistance can be

changed with an EMRS set command. ^tMOD (MAX) updates the R_TTsetting.

Figure 80: Timing for MRS Command to ODT Update Delay

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

EMRS

NOP

Command

CK#

ODT

MOD

AOFD

0ns

Internal

_TTsetting

Old setting

Undefined

New setting

Indicates a break in

time scale

1. The LM command is directed to the mode register, which updates the information in

EMR (A6, A2), that is, R_TT(nominal).

Notes:

2. To prevent any impedance glitch on the channel, the following conditions must be met:

^tAOFD must be met before issuing the LM command; ODT must remain LOW for the en-

tire duration of the ^tMOD window until ^tMOD is met.

Figure 81: ODT Timing for Active or Fast-Exit Power-Down Mode

CK#

Valid

Command

Address

CKE

AOND

ODT

AOFD

AON (MIN)

AOF (MAX)

AOF (MIN)

AON (MAX)

Unknown

Don’t Care

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ODT Timing

Figure 82: ODT Timing for Slow-Exit or Precharge Power-Down Modes

CK#

Valid

Command

Address

CKE

ODT

AONPD (MAX)

AONPD (MIN)

R_TT

AOFPD (MIN)

AOFPD (MAX)

Transitioning R_TT

R_TTUnknown

R_TTOn

Don’t Care

Figure 83: ODT Turn-Off Timings When Entering Power-Down Mode

CK#

NOP

Command

ANPD (MIN)

CKE

AOFD

ODT

AOF (MAX)

AOF (MIN)

AOFPD (MAX)

ODT

AOFPD (MIN)

Transitioning R

Unknown

R ON

Don’t Care

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ODT Timing

Figure 84: ODT Turn-On Timing When Entering Power-Down Mode

CK#

Command

NOP

ANPD (MIN)

CKE

ODT

AOND

AON (MAX)

AON (MIN)

ODT

AONPD (MAX)

AONPD (MIN)

Transitioning R

Unknown

R On

Don’t Care

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ODT Timing

Figure 85: ODT Turn-Off Timing When Exiting Power-Down Mode

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

CK#

NOP

Command

CKE

AXPD (MIN)

CKE (MIN)

AOFD

ODT

AOF (MAX)

AOF (MIN)

AOFPD (MAX)

ODT

AOFPD (MIN)

Indicates a break in

time scale

Unknown

Transitioning R

Don’t Care

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ODT Timing

Figure 86: ODT Turn-On Timing When Exiting Power-Down Mode

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

CK#

Command

NOP

AXPD (MIN)

CKE

CKE (MIN)

ODT

AOND

AON (MAX)

AON (MIN)

ODT

AONPD (MAX)

AONPD (MIN)

Indicates a break in

time scale

Unknown

Transitioning R

Don’t Care

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

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133

MT47H64M8B6-25ELDTR [MICRON]

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