MT48LC2M32B2TG [MICRON]
SYNCHRONOUS DRAM; 同步DRAM
| 型号： | MT48LC2M32B2TG |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | SYNCHRONOUS DRAM |
| 文件： | 总53页 (文件大小：1810K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
64Mb: x32
SDRAM
MT48LC2M32B2 - 512K x 32 x 4 banks
SYNCHRONOUS
DRAM
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/sdramds
FEATURES
• PC100 functionality
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh (15.6µs/row)
• LVTTL-compatible inputs and outputs
• Single +3.3V 0.3V power supply
• Supports CAS latency of 1, 2, and 3
PINASSIGNMENT(TOPVIEW)
86-PINTSOP
V
DQ0
DD
1
2
3
4
5
6
7
8
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
9
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
V
SS
Q
DQ7
NC
V
DQM0
WE#
CAS#
RAS#
CS#
DD
OPTIONS
• Configuration
2 Meg x 32 (512K x 32 x 4 banks)
• Plastic Package - OCPL1
86-pin TSOP (400 mil)
MARKING
NC
2M32B2
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
NC
TG
BA0
BA1
A10
A0
A1
A2
DQM2
V
NC
DQ16
• Timing (Cycle Time)
5ns (200 MHz)
5.5ns (183 MHz)
6ns (166 MHz)
7ns (143 MHz)
-5
-55
-6
DD
-7
• Operating Temperature Range
Commercial (0° to +70°C)
V
SS
Q
DQ17
DQ18
None
IT2
Extended (-40°C to +85°C)
V
DD
Q
DQ19
DQ20
NOTE: 1. Off-center parting line
V
SS
Q
VDDQ
DQ26
DQ25
VSSQ
DQ24
2. Available on -7
DQ21
DQ22
Part Number Example:
V
DD
Q
MT48LC2M32B2TG-7
DQ23
V
DD
VSS
KEYTIMINGPARAMETERS
Note: The # symbol indicates signal is active LOW.
SPEED
GRADE FREQUENCY
CLOCK
ACCESS TIME SETUP
HOLD
TIME
CL = 3*
TIME
2 Meg x 32
-5
-55
-6
200MHz
183MHz
166MHz
143MHz
4.5ns
5ns
5.5ns
5.5ns
1.5ns
1.5ns
1.5ns
2ns
1ns
1ns
1ns
1ns
Configuration
512K x 32 x 4 banks
4K
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
2K (A0-A10)
4 (BA0, BA1)
256 (A0-A7)
-7
*CL = CAS (READ) latency
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
1
64Mb: x32
SDRAM
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.
64Mb (x32) SDRAM PART NUMBER
PART NUMBER
ARCHITECTURE
MT48LC2M32B2TG
2 Meg x 32
The 64Mb SDRAM uses an internal pipelined archi-
tecture to achieve high-speed operation. This archi-
tecture is compatible with the 2n rule of prefetch archi-
tectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while ac-
cessing one of the other three banks will hide the
precharge cycles and provide seamless, high-speed,
random-access operation.
The 64Mb SDRAM is designed to operate in 3.3V,
low-power memory systems. An auto refresh mode is
provided, along with a power-saving, power-down
mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM oper-
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks to hide precharge time and
the capability to randomly change column addresses
on each clock cycle during a burst access.
GENERALDESCRIPTION
The 64Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 67,108,864-bits. It
is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
16,777,216-bit banks is organized as 2,048 rows by 256
columns by 32 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0, BA1
select the bank, A0-A10 select the row). The address
bits registered coincident with the READ or WRITE com-
mand are used to select the starting column location
for the burst access.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
2
64Mb: x32
SDRAM
TABLEOFCONTENTS
Functional Block Diagram - 2 Meg x 32 .................
Pin Descriptions .....................................................
4
5
Concurrent Auto Precharge .............................. 23
Write with Auto Precharge ............................... 24
Truth Table 2 (CKE) ................................................ 25
Truth Table 3 (Current State, Same Bank) ..................... 26
Truth Table 4 (Current State, Different Bank) ................. 28
Absolute Maximum Ratings .................................. 30
DCElectricalCharacteristics
and Operating Conditions...................................... 30
IDD Specifications and Conditions ......................... 30
Capacitance ............................................................ 32
Functional Description.........................................
Initialization ......................................................
Register Definition ............................................
Mode Register ...............................................
Burst Length............................................
Burst Type ...............................................
CAS Latency ............................................
Operating Mode ......................................
Write Burst Mode ....................................
Commands ............................................................
Truth Table 1 (Commands and DQM Operation) ............
6
6
6
6
6
7
8
8
8
9
9
AC Electrical Characteristics (Timing Table) .... 32
AC Electrical Characteristics ................................... 34
Timing Waveforms
Command Inhibit ............................................. 10
No Operation (NOP).......................................... 10
Load Mode Register ........................................... 10
Active ................................................................ 10
Read ................................................................ 10
Write ................................................................ 10
Precharge ........................................................... 10
Auto Precharge .................................................. 10
Burst Terminate ................................................. 11
Auto Refresh ...................................................... 11
Self Refresh ........................................................ 11
Operation ............................................................... 12
Bank/Row Activation ........................................ 12
Reads ................................................................ 13
Writes ................................................................ 19
Precharge ........................................................... 21
Power-Down ...................................................... 21
Clock Suspend .................................................. 22
Burst Read/Single Write .................................... 22
Initialize and Load Mode Register .................... 36
Power-Down Mode .......................................... 37
Clock Suspend Mode........................................ 38
Auto Refresh Mode ........................................... 39
Self Refresh Mode ............................................. 40
Reads
Read – Single Read....................................... 41
Read – Without Auto Precharge ................. 42
Read – With Auto Precharge ....................... 43
Alternating Bank Read Accesses .................. 44
Read – Full-Page Burst ................................. 45
Read – DQM Operation .............................. 46
Writes
Write – Single Write ..................................... 47
Write – Without Auto Precharge ................ 48
Write – With Auto Precharge ...................... 49
Alternating Bank Write Accesses ................. 50
Write – Full-Page Burst ................................ 51
Write – DQM Operation ............................. 52
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
3
64Mb: x32
SDRAM
FUNCTIONALBLOCKDIAGRAM
2 Meg x 32 SDRAM
CKE
CLK
CONTROL
LOGIC
CS#
WE#
BANK3
CAS#
RAS#
BANK2
BANK1
BANK0
REFRESH
COUNTER
11
MODE REGISTER
11
BANK0
ROW-
ADDRESS
LATCH
&
ROW-
ADDRESS
MUX
11
BANK0
MEMORY
ARRAY
4
4
2048
DQM0-
DQM3
11
(2,048 x 256 x 32)
DECODER
DATA
OUTPUT
REGISTER
SENSE AMPLIFIERS
8192
32
DQ0-
DQ31
I/O GATING
2
32
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
BANK
CONTROL
LOGIC
A0-A10,
BA0, BA1
ADDRESS
REGISTER
13
DATA
INPUT
REGISTER
2
32
256
(x32)
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
8
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
4
64Mb: x32
SDRAM
PINDESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
68
CLK
Input Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counterandcontrolstheoutputregisters.
67
CKE
Input ClockEnable:CKEactivates(HIGH)anddeactivates(LOW)theCLKsignal.
DeactivatingtheclockprovidesPRECHARGEPOWER-DOWNandSELFREFRESH
operation(allbanksidle),ACTIVEPOWER-DOWN(rowactiveinanybank)or
CLOCKSUSPENDoperation(burst/accessinprogress).CKEissynchronous
exceptafterthedeviceenterspower-downandselfrefreshmodes,where
CKEbecomesasynchronousuntilafterexitingthesamemode.Theinput
buffers,includingCLK,aredisabledduringpower-downandselfrefresh
modes,providinglowstandbypower.CKEmaybetiedHIGH.
20
CS#
Input ChipSelect:CS#enables(registeredLOW)anddisables(registeredHIGH)the
commanddecoder.AllcommandsaremaskedwhenCS#isregisteredHIGH.
CS#providesforexternalbankselectiononsystemswithmultiplebanks.
CS#isconsideredpartofthecommandcode.
17, 18, 19
WE#,CAS#, Input CommandInputs:WE#,CAS#,andRAS#(alongwithCS#)definethe
RAS#
commandbeingentered.
16, 71, 28, 59
DQM0-
DQM3
Input Input/OutputMask:DQMissampledHIGHandisaninputmasksignal
for write accesses and an output enable signal for read accesses. Input data
ismaskedduringaWRITEcycle. TheoutputbuffersareplacedinaHigh-Z
state(two-clocklatency)duringaREADcycle.DQM0correspondstoDQ0-
DQ7;DQM1correspondstoDQ8-DQ15;DQM2correspondstoDQ16-DQ23;
andDQM3correspondstoDQ24-DQ31.DQM0-DQM3areconsideredsame
statewhenreferencedasDQM.
22, 23
BA0,BA1
A0-A10
Input BankAddressInput(s):BA0andBA1definetowhichbanktheACTIVE,READ,
WRITEorPRECHARGEcommandisbeingapplied.
25-27, 60-66, 24
Input AddressInputs:A0-A10aresampledduringtheACTIVEcommand(row-
addressA0-A10)andREAD/WRITEcommand(column-addressA0-A7withA10
definingautoprecharge)toselectonelocationoutofthememoryarrayin
therespectivebank.A10issampledduringaPRECHARGEcommandto
determineifallbanksaretobeprecharged(A10HIGH)orbankselectedby
BA0,BA1(LOW).Theaddressinputsalsoprovidetheop-codeduringaLOAD
MODEREGISTERcommand.
2, 4, 5, 7, 8, 10, 11, 13,
74, 76, 77, 79, 80, 82, 83,
85, 31, 33, 34, 36, 37, 39,
40, 42, 45, 47, 48, 50, 51,
53, 54, 56
DQ0-DQ31 Input/ Data I/Os: Data bus.
Output
14, 21, 30, 57, 69, 70, 73
NC
–
NoConnect:Thesepinsshouldbeleftunconnected.Pin70isreserved
forSSTLreferencevoltagesupply.
3, 9, 35, 41, 49, 55, 75, 81
6, 12, 32, 38, 46, 52, 78, 84
1, 15, 29, 43
V
DD
Q
Supply DQ PowerSupply: Isolatedonthedieforimprovednoiseimmunity.
Supply DQ Ground:ProvideisolatedgroundtoDQsforimprovednoiseimmunity.
Supply PowerSupply:+3.3V 0.3V. (Seenote27onpage35.)
Supply Ground.
V
SS
Q
V
DD
44, 58, 72, 86
V
SS
64Mb: x32 SDRAM
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
5
©2002,MicronTechnology,Inc.
64Mb: x32
SDRAM
FUNCTIONALDESCRIPTION
RegisterDefinition
In general, this 64Mb SDRAM (512K x 32 x 4 banks) is
a quad-bank DRAM that operates at 3.3V and includes
a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the
16,777,216-bit banks is organized as 2,048 rows by 256
columns by 32-bits.
MODE REGISTER
The Mode Register is used to define the specific
mode of operation of the SDRAM. This definition in-
cludes the selection of a burst length, a burst type, a
CAS latency, an operating mode and a write burst mode,
as shown in Figure 1. The Mode Register is programmed
via the LOAD MODE REGISTER command and will re-
tain the stored information until it is programmed again
or the device loses power.
Mode Register bits M0-M2 specify the burst length,
M3 specifies the type of burst (sequential or inter-
leaved), M4-M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write burst
mode, and M10 is reserved for future use.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0 and BA1
select the bank, A0-A10 select the row). The address
bits (A0-A7) registered coincident with the READ or
WRITE command are used to select the starting col-
umn location for the burst access.
The Mode Register must be loaded when all banks
are idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating
either of these requirements will result in unspecified
operation.
Prior to normal operation, the SDRAM must be ini-
tialized. The following sections provide detailed infor-
mation covering device initialization, register defini-
tion, command descriptions and device operation.
Burst Length
Read and write accesses to the SDRAM are burst
oriented, with the burst length being programmable,
as shown in Figure 1. The burst length determines the
maximum number of column locations that can be ac-
cessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4, or 8 locations are available for both the
sequential and the interleaved burst types, and a full-
page burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst
lengths.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to VDD and VDDQ (simulta-
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COMMAND
INHIBIT or a NOP. Starting at some point during this
100µs period and continuing at least through the end
of this period, COMMAND INHIBIT or NOP commands
should be applied.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached. The block is uniquely se-
lected by A1-A7 when the burst length is set to two; by
A2-A7 when the burst length is set to four; and by A3-A7
when the burst length is set to eight. The remaining
(least significant) address bit(s) is (are) used to select
the starting location within the block. Full-page bursts
wrap within the page if the boundary is reached.
Once the 100µs delay has been satisfied with at
least one COMMAND INHIBIT or NOP command hav-
ing been applied, a PRECHARGE command should be
applied. All banks must then be precharged, thereby
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for Mode Register
programming. Because the Mode Register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
6
64Mb: x32
SDRAM
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 1.
Table 1
Burst Definition
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
A0
0
1
0-1
1-0
0-1
1-0
2
4
A1 A0
Figure 1
Mode Register Definition
0
0
1
1
0
1
0
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
A8
A6 A5 A4
A1
Address Bus
A10
A7
A3 A2
A0
A9
A2 A1 A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn-1,
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
9
8
6
5
4
1
10
7
3
2
0
Mode Register (Mx)
Reserved* WB Op Mode CAS Latency
BT
Burst length
1. *Should program
8
A10, BA0, and BA1= “0”
to ensure compatibility
with future device
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
Full
Page
(256)
n = A0-A7
8
Not Supported
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
(Location0-256)
Cn…
NOTE: 1. For a burst length of two, A1-A7 select the block-
of-two burst; A0 selects the starting column
within the block.
Burst Type
M3
0
2. For a burst length of four, A2-A7 select the block-
of-four burst; A0-A1 select the starting column
within the block.
Sequential
Interleave
1
CAS Latency
M6 M5 M4
3. For a burst length of eight, A3-A7 select the block-
of-eight burst; A0-A2 select the starting column
within the block.
4. For a full-page burst, the full row is selected and
A0-A7 select the starting column.
5. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
6. For a burst length of one, A0-A7 select the unique
column to be accessed, and mode register bit M3
is ignored.
Reserved
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
Reserved
Reserved
Reserved
Reserved
M8
0
M7
0
M6 - M0
Defined
-
Operating Mode
Standard operation
All other states reserved
-
-
Write Burst Mode
M9
0
1
Programmed Burst Length
Single Location Access
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
7
64Mb: x32
SDRAM
CAS Latency
The CAS latency is the delay, in clock cycles, be-
tween the registration of a READ command and the
availability of the first piece of output data. The la-
tency can be set to one, two or three clocks.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available by
clock edge n + m. The DQs will start driving as a result of
the clock edge one cycle earlier (n + m - 1), and provided
that the relevant access times are met, the data will be
valid by clock edge n + m. For example, assuming that
the clock cycle time is such that all relevant access times
are met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as
shown in Figure 2. Table 2 below indicates the operat-
ing frequencies at which each CAS latency setting can
be used.
Operating Mode
The normal operating mode is selected by setting
M7 and M8 to zero; the other combinations of values for
M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via
M0-M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (nonburst)
accesses.
Figure 2
CAS Latency
Table 2
T0
T1
T2
CAS Latency
CLK
COMMAND
READ
NOP
t
ALLOWABLE OPERATING
FREQUENCY (MHz)
t
LZ
OH
DOUT
DQ
t
AC
CAS
CAS
CAS
SPEED
- 5
-55
- 6
- 7
LATENCY = 1 LATENCY = 2 LATENCY = 3
CAS Latency = 1
-
-
≤200
≤183
≤166
≤143
-
-
≤50
≤50
≤100
≤100
T0
T1
T2
T3
CLK
COMMAND
READ
NOP
t
NOP
t
LZ
OH
DOUT
DQ
t
AC
CAS Latency = 2
T0
T1
T2
T3
T4
CLK
COMMAND
READ
NOP
NOP
NOP
t
t
LZ
OH
DOUT
DQ
t
AC
CAS Latency = 3
DON’T CARE
UNDEFINED
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64Mb: x32
SDRAM
Commands
Truth Table 1 provides a quick reference of avail-
able commands. This is followed by a written descrip-
tion of each command. Three additional Truth Tables
appear following the Operation section; these tables
provide current state/next state information.
TRUTH TABLE 1 – COMMANDS AND DQM OPERATION
(Note: 1)
NAME (FUNCTION)
CS# RAS# CAS# WE# DQM
ADDR
DQs NOTES
COMMAND INHIBIT (NOP)
H
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
X
X
X
X
X
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
Bank/Row
X
X
3
4
4
H
H
H
L
L/H8 Bank/Col
L/H8 Bank/Col
L
Valid
Active
X
H
H
L
L
X
X
X
X
Code
X
PRECHARGE (Deactivate row in bank or banks)
L
5
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
L
H
X
6, 7
LOAD MODE REGISTER
L
–
L
–
–
L
–
–
L
–
–
X
L
Op-Code
X
2
8
8
Write Enable/Output Enable
Write Inhibit/Output High-Z
–
–
Active
High-Z
–
H
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A10 define the op-code written to the Mode Register.
3. A0-A10 provide row address, BA0 and BA1 determine which bank is made active.
4. A0-A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while
A10 LOW disables the auto precharge feature; BA0 and BA1 determine which bank is being read from
or written to.
5. A10 LOW: BA0 and BA1 determine the bank being precharged. A10 HIGH: All banks precharged and
BA0 and BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0
controls DQ0-DQ7; DQM1 controls DQ8-DQ15; DQM2 controls DQ16-DQ23; and DQM3 controls
DQ24-DQ31.
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64Mb: x32
SDRAM
COMMAND INHIBIT
WRITE
The COMMAND INHIBIT function prevents new
commands from being executed by the SDRAM, re-
gardless of whether the CLK signal is enabled. The
SDRAM is effectively deselected. Operations already
in progress are not affected.
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0 and BA1
inputs selects the bank, and the address provided on
inputs A0-A7 selects the starting column location. The
value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
WRITE burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Input data
appearing on the DQs is written to the memory array
subject to the DQM input logic level appearing coinci-
dent with the data. If a given DQM signal is registered
LOW, the corresponding data will be written to memory;
if the DQM signal is registered HIGH, the correspond-
ing data inputs will be ignored, and a WRITE will not be
executed to that byte/column location.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to
perform a NOP to an SDRAM which is selected (CS# is
LOW). This prevents unwanted commands from being
registered during idle or wait states. Operations already
in progress are not affected.
LOAD MODE REGISTER
The mode register is loaded via inputs A0-A10. See
mode register heading in the Register Definition sec-
tion. The LOAD MODE REGISTER command can only
be issued when all banks are idle, and a subsequent
executable command cannot be issued until MRD is
met.
PRECHARGE
t
The PRECHARGE command is used to deactivate
the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access a specified time (tRP) after the PRECHARGE
command is issued. Input A10 determines whether
one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0
and BA1 select the bank. Otherwise BA0 and BA1 are
treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank.
ACTIVE
The ACTIVE command is used to open (or activate)
a row in a particular bank for a subsequent access. The
value on the BA0 and BA1 inputs selects the bank, and
the address provided on inputs A0-A10 selects the row.
This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before open-
ing a different row in the same bank.
READ
AUTO PRECHARGE
The READ command is used to initiate a burst read
access to an active row. The value on the BA0 and BA1
(B1) inputs selects the bank, and the address provided
on inputs A0-A7 selects the starting column location.
The value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
READ burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Read data
appears on the DQs subject to the logic level on the
DQM inputs two clocks earlier. If a given DQMx signal
was registered HIGH, the corresponding DQs will be
High-Z two clocks later; if the DQMx signal was regis-
tered LOW, the corresponding DQs will provide valid
data. DQM0 corresponds to DQ0-DQ7, DQM1 corre-
sponds to DQ8-DQ15, DQM2 corresponds to DQ16-
DQ23 and DQM3 corresponds to DQ24-DQ31.
Auto precharge is a feature which performs the
same individual-bank PRECHARGE function de-
scribed above, without requiring an explicit command.
This is accomplished by using A10 to enable auto
precharge in conjunction with a specific READ or WRITE
command. A PRECHARGE of the bank/row that is ad-
dressed with the READ or WRITE command is auto-
matically performed upon completion of the READ or
WRITE burst, except in the full-page burst mode, where
auto precharge does not apply. Auto precharge is non-
persistent in that it is either enabled or disabled for
each individual READ or WRITE command.
Auto precharge ensures that the precharge is initi-
ated at the earliest valid stage within a burst. The user
must not issue another command to the same bank
until the precharge time (tRP) is completed. This is
determined as if an explicit PRECHARGE command
was issued at the earliest possible time, as described
for each burst type in the Operation section of this data
sheet.
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64Mb: x32
SDRAM
BURST TERMINATE
SELF REFRESH
The BURST TERMINATE command is used to trun-
cate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated,
as shown in the Operation section of this data sheet.
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
SDRAM retains data without external clocking. The SELF
REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). Once the SELF
REFRESH command is registered, all the inputs to the
SDRAM become “Don’t Care” with the exception of
CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM pro-
vides its own internal clocking, causing it to perform its
own AUTO REFRESH cycles. The SDRAM must remain
in self refresh mode for a minimum period equal to
tRAS and may remain in self refresh mode for an indefi-
nite period beyond that.
The procedure for exiting self refresh requires a se-
quence of commands. First, CLK must be stable (stable
clock is defined as a signal cycling within timing con-
straints specified for the clock pin) prior to CKE going
back HIGH. Once CKE is HIGH, the SDRAM must have
NOP commands issued (a minimum of two clocks) for
tXSR because time is required for the completion of any
internal refresh in progress.
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analagous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This com-
mand is nonpersistent, so it must be issued each time
a refresh is required.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The 64Mb
SDRAM requires 4,096 AUTO REFRESH cycles every
64ms (tREF), regardless of width option. Providing a
distributed AUTO REFRESH command every 15.625µs
will meet the refresh requirement and ensure that each
row is refreshed. Alternatively, 4,096 AUTO REFRESH
commands can be issued in a burst at the minimum
cycle rate (tRC), once every 64ms.
Upon exiting SELF REFRESH mode, AUTO REFRESH
commands must be issued every 15.625ms or less as
both SELF REFRESH and AUTO REFRESH utililze the
row refresh counter.
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64Mb: x32
SDRAM
Operation
Figure 3
Activating a Specific Row in a
Specific Bank
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be is-
sued to a bank within the SDRAM, a row in that bank
must be “opened.” This is accomplished via the AC-
TIVE command, which selects both the bank and the
row to be activated. See Figure 3.
CLK
After opening a row (issuing an ACTIVE command),
a READ or WRITE command may be issued to that row,
CKE
CS#
HIGH
t
t
subject to the RCD specification. RCD (MIN) should
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE
t
command can be issued. For example, a RCD specifi-
RAS#
cation of 20ns with a 125 MHz clock (8ns period) results
in 2.5 clocks, rounded to 3. This is reflected in Figure 4,
t
which covers any case where 2 < RCD (MIN)/tCK - 3.
CAS#
WE#
(The same procedure is used to convert other specifi-
cation limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
ROW
ADDRESS
A0–A10
t
mands to the same bank is defined by RC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
tRRD.
BANK
ADDRESS
BA0, BA1
Figure 4
Example: Meeting RCD (MIN) When 2 < RCD (MIN)/ CK - 3
t
t
t
T0
T1
T2
T3
CLK
t
t
t
CK
CK
CK
READ or
WRITE
COMMAND
ACTIVE
NOP
NOP
t
RCD (MIN)
t
t
RCD (MIN) +0.5 CK
t
t
t
RCD (MIN) = 20ns, CK = 8ns
RCD (MIN) x CK
DON’T CARE
t
where x = number of clocks for equation to be true.
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64Mb: x32
SDRAM
READs
READ bursts are initiated with a READ command,
as shown in Figure 5.
Upon completion of a burst, assuming no other com-
mands have been initiated, the DQs will go High-Z. A
full-page burst will continue until terminated. (At the
end of the page, it will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixed-
length READ burst may be immediately followed by
data from a READ command. In either case, a continu-
ous flow of data can be maintained. The first data ele-
ment from the new burst follows either the last ele-
ment of a completed burst or the last desired data ele-
ment of a longer burst that is being truncated. The new
READ command should be issued x cycles before the
clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This
is shown in Figure 7 for CAS latencies of one, two and
The starting column and bank addresses are pro-
vided with the READ command, and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric READ commands used in the following illustra-
tions, auto precharge is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available fol-
lowing the CAS latency after the READ command. Each
subsequent data-out element will be valid by the next
positive clock edge. Figure 6 shows general timing for
each possible CAS latency setting.
Figure 6
Figure 5
CAS Latency
READ Command
T0
T1
T2
CLK
CLK
COMMAND
CKE
CS#
HIGH
READ
NOP
t
t
LZ
OH
DOUT
DQ
t
AC
CAS Latency = 1
RAS#
T0
T1
T2
T3
CAS#
WE#
CLK
COMMAND
READ
NOP
t
NOP
t
LZ
OH
DOUT
DQ
t
COLUMN
ADDRESS
AC
A0–A7
A8, A9
CAS Latency = 2
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
T0
T1
T2
T3
T4
A10
CLK
COMMAND
READ
NOP
NOP
NOP
t
t
BANK
ADDRESS
LZ
OH
BA0, 1
DOUT
DQ
t
AC
CAS Latency = 3
DON’T CARE
UNDEFINED
64Mb: x32 SDRAM
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64Mb: x32
SDRAM
three; data element n + 3 is either the last of a burst of
four or the last desired of a longer burst. This 64Mb
SDRAM uses a pipelined architecture and therefore
does not require the 2n rule associated with a prefetch
architecture. A READ command can be initiated on any
clock cycle following a previous READ command. Full-
speed random read accesses can be performed to the
same bank, as shown in Figure 8, or each subsequent
READ may be performed to a different bank.
Figure 7
Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
CLK
READ
NOP
NOP
NOP
READ
NOP
COMMAND
X = 0 cycles
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
D
OUT
D
n + 1
OUT
D
n + 2
OUT
DOUT
D
OUT
n
n + 3
b
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
COMMAND
X = 1 cycle
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
D
OUT
D
n + 1
OUT
DOUT
D
n + 3
OUT
D
OUT
n
n + 2
b
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
COMMAND
X = 2 cycles
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
D
OUT
DOUT
D
n + 2
OUT
D
n + 3
OUT
DOUT
b
n
n + 1
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DON’T CARE
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64Mb: x32
SDRAM
Figure 8
Random READ Accesses
T0
T1
T2
T3
T4
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
DOUT
D
OUT
D
OUT
n
a
x
m
CAS Latency = 1
T0
T1
T2
T3
T4
T5
CLK
COMMAND
ADDRESS
DQ
READ
READ
READ
READ
NOP
NOP
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
DOUT
D
OUT
D
OUT
n
a
x
m
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
CLK
READ
READ
READ
READ
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
D
OUT
D
OUT
D
OUT
n
a
x
m
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
DON’T CARE
64Mb: x32 SDRAM
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64Mb: x32
SDRAM
Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixed-
length READ burst may be immediately followed by
data from a WRITE command (subject to bus turn-
around limitations). The WRITE burst may be initiated
on the clock edge immediately following the last (or last
desired) data element from the READ burst, provided
that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driv-
ing the input data will go Low-Z before the SDRAM DQs
go High-Z. In this case, at least a single-cycle delay
should occur between the last read data and the WRITE
command.
The DQM input is used to avoid I/O contention, as
shown in Figures 9 and 10. The DQM signal must be
asserted (HIGH) at least two clocks prior to the WRITE
command (DQM latency is two clocks for output buff-
ers) to suppress data-out from the READ. Once the
WRITE command is registered, the DQs will go High-Z
(or remain High-Z), regardless of the state of the DQM
signal; provided the DQM was active on the clock just
prior to the WRITE command that truncated the READ
command. If not, the second WRITE will be an invalid
WRITE. For example, if DQM was low during T4 in Fig-
ure 10, then the WRITEs at T5 and T7 would be valid,
while the WRITE at T6 would be invalid.
The DQM signal must be de-asserted prior to the
WRITE command (DQM latency is zero clocks for input
buffers) to ensure that the written data is not masked.
Figure 9 shows the case where the clock frequency al-
lows for bus contention to be avoided without adding a
NOP cycle, and Figure 10 shows the case where the
additional NOP is needed.
Figure 9
READ to WRITE
T0
T1
T2
T3
T4
CLK
DQM
READ
NOP
NOP
NOP
WRITE
COMMAND
ADDRESS
Figure 10
READ to WRITE with
Extra Clock Cycle
BANK,
COL n
BANK,
COL b
t
CK
t
HZ
T0
T1
T2
T3
T4
T5
DOUT n
DIN b
CLK
DQ
t
DS
DON’T CARE
DQM
READ
NOP
NOP
NOP
NOP
WRITE
COMMAND
ADDRESS
NOTE:
A CAS latency of three is used for illustration. The READ
command may be to any bank, and the WRITE command
BANK,
BANK,
COL n
COL b
t
HZ
DOUT
n
DIN
b
DQ
t
DS
DON’T CARE
NOTE:
A CAS latency of three is used for illustration. The READ command
may be to any bank, and the WRITE command may be to any bank.
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64Mb: x32
SDRAM
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not acti-
vated), and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles be-
fore the clock edge at which the last desired data ele-
ment is valid, where x equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS
latency; data element n + 3 is either the last of a burst of
four or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until RP is met. Note
that part of the row precharge time is hidden during
the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
t
Figure 11
READ to PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
COMMAND
ADDRESS
DQ
X = 0 cycles
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
DOUT
D
n + 1
OUT
DOUT
D
OUT
n
n + 2
n + 3
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
COMMAND
ADDRESS
DQ
X = 1 cycle
BANK
(a or all)
BANK a,
BANK a,
ROW
COL
n
D
OUT
D
n + 1
OUT
DOUT
DOUT
n + 3
n
n + 2
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t
RP
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
COMMAND
ADDRESS
DQ
X = 2 cycles
BANK
(a or all)
BANK a,
BANK a,
ROW
COL
n
D
OUT
D
OUT
DOUT
D
n + 3
OUT
n
n + 1
n + 2
CAS Latency = 3
NOTE: DQM is LOW.
DON’T CARE
64Mb: x32 SDRAM
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64Mb: x32
SDRAM
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropri-
ate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to trun-
cate fixed-length or full-page bursts.
bursts may be truncated with a BURST TERMINATE
command, provided that auto precharge was not acti-
vated. The BURST TERMINATE command should be
issued x cycles before the clock edge at which the last
desired data element is valid, where x equals the CAS
latency minus one. This is shown in Figure 12 for each
possible CAS latency; data element n + 3 is the last
desired data element of a longer burst.
Full-page READ bursts can be truncated with the
BURST TERMINATE command, and fixed-length READ
Figure 12
Terminating a READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
X = 0 cycles
BANK,
COL n
D
OUT
D
n + 1
OUT
D
n + 2
OUT
DOUT
n
n + 3
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
CLK
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
X = 1 cycle
BANK,
COL n
D
OUT
D
n + 1
OUT
DOUT
D
n + 3
OUT
n
n + 2
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
ADDRESS
DQ
BURST
TERMINATE
READ
NOP
NOP
NOP
NOP
NOP
NOP
X = 2 cycles
BANK,
COL n
D
OUT
D
OUT
D
n + 2
OUT
D
n + 3
OUT
n
n + 1
CAS Latency = 3
NOTE: DQM is LOW.
DON’T CARE
64Mb: x32 SDRAM
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64Mb: x32
SDRAM
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 13.
can be issued on any clock following the previous WRITE
command, and the data provided coincident with the
new command applies to the new command. An ex-
ample is shown in Figure 15. Data n + 1 is either the last
of a burst of two or the last desired of a longer burst.
This 64Mb SDRAM uses a pipelined architecture and
therefore does not require the 2n rule associated with a
prefetch architecture. A WRITE command can be initi-
ated on any clock cycle following a previous WRITE
command. Full-speed random write accesses within a
page can be performed to the same bank, as shown in
Figure 16, or each subsequent WRITE may be per-
formed to a different bank.
The starting column and bank addresses are pro-
vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following
illustrations,auto precharge is disabled.
During WRITE bursts, the first valid data-in ele-
ment will be registered coincident with the WRITE com-
mand. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z and
any additional input data will be ignored (see Figure
14). A full-page burst will continue until terminated.
(At the end of the page, it will wrap to column 0 and
continue.)
Figure 14
WRITE Burst
T0
T1
T2
T3
CLK
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixed-
length WRITE burst may be immediately followed by
data for a WRITE command. The new WRITE command
WRITE
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COL n
Figure 13
WRITE Command
D
IN
DIN
n + 1
n
CLK
CKE HIGH
Figure 15
WRITE to WRITE
CS#
T0
T1
T2
RAS#
CLK
CAS#
WE#
WRITE
NOP
WRITE
COMMAND
ADDRESS
DQ
BANK,
COL n
BANK,
COL b
COLUMN
ADDRESS
A0–A7
A8, A9
DIN
DIN
DIN
b
n
n + 1
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
A10
DON’T CARE
NOTE: DQM is LOW. Each WRITE command may
be to any bank.
BANK
ADDRESS
BA0, 1
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64Mb: x32
SDRAM
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-
length WRITE burst may be immediately followed by a
READ command. Once the READ command is regis-
tered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 17.
Data n + 1 is either the last of a burst of two or the last
desired of a longer burst.
Data for a fixed-length WRITE burst may be fol-
lowed by, or truncated with, a PRECHARGE command
to the same bank (provided that auto precharge was
not activated), and a full-page WRITE burst may be
truncated with a PRECHARGE command to the same
bank. The PRECHARGE command should be issued
tWR after the clock edge at which the last desired input
data element is registered. The “two-clock” write-back
requires at least one clock plus time, regardless of fre-
quency, in auto precharge mode. In addition, when
truncating a WRITE burst, the DQM signal must be
used to mask input data for the clock edge prior to, and
the clock edge coincident with, the PRECHARGE com-
mand. An example is shown in Figure 18. Data n + 1 is
either the last of a burst of two or the last desired of a
longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be
t
issued until RP is met. The precharge will actually be-
gin coincident with the clock-edge (T2 in Figure 18) on
t
a “one-clock” WR and sometime between the first and
second clock on a “two-clock” tWR (between T2 and T3
in Figure 18.)
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropri-
ate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to trun-
cate fixed-length or full-page bursts.
Figure 16
Random WRITE Cycles
T0
T1
T2
T3
CLK
WRITE
WRITE
WRITE
WRITE
COMMAND
ADDRESS
DQ
Figure 18
WRITE to PRECHARGE
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
T0
T1
T2
T3
T4
T5
T6
D
IN
D
IN
D
IN
DIN
x
CLK
m
n
a
t
t
t
WR = 1 CLK ( CK > WR)
DON’T CARE
DQM
NOTE: Each WRITE command may be to any bank. DQM is LOW.
t
RP
NOP
NOP
NOP
WRITE
NOP
PRECHARGE
ACTIVE
COMMAND
ADDRESS
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
Figure 17
t
WR
WRITE to READ
D
n
IN
DIN
n + 1
DQ
T0
T1
T2
T3
T4
T5
t
t
t
CLK
WR = 2 CLK (when WR > CK)
DQM
WRITE
NOP
READ
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
t
RP
NOP
NOP
WRITE
NOP
NOP
PRECHARGE
ACTIVE
COMMAND
ADDRESS
BANK,
COL n
BANK,
COL b
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t
WR
DIN
n
DIN
n + 1
DOUT
b
DOUT
b + 1
D
IN
DIN
n + 1
DQ
n
DON’T CARE
NOTE:
DQM could remain LOW in this example if the WRITE burst is a fixed
length of two.
DON’T CARE
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64Mb: x32
SDRAM
Fixed-length or full-page WRITE bursts can be trun-
cated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coin-
cident with the BURST TERMINATE command will be
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one
clock previous to the BURST TERMINATE command.
This is shown in Figure 19, where data n is the last
desired data element of a longer burst.
PRECHARGE
The PRECHARGE command (Figure 20) is used to
deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (tRP) af-
ter the PRECHARGE command is issued. Input A10
determines whether one or all banks are to be
precharged, and in the case where only one bank is to
be precharged, inputs BA0 and BA1 select the bank.
When all banks are to be precharged, inputs BA0 and
BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank.
Figure 19
Terminating a WRITE Burst
T0
T1
T2
POWER-DOWN
CLK
Power-down occurs if CKE is registered LOW coinci-
dent with a NOP or COMMAND INHIBIT when no ac-
cesses are in progress (see Figure 21). If power-down
occurs when all banks are idle, this mode is referred to
as precharge power-down; if power-down occurs when
there is a row active in either bank, this mode is referred
to as active power-down. Entering power-down deacti-
vates the input and output buffers, excluding CKE, for
maximum power savings while in standby. The device
may not remain in the power-down state longer than
the refresh period (64ms) since no refresh operations
are performed in this mode.
BURST
TERMINATE
NEXT
COMMAND
WRITE
COMMAND
ADDRESS
DQ
BANK,
COL n
(ADDRESS)
(DATA)
DIN
n
NOTE: DQMs are LOW.
The power-down state is exited by registering a NOP
or COMMAND INHIBIT and CKE HIGH at the desired
t
clock edge (meeting CKS).
Figure 20
PRECHARGECommand
Figure 21
CLK
Power-Down
CKE
CS#
HIGH
( (
) )
( (
CLK
) )
> t
CKS
t
CKS
CKE
( (
) )
( (
) )
( (
) )
RAS#
COMMAND
NOP
NOP
ACTIVE
t
All banks idle
RCD
CAS#
WE#
Input buffers gated off
t
RAS
t
RC
Enter power-down mode.
Exit power-down mode.
DON’T CARE
A0–A9
A10
All Banks
Bank Selected
BANK
ADDRESS
BA0, 1
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64Mb: x32
SDRAM
CLOCK SUSPEND
The clock suspend mode occurs when a column ac-
cess/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deacti-
vated, “freezing” the synchronous logic.
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will re-
sume on the subsequent positive clock edge.
For each positive clock edge on which CKE is
sampled LOW, the next internal positive clock edge is
suspended. Any command or data present on the in-
put pins at the time of a suspended internal clock edge
is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as
long as the clock is suspended. (See examples in Fig-
ures 22 and 23.)
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by pro-
gramming the write burst mode bit (M9) in the Mode
Register to a logic 1. In this mode, all WRITE commands
result in the access of a single column location (burst of
one), regardless of the programmed burst length. READ
commands access columns according to the pro-
grammed burst length and sequence, just as in the
normal mode of operation (M9 = 0).
Figure 22
Figure 23
CLOCK SUSPEND During WRITE Burst
CLOCK SUSPEND During READ Burst
T0
T1
T2
T3
T4
T5
T6
T0
T1
T2
T3
T4
T5
CLK
CKE
CLK
CKE
INTERNAL
CLOCK
INTERNAL
CLOCK
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
NOP
WRITE
NOP
NOP
COMMAND
ADDRESS
BANK,
COL n
BANK,
COL n
D
OUT
D
OUT
D
n + 2
OUT
DOUT
n + 3
n
n + 1
D
n
IN
D
n + 1
IN
DIN
n + 2
D
IN
DON’T CARE
NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and
DQM is LOW.
DON’T CARE
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64Mb: x32
SDRAM
CONCURRENT AUTO PRECHARGE
An access command to (READ or WRITE) another
bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the SDRAM supports CONCURRENT AUTO
PRECHARGE. Micron SDRAMs support CONCURRENT
AUTO PRECHARGE. Four cases where CONCURRENT
AUTO PRECHARGE occurs are defined below.
on bank n, CAS latency later. The PRECHARGE to
bank n will begin when the READ to bank m is regis-
tered (Figure 24).
2. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used
two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank n will
begin when the WRITE to bank m is registered (Fig-
ure 25).
READ with auto precharge
1. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a READ
Figure 24
READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
t
Idle
BANK n
t
RP - BANK n
RP - BANK m
Internal
States
Precharge
Page Active
READ with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
D
a
OUT
D
a + 1
OUT
D
OUT
DOUT
d + 1
d
CAS Latency = 3 (BANK n)
CAS Latency = 3 (BANK m)
NOTE: DQM is LOW.
Figure 25
READ With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page
Active
READ with Burst of 4
Page Active
Interrupt Burst, Precharge
t
Idle
WR - BANK m
BANK n
t
RP - BANK
n
Internal
States
Write-Back
WRITE with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
1
DQM
D
OUT
DIN
d
D
d + 1
IN
D
d + 2
IN
DIN
d + 3
DQ
a
CAS Latency = 3 (BANK n)
NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.
DON’T CARE
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64Mb: x32
SDRAM
WRITE WITH AUTO PRECHARGE
3. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a WRITE
on bank n when registered, with the data-out ap-
pearing CAS latency later. The PRECHARGE to bank
n will begin after tWR is met, where tWR begins when
the READ to bank m is registered. The last valid
WRITE to bank n will be data-in registered one clock
prior to the READ to bank m (Figure 26).
4. Interrupted by a WRITE (with or without auto
precharge): A WRITE to bank m will interrupt a
WRITE on bank n when registered. The PRECHARGE
t
t
to bank n will begin after WR is met, where WR
begins when the WRITE to bank m is registered. The
last valid data WRITE to bank n will be data regis-
tered one clock prior to a WRITE to bank m (Figure
27).
Figure 26
WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
BANK n
t
RP - BANK n
t
WR - BANK n
Internal
States
t
RP - BANK m
Page Active
READ with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
DIN
D
a + 1
IN
D
OUT
DOUT
d + 1
a
d
CAS Latency = 3 (BANK m)
NOTE: 1. DQM is LOW.
Figure 27
WRITE With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
BANK n
t
RP - BANK n
t
WR - BANK n
Internal
States
t
WR - BANK m
Write-Back
Page Active
WRITE with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
DIN
D
a + 1
IN
D
a + 2
IN
DIN
D
d + 1
IN
D
d + 2
IN
DIN
d + 3
a
d
NOTE: 1. DQM is LOW.
DON’T CARE
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64Mb: x32
SDRAM
TRUTH TABLE 2 – CKE
(Notes: 1-4)
CKEn-1 CKEn
CURRENT STATE
COMMANDn
ACTIONn
NOTES
L
L
L
H
L
Power-Down
Self Refresh
X
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
Exit Power-Down
X
Clock Suspend
Power-Down
Self Refresh
X
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
X
5
6
7
Exit Self Refresh
Clock Suspend
All Banks Idle
All Banks Idle
Reading or Writing
Exit Clock Suspend
Power-Down Entry
Self Refresh Entry
H
COMMAND INHIBIT or NOP
AUTO REFRESH
VALID
Clock Suspend Entry
H
H
See Truth Table 3
NOTE: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock
edge n + 1 (provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met.
COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR
period. A minimum of two NOP commands must be provided during tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next
command at clock edge n + 1.
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SDRAM
TRUTH TABLE 3 – CURRENT STATE BANK n, COMMAND TO BANK n
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE#
COMMAND (ACTION)
NOTES
Any
Idle
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
L
AUTO REFRESH
7
7
L
L
LOAD MODE REGISTER
L
H
L
L
PRECHARGE
11
10
10
8
H
H
L
H
L
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
Row Active
L
H
L
L
Read
(Auto
H
H
L
H
L
10
10
8
L
Precharge
Disabled)
Write
H
H
L
L
H
H
H
L
L
9
H
L
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
10
10
8
(Auto
L
Precharge
Disabled)
H
H
L
H
L
9
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the
commands shown are those allowed to be issued to that bank when in that state. Exceptions are
covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND
INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock
edge occurring during these states. Allowable commands to the other bank are determined by its
current state and Truth Table 3, and according to Truth Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once
tRCD is met, the bank will be in the row active state.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and
t
t
ends when RP has been met. Once RP is met, the bank will be in the idle state.
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SDRAM
NOTE (continued):
Write w/Auto
Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and
ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP
commands must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met.
Once tRC is met, the SDRAM will be in the all banks idle state.
Accessing Mode
Register:
Starts with registration of a LOAD MODE REGISTER command and ends when
tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle
state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met.
Once tRP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for
precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto
precharge enabled and READs or WRITEs with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
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64Mb: x32
SDRAM
TRUTH TABLE 4 – CURRENT STATE BANK n, COMMAND TO BANK m
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE#
COMMAND (ACTION)
NOTES
Any
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
X
H
X
H
L
X
H
X
H
H
L
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (Select and activate row)
Idle
Row
Activating,
Active, or
Precharging
Read
H
H
L
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
7
7
L
H
H
L
L
L
H
H
L
ACTIVE (Select and activate row)
(Auto
H
H
L
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
7, 10
7, 11
9
Precharge
Disabled)
Write
L
H
H
L
L
L
H
H
L
ACTIVE (Select and activate row)
(Auto
H
H
L
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
7, 12
7, 13
9
Precharge
Disabled)
Read
L
H
H
L
L
L
H
H
L
ACTIVE (Select and activate row)
(With Auto
Precharge)
H
H
L
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
7, 8, 14
7, 8, 15
9
L
H
H
L
L
Write
L
H
H
L
ACTIVE (Select and activate row)
(With Auto
Precharge)
H
H
L
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
7, 8, 16
7, 8, 17
9
L
H
L
NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been
met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n
and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a
state that the given command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Read w/Auto
Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and
ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
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28
64Mb: x32
SDRAM
NOTE (continued):
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued when all
banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented
by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has
been interrupted by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the
READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 7).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the
WRITE to bank m will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should
be used one clock prior to the WRITE command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the
READ to bank m will interrupt the WRITE on bank n when registered (Figure 17), with the data-out
appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior
to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the
WRITE to bank m will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE
to bank n will be data-in registered one clock prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to
bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin
when the READ to bank m is registered (Figure 24).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the
WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two
clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will
begin when the WRITE to bank m is registered (Figure 25).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ
to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS
latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the
READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior
to the READ to bank m (Figure 26).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE
to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin
after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to
bank n will be data registered one clock prior to the WRITE to bank m (Figure 27).
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
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29
64Mb: x32
SDRAM
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
ABSOLUTEMAXIMUMRATINGS*
Voltage on VDD, VDDQ Supply
Relative to VSS .............................................. -1V to +4.6V
Voltage on Inputs, NC or I/O Pins
Relative to VSS .............................................. -1V to +4.6V
Operating Temperature, TA ............................ 0°C to +70°C
Extended Temperature .......................... -40°C to +85°C
Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ........................................................ 1W
DCELECTRICALCHARACTERISTICSANDOPERATINGCONDITIONS
(Notes: 1, 6, 27; notes appear on page 35) (VDD, VDDQ = +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
VDD, VDDQ
VIH
MIN
3
MAX UNITS NOTES
SUPPLY VOLTAGE
3.6
VDD + 0.3
0.8
V
V
V
27
22
22
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
2
VIL
-0.3
INPUT LEAKAGE CURRENT:
Any input 0V ≤ VIN ≤ VDD
(All other pins not under test = 0V)
II
-5
5
µA
OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V ≤ VOUT ≤ VDDQ
IOZ
-5
5
–
µA
V
OUTPUT LEVELS:
VOH
2.4
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = 4mA)
VOL
–
0.4
V
64Mb: x32 SDRAM
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64Mb: x32
SDRAM
IDD SPECIFICATIONSANDCONDITIONS
(Notes: 1, 6, 11, 13, 27; notes appear on page 35) (VDD, VDDQ = +3.3V 0.3V)
MAX
PARAMETER/CONDITION
SYMBOL
-6
-7
UNITS NOTES
OPERATING CURRENT: Active Mode;
IDD1
150
130
mA
3, 18,
19, 26
t
Burst = 2; READ or WRITE; tRC = RC (MIN);
CAS latency = 3
STANDBY CURRENT: Power-Down Mode;
CKE = LOW; All banks idle
IDD2
IDD3
2
2
mA
mA
STANDBY CURRENT: Active Mode; CS# = HIGH;
60
50
3, 12,
19, 26
t
CKE = HIGH; All banks active after RCD met;
No accesses in progress
OPERATING CURRENT: Burst Mode; Continuous burst;
READ or WRITE; All banks active,
CAS latency = 3
IDD4
IDD5
IDD6
180
225
2
160
225
2
mA
mA
mA
3, 18,
19, 26
t
AUTO REFRESH CURRENT:
tRFC = RFC (MIN)
3, 12,
18, 19,
26, 29
CAS latency = 3; CKE, CS# = HIGH
SELF REFRESH CURRENT: CKE ≤ 0.2V
4
IDD SPECIFICATIONSANDCONDITIONS
(Notes: 1, 6, 11, 13, 27; notes appear on page 35) (VDD, VDDQ = +3.3V 0.3V)
MAX
PARAMETER/CONDITION
SYMBOL
-5
-55
UNITS NOTES
OPERATING CURRENT: Active Mode;
IDD1
200
190
mA
3, 18,
19, 26
t
Burst = 2; READ or WRITE; tRC = RC (MIN);
CAS latency = 3
STANDBYCURRENT:Power-DownMode;
CKE = LOW; All banks idle
IDD2
IDD3
2
2
mA
mA
STANDBY CURRENT: Active Mode; CS# = HIGH;
80
70
3, 12,
t
CKE = HIGH; All banks active after RCD met;
19, 26
No accesses in progress
OPERATING CURRENT: Burst Mode; Continuous burst;
READ or WRITE; All banks active,
CAS latency = 3
IDD4
IDD5
IDD6
280
225
2
260
225
2
mA
mA
mA
3, 18,
19, 26
AUTOREFRESHCURRENT:
tRFC = tRFC (MIN)
3, 12,
18, 19,
26, 29
CAS latency = 3; CKE, CS# = HIGH
SELF REFRESH CURRENT: CKE ≤ 0.2V
4
64Mb: x32 SDRAM
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64Mb: x32
SDRAM
CAPACITANCE
(Note: 2; notes appear on page 35)
PARAMETER
SYMBOL MIN
MAX UNITS
Input Capacitance: CLK
CI1
CI2
CIO
2.5
2.5
4.0
4.0
4.0
6.5
pF
pF
pF
Input Capacitance: All other input-only pins
Input/Output Capacitance: DQs
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 5, 6, 8, 9, 11; notes appear on page 35)
AC CHARACTERISTICS
PARAMETER
Access time from CLK
(pos.edge)
-5
-55
SYMBOL
MIN MAX MIN MAX UNITS NOTES
t
CL = 3
CL = 2
CL = 1
AC(3)
AC(2)
AC(1)
4.5
-
-
5
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
t
t
t
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
AH
AS
CH
CL
1
1.5
2
2
5
1
1.5
2
2
5.5
-
t
t
t
t
CL = 3
CL = 2
CL = 1
CK (3)
CK (2)
23
23
23
t
-
t
CK (1)
-
1
1.5
1
1.5
1
1.5
4.5
-
-
1
-
1
1.5
1
1.5
1
1.5
5
-
-
1
t
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
CKH
CKS
t
t
CMH
CMS
t
t
DH
DS
t
Data-in setup time
Data-outhigh-impedancetime
t
CL = 3
CL = 2
CL = 1
HZ (3)
HZ (2)
HZ (1)
10
10
10
t
t
t
Data-outlow-impedancetime
Data-outholdtime
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
AUTO REFRESH period
ACTIVE to READ or WRITE delay
Refresh period (4,096 rows)
PRECHARGE command period
ACTIVE bankatoACTIVEbankbcommand
Transition time
LZ
t
OH
1.5
2
t
RAS
RC
RFC
38.7 120k 38.7 120k
t
55
60
15
55
60
t
t
RCD
16.5
t
REF
64
64
t
RP
15
10
0.3
2
16.5
11
t
RRD
25
7
24
20
t
T
1.2
0.3
2
55
1.2
t
t
WRITE recovery time
Exit SELF REFRESH to ACTIVE command
WR
CK
ns
t
XSR
55
64Mb: x32 SDRAM
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32
64Mb: x32
SDRAM
ELECTRICALCHARACTERISTICSANDRECOMMENDEDACOPERATINGCONDITIONS
(Notes: 5, 6, 8, 9, 11; notes appear on page 35)
ACCHARACTERISTICS
PARAMETER
Access time from CLK
(pos.edge)
-6
-7
SYMBOL
MIN MAX MIN MAX UNITS NOTES
t
CL = 3
CL = 2
CL = 1
AC(3)
AC(2)
AC(1)
AH
AS
CH
CL
CK (3)
CK (2)
CK (1)
CKH
CKS
CMH
CMS
DH
DS
5.5
7.5
17
5.5
8
17
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
t
t
t
Address hold time
Address setup time
CLKhigh-levelwidth
CLK low-level width
Clock cycle time
1
1.5
2.5
2.5
6
10
20
1
1.5
1
1.5
1
1
2
2.75
2.75
7
10
20
1
2
1
2
1
t
t
t
t
CL = 3
CL = 2
CL = 1
23
23
23
t
t
t
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
t
t
t
t
t
Data-in setup time
Data-outhigh-impedancetime
1.5
2
t
CL = 3
CL = 2
CL = 1
HZ (3)
HZ (2)
HZ (1)
5.5
7.5
17
5.5
8
17
10
10
10
t
t
t
Data-outlow-impedancetime
Data-outholdtime
ACTIVEtoPRECHARGEcommand
ACTIVEtoACTIVEcommandperiod
AUTOREFRESHperiod
ACTIVE to READ or WRITE delay
Refresh period (4,096 rows)
PRECHARGEcommandperiod
ACTIVE bankatoACTIVE bankbcommand
Transition time
LZ
OH
RAS
RC
RFC
RCD
REF
RP
1
2
42
60
60
18
1
t
2.5
42
70
70
20
t
120k
120k
t
t
t
t
64
64
t
18
12
0.3
20
14
0.3
t
RRD
T
25
7
24
t
1.2
1.2
t
t
WRITE recovery time
WR
1CLK+
6ns
1CLK+
7ns
CK
12ns
70
14ns
70
ns
ns
28
20
t
Exit SELF REFRESH to ACTIVE command
XSR
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
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64Mb: x32
SDRAM
AC FUNCTIONAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 11; notes appear on page 35)
PARAMETER
SYMBOL
CCD
-5
1
1
1
0
0
2
0
5
-
-55
1
1
1
0
0
2
0
5
-
-6
1
1
1
0
0
2
0
5
4
3
2
1
1
2
2
3
2
–
-7
1
1
1
0
0
2
0
5
4
3
2
1
1
2
2
3
2
1
UNITS NOTES
t
t
READ/WRITEcommandtoREAD/WRITEcommand
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQMtodatahigh-impedanceduringREADs
WRITE command to input data delay
Data-intoACTIVEcommand
CK
CK
17
14
14
17
17
17
17
t
t
CKED
t
t
PED
CK
t
t
DQD
CK
t
t
DQM
CK
t
t
DQZ
CK
t
t
DWD
CK
t
t
CL = 3
CL = 2
CL = 1
DAL(3)
DAL(2)
DAL(1)
CK 15, 21
t
t
CK 15, 21
t
t
-
-
CK 15, 21
t
t
Data-intoPRECHARGEcommand
Last data-in to burst STOP command
Lastdata-intonewREAD/WRITEcommand
Lastdata-intoPRECHARGEcommand
LOADMODEREGISTERcommandtoACTIVEorREFRESHcommand
Data-outtohigh-impedancefromPRECHARGEcommand
DPL
2
1
1
2
2
3
-
2
1
1
2
2
3
-
CK 16, 21
t
t
BDL
CK
17
17
t
t
CDL
CK
t
t
RDL
CK 16, 21
t
t
MRD
CK
26
17
17
17
t
t
CL = 3
CL = 2
CL = 1
ROH(3)
ROH(2)
ROH(1)
CK
t
t
CK
t
t
-
-
CK
64Mb: x32 SDRAM
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64Mb: x32
SDRAM
NOTES
1. All voltages referenced to VSS.
13. IDD specifications are tested after the device is prop-
erly initialized.
14. Timing actually specified by CKS; clock(s) speci-
2. This parameter is sampled. VDD, VDDQ = +3.3V;
f = 1 MHz, TA = 25°C; pin under test biased at 1.4V.
AC can range from 0pF to 6pF.
3. IDD is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
t
fied as a reference only at minimum cycle rate.
t
t
15. Timing actually specified by WR plus RP; clock(s)
specified as a reference only at minimum cycle rate.
t
16. Timing actually specified by WR.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indi-
cate cycle time at which proper operation over the
17. Required clocks are specified by JEDEC function-
ality and are not dependent on any timing param-
eter.
18. The IDD current will decrease as the CAS latency is
reduced. This is due to the fact that the maximum
cycle rate is slower as the CAS latency is reduced.
19. Address transitions average one transition every
two clocks.
full temperature range (0°C ≤ TA
≤
+70°C and
-40°C ≤ TA ≤ +85°C for IT parts) is ensured.
6. An initial pause of 100µs is required after power-
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (VDD
and VDDQ must be powered up simultaneously. VSS
and VSSQ must be at same potential.) The two
AUTO REFRESH command wake-ups should be
20. CLK must be toggled a minimum of two times dur-
ing this period.
t
21. Based on CK = 143 MHz for -7, 166 MHz for -6,
t
repeated any time the REF refresh requirement is
183 MHz for -55, and 200 MHz for -5.
exceeded.
7. AC characteristics assume T = 1ns.
8. In addition to meeting the transition rate specifi-
cation, the clock and CKE must transit between VIH
and VIL (or between VIL and VIH) in a monotonic
manner.
22. VIH overshoot: VIH(MAX) = VDDQ + 1.2V for a pulse
width ≤ 3ns, and the pulse width cannot be greater
than one third of the cycle rate. VIL undershoot:
VIL(MIN) = -1.2V for a pulse width ≤ 3ns, and the
pulse width cannot be greater than one third of the
cycle rate.
t
23. The clock frequency must remain constant during
access or precharge states (READ, WRITE, includ-
Q
30pF
t
ing WR, and PRECHARGE commands). CKE may
be used to reduce the data rate.
24. Auto precharge mode only.
9. Outputs measured at 1.5V with equivalent load:
10. HZ defines the time at which the output achieves
25. JEDEC and PC100 specify three clocks.
26. CK = 7ns for -7, 6ns for -6, 5.5ns for -5.5, and
t
t
the open circuit condition; it is not a reference to
VOH or VOL. The last valid data element will meet
tOH before going High-Z.
5ns for -5.
27. VDD(MIN) = 3.135V for -6, -55, and -5 speed grades.
28. Check factory for availability of specially screened
t
11. AC timing and IDD tests have VIL = .25 and VIH = 2.75,
with timing referenced to 1.5V crossover point.
12. Other input signals are allowed to transition no
more than once in any two-clock period and are
otherwise at valid VIH or VIL levels.
devices having WR = 10ns. tWR = 1 tCK for 100 MHz
and slower (tCK = 10ns and higher) in manual
precharge.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
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35
64Mb: x32
SDRAM
INITIALIZEANDLOADMODEREGISTER
T0
T1
Tn + 1
To + 1
CL
Tp + 1
Tp + 2
Tp + 3
( (
) )
( (
) )
( (
) )
t
t
CK
CLK
CKE
((
))
t
( (
) )
( (
) )
( (
) )
CH
t
t
CKH
CKS
((
))
((
))
( (
) )
( (
) )
( (
) )
( (
) )
t
t
t
t
t
t
CMS CMH
CMS CMH
CMS CMH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
AUTO
REFRESH
AUTO
REFRESH
LOAD MODE
REGISTER
COMMAND
DQM 0-3
NOP
PRECHARGE
NOP
NOP
NOP
NOP
NOP
ACTIVE
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
CODE
ROW
ROW
BANK
A0-A9
A10
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
CODE
SINGLE BANK
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
ALL
BANKS
CODE
BA0, BA1
DQ
High-Z
((
))
((
))
T = 100µs
(MIN)
t
t
t
t
MRD
RP
RFC
RFC
Power-up:
Program Mode Register 1, 2, 5
AUTO REFRESH
VDD and
AUTO REFRESH
Precharge
all banks
CK stable
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
MAX
MIN
1
MAX UNITS
t
t
AH
AS
1
1.5
2
1
2
ns
ns
ns
ns
ns
ns
ns
CKH
CKS
1
1.5
1
1
1.5
1
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
1.5
2.5
2.5
6
2
CH
2.75
2.75
7
CMH
CMS
MRD
RFC
1
CL
2
1.5
2
1.5
2
2
t
t
CLK (3)
CLK (2)
CLK (1)
5
2
CK
t
t
10
10
60
15
60
18
70
20
ns
ns
20
20
RP
*CAS latency indicated in parentheses.
NOTE: 1. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.
2. Outputs are guaranteed High-Z after command is issued.
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SDRAM
POWER-DOWN MODE 1
T0
T1
T2
Tn + 1
Tn + 2
( (
) )
t
CK
t
CL
CLK
CKE
( (
t
CH
) )
t
t
CKS
CKS
( (
) )
t
t
CKS
CKH
t
t
CMS CMH
PRECHARGE
( (
) )
COMMAND
DQM 0-3
NOP
NOP
NOP
ACTIVE
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
A0-A9
A10
ROW
ROW
ALL BANKS
( (
) )
( (
) )
SINGLE BANK
t
AS
t
AH
( (
) )
( (
) )
BANK
BA0, BA1
DQ
BANK(S)
High-Z
( (
) )
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
20
MAX
MIN
20
1
MAX UNITS
t
t
AH
AS
1
1.5
2
ns
ns
ns
ns
ns
ns
CK (1)
ns
ns
ns
ns
ns
t
t
t
t
1.5
2.5
2.5
6
2
CKH
CKS
1
1.5
1
1
t
t
t
CH
2.75
2.75
7
1.5
1
2
CL
2
CMH
CMS
1
t
CK (3)
CK (2)
5
1.5
1.5
2
t
10
10
*CAS latency indicated in parentheses.
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
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SDRAM
CLOCK SUSPEND MODE 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
CK
t
CL
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
DQM0-3
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
t
t
CMS
CMH
t
AS
t
AH
2
2
A0-A9
COLUMN m
COLUMN e
t
AS
t
AH
A10
t
AS
t
AH
BA0, BA1
BANK
BANK
t
AC
t
AC
t
OH
t
HZ
t
DS
t
DH
DOUT
m
DOUT m + 1
DOUT
e
DOUT e + 1
DQ
t
LZ
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
MAX
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
1.5
1
MAX
MIN
MAX UNITS
t
t
AC (3)
4.5
5.5
7.5
17
5.5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKS
1.5
1
2
1
2
1
2
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
AC (2)
CMH
CMS
DH
t
AC (1)
17
1.5
1
1.5
1
t
AH
AS
1
1.5
2
1
1.5
2.5
2.5
6
1
2
t
t
t
DS
1.5
1.5
CH
2.75
2.75
7
HZ (3)
HZ (2)
HZ (1)
4.5
–
5.5
7.5
17
5.5
8
ns
ns
ns
ns
ns
CL
2
t
CK (3)
CK (2)
CK (1)
5
–
17
t
t
t
–
10
20
1
10
20
1
LZ
1
1
2
1
t
–
OH
1.5
2.5
CKH
1
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled.
2. A8 and A9 = “Don’t Care.”
64Mb: x32 SDRAM
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64Mb: x32
SDRAM
AUTOREFRESHMODE
T0
T1
T2
Tn + 1
CL
To + 1
( (
) )
( (
) )
t
CLK
CKE
t
t
( (
( (
CK
CH
) )
) )
( (
) )
( (
) )
t
t
CKS
CKH
t
t
CMS
CMH
( (
) )
( (
) )
AUTO
REFRESH
AUTO
REFRESH
COMMAND
DQM 0–3
PRECHARGE
NOP
NOP
NOP
NOP
NOP
ACTIVE
( (
( (
) )
) )
( (
) )
( (
) )
( (
( (
) )
) )
( (
) )
( (
) )
( (
) )
( (
) )
A0–A9
A10
ROW
ROW
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
SINGLE BANK
t
t
AH
AS
( (
) )
( (
) )
BANK(S)
BA0, BA1
DQ
BANK
( (
( (
) )
) )
High-Z
( (
) )
( (
) )
t
t
t
RP
RFC
RFC
Precharge all
active banks
DON’T CARE
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
t
t
AH
AS
1
1.5
2
ns
ns
ns
ns
ns
ns
ns
CKH
CKS
1
1.5
1
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
1.5
2.5
2.5
6
2
1.5
1
2
CH
2.75
2.75
7
CMH
CMS
RFC
1
CL
2
1.5
60
15
1.5
60
2
t
CK (3)
CK (2)
CK (1)
5
70
20
t
t
10
10
RP
18
20
20
*CAS latency indicated in parentheses.
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SDRAM
SELFREFRESHMODE
T0
T1
T2
Tn + 1
To + 1
To + 2
( (
) )
( (
) )
t
CL
CLK
CKE
t
( (
) )
( (
) )
t
CK
CH
t
> t
RAS
CKS
( (
) )
( (
) )
( (
) )
t
t
CKS
t
CKS
CKH
t
t
CMS
CMH
( (
) )
( (
) )
( (
) )
( (
) )
AUTO
REFRESH
AUTO
REFRESH
COMMAND
DQM 0-3
PRECHARGE
NOP
NOP
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
A0-A9
A10
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
SINGLE BANK
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
BA0, BA1
DQ
BANK(S)
High-Z
( (
) )
( (
) )
t
t
RP
XSR
Precharge all
active banks
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
DON’T CARE
CLK stable prior to exiting
self refresh mode
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
t
t
t
t
t
t
t
AH
AS
1
1.5
2
ns
ns
ns
ns
ns
ns
ns
CKH
CKS
1
1.5
1
ns
ns
ns
ns
t
t
t
1.5
2.5
2.5
6
2
1.5
1
2
CH
2.75
2.75
7
CMH
CMS
RAS
1
CL
2
1.5
1.5
42
18
70
2
t
CK (3)
CK (2)
CK (1)
5
38.7 120,000
120,000
42
20
70
120,000
ns
ns
ns
t
t
10
10
RP
15
55
t
20
20
XSR
*CAS latency indicated in parentheses.
64Mb: x32 SDRAM
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SDRAM
1
SINGLE READ
T0
T1
T2
T3
T4
T5
t
t
CL
CK
CLK
t
CH
t
t
t
CKS
CKH
CKE
t
CMS
CMH
COMMAND
ACTIVE
NOP
READ
PRECHARGE
NOP
ACTIVE
t
t
CMS
CMH
DQM /
DQML, DQMH
t
t
AS
AH
2
A0-A9
ROW
ROW
COLUMN
m
t
t
AS
AH
ALL BANKS
SINGLE BANK
BANK
ROW
ROW
A10
DISABLE AUTO PRECHARGE
BANK
t
t
AH
AS
BA0, BA1
BANK
BANK
t
t
OH
AC
D
OUTm
DQ
t
LZ
t
HZ
t
RCD
CAS Latency
t
t
RP
RAS
t
RC
DON’T CARE
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
MAX
5.5
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
MAX
MIN
MAX UNITS
t
t
AC (3)
4.5
5.5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
1
1
1
2
ns
ns
t
t
t
t
t
t
AC (2)
-
-
7.5
1.5
1.5
t
AC (1)
17
17
HZ (3)
HZ (2)
HZ (1)
4.5
5.5
7.5
17
5.5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AH
AS
1
1.5
2
1
1.5
2.5
2.5
6
1
2
-
-
t
t
t
17
CH
2.75
2.75
7
LZ
1
1
1
t
CL
2
OH
1.5
2
2.5
42
70
20
20
t
t
CK (3)
CK (2)
CK (1)
5
RAS
RC
38.7 120,000
42
60
18
18
120,000
120,000
t
t
t
t
t
t
-
10
20
1
10
20
1
55
15
15
-
RCD
CKH
1
RP
t
CKS
1.5
1.5
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A8, A9 = “Don’t Care.”
64Mb: x32 SDRAM
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SDRAM
READ – WITHOUT AUTO PRECHARGE 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
t
CMH
CMS
DQM 0-3
A0-A9
t
t
AH
AS
2
ROW
ROW
COLUMN m
t
t
AH
AS
ALL BANKS
ROW
ROW
A10
SINGLE BANK
DISABLE AUTO PRECHARGE
BANK
t
t
AH
AS
BA0, BA1
BANK
BANK
t
BANK
t
t
AC
AC
AC
t
t
t
t
t
OH
AC
OH
OH
OH
DOUT
m
DOUT m + 1
D
OUT m + 2
DOUT m + 3
DQ
t
LZ
t
HZ
t
t
RCD
CAS Latency
RP
t
RAS
t
RC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
MAX
5.5
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
MAX
MIN
MAX UNITS
t
t
AC (3)
4.5
5.5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
1
1
1
2
ns
ns
t
t
t
t
t
t
AC (2)
-
-
7.5
1.5
1.5
t
AC (1)
17
17
HZ (3)
HZ (2)
HZ (1)
4.5
5.5
7.5
17
5.5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AH
AS
1
1.5
2
1
1.5
2.5
2.5
6
1
2
-
-
t
t
t
17
CH
2.75
2.75
7
LZ
1
1
1
t
CL
2
OH
1.5
2
2.5
42
70
20
20
t
t
CK (3)
CK (2)
CK (1)
5
RAS
RC
38.7 120,000
42
60
18
18
120,000
120,000
t
t
t
t
t
t
-
10
20
1
10
20
1
55
15
15
-
RCD
CKH
1
RP
t
CKS
1.5
1.5
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A8 and A9 = “Don’t Care.”
64Mb: x32 SDRAM
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SDRAM
READ – WITH AUTO PRECHARGE 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS CMH
COMMAND
DQM 0-3
A0-A9
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
CMS
CMH
t
t
AH
AS
2
ROW
ROW
COLUMN m
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
ROW
A10
t
t
AH
AS
BANK
BANK
BA0, BA1
BANK
t
t
t
AC
AC
AC
t
t
t
t
t
AC
OH
OH
OH
OH
DOUT
m
D
OUT
m
+ 1
D
OUT
m
+ 2
DOUT m + 3
DQ
t
LZ
t
HZ
t
t
RCD
CAS Latency
RP
t
RAS
t
RC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
MAX
5.5
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
MAX
MIN
MAX UNITS
t
t
AC (3)
4.5
5.5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
1
1
1
2
ns
ns
t
t
t
t
t
t
AC (2)
-
-
7.5
1.5
1.5
t
AC (1)
17
17
HZ (3)
HZ (2)
HZ (1)
4.5
5.5
7.5
17
5.5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AH
AS
1
1.5
2
1
1.5
2.5
2.5
6
1
2
-
-
t
t
t
17
CH
2.75
2.75
7
LZ
1
1
1
t
CL
2
OH
1.5
2
2.5
42
70
20
20
t
t
CK (3)
CK (2)
CK (1)
5
RAS
RC
38.7 120,000
42
60
18
18
120,000
120,000
t
t
t
t
t
t
-
10
20
1
10
20
1
55
15
15
-
RCD
CKH
1
RP
t
CKS
1.5
1.5
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. A8 and A9 = “Don’t Care.”
64Mb: x32 SDRAM
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SDRAM
ALTERNATING BANK READ ACCESSES 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
CK
t
CL
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
DQM 0-3
ACTIVE
NOP
READ
t
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
t
CMS
CMH
t
AS
t
AH
2
2
ROW
ROW
ROW
ROW
COLUMN m
COLUMN b
A0-A9
t
t
AH
AS
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
ROW
A10
t
AS
t
AH
BANK 0
BANK 0
BANK 4
t
BANK 4
BA0, BA1
BANK 0
t
AC
t
t
AC
t
AC
AC
AC
t
AC
t
OH
t
OH
t
OH
t
OH
t
OH
DOUT
m
D
OUT m + 1
D
OUT m + 2
D
OUT m + 3
DOUT b
DQ
t
LZ
t
t
RCD - BANK 0
t
RP - BANK 0
RCD - BANK 0
CAS Latency - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
t
RCD - BANK 4
CAS Latency - BANK 4
RRD
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
MAX
5.5
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
1.5
1
MAX
MIN
2
MAX UNITS
t
t
AC (3)
4.5
5.5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKS
1.5
1
ns
ns
ns
ns
ns
t
t
t
t
AC (2)
-
-
7.5
CMH
CMS
1
t
AC (1)
17
17
1.5
1
1.5
1
2
t
AH
AS
1
1.5
2
1
1.5
2.5
2.5
6
1
2
LZ
1
t
t
t
t
OH
1.5
2
2.5
42
70
20
20
14
t
CH
2.75
2.75
7
RAS
RC
38.7 120,000
42
60
18
18
12
120,000
120,000
ns
ns
ns
ns
ns
t
t
t
CL
2
55
15
15
10
t
CK (3)
CK (2)
CK (1)
5
RCD
t
t
t
-
10
20
1
10
20
1
RP
t
-
RRD
CKH
1.5
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.
2. A8 and A9 = “Don’t Care.”
64Mb: x32 SDRAM
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64Mb: x32
SDRAM
READ – FULL-PAGE BURST 1
T0
T1
T2
T3
T4
T5
T6
Tn + 1
Tn + 2
Tn + 3
Tn + 4
( (
) )
( (
) )
t
CL
t
CK
CLK
t
CH
t
t
CKS
CKH
( (
) )
CKE
( (
) )
t
t
CMS
CMH
( (
) )
( (
) )
COMMAND
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
BURST TERM
NOP
NOP
t
CMS
CMH
( (
) )
DQM 0-3
A0-A9
( (
) )
t
AS
t
AH
( (
) )
( (
) )
2
ROW
COLUMN m
t
AS
t
AH
( (
) )
( (
) )
ROW
A10
t
AS
t
AH
( (
) )
( (
) )
BA0, BA1
BANK
BANK
t
t
t
t
t
AC
AC
AC
AC
AC
( (
) )
t
AC
t
t
t
OH
t
t
t
OH
OH
OH
OH
OH
( (
) )
( (
) )
Dout
m
D
OUT m+1
D
OUT m+2
D
OUT m-1
D
OUT
m
DOUT m+1
DQ
t
LZ
t
HZ
t
256 locations within same row
Full page completed
RCD
CAS Latency
DON’T CARE
UNDEFINED
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
3
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
MAX
5.5
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
MAX UNITS
t
t
AC (3)
4.5
5.5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKH
1
1.5
1
1
2
1
2
ns
ns
ns
ns
t
t
t
t
t
t
t
t
AC (2)
-
-
7.5
CKS
1.5
1
t
AC (1)
17
17
CMH
CMS
t
AH
AS
1
1.5
2
1
1
2
1.5
1.5
t
t
t
1.5
2.5
2.5
6
HZ (3)
HZ (2)
HZ (1)
4.5
5
5.5
8
ns
ns
ns
ns
ns
ns
CH
2.75
2.75
7
-
-
7.5
17
CL
2
17
t
CK (3)
CK (2)
CK (1)
5
LZ
1
1
2
1
t
t
t
-
10
20
10
OH
1.5
15
2.5
20
t
-
20
RCD
18
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the CAS latency = 2.
2. A8 and A9 = “Don’t Care.”
3. Page left open; no tRP.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
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64Mb: x32
SDRAM
READ – DQM OPERATION 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS CMH
DQM 0-3
A0-A9
t
t
AH
AS
2
ROW
COLUMN m
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
A10
DISABLE AUTO PRECHARGE
BANK
t
t
AH
AS
BA0, BA1
BANK
t
AC
t
t
t
t
t
OH
AC
OH
AC
OH
DQ
D
OUT
m
DOUT m + 2
D
OUT m + 3
t
LZ
t
t
t
LZ
HZ
HZ
t
RCD
CAS Latency
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
MAX
5.5
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
MAX UNITS
t
t
AC (3)
4.6
5.5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKH
1
1.5
1
1
2
1
2
ns
ns
ns
ns
t
t
t
t
t
t
t
t
AC (2)
-
-
7.5
CKS
1.5
1
t
AC (1)
17
17
CMH
CMS
t
AH
AS
1
1.5
2
1
1
2
1.5
1.5
t
t
t
1.5
2.5
2.5
6
HZ (3)
HZ (2)
HZ (1)
4.5
5
5.5
8
ns
ns
ns
ns
ns
ns
CH
2.75
2.75
7
-
-
7.5
17
CL
2
17
t
CK (3)
CK (2)
CK (1)
5
LZ
1
1
2
1
t
t
t
-
10
20
10
OH
1.5
15
2.5
20
t
-
20
RCD
18
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the CAS latency = 2.
2. A8 and A9 = “Don’t Care.”
64Mb: x32 SDRAM
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64Mb: x32
SDRAM
SINGLEWRITE
T0
T1
T2
T3
T4
T5
T6
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
PRECHARGE
NOP
ACTIVE
t
t
CMS
CMH
DQM /
DQML, DQMH
t
t
t
t
AH
AS
3
A0-A9
ROW
t
ROW
ROW
BANK
COLUMN m
AS
AH
ALL BANKS
ROW
t
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
AS
AH
BA0, BA1
BANK
t
t
DH
DS
D
IN m
DQ
2
t
t
t
RCD
RP
WR
t
RAS
t
RC
DON’T CARE
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
t
t
AH
AS
1
1.5
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
DH
1
1.5
1
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
1.5
2.5
2.5
6
2
1.5
1
2
CH
2.75
2.75
7
1
CL
2
DS
1.5
1.5
42
60
18
18
12
2
t
CK (3)
CK (2)
CK (1)
5
RAS
RC
38.7 120,000
120,000
42
70
20
20
14
120,000
ns
ns
ns
ns
ns
t
t
t
10
20
1
10
20
1
55
15
15
RCD
CKH
1
RP
t
t
t
CKS
1.5
1.5
2
WR
2 CK
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 10ns is required between <DIN m> and the PRECHARGE command, regardless of frequency, to meet tWR.
3. A8, A9 = “Don’t Care.”
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
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SDRAM
WRITE – WITHOUT AUTO PRECHARGE 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
t
CMS
CMH
DQM 0-3
A0-A9
t
t
t
t
AH
AS
3
ROW
t
ROW
ROW
BANK
COLUMN m
AS
AH
ALL BANKs
ROW
t
A10
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
BANK
AS
AH
BANK
BA0, BA1
t
t
t
t
t
t
t
t
DH
DS
DH
DS
DH
DS
DH
DS
DIN
m
DIN m + 1
DIN m + 2
DIN m + 3
DQ
2
t
t
t
RCD
RP
WR
t
RAS
t
RC
DON’T CARE
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
t
t
AH
AS
1
1.5
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
DH
1
1.5
1
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
1.5
2.5
2.5
6
2
1.5
1
2
CH
2.75
2.75
7
1
CL
2
DS
1.5
1.5
42
60
18
18
12
2
t
CK (3)
CK (2)
CK (1)
5
RAS
RC
38.7 120,000
120,000
42
70
20
20
14
120,000
ns
ns
ns
ns
ns
t
t
t
10
20
1
10
20
1
55
15
15
RCD
CKH
1
RP
t
t
4
t
CKS
1.5
2
2
WR
2 CK
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. Faster frequencies require two clocks (when tWR > tCK).
3. A8 and A9 = “Don’t Care.”
t
4. WR of 1 CLK available if running 100 MHz or slower. Check factory for availability.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
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SDRAM
WRITE – WITH AUTO PRECHARGE 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
t
t
CMS
CMH
DQM 0-3
A0-A9
t
t
AS
AH
3
ROW
ROW
ROW
BANK
COLUMN m
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
t
A10
t
AS
AH
BANK
BANK
BA0, BA1
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
D
IN
m
D
IN m + 1
D
IN m + 2
DIN m + 3
DQ
2
t
t
RP
t
RCD
WR
t
RAS
t
RC
DON’T CARE
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
MAX
MIN
2
MAX UNITS
t
t
AH
AS
1
1.5
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMS
DH
1.5
1
1.5
1
ns
ns
ns
t
t
t
t
t
t
t
t
t
1.5
2.5
2.5
6
2
1
CH
2.75
2.75
7
DS
1.5
1.5
42
2
CL
2
RAS
RC
38.7 120,000
120,000
42
70
20
20
120,000
ns
ns
ns
ns
ns
t
CK (3)
CK (2)
CK (1)
CKH
5
55
15
15
60
t
t
t
t
t
10
20
1
10
20
1
RCD
18
RP
18
t
t
1
1.5
1
WR
2 CK
1 CLK+
6
1 CLK+
7
CKS
2
2
CMH
1
1
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. Faster frequencies require two clocks (when tWR > tCK).
3. A8 and A9 = “Don’t Care.”
64Mb: x32 SDRAM
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SDRAM
ALTERNATINGBANKWRITEACCESSES 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
t
CMS
CMH
DQM /
DQML, DQMH
t
t
AH
AS
2
2
A0-A9
ROW
ROW
ROW
ROW
ROW
COLUMN m
COLUMN b
t
t
AH
AS
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
A10
t
t
AH
AS
BA0, BA1
BANK 0
BANK 0
BANK 1
t
BANK 1
BANK 0
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DH
t
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
DS
DS
DH
DIN
m
DIN m + 1
DIN m + 2
DIN m + 3
DIN
b
DIN b + 1
DIN b + 2
DIN b + 3
DQ
t
t
t
t
RCD - BANK 0
WR - BANK 0
RP - BANK 0
RCD - BANK 0
t
RAS - BANK 0
t
RC - BANK 0
t
t
WR - BANK 1
t
RCD - BANK 1
RRD
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
MAX
MIN
1
MAX UNITS
t
t
t
t
t
t
t
AH
AS
1
1.5
2
1
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DH
DS
1
1.5
38.7
55
1
1.5
42
ns
ns
t
t
t
1.5
2.5
2.5
6
2
CH
2.75
2.75
7
RAS
RC
120,000
42
70
20
20
14
120,000
ns
ns
ns
ns
ns
ns
CL
2
60
t
CK (3)
CK (2)
CK (1)
5
RCD
15
18
t
t
t
10
20
1
10
20
1
RP
15
18
t
RRD
WR
10
12
t
t
CKH
1
1.5
1
2 CK
1 CLK+
6
1 CLK+
7
t
CKS
2
2
t
CMH
CMS
1
1
t
1.5
1.5
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. Faster frequencies require two clocks (when tWR > tCK).
3. A8 and A9 = “Don’t Care.”
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
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64Mb: x32
SDRAM
WRITE–FULL-PAGEBURST
T0
T1
T2
T3
T4
T5
Tn + 1
Tn + 2
Tn + 3
( (
) )
( (
) )
t
t
CK
CL
CLK
t
CH
t
t
CKS
CKH
( (
) )
CKE
( (
) )
t
t
CMS
CMH
( (
) )
( (
) )
COMMAND
ACTIVE
NOP
WRITE
t
NOP
NOP
NOP
NOP
BURST TERM
NOP
t
CMH
CMS
( (
) )
( (
) )
DQM 0-3
A0-A9
t
t
AH
AS
( (
) )
( (
) )
1
ROW
COLUMN m
t
t
AH
AS
( (
) )
( (
) )
ROW
A10
t
t
AH
AS
( (
) )
( (
) )
BA0, BA1
BANK
BANK
t
t
t
t
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DS
DH
DS
DH
( (
) )
DIN
m
DIN m + 1
DIN m + 2
DIN m + 3
DIN m - 1
DQ
( (
) )
t
RCD
Full-page burst does
256 locations within same row
not self-terminate. Can
use BURST TERMINATE
2, 3
command to stop.
Full page completed
DON’T CARE
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
MAX
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
t
t
t
t
t
t
t
t
AH
AS
1
1.5
2
1
ns
ns
ns
ns
ns
ns
ns
CKH
CKS
CMH
CMS
DH
1
1.5
1
ns
ns
ns
ns
ns
ns
ns
t
t
t
1.5
2.5
2.5
6
2
1.5
1
2
CH
2.75
2.75
7
1
CL
2
1.5
1
2
2
t
CK (3)
CK (2)
CK (1)
5
1
1
t
t
10
20
10
DS
1.5
15
1.5
18
2
20
RCD
20
*CAS latency indicated in parentheses.
NOTE: 1. A8 and A9 = “Don’t Care.”
t
2. WR must be satisfied prior to PRECHARGE command.
3. Page left open; no tRP.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
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51
64Mb: x32
SDRAM
WRITE – DQM OPERATION 1
T0
T1
T2
T3
T4
T5
T6
T7
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
COMMAND
DQM 0-3
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
t
t
CMS CMH
t
t
t
t
AS
AH
2
A0-A9
ROW
COLUMN m
t
AS
AH
ENABLE AUTO PRECHARGE
ROW
A10
t
DISABLE AUTO PRECHARGE
BANK
AS
AH
BA0, BA1
BANK
t
t
t
t
t
t
DS
DH
DS
DH
DS
DH
DIN m
D
IN m + 2
DIN m + 3
DQ
t
RCD
DON’T CARE
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
1
MAX UNITS
t
t
AH
AS
1
1.5
2
ns
ns
ns
ns
ns
ns
ns
CKH
CKS
CMH
CMS
DH
1
1.5
1
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
1.5
2.5
2.5
6
2
2
2
CH
2.75
2.75
7
1
1
CL
2
1.5
1
1.5
1
2
t
CK (3)
CK (2)
CK (1)
5
1
t
t
10
10
DS
1.5
15
1.5
18
2
20
20
RCD
20
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4.
2. A8 and A9 = “Don’t Care.”
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
52
64Mb: x32
SDRAM
86-PIN PLASTIC TSOP (400 MIL)
SEE DETAIL A
22.22 .08
.61
.50
TYP
.10 (2X)
+.07
-.03
0.20
2.80 (2X)
11.76 .10
10.16 .08
R .75 (2X)
PIN #1 ID
+.03
-.02
.15
R 1.00
(2X)
.25
GUAGE
PLANE
+.10
-.05
.10
.10
.50 .10
1.20 MAX
.80
TYP
DETAIL A
MAX
MIN
NOTE: 1. All dimensions in millimeters
or typical where noted.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.025mm
per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail:prodmktg@micronsemi.com,Internet:http://www.micronsemi.com,CustomerCommentLine:800-932-4992
Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
53
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