MT4LC16M4A7TG-5_技术文档

16 MEG x 4

FPM DRAM

MT4LC16M4A7, MT4LC16M4T8

DRAM

For the latest data sheet, please refer to the Micron Web

site: www.micronsemi.com/mti/msp/html/datasheet.html

FEATURES

• Sin gle +3.3V ±0.3V power supply

• In dustry-stan dard x4 pin out, tim in g, fun ction s,

an d packages

• 13 row, 11 colum n addresses (A7)

12 row, 12 colum n addresses (T8)

• High -perform an ce CMOS silicon -gate process

• All in puts, outputs an d clocks are LVTTL-com pat-

ible

• FAST-PAGE-MODE (FPM) access

• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH

distributed across 64m s

• Option al self refresh (S) for low-power data

reten tion

PIN ASSIGNMENT (To p Vie w )

32-Pin SOJ

32-Pin TSOP

V

CC

1

2

3

4

5

6

7

8

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VSS

V

CC

1

2

3

4

5

6

7

8

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VSS

DQ0

DQ1

NC

DQ3

DQ2

NC

CAS#

OE#

A12/NC**

A11

A10

A9

DQ0

DQ1

NC

DQ3

DQ2

NC

CAS#

OE#

A12/NC**

A11

A10

A9

NC

WE#

RAS#

A0

A1

A2

A3

A4

A5

NC

9

WE#

RAS#

A0

A1

A2

A3

A4

A5

10

11

12

13

14

15

16

9

10

11

12

13

14

15

16

A8

A7

A6

VSS

A8

A7

A6

VSS

OPTIONS

MARKING

VCC

• Refresh Addressin g

4,096 (4K) rows

8,192 (8K) rows

VCC

T8

A7

**A12 on A7 version and NC on T8 version

• Plastic Packages

32-pin SOJ (400 m il)

32-pin TSOP (400 m il)

DJ

TG

16 MEG x 4 FPM DRAM PART NUMBERS

• Tim in g

REFRESH

50n s access

60n s access

-5

-6

PART NUMBER

ADDRESSING PACKAGE REFRESH

MT4LC16M4A7DJ-x

MT4LC16M4A7DJ-x S

MT4LC16M4A7TG-x

MT4LC16M4A7TG-x S

MT4LC16M4T8DJ-x

MT4LC16M4T8DJ-x S

MT4LC16M4T8TG-x

MT4LC16M4T8TG-x S

8K

4K

SOJ

Standard

Self

• Refresh Rates

TSOP

SOJ

Standard

Self

Stan dard Refresh

Self Refresh (128m s period)

Non e

S*

Standard

Self

NOTE: 1. Th e 16 Meg x 4 FPM DRAM base n um ber

differen tiates th e offerin gs in on e place—

SOJ

TSOP

Standard

Self

MT4LC16M4A7. Th e fifth field distin guish es

various option s: A7 design ates an 8K refresh an d

T8 design ates a 4K refresh for FPM DRAMs.

2. Th e # sym bol in dicates sign al is active LOW.

x = speed

*Con tact factory for availability

GENERAL DESCRIPTION

Th e 16 Meg x 4 DRAMs are h igh -speed CMOS,

dyn am ic ran dom -access m em ory devices con tain -in g

67,108,864 bits organ ized in a x4 con figuration . Th e

MT4LC16M4A7 an d MT4LC16M4T8 are fun ction ally

organ ized as 16,777,216 location s con tain in g four bits

each . Th e 16,777,216 m em ory location s are arran ged in

8,192 rows by 2,048 colum n s for th e MT4LC16M4A7 or

4,096 rows by 4,096 colum n s for th e MT4LC16M4T8.

Durin g READ or WRITEcycles, each location is un iquely

Part Number Example:

MT4LC16M4A7DJ

KEY TIMING PARAMETERS

t

SPEED

RC

RAC

PC

AA

CAC

-5

-6

90ns

50ns

60ns

30ns

35ns

25ns

30ns

13ns

15ns

110ns

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

1

16 MEG x 4

FPM DRAM

FUNCTIONAL BLOCK DIAGRAM

MT4LC16M4A7 (13 row addresses)

WE#

CAS#

4

DATA-IN

BUFFER

DQ0

DQ1

DQ2

DQ3

CONTROL

LOGIC

DATA-OUT

BUFFER

NO. 2 CLOCK

GENERATOR

4

OE#

COLUMN-

ADDRESS

BUFFER(11)

COLUMN

DECODER

11

A0

A1

11

4

2,048

A2

A3

REFRESH

CONTROLLER

SENSE AMPLIFIERS

I/O GATING

A4

A5

A6

2,048

REFRESH

A7

COUNTER

A8

A9

13

8,192 x 2,048 x 4

MEMORY

A10

A11

A12

ROW-

ADDRESS

BUFFERS (13)

ARRAY

8,192

13

8,192

NO. 1 CLOCK

GENERATOR

V

DD

RAS#

VSS

FUNCTIONAL BLOCK DIAGRAM

MT4LC16M4T8 (12 row addresses)

WE#

CAS#

4

DATA-IN

BUFFER

DQ0

DQ1

DQ2

DQ3

CONTROL

LOGIC

DATA-OUT

BUFFER

NO. 2 CLOCK

GENERATOR

4

OE#

COLUMN-

ADDRESS

BUFFER(12)

COLUMN

DECODER

12

A0

A1

12

4

4,096

A2

A3

REFRESH

CONTROLLER

SENSE AMPLIFIERS

I/O GATING

A4

A5

A6

4,096

REFRESH

A7

COUNTER

A8

A9

12

4,096 x 4,096 x 4

MEMORY

A10

A11

ROW-

ADDRESS

BUFFERS (12)

ARRAY

4,096

12

4,096

NO. 1 CLOCK

GENERATOR

V

DD

RAS#

VSS

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2

16 MEG x 4

FPM DRAM

GENERAL DESCRIPTION (co n t in u e d )

addressed via th e address bits. First, th e row address is

latch ed by th e RAS# sign al, th en th e colum n address by

CAS#. Both devices provide FAST-PAGE-MODE opera-

tion , allowin g for fast successive data operation s (READ,

WRITE, or READ-MODIFY-WRITE) with in a given row.

Th e MT4LC16M4A7 an d MT4LC16M4T8 m ust be

refresh ed periodically in order to retain stored data.

wh ereas th e MT4LC16M4T8 refresh es on e row for every

CBR cycle. So with eith er device, executin g 4,096 CBR

cycles covers all rows. Th e CBR refresh will in voke th e

in tern al refresh coun ter for autom atic RAS# address-

in g. Altern atively, RAS#-ONLY REFRESH capability is

in h eren tly provided. However, with th is m eth od on ly

on e row is refresh ed at a tim e; so for th e MT4LC16M4A7,

8,192 RAS#-ONLY REFRESH cycles m ust be executed

every 64m s to cover all rows. Som e com patibility issues

m ay becom e apparen t. JEDEC stron gly recom m en ds

th e use of CBR REFRESH for th is device.

FAST PAGE MODE ACCESS

Each location in th e DRAM is un iquely addressable

as m en tion ed in th e Gen eral Description . Th e data for

each location is accessed via th e four I/O pin s (DQ0-

DQ3). Th e WE# sign al m ust be activated to execute a

WRITE operation ; oth erwise, a READ operation will be

perform ed. Th e OE# sign al m ust be activated to en able

th e DQ output drivers for a read access an d can be

deactivated to disable output data if n ecessary.

FAST-PAGE-MODE operation s are always in itiated

with a row address strobed in by th e RAS# sign al,

followed by a colum n address strobed in by CAS#, just

like for sin gle location accesses. However, subsequen t

colum n location s with in th e row m ay th en be accessed

at th e page m ode cycle tim e. Th is is accom plish ed by

cyclin g CAS# wh ile h oldin g RAS# LOW an d en terin g

n ew colum n addresses with each CAS# cycle. Return in g

RAS# HIGH term in ates th e FAST-PAGE-MODE opera-

tion .

An option al self refresh m ode is also available on th e

“S” version . Th e self refresh feature is in itiated by

perform in g a CBR REFRESH cycle an d h oldin g RAS#

t

LOW for th e specified RASS. Th e “S” option allows for

an exten ded refresh period of 128m s, or 31.25µs per

row for a 4K refresh an d 15.625µs per row for an 8K

refresh , wh en usin g a distributed CBR REFRESH. Th is

refresh rate can be applied durin g n orm al operation , as

well as durin g a stan dby or battery backup m ode.

Th e self refresh m ode is term in ated by drivin g RAS#

HIGH for a m in im um tim e of ^tRPS. Th is delay allows for

th e com pletion of an y in tern al refresh cycles th at m ay

be in process at th e tim e of th e RAS# LOW-to-HIGH

tran sition . If th e DRAM con troller uses a distributed

CBR refresh sequen ce, a burst refresh is n ot required

upon exitin g self refresh . However, if th e DRAM con -

troller utilizes RAS#-ONLY or burst CBR refresh se-

quen ce, all rows m ust be refresh ed with in th e average

in tern al refresh rate prior to th e resum ption of n orm al

operation .

DRAM REFRESH

Th e supply voltage m ust be m ain tain ed at th e speci-

fied levels, an d th e refresh requirem en ts m ust be m et in

order to retain stored data in th e DRAM. Th e refresh

requirem en ts are m et by refresh in g all 8,192 rows (A7)

or all 4,096 rows (T8) in th e DRAM array at least on ce

every 64m s. Th e recom m en ded procedure is to execute

4,096 CBR REFRESH cycles, eith er un iform ly spaced or

grouped in bursts, every 64m s. Th e MT4LC16M4A7

in tern ally refresh es two rows for every CBR cycle,

STANDBY

Return in g RAS# an d CAS# HIGH term in ates a

m em ory cycle an d decreases ch ip curren t to a reduced

stan dby level. Th e ch ip is precon dition ed for th e n ext

cycle durin g th e RAS# HIGH tim e.

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

3

16 MEG x 4

FPM DRAM

*Stresses greater th an th ose listed un der “Absolute

Maxim um Ratin gs” m ay cause perm an en t dam age to

th e device. Th is is a stress ratin g on ly, an d fun ction al

operation of th e device at th ese or an y oth er con dition s

above th ose in dicated in th e operation al section s of

th is specification is n ot im plied. Exposure to absolute

m axim um ratin g con dition s for exten ded periods m ay

affect reliability.

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC Relative to VSS ................ -1V to +4.6V

Voltage on NC, In puts or I/O Pin s

Relative to V^SS..................................... -1V to +4.6V

Operatin g Tem perature, T_A(am bien t) ... 0°C to +70°C

Storage Tem perature (plastic) ............ -55°C to +150°C

Power Dissipation ................................................... 1W

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1, 5, 6) (VCC = +3.3V ±0.3V)

PARAMETER/CONDITION

SYMBOL MIN

MAX UNITS NOTES

SUPPLY VOLTAGE

VCC

VIH

VIL

II

3

3.6

VCC + 0.3

0.8

V

INPUT HIGH VOLTAGE:

Valid Logic 1; All inputs, I/Os and any NC

2

V

26

INPUT LOW VOLTAGE:

Valid Logic 0; All inputs, I/Os and any NC

-0.3

-2

V

INPUT LEAKAGE CURRENT:

Any input at VIN (0V ≤ VIN ≤ VCC + 0.3V);

All other pins not under test = 0V

2

µA

OUTPUT HIGH VOLTAGE:

IOUT = -2mA

VOH

VOL

IOZ

2.4

–

0.4

5

V

OUTPUT LOW VOLTAGE:

IOUT = 2mA

OUTPUT LEAKAGE CURRENT:

Any output at VOUT (0V ≤ VOUT ≤ VCC + 0.3V);

DQ is disabled and in High-Z state

-5

µA

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4

16 MEG x 4

FPM DRAM

ICC OPERATING CONDITIONS AND MAXIMUM LIMITS

(Notes: 1, 2, 3, 5, 6) (VCC = +3.3V ±0.3V)

4K

8K

PARAMETER/CONDITION

SYMBOL SPEED REFRESH REFRESH UNITS NOTES

STANDBY CURRENT: TTL

(RAS# = CAS# = VIH)

ICC1

ALL

1

mA

STANDBY CURRENT: CMOS

(RAS# = CAS# VCC - 0.2V, DQs may be left open,

other inputs: VIN VCC - 0.2V or VIN ≤ 0.2V)

ICC2

500

µA

OPERATING CURRENT: Random READ/WRITE

Average power supply current

I^CC3

-5

-6

170

160

130

120

mA

25

t

(RAS#, CAS#, address cycling: ^tRC = RC [MIN])

OPERATING CURRENT: FAST PAGE MODE

Average power supply current (RAS# = VIL,

ICC4

ICC5

ICC6

-5

-6

100

90

100

90

mA

t

CAS#, address cycling: ^tPC = PC [MIN])

REFRESH CURRENT: RAS#-ONLY

Average power supply current

-5

-6

170

160

130

120

22

t

(RAS# cycling, CAS# = VIH: ^tRC = RC [MIN])

REFRESH CURRENT: CBR

-5

-6

170

160

130

120

4, 7

Average power supply current

t

(RAS#, CAS#, address cycling: ^tRC = RC [MIN])

REFRESH CURRENT: Extended (“S” version only)

Average power supply current: CAS# = 0.2V or

t

CBR cycling; RAS# = RAS (MIN); WE# = VCC - 0.2V;

ICC7

ALL

400

µA

4, 7

A0-A11, OE# and D^IN= VCC - 0.2V or 0.2V

(DIN may be left open)

REFRESH CURRENT: Self (“S” version only)

Average power supply current: CBR with

RAS# ^tRASS (MIN) and CAS# held LOW;

WE# = VCC - 0.2V; A0-A11, OE# and DIN =

V^CC- 0.2V or 0.2V (DIN may be left open)

I^CC8

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

5

16 MEG x 4

FPM DRAM

CAPACITANCE

(Note: 2)

PARAMETER

SYMBOL MAX

UNITS

pF

Input Capacitance: Address pins

Input Capacitance: RAS#, CAS#, WE#, OE#

Input/Output Capacitance: DQ

CI1

CI2

CIO

5

7

pF

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V)

AC CHARACTERISTICS

-5

-6

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

NOTES

t

Access time from column address

Column-address hold time (referenced to RAS#)

Column-address setup time

Row-address setup time

AA

AR

25

30

t

40

0

45

0

t

ASC

ASR

0

t

Column address to WE# delay time

Access time from CAS#

AWD

48

55

18

t

CAC

CAH

13

15

t

Column-address hold time

CAS# pulse width

8

13

15

3

10

15

3

t

CAS

CHD

CHR

10,000

t

CAS# LOW to “Don’t Care” during Self Refresh

CAS# hold time (CBR Refresh)

CAS# to output in Low-Z

CAS# precharge time (FAST PAGE MODE)

Access time from CAS# precharge

CAS# to RAS# precharge time

CAS# hold time

t

4

t

CLZ

t

CP

8

10

13

t

CPA

CRP

CSH

CSR

30

35

t

5

50

5

60

5

t

CAS# setup time (CBR Refresh)

CAS# to WE# delay time

4

t

CWD

36

13

8

40

15

10

0

18

t

WRITE command to CAS# lead time

Data-in hold time

CWL

t

DH

19

t

Data-in setup time

DS

0

t

Output disable

OD

3

13

3

15

23, 24

20

t

Output enable time

OE

t

OE# hold time from WE# during

READ-MODIFY-WRITE cycle

OEH

13

15

24

t

Output buffer turn-off delay

OFF

3

0

13

50

3

0

15

60

ns

17, 23

t

OE# setup prior to RAS# during

HIDDEN REFRESH cycle

ORD

t

FAST-PAGE-MODE READ or WRITE cycle time

FAST-PAGE-MODE READ-WRITE cycle time

Access time from RAS#

PC

30

76

35

85

ns

t

PRWC

t

RAC

t

RAS# to column-address delay time

RAD

13

15

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

6

16 MEG x 4

FPM DRAM

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V)

AC CHARACTERISTICS

-5

-6

PARAMETER

SYMBOL

MIN

8

MAX

MIN

10

MAX

UNITS

ns

µs

NOTES

t

Row-address hold time

RAH

t

RAS# pulse width

RAS

50

100

90

18

0

10,000

60

10,000

t

RAS# pulse width (FAST PAGE MODE)

RAS# pulse width during Self Refresh

Random READ or WRITE cycle time

RAS# to CAS# delay time

RASP

RASS

125,000

60

125,000

23

100

110

20

t

RC

ns

ms

ns

t

RCD

RCH

RCS

14

16

t

READ command hold time (referenced to CAS#)

READ command setup time

Refresh period

0

t

0

t

REF

64

22

4

Refresh period (4,096 cycles) “S” version

RAS# precharge time

128

t

RP

30

0

40

0

t

RAS# to CAS# precharge time

RAS# precharge time exiting Self Refresh

READ command hold time (referenced to RAS#)

RAS# hold time

RPC

RPS

t

90

0

105

0

t

RRH

RSH

16

18

t

13

131

73

13

2

15

155

85

15

2

t

READ-WRITE cycle time

RWC

RWD

t

RAS# to WE# delay time

t

WRITE command to RAS# lead time

Transition time (rise or fall)

WRITE command hold time

WRITE command hold time (referenced to RAS#)

WE# command setup time

RWL

t

T

50

t

WCH

WCR

8

10

45

0

t

40

0

t

WCS

18

t

WRITE command pulse width

WE# hold time (CBR Refresh)

WE# setup time (CBR Refresh)

WP

8

10

t

WRH

WRP

10

4, 23

t

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

7

16 MEG x 4

FPM DRAM

NOTES

t

1. All voltages referen ced to VSS.

18. WCS, RWD, AWD, an d CWD are n ot

t

2. Th is param eter is sam pled. VCC = +3.3V; f = 1

MHz.

restrictive operatin g param eters. WCS applies to

t

EARLY WRITE cycles. If WCS > WCS (MIN), th e

cycle is an EARLY WRITE cycle an d th e data

output will rem ain an open circuit th rough out

3. I^CCis depen den t on output loadin g an d cycle

rates. Specified values are obtain ed with m in i-

m um cycle tim e an d th e outputs open .

4. En ables on -ch ip refresh an d address coun ters.

5. Th e m in im um specification s are used on ly to

in dicate cycle tim e at wh ich proper operation

over th e full tem perature ran ge is en sured.

6. An in itial pause of 100µs is required after power-

up, followed by eigh t RAS# refresh cycles (RAS#-

ONLY or CBR with WE# HIGH), before proper

device operation is en sured. Th e eigh t RAS# cycle

t

th e en tire cycle. RWD, AWD, an d CWD defin e

READ-MODIFY-WRITE cycles. Meetin g th ese

lim its allows for readin g an d disablin g output

data an d th en applyin g in put data. Th e values

sh own were calculated for referen ce allowin g

10n s for th e extern al latch in g of read data an d

application of write data. OE# h eld HIGH an d

WE# taken LOW after CAS# goes LOW result in a

t

LATE WRITE (OE#-con trolled) cycle. WCS,

^tRWD, CWD an d AWD are n ot applicable in a

t

wake-ups sh ould be repeated an y tim e th e REF

refresh requirem en t is exceeded.

7. AC ch aracteristics assum e T = 5n s.

LATE WRITE cycle.

t

19. Th ese param eters are referen ced to CAS# leadin g

edge in EARLY WRITE cycles an d WE# leadin g

edge in LATE WRITE or READ-MODIFY-WRITE

cycles.

20. If OE# is tied perm an en tly LOW, LATE WRITE or

READ-MODIFY-WRITE operation s are n ot

possible.

21. A HIDDEN REFRESH m ay also be perform ed after

a WRITE cycle. In th is case, WE# = LOW an d OE#

= HIGH.

22. RAS#-ONLY REFRESH requires th at all 8,192 rows

of th e MT4LC16M4A7 or all 4,096 rows of th e

MT4LC16M4T8 be refresh ed at least on ce every

64m s. CBR REFRESH for eith er device requires

th at at least 4,096 cycles be com pleted every

64m s.

8. VIH (MIN) an d VIL (MAX) are referen ce levels for

m easurin g tim in g of in put sign als. Tran sition

tim es are m easured between V^IHan d VIL (or

between VIL an d VIH).

9. In addition to m eetin g th e tran sition rate

specification , all in put sign als m ust tran sit

between V^IHan d VIL (or between VIL an d VIH) in a

m on oton ic m an n er.

10. If CAS# = V^IH, data output is High -Z.

11. If CAS# = VIL, data output m ay con tain data from

th e last valid READ cycle.

12. Measured with a load equivalen t to two TTL

gates, 100pF an d V^OL= 0.8V an d VOH = 2V.

13. If CAS# is LOW at th e fallin g edge of RAS#,

output data will be m ain tain ed from th e previous

cycle. To in itiate a n ew cycle an d clear th e data-

t

23. Th e DQs open durin g READ cycles on ce OD or

t

out buffer, CAS# m ust be pulsed HIGH for CP.

^tOFF occur. If CAS# goes HIGH before OE#, th e

DQs will open regardless of th e state of OE#. If

CAS# stays LOW wh ile OE# is brough t HIGH, th e

DQs will open . If OE# is brough t back LOW

(CAS# still LOW), th e DQs will provide th e

previously read data.

t

14. Th e RCD (MAX) lim it is n o lon ger specified.

^tRCD (MAX) was specified as a referen ce poin t

t

on ly. If RCD was greater th an th e specified RCD

(MAX) lim it, th en access tim e was con trolled

t

exclusively by CAC (^tRAC [MIN] n o lon ger

t

applied). With or with out th e RCD lim it, AA

24. LATE WRITE an d READ-MODIFY-WRITE cycles

t

an d CAC m ust always be m et.

m ust h ave both OD an d OEH m et (OE# HIGH

durin g WRITE cycle) in order to en sure th at th e

output buffers will be open durin g th e WRITE

cycle. If OE# is taken back LOW wh ile CAS#

rem ain s LOW, th e DQs will rem ain open .

25. Colum n address ch an ged on ce each cycle.

26. V^IHoversh oot: VIH (MAX) = VCC + 2V for a pulse

width ≤ 10n s, an d th e pulse width can n ot be

greater th an on e th ird of th e cycle rate. VIL

un dersh oot: VIL (MIN) = -2V for a pulse width ≤

10n s, an d th e pulse width can n ot be greater th an

on e th ird of th e cycle rate.

t

15. Th e RAD (MAX) lim it is n o lon ger specified.

^tRAD (MAX) was specified as a referen ce poin t

t

on ly. If RAD was greater th an th e specified RAD

(MAX) lim it, th en access tim e was con trolled

t

exclusively by AA (^tRAC an d CAC n o lon ger

t

applied). With or with out th e RAD (MAX) lim it,

^tAA, RAC, an d CAC m ust always be m et.

16. Eith er RCH or RRH m ust be satisfied for a READ

cycle.

17. OFF (MAX) defin es th e tim e at wh ich th e output

t

ach ieves th e open circuit con dition an d is n ot

referen ced to VOH or VOL.

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

8

16 MEG x 4

FPM DRAM

READ CYCLE

t

RC

t

RAS

RP

V

IH

IL

RAS#

CAS#

t

CSH

RSH

CAS

RRH

t

RCD

CRP

V

IH

IL

t

AR

t

RAD

RAH

t

ASR

ASC

CAH

V

IH

IL

ROW

COLUMN

ROW

ADDR

WE#

t

RCS

RCH

V

IH

IL

t

AA

RAC

CAC

CLZ

t

OFF

V

IOH

IOL

DQ

OPEN

VALID DATA

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

MAX

13

MIN

MAX

15

UNITS

ns

t

AA

25

30

OFF

RAC

RAD

RAH

RAS

RC

3

t

AR

40

0

45

0

ns

50

60

ns

t

ASC

ns

13

8

15

10

60

110

20

0

ns

t

ASR

0

ns

t

CAC

13

15

ns

50

90

18

0

10,000

ns

t

CAH

8

13

3

10

15

3

ns

t

CAS

10,000

ns

RCD

RCH

RCS

RP

ns

t

CLZ

ns

t

CRP

5

ns

0

ns

t

CSH

50

3

60

3

ns

30

0

40

0

ns

t

OD

13

15

ns

RRH

RSH

ns

t

OE

ns

13

15

ns

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

9

16 MEG x 4

FPM DRAM

EARLY WRITE CYCLE

t

RC

t

RP

RAS

V

IH

IL

RAS#

CAS#

t

CSH

t

RSH

t

CRP

RCD

CAS

V

IH

IL

t

AR

t

RAD

RAH

t

ASC

t

ASR

CAH

V

IH

IL

ADDR

ROW

COLUMN

ROW

t

CWL

t

RWL

WCR

WCH

WP

t

WCS

V

IH

IL

WE#

DQ

t

DS

DH

V

IOH

IOL

VALID DATA

V

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

40

0

MAX

MIN

45

0

MAX

UNITS

ns

SYMBOL

MIN

8

MAX

MIN

10

60

110

20

40

15

10

45

0

MAX

UNITS

ns

t

AR

RAH

t

ASC

ns

RAS

50

90

18

30

13

8

10,000

ns

t

ASR

0

ns

RC

ns

t

CAH

8

10

15

5

ns

RCD

ns

t

CAS

13

5

10,000

ns

RP

ns

t

CRP

ns

RSH

ns

t

CSH

50

13

8

60

15

10

0

ns

RWL

ns

t

CWL

ns

WCH

ns

t

DH

ns

WCR

40

0

ns

t

DS

0

ns

WCS

ns

t

RAD

13

15

ns

WP

8

10

ns

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

10

16 MEG x 4

FPM DRAM

READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

t

RWC

t

RAS

RP

V

IH

IL

RAS#

CAS#

t

CSH

t

RSH

t

CAS

CRP

ASR

RCD

V

IH

IL

t

AR

t

RAD

t

CAH

RAH

ASC

RCS

V

IH

IL

ADDR

ROW

COLUMN

ROW

t

RWD

CWL

RWL

WP

t

CWD

t

AWD

V

IH

IL

WE#

t

AA

t

RAC

t

CAC

t

DS

DH

t

CLZ

V

IOH

IOL

VALID D

DQ

OPEN

OUT

IN

t

OE

OD

OEH

V

IH

IL

OE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

MAX

13

MIN

MAX

15

UNITS

ns

t

AA

25

30

OD

3

t

AR

40

0

45

0

ns

OE

13

15

ns

t

ASC

ns

OEH

RAC

RAD

RAH

RAS

RCD

RCS

RP

13

15

ns

t

ASR

0

ns

50

60

ns

t

AWD

48

55

ns

13

8

15

10

60

20

0

ns

t

CAC

13

15

ns

t

CAH

8

13

3

10

15

3

ns

50

18

0

10,000

ns

t

CAS

10,000

ns

t

CLZ

ns

t

CRP

5

ns

30

13

131

73

13

8

40

15

155

85

15

10

ns

t

CSH

50

36

13

8

60

40

15

10

0

ns

RSH

RWC

RWD

RWL

WP

ns

t

CWD

ns

t

CWL

ns

t

DH

ns

t

DS

0

ns

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

11

16 MEG x 4

FPM DRAM

FAST-PAGE-MODE READ CYCLE

t

RASP

RP

V

IH

IL

RAS#

CAS#

t

RSH

CAS

CSH

PC

t

CRP

RCD

CAS

CP

CAS

CP

V

IH

IL

t

AR

t

RAD

RAH

t

CAH

ASR

ASC

CAH

ASC

CAH

ASC

V

IH

IL

ADDR

WE#

ROW

COLUMN

t

COLUMN

t

ROW

t

RCS

t

RCS

RRH

t

RCS

RCH

t

RCH

V

IH

IL

t

AA

RAC

CAC

CPA

CAC

CPA

CAC

t

OFF

t

OFF

t

CLZ

V

IOH

IOL

VALID

DATA

VALID

DATA

VALID

DATA

DQ

OPEN

t

OE

OD

OE

OD

OE

OD

V

IH

IL

OE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

SYMBOL

MIN

MAX

13

MIN

MAX

15

UNITS

ns

t

AA

25

30

ns

OE

t

AR

40

0

45

0

OFF

3

13

3

15

ns

t

ASC

PC

30

35

ns

t

ASR

0

RAC

50

60

ns

t

CAC

13

15

RAD

13

8

15

10

60

20

0

ns

t

CAH

8

13

3

10

15

3

RAH

ns

t

CAS

10,000

RASP

50

18

0

125,000

ns

t

CLZ

RCD

ns

t

CP

8

10

RCH

ns

t

CPA

30

13

35

15

RCS

0

ns

t

CRP

5

50

3

5

60

3

RP

30

0

40

0

ns

t

CSH

RRH

ns

t

OD

RSH

13

15

ns

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

12

16 MEG x 4

FPM DRAM

FAST-PAGE-MODE EARLY WRITE CYCLE

t

RP

RASP

V

IH

IL

RAS#

CAS#

t

CSH

PC

RSH

CAS

t

CRP

RCD

CAS

CP

CAS

CP

V

IH

IL

t

AR

t

RAD

t

CAH

ASR

RAH

ASC

CAH

ASC

CAH

ASC

V

IH

IL

ADDR

ROW

COLUMN

ROW

t

CWL

WCH

WP

t

WCS

WCH

WP

WCS

WCH

WP

V

IH

IL

WE#

t

WCR

DH

RWL

t

DS

DH

DS

DH

V

IOH

IOL

DQ

VALID DATA

V

IH

IL

OE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

40

0

MAX

MIN

45

0

MAX

UNITS

ns

SYMBOL

MIN

13

8

MAX

MIN

15

10

60

20

40

15

10

45

0

MAX

UNITS

ns

t

AR

RAD

t

ASC

ns

RAH

ns

t

ASR

0

ns

RASP

50

18

30

13

8

125,000

ns

t

CAH

8

10

15

10

5

ns

RCD

ns

t

CAS

13

8

10,000

ns

RP

ns

t

CP

ns

RSH

ns

t

CRP

5

ns

RWL

ns

t

CSH

50

13

8

60

15

10

0

ns

WCH

ns

t

CWL

ns

WCR

40

0

ns

t

DH

ns

WCS

ns

t

DS

0

ns

WP

8

10

ns

t

PC

30

35

ns

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

13

16 MEG x 4

FPM DRAM

FAST-PAGE-MODE READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

t

RASP

RP

V

IH

IL

RAS#

CAS#

t

CSH

NOTE 1

CP

PC

t

PRWC

RSH

CAS

t

CRP

RCD

CAS

CP

V

IH

IL

t

AR

t

RAD

RAH

t

CAH

ASR

ASC

CAH

ASC

CAH

ASC

V

IH

IL

ADDR

ROW

COLUMN

ROW

t

RWD

t

RWL

t

RCS

t

CWL

t

WP

t

AWD

CWD

t

CWD

V

IH

IL

WE#

t

AA

t

RAC

t

DH

t

CPA

t

DS

t

CAC

CLZ

CAC

CLZ

CAC

CLZ

V

IOH

IOL

VALID

OUT

VALID

IN

VALID

OUT

VALID

IN

VALID

OUT

VALID

IN

DQ

OPEN

D

t

OD

t

OE

OEH

V

IH

IL

OE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

SYMBOL

MIN

MAX

13

MIN

MAX

15

UNITS

ns

t

AA

25

30

ns

OD

3

t

AR

40

0

45

0

OE

13

15

ns

t

ASC

OEH

13

30

76

15

35

85

ns

t

ASR

0

PC

ns

t

AWD

48

55

PRWC

ns

t

CAC

13

15

RAC

50

60

ns

t

CAH

8

13

3

10

15

3

RAD

13

8

15

10

60

20

0

ns

t

CAS

10,000

RAH

ns

t

CLZ

RASP

50

18

0

125,000

ns

t

CP

8

10

RCD

ns

t

CPA

30

35

RCS

ns

t

CRP

5

50

36

13

8

5

RP

30

13

73

13

8

40

15

85

15

10

ns

t

CSH

60

40

15

10

0

RSH

ns

t

CWD

RWD

ns

t

CWL

RWL

ns

t

DH

WP

ns

t

DS

0

t

NOTE: 1. PC is for LATE WRITE only.

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

14

16 MEG x 4

FPM DRAM

FAST-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

t

RASP

RP

V

IH

IL

RAS#

CAS#

t

RSH

t

CSH

AR

PC

t

CP

CRP

RCD

CAS

CP

CAS

V

IH

IL

t

RAD

RAH

t

CAH

t

CAH

ASC

ASR

ASC

V

IH

IL

ADDR

ROW

COLUMN

t

ROW

CWL

t

RCS

RWL

t

WP

t

WCS

WCH

V

IH

IL

WE#

DQ

t

CAC

NOTE 1

t

DH

CLZ

OFF

DS

V

VALID

DATA

OH

OL

VALID DATA

OPEN

V

t

AA

t

RAC

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

3

MAX

MIN

MAX

UNITS

ns

t

AA

25

30

OFF

PC

13

3

15

t

AR

40

0

45

0

ns

30

35

ns

t

ASC

ns

RAC

RAD

RAH

50

60

ns

t

ASR

0

ns

13

8

15

10

60

20

0

ns

t

CAC

13

15

ns

t

CAH

8

13

3

10

15

3

ns

RASP

RCD

RCS

RP

50

18

0

125,000

ns

t

CAS

10,000

ns

t

CLZ

ns

t

CP

8

10

5

ns

30

13

8

40

15

10

0

ns

t

CRP

5

ns

RSH

RWL

WCH

WCS

WP

ns

t

CSH

50

13

8

60

15

10

0

ns

t

CWL

ns

t

DH

ns

0

ns

t

DS

0

ns

8

10

ns

NOTE: 1. Do not drive input data prior to output data going High-Z.

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

15

16 MEG x 4

FPM DRAM

RAS#-ONLY REFRESH CYCLE

(OE# and WE# = DON’T CARE)

t

RC

t

RP

RAS

V

IH

IL

RAS#

CAS#

t

CRP

RPC

V

IH

IL

t

RAH

ASR

V

IH

IL

ADDR

DQ

ROW

V

OH

OL

OPEN

V

CBR REFRESH CYCLE

(Addresses and OE# = DON’T CARE)

t

RAS

RP

RAS

NOTE 1

RP

V

IH

IL

RAS#

t

RPC

CP

t

RPC

t

CHR

CSR

CHR

CSR

V

IH

IL

CAS#

DQ

V

OH

OL

OPEN

V

t

WRH

WRP

WRH

WRP

V

IH

IL

WE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

0

MAX

UNITS

ns

SYMBOL

MIN

50

90

30

0

MAX

MIN

60

MAX

10,000

UNITS

ns

t

ASR

0

15

8

RAS

10,000

t

CHR

15

10

5

ns

RC

110

40

ns

t

CP

ns

RP

ns

t

CRP

5

ns

RPC

0

ns

t

CSR

5

ns

WRH

10

ns

t

RAH

8

10

ns

WRP

10

ns

NOTE: 1. End of CBR REFRESH cycle.

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

16

16 MEG x 4

FPM DRAM

1

HIDDEN REFRESH CYCLE

(WE# = HIGH; OE# = LOW)

t

RAS

RP

V

IH

IL

RAS#

CAS#

t

CRP

RCD

RSH

CHR

V

IH

IL

t

AR

RAD

t

CAH

ASR

RAH

ASC

V

IH

IL

ADDR

ROW

COLUMN

t

AA

t

RAC

CAC

CLZ

t

OFF

V

IOH

IOL

DQ

OPEN

VALID DATA

OPEN

t

OE

OD

V

t

IH

IL

ORD

OE#

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ns

SYMBOL

MIN

MAX

MIN

MAX

15

UNITS

ns

t

AA

25

30

OE

13

t

AR

40

0

45

0

ns

OFF

ORD

RAC

RAD

RAH

RAS

RCD

RP

3

0

3

0

15

ns

t

ASC

ns

t

ASR

0

ns

50

60

ns

t

CAC

13

15

ns

13

8

15

10

60

20

40

15

ns

t

CAH

8

15

3

10

15

3

ns

t

CHR

ns

50

18

30

13

10,000

ns

t

CLZ

ns

t

CRP

5

ns

t

OD

3

13

3

ns

RSH

ns

NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

17

16 MEG x 4

FPM DRAM

SELF REFRESH CYCLE

(Addresses and OE# = DON’T CARE)

NOTE 1

t

RP

RASS

RPS

( (

) )

NOTE 2

V

IH

IL

RAS#

CAS#

t

( (

) )

( (

) )

RPC

CP

RPC

t

CP

CSR

CHD

( (

) )

V

IH

IL

( (

) )

V

( (

) )

OH

OL

OPEN

DQ

t

WRH

WRP

WRH

WRP

( (

) )

V

IH

IL

WE#

( (

) )

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

-5

-6

SYMBOL

MIN

15

8

MAX

MIN

15

MAX

UNITS

SYMBOL

MIN

0

MAX

MIN

MAX

UNITS

ns

t

CHD

ns

µs

ns

RPC

0

t

CP

10

RPS

90

10

105

10

ns

t

CSR

5

WRH

ns

t

RASS

100

30

100

40

WRP

10

ns

t

RP

t

NOTE: 1. Once RASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.

t

2. Once RPS is satisfied, a complete burst of all rows should be executed, if RAS#-only or burst CBR refresh is used.

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

18

16 MEG x 4

FPM DRAM

32-PIN PLASTIC SOJ (400 m il)

.829 (21.05)

.823 (20.90)

.750[19.05] (TYP)

.050[1.27] (TYP)

.445 (11.31)

.435 (11.05)

.405 (10.29)

.399 (10.13)

.145 (3.68)

.132 (3.35)

PIN #1 INDEX

.095 (2.42)

.080 (2.03)

.037 [0.95] MAX DAMBAR PROTRUSION

.032 (0.82)

.026 (0.67)

.030 [0.76] MIN

.024 [0.61]

SEATING

PLANE

.020 (0.51)

.015 (0.38)

.040 (1.02)

.030 (0.77)

R

.380 (9.65)

.360 (9.14)

MAX

MIN

NOTE: 1. All dimensions in inches (millimeters)

or typical where noted.

2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

19

16 MEG x 4

FPM DRAM

32-PIN PLASTIC TSOP (400 m il)

20.96 ±0.08

SEE DETAIL A

1.27

TYP

0.95

11.76 ±0.10

10.16 ±0.08

PIN 1 ID

+0.07

0.43

+0.03

-0.02

0.15

-0.13

0.25

0.10

1.20

MAX

GAGE PLANE

+0.10

-0.05

0.10

0.80 TYP

0.50 ±0.10

DETAIL A

MAX

MIN

NOTE: 1. All dimensions in millimeters

or typical where noted.

2. Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side.

8000 S. Fe d e ra l Wa y, P.O. Bo x 6, Bo ise , ID 83707-0006, Te l: 208-368-3900

E-m a il: p ro d m kt g @m icro n .co m , In t e rn e t : h t t p ://w w w .m icro n .co m , Cu st o m e r Co m m e n t Lin e : 800-932-4992

Micron is a registered trademark of Micron Technology, Inc.

16 Meg x 4 FPM DRAM

D21_2.p65 – Rev. 5/00

Micron Technology, Inc., reserves the right to change products or specifications without notice.

20


型号：	MT4LC16M4A7TG-5
厂家：	MICRON TECHNOLOGY
描述：	DRAM DRAM 动态存储器
文件：	总20页 (文件大小：350K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT4LC16M4A7TG-5 [MICRON]

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