MT54W2MH18B-5 [MICRON]
36Mb QDR⑩II SRAM 2-WORD BURST; 36MB QDR⑩II SRAM 2字突发
| 型号： | MT54W2MH18B-5 |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | 36Mb QDR⑩II SRAM 2-WORD BURST |
| 文件： | 总27页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE‡
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W4MH8B
36Mb QDR™II SRAM
2-WORD BURST
MT54W4MH9B
MT54W2MH18B
MT54W1MH36B
FEATURES
Figure 1
165-Ball FBGA
•
DLL circuitry for accurate output data placement
Separate independent read and write data ports
with concurrent transactions
•
•
100 percent bus utilization DDR READ and WRITE
operation
•
•
•
•
•
Fast clock to valid data times
Full data coherency, providing most current data
Two-tick burst counter for low DDR transaction size
Double data rate operation on read and write ports
Two input clocks (K and K#) for precise DDR timing
at clock rising edges only
•
Two output clocks (C and C#) for precise flight time
and clock skew matching—clock and data delivered
together to receiving device
•
•
•
•
•
•
Single address bus
Simple control logic for easy depth expansion
Internally self-timed, registered writes
+1.8V core and HSTL I/O
Clock-stop capability
15mm x 17mm, 1mm pitch, 11 x 15 grid FBGA
package
VALID PART NUMBERS
PART NUMBER
DESCRIPTION
MT54W4MH8BF-xx
MT54W4MH9BF-xx
4 Meg x 8, QDRIIb2 FBGA
4 Meg x 9, QDRIIb2 FBGA
•
•
User-programmable impedance output
JTAG boundary scan
MT54W2MH18BF-xx 2 Meg x 18, QDRIIb2 FBGA
MT54W1MH36BF-xx 1 Meg x 36, QDRIIb2 FBGA
OPTIONS
MARKING1
•
•
•
Clock Cycle Timing
4ns (250 MHz)
5ns (200 MHz)
6ns (167 MHz)
7.5ns (133 MHz)
Configurations
4 Meg x 8
4 Meg x 9
2 Meg x 18
1 Meg x 36
Package
GENERAL DESCRIPTION
The Micron® QDR™II (Quad Data Rate™) synchro-
nous, pipelined burst SRAM employs high-speed, low-
power CMOS designs using an advanced 6T CMOS
process.
-4
-5
-6
-7.5
The QDR architecture consists of two separate DDR
(double data rate) ports to access the memory array.
The read port has dedicated data outputs to support
READ operations. The write port has dedicated data
inputs to support WRITE operations. This architecture
eliminates the need for high-speed bus turnaround.
Access to each port is accomplished using a common
address bus. Addresses for reads and writes are latched
on rising edges of the K and K# input clocks, respec-
tively. Each address location is associated with two
words that burst sequentially into or out of the device.
MT54W4MH8B
MT54W4MH9B
MT54W2MH18B
MT54W1MH36B
165-ball, 15mm x 17mm FBGA
F
NOTE:
1. A Part Marking Guide for the FBGA devices can be found
on Micron’s Web site—http://www.micron.com/number-
guide.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev. 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
1
‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
GENERAL DESCRIPTION (continued)
Since data can be transferred into and out of the
device on every rising edge of both clocks (K and K#, C
and C#), memory bandwidth is maximized while sys-
tem design is simplified by eliminating bus turn-
arounds.
The SRAM operates from a +1.8V power supply, and
all inputs and outputs are HSTL-compatible. The
device is ideally suited for applications that benefit
from a high-speed, fully-utilized DDR data bus.
Please refer to Micron’s Web site (www.micron.com/
sramds) for the latest data sheet.
Depth expansion is accomplished with port selects
for each port (read R#, write W#), which are received at
K rising edge. Port selects permit independent port
operation.
READ/WRITE OPERATIONS
All bus transactions operate on an uninterruptable
burst of two data, requiring one full clock cycle of bus
utilization. The resulting benefit is that short data
transactions can remain in operation on both buses
provided that the address rate can be maintained by
the system (2x the clock frequency).
All synchronous inputs pass through registers con-
trolled by the K or K# input clock rising edges. Active
LOW byte writes (BWx#) permit byte or nibble write
selection. Write data and byte writes are registered on
the rising edges of both K and K#. The addressing
within each burst of two is fixed and sequential, begin-
ning with the lowest and ending with the highest
address. All synchronous data outputs pass through
output registers controlled by the rising edges of the
output clocks (C and C# if provided, otherwise K and
K#).
Four balls are used to implement JTAG test capabili-
ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 1.8V I/O levels to shift data
during this testing mode of operation.
READ cycles are pipelined. The request is initiated
by asserting R# LOW at K rising edge. Data is delivered
after the rising edge of K# (t + 1) using C and C# as the
output timing references or using K and K#, if C and C#
are tied HIGH. If C and C# are tied HIGH, they may not
be toggled during device operation. Output tri-stating
is automatically controlled such that the bus is
released if no data is being delivered. This permits
banked SRAM systems with no complex OE timing
generation. Back-to-back READ cycles are initiated
every K rising edge.
Figure 2
Functional Block Diagram: 2 Meg x 18
n
ADDRESS
R#
n
ADDRESS
REGISTRY
& LOGIC
W#
K
K#
W#
BW0#
BW1#
O
B
D
R
I
V
E
R
O
U
T
O
U
T
S
E
L
E
C
T
W R
R E
I G
T
W
R
I
T
E
S
E
N
S
R
E
U U
DATA
REGISTRY
& LOGIC
A
M
P
n
18
36
36
18
2
x 36
36
T
P
U
T
F
F
E
R
G
D (Data In)
MUX
Q
MEMORY
ARRAY
P
P
(Data Out)
2
R#
U
T
U
T
A
S
E 2
E
K
C
K
K#
CQ, CQ#
C, C#
(Echo Clock Out)
or
K, K#
NOTE:
1. The functional block diagram illustrates simplified device operation. See truth table, ball descriptions, and timing diagrams for
detailed information. The x8, x9, and x36 operations are the same, with apporpriate adjustments of depth and width.
2. n = 20
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
2
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
READ/WRITE OPERATIONS (continued)
PROGRAMMABLE IMPEDANCE OUTPUT
BUFFER
WRITE cycles are initiated by W# LOW at K rising
edge. The address for the WRITE cycle is provided at
the following K# rising edge. Data is expected at the
rising edge of K and K#, beginning at the same K that
initiated the cycle. Write registers are incorporated to
facilitate pipelined, self-timed WRITE cycles and to
provide fully coherent data for all combinations of
reads and writes. A read can immediately follow a
write, even if they are to the same address. Although
the write data has not been written to the memory
array, the SRAM will deliver the data from the write
register instead of using the older data from the mem-
ory array. The latest data is always utilized for all bus
transactions. WRITE cycles can be initiated on every K
rising edge.
The QDR SRAM is equipped with programmable
impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ ball and VSS. The value of the
resistor must be five times the desired impedance. For
example, a 350ꢀ resistor is required for an output
impedance of 70ꢀ. To ensure that output impedance
is one-fifth the value of RQ (within 15 percent), the
range of RQ is 175ꢀ to 350ꢀ. Alternately, the ZQ ball
can be connected directly to VDDQ, which will place
the device in a minimum impedance mode.
Output impedance updates may be required
because variations may occur over time in supply volt-
age and temperature. The device samples the value of
RQ. Impedance updates are transparent to the system;
they do not affect device operation, and all data sheet
timing and current specifications are met during an
update.
The device will power up with an output impedance
set at 50ꢀ. To guarantee optimum output driver
impedance after power-up, the SRAM needs 1,024
cycles to update the impedance. The user can operate
the part with fewer than 1,024 clock cycles, but optimal
output impedance is not guaranteed.
PARTIAL WRITE OPERATIONS
BYTE WRITE operations are supported, except for
the x8 devices in which nibble write is supported. The
active LOW byte write controls, BWx# (NWx#), are reg-
istered coincident with their corresponding data. This
feature can eliminate the need for some READ-MOD-
IFY-WRITE cycles, collapsing it to a single BYTE/NIB-
BLE WRITE operation in some instances.
Figure 3
Application Example
SRAM #1
SRAM #4
B
R = 250Ω
R = 250Ω
Vt
ZQ
Q
C# K K#
ZQ
Q
C# K K#
B
R W W
# #
D
D
SA
R W W
# #
#
R
SA
C
#
C
DATA IN
DATA OUT
Address
Read#
Vt
Vt
R
BUS
MASTER
(CPU
Write#
BW#
or
ASIC)
Source K
Source K#
Delayed K
Delayed K#
R
R = 50Ω
Vt = VREF/2
NOTE:
In this approach, the second clock pair drives the C and C# clocks but is delayed such that return data meets data setup and
hold times at the bus master.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
3
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
CLOCK CONSIDERATIONS
DEPTH EXPANSION
This device utilizes internal delay-locked loops for
maximum output data valid window. It can be placed
into a stopped-clock state to minimize power with a
modest restart time of 1,024 clock cycles. Circuitry
automatically resets the DLL when the absence of
input clock is detected. See Micron Technical Note TN-
54-02 for more information on clock DLL start-up pro-
cedures.
Port select inputs are provided for the read and
write ports. This allows for easy depth expansion. Both
port selects are sampled on the rising edge of K only.
Each port can be independently selected and dese-
lected and does not affect the operation of the oppo-
site port. All pending transactions are completed prior
to a port deselecting. Depth expansion requires repli-
cating R# and W# control signals for each bank if it is
desired to have the bank independent of READ and
WRITE operations.
SINGLE CLOCK MODE
The SRAM can be used with the single K, K# clock
pair by tying C and C# HIGH. In this mode, the SRAM
will use K and K# in place of C and C#. This mode pro-
vides the most rapid data output but does not com-
pensate for system clock skew and flight times.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
4
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
4 MEG x 8 BALL ASSIGNMENT (TOP VIEW)
165-BALL FBGA
1
2
3
SA
4
5
6
7
8
9
SA
10
SA
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
VSS/SA1
NC
NW1#2
NC/SA4
SA
NC/SA3
NW0#5
SA
A
B
C
D
E
CQ#
NC
W#
K#
K
R#
NC
NC
NC
Q4
NC
Q5
VDDQ
NC
NC
D6
SA
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
NC
NC
NC
D2
NC
NC
D4
VSS
SA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
NC
VSS
VSS
VSS
VSS
NC
NC
NC
D5
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
F
NC
VDD
VDD
VDD
VDD
VDD
VSS
VDD
VDD
VDD
VDD
VDD
VSS
NC
NC
VREF
Q1
NC
NC
NC
NC
NC
TMS
G
H
J
NC
DLL#
NC
VREF
NC
NC
Q6
NC
D7
K
L
NC
NC
M
N
P
NC
NC
NC
Q7
SA
VSS
VSS
NC
VSS
SA
SA
VSS
NC
NC
TCK
SA
SA
SA
SA
R
TDO
SA
SA
C#
SA
SA
NOTE:
1. Expansion address: 2A for 72Mb
2. NW1# controls writes to D4:D7
3. Expansion address: 7A for 144Mb
4. Expansion address: 5B for 288Mb
5. NW0# controls writes to D0:D3
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
5
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
4 MEG x 9 BALL ASSIGNMENT (TOP VIEW)
165-BALL FBGA
1
2
3
SA
4
5
6
7
8
9
SA
10
SA
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
VSS/SA1
NC
NC/SA2
BW0#4
SA
A
B
C
D
E
CQ#
NC
W#
NC
K#
K
R#
NC/SA3
SA
NC
NC
NC
Q5
NC
Q6
VDDQ
NC
NC
D7
SA
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
NC
NC
NC
D3
NC
NC
VSS
SA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
VSS
NC
D5
NC
NC
D6
VSS
VSS
VSS
VSS
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
F
NC
VDD
VDD
VDD
VDD
VDD
VSS
VDD
VDD
VDD
VDD
VDD
VSS
NC
NC
VREF
Q2
NC
NC
NC
NC
D0
G
H
J
NC
DLL#
NC
VREF
NC
NC
Q7
NC
D8
K
L
NC
NC
M
N
P
NC
NC
NC
Q8
SA
VSS
VSS
NC
VSS
SA
SA
VSS
NC
NC
TCK
SA
SA
SA
SA
R
TDO
SA
SA
C#
SA
SA
TMS
NOTE:
1. Expansion address: 2A for 72Mb
2. Expansion address: 7A for 144Mb
3. Expansion address: 5B for 288Mb
4. BW0# controls writes to D0:D8
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
6
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
2 MEG x 18 BALL ASSIGNMENT (TOP VIEW)
165-BALL FBGA
1
2
3
4
5
6
7
8
9
10
11
VSS/SA1
Q9
BW1#2
NC
NC/SA3
VSS/SA4
NC
CQ#
NC
SA
W#
K#
R#
SA
CQ
A
B
C
D
E
BW0#5
SA
D9
D10
Q10
Q11
D12
Q13
VDDQ
D14
Q14
D15
D16
Q16
Q17
SA
SA
VSS
K
SA
VSS
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
NC
NC
D11
NC
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
Q7
NC
D6
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
Q12
D13
VREF
NC
NC
NC
VREF
Q4
D3
F
NC
G
H
J
DLL#
NC
NC
NC
K
L
NC
Q15
NC
NC
Q1
NC
D0
NC
M
N
P
NC
D17
NC
VSS
VSS
NC
SA
SA
SA
SA
TDO
TCK
SA
SA
C#
SA
SA
TMS
R
NOTE:
1. Expansion address: 2A for 144Mb
2. BW1# controls writes to D9:D17
3. Expansion address: 7A for 288Mb
4. Expansion address: 10A for 72Mb
5. BW0# controls writes to D0:D8
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
7
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
1 MEG x 36 BALL ASSIGNMENT (TOP VIEW)
165-BALL FBGA
1
2
3
4
5
6
7
8
9
10
11
VSS/SA1
Q18
NC/SA2
D18
BW2#3
BW1#4
VSS/SA5
Q17
CQ#
Q27
D27
D28
Q29
Q30
D30
DLL#
D31
Q32
Q33
D33
D34
Q35
TDO
W#
K#
R#
SA
CQ
A
B
C
D
E
BW3#6
SA
BW0#7
SA
SA
VSS
K
SA
VSS
D17
D16
Q16
Q15
D14
Q13
VDDQ
D12
Q12
D11
D10
Q10
Q9
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Q28
D20
D29
Q21
D22
VREF
Q31
D32
Q24
Q34
D26
D35
TCK
D19
Q19
Q20
D21
Q22
VDDQ
D23
Q23
D24
D25
Q25
Q26
SA
SA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
Q7
D15
D6
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
Q14
D13
VREF
Q4
F
G
H
J
D3
K
L
Q11
Q1
M
N
P
VSS
VSS
D9
SA
SA
SA
SA
D0
SA
SA
C#
SA
SA
SA
TMS
R
NOTE:
1. Expansion address: 2A for 288Mb
2. Expansion address: 3A for 72Mb
3. BW2# controls writes to D18:D26
4. BW1# controls writes to D9:D17
5. Expansion address: 10A for 144Mb
6. BW3# controls writes to D27:D35
7. BW0# controls writes to D0:D8
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
8
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
FBGA BALL DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
SA
Input
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of K for READ cycles and K# for WRITE cycles. See Ball
Assignment figures for address expansion inputs. All transactions operate on a burst of two
words (one clock period of bus activity). These inputs are ignored when both ports are
deselected.
R#
Input
Input
Input
Synchronous Read: When LOW, this input causes the address inputs to be registered and a
READ cycle to be initiated. This input must meet setup and hold times around the rising edge
of K.
W#
Synchronous Write: When LOW, this input causes the address inputs to be registered and a
WRITE cycle to be initiated. This input must meet setup and hold times around the rising
edge of K.
BW_#
NW_#
Synchronous Byte Writes (or Nibble Writes on the x8): When LOW, these inputs cause their
respective Bytes to be registered and written if W# had initiated a WRITE cycle. These signals
must meet setup and hold times around the rising edges of K and K# for each of the two
rising edges comprising the WRITE cycle. See Ball Assignment figures for signal to data
relationships.
K
K#
Input
Input
Input Clock: This input clock pair registers address and control inputs on the rising edge of K,
and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees
out of phase with K. All synchronous inputs must meet setup and hold times around the clock
rising edges.
C
C#
Output Clock: This clock pair provides a user-controlled means of tuning device output data.
The rising edge of C is used as the output timing reference for second output data. The rising
edge of C# is used as the output reference for first output data. Ideally, C# is 180 degrees out
of phase with C. C and C# may be tied HIGH to force the use of K and K# as the output
reference clocks instead of having to provide C and C# clocks. If tied HIGH, these inputs may
not be allowed to toggle during device operation.
TMS
TDI
Input
Input
Input
Input
IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left as No Connects if the JTAG
function is not used in the circuit.
TCK
VREF
ZQ
IEEE 1149.1 Clock Input: 1.8V I/O levels. This ball must be tied to VSS if the JTAG function is not
used in the circuit.
HSTL Input Reference Voltage: Nominally VDDQ/2, but may be adjusted to improve system
noise margin. Provides a reference voltage for the HSTL input buffer trip point.
Output Impedance Matching Input: This input is used to tune the device outputs to the
system data bus impedance. DQ output impedance is set to 0.2 x RQ, where RQ is a resistor
from this ball to ground. Alternately, this ball can be connected directly to VDDQ to enable
the minimum impedance mode. This ball cannot be connected directly to GND or left
unconnected.
DLL#
D_
Input
Input
DLL Disable: When LOW, this input causes the DLL to be bypassed for stable, low-frequency
operation.
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges
of K and K# during WRITE operations. See Ball Assignment figures for ball site location of
individual signals. The x8 device uses D0-D7. Remaining signals are NC. The x9 device uses D0-
D8. Remaining signals are NC. The x18 device uses D0–D17. Remaining signals are NC. The x36
device uses D0–D35. Remaining signals are NC.
CQ#, CQ
TDO
Output
Output
Synchronous Echo Clock Outputs: The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as data valid indication. These signals run freely
and do not stop when Q tri-states.
IEEE 1149.1 Test Output: 1.8V I/0 level.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
9
©2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
FBGA BALL DESCRIPTIONS (continued)
SYMBOL
TYPE
DESCRIPTION
Q_
Output
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K
and K# rising edges if C and C# are tied HIGH. This bus operates in response to R# commands.
See Ball Assignment figures for ball site location of individual signals. The x8 device uses D0-
D7. The x9 device uses D0-D8. The x18 device uses Q0–Q17. Remaining signals are NC. The x36
device uses Q0–Q35. Remaining signals are NC.
VDD
Supply
Supply
Power Supply: 1.8V nominal. See DC Electrical Characteristics and Operating Conditions for
range.
VDDQ
Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC
Electrical Characteristics and Operating Conditions for range.
VSS
NC
Supply
–
Power Supply: GND.
No Connect: These signals are not internally connected and may be connected to ground to
improve package heat dissipation.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
10
©2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
Figure 4
Bus Cycle State Diagram
RD
RD
LOAD NEW
/RD
READ DOUBLE
READ PORT NOP
R_Init=0
READ ADDRESS
always
Supply voltage
provided
/RD
POWER-UP
WT
Supply voltage
provided
WT
LOAD NEW
WRITE ADDRESS
AT K#↑
/WT
WRITE PORT NOP
WRITE DOUBLE
AT K#↑
always
/WT
NOTE:
1. The address is concatenated with one additional internal LSB to facilitate burst operation. The address order is always fixed as xxx .
. . xxx + 0, xxx . . . xxx + 1. Bus cycle is terminated at the end of this sequence (burst count = 2).
2. State transitions: RD = (R# = LOW); WT = (W# = LOW).
3. Read and write state machines can be simultaneously active.
4. State machine control timing sequence is controlled by K.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
11
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
TRUTH TABLE
Notes 1-6
OPERATION
K
R#
W#
D or Q
D or Q
LJH
X
L
DA(A + 0)
at
K(t)I
DA(A + 1)
at
K#(t)I
WRITE Cycle:
Load address, input write data on
consecutive K and K# rising edges
LJH
L
X
QA(A + 0)
at
C#(t + 1)I
QA(A + 1)
at
C(t + 2)I
READ Cycle:
Load address, output data on
consecutive C and C# rising edges
NOP: No operation
LJH
H
X
H
X
D = X
Q = High-Z
D = X
Q = High-Z
STANDBY: Clock stopped
Stopped
Previous
State
Previous
State
BYTE WRITE OPERATION
Notes 7, 8
OPERATION
K
K#
BW0#
BW1#
LJH
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
WRITE D0-17 at K rising edge
WRITE D0-17 at K# rising edge
WRITE D0-8 at K rising edge
WRITE D0-8 at K# rising edge
WRITE D9-17 at K rising edge
WRITE D9-17 at K# rising edge
WRITE nothing at K rising edge
WRITE nothing at K# rising edge
LJH
LJH
LJH
LJH
LJH
LJH
LJH
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. I means rising edge; K means falling edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges, except if C and C# are
HIGH, then data outputs are delivered at K and K# rising edges.
3. R# and W# must meet setup and hold times around the rising edge (LOW to HIGH) of K and are registered at the rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential, but permits most rapid restart by overcoming
transmission line charging symmetrically.
7. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation, provided that
the setup and hold requirements are satisfied.
8. This table illustrates operation for the x18 devices. The x36 device operation is similar, except for the addition of BW2# (controls
D18:D26) and BW3# (controls D27:D35). The x9 device operation is similar, except that BW1# and D8:D17 are not available. The x8
device operation is similar, except that NW0# controls D0:D3, and NW1# controls D4:D7.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
12
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
*Stresses greater than those listed under Absolute Maximum
ABSOLUTE MAXIMUM RATINGS*
Ratings may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
**Maximum junction temperature depends upon package
type, cycle time, loading, ambient temperature, and airflow.
See Micron Technical Note TN-05-14 for more information.
Voltage on VDD Supply
Relative to VSS ........................................ 0.5V to +2.8V
Voltage on VDDQ Supply
Relative to VSS ....................................... -0.5V to +VDD
VIN ..................................................... -0.5V to VDD + 0.5V
Storage Temperature..............................-55ºC to +125ºC
Junction Temperature**....................................... +125ºC
Short Circuit Output Current .............................. 70mA
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
0ºC
?
TA
?
+70ºC; +1.7V ? VDD ? +1.9V unless otherwise noted
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS NOTES
VIH(DC)
VIL(DC)
VIN
VREF + 0.1
VDDQ + 0.3
V
V
3, 4
3, 4
3, 4
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Clock Input Signal Voltage
Input Leakage Current
-0.3
-0.3
-5
VREF - 0.1
VDDQ + 0.3
V
0V ? VIN ? VDDQ
ILI
5
5
µA
µA
Output(s) disabled,
ILO
-5
Output Leakage Current
0V ? VIN ? VDDQ (Q)
|IOH| ? 0.1mA
Note 1
VOH (LOW)
VOH
VDDQ - 0.2
VDDQ/2 - 0.12
VSS
VDDQ
VDDQ/2 + 0.12
0.2
V
V
V
V
V
V
V
3, 5, 7
3, 5, 7
3, 5, 7
3, 5, 7
3
Output High Voltage
Output Low Voltage
IOL ? 0.1mA
Note 2
VOL (LOW)
VOL
VDDQ/2 - 0.12
1.7
VDDQ/2 + 0.12
1.9
Supply Voltage
VDD
Isolated Output Buffer Supply
Reference Voltage
VDDQ
VREF
1.4
VDD
3, 6
0.68
0.95
3
AC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
0ºC
?
TA
?
+70ºC; +1.7V ? VDD ? +1.9V unless otherwise noted
DESCRIPTION
CONDITIONS
SYMBOL
VIH AC)
MIN
VREF + 0.2
–
MAX
–
UNITS
NOTES
3, 4, 8
3, 4, 8
V
V
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
NOTE:
VIL(AC)
VREF - 0.2
1. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175ꢀ ? RQ ? 350ꢀ.
2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175ꢀ ? RQ ? 350ꢀ.
3. All voltages referenced to VSS (GND).
t
4. Overshoot:
VIH(AC) ? VDD + 0.7V for t ? KHKH/2
t
Undershoot: VIL(AC)ꢁO -0.5V for t ? KHKH/2
Power-up:
VIH ? VDDQ + 0.3V and VDD ? 1.7V and VDDQ ? 1.4V for t ? 200ms
t
During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than KHKL
t
(MIN) or operate at cycle rates less than KHKH (MIN).
5. AC load current is higher than the shown DC values. AC I/O curves are available upon request.
6. Output buffer supply can be set to 1.5V or 1.8V nominal 0.1 with appropriate derating of AC timing parameters. Consult factory for
further information.
7. HSTL outputs meet JEDEC HSTL Class I and Class II standards.
8. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC).
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
13
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
0ºC
?
TA
?
+70ºC; VDD = MAX unless otherwise noted
MAX
DESCRIPTION
CONDITIONS
SYMBOL
TYP
-4
-5
-6
-7.5 UNITS NOTES
Operating Supply
Current: DDR
All inputs ? VIL or O VIH;
IDD
(x8, x9, x18)
(x36)
t
TBD
mA
1, 2, 3
Cycle time Oꢀ KHKH (MIN);
600
800
490
655
415
550
340
450
Outputs open
tKHKH = tKHKH (MIN);
Device in NOP state;
All addresses/data static
ISB1
(x8, x9 x18)
(x36)
Standby Supply
Current: NOP
TBD
TBD
mA
mA
2, 4
2
200
210
170
180
150
160
125
135
Cycle time = 0; Input Static
Stop Clock Current
ISB
75
75
75
75
IDDQ
(x8, x9)
(x18)
Output Supply
Current: DDR
(Information only)
32
71
142
25
57
113
21
47
95
17
38
76
CL = 15pF
TBD
mA
5
(x36)
CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
MAX
UNITS
NOTES
CI
4
5
pF
6
Address/Control Input
Capacitance
TA = 25ºC; f = 1 MHz
Output Capacitance (Q)
Clock Capacitance
CO
6
5
7
6
pF
pF
6
6
CCK
THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
UNITS
NOTES
ꢀJA
25
ºC/W
6, 7
Junction to Ambient
(Airflow of 1m/s)
Soldered on a 4.25 x 1.125 inch, 4-layer
printed circuit board
Junction to Case (Top)
Junction to Balls (Bottom)
NOTE:
ꢀ
JC
10
12
ºC/W
ºC/W
6
ꢀ
JB
6, 8
1. IDD is specified with no output current. IDD is linear with frequency. Typical value is measured at 6ns cycle time.
2. Typical values are measured at VDD = 1.8V, VDDQ = 1.5V, and temperature = 25°C.
3. Operating supply currents and burst mode currents are measured at 100 percent bus utilization.
4. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed.
5. Average I/O current and power is provided for information purposes only and is not tested. Calculation assumes that all outputs are
loaded with CL (in farads), f = input clock frequency, half of outputs toggle at each transition (for example, n = 18 for x36), CO = 6pF,
VDDQ = 1.5V and uses the equations: Average I/O Power as dissipated by the SRAM is:
2
P = 0.5 × n x f x VDDQ x (CL + 2CO). Average IDDQ = n x f x VDDQ x (CL + CO).
6. This parameter is sampled.
7. Average thermal resistance between the die and the case top surface per MIL SPEC 883 Method 1012.1.
8. Junction temperature is a function of total device power dissipation and device mounting environment. Measured per SEMI G38-
87.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
14
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING
CONDITIONS 1, 2, 3, 6, 8
0ºC
?
TA
?
+70ºC; +1.7V ?ꢁVDD ? +1.9V
-4
-5
-6
-7.5
DESCRIPTION
SYMBOL
UNITS
MIN
MAX
5.00
0.20
MIN
MAX
6.00
0.20
MIN
MAX
7.50
0.20
MIN
MAX
8.00
0.20
Clock
tKHKH
tKC var
4.00
5.00
6.0
7.50
ns
ns
Clock cycle time
(K, K#, C, C#)4
Clock phase jitter
(K, K#, C, C#)5
tKHKL
tKLKH
Clock HIGH time
(K, K#, C, C#)
Clock LOW time
(K, K#, C, C#)
Clock to clock#
(KIJK#I, CIJC#I) at
tKHKH minimum
1.60
1.60
1.80
2.00
2.00
2.20
2.40
2.40
2.70
3.00
3.00
3.38
ns
ns
ns
tKHK#H
tK#HKH
tKHCH
1.80
0.00
2.20
0.00
2.70
0.00
3.38
0.00
ns
ns
Clock to clock#
(K#IJKI, C#IJCI)
Clock to data clock
(KIJCI, K#IJC#I)
1.80
2.30
2.80
3.55
tKC lock
tKC reset
DLL lock time (K, C)6
K static to DLL reset
1,024
30
1,024
30
1,024
30
1,024
30
cycles
ns
Output Times
C, C# HIGH to output valid
tCHQV
tCHQX
tCHCQV
0.40
0.33
0.43
0.36
0.45
0.38
0.45
0.38
ns
ns
ns
-0.40
-0.33
-0.43
-0.36
-0.45
-0.38
-0.45
-0.38
C, C# HIGH to output hold
C, C# HIGH to echo clock
valid
tCHCQX
tCQHQV
C, C# HIGH to echo clock
hold
CQ, CQ# HIGH to output
valid7
ns
ns
0.35
0.0
0.38
0.43
0.40
0.45
0.40
0.45
tCQHQX
-0.35
-0.38
-0.40
-0.40
ns
CQ, CQ# HIGH to output
hold7
tCHQZ
tCHQX1
ns
ns
C HIGH to output High-Z
C HIGH to output Low-Z
-0.40
0.40
0.40
0.40
-0.43
0.50
0.50
0.50
-0.45
0.60
0.60
0.60
-0.45
0.70
0.70
0.70
Setup Times
Address valid to K rising
edge8
Control inputs valid to K
rising edge8
tAVKH
tIVKH
ns
ns
ns
tDVKH
Data-in valid to K, K# rising
edge8
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
15
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING
CONDITIONS 1, 2, 3, 6, 8
0ºC
?
TA
?
+70ºC; +1.7V ?ꢁVDD ? +1.9V
-4
-5
-6
-7.5
DESCRIPTION
SYMBOL
UNITS
MIN
0.40
0.40
0.40
MAX
MIN
0.50
0.50
0.50
MAX
MIN
0.60
0.70
0.60
MAX
MIN
0.70
0.70
0.70
MAX
Hold Times
K rising edge to address
hold8
K rising edge to control
inputs hold8
K, K# rising edge to data-in
tKHAX
tKHIX
ns
ns
ns
tKHDX
hold8
NOTE:
1. Test conditions as specified with the output loading shown in Figure 5, unless otherwise noted.
t
2. Control input signals may not be operated with pulse widths less than KHKL (MIN).
3. If C and C# are tied HIGH, K and K# become the references for C and C# timing parameters.
t
4. The device will operate at clock frequencies slower than KHKH (MAX). See Micron Technical Note TN-54-02 for more information.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. VDD slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
7. Echo clock is tightly controlled to data valid/data hold. By design, there is a 0.1ns variation from echo clock to data. The data sheet
parameters reflect tester guardbands and test setup variations.
8. This is a syncrhonous device. All addresses, data, and control lines must meet the specified setup and hold times for all latching clock
edges.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
16
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
AC TEST CONDITIONS
Figure 5
Output Load Equivalent
Input pulse levels . . . . . . . . . . . . . . . . . . 0.25V to 1.25V
Input rise and fall times . . . . . . . . . . . . . . . . . . . . 0.7ns
Input timing reference levels . . . . . . . . . . . . . . . . 0.75V
Output reference levels . . . . . . . . . . . . . . . . . . .VDDQ/2
ZQ for 50ꢀ impedance . . . . . . . . . . . . . . . . . . . . . 250ꢀ
Output load . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 5
0.75V
VDDQ/2
VREF
50Ω
Z
= 50Ω
O
SRAM
250Ω
ZQ
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
17
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
Figure 6
READ/WRITE Timing3
READ
WRITE
READ
WRITE
READ
WRITE
NOP
WRITE
NOP
(Note 2)
6
1
2
3
4
5
7
8
10
9
K
t
t
t
t
KHKL
KLKH
KHKH
KHK#H
K#
R#
t
t
KHIX
IVKH
W#
A
(Note 3)
t
A5
A6
A0
A1
t
A2
A3
A4
t
t
AVKH KHAX AVKH KHAX
D
Q
D10
D11
D30
D31
D50
D51
Q01
D60
Q20
D61
t
t
KHDX
t
t
KHDX
DVKH
DVKH
(Note 1)
Q00
Q21
Q40
Q41
t
CHQZ
t
CHQX1
t
t
CHQX
t
CQHQV
CHQX
t
KHCH
t
KLKH
t
t
CHQV
CHQV
C
C#
t
KHKL
t
t
KHKH
KHK#H
t
KHCH
t
CHCQV
CHCQX
t
CQ
t
CHCQV
CHCQX
t
CQ#
DON’T CARE
UNDEFINED
NOTE:
1. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following
A0, i.e., A0 + 1.
2. Outputs are disabled (High-Z) one clock cycle after a NOP.
3. In this example, if address A0 =ꢁA1, then data Q00 = D10, Q01 = D11. Write data is forwarded immediately as read results.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
18
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
IEEE 1149.1 SERIAL BOUNDARY SCAN
(JTAG)
Figure 7
TAP Controller State Diagram
The QDR SRAM incorporates a serial boundary scan
TEST-LOGIC
RESET
1
0
test access port (TAP). This port operates in accor-
dance with IEEE Standard 1149.1-2001. The TAP oper-
ates using JEDEC-standard 1.8V I/O logic levels.
The SRAM contains a TAP controller, instruction
register, boundary scan register, bypass register, and
ID register.
0
1
1
1
RUN-TEST/
IDLE
SELECT
SELECT
IR-SCAN
DR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
Disabling the JTAG Feature
1
1
EXIT1-DR
EXIT1-IR
It is possible to operate the SRAM without using the
JTAG feature. To disable the TAP controller, TCK must
be tied LOW (VSS) to prevent clocking of the device.
TDI and TMS are internally pulled up and may be
unconnected. Alternately, they may be connected to
VDD through a pull-up resistor. TDO should be left
unconnected. Upon power-up, the device will come up
in a reset state, which will not interfere with the opera-
tion of the device.
0
0
PAUSE-DR
1
0
PAUSE-IR
1
0
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
TEST ACCESS PORT (TAP)
Test Clock (TCK)
NOTE:
The 0 or 1 next to each state represents the value of TMS at
the rising edge of TCK.
The test clock is used only with the TAP controller.
All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.
Test Data-In (TDI)
The TDI ball is used to serially input information
into the registers and can be connected to the input of
any of the registers. The register between TDI and TDO
is chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 7. TDI is internally
pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most-signifi-
cant bit (MSB) of any register, as illustrated in Figure 8.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP
controller and is sampled on the rising edge of TCK. It
is allowable to leave this ball unconnected if the TAP is
not used. The ball is pulled up internally, resulting in a
logic HIGH level.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-
out from the registers. The output is active depending
upon the current state of the TAP state machine. (See
Figure 7.) The output changes on the falling edge of
TCK. TDO is connected to the least-significant bit
(LSB) of any register, as depicted in Figure 8.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
19
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
Figure 8
TAP Controller Block Diagram
Bypass Register
To save time when serially shifting data through reg-
isters, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that
can be placed between the TDI and TDO balls. This
allows data to be shifted through the SRAM with mini-
mal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
0
Bypass Register
2
1 0
Selection
Circuitry
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
TDI
TDO
.
.
. 2 1 0
x
.
.
.
.
. 2 1 0
Boundary Scan Register
The boundary scan register is connected to all the
input and bidirectional balls on the SRAM. Several no
connect (NC) balls are also included in the scan regis-
ter to reserve balls. The SRAM has a 109-bit-long regis-
ter.
Boundary Scan Register
TCK
TMS
TAP CONTROLLER
The boundary scan register is loaded with the con-
tents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the
Shift-DR state.
NOTE:
X = 108 for all configurations.
The Boundary Scan Order tables show the order in
which the bits are connected. Each bit corresponds to
one of the balls on the SRAM package. The MSB of the
register is connected to TDI, and the LSB is connected
to TDO.
Performing a TAP RESET
A RESET is performed by forcing TMS HIGH (VDD)
for five rising edges of TCK. This RESET does not affect
the operation of the SRAM and may be performed
while the SRAM is operating.
Identification (ID) Register
At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
The ID register is loaded with a vendor-specific, 32-
bit code during the Capture-DR state when the
IDCODE command is loaded in the instruction regis-
ter. The IDCODE is hardwired into the SRAM and can
be shifted out when the TAP controller is in the Shift-
DR state. The ID register has a vendor code and other
information described in the Identification Register
Definitions table.
TAP REGISTERS
Registers are connected between the TDI and TDO
balls and allow data to be scanned into and out of the
SRAM test circuitry. Only one register can be selected
at a time through the instruction register. Data is seri-
ally loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of
TCK.
TAP INSTRUCTION SET
Overview
Eight different instructions are possible with the
three-bit instruction register. All combinations are
listed in the Instruction Codes table. Three of these
instructions are listed as RESERVED and should not be
used. The other five instructions are described below
in detail.
The TAP controller used in this SRAM is fully com-
pliant to the 1149.1 convention.
Instructions are loaded into the TAP controller dur-
ing the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state,
instructions are shifted through the instruction regis-
Instruction Register
Three-bit instructions can be serially loaded into
the instruction register. This register is loaded when it
is placed between the TDI and TDO balls as shown in
Figure 8. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state, as described in the previous section.
When the TAP controller is in the Capture-IR state,
the two LSBs are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test
data path.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
20
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
ter, and through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller
needs to be moved into the Update-IR state.
The user must be aware that the TAP controller
clock can only operate at a frequency up to 10 MHz,
while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in
the clock frequencies, it is possible that during the
Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not
harm the device, but there is no guarantee as to the
value that will be captured. Repeatable results may not
be possible.
EXTEST
The EXTEST instruction allows circuitry external to
the component package to be tested. Boundary scan
register cells at output balls are used to apply test vec-
tors, while those at input balls capture test results. Typ-
ically, the first test vector to be applied using the
EXTEST instruction will be shifted into the boundary
scan register using the PRELOAD instruction. Thus,
during the Update-IR state of EXTEST, the output drive
is turned on and the PRELOAD data is driven onto the
output pins.
To guarantee that the boundary scan register will
capture the correct value of a signal, the SRAM signal
must be stabilized long enough to meet the TAP con-
t
troller’s capture setup plus hold time (tCS plus CH).
The SRAM clock input might not be captured correctly
if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and
simply ignore the value of the C and C#, and K and K#,
captured in the boundary scan register.
Once the data is captured, it is possible to shift out
the data by putting the TAP into the Shift-DR state.
This places the boundary scan register between the
TDI and TDO balls.
IDCODE
The IDCODE instruction causes a vendor-specific,
32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI
and TDO balls and allows the IDCODE to be shifted
out of the device when the TAP controller enters the
Shift-DR state. The IDCODE instruction is loaded into
the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
BYPASS
SAMPLE Z
When the BYPASS instruction is loaded in the
instruction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between the TDI
and TDO balls. The advantage of the BYPASS instruc-
tion is that it shortens the boundary scan path when
multiple devices are connected together on a board.
The SAMPLE Z instruction causes the boundary
scan register to be connected between the TDI and
TDO balls when the TAP controller is in a Shift-DR
state. It also places all SRAM outputs into a High-Z
state.
SAMPLE/PRELOAD
RESERVED
These instructions are not implemented but are
reserved for future use. Do not use these instructions.
When the SAMPLE/PRELOAD instruction is loaded
into the instruction register and the TAP controller is in
the Capture-DR state, a snapshot of data on the inputs
and bidirectional balls is captured in the boundary
scan register.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
21
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
Figure 9
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
t
THTH
THTL
TLTH
t
t
MVTH
DVTH
THMX
Test Mode Select
(TMS)
t
THDX
Test Data-In
(TDI)
t
TLOV
t
TLOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP DC ELECTRICAL CHARACTERISTICS1,2
0ºC
?
TA
?
+70ºC; +1.7V ? VDD ? +1.9V
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Clock
tTHTH
fTF
tTHTL
tTLTH
100
ns
MHz
ns
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
10
40
40
ns
Output Times
tTLOX
tTLOV
tDVTH
tTHDX
0
ns
ns
ns
ns
TCK LOW to TDO unknown
20
TCK LOW to TDO valid
TDI valid to TCK HIGH
TCK HIGH to TDI invalid
10
10
Setup Times
tMVTH
tCS
TMS setup
10
10
ns
ns
Capture setup
Hold Times
tTHMX
tCH
TMS hold
10
10
ns
ns
Capture hold
NOTE:
t
t
1. CS and CH refer to the setup and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in Figure 10.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
22
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
TAP AC TEST CONDITIONS
Figure 10
TAP AC Output Load Equivalent
Input pulse levels . . . . . . . . . . . . . . . . . . . . . VSS to 1.8V
Input rise and fall times . . . . . . . . . . . . . . . . . . . . . .1ns
Input timing reference levels . . . . . . . . . . . . . . . . . 0.9V
Output reference levels . . . . . . . . . . . . . . . . . . . . . . 0.9V
Test load termination supply voltage. . . . . . . . . . 0.9V
0.9V
50Ω
TDO
ZO= 50Ω
20pF
TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
0ºC
?
TA
?
+70ºC; +1.7V ? VDD ? +1.9V unless otherwise noted
DESCRIPTION
CONDITIONS
SYMBOL
VIH
MIN
1.3
MAX
VDD + 0.3
0.5
UNITS NOTES
Input High (Logic 1) Voltage1,2
Input Low (Logic 0) Voltage1,2
Input Leakage Current
V
V
1, 2
1, 2
VIL
-0.3
0V ? VIN ? VDD
ILI
-5.0
-5.0
5.0
5.0
µA
µA
Output Leakage Current
Output(s) disabled,
ILO
0V ? VIN ? VDDQ (DQx)
Output Low Voltage1
Output Low Voltage1
Output High Voltage1
Output High Voltage1
NOTE:
IOLC = 100µA
VOL1
VOL2
VOH1
VOH1
0.2
0.4
V
V
V
V
1
1
1
1
IOLT = 2mA
IOHC = -100µA
IOHT = -2mA
1.6
1.4
1. 1All voltages referenced to Vss (GND).
t
2. Overshoot:
VIH(AC) ? VDD + 0.7V for t ? KHKH/2
t
Undershoot: VIL(AC)ꢁO -0.5V for t ? KHKH/2
Power-up: VIH ? VDDQ + 0.3V and VDD ? +1.7V and VDDQ ? 1.4V for t ? 200ms
During normal operation, VDDQ must not exceed VDD. Control input signals (R#, W#, etc.) may not have pulse widths less than
t
t
KHKL (MIN) or operate at frequencies exceeding KF (MAX).
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
23
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
IDENTIFICATION REGISTER DEFINITIONS
INSTRUCTION FIELD
ALL DEVICES
DESCRIPTION
REVISION NUMBER (31:28)
DEVICE ID (28:12)
000
Version number.
00def0Wx0t0q0b0s0 def = 001 for 36Mb density
wx = 11 for x36, 10 for x18, 00 for x9, and 01 for x8
t = 1 for DLL version, 0 for non-DLL version
q = 1 for QDR, 0 for DDR
b = 1 for four-word burst, 0 for two-word burst
s = 1 for separate I/O, 0 for common I/O
00000101100
1
MICRON JEDEC ID CODE
(11:1)
Allows unique identification of SRAM vendor.
ID Register Presence
Indicator (0)
Indicates the presence of an ID register.
SCAN REGISTER SIZES
REGISTER NAME
BIT SIZE (x18)
3
1
Instruction
Bypass
32
109
ID
Boundary Scan
INSTRUCTION CODES
INSTRUCTION
CODE
DESCRIPTION
EXTEST1, 2
000
Captures I/O ring contents. Places the boundary scan register between
TDI and TDO.
001
010
IDCODE
Loads the ID register with the vendor ID code and places the register
between TDI and TDO. This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between
TDI and TDO.
101
110
111
RESERVED
RESERVED
BYPASS
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does
not affect SRAM operations.
NOTE:
1. Data in output register is not guaranteed if EXTEST instruction is loaded.
2. After performing EXTEST, power-up conditions are required in order to return part to normal operation.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
24
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
BOUNDARY SCAN (EXIT) ORDER
BIT#
FBGA BALL
BIT#
FBGA BALL
BIT#
FBGA BALL
1
6R
6P
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
10D
9E
73
74
2C
3E
2
3
6N
10C
11D
9C
75
2D
2E
4
7P
76
5
7N
77
1E
6
7R
9D
11B
11C
9B
78
2F
7
8R
79
3F
8
8P
80
1G
1F
9
9R
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11P
10P
10N
9P
10B
11A
10A
9A
8B
82
3G
2G
1H
1J
83
84
85
10M
11N
9M
9N
86
2J
7C
87
3K
3J
6C
88
8A
7A
7B
89
2K
1K
2L
11L
11M
9L
90
91
6B
92
3L
10L
11K
10K
9J
6A
5B
93
1M
1L
94
5A
4A
5C
95
3N
3M
1N
2M
3P
96
9K
97
10J
11J
11H
10G
9G
4B
98
3A
2A
1A
2B
99
100
101
102
103
104
105
106
107
108
109
2N
2P
1P
11F
11G
9F
3B
3R
1C
4R
1B
4P
10F
11E
10E
3D
3C
5P
5N
5R
1D
INTERNAL
NOTE:
For NC balls in the range of 1B-1P, 2B-2P, 3B-3P, 9B-9P, 10B-10P, and 11B-11P, a logic zero will be read from the chain. All other
NC balls will appear in the scan chain as the logic level present on the ball site.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
25
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
Figure 11
165-Ball FBGA
0.850 0.075
SEATING PLANE
C
0.12 C
10.00
1.00
TYP
BALL A11
165X 0.45
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE-
BALL A1
1.20 MAX
PIN A1 ID
PIN A1 ID
REFLOW DIAMETER IS Ø 0.40
1.00
TYP
14.00
17.00 0.10
7.00 0.05
8.50 0.10
MOLD COMPOUND: EPOXY NOVOLAC
7.50 0.05
5.00 0.05
SUBSTRATE: PLASTIC LAMINATE
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 36% Pb, 2%Ag
15.00 0.10
SOLDER BALL PAD: Ø .33mm
NOTE:
1. All dimensions are in millimeters.
DATA SHEET DESIGNATION
Advance: This data sheet contains initial descriptions of products still under development.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron and the M logo are registered trademarks and SyncBurst and the Micron logo are trademarks of Micron Technology, Inc.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, Micron Technology,
Inc., NEC, and Samsung.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
©2002, Micron Technology Inc.
26
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, QDRIIb2 SRAM
REVISION HISTORY
•
Rev. A, Pub. 9/02..........................................................................................................................................................9/02
New ADVANCE data sheet
•
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
27
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