MT58L256L32P [MICRON]
8Mb: 512K x 18, 256K x 32/36 PIPELINED, SCD SYNCBURST SRAM; 8MB ： 512K ×18 ， 256K X 32/36流水线， SCD SyncBurst SRAM
| 型号： | MT58L256L32P |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | 8Mb: 512K x 18, 256K x 32/36 PIPELINED, SCD SYNCBURST SRAM |
| 文件： | 总27页 (文件大小：391K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
8Mb SYNCBURST™
SRAM
MT58L512L18P, MT58L256L32P, MT58L256L36P;
MT58L512V18P, MT58L256V32P, MT58L256V36P
3.3V VDD, 3.3V or 2.5V I/O, Pipelined, Single-Cycle
Deselect
FEATURES
1
100-Pin TQFP
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (VDD)
• Separate +3.3V or +2.5V isolated output buffer
supply (VDDQ)
• SNOOZE MODE for reduced-power standby
• Single-cycle deselect (Pentium® BSRAM-compatible)
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL
WRITE
• Three chip enables for simple depth expansion
and address pipelining
• Clock-controlled and registered addresses, data
I/Os and control signals
165-Pin FBGA
• Internally self-timed WRITE cycle
• Burst control (interleaved or linear burst)
• Automatic power-down for portable applications
• 100-pin TQFP package
• 165-pin FBGA package
• Low capacitive bus loading
• x18, x32, and x36 versions available
OPTIONS
MARKING
• Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
3.3V I/O
-6
-7.5
-10
NOTE:1. JEDEC-standard MS-026 BHA (LQFP).
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
**Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
512K x 18
256K x 32
256K x 36
MT58L512L18P
MT58L256L32P
MT58L256L36P
2.5V I/O
512K x 18
256K x 32
256K x 36
MT58L512V18P
MT58L256V32P
MT58L256V36P
GENERAL DESCRIPTION
The Micron® SyncBurst™ SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
• Packages
100-pin TQFP (2-chip enable)
100-pin TQFP (3-chip enable)
165-pin, 13mm x 15mm FBGA
• Operating Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)**
T
S
F*
Micron’s 8Mb SyncBurst SRAMs integrate a 512K x
18, 256K x 32, or 256K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single-clock in-
put (CLK). The synchronous inputs include all ad-
dresses, all data inputs, active LOW chip enable (CE#),
two additional chip enables for easy depth expansion
(CE2, CE2#), burst control inputs (ADSC#, ADSP#,
ADV#), byte write enables (BWx#) and global write
None
IT
Part Number Example:
MT58L512L18PT-6
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
FUNCTIONAL BLOCK DIAGRAM
512K X 18
19
17
19
19
2
ADDRESS
REGISTER
SA0, SA1, SAs
MODE
SA0-SA1
Q1
SA1'
ADV#
CLK
BINARY
COUNTER AND
LOGIC
SA0'
CLR
Q0
ADSC#
ADSP#
BYTE “b”
WRITE DRIVER
BYTE “b”
WRITE REGISTER
9
9
OUTPUT
BUFFERS
BWb#
512K x 9 x 2
MEMORY
ARRAY
DQs
DQPa
DQPb
OUTPUT
REGISTERS
SENSE
AMPS
18
18
18
18
BYTE “a”
WRITE DRIVER
E
BYTE “a”
WRITE REGISTER
BWa#
BWE#
INPUT
REGISTERS
GW#
18
ENABLE
REGISTER
CE#
CE2
PIPELINED
ENABLE
CE2#
OE#
2
FUNCTIONAL BLOCK DIAGRAM
256K X 32/36
18
16
18
18
ADDRESS
REGISTER
SA0, SA1, SAs
MODE
SA0-SA1
SA1'
SA0'
Q1
BINARY
COUNTER
ADV#
CLK
CLR
Q0
ADSC#
ADSP#
BYTE “d”
WRITE REGISTER
9
9
BWd#
BWc#
256K x 8 x 4
(x32)
BYTE “c”
WRITE DRIVER
BYTE “c”
WRITE REGISTER
OUTPUT
BUFFERS
OUTPUT
REGISTERS
DQs
256K x 9 x 4
(x36)
SENSE
AMPS
36
36
36
36
DQPa
DQPb
DQPc
DQPd
E
BYTE “b”
WRITE DRIVER
MEMORY
ARRAY
BYTE “b”
WRITE REGISTER
9
9
BWb#
BYTE “a”
WRITE DRIVER
BYTE “a”
WRITE REGISTER
BWa#
BWE#
INPUT
REGISTERS
36
GW#
CE#
CE2
ENABLE
REGISTER
PIPELINED
ENABLE
CE2#
OE#
4
NOTE: Functional Block Diagrams illustrate simplified device operation. See Truth Table, Pin Descriptions, and timing diagrams
for detailed information.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
2
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
(GW#). Note that CE2# is not available on the
T Version.
DQc pins and DQPc; BWd# controls DQd pins and
DQPd. GW# LOW causes all bytes to be written. Parity
bits are only available on the x18 and x36 versions.
This device incorporates a single-cycle deselect fea-
ture during READ cycles. If the device is immediately
deselected after a READ cycle, the output bus goes to a
High-Z state tKQHZ nanoseconds after the rising edge
of clock.
Micron’s 8Mb SyncBurst SRAMs operate from a
+3.3V VDD power supply, and all inputs and outputs are
TTL-compatible. Users can choose either a 3.3V or 2.5V
I/O version. The device is ideally suited for Pentium
and PowerPC pipelined systems and systems that ben-
efit from a very wide, high-speed data bus. The device
is also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-
wide applications.
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is also
a burst mode input (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can
be from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
internally generated as controlled by the burst advance
input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins and DQPa; BWb# controls
DQb pins and DQPb. During WRITE cycles on the x32
and x36 devices, BWa# controls DQa pins and DQPa;
BWb# controls DQb pins and DQPb; BWc# controls
PleaserefertoMicron’sWebsite(www.micron.com/
sramds) for the latest data sheet.
TQFP PINOUTS
At the time of the writing of this data sheet, there are
two pinouts in the industry. Micron will support both
pinouts for this part.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
TQFP PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
x18
NC
NC
NC
x32/x36
NF/DQPc*
DQc
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
x18
x32/x36
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x18
NC
NC
NC
x32/x36
NF/DQPa*
DQa
PIN #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
x18
x32/x36
VSS
VSS
VDDQ
VDDQ
DQc
NC
NC
NC
DQd
DQd
NF/DQPd*
MODE
DQa
NC
NC
SA
DQb
DQb
NF/DQPb*
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
VDDQ
VSS
VDDQ
VSS
NC
NC
DQb
DQb
DQc
DQc
DQc
DQc
NC
NC
DQa
DQa
SA
SA
SA
DQa
DQa
VSS
VDDQ
DQa
DQa
ZZ
VDD
NC
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
VDDQ
SA
SA1
SA0
DNU
DNU
VSS
DQb
DQb
DQc
DQc
VDD
VDD
NC
VSS
VDD
VDD
NF
VSS
SA (T Version)
CE2# (S Version)
BWa#
DQb
DQb
DQd
DQd
NF (T Version)
SA (S Version)
DQa
DQa
DQb
DQb
93
94
95
96
97
98
99
100
VDDQ
VSS
44
45
46
47
48
49
50
SA
SA
SA
SA
SA
SA
SA
VDDQ
VSS
BWb#
NC
NC
BWc#
BWd#
DQb
DQb
DQPb
NC
DQd
DQd
DQd
DQd
DQa
DQa
DQPa
NC
DQb
DQb
DQb
DQb
CE2
CE#
SA
SA
*No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
4
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
PIN ASSIGNMENT (TOP VIEW)
100-PIN TQFP, 2-CHIP ENABLE,
T VERSION
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SA
SA
81
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SA
SA
SA
SA
SA
SA
SA
NF
NF
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
V
SS
DD
V
V
DD
SS
V
x18
SA
BWa#
BWb#
NC
DNU
DNU
SA0
SA1
SA
NC
CE2
CE#
SA
SA
SA
SA
SA
100
MODE
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SA
81
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SA
SA
ADV#
ADSP#
ADSC#
OE#
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
SA
SA
SA
SA
SA
SA
NF
NF
BWE#
GW#
CLK
V
SS
DD
V
V
DD
SS
V
x32/x36
SA
BWa#
BWb#
BWc#
BWd#
CE2
DNU
DNU
SA0
SA1
SA
SA
CE#
SA
SA
SA
SA
100
MODE
1
2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
*No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
5
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
PIN ASSIGNMENT (TOP VIEW)
100-PIN TQFP, 3-CHIP ENABLE,
S VERSION
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SA
SA
81
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SA
SA
SA
SA
SA
SA
SA
SA
NF
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
V
SS
DD
V
V
DD
SS
V
x18
CE2#
BWa#
BWb#
NC
DNU
DNU
SA0
SA1
SA
NC
CE2
CE#
SA
SA
SA
SA
SA
100
MODE
1
2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SA
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SA
SA
ADV#
ADSP#
ADSC#
OE#
SA
SA
SA
SA
SA
SA
SA
NF
BWE#
GW#
CLK
V
SS
DD
V
V
DD
SS
V
x32/x36
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
DNU
DNU
SA0
SA1
SA
SA
CE#
SA
SA
SA
SA
100
MODE
1
2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
*No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
6
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS
x18
x32/x36
SYMBOL TYPE
DESCRIPTION
37
36
37
36
SA0
SA1
SA
Input Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK. Two
different pinouts are available for the TQFP package.
32-35, 44-50, 32-35, 44-50,
80-82, 99,
100
81, 82, 99,
100
92 (T Version) 92 (T Version)
43 (S Version) 43 (S Version)
93
94
–
93
94
95
96
BWa#
BWb#
BWc#
BWd#
Input Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only available
on the x18 and x36 versions.
–
87
88
89
87
88
89
BWE#
GW#
CLK
Input Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
Input Clock: This signal registers the address, data, chip enable, byte write
enables and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
98
98
CE#
CE2#
ZZ
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
92
92
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded. CE2# is only available on the S version.
(S Version)
(S Version)
64
97
64
97
Input Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
CE2
Input Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
86
83
86
83
OE#
Input Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
ADV#
Input Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
external address is loaded. A HIGH on this pin effectively causes wait
states to be generated (no address advance). To ensure use of correct
address during a WRITE cycle, ADV# must be HIGH at the rising edge
of the first clock after an ADSP# cycle is initiated.
(continued on next page)
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
7
©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS (continued)
x18
x32/x36
SYMBOL TYPE
DESCRIPTION
84
84
ADSP#
Input Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address, independent
of the byte write enables and ADSC#, but dependent upon CE#, CE2
and CE2#. ADSP# is ignored if CE# is HIGH. Power-down state is
entered if CE2 is LOW or CE2# is HIGH.
85
85
ADSC#
MODE
Input Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
31
31
Input Mode: This input selects the burst sequence. A LOW on this pin
selects “linear burst.” NC or HIGH on this pin selects “interleaved
burst.” Do not alter input state while device is operating.
(a) 58, 59,
62, 63, 68, 69, 56-59, 62, 63
72, 73
(b) 8, 9, 12,
13, 18, 19, 22, 72-75, 78, 79
(a) 52, 53,
DQa
DQb
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte “b”
Output is DQb pins. For the x32 and x36 versions, Byte “a” is DQa pins;
Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins.
Input data must meet setup and hold times around the rising edge
of CLK.
(b) 68, 69
23
(c) 2, 3, 6-9,
12, 13
(d) 18, 19,
22-25, 28, 29
DQc
DQd
74
24
–
51
80
1
NF/DQPa
NF/DQPb
NF/DQPc
NF/DQPd
NF / No Function/Parity Data I/Os: On the x32 version, these pins are No
I/O
Function (NF). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
–
30
14, 15, 41, 65, 14, 15, 41, 65,
91 91
V
DD
Supply Power Supply: See DC Electrical Characteristics and Operating
Conditions for range.
4, 11, 20, 27, 4, 11, 20, 27,
54, 61, 70, 77 54, 61, 70, 77
V
DDQ
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Operating Conditions for range.
5, 10, 17, 21, 5, 10, 17, 21,
26, 40, 55, 60, 26, 40, 55, 60,
67, 71, 76, 90 67, 71, 76, 90
V
SS
Supply Ground: GND.
38, 39
38, 39
DNU
NC
–
–
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1-3, 6, 7,
16, 25, 28-30,
51-53, 56, 57,
66, 75, 78, 79,
95, 96
16, 66
No Connect: These signals are not internally connected and may be
connected to ground to improve package heat dissipation.
42
42
NF
–
No Function: These pins are internally connected to the die and
have the capacitance of an input pin. It is allowable to leave these
pins unconnected or driven by signals. On the S version, pin 42 is
reserved as an address upgrade pin for the 18Mb SyncBurst SRAM.
43 (T Version) 43 (T Version)
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
8
©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
PIN LAYOUT (TOP VIEW)
165-PIN FBGA
x18
x32/x36
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
A
B
C
D
E
A
B
C
D
E
A
B
C
D
E
NC
NC
NC
NC
NC
NC
NC
SA
SA
CE# BWb#
NC
CE2# BWE# ADSC# ADV#
SA
SA
NC
NC
NC
SA
SA
CE# BWc# BWb# CE2# BWE# ADSC# ADV#
SA
NC
NC
CE2
NC
BWa# CLK
GW# OE# (G#) ADSP# SA
CE2 BWd# BWa# CLK
GW# OE# (G#) ADSP# SA
NC
V
DD
DD
DD
DD
DD
Q
V
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
V
V
V
V
V
DD
DD
DD
DD
DD
Q
Q
Q
Q
Q
NC NF/DQPa
NF/DQPc NC
V
V
V
V
V
DD
DD
DD
DD
DD
Q
Q
Q
Q
Q
V
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
SS
V
V
V
V
V
DD
DD
DD
DD
DD
Q
Q
Q
Q
Q
NC NF/DQPb
DQb DQb
DQb DQb
DQb DQb
DQb DQb
DQb
DQb
DQb
DQb
V
V
V
V
Q
Q
Q
Q
V
V
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
V
V
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
DD
DD
NC
NC
DQa
DQa
DQa
DQa
ZZ
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
F
F
F
F
NC
G
H
J
G
H
J
G
H
J
G
H
J
NC
V
DD
DQb
DQb
DQb
DQb
V
SS
NC
NC
NC
VDD
VSS
NC
NC
NC
ZZ
NC
NC
NC
NC
V
DD
DD
DD
DD
DD
Q
V
DD
DD
DD
DD
DD
Q
DQa
DQa
DQa
DQa
NC
NC
DQd DQd
DQd DQd
DQd DQd
DQd DQd
NF/DQPd NC
V
DD
DD
DD
DD
DD
Q
V
DD
DD
DD
DD
DD
Q
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
K
L
K
L
K
L
K
L
V
V
V
V
Q
Q
Q
Q
V
V
V
V
Q
Q
Q
Q
NC
V
V
V
V
Q
Q
Q
Q
V
V
V
V
Q
Q
Q
Q
NC
M
N
P
M
N
P
M
N
P
M
N
P
NC
NF/DQPb NC
V
SS
NC
NC
SA1
SA0
V
SS
NC
VSS
NC
NC
SA1
SA0
VSS
NC NF/DQPa
NC
NC
SA
SA
SA
SA
DNU
DNU
DNU
DNU
SA
SA
SA
SA
SA
SA
NC
NC
SA
SA
SA
SA
DNU
DNU
DNU
DNU
SA
SA
SA
SA
SA
SA
SA
SA
R
R
R
R
MODE NC
(LBO#)
SA
SA
MODE NC
(LBO#)
TOP VIEW
TOP VIEW
*No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
9
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
FBGA PIN DESCRIPTIONS
x18
x32/x36
SYMBOL TYPE
DESCRIPTION
6R
6P
6R
6P
SA0
SA1
SA
Input Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
2A, 2B, 3P,
3R, 4P, 4R,
2A, 2B, 3P,
3R, 4P, 4R,
8P, 8R, 9P, 9R, 8P, 8R, 9P,
10A, 10B, 10P, 9R, 10A, 10B,
10R, 11A, 11P, 10P, 10R, 11P,
11R
11R
5B
4A
–
5B
5A
4A
4B
BWa#
BWb#
BWc#
BWd#
Input Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb.
For the x32 and x36 versions, BWa# controls DQa’s and DQPa; BWb#
controls DQb’s and DQPb; BWc# controls DQc’s and DQPc; BWd#
controls DQd’s and DQPd. Parity is only available on the x18 and x36
versions.
–
7A
7B
6B
7A
7B
6B
BWE#
GW#
CLK
Input Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
Input Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
3A
6A
3A
6A
CE#
CE2#
ZZ
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
Input Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
11H
11H
Input Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
3B
8B
3B
8B
CE2
Input Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
OE#(G#)
Input Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
(continued on next page)
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
10
©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
FBGA PIN DESCRIPTIONS (continued)
x18
x32/x36
SYMBOL TYPE
DESCRIPTION
9A
9A
ADV#
ADSP#
ADSC#
Input Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on ADV# effectively causes
wait states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
9B
9B
Input Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
8A
1R
8A
1R
Input Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
MODE
(LB0#)
Input Mode: This input selects the burst sequence. A LOW on this input
selects “linear burst.” NC or HIGH on this input selects “interleaved
burst.” Do not alter input state while device is operating.
(a) 10J, 10K, (a) 10J, 10K,
10L, 10M, 11D, 10L, 10M, 11J,
11E, 11F, 11G 11K, 11L, 11M
DQa
DQb
DQc
DQd
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated DQa’s;
Output Byte “b” is associated with DQb’s. For the x32 and x36 versions,
Byte “a” is associated with DQa’s; Byte “b” is associated with DQb's;
Byte “c” is associated with DQc’s; Byte “d” is associated with DQd’s.
Input data must meet setup and hold times around the rising edge
of CLK.
(b) 1J, 1K,
(b) 10D, 10E,
1L, 1M, 2D, 10F, 10G, 11D,
2E, 2F, 2G 11E, 11F, 11G
(c) 1D, 1E,
1F, 1G, 2D,
2E, 2F, 2G
(d) 1J, 1K, 1L,
1M, 2J, 2K,
2L, 2M
11C
1N
–
11N
11C
1C
NF/DQPa
NF/DQPb
NF/DQPc
NF/DQPd
NF/
I/O
No Function/Parity Data I/Os: On the x32 version, these are No
Function (NF). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
–
1N
1H, 4D, 4E, 4F, 1H, 4D, 4E, 4F,
V
DD
Supply Power Supply: See DC Electrical Characteristics and Operating
Conditions for range.
4G, 4H, 4J,
4K, 4L, 4M,
8D, 8E, 8F,
8G, 8H, 8J,
8K, 8L, 8M
4G, 4H, 4J,
4K, 4L, 4M,
8D, 8E, 8F,
8G, 8H, 8J,
8K, 8L, 8M
(continued on next page)
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
11
©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
FBGA PIN DESCRIPTIONS (continued)
x18
x32/x36
SYMBOL TYPE
DESCRIPTION
3C, 3D, 3E,
3F, 3G, 3J,
3K, 3L, 3M,
3N, 9C, 9D,
9E, 9F, 9G,
9J, 9K, 9L,
9M, 9N
3C, 3D, 3E,
3F, 3G, 3J,
3K, 3L, 3M,
3N, 9C, 9D,
9E, 9F, 9G,
9J, 9K, 9L,
9M, 9N
V
DDQ
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Operating Conditions for range.
2H, 4C, 4N, 5C, 2H, 4C, 4N, 5C,
V
SS
Supply Ground: GND.
5D, 5E 5F,
5G, 5H, 5J,
5K, 5L, 5M,
5D, 5E 5F,
5G, 5H, 5J,
5K, 5L, 5M,
6C, 6D, 6E, 6F, 6C, 6D, 6E, 6F,
6G, 6H, 6J,
6K, 6L, 6M,
7C, 7D, 7E,
7F, 7G, 7H,
7J, 7K, 7L,
6G, 6H, 6J,
6K, 6L, 6M,
7C, 7D, 7E,
7F, 7G, 7H,
7J, 7K, 7L,
7M, 7N, 8C, 8N 7M, 7N, 8C, 8N
5P, 5R, 7P, 7R 5P, 5R, 7P, 7R
DNU
NC
–
–
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1A, 1B, 1C,
1D, 1E, 1F,
1G, 1P, 2C,
2J, 2K, 2L,
2M, 2N, 2P,
2R, 3H, 4B,
5A, 5N, 6N,
9H, 10C, 10D,
10E, 10F,
1A, 1B, 1P,
2C, 2N,
2P, 2R, 3H,
5N, 6N, 9H,
10C, 10H,
10N, 11A,
11B
No Connect: These signals are not internally connected and
may be connected to ground to improve package heat
dissipation. Pin 6N reserved for address pin expansion; 18Mb.
10G, 10H,
10N, 11B,
11J, 11K,
11L, 11M,
11N
NF
—
No Function: These pins are internally connected to the die and
have the capacitance of an input pin. It is allowable to leave
these pins unconnected or driven by signals.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
12
©2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X00
X...X11
X...X10
X...X10
X...X11
X...X00
X...X01
X...X11
X...X10
X...X01
X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X10
X...X11
X...X00
X...X10
X...X11
X...X00
X...X01
X...X11
X...X00
X...X01
X...X10
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18)
FUNCTION
READ
GW#
H
BWE#
BWa#
BWb#
H
L
X
H
L
X
H
H
L
READ
H
WRITE Byte “a”
WRITE Byte “b”
WRITE All Bytes
WRITE All Bytes
H
L
H
L
H
L
H
L
L
L
X
X
X
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36)
FUNCTION
READ
GW#
BWE#
BWa#
BWb#
BWc# BWd#
H
H
H
H
L
H
L
X
H
L
X
H
H
L
X
H
H
L
X
H
H
L
READ
WRITE Byte “a”
WRITE All Bytes
WRITE All Bytes
L
L
L
X
X
X
X
X
NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
13
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
TRUTH TABLE
OPERATION
ADDRESS CE# CE2# CE2 ZZ ADSP# ADSC# ADV# WRITE# OE#
USED
CLK
DQ
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
SNOOZE MODE, Power-Down
READ Cycle, Begin Burst
None
H
X
X
H
X
H
X
L
X
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H
L-H
L-H
L-H
L-H
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
None
L
L
L
None
L
X
L
L
None
L
H
H
X
L
None
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
None
X
L
X
X
X
L
External
External
External
External
External
Next
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
READ Cycle, Begin Burst
L
L
L
H
X
L
High-Z
D
WRITE Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
READ Cycle, Begin Burst
L
L
L
H
H
H
H
H
H
L
Q
READ Cycle, Begin Burst
L
L
L
H
L
High-Z
Q
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z
Q
H
X
X
High-Z
D
L
D
NOTE: 1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or
GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.
3. BWa# enables WRITEs to DQa’s and DQPa. BWb# enables WRITEs to DQb’s and DQPb. BWc# enables WRITEs to DQc’s
and DQPc. BWd# enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions.
DQPc and DQPd are only available on the x36 version.
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held
HIGH throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
14
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
**Maximum junction temperature depends upon
package type, cycle time, loading, ambient tempera-
ture and airflow. See Micron Technical Note TN-05-
14 for more information.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply
Relative to VSS .............................. -0.5V to +4.6V
Voltage on VDDQ Supply
Relative to VSS .............................. -0.5V to +4.6V
VIN (DQx) .................................. -0.5V to VDDQ + 0.5V
VIN (inputs)................................... -0.5V to VDD + 0.5V
Storage Temperature (plastic)............-55°C to +150°C
Storage Temperature (FBGA) .............-55°C to +125°C
Junction Temperature**................................... +150°C
Short Circuit Output Current ..........................100mA
3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C ≤ TA ≤ +70°C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL MIN
MAX
VDD + 0.3
0.8
UNITS
V
NOTES
1, 2
1, 2
3
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
VIH
VIL
ILI
2.0
-0.3
-1.0
-1.0
V
0V ≤ VIN ≤ VDD
1.0
µA
µA
Output(s) disabled,
ILO
1.0
0V ≤ VIN ≤ VDD
Output High Voltage
Output Low Voltage
Supply Voltage
IOH = -4.0mA
VOH
VOL
2.4
–
–
V
V
V
V
1, 4
1, 4
1
IOL = 8.0mA
0.4
3.6
3.6
VDD
3.135
3.135
Isolated Output Buffer Supply
VDDQ
1, 5
NOTE: 1. All voltages referenced to VSS (GND).
t
2. Overshoot:
VIH ≤ +4.6V for t ≤ KC/2 for I ≤ 20mA
t
Undershoot: VIL ≥ -0.7V for t ≤ KC/2 for I ≤ 20mA
Power-up: VIH ≤ +3.6V and VDD ≤ 3.135V for t ≤ 200ms
3. MODE has an internal pull-up, and input leakage = 10µA.
4. The load used for VOH, VOL testing is shown in Figure 2 for 3.3V I/O. AC load current is higher than the shown DC
values. AC I/O curves are available upon request.
5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
15
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C ≤ TA ≤ 70°C; VDD = +3.3V +0.3V/-0.165V; VDDQ = +2.5V +0.4V/-0.125V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage
CONDITIONS
Data bus (DQx)
Inputs
SYMBOL MIN
MAX
UNITS
NOTES
1, 2
1, 2
VIHQ
VIH
1.7
1.7
VDDQ + 0.3
VDD + 0.3
V
V
Input Low (Logic 0) Voltage
Input Leakage Current
VIL
ILI
-0.3
-1.0
-1.0
0.7
1.0
1.0
V
1, 2
3
0V ≤ VIN ≤ VDD
µA
µA
Output Leakage Current
Output(s) disabled,
ILO
0V ≤ VIN ≤ VDDQ (DQx)
Output High Voltage
Output Low Voltage
IOH = -2.0mA
IOH = -1.0mA
VOH
VOH
1.7
2.0
–
–
V
V
1, 4
1, 4
IOL = 2.0mA
IOL = 1.0mA
VOL
VOL
–
–
0.7
0.4
V
V
1, 4
1, 4
Supply Voltage
VDD
3.135
2.375
3.6
2.9
V
V
1
1
Isolated Output Buffer Supply
VDDQ
TQFP CAPACITANCE
DESCRIPTION
CONDITIONS
TA = 25°C; f = 1 MHz;
VDD = 3.3V
SYMBOL
TYP
3
MAX
4
UNITS
pF
NOTES
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
CI
CO
CA
CCK
5
5
5
5
4
5
pF
3
3.5
3.5
pF
3
pF
FBGA CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL TYP
MAX
3.5
5
UNITS NOTES
Address/Control Input Capacitance
Output Capacitance (Q)
Clock Capacitance
CI
2.5
4
pF
pF
pF
5, 6
5, 6
5, 6
TA = 25°C; f = 1 MHz
CO
CCK
2.5
3.5
NOTE: 1. All voltages referenced to VSS (GND).
t
2. Overshoot:
VIH ≤ +4.6V for t ≤ KC/2 for I ≤ 20mA
t
Undershoot: VIL ≥ -0.7V for t ≤ KC/2 for I ≤ 20mA
Power-up: VIH ≤ +3.6V and VDD ≤ 3.135V for t ≤ 200ms
3. MODE has an internal pull-up, and input leakage = 10µA.
4. The load used for VOH, VOL testing is shown in Figure 4 for 2.5V I/O. AC load current is higher than the shown DC
values. AC I/O curves are available upon request.
5. This parameter is sampled.
6. Preliminary package data.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
16
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
TQFP THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYMBOL TYP
UNITS NOTES
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
1-layer
θJA
40
°C/W
1
Thermal Resistance
(Junction to Top of Case)
θJC
8
°C/W
1
FBGA THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
UNITS NOTES
Junction to Ambient
(Airflow of 1m/s)
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
θJA
40
°C/W
1, 2
Junction to Case (Top)
θJC
θJB
9
°C/W
°C/W
1, 2
1, 2
Junction to Pins
(Bottom)
17
NOTE: 1. This parameter is sampled.
2. Preliminary package data.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
17
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(0°C ≤ TA ≤ +70°C; VDD = +3.3V +0.3V/-0.165V; VDDQ = +3.3V +0.3V/-0.165V for 3.3V I/O and
+2.5V +0.4V/-0.125V for 2.5V I/O)
MAX
DESCRIPTION
CONDITIONS
SYMBOL TYP
-6
-7.5
-10
UNITS NOTES
Power Supply
Current: Operating
Device selected; All inputs ≤ VIL
or ≥ VIH; Cycle time ≥ KC (MIN);
t
I
DD
225
55
475
375
300
mA
mA
1, 2, 3
1, 2, 3
V
DD = MAX; Outputs open
Power Supply
Current: Idle
Device selected; VDD = MAX;
ADSC#, ADSP#, GW#, BWx#,
I
DD
1
110
90
85
ADV# ≥ VIH; All inputs ≤ VSS + 0.2 or
t
≥ VDD - 0.2; Cycle time ≥ KC (MIN)
CMOS Standby
TTL Standby
Device deselected; VDD = MAX;
All inputs ≤ VSS + 0.2 or ≥ VDD - 0.2;
All inputs static; CLK frequency = 0
I
SB
SB
SB
2
0.4
8
10
25
10
25
90
10
25
85
mA
mA
mA
2, 3
2, 3
2, 3
Device deselected; VDD = MAX;
All inputs ≤ VIL or ≥ VIH
;
I
3
All inputs static; CLK frequency = 0
Clock Running
Device deselected; VDD = MAX;
ADSC#, ADSP#, GW#, BWx#,
I
4
55
110
ADV# ≥ VIH; All inputs ≤ VSS + 0.2 or
t
≥ VDD - 0.2; Cycle time ≥ KC (MIN)
NOTE: 1. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and
greater output loading.
2. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means
device is active (not in power-down mode).
3. Typical values are measured at 3.3V, 25°C and 10ns cycle time.
4. This parameter is sampled.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
18
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1)(0°C ≤ TA ≤ +70°C; VDD = +3.3V +0.3V/-0.165V)
6
-7.5
-10
DESCRIPTION
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX UNITS NOTES
Clock
Clock cycle time
Clock frequency
Clock HIGH time
t
KC
KF
6.0
7.5
10
ns
f
166
133
100
5.0
MHz
ns
ns
t
KH
2.3
2.3
2.5
2.5
3.0
3.0
2
2
t
Clock LOW time
KL
Output Times
t
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
KQ
3.5
4.0
ns
ns
ns
ns
ns
ns
ns
t
KQX
KQLZ
KQHZ
OEQ
OELZ
OEHZ
1.5
0
1.5
0
1.5
1.5
3
t
3, 4, 5, 6
3, 4, 5, 6
7
t
3.5
3.5
4.2
4.2
5.0
5.0
t
t
0
0
0
3, 4, 5, 6
3, 4, 5, 6
t
3.5
4.2
4.5
t
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
AS
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
ns
ns
ns
ns
8, 9
8, 9
8, 9
8, 9
t
ADSS
t
AAS
WS
t
Write signals
(BWa#-BWd#, BWE#, GW#)
t
Data-in
Chip enables (CE#, CE2#, CE2)
Hold Times
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
DS
1.5
1.5
1.5
1.5
2.0
2.0
ns
ns
8, 9
8, 9
t
CES
t
AH
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
8, 9
8, 9
8, 9
8, 9
t
ADSH
t
AAH
t
Write signals
WH
(BWa#-BWd#, BWE#, GW#)
t
Data-in
Chip enables (CE#, CE2#, CE2)
DH
0.5
0.5
0.5
.5
0.5
0.5
ns
ns
8, 9
8, 9
t
CEH
NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V +0.3V/-0.165V) and
Figure 3 for 2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V) unless otherwise noted.
2. Measured as HIGH above VIH and LOW below VIL.
3. This parameter is measured with output load as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
4. This parameter is sampled.
5. Transition is measured 500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough
discussion on these parameters.
7. OE# is a “Don’t Care” when a byte write enable is sampled LOW.
8. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold
times. A READ cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the required
setup and hold times.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold
times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
19
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
3.3V I/O AC TEST CONDITIONS
2.5V I/O AC TEST CONDITIONS
Input pulse levels.................. VIH = (VDD/2.2) + 1.5V
Input pulse levels.............. VIH = (VDD/2.64) + 1.25V
.................... VIL = (VDD/2.2) - 1.5V
................ VIL = (VDD/2.64) - 1.25V
Input rise and fall times ..................................... 1ns
Input timing reference levels ......................VDD/2.2
Output reference levels ............................ VDDQ/2.2
Output load ............................. See Figures 1 and 2
Input rise and fall times ..................................... 1ns
Input timing reference levels ................... VDD/2.64
Output reference levels ............................... VDDQ/2
Output load ............................. See Figures 3 and 4
Q
Q
ZO= 50
50
ZO= 50Ω
50Ω
VT = 1.5V
VT = 1.25V
Figure 1
3.3V I/O Output Load Equivalent
Figure 3
2.5V I/O Output Load Equivalent
+2.5V
+3.3V
225Ω
317
Q
Q
5pF
5pF
351
225Ω
Figure 4
2.5V I/O Output Load Equivalent
Figure 2
3.3V I/O Output Load Equivalent
LOAD DERATING CURVES
Micron 512K x 18, 256K x 32, and 256K x 36
SyncBurst SRAM timing is dependent upon the capaci-
tive loading on the outputs.
Consult the factory for copies of I/O current versus
voltage curves.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
20
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
SNOOZE MODE
SNOOZE MODE is a low-current, “power-down”
mode in which the device is deselected and current is
reduced to ISB2Z. The duration of SNOOZE MODE is
dictated by the length of time ZZ is in a HIGH state.
After the device enters SNOOZE MODE, all inputs
except ZZ become gated inputs and are ignored.
ZZ is an asynchronous, active HIGH input that
causes the device to enter SNOOZE MODE. When ZZ
becomes a logic HIGH, ISB2Z is guaranteed after the
setup time tZZ is met. Any READ or WRITE operation
pending when the device enters SNOOZE MODE is not
guaranteed to complete successfully. Therefore,
SNOOZE MODE must not be initiated until valid pend-
ing operations are completed.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYMBOL
ISB2Z
tZZ
tRZZ
tZZI
MIN
MAX
10
2(tKC)
UNITS
mA
ns
NOTES
Current during SNOOZE MODE
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to snooze current
ZZ inactive to exit snooze current
ZZ ≥ VIH
1
1
1
1
2(tKC)
0
ns
2(tKC)
ns
tRZZI
ns
NOTE: 1. This parameter is sampled.
SNOOZE MODE WAVEFORM
CLK
t
ZZ
t
RZZ
ZZ
t
ZZI
I
SUPPLY
I
ISB2Z
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
21
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
3
READ TIMING
t
KC
CLK
t
t
KL
KH
t
t
ADSH
ADSS
ADSP#
ADSC#
t
t
ADSH
ADSS
t
t
AH
AS
A1
A2
A3
Burst continued with
ADDRESS
t
t
WH
WS
new base address.
GW#, BWE#,
BWa#-BWd#
Deselect
cycle.
t
t
CEH
CES
CE#
(NOTE 2)
(NOTE 4)
t
t
AAH
AAS
ADV#
OE#
ADV#
suspends
burst.
t
t
OEQ
KQ
(NOTE 3)
High-Z
t
t
OEHZ
t
OELZ
t
KQHZ
KQX
t
KQLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A1)
Q
t
KQ
Burst wraps around
to its initial state.
(NOTE 1)
Single READ
BURST READ
DON’T CARE
UNDEFINED
READ TIMING PARAMETERS
-6
-7.5
MAX
-10
-6
-7.5
MAX
-10
SYMBOL
MIN
MAX
MIN
MIN
MAX UNITS
SYMBOL
MIN
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
MAX
MIN
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
MIN
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
MAX UNITS
t
t
KC
6.0
7.5
10
ns
AS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
t
KF
166
133
4.0
100
5.0
MHz
ns
ADSS
t
t
KH
2.3
2.3
2.5
2.5
3.0
3.0
AAS
t
t
KL
ns
WS
t
t
KQ
3.5
ns
CES
t
t
KQX
1.5
0
1.5
0
1.5
1.5
ns
AH
t
t
KQLZ
ns
ADSH
t
t
KQHZ
3.5
3.5
4.2
4.2
5.0
5.0
ns
AAH
t
t
OEQ
ns
WH
t
t
OELZ
0
0
0
ns
CEH
t
OEHZ
3.5
4.2
4.5
ns
NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q
to be driven until after the following clock rising edge.
4. Outputs are disabled within one clock cycle after deselect.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
22
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
WRITE TIMING
t
KC
CLK
t
t
KL
KH
t
t
ADSH
ADSS
ADSP#
ADSC# extends burst.
t
t
t
ADSH
ADSS
t
ADSH
ADSS
ADSC#
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are
ignored for first cycle when
ADSP# initiates burst.
t
WS
t
WH
BWE#,
BWa#-BWd#
t
t
WH (NOTE 5)
WS
GW#
t
t
CEH
CES
CE#
(NOTE 2)
t
AAS
t
AAH
ADV#
OE#
ADV# suspends burst.
(NOTE 4)
(NOTE 3)
t
t
DH
DS
D
Q
D(A2)
D(A2 + 1)
(NOTE 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
t
OEHZ
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE UNDEFINED
WRITE TIMING PARAMETERS
-6
-7.5
MAX
-10
-6
-7.5
MAX
-10
SYMBOL
MIN
MAX
MIN
MIN
MAX UNITS
SYMBOL
MIN
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
MAX
MIN
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
MIN
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
MAX UNITS
t
t
KC
6.0
7.5
10
ns
DS
ns
ns
ns
ns
ns
ns
ns
ns
f
t
KF
166
133
4.2
100
4.5
MHz
ns
CES
t
t
KH
2.3
2.3
2.5
2.5
3.0
3.0
AH
t
t
KL
ns
ADSH
t
t
OEHZ
3.5
ns
AAH
t
t
AS
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
ns
WH
t
t
ADSS
ns
DH
t
t
AAS
ns
CEH
t
WS
ns
NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH.
When CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents
input/output data contention for the time period prior to the byte write enable inputs being sampled.
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device;
or GW# HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
23
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
3
READ/WRITE TIMING
t
KC
CLK
t
t
KL
KH
t
t
ADSH
ADSS
ADSP#
ADSC#
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WH
WS
BWE#,
BWa#-BWd#
(NOTE 4)
t
t
CEH
CES
CE#
(NOTE 2)
ADV#
OE#
t
t
DH
t
KQ
DS
t
OELZ
D
Q
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
KQLZ
(NOTE 1)
Q(A4)
Q(A1)
Q(A2)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back READs
(NOTE 5)
Single WRITE
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
READ/WRITE TIMING PARAMETERS
-6
-7.5
MAX
-10
-6
-7.5
MAX
-10
SYMBOL
MIN
MAX
MIN
MIN
MAX UNITS
SYMBOL
MIN
MAX
MIN
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
MIN
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
MAX UNITS
t
t
t
t
t
t
t
t
t
t
KC
6.0
7.5
10
ns
ADSS
WS
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
KF
166
133
4.0
4.2
100
5.0
4.5
MHz
ns
t
KH
2.3
2.3
2.5
2.5
3.0
3.0
DS
t
KL
ns
CES
AH
t
KQ
3.5
3.5
ns
t
KQLZ
0
0
0
0
1.5
0
ns
ADSH
WH
DH
t
OELZ
ns
t
OEHZ
ns
t
AS
1.5
1.5
2.0
ns
CEH
NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
24
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
100-PIN PLASTIC TQFP (JEDEC LQFP)
PIN #1 ID
+0.03
-0.02
0.15
0.32
+0.06
-0.10
+0.10
-0.15
0.65
22.10
20.10 0.10
DETAIL A
0.62
1.50 0.10
0.10
14.00 0.10
+0.20
16.00
+0.10
-0.05
0.25
-0.05
0.10
GAGE PLANE
1.00 (TYP)
1.40 0.05
0.60 0.15
DETAIL A
MAX
MIN
NOTE: 1. All dimensions in millimeters
or typical where noted.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.01" per side.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
25
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
165-PIN FBGA
0.85 ±0.075
0.12
C
SEATING PLANE
C
BALL A11
165X Ø 0.45
10.00
SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION. THE
PRE-REFLOW DIAMETER IS Ø 0.40
BALL A1
PIN A1 ID
1.20 MAX
1.00
TYP
PIN A1 ID
7.50 ±0.05
14.00
15.00 ±0.10
7.00 ±0.05
1.00
TYP
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE: PLASTIC LAMINATE
6.50 ±0.05
5.00 ±0.05
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb
SOLDER BALL PAD: Ø .33mm
13.00 ±0.10
MAX
NOTE: 1. All dimensions in millimeters
or typical where noted.
MIN
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.
SyncBurst is a trademark of Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
26
8Mb: 512K x 18, 256K x 32/36
PIPELINED, SCD SYNCBURST SRAM
REVISION HISTORY
Removed “Preliminary Package Data” from front page ........................................................................ February 22/02
Removed -5 speed grade
Removed 119-pin PBGA package and references .................................................................................. February 14/02
Removed note "Not Recommended for New Designs," Rev. 6/01 ................................................................. June 7/01
Added industrial temperature references and notes, Rev. 3/01 ................................................................ March 19/01
Changed 16Mb references to 18Mb
Changed NC/DQPx to NF/DQPx
Added 119-pin PBGA package, Rev. 1/01, FINAL .................................................................................... January 10/01
Removed FBGA Part Marking Guide, Rev. 8/00, FINAL ............................................................................. August 1/00
Added FBGA Part Marking Guide, Rev 7/00 .................................................................................................. July 18/00
Added Revision History
Removed 119-Pin PBGA package and references
Removed Industrial Temperature references
Added 165-pin FBGA Package ....................................................................................................................... June 13/00
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
27
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