MT8HTF6464AY [MICRON]
DDR2 SDRAM UDIMM;
| 型号： | MT8HTF6464AY |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | DDR2 SDRAM UDIMM 动态存储器 双倍数据速率 |
| 文件： | 总18页 (文件大小：369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
DDR2 SDRAM UDIMM
MT8HTF3264AY – 256MB
MT8HTF6464AY – 512MB
MT8HTF12864AY – 1GB
Figure 1: 240-Pin UDIMM (MO-237 R/C A and D)
Features
PCB height: 30.0mm (1.18in)
240-pin, unbuffered dual in-line memory module
•
•
Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, PC2-6400, or PC2-8500
256MB (32 Meg x 64), 512MB (64 Meg x 64),
or 1GB (128 Meg x 64
•
VDD = VDDQ = 1.8V
•
•
•
•
•
•
Options
Marking
VDDSPD = 1.7–3.6V
Operating temperature
– Commercial (0°C ≤ TA ≤ +70°C)
– Industrial (–40°C ≤ TA ≤ +85°C)1
Package
•
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
None
I
•
•
Multiple internal device banks for concurrent
operation
240-pin DIMM (lead-free)
Y
–
Frequency/CL2
•
•
•
•
•
•
•
•
•
•
1.875ns @ CL = 7 (DDR2-1066)3
2.5ns @ CL = 5 (DDR2-800)
2.5ns @ CL = 6 (DDR2-800)
3.0ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-533)4
5.0ns @ CL = 3 (DDR2-400)
-1GA
-80E
-800
-667
-53E
-40E
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1 tCK
Programmable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
–
–
–
–
–
–
1. Contact Micron for industrial temperature
module offerings.
Notes:
On-die termination (ODT)
Serial presence detect (SPD) with EEPROM
Gold edge contacts
2. CL = CAS (READ) latency.
3. Available only in 1GB, Rev. E devices.
4. Not recommended for new designs.
Single rank
Table 1: Key Timing Parameters
Data Rate (MT/s)
Speed
Grade
Industry
Nomenclature
tRCD
(ns)
tRP
(ns)
tRC
(ns)
CL = 7
CL = 6
CL = 5
667
800
667
667
–
CL = 4
CL = 3
400
-1GA
-80E
-800
-667
-53E
-40E
PC2-8500
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
1066
800
800
800
–
533
533
533
553
553
400
13.125
12.5
15
13.125
12.5
15
58.125
57.5
60
400
400
400
15
15
60
400
15
15
55
–
400
15
15
55
–
–
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
© 2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
Table 2: Addressing
Parameter
256MB
8K
512MB
8K
1GB
8K
Refresh count
Row address
16K A[12:0]
4 BA[2:0]
16K A[13:0]
4 BA[2:0]
16K A[13:0]
8 BA[3:0]
1Gb (128 Meg x 8)
1K A[9:0]
1 S0#
Device bank address
Device configuration
Column address
Module rank address
256Mb (32 Meg x 8)
1K A[9:0]
1 S0#
512Mb (64 Meg x 8)
1K A[9:0]
1 S0#
Table 3: Part Numbers and Timing Parameters – 256MB Modules (End of Life)
Base device: MT47H32M8,1 256Mb DDR2 SDRAM
Module
Density
Module
Bandwidth
Memory Clock/
Clock Cycles
(CL-tRCD-tRP)
Part Number2
Configuration
32 Meg x 64
32 Meg x 64
32 Meg x 64
Data Rate
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
MT8HTF3264A(I)Y-667__
MT8HTF3264A(I)Y-53E__
MT8HTF3264A(I)Y-40E__
256MB
256MB
256MB
5.3 GB/s
4.3 GB/s
3.2 GB/s
5-5-5
4-4-4
3-3-3
Table 4: Part Numbers and Timing Parameters – 512MB Modules
Base device: MT47H64M8,1 512Mb DDR2 SDRAM
Module
Density
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Part Number2
Configuration
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
MT8HTF6464A(I)Y-80E__
MT8HTF6464A(I)Y-800__
MT8HTF6464A(I)Y-667__
MT8HTF6464A(I)Y-53E__
MT8HTF6464A(I)Y-40E__
512MB
512MB
512MB
512MB
512MB
6.2 GB/s
6.2 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
© 2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Features
Table 5: Part Numbers and Timing Parameters – 1GB Modules
Base device: MT47H128M8,1 1Gb DDR2 SDRAM
Module
Density
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Part Number2
Configuration
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
MT8HTF12864A(I)Y-1GA__
MT8HTF12864A(I)Y-80E__
MT8HTF12864A(I)Y-800__
MT8HTF12864A(I)Y-667__
MT8HTF12864A(I)Y-53E__
MT8HTF12864A(I)Y-40E__
1GB
8.5 GB/s
6.2 GB/s
6.2 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
1.875ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
7-7-7
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
1GB
1GB
1GB
1GB
1GB
1. The data sheet for the base device can be found on Micron’s Web site.
Notes:
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT8HTF12864AY-667E1.
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
3
© 2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Pin Assignments
Pin Assignments
Table 6: Pin Assignments
240-Pin UDIMM Front
240-Pin UDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
VREF
VSS
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
DQ19
VSS
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
A4
VDDQ
A2
91
92
VSS
DQS5#
DQS5
VSS
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
VSS
DQ4
DQ5
VSS
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
VSS
DQ28
DQ29
VSS
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
VDDQ
A3
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
DM5
NC
2
3
DQ0
DQ1
VSS
DQ24
DQ25
VSS
93
A1
VSS
4
VDD
94
VDD
DQ46
DQ47
VSS
5
VSS
95
DQ42
DQ43
VSS
DM0
NC
DM3
NC
CK0
CK0#
VDD
6
DQS0#
DQS0
VSS
DQS3#
DQS3
VSS
VSS
96
7
VDD
97
VSS
VSS
DQ52
DQ53
VSS
8
NC
98
DQ48
DQ49
VSS
DQ6
DQ7
VSS
DQ30
DQ31
VSS
A0
9
DQ2
DQ3
VSS
DQ26
DQ27
VSS
VDD
99
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A10
BA0
VDDQ
WE#
CAS#
VDDQ
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
BA1
VDDQ
RAS#
S0#
CK2
SA2
DQ12
DQ13
VSS
NC
CK2#
VSS
DQ8
DQ9
VSS
NC
NC
NC
NC
VSS
VSS
DM6
NC
VSS
DQS6#
DQS6
VSS
DM1
NC
NC
VDDQ
ODT0
DQS1#
DQS1
VSS
NC
NC
VSS
NC
VSS
VSS
196 NC/A132 226
DQ54
DQ55
VSS
VSS
NC
DQ50
DQ51
VSS
CK1
CK1#
VSS
NC
197
198
199
200
201
202
203
204
205
206
207
208
209
210
VDD
VSS
227
228
229
230
231
232
233
234
235
236
237
238
239
240
NC
NC
VDDQ
VSS
NC
NC
NC
VSS
DQ36
DQ37
VSS
DQ60
DQ61
VSS
VSS
VSS
DQ32
DQ33
VSS
DQ56
DQ57
VSS
DQ14
DQ15
VSS
VDDQ
NC
DQ10
DQ11
VSS
VDDQ
CKE0
VDD
VDD
NC
DM4
NC
DM7
NC
DQS4#
DQS4
VSS
DQS7#
DQS7
VSS
DQ20
DQ21
VSS
DQ16
DQ17
VSS
54 NC/BA21 84
NC
VSS
VSS
55
56
57
58
59
60
NC
VDDQ
A11
A7
85
86
87
88
89
90
VDDQ
A12
A9
DQ38
DQ39
VSS
DQ62
DQ63
VSS
DQ34
DQ35
VSS
DQ58
DQ59
VSS
DM2
NC
DQS2#
DQS2
VSS
VSS
VDD
A8
DQ44
DQ45
VSS
VDDSPD
SA0
VDD
A5
DQ40
DQ41
SDA
DQ22
DQ23
DQ18
SCL
A6
SA1
1. Pin 54 is NC for 256MB and 512MB or BA2 for 1GB.
2. Pin 196 is NC for 256MB or A13 for 512MB and 1GB.
Notes:
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
4
© 2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR2
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 7: Pin Descriptions
Symbol
Type
Description
Ax
Input
Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
BAx
Input
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, and MR3) is loaded during the LOAD MODE command.
CKx,
CK#x
Input
Input
Input
Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DDR2 SDRAM.
DMx,
Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
ODTx
Input
On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Par_In
Input
Input
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE#
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET#
S#x
Input
Input
Input
Input
Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This
signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs: Used to configure the SPD EEPROM address range on the I2C
bus.
SAx
SCL
Serial clock for SPD EEPROM: Used to synchronize communication to and from the
SPD EEPROM on the I2C bus.
CBx
I/O
I/O
I/O
Check bits. Used for system error detection and correction.
Data input/output: Bidirectional data bus.
DQx
DQSx,
DQS#x
Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the con-
troller. Output with read data; input with write data for source synchronous opera-
tion. DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command.
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
5
© 2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Pin Descriptions
Table 7: Pin Descriptions (Continued)
Symbol
Type
Description
SDA
I/O
Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on
the I2C bus.
RDQSx,
RDQS#x
Output
Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS
is output with read data only and is ignored during write data. When RDQS is disa-
bled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled
and differential data strobe mode is enabled.
Err_Out#
VDD/VDDQ
Output
(open drain)
Parity error output: Parity error found on the command and address bus.
Supply
Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the mod-
ule VDD
.
VDDSPD
VREF
VSS
Supply
SPD EEPROM power supply: 1.7–3.6V.
Supply
Reference voltage: VDD/2.
Supply
Ground.
NC
No connect: These pins are not connected on the module.
No function: These pins are connected within the module, but provide no functionality.
Not used: These pins are not used in specific module configurations/operations.
Reserved for future use.
–
–
–
–
NF
NU
RFU
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
6
© 2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram – Raw Card D
S0#
DQS0#
DQS0
DM0
DQS4#
DQS4
DM4
VSS
BA[2/1:0]: DDR2 SDRAM
A[13:0]: DDR2 SDRAM
RAS#: DDR2 SDRAM
CAS#: DDR2 SDRAM
WE#: DDR2 SDRAM
CKE0: DDR2 SDRAM
BA[2/1:0]
A[13:0]
RAS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
CAS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
WE#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CKE0
U1
U6
VSS
VSS
ODT0
ODT0: DDR2 SDRAM
DQS1#
DQS1
DM1
DQS5#
DQS5
DM5
VDDSPD
VDD/VDDQ
VREF
SPD EEPROM
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U2
U7
VSS
DQS2#
DQS2
DM2
DQS6#
DQS6
DM6
U5
SPD EEPROM
WP A0 A1 A2
SCL
SDA
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
VSS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
SA0 SA1 SA2
U3
U8
CK0
CK0#
DQS7#
DQS7
DM7
DQS3#
DQS3
DM3
U4, U6
CK1
CK1#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
U1–U3
U7–U9
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CK2
CK2#
U4
U9
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
7
© 2003 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Functional Block Diagram
Figure 3: Functional Block Diagram – Alternate Clock
S0#
DQS0#
DQS0
DM0
DQS4#
DQS4
DM4
VSS
BA[2/1:0]: DDR2 SDRAM
A[13:0]: DDR2 SDRAM
RAS#: DDR2 SDRAM
CAS#: DDR2 SDRAM
WE#: DDR2 SDRAM
CKE0: DDR2 SDRAM
BA[2/1:0]
A[13:0]
RAS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CAS#
WE#
U1
U5
CKE0
VSS
VSS
ODT0
ODT0: DDR2 SDRAM
DQS1#
DQS1
DM1
DQS5#
DQS5
DM5
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
VDDSPD
VDD/VDDQ
VREF
SPD EEPROM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U2
U6
VSS
DQS2#
DQS2
DM2
DQS6#
DQS6
DM6
U9
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
SPD EEPROM
WP A0 A1 A2
SCL
SDA
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ
DQ
DQ
DQ
DQ
DQ
DQ
VSS
SA0 SA1 SA2
U3
U7
CK0
DQS3#
DQS3
DM3
DQS7#
DQS7
DM7
CK0#
CK1
CK1#
U1–U4
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CK2
CK2#
U5–U8
U4
U8
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256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
General Description
General Description
DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
ules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM
modules use DDR architecture to achieve high-speed operation. DDR2 architecture is
essentially a 4n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM
module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans-
fers at the I/O pins.
DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is trans-
mitted externally, along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR2 SDRAM device during READs and by the memory con-
troller during WRITEs. DQS is edge-aligned with data for READs and center-aligned
with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
mands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Serial Presence-Detect EEPROM Operation
DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the mod-
ule type and various SDRAM organizations and timing parameters. The remaining 128
bytes of storage are available for use by the customer. System READ/WRITE operations
between the master (system logic) and the slave EEPROM device occur via a standard
I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect
(WP) is connected to VSS, permanently disabling hardware write protection.
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256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in the device data sheet is not implied. Exposure to
absolutemaximumratingconditionsforextendedperiodsmayadverselyaffectreliability.
Table 8: Absolute Maximum Ratings
Symbol
VDD/VDDQ
VIN, VOUT
II
Parameter
Min
–0.5
–0.5
–40
Max
2.3
2.3
40
Units
V
VDD/VDDQ supply voltage relative to VSS
Voltage on any pin relative to VSS
V
Address inputs, RAS#,
CAS#, WE#, S#, CKE,
ODT, BA
µA
Input leakage current; Any input 0V ≤ VIN ≤ VDD
VREF input 0V ≤ VIN ≤ 0.95V; (All other pins not
under test = 0V)
;
CK0, CK0#
(raw card D)
–10
–15
–20
10
15
20
CK1, CK1#, CK2, CK2#
(raw card D)
CK1, CK1#, CK2, CK2#
(alternate clock)
DM
–5
–5
5
5
IOZ
DQ, DQS, DQS#
µA
Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ
and ODT are disabled
IVREF
VREF leakage current; VREF = valid VREF level
–16
0
16
85
95
70
85
µA
°C
°C
°C
°C
1
TC
DDR2 SDRAM component operating tempera-
ture2
Commercial
Industrial
–40
0
TA
Module ambient operating temperature
Commercial
Industrial
–40
1. The refresh rate is required to double when TC exceeds 85°C.
Notes:
2. For further information, refer to technical note TN-00-08: "Thermal Applications," avail-
able on Micron’s Web site.
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256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
DRAM Operating Conditions
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR2 component data sheets.
Component specifications are available on Micron's Web site. Module speed grades cor-
relate with component speed grades.
Table 9: Module and Component Speed Grades
DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade
Component Speed Grade
-1GA
-80E
-800
-667
-53E
-40E
-187E
-25E
-25
-3
-37E
-5E
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully de-
signed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level. Mi-
cron encourages designers to simulate the signal characteristics of the system's memo-
ry bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to en-
sure the required supply voltage is maintained.
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256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
IDD Specifications
Table 10: DDR2 IDD Specifications and Conditions – 256MB
Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8)
component data sheet
Parameter
Symbol
-667
-53E
-40E Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC
(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
IDD0
720
640
600
mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL =
4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Ad-
dress bus inputs are switching; Data pattern is same as IDD4W
IDD1
800
720
680
mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
IDD2P
IDD2Q
IDD2N
40
40
40
mA
mA
mA
mA
320
320
280
280
200
240
Active power-down current: All device banks open; tCK = Fast PDN exit
tCK (IDD); CKE is LOW; Other control and address bus inputs MR[12] = 0
IDD3PF
IDD3PS
IDD3N
240
48
200
48
160
48
are stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
Active standby current: All device banks open; tCK = tCK (IDD), tRAS =
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus inputs
are switching
400
320
240
mA
mA
mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
IDD4W
1520
1440
1280
1200
1000
920
Operating burst read current: All device banks open; Continuous burst
read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
IDD4R
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD5
1440
40
1360
40
1320
40
mA
mA
IDD6
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
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256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
Table 10: DDR2 IDD Specifications and Conditions – 256MB (Continued)
Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8)
component data sheet
Parameter
Symbol
-667
-53E
-40E Units
1840 mA
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK =
tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH,
S# is HIGH between valid commands; Address bus inputs are stable during
deselects; Data bus inputs are switching
IDD7
2000
1920
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256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
Table 11: DDR2 IDD Specifications and Conditions – 512MB
Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8)
component data sheet
-80E
Parameter
Symbol -800 -667 -53E -40E Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC =
tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
IDD0
800
720
640
640
mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL =
4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN
(IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as IDD4W
IDD1
920
840
760
720
mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
Active power-down current: All device banks open; tCK Fast PDN exit
= tCK (IDD); CKE is LOW; Other control and address bus in- MR[12] = 0
puts are stable; Data bus inputs are floating
IDD2P
IDD2Q
IDD2N
IDD3PF
56
56
56
56
mA
mA
mA
mA
400
400
360
400
320
360
280
320
320
96
280
96
240
96
200
96
Slow PDN exit IDD3PS
MR[12] = 1
Active standby current: All device banks open; tCK = tCK (IDD), tRAS =
IDD3N
IDD4W
IDD4R
560
520
440
360
mA
mA
mA
tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX
(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
1560 1360 1120
1640 1440 1160
920
920
Operating burst read current: All device banks open; Continuous burst
read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC
(IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
IDD5
1840 1440 1360 1320
mA
mA
IDD6
56
56
56
56
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
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256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
Table 11: DDR2 IDD Specifications and Conditions – 512MB (Continued)
Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8)
component data sheet
-80E
Parameter
Symbol -800 -667 -53E -40E Units
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK
= tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
IDD7 2400 1920 1800 1760 mA
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256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
IDD Specifications
Table 12: DDR2 IDD Specifications and Conditions – 1GB
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
Parameter
Symbol -667
-53E
-40E Units
Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC
(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
IDD0
720
640
560
mA
Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL
= CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD =
tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
puts are switching; Data pattern is same as IDD4W
IDD1
800
760
640
mA
Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are float-
ing
Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
IDD2P
IDD2Q
IDD2N
56
56
56
mA
mA
mA
mA
440
480
328
360
280
320
Active power-down current: All device banks open; tCK =
Fast PDN exit
IDD3PF
IDD3PS
IDD3N
320
80
240
80
200
80
tCK (IDD); CKE is LOW; Other control and address bus inputs are MR[12] = 0
stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are switching
560
440
360
mA
mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP =
tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are switching; Data bus inputs are switching
IDD4W
IDD4R
IDD5
1280
1280
2080
1040
1160
2000
880
880
Operating burst read current: All device banks open; Continuous burst read,
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
mA
mA
Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD
)
1760
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
IDD6
IDD7
56
56
56
mA
mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK
(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is
HIGH between valid commands; Address bus inputs are stable during deselects;
Data bus inputs are switching
2400
2320
2080
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256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Serial Presence-Detect
Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 13: SPD EEPROM Operating Conditions
Parameter/Condition
Symbol
VDDSPD
VIH
Min
Max
Units
V
Supply voltage
1.7
3.6
Input high voltage: logic 1; All inputs
Input low voltage: logic 0; All inputs
Output low voltage: IOUT = 3mA
VDDSPD × 0.7
VDDSPD + 0.5
V
VIL
–0.6
–
VDDSPD × 0.3
V
VOL
0.4
3
V
Input leakage current: VIN = GND to VDD
Output leakage current: VOUT = GND to VDD
Standby current
ILI
0.1
0.05
1.6
0.4
2
µA
µA
µA
mA
mA
ILO
3
ISB
4
Power supply current, READ: SCL clock frequency = 100 kHz
Power supply current, WRITE: SCL clock frequency = 100 kHz
ICCR
ICCW
1
3
Table 14: SPD EEPROM AC Operating Conditions
Parameter/Condition
Symbol
Min
Max
0.9
–
Units
µs
Notes
SCL LOW to SDA data-out valid
Time bus must be free before a new transition can start
Data-out hold time
tAA
tBUF
tDH
tF
tR
tHD:DAT
tHD:STA
tHIGH
tI
tLOW
tSCL
tSU:DAT
tSU:STA
tSU:STO
tWRC
0.2
1.3
200
–
1
µs
ns
–
SDA and SCL fall time
300
300
–
ns
2
2
SDA and SCL rise time
ns
–
Data-in hold time
0
µs
Start condition hold time
Clock HIGH period
0.6
0.6
–
µs
–
µs
–
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
50
–
µs
1.3
–
µs
SCL clock frequency
400
–
kHz
ns
Data-in setup time
100
0.6
0.6
–
Start condition setup time
Stop condition setup time
WRITE cycle time
µs
3
4
–
µs
–
10
ms
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
Notes:
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-
up resistance, and the EEPROM does not respond to its slave address.
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256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
Module Dimensions
Module Dimensions
Figure 4: 240-Pin DDR2 UDIMM
FRONT VIEW
133.5 (5.256)
133.2 (5.244)
2.7 (0.106)
MAX
2.0 (0.079) R
(4X)
U1
U2
U3
U4
U5
U6
U7
U8
30.5 (1.2)
29.85 (1.175)
U9
17.78 (0.7)
TYP
2.5 (0.098) D
(2X)
2.3 (0.091) TYP
0.054 (1.37)
0.046 (1.17)
0.76 (0.03) R
PIN 1
10.0 (0.394)
TYP
1.0 (0.039)
TYP
0.8 (0.031)
TYP
2.21 (0.087) TYP
1.0 (0.039) TYP
PIN 120
70.66 (2.782)
TYP
123.0 (4.840)
TYP
BACK VIEW
45° (4X)
No Components This Side of Module
PIN 121
PIN 240
3.04 (0.1197)
TYP
5.0 (0.197) TYP
55.0 (2.165)
TYP
63.0 (2.48)
TYP
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
Notes:
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for
additional design dimensions.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
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SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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