MT8KTF12864AZ_技术文档

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

Features

1.35V DDR3L SDRAM UDIMM

MT8KTF12864AZ – 1GB

MT8KTF25664AZ – 2GB

MT8KTF51264AZ – 4GB

Figure 1: 240-Pin UDIMM (MO-269 R/C-A)

Features

• DDR3L functionality and operations supported as

defined in the component data sheet

Module height: 30mm (1.181in)

• 240-pin, unbuffered dual in-line memory module

(UDIMM)

• Fast data transfer rates: PC3-14900, PC3-12800, or

PC3-10600

Figure 2: 240-Pin UDIMM (MO-269 R/C-A1)

• 1GB (128 Meg x 64), 2GB (256 Meg x 64), or 4GB (512

Meg x 64)

Module Height: 30.0mm (1.181in)

• V_DD= V_DDQ= 1.35V (1.238–1.45V)

• V_DD= V_DDQ= 1.5V (1.425–1.575V)

• Backward-compatible to V_DD= V_DDQ= 1.5V ±0.075V

• V_DDSPD= 3.0–3.6V

• Reset pin for improved system stability

Options

Marking

• Nominal and dynamic on-die termination (ODT) for

data, strobe, and mask signals

• Operating temperature

– Commercial (0°C ≤ T_A≤ 70°C)

• Package

None

Z

• Single-rank

– 240-pin DIMM (halogen-free)

• Frequency/CAS latency

– 1.07ns @ CL = 13 (DDR3-1866)

– 1.25ns @ CL = 11 (DDR3-1600)

– 1.5ns @ CL = 9 (DDR3-1333)

• Fixed burst chop (BC) of 4 and burst length (BL) of 8

via the mode register set (MRS)

-1G9

-1G6

-1G4

• Adjustable data-output drive strength

• Serial presence-detect (SPD) EEPROM

• Gold edge contacts

• Halogen-free

• Fly-by topology

• Terminated control, command, and address bus

Table 1: Key Timing Parameters

Data Rate (MT/s)

Speed

Grade Nomenclature

Industry

CL =

13

CL =

11

CL =

10

^tRCD

(ns)

^tRP

(ns)

^tRC

(ns)

CL = 9 CL = 8 CL = 7 CL = 6 CL = 5

-1G9

-1G6

-1G4

-1G1

-1G0

-80B

PC3-14900

PC3-12800

PC3-10600

PC3-8500

PC3-6400

1866

1600

1333

–

1333

–

1066

–

1066

–

800

667

13.125 13.125 47.125

13.125 13.125 48.125

13.125 13.125 49.125

13.125 13.125 50.625

–

1600

–

15

52.5

–

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

1

Products and specifications discussed herein are subject to change by Micron without notice.

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

Features

Table 2: Addressing

Parameter

1GB

8K

2GB

8K

4GB

8K

Refresh count

Row address

16K A[13:0]

8 BA[2:0]

1Gb (128 Meg x 8)

1K A[9:0]

1 S0#

32K A[14:0]

8 BA[2:0]

2Gb (256 Meg x 8)

1K A[9:0]

1 S0#

64K A[15:0]

8 BA[2:0]

4Gb (512 Meg x 8)

1K A[9:0]

1 S0#

Device bank address

Device configuration

Column address

Module rank address

Table 3: Part Numbers and Timing Parameters – 1GB Modules

Base device: MT41K128M8,¹1Gb DDR3L SDRAM

Module

Density

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-^tRCD-^tRP)

Part Number²

Configuration

128 Meg x 64

MT8KTF12864AZ-1G6__

MT8KTF12864AZ-1G4__

1GB

12.8 GB/s

1.25ns/1600 MT/s

1.5ns/1333 MT/s

11-11-11

9-9-9

10.6 GB/s

Table 4: Part Numbers and Timing Parameters – 2GB Modules

Base device: MT41K256M8,¹2Gb DDR3L SDRAM

Module

Density

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-^tRCD-^tRP)

Part Number²

Configuration

256 Meg x 64

MT8KTF25664AZ-1G6__

MT8KTF25664AZ-1G4__

2GB

12.8 GB/s

10.6 GB/s

1.25ns/1600 MT/s

1.5ns/1333 MT/s

11-11-11

9-9-9

Table 5: Part Numbers and Timing Parameters – 4GB Modules

Base device: MT41K512M8,¹4Gb DDR3L SDRAM

Module

Density

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-^tRCD-^tRP)

Part Number²

Configuration

512 Meg x 64

MT8KTF51264AZ-1G9__

MT8KTF51264AZ-1G6__

4GB

14.9 GB/s

12.8 GB/s

1.07ns/1866 MT/s

1.25ns/1600 MT/s

13-13-13

11-11-11

1. Data sheets for the base device parts can be found on Micron’s Web site.

Notes:

2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.

Consult factory for current revision codes. Example: MT8KTF51264AZ-1G9P1.

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ktf8c128_256_512x64az.pdf – Rev. K 9/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

Pin Assignments

Table 6: Pin Assignments

240-Pin DDR3 UDIMM Front

240-Pin DDR3 UDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

1

2

V_REFDQ31 DQ25 61

A2

V_DD

NF

91

92

DQ41

V_SS

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

V_SS

DQ4

DQ5

V_SS

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

V_SS

DM3

NC

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

A1

V_DD

CK0

CK0#

V_DD

NC

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

V_SS

DM5

NC

V_SS

DQ0

DQ1

V_SS

32

V_SS

62

3

33 DQS3# 63

34 DQS3 64

93

DQS5#

DQS5

V_SS

4

NF

94

V_SS

5

35

V_SS

65

V_DD

95

DM0

NC

DQ30

DQ31

V_SS

DQ46

DQ47

V_SS

6

DQS0# 36 DQ26 66

96

DQ42

DQ43

V_SS

7

DQS0 37 DQ27 67 V_REFCA

97

V_SS

8

V_SS

DQ2

DQ3

V_SS

38

39

40

41

42

43

44

V_SS

NC

68

69

70

71

72

73

74

75

76

77

78

79

80

NC

V_DD

A10

BA0

V_DD

WE#

CAS#

V_DD

NC

98

DQ6

DQ7

V_SS

NC

A0

DQ52

DQ53

V_SS

9

99

DQ48

DQ49

V_SS

NC

V_DD

BA1

V_DD

RAS#

S0#

10

11

12

13

14

NC

100

101

V_SS

NC

DQ12

DQ13

V_SS

NC

DM6

NC

DQ8

DQ9

V_SS

102 DQS6#

NC

103

104

105

106

107

108

109

110

DQS6

V_SS

NC

DM1

NC

V_DD

ODT0

A13

V_DD

NC

DQ54

DQ55

V_SS

15 DQS1# 45

16 DQS1 46

DQ50

DQ51

V_SS

NC

V_SS

17

V_SS

47

V_SS

NC

DQ14

DQ15

V_SS

NC

DQ60

DQ61

V_SS

18 DQ10 48

19 DQ11 49

V_DD

NC

DQ56

DQ57

V_SS

168 RESET# 198

NC

169

NC

199

V_SS

20

V_SS

50

CKE0

V_DD

BA2

NC

V_SS

DQ20

DQ21

V_SS

170

V_DD

200

DQ36

DQ37

V_SS

DM7

NC

21 DQ16 51

22 DQ17 52

81 DQ32

82 DQ33

111 DQS7#

171 NF/A15¹201

172 NF/A14²202

112

113

DQS7

V_SS

23

V_SS

53

83

V_SS

DM2

NC

173

174

175

176

177

178

179

180

V_DD

A12

A9

203

204

205

206

207

208

209

210

DM4

NC

DQ62

DQ63

V_SS

24 DQS2# 54

25 DQS2 55

V_DD

A11

A7

84 DQS4# 114

DQ58

DQ59

V_SS

85 DQS4

86 V_SS

115

116

117

118

119

120

V_SS

26

V_SS

56

DQ22

DQ23

V_SS

V_DD

A8

DQ38

DQ39

V_SS

236 V_DDSPD

27 DQ18 57

28 DQ19 58

V_DD

A5

87 DQ34

88 DQ35

SA0

SCL

237

238

239

240

SA1

SDA

V_SS

A6

29

V_SS

59

A4

89

V_SS

SA2

V_TT

DQ28

DQ29

V_DD

A3

DQ44

DQ45

30 DQ24 60

V_DD

90 DQ40

V_TT

1. Pin 171 is NF for 1GB and 2GB; A14 for 4GB.

2. Pin 172 is NF for 1GB; A14 for 2GB and 4GB.

Notes:

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

3

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for all DDR3

modules. All pins listed may not be supported on this module. See Pin Assignments for

information specific to this module.

Table 7: Pin Descriptions

Symbol

Type

Description

Ax

Input

Address inputs: Provide the row address for ACTIVE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location

out of the memory array in the respective bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one bank (A10 LOW, bank

selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code

during a LOAD MODE command. See the Pin Assignments table for density-specific ad-

dressing information.

BAx

Input

Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or

PRECHARGE command is being applied. BA define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command.

CKx,

CKx#

Input

Clock: Differential clock inputs. All control, command, and address input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#.

CKEx

DMx

Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-

try and clocks on the DRAM.

Data mask (x8 devices only): DM is an input mask signal for write data. Input data

is masked when DM is sampled HIGH, along with that input data, during a write ac-

cess. Although DM pins are input-only, DM loading is designed to match that of the

DQ and DQS pins.

ODTx

Input

On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-

nation resistance internal to the DDR3 SDRAM. When enabled in normal operation,

ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input

will be ignored if disabled via the LOAD MODE command.

Par_In

Input

Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.

RAS#, CAS#, WE#

Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being

entered.

RESET#

Input

(LVCMOS)

Reset: RESET# is an active LOW asychronous input that is connected to each DRAM

and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitial-

ized as though a normal power-up was executed.

Sx#

SAx

SCL

Input

Chip select: Enables (registered LOW) and disables (registered HIGH) the command

decoder.

Serial address inputs: Used to configure the temperature sensor/SPD EEPROM ad-

dress range on the I²C bus.

Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communi-

cation to and from the temperature sensor/SPD EEPROM on the I²C bus.

CBx

I/O

Check bits: Used for system error detection and correction.

Data input/output: Bidirectional data bus.

DQx

DQSx,

Data strobe: Differential data strobes. Output with read data; edge-aligned with

DQSx#

read data; input with write data; center-aligned with write data.

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

4

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

Pin Descriptions

Table 7: Pin Descriptions (Continued)

Symbol

Type

Description

SDA

I/O

Serial data: Used to transfer addresses and data into and out of the temperature sen-

sor/SPD EEPROM on the I²C bus.

TDQSx,

TDQSx#

Output

Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD

MODE command to the extended mode register (EMR). When TDQS is enabled, DM is

disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are

no function.

Err_Out#

EVENT#

V_DD

Output

(open drain)

Parity error output: Parity error found on the command and address bus.

Output

Temperature event: The EVENT# pin is asserted by the temperature sensor when crit-

(open drain) ical temperature thresholds have been exceeded.

Supply

Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The

component V_DDand V_DDQare connected to the module V_DD

.

V_DDSPD

V_REFCA

V_REFDQ

V_SS

Supply

–

Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.

Reference voltage: Control, command, and address V_DD/2.

Reference voltage: DQ, DM V_DD/2.

Ground.

V_TT

Termination voltage: Used for control, command, and address V_DD/2.

No connect: These pins are not connected on the module.

NC

NF

–

No function: These pins are connected within the module, but provide no functional-

ity.

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5

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

DQ Map

Table 8: Component-to-Module DQ Map

Component

Reference

Number

Reference

Number

Component

DQ

Module Pin

Number

Component

DQ

Module Pin

Number

Module DQ

U1

U3

U5

U7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

129

123

128

3

U2

U4

U6

U8

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

15

13

14

8

138

132

137

12

5

6

0

3

10

11

12

10

9

19

4

122

9

131

18

2

1

4

13

23

21

22

16

19

20

18

17

39

37

38

32

35

36

34

33

55

53

54

48

51

52

50

49

147

141

146

21

31

29

30

24

27

28

26

25

47

45

46

40

43

44

42

41

63

61

62

56

59

60

58

57

156

150

155

30

28

37

140

27

149

36

22

31

207

201

206

81

216

210

215

90

88

97

200

87

209

96

82

91

225

219

224

99

234

228

233

108

115

227

114

109

106

218

105

100

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6

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

Functional Block Diagram

Figure 3: Functional Block Diagram

S0#

DQS0#

DQS0

DM0

DQS4#

DQS4

DM4

BA[2:0]

A[15/14/13:0]

RAS#

BA[2:0]: DDR3 SDRAM

A[15/14/13:0]: DDR3 SDRAM

RAS#: DDR3 SDRAM

CAS#: DDR3 SDRAM

WE#: DDR3 SDRAM

DM CS# DQS DQS#

DQ

CAS#

DQ

ZQ

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

WE#

DQ

ZQ

CKE0

CKE0: DDR3 SDRAM

ODT0: DDR3 SDRAM

RESET#: DDR3 SDRAM

ODT0

U1

U5

RESET#

Address, command, control, and clock line terminations:

DDR3

V

SS

DQS1#

DQS1

DM1

DQS5#

DQS5

DM5

SDRAM

CKE0, A[15/14/13:0],

RAS#, CAS#, WE#,

S0#, ODT0, BA[2:0]

DM CS# DQS DQS#

DQ

V

DQ8

DQ9

TT

DQ

ZQ

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ

ZQ

DDR3

SDRAM

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

U2

U6

CK0

CK0#

V

DD

V

SS

U9

DQS2#

DQS2

DM2

DQS6#

DQS6

DM6

SPD EEPROM

WP A0 A1 A2

SDA

SCL

DM CS# DQS DQS#

DQ

ZQ

DQ

ZQ

DQ16

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

SA0 SA1 SA2

V_SS

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

CK0

CK0#

DDR3 SDRAM x8

U3

U7

CK1

CK1#

Unused clock termination

V

SS

V

SS

DQS3#

DQS3

DM3

DQS7#

DQS7

DM7

V

SPD EEPROM

DDR3 SDRAM

DDSPD

V

DQ24

DD

DM CS# DQS DQS#

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ

ZQ

DQ

ZQ

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

Address, command,

and control termination

V

TT

V

DDR3 SDRAM

REFCA

U4

U8

V

DDR3 SDRAM

REFDQ

V

SS

V

SS

V

SS

1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor

that is tied to ground. It is used for the calibration of the component’s ODT and output

driver.

Note:

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7

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

General Description

DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory mod-

ules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM mod-

ules use DDR architecture to achieve high-speed operation. DDR3 architecture is essen-

tially an 8n-prefetch architecture with an interface designed to transfer two data words

per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM mod-

ule effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the inter-

nal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers

at the I/O pins.

DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK

and CK# to capture commands, addresses, and control signals. Differential clocks and

data strobes ensure exceptional noise immunity for these signals and provide precise

crossing points to capture input signals.

Fly-By Topology

DDR3 modules use faster clock speeds than earlier DDR technologies, making signal

quality more important than ever. For improved signal quality, the clock, control, com-

mand, and address buses have been routed in a fly-by topology, where each clock, con-

trol, command, and address pin on each DRAM is connected to a single trace and ter-

minated (rather than a tree structure, where the termination is off the module near the

connector). Inherent to fly-by topology, the timing skew between the clock and DQS sig-

nals can be easily accounted for by using the write-leveling feature of DDR3.

Serial Presence-Detect EEPROM Operation

DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a

256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with

JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM

Modules." These bytes identify module-specific timing parameters, configuration infor-

mation, and physical attributes. The remaining 128 bytes of storage are available for use

by the customer. System READ/WRITE operations between the master (system logic)

and the slave EEPROM device occur via a standard I²C bus using the DIMM’s SCL

(clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to V_SS, per-

manently disabling hardware write protection. For further information refer to Micron

technical note TN-04-42, "Memory Module Serial Presence-Detect."

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8

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

Electrical Specifications

Stresses greater than those listed may cause permanent damage to the module. This is a

stress rating only, and functional operation of the module at these or any other condi-

tions outside those indicated in each device's data sheet is not implied. Exposure to ab-

solute maximum rating conditions for extended periods may adversely affect reliability.

Table 9: Absolute Maximum Ratings

Symbol

V_DD

Parameter

Min

–0.4

Max

1.975

Units

V_DDsupply voltage relative to V_SS

Voltage on any pin relative to V_SS

V

V_IN, V_OUT

Table 10: Operating Conditions

Symbol Parameter

Min

1.283

1.425

–600

Nom

1.35

1.5

Max

Units Notes

V_DD

V_DDsupply voltage

1.45

1.575

600

V

mA

V

1

2

I_VTT

V_TT

Termination reference current from V_TT

–

Termination reference voltage (DC)

– command/address bus

0.49 × V_DD- 20mV 0.5 × V_DD0.51 × V_DD+ 20mV

I_I

Input leakage current;

Address in-

–16

0

16

µA

Any input 0V ≤ V_IN≤ V_DD

V_REFinput 0V ≤ V_IN≤ 0.95V

;

puts, RAS#,

CAS#, WE#,

(All other pins not under test BA, S#, CKE,

= 0V)

ODT, CK,

CK#

DM

–2

–5

0

2

5

I_OZ

Output leakage current;

0V ≤ V_OUT≤ V_DDQ; DQ and

ODT are disabled; ODT is HIGH

DQ, DQS,

DQS#

µA

I_VREF

V_REFsupply leakage current; V_REFDQ= V_DD/2

or V_REFCA= V_DD/2 (All other pins not under

test = 0V.)

–8

0

8

T_A

T_C

Module ambient operating

temperature

Commercial

0

–

70

95

°C

3, 4

DDR3 SDRAM component case Commercial

operating temperature

3, 4, 5

1. Module is backward-compatible with 1.5V operation. Refer to device specification for

details and operation guidance.

Notes:

2. V_TTtermination voltage in excess of the stated limit will adversely affect the command

and address signals’ voltage margin and will reduce timing margins.

3. T_Aand T_Care simultaneous requirements.

4. For further information, refer to technical note TN-00-08: ”Thermal Applications,” avail-

able on Micron’s Web site.

5. The refresh rate is required to double when 85°C < T_C≤ 95°C.

PDF: 09005aef8413b5fe

ktf8c128_256_512x64az.pdf – Rev. K 9/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

9

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR3 component data sheets.

Component specifications are available at micron.com. Module speed grades correlate

with component speed grades, as shown below.

Table 11: Module and Component Speed Grades

DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades

Module Speed Grade

Component Speed Grade

-2G1

-1G9

-1G6

-1G4

-1G1

-1G0

-80C

-80B

-093

-107

-125

-15E

-187E

-187

-25E

-25

Design Considerations

Simulations

Micron memory modules are designed to optimize signal integrity through carefully de-

signed terminations, controlled board impedances, routing topologies, trace length

matching, and decoupling. However, good signal integrity starts at the system level.

Micron encourages designers to simulate the signal characteristics of the system's

memory bus to ensure adequate signal integrity of the entire memory system.

Power

Operating voltages are specified at the DRAM, not at the edge connector of the module.

Designers must account for any system voltage drops at anticipated power levels to en-

sure the required supply voltage is maintained.

PDF: 09005aef8413b5fe

ktf8c128_256_512x64az.pdf – Rev. K 9/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

10

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

I_DDSpecifications

Table 12: DDR3 I_DDSpecifications and Conditions – 1GB (Die Revision J)

Values are for the MT41K128M8 DDR3L SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8)

component data sheet

Parameter

Symbol

I_DD0

1600

272

360

96

1333

264

344

96

Units

mA

Operating current 0: One bank ACTIVATE-to-PRECHARGE

Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE

Precharge power-down current: Slow exit

Precharge power-down current: Fast exit

Precharge quiet standby current

Precharge standby current

I_DD1

I_DD2P0

I_DD2P1

I_DD2Q

I_DD2N

I_DD2NT

I_DD3P

I_DD3N

I_DD4R

I_DD4W

I_DD5B

I_DD6

96

120

136

200

112

192

664

704

1280

96

120

136

192

112

184

576

616

1240

96

Precharge standby ODT current

Active power-down current

Active standby current

Burst read operating current

Burst write operating current

Refresh current

Self refresh temperature current: MAX T_C= 85°C

Self refresh temperature current (SRT-enabled): MAX T_C= 95°C

All banks interleaved read current

Reset current

I_DD6ET

I_DD7

112

1192

112

1152

112

I_DD8

PDF: 09005aef8413b5fe

ktf8c128_256_512x64az.pdf – Rev. K 9/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

11

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

I_DDSpecifications

Table 13: DDR3 I_DDSpecifications and Conditions – 2GB (Die Revision K)

Values are for the MT41K256M8 DDR3L SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8)

component data sheet

Parameter

Symbol

I_DD0

1600

312

416

96

1333

304

400

96

Units

mA

Operating current 0: One bank ACTIVATE-to-PRECHARGE

Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE

Precharge power-down current: Slow exit

Precharge power-down current: Fast exit

Precharge quiet standby current

Precharge standby current

I_DD1

I_DD2P0

I_DD2P1

I_DD2Q

I_DD2N

I_DD2NT

I_DD3P

I_DD3N

I_DD4R

I_DD4W

I_DD5B

I_DD6

112

160

168

248

168

256

752

776

1440

96

112

160

168

232

168

240

656

680

1432

96

Precharge standby ODT current

Active power-down current

Active standby current

Burst read operating current

Burst write operating current

Refresh current

Self refresh temperature current: MAX T_C= 85°C

Self refresh temperature current (SRT-enabled): MAX T_C= 95°C

All banks interleaved read current

Reset current

I_DD6ET

I_DD7

120

1248

112

120

1200

112

I_DD8

PDF: 09005aef8413b5fe

ktf8c128_256_512x64az.pdf – Rev. K 9/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

12

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

I_DDSpecifications

Table 14: DDR3 I_DDSpecifications and Conditions – 4GB (Die Revision E)

Values are for the MT41K512M8 DDR3L SDRAM only and are computed from values specified in the 4Gb (512 Meg x 8)

component data sheet

Parameter

Symbol

I_DD0

1866

496

1600

440

Units

mA

Operating current 0: One bank ACTIVATE-to-PRECHARGE

Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE

Precharge power-down current: Slow exit

Precharge power-down current: Fast exit

Precharge quiet standby current

Precharge standby current

I_DD1

560

528

I_DD2P0

I_DD2P1

I_DD2Q

I_DD2N

I_DD2NT

I_DD3P

I_DD3N

I_DD4R

I_DD4W

I_DD5B

I_DD6

144

296

256

280

256

280

256

Precharge standby ODT current

336

312

Active power-down current

328

304

Active standby current

328

304

Burst read operating current

1392

1128

1936

160

1256

1000

1880

160

Burst write operating current

Refresh current

Self refresh temperature current: MAX T_C= 85°C

Self refresh temperature current (SRT-enabled): MAX T_C= 95°C

All banks interleaved read current

Reset current

I_DD6ET

I_DD7

200

2008

160

1760

160

I_DD8

PDF: 09005aef8413b5fe

ktf8c128_256_512x64az.pdf – Rev. K 9/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

13

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

I_DDSpecifications

Table 15: DDR3 I_DDSpecifications and Conditions – 4GB (Die Revision N)

Values are for the MT41K512M8 DDR3L SDRAM only and are computed from values specified in the 4Gb (512 Meg x 8)

component data sheet

Parameter

Symbol

I_DD0

1866

392

512

64

1600

376

488

64

Units

mA

Operating current 0: One bank ACTIVATE-to-PRECHARGE

Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE

Precharge power-down current: Slow exit

Precharge power-down current: Fast exit

Precharge quiet standby current

Precharge standby current

I_DD1

I_DD2P0

I_DD2P1

I_DD2Q

I_DD2N

I_DD2NT

I_DD3P

I_DD3N

I_DD4R

I_DD4W

I_DD5B

I_DD6

128

208

240

224

256

840

1440

96

112

192

224

208

240

760

1400

96

Precharge standby ODT current

Active power-down current

Active standby current

Burst read operating current

Burst write operating current

Refresh current

Self refresh temperature current: MAX T_C= 85°C

Self refresh temperature current (SRT-enabled): MAX T_C= 95°C

All banks interleaved read current

Reset current

I_DD6ET

I_DD7

128

1120

80

128

1040

80

I_DD8

PDF: 09005aef8413b5fe

ktf8c128_256_512x64az.pdf – Rev. K 9/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

14

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

I_DDSpecifications

Table 16: DDR3 I_DDSpecifications and Conditions – 4GB (Die Revision P)

Values are for the MT41K512M8 DDR3L SDRAM only and are computed from values specified in the 4Gb (512 Meg x 8)

component data sheet

Parameter

Symbol

I_DD0

1866

232

352

88

1600

224

344

80

Units

mA

Operating current 0: One bank ACTIVATE-to-PRECHARGE

Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE

Precharge power-down current: Slow exit

Precharge power-down current: Fast exit

Precharge quiet standby current

Precharge standby current

I_DD1

I_DD2P0

I_DD2P1

I_DD2Q

I_DD2N

I_DD2NT

I_DD3P

I_DD3N

I_DD4R

I_DD4W

I_DD5B

I_DD6

88

120

136

176

120

168

816

904

1216

120

184

1168

104

120

128

160

120

160

720

808

1216

120

184

1040

104

Precharge standby ODT current

Active power-down current

Active standby current

Burst read operating current

Burst write operating current

Refresh current

Self refresh temperature current: MAX T_C= 85°C

Self refresh temperature current (SRT-enabled): MAX T_C= 95°C

All banks interleaved read current

Reset current

I_DD6ET

I_DD7

I_DD8

PDF: 09005aef8413b5fe

ktf8c128_256_512x64az.pdf – Rev. K 9/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

15

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

Serial Presence-Detect EEPROM

For the latest SPD data, refer to Micron's SPD page: micron.com/spd.

Table 17: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to V_DDSPD

Parameter/Condition

Symbol

V_DDSPD

V_IL

Min

Max

3.6

Units

V

Supply voltage

3.0

–0.45

V_DDSPDx 0.7

–

Input low voltage: Logic 0; All inputs

Input high voltage: Logic 1; All inputs

Output low voltage: I_OUT= 3mA

Input leakage current: V_IN= GND to V_DD

Output leakage current: V_OUT= GND to V_DD

V_DDSPDx 0.3

V_DDSPD+ 1.0

0.4

V

V_IH

V

V_OL

V

I_LI

0.1

2.0

µA

I_LO

0.05

2.0

Table 18: Serial Presence-Detect EEPROM AC Operating Conditions

Parameter/Condition

Clock frequency

Symbol

^tSCL

^tHIGH

^tLOW

Min

10

Max

400

–

Units

kHz

µs

Notes

Clock pulse width HIGH time

Clock pulse width LOW time

SDA rise time

0.6

1.3

–

µs

^tR

^tF

300

–

µs

1

SDA fall time

20

ns

Data-in setup time

^tSU:DAT

^tHD:DI

^tHD:DAT

^tAA:DAT

^tSU:STA

^tHD:STA

^tSU:STO

^tBUF

100

0

ns

Data-in hold time

–

µs

Data-out hold time

200

0.2

0.6

1.3

900

0.9

–

ns

Data out access time from SCL LOW

Start condition setup time

Start condition hold time

Stop condition setup time

µs

2

3

µs

–

µs

–

µs

Time the bus must be free before a new transition can

start

–

µs

WRITE time

^tW

–

10

ms

1. Guaranteed by design and characterization, not necessarily tested.

Notes:

2. To avoid spurious start and stop conditions, a minimum delay is placed between the fall-

ing edge of SCL and the falling or rising edge of SDA.

3. For a restart condition, or following a WRITE cycle.

PDF: 09005aef8413b5fe

ktf8c128_256_512x64az.pdf – Rev. K 9/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

16

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

Module Dimensions

Figure 4: 240-Pin DDR3 UDIMM (R/C-A)

Front view

2.7 (0.106)

MAX

133.50 (5.256)

133.20 (5.244)

0.9 (0.035) TYP

0.50 (0.02) R

(4X)

0.75 (0.03) R

U1

U2

U3

U4

U5

U6

U7

U8

30.50 (1.20)

29.85 (1.175)

(8X)

23.3 (0.92)

TYP

2.50 (0.098) D

(2X)

17.3 (0.68)

TYP

U9

2.30 (0.091) TYP

1.37 (0.054)

1.17 (0.046)

0.76 (0.030) R

Pin 1

2.20 (0.087) TYP

1.0 (0.039)

TYP

0.80 (0.031)

TYP

9.5 (0.374)

TYP

1.45 (0.057) TYP

Pin 120

54.68 (2.15)

TYP

123.0 (4.84)

TYP

15.0 (0.59)

4X TYP

1.0 (0.039) R (8X)

Back view

45°, 4X

5.1 (0.2) TYP

3.1 (0.122) 2X TYP

No components this side of module

3.0 (0.118) 4X TYP

3.05 (0.12) TYP

Pin 121

Pin 240

5.0 (0.197) TYP

71.0 (2.79)

TYP

47.0 (1.85)

TYP

1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

Notes:

2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for ad-

ditional design dimensions.

PDF: 09005aef8413b5fe

ktf8c128_256_512x64az.pdf – Rev. K 9/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

17

1GB, 2GB, 4GB (x64, SR) 240-Pin 1.35V DDR3L UDIMM

Module Dimensions

Figure 5: 240-Pin DDR3 UDIMM (R/C-A1)

Front view

2.7 (0.106)

MAX

133.50 (5.256)

133.20 (5.244)

0.75 (0.03) R

(8X)

U1

U2

U3

U4

U5

U6

U7

U8

30.50 (1.20)

29.85 (1.175)

U9

2.50 (0.098) D

(2X)

17.3 (0.68)

TYP

2.30 (0.091) TYP

1.37 (0.054)

1.17 (0.046)

0.76 (0.030) R

Pin 1

2.20 (0.087) TYP

1.45 (0.057) TYP

9.5 (0.374)

TYP

1.0 (0.039)

TYP

0.80 (0.031)

TYP

Pin 120

54.68 (2.15)

TYP

123.0 (4.84)

TYP

0.6 (0.024) x 45° (4X)

Back view

No components this side of module

3.0 (0.118) x4 TYP

3.05 (0.12) TYP

Pin 121

Pin 240

5.0 (0.197) TYP

71.0 (2.79)

TYP

47.0 (1.85)

TYP

1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

Notes:

2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for ad-

ditional design dimensions.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

PDF: 09005aef8413b5fe

ktf8c128_256_512x64az.pdf – Rev. K 9/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

18


型号：	MT8KTF12864AZ
厂家：	MICRON TECHNOLOGY
描述：	1.35V DDR3L SDRAM UDIMM 动态存储器双倍数据速率
文件：	总18页 (文件大小：429K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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