MTFC4GMVEA-4MIT [MICRON]
4GB, 8GB, 16GB, 32GB, 64GB e MMC; 4GB ， 8GB ， 16GB ， 32GB ， 64GB MMC ê
| 型号： | MTFC4GMVEA-4MIT |
| 厂家： | 
MICRON TECHNOLOGY |
| 描述： | 4GB, 8GB, 16GB, 32GB, 64GB e MMC |
| 文件： | 总24页 (文件大小：479K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Micron Confidential and Proprietary
4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
Features
e·MMC™ Memory
MTFC4GMVEA-4M IT, MTFC8GLVEA-4M IT, MTFC16GJVEC-4M IT,
MTFC32GJVED-4M IT, MTFC64GJVDN-4M IT
Figure 1: Micron e·MMC Device
Features
• MultiMediaCard (MMC) controller and NAND Flash
• 153- or 169-ball WFBGA/VFBGA/LFBGA (RoHS 6/6-
compliant)
• VCC: 2.7–3.6V
• VCCQ (dual voltage): 1.65–1.95V; 2.7–3.6V
• Temperature ranges
MMC
interface
MMC
MMC controller
NAND Flash
power
– Industrial temperature: –40˚C to +85˚C
– Storage temperature: –40˚C to +85˚C
• Typical current consumption
– Standby current: 120µA for 4GB–16GB; 140µA for
32GB; 160µA for 64GB
NAND Flash
power
– Active current (RMS): 80mA (4GB–64GB)
MMC-Specific Features
• JEDEC/MMC standard version 4.41-compliant
(JEDEC Standard No. 84-A441) – SPI mode not
supported (see www.jedec.org/sites/default/files/
docs/JESD84-A441.pdf)
– Advanced 11-signal interface
– x1, x4, and x8 I/Os, selectable by host
– MMC mode operation
– Command classes: class 0 (basic); class 2 (block
read); class 4 (block write); class 5 (erase);
class 6 (write protection); class 7 (lock card)
– MMCplus™ and MMCmobile™ protocols
– Temporary write protection
MMC-Specific Features (Continued)
– Enhanced reliable write
– Configurable reliability settings
– Background operation
– Fully enhanced configurable
– Backward-compatible with previous MMC
modes
• ECC and block management implemented
– 52 MHz clock speed (MAX)
– Boot operation (high-speed boot)
– Sleep mode
– Replay-protected memory block (RPMB)
– Secure erase and trim
– Hardware reset signal
– Multiple partitions with enhanced attribute
– Permanent and power-on write protection
– Double data rate (DDR) function
– High-priority interrupt (HPI)
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2012 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Confidential and Proprietary
4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
Features
e·MMC Performance
Table 1: MLC Partition Performance
Part Number
MTFC16GJVEC-4M IT
MTFC4GMVEA-4M IT
MTFC8GLVEA-4M IT
MTFC32GJVED-4M IT
MTFC64GJVDN-4M IT
Condition
Units
MB/s
MB/s
Sequential write
Sequential read
13.5
44
20
44
1. Sequential access of 1MB chunk. Additional performance data, such as power consumption or timing for dif-
ferent device modes, will be provided in a separate document upon customer request.
Note:
Ordering Information
Table 2: Ordering Information
Base Part Number
Density
Package
NAND Flash Type
Shipping Media
Tray
MTFC4GMVEA-4M IT
4GB
153-ball WFBGA
2 x 16Gb, MLC, 25nm
11.5mm x 13.0mm x 0.8mm
Tape and reel
Tray
MTFC8GLVEA-4M IT
MTFC16GJVEC-4M IT
MTFC32GJVED-4M IT
MTFC64GJVDN-4M IT
8GB
16GB
32GB
64GB
153-ball WFBGA
11.5mm x 13.0mm x 0.8mm
2 x 32Gb, MLC, 25nm
2 x 64Gb, MLC, 25nm
4 x 64Gb, MLC, 25nm
8 x 64Gb, MLC, 25nm
Tape and reel
Tray
169-ball WFBGA
14.0mm x 18.0mm x 0.8mm
Tape and reel
Tray
169-ball VFBGA
14.0mm x 18.0mm x 1.0mm
Tape and reel
Tray
169-ball LFBGA
14.0mm x 18.0mm x 1.4mm
Tape and reel
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Micron Confidential and Proprietary
4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
Features
Part Numbering Information
Micron®e·MMC memory devices are available in different configurations and densities. Verify valid part numbers
by using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 2: Marketing Part Number Chart
MT FC 4G
M
V
x
EA - 0
M
WT
Micron Technology
Production Status
Blank = Production
Product Family
FC = NAND Flash + controller
ES = Engineering samples
MS = Mechanical samples
NAND Flash Density
2G = 2GB
Operating Temperature Range
Blank = 0°C to 70°C
4G = 4GB
WT = Standard (–25°C to +85°C)
IT = Extended (–40°C to +85)°C
8G = 8GB
16G = 16GB
32G = 32GB
64G = 64GB
SLC Enhanced Area
F = 40%
M = 100%
NAND Flash Component
Mark Device
Maximum Boot Size
0 = 1MB
J
MLC 64Gb, x8, 3.3V (25nm)
MLC 32Gb, x8, 3.3V (25nm)
MLC 16Gb, x8, 3.3V (25nm)
1 = 2MB
L
2 = 4MB
M
3 = 8MB
Controller Revision
4 = 16MB
Mark (Rev.) Controller ID
Package Codes (Pb-free)
T
Enhanced
Combo
DN = 169 LFBGA 14mm x 18mm x 1.4mm
DQ = 100 LFBGA 14mm x 18mm x 1.4mm
EA = 153 WFBGA 11.5mm x 13mm x 0.8mm
EC = 169 WFBGA 14mm x 18mm x 0.8mm
ED = 169 VFBGA 14mm x 18mm x 1.0mm
V
Reserved for Future Use
1. Not all combinations are necessarily available. For a list of available devices or for further information on
any aspect of these products, please contact your nearest Micron sales office.
Note:
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Micron Confidential and Proprietary
4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
General Description
General Description
Micron e·MMC is a communication and mass data storage device that includes a Multi-
MediaCard (MMC) interface, a NAND Flash component, and a controller on an ad-
vanced 11-signal bus, which is compliant with the MMC system specification. Its cost
per bit, small package sizes, and high reliability make it an ideal choice for industrial
applications like infrastructure and networking equipment, PC and servers, a variety of
other industrial products.
The nonvolatile e·MMC draws no power to maintain stored data, delivers high perform-
ance across a wide range of operating temperatures, and resists shock and vibration dis-
ruption.
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Micron Confidential and Proprietary
4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
Signal Descriptions
Signal Descriptions
Table 3: Signal Descriptions
Symbol
Type
Description
CLK
Input
Clock: Each cycle of the clock directs a transfer on the command line and on the data line(s). The
frequency can vary between the minimum and the maximum clock frequency.
RST_n
CMD
Input
I/O
Reset: The RST_n signal is used by the host for resetting the device, moving the device to the pre-
idle state. By default, the RST_n signal is temporarily disabled in the device. The host must set ECSD
register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it.
Command: This signal is a bidirectional command channel used for command and response trans-
fers. The CMD signal has two bus modes: open-drain mode and push-pull mode (see Operating
Modes). Commands are sent from the MMC host to the device, and responses are sent from the
device to the host.
DAT[7:0]
I/O
Data I/O: These are bidirectional data signals. The DAT signals operate in push-pull mode. By de-
fault, after power-on or assertion of the RST_n signal, only DAT0 is used for data transfer. The
MMC controller can configure a wider data bus for data transfer either using DAT[3:0] (4-bit mode)
or DAT[7:0] (8-bit mode). e·MMC includes internal pull-up resistors for data lines DAT[7:1]. Immedi-
ately after entering the 4-bit mode, the device disconnects the internal pull-up resistors on the
DAT[3:1] lines. Upon entering the 8-bit mode, the device disconnects the internal pull-ups on the
DAT[7:1] lines.
VCC
Supply VCC: NAND interface (I/F) I/O and NAND Flash power supply.
Supply VCCQ: e·MMC controller core and e·MMC I/F I/O power supply.
Supply VSS: NAND I/F I/O and NAND Flash ground connection.
Supply VSSQ: e·MMC controller core and e·MMC I/F ground connection.
VCCQ
1
VSS
1
VSSQ
VDDI
Internal voltage node: At least a 0.1μF capacitor is required to connect VDDI to ground. A 1μF ca-
pacitor is recommended. Do not tie to supply voltage or ground.
NC
–
–
No connect: No internal connection is present.
RFU
Reserved for future use: No internal connection is present. Leave it floating externally.
1. VSS and VSSQ are connected internally.
Note:
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Micron Confidential and Proprietary
4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
153-Ball Signal Assignments
153-Ball Signal Assignments
Figure 3: 153-Ball FBGA (top view, ball down)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
D
E
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC DAT0 DAT1 DAT2 RFU
DAT3 DAT4 DAT5 DAT6 DAT7
RFU
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
NC
NC
NC
NC
RFU
NC
NC
NC
NC
NC
NC
V
RFU
V
CCQ
NC
DDI
SSQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RFU
V
V
RFU
RFU
RFU
RFU
RFU
CC
SS
F
V
CC
G
H
J
V
SS
RFU
RFU
V
SS
V
CC
RST_n RFU
RFU
V
V
RFU
K
L
SS
CC
V
CMD CLK
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
M
N
P
CCQ
V
V
V
V
NC
SSQ
CCQ
SSQ
NC
V
V
V
SSQ
RFU
RFU
CCQ
SSQ
CCQ
1. Some test pads on the device are not shown. They are not solder balls and are for Mi-
cron internal use only.
Notes:
2. Some previous versions of the JEDEC product or mechanical specification had defined
reserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the pre-
vious specifications could have been connected to ground on the system board. To ena-
ble new feature introduction, some of these balls are assigned as RFU in the v4.4 me-
chanical specification. Any new PCB footprint implementations should use the new ball
assignments and leave the RFU balls floating on the system board.
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Micron Confidential and Proprietary
4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
169-Ball Signal Assignments
169-Ball Signal Assignments
Figure 4: 169-Ball FBGA (top view, ball down)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
D
E
NC
NC
NC
NC
1
NC
NC
NC
NC
F
G
H
J
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC DAT0 DAT1 DAT2 RFU
RFU
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DAT3 DAT4 DAT5
DAT6 DAT7
K
L
VDDI
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSSQ
NC
NC
NC
VSSQ RFU VCCQ
NC
NC
M
N
NC
RFU
VCC
VSS
VCC
VSS
RFU
RFU
RFU
RFU
RFU
VSS
NC
RFU
NC
P
R
RFU
RFU
T
U
V
NC
VCC
RFU
NC
RST_n RFU
RFU
VSS
VCC
NC
W
NC
CMD CLK
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCCQ
VCCQ
VSSQ
Y
NC
VSSQ
NC
AA
VCCQ
VCCQ VSSQ
RFU
RFU
AB
AC
AD
AE
AF
NC
NC
AG
AH
NC
NC
NC
NC
NC
NC
1. Empty balls do not denote actual solder balls; they are position indicators only.
Notes:
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Micron Confidential and Proprietary
4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
169-Ball Signal Assignments
2. Some test pads on the device are not shown. They are not solder balls and are for Mi-
cron internal use only.
3. Some previous versions of the JEDEC product or mechanical specification had defined
reserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the pre-
vious specifications could have been connected to ground on the system board. To ena-
ble new feature introduction, some of these balls are assigned as RFU in the v4.4 me-
chanical specification. Any new PCB footprint implementations should use the new ball
assignments and leave the RFU balls floating on the system board.
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Micron Confidential and Proprietary
4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
Package Dimensions
Package Dimensions
Figure 5: 153-Ball WFBGA – 11.5mm x 13.0mm x 0.8mm (Package Code: EA)
Seating plane
A
0.08 A
153X Ø0.30
Dimensions apply
to solder balls post-
reflow on Ø0.30
SMD ball pads.
Ball A1 ID
(covered by SR)
Ball A1 ID
14 12 10
13 11
8
6
4
2
9
7
5
3
1
A
B
C
D
E
6.5 CTR
F
G
H
J
K
L
13 ±0.1
M
N
P
0.5 TYP
0.5 TYP
0.7 ±0.1
6.5 CTR
0.17 MIN
11.5 ±0.1
1. Dimensions are in millimeters.
Note:
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4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
Package Dimensions
Figure 6: 169-Ball WFBGA – 14.0mm x 18.00mm x 0.8mm (Package Code: EC)
Seating plane
A
0.08
A
169X Ø0.3
Dimensions apply to
solder balls post-reflow
on Ø0.30 SMD OSP ball
pads.
Ball A1 ID
Ball A1 ID
14 12 10
13 11
8
6
4
2
9
7
5
3
1
A
B
C
D
E
F
G
H
J
K
13.5 CTR
6.5 CTR
L
M
N
P
R
T
U
V
18 ±0.1
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
0.5 TYP
0.5 TYP
6.5 CTR
14 ±0.1
0.7 ±0.1
0.17 MIN
1. Dimensions are in millimeters.
Note:
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Micron Confidential and Proprietary
4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
Package Dimensions
Figure 7: 169-Ball VFBGA – 14.0mm x 18.00mm x 1.0mm (Package Code: ED)
Seating plane
A
0.08
A
169X Ø0.3
Dimensions apply to
solder balls post-reflow
on Ø0.30 SMD ball pads.
Ball A1 ID
Ball A1 ID
14 12 10
13 11
8
6
4
2
9
7
5
3
1
A
B
C
D
E
F
G
H
J
K
13.5 CTR
L
M
N
P
6.5 CTR
R
T
U
V
18 ±0.1
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
0.5 TYP
0.5 TYP
6.5 CTR
14 ±0.1
0.9 ±0.1
0.17 MIN
1. Dimensions are in millimeters.
Note:
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4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
Package Dimensions
Figure 8: 169-Ball LFBGA – 14.0mm x 18.00mm x 1.4mm (Package Code: DN)
Seating plane
A
0.08 A
169X Ø0.3
Dimensions apply
to solder balls post-
reflow on Ø0.30 SMD
ball pads.
Ball A1 ID
(covered by SR)
Ball A1 ID
14 12 10
13 11
8
6
4
2
9
7
5
3
1
A
B
C
D
E
F
G
H
J
K
L
13.5 CTR
M
N
P
R
T
6.5 CTR
U
V
W
Y
18 ±0.1
AA
AB
AC
AD
AE
AF
AG
AH
0.5 TYP
0.5 TYP
1.3 ±0.1
6.5 CTR
14 ±0.1
0.16 MIN
1. Dimensions are in millimeters.
Note:
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4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
Architecture
Architecture
Figure 9: e·MMC Functional Block Diagram
e·MMC
MMC
VCC
controller
VCCQ
RST_n
CMD
CLK
Registers
CSD
DAT[7:0]
OCR
CID
RCA
DSR
VDDI
1
VSS
ECSD
1
VSSQ
NAND Flash
1. VSS and VSSQ are internally connected.
Note:
MMC Protocol Independent of NAND Flash Technology
The MMC specification defines the communication protocol between a host and a de-
vice. The protocol is independent of the NAND Flash features included in the device.
The device has an intelligent on-board controller that manages the MMC communica-
tion protocol.
The controller also handles block management functions such as logical block alloca-
tion and wear leveling. These management functions require complex algorithms and
depend entirely on NAND Flash technology (generation or memory cell type).
The device handles these management functions internally, making them invisible to
the host processor.
Defect and Error Management
Micron e·MMC incorporates advanced technology for defect and error management. If
a defective block is identified, the device completely replaces the defective block with
one of the spare blocks. This process is invisible to the host and does not affect data
space allocated for the user.
The device also includes a built-in error correction code (ECC) algorithm to ensure that
data integrity is maintained.
To make the best use of these advanced technologies and ensure proper data loading
and storage over the life of the device, the host must exercise the following precautions:
• Check the status after WRITE, READ, and ERASE operations.
• Avoid power-down during WRITE and ERASE operations.
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4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
CID Register
CID Register
The card identification (CID) register is 128 bits wide. It contains the device identifica-
tion information used during the card identification phase as required by e·MMC proto-
col. Each device is created with a unique identification number.
Table 4: CID Register Field Parameters
Name
Field
MID
–
Width
CID Bits
[127:120]
[119:114]
[113:112]
[111:104]
[103:56]
CID Value
Manufacturer ID
Reserved
8
6
FEh
–
Card/BGA
CBX
OID
PNM
2
01h
–
OEM/application ID
Product name
8
48
MMC04G
MMC08G
MMC16G
MMC32G
MMC64G
Product revision
PRV
PSN
MDT
CRC
–
8
32
8
[55:48]
[47:16]
[15:8]
[7:1]
–
–
–
–
–
Product serial number
Manufacturing date
CRC7 checksum
7
Not used; always 1
1
0
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4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
CSD Register
CSD Register
The card-specific data (CSD) register provides information about accessing the device
contents. The CSD register defines the data format, error correction type, maximum da-
ta access time, and data transfer speed, as well as whether the DS register can be used.
The programmable part of the register (entries marked with W or E in the following ta-
ble) can be changed by the PROGRAM_CSD (CMD27) command.
Table 5: CSD Register Field Parameters
Name
Cell
Width Type1
CSD
Bits
CSD
Value
Field
CSD structure
CSD_STRUCTURE
2
4
2
8
8
R
R
[127:126]
[125:122]
[121:120]
[119:112]
[111:104]
03h
4h
System specification version
Reserved2
SPEC_VERS
–
TBD
R
–
Data read access time 1
TAAC
4Fh
01h
Data read access time 2 in CLK cy- NSAC
cles (NSAC × 100)
R
Maximum bus clock frequency
Card command classes
TRAN_SPEED
CCC
8
12
4
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
[103:96]
[95:84]
[83:80]
79
32h
0F5h
9h
Maximum read data block length READ_BL_LEN
Partial blocks for reads supported READ_BL_PARTIAL
1
0h
Write block misalignment
Read block misalignment
DS register implemented
Reserved
WRITE_BLK_MISALIGN
1
78
0h
READ_BLK_MISALIGN
DSR_IMP
77
1
77
0h
76
1h
–
2
[75:74]
[73:62]
[61:59]
[58:56]
[55:53]
[52:50]
[49:47]
[46:42]
[41:37]
[36:32]
–
Device size
C_SIZE
12
3
FFFh
7h
Maximum read current at VDD,min
VDD_R_CURR_MIN
Maximum read current at VDD,max VDD_R_CURR_MAX
Maximum write current at VDD,min VDD_W_CURR_MIN
Maximum write current at VDD,max VDD_W_CURR_MAX
3
7h
3
7h
3
7h
Device size multiplier
Erase group size
C_SIZE_MULT
3
7h
ERASE_GRP_SIZE
ERASE_GRP_MULT
WP_GRP_SIZE
5
1Fh
1Fh
07h
0Fh
1Fh
Erase group size multiplier
Write protect group size
5
MTFC4GMVEA-4M IT
MTFC8GLVEA-4M IT
5
MTFC16GJVEC-4M IT,
MTFC32GJVED-4M IT,
MTFC64GJVDN-4M IT
Write protect group enable
Manufacturer default ECC
Write-speed factor
WP_GRP_ENABLE
DEFAULT_ECC
R2W_FACTOR
1
2
3
4
1
R
R
R
R
R
31
1h
0h
2h
9h
0h
[30:29]
[28:26]
[25:22]
21
Maximum write data block length WRITE_BL_LEN
Partial blocks for writes supported WRITE_BL_PARTIAL
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CSD Register
Table 5: CSD Register Field Parameters (Continued)
Cell
Width Type1
CSD
Bits
CSD
Value
Name
Field
Reserved
–
4
1
1
1
1
1
2
2
7
1
R
[20:17]
16
–
Content protection application
File-format group
Copy flag (OTP)
Permanent write protection
Temporary write protection
File format
CONTENT_PROT_APP
R
0h
0h
0h
0h
0h
0h
0h
–
FILE_FORMAT_GRP
R/W
R/W
R/W
R/W/E
R/W
R/W/E
R/W/E
–
15
COPY
14
PERM_WRITE_PROTECT
13
TMP_WRITE_PROTECT
12
FILE_FORMAT
[11:10]
[9:8]
[7:1]
0
ECC
ECC
CRC
–
CRC
Not used; always 1
1h
1. R = Read-only
R/W = One-time programmable and readable
Notes:
R/W/E = Multiple writable with value kept after a power cycle, assertion of the RST_n
signal, and any CMD0 reset, and readable
TBD = To be determined
2. Reserved bits should be read as 0.
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ECSD Register
ECSD Register
The 512-byte extended card-specific data (ECSD) register defines device properties and
selected modes. The most significant 320 bytes are the properties segment. This seg-
ment defines device capabilities and cannot be modified by the host. The lower 192
bytes are the modes segment. The modes segment defines the configuration in which
the device is working. The host can change the properties of modes segments using the
SWITCH command.
Table 6: ECSD Register Field Parameters
Size
Cell
ECSD
Bytes
ECSD
Value
Name
Field
(Bytes) Type1
Properties Segment
Reserved2
–
7
1
–
R
R
R
–
[511:505]
504
–
Supported command sets
HPI features
S_CMD_SET
1h
3h
1h
–
HPI_FEATURES
1
503
Background operations support BKOPS_SUPPORT
Reserved
1
502
–
255
1
[501:247]
246
Background operations status
BKOPS_STATUS
R
R
0h
–
Number of correctly program-
med sectors
CORRECTLY_PRG_
SECTORS_NUM
4
[245:242]
First initialization time after par- INI_TIMEOUT_PA
titioning
(first CMD1 to device ready)
MTFC4GMVEA-4M IT
1
R
241
78h
F4h
F6h
FFh
MTFC8GLVEA-4M IT
MTFC16GJVEC-4M IT
MTFC32GJVED-4M IT,
MTFC64GJVDN-4M IT
Reserved
–
–
1
1
–
240
239
–
Power class for 52 MHz, DDR at PWR_CL_DDR_52_360
3.6V3
R
0h
Power class for 52 MHz, DDR at PWR_CL_DDR_52_195
1.95V3
1
R
238
0h
Reserved
2
1
–
[237:236]
235
–
Minimum write performance for MIN_PERF_DDR_W_8_52
8-bit at 52 MHz in DDR mode
R
0h
Minimum read performance for MIN_PERF_DDR_R_8_52
8-bit at 52 MHz in DDR mode
1
R
234
0h
Reserved
–
1
1
–
233
232
–
TRIM multiplier
TRIM_MULT
MTFC4GMVEA-4M IT,
MTFC8GLVEA-4M IT
R
06h
MTFC16GJVEC-4M IT,
MTFC32GJVED-4M IT,
MTFC64GJVDN-4M IT
0Fh
15h
Secure feature support
SEC_FEATURE_SUPPORT
1
R
231
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ECSD Register
Table 6: ECSD Register Field Parameters (Continued)
Size
Cell
ECSD
Bytes
ECSD
Value
Name
Field
MTFC4GMVEA-4M IT,
(Bytes) Type1
SECURE ERASE multiplier
SEC_ERASE_MULT
SEC_TRIM_MULT
BOOT_INFO
1
1
R
230
02h
MTFC8GLVEA-4M IT
MTFC16GJVEC-4M IT,
MTFC32GJVED-4M IT,
MTFC64GJVDN-4M IT
06h
SECURE TRIM multiplier
MTFC4GMVEA-4M IT,
MTFC8GLVEA-4M IT
R
229
03h
09h
MTFC16GJVEC-4M IT,
MTFC32GJVED-4M IT,
MTFC64GJVDN-4M IT
Boot information
Reserved
1
1
1
1
R
–
228
227
226
225
7h
–
–
Boot partition size
Access size
BOOT_SIZE_MULT
ACC_SIZE
R
R
80h
06h
MTFC4GMVEA-4M IT,
MTFC8GLVEA-4M IT
MTFC16GJVEC-4M IT,
MTFC32GJVED-4M IT,
MTFC64GJVDN-4M IT
07h
High-capacity erase unit size
HC_ERASE_GRP_SIZE MTFC4GMVEA-4M IT,
MTFC8GLVEA-4M IT
1
R
224
08h
10h
MTFC16GJVEC-4M IT,
MTFC32GJVED-4M IT,
MTFC64GJVDN-4M IT
High-capacity erase timeout
Reliable write-sector count
ERASE_TIMEOUT_MULT
REL_WR_SEC_C
1
1
1
R
R
R
223
222
221
01h
01h
01h
02h
High-capacity write protect
group size
HC_WP_GRP_SIZE
MTFC4GMVEA-4M IT
MTFC8GLVEA-4M IT,
MTFC16GJVEC-4M IT
MTFC32GJVED-4M IT
MTFC64GJVDN-4M IT
04h
08h
08h
08h
–
Sleep current (VCC
)
S_C_VCC
1
1
1
1
1
4
R
R
–
220
219
218
217
216
Sleep current (VCCQ
Reserved
)
S_C_VCCQ
–
–
Sleep/awake timeout
Reserved
S_A_TIMEOUT
SEC_COUNT
R
–
10h
–
Sector count
MTFC4GMVEA-4M IT
MTFC8GLVEA-4M IT
MTFC16GJVEC-4M IT
MTFC32GJVED-4M IT
MTFC64GJVDN-4M IT
R
[215:212] 0070C000h
00E88000h
01D30000h
03B20000h
07700000h
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ECSD Register
Table 6: ECSD Register Field Parameters (Continued)
Size
Cell
ECSD
Bytes
ECSD
Value
Name
Field
(Bytes) Type1
Reserved
–
1
1
–
211
210
–
Minimum write performance for MIN_PERF_W_8_52
8-bit at 52 MHz
R
08h
Minimum read performance for MIN_PERF_R_8_52
8-bit at 52 MHz
1
1
R
R
209
208
08h
08h
Minimum write performance for MIN_PERF_W_8_26_4_52
8-bit at 26 MHz and 4-bit at 52
MHz
Minimum read performance for MIN_PERF_R_8_26_4_52
1
R
207
08h
8-bit at 26 MHz and 4-bit at 52
MHz
Minimum write performance for MIN_PERF_W_4_26
4-bit at 26 MHz
1
1
R
R
206
205
08h
08h
Minimum read performance for MIN_PERF_R_4_26
4-bit at 26 MHz
Reserved
–
1
1
1
1
1
1
1
1
1
1
1
1
1
–
R
R
R
R
R
R
–
204
203
202
201
200
199
198
197
196
195
194
193
192
–
Power class for 26 MHz at 3.6V3 PWR_CL_26_360
Power class for 52 MHz at 3.6V3 PWR_CL_52_360
Power class for 26 MHz at 1.95V3 PWR_CL_26_195
Power class for 52 MHz at 1.95V3 PWR_CL_52_195
00h
00h
00h
00h
1h
02h
–
Partition switching timing
Out-of-interrupt busy timing
Reserved
PARTITION_SWITCH_TIME
OUT_OF_INTERRUPT_TIME
–
Card type
CARD_TYPE
R
–
07h
–
Reserved
–
CSD_STRUCTURE
–
CSD structure version
Reserved
R
–
2h
–
Extended CSD revision
Modes Segment
Command set
EXT_CSD_REV
R
5h
CMD_SET
1
R/W/E_
P
191
0h
Reserved
–
CMD_SET_REV
–
1
1
1
1
–
R
–
190
189
188
187
–
Command set revision
Reserved
0h
–
Power class
POWER_CLASS
R/W/E_
P
0h
Reserved
–
1
1
–
186
185
–
High-speed interface timing
HS_TIMING
R/W/E_
P
0h
Reserved
–
1
–
184
–
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ECSD Register
Table 6: ECSD Register Field Parameters (Continued)
Size
Cell
ECSD
Bytes
ECSD
Value
Name
Field
(Bytes) Type1
Bus width mode
Reserved
BUS_WIDTH
1
1
1
1
1
W/E_P
183
182
181
180
179
0h
–
–
–
R
–
Erased memory content
Reserved
ERASED_MEM_CONT
PARTITION_CONFIG
0h
–
–
Partition configuration
R/W/E,
R/W/E_
P
0h
Boot configuration protection
BOOT_CONFIG_PROT
BOOT_BUS_WIDTH
1
R/W,
R/W/C_
P
178
0h
Boot bus width
Reserved
1
1
1
R/W/E
–
177
176
175
0h
–
–
–
High-density erase group defini- ERASE_GROUP_DEF
tion
R/W/E_
P
00h
Reserved
1
1
–
174
173
–
Boot area write protection regis- BOOT_WP
ter
R/W,
R/W/C_
P
0h
Reserved
–
–
1
1
–
172
171
–
User write protection register
USER_WP
R/W,
R/W/
C_P,
R/W/E_
P
0h
Reserved
1
1
1
1
1
–
R/W
R
170
169
168
167
166
–
Firmware configuration
FW_CONFIG
0h
RPMB size
RPMB_SIZE_MULT
1h
00h4
Write reliability setting register3 WR_REL_SET
R/W
R
Write reliability parameter regis- WR_REL_PARAM
ter
05h
Reserved
–
1
1
–
165
164
–
–
Manually start background oper- BKOPS_START
ations
W/E_P
Enable background operations
handshake
BKOPS_EN
1
R/W
163
0h
Hardware reset function
HPI management
RST_n_FUNCTION
HPI_MGMT
1
1
R/W
162
161
0h
0h
R/W/E_
P
Partitioning support
PARTITIONING_SUPPORT
1
R
160
3h
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4GB, 8GB, 16GB, 32GB, 64GB: e·MMC
ECSD Register
Table 6: ECSD Register Field Parameters (Continued)
Size
Cell
ECSD
Bytes
ECSD
Value
Name
Field
MAX_ENH_SIZE_MULT MTFC4GMVEA-4M IT
MTFC8GLVEA-4M IT
(Bytes) Type1
Maximum enhanced area size
3
R
[159:157] 0001C3h
0001D1h
MTFC16GJVEC-4M IT
0001D3h
MTFC32GJVED-4M IT
0001D9h
MTFC64GJVDN-4M IT
0001DCh
Partitions attribute
PARTITIONS_ATTRIBUTE
PARTITION_SETTING_COMPLETED
GP_SIZE_MULT
1
1
R/W
R/W
R/W
R/W
R/W
–
156
155
0h
0h
0h
0h
0h
–
Partitioning setting
General-purpose partition size
Enhanced user data area size
12
3
[154:143]
[142:140]
[139:136]
135
ENH_SIZE_MULT
Enhanced user data start address ENH_START_ADDR
Reserved
4
–
1
Bad block management mode
Reserved
SEC_BAD_BLK_MGMNT
1
R/W
–
134
0h
–
–
134
[133:0]
1. R = Read-only
R/W = One-time programmable and readable
Notes:
R/W/E = Multiple writable with the value kept after a power cycle, assertion of the
RST_n signal, and any CMD0 reset, and readable
R/W/C_P = Writable after the value is cleared by a power cycle and assertion of the
RST_n signal (the value not cleared by CMD0 reset) and readable
R/W/E_P = Multiple writable with the value reset after a power cycle, assertion of the
RST_n signal, and any CMD0 reset, and readable
W/E_P = Multiple writable with the value reset after power cycle, assertion of the RST_n
signal, and any CMD0 reset, and not readable
TBD = To be determined
2. Reserved bits should be read as 0.
3. Micron has tested power failure under best application knowledge conditions with posi-
tive results. Customers may request a dedicated test for their specific application condi-
tion.
4. Set at 00h when shipped for optimized write performance; can be set to 1Fh to enable
protection on previously written data if power failure occurs during a WRITE operation.
This byte is one-time programmable.
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DC Electrical Specifications – Device Power
DC Electrical Specifications – Device Power
The device current consumption for various device configurations is defined in the
power class fields of the ECSD register.
VCC is used for the NAND Flash device and its interface voltage; VCCQ is used for the
controller and the e·MMC interface voltage. A CREG capacitor must be connected to the
VDDI terminal to stabilize regulator output on the system.
Figure 10: Device Power Diagram
VCC
VCCQ
Core regulator
NAND
NAND Flash
VDDI
control signals
CREG
Core
logic block
CLK
NAND
CMD
data bus
DAT[7:0]
MMC controller
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only, and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not guaranteed. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Table 7: Absolute Maximum Ratings
Parameters
Voltage input
VCC supply
Symbol
Min
–0.6
–0.6
–0.6
–40
Max
4.6
4.6
4.6
85
Unit
V
VIN
VCC
V
VCCQ supply
VCCQ
TSTG
V
Storage temperature
°C
1. Voltage on any pin relative to VSS.
Note:
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DC Electrical Specifications – Device Power
Table 8: Operating Conditions
Parameters
Symbol
Min
1.65
2.70
2.70
–
Typ
–
Max
1.95
3.6
3.6
35
Unit
Supply voltage (controller
and I/O)
VCCQ
V
–
Supply voltage (NAND)
Supply power-on for 3.3V
Supply power-on for 1.8V
VDDI capacitance value
Operating temperature
VCC
–
V
tPRUH
tPRUL
–
ms
ms
µF
ºC
–
–
25
1
CREG
0.1
–40
–
–
TA
–
85
1. CREG is used to stabilize the internal regulator output to controller core logic voltages.
Micron recommends using the following capacitor values:
CVCC (capacitor for VCC) = 4.3µF.
Note:
CVCCQ (capacitor for VCCQ) = 4.3µF
CREG = 1.0µF.
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Revision History
Revision History
Rev. D – 07/12
• Updated MMC-Specific Features
• Updated Ordering Information table
• Added Part Numbering information
• Updated 169-ball LFBGA package dimension drawing (package code DN)
• Corrected typographical error in ECSD Register table and updated note 4
Rev. C – 05/12
• Updated CSD Register and ECSD Register
• Corrected Ordering Information
• To Production status
Rev. B – 02/12
Rev. A – 01/12
• Changed the part numbers and the minimum operating temperature from -25 to -40
degrees C
• Initial release
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
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500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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