PC28F256P30TFE_技术文档

256Mb and 512Mb (256Mb/256Mb), P30-65nm

Features

Micron Parallel NOR Flash Embedded

Memory (P30-65nm)

JS28F256P30B/TFx, RC28F256P30B/TFx, PC28F256P30B/TFx,

RD48F4400P0VBQEx, RC48F4400P0VB0Ex,

PC48F4400P0VB0Ex, PF48F4000P0ZB/TQEx

• Security

Features

• High performance

– One-Time Programmable Register: 64 OTP bits,

programmed with unique information from Mi-

cron; 2112 OTP bits available for customer pro-

gramming

– 100ns initial access for Easy BGA

– 110ns initial access for TSOP

– 25ns 16-word asychronous page read mode

– 52 MHz (Easy BGA) with zero WAIT states and

17ns clock-to-data output synchronous burst

read mode

– Absolute write protection: VPP = VSS

– Power-transition erase/program lockout

– Individual zero-latency block locking

– Individual block lock-down

– Password access

• Software

– 4-, 8-, 16-, and continuous word options for burst

mode

– Buffered enhanced factory programming (BEFP)

at 2MB/s (TYP) using a 512 word buffer

– 1.8V buffered programming at 1.14MB/s (TYP)

using a 512 word buffer

– 25μs (TYP) program suspend

– 25μs (TYP) erase suspend

– Flash Data Integrator optimized

– Basic command set and extended function Inter-

face (EFI) command set compatible

– Common flash interface

• Architecture

– MLC: highest density at lowest cost

– Asymmetrically blocked architecture

– Four 32-KB parameter blocks: top or bottom con-

figuration

– 128KB main blocks

– Blank check to verify an erased block

• Voltage and power

• Density and Packaging

– 56-lead TSOP package (256Mb only)

– 64-ball Easy BGA package (256Mb, 512Mb)

– QUAD+ and SCSP packages (256Mb, 512Mb)

– 16-bit wide data bus

• Quality and Reliabilty

– V_CC(core) voltage: 1.7V to 2.0V

– V_CCQ(I/O) voltage: 1.7V to 3.6V

– Standy current: 65µA (TYP) for 256Mb

– 52 MHz continuous synchronous read current:

21mA (TYP), 24mA (MAX)

– JESD47E compliant

– Operating temperature: –40 °C to +85 °C

– Minimum 100,000 erase cycles per block

– 65nm process technology

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Micron Technology, Inc. reserves the right to change products or specifications without notice.

1

Products and specifications discussed herein are subject to change by Micron without notice.

256Mb and 512Mb (256Mb/256Mb), P30-65nm

Features

Discrete and MCP Part Numbering Information

Devices are shipped from the factory with memory content bits erased to 1. For available options, such as pack-

ages or for further information, contact your Micron sales representative. Part numbers can be verified at www.mi-

cron.com. Feature and specification comparison by device type is available at www.micron.com/products. Con-

tact the factory for devices not found.

Table 1: Discrete Part Number Information

Part Number Category

Category Details

Package

JS = 56-lead TSOP, lead free

PC = 64-ball Easy BGA, lead-free

RC = 64-ball Easy BGA, leaded

28F = Micron Flash memory

256 = 256Mb

Product Line

Density

Product Family

Parameter Location

Lithography

P30 (VCC = 1.7 to 2.0V; VCCQ = 1.7 to 3.6V)

B/T = Bottom/Top parameter

F = 65nm

Features

*

1. The last digit is assigned randomly to cover packaging media, features, or other specific configuration infor-

mation. Sample part number: JS28F256P30BF*

Note:

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2

256Mb and 512Mb (256Mb/256Mb), P30-65nm

Features

Table 2: MCP Part Number Information

Part Number Category

Category Details

Package

RD = Micron MCP, leaded

PF = Micron MCP, lead-free

RC = 64-ball Easy BGA, leaded

PC = 64-ball Easy BGA, lead-free

48F = Micron Flash memory only

0 = No die

Product Line

Density

4 = 256Mb

Product Family

P = Micron Flash memory (P30)

0 = No die

IO Voltage and Chip Configuration

Z = Individual Chip Enables

V = Virtual Chip Enables

VCC = 1.7 to 2.0V; VCCQ = 1.7 to 3.6V

B/T = Bottom/Top parameter

Q = QUAD+

Parameter Location

Ballout

0 = Discrete

Lithography

Features

E = 65nm

*

1. The last digit is assigned randomly to cover packaging media, features, or other specific configuration infor-

mation. Sample part number: RD48F4400P0VB0E*

Note:

Table 3: Discrete and MCP Part Combinations

Package

Density

Packing Media

Tray

Boot Configuration ¹

Part Number

JS28F256P30BFE

JS

256Mb

B

Tape and Reel

Tray

JS28F256P30BFF

T

B

JS28F256P30TFE

PC

PF

256Mb

Tray

PC28F256P30BFE

PC28F256P30BFF

PC28F256P30TFE

PC48F4400P0VB0EE

PC48F4400P0VB0EF

PF48F4000P0ZBQEF

PF48F4000P0ZTQEJ

PF48F4400P0VBQEF

PF48F4400P0VBQEK

Tape and Reel

Tray

T

512Mb

(256Mb/256Mb)

Tray

B/T

Tape and Reel

Tray

256Mb

B

T

Tray

512Mb

(256Mb/256Mb)

Tray

B/T

Tape and Reel

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256Mb and 512Mb (256Mb/256Mb), P30-65nm

Features

Table 3: Discrete and MCP Part Combinations (Continued)

Package

Density

Packing Media

Tray

Boot Configuration ¹

Part Number

RC28F256P30BFE

RC28F256P30TFE

RC28F256P30TFF

RC48F4400P0VB0EJ

RC

256Mb

B

T

Tray

Tape and Reel

Tray

512Mb

(256Mb/256Mb)

B/T

RD

512Mb

Tray

RD48F4400P0VBQEJ

(256Mb/256Mb)

1. Bottom Boot/Top Boot = B/T

Note:

Table 4: OTP Feature Part Combinations

Package

Density

Packing Media

Boot Configuration ¹

Part Number

JS

PC

PF

–

B

–

256Mb

Tape and Reel

PC28F256P30BFR

–

RC

RD

1. This data sheet covers only standard parts. For OTP parts, contact your local Micron representative.

2. Bottom Boot/Top Boot = B/T

Notes:

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256Mb and 512Mb (256Mb/256Mb), P30-65nm

Features

Contents

Introduction .................................................................................................................................................... 9

Overview .......................................................................................................................................................... 9

Virtual Chip Enable Description ...................................................................................................................... 10

Memory Map ................................................................................................................................................. 12

Package Dimensions ....................................................................................................................................... 13

Pinouts and Ballouts ....................................................................................................................................... 17

Signals ........................................................................................................................................................... 20

Bus Operations ............................................................................................................................................... 23

Reads ......................................................................................................................................................... 23

Writes ........................................................................................................................................................ 23

Output Disable ........................................................................................................................................... 23

Standby ..................................................................................................................................................... 24

Reset .......................................................................................................................................................... 24

Device Command Codes ................................................................................................................................. 25

Device Command Bus Cycles .......................................................................................................................... 28

Read Operation .............................................................................................................................................. 30

Asynchronous Page-Mode Read .................................................................................................................. 30

Synchronous Burst-Mode Read ................................................................................................................... 30

Read Device Identifier ................................................................................................................................ 31

Read CFI .................................................................................................................................................... 31

Program Operation ......................................................................................................................................... 32

Word Programming .................................................................................................................................... 32

Buffered Programming ............................................................................................................................... 32

Buffered Enhanced Factory Programming ................................................................................................... 33

BEFP Requirements and Considerations .................................................................................................. 34

BEFP Setup Phase ................................................................................................................................... 34

BEFP Program/Verify Phase .................................................................................................................... 35

BEFP Exit Phase ..................................................................................................................................... 35

Program Suspend ....................................................................................................................................... 36

Program Resume ........................................................................................................................................ 36

Program Protection .................................................................................................................................... 37

Erase Operations ............................................................................................................................................ 38

Block Erase ................................................................................................................................................ 38

Blank Check ............................................................................................................................................... 38

Erase Suspend ............................................................................................................................................ 39

Erase Resume ............................................................................................................................................. 39

Erase Protection ......................................................................................................................................... 39

Security Modes ............................................................................................................................................... 40

Block Locking ............................................................................................................................................. 40

Lock Block ............................................................................................................................................. 40

Unlock Block .......................................................................................................................................... 40

Lock-Down Block ................................................................................................................................... 40

Block Lock Status ................................................................................................................................... 41

Block Locking During Suspend ............................................................................................................... 41

Selectable One-Time Programmable Blocks ................................................................................................. 42

Password Access ......................................................................................................................................... 42

Registers ........................................................................................................................................................ 43

Read Status Register ................................................................................................................................... 43

Clear Status Register ............................................................................................................................... 44

Read Configuration Register ....................................................................................................................... 44

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256Mb and 512Mb (256Mb/256Mb), P30-65nm

Features

Read Mode ............................................................................................................................................. 45

Latency Count ........................................................................................................................................ 45

End of Word Line (EOWL) Considerations ................................................................................................ 46

WAIT Signal Polarity and Functionality .................................................................................................... 47

WAIT Delay ............................................................................................................................................ 48

Burst Sequence ...................................................................................................................................... 49

Clock Edge ............................................................................................................................................. 49

Burst Wrap ............................................................................................................................................. 50

Burst Length .......................................................................................................................................... 50

One-Time-Programmable (OTP) Registers ................................................................................................... 50

Reading the OTP Registers ...................................................................................................................... 51

Programming the OTP Registers .............................................................................................................. 51

Locking the OTP Registers ....................................................................................................................... 52

Common Flash Interface ................................................................................................................................ 53

READ CFI Structure Output ........................................................................................................................ 53

Flowcharts ..................................................................................................................................................... 66

Power-Up and Power-Down ............................................................................................................................ 75

Reset Specifications ........................................................................................................................................ 75

Power Supply Decoupling ............................................................................................................................... 76

Absolute Maximum Ratings ............................................................................................................................ 77

Operating Conditions ..................................................................................................................................... 77

DC Current Characteristics ............................................................................................................................. 78

DC Voltage Characteristics .............................................................................................................................. 79

AC Test Conditions ......................................................................................................................................... 80

Capacitance ................................................................................................................................................... 81

AC Read Specifications ................................................................................................................................... 82

AC Write Specifications ................................................................................................................................... 89

Program and Erase Characteristics .................................................................................................................. 94

Revision History ............................................................................................................................................. 95

Rev. A – 10/12 ............................................................................................................................................. 95

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256Mb and 512Mb (256Mb/256Mb), P30-65nm

Features

List of Figures

Figure 1: 512Mb Easy BGA Block Diagram ...................................................................................................... 10

Figure 2: 512Mb QUAD+ Block Diagram ......................................................................................................... 11

Figure 3: P30-65nm, 256Mb and 512Mb Memory Map .................................................................................... 12

Figure 4: 56-Pin TSOP – 14mm x 20mm .......................................................................................................... 13

Figure 5: 64-Ball Easy BGA – 10mm x 13mm x 1.2mm ...................................................................................... 14

Figure 6: 88-Ball QUAD+ – 8mm x 11mm x 1.0mm .......................................................................................... 15

Figure 7: 88-Ball QUAD+ – 8mm x 11mm x 1.2mm .......................................................................................... 16

Figure 8: 56-Lead TSOP Pinout (256Mb) ......................................................................................................... 17

Figure 9: 64-Ball Easy BGA Ballout (256Mb, 512Mb) ........................................................................................ 18

Figure 10: QUAD+ MCP Ballout ..................................................................................................................... 19

Figure 11: Example VPP Supply Connections .................................................................................................. 37

Figure 12: Block Locking State Diagram .......................................................................................................... 41

Figure 13: First Access Latency Count ............................................................................................................ 45

Figure 14: Example Latency Count Setting Using Code 3 ................................................................................. 46

Figure 15: End of Wordline Timing Diagram ................................................................................................... 47

Figure 16: OTP Register Map .......................................................................................................................... 51

Figure 17: Word Program Procedure ............................................................................................................... 66

Figure 18: Buffer Program Procedure .............................................................................................................. 67

Figure 19: Buffered Enhanced Factory Programming (BEFP) Procedure ........................................................... 68

Figure 20: Block Erase Procedure ................................................................................................................... 69

Figure 21: Program Suspend/Resume Procedure ............................................................................................ 70

Figure 22: Erase Suspend/Resume Procedure ................................................................................................. 71

Figure 23: Block Lock Operations Procedure ................................................................................................... 72

Figure 24: OTP Register Programming Procedure ............................................................................................ 73

Figure 25: Status Register Procedure .............................................................................................................. 74

Figure 26: Reset Operation Waveforms ........................................................................................................... 76

Figure 27: AC Input/Output Reference Timing ................................................................................................ 80

Figure 28: Transient Equivalent Load Circuit .................................................................................................. 80

Figure 29: Clock Input AC Waveform .............................................................................................................. 80

Figure 30: Asynchronous Single Word Read (ADV# LOW) ................................................................................ 84

Figure 31: Asynchronous Single Word Read (ADV# Latch) ............................................................................... 84

Figure 32: Asynchronous Page Mode Read ...................................................................................................... 85

Figure 33: Synchronous Single Word Array or Nonarray Read .......................................................................... 86

Figure 34: Continuous Burst Read with Output Delay (ADV# LOW) ................................................................. 87

Figure 35: Synchronous Burst Mode 4-Word Read ........................................................................................... 88

Figure 36: Write to Write Timing .................................................................................................................... 90

Figure 37: Asynchronous Read to Write Timing ............................................................................................... 90

Figure 38: Write to Asynchronous Read Timing ............................................................................................... 91

Figure 39: Synchronous Read to Write Timing ................................................................................................ 92

Figure 40: Write to Synchronous Read Timing ................................................................................................ 93

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256Mb and 512Mb (256Mb/256Mb), P30-65nm

Features

List of Tables

Table 1: Discrete Part Number Information ...................................................................................................... 2

Table 2: MCP Part Number Information ........................................................................................................... 3

Table 3: Discrete and MCP Part Combinations .................................................................................................. 3

Table 4: OTP Feature Part Combinations .......................................................................................................... 4

Table 5: Virtual Chip Enable Truth Table for 512Mb (QUAD+ Package) ............................................................. 10

Table 6: Virtual Chip Enable Truth Table for 512Mb (Easy BGA Packages) ........................................................ 10

Table 7: TSOP and Easy BGA Signal Descriptions ............................................................................................ 20

Table 8: QUAD+ SCSP Signal Descriptions ...................................................................................................... 21

Table 9: Bus Operations ................................................................................................................................. 23

Table 10: Command Codes and Definitions .................................................................................................... 25

Table 11: Command Bus Cycles ..................................................................................................................... 28

Table 12: Device Identifier Information .......................................................................................................... 31

Table 13: Device ID codes .............................................................................................................................. 31

Table 14: BEFP Requirements ........................................................................................................................ 34

Table 15: BEFP Considerations ...................................................................................................................... 34

Table 16: Status Register Description .............................................................................................................. 43

Table 17: Read Configuration Register ............................................................................................................ 44

Table 18: Latency Count and Frequency Support ............................................................................................ 46

Table 19: End of Wordline Data and WAIT State Comparison ........................................................................... 47

Table 20: WAIT Functionality Table ................................................................................................................ 48

Table 21: Burst Sequence Word Ordering ........................................................................................................ 49

Table 22: Example of CFI Output (x16 device) as a Function of Device and Mode ............................................. 53

Table 23: CFI Database: Addresses and Sections ............................................................................................. 54

Table 24: CFI ID String ................................................................................................................................... 54

Table 25: System Interface Information .......................................................................................................... 55

Table 26: Device Geometry ............................................................................................................................ 56

Table 27: Block Region Map Information ........................................................................................................ 56

Table 28: Primary Vendor-Specific Extended Query ........................................................................................ 57

Table 29: Optional Features Field ................................................................................................................... 58

Table 30: One Time Programmable (OTP) Space Information .......................................................................... 58

Table 31: Burst Read Information ................................................................................................................... 59

Table 32: Partition and Block Erase Region Information .................................................................................. 60

Table 33: Partition Region 1 Information: Top and Bottom Offset/Address ....................................................... 61

Table 34: Partition Region 1 Information ........................................................................................................ 61

Table 35: Partition Region 1: Partition and Erase Block Map Information ......................................................... 64

Table 36: CFI Link Information ...................................................................................................................... 65

Table 37: Additional CFI Link Field ................................................................................................................. 65

Table 38: Power and Reset .............................................................................................................................. 75

Table 39: Absolute Maximum Ratings ............................................................................................................. 77

Table 40: Operating Conditions ...................................................................................................................... 77

Table 41: DC Current Characteristics .............................................................................................................. 78

Table 42: DC Voltage Characteristics .............................................................................................................. 79

Table 43: Test Configuration: Worst Case Speed Condition .............................................................................. 80

Table 44: Capacitance .................................................................................................................................... 81

Table 45: AC Read Specifications .................................................................................................................... 82

Table 46: AC Write Specifications ................................................................................................................... 89

Table 47: Program and Erase Specifications .................................................................................................... 94

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256Mb and 512Mb (256Mb/256Mb), P30-65nm

Introduction

This document provides information about the Micron Flash memory (P30-65nm)

product and describes its features, operations, and specifications.

The Micron Flash memory (P30-65nm) is the latest generation of flash memory devices.

P30-65nm device will be offered in 64Mb up through 2Gb densities. This document cov-

ers specifically 256Mb and 512Mb (256Mb/256Mb) product information. Benefits in-

clude more density in less space, high-speed interface device, and support for code and

data storage. Features include high-performance synchronous-burst read mode, fast

asynchronous access times, low power, flexible security options, and three industry-

standard package choices. The P30-65nm product family is manufactured using Micron

65nm process technology.

Overview

This section provides an overview of the features and capabilities of the P30-65nm.

The P30-65nm family devices provides high performance at low voltage on a 16-bit data

bus. Individually erasable memory blocks are sized for optimum code and data storage.

Upon initial power up or return from reset, the device defaults to asynchronous page-

mode read. Configuring the Read Configuration Register enables synchronous burst-

mode reads. In synchronous burst mode, output data is synchronized with a user-sup-

plied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization.

In addition to the enhanced architecture and interface, the device incorporates technol-

ogy that enables fast factory program and erase operations. Designed for low-voltage

systems, the P30-65nm supports read operations with V_CCat 1.8 V, and erase and pro-

gram operations with V_PPat 1.8 V or 9.0 V. Buffered Enhanced Factory Programming

(BEFP) provides the fastest flash array programming performance with V_PPat 9.0 V,

which increases factory throughput. With V_PPat 1.8 V, VCC and VPP can be tied together

for a simple, ultra low power design. In addition to voltage flexibility, a dedicated VPP

connection provides complete data protection when V_PP≤ V_PPLK

.

A Command User Interface (CUI) is the interface between the system processor and all

internal operations of the device. An internal Write State Machine (WSM) automatically

executes the algorithms and timings necessary for block erase and program. A Status

Register indicates erase or program completion and any errors that may have occurred.

An industry-standard command sequence invokes program and erase automation.

Each erase operation erases one block. The Erase Suspend feature allows system soft-

ware to pause an erase cycle to read or program data in another block. Program Sus-

pend allows system software to pause programming to read other locations. Data is pro-

grammed in word increments (16 bits).

The P30-65nm protection register allows unique flash device identification that can be

used to increase system security. The individual Block Lock feature provides zero-laten-

cy block locking and unlocking. The P30-65nm device includes enhanced protection via

Password Access; this new feature allows write and/or read access protection of user-

defined blocks. In addition, the P30-65nm device also provides the full-device One-

Time Programmable (OTP) security feature.

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256Mb and 512Mb (256Mb/256Mb), P30-65nm

Virtual Chip Enable Description

The P30-65nm 512Mb devices employ a virtual chip enable feature, which combines

two 256Mb die with a common chip enable, F1-CE# for QUAD+ packages, or CE# for

Easy BGA Packages. The maximum address bit is then used to select between the die

pair with F1-CE#/CE# asserted depending upon the package option used. When chip

enable is asserted and the maximum address bit is LOW (V_IL), the lower parameter die

is selected; when chip enable is asserted and the maximum address bit is HIGH (V_IH),

the upper parameter die is selected (see the tables below).

Table 5: Virtual Chip Enable Truth Table for 512Mb (QUAD+ Package)

Die Selected

Lower Param Die

Upper Param Die

F1-CE#

A24

L

H

Table 6: Virtual Chip Enable Truth Table for 512Mb (Easy BGA Packages)

Die Selected

Lower Param Die

Upper Param Die

CE#

A25

L

H

Figure 1: 512Mb Easy BGA Block Diagram

Easy BGA 512Mb (Dual Die) Top/Bottom

Parameter Configuration

Top Parameter Die

256Mb

CE#

WP#

OE#

RST#

V

CC

V

WE#

CLK

PP

V

CCQ

Bottom Parameter Die

256Mb

V

ADV#

SS

DQ[15:0]

WAIT

A[MAX:1]

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256Mb and 512Mb (256Mb/256Mb), P30-65nm

Virtual Chip Enable Description

Figure 2: 512Mb QUAD+ Block Diagram

QUAD+ 512Mb (Dual Die) Top/Bottom

Parameter Configuration

Top Parameter Die

256Mb

F1-CE#

WP#

OE#

RST#

V

CC

V

WE#

CLK

PP

V

CCQ

Bottom Parameter Die

256Mb

V

ADV#

SS

DQ[15:0]

WAIT

A[MAX:0]

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256Mb and 512Mb (256Mb/256Mb), P30-65nm

Memory Map

Figure 3: P30-65nm, 256Mb and 512Mb Memory Map

A[24:1] 256Mb, Easy BGA, TSOP

A[23:0] 256Mb, Quad+

A[24:1] 256Mb, Easy BGA, TSOP

A[23:0] 256Mb, Quad+

FF0000 - FFFFFF

FFC000 - FFFFFF

FF8000 - FFBFFF

FF4000 - FF7FFF

FF0000 - FF3FFF

FE0000 - FEFFFF

16 KWord Block 258

16 KWord Block 257

16 KWord Block 256

16 KWord Block 255

64 KWord Block 254

64 KWord Block 258

7F0000 - 7FFFFF

3F0000 - 3FFFFF

64 KWord Block 130

64 KWord Block 66

256Mb

020000 - 02FFFF

010000 - 01FFFF

00C000 - 00FFFF

008000 - 00BFFF

004000 - 007FFF

000000 - 003FFF

64 KWord Block 5

64 KWord Block 4

16 KWord Block 3

16 KWord Block 2

16 KWord Block 1

16 KWord Block 0

010000 - 01FFFF

000000 - 00FFFF

64 KWord Block 1

64 KWord Block 0

Bottom Boot 256Mb, World-Wide x16 Mode

Top Boot 256Mb, World-Wide x16 Mode

A[25:1] 512Mb (256Mb/256Mb), Easy BGA, TSOP

A[24:0] 512Mb (256Mb/256Mb), Quad+

1FFC000 - 1FFFFFF

16 KWord Block 517

16 KWord Block 516

16 KWord Block 515

16 KWord Block 514

64 KWord Block 513

64 KWord Block 512

1FF8000 - 1FFBFFF

1FF4000 - 1FF7FFF

1FF0000 - 1FF3FFF

1FE0000 - 1FEFFFF

1FD0000 - 1FDFFFF

512Mb (256Mb/256Mb)

020000 - 02FFFF

010000 - 01FFFF

00C000 - 00FFFF

008000 - 00BFFF

004000 - 007FFF

000000 - 003FFF

64 KWord Block 5

64 KWord Block 4

16 KWord Block 3

16 KWord Block 2

16 KWord Block 1

16 KWord Block 0

512Mb (256Mb/256Mb), World Wide x16 Mode

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256Mb and 512Mb (256Mb/256Mb), P30-65nm

Package Dimensions

Figure 4: 56-Pin TSOP – 14mm x 20mm

20 ±0.2

18.4 ±0.2

0.995 ±0.03

Pin #1 index

See notes 2

See note 2

0.5 TYP

14.00 ±0.2

0.22 ±0.05

See note 2

0.25 ±0.1

0.15 ±0.05

0.10

+2°

3°

-3°

See Detail A

Seating

plane

1.20 MAX

0.05 MIN

0.60 ±0.10

Detail A

1. All dimensions are in millimeters. Drawing not to scale.

Notes:

2. One dimple on package denotes pin 1; if two dimples, then the larger dimple denotes

pin 1. Pin 1 will always be in the upper left corner of the package, in reference to the

product mark.

3. For the lead width value of 0.22 ±0.05, there is also a legacy value of 0.15 ±0.05.

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256Mb and 512Mb (256Mb/256Mb), P30-65nm

Package Dimensions

Figure 5: 64-Ball Easy BGA – 10mm x 13mm x 1.2mm

0.78 TYP

0.25 MIN

Seating

plane

0.1

1.00 TYP

Ball A1 ID

1.5 ±0.1

64X Ø0.43 ±0.1

Ball A1 ID

8

7

6

5

4

3

2

1

3.0 ±0.1

A

B

C

D

E

13 ±0.1

F

1.00 TYP

G

H

10 ±0.1

1.20 MAX

1. All dimensions are in millimeters. Drawing not to scale.

Note:

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256Mb and 512Mb (256Mb/256Mb), P30-65nm

Package Dimensions

Figure 6: 88-Ball QUAD+ – 8mm x 11mm x 1.0mm

1.20 ±0.10

1.10 ±0.10

A 1 Index

Mark

1

2

3

4

5

6

7

8

7

6

5

4

3

2

1

A

B

C

D

E

A

B

C

D

E

F

11.00 ±0.10

0.80 TYP

G

H

J

H

J

K

L

M

0.35 ±0.05

8.00 ±0.10

Bottom View - Ball Up

1.00 MAX

Top View - Ball Down

0.740 TYP

0.20 MIN

0.10 MAX

1. All dimensions are in millimeters. Drawing not to scale.

Note:

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Package Dimensions

Figure 7: 88-Ball QUAD+ – 8mm x 11mm x 1.2mm

1.20 ±0.10

1.10 ±0.10

A 1 Index

Mark

1

2

3

4

5

6

7

8

7

6

5

4

3

2

1

A

B

C

D

E

A

B

C

D

E

F

11.00 ±0.10

0.80 TYP

G

H

J

H

J

K

L

M

0.375 ±0.050

8.00 ±0.10

Bottom View - Ball Up

1.20 MAX

Top View - Ball Down

0.860 TYP

0.20 MIN

0.10 MAX

1. All dimensions are in millimeters. Drawing not to scale.

Note:

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256Mb and 512Mb (256Mb/256Mb), P30-65nm

Pinouts and Ballouts

Figure 8: 56-Lead TSOP Pinout (256Mb)

WAIT

A17

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

A 16

A 15

DQ15

DQ7

DQ14

DQ 6

DQ13

DQ5

DQ12

DQ4

ADV#

CLK

A 14

A 13

A 12

A 11

A 10

A 9

A 23

A 22

A 21

VSS

RFU

WE #

WP #

A 20

A 19

A 18

A 8

A 7

A 6

A 5

A 4

A 3

A 2

A 24

RFU

VSS

56-Lead TSOP Pinout

14mm x 20mm

RST#

VPP

DQ11

DQ 3

DQ10

DQ 2

VCCQ

DQ 9

DQ1

DQ 8

DQ 0

VCC

Top View

OE#

VSS

CE#

A 1

1. A1 is the least significant address bit.

Notes:

2. A24 is valid for 256Mb densities; otherwise, it is a no connect (NC).

3. No Internal Connection on Pin 13; it may be driven or floated. For legacy designs, it is

VCC pin and can be tied to Vcc.

4. One dimple on package denotes Pin 1 which will always be in the upper left corner of

the package, in reference to the product mark.

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Pinouts and Ballouts

Figure 9: 64-Ball Easy BGA Ballout (256Mb, 512Mb)

5

8

5

1

2

3

4

6

7

6

4

3

2

1

A

B

C

D

A

B

C

D

E

A1

A6

A8

VPP A13 VCC A18 A22

A22 A18 VCC A13 VPP A8

RFU A19 A25 A14 CE# A9

A21 A20 WP# A15 A12 A10

A17 A16 VCCQ VCCQ RST# A11

A6

VSS

A7

A1

A2

A3

A4

A2 VSS

A9 CE# A14 A25 A19 RFU

A10 A12 A15 WP# A20 A21

A11 RST# VCCQ VCCQ A16 A17

A3

A4

A7

A5

E

F

DQ8 DQ1 DQ9 DQ3 DQ4 CLK DQ15 RFU

RFU DQ0 DQ10 DQ11 DQ12 ADV# WAIT OE#

A23 RFU DQ2 VCCQ DQ5 DQ6 DQ14 WE#

RFU DQ15 CLK DQ4 DQ3 DQ9 DQ1 DQ8

OE# WAIT ADV# DQ12 DQ11 DQ10 DQ0 RFU

WE# DQ14 DQ6 DQ5 VCCQ DQ2 RFU A23

F

G

H

G

H

RFU VSS VCC VSS DQ13 VSS DQ7 A24

A24 DQ7 VSS DQ13 VSS VCC VSS RFU

Easy BGA

Top View - Ball side down

Bottom View - Ball side up

1. A1 is the least significant address bit.

Notes:

2. A24 is valid for 256Mb densities and above; otherwise, it is a no connect (NC).

3. A25 is valid for 512-Mbit densities; otherwise, it is a no connect.

4. One dimple on package denotes A1 Pin which will always be in the upper left corner of

the package, in reference to the product mark.

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Pinouts and Ballouts

Figure 10: QUAD+ MCP Ballout

Pin 1

1

2

3

4

5

6

7

8

A

B

C

D

E

F

DU

A4

DU

Depop

A19

Depop

VSS

Depop

VCC

RFU

ADV#

WE#

DQ5

DQ12

DQ4

RFU

VSS

Depop

VCC

CLK

RFU

A20

DU

A

B

C

D

E

F

A18

RFU

A17

A7

A21

A22

A9

A11

A5

A23

VSS

A12

A3

A24

VPP

A13

A2

RFU

DQ2

DQ1

DQ9

RFU

VCCQ

WP#

RST#

DQ10

DQ3

DQ11

RFU

VCC

A10

A14

WAIT

DQ7

DQ15

VCCQ

VSS

A15

A1

A6

A8

A16

G

H

J

A0

DQ8

DQ0

OE#

RFU

VSS

DQ13

DQ14

DQ6

VCC

VSS

F2-CE#

F2-OE#

VCCQ

RFU

VSS

G

H

J

RFU

F1-CE#

VSS

K

L

K

L

M

DU

1

DU

2

Depop

3

Depop

4

Depop

5

Depop

6

DU

7

DU

8

M

Top View - Ball Side Down

Control Signals

De-Populated Ball

Reserved for Future Use

Do Not Use

Address

Data

Power/Ground

Legends :

1. A23 is valid for 256Mb densities and above; otherwise, it is a no connect.

2. A24 is valid for 512Mb densities and above; otherwise, it is a no connect.

3. F2-CE# and F2-OE# are no connect for all densities.

4. A0 is LSB for Address.

Notes:

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Signals

Table 7: TSOP and Easy BGA Signal Descriptions

Symbol

Type

Name and Function

A[MAX:1]

Input

Address inputs: Device address inputs. 256Mb: A[24:1]; 512Mb: A[25:1]. Note: The virtual

selection of the 256Mb top parameter die in the dual-die 51Mb configuration is accom-

plished by setting A25 HIGH (V_IH).

Note: The active address pins unused in design should not be left floating; tie them to

V_CCQor V_SSaccording to specific design requirements.

DQ[15:0]

ADV#

Input/Output Data input/output: Inputs data and commands during write cycles; outputs data during

memory, status register, protection register, and read configuration register reads. Data

balls float when the CE# or OE# are de-asserted. Data is internally latched during writes.

Input

Address valid: Active LOW input. During synchronous READ operations, addresses are

latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# LOW, which-

ever occurs first.

In asynchronous mode, the address is latched when ADV# goes HIGH or continuously flows

through if ADV# is held LOW.

Note: Designs not using ADV# must tie it to V_SSto allow addresses to flow through.

CE#

CLK

Input

Chip enable: Active LOW input. CE# LOW selects the associated flash memory die. When

asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are ac-

tive. When de-asserted, the associated flash die is deselected, power is reduced to standby

levels, data and wait outputs are placed in High-Z state.

Note: Chip enable must be driven HIGH when device is not in use.

Clock: Synchronizes the device with the system bus frequency in synchronous-read mode.

During synchronous READs, addresses are latched on the rising edge of ADV#, or on the

next valid CLK edge with ADV# LOW, whichever occurs first.

Note:Designs not using CLK for synchronous read mode must tie it to V_CCQor V_SS.

OE#

Input

Output enable: Active LOW input. OE# LOW enables the device’s output data buffers

during read cycles. OE# HIGH places the data outputs and WAIT in High-Z.

RST#

Reset: Active LOW input. RST# resets internal automation and inhibits WRITE operations.

This provides data protection during power transitions. RST# HIGH enables normal opera-

tion. Exit from reset places the device in asynchronous read array mode.

WAIT

Output

Wait: Indicates data valid in synchronous array or non-array burst reads. Read Configura-

tion Register bit 10 (RCR.10, WT) determines its polarity when asserted. This signal's active

output is V_OLor V_OHwhen CE# and OE# are V_IL. WAIT is High-Z if CE# or OE# is V_IH.

• In synchronous array or non-array read modes, this signal indicates invalid data when as-

serted and valid data when de-asserted.

• In asynchronous page mode, and all write modes, this signal is de-asserted.

WE#

WP#

Input

Write enable: Active LOW input. WE# controls writes to the device. Address and data are

latched on the rising edge of WE# or CE#, whichever occurs first.

Write protect: Active LOW input. WP# LOW enables the lock-down mechanism. Blocks in

lock-down cannot be unlocked with the Unlock command. WP# HIGH overrides the lock-

down function enabling blocks to be erased or programmed using software commands.

Note: Designs not using WP# for protection could tie it to V_CCQor V_SSwithout additional

capacitor.

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Signals

Table 7: TSOP and Easy BGA Signal Descriptions (Continued)

Symbol

Type

Name and Function

V_PP

Power/Input Erase and program power: A valid voltage on this pin allows erasing or programming.

Memory contents cannot be altered when V_PP≤ V_PPLK. Block erase and program at invalid

V_PPvoltages should not be attempted.

Set V_PP= V_PPLfor in-system PROGRAM and ERASE operations. To accommodate resistor or

diode drops from the system supply, the V_IHlevel of V_PPcan be as low as V_PPL,min. V_PPmust

remain above V_PPL,minto perform in-system flash modification. V_PPmay be 0V during READ

operations.

V_PPHcan be applied to main blocks for 1000 cycles maximum and to parameter blocks for

2500 cycles. V_PPcan be connected to 9V for a cumulative total not to exceed 80 hours. Ex-

tended use of this pin at 9V may reduce block cycling capability.

V_CC

Power

Device core power supply: Core (logic) source voltage. Writes to the flash array are in-

hibited when V_CC≤ V_LKO. Operations at invalid V_CCvoltages should not be attempted.

V_CCQ

V_SS

Power

—

Output power supply: Output-driver source voltage.

Ground: Connect to system ground. Do not float any V_SSconnection.

RFU

Reserved for future use: Reserved by Micron for future device functionality and en-

hancement. These should be treated in the same way as a Do Not Use (DNU) signal.

DU

NC

—

Do not use: Do not connect to any other signal, or power supply; must be left floating.

No connect: No internal connection; can be driven or floated.

Table 8: QUAD+ SCSP Signal Descriptions

Symbol

Type

Name and Function

A[MAX:0]

Input

Address inputs: Device address inputs. 256Mb: A[23:0]; 512Mb: A[24:0]. Note: The virtual

selection of the 256Mb top parameter die in the dual-die 512Mb configuration is accom-

plished by setting A24 HIGH (V_IH).

Note: The address pins unused in design should not be left floating; tie them to V_CCQor

V_SSaccording to specific design requirements.

DQ[15:0]

ADV#

Input/Output Data input/output: Inputs data and commands during write cycles; outputs data during

memory, status register, protection register, and read configuration register reads. Data

balls float when the CE# or OE# are de-asserted. Data is internally latched during writes.

Input

Address valid: Active LOW input. During synchronous READ operations, addresses are

latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# LOW, which-

ever occurs first.

In asynchronous mode, the address is latched when ADV# goes HIGH or continuously flows

through if ADV# is held LOW.

Note: Designs not using ADV# must tie it to V_SSto allow addresses to flow through.

F1-CE#

Input

Flash chip enable: Active LOW input. CE# LOW selects the associated flash memory die.

When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers

are active. When de-asserted, the associated flash die is deselected, power is reduced to

standby levels, data and wait outputs are placed in High-Z state.

Note: Chip enable must be driven HIGH when device is not in use.

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Signals

Table 8: QUAD+ SCSP Signal Descriptions (Continued)

Symbol

Type

Name and Function

CLK

Input

Clock: Synchronizes the device with the system bus frequency in synchronous-read mode.

During synchronous READ operations, addresses are latched on the rising edge of ADV#,

or on the next valid CLK edge with ADV# LOW, whichever occurs first.

Note: Designs not using CLK for synchronous read mode must tie it to V_CCQor V_SS.

F1-OE#

RST#

Input

Output enable: Active LOW input. OE# LOW enables the device’s output data buffers

during read cycles. OE# HIGH places the data outputs and wait in High-Z.

Reset: Active LOW input. RST# resets internal automation and inhibits WRITE operations.

This provides data protection during power transitions. RST# HIGH enables normal opera-

tion. Exit from reset places the device in asynchronous read array mode.

WAIT

Output

Wait: Indicates data valid in synchronous array or non-array burst reads. Read configura-

tion register bit 10 (RCR.10, WT) determines its polarity when asserted. The active output is

V_OLor V_OHwhen CE# and OE# are V_IL. WAIT is High-Z if CE# or OE# is V_IH.

• In synchronous array or non-array read modes, WAIT indicates invalid data when asser-

ted and valid data when de-asserted.

• In asynchronous page mode, and all write modes, WAIT is de-asserted.

WE#

WP#

Input

Write enable: Active LOW input. WE# controls writes to the device. Address and data are

latched on the rising edge of WE# or CE#, whichever occurs first.

Write protect: Active LOW input. WP# LOW enables the lock-down mechanism. Blocks in

lock-down cannot be unlocked with the UNLOCK command. WP# HIGH overrides the lock-

down function enabling blocks to be erased or programmed using software commands.

Note: Designs not using WP# for protection could tie it to V_CCQor V_SSwithout additional

capacitor.

V_PP

Power/lnput Erase and program power: A valid voltage on this pin allows erasing or programming.

Memory contents cannot be altered when V_PP≤ V_PPLK. Block erase and program at invalid

V_PPvoltages should not be attempted.

Set V_PP= V_PPLfor in-system PROGRAM and ERASE operations. To accommodate resistor or

diode drops from the system supply, the V_IHlevel of V_PPcan be as low as V_PPL,min. V_PPmust

remain above V_PPL,minto perform in-system flash modification. V_PPmay be 0V during READ

operations.

V_PPHcan be applied to main blocks for 1000 cycles maximum and to parameter blocks for

2500 cycles. V_PPcan be connected to 9V for a cumulative total not to exceed 80 hours. Ex-

tended use of this pin at 9V may reduce block cycling capability.

V_CC

Power

Device core power supply: Core (logic) source voltage. Writes to the flash array are in-

hibited when V_CC≤ V_LKO. Operations at invalid V_CCvoltages should not be attempted.

V_CCQ

V_SS

Power

—

Output power supply: Output driver source voltage.

Ground: Connect to system ground. Do not float any V_SSconnection.

RFU

Reserved for future use: Reserved by Micron for future device functionality and en-

hancement. These should be treated in the same way as a Do Not Use (DNU) signal.

DU

NC

—

Do not use: Do not connect to any other signal, or power supply; must be left floating.

No connect: No internal connection; can be driven or floated.

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Bus Operations

CE# low and RST# high enable device read operations. The device internally decodes

upper address inputs to determine the accessed block. ADV# low opens the internal ad-

dress latches. OE# low activates the outputs and gates selected data onto the I/O bus.

In asynchronous mode, the address is latched when ADV# goes high or continuously

flows through if ADV# is held low. In synchronous mode, the address is latched by the

first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE# and

RST# must be V_IH; CE# must be V_IL).

Bus cycles to/from the P30-65nm device conform to standard microprocessor bus oper-

ations. The Bus Operations table shows the bus operations and the logic levels that

must be applied to the device control signal inputs.

Table 9: Bus Operations

Bus Operation

RST#

V_IH

V_IL

CLK

ADV#

CE#

L

OE#

L

WE#

H

WAIT

Deasserted

Driven

DQ[15:0] Notes

Read

Asynchronous

Synchronous

Write

X

L

Output

Input

1

Running

L

H

X

L

H

L

High-Z

1, 2

1

Output Disable

X

L

H

High-Z

Standby

Reset

H

X

High-Z

1

X

High-Z

1, 3

1. X = Don’t Care (H or L).

Notes:

2. Refer to the Command Bus Cycles table for valid DQ[15:0] during a write operation.

3. RST# must be at V_SS± 0.2 V to meet the maximum specified power-down current.

Reads

Writes

To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are

asserted. CE# is the device-select control. When asserted, it enables the flash memory

device. OE# is the data-output control. When asserted, the addressed flash memory da-

ta is driven onto the I/O bus.

To perform a write operation, both CE# and WE# are asserted while RST# and OE# are

deasserted. During a write operation, address and data are latched on the rising edge of

WE# or CE#, whichever occurs first. The Command Bus Cycles table shows the bus cycle

sequence for each of the supported device commands, while the Command Codes and

Definitions table describes each command.

Note: Write operations with invalid V_CCand/or V_PPvoltages can produce spurious re-

sults and should not be attempted.

Output Disable

When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-im-

pedance (High-Z) state, WAIT is also placed in High-Z.

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Bus Operations

Standby

When CE# is deasserted the device is deselected and placed in standby, substantially re-

ducing power consumption. In standby, the data outputs are placed in High-Z, inde-

pendent of the level placed on OE#. Standby current, I_CCS, is the average current meas-

ured over any 5 ms time interval, 5μs after CE# is deasserted. During standby, average

current is measured over the same time interval 5μs after CE# is deasserted.

When the device is deselected (while CE# is deasserted) during a program or erase oper-

ation, it continues to consume active power until the program or erase operation is

completed.

Reset

As with any automated device, it is important to assert RST# when the system is reset.

When the system comes out of reset, the system processor attempts to read from the

flash memory if it is the system boot device. If a CPU reset occurs with no flash memory

reset, improper CPU initialization may occur because the flash memory may be provid-

ing status information rather than array data. Flash memory devices from Micron allow

proper CPU initialization following a system reset through the use of the RST# input.

RST# should be controlled by the same low-true reset signal that resets the system CPU.

After initial power-up or reset, the device defaults to asynchronous Read Array mode,

and the Status Register is set to 0x80. Asserting RST# de-energizes all internal circuits,

and places the output drivers in High-Z. When RST# is asserted, the device shuts down

the operation in progress, a process which takes a minimum amount of time to com-

plete. When RST# has been deasserted, the device is reset to asynchronous Read Array

state.

When device returns from a reset (RST# deasserted), a minimum wait is required before

the initial read access outputs valid data. Also, a minimum delay is required after a reset

before a write cycle can be initiated. After this wake-up interval passes, normal opera-

tion is restored.

Note: If RST# is asserted during a program or erase operation, the operation is termina-

ted and the memory contents at the aborted location (for a program) or block (for an

erase) are no longer valid, because the data may have been only partially written or

erased.

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Device Command Codes

The system CPU provides control of all in-system READ, WRITE, and ERASE operations

of the device via the system bus. The device manages all block-erase and word-program

algorithms.

Device commands are written to the command user interface (CUI) to control all flash

memory device operations. The CUI does not occupy an addressable memory location;

it is the mechanism through which the Flash device is controlled.

Note: For 512Mb (256Mb/256Mb) device, all the setup commands should be re-issued

to the device when a different die is selected.

Table 10: Command Codes and Definitions

Mode

Code

Device Mode

Read Array

Description

Read

0xFF

Places the device in Read Array mode. Array data is output on

DQ[15:0].

0x70

0x90

Read Status Register Places the device in Read Status Register mode. The device enters this

mode after a program or erase command is issued. Status Register data

is output on DQ[7:0].

Read Device ID or

Places device in Read Device Identifier mode. Subsequent reads output

Read Configuration manufacturer/device codes, Configuration Register data, Block Lock

Register (RCR)

Read CFI

status, or Protection Register data on DQ[15:0].

0x98

0x50

0x40

Places the device in Read CFI mode. Subsequent reads output Common

Flash Interface information on DQ[7:0].

Clear Status Register The device sets Status Register error bits. The Clear Status Register com-

mand is used to clear the SR error bits.

Write

Word Program Setup First cycle of a 2-cycle programming command; prepares the CUI for a

write operation. On the next write cycle, the address and data are

latched and the device executes the programming algorithm at the ad-

dressed location. During program operations, the device responds only

to Read Status Register and Program Suspend commands. CE# or OE#

must be toggled to update the Status Register in asynchronous read.

CE# or ADV# must be toggled to update the Status Register Data for

synchronous Non-array reads. The Read Array command must be issued

to read array data after programming has finished.

0xE8

0xD0

Buffered Program

This command loads a variable number of words up to the buffer size

of 512 words onto the program buffer.

Buffered Program

Confirm

The confirm command is issued after the data streaming for writing in-

to the buffer is completed. The device then performs the Buffered Pro-

gram algorithm, writing the data from the buffer to the Flash memory

array.

0x80

0xD0

BEFP Setup

First cycle of a 2-cycle command; initiates Buffered Enhanced Factory

Program mode (BEFP). The CUI then waits for the BEFP Confirm com-

mand, 0xD0, that initiates the BEFP algorithm. All other commands are

ignored when BEFP mode begins.

BEFP Confirm

If the previous command was BEFP Setup (0x80), the CUI latches the ad-

dress and data, and prepares the device for BEFP mode.

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Device Command Codes

Table 10: Command Codes and Definitions (Continued)

Mode

Code

Device Mode

Description

Erase

0x20

Block Erase Setup

First cycle of a 2-cycle command; prepares the CUI for a block-erase op-

eration. The device performs the erase algorithm on the block ad-

dressed by the Erase Confirm command. If the next command is not the

Erase Confirm (0xD0) command, the CUI sets Status Register bits SR.4

and SR.5, and places the device in read status register mode.

0xD0

0xB0

Block Erase Confirm If the first command was Block Erase Setup (0x20), the CUI latches the

address and data, and the device erases the addressed block. During

block-erase operations, the device responds only to Read Status Regis-

ter and Erase Suspend commands. CE# or OE# must be toggled to up-

date the Status Register in asynchronous read. CE# or ADV# must be

toggled to update the Status Register Data for synchronous Non-array

reads.

Suspend

Program or Erase

Suspend

This command issued to any device address initiates a suspend of the

currently-executing program or block erase operation. The Status Reg-

ister indicates successful suspend operation by setting either SR.2 (pro-

gram suspended) or SR.6 (erase suspended), along with SR.7 (ready).

The Write State Machine remains in the suspend mode regardless of

control signal states (except for RST# asserted).

0xD0

0x60

Suspend Resume

Block lock Setup

This command issued to any device address resumes the suspended

program or block-erase operation.

Block Locking/

Unlocking

First cycle of a 2-cycle command; prepares the CUI for block lock config-

uration changes. If the next command is not Block Lock (0x01), Block

Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets Status Register

bits SR.5 and SR.4, indicating a command sequence error.

0x01

0xD0

Block lock

If the previous command was Block Lock Setup (0x60), the addressed

block is locked.

Block Unlock

If the previous command was Block Lock Setup (0x60), the addressed

block is unlocked. If the addressed block is in a lock-down state, the

operation has no effect.

0x2F

Block Lock-Down

If the previous command was Block Lock Setup (0x60), the addressed

block is locked down.

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Device Command Codes

Table 10: Command Codes and Definitions (Continued)

Mode

Code

Device Mode

Description

Protection

0x60

Block lock Setup

First cycle of a 2-cycle command; prepares the CUI for block lock config-

uration changes. If the next command is not Block Lock (0x01), Block

Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets Status Register

bits SR.5 and SR.4, indicating a command sequence error.

0x01

0xD0

Block lock

If the previous command was Block Lock Setup (0x60), the addressed

block is locked.

Block Unlock

If the previous command was Block Lock Setup (0x60), the addressed

block is unlocked. If the addressed block is in a lock-down state, the

operation has no effect.

0x2F

0xC0

Block Lock-Down

If the previous command was Block Lock Setup (0x60), the addressed

block is locked down.

OTP Register or Lock First cycle of a 2-cycle command; prepares the device for a OTP register

Register program

setup

or Lock Register program operation. The second cycle latches the regis-

ter address and data, and starts the programming algorithm to pro-

gram data the the OTP array.

Configuration

0x60

0x03

Read Configuration First cycle of a 2-cycle command; prepares the CUI for device read con-

Register Setup

figuration. If the Set Read Configuration Register command (0x03) is

not the next command, the CUI sets Status Register bits SR.4 and SR.5,

indicating a command sequence error.

Read Configuration If the previous command was Read Configuration Register Setup

Register

(0x60), the CUI latches the address and writes A[16:1] to the Read Con-

figuration Register for Easy BGA and TSOP, A[15:0] for QUAD+. Follow-

ing a Configure Read Configuration Register command, subsequent

read operations access array data.

Blank Check

0xBC

0xD0

0xEB

Block Blank Check

First cycle of a 2-cycle command; initiates the Blank Check operation on

a main block.

Block Blank Check

Confirm

Second cycle of blank check command sequence; it latches the block

address and executes blank check on the main array block.

EFI

Extended Function

First cycle of a multiple-cycle command; initiate operation using exten-

Interface command ded function interface. The second cycle is a Sub-Op-Code, the data

written on third cycle is one less than the word count; the allowable

value on this cycle are 0–511. The subsequent cycles load data words in-

to the program buffer at a specified address until word count is ach-

ieved.

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Device Command Bus Cycles

Device operations are initiated by writing specific device commands to the command

user interface (CUI). Several commands are used to modify array data including Word

Program and Block Erase commands. Writing either command to the CUI initiates a se-

quence of internally timed functions that culminate in the completion of the requested

task. However, the operation can be aborted by either asserting RST# or by issuing an

appropriate suspend command.

Table 11: Command Bus Cycles

First Bus Cycle

Second Bus Cycle

Bus

Cycles

Mode

Command

Op

Addr¹

DnA

WA

Data²

Op

–

Addr¹

Data²

Read

Read Array

1

≥2

2

Write

0xFF

0x90

0x98

0x70

0x50

0x40

0xE8

0x80

–

Read Device Identifier

Read CFI

Read

DBA + IA

ID

Read DBA + CFI-A

CFI-D

SRD

–

Read Status Register

Clear Status Register

Word Program

Buffered Program³

Read

–

DnA

–

1

Program

2

Write

WA

WD

N - 1

0xD0

>2

WA

Buffered Enhanced Factory

Program (BEFP)⁴

WA

Erase

Block Erase

2

1

2

Write

BA

DnA

BA

0x20

0xB0

0xD0

0x60

0xC0

0x60

Write

–

BA

–

0xD0

–

Suspend

Program/Erase Suspend

Program/Erase Resume

Block Lock

–

Block

Locking/

Unlocking

Write

BA

0x01

0xD0

0x2F

0x01

0xD0

0x2F

OTP-D

LRD

0x03

Block Unlock

BA

Block Lock-down

Block Lock

BA

Protection

BA

Block Unlock

BA

Block Lock-down

Program OTP register

Program Lock Register

BA

PRA

LRA

RCD

OTP-RA

LRA

RCD

Configuration Configure Read

Configuration Register

Block Blank Check

Blank Check

EFI

2

Write

BA

0xBC

0xEB

Write

BA

D0

Extended Function

Interface command ⁵

>2

WA

Sub-Op code

1. First command cycle address should be the same as the operation’s target address. DBA

= Device base address (needed for dual die 512Mb device); DnA = Address within the de-

vice; IA = Identification code address offset; CFI-A = Read CFI address offset; WA = Word

address of memory location to be written; BA = Address within the block; OTP-RA = Pro-

tection register address; LRA = Lock register address; RCD = Read configuration register

data on A[16:1] for Easy BGA and TSOP, A[15:0] for QUAD+ package.

Notes:

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Device Command Bus Cycles

2. ID = Identifier data; CFI-D = CFI data on DQ[15:0]; SRD = Status register data; WD = Word

data; N = Word count of data to be loaded into the write buffer; OTP-D = Protection

register data; LRD = Lock register data.

3. The second cycle of the BUFFERED PROGRAM command is the word count of the data to

be loaded into the write buffer. This is followed by up to 512 words of data. Then the

CONFIRM command (0xD0) is issued, triggering the array programming operation.

4. The CONFIRM command (0xD0) is followed by the buffer data.

5. The second cycle is a Sub-Op-Code, the data written on third cycle is N-1; 1≤ N ≤ 512.

The subsequent cycles load data words into the program buffer at a specified address

until word count is achieved, after the data words are loaded, the final cycle is the con-

firm cycle 0xD0).

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Read Operation

The device supports two read modes: asynchronous page mode and synchronous burst

mode. Asynchronous page mode is the default read mode after device power-up or a re-

set. The Read Configuration Register must be configured to enable synchronous burst

reads of the flash memory array.

The device can be in any of four read states: Read Array, Read Identifier, Read Status or

Read CFI. Upon power-up, or after a reset, the device defaults to Read Array. To change

the read state, the appropriate read command must be written to the device.

Asynchronous Page-Mode Read

Following a device power-up or reset, asynchronous page mode is the default read

mode and the device is set to Read Array. However, to perform array reads after any oth-

er device operation (e.g. write operation), the Read Array command must be issued in

order to read from the flash memory array.

Asynchronous page-mode reads can only be performed when Read Configuration Reg-

ister bit RCR.15 is set.

To perform an asynchronous page-mode read, an address is driven onto the Address

bus, and CE# and ADV# are asserted. WE# and RST# must already have been deasser-

ted. WAIT is deasserted during asynchronous page mode. ADV# can be driven high to

latch the address, or it must be held low throughout the read cycle. CLK is not used for

asynchronous page-mode reads, and is ignored. If only asynchronous reads are to be

performed, CLK should be tied to a valid V_IHor V_SSlevel, WAIT signal can be floated and

ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial access

time t_AVQVdelay.

In asynchronous page mode, sixteen data words are “sensed” simultaneously from the

flash memory array and loaded into an internal page buffer. The buffer word corre-

sponding to the initial address on the Address bus is driven onto DQ[15:0] after the ini-

tial access delay. The lowest four address bits determine which word of the 16-word

page is output from the data buffer at any given time.

Note: Asynchronous page read mode is only supported in main array.

Synchronous Burst-Mode Read

Read Configuration register bits RCR[15:0] must be set before synchronous burst opera-

tion can be performed. Synchronous burst mode can be performed for both array and

non-array reads such as Read ID, Read Status or Read Query.

To perform a synchronous burst-read, an initial address is driven onto the Address bus,

and CE# and ADV# are asserted. WE# and RST# must already have been deasserted.

ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can re-

main asserted throughout the burst access, in which case the address is latched on the

next valid CLK edge while ADV# is asserted.

During synchronous array and non-array read modes, the first word is output from the

data buffer on the next valid CLK edge after the initial access latency delay. Subsequent

data is output on valid CLK edges following a minimum delay. However, for a synchro-

nous non-array read, the same word of data will be output on successive clock edges

until the burst length requirements are satisfied. Refer to the timing diagrams for more

detailed information.

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Read Operation

Read Device Identifier

The Read Device Identifier command instructs the device to output manufacturer code,

device identifier code, block-lock status, protection register data, or configuration regis-

ter data.

Table 12: Device Identifier Information

Item

Address

Data

Manufacturer code

0x00

0x01

0x89h

Device ID code

ID (see the Device ID Codes table )

Lock bit:

Block lock configuration:

• Block is unlocked

Block base address + 0x02

DQ₀= 0b0

• Block is locked

DQ₀= 0b1

• Block is not locked down

• Block is locked down

Read configuration register

General purpose register

Lock register 0

DQ₁= 0b0

DQ₁= 0b1

0x05

Device base address + 0x07

0x80

RCR contents

General purpose register data

PR-LK0 data

64-bit factory-programmed OTP register

64-bit user-programmable OTP register

Lock register 1

0x81–0x84

Factory OTP register data

User OTP register data

PR-LK1 OTP register lock data

OTP register data

0x85–0x88

0x89

128-bit user-programmable protection regis-

ters

0x8A–0x109

Table 13: Device ID codes

Device Identifier Codes

ID Code Type

Device Density

–T (Top Parameter)

–B (Bottom Parameter)

Device Code

256Mb

8919

891C

1. The 512Mb devices do not have a unique device ID associated with them. Each die with-

in the stack can be identified by either of the 256Mb Device ID codes depending on its

parameter option.

Note:

Read CFI

The Read CFI command instructs the device to output Common Flash Interface (CFI)

data when read. See READ CFI Structure Output for details on issuing the Read CFI

command. The CFI Database: Addresses and Sections table shows CFI information and

address offsets within the CFI database.

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Program Operation

The device supports three programming methods: Word Programming (40h or 10h),

Buffered Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h,

D0h). See Device Command Codes for details on the various programming commands

issued to the device. The following sections describe device programming in detail.

Successful programming requires the addressed block to be unlocked. If the block is

locked down, WP# must be de-asserted and the block must be unlocked before at-

tempting to program the block. Attempting to program a locked block causes a program

error (SR.4 and SR.1 set) and termination of the operation. See Security Modes for de-

tails on locking and unlocking blocks.

Word Programming

Word programming operations are initiated by writing the Word Program Setup com-

mand to the device (see the Command Codes and Definitions table). This is followed by

a second write to the device with the address and data to be programmed. The device

outputs status register data when read (see the Word Program Flowchart). V_PPmust be

above V_PPLK, and within the specified V_PPLmin/max values.

During programming, the write state machine (WSM) executes a sequence of internal-

ly-timed events that program the desired data bits at the addressed location, and veri-

fies that the bits are sufficiently programmed. Programming the flash memory array

changes 1s to 0s. Memory array bits that are 0s can be changed to 1s only by erasing the

block (see Erase Operations).

The Status Register can be examined for programming progress and errors by reading at

any address. The device remains in the read status register state until another com-

mand is written to the device.

Status Register bit SR.7 indicates the programming status while the sequence executes.

Commands that can be issued to the device during programming are Program Suspend,

Read Status Register, Read Device Identifier, Read CFI, and Read Array (this returns un-

known data).

When programming has finished, status register bit SR.4 (when set) indicates a pro-

gramming failure. If SR.3 is set, the WSM could not perform the word programming op-

eration because V_PPwas outside of its acceptable limits. If SR.1 is set, the word pro-

gramming operation attempted to program a locked block, causing the operation to

abort.

Before issuing a new command, the status register contents should be examined and

then cleared using the Clear Status Register command. Any valid command can follow,

when word programming has completed.

Buffered Programming

The device features a 512-word buffer to enable optimum programming performance.

For Buffered Programming, data is first written to an on-chip write buffer. Then the buf-

fer data is programmed into the flash memory array in buffer-size increments. This can

improve system programming performance significantly over non-buffered program-

ming.

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Program Operation

When the Buffered Programming Setup command is issued, Status Register information

is updated and reflects the availability of the buffer. SR.7 indicates buffer availability: if

set, the buffer is available; if cleared, the buffer is not available.

Note: The device default state is to output SR data after the Buffer Programming Setup

Command. CE# and OE# low drive device to update Status Register. It is not allowed to

issue 70h to read SR data after E8h command otherwise 70h would be counted as Word

Count.

On the next write, a word count is written to the device at the buffer address. This tells

the device how many data words will be written to the buffer, up to the maximum size

of the buffer.

On the next write, a device start address is given along with the first data to be written to

the flash memory array. Subsequent writes provide additional device addresses and da-

ta. All data addresses must lie within the start address plus the word count. Optimum

programming performance and lower power usage are obtained by aligning the starting

address at the beginning of a 512-word boundary (A[9:1] = 0x00 for Easy BGA and TSOP,

A[8:0] for QUAD+ package). The maximum buffer size would be 256-word if the mis-

aligned address range is crossing a 512-word boundary during programming.

After the last data is written to the buffer, the Buffered Programming Confirm command

must be issued to the original block address. The WSM begins to program buffer con-

tents to the flash memory array. If a command other than the Buffered Programming

Confirm command is written to the device, a command sequence error occurs and Sta-

tus Register bits SR[7,5,4] are set. If an error occurs while writing to the array, the device

stops programming, and Status Register bits SR[7,4] are set, indicating a programming

failure.

When Buffered Programming has completed, additional buffer writes can be initiated

by issuing another Buffered Programming Setup command and repeating the buffered

program sequence. Buffered programming may be performed with V_PP= V_PPLor V_PPH

(see Operating Conditions for limitations when operating the device with V_PP= V_PPH).

If an attempt is made to program past an erase-block boundary using the Buffered Pro-

gram command, the device aborts the operation. This generates a command sequence

error, and Status Register bits SR[5,4] are set.

If Buffered programming is attempted while V_PPis at or below V_PPLK, Status Register bits

SR[4,3] are set. If any errors are detected that have set Status Register bits, the Status

Register should be cleared using the Clear Status Register command.

Buffered Enhanced Factory Programming

Buffered Enhanced Factory Programing (BEFP) speeds up multilevel cell (MLC) flash

programming. The enhanced programming algorithm used in BEFP eliminates tradi-

tional programming elements that drive up overhead in device programmer systems.

BEFP consists of three phases: Setup, Program/Verify, and Exit (see the BEFP Flow-

chart). It uses a write buffer to spread MLC program performance across 512 data

words. Verification occurs in the same phase as programming to accurately program the

flash memory cell to the correct bit state.

A single two-cycle command sequence programs the entire block of data. This en-

hancement eliminates three write cycles per buffer: two commands and the word count

for each set of 512 data words. Host programmer bus cycles fill the device write buffer

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Program Operation

followed by a status check. SR.0 indicates when data from the buffer has been program-

med into sequential flash memory array locations.

Following the buffer-to-flash array programming sequence, the write state machine

(WSM) increments internal addressing to automatically select the next 512-word array

boundary. This aspect of BEFP saves host programming equipment the address bus set-

up overhead.

With adequate continuity testing, programming equipment can rely on the WSM’s in-

ternal verification to ensure that the device has programmed properly. This eliminates

the external post-program verification and its associated overhead.

BEFP Requirements and Considerations

Table 14: BEFP Requirements

Parameter/Issue

Case Temperature

V_CC

Requirement

Notes

T_C= 30°C ± 10 °C

Nominal V_CC

V_PP

Driven to V_PPH

Setup and Confirm

Programming

Target block must be unlocked before issuing the BEFP Setup and Confirm commands.

The first-word address (WA0) of the block to be programmed must be held constant

from the setup phase through all data streaming into the target block, until transition

to the exit phase is desired.

Buffer Alignment

WA0 must align with the start of an array buffer boundary.

1

1. Word buffer boundaries in the array are determined by A[9:1] for Easy BGA and TSOP;

A[8:0] for QUAD+ package (0x000 through 0x1FF). The alignment start point is A[9:1] =

0x000 for Easy BGA and TSOP; A[8:0] = 0x000 for QUAD+ package.

Note:

Table 15: BEFP Considerations

Parameter/Issue

Requirement

Notes

Cycling

For optimum performance, cycling must be limited below 50 erase cycles per block.

1

2

Programming blocks BEFP programs one block at a time; all buffer data must fall within a single block.

Suspend

BEFP cannot be suspended.

Programming the

flash memory array

Programming to the flash memory array can occur only when the buffer is full.

3

1. Some degradation in performance may occur if this limit is exceeded, but the internal

algorithm continues to work properly.

Notes:

2. If the internal address counter increments beyond the block's maximum address, ad-

dressing wraps around to the beginning of the block.

3. If the number of words is less than 512, remaining locations must be filled with 0xFFFF.

BEFP Setup Phase

After receiving the BEFP Setup and Confirm command sequence, Status Register bit SR.

7 (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A de-

lay before checking SR.7 is required to allow the WSM enough time to perform all of its

setups and checks (Block-Lock status, V_PPlevel, etc.). If an error is detected, SR.4 is set

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Program Operation

and BEFP operation terminates. If the block was found to be locked, SR.1 is also set. SR.

3 is set if the error occurred due to an incorrect V_PPlevel.

Note: Reading from the device after the BEFP Setup and Confirm command sequence

outputs status register data. Do not issue the Read Status Register command; it will be

interpreted as data to be loaded into the buffer.

BEFP Program/Verify Phase

After the BEFP Setup Phase has completed, the host programming system must check

SR[7,0] to determine the availability of the write buffer for data streaming. SR.7 cleared

indicates the device is busy and the BEFP program/verify phase is activated. SR.0 indi-

cates the write buffer is available.

Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer

data programming to the array. For BEFP, the count value for buffer loading is always

the maximum buffer size of 512 words. During the buffer-loading sequence, data is stor-

ed to sequential buffer locations starting at address 0x00. Programming of the buffer

contents to the flash memory array starts as soon as the buffer is full. If the number of

words is less than 512, the remaining buffer locations must be filled with 0xFFFF.

Note: The buffer must be completely filled for programming to occur. Supplying an ad-

dress outside of the current block's range during a buffer-fill sequence causes the algo-

rithm to exit immediately. Any data previously loaded into the buffer during the fill cy-

cle is not programmed into the array.

The starting address for data entry must be buffer size aligned, if not the BEFP algo-

rithm will be aborted and the program fails and (SR.4) flag will be set.

Data words from the write buffer are directed to sequential memory locations in the

flash memory array; programming continues from where the previous buffer sequence

ended. The host programming system must poll SR.0 to determine when the buffer pro-

gram sequence completes. SR.0 cleared indicates that all buffer data has been transfer-

red to the flash array; SR.0 set indicates that the buffer is not available yet for the next

fill cycle. The host system may check full status for errors at any time, but it is only nec-

essary on a block basis after BEFP exit. After the buffer fill cycle, no write cycles should

be issued to the device until SR.0 = 0 and the device is ready for the next buffer fill.

Note: Any spurious writes are ignored after a buffer fill operation and when internal

program is proceeding.

The host programming system continues the BEFP algorithm by providing the next

group of data words to be written to the buffer. Alternatively, it can terminate this phase

by changing the block address to one outside of the current block’s range.

The Program/Verify phase concludes when the programmer writes to a different block

address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the

device enters the BEFP Exit phase.

BEFP Exit Phase

When SR.7 is set, the device has returned to normal operating conditions. A full status

check should be performed at this time to ensure the entire block programmed success-

fully. When exiting the BEFP algorithm with a block address change, the read mode will

not change. After BEFP exit, any valid command can be issued to the device.

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Program Operation

Program Suspend

Issuing the Program Suspend command while programming suspends the program-

ming operation. This allows data to be accessed from the device other than the one be-

ing programmed. The Program Suspend command can be issued to any device address.

A program operation can be suspended to perform reads only. Additionally, a program

operation that is running during an erase suspend can be suspended to perform a read

operation.

When a programming operation is executing, issuing the Program Suspend command

requests the WSM to suspend the programming algorithm at predetermined points.

The device continues to output Status Register data after the Program Suspend com-

mand is issued. Programming is suspended when Status Register bits SR[7,2] are set.

To read data from the device, the Read Array command must be issued. Read Array,

Read Status Register, Read Device Identifier, Read CFI, and Program Resume are valid

commands during a program suspend.

During a program suspend, deasserting CE# places the device in standby, reducing ac-

tive current. V_PPmust remain at its programming level, and WP# must remain un-

changed while in program suspend. If RST# is asserted, the device is reset.

Program Resume

The Resume command instructs the device to continue programming, and automati-

cally clears Status Register bits SR[7,2]. This command can be written to any address. If

error bits are set, the Status Register should be cleared before issuing the next instruc-

tion. RST# must remain deasserted.

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Program Operation

Program Protection

When V_PP= V_IL, absolute hardware write protection is provided for all device blocks. If

V_PPis at or below V_PPLK, programming operations halt and SR.3 is set indicating a V_PP

level error. Block lock registers are not affected by the voltage level on V_PP; they may still

be programmed and read, even if V_PPis less than V_PPLK

-

.

Figure 11: Example VPP Supply Connections

V_CC

V_PP

V_CC

V_PP

V_CC

V_PP

PROT#

<

10K Ω

-Factory programming with V_PP= V_PPH

-Complete with program/erase

-Low voltage programming only

-Logic control of device protection

protection when V_PP

<

V_PPLK

V_CC

V_PP

V_CC

V_PP

V

PPH

=

-Low voltage and factory programming

-Low voltage programming only

-Full device protection unavailable

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Erase Operations

Flash erasing is performed on a block basis. An entire block is erased each time an erase

command sequence is issued, and only one block is erased at a time. When a block is

erased, all bits within that block read as logical ones. The following sections describe

block erase operations in detail.

Block Erase

Block erase operations are initiated by writing the Block Erase Setup command to the

address of the block to be erased. Next, the Block Erase Confirm command is written to

the address of the block to be erased. If the device is placed in standby (CE# deasserted)

during an erase operation, the device completes the erase operation before entering

standby. The V_PPvalue must be above V_PPLKand the block must be unlocked.

During a block erase, the Write State Machine (WSM) executes a sequence of internally-

timed events that conditions, erases, and verifies all bits within the block. Erasing the

flash memory array changes “zeros” to “ones”. Memory block array that are ones can be

changed to zeros only by programming the block.

The Status Register can be examined for block erase progress and errors by reading any

address. The device remains in the Read Status Register state until another command is

written. SR.0 indicates whether the addressed block is erasing. Status Register bit SR.7 is

set upon erase completion.

Status Register bit SR.7 indicates block erase status while the sequence executes. When

the erase operation has finished, Status Register bit SR.5 indicates an erase failure if set.

SR.3 set would indicate that the WSM could not perform the erase operation because

V_PPwas outside of its acceptable limits. SR.1 set indicates that the erase operation at-

tempted to erase a locked block, causing the operation to abort.

Before issuing a new command, the Status Register contents should be examined and

then cleared using the Clear Status Register command. Any valid command can follow

once the block erase operation has completed.

The Block Erase operation is aborted by performing a reset or powering down the de-

vice. In this case, data integrity cannot be ensured, and it is recommended to erase

again the blocks aborted.

Blank Check

The Blank Check operation determines whether a specified main block is blank; that is,

completely erased. Without Blank Check, Block Erase would be the only other way to

ensure a block is completely erased. Blank Check is especially useful in the case of erase

operation interrupted by a power loss event.

Blank check can apply to only one block at a time, and no operations other than Status

Register Reads are allowed during Blank Check (e.g. reading array data, program, erase

etc). Suspend and resume operations are not supported during Blank Check, nor is

Blank Check supported during any suspended operations.

Blank Check operations are initiated by writing the Blank Check Setup command to the

block address. Next, the Check Confirm command is issued along with the same block

address. When a successful command sequence is entered, the device automatically en-

ters the Read Status State. The WSM then reads the entire specified block, and deter-

mines whether any bit in the block is programmed or over-erased.

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Erase Operations

The status register can be examined for Blank Check progress and errors by reading any

address within the block being accessed. During a blank check operation, the Status

Register indicates a busy status (SR.7 = 0). Upon completion, the Status Register indi-

cates a ready status (SR.7 = 1). The Status Register should be checked for any errors, and

then cleared. If the Blank Check operation fails, which means the block is not complete-

ly erased, the Status Register bit SR.5 will be set (“1”). CE# or OE# toggle (during polling)

updates the Status Register.

After examining the Status Register, it should be cleared by the Clear Status Register

command before issuing a new command. The device remains in Status Register Mode

until another command is written to the device. Any command can follow once the

Blank Check command is complete.

Erase Suspend

Issuing the Erase Suspend command while erasing suspends the block erase operation.

This allows data to be accessed from memory locations other than the one being

erased. The Erase Suspend command can be issued to any device address. A block erase

operation can be suspended to perform a word or buffer program operation, or a read

operation within any block except the block that is erase suspended.

When a block erase operation is executing, issuing the Erase Suspend command re-

quests the WSM to suspend the erase algorithm at predetermined points. The device

continues to output Status Register data after the Erase Suspend command is issued.

Block erase is suspended when Status Register bits SR[7,6] are set.

To read data from the device (other than an erase-suspended block), the Read Array

command must be issued. During Erase Suspend, a Program command can be issued to

any block other than the erase-suspended block. Block erase cannot resume until pro-

gram operations initiated during erase suspend complete. Read Array, Read Status Reg-

ister, Read Device Identifier, Read CFI, and Erase Resume are valid commands during

Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block

Lock, Block Unlock, and Block Lock-Down are valid commands during Erase Suspend.

During an erase suspend, deasserting CE# places the device in standby, reducing active

current. V_PPmust remain at a valid level, and WP# must remain unchanged while in

erase suspend. If RST# is asserted, the device is reset.

Erase Resume

The Erase Resume command instructs the device to continue erasing, and automatical-

ly clears status register bits SR[7,6]. This command can be written to any address. If sta-

tus register error bits are set, the Status Register should be cleared before issuing the

next instruction. RST# must remain deasserted.

Erase Protection

When V_PP= V_IL, absolute hardware erase protection is provided for all device blocks. If

V_PPis at or below V_PPLK, erase operations halt and SR.3 is set indicating a V_PP-level error.

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Security Modes

The device features security modes used to protect the information stored in the flash

memory array. The following sections describe each security mode in detail.

Block Locking

Individual instant block locking is used to protect user code and/or data within the

flash memory array. All blocks power-up in a locked state to protect array data from be-

ing altered during power transitions. Any block can be locked or unlocked with no la-

tency. Locked blocks cannot be programmed or erased; they can only be read.

Software-controlled security is implemented using the Block Lock and Block Unlock

commands. Hardware-controlled security can be implemented using the Block Lock-

Down command along with asserting WP#. Also, V_PPdata security can be used to inhibit

program and erase operations.

Lock Block

To lock a block, issue the Block Lock Setup command, followed by the Block Lock com-

mand issued to the desired block’s address. If the Set Read Configuration Register com-

mand is issued after the Block Lock Setup command, the device configures the RCR in-

stead.

Block lock and unlock operations are not affected by the voltage level on V_PP. The block

lock bits may be modified and/or read even if V_PPis at or below V_PPLK

.

Unlock Block

The Block Unlock command is used to unlock blocks. Unlocked blocks can be read,

programmed, and erased. Unlocked blocks return to a locked state when the device is

reset or powered down. If a block is in a lock-down state, WP# must be deasserted be-

fore it can be unlocked.

Lock-Down Block

A locked or unlocked block can be locked-down by writing the Block Lock-Down com-

mand sequence. Blocks in a lock-down state cannot be programmed or erased; they can

only be read. However, unlike locked blocks, their locked state cannot be changed by

software commands alone. A locked-down block can only be unlocked by issuing the

Block Unlock command with WP# deasserted. To return an unlocked block to locked-

down state, a Block Lock-Down command must be issued prior to changing WP# to V_IL

.

Locked-down blocks revert to the locked state upon reset or power up the device.

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Security Modes

Block Lock Status

The Read Device Identifier command is used to determine a block’s lock status. Data

bits DQ[1:0] display the addressed block’s lock status; DQ0 is the addressed block’s lock

bit, while DQ1 is the addressed block’s lock-down bit.

Figure 12: Block Locking State Diagram

(Power-up/

Reset default)

[000]

D0h

01h

[001]

2Fh

Program/Erase Allowed

WP# = V_IL= 0

Program/Erase Prevented

WP# = V_IL= 0

2Fh

WP# toggle

D0h, 01h, or 2Fh

[010]

[011] (Locked-down)

(Virtual lock-down)

WP# toggle

(Lock-down

disabled,

WP# = V_IH)

D0h

[110]

[100]

01h/2Fh

[111]

Program/Erase Allowed

WP# = V_IH= 1

Program/Erase Prevented

WP# = V_IH= 1

2Fh

01h

2Fh

(Power-up/

Reset default)

[101]

1. D0h = UNLOCK command; 01h = LOCK command; 60h (not shown) LOCK SETUP com-

mand; 2Fh = LOCK-DOWN command.

Note:

Block Locking During Suspend

Block lock and unlock changes can be performed during an erase suspend. To change

block locking during an erase operation, first issue the Erase Suspend command. Moni-

tor the Status Register until SR.7 and SR.6 are set, indicating the device is suspended

and ready to accept another command.

Next, write the desired lock command sequence to a block, which changes the lock

state of that block. After completing block lock or unlock operations, resume the erase

operation using the Erase Resume command.

Note:

A Lock Block Setup command followed by any command other than Lock Block, Unlock

Block, or Lock-Down Block produces a command sequence error and set Status Register

bits SR.4 and SR.5. If a command sequence error occurs during an erase suspend, SR.4

and SR.5 remains set, even after the erase operation is resumed. Unless the Status Reg-

ister is cleared using the Clear Status Register command before resuming the erase op-

eration, possible erase errors may be masked by the command sequence error.

If a block is locked or locked-down during an erase suspend of the same block, the lock

status bits change immediately. However, the erase operation completes when it is re-

sumed. Block lock operations cannot occur during a program suspend.

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256Mb and 512Mb (256Mb/256Mb), P30-65nm

Security Modes

Selectable One-Time Programmable Blocks

The OTP security feature on P30-65nm device is backward compatible to the

P30-130nm device. Contact your local Micron representative for details about its imple-

mentation.

Password Access

The Password Access is a security enhancement offered on the P30-65nm device. This

feature protects information stored in array blocks by preventing content alteration or

reads until a valid 64-bit password is received. The Password Access may be combined

with Non-Volatile Protection and/or Volatile Protection to create a multi-tiered solu-

tion.

Contact your Micron sales office for further details concerning Password Access.

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Registers

When non-array reads are performed in asynchronous page mode only the first data is

valid and all subsequent data are undefined. When a non-array read operation occurs

as synchronous burst mode, the same word of data requested will be output on succes-

sive clock edges until the burst length requirements are satisfied.

Read Status Register

To read the Status Register, issue the Read Status Register command at any address. Sta-

tus Register information is available to which the Read Status Register, Word Program,

or Block Erase command was issued. Status Register data is automatically made availa-

ble following a Word Program, Block Erase, or Block Lock command sequence. Reads

from the device after any of these command sequences outputs the device’s status until

another valid command is written (e.g. Read Array command).

The Status Register is read using single asynchronous-mode or synchronous burst

mode reads. Status Register data is output on DQ[7:0], while 0x00 is output on DQ[15:8].

In asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates

and latches the Status Register contents. However, reading the Status Register in syn-

chronous burst mode, CE# or ADV# must be toggled to update status data.

The Device Write Status bit (SR.7) provides overall status of the device. Status register

bits SR[6:1] present status and error information about the program, erase, suspend,

V_PP, and block-locked operations.

Table 16: Status Register Description

Bit Name

Description

7

6

5

Device Ready Status

(DWS)

0 = Device is busy; program or erase cycle in progress; SR.0 valid.

1 = Device is ready; SR[6:1] are valid.

Erase Suspend Status

(ESS)

0 = Erase suspend not in effect.

1 = Erase suspend in effect.

Erase /Blank Command SR.5 SR.4 Description

Check Status Sequence

(ES)

Error

4

Program Sta-

tus (PS)

0

1

0

1

0

1

Program or Erase operation successful.

Program error - operation aborted.

Erase or Blank check error - operation aborted.

Command sequence error - command aborted.

3

2

1

0

V_PPStatus (VPPS)

0 = VPP within acceptable limits during program or erase operation.

1 = VPP ≤ VPPLK during program or erase operation.

Program Suspend Status 0 = Program suspend not in effect.

(PSS) 1 = Program suspend in effect.

Block-Locked Status (BLS) 0 = Block not locked during program or erase.

1 = Block locked during program or erase; operation aborted.

BEFP Status (BWS)

After Buffered Enhanced Factory Programming (BEFP) data is loaded into the buffer:

0 = BEFP complete.

1 = BEFP in-progress.

1. Default Value = 0x80

Notes:

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Registers

2. Always clear the Status Register prior to resuming erase operations. It avoids Status Reg-

ister ambiguity when issuing commands during Erase Suspend. If a command sequence

error occurs during an erase-suspend state, the Status Register contains the command

sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes,

possible errors during the erase operation cannot be detected via the Status Register be-

cause it contains the previous error status.

3. A Clear SR command (50h) or Reset must be issued with 15µs delay after the Error bits

(SR4 or SR5) is set during Program/Erase operations.

Clear Status Register

The Clear Status Register command clears the status register. It functions independent

of V_PP. The Write State Machine (WSM) sets and clears SR[7,6,2], but it sets bits SR[5:3,1]

without clearing them. The Status Register should be cleared before starting a com-

mand sequence to avoid any ambiguity. A device reset also clears the Status Register.

Read Configuration Register

The Read Configuration Register (RCR) is a 16-bit read/write register used to select bus-

read mode (synchronous or asynchronous), and to configure device synchronous burst

read characteristics. To modify RCR settings, use the Configure Read Configuration Reg-

ister command. RCR contents can be examined using the Read Device Identifier com-

mand, and then reading from offset 0x05. On power-up or exit from reset, the RCR de-

faults to asynchronous mode. Details about each RCR bit follow the table.

Table 17: Read Configuration Register

Bit Name

Description

15 Read mode (RM)

0 = Synchronous burst-mode read

1 = Asynchronous page-mode read (default)

14:11 Latency count

(LC[3:0])

0000 = Code 0 (reserved)

0001 = Code 1 (reserved)

0010 = Code 2

0011 = Code 3

0100 = Code 4

0110 = Code 6

0111 = Code 7

1000 = Code 8

1001 = Code 9

1010 = Code 10

1011 = Code11

1100 = Code 12

1101 = Code 13

1110 = Code 14

1111 = Code 15 (default)

0101 = Code 5

10 WAIT polarity (WP)

0 = WAIT signal is active low (default)

1 = WAIT signal is active high

9

8

Reserved (R)

Default 0, Non-changeable

WAIT delay (WD)

0 = WAIT deasserted with valid data

1 = WAIT deasserted one data cycle before valid data (default)

7

6

Burst sequence (BS)

Clock edge (CE)

Default 0, Non-changeable

0 = Falling edge

1 = Rising edge (default)

5:4 Reserved (R)

Burst wrap (BW)

Default 0, Non-changeable

3

0 = Wrap; Burst accesses wrap within burst length set by BL[2:0]

1 = No Wrap; Burst accesses do not wrap within burst length (default)

2:0 Burst length (BL[2:0]) 001 = 4-word burst

010 = 8-word burst

011 = 16-word burst

111 = Continuous-word burst (default)

(Other bit settings are reserved)

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Registers

Read Mode

The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode

operation for the device. When the RM bit is set, asynchronous page mode is selected

(default). When RM is cleared, synchronous burst mode is selected.

Latency Count

The Latency Count (LC) bits tell the device how many clock cycles must elapse from the

rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the

first valid data word is to be driven onto DQ[15:0]. The input clock frequency is used to

determine this value and the First Access Latency Count figure shows the data output

latency for the different settings of LC. The minimum Latency Count for P30-65nm

would be Code 4 based on the Max Clock frequency specification of 52 MHz, and there

will be zero WAIT States when bursting within the word line. Refer to End of Word Line

Considerations for more information on EOWL, and the Latency Count and Frequency

Support table for latency code settings.

Figure 13: First Access Latency Count

CLK [C]

Valid

Address [A]

Address

ADV# [V]

Code 0 (Reserved

)

Valid

DQ[15:0] [D/Q]

Output

Code

1

Valid

(Reserved

)

DQ[15:0] [D/Q]

Output

Code

2

Valid

Output

3

Valid

Output

Code

4

5

6

7

Valid

Output

Valid

Output

Valid

Output

Valid

Output

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Registers

Table 18: Latency Count and Frequency Support

Latency Count Settings

5 (TSOP); 4 (Easy BGA)

5 (Easy BGA)

Frequency Support (MHz)

≤ 40

≤ 52

Figure 14: Example Latency Count Setting Using Code 3

t

Data

0

1

2

3

4

CLK

CE#

ADV#

Address

A[MAX:1]

Code 3

High-Z

D[15:0]

Data

R103

End of Word Line (EOWL) Considerations

End of Wordline (EOWL) WAIT states can result when the starting address of the burst

operation is not aligned to a 16-word boundary; that is, A[3:0] of start address does not

equal 0x0. The End of Wordline Timing Diagram illustrates the end of wordline WAIT

state(s) that occur after the first 16-word boundary is reached. The number of data

words and the number of WAIT states is summarized in the End of Wordline Data and

WAIT State Comparison table for both P30-130nm and P30-65nm devices.

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256Mb and 512Mb (256Mb/256Mb), P30-65nm

Registers

Figure 15: End of Wordline Timing Diagram

Latency Count

CLK

A[Max:1]

DQ[15:0]

Address

Data

ADV #

OE #

WAIT

EOWL

Table 19: End of Wordline Data and WAIT State Comparison

P30-130nm

P30-65nm

Latency Count

Data States

WAIT States

Not Supported

0 to 1

Data States

WAIT States

1

2

Not Supported

0 to 1

4

16

3

4

0 to 2

4

0 to 3

5

4

0 to 4

6

4

0 to 5

7

4

0 to 6

8

Not Supported

0 to 7

9

0 to 8

10

11

12

13

14

15

0 to 9

0 to 10

0 to 11

0 to 12

0 to 13

0 to 14

WAIT Signal Polarity and Functionality

The WAIT Polarity bit (WP), RCR.10 determines the asserted level (V_OHor V_OL) of WAIT.

When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is asserted

low. WAIT changes state on valid clock edges during active bus cycles (CE# asserted,

OE# asserted, RST# deasserted).

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Registers

The WAIT signal indicates data valid when the device is operating in synchronous mode

(RCR.15 =0). The WAIT signal is only deasserted when data is valid on the bus. When the

device is operating in synchronous non-array read mode, such as read status, read ID,

or read CFI, the WAIT signal is also deasserted when data is valid on the bus. WAIT be-

havior during synchronous non-array reads at the end of word line works correctly only

on the first data access. When the device is operating in asynchronous page mode,

asynchronous single word read mode, and all write operations, WAIT is set to a deasser-

ted state as determined by RCR.10.

Table 20: WAIT Functionality Table

Condition

WAIT

High-Z

Active

Notes

CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’

CE# =’0’, OE# = ‘0’

1, 2

1

Synchronous Array Reads

Synchronous Non-Array Reads

All Asynchronous Reads

All Writes

Active

1

Active

1

Deasserted

High-Z

1

1, 2

1. Active means that WAIT is asserted until data becomes valid, then desserts.

2. When OE# = V_IHduring writes, WAIT = High-Z.

Notes:

WAIT Delay

The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during synchro-

nous burst reads. WAIT can be asserted either during or one data cycle before valid data

is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle before valid

data (default). When WD is cleared, WAIT is deasserted during valid data.

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Registers

Burst Sequence

The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst

sequence is supported. The synchronous burst sequence for all burst lengths, as well as

the effect of the Burst Wrap (BW) setting are shown here.

Table 21: Burst Sequence Word Ordering

Start

Address

(DEC)

Burst

Wrap

(RCR.3)

Burst Addressing Sequence (DEC)

4-Word Burst

(BL[2:0] =

0b001)

8-Word Burst

16-Word Burst

(BL[2:0] = 0b011)

Continuous Burst

(BL[2:0] = 0b111)

(BL[2:0] = 0b010)

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

⋮

0

1

0

⋮

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3-4…14-15

1-2-3-4-5…15-0

0-1-2-3-4-5-6-…

1-2-3-4-5-6-7-…

2-3-4-5-6-7-8-…

3-4-5-6-7-8-9-…

4-5-6-7-8-9-10…

5-6-7-8-9-10-11…

6-7-8-9-10-11-12-…

7-8-9-10-11-12-13…

⋮

2

2-3-4-5-6…15-0-1

3-4-5-6-7…15-0-1-2

4-5-6-7-8…15-0-1-2-3

5-6-7-8-9…15-0-1-2-3-4

6-7-8-9-10…15-0-1-2-3-4-5

7-8-9-10…15-0-1-2-3-4-5-6

⋮

3

4

5

6

7

⋮

14

15

⋮

0

⋮

14-15-0-1-2…12-13

15-0-1-2-3…13-14

⋮

14-15-16-17-18-19-20-…

15-16-17-18-19-20-21-…

⋮

0

1

⋮

0-1-2-3

1-2-3-4

2-3-4-5

3-4-5-6

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-8

2-3-4-5-6-7-8-9

3-4-5-6-7-8-9-10

4-5-6-7-8-9-10-11

5-6-7-8-9-10-11-12

6-7-8-9-10-11-12-13

7-8-9-10-11-12-13-14

⋮

0-1-2-3-4…14-15

1-2-3-4-5…15-16

2-3-4-5-6…16-17

3-4-5-6-7…17-18

4-5-6-7-8…18-19

5-6-7-8-9…19-20

6-7-8-9-10…20-21

7-8-9-10-11…21-22

⋮

0-1-2-3-4-5-6-…

1-2-3-4-5-6-7-…

2-3-4-5-6-7-8-…

3-4-5-6-7-8-9-…

4-5-6-7-8-9-10…

5-6-7-8-9-10-11…

6-7-8-9-10-11-12-…

7-8-9-10-11-12-13…

⋮

1

2

3

4

5

6

7

⋮

14

15

1

14-15-16-17-18…28-29

15-16-17-18-19…29-30

14-15-16-17-18-19-20-…

15-16-17-18-19-20-21-…

Clock Edge

The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK.

This clock edge is used at the start of a burst cycle, to output synchronous data, and to

assert/deassert WAIT.

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Registers

Burst Wrap

The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length

accesses wrap within the selected word-length boundaries or cross word-length boun-

daries. When BW is set, burst wrapping does not occur (default). When BW is cleared,

burst wrapping occurs.

When performing synchronous burst reads with BW set (no wrap), an output delay may

occur when the burst sequence crosses its first device-row (16-word) boundary. If the

burst sequence’s start address is 4-word aligned, then no delay occurs. If the start ad-

dress is at the end of a 4-word boundary, the worst case output delay is one clock cycle

less than the first access Latency Count. This delay can take place only once, and

doesn’t occur if the burst sequence does not cross a device-row boundary. WAIT in-

forms the system of this delay when it occurs.

Burst Length

The Burst Length bits (BL[2:0]) select the linear burst length for all synchronous burst

reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word or con-

tinuous.

Continuous-burst accesses are linear only, and do not wrap within any word length

boundaries. When a burst cycle begins, the device outputs synchronous burst data until

it reaches the end of the “burstable” address space.

One-Time-Programmable (OTP) Registers

The device contains 17 one-time programmable (OTP) registers that can be used to im-

plement system security measures and/or device identification. Each OTP register can

be individually locked.

The first 128-bit OTP Register is comprised of two 64-bit (8-word) segments. The lower

64-bit segment is pre-programmed at the Micron factory with a unique 64-bit number.

The upper 64-bit segment, as well as the other sixteen 128-bit OTP Registers, are blank.

Users can program these registers as needed. Once programmed, users can then lock

the OTP Register(s) to prevent additional bit programming (see the OTP Register Map

figure).

The OTP Registers contain one-time programmable (OTP) bits; when programmed, PR

bits cannot be erased. Each OTP Register can be accessed multiple times to program in-

dividual bits, as long as the register remains unlocked.

Each OTP Register has an associated Lock Register bit. When a Lock Register bit is pro-

grammed, the associated OTP Register can only be read; it can no longer be program-

med. Additionally, because the Lock Register bits themselves are OTP, when program-

med, Lock Register bits cannot be erased. Therefore, when a OTP Register is locked, it

cannot be unlocked.

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Registers

Figure 16: OTP Register Map

0x109

128-bit OTP

Register 16

User Programmable

0x102

0x91

128-bit OTP

Register 1

User Programmable

Lock Register 1

0x8A

0x89

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

0x88

64-bit Segment

User Programmable

128-bit OTP

Register 0

0x85

0x84

64-bit Segment

Factory Programed

0x81

0x80

Lock Register 0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reading the OTP Registers

The OTP Registers can be read from OTP-RA address. To read the OTP Register, first is-

sue the Read Device Identifier command at OTP-RA address to place the device in the

Read Device Identifier state. Next, perform a read operation using the address offset

corresponding to the register to be read. The Device Identifier Information table shows

the address offsets of the OTP Registers and Lock Registers. PR data is read 16 bits at a

time.

Programming the OTP Registers

To program an OTP Register, first issue the Program OTP Register command at the pa-

rameter’s base address plus the offset of the desired OTP Register location. Next, write

the desired OTP Register data to the same OTP Register address.

The device programs the 64-bit and 128-bit user-programmable OTP Register data 16

bits at a time. Issuing the Program OTP Register command outside of the OTP Register’s

address space causes a program error (SR.4 set). Attempting to program a locked OTP

Register causes a program error (SR.4 set) and a lock error (SR.1 set).

Note:

When programming the OTP bits in the OTP registers for a Top Parameter Device, the

following upper address bits must also be driven properly: A[Max:17] driven high (V_IH

for TSOP and Easy BGA packages, and A[Max:16] driven high (V_IH) for QUAD+ SCSP.

)

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Registers

Locking the OTP Registers

Each OTP Register can be locked by programming its respective lock bit in the Lock

Register. To lock an OTP Register, program the corresponding bit in the Lock Register by

issuing the Program Lock Register command, followed by the desired Lock Register da-

ta. The physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for regis-

ter 1. These addresses are used when programming the lock registers.

Bit 0 of Lock Register 0 is already programmed during the manufacturing process, lock-

ing the lower half segment of the first 128-bit OTP Register. Bit 1 of Lock Register 0 can

be programmed by user to the upper half segment of the first 128-bit OTP Register.

When programming Bit 1 of Lock Register 0, all other bits need to be left as ‘1’ such that

the data programmed is 0xFFFD.

Lock Register 1 controls the locking of the upper sixteen 128-bit OTP Registers. Each bit

of Lock Register 1 corresponds to a specific 128-bit OTP Register. Programming a bit in

Lock Register 1 locks the corresponding 128-bit OTP Register; e.g., programming LR1.0

locks the corresponding OTP Register 1.

Note: After being locked, the OTP Registers cannot be unlocked.

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256Mb and 512Mb (256Mb/256Mb), P30-65nm

Common Flash Interface

The Common Flash Interface (CFI) is part of an overall specification for multiple com-

mand-set and control-interface descriptions. System software can parse the CFI data-

base structure to obtain information about the Flash device, such as block size, density,

bus width, and electrical specifications. The system software determines which com-

mand set to use to properly perform a Flash WRITE command, a block ERASE or READ

command, and to otherwise control the flash device. Information in the CFI database

can be viewed by issuing the READ CFI command.

READ CFI Structure Output

The READ CFI command obtains CFI database structure information and always out-

puts it on the lower byte, DQ[7:0], for a word-wide (x16) Flash device. This CFI-compli-

ant device always outputs 00h data on the upper byte (DQ[15:8]).

The numerical offset value is the address relative to the maximum bus width the Flash

device supports. For this Flash device family, the starting address is a 10h, which is a

word address for x16 devices. For example, at this starting address of 10h, a READ CFI

command outputs an ASCII Q in the lower byte and 00h in the higher byte as shown

here.

In all the CFI tables shown here, address and data are represented in hexadecimal nota-

tion. In addition, since the upper byte of word-wide devices is always 00h as shown in

the example here, the leading 00 has been dropped and only the lower byte value is

shown. Following is a table showing the CFI output for a x16 device, beginning at ad-

dress 10h and a table showing an overview of the CFI database sections with their ad-

dresses.

Table 22: Example of CFI Output (x16 device) as a Function of Device and Mode

Hex

Offset

Hex

Code

ASCII Value

(DQ[15:8])

ASCII Value

(DQ[7:0])

Device

Address

00010:

00011:

00012:

00013:

00014:

00015:

00016:

00017:

00018:

51

52

00

Q

R

59

Y

P_ID_LO

P_ID_HI

P_LO

Primary vendor ID

Primary vendor table address

Alternate vendor ID

P_HI

A_ID_LO

A_ID_HI

:

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Common Flash Interface

Table 23: CFI Database: Addresses and Sections

Address

00001:Fh

00010h

Section Name

Description

Reserved

Reserved for vendor-specific information

CFI ID string

Flash device command set ID (identification) and vendor da-

ta offset

0001Bh

00027h

P

System interface information

Device geometry definition

Flash device timing and voltage

Flash device layout

Primary Micron-specific extended query Vendor-defined informaton specific to the primary vendor

algorithm (offset 15 defines P which points to the primary

Micron-specific extended query table.)

Table 24: CFI ID String

Hex

Code

ASCII Value

(DQ[7:0])

Offset

Length

Description

Address

10:

10h

3

Query unique ASCII string “QRY”

- -51

- -52

- -59

- -01

- -00

Q

11:

R

12:

Y

13h

2

Primary vendor command set and control

interface ID code. 16-bit ID code for ven-

dor-specified algorithms.

13:

Primary vendor ID number

14:

15h

17h

2

Extended query table primary algorithm

address.

15:

16:

17:

18:

- -0A

- -01

- -00

Primary vendor table ad-

dress, primary algorithm

Alternate vendor command set and control

interface ID code. 0000h means no second

vendor-specified algorithm exists.

Alternate vendor ID number

19h

2

Secondary algorithm extended query table

address. 0000h means none exists.

19:

- -00

Primary vendor table ad-

dress, secondary algorithm

1A:

1. The CFI ID string provides verification that the device supports the CFI specification. It

also indicates the specification version and supported vendor-specific command sets.

Note:

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Common Flash Interface

Table 25: System Interface Information

Hex

Code

ASCII Value

(DQ[7:0])

Offset

Length

Description

Address

1Bh

1

V_CClogic supply minimum program/erase voltage.

bits 0 - 3 BCD 100 mV

1Bh

- -17

1.7V

bits 4 - 7 BCD volts

1Ch

1Dh

1Eh

1

V_CClogic supply maximum program/erase volt-

age.

bits 0 - 3 BCD 100 mV

bits 4 - 7 BCD volts

1Ch

1Dh

1Eh

- -20

2.0V

V_PP[programming] supply minimum program/

erase voltage.

bits 0 - 3 BCD 100 mV

- -85

- -95

8.5V

9.5V

bits 4 - 7 hex volts

V_PP[programming] supply maximum program/

erase voltage.

bits 0 - 3 BCD 100 mV

bits 4 - 7 hex volts

1Fh

20h

1

“n” such that typical single word program time-

1Fh

20h

- -09

- -0A

512µs

out = 2ⁿμs.

“n” such that typical full buffer write timeout =

2ⁿμs.

1024µs

21h

22h

1

“n” such that typical block erase timeout = 2ⁿms.

“n” such that typical full chip erase timeout = 2ⁿ

ms.

21h

22h

- -0A

- -00

1s

NA

23h

24h

25h

26h

1

“n” such that maximum word program timeout =

2ⁿtimes typical.

23h

24h

25h

26h

- -01

- -02

- -00

1024µs

4096µs

4s

“n” such that maximum buffer write timeout =

2ⁿtimes typical.

“n” such that maximum block erase timeout = 2ⁿ

times typical.

“n” such that maximum chip erase timeout = 2ⁿ

times typical.

NA

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Common Flash Interface

Table 26: Device Geometry

Hex

Code

ASCII Value

(DQ[7:0])

Offset Length

Description

n such that device size in bytes = 2ⁿ.

Address

27:

27h

28h

1

2

1

Flash device interface code assignment: n such that n + 1

specifies the bit field that represents the flash device width

capabilities as described here:

bit 0: x8

28:

- -01

- -00

x16

29:

bit 1: x16

bit 2: x32

bit 3: x64

bits 4 - 7: –

bits 8 - 15: –

2Ah

2Ch

2

1

n such that maximum number of bytes in write buffer = 2ⁿ.

2Ah

2Bh

2Ch

- -0A

- -00

1024

Number of erase block regions (x) within the device:

1) x = 0 means no erase blocking; the device erases in bulk.

2) x specifies the number of device regions with one or more

contiguous, same-size erase blocks.

See Note 1

3) Symmetrically blocked partitions have one blocking region.

2Dh

31h

35h

4

Erase block region 1 information:

bits 0 - 15 = y, y + 1 = number of identical-size erase blocks.

bits 16 - 31 = z, region erase block(s) size are z x 256 bytes.

2D:

2E:

2F:

30:

See Note 1

Erase block region 2 information:

bits 0 - 15 = y, y + 1 = number of identical-size erase blocks.

bits 16 - 31 = z, region erase block(s) size are z x 256 bytes.

31:

32:

33:

34:

Reserved for future erase block region information.

35:

36:

37:

38:

1. See Block Region Map Information table.

Note:

Table 27: Block Region Map Information

256Mb

Address

27:

Bottom

--19

Top

--19

--01

--00

--0A

--00

--02

--FE

Address

30:

Bottom

--00

Top

--02

--03

--00

--80

--00

28:

--01

31:

--FE

29:

--00

32:

--00

2A:

--0A

--00

33:

--00

2B:

34:

--02

2C:

--02

35:

--00

2D:

--03

36:

--00

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Common Flash Interface

Table 27: Block Region Map Information (Continued)

256Mb

Address

2E:

Bottom

--00

Top

--00

Address

37:

Bottom

--00

Top

--00

2F:

--80

38:

--00

Table 28: Primary Vendor-Specific Extended Query

Hex Offset

ASCII Value

(DQ[7:0])

P = 10Ah

Length

Description

Address Hex Code

(P+0)h

(P+1)h

(P+2)h

3

Primary extended query table, unique ASCII

string: PRI

10A:

10B:

10C:

10D:

10E:

10F:

110:

111:

112:

- -50

- -52

P

R

I

- -49

(P+3)h

(P+4)h

1

4

Major version number, ASCII

Minor version number, ASCII

- -31

1

4

–

- -34

(P+5)h

(P+6)h

(P+7)h

(P+8)h

Optional feature and command support (1 = yes;

0 = no)

Bits 11 - 29 are reserved; undefined bits are 0

If bit 31 = 1, then another 31-bit field of optional

features follows at the end of the bit 30 field.

- -E6

- -01

- -00

See Note 1

Bit 0: Chip erase supported.

bit 0 = 0

No

Yes

Bit 1: Suspend erase supported.

bit 1 = 1

bit 2 = 1

bit 3 = 0

bit 4 = 0

bit 5 = 1

bit 6 = 1

bit 7 = 1

bit 8 = 1

bit 9 = 0

Bit 2: Suspend program supported.

Bit 3: Legacy lock/unlock supported.

Bit 4: Queued erase supported.

Yes

No

Bit 5: Instant individual block locking supported.

Bit 6: OTP bits supported.

Yes

Bit 7: Page mode read supported.

Bit 8: Synchronous read supported.

Bit 9: Simultaneous operations supported.

Bit 10: Extended Flash array block supported

Bit 30: CFI links to follow:

Yes

No

bit 10 = 0

bit 30 = 0

bit 31 = 0

No

See Note 1

Bit 31: Another optional features field to follow.

(P+9)h

1

Supported functions after SUSPEND: READ AR-

RAY, STATUS, QUERY. Other supported options in-

clude:

113:

- -01

–

Bits 1 - 7: Reserved; undefined bits are 0.

Bit 0: Program supported after ERASE SUSPEND.

bit 0 = 1

Yes

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Common Flash Interface

Table 28: Primary Vendor-Specific Extended Query (Continued)

Hex Offset

P = 10Ah

ASCII Value

(DQ[7:0])

Length

Description

Block Status Register mask:

Bits 2 - 15 are reserved; undefined bits are 0.

Address Hex Code

(P+A)h

(P+B)h

2

114:

115:

- -03

- -00

–

Bit 0: Block lock-bit status register active.

Bit 1: Block lock-down bit status active.

Bit 4: EFA block lock-bit status register active.

Bit 5: EFA block lock-bit status active.

bit 0 = 1

bit 1 = 1

bit 4 = 0

bit 5 = 0

Yes

No

1.8V

(P+C)h

(P+D)h

1

V_CClogic supply highest performance program/

erase voltage.

bits 0 - 3 BCD 100 mV

116:

117:

- -18

- -90

bits 4 - 7 hex value in volts

V_PPoptimum program/erase voltage.

bits 0 - 3 BCD 100mV

9.0V

bits 4 - 7 hex value in volts

1. See Optional Features Fields table.

Note:

Table 29: Optional Features Field

Discrete

512Mb

Address

Bottom

Top

–

Bottom

Top

–

die 1 (B)

40:

die 2 (T)

--00

die 1 (T)

--40

die 2 (B)

--00

112:

--00

Table 30: One Time Programmable (OTP) Space Information

Hex Offset

Hex

Code

ASCII Value

(DQ[7:0])

P = 10Ah

Length

Description

Address

(P+E)h

1

Number of OTP block fields in JEDEC ID space.

00h indicates that 256 OTP fields are available.

118:

- -02

2

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Common Flash Interface

Table 30: One Time Programmable (OTP) Space Information (Continued)

Hex Offset

P = 10Ah

Hex

Code

ASCII Value

(DQ[7:0])

Length

Description

Address

119:

OTP Field 1: OTP Description:

- -80

- -00

- -03

80h

00h

This field describes user-available OTP bytes.

Some are preprogrammed with device-unique se-

rial numbers. Others are user-programmable.

Bits 0-15 point to the OTP Lock byte (the first

byte).

11A:

1B:

8 byte

11C:

(P+F)h

(P+10)h

(P+11)h

(P+12)h

The following bytes are factory preprogrammed

and user-programmable:

Bits 0 - 7 = Lock/bytes JEDEC plane physical low

address.

4

Bits 8 - 15 = Lock/bytes JEDEC plane physical high

address.

Bits 16 - 23 = n where 2ⁿequals factory preprog-

rammed bytes.

Bits 24 - 31 = n where 2ⁿequals user-programma-

ble bytes.

(P+13)h

(P+14)h

(P+15)h

(P+16)h

10

Protection field 2: protection description

Bits 0 - 31 point to the protection register physi-

cal lock word address in the JEDEC plane.

The bytes that follow are factory or user-progam-

mable.

11D:

11E:

11F:

120:

- -89

- -00

89h

00h

(P+17)h

(P+18)h

(P+19)h

Bits 32 - 39 = n where n equals factory program-

med groups (low byte).

Bits 40 - 47 = n where n equals factory program-

med groups (high byte).

121:

122:

123:

- -00

0

Bits 48 - 55 = n where 2n equals factory program-

med bytes/groups.

(P+1A)h

(P+1B)h

(P+1C)h

Bits 56 - 63 = n where n equals user programmed

groups (low byte).

Bits 64 - 71 = n where n equals user programmed

groups (high byte).

Bits 72 - 79 = n where 2ⁿequals user programma-

ble bytes/groups.

124:

125:

126:

- -10

- -00

- -04

16

0

16

Table 31: Burst Read Information

Hex Offset

Hex

Code

ASCII Value

(DQ[7:0])

P = 10Ah

Length

Description

Address

1

Page Mode Read capability:

127:

- -05

32 byte

Bits 7 - 0 = n where 2ⁿhex value represents the

number of read-page bytes. See offset 28h for

device word width to determine page-mode data

output width. 00h indicates no read page buffer.

(P+1D)h

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Common Flash Interface

Table 31: Burst Read Information (Continued)

Hex Offset

Hex

Code

ASCII Value

(DQ[7:0])

P = 10Ah

Length

Description

Address

1

Number of synchronous mode read configuration

128:

- -04

(P+1E)h

fields that follow. 00h indicates no burst capabili-

ty.

4

1

Synchronous mode read capability configuration

1:

129:

- -01

Bits 3 - 7 = Reserved.

Bits 0 - 2 = n where 2ⁿ⁺¹hex value represents the

maximum number of continuous synchronous

reads when the device is configured for its maxi-

mum word width.

A value of 07h indicates that the device is capa-

ble of continuous linear bursts that will output

data until the internal burst counter reaches the

end of the device’s burstable address space.

This fields’s 3-bit value can be written directly to

the Read Configuration Register bits 0 - 2 if the

device is configured for its maximum word width.

See offset 28h for word width to determine the

burst data output width.

(P+1F)h

4

1

Synchronous mode read capability configuration

2.

12A:

12B:

12C:

- -02

- -03

- -07

8

16

(P+20)h

(P+21)h

(P+22)

Synchronous mode read capability configuration

3.

Synchronous mode read capability configuration

4.

Continued

Table 32: Partition and Block Erase Region Information

Hex Offset

P = 10Ah

Address

Bottom

12D:

Description

Optional Flash features and commands

Bottom

Top

Length

Top

(P+23)h

Number of device hardware-partition regions

within the device:

1

12D:

x = 0: a single hardware partition device (no

fields follow).

x specifies the number of device partition regions

containing one or more contiguous erase block

regions

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Common Flash Interface

Table 33: Partition Region 1 Information: Top and Bottom Offset/Address

Hex Offset

P = 10Ah

Address

Bottom

Description

Optional Flash features and commands

Bottom

Top

Length

Top

12E:

12F:

(P+24)h

(P+25)h

(P+24)h

(P+25)h

Data size of this Partition Region information field

(number of addressable locations, including this

field.

2

12E:

12F:

(P+26)h

(P+27)h

(P+26)h

(P+27)h

Number of identical partitions within the partition

region.

2

1

130:

131:

132:

130:

131:

132:

(P+28)h

(P+29)h

(P+28)h

(P+29)h

Number of program or erase operations allowed in a

partition:

Bits 0 - 3 = Number of simultaneous program opera-

tions.

Bits 4 - 7 = Number of simultaneous erase operations.

Simultaneous program or erase operations allowed

in other partitions while a partition in this region is

in program mode:

Bits 0 - 3 = Number of simultaneous program opera-

tions.

1

133:

134:

135:

133:

134:

135:

Bits 4 - 7 = Number of simultaneous erase operations.

(P+2A)h

(P+2B)h

(P+2A)h

(P+2B)h

Simultaneous program or erase operations allowed

in other partitions while a partition in this region is

in erase mode:

Bits 0 - 3 = Number of simultaneous program opera-

tions.

Bits 4 - 7 = Number of simultaneous erase operations.

Types of erase block regions in this partition region:

x=0: No erase blocking; the partition region erases in

bulk.

x = Number of erase block regions with contiguous,

same-size erase blocks.

Symmetrically blocked partitions have one blocking

region.

Partition size = (Type 1 blocks) x (Type 1 block sizes) +

(Type 2 blocks) x (Type 2 block sizes) +...+ (Type n

blocks) x (Type n block sizes).

Table 34: Partition Region 1 Information

Hex Offset

P = 10Ah

Description

Address

Bottom/Top

Optional Flash features and commands

Length

Bottom/Top

(P+2C)h

(P+2D)h

(P+2E)h

(P+2F)h

Partition region 1 erase block type 1 information:

Bits 0-15 = y, y+1 = Number of identical-sized erase blocks in a

partition.

4

136:

137:

138:

139:

Bits 16-31 = z, where region erase block(s) size is z x 256 bytes.

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Common Flash Interface

Table 34: Partition Region 1 Information (Continued)

Hex Offset

P = 10Ah

Description

Address

Bottom/Top

Optional Flash features and commands

Length

Bottom/Top

(P+30)h

(P+31)h

Partition 1 (erase block type 1):

Minimum block erase cycles x 1000

2

13A:

13B:

13C:

(P+32)h

(P+33)h

Partition 1 (erase block type 1) bits per cell; internal ECC:

Bits 0 - 3 = bits per cell in erase region

Bit 4 = reserved for “internal ECC used” (1=yes, 0=no)

Bit 5 - 7 = reserved for future use

1

Partition 1 (erase block type 1) page mode and synchronous

mode capabilities:

13D:

Bits 0 = page-mode host reads permitted (1=yes, 0=no)

Bit 1 = synchronous host reads permitted (1=yes, 0=no)

Bit 2 = synchronous host writes permitted (1=yes, 0=no)

Bit 3 - 7 = reserved for future use

(P+34)h

(P+35)h

(P+36)h

(P+37)h

(P+38)h

(P+39)h

Partition 1 (erase block type 1) programming region information:

Bits 0 - 7 = x, 2^x: programming region aligned size (bytes)

Bit 8-14 = reserved for future use

Bit 15 = legacy flash operation; ignore 0:7

Bit 16 - 23 = y: control mode valid size (bytes)

Bit 24 - 31 = reserved for future use

6

13E:

13F:

140:

141:

142:

143:

Bit 32 - 39 = z: control mode invalid size (bytes)

Bit 40 - 46 = reserved for future use

Bit 47 = legacy flash operation (ignore 23:16 and 39:32)

(P+3A)h

(P+3B)h

(P+3C)h

(P+3D)h

Partition 1 erase block type 2 information:

Bits 0-15 = y, y+1 = Number of identical-size erase blocks in a par-

tition.

Bits 16 - 31 = z, where region erase block(s) size is z x 256 bytes.

(bottom parameter device only)

4

144:

145:

146:

147:

(P+3E)h

(P+3F)h

Partition 1 (erase block type 2)

Minimum block erase cycles x 1000

2

1

148:

149:

14A:

(P+40)h

Partition 1 (erase block type 2) bits per cell, internal EDAC:

Bits 0 - 3 = bits per cell in erase region

Bit 4 = reserved for “internal ECC used” (1=yes, 0=no)

Bits 5 - 7 = reserved for future use

(P+41)h

Partition 1 (erase block type 2) page mode and synchronous

mode capabilities:

1

14B:

Bit 0 = page-mode host reads permitted (1=yes, 0=no)

Bit 1 = synchronous host reads permitted (1=yes, 0=no)

Bit 2 = synchronous host writes permitted (1=yes, 0=no)

Bits 3-7 = reserved for future use

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Common Flash Interface

Table 34: Partition Region 1 Information (Continued)

Hex Offset

P = 10Ah

Description

Address

Bottom/Top

Optional Flash features and commands

Length

Bottom/Top

(P+42)h

(P+43)h

(P+44)h

(P+45)h

(P+46)h

(P+47)h

Partition 1 (erase block type 2) programming region information:

Bits 0-7 = x, 2ⁿx = Programming region aligned size (bytes)

Bits 8-14 = reserved for future use

Bit 15 = legacy flash operation (ignore 0:7)

Bits 16 - 23 = y = Control mode valid size in bytes Bits 24 - 31 =

reserved

6

14C:

14D:

14E:

14F:

150:

151:

Bits 32 - 39 = z = Control mode invalid size in bytes

Bits 40 - 46 = reserved

Bit 47 = legacy flash operation (ignore 23:16 and 39:32)

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Common Flash Interface

Table 35: Partition Region 1: Partition and Erase Block Map Information

256Mb

Address

12D:

12E:

12F:

130:

131:

132:

133:

134:

135:

136:

137:

138:

139:

13A:

13B:

13C:

13D:

13E:

13F:

140:

141:

142:

143:

144:

145:

146:

147:

148:

149:

14A:

14B:

14C:

14D:

14E:

14F:

150:

151:

Bottom

- -01

- -24

- -00

- -01

- -00

- -11

- -00

- -02

- -03

- -00

- -80

- -00

- -64

- -00

- -02

- -03

- -00

- -80

- -00

- -80

- -FE

- -00

- -02

- -64

- -00

- -02

- -03

- -00

- -80

- -00

- -80

Top

- -01

- -24

- -00

- -01

- -00

- -11

- -00

- -02

- -FE

- -00

- -02

- -64

- -00

- -02

- -03

- -00

- -80

- -00

- -80

- -03

- -00

- -80

- -00

- -64

- -00

- -02

- -03

- -00

- -80

- -00

- -80

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Common Flash Interface

Table 36: CFI Link Information

Offset

ASCII Value

P = 10Ah

Length

Description

Address

(DQ[7:0])

CFI Link field bit definitions:

(P+48)h

4

Bits 0 - 9 = Address offset (within 32Mbit segment of refer-

enced CFI table)

152:

See Note 1

(P+49)h

(P+4A)h

(P+4B)h

(P+4C)h

Bits 10 - 27 = nth 32Mbit segment of referenced CFI table

Bits 28 - 30 = Memory Type

153:

154:

155:

156:

Bit 31 = Another CFI link field immediately follows

1

CFI Link field quantity subfield definitions:

Bits 0 - 3 = Quantity field (n such that n+1 equals quantity)

Bit 4 = Table and die relative location

Bit 5 = Link field and table relative location

Bits 6 - 7 = Reserved

1. See Additional CFI Link Field table.

Note:

Table 37: Additional CFI Link Field

Discrete

512Mb

Address

Bottom

–

Top

–

Bottom

Top

die 1 (B)

--10

die 2 (T)

--FF

die 1 (T)

--10

die 2 (B)

--FF

152:

153:

154:

155:

156:

--FF

--20

--FF

--20

--FF

--00

--FF

--00

--FF

--00

--FF

--00

--FF

--10

--FF

--10

--FF

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Flowcharts

Figure 17: Word Program Procedure

Start

Command Cycle

- Issue PROGRAM command

- Address = location to program

- Data = 0x40

Data Cycle

- Address = location to program

- Data = data to program

Check Ready Status

- READ STATUS REGISTER command not required

- Perform READ operation

- Read ready status on signal D7

No

Program suspend

(See Suspend/Resume

Flowchart

No

Yes

D7 = 1?

Suspend?

Errors?

Yes

Read Status Register

- Toggle CE# or OE# to update status register

- See Status Register Flowchart

Error-handler

user-defined routine

Progam

complete

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Flowcharts

Figure 18: Buffer Program Procedure

Start

X = X + 1

Write buffer data,

start address

Write buffer data,

(at block address)

within buffer range

No

Device

supports buffer

writes?

No

Use single word

programming

X = 0

Yes

Abort

No

X = N

bufferred program

?

Set timeout or

loop counter

Yes

Get next

target address

Write confirm D0h

(at block address)

Write to another

block address

Buffered program

aborted

Read status register

(at block address)

CE# and OE# LOW

updates status register

Issue WRITE-to-BUFFER

command E8h

(at block address)

SR[7]?

1 = Ready

0 = Busy

0

Suspend

program loop

Suspend

program

Read status register

SR.7 = Valid

(at block address )

1

No

Full status

check (if desired)

Device

ready? SR[7] = 0/1

Timeout

or count expired?

0 = No

Yes

Another

buffered

programming

?

Yes

1 = Yes

Write word count (N-1)

N = 0 corresponds to

count = 1

No

(at block address)

Program

complete

1. Word count values on DQ0:DQ15 are loaded into the count register. Count ranges for

this device are N = 0000h to 01FFh.

Notes:

2. Device outputs the status register when read.

3. Write buffer contents will be programmed at the device start address or destination ad-

dress.

4. Align the start address on a write buffer boundary for maximum programming perform-

ance; that is, A[9:1] of the start address = 0).

5. Device aborts the BUFFERED PROGRAM command if the current address is outside the

original block address.

6. Status register indicates an improper command sequence if the BUFFERED PROGRAM

command is aborted. Follow this with a CLEAR STATUS REGISTER command.

7. Device defaults to SR output data after Buffered Programming Setup Command (E8h) is

issued . CE# or OE# must be toggled to update Status Register . Don’t issue the Read SR

command (70h); it is interpreted by the device as Buffer Word Count.

8. Full status check can be done after erase and write sequences complete. Write FFh after

the last operation to reset the device to read array mode.

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Flowcharts

Figure 19: Buffered Enhanced Factory Programming (BEFP) Procedure

Setup Phase

Program and Verify Phase

Exit Phase

Read status

register

Read status

register

Start

Issue BEFP SETUP

Data = 0x80

Buffer ready?

BEFP exited?

No (SR[0] = 1)

No (SR[7] = 0)

Yes (SR[7] = 1)

Yes (SR[0] = 0)

Issue BEFP CONFIRM

Data = 00D0h

Full status

register check

for errors

Write data

word to buffer

BEFP setup

delay

No

Buffer full?

Yes

Finish

Read status

register

Read status

register

Yes (SR[7] = 0)

BEFP setup

done?

No (SR[0] = 1)

Program

done?

No (SR[7] = 1)

SR error-handler

user-defined

Yes (SR[0] = 0)

Yes

Program

more data

Exit

?

No

Write 0xFFFF

outside block

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Flowcharts

Figure 20: Block Erase Procedure

Start

Command Cycle

- Issue ERASE command

- Address = block to be erased

- Data = 0x20

Confirm Cycle

- Issue CONFIRM command

- Address = block to be erased

- Data = erase confirm (0xD0)

Check Ready Status

- READ STATUS REGISTER

command not required

- Perform READ operation

- Read ready status on SR[7]

No

Erase Suspend

See Suspend/

Resume Flowchart

Yes

No

SR[7] = 1?

Suspend?

Errors?

Yes

Read Status Register

- Toggle CE# or OE#

to update status register

- See Status Register Flowchart

Error Handler

user-defined

routine

End

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Flowcharts

Figure 21: Program Suspend/Resume Procedure

Start

=

SR.2

0

Program

Completed

1 = Suspended

0 = Completed

Read Status

Write 70h

1

Any Address

Read Array

Program Suspend

Write FFh

Any Address

Write B0h

Any Address

Read Array Data

from a block other than

from the one being

programmed

Read Status Register

Initiate Read cycle to

update the status register

(Address = Block to suspend)

Done

No

Reading

=

SR.7

0

Yes

1 = Ready

0 = Busy

Read Array

Write FFh

Program Resume

1

Write D0h

Any Address

Program

Resumed

Read Array

Data

Read Status

Write 70h

Any Address

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Flowcharts

Figure 22: Erase Suspend/Resume Procedure

=

SR.6

Start

0

Erase

Completed

1 = Suspended

0 = Completed

Read Status

1

Write 70h

Any Address

Read

Program

Erase Suspend

Read/Program?

(FFh/40h)

Write B0h

Any Address

Read Array Data from

a block other than the

one being erased

Program Loop: to a

block other than the

one being erased

No

Done?

Address = X

Read Status Register

Toggle CE#/OE# to

update the

status register

Yes

Erase Resume

=

SR.7

0

1 = Ready

0 = Busy

Read Array

Write D0h

Any Address

1

Write FFh

1

Erase

Resumed

Read Array

Data

Read Status

Write 70h

Any Address

1. The ^tERS/SUSP timing between the initial block erase or erase resume command and a

subsequent erase suspend command should be followed.

Note:

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Flowcharts

Figure 23: Block Lock Operations Procedure

Start

Lock Setup

Write 60h

Block Address

Lock Confirm

Write 01h, D0h, 2Fh

Block Address

Read ID Plane

Write 90h

Read Block

Lock Status

Optional

No

Locking

Change?

Yes

Read Array

Write FFh

Any Address

Lock Change

Complete

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Flowcharts

Figure 24: OTP Register Programming Procedure

Start

OTP Program Setup

- Write 0xC0

- OTP Address

Confirm Data

- Write OTP Address and Data

Check Ready Status

- READ STATUS REGISTER

command not required

- Perform READ operation

- Read ready status on SR[7]

No

SR[7] = 1?

Yes

Read Status Register

- Toggle CE# or OE#

to update status register

- See Status Register Flowchart

End

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Flowcharts

Figure 25: Status Register Procedure

Start

Command Cycle

- Issue STATUS REGISTER command

- Address = any device address

- Data = 0x70

Data Cycle

- Read Status Register SR[7:0]

No

SR[7] = 1

Yes

Erase Suspend

See Suspend/

Yes

SR[6] = 1

Resume Flowchart

No

Program Suspend

See Suspend/

Resume Flowchart

Yes

SR[2] = 1

No

Error

Command

sequence

No

SR[5] = 1

SR[4] = 1

Yes

Error

Erase failure

No

Yes

Error

Program failure

SR[4] = 1

No

Error

V

/V

<

SR[3] = 1

PEN PP

/V

PENLK PPLK

No

Error

Block locked

SR[1] = 1

No

End

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Power-Up and Power-Down

Power supply sequencing is not required if V_PPis connected to V_CCor V_CCQ. Otherwise,

V_CCshould attain V_CCminbefore applying V_CCQand V_PP. Device inputs should not be

driven before supply voltage = V_CCmin

.

Power supply transitions should only occur when RST# is low. This protects the device

from accidental programming or erasure during power transitions.

Reset Specifications

Asserting RST# during a system reset is important with automated program/erase devi-

ces because systems typically expect to read from flash memory when coming out of re-

set. If a CPU reset occurs without a flash memory reset, proper CPU initialization may

not occur. This is because the flash memory may be providing status information, in-

stead of array data as expected. Connect RST# to the same active low reset signal used

for CPU initialization.

Also, because the device is disabled when RST# is asserted, it ignores its control inputs

during power-up/down. Invalid bus conditions are masked, providing a level of memo-

ry protection.

Table 38: Power and Reset

Number

Symbol Parameter

t_PLPHRST# pulse width low

t_PLRH

Min

100

-

Max

Unit

ns

Notes

P1

P2

-

1, 2, 3, 4

1, 3, 4, 7

1, 4, 5, 6

RST# low to device reset during erase

RST# low to device reset during program

V_CCPower valid to RST# de-assertion (high)

25

-

us

-

P3

t_VCCPH

300

1. These specifications are valid for all device versions (packages and speeds).

2. The device may reset if t_PLPHis < t_{PLPH MIN}, but this is not guaranteed.

3. Not applicable if RST# is tied to Vcc.

Notes:

4. Sampled, but not 100% tested.

5. When RST# is tied to the V_CCsupply, device will not be ready until t_VCCPHafter V_CC

V_CCMIN

6. When RST# is tied to the V_CCQsupply, device will not be ready until t_VCCPHafter V_CC

V_CCMIN

≥

.

≥

.

7. Reset completes within t_PLPHif RST# is asserted while no erase or program operation is

executing.

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Power Supply Decoupling

Figure 26: Reset Operation Waveforms

^tPLPH

^tPLRH

^tPHQV

V_IH

V_IL

(A) Reset during

RST#

read mode

Abort

^tPHQV

complete

V_IH

V_IL

(B) Reset during

program or block erase

P1 £ P2

RST#

^tPLRH

^tPHQV

Abort

complete

V_IH

V_IL

(C) Reset during

program or block erase

P1 ³ P2

^tVCCPH

(D) V_CCpower-up to

RST# HIGH

V_CC

0V

V

CC

Power Supply Decoupling

Flash memory devices require careful power supply de-coupling. Three basic power

supply current considerations are 1) standby current levels, 2) active current levels, and

3) transient peaks produced when CE# and OE# are asserted and deasserted.

When the device is accessed, many internal conditions change. Circuits within the de-

vice enable charge-pumps, and internal logic states change at high speed. All of these

internal activities produce transient signals. Transient current magnitudes depend on

the device outputs’ capacitive and inductive loading. Two-line control and correct de-

coupling capacitor selection suppress transient voltage peaks.

Because flash memory devices draw their power from VCC, VPP, and VCCQ, each power

connection should have a 0.1 µF ceramic capacitor to ground. High-frequency, inher-

ently low-inductance capacitors should be placed as close as possible to package leads.

Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor

should be placed between power and ground close to the devices. The bulk capacitor is

meant to overcome voltage droop caused by PCB trace inductance.

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Absolute Maximum Ratings

Caution: Stressing the device beyond the “Absolute Maximum Ratings” may cause per-

manent damage. These are stress ratings only.

Table 39: Absolute Maximum Ratings

Parameter

Maximum Rating

–40 °C to + 85 °C

–65 °C to + 125 °C

–2.0 V to + 4.0 V

–2.0 V to + 11.5 V

–2.0 V to + 4.0 V

–2.0 V to + 5.6 V

100 mA

Notes

Temperature under bias

Storage temperature

Voltage on any signal (except V_CC, V_PPand V_CCQ

V_PPvoltage

-

)

1

1, 2

1

V_CCvoltage

V_CCQvoltage

1

Output short circuit current

3

1. Voltages shown are specified with respect to VSS. During infrequent non-periodic transi-

tions, the level may undershoot to –2.0 V for periods less than 20 ns or overshoot to V_CC

+ 2.0 V or V_CCQ+ 2.0 V for periods less than 20 ns.

Notes:

2. Program/erase voltage is typically 1.7 V ~ 2.0 V. 9.0 V can be applied for 80 hours maxi-

mum total. 9.0 V program/erase voltage may reduce block cycling capability.

3. Output shorted for no more than one second. No more than one output shorted at a

time.

Operating Conditions

Caution: Operation beyond the “Operating Conditions” is not recommended and ex-

tended exposure beyond the “Operating Conditions” may affect device reliability.

Table 40: Operating Conditions

Symbol

T_C

Parameter

Min

–40

Max

+85

2.0

3.6

9.5

80

-

Unit Notes

Operating Temperature

V_CCSupply Voltage

I/O Supply Voltage

°C

V

1

3

V_CC

1.7

V_CCQ

CMOS inputs

TTL inputs

1.7

2.4

V_PPL

V_PPH

t_PPH

V_PPVoltage Supply (Logic Level)

0.9

2

Buffered Enhanced Factory Programming V_PP

Maximum V_PPHours

8.5

V_PP= V_PPH

V_PP= V_PPL

V_PP= V_PPH

-

Hours

Cycles

Block Erase Main and Parameter Blocks

100,000

Cycles

Main Blocks

-

Parameter Blocks

-

1. T_C= Case Temperature.

Notes:

2. In typical operation VPP program voltage is V_PPL

.

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DC Current Characteristics

Table 41: DC Current Characteristics

CMOS Inputs

TTL Inputs

(V_CCQ= 1.7V - (V_CCQ= 2.4 V -

3.6 V) 3.6 V)

Typ Max Unit Test Conditions

Sym-

bol Parameter

Typ

Max

Notes

I_LI

Input Load Current

-

±1

-

±2

µA V_CC= V_CCMax V_CCQ= V_CCQMax

1, 6

V_IN= V_CCQor V_SS

I_LO

Output DQ[15:0], WAIT

Leakage

-

±1

-

±10

µA V_CC= V_CCMax V_CCQ= V_CCQMax

V_IN= V_CCQor V_SS

Current

I_CCS

,

V_CCStandby,

256-Mbit

512-Mbit

65

210

420

65

210

420

µA V_CC= V_CCMax V_CCQ= V_CCQMax

CE# = V_CCQRST# = V_CCQ(for I_CCS

RST# = V_SS(for I_CCD) WP# = V_IH

1. 2

1

I_CCDPower-Down

)

130

I_CCRAverage Asynchronous Sin-

26

31

26

31

mA 16-Word Read V_CC= V_CCMax

V_CC

Read

Current

gle-Word f = 5 MHz

(1 CLK)

CE# = V_IL

OE# = V_IH

Inputs: V_ILor

Page-Mode Read f =

13 MHz (17 CLK)

12

16

12

16

mA 16-Word Read

V_IH

Synchronous Burst f

= 52 MHz, LC=4

19

16

21

22

18

24

19

16

21

22

18

24

mA 8-Word Read

mA 16-Word Read

mA Continuous

Read

I_CCW,V_CCProgram Current,

I_CCEV_CCErase Current

35

50

35

50

mA V_PP= V_PPL

Pgm/Ers in progress

V_PP= V_PPH

Pgm/Ers in progress

µA CE# = V_CCQ; suspend in progress 1, 3, 4

,

1, 3, 5

,

1, 3, 5

I_CCWS,V_CCProgram Sus-

I_CCESpend Current,

V_CCErase Suspend

Current

256-Mbit

512-Mbit

65

70

210

225

65

70

210

225

I_PPS,V_PPStandby Current,

0.2

5

0.2

5

µA V_PP= V_PPL

,

1, 3, 7

I_PPWS,V_PPProgram Suspend Current,

V_PPErase Suspend Current

suspend in progress

IPPES

I_PPRV_PPRead

2

15

2

15

µA V_PP= V_PPL

1, 3

3

I_PPWV_PPProgram Current

0.05

0.10

0.05

0.10

mA V_PP= V_PPL,program in progress

V_PP= V_PPH,program in progress

mA V_PP= V_PPL,erase in progress

V_PP= V_PPH,erase in progress

mA V_PP= V_PPL

I_PPEV_PPErase Current

I_PPBCV_PPBlank Check

3

V_PP= V_PPH

1. All currents are RMS unless noted. Typical values at typical V_CC, T_C= +25 °C.

Notes:

2. I_CCSis the average current measured over any 5 ms time interval 5 µs after CE# is deas-

serted.

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DC Voltage Characteristics

3. Sampled, not 100% tested.

4. I_CCESis specified with the device deselected. If device is read while in erase suspend, cur-

rent is I_CCESplus I_CCR

.

5. I_CCW, I_CCEmeasured over typical or max times specified in Program and Erase Characteris-

tics (page 94) .

6. if V_IN> V_CCthe input load current increases to 10uA max.

7. the I_{PPS, PPWS, PPES}Will increase to 200uA when Vpp/WP# is at V_PPH.

I

DC Voltage Characteristics

Table 42: DC Voltage Characteristics

CMOS Inputs (V_CCQ = TTL Inputs ⁽¹⁾(V_CCQ =

1.7 V – 3.6 V) 2.4 V – 3.6 V)

Min Max Min Max

-0.5 0.4 -0.5 0.6

V_CCQ– 0.4 V_CCQ+ 0.5

Symbol Parameter

Unit Test Conditions

Notes

V_IL

V_IH

V_OL

Input Low Voltage

V

2

Input High Voltage

Output Low Voltage

2

-

V_CCQ+ 0.5

0.2

-

0.2

V

V_CC= V_CCMin V_CCQ

V_CCQMin I_OL= 100 µA

V_CC= V_CCMin V_CCQ

V_CCQMin I_OH= –100 µA

=

-

V_OH

Output High Voltage

V_CCQ– 0.2

-

V_CCQ– 0.2

-

V

=

V_PPLKV_PPLock-Out Voltage

V_LKOV_CCLock Voltage

V_LKOQV_CCQLock Voltage

-

0.4

-

0.4

-

V

3

-

1.0

0.9

1.5

1.0

0.9

1.5

-

V_PPL

V_PPVoltage Supply

(Logic Level)

3.6

V_PPH

Buffered Enhanced

Factory Programming

V_PP

8.5

9.5

8.5

9.5

V

1. Synchronous read mode is not supported with TTL inputs.

Notes:

2. V_ILcan undershoot to –1.0 V for duration of 2ns or less and V_IHcan overshoot to V_CCQ

1.0 V for durations of 2ns or less.

+

3. V_PP≤ V_PPLKinhibits erase and program operations. Do not use V_PPLand V_{PPH outside their}

valid ranges.

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AC Test Conditions

Figure 27: AC Input/Output Reference Timing

V_CCQ

Input V

/2

Test points

V

/2 output

CCQ

0V

1. AC test inputs are driven at V_CCQfor Logic "1" and 0 V for Logic "0". Input/output tim-

ing begins/ends at V_CCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case

Note:

speed occurs at V_CC= V_CCMin

.

Figure 28: Transient Equivalent Load Circuit

Device under

test

Out

C

L

1. See the Test Configuration Component Value For Worst Case Speed Conditions table for

component values.

Notes:

2. CL includes jig capacitance.

Table 43: Test Configuration: Worst Case Speed Condition

Test Configuration

C_L(pF)

V_CCQMin Standard Test

30

Figure 29: Clock Input AC Waveform

^tCLK

V_IH

V_IL

CLK

^tCH/CL

^tFCLK/RCLK

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Capacitance

Table 44: Capacitance

Parameter

Signal

Density

Min

Typ

7

Max

8

Unit

Condition

Notes

Input

Capacitance

Address, Data,

CE#, WE#, OE#,

RST#, CLK,

256Mb

3

6

pF

Typ temp = 25 °C, Max temp

= 85 °C, V_CC= (0 V - 2.0 V),

V_CCQ= (0 V - 3.6 V), Discrete

silicon die

1

256Mb/

256Mb

14

16

ADV#, WP#

Output

Capacitance

Data, WAIT

256Mb

3

6

5

7

256Mb/

256Mb

10

14

1. Sampled, but not 100% tested.

Note:

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AC Read Specifications

Table 45: AC Read Specifications

Number Symbol Parameter

Asynchronous Specifications

Min

Max

Unit

Note

R1

R2

R3

t_AVAV

t_AVQV

t_ELQV

Read cycle time

Easy BGA/QUAD+

TSOP

100

110

-

ns

-

Address to output valid

CE# low to output valid

Easy BGA/QUAD+

TSOP

100

110

100

110

25

-

Easy BGA/QUAD+

TSOP

-

R4

R5

R6

R7

R8

t_GLQV

t_PHQV

t_ELQX

t_GLQX

t_EHQZ

OE# low to output valid

RST# high to output valid

CE# low to output in low-Z

OE# low to output in low-Z

-

1, 2

1

150

-

0

-

1, 3

1, 2, 3

1, 3

-

CE# high to output in high-

Z

20

R9

t_GHQZ

t_OH

OE# high to output in high-

Z

-

15

-

ns

R10

Output hold from first oc-

curring address, CE#, or OE#

change

0

R11

R12

R13

R15

R16

R17

t_EHEL

t_ELTV

t_EHTZ

t_GLTV

t_GLTX

t_GHTZ

CE# pulse width high

17

-

ns

1

CE# low to WAIT valid

CE# high to WAIT high-Z

OE# low to WAIT valid

OE# low to WAIT in low-Z

OE# high to WAIT in high-Z

17

20

17

-

1, 3

1

-

0

-

1, 3

20

Latching Specifications

R101

R102

R103

t_AVVH

t_ELVH

t_VLQV

Address setup to ADV# high

CE# low to ADV# high

10

-

ns

1

-

ADV# low to output valid

Easy BGA/QUAD+

TSOP

100

-

110

R104

R105

R106

t_VLVH

t_VHVL

t_VHAX

ADV# pulse width low

ADV# pulse width high

10

9

-

Address hold from ADV#

high

1, 4

1

R108

R111

t_APA

Page address access

-

25

-

ns

t_PHVH

RST# high to ADV# high

30

Clock Specifications

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AC Read Specifications

Table 45: AC Read Specifications (Continued)

Number Symbol Parameter

Min

-

Max

Unit

MHz

ns

Note

R200

R201

R202

R203

f_CLK

CLK frequency

Easy BGA/QUAD+

TSOP

52

40

-

1, 3, 5

-

t_CLK

CLK period

Easy BGA/QUAD+

TSOP

19.2

25

5

-

ns

t_CH/CL

CLK high/low time

Easy BGA/QUAD+

TSOP

-

ns

9

t_FCLK/RCLKCLK fall/rise time

0.3

3

ns

Synchronous Specifications⁽⁵⁾

R301

R302

R303

R304

t_AVCH/LAddress setup to CLK

-

9

-

ns

1, 6

t_VLCH/L

t_ELCH/L

ADV# low setup to CLK

CE# low setup to CLK

CLK to output valid

-

t_{CHQV /}

Easy BGA/QUAD+

17

20

-

tCLQV

TSOP

-

1, 6

R305

R306

R307

t_CHQX

t_CHAX

t_CHTV

Output hold from CLK

Address hold from CLK

CLK to WAIT valid

-

3

10

-

1, 4, 6

1, 6

Easy BGA/QUAD+

17

20

-

TSOP

-

R311

R312

t_CHVL

t_CHTX

CLK Valid to ADV# Setup

WAIT Hold from CLK

-

3

5

ns

1

Easy BGA/QUAD+

TSOP

-

1, 6

-

1. See on page for timing measurements and max allowable input slew rate.

Notes:

2. OE# may be delayed by up to t_ELQV– t_GLQVafter CE#’s falling edge without impact to

t_ELQV.

3. Sampled, not 100% tested.

4. Address hold in synchronous burst mode is t_CHAXor t_VHAX, whichever timing specifica-

tion is satisfied first.

5. Synchronous read mode is not supported with TTL level inputs.

6. Applies only to subsequent synchronous reads.

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AC Read Specifications

Figure 30: Asynchronous Single Word Read (ADV# LOW)

^tAVAV

^tAVQV

A

ADV#

CE#

^tELQV

^tEHQZ

^tGHQZ

^tGLQV

OE#

^tGLTV

^tGHTZ

WAIT

^tGLQX

^tELQX

DQ

^tPHQV

RST#

1. WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).

Note:

Figure 31: Asynchronous Single Word Read (ADV# Latch)

^tAVAV

^tAVQV

A[MAX:5]

A[4:1]

^tAVVH

^tVHAX

^tVHVL

ADV#

CE#

^tELQV

^tEHQZ

^tGLQV

^tGHQZ

OE#

^tGHTZ

^tGLTV

WAIT

^tGLQX

^tOH

^tELQX

DQ

1. WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).

Note:

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AC Read Specifications

Figure 32: Asynchronous Page Mode Read

^tAVQV

Valid address

A[MAX:4]

^tOH

A[3:0]

ADV#

0

1

2

F

^tAVVH

^tVHVL

^tVHAX

^tEHQZ

^tGHQZ

^tELQV

^tGLQV

CE#

OE#

WAIT

DQ

^tELQX

^tAPA

^tEHTZ

Q1

Q2

Q3

Q16

1. WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).

Note:

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AC Read Specifications

Figure 33: Synchronous Single Word Array or Nonarray Read

^tAVCH

^tCHAX

^tAVQV

CLK

A

^tAVVH

^tVHVL

^tELCH

^tVHAX

^tVLVH

ADV#

^tELVH

^tELQV

^tEHQZ

^tGHQZ

CE#

OE#

^tGLQX

^tCHTV

^tCHQV

^tGHTZ

^tCHTX

WAIT

^tGLQV

^tCHQX

DQ

1. WAIT is driven per OE# assertion during synchronous array or non-array read, and can

be configured to assert either during or one data cycle before valid data.

Notes:

2. This diagram illustrates the case in which an n-word burst is initiated to the flash memo-

ry array and it is terminated by CE# deassertion after the first word in the burst.

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AC Read Specifications

Figure 34: Continuous Burst Read with Output Delay (ADV# LOW)

t

AVCH

t

VLCH CHAX

CHQV

CLK

t

AVQV

t

AVVH

A

t

VHAX

VHVL

ADV#

t

ELCH

t

ELVH

t

ELQV

CE#

OE#

t

GLTV

CHTV

CHTX

WAIT

DQ

t

CHQV

t

GLQV

t

CHQX

t

CHQX

GLQX

1. WAIT is driven per OE# assertion during synchronous array or non-array read, and can

be configured to assert either during or one data cycle before valid data.

Notes:

2. At the end of Word Line; the delay incurred when a burst access crosses a 16-word

boundary and the starting address is not 4-word boundary aligned.

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AC Read Specifications

Figure 35: Synchronous Burst Mode 4-Word Read

^tAVCH

Latency count

^tAVQV

^tVLCH ^tCHAX

CLK

^tAVVH

A

^tVHAX

^tVHVL

^tELVH

ADV#

^tELCH

^tELQV

CE#

OE#

^tCHTX

^tGLTV

^tCHTV

^tCHQV

^tCHTX

WAIT

DQ

^tCHQV

^tCHQX

^tGLQV

^tGLQX

^tCHQX

Q0

Q1

Q2

Q3

1. WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT as-

serted during initial latency and deasserted during valid data (RCR.10 = 0, WAIT asserted

low).

Note:

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AC Write Specifications

Table 46: AC Write Specifications

Number

W1

Symbol

t_PHWL

t_ELWL

Parameter

Min

Max

Unit

ns

Notes

1, 2, 3

1, 2, 4

1, 2, 12

1, 2

RST# high recovery to WE# low

CE# setup to WE# low

WE# write pulse width low

Data setup to WE# high

Address setup to WE# high

CE# hold from WE# high

Data hold from WE# high

Address hold from WE# high

WE# pulse width high

V_PPsetup to WE# high

V_PPhold from Status read

WP# hold from Status read

WP# setup to WE# high

WE# high to OE# low

150

-

W2

0

W3

t_WLWH

t_DVWH

t_AVWH

t_WHEH

t_WHDX

t_WHAX

t_WHWL

t_VPWH

t_QVVL

50

W4

50

W5

50

W6

0

W7

0

W8

0

W9

20

1, 2, 5

W10

W11

W12

W13

W14

W16

200

1, 2, 3, 7

0

t_QVBL

0

200

1, 2, 3, 7

1, 2, 9

t_BHWH

t_WHGL

t_WHQV

0

WE# high to read valid

t_AVQV+ 35

1, 2, 3, 6,

10

Write to Asynchronous Read Specifications

W18 t_WHAVWE# high to Address valid

Write to Synchronous Read Specifications

0

-

ns

1, 2, 3, 6, 8

W19

W20

W28

t_WHCH/L

t_WHVH

t_WHVL

WE# high to Clock valid

WE# high to ADV# high

WE# high to ADV# low

19

7

-

ns

1, 2, 3, 6,

10

Write Specifications with Clock Active

W21

W22

t_VHWL

t_CHWL

Notes:

ADV# high to WE# low

Clock high to WE# low

-

20

ns

1, 2, 3, 11

1. Write timing characteristics during erase suspend are the same as write-only operations.

2. A write operation can be terminated with either CE# or WE#.

3. Sampled, not 100% tested.

4. Write pulse width low (t_WLWHor t_ELEH) is defined from CE# or WE# low (whichever occurs

last) to CE# or WE# high (whichever occurs first). Thus, t_WLWH= t_ELEH= t_WLEH= t_ELWH

.

5. Write pulse width high (t_WHWLor t_EHEL) is defined from CE# or WE# high (whichever oc-

curs first) to CE# or WE# low (whichever occurs last). Thus, t_WHWL= t_EHEL= t_WHEL= t_EHWL).

6. t_WHVHor t_WHCH/Lmust be met when transiting from a write cycle to a synchronous burst

read.

7. V_PPand WP# should be at a valid level until erase or program success is determined.

8. This specification is only applicable when transiting from a write cycle to an asynchro-

nous read. See spec W19 and W20 for synchronous read.

9. When doing a Read Status operation following any command that alters the Status Reg-

ister, W14 is 20 ns.

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AC Write Specifications

10. Add 10 ns if the write operation results in a RCR or block lock status change, for the sub-

sequent read operation to reflect this change.

11. These specs are required only when the device is in a synchronous mode and clock is ac-

tive during address setup phase.

12. This specification must be complied with by customer’s writing timing. The result would

be unpredictable if any violation to this timing specification.

Figure 36: Write to Write Timing

Figure 37: Asynchronous Read to Write Timing

^tAVAV

^tAVQV

^tAVWH

^tWHAX

A

^tEHQZ

^tELQV

CE#

^tGLQV

^tGHQZ

OE#

^tELWL

^tWLWH

^tWHEH

WE#

^tGLTV

^tGHTZ

^tOH

WAIT

^tGLQX

^tELQX

^tWHDX

^tDVWH

DQ

Q

D

^tPHQV

RST#

1. WAIT deasserted during asynchronous read and during write. WAIT High-Z during write

per OE# deasserted.

Note:

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AC Write Specifications

Figure 38: Write to Asynchronous Read Timing

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AC Write Specifications

Figure 39: Synchronous Read to Write Timing

t

AVCH

Latency count

t

VLCH CHAX

CLK

t

AVQV

t

AVVH

WHAV

AVWH

A

t

VHVL

t

VHAX

t

ELVH

t

VLVH

ADV#

t

EHEL

ELCH

t

ELQV

t

EHTZ

WHEH

CE#

OE#

t

EHQZ

GLQV

t

VHWL

t

VHWL

t

CHWL

VLWH

t

WHAX

CHWL

ELWL

t

WHWL

WLWH

WE#

t

GLTX

CHTX

t

CHTV

WAIT

t

WHDX

CHQX

GLQX

t

CHQV

Q

DQ

D

1. WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR.

10=0, WAIT asserted low). Clock is ignored during write operation.

Note:

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AC Write Specifications

Figure 40: Write to Synchronous Read Timing

Latency count

VLCH

t

AVCH

AVQV

CLK

t

AVWH

WHAX

t

CHAX

A

t

VHAX

VLVH

ADV#

t

ELWL

WHEH

t

EHEL ELCH

CE#

WHAV

t

WHCH/L

t

WLWH

WHVH

WE#

OE#

t

GLQV

t

GLTV

t

CHTV

WAIT

t

CHQV

CHQX

t

DVWH

WHDX

ELQV

CHQV

DQ

D

Q

t

PHWL

RST#

1. WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR.

10=0, WAIT asserted low).

Note:

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Program and Erase Characteristics

Table 47: Program and Erase Specifications

V_PPL

V_PPH

Number

Symbol Parameter

Min

Typ Max Min

Typ Max Unit

Notes

Conventional Word Programming

W200

t_PROG/W

Program Single word

Time

-

270

456

-

270

456

µs

1

Buffered Programming

W250 t_PROG

Program Aligned 32-Word, BP

-

310

716

900

-

310

716

900

1

Time

time (32 words)

Aligned 64-Wd, BP

time (64 words)

Aligned 128-Wd, BP

time (128 words)

375 1140

505 1690

900 3016

375 1140

505 1690

900 3016

Aligned 256-Wd, BP

time (256 words)

one full buffer, BP

time (512 words)

Buffered Enhanced Factory Programming

W451

W452

t_BEFP/B

Program Single byte

BEFP Setup

n/a

-

0.5

-

µs

1, 2

1

t_BEFP/Setup

5

Erase and Suspend

W500

W501

t_ERS/PB

t_ERS/MB

t_SUSP/P

Erase

Time

32-KByte Parameter

128-KByte Main

-

0.8

25

4.0

30

-

0.8

25

4.0

30

-

s

1

W600

Suspend Program suspend

Latency

µs

W601

t_SUSP/E

Erase suspend

25

W602

t_ERS/SUSP

Erase to Suspend

500

1, 3

Blank Check

W702

t_BC/MB

blank

check

Main Array Block

-

3.2

-

3.2

-

ms

1. Typical values measured at T_C= +25 °C and nominal voltages. Performance numbers are

valid for all speed versions. Excludes system overhead. Sampled, but not 100% tested.

Notes:

2. Averaged over entire device.

3. W602 is the typical time between an initial block erase or erase resume command and

the a subsequent erase suspend command. Violating the specification repeatedly during

any particular block erase may cause erase failures.

PDF: 09005aef84566799

p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

94

256Mb and 512Mb (256Mb/256Mb), P30-65nm

Revision History

Rev. A – 10/12

• Initial Micron brand release

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

PDF: 09005aef84566799

p30_65nm_256Mb-512mb.pdf - Rev. A 1/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

95


型号：	PC28F256P30TFE
厂家：	MICRON TECHNOLOGY
描述：	256Mb and 512Mb (256Mb/256Mb), P30-65nm 256MB和512MB （256 / 256MB ）， P30-65nm 闪存内存集成电路
文件：	总95页 (文件大小：1351K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PC28F256P30TFE [MICRON]

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