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A14100A-CQG256B [MICROSEMI]

Field Programmable Gate Array, 1377 CLBs, 10000 Gates, 100MHz, CMOS, CQFP256, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, QFP-256;
A14100A-CQG256B
型号： A14100A-CQG256B
厂家： Microsemi    Microsemi
描述：

Field Programmable Gate Array, 1377 CLBs, 10000 Gates, 100MHz, CMOS, CQFP256, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, QFP-256

时钟 栅 现场可编程门阵列 可编程逻辑
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Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
• More than 500 Macro Functions  
Features  
• Replaces up to Twenty 32 Macro-Cell CPLDs  
• Up to 10,000 Gate Array Equivalent Gates (up to 25,000  
equivalent PLD Gates)  
• Replaces up to One Hundred 20-Pin PAL® Packages  
• Up to 1,153 Dedicated Flip-Flops  
• VQFP, TQFP, BGA, and PQFP Packages  
• Nonvolatile, User Programmable  
• Fully Tested Prior to Shipment  
• 5.0 V and 3.3 V Versions  
• Optimized for Logic Synthesis Methodologies  
• Low Power CMOS Technology  
• Highly Predictable Performance with 100% Automatic Place-  
and-Route  
• As Low as 9.0 ns Clock-to-Output Times (–1 Speed Grade)  
• Up to 186 MHz On-Chip Performance (–1 Speed Grade)  
• Up to 228 User-Programmable I/O Pins  
• Four Fast, Low-Skew Clock Networks  
Table 1 • ACT 3 Family Product Information  
Device  
A1415  
A1425  
A1440  
A1460  
A14100  
Capacity  
Gate Array Equivalent Gates  
1,500  
3,750  
40  
2,500  
6,250  
60  
4,000  
10,000  
100  
6,000  
15,000  
150  
10,000  
25,000  
250  
PLD Equivalent Gates  
TTL Equivalent Package (40 gates)  
20-Pin PAL Equivalent Packages (100 gates)  
Logic Modules  
15  
25  
40  
60  
100  
200  
104  
96  
310  
160  
150  
360  
100  
564  
848  
1,377  
697  
S-Module  
288  
432  
C-Module  
Dedicated Flip-Flops1  
276  
416  
680  
264  
568  
768  
1,153  
228  
User I/Os (maximum)  
80  
140  
168  
Maximum Performance2 (worst-case commercial, –1 speed grade)  
Chip-to-Chip3 (MHz)  
80  
47  
80  
47  
80  
47  
78  
47  
76  
47  
Accumulators (16-bit, MHz)  
Loadable Counter (16-bit, MHz)  
Prescaled Loadable Counters (16-bit, MHz)  
Datapath, Shift Registers (MHz)  
Clock-to-Output (pad-to-pad, ns)  
Packages4 (by pin count)  
82  
82  
82  
82  
78  
186  
186  
9.0  
186  
186  
9.0  
186  
186  
9.5  
150  
150  
10.0  
150  
150  
10.5  
CPGA  
PLCC  
PQFP  
RQFP  
VQFP  
TQFP  
BGA  
PG1005  
PL84  
PQ100  
–
PG1335  
PL84  
PQ100, PQ160  
PG1755  
PL84  
PQ160  
–
VQ100  
TQ176  
–
PG207  
PG257  
–
PQ160, PQ208  
–
–
–
–
VQ100  
–
RQ208  
–
VQ100  
–
TQ176  
BG2255  
CQ196  
–
–
–
–
–
BG313  
CQ256  
CQFP  
CQ132  
–
Notes:  
1. One flip-flop per S0Module, two flip-flops per I/O Module.  
2. Based on A1415A-1, A1425A-1, A1440A-1, A1460A-1, and A14100A-1.  
3. Clock-to-Output (pad-to-pad) + assumed trace delay + setup time. Refer to the "System Performance Model" on page 1-1 and  
Table 1-1 on page 1-2.  
4. See the "Product Plan" table on page III for package availability.  
5. Discontinued device and package combination.  
6. –2 and –3 speed grades have been discontinued. For more information about discontinued devices, refer to the Product  
Discontinuation Notices (PDNs) listed below, available on the Microsemi SoC Products Group website:  
PDN March 2001, PDN 0104, PDN 0203, PDN 0604, PDN 1004  
January 2012  
I
© 2012 Microsemi Corporation  
Accelerator Series FPGAs – ACT 3 Family  
Ordering Information  
_
RQ  
G
208  
A
1
A14100  
C
Application (Temperature Range)  
C = Commercial (0 to +70°C)  
I = Industrial (–40 to +85°C)  
M = Military (–55 to +125°C)  
B = MIL-STD-883  
Package Lead Count  
Lead-Free Packaging  
Blank = Standard Packaging  
G = RoHS Compliant Packaging  
Package Type  
PG = Ceramic Pin Grid Array  
PL = Plastic Leaded Chip Carrier  
PQ = Plastic Quad Flatpack  
RQ = Plastic Power Quad Flatpack  
VQ = Very Thin (1.0 mm) Quad Flatpack  
TQ = Thin (1.4 mm) Quad Flatpack  
CQ = Ceramic Quad Flatpack  
BG = Plastic Ball Grid Array  
Speed Grade  
Std = Standard Speed  
–1 = Approximately 15% faster than Standard  
–2 = Approximately 25% faster than Standard  
–3 = Approximately 35% faster than Standard  
Die Revision  
A = 1.0 mm CMOS Process  
Part Number  
A1415A = 1,500 Gates  
A14V15A = 1,500 Gates (3.3 V)  
A1425A = 2,500 Gates  
A14V25A = 2,500 Gates (3.3 V)  
A1440A = 4,000 Gates  
A14V40A = 4,000 Gates (3.3 V)  
A1460A = 6,000 Gates  
A14V60A = 6,000 Gates (3.3 V)  
A14100A = 10,000 Gates  
A14V100A = 10,000 Gates (3.3 V)  
Notes:  
1. The –2 and –3 speed grades have been discontinued.  
2. The Ceramic Pin Grid Array packages PG100, PG133, and PG175 have been discontinued in all device densities, speed  
grades, and temperature grades.  
3. The Plastic Ball Grid Array package BG225 has been discontinued in all device densities (specifically for A1460A), all speed  
grades, and all temperature grades.  
4. Military Grade devices are no longer available for the A1440A device.  
5. For more information about discontinued devices, refer to the Product Discontinuation Notices (PDNs) listed below, available on  
the Microsemi SoC Products Group website:  
PDN March 2001  
PDN 0104  
PDN 0203  
PDN 0604  
PDN 1004  
II  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
Product Plan  
Speed Grade1  
Application1  
Device/Package  
Std.  
–1  
–2  
–3  
C
I
M
B
A1415A Device  
84-Pin Plastic Leaded Chip Carrier (PLCC)  
D
D
D
D
D
D
D
D
✓
✓
✓
–
–
–
–
–
✓
✓
✓
D
✓
✓
✓
D
✓
✓
✓
D
✓
✓
✓
–
100-Pin Plastic Quad Flatpack (PQFP)  
100-Pin Very Thin Quad Flatpack (VQFP)  
100-Pin Ceramic Pin Grid Array (CPGA)  
A14V15A Device  
84-Pin Plastic Leaded Chip Carrier (PLCC)  
–
–
–
–
–
–
–
–
–
–
–
–
✓
✓
✓
✓
100-Pin Very Thin Quad Flatpack (VQFP)  
A1425A Device  
84-Pin Plastic Leaded Chip Carrier (PLCC)  
D
D
D
–
D
D
D
–
✓
✓
✓
✓
D
✓
✓
✓
✓
D
✓
✓
✓
✓
D
✓
✓
✓
–
100-Pin Plastic Quad Flatpack (PQFP)  
100-Pin Very Thin Quad Flatpack (VQFP)  
132-Pin Ceramic Quad Flatpack (CQFP)  
–
–
–
–
✓
D
–
✓
D
–
133-Pin Ceramic Pin Grid Array (CPGA)  
160-Pin Plastic Quad Flatpack (PQFP)  
D
D
D
D
–
✓
✓
✓
✓
A14V25A Device  
84-Pin Plastic Leaded Chip Carrier (PLCC)  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
✓
✓
✓
✓
✓
✓
100-Pin Very Thin Quad Flatpack (VQFP)  
160-Pin Plastic Quad Flatpack (PQFP)  
A1440A Device  
84-Pin Plastic Leaded Chip Carrier (PLCC)  
D
D
D
D
D
D
–
–
–
–
–
–
✓
✓
✓
D
✓
✓
✓
D
✓
✓
✓
✓
100-Pin Very Thin Quad Flatpack (VQFP)  
160-Pin Plastic Quad Flatpack (PQFP)  
✓
D
✓
–
175-Pin Ceramic Pin Grid Array (CPGA)  
176-Pin Thin Quad Flatpack (TQFP)  
D
D
D
D
–
–
–
–
✓
✓
✓
✓
Notes:  
Availability:  
✓ = Available  
P = Planned  
– = Not planned  
D = Discontinued  
Speed Grade:  
1. Applications:  
C = Commercial  
I = Industrial  
M = Military  
2. Commercial only  
–1 = Approx. 15% faster than Std.  
–2 = Approx. 25% faster than Std.  
–3 = Approx. 35% faster than Std.  
(–2 and –3 speed grades have  
been discontinued.)  
Revision 3  
III  
Accelerator Series FPGAs – ACT 3 Family  
Speed Grade1  
Application1  
Device/Package  
Std.  
–1  
–2  
–3  
C
I
M
B
A14V40A Device  
84-Pin Plastic Leaded Chip Carrier (PLCC)  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
✓
✓
✓
✓
✓
✓
✓
✓
100-Pin Very Thin Quad Flatpack (VQFP)  
160-Pin Plastic Quad Flatpack (PQFP)  
176-Pin Thin Quad Flatpack (TQFP)  
A1460A Device  
160-Pin Plastic Quad Flatpack (PQFP)  
176-Pin Thin Quad Flatpack (TQFP)  
196-Pin Ceramic Quad Flatpack (CQFP)  
207-Pin Ceramic Pin Grid Array (CPGA)  
208-Pin Plastic Quad Flatpack (PQFP)  
225-Pin Plastic Ball Grid Array (BGA)  
A14V60A Device  
✓
✓
✓
✓
✓
D
✓
✓
✓
✓
✓
D
D
D
–
D
D
–
✓
✓
✓
✓
✓
D
✓
✓
–
–
–
–
–
✓
✓
–
✓
✓
–
D
D
D
D
D
D
–
✓
–
–
–
160-Pin Plastic Quad Flatpack (PQFP)  
176-Pin Thin Quad Flatpack (TQFP)  
208-Pin Plastic Quad Flatpack (PQFP)  
A14100A Device  
✓
✓
✓
–
–
–
–
–
–
–
–
–
✓
✓
✓
–
–
–
–
–
–
–
–
–
208-Pin Power Quad Flatpack (RQFP)  
257-Pin Ceramic Pin Grid Array (CPGA)  
313-Pin Plastic Ball Grid Array (BGA)  
256-Pin Ceramic Quad Flatpack (CQFP)  
A14V100A Device  
✓
✓
✓
✓
✓
✓
✓
✓
D
D
D
–
D
D
D
–
✓
✓
✓
✓
✓
–
–
✓
–
–
✓
–
–
–
✓
✓
208-Pin Power Quad Flatpack (RQFP)  
313-Pin Plastic Ball Grid Array (BGA)  
✓
✓
–
–
–
–
–
–
✓
✓
–
–
–
–
–
–
Notes:  
Availability:  
✓ = Available  
P = Planned  
– = Not planned  
D = Discontinued  
Speed Grade:  
1. Applications:  
C = Commercial  
I = Industrial  
M = Military  
2. Commercial only  
–1 = Approx. 15% faster than Std.  
–2 = Approx. 25% faster than Std.  
–3 = Approx. 35% faster than Std.  
(–2 and –3 speed grades have  
been discontinued.)  
IV  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
Plastic Device Resources  
User I/Os  
PQ160 PQ/RQ208 VQ100  
Device  
Series  
Logic  
Modules  
Gates  
1500  
2500  
4000  
6000  
10000  
PL84  
70  
70  
70  
–
PQ100  
TQ176  
BG225*  
BG313  
A1415  
A1425  
A1440  
A1460  
A14100  
200  
310  
80  
80  
–
–
–
–
80  
83  
83  
–
–
–
–
–
–
–
100  
131  
131  
–
564  
–
140  
151  
–
–
–
848  
–
167  
175  
168  
–
–
1377  
–
–
–
228  
Note: *Discontinued  
Hermetic Device Resources  
User I/Os  
Device  
Series  
Logic  
Modules  
Gates  
1500  
2500  
4000  
6000  
10000  
PG100*  
PG133*  
PG175*  
PG207  
PG257  
CQ132  
CQ196  
CQ256  
A1415  
A1425  
A1440  
A1460  
A14100  
200  
310  
80  
–
–
100  
–
–
–
–
–
–
–
–
100  
–
–
–
–
–
564  
–
140  
–
–
–
–
–
848  
–
–
168  
–
–
–
168  
–
–
1377  
–
–
–
228  
–
228  
Note: *Discontinued  
Contact your local Microsemi SoC Products Group (formerly Actel) representative for device availability:  
http://www.microsemi.com/soc/contact/default.aspx.  
Revision 3  
V
Table of Contents  
ACT 3 Family Overview  
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1  
Detailed Specifications  
Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1  
Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2  
I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3  
Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4  
Routing Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5  
5 V Operating Conditions  
3.3 V Operating Conditions  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10  
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11  
ACT 3 Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16  
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42  
Package Pin Assignments  
PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1  
PQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3  
PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5  
PQ208, RQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8  
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12  
CQ132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14  
CQ196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16  
CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18  
BG225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20  
BG313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22  
PG100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24  
PG133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26  
PG175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28  
PG207 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30  
PG257 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32  
Datasheet Information  
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1  
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3  
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3  
VI  
Revision 3  
1 – ACT 3 Family Overview  
General Description  
Microsemi’s ACT 3 Accelerator Series of FPGAs offers the industry’s fastest high-capacity  
programmable logic device. ACT 3 FPGAs offer a high performance, PCI compliant programmable  
solution capable of 186 MHz on-chip performance and 9.0 nanosecond clock-to-output (–1 speed grade),  
with capacities spanning from 1,500 to 10,000 gate array equivalent gates.  
The ACT 3 family builds on the proven two-module architecture consisting of combinatorial and  
sequential logic modules used in Microsemi’s 3200DX and 1200XL families. In addition, the ACT 3 I/O  
modules contain registers which deliver 9.0 nanosecond clock-to-out times (–1 speed grade). The  
devices contain four clock distribution networks, including dedicated array and I/O clocks, supporting  
very fast synchronous and asynchronous designs. In addition, routed clocks can be used to drive high  
fanout signals such as flip-flop resets and output.  
The ACT 3 family is supported by Microsemi’s Designer Series Development System which offers  
automatic placement and routing (with automatic or fixed pin assignments), static timing analysis, user  
programming, and debug and diagnostic probe capabilities.  
Accumulators (16-Bit)  
47 MHz  
Loadable Counters (16-Bit)  
82 MHz  
Prescaled Loadable Counters (16-Bit)  
Shift Registers  
186 MHz  
186 MHz  
Figure 1-1 • Predictable Performance (worst-case commercial, –1 speed grade)  
System Performance Model  
Chip #1 I/O Module  
Chip #2 I/O Module  
35 pF  
I/O CLK  
I/O CLK  
tCKHS  
tTRACE  
tINSU  
Revision 3  
1-1  
ACT 3 Family Overview  
Table 1-1 • Chip-to-Chip Performance (worst-case commercial)  
Device and Speed  
Grade  
t
CKHS (ns)  
7.5  
tTRACE (ns)  
tINSU (ns)  
1.8  
Total (ns)  
10.3  
MHz  
97  
88  
95  
87  
81  
78  
73  
69  
A1425A -3  
A1460A -3  
A1425A -2  
A1460A -2  
A1425A -1  
A1460A -1  
A1425A STD  
A1460A STD  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
1.0  
9.0  
1.3  
11.3  
7.5  
2.0  
10.5  
9.0  
1.5  
11.5  
9.0  
2.3  
12.3  
10.0  
10.0  
11.5  
1.8  
12.8  
2.7  
13.7  
2.0  
14.5  
Note: The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN  
0604, and PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
1-2  
Revision 3  
2 – Detailed Specifications  
This section of the datasheet is meant to familiarize the user with the architecture of the ACT 3 family of  
FPGA devices. A generic description of the family will be presented first, followed by a detailed  
description of the logic blocks, the routing structure, the antifuses, and the special function circuits. The  
on-chip circuitry required to program the devices is not covered.  
Topology  
The ACT 3 family architecture is composed of six key elements: Logic modules, I/O modules, I/O Pad  
Drivers, Routing Tracks, Clock Networks, and Programming and Test Circuits. The basic structure is  
similar for all devices in the family, differing only in the number of rows, columns, and I/Os. The array  
itself consists of alternating rows of modules and channels. The logic modules and channels are in the  
center of the array; the I/O modules are located along the array periphery. A simplified floor plan is  
depicted in Figure 2-1.  
An Array with n rows and m columns  
0
1
2
3
4
5
c–1  
c
c+1  
m m+1 m+2 m+3  
Columns  
Rows  
n+1  
Channels  
n+2  
IO IO IO IO IO IO  
Top I/Os  
IO IO IO CLKM  
n+1  
n
IO IO BIN S  
IO IO BIN S  
IO IO BIN S  
S
S
S
S
C
C
C
C
C
C
C
C
S
S
S
S
S
S
S
S
C
C
C
C
C
C
C
C
S
S
S
S
C
C
C
C
S
S
S
S
IO IO  
n
IO IO  
IO IO  
n–1  
•
•
•
n–1  
•
•
•
2
2
IO IO  
IO IO BIN S  
Left I/Os  
1
0
1
0
Right I/Os  
Bottom I/Os  
BIO IO IO IO IO IO  
IO IO IO IO IO IO  
Figure 2-1 • Generalized Floor Plan of ACT 3 Device  
Revision 3  
2-1  
Detailed Specifications  
Logic Modules  
ACT 3 logic modules are enhanced versions of the 1200XL family logic modules. As in the 1200XL  
family, there are two types of modules: C-modules and S-modules (Figure 2-2 and Figure 2-3). The C-  
module is functionally equivalent to the 1200XL C-module and implements high fanin combinatorial  
macros, such as 5-input AND, 5-input OR, and so on. It is available for use as the CM8 hard macro. The  
S-module is designed to implement high-speed sequential functions within a single module.  
D00  
D01  
OUT  
Y
D10  
D11  
S1  
S0  
A1 B1  
A0 B0  
Figure 2-2 • C-Module Diagram  
D00  
D01  
Y
D
Q
OUT  
D10  
D11  
S1  
S0  
CLK  
CLR  
A1 B1  
A0 B0  
Figure 2-3 • S-Module Diagram  
S-modules consist of a full C-module driving a flip-flop, which allows an additional level of logic to be  
implemented without additional propagation delay. It is available for use as the DFM8A/B and DLM8A/B  
hard macros. C-modules and S-modules are arranged in pairs called module-pairs. Module-pairs are  
arranged in alternating patterns and make up the bulk of the array. This arrangement allows the  
placement software to support two-module macros of four types (CC, CS, SC, and SS). The C-module  
implements the following function:  
Y = !S1 * !S0 * D00 + !S1 * S0 * D01 + S1 * !S0 * D10 + S1 * S0 * D11  
EQ 1  
where: S0 = A0 * B0 and S1 = A1 + B1  
2-2  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
The S-module contains a full implementation of the C-module plus a clearable sequential element that  
can either implement a latch or flip-flop function. The S-module can therefore implement any function  
implemented by the C-module. This allows complex combinatorial-sequential functions to be  
implemented with no delay penalty. The Designer Series Development System will automatically  
combine any C-module macro driving an S-module macro into the S-module, thereby freeing up a logic  
module and eliminating a module delay.  
The clear input CLR is accessible from the routing channel. In addition, the clock input may be connected  
to one of three clock networks: CLKA, CLKB, or HCLK. The C-module and S-module functional  
descriptions are shown in Figure 2-2 and Figure 2-3 on page 2-2. The clock selection is determined by a  
multiplexer select at the clock input to the S-module.  
I/Os  
I/O Modules  
I/O modules provide an interface between the array and the I/O Pad Drivers. I/O modules are located in  
the array and access the routing channels in a similar fashion to logic modules. The I/O module  
schematic is shown in Figure 4. The signals DataIn and DataOut connect to the I/O pad driver.  
0
MUX  
1
DATAOUT  
D
0
MUX  
Q
D
1
CLR/PRE  
ODE  
0
1
2
3
S0  
S1  
Y
MUX  
1
MUX  
D
Q
0
DATAIN  
CLR/PRE  
IOPCL  
IOCLK  
Figure 2-4 • Functional Diagram for I/O Module  
Each I/O module contains two D-type flip-flops. Each flip-flop is connected to the dedicated I/O clock  
(IOCLK). Each flip-flop can be bypassed by nonsequential I/Os. In addition, each flip-flop contains a data  
enable input that can be accessed from the routing channels (ODE and IDE). The asynchronous  
preset/clear input is driven by the dedicated preset/clear network (IOPCL). Either preset or clear can be  
selected individually on an I/O module by I/O module basis.  
Revision 3  
2-3  
Detailed Specifications  
The I/O module output Y is used to bring Pad signals into the array or to feed the output register back into  
the array. This allows the output register to be used in high-speed state machine applications. Side I/O  
modules have a dedicated output segment for Y extending into the routing channels above and below  
(similar to logic modules). Top/Bottom I/O modules have no dedicated output segment. Signals coming  
into the chip from the top or bottom are routed using F-fuses and LVTs (F-fuses and LVTs are explained  
in detail in the routing section).  
I/O Pad Drivers  
All pad drivers are capable of being tristate. Each buffer connects to an associated I/O module with four  
signals: OE (Output Enable), IE (Input Enable), DataOut, and DataIn. Certain special signals used only  
during programming and test also connect to the pad drivers: OUTEN (global output enable), INEN  
(global input enable), and SLEW (individual slew selection). See Figure 2-5.  
OE  
SLEW  
DATAOUT  
PAD  
DATAIN  
IEN  
INEN  
OUTEN  
Figure 2-5 • Function Diagram for I/O Pad Driver  
Special I/Os  
The special I/Os are of two types: temporary and permanent. Temporary special I/Os are used during  
programming and testing. They function as normal I/Os when the MODE pin is inactive. Permanent  
special I/Os are user programmed as either normal I/Os or special I/Os. Their function does not change  
once the device has been programmed. The permanent special I/Os consist of the array clock input  
buffers (CLKA and CLKB), the hard-wired array clock input buffer (HCLK), the hard-wired I/O clock input  
buffer (IOCLK), and the hard-wired I/O register preset/clear input buffer (IOPCL). Their function is  
determined by the I/O macros selected.  
Clock Networks  
The ACT 3 architecture contains four clock networks: two high-performance dedicated clock networks  
and two general purpose routed networks. The high-performance networks function up to 200 MHz,  
while the general purpose routed networks function up to 150 MHz.  
2-4  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
Dedicated Clocks  
Dedicated clock networks support high performance by providing sub-nanosecond skew and guaranteed  
performance. Dedicated clock networks contain no programming elements in the path from the I/O Pad  
Driver to the input of S-modules or I/O modules. There are two dedicated clock networks: one for the  
array registers (HCLK), and one for the I/O registers (IOCLK). The clock networks are accessed by  
special I/Os.  
CLKB  
CLKA  
CLKINB  
CLKINA  
FROM  
PADS  
S0  
S1  
INTERNAL  
SIGNAL  
CLKMOD  
CLKO(17)  
CLKO(16)  
CLKO(15)  
CLOCK  
DRIVERS  
CLKO(2)  
CLKO(1)  
CLOCK TRACKS  
Figure 2-6 • Clock Networks  
The routed clock networks are referred to as CLK0 and CLK1. Each network is connected to a clock  
module (CLKMOD) that selects the source of the clock signal and may be driven as follows (Figure 2-6):  
•
•
•
•
Externally from the CLKA pad  
Externally from the CLKB pad  
Internally from the CLKINA input  
Internally from the CLKINB input  
The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal  
clock track are located in each horizontal routing channel. The function of the clock module is determined  
by the selection of clock macros from the macro library. The macro CLKBUF is used to connect one of  
the two external clock pins to a clock network, and the macro CLKINT is used to connect an internally  
generated clock signal to a clock network. Since both clock networks are identical, the user does not care  
whether CLK0 or CLK1 is being used. Routed clocks can also be used to drive high fanout nets like  
resets, output enables, or data enables. This saves logic modules and results in performance increases  
in some cases.  
Routing Structure  
The ACT 3 architecture uses vertical and horizontal routing tracks to connect the various logic and I/O  
modules. These routing tracks are metal interconnects that may either be of continuous length or broken  
into segments. Segments can be joined together at the ends using antifuses to increase their lengths up  
to the full length of the track.  
Revision 3  
2-5  
Detailed Specifications  
Horizontal Routing  
Horizontal channels are located between the rows of modules and are composed of several routing  
tracks. The horizontal routing tracks within the channel are divided into one or more segments. The  
minimum horizontal segment length is the width of a module-pair, and the maximum horizontal segment  
length is the full length of the channel. Any segment that spans more than one-third the row length is  
considered a long horizontal segment. A typical channel is shown in Figure 2-7. Undedicated horizontal  
routing tracks are used to route signal nets. Dedicated routing tracks are used for the global clock  
networks and for power and ground tie-off tracks.  
Module Row  
HCLK  
CLK0  
NVCC  
SIGNAL  
Track  
Segment  
SIGNAL  
(LHT)  
|
|
|
|
|
|
|
HF  
SIGNAL  
NVSS  
CLK1  
Module Row  
Figure 2-7 • Horizontal Routing Tracks and Segments  
Vertical Routing  
Other tracks run vertically through the modules. Vertical tracks are of three types: input, output, and long.  
Vertical tracks are also divided into one or more segments. Each segment in an input track is dedicated  
to the input of a particular module. Each segment in an output track is dedicated to the output of a  
particular module. Long segments are uncommitted and can be assigned during routing. Each output  
segment spans four channels (two above and two below), except near the top and bottom of the array  
where edge effects occur. LVTs contain either one or two segments. An example of vertical routing tracks  
and segments is shown in Figure 2-8.  
LVTs  
C-Module  
Module Row  
Channel  
S-Module  
VF  
XF  
Vertical Input  
Segment  
FF  
C-Module  
S-Module  
Figure 2-8 • Vertical Routing Tracks and Segments  
2-6  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
Antifuse Connections  
An antifuse is a “normally open” structure as opposed to the normally closed fuse structure used in  
PROMs or PALs. The use of antifuses to implement a programmable logic device results in highly  
testable structures as well as an efficient programming architecture. The structure is highly testable  
because there are no preexisting connections; temporary connections can be made using pass  
transistors. These temporary connections can isolate individual antifuses to be programmed as well as  
isolate individual circuit structures to be tested. This can be done both before and after programming. For  
example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the  
functionality of all logic modules can be verified.  
Four types of antifuse connections are used in the routing structure of the ACT 3 array. (The physical  
structure of the antifuse is identical in each case; only the usage differs.)  
Table 2-1 shows four types of antifuses.  
Table 2-1 • Antifuse Types  
Type  
XF  
Description  
Horizontal-to-vertical connection  
HF  
Horizontal-to-horizontal connection  
Vertical-to-vertical connection  
"Fast" vertical connection  
VF  
FF  
Examples of all four types of connections are shown in Figure 2-7 on page 2-6 and Figure 2-8 on  
page 2-6.  
Module Interface  
Connections to Logic and I/O modules are made through vertical segments that connect to the module  
inputs and outputs. These vertical segments lie on vertical tracks that span the entire height of the array.  
Module Input Connections  
The tracks dedicated to module inputs are segmented by pass transistors in each module row. During  
normal user operation, the pass transistors are inactive, which isolates the inputs of a module from the  
inputs of the module directly above or below it. During certain test modes, the pass transistors are active  
to verify the continuity of the metal tracks. Vertical input segments span only the channel above or the  
channel below. The logic modules are arranged such that half of the inputs are connected to the channel  
above and half of the inputs to segments in the channel below, as shown in Figure 2-9.  
Y+2  
Y+1  
Y+2  
Y+1  
B1 B0  
A1 D10 D11  
D01 D00  
B0  
B1 D01  
Y
Y
A0  
D10  
A0 D11 A1  
Y-1  
Y-1  
Y-2  
Y-2  
LVTs  
C-Modules  
S-Modules  
Figure 2-9 • Logic Module Routing Interface  
Revision 3  
2-7  
Detailed Specifications  
Module Output Connections  
Module outputs have dedicated output segments. Output segments extend vertically two channels above  
and two channels below, except at the top or bottom of the array. Output segments twist, as shown in  
Figure 10, so that only four vertical tracks are required.  
LVT Connections  
Outputs may also connect to nondedicated segments called Long Vertical Tracks (LVTs). Each module  
pair in the array shares four LVTs that span the length of the column. Any module in the column pair can  
connect to one of the LVTs in the column using an FF connection. The FF connection uses antifuses  
connected directly to the driver stage of the module output, bypassing the isolation transistor. FF  
antifuses are programmed at a higher current level than HF, VF, or XF antifuses to produce a lower  
resistance value.  
Antifuse Connections  
In general every intersection of a vertical segment and a horizontal segment contains an unprogrammed  
antifuse (XF-type). One exception is in the case of the clock networks.  
Clock Connections  
To minimize loading on the clock networks, a subset of inputs has antifuses on the clock tracks. Only a  
few of the C-module and S-module inputs can be connected to the clock networks. To further reduce  
loading on the clock network, only a subset of the horizontal routing tracks can connect to the clock  
inputs of the S-module.  
Programming and Test Circuits  
The array of logic and I/O modules is surrounded by test and programming circuits controlled by the  
temporary special I/O pins MODE, SDI, and DCLK. The function of these pins is similar to all ACT family  
devices. The ACT 3 family also includes support for two Actionprobe® circuits, allowing complete  
observability of any logic or I/O module in the array using the temporary special I/O pins, PRA and PRB.  
2-8  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
5 V Operating Conditions  
Table 2-2 • Absolute Maximum Ratings1, Free Air Temperature Range  
Symbol  
VCC  
VI  
Parameter  
DC supply voltage  
Limits  
–0.5 to +7.0  
–0.5 to VCC + 0.5  
–0.5 to VCC + 0.5  
±20  
Units  
V
Input voltage  
V
VO  
Output voltage  
V
IIO  
I/O source sink current2  
mA  
°C  
TSTG  
Notes:  
Storage temperature  
–65 to +150  
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.  
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be  
operated outside the recommended operating conditions.  
2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater  
than VCC + 0.5 V for less than GND –0.5 V, the internal protection diodes will forward bias and can draw excessive  
current.  
Table 2-3 • Recommended Operating Conditions  
Parameter  
Commercial  
0 to +70  
±5  
Industrial  
–40 to +85  
±10  
Military  
–55 to +125  
±10  
Units  
°C  
Temperature range*  
5 V power supply tolerance  
%VCC  
Note: *Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military.  
Table 2-4 • Electrical Specifications  
Commercial  
Industrial  
Military  
Min. Max.  
3.7  
Symbol  
VOH1,2 High level output  
Parameter  
Test Condition  
IOH = –4 mA (CMOS)  
IOH = –6 mA (CMOS)  
IOH = –10 mA (TTL)3  
IOL = +6 mA (CMOS)  
IOL = +12 mA (TTL)3  
TTL inputs  
Min.  
Max.  
Min.  
3.7  
Max.  
Units  
–
–
–
–
V
V
V
V
3.84  
2.40  
VOL1,2 Low level output  
0.33  
0.50  
0.4  
0.4  
VIH  
VIL  
IIN  
High level input  
Low level input  
Input leakage  
2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3  
V
V
TTL inputs  
–0.3  
–10  
–10  
0.8  
+10  
+10  
10  
–0.3  
–10  
–10  
0.8  
+10  
+10  
10  
–0.3  
–10  
–10  
0.8  
+10  
+10  
10  
VI = VCC or GND  
µA  
µA  
pF  
mA  
IOZ  
CIO  
3-state output leakage VO = VCC or GND  
I/O capacitance3,4  
ICC(S) Standby VCC supply current (typical = 0.7 mA)  
2
10  
20  
ICC(D) Dynamic VCC supply current. See the Power Dissipation section.  
Notes:  
1. Microsemi devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is  
required.  
2. Tested one output at a time, VCC = minimum.  
3. Not tested; for information only.  
4. VOUT = 0 V, f = 1 MHz  
5. Typical standby current = 0.7 mA. All outputs unloaded. All inputs = VCC or GND.  
Revision 3  
2-9  
Detailed Specifications  
3.3 V Operating Conditions  
Table 2-5 • Absolute Maximum Ratings1, Free Air Temperature Range  
Symbol  
VCC  
VI  
Parameter  
DC supply voltage  
Limits  
–0.5 to +7.0  
–0.5 to VCC + 0.5  
–0.5 to VCC + 0.5  
±20  
Units  
V
Input voltage  
V
VO  
Output voltage  
V
IIO  
I/O source sink current2  
mA  
°C  
TSTG  
Notes:  
Storage temperature  
–65 to +150  
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.  
Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be  
operated outside the recommended operating conditions.  
2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater  
than VCC + 0.5 V for less than GND –0.5 V, the internal protection diodes will forward bias and can draw excessive  
current.  
Table 2-6 • Recommended Operating Conditions  
Parameter  
Commercial  
0 to +70  
Units  
°C  
Temperature range*  
Power supply tolerance  
3.0 to 3.6  
V
Note: *Ambient temperature (TA) is used for commercial.  
Table 2-7 • Electrical Specifications  
Commercial  
Parameter  
Min.  
Max.  
Units  
VOH1  
IOH = –4 mA  
IOH = –3.2 mA  
IOL = 6 mA  
2.15  
2.4  
–
V
V
VOL1  
0.4  
0.8  
V
VIL  
–0.3  
2.0  
V
VIH  
VCC + 0.3  
+10  
V
2
Input transition time tR, tF  
CIO I/O Capacitance2,3  
Standby current, ICC4 (typical = 0.3 mA)  
Leakage current5  
VI = VCC or GND  
–10  
µA  
pF  
mA  
µA  
10  
0.75  
10  
–10  
1. Only one output tested at a time. VCC = minimum.  
2. Not tested; for information only.  
3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f - 1 MHz.  
4. Typical standby current = 0.3 mA. All outputs unloaded. All inputs = VCC or GND.  
5. VO, VIN = VCC or GND  
2-10  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
Package Thermal Characteristics  
The device junction to case thermal characteristic is θjc, and the junction to ambient air characteristic is  
θja. The thermal characteristics for θja are shown with two different air flow rates.  
Maximum junction temperature is 150°C.  
A sample calculation of the absolute maximum power dissipation allowed for a CPGA 175-pin package at  
commercial temperature and still air is as follows:  
Max. junction temp. (°C) – Max. ambient temp. (°C)  
150°C – 70°C  
---------------------------------------------------------------------------------------------------------------------------------------  
-----------------------------------  
=
= 3.2 W  
θja°C/W  
25°C/W  
EQ 2  
Table 2-8 • Package Thermal Characteristics  
θja  
θja  
Package Type*  
Pin Count  
100  
133  
175  
207  
257  
132  
196  
256  
100  
160  
208  
100  
176  
208  
84  
θjc  
20  
20  
20  
20  
20  
13  
13  
13  
13  
10  
10  
12  
11  
0.4  
12  
10  
10  
Still Air  
300 ft./min.  
Units  
Ceramic Pin Grid Array  
35  
17  
15  
14  
13  
8
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
30  
25  
22  
15  
Ceramic Quad Flatpack  
Plastic Quad Flatpack  
55  
30  
24  
18  
40  
26  
26  
35  
25  
13  
28  
19  
17  
36  
30  
51  
33  
33  
Very Thin Quad Flatpack  
Thin Quad Flatpack  
43  
32  
Power Quad Flatpack  
Plastic Leaded Chip Carrier  
Plastic Ball Grid Array  
17  
37  
225  
313  
25  
23  
Note: Maximum power dissipation in still air:  
PQ160 = 2.4 W  
PQ208 = 2.4 W  
PQ100 = 1.6 W  
VQ100 = 1.9 W  
TQ176 = 2.5 W  
PL84 = 2.2 W  
RQ208 = 4.7 W  
BG225 = 3.2 W  
BG313 = 3.5 W  
Revision 3  
2-11  
Detailed Specifications  
Power Dissipation  
P = [ICC standby + Iactive] * VCC * IOL * VOL * N + IOH* (VCC – VOH) * M  
EQ 3  
where:  
ICC standby is the current flowing when no inputs or outputs are changing  
Iactive is the current flowing due to CMOS switching.  
IOL and IOH are TTL sink/source current.  
VOL and VOH are TTL level output voltages.  
N is the number of outputs driving TTL loads to VOL.  
M equals the number of outputs driving TTL loads to VOH.  
An accurate determination of N and M is problematical because their values depend on the design and  
on the system I/O. The power can be divided into two components: static and active.  
Static Power Component  
Microsemi FPGAs have small static power components that result in lower power dissipation than PALs  
or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level  
power dissipation can be achieved.  
The power due to standby current is typically a small component of the overall power. Standby power is  
calculated in Table 2-9 for commercial, worst case conditions.  
Table 2-9 • Standby Power Calculation  
ICC  
VCC  
Power  
2 mA  
5.25 V  
10.5 mW  
The static power dissipated by TTL loads depends on the number of outputs driving high or low and the  
DC load current. Again, this value is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33 V will  
generate 42 mW with all outputs driving low, and 140 mW with all outputs driving high. The actual  
dissipation will average somewhere between as I/Os switch states with time.  
Active Power Component  
Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This  
component is frequency dependent, a function of the logic and the external I/O. Active power dissipation  
results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module  
inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs.  
An additional component of the active power dissipation is the totem-pole current in CMOS transistor  
pairs. The net effect can be associated with an equivalent capacitance that can be combined with  
frequency and voltage to represent active power dissipation.  
Equivalent Capacitance  
The power dissipated by a CMOS circuit can be expressed by EQ 4.  
Power (µW) = CEQ * VCC2 * F  
EQ 4  
Where:  
CEQ is the equivalent capacitance expressed in pF.  
VCC is the power supply in volts.  
F is the switching frequency in MHz.  
2-12  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
Equivalent capacitance is calculated by measuring ICC active at a specified frequency and voltage for  
each circuit component of interest. Measurements have been made over a range of frequencies at a  
fixed value of VCC. Equivalent capacitance is frequency independent so that the results may be used  
over a wide range of operating conditions. Equivalent capacitance values are shown in Figure 2-10.  
Table 2-10 • CEQ Values for Microsemi FPGAs  
Item  
CEQ Value  
6.7  
Modules (CEQM  
)
Input Buffers (CEQI  
Output Buffers (CEQO  
Routed Array Clock Buffer Loads (CEQCR  
)
7.2  
)
10.4  
1.6  
)
Dedicated Clock Buffer Loads (CEQCD  
)
0.7  
I/O Clock Buffer Loads (CEQCI)  
0.9  
To calculate the active power dissipated from the complete design, the switching frequency of each part  
of the logic must be known. EQ 5 shows a piece-wise linear summation over all components.  
Power =VCC2 * [(m * CEQM * fm)modules + (n * CEQI * fn) inputs  
+ (p * (CEQO+ CL) * fp)outputs  
+ 0.5 * (q1 * CEQCR * fq1 routed_Clk1  
+ 0.5 * (q2 * CEQCR * fq2)routed_Clk2  
+ (r2 * fq2 routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk  
+ (s2 * CEQCI * fs2)IO_Clk  
)
+ (r1 * fq1)routed_Clk1  
)
]
EQ 5  
Where:  
m = Number of logic modules switching at fm  
n = Number of input buffers switching at fn  
p = Number of output buffers switching at fp  
q1 = Number of clock loads on the first routed array clock  
q2 = Number of clock loads on the second routed array clock  
r1 = Fixed capacitance due to first routed array clock  
r2 = Fixed capacitance due to second routed array clock  
s1 = Fixed number of clock loads on the dedicated array clock  
s2 = Fixed number of clock loads on the dedicated I/O clock  
C
EQM = Equivalent capacitance of logic modules in pF  
EQI = Equivalent capacitance of input buffers in pF  
C
CEQO = Equivalent capacitance of output buffers in pF  
C
EQCR = Equivalent capacitance of routed array clock in pF  
EQCD = Equivalent capacitance of dedicated array clock in pF  
C
CEQCI = Equivalent capacitance of dedicated I/O clock in pF  
CL = Output lead capacitance in pF  
f
m = Average logic module switching rate in MHz  
fn = Average input buffer switching rate in MHz  
fp = Average output buffer switching rate in MHz  
fq1 = Average first routed array clock rate in MHz  
f
f
q2 = Average second routed array clock rate in MHz  
s1 = Average dedicated array clock rate in MHz  
fs2 = Average dedicated I/O clock rate in MHz  
Revision 3  
2-13  
Detailed Specifications  
Table 2-11 • Fixed Capacitance Values for Microsemi FPGAs  
Device Type  
r1, routed_Clk1  
r2, routed_Clk2  
A1415A  
60  
57  
60  
57  
A14V15A  
A1425A  
75  
75  
A14V25A  
A1440A  
72  
72  
105  
100  
105  
165  
157  
165  
195  
185  
195  
105  
100  
105  
165  
157  
165  
195  
185  
195  
A14V40A  
A1440B  
A1460A  
A14V60A  
A1460B  
A14100A  
A14V100A  
A14100B  
Table 2-12 • Fixed Clock Loads (s1/s2)  
s1, Clock Loads on Dedicated  
Array Clock  
s2, Clock Loads on Dedicated  
I/O Clock  
Device Type  
A1415A  
104  
104  
160  
160  
288  
288  
288  
432  
432  
432  
697  
697  
697  
80  
A14V15A  
A1425A  
80  
100  
100  
140  
140  
140  
168  
168  
168  
228  
228  
228  
A14V25A  
A1440A  
A14V40A  
A1440B  
A1460A  
A14V60A  
A1460B  
A14100A  
A14V100A  
A14100B  
2-14  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
Determining Average Switching Frequency  
To determine the switching frequency for a design, you must have a detailed understanding of the data  
input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that  
they can be generally used to predict the upper limits of power dissipation. These guidelines are as  
follows:  
Table 2-13 • Guidelines for Predicting Power Dissipation  
Data  
Value  
80% of modules  
Logic Modules (m)  
Inputs switching (n)  
# inputs/4  
Outputs switching (p)  
# output/4  
First routed array clock loads (q1)  
Second routed array clock loads (q2)  
Load capacitance (CL)  
40% of sequential modules  
40% of sequential modules  
35 pF  
F/10  
F/5  
F/10  
F/2  
F/2  
F
Average logic module switching rate (fm)  
Average input switching rate (fn)  
Average output switching rate (fp)  
Average first routed array clock rate (fq1)  
Average second routed array clock rate (fq2)  
Average dedicated array clock rate (fs1)  
Average dedicated I/O clock rate (fs2)  
F
Revision 3  
2-15  
Detailed Specifications  
ACT 3 Timing Model  
Input Delays  
Internal Delays  
Predicted  
Routing  
Delays  
Output Delays  
I/O Module  
Combinatorial  
Logic Module  
I/O Module  
t
= 3.6 ns  
INY  
t
= 1.6 ns  
IRD2  
t
= 6.4 ns  
DHS  
t
= 1.1 ns  
= 2.2 ns  
= 3.6 ns  
RD1  
D
Q
t
= 2.6 ns  
PD  
t
RD4  
RD8  
t
I/O Module  
t
= 6.4 ns  
DHS  
Sequential  
Logic Module  
t
= 0.0 ns  
= 2.3 ns  
= 6.0 ns  
INH  
t
t
INSU  
ICKY  
D
D
Q
Q
Comb.  
Logic  
Included  
t
= 1.1 ns  
t
= 5.1 ns  
RD1  
ENZHS  
in tSUD  
t
= 0.9 ns  
= 0.9 ns  
OUTH  
t
OUTSU  
t
= 2.6 ns  
t
= 0.7 ns  
= 0.0 ns  
CO  
SUD  
ARRAY  
CLOCK  
t
HD  
t
= 3.9 ns  
HCKH  
F
= 150 MHz  
HMAX  
t
= 9.0 ns  
(pad-pad)  
CKHS  
I/O CLOCK  
F
= 150 MHz  
IOMAX  
Note: Values shown for A1425A –1 speed grade device.  
Figure 2-10 • Timing Model  
2-16  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
E
D
TRIBUFF  
To AC test loads (shown below)  
PAD  
VCC  
50%  
VCC  
VCC  
In  
GND  
1.5 V  
50%  
En  
Out  
GND  
10%  
En  
GND  
90%  
50%  
50%  
VCC  
50%  
VOH  
50%  
VOH  
1.5 V  
VOL  
Out  
VOL  
Out  
GND  
1.5 V  
1.5 V  
t
t
t
t
t
t
ENHSZ  
DHS,  
DHS  
ENZHS,  
ENHSZ  
ENZHS,  
Figure 2-11 • Output Buffers  
Load 2  
(Used to measure rising/falling edges)  
Load 1  
(Used to measure propagation delay)  
VCC  
GND  
To the output under test  
35 pF  
R to VCCfor tPLZ / tPZL  
R to GND for tPHZ / tPZH  
R = 1 kΩ  
To the output under test  
35 pF  
Figure 2-12 • AC Test Loads  
Y
PAD  
INBUF  
3 V  
In  
0 V  
50%  
1.5 V  
VCC  
1.5 V  
Out  
GND  
50%  
t
t
INY  
INY  
Figure 2-13 • Input Buffer Delays  
Revision 3  
2-17  
Detailed Specifications  
S
A
B
Y
VCC  
GND  
S, A or B  
50% 50%  
VCC  
50%  
Out  
50%  
GND  
t
t
PD  
PD  
VCC  
50%  
Out  
GND  
50%  
t
t
PD  
PD  
Figure 2-14 • Module Delays  
Flip-Flops  
D
Q
CLK  
CLR  
(Positive edge triggered)  
t
HD  
D
t
t
t
A
WCLKA  
SUD  
CLK  
t
WCLKA  
t
CO  
Q
t
CLR  
CLR  
t
WASYN  
Figure 2-15 • Sequential Module Timing Characteristics  
2-18  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
D
E
Y
PRE  
CLR  
IOCLK  
(Positive edge triggered)  
t
INH  
D
t
t
IOP  
t
IOPWH  
INSU  
IOCLK  
t
t
t
IDESU  
IOPWL  
IDEH  
E
Y
t
ICKY  
t
ICLRY  
PRE, CLR  
t
IOASPW  
Figure 2-16 • I/O Module: Sequential Input Timing Characteristics  
Q
D
E
PRE  
CLR  
IOCLK  
Y
(Positive edge triggered)  
t
OUTH  
D
t
t
t
IOP  
IOPWH  
OUTSU  
IOCLK  
t
t
t
ODESU  
IOPWL  
ODEH  
E
Y
t
OCKY  
t
CKHS,  
tCKLS  
Q
t
OCLRY  
PRE, CLR  
t
IOASPW  
Figure 2-17 • I/O Module: Sequential Output Timing Characteristics  
Revision 3  
2-19  
Detailed Specifications  
Tightest Delay Distributions  
Propagation delay between logic modules depends on the resistive and capacitive loading of the routing  
tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as  
the length of routing tracks, the number of interconnect elements, or the number of inputs increases.  
From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout  
(number of loads) driven by a module. Higher fanout usually requires some paths to have longer lengths  
of routing track. The ACT 3 family delivers the tightest fanout delay distribution of any FPGA. This tight  
distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by  
decreasing the number of interconnect elements per path.  
Microsemi’s patented PLICE antifuse offers a very low resistive/capacitive interconnect. The ACT 3  
family’s antifuses, fabricated in 0.8 micron m lithography, offer nominal levels of 200Ω resistance and 6  
femtofarad (fF) capacitance per antifuse. The ACT 3 fanout distribution is also tighter than alternative  
devices due to the low number of antifuses required per interconnect path. The ACT 3 family’s  
proprietary architecture limits the number of antifuses per path to only four, with 90% of interconnects  
using only two antifuses.  
The ACT 3 family’s tight fanout delay distribution offers an FPGA design environment in which fanout can  
be traded for the increased performance of reduced logic level designs. This also simplifies performance  
estimates when designing with ACT 3 devices.  
Table 2-14 • Logic Module and Routing Delay by Fanout (ns); Worst-Case Commercial Conditions  
Speed Grade  
ACT 3 –3  
ACT 3 –2  
ACT 3 –1  
ACT 3 STD  
Notes:  
FO = 1  
2.9  
FO = 2  
3.2  
FO = 3  
3.4  
FO = 4  
3.7  
FO = 8  
4.8  
3.3  
3.7  
3.9  
4.2  
5.5  
3.7  
4.2  
4.4  
4.8  
6.2  
4.3  
4.8  
5.1  
5.5  
7.2  
1. Obtained by added t  
datasheet.  
to t  
from the Logic Module Timing Characteristics Tables found in this  
RD(x=FO)  
PD  
2. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and  
PDN 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
Timing Characteristics  
Timing characteristics for ACT 3 devices fall into three categories: family dependent, device dependent,  
and design dependent. The input and output buffer characteristics are common to all ACT 3 family  
members. Internal routing delays are device dependent. Design dependency means actual delays are  
not determined until after placement and routing of the user’s design is complete. Delay values may then  
be determined by using the ALS Timer utility or performing simulation with post-layout delays.  
Critical Nets and Typical Nets  
Propagation delays are expressed only for typical nets, which are used for initial design performance  
evaluation. Critical net delays can then be applied to the most time-critical paths. Critical nets are  
determined by net property assignment prior to placement and routing. Up to 6% of the nets in a design  
may be designated as critical, while 90% of the nets in a design are typical.  
Long Tracks  
Some nets in the design use long tracks. Long tracks are special routing resources that span multiple  
rows, columns, or modules. Long tracks employ three and sometimes four antifuse connections. This  
increases capacitance and resistance, result ng in longer net delays for macros connected to long tracks.  
Typically up to 6% of nets in a fully utilized device require long tracks. Long tracks contribute  
approximately 4 ns to 14 ns delay. This additional delay is represented statistically in higher fanout  
(FO = 8) routing delays in the datasheet specifications section.  
2-20  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
Timing Derating  
ACT 3 devices are manufactured in a CMOS process. Therefore, device performance varies according  
to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating  
voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect  
minimum operating voltage, maximum operating temperature, and worst-case processing.  
Table 2-15 • Timing Derating Factor (Temperature and Voltage)  
(Commercial Minimum/Maximum Specification) x  
Industrial  
Military  
Min. Max.  
0.63 1.17  
Min.  
0.66  
Max.  
1.07  
Table 2-16 • Timing Derating Factor for Designs at Typical Temperature (TJ = 25°C)  
and Voltage (5.0 V)  
(Commercial Maximum Specification) x  
0.85  
Table 2-17 • Temperature and Voltage Derating Factors  
(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)  
–55  
0.72  
0.70  
0.68  
0.66  
0.63  
–40  
0.76  
0.73  
0.71  
0.69  
0.66  
0
25  
70  
85  
125  
1.117  
1.12  
1.09  
1.06  
1.01  
4.50  
4.75  
5.00  
5.25  
5.50  
0.85  
0.82  
0.79  
0.77  
0.74  
0.90  
0.87  
0.84  
0.82  
0.79  
1.04  
1.00  
0.97  
0.94  
0.90  
1.07  
1.03  
1.00  
0.97  
0.93  
1.20  
1.10  
1.00  
0.90  
0.80  
0.70  
0.60  
4.50  
4.75  
5.00  
Voltage (V)  
5.25  
5.50  
Note: This derating factor applies to all routing and propagation delays.  
Figure 2-18 • Junction Temperature and Voltage Derating Curves  
(normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C)  
Revision 3  
2-21  
Detailed Specifications  
A1415A, A14V15A Timing Characteristics  
Table 2-18 • A1415A, A14V15A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C1  
Logic Module Propagation Delays2 –3 Speed3 –2 Speed3 Std. Speed 3.3 V Speed1  
–1 Speed  
Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
Units  
tPD  
Internal Array Module  
2.0  
2.0  
2.0  
2.3  
2.3  
2.3  
2.6  
2.6  
2.6  
3.0  
3.0  
3.0  
3.9  
3.9  
3.9  
ns  
ns  
ns  
tCO  
Sequential Clock to Q  
tCLR  
Asynchronous Clear to Q  
Predicted Routing Delays4  
tRD1  
tRD2  
tRD3  
tRD4  
tRD8  
FO = 1 Routing Delay  
FO = 2 Routing Delay  
FO = 3 Routing Delay  
FO = 4 Routing Delay  
FO = 8 Routing Delay  
0.9  
1.2  
1.4  
1.7  
2.8  
1.0  
1.4  
1.6  
1.9  
3.2  
1.1  
1.6  
1.8  
2.2  
3.6  
1.3  
1.8  
2.1  
2.5  
4.2  
1.7  
2.4  
2.8  
3.3  
5.5  
ns  
ns  
ns  
ns  
ns  
Logic Module Sequential Timing  
tSUD  
tHD  
tSUD  
tHD  
Flip-Flop Data Input Setup  
Flip-Flop Data Input Hold  
Latch Data Input Setup  
Latch Data Input Hold  
0.5  
0.0  
0.5  
0.0  
1.9  
1.9  
4.0  
0.6  
0.0  
0.6  
0.0  
2.4  
2.4  
5.0  
0.7  
0.0  
0.7  
0.0  
3.2  
3.2  
6.8  
0.8  
0.0  
0.8  
0.0  
3.8  
3.8  
8.0  
0.8  
0.0  
0.8  
0.0  
4.8  
4.8  
10.0  
ns  
ns  
ns  
ns  
tWASYN Asynchronous Pulse Width  
tWCLKA Flip-Flop Clock Pulse Width  
ns  
ns  
tA  
Flip-Flop Clock Input Period  
Flip-Flop Clock Frequency  
ns  
fMAX  
Notes:  
250  
200  
150  
125  
100  
MHz  
1. VCC = 3.0 V for 3.3 V specifications.  
2. For dual-module macros, use t + t  
+ t  
+ t + t  
+ t  
or t  
+ t  
+ t  
, whichever is appropriate.  
SUD  
PD  
RD1  
PDn  
CO  
RD1  
PDn  
PD1  
RD1  
3. The –2 and –3 speed grades have been discontinued. Please refer to the Product Discontinuation Notices (PDNs) listed  
below:  
PDN March 2001  
PDN 0104  
PDN 0203  
PDN 0604  
PDN 1004  
4. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for  
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case  
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to  
shipment.  
2-22  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
A1415A, A14V15A Timing Characteristics (continued)  
Table 2-19 • A1415A, A14V15A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C  
Units  
I/O Module Input Propagation Delays  
Parameter/Description  
–3 Speed1 –2Speed1 –1 Speed Std. Speed 3.3 V Speed2  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tINY  
Input Data Pad to Y  
2.8  
4.7  
4.7  
4.7  
4.7  
3.2  
5.3  
5.3  
5.3  
5.3  
3.6  
6.0  
6.0  
6.0  
6.0  
4.2  
7.0  
7.0  
7.0  
7.0  
5.5  
9.2  
9.2  
9.2  
9.2  
ns  
ns  
ns  
ns  
ns  
tICKY  
Input Reg IOCLK Pad to Y  
tOCKY Output Reg IOCLK Pad to Y  
tICLRY Input Asynchronous Clear to Y  
tOCLRY Output Asynchronous Clear to Y  
Predicted Input Routing Delays2  
tRD1  
tRD2  
tRD3  
tRD4  
tRD8  
FO = 1 Routing Delay  
FO = 2 Routing Delay  
FO = 3 Routing Delay  
FO = 4 Routing Delay  
FO = 8 Routing Delay  
0.9  
1.2  
1.4  
1.7  
2.8  
1.0  
1.4  
1.6  
1.9  
3.2  
1.1  
1.6  
1.8  
2.2  
3.6  
1.3  
1.8  
2.1  
2.5  
4.2  
1.7  
2.4  
2.8  
3.3  
5.5  
ns  
ns  
ns  
ns  
ns  
I/O Module Sequential Timing (wrt IOCLK pad)  
tINH  
Input F-F Data Hold  
Input F-F Data Setup  
Input Data Enable Hold  
0.0  
2.0  
0.0  
5.8  
0.7  
0.7  
0.3  
1.3  
0.0  
2.3  
0.0  
6.5  
0.8  
0.8  
0.4  
1.5  
0.0  
2.5  
0.0  
7.5  
0.9  
0.9  
0.4  
1.7  
0.0  
3.0  
0.0  
8.6  
1.0  
1.0  
0.5  
2.0  
0.0  
3.0  
0.0  
8.6  
1.0  
1.0  
0.5  
2.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tINSU  
tIDEH  
tIDESU Input Data Enable Setup  
tOUTH Output F-F Data hold  
tOUTSU Output F-F Data Setup  
tODEH Output Data Enable Hold  
fODESU Output Data Enable Setup  
Notes:  
1. The –2 and –3 speed grades have been discontinued. Please refer to the Product Discontinuation Notices (PDNs) listed  
below:  
PDN March 2001  
PDN 0104  
PDN 0203  
PDN 0604  
PDN 1004  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for  
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case  
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to  
shipment.  
Revision 3  
2-23  
Detailed Specifications  
A1415A, A14V15A Timing Characteristics (continued)  
Table 2-20 • A1415A, A14V15A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C  
I/O Module – TTL Output Timing1  
–3 Speed2 –2 Speed2 –1 Speed Std. Speed 3.3 V Speed1  
Units  
Parameter/Description  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tDHS  
tDLS  
Data to Pad, High Slew  
Data to Pad, Low Slew  
5.0  
8.0  
5.6  
9.0  
6.4  
10.2  
5.1  
7.5  
9.8  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
12.0  
6.0  
15.6  
7.8  
tENZHS Enable to Pad, Z to H/L, High Slew  
tENZLS Enable to Pad, Z to H/L, Low Slew  
tENHSZ Enable to Pad, H/L to Z, High Slew  
tENLSZ Enable to Pad, H/L to Z, Low Slew  
tCKHS IOCLK Pad to Pad H/L, High Slew  
tCKLS IOCLK Pad to Pad H/L, Low Slew  
dTLHHS Delta Low to High, High Slew  
dTLHLS Delta Low to High, Low Slew  
dTHLHS Delta High to Low, High Slew  
dTHLLS Delta High to Low, Low Slew  
I/O Module – CMOS Output Timing1  
4.0  
4.5  
7.4  
8.3  
9.4  
11.0  
10.0  
10.0  
10.0  
15.0  
0.03  
0.07  
0.05  
0.07  
14.3  
13.0  
13.0  
13.0  
19.5  
6.5  
7.5  
8.5  
6.5  
7.5  
8.5  
7.5  
7.5  
9.0  
11.3  
0.02  
0.05  
0.04  
0.05  
11.3  
0.02  
0.05  
0.04  
0.05  
13.5  
0.03  
0.06  
0.04  
0.06  
0.04 ns/pF  
0.09 ns/pF  
0.07 ns/pF  
0.09 ns/pF  
tDHS  
tDLS  
Data to Pad, High Slew  
Data to Pad, Low Slew  
6.2  
11.7  
5.2  
7.0  
13.1  
5.9  
7.9  
14.9  
6.6  
9.3  
12.1  
22.8  
10.1  
17.3  
13.0  
13.0  
15.3  
22.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
17.5  
7.8  
tENZHS Enable to Pad, Z to H/L, High Slew  
tENZLS Enable to Pad, Z to H/L, Low Slew  
tENHSZ Enable to Pad, H/L to Z, High Slew  
tENLSZ Enable to Pad, H/L to Z, Low Slew  
tCKHS IOCLK Pad to Pad H/L, High Slew  
tCKLS IOCLK Pad to Pad H/L, Low Slew  
dTLHHS Delta Low to High, High Slew  
dTLHLS Delta Low to High, Low Slew  
dTHLHS Delta High to Low, High Slew  
dTHLLS Delta High to Low, Low Slew  
8.9  
10.0  
7.5  
11.3  
8.5  
13.3  
10.0  
10.0  
11.8  
17.3  
0.06  
0.11  
0.04  
0.05  
6.7  
6.7  
7.5  
9.0  
8.9  
8.9  
10.7  
15.6  
0.05  
0.09  
0.03  
0.04  
13.0  
0.04  
0.07  
0.03  
0.04  
13.0  
0.04  
0.08  
0.03  
0.04  
0.08 ns/pF  
0.14 ns/pF  
0.05 ns/pF  
0.07 ns/pF  
Notes:  
1. Delays based on 35 pF loading.  
2. The –2 and –3 speed grades have been discontinued. Please refer to the Product Discontinuation Notices (PDNs) listed  
below:  
PDN March 2001  
PDN 0104  
PDN 0203  
PDN 0604  
PDN 1004  
2-24  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
A1415A, A14V15A Timing Characteristics (continued)  
Table 2-21 • A1415A, A14V15A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C  
Units  
Dedicated (hardwired) I/O Clock Network  
Parameter/Description  
–3 Speed –2 Speed –1 Speed Std. Speed 3.3 V Speed1  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tIOCKH  
Input Low to High (pad to I/O module  
input)  
2.0  
2.3  
2.6  
3.0  
3.5  
0.4  
ns  
tIOPWH  
tIPOWL  
Minimum Pulse Width High  
Minimum Pulse Width Low  
1.9  
1.9  
1.9  
2.4  
2.4  
2.4  
3.3  
3.3  
3.3  
3.8  
3.8  
3.8  
4.8  
4.8  
4.8  
ns  
ns  
ns  
ns  
ns  
tIOSAPW Minimum Asynchronous Pulse Width  
tIOCKSW Maximum Skew  
0.4  
0.4  
0.4  
0.4  
tIOP  
Minimum Period  
4.0  
5.0  
6.8  
8.0  
10.0  
fIOMAX  
Maximum Frequency  
250  
200  
150  
125  
100 MHz  
Dedicated (hardwired) Array Clock  
tHCKH  
Input Low to High (pad to S-module  
input)  
3.0  
3.0  
3.4  
3.4  
3.9  
3.9  
4.5  
4.5  
5.5  
5.5  
ns  
ns  
tHCKL  
Input High to Low (pad to S-module  
input)  
tHPWH  
tHPWL  
Minimum Pulse Width High  
Minimum Pulse Width Low  
1.9  
1.9  
2.4  
2.4  
3.3  
3.3  
3.8  
3.8  
4.8  
4.8  
ns  
ns  
ns  
ns  
tHCKSW Delta High to Low, Low Slew  
0.3  
0.3  
0.3  
0.3  
0.3  
tHP  
Minimum Period  
4.0  
5.0  
6.8  
8.0  
10.0  
fHMAX  
Maximum Frequency  
250  
200  
150  
125  
100 MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRPWH  
tRPWL  
Input Low to High (FO = 64)  
Input High to Low (FO = 64)  
Min. Pulse Width High (FO = 64)  
Min. Pulse Width Low (FO = 64)  
3.7  
4.0  
4.1  
4.5  
4.7  
5.1  
5.5  
6.0  
9.0  
9.0  
ns  
ns  
3.3  
3.3  
3.8  
3.8  
4.2  
4.2  
4.9  
4.9  
6.5  
6.5  
ns  
ns  
tRCKSW Maximum Skew (FO = 128)  
0.7  
0.8  
0.9  
1.0  
1.0  
75  
ns  
tRP  
Minimum Period (FO = 64)  
6.8  
8.0  
8.7  
10.0  
13.4  
ns  
fRMAX  
Maximum Frequency (FO = 64)  
150  
125  
115  
100  
MHz  
Clock-to-Clock Skews  
tIOHCKSW I/O Clock to H-Clock Skew  
0.0 1.7 0.0 1.8 0.0 2.0 0.0 2.2  
0.0  
0.0  
3.0  
3.0  
ns  
ns  
ns  
tIORCKSW I/O Clock to R-Clock Skew (FO = 64) 0.0 1.0 0.0 1.0 0.0 1.0 0.0 1.0  
tHRCKSW H-Clock to R-Clock Skew (FO = 64)  
(FO = 50% maximum)  
0.0 1.0 0.0 1.0 0.0 1.0 0.0 1.0  
0.0  
0.0  
3.0  
3.0  
Notes:  
1. Delays based on 35 pF loading.  
2. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
Revision 3  
2-25  
Detailed Specifications  
A1425A, A14V25A Timing Characteristics  
Table 2-22 • A1425A, A14V25A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C1  
Logic Module Propagation Delays2 –3 Speed3 –2 Speed3 Std. Speed 3.3 V Speed1  
–1 Speed  
Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
Units  
tPD  
Internal Array Module  
2.0  
2.0  
2.0  
2.3  
2.3  
2.3  
2.6  
2.6  
2.6  
3.0  
3.0  
3.0  
3.9  
3.9  
3.9  
ns  
ns  
ns  
tCO  
Sequential Clock to Q  
tCLR  
Asynchronous Clear to Q  
Predicted Routing Delays4  
tRD1  
tRD2  
tRD3  
tRD4  
tRD8  
FO = 1 Routing Delay  
FO = 2 Routing Delay  
FO = 3 Routing Delay  
FO = 4 Routing Delay  
FO = 8 Routing Delay  
0.9  
1.2  
1.4  
1.7  
2.8  
1.0  
1.4  
1.6  
1.9  
3.2  
1.1  
1.6  
1.8  
2.2  
3.6  
1.3  
1.8  
2.1  
2.5  
4.2  
1.7  
2.4  
2.8  
3.3  
5.5  
ns  
ns  
ns  
ns  
ns  
Logic Module Sequential Timing  
tSUD  
tHD  
tSUD  
tHD  
Flip-Flop Data Input Setup  
Flip-Flop Data Input Hold  
Latch Data Input Setup  
Latch Data Input Hold  
0.5  
0.0  
0.5  
0.0  
1.9  
1.9  
4.0  
0.6  
0.0  
0.6  
0.0  
2.4  
2.4  
5.0  
0.7  
0.0  
0.7  
0.0  
3.2  
3.2  
6.8  
0.8  
0.0  
0.8  
0.0  
3.8  
3.8  
8.0  
0.8  
0.0  
0.8  
0.0  
4.8  
4.8  
10.0  
ns  
ns  
ns  
ns  
tWASYN Asynchronous Pulse Width  
tWCLKA Flip-Flop Clock Pulse Width  
ns  
ns  
tA  
Flip-Flop Clock Input Period  
Flip-Flop Clock Frequency  
ns  
fMAX  
Notes:  
250  
200  
150  
125  
100  
MHz  
1. VCC = 3.0 V for 3.3 V specifications.  
2. For dual-module macros, use t + t  
+ t  
+ t + t  
+ t  
or t  
+ t  
+ t  
, whichever is appropriate.  
SUD  
PD  
RD1  
PDn  
CO  
RD1  
PDn  
PD1  
RD1  
3. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
4. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for  
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case  
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to  
shipment.  
2-26  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
A1425A, A14V25A Timing Characteristics (continued)  
Table 2-23 • A1425A, A14V25A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C  
Units  
I/O Module Input Propagation Delays  
Parameter/Description  
–3 Speed1 –2Speed1 –1 Speed Std. Speed 3.3 V Speed1  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tINY  
Input Data Pad to Y  
2.8  
4.7  
4.7  
4.7  
4.7  
3.2  
5.3  
5.3  
5.3  
5.3  
3.6  
6.0  
6.0  
6.0  
6.0  
4.2  
7.0  
7.0  
7.0  
7.0  
5.5  
9.2  
9.2  
9.2  
9.2  
ns  
ns  
ns  
ns  
ns  
tICKY  
Input Reg IOCLK Pad to Y  
tOCKY Output Reg IOCLK Pad to Y  
tICLRY Input Asynchronous Clear to Y  
tOCLRY Output Asynchronous Clear to Y  
Predicted Input Routing Delays2  
tRD1  
tRD2  
tRD3  
tRD4  
tRD8  
FO = 1 Routing Delay  
FO = 2 Routing Delay  
FO = 3 Routing Delay  
FO = 4 Routing Delay  
FO = 8 Routing Delay  
0.9  
1.2  
1.4  
1.7  
2.8  
1.0  
1.4  
1.6  
1.9  
3.2  
1.1  
1.6  
1.8  
2.2  
3.6  
1.3  
1.8  
2.1  
2.5  
4.2  
1.7  
2.4  
2.8  
3.3  
5.5  
ns  
ns  
ns  
ns  
ns  
I/O Module Sequential Timing (wrt IOCLK pad)  
tINH  
Input F-F Data Hold  
Input F-F Data Setup  
Input Data Enable Hold  
0.0  
1.8  
0.0  
5.8  
0.7  
0.7  
0.3  
1.3  
0.0  
2.0  
0.0  
6.5  
0.8  
0.8  
0.4  
1.5  
0.0  
2.3  
0.0  
7.5  
0.9  
0.9  
0.4  
1.7  
0.0  
2.7  
0.0  
8.6  
1.0  
1.0  
0.5  
2.0  
0.0  
3.0  
0.0  
8.6  
1.0  
1.0  
0.5  
2.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tINSU  
tIDEH  
tIDESU Input Data Enable Setup  
tOUTH Output F-F Data hold  
tOUTSU Output F-F Data Setup  
tODEH Output Data Enable Hold  
fODESU Output Data Enable Setup  
Notes: *  
1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for  
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case  
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to  
shipment.  
Revision 3  
2-27  
Detailed Specifications  
A1425A, A14V25A Timing Characteristics (continued)  
Table 2-24 • A1425A, A14V25A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C  
I/O Module – TTL Output Timing1  
–3 Speed2 –2Speed2 –1 Speed Std. Speed 3.3 V Speed1  
Units  
Parameter/Description  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tDHS  
tDLS  
Data to Pad, High Slew  
Data to Pad, Low Slew  
5.0  
8.0  
5.6  
9.0  
6.4  
10.2  
5.1  
7.5  
9.8  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
12.0  
6.0  
15.6  
7.8  
tENZHS Enable to Pad, Z to H/L, High Slew  
tENZLS Enable to Pad, Z to H/L, Low Slew  
tENHSZ Enable to Pad, H/L to Z, High Slew  
tENLSZ Enable to Pad, H/L to Z, Low Slew  
tCKHS IOCLK Pad to Pad H/L, High Slew  
tCKLS IOCLK Pad to Pad H/L, Low Slew  
dTLHHS Delta Low to High, High Slew  
dTLHLS Delta Low to High, Low Slew  
dTHLHS Delta High to Low, High Slew  
dTHLLS Delta High to Low, Low Slew  
I/O Module – CMOS Output Timing1  
4.0  
4.5  
7.4  
8.3  
9.4  
11.0  
10.0  
10.0  
10.0  
15.0  
0.03  
0.07  
0.05  
0.07  
14.3  
13.0  
13.0  
13.0  
19.5  
6.5  
7.5  
8.5  
6.5  
7.5  
8.5  
7.5  
7.5  
9.0  
11.3  
0.02  
0.05  
0.04  
0.05  
11.3  
0.02  
0.05  
0.04  
0.05  
13.5  
0.03  
0.06  
0.04  
0.06  
0.04 ns/pF  
0.09 ns/pF  
0.07 ns/pF  
0.09 ns/pF  
tDHS  
tDLS  
Data to Pad, High Slew  
Data to Pad, Low Slew  
6.2  
11.7  
5.2  
7.0  
13.1  
5.9  
7.9  
14.9  
6.6  
9.3  
12.1  
22.8  
10.1  
17.3  
13.0  
13.0  
15.3  
22.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
17.5  
7.8  
tENZHS Enable to Pad, Z to H/L, High Slew  
tENZLS Enable to Pad, Z to H/L, Low Slew  
tENHSZ Enable to Pad, H/L to Z, High Slew  
tENLSZ Enable to Pad, H/L to Z, Low Slew  
tCKHS IOCLK Pad to Pad H/L, High Slew  
tCKLS IOCLK Pad to Pad H/L, Low Slew  
dTLHHS Delta Low to High, High Slew  
dTLHLS Delta Low to High, Low Slew  
dTHLHS Delta High to Low, High Slew  
dTHLLS Delta High to Low, Low Slew  
8.9  
10.0  
7.5  
11.3  
8.5  
13.3  
10.0  
10.0  
11.8  
17.3  
0.06  
0.11  
0.04  
0.05  
6.7  
6.7  
7.5  
9.0  
8.9  
8.9  
10.7  
15.6  
0.05  
0.09  
0.03  
0.04  
13.0  
0.04  
0.07  
0.03  
0.04  
13.0  
0.04  
0.08  
0.03  
0.04  
0.08 ns/pF  
0.14 ns/pF  
0.05 ns/pF  
0.07 ns/pF  
Notes: *  
1. Delays based on 35 pF loading.  
2. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
2-28  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
A1425A, A14V25A Timing Characteristics (continued)  
Table 2-25 • A1425A, A14V25A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C  
Units  
Dedicated (hardwired) I/O Clock Network  
Parameter/Description  
–3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tIOCKH  
Input Low to High (pad to I/O module  
input)  
2.0  
2.3  
2.6  
3.0  
3.5  
0.4  
ns  
tIOPWH  
tIPOWL  
Minimum Pulse Width High  
Minimum Pulse Width Low  
1.9  
1.9  
1.9  
2.4  
2.4  
2.4  
3.3  
3.3  
3.3  
3.8  
3.8  
3.8  
4.8  
4.8  
4.8  
ns  
ns  
ns  
ns  
ns  
tIOSAPW Minimum Asynchronous Pulse Width  
tIOCKSW Maximum Skew  
0.4  
0.4  
0.4  
0.4  
tIOP  
Minimum Period  
4.0  
5.0  
6.8  
8.0  
10.0  
fIOMAX  
Maximum Frequency  
250  
200  
150  
125  
100 MHz  
Dedicated (hardwired) Array Clock  
tHCKH  
Input Low to High (pad to S-module  
input)  
3.0  
3.0  
3.4  
3.4  
3.9  
3.9  
4.5  
4.5  
5.5  
5.5  
ns  
ns  
tHCKL  
Input High to Low (pad to S-module  
input)  
tHPWH  
tHPWL  
Minimum Pulse Width High  
Minimum Pulse Width Low  
1.9  
1.9  
2.4  
2.4  
3.3  
3.3  
3.8  
3.8  
4.8  
4.8  
ns  
ns  
ns  
ns  
tHCKSW Delta High to Low, Low Slew  
0.3  
0.3  
0.3  
0.3  
0.3  
tHP  
Minimum Period  
4.0  
5.0  
6.8  
8.0  
10.0  
fHMAX  
Maximum Frequency  
250  
200  
150  
125  
100 MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRPWH  
tRPWL  
Input Low to High (FO = 64)  
Input High to Low (FO = 64)  
Min. Pulse Width High (FO = 64)  
Min. Pulse Width Low (FO = 64)  
3.7  
4.0  
4.1  
4.5  
4.7  
5.1  
5.5  
6.0  
9.0  
9.0  
ns  
ns  
3.3  
3.3  
3.8  
3.8  
4.2  
4.2  
4.9  
4.9  
6.5  
6.5  
ns  
ns  
tRCKSW Maximum Skew (FO = 128)  
0.7  
0.8  
0.9  
1.0  
1.0  
75  
ns  
tRP  
Minimum Period (FO = 64)  
6.8  
8.0  
8.7  
10.0  
13.4  
0.0  
ns  
fRMAX  
Maximum Frequency (FO = 64)  
150  
125  
115  
100  
MHz  
Clock-to-Clock Skews  
tIOHCKSW I/O Clock to H-Clock Skew  
0.0 1.7 0.0 1.8 0.0 2.0 0.0 2.2  
3.0  
ns  
ns  
tIORCKSW I/O Clock to R-Clock Skew (FO = 64) 0.0 1.0 0.0 1.0 0.0 1.0 0.0 1.0  
0.0  
0.0  
3.0  
3.0  
(FO = 80)  
0.0 3.0 0.0 3.0 0.0 3.0 0.0 3.0  
tHRCKSW H-Clock to R-Clock Skew (FO = 64)  
(FO = 80)  
0.0 1.0 0.0 1.0 0.0 1.0 0.0 1.0  
0.0 3.0 0.0 3.0 0.0 3.0 0.0 3.0  
0.0  
0.0  
1.0  
3.0  
ns  
Notes:  
1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
2. Delays based on 35 pF loading.  
Revision 3  
2-29  
Detailed Specifications  
A1440A, A14V40A Timing Characteristics  
Table 2-26 • A1440A, A14V40A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C1  
Logic Module Propagation Delays2 –3 Speed 3 –2 Speed3 Std. Speed 3.3 V Speed1  
–1 Speed  
Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
Units  
tPD  
Internal Array Module  
2.0  
2.0  
2.0  
2.3  
2.3  
2.3  
2.6  
2.6  
2.6  
3.0  
3.0  
3.0  
3.9  
3.9  
3.9  
ns  
ns  
ns  
tCO  
Sequential Clock to Q  
tCLR  
Asynchronous Clear to Q  
Predicted Routing Delays4  
tRD1  
tRD2  
tRD3  
tRD4  
tRD8  
FO = 1 Routing Delay  
FO = 2 Routing Delay  
FO = 3 Routing Delay  
FO = 4 Routing Delay  
FO = 8 Routing Delay  
0.9  
1.2  
1.4  
1.7  
2.8  
1.0  
1.4  
1.6  
1.9  
3.2  
1.1  
1.6  
1.8  
2.2  
3.6  
1.3  
1.8  
2.1  
2.5  
4.2  
1.7  
2.4  
2.8  
3.3  
5.5  
ns  
ns  
ns  
ns  
ns  
Logic Module Sequential Timing  
tSUD  
tHD  
tSUD  
tHD  
Flip-Flop Data Input Setup  
Flip-Flop Data Input Hold  
Latch Data Input Setup  
Latch Data Input Hold  
0.5  
0.0  
0.5  
0.0  
1.9  
1.9  
4.0  
0.6  
0.0  
0.6  
0.0  
2.4  
2.4  
5.0  
0.7  
0.0  
0.7  
0.0  
3.2  
3.2  
6.8  
0.8  
0.0  
0.8  
0.0  
3.8  
3.8  
8.0  
0.8  
0.0  
0.8  
0.0  
4.8  
4.8  
10.0  
ns  
ns  
ns  
ns  
tWASYN Asynchronous Pulse Width  
tWCLKA Flip-Flop Clock Pulse Width  
ns  
ns  
tA  
Flip-Flop Clock Input Period  
Flip-Flop Clock Frequency  
ns  
fMAX  
Notes:  
250  
200  
150  
125  
100  
MHz  
1. VCC = 3.0 V for 3.3 V specifications.  
2. For dual-module macros, use t + t  
+ t  
+ t + t  
+ t  
or t  
+ t  
+ t  
, whichever is appropriate.  
SUD  
PD  
RD1  
PDn  
CO  
RD1  
PDn  
PD1  
RD1  
3. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
4. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for  
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case  
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to  
shipment.  
2-30  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
A1440A, A14V40A Timing Characteristics (continued)  
Table 2-27 • A1440A, A14V40A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C  
Units  
I/O Module Input Propagation Delays  
Parameter/Description  
–3 Speed1 –2Speed1 –1 Speed Std. Speed 3.3 V Speed1  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tINY  
Input Data Pad to Y  
2.8  
4.7  
4.7  
4.7  
4.7  
3.2  
5.3  
5.3  
5.3  
5.3  
3.6  
6.0  
6.0  
6.0  
6.0  
4.2  
7.0  
7.0  
7.0  
7.0  
5.5  
9.2  
9.2  
9.2  
9.2  
ns  
ns  
ns  
ns  
ns  
tICKY  
Input Reg IOCLK Pad to Y  
tOCKY Output Reg IOCLK Pad to Y  
tICLRY Input Asynchronous Clear to Y  
tOCLRY Output Asynchronous Clear to Y  
Predicted Input Routing Delays2  
tRD1  
tRD2  
tRD3  
tRD4  
tRD8  
FO = 1 Routing Delay  
FO = 2 Routing Delay  
FO = 3 Routing Delay  
FO = 4 Routing Delay  
FO = 8 Routing Delay  
0.9  
1.2  
1.4  
1.7  
2.8  
1.0  
1.4  
1.6  
1.9  
3.2  
1.1  
1.6  
1.8  
2.2  
3.6  
1.3  
1.8  
2.1  
2.5  
4.2  
1.7  
2.4  
2.8  
3.3  
5.5  
ns  
ns  
ns  
ns  
ns  
I/O Module Sequential Timing (wrt IOCLK pad)  
tINH  
Input F-F Data Hold  
Input F-F Data Setup  
Input Data Enable Hold  
0.0  
1.8  
0.0  
5.8  
0.7  
0.7  
0.3  
1.3  
0.0  
1.7  
0.0  
6.5  
0.8  
0.8  
0.4  
1.5  
0.0  
2.0  
0.0  
7.5  
0.9  
0.9  
0.4  
1.7  
0.0  
2.3  
0.0  
8.6  
1.0  
1.0  
0.5  
2.0  
0.0  
2.3  
0.0  
8.6  
1.0  
1.0  
0.5  
2.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tINSU  
tIDEH  
tIDESU Input Data Enable Setup  
tOUTH Output F-F Data hold  
tOUTSU Output F-F Data Setup  
tODEH Output Data Enable Hold  
fODESU Output Data Enable Setup  
Notes:  
1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for  
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case  
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to  
shipment.  
Revision 3  
2-31  
Detailed Specifications  
A1440A, A14V40A Timing Characteristics (continued)  
Table 2-28 • A1440A, A14V40A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C  
I/O Module – TTL Output Timing1  
–3 Speed2 –2Speed2 –1 Speed Std. Speed 3.3 V Speed1  
Units  
Parameter/Description  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tDHS  
tDLS  
Data to Pad, High Slew  
Data to Pad, Low Slew  
5.0  
8.0  
5.6  
9.0  
6.4  
10.2  
5.1  
7.5  
9.8  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
12.0  
6.0  
15.6  
7.8  
tENZHS Enable to Pad, Z to H/L, High Slew  
tENZLS Enable to Pad, Z to H/L, Low Slew  
tENHSZ Enable to Pad, H/L to Z, High Slew  
tENLSZ Enable to Pad, H/L to Z, Low Slew  
tCKHS IOCLK Pad to Pad H/L, High Slew  
tCKLS IOCLK Pad to Pad H/L, Low Slew  
dTLHHS Delta Low to High, High Slew  
dTLHLS Delta Low to High, Low Slew  
dTHLHS Delta High to Low, High Slew  
dTHLLS Delta High to Low, Low Slew  
I/O Module – CMOS Output Timing1  
4.0  
4.5  
7.4  
8.3  
9.4  
11.0  
11.0  
11.0  
11.0  
15.0  
0.03  
0.07  
0.05  
0.07  
14.3  
14.3  
14.3  
14.3  
19.5  
7.4  
8.3  
9.4  
7.4  
8.3  
9.4  
8.5  
8.5  
9.5  
11.3  
0.02  
0.05  
0.04  
0.05  
11.3  
0.02  
0.05  
0.04  
0.05  
13.5  
0.03  
0.06  
0.04  
0.06  
0.04 ns/pF  
0.09 ns/pF  
0.07 ns/pF  
0.09 ns/pF  
tDHS  
tDLS  
Data to Pad, High Slew  
Data to Pad, Low Slew  
6.2  
11.7  
5.2  
7.0  
13.1  
5.9  
7.9  
14.9  
6.6  
9.3  
12.1  
22.8  
10.1  
17.3  
14.3  
14.3  
14.3  
22.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
17.5  
7.8  
tENZHS Enable to Pad, Z to H/L, High Slew  
tENZLS Enable to Pad, Z to H/L, Low Slew  
tENHSZ Enable to Pad, H/L to Z, High Slew  
tENLSZ Enable to Pad, H/L to Z, Low Slew  
tCKHS IOCLK Pad to Pad H/L, High Slew  
tCKLS IOCLK Pad to Pad H/L, Low Slew  
dTLHHS Delta Low to High, High Slew  
dTLHLS Delta Low to High, Low Slew  
dTHLHS Delta High to Low, High Slew  
dTHLLS Delta High to Low, Low Slew  
8.9  
10.0  
8.3  
11.3  
9.4  
13.3  
11.0  
11.0  
11.8  
17.3  
0.06  
0.11  
0.04  
0.05  
7.4  
7.4  
8.3  
9.4  
9.0  
9.0  
10.1  
15.6  
0.05  
0.09  
0.03  
0.04  
13.0  
0.04  
0.07  
0.03  
0.04  
13.0  
0.04  
0.08  
0.03  
0.04  
0.08 ns/pF  
0.14 ns/pF  
0.05 ns/pF  
0.07 ns/pF  
Notes:  
1. Delays based on 35 pF loading.  
2. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
2-32  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
A1440A, A14V40A Timing Characteristics (continued)  
Table 2-29 • A1440A, A14V40A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C  
Units  
Dedicated (hardwired) I/O Clock Network  
Parameter/Description  
–3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tIOCKH  
Input Low to High (pad to I/O module  
input)  
2.0  
2.3  
2.6  
3.0  
3.5  
0.4  
ns  
tIOPWH  
tIPOWL  
Minimum Pulse Width High  
Minimum Pulse Width Low  
1.9  
1.9  
1.9  
2.4  
2.4  
2.4  
3.3  
3.3  
3.3  
3.8  
3.8  
3.8  
4.8  
4.8  
4.8  
ns  
ns  
ns  
ns  
ns  
tIOSAPW Minimum Asynchronous Pulse Width  
tIOCKSW Maximum Skew  
0.4  
0.4  
0.4  
0.4  
tIOP  
Minimum Period  
4.0  
5.0  
6.8  
8.0  
10.0  
fIOMAX  
Maximum Frequency  
250  
200  
150  
125  
100 MHz  
Dedicated (hardwired) Array Clock  
tHCKH  
Input Low to High (pad to S-module  
input)  
3.0  
3.0  
3.4  
3.4  
3.9  
3.9  
4.5  
4.5  
5.5  
5.5  
ns  
ns  
tHCKL  
Input High to Low (pad to S-module  
input)  
tHPWH  
tHPWL  
Minimum Pulse Width High  
Minimum Pulse Width Low  
1.9  
1.9  
2.4  
2.4  
3.3  
3.3  
3.8  
3.8  
4.8  
4.8  
ns  
ns  
ns  
ns  
tHCKSW Delta High to Low, Low Slew  
0.3  
0.3  
0.3  
0.3  
0.3  
tHP  
Minimum Period  
4.0  
5.0  
6.8  
8.0  
10.0  
fHMAX  
Maximum Frequency  
250  
200  
150  
125  
100 MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRPWH  
tRPWL  
Input Low to High (FO = 64)  
Input High to Low (FO = 64)  
Min. Pulse Width High (FO = 64)  
Min. Pulse Width Low (FO = 64)  
3.7  
4.0  
4.1  
4.5  
4.7  
5.1  
5.5  
6.0  
9.0  
9.0  
ns  
ns  
3.3  
3.3  
3.8  
3.8  
4.2  
4.2  
4.9  
4.9  
6.5  
6.5  
ns  
ns  
tRCKSW Maximum Skew (FO = 128)  
0.7  
0.8  
0.9  
1.0  
1.0  
75  
ns  
tRP  
Minimum Period (FO = 64)  
6.8  
8.0  
8.7  
10.0  
13.4  
0.0  
ns  
fRMAX  
Maximum Frequency (FO = 64)  
150  
125  
115  
100  
MHz  
Clock-to-Clock Skews  
tIOHCKSW I/O Clock to H-Clock Skew  
0.0 1.7 0.0 1.8 0.0 2.0 0.0 2.2  
3.0  
ns  
ns  
tIORCKSW I/O Clock to R-Clock Skew (FO = 64) 0.0 1.0 0.0 1.0 0.0 1.0 0.0 1.0  
0.0  
0.0  
3.0  
3.0  
(FO = 144)  
0.0 3.0 0.0 3.0 0.0 3.0 0.0 3.0  
tHRCKSW H-Clock to R-Clock Skew (FO = 64)  
(FO = 144)  
0.0 1.0 0.0 1.0 0.0 1.0 0.0 1.0  
0.0 3.0 0.0 3.0 0.0 3.0 0.0 3.0  
0.0  
0.0  
1.0  
3.0  
ns  
Notes:  
1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
2. Delays based on 35 pF loading.  
Revision 3  
2-33  
Detailed Specifications  
A1460A, A14V60A Timing Characteristics  
Table 2-30 • A1460A, A14V60A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C1  
Logic Module Propagation Delays2 –3 Speed3 –2 Speed 3 –1 Speed Std. Speed 3.3 V Speed1  
Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
Units  
tPD  
Internal Array Module  
2.0  
2.0  
2.0  
2.3  
2.3  
2.3  
2.6  
2.6  
2.6  
3.0  
3.0  
3.0  
3.9  
3.9  
3.9  
ns  
ns  
ns  
tCO  
Sequential Clock to Q  
tCLR  
Asynchronous Clear to Q  
Predicted Routing Delays4  
tRD1  
tRD2  
tRD3  
tRD4  
tRD8  
FO = 1 Routing Delay  
FO = 2 Routing Delay  
FO = 3 Routing Delay  
FO = 4 Routing Delay  
FO = 8 Routing Delay  
0.9  
1.2  
1.4  
1.7  
2.8  
1.0  
1.4  
1.6  
1.9  
3.2  
1.1  
1.6  
1.8  
2.2  
3.6  
1.3  
1.8  
2.1  
2.5  
4.2  
1.7  
2.4  
2.8  
3.3  
5.5  
ns  
ns  
ns  
ns  
ns  
Logic Module Sequential Timing  
tSUD  
tHD  
tSUD  
tHD  
Flip-Flop Data Input Setup  
Flip-Flop Data Input Hold  
Latch Data Input Setup  
Latch Data Input Hold  
0.5  
0.0  
0.5  
0.0  
2.4  
2.4  
5.0  
0.6  
0.0  
0.6  
0.0  
3.2  
3.2  
6.8  
0.7  
0.0  
0.7  
0.0  
3.8  
3.8  
8.0  
0.8  
0.0  
0.8  
0.0  
4.8  
4.8  
10.0  
0.8  
0.0  
0.8  
0.0  
6.5  
6.5  
13.4  
ns  
ns  
ns  
ns  
tWASYN Asynchronous Pulse Width  
tWCLKA Flip-Flop Clock Pulse Width  
ns  
ns  
tA  
Flip-Flop Clock Input Period  
Flip-Flop Clock Frequency  
ns  
fMAX  
Notes:  
200  
150  
125  
100  
75  
MHz  
1. VCC = 3.0 V for 3.3 V specifications.  
2. For dual-module macros, use t + t  
+ t  
+ t + t  
+ t  
or t  
+ t  
+ t  
, whichever is appropriate.  
SUD  
PD  
RD1  
PDn  
CO  
RD1  
PDn  
PD1  
RD1  
3. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
4. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for  
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case  
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to  
shipment.  
2-34  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
A1460A, A14V60A Timing Characteristics (continued)  
Table 2-31 • A1460A, A14V60A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C  
Units  
I/O Module Input Propagation Delays  
Parameter/Description  
–3 Speed1 –2Speed1 –1 Speed Std. Speed 3.3 V Speed1  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tINY  
Input Data Pad to Y  
2.8  
4.7  
4.7  
4.7  
4.7  
3.2  
5.3  
5.3  
5.3  
5.3  
3.6  
6.0  
6.0  
6.0  
6.0  
4.2  
7.0  
7.0  
7.0  
7.0  
5.5  
9.2  
9.2  
9.2  
9.2  
ns  
ns  
ns  
ns  
ns  
tICKY  
Input Reg IOCLK Pad to Y  
tOCKY Output Reg IOCLK Pad to Y  
tICLRY Input Asynchronous Clear to Y  
tOCLRY Output Asynchronous Clear to Y  
Predicted Input Routing Delays2  
tRD1  
tRD2  
tRD3  
tRD4  
tRD8  
FO = 1 Routing Delay  
FO = 2 Routing Delay  
FO = 3 Routing Delay  
FO = 4 Routing Delay  
FO = 8 Routing Delay  
0.9  
1.2  
1.4  
1.7  
2.8  
1.0  
1.4  
1.6  
1.9  
3.2  
1.1  
1.6  
1.8  
2.2  
3.6  
1.3  
1.8  
2.1  
2.5  
4.2  
1.7  
2.4  
2.8  
3.3  
5.5  
ns  
ns  
ns  
ns  
ns  
I/O Module Sequential Timing (wrt IOCLK pad)  
tINH  
Input F-F Data Hold  
Input F-F Data Setup  
Input Data Enable Hold  
0.0  
1.3  
0.0  
5.8  
0.7  
0.7  
0.3  
1.3  
0.0  
1.5  
0.0  
6.5  
0.8  
0.8  
0.4  
1.5  
0.0  
1.8  
0.0  
7.5  
0.9  
0.9  
0.4  
1.7  
0.0  
2.0  
0.0  
8.6  
1.0  
1.0  
0.5  
2.0  
0.0  
2.0  
0.0  
8.6  
1.0  
1.0  
0.5  
2.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tINSU  
tIDEH  
tIDESU Input Data Enable Setup  
tOUTH Output F-F Data hold  
tOUTSU Output F-F Data Setup  
tODEH Output Data Enable Hold  
fODESU Output Data Enable Setup  
Notes:  
5. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
6. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for  
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case  
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to  
shipment.  
Revision 3  
2-35  
Detailed Specifications  
A1460A, A14V60A Timing Characteristics (continued)  
Table 2-32 • A1460A, A14V60A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C  
I/O Module – TTL Output Timing1  
–3 Speed2 –2Speed2 –1 Speed Std. Speed 3.3 V Speed1  
Units  
Parameter/Description  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tDHS  
tDLS  
Data to Pad, High Slew  
Data to Pad, Low Slew  
5.0  
8.0  
5.6  
9.0  
6.4  
10.2  
5.1  
7.5  
9.8  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
12.0  
6.0  
15.6  
7.8  
tENZHS Enable to Pad, Z to H/L, High Slew  
tENZLS Enable to Pad, Z to H/L, Low Slew  
tENHSZ Enable to Pad, H/L to Z, High Slew  
tENLSZ Enable to Pad, H/L to Z, Low Slew  
tCKHS IOCLK Pad to Pad H/L, High Slew  
tCKLS IOCLK Pad to Pad H/L, Low Slew  
dTLHHS Delta Low to High, High Slew  
dTLHLS Delta Low to High, Low Slew  
dTHLHS Delta High to Low, High Slew  
dTHLLS Delta High to Low, Low Slew  
I/O Module – CMOS Output Timing1  
4.0  
4.5  
7.4  
8.3  
9.4  
11.0  
11.6  
11.0  
11.5  
17.0  
0.03  
0.07  
0.05  
0.07  
14.3  
15.1  
14.3  
15.0  
22.1  
7.8  
8.7  
9.9  
7.4  
8.3  
9.4  
9.0  
9.0  
10.0  
15.3  
0.03  
0.06  
0.04  
0.06  
12.8  
0.02  
0.05  
0.04  
0.05  
12.8  
0.02  
0.05  
0.04  
0.05  
0.04 ns/pF  
0.09 ns/pF  
0.07 ns/pF  
0.09 ns/pF  
tDHS  
tDLS  
Data to Pad, High Slew  
Data to Pad, Low Slew  
6.2  
11.7  
5.2  
7.0  
13.1  
5.9  
7.9  
14.9  
6.6  
9.3  
12.1  
22.8  
10.1  
17.3  
14.3  
14.3  
17.9  
25.1  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
17.5  
7.8  
tENZHS Enable to Pad, Z to H/L, High Slew  
tENZLS Enable to Pad, Z to H/L, Low Slew  
tENHSZ Enable to Pad, H/L to Z, High Slew  
tENLSZ Enable to Pad, H/L to Z, Low Slew  
tCKHS IOCLK Pad to Pad H/L, High Slew  
tCKLS IOCLK Pad to Pad H/L, Low Slew  
dTLHHS Delta Low to High, High Slew  
dTLHLS Delta Low to High, Low Slew  
dTHLHS Delta High to Low, High Slew  
dTHLLS Delta High to Low, Low Slew  
8.9  
10.0  
8.3  
11.3  
9.4  
13.3  
11.0  
11.0  
13.8  
19.3  
0.06  
0.11  
0.04  
0.05  
7.4  
7.4  
8.3  
9.4  
10.4  
14.5  
0.04  
0.07  
0.03  
0.04  
10.4  
14.5  
0.04  
0.08  
0.03  
0.04  
12.1  
17.4  
0.05  
0.09  
0.03  
0.04  
0.08 ns/pF  
0.14 ns/pF  
0.05 ns/pF  
0.07 ns/pF  
Notes:  
1. Delays based on 35 pF loading.  
2. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
2-36  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
A1460A, A14V60A Timing Characteristics (continued)  
Table 2-33 • A1460A, A14V60A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C  
Units  
Dedicated (hardwired) I/O Clock Network  
Parameter/Description  
–3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tIOCKH  
Input Low to High (pad to I/O module  
input)  
2.3  
2.6  
3.0  
3.5  
4.5  
ns  
tIOPWH  
tIPOWL  
Minimum Pulse Width High  
Minimum Pulse Width Low  
2.4  
2.4  
2.4  
3.2  
3.2  
3.2  
3.8  
3.8  
3.8  
4.8  
4.8  
4.8  
6.5  
6.5  
6.5  
ns  
ns  
tIOSAPW Minimum Asynchronous Pulse Width  
tIOCKSW Maximum Skew  
ns  
0.6  
0.6  
0.6  
0.6  
0.6  
75  
ns  
tIOP  
Minimum Period  
5.0  
6.8  
8.0  
10.0  
13.4  
ns  
fIOMAX  
Maximum Frequency  
200  
150  
125  
100  
MHz  
Dedicated (hardwired) Array Clock  
tHCKH  
Input Low to High (pad to S-module  
input)  
3.7  
3.7  
4.1  
4.1  
4.7  
4.7  
5.5  
5.5  
7.0  
7.0  
ns  
ns  
tHCKL  
Input High to Low (pad to S-module  
input)  
tHPWH  
tHPWL  
Minimum Pulse Width High  
Minimum Pulse Width Low  
2.4  
2.4  
3.2  
3.2  
3.8  
3.8  
4.8  
4.8  
6.5  
6.5  
ns  
ns  
tHCKSW Delta High to Low, Low Slew  
0.6  
0.6  
0.6  
0.6  
0.6  
75  
ns  
tHP  
Minimum Period  
5.0  
6.8  
8.0  
10.0  
13.4  
ns  
fHMAX  
Maximum Frequency  
200  
150  
125  
100  
MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRPWH  
tRPWL  
Input Low to High (FO = 64)  
Input High to Low (FO = 64)  
Min. Pulse Width High (FO = 64)  
Min. Pulse Width Low (FO = 64)  
6.0  
6.0  
6.8  
6.8  
7.7  
7.7  
9.0  
9.0  
11.8  
11.8  
ns  
ns  
4.1  
4.1  
4.5  
4.5  
5.4  
5.4  
6.1  
6.1  
8.2  
8.2  
ns  
ns  
tRCKSW Maximum Skew (FO = 128)  
1.2  
1.4  
1.6  
90  
1.8  
80  
1.8  
60  
ns  
tRP  
Minimum Period (FO = 64)  
8.3  
9.3  
11.1  
12.5  
16.7  
0.0  
ns  
fRMAX  
Maximum Frequency (FO = 64)  
120  
105  
MHz  
Clock-to-Clock Skews  
tIOHCKSW I/O Clock to H-Clock Skew  
0.0 2.6 0.0 2.7 0.0 2.9 0.0 3.0  
3.0  
ns  
ns  
tIORCKSW I/O Clock to R-Clock Skew (FO = 64) 0.0 1.7 0.0 1.7 0.0 1.7 0.0 1.7  
0.0  
0.0  
5.0  
5.0  
(FO = 216)  
0.0 5.0 0.0 5.0 0.0 5.0 0.0 5.0  
tHRCKSW H-Clock to R-Clock Skew (FO = 64)  
(FO = 216)  
0.0 1.3 0.0 1.0 0.0 1.0 0.0 1.0  
0.0 3.0 0.0 3.0 0.0 3.0 0.0 3.0  
0.0  
0.0  
1.0  
3.0  
ns  
Notes:  
1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
2. Delays based on 35 pF loading.  
Revision 3  
2-37  
Detailed Specifications  
A14100A, A14V100A Timing Characteristics  
Table 2-34 • A14100A, A14V100A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C1  
Logic Module Propagation Delays2 –3 Speed3 –2 Speed 3 –1 Speed Std. Speed 3.3 V Speed1  
Parameter/Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
Units  
tPD  
Internal Array Module  
2.0  
2.0  
2.0  
2.3  
2.3  
2.3  
2.6  
2.6  
2.6  
3.0  
3.0  
3.0  
3.9  
3.9  
3.9  
ns  
ns  
ns  
tCO  
Sequential Clock to Q  
tCLR  
Asynchronous Clear to Q  
Predicted Routing Delays4  
tRD1  
tRD2  
tRD3  
tRD4  
tRD8  
FO = 1 Routing Delay  
FO = 2 Routing Delay  
FO = 3 Routing Delay  
FO = 4 Routing Delay  
FO = 8 Routing Delay  
0.9  
1.2  
1.4  
1.7  
2.8  
1.0  
1.4  
1.6  
1.9  
3.2  
1.1  
1.6  
1.8  
2.2  
3.6  
1.3  
1.8  
2.1  
2.5  
4.2  
1.7  
2.4  
2.8  
3.3  
5.5  
ns  
ns  
ns  
ns  
ns  
Logic Module Sequential Timing  
tSUD  
tHD  
tSUD  
tHD  
Flip-Flop Data Input Setup  
Flip-Flop Data Input Hold  
Latch Data Input Setup  
Latch Data Input Hold  
0.5  
0.0  
0.5  
0.0  
2.4  
2.4  
5.0  
0.6  
0.0  
0.6  
0.0  
3.2  
3.2  
6.8  
0.8  
0.5  
0.8  
0.5  
3.8  
3.8  
8.0  
0.8  
0.5  
0.8  
0.5  
4.8  
4.8  
10.0  
0.8  
0.5  
0.8  
0.5  
6.5  
6.5  
13.4  
ns  
ns  
ns  
ns  
tWASYN Asynchronous Pulse Width  
tWCLKA Flip-Flop Clock Pulse Width  
ns  
ns  
tA  
Flip-Flop Clock Input Period  
Flip-Flop Clock Frequency  
ns  
fMAX  
Notes:  
200  
150  
125  
100  
75  
MHz  
1. VCC = 3.0 V for 3.3 V specifications.  
2. For dual-module macros, use t + t  
+ t  
+ t + t  
+ t  
or t  
+ t  
+ t  
, whichever is appropriate.  
SUD  
PD  
RD1  
PDn  
CO  
RD1  
PDn  
PD1  
RD1  
3. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
4. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for  
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case  
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to  
shipment.  
2-38  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
A14100A, A14V100A Timing Characteristics (continued)  
Table 2-35 • A14100A, A14V100A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C  
Units  
I/O Module Input Propagation Delays  
Parameter/Description  
–3 Speed1 –2Speed1 –1 Speed Std. Speed 3.3 V Speed1  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tINY  
Input Data Pad to Y  
2.8  
4.7  
4.7  
4.7  
4.7  
3.2  
5.3  
5.3  
5.3  
5.3  
3.6  
6.0  
6.0  
6.0  
6.0  
4.2  
7.0  
7.0  
7.0  
7.0  
5.5  
9.2  
9.2  
9.2  
9.2  
ns  
ns  
ns  
ns  
ns  
tICKY  
Input Reg IOCLK Pad to Y  
tOCKY Output Reg IOCLK Pad to Y  
tICLRY Input Asynchronous Clear to Y  
tOCLRY Output Asynchronous Clear to Y  
Predicted Input Routing Delays2  
tRD1  
tRD2  
tRD3  
tRD4  
tRD8  
FO = 1 Routing Delay  
FO = 2 Routing Delay  
FO = 3 Routing Delay  
FO = 4 Routing Delay  
FO = 8 Routing Delay  
0.9  
1.2  
1.4  
1.7  
2.8  
1.0  
1.4  
1.6  
1.9  
3.2  
1.1  
1.6  
1.8  
2.2  
3.6  
1.3  
1.8  
2.1  
2.5  
4.2  
1.7  
2.4  
2.8  
3.3  
5.5  
ns  
ns  
ns  
ns  
ns  
I/O Module Sequential Timing (wrt IOCLK pad)  
tINH  
Input F-F Data Hold  
Input F-F Data Setup  
Input Data Enable Hold  
0.0  
1.2  
0.0  
5.8  
0.7  
0.7  
0.3  
1.3  
0.0  
1.4  
0.0  
6.5  
0.8  
0.8  
0.4  
1.5  
0.0  
1.5  
0.0  
7.5  
1.0  
1.0  
0.5  
2.0  
0.0  
1.8  
0.0  
8.6  
1.0  
1.0  
0.5  
2.0  
0.0  
1.8  
0.0  
8.6  
1.0  
1.0  
0.5  
2.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tINSU  
tIDEH  
tIDESU Input Data Enable Setup  
tOUTH Output F-F Data hold  
tOUTSU Output F-F Data Setup  
tODEH Output Data Enable Hold  
fODESU Output Data Enable Setup  
Notes: *  
1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for  
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case  
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to  
shipment.  
Revision 3  
2-39  
Detailed Specifications  
A14100A, A14V100A Timing Characteristics (continued)  
Table 2-36 • A14100A, A14V100A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C  
I/O Module – TTL Output Timing1  
–3 Speed2 –2Speed2 –1 Speed Std. Speed 3.3 V Speed1  
Units  
Parameter/Description  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tDHS  
tDLS  
Data to Pad, High Slew  
Data to Pad, Low Slew  
5.0  
8.0  
5.6  
9.0  
6.4  
10.2  
5.1  
7.5  
9.8  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
12.0  
6.0  
15.6  
7.8  
tENZHS Enable to Pad, Z to H/L, High Slew  
tENZLS Enable to Pad, Z to H/L, Low Slew  
tENHSZ Enable to Pad, H/L to Z, High Slew  
tENLSZ Enable to Pad, H/L to Z, Low Slew  
tCKHS IOCLK Pad to Pad H/L, High Slew  
tCKLS IOCLK Pad to Pad H/L, Low Slew  
dTLHHS Delta Low to High, High Slew  
dTLHLS Delta Low to High, Low Slew  
dTHLHS Delta High to Low, High Slew  
dTHLLS Delta High to Low, Low Slew  
I/O Module – CMOS Output Timing1  
4.0  
4.5  
7.4  
8.3  
9.4  
11.0  
12.0  
11.0  
12.0  
17.0  
0.03  
0.07  
0.05  
0.07  
14.3  
15.6  
14.3  
15.6  
22.1  
8.0  
9.0  
10.2  
9.4  
7.4  
8.3  
9.5  
9.5  
10.5  
15.3  
0.03  
0.06  
0.04  
0.06  
12.8  
0.02  
0.05  
0.04  
0.05  
12.8  
0.02  
0.05  
0.04  
0.05  
0.04 ns/pF  
0.09 ns/pF  
0.07 ns/pF  
0.09 ns/pF  
tDHS  
tDLS  
Data to Pad, High Slew  
Data to Pad, Low Slew  
6.2  
11.7  
5.2  
7.0  
13.1  
5.9  
7.9  
14.9  
6.6  
9.3  
12.1  
22.8  
10.1  
17.3  
15.6  
14.3  
17.9  
25.1  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
17.5  
7.8  
tENZHS Enable to Pad, Z to H/L, High Slew  
tENZLS Enable to Pad, Z to H/L, Low Slew  
tENHSZ Enable to Pad, H/L to Z, High Slew  
tENLSZ Enable to Pad, H/L to Z, Low Slew  
tCKHS IOCLK Pad to Pad H/L, High Slew  
tCKLS IOCLK Pad to Pad H/L, Low Slew  
dTLHHS Delta Low to High, High Slew  
dTLHLS Delta Low to High, Low Slew  
dTHLHS Delta High to Low, High Slew  
dTHLLS Delta High to Low, Low Slew  
8.9  
10.0  
9.0  
11.3  
10.0  
9.4  
13.3  
12.0  
11.0  
13.8  
19.3  
0.06  
0.11  
0.04  
0.05  
8.0  
7.4  
8.3  
10.4  
14.5  
0.04  
0.07  
0.03  
0.04  
10.4  
14.5  
0.04  
0.08  
0.03  
0.04  
12.4  
17.4  
0.05  
0.09  
0.03  
0.04  
0.08 ns/pF  
0.14 ns/pF  
0.05 ns/pF  
0.07 ns/pF  
Notes: *  
1. Delays based on 35 pF loading.  
2. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
2-40  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
A14100A, A14V100A Timing Characteristics (continued)  
Table 2-37 • A14100A, A14V100A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C  
Units  
Dedicated (hardwired) I/O Clock Network  
Parameter/Description  
–3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tIOCKH  
Input Low to High (pad to I/O module  
input)  
2.3  
2.6  
3.0  
3.5  
4.5  
ns  
tIOPWH  
tIPOWL  
Minimum Pulse Width High  
Minimum Pulse Width Low  
2.4  
2.4  
2.4  
3.3  
3.3  
3.3  
3.8  
3.8  
3.8  
4.8  
4.8  
4.8  
6.5  
6.5  
6.5  
ns  
ns  
tIOSAPW Minimum Asynchronous Pulse Width  
tIOCKSW Maximum Skew  
ns  
0.6  
0.6  
0.7  
0.8  
0.6  
75  
ns  
tIOP  
Minimum Period  
5.0  
6.8  
8.0  
10.0  
13.4  
ns  
fIOMAX  
Maximum Frequency  
200  
150  
125  
100  
MHz  
Dedicated (hardwired) Array Clock  
tHCKH  
Input Low to High (pad to S-module  
input)  
3.7  
3.7  
4.1  
4.1  
4.7  
4.7  
5.5  
5.5  
7.0  
7.0  
ns  
ns  
tHCKL  
Input High to Low (pad to S-module  
input)  
tHPWH  
tHPWL  
Minimum Pulse Width High  
Minimum Pulse Width Low  
2.4  
2.4  
3.3  
3.3  
3.8  
3.8  
4.8  
4.8  
6.5  
6.5  
ns  
ns  
tHCKSW Delta High to Low, Low Slew  
0.6  
0.6  
0.7  
0.8  
0.6  
75  
ns  
tHP  
Minimum Period  
5.0  
6.8  
8.0  
10.0  
13.4  
ns  
fHMAX  
Maximum Frequency  
200  
150  
125  
100  
MHz  
Routed Array Clock Networks  
tRCKH  
tRCKL  
tRPWH  
tRPWL  
Input Low to High (FO = 64)  
Input High to Low (FO = 64)  
Min. Pulse Width High (FO = 64)  
Min. Pulse Width Low (FO = 64)  
6.0  
6.0  
6.8  
6.8  
7.7  
7.7  
9.0  
9.0  
11.8  
11.8  
ns  
ns  
4.1  
4.1  
4.5  
4.5  
5.4  
5.4  
6.1  
6.1  
8.2  
8.2  
ns  
ns  
tRCKSW Maximum Skew (FO = 128)  
1.2  
1.4  
1.6  
90  
1.8  
80  
1.8  
60  
ns  
tRP  
Minimum Period (FO = 64)  
8.3  
9.3  
11.1  
12.5  
16.7  
0.0  
ns  
fRMAX  
Maximum Frequency (FO = 64)  
120  
105  
MHz  
Clock-to-Clock Skews  
tIOHCKSW I/O Clock to H-Clock Skew  
0.0 2.6 0.0 2.7 0.0 2.9 0.0 3.0  
3.0  
ns  
ns  
tIORCKSW I/O Clock to R-Clock Skew (FO = 64) 0.0 1.7 0.0 1.7 0.0 1.7 0.0 1.7  
0.0  
0.0  
5.0  
5.0  
(FO = 350)  
0.0 5.0 0.0 5.0 0.0 5.0 0.0 5.0  
tHRCKSW H-Clock to R-Clock Skew (FO = 64)  
(FO = 350)  
0.0 1.3 0.0 1.0 0.0 1.0 0.0 1.0  
0.0 3.0 0.0 3.0 0.0 3.0 0.0 3.0  
0.0  
0.0  
1.0  
3.0  
ns  
Notes: *  
1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at  
http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.  
2. Delays based on 35 pF loading.  
Revision 3  
2-41  
Detailed Specifications  
Pin Descriptions  
CLKA  
Clock A (Input)  
Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic modules.  
This pin can also be used as an I/O.  
CLKB  
Clock B (Input)  
Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic modules.  
This pin can also be used as an I/O.  
GND  
Ground  
LOW supply voltage.  
HCLK Dedicated (Hard-wired)  
Array Clock (Input)  
Clock input for sequential modules. This input is directly wired to each S-Module and offers clock speeds  
independent of the number of S-Modules being driven. This pin can also be used as an I/O.  
I/O  
Input/Output (Input, Output)  
The I/O pin functions as an input, output, three-state, or bidirectional buffer. Input and output levels are  
compatible with standard TTL and CMOS specifications. Unused I/O pins are tristated by the Designer  
Series software.  
IOCLK  
Dedicated (Hard-wired)  
I/O Clock (Input)  
Clock input for I/O modules. This input is directly wired to each I/O module and offers clock speeds  
independent of the number of I/O modules being driven. This pin can also be used as an I/O.  
IOPCL  
Dedicated (Hard-wired)  
I/O Preset/Clear (Input)  
Input for I/O preset or clear. This global input is directly wired to the preset and clear inputs of all I/O  
registers. This pin functions as an I/O when no I/O preset or clear macros are used.  
MODE  
Mode (Input)  
The MODE pin controls the use of diagnostic pins (DCLK, PRA, PRB, SDI). When the MODE pin is  
HIGH, the special functions are active. When the MODE pin is LOW, the pins function as I/Os. To provide  
Actionprobe capability, the MODE pin should be terminated to GND through a 10K resistor so that the  
MODE pin can be pulled high when required.  
NC  
No Connection  
This pin is not connected to circuitry within the device.  
PRA Probe A (Output)  
The Probe A pin is used to output data from any user-defined design node within the device. This  
independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic  
output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when  
debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect  
programmed design confidentiality. PRA is accessible when the MODE pin is HIGH. This pin functions as  
an I/O when the MODE pin is LOW.  
PRB  
Probe B (Output)  
The Probe B pin is used to output data from any user-defined design node within the device. This  
independent diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic  
output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when  
debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect  
programmed design confidentiality. PRB is accessible when the MODE pin is HIGH. This pin functions as  
an I/O when the MODE pin is LOW.  
SDI  
Serial Data Input (Input)  
Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is  
HIGH. This pin functions as an I/O when the MODE pin is LOW.  
2-42  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
SDO  
Serial Data Output (Output)  
Serial data output for diagnostic probe. SDO is active when the MODE pin is High. This pin functions as  
an I/O when the MODE pin is Low.  
DCLK  
Diagnostic Clock (Input)  
Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH.  
This pin functions as an I/O when the MODE pin is LOW.  
VCC  
5 V Supply Voltage  
HIGH supply voltage.  
Revision 3  
2-43  
3 – Package Pin Assignments  
PL84  
11 10  
9
8
7
6
5
4
3
2
1
84 83 82 81 80 79 78 77 76 75  
12  
74  
13  
14  
73  
72  
15  
16  
17  
18  
71  
70  
69  
68  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
84-Pin  
PLCC  
29  
30  
31  
32  
57  
56  
55  
54  
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  
Note: This is the top view of the package.  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.  
Revision 3  
3-1  
Package Pin Assignments  
PL84  
Pin Number  
A1415, A14V15 Function  
A1425, A14V25 Function  
VCC  
A1440, A14V40 Function  
VCC  
1
VCC  
GND  
2
GND  
GND  
3
VCC  
VCC  
VCC  
4
PRA, I/O  
DCLK, I/O  
SDI, I/O  
MODE  
GND  
PRA, I/O  
DCLK, I/O  
SDI, I/O  
MODE  
PRA, I/O  
DCLK, I/O  
SDI, I/O  
MODE  
11  
12  
16  
27  
28  
40  
41  
42  
43  
45  
52  
53  
59  
60  
61  
68  
69  
74  
83  
84  
GND  
GND  
VCC  
VCC  
VCC  
PRB, I/O  
VCC  
PRB, I/O  
VCC  
PRB, I/O  
VCC  
GND  
GND  
GND  
VCC  
VCC  
VCC  
HCLK, I/O  
SDO  
HCLK, I/O  
SDO  
HCLK, I/O  
SDO  
IOPCL, I/O  
VCC  
IOPCL, I/O  
VCC  
IOPCL, I/O  
VCC  
VCC  
VCC  
VCC  
GND  
GND  
GND  
VCC  
VCC  
VCC  
GND  
GND  
GND  
IOCLK, I/O  
CLKA, I/O  
CLKB, I/O  
IOCLK, I/O  
CLKA, I/O  
CLKB, I/O  
IOCLK, I/O  
CLKA, I/O  
CLKB, I/O  
Notes:  
1. All unlisted pin numbers are user I/Os.  
2. NC denotes no connection.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be  
terminated directly to GND.  
3-2  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
PQ100  
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
100-Pin  
PQFP  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30  
Note: This is the top view of the package.  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx  
Revision 3  
3-3  
Package Pin Assignments  
PQ100  
A1415 Function  
IOCLK, I/O  
CLKA, I/O  
CLKB, I/O  
VCC  
Pin Number  
2
A1425 Function  
IOCLK, I/O  
CLKA, I/O  
CLKB, I/O  
VCC  
14  
15  
16  
17  
GND  
GND  
18  
VCC  
VCC  
19  
GND  
GND  
20  
PRA, I/O  
DCLK, I/O  
GND  
PRA, I/O  
DCLK, I/O  
GND  
27  
28  
29  
SDI, I/O  
MODE  
VCC  
SDI, I/O  
MODE  
VCC  
34  
35  
36  
GND  
GND  
47  
GND  
GND  
48  
VCC  
VCC  
61  
PRB, I/O  
GND  
PRB, I/O  
GND  
62  
63  
VCC  
VCC  
64  
GND  
GND  
65  
VCC  
VCC  
67  
HCLK, I/O  
SDO  
HCLK, I/O  
SDO  
77  
78  
IOPCL, I/O  
GND  
IOPCL, I/O  
GND  
79  
85  
VCC  
VCC  
86  
VCC  
VCC  
87  
GND  
GND  
96  
VCC  
VCC  
97  
GND  
GND  
Notes:  
1. All unlisted pin numbers are user I/Os.  
2. NC denotes no connection.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be  
terminated directly to GND.  
3-4  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
PQ160  
1
2
3
4
5
6
7
8
9
120  
119  
118  
117  
116  
115  
114  
113  
112  
111  
110  
109  
108  
107  
106  
105  
104  
103  
102  
101  
100  
99  
98  
97  
96  
95  
94  
93  
92  
91  
90  
89  
88  
87  
86  
85  
84  
83  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
160-Pin  
PQFP  
82  
81  
Note: This is the top view of the package  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx  
Revision 3  
3-5  
Package Pin Assignments  
PQ160  
Pin Number  
1
A1425, A14V25 Function  
A1440, A14V40 Function  
A1460, A14V60 Function  
GND  
SDI, I/O  
NC  
GND  
SDI, I/O  
I/O  
GND  
SDI, I/O  
I/O  
2
5
9
MODE  
VCC  
NC  
MODE  
VCC  
I/O  
MODE  
VCC  
I/O  
10  
14  
15  
18  
19  
20  
24  
27  
28  
29  
40  
41  
43  
45  
46  
47  
49  
51  
53  
58  
59  
60  
62  
63  
74  
75  
76  
77  
78  
79  
80  
81  
90  
91  
GND  
VCC  
GND  
NC  
GND  
VCC  
GND  
I/O  
GND  
VCC  
GND  
I/O  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
VCC  
VCC  
GND  
NC  
VCC  
VCC  
GND  
I/O  
VCC  
VCC  
GND  
I/O  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
VCC  
NC  
VCC  
I/O  
VCC  
I/O  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
PRB, I/O  
GND  
VCC  
HCLK, I/O  
GND  
NC  
PRB, I/O  
GND  
VCC  
HCLK, I/O  
GND  
I/O  
PRB, I/O  
GND  
VCC  
HCLK, I/O  
GND  
I/O  
VCC  
NC  
VCC  
I/O  
VCC  
I/O  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
SDO  
IOPCL, I/O  
GND  
VCC  
VCC  
SDO  
IOPCL, I/O  
GND  
VCC  
VCC  
SDO  
IOPCL, I/O  
GND  
VCC  
VCC  
3-6  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
PQ160  
Pin Number  
92  
A1425, A14V25 Function  
A1440, A14V40 Function  
A1460, A14V60 Function  
NC  
NC  
I/O  
I/O  
I/O  
I/O  
93  
98  
GND  
VCC  
NC  
GND  
VCC  
I/O  
GND  
VCC  
I/O  
99  
100  
103  
107  
109  
110  
111  
GND  
NC  
GND  
I/O  
GND  
I/O  
NC  
I/O  
I/O  
VCC  
GND  
VCC  
NC  
VCC  
GND  
VCC  
I/O  
VCC  
GND  
VCC  
I/O  
112  
113  
119  
120  
121  
124  
127  
136  
137  
138  
139  
140  
141  
142  
143  
145  
147  
149  
151  
153  
154  
160  
NC  
I/O  
I/O  
IOCLK, I/O  
GND  
NC  
IOCLK, I/O  
GND  
I/O  
IOCLK, I/O  
GND  
I/O  
NC  
I/O  
I/O  
CLKA, I/O  
CLKB, I/O  
VCC  
GND  
VCC  
GND  
PRA, I/O  
NC  
CLKA, I/O  
CLKB, I/O  
VCC  
GND  
VCC  
GND  
PRA, I/O  
I/O  
CLKA, I/O  
CLKB, I/O  
VCC  
GND  
VCC  
GND  
PRA, I/O  
I/O  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
NC  
I/O  
I/O  
VCC  
DCLK, I/O  
VCC  
DCLK, I/O  
VCC  
DCLK, I/O  
Notes:  
1. All unlisted pin numbers are user I/Os.  
2. NC denotes no connection.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be  
terminated directly to GND.  
Revision 3  
3-7  
Package Pin Assignments  
PQ208, RQ208  
1
2
3
4
5
6
7
8
9
156  
155  
154  
153  
152  
151  
150  
149  
148  
147  
146  
145  
144  
143  
142  
141  
140  
139  
138  
137  
136  
135  
134  
133  
132  
131  
130  
129  
128  
127  
126  
125  
124  
123  
122  
121  
120  
119  
118  
117  
116  
115  
114  
113  
112  
111  
110  
109  
108  
107  
106  
105  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
208-Pin  
PQFP, RQFP  
Note: This is the top view of the package  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx  
3-8  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
PQ208, RQ208  
PQ208, RQ208  
A1460, A14V60  
Function  
A14100, A14V100  
Function  
A1460, A14V60  
Function  
A14100, A14V100  
Function  
Pin Number  
Pin Number  
115  
1
2
GND  
SDI, I/O  
MODE  
VCC  
GND  
SDI, I/O  
MODE  
VCC  
VCC  
NC  
VCC  
I/O  
116  
11  
129  
130  
131  
132  
145  
146  
147  
148  
156  
157  
158  
164  
180  
181  
182  
183  
184  
185  
186  
195  
201  
205  
208  
GND  
GND  
12  
25  
26  
27  
28  
40  
41  
52  
53  
60  
65  
76  
77  
78  
79  
80  
82  
98  
102  
103  
104  
105  
114  
VCC  
VCC  
VCC  
VCC  
GND  
GND  
GND  
GND  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
GND  
GND  
GND  
GND  
VCC  
VCC  
NC  
I/O  
VCC  
VCC  
VCC  
VCC  
GND  
GND  
IOCLK, I/O  
GND  
IOCLK, I/O  
GND  
NC  
I/O  
VCC  
VCC  
NC  
I/O  
NC  
I/O  
VCC  
VCC  
PRB, I/O  
GND  
PRB, I/O  
GND  
CLKA, I/O  
CLKB, I/O  
VCC  
CLKA, I/O  
CLKB, I/O  
VCC  
VCC  
VCC  
GND  
GND  
GND  
GND  
VCC  
VCC  
VCC  
VCC  
HCLK, I/O  
VCC  
HCLK, I/O  
VCC  
GND  
GND  
PRA, I/O  
NC  
PRA, I/O  
I/O  
NC  
I/O  
SDO  
SDO  
VCC  
VCC  
IOPCL, I/O  
GND  
IOPCL, I/O  
GND  
NC  
I/O  
DCLK, I/O  
DCLK, I/O  
VCC  
VCC  
Notes:  
1. All unlisted pin numbers are user I/Os.  
2. NC denotes no connection.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be  
terminated directly to GND.  
Revision 3  
3-9  
Package Pin Assignments  
TQ176  
1
2
3
4
5
6
7
8
9
132  
131  
130  
129  
128  
127  
126  
125  
124  
123  
122  
121  
120  
119  
118  
117  
116  
115  
114  
113  
112  
111  
110  
109  
108  
107  
106  
105  
104  
103  
102  
101  
100  
99  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
176-Pin  
TQFP  
98  
97  
96  
95  
94  
93  
92  
91  
90  
89  
Note: This is the top view.  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx  
3-10  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
TQ176  
TQ176  
A1440, A14V40  
Function  
A1460, A14V60  
Function  
A1440, A14V40  
Function  
A1460, A14V60  
Function  
Pin Number  
Pin Number  
89  
1
GND  
SDI, I/O  
MODE  
VCC  
GND  
SDI, I/O  
MODE  
VCC  
GND  
VCC  
GND  
VCC  
2
98  
10  
11  
20  
21  
22  
23  
32  
33  
44  
49  
51  
63  
64  
65  
66  
67  
69  
82  
83  
87  
88  
99  
VCC  
VCC  
108  
109  
110  
GND  
GND  
NC  
I/O  
VCC  
VCC  
GND  
VCC  
GND  
VCC  
GND  
GND  
119  
NC  
I/O  
GND  
VCC  
GND  
VCC  
121  
122  
123  
124  
132  
133  
138  
152  
153  
154  
155  
156  
157  
158  
170  
176  
NC  
I/O  
VCC  
VCC  
VCC  
VCC  
GND  
GND  
GND  
NC  
GND  
I/O  
VCC  
VCC  
IOCLK, I/O  
GND  
IOCLK, I/O  
GND  
NC  
I/O  
NC  
I/O  
NC  
I/O  
PRB, I/O  
GND  
VCC  
PRB, I/O  
GND  
VCC  
CLKA, I/O  
CLKB, I/O  
VCC  
CLKA, I/O  
CLKB, I/O  
VCC  
VCC  
VCC  
GND  
GND  
HCLK, I/O  
NC  
HCLK, I/O  
I/O  
VCC  
VCC  
PRA, I/O  
NC  
PRA, I/O  
I/O  
NC  
I/O  
SDO  
SDO  
NC  
I/O  
IOPCL, I/O  
IOPCL, I/O  
DCLK, I/O  
DCLK, I/O  
Notes:  
1. All unlisted pin numbers are user I/Os.  
2. NC denotes no connection.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be  
terminated directly to GND.  
Revision 3  
3-11  
Package Pin Assignments  
VQ100  
1
75  
2
3
74  
73  
4
5
6
7
72  
71  
70  
69  
8
9
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
10  
11  
12  
13  
14  
15  
16  
17  
100-Pin  
VQFP  
18  
19  
20  
21  
58  
57  
56  
55  
22  
23  
24  
25  
54  
53  
52  
51  
Note: This is the top view.  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx  
3-12  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
VQ100  
A1425, A14V25 Function  
Pin Number  
A1415, A14V15 Function  
GND  
A1440, A14V40 Function  
GND  
1
2
GND  
SDI, I/O  
MODE  
VCC  
SDI, I/O  
MODE  
VCC  
SDI, I/O  
MODE  
VCC  
7
8
9
GND  
GND  
GND  
20  
21  
34  
35  
36  
37  
39  
49  
50  
51  
57  
58  
67  
68  
69  
74  
75  
87  
88  
89  
90  
91  
92  
93  
100  
VCC  
VCC  
VCC  
NC  
I/O  
I/O  
PRB, I/O  
VCC  
PRB, I/O  
VCC  
PRB, I/O  
VCC  
GND  
GND  
GND  
VCC  
VCC  
VCC  
HCLK, I/O  
SDO  
HCLK, I/O  
SDO  
HCLK, I/O  
SDO  
IOPCL, I/O  
GND  
IOPCL, I/O  
GND  
IOPCL, I/O  
GND  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
GND  
GND  
GND  
GND  
GND  
GND  
NC  
I/O  
I/O  
IOCLK, I/O  
CLKA, I/O  
CLKB, I/O  
VCC  
IOCLK, I/O  
CLKA, I/O  
CLKB, I/O  
VCC  
IOCLK, I/O  
CLKA, I/O  
CLKB, I/O  
VCC  
VCC  
VCC  
VCC  
GND  
GND  
GND  
PRA, I/O  
NC  
PRA, I/O  
I/O  
PRA, I/O  
I/O  
DCLK, I/O  
DCLK, I/O  
DCLK, I/O  
Notes:  
1. All unlisted pin numbers are user I/Os.  
2. NC denotes no connection.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be  
terminated directly to GND.  
Revision 3  
3-13  
Package Pin Assignments  
CQ132  
132 131 130 129 128 127 126 125 124  
107 106 105 104 103 102 101 100  
Pin #1  
Index  
1
2
3
4
5
6
7
8
99  
98  
97  
96  
95  
94  
93  
92  
132-Pin  
CQFP  
25  
26  
27  
28  
29  
30  
31  
32  
33  
75  
74  
73  
72  
71  
70  
69  
68  
67  
34 35 36 37 38 39 40 41 42  
59 60 61 62 63 64 65 66  
Note: This is the top view  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx  
3-14  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
CQ132  
CQ132  
Pin Number  
A1425 Function  
NC  
Pin Number  
A1425 Function  
NC  
1
67  
74  
2
GND  
GND  
3
SDI, I/O  
MODE  
GND  
75  
VCC  
9
78  
VCC  
10  
11  
22  
26  
27  
34  
36  
42  
43  
48  
50  
58  
59  
63  
64  
65  
66  
89  
VCC  
VCC  
90  
GND  
VCC  
91  
VCC  
GND  
92  
GND  
VCC  
98  
IOCLK, I/O  
NC  
NC  
99  
GND  
100  
101  
106  
107  
116  
117  
118  
122  
123  
131  
132  
NC  
GND  
GND  
VCC  
GND  
PRB, I/O  
HCLK, I/O  
GND  
VCC  
CLKA, I/O  
CLKB, I/O  
PRA, I/O  
GND  
VCC  
SDO  
IOPCL, I/O  
GND  
VCC  
DCLK, I/O  
NC  
NC  
Notes:  
1. All unlisted pin numbers are user I/Os.  
2. NC denotes no connection.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be  
terminated directly to GND.  
Revision 3  
3-15  
Package Pin Assignments  
CQ196  
196 195 194 193 192 191 190 189 188  
155 154 153 152 151 150 149 148  
Pin #1  
Index  
1
2
3
4
5
6
7
8
147  
146  
145  
144  
143  
142  
141  
140  
196-Pin  
CQFP  
41  
42  
43  
44  
45  
46  
47  
48  
49  
107  
106  
105  
104  
103  
102  
101  
100  
99  
50 51 52 53 54 55 56 57 58  
91 92 93 94 95 96 97 98  
Note: This is the top view.  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx  
3-16  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
CQ196  
CQ196  
Pin Number  
A1460 Function  
GND  
Pin Number  
A1460 Function  
GND  
1
2
101  
110  
111  
112  
137  
138  
139  
140  
148  
149  
155  
162  
172  
173  
174  
183  
189  
193  
196  
SDI, I/O  
MODE  
VCC  
VCC  
11  
12  
13  
37  
38  
39  
51  
52  
59  
64  
77  
79  
86  
94  
98  
99  
100  
VCC  
GND  
GND  
VCC  
GND  
GND  
VCC  
GND  
VCC  
VCC  
GND  
IOCLK, I/O  
GND  
GND  
VCC  
VCC  
GND  
GND  
HCLK, I/O  
PRB, I/O  
GND  
CLKA, I/O  
CLKB, I/O  
PRA, I/O  
GND  
VCC  
GND  
VCC  
SDO  
GND  
IOPCL, I/O  
DCLK, I/O  
Notes:  
1. All unlisted pin numbers are user I/Os.  
2. NC denotes no connection.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be  
terminated directly to GND.  
Revision 3  
3-17  
Package Pin Assignments  
CQ256  
256 255 254 253 252 251 250 249 248  
200 199 198 197 196 195 194 193  
Pin #1  
Index  
1
2
3
4
5
6
7
8
192  
191  
190  
189  
188  
187  
186  
185  
256-Pin  
CQFP  
56  
57  
58  
59  
60  
61  
62  
63  
64  
137  
136  
135  
134  
133  
132  
131  
130  
129  
65 66 67 68 69 70 71 72 73  
121 122 123 124 125 126 127 128  
Note: This is the top view.  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx  
3-18  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
CQ256  
A14100 Function  
CQ256  
Pin Number  
Pin Number  
A14100 Function  
VCC  
1
2
GND  
SDI, I/O  
MODE  
VCC  
141  
158  
159  
160  
161  
174  
175  
176  
188  
189  
219  
220  
221  
222  
223  
224  
225  
240  
256  
GND  
11  
VCC  
28  
29  
30  
31  
46  
59  
90  
91  
92  
93  
94  
96  
110  
126  
127  
128  
GND  
GND  
VCC  
VCC  
VCC  
GND  
GND  
VCC  
GND  
GND  
IOCLK, I/O  
GND  
PRB, I/O  
GND  
CLKA, I/O  
CLKB, I/O  
VCC  
VCC  
GND  
VCC  
GND  
HCLK, I/O  
GND  
VCC  
GND  
SDO  
PRA, I/O  
GND  
IOPCL, I/O  
GND  
DCLK, I/O  
Notes:  
1. All unlisted pin numbers are user I/Os.  
2. NC denotes no connection.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be  
terminated directly to GND.  
Revision 3  
3-19  
Package Pin Assignments  
BG225  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
A
A
B
C
D
E
F
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
M
N
P
R
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
Note: This is the top view.  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx  
3-20  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
BG225  
A1460 Function  
CLKA or I/O  
CLKB or I/O  
DCLK or I/O  
GND  
Location  
C8  
B8  
B2  
A1, A15, D15, F8, G7, G8, G9, H6, H7, H8, H9, H10, J7, J8, J9, K8, P2, R15  
HCLK or I/O  
IOCLK or I/O  
IOPCL or I/O  
MODE  
P9  
B14  
P14  
D1  
NC  
A11, B5, B7, D8, D12, F6, F11, H1, H12, H14, K11, L1, L13, N8, P5, R1, R8, R11, R14  
PRA or I/O  
PRB or I/O  
SDI or I/O  
SDO  
A7  
L7  
D4  
N13  
VCC  
A8, B12, D5, D14, E3, E8, E13, H2, H3, H11, H15, K4, L2, L12, M8, M15, P4, P8, R13  
Notes:  
1. All unlisted pin numbers are user I/Os.  
2. NC denotes no connection.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be  
terminated directly to GND.  
4. The BG225 package has been discontinued.  
Revision 3  
3-21  
Package Pin Assignments  
BG313  
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25  
A
B
C
D
E
F
A
B
C
D
E
F
G
G
H
J
H
J
K
L
K
L
M
N
P
R
M
N
P
R
T
T
U
U
V
V
W
W
Y
Y
AA  
AA  
AB  
AC  
AB  
AC  
AD  
AE  
AD  
AE  
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25  
Note: This is the top view.  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx  
3-22  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
BG313  
A14100, A14V100  
Function  
Location  
J13  
CLKA or I/O  
CLKB or I/O  
DCLK or I/O  
GND  
G13  
B2  
A1, A25, AD2, AE25, J21, L13, M12, M14, N11, N13, N15, P12, P14, R13  
HCLK or I/O  
IOCLK or I/O  
IOPCL or I/O  
MODE  
T14  
B24  
AD24  
G3  
NC  
A3, A13, A23, AA5, AA9, AA23, AB2, AB4, AB20, AC13, AC25, AD22, AE1, AE21, B14, C5,  
C25, D4, D24, E3, E21, F6, F10, F16, G1, G25, H18, H24, J1, J7, J25, K12, L15, L17, M6, N1,  
N5, N7, N21, N23, P20, R11, T6, T8, U9, U13, U21, V16, W7, Y20, Y24  
PRA or I/O  
PRB or I/O  
SDI or I/O  
SDO  
H12  
AD12  
C1  
AE23  
VCC  
AB18, AD6, AE13, C13, C19, E13, G9, H22, K8, K20, M16, N3, N9, N25, U5, W13, V2, V22,  
V24  
Notes:  
1. All unlisted pin numbers are user I/Os.  
2. NC denotes no connection.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be  
terminated directly to GND.  
Revision 3  
3-23  
Package Pin Assignments  
PG100  
1
2
3
4
5
6
7
8
9
10 11  
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
100-Pin  
CPGA  
G
H
J
K
L
K
L
1
2
3
4
5
6
7
8
9
10 11  
Orientation Pin  
Note: This is the top view.  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx  
3-24  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
PG100  
A1415 Function  
CLKA or I/O  
CLKB or I/O  
DCLK or I/O  
GND  
Location  
C7  
D6  
C4  
C3, C6, C9, E9, F3, F9, J3, J6, J8, J9  
HCLK or I/O  
IOCLK or I/O  
IOPCL or I/O  
MODE  
H6  
C10  
K9  
C2  
PRA or I/O  
PRB or I/O  
SDI or I/O  
SDO  
A6  
L3  
B3  
L9  
VCC  
B6, B10, E11, F2, F10, G2, K2, K6, K10  
Notes:  
1. All unlisted pin numbers are user I/Os.  
2. NC denotes no connection.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be  
terminated directly to GND.  
4. The PG100 package has been discontinued.  
Revision 3  
3-25  
Package Pin Assignments  
PG133  
1
2
3
4
5
6
7
8
9
10 11 12 13  
A
B
C
D
E
F
A
B
C
D
E
F
133-Pin  
CPGA  
G
H
J
G
H
J
K
L
K
L
M
N
M
N
1
2
3
4
5
6
7
8
9
10 11 12 13  
Note: This is the top view.  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx  
3-26  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
PG133  
A1425 Function  
CLKA or I/O  
CLKB or I/O  
DCLK or I/O  
GND  
Location  
D7  
B6  
D4  
A2, C3, C7, C11, C12, F10, G3, G11, L3, L7, L11, M3, N12  
HCLK or I/O  
IOCLK or I/O  
IOPCL or I/O  
MODE  
K7  
C10  
L10  
E3  
NC  
A1, A7, A13, G1, G13, N1, N7, N13  
PRA or I/O  
PRB or I/O  
SDI or I/O  
SDO  
A6  
L6  
C2  
M11  
VCC  
B2, B7, B12, E11, G2, G12, J2, J12, M2, M7, M12  
Notes:  
1. All unlisted pin numbers are user I/Os.  
2. NC denotes no connection.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be  
terminated directly to GND.  
4. The PG133 package has been discontinued.  
Revision 3  
3-27  
Package Pin Assignments  
PG175  
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
175-Pin  
CPGA  
8
9
10  
11  
12  
13  
14  
15  
10  
11  
12  
13  
14  
15  
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Note: This is the top view.  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx  
3-28  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
PG175  
A1440 Function  
CLKA or I/O  
CLKB or I/O  
DCLK or I/O  
GND  
Location  
C9  
A9  
D5  
D4, D8, D11, D12, E4, E14, H4, H12, L4, L12, M4, M8, M12  
HCLK or I/O  
IOCLK or I/O  
IOPCL or I/O  
MODE  
R8  
E12  
P13  
F3  
NC  
A1, A2, A15, B2, B3, P2, P14, R1, R2, R14, R15  
PRA or I/O  
PRB or I/O  
SDI or I/O  
SDO  
B8  
R7  
D3  
N12  
VCC  
C3, C8, C13, E15, H3, H13, L1, L14, N3, N8, N13  
Notes:  
1. All unlisted pin numbers are user I/Os.  
2. NC denotes no connection.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be  
terminated directly to GND.  
4. The PG175 package has been discontinued.  
Revision 3  
3-29  
Package Pin Assignments  
PG207  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
207-Pin  
CPGA  
K
L
K
L
M
N
P
R
S
T
M
N
P
R
S
T
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
Note: This is the top view.  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx  
3-30  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
PG207  
A1460 Function  
CLKA or I/O  
CLKB or I/O  
DCLK or I/O  
GND  
Location  
K1  
J3  
E4  
C14, D4, D5, D9, D14, J4, J14, P3, P4, P7, P9, P14, R15  
HCLK or I/O  
IOCLK or I/O  
IOPCL or I/O  
MODE  
J15  
P5  
N14  
D7  
NC  
A1, A2, A16, A17, B1, B17, C1, C2, S1, S3, S17, T1, T2, T16, T17  
PRA or I/O  
PRB or I/O  
SDI or I/O  
SDO  
H1  
K16  
C3  
P15  
VCC  
B2, B9, B16, D11, J2, J16, P12, S2, S9, S16, T5  
Notes:  
1. All unlisted pin numbers are user I/Os.  
2. NC denotes no connection.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be  
terminated directly to GND.  
Revision 3  
3-31  
Package Pin Assignments  
PG257  
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19  
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
257-Pin  
CPGA  
K
L
K
L
M
N
P
R
T
M
N
P
R
T
V
X
Y
V
X
Y
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19  
Note: This is the top view.  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx  
3-32  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
PG257  
A14100 Function  
CLKA or I/O  
CLKB or I/O  
DCLK or I/O  
GND  
Location  
L4  
L5  
E4  
B16, C4, D4, D10, D16, E11, J5, K4, K16, L15, R4, T4, T10, T16, T17, X7  
HCLK or I/O  
IOCLK or I/O  
IOPCL or I/O  
MODE  
J16  
T5  
R16  
A5  
NC  
E5  
PRA or I/O  
PRB or I/O  
SDI or I/O  
SDO  
J1  
J17  
B4  
R17  
VCC  
C3, C10, C13, C17, K3, K17, V3, V7, V10, V17, X14  
Notes:  
1. All unlisted pin numbers are user I/Os.  
2. NC denotes no connection.  
3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be  
terminated directly to GND.  
Revision 3  
3-33  
4 – Datasheet Information  
List of Changes  
The following table lists critical changes that were made in each version of the datasheet.  
Revision  
Changes  
Page  
Revision 3  
(January 2012)  
The description for SDO pins had earlier been removed from the datasheet and has  
now been included again, in the "Pin Descriptions" section (SAR 35820).  
2-21  
SDO pin numbers had earlier been removed from package pin assignment tables in  
the datasheet, and have now been restored to the pin tables (SAR 35820).  
3-1  
Revision 2  
The ACT 3 datasheet was formatted newly in the style used for current datasheets.  
N/A  
(September 2011) The same information is present (other than noted in the list of changes for this  
revision) but divided into chapters.  
The datasheet was revised to note in multiple places that speed grades –2 and –3 I and  
have been discontinued. The following device/package combinations have been others  
discontinued for all speed grades and temperatures (SAR 33872):  
A1415 PG100  
A1425 PG133  
A1440 PG175  
A1460 BG225  
Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004.  
The "Features" section was revised to state the clock-to-ouput time and on-chip  
performance for –1 speed grade as 9.0 ns and 186 MHz. The "General Description"  
section was revised in accordance (SAR 33872).  
I
I
The maximum performance values were updated in Table 1 • ACT 3 Family Product  
Information, and now reflect worst-case commercial for the –1 speed grade (SAR  
33872).  
The "Product Plan" table was updated as follows to conform to current offerings (SAR  
33872):  
III  
The A1415A device is offered in PL84, PG100, and VQ100 packages for Military  
application.  
The A1440A device is offered in TQ176 and VQ100 packages for Industrial  
application.  
Table 1-1 • Chip-to-Chip Performance (worst-case commercial) was updated to  
include data for all speed grades instead of only –3 (SAR 33872).  
1-2  
1-1  
Figure 1-1 • Predictable Performance (worst-case commercial, –1 speed grade) was  
revised to reflect values for the –1 speed grade (SAR 33872).  
Figure 2-10 • Timing Model was updated to show data for the –1 speed grade instead  
of –3 (SAR 33872).  
2-16  
2-20  
Table 2-14 • Logic Module and Routing Delay by Fanout (ns); Worst-Case Commercial  
Conditions was updated to include data for all speed grades instead of only –3 (SAR  
33872).  
Package names used in the "Package Pin Assignments" section and throughout the  
document were revised to match standards given in Package Mechanical Drawings  
(SAR 27395).  
3-1  
Revision 3  
4-1  
Datasheet Information  
Revision  
Changes  
Page  
Revision 2  
(continued)  
In the "Package Pin Assignments" section, notes were added to the pin tables for the  
following packages, stating that they are discontinued:  
3-20  
3-24  
3-26  
3-28  
"BG225"  
"PG100"  
"PG133"  
"PG175"  
Revision 1  
RoHS compliant information was added to the "Ordering Information" section.  
II  
(June 2006)  
4-2  
Revision 3  
Accelerator Series FPGAs – ACT 3 Family  
Datasheet Categories  
Categories  
In order to provide the latest information to designers, some datasheet parameters are published before  
data has been fully characterized from silicon devices. The data provided for a given device is  
designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these  
categories are as follows:  
Product Brief  
The product brief is a summarized version of a datasheet (advance or production) and contains general  
product information. This document gives an overview of specific device and family information.  
Advance  
This version contains initial estimated information based on simulation, other products, devices, or speed  
grades. This information can be used as estimates, but not for production. This label only applies to the  
DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not  
been fully characterized.  
Preliminary  
The datasheet contains information based on simulation and/or initial characterization. The information is  
believed to be correct, but changes are possible.  
Production  
This version contains information that is considered to be final.  
Export Administration Regulations (EAR)  
The products described in this document are subject to the Export Administration Regulations (EAR).  
They could require an approved export license prior to export from the United States. An export includes  
release of product or disclosure of technology to a foreign national inside or outside the United States.  
Safety Critical, Life Support, and High-Reliability Applications  
Policy  
The products described in this advance status document may not have completed the Microsemi  
qualification process. Products may be amended or enhanced during the product introduction and  
qualification process, resulting in changes in device functionality or performance. It is the responsibility of  
each customer to ensure the fitness of any product (but especially a new product) for a particular  
purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications.  
Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating  
to life-support applications. A reliability report covering all of the SoC Products Group’s products is  
available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety  
of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for  
additional reliability information.  
Revision 3  
4-3  
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor  
solutions for: aerospace, defense and security; enterprise and communications; and industrial  
and alternative energy markets. Products include high-performance, high-reliability analog and  
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and  
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at  
www.microsemi.com.  
Microsemi Corporate Headquarters  
One Enterprise, Aliso Viejo CA 92656 USA  
Within the USA: +1 (949) 380-6100  
Sales: +1 (949) 380-6136  
© 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of  
Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.  
Fax: +1 (949) 215-4996  
5172106-3/1.12  

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