A2F060M3G-1TQ208YI_技术文档

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

–

Programmable Embedded FIFO Control Logic

Microcontroller Subsystem (MSS)

•

Secure ISP with 128-Bit AES via JTAG

FlashLock^®to Secure FPGA Contents

Five Clock Conditioning Circuits (CCCs) with up to 2

Integrated Analog PLLs

–

•

Hard 100 MHz 32-Bit ARM^®Cortex™-M3

–

1.25 DMIPS/MHz Throughput from Zero Wait State

Memory

–

Memory Protection Unit (MPU)

Phase Shift, Multiply/Divide, and Delay Capabilities

Frequency: Input 1.5–350 MHz, Output 0.75 to

350 MHz

Single Cycle Multiplication, Hardware Divide

JTAG Debug (4 wires), Serial Wire Debug (SWD, 2

wires), and Single Wire Viewer (SWV) Interfaces

•

Internal Memory

Programmable Analog

–

Embedded Nonvolatile Flash Memory (eNVM), 128

Kbytes to 512 Kbytes

Analog Front-End (AFE)

•

Up to Three 12-Bit SAR ADCs

–

Embedded High-Speed SRAM (eSRAM), 16 Kbytes

to 64 Kbytes, Implemented in 2 Physical Blocks to

–

500 Ksps in 12-Bit Mode

550 Ksps in 10-Bit Mode

600 Ksps in 8-Bit Mode

Enable Simultaneous Access from

Masters

2 Different

•

Multi-Layer AHB Communications Matrix

•

Internal 2.56

Reference

V

Reference or Optional External

–

Provides up to 16 Gbps of On-Chip Memory

Bandwidth,¹Allowing Multi-Master Schemes

One First-Order  DAC (sigma-delta) per ADC

8-Bit, 16-Bit, or 24-Bit 500 Ksps Update Rate

•

10/100 Ethernet MAC with RMII Interface²

Programmable External Memory Controller, Which

Supports:

–

Up to 5 High-Performance Analog Signal Conditioning

Blocks (SCB) per Device, Each Including:

–

Asynchronous Memories

NOR Flash, SRAM, PSRAM

Synchronous SRAMs

–

Two High-Voltage Bipolar Voltage Monitors (with 4

input ranges from ±2.5 V to –11.5/+14 V) with 1%

Accuracy

High Gain Current Monitor, Differential Gain = 50, up

to 14 V Common Mode

•

Two I²C Peripherals

–

Two 16550 Compatible UARTs

Two SPI Peripherals

Two 32-Bit Timers

32-Bit Watchdog Timer

8-Channel DMA Controller to Offload the Cortex-M3

from Data Transactions

Clock Sources

–

Temperature Monitor (Resolution = ¼°C in 12-Bit

Mode; Accurate from –55°C to 150°C)

•

Up to Ten High-Speed Voltage Comparators

(t_pd= 15 ns)

Analog Compute Engine (ACE)

•

Offloads Cortex-M3–Based MSS from Analog

Initialization and Processing of ADC, DAC, and SCBs

Sample Sequence Engine for ADC and DAC Parameter

Set-Up

•

32 KHz to 20 MHz Main Oscillator

Battery-Backed 32 KHz Low Power Oscillator with

Real-Time Counter (RTC)

100 MHz Embedded RC Oscillator; 1% Accurate

Embedded Analog PLL with 4 Output Phases (0, 90,

180, 270)

Post-Processing Engine for Functions such as Low-

Pass Filtering and Linear Transformation

Easily Configured via GUI in Libero^®System-on-Chip

(SoC) Software

–

High-Performance FPGA

I/Os and Operating Voltage

•

Based on proven ProASIC^®3 FPGA Fabric

Low Power, Firm-Error Immune 130-nm, 7-Layer Metal,

Flash-Based CMOS Process

•

FPGA I/Os

–

LVDS, PCI, PCI-X, up to 24 mA IOH/IOL

Up to 350 MHz

•

Nonvolatile, Instant On, Retains Program When

Powered Off

•

MSS I/Os

•

350 MHz System Performance

Embedded SRAMs and FIFOs

–

Schmitt Trigger, up to 6 mA IOH, 8 mA IOL

Up to 180 MHz

–

Variable Aspect Ratio 4,608-Bit SRAM Blocks

x1, x2, x4, x9, and x18 Organizations

True Dual-Port SRAM (excluding x18)

•

Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

External 1.5 V Is Allowed by Bypassing Regulator

(digital VCC = 1.5 V for FPGA and MSS, analog VCC =

3.3 V and 1.5 V)

1 Theoretical maximum

2 A2F200 and larger devices

January 2013

I

SmartFusion Customizable System-on-Chip (cSoC)

SmartFusion cSoC Family Product Table

A2F060

A2F200

A2F500

FPGA Fabric

TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484

System Gates

60,000

1,536

8

200,000

4,608

8

500,000

11,520

24

Tiles (D-flip-flops)

RAM Blocks (4,608 bits)

A2F060

A2F200

A2F500

Microcontroller Subsystem (MSS) TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484

Flash (Kbytes)

128

16

256

512

SRAM (Kbytes)

64

Cortex-M3 processor with MPU

10/100 Ethernet MAC

External Memory Controller (EMC)

Yes

No

Yes

–

1

26-/16-bit

address/data

26-bit address,16-bit data

–

26-/16-bit address/data

DMA

8 Ch

2

8 Ch

I²C

2

SPI

2

1

2

1

16550 UART

2

1

32-Bit Timer

2

PLL

1

2

1

2

32 KHz Low Power Oscillator

100 MHz On-Chip RC Oscillator

Main Oscillator (32 KHz to 20 MHz)

1

A2F060

A2F200

A2F500

Programmable Analog

ADCs (8-/10-/12-bit SAR)

DACs (8-/16-/24-bit sigma-delta)

Signal Conditioning Blocks (SCBs)

Comparator*

TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484

1

2

1

2

4

8

4

8

2

4

8

4

8

3

5

10

5

Current Monitors*

Temperature Monitors*

Bipolar High Voltage Monitors*

5

10

Note: *These functions share I/O pins and may not all be available at the same time. See the "Analog Front-End Overview" section in

the SmartFusion Programmable Analog User’s Guide for details.

II

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Package I/Os: MSS + FPGA I/Os

Device

A2F060¹

A2F200²

A2F500²

Package

TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484

Direct Analog Inputs

Shared Analog Inputs

Total Analog Inputs

Analog Outputs

MSS I/Os^3,4

FPGA I/Os

11

4

11

4

11

4

8

16

24

1

8

16

24

2

8

16

24

2

8

16

24

2

8

16

24

1

8

16

24

2

8

16

24

2

12

20

15

32

1

3

21⁵

33⁶

70

28⁵

68

112

26⁵

66

108

22

66

113

31

78

135

25

66

117

41

94

161

22

66⁶

113

31

78

135

25

66

117

41

128

204

Total I/Os

Notes:

1. There are no LVTTL capable direct inputs available on A2F060 devices.

2. These pins are shared between direct analog inputs to the ADCs and voltage/current/temperature monitors.

3. 16 MSS I/Os are multiplexed and can be used as FPGA I/Os, if not needed for MSS. These I/Os support Schmitt triggers and

support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V) standards.

4. 9 MSS I/Os are primarily for 10/100 Ethernet MAC and are also multiplexed and can be used as FPGA I/Os if Ethernet MAC is

not used in a design. These I/Os support Schmitt triggers and support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V

standards.

5. 10/100 Ethernet MAC is not available on A2F060.

6. EMC is not available on the A2F500 PQ208 and A2F060 TQ144 package.

Table 1 • SmartFusion cSoC Package Sizes Dimensions

Package

TQ144

20 × 20

400

PQ208

28 × 28

784

CS288

FG256

17 × 17

289

FG484

23 × 23

529

Length × Width (mm\mm)

Nominal Area (mm²)

Pitch (mm)

0.5

1.0

Height (mm)

1.40

3.40

1.60

2.23

SmartFusion cSoC Device Status

Device

Status

A2F060

Preliminary: CS288, FG256, TQ144

Production: CS288, FG256, FG484, PQ208

A2F200

A2F500

Revision 10

III

SmartFusion Customizable System-on-Chip (cSoC)

SmartFusion cSoC Block Diagram

™

PPB

Supervisor

OSC

Cortex -M3

SysReg

PLL

RC

JTAG

SWD

NVIC

SysTick

MPU

+

–

Microcontroller Subsystem

Programmable Analog

FPGA Fabric

ENVM

WDT

32 KHz

RTC

3V

ESRAM

S

D

I

APB

EFROM

IAP

SPI 1

APB

SPI 2

AHB Bus Matrix

UART 1

2

Timer1

Timer2

UART 2

2

10/100

EMAC

PDMA

APB

EMC

I

C 1

I

C 2

SCB

Analog Compute

Engine

Volt Mon.

Temp.

Mon.

(

)

ABPS

DAC

(SDD)

Curr.

Mon.

ADC

Comparator

Sample Sequencing

Engine

VersaTiles

........

SCB

Volt Mon.

Temp.

Mon.

DAC

(SDD)

ADC

(

)

ABPS

Post Processing

Engine

Curr.

Mon.

SRAM

........

SRAM

Comparator

Legend:

SDD – Sigma-delta DAC

SCB – Signal conditioning block

PDMA – Peripheral DMA

IAP – In-application programming

ABPS – Active bipolar prescaler

WDT – Watchdog Timer

SWD – Serial Wire Debug

IV

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

SmartFusion cSoC System Architecture

Bank 0

Embedded FlashROM

(eFROM)

ISP AES Decryption

Charge Pumps

Embedded NVM

(eNVM)

Cortex-M3 Microcontroller Subsystem (MSS)

Embedded SRAM

(eSRAM)

SCB

Osc.

ADC and DAC ADC and DAC

SCB

Bank 3

MSS

CCC

PLL/CCC

FPGA

Analog

Note: Architecture for A2F200

Revision 10

V

SmartFusion Customizable System-on-Chip (cSoC)

Product Ordering Codes

_

A2F200

M3

1

G

Y

I

F

FG

484

Application (junction temperature range)

Blank Commercial (0 to +85°C)

I = Industrial (–40 to +100°C)

ES = Engineering Silicon (room temperature only)

=

Security Feature*

Y = Device Includes License to Implement IP Based on the

Cryptography Research, Inc. (CRI) Patent Portfolio

Blank = Device Does Not Include License to Implement IP Based

on the Cryptography Research, Inc. (CRI) Patent Portfolio

Package Lead Count

208

256

288

484

Lead-Free Packaging Options

Blank = Standard Packaging

G = RoHS-Compliant (green) Packaging

Package Type

=

TQ

PQ

CS

FG

Thin Quad Flat Pack (0.5 mm pitch)

Plastic Quad Flat Pack (0.5 mm pitch)

Chip Scale Package (0.5 mm pitch)

Fine Pitch Ball Grid Array (1.0 mm pitch)

Speed Grade

Blank

= 80 MHz MSS Speed; FPGA Fabric at Standard Speed

–1 = 100 MHz MSS Speed; FPGA Fabric 15% Faster than Standard

eNVM Size

=

Currently only the following eNVM sizes are available

per device:

A

B

C

D

E

F

8 Kbytes

=

16 Kbytes

32 Kbytes

64 Kbytes

128 Kbytes

256 Kbytes

512 Kbytes

A2F500M3 – G

A2F200M3 – F

A2F060M3 – E

CPU Type

G

M3 = Cortex-M3

Part Number

SmartFusion Devices

A2F060 = 60,000 System Gates

A2F200 = 200,000 System Gates

A2F500 = 500,000 System Gates

Note: *Most devices in the SmartFusion cSoC family can be ordered with the Y suffix. Devices with a package size greater or equal to

5x5 mm are supported. Contact your local Microsemi SoC Products Group sales representative for more information.

Temperature Grade Offerings

SmartFusion cSoC

TQ144

A2F060

C, I

–

A2F200

–

A2F500

–

PQ208

C, I

CS288

C, I

–

C, I

FG256

C, I

FG484

C, I

Notes:

1. C = Commercial Temperature Range: 0°C to 85°C Junction

2. I = Industrial Temperature Range: –40°C to 100°C Junction

VI

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Table of Contents

SmartFusion Family Overview

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

SmartFusion DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61

Main and Lower Power Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

FPGA Fabric SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65

Embedded Nonvolatile Memory Block (eNVM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75

Embedded FlashROM (eFROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-76

Programmable Analog Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-77

Serial Peripheral Interface (SPI) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89

Inter-Integrated Circuit (I²C) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-91

SmartFusion Development Tools

Types of Design Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

SmartFusion Ecosystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Middleware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6

SmartFusion Programming

In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

In-Application Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

Typical Programming and Erase Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Pin Descriptions

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

User-Defined Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Global I/O Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

Microcontroller Subsystem (MSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

Analog Front-End (AFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

Analog Front-End Pin-Level Function Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16

TQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18

CS288 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22

PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32

FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39

Revision 10

Table of Contents

FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13

Microsemi SoC Products Group Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . 6-13

Revision 10

1 – SmartFusion Family Overview

Introduction

The SmartFusion^®family of cSoCs builds on the technology first introduced with the Fusion mixed signal

FPGAs. SmartFusion cSoCs are made possible by integrating FPGA technology with programmable

high-performance analog and hardened ARM Cortex-M3 microcontroller blocks on a flash semiconductor

process. The SmartFusion cSoC takes its name from the fact that these three discrete technologies are

integrated on a single chip, enabling the lowest cost of ownership and smallest footprint solution to you.

General Description

Microcontroller Subsystem (MSS)

The MSS is composed of a 100 MHz Cortex-M3 processor and integrated peripherals, which are

interconnected via a multi-layer AHB bus matrix (ABM). This matrix allows the Cortex-M3 processor,

FPGA fabric master, Ethernet message authentication controller (MAC), when available, and peripheral

DMA (PDMA) controller to act as masters to the integrated peripherals, FPGA fabric, embedded

nonvolatile memory (eNVM), embedded synchronous RAM (eSRAM), external memory controller

(EMC), and analog compute engine (ACE) blocks.

SmartFusion cSoCs of different densities offer various sets of integrated peripherals. Available

peripherals include SPI, I²C, and UART serial ports, embedded FlashROM (EFROM), 10/100 Ethernet

MAC, timers, phase-locked loops (PLLs), oscillators, real-time counters (RTC), and peripheral DMA

controller (PDMA).

Programmable Analog

Analog Front-End (AFE)

SmartFusion cSoCs offer an enhanced analog front-end compared to Fusion devices. The successive

approximation register analog-to-digital converters (SAR ADC) are similar to those found on Fusion

devices. SmartFusion cSoC also adds first order sigma-delta digital-to-analog converters (SDD DAC).

SmartFusion cSoCs can handle multiple analog signals simultaneously with its signal conditioning blocks

(SCBs). SCBs are made of a combination of active bipolar prescalers (ABPS), comparators, current

monitors and temperature monitors. ABPS modules allow larger bipolar voltages to be fed to the ADC.

Current monitors take the voltage across an external sense resistor and convert it to a voltage suitable

for the ADC input range. Similarly, the temperature monitor reads the current through an external PN-

junction (diode or transistor) and converts it internally for the ADC. The SCB also includes comparators

to monitor fast signal thresholds without using the ADC. The output of the comparators can be fed to the

analog compute engine or the ADC.

Analog Compute Engine (ACE)

The mixed signal blocks found in SmartFusion cSoCs are controlled and connected to the rest of the

system via a dedicated processor called the analog compute engine (ACE). The role of the ACE is to

offload control of the analog blocks from the Cortex-M3, thus offering faster throughput or better power

consumption compared to a system where the main processor is in charge of monitoring the analog

resources. The ACE is built to handle sampling, sequencing, and post-processing of the ADCs, DACs,

and SCBs.

Revision 10

1-1

SmartFusion Family Overview

ProASIC3 FPGA Fabric

The SmartFusion cSoC family, based on the proven, low power, firm-error immune ProASIC^®3 flash

FPGA architecture, benefits from the advantages only flash-based devices offer:

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, high performance, and ease of use. Flash-

based SmartFusion cSoCs are Instant On and do not need to be loaded from an external boot PROM at

each power-up. On-board security mechanisms prevent access to the programming information and

enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system

programming (ISP) to support future design iterations and critical field upgrades, with confidence that

valuable IP cannot be compromised or copied. Secure ISP can be performed using the industry standard

AES algorithm with MAC data authentication on the device.

Low Power

Flash-based SmartFusion cSoCs exhibit power characteristics similar to those of an ASIC, making them

an ideal choice for power-sensitive applications. With SmartFusion cSoCs, there is no power-on current

and no high current transition, both of which are common with SRAM-based FPGAs.

SmartFusion cSoCs also have low dynamic power consumption and support very low power time-

keeping mode, offering further power savings.

Security

As the nonvolatile, flash-based SmartFusion cSoC family requires no boot PROM, there is no vulnerable

external bitstream. SmartFusion cSoCs incorporate FlashLock^®, which provides a unique combination of

reprogrammability and design security without external overhead, advantages that only a device with

nonvolatile flash programming can offer.

SmartFusion cSoCs utilize a 128-bit flash-based key lock and a separate AES key to provide security for

programmed IP and configuration data. The FlashROM data in Fusion devices can also be encrypted

prior to loading. Additionally, the flash memory blocks can be programmed during runtime using the AES-

128 block cipher encryption standard (FIPS Publication 192).

SmartFusion cSoCs with AES-based security are designed to provide protection for remote field updates

over public networks, such as the Internet, and help to ensure that valuable IP remains out of the hands

of system overbuilders, system cloners, and IP thieves. As an additional security measure, the FPGA

configuration data of a programmed Fusion device cannot be read back, although secure design

verification is possible. During design, the user controls and defines both internal and external access to

the flash memory blocks.

Security, built into the FPGA fabric, is an inherent component of the SmartFusion cSoC family. The flash

cells are located beneath seven metal layers, and many device design and layout techniques have been

used to make invasive attacks extremely difficult. SmartFusion cSoCs, with FlashLock and AES security,

are unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is

protected with industry standard security measures, making remote ISP feasible. A SmartFusion cSoC

provides the highest security available for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the

configuration data is an inherent part of the FPGA structure, and no external configuration data needs to

be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based SmartFusion

cSoCs do not require system configuration components such as electrically erasable programmable

read-only memories (EEPROMs) or microcontrollers to load device configuration data during power-up.

This reduces bill-of-materials costs and PCB area, and increases system security and reliability.

Instant On

Flash-based SmartFusion cSoCs are Instant On. Instant On SmartFusion cSoCs greatly simplify total

system design and reduce total system cost by eliminating the need for complex programmable logic

devices (CPLDs). SmartFusion Instant On clocking (PLLs) replace off-chip clocking resources. In

addition, glitches and brownouts in system power will not corrupt the SmartFusion flash configuration.

Unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored.

This enables reduction or complete removal of expensive voltage monitor and brownout detection

1-2

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

devices from the PCB design. Flash-based SmartFusion cSoCs simplify total system design and reduce

cost and design risk, while increasing system reliability.

Immunity to Firm Errors

Firm errors occur most commonly when high-energy neutrons, generated in the atmosphere, strike a

configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O configuration behavior in an unpredictable

way.

Another source of radiation-induced firm errors is alpha particles. For alpha radiation to cause a soft or

firm error, its source must be in very close proximity to the affected circuit. The alpha source must be in

the package molding compound or in the die itself. While low-alpha molding compounds are being used

increasingly, this helps reduce but does not entirely eliminate alpha-induced firm errors.

Firm errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a

complete system failure. Firm errors do not occur in SmartFusion cSoCs. Once it is programmed, the

flash cell configuration element of SmartFusion cSoCs cannot be altered by high energy neutrons and is

therefore immune to errors from them. Recoverable (or soft) errors occur in the user data SRAMs of all

FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry

built into the FPGA fabric.

Specifying I/O States During Programming

You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for

PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.

Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have

limited display of Pin Numbers only.

The I/Os are controlled by the JTAG Boundary Scan register during programming, except for the analog

pins (AC, AT and AV). The Boundary Scan register of the AG pin can be used to enable/disable the gate

driver in software v9.0.

1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during

programming.

2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator

window appears.

3. Click the Specify I/O States During Programming button to display the Specify I/O States During

Programming dialog box.

4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.

Select the I/Os you wish to modify (Figure 1-1 on page 1-4).

5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings

for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state

settings:

1 – I/O is set to drive out logic High

0 – I/O is set to drive out logic Low

Last Known State – I/O is set to the last value that was driven out prior to entering the

programming mode, and then held at that value during programming

Z -Tri-State: I/O is tristated

Revision 10

1-3

SmartFusion Family Overview

Figure 1-1 • I/O States During Programming Window

6. Click OK to return to the FlashPoint – Programming File Generator window.

Note: I/O States During programming are saved to the ADB and resulting programming files after

completing programming file generation.

1-4

Revision 10

2 – SmartFusion DC and Switching Characteristics

General Specifications

Operating Conditions

Stresses beyond the operating conditions listed in Table 2-1 may cause permanent damage to the

device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any

other conditions beyond those listed under the Recommended Operating Conditions specified in

Table 2-3 on page 2-3 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol

VCC

Parameter

DC core supply voltage

Limits

Units

–0.3 to 1.65

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

–0.3 V to 3.6 V

V

VJTAG

VPP

JTAG DC voltage

Programming voltage

Analog power supply (PLL)

VCCPLLx

VCCFPGAIOBx DC FPGA I/O buffer supply voltage

VCCMSSIOBx DC MSS I/O buffer supply voltage

VI

I/O input voltage

(when I/O hot insertion mode is enabled)

–0.3 V to (VCCxxxxIOBx + 1 V) or 3.6 V,

whichever voltage is lower (when I/O hot-

insertion mode is disabled)

VCC33A

Analog clean 3.3 V supply to the analog

circuitry

–0.3 to 3.75

V

VCC33ADCx

VCC33AP

VCC33SDDx

VAREFx

Analog 3.3 V supply to ADC

–0.3 to 3.75

1.0 to 3.75

V

Analog clean 3.3 V supply to the charge pump

Analog 3.3 V supply to the sigma-delta DAC

Voltage reference for ADC

VCCRCOSC

VDDBAT

Analog supply to the integrated RC oscillator

External battery supply

–0.3 to 3.75

VCCMAINXTAL Analog supply to the main crystal oscillator

VCCLPXTAL

Analog supply to the low power 32 kHz crystal

oscillator

VCCENVM

VCCESRAM

VCC15A

Embedded nonvolatile memory supply

Embedded SRAM supply

–0.3 to 1.65

–65 to +150

125

V

Analog 1.5 V supply to the analog circuitry

Analog 1.5 V supply to the ADC

Storage temperature

V

VCC15ADCx

V

1

T_STG

°C

1

T_J

Junction temperature

Notes:

1. For flash programming and retention maximum limits, refer to Table 2-4 on page 2-4. For recommended operating

conditions, refer to Table 2-3 on page 2-3.

2. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may

undershoot or overshoot according to the limits shown in Table 2-5 on page 2-4.

Revision 10

2-1

SmartFusion DC and Switching Characteristics

Table 2-2 • Analog Maximum Ratings

Parameter

Conditions

Min.

Max.

Units

ABPS[n] pad voltage (relative to ground) GDEC[1:0] = 00 (±15.36 V range)

Absolute maximum

–11.5

–11

–11.5

–6

14.4

14

12

6

V

Recommended

GDEC[1:0] = 01 (±10.24 V range)

GDEC[1:0] = 10 (±5.12 V range)

GDEC[1:0] = 11 (±2.56 V range)

–3

3

CM[n] pad voltage relative to ground)

CMB_DI_ON = 0 (ADC isolated)

COMP_EN = 0 (comparator off, for the

associated even-numbered comparator)

Absolute maximum

Recommended

–0.3

14.4

14

3

V

CMB_DI_ON = 0 (ADC isolated)

COMP_EN = 1 (comparator on)

TMB_DI_ON = 1 (direct ADC in)

–0.3

3

V

TM[n] pad voltage (relative to ground)

ADC[n] pad voltage (relative to ground)

TMB_DI_ON = 0 (ADC isolated)

COMP_EN = 1(comparator on)

TMB_DI_ON = 1 (direct ADC in)

–0.3

3

V

3.6

2-2

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Table 2-3 • Recommended Operating Conditions^5,6

Symbol

Parameter¹

Commercial

0 to +85

Industrial

–40 to +100

1.425 to 1.575

1.425 to 3.6

3.15 to 3.45

0 to 3.6

Units

°C

V

T_J

Junction temperature

VCC ²

VJTAG

VPP

1.5 V DC core supply voltage

JTAG DC voltage

1.425 to 1.575

1.425 to 3.6

3.15 to 3.45

0 to 3.6

V

Programming voltage

Programming mode³

Operation⁴

V

VCCPLLx

Analog power supply (PLL)

1.425 to 1.575

1.7 to 1.9

1.425 to 1.575

1.7 to 1.9

V

VCCFPGAIOBx/ 1.5 V DC supply voltage

V

VCCMSSIOBx⁵

1.8 V DC supply voltage

V

2.5 V DC supply voltage

3.3 V DC supply voltage

LVDS differential I/O

2.3 to 2.7

V

3.0 to 3.6

V

2.375 to 2.625

3.0 to 3.6

2.375 to 2.625

3.0 to 3.6

V

LVPECL differential I/O

V

VCC33A⁶

Analog clean 3.3 V supply to the analog circuitry

Analog 3.3 V supply to ADC

3.15 to 3.45

2.527 to 3.3

3.15 to 3.45

2.7 to 3.63

3.15 to 3.45

2.527 to 3.3

3.15 to 3.45

2.7 to 3.63

3.15 to 3.45

V

VCC33ADCx⁶

VCC33AP⁶

VCC33SDDx⁶

VAREFx

V

Analog clean 3.3 V supply to the charge pump

Analog 3.3 V supply to sigma-delta DAC

Voltage reference for ADC

V

VCCRCOSC

VDDBAT

Analog supply to the integrated RC oscillator

External battery supply

V

VCCMAINXTAL⁶Analog supply to the main crystal oscillator

V

VCCLPXTAL⁶

Analog supply to the low power 32 KHz crystal

oscillator

V

VCCENVM

VCCESRAM

VCC15A²

Embedded nonvolatile memory supply

Embedded SRAM supply

1.425 to 1.575

V

Analog 1.5 V supply to the analog circuitry

Analog 1.5 V supply to the ADC

VCC15ADCx²

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC,

VCC15A, and VCC15ADCx.

3. The Programming temperature range supported is T

= 0°C to 85°C.

ambient

4. VPP can be left floating during operation (not programming mode).

5. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-19 on page 2-23. VCCxxxxIOBx should be at the same voltage within a given I/O bank.

6. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A,

VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL.

7.

Revision 10

2-3

SmartFusion DC and Switching Characteristics

Table 2-4 • FPGA and Embedded Flash Programming, Storage and Operating Limits

Grade Programming

Product Grade

Storage Temperature

Min. T_J= 0°C

Element

Cycles

Retention

20 years

10 years

5 years

Commercial

FPGA/FlashROM

Embedded Flash

500

Max. T_J= 85°C

< 1,000

< 10,000

< 15,000

500

Industrial

Min. T_J= –40°C

Max. T_J= 100°C

FPGA/FlashROM

Embedded Flash

20 years

10 years

5 years

< 1,000

< 10,000

< 15,000

Table 2-5 • Overshoot and Undershoot Limits ¹

Average VCCxxxxIOBx–GND Overshoot or Undershoot

Maximum Overshoot/

Undershoot²

VCCxxxxIOBx

Duration as a Percentage of Clock Cycle²

2.7 V or less

10%

5%

1.4 V

1.49 V

1.1 V

3 V

10%

5%

1.19 V

0.79 V

0.88 V

0.45 V

0.54 V

3.3 V

3.6 V

Notes:

10%

5%

10%

5%

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the

maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

Power Supply Sequencing Requirement

SmartFusion cSoCs have an on-chip 1.5 V regulator, but usage of an external 1.5 V supply is also

allowed while the on-chip regulator is disabled. In that case, the 3.3 V supplies (VCC33A, etc.) should be

powered before 1.5 V (VCC, etc.) supplies. The 1.5 V supplies should be enabled only after 3.3 V

supplies reach a value higher than 2.7 V.

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every SmartFusion cSoC. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1

on page 2-6.

There are five regions to consider during power-up.

SmartFusion I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCxxxxIOBx are above the minimum specified trip points (Figure 2-1 on page 2-6).

2. VCCxxxxIOBx > VCC – 0.75 V (typical)

3. Chip is in the SoC Mode.

2-4

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

VCCxxxxIOBx Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCxxxxIOBx ramp-up trip points are about 100 mV higher than ramp-down trip points. This

specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the

following:

•

By default, during programming I/Os become tristated and weakly pulled up to VCCxxxxIOBx.

You can modify the I/O states during programming in FlashPro. For more details, refer to

"Specifying I/O States During Programming" on page 1-3.

•

JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

PLL Behavior at Brownout Condition

The Microsemi SoC Products Group recommends using monotonic power supplies or voltage regulators

to ensure proper power-up behavior. Power ramp-up should be monotonic at least until VCC and

VCCPLLx exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case

(see Figure 2-1 on page 2-6 for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25

V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down

Behavior of Low Power Flash Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for

information on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

Output buffers, after 200 ns delay from input buffer activation

Revision 10

2-5

SmartFusion DC and Switching Characteristics

VCC = VCCxxxxIOBx + VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCC

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because

Region 1: I/O Buffers are OFF

speed, VIH / VIL , VOH / VOL , etc.

VCCxxxxIOBx

below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

VCC = 1.425 V

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because VCCxxxxIOBx / V_CCare

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

below specification. For the same reason, input

buffers do not meet VIH / VIL levels, and

output buffers do not meet VOH / VOL levels.

but I/Os are slower because

the VCC is below specification.

Activation trip point:

V_a= 0.85 V ± 0.25 V

Deactivation trip point:

V_d= 0.75 V ± 0.25 V

Region 1: I/O buffers are OFF

VCCxxxxIOBx

Activation trip point:

Min VCCxxxxIOBx datasheet specification

V_a= 0.9 V ± 0.3 V

Deactivation trip point:

V_d= 0.8 V ± 0.3 V

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

Figure 2-1 • I/O State as a Function of VCCxxxxIOBx and VCC Voltage Levels

2-6

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Thermal Characteristics

Introduction

The temperature variable in the SoC Products Group Designer software refers to the junction

temperature, not the ambient, case, or board temperatures. This is an important distinction because

dynamic and static power consumption will cause the chip's junction temperature to be higher than the

ambient, case, or board temperatures. EQ 1 through EQ 3 give the relationship between thermal

resistance, temperature gradient, and power.

T_J– _A

------------------

_JA

_JB

_JC

=

P

EQ 1

T_J– T_B

------------------

P

EQ 2

EQ 3

T_J– T_C

------------------

P

where

_JA= Junction-to-air thermal resistance

_JB= Junction-to-board thermal resistance

_JC= Junction-to-case thermal resistance

T_J= Junction temperature

T_A= Ambient temperature

T_B= Board temperature (measured 1.0 mm away from the

package edge)

T_C= Case temperature

P

= Total power dissipated by the device

Table 2-6 • Package Thermal Resistance

_JA

1.0 m/s

30.0

Product

Still Air

33.7

2.5 m/s

28.3

_JC

9.3

7.7

7.3

0.7

_JB

24.8

16.8

9.4

Units

A2F200M3F-FG256

A2F200M3F-FG484

A2F200M3F-CS288

A2F200M3F-PQG208I

°C/W

21.8

18.2

16.7

26.6

20.2

18.1

38.5

34.6

33.1

31.6

Revision 10

2-7

SmartFusion DC and Switching Characteristics

Theta-JA

Junction-to-ambient thermal resistance (_JA) is determined under standard conditions specified by

JEDEC (JESD-51), but it has little relevance in actual performance of the product. It should be used with

caution but is useful for comparing the thermal performance of one package to another.

A sample calculation showing the maximum power dissipation allowed for the A2F200-FG484 package

under forced convection of 1.0 m/s and 75°C ambient temperature is as follows:

T

_J(MAX)– T_A(MAX)

---------------------------------------------

Maximum Power Allowed =

_JA

EQ 4

where

_JA= 19.00°C/W (taken from Table 2-6 on page 2-7).

T_A= 75.00°C

100.00°C – 75.00°C

----------------------------------------------------

Maximum Power Allowed =

= 1.3 W

19.00°C/W

EQ 5

The power consumption of a device can be calculated using the Microsemi SoC Products Group power

calculator. The device's power consumption must be lower than the calculated maximum power

dissipation by the package. If the power consumption is higher than the device's maximum allowable

power dissipation, a heat sink can be attached on top of the case, or the airflow inside the system must

be increased.

Theta-JB

Junction-to-board thermal resistance (_JB) measures the ability of the package to dissipate heat from the

surface of the chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal resistance

from junction to board uses an isothermal ring cold plate zone concept. The ring cold plate is simply a

means to generate an isothermal boundary condition at the perimeter. The cold plate is mounted on a

JEDEC standard board with a minimum distance of 5.0 mm away from the package edge.

Theta-JC

Junction-to-case thermal resistance (_JC) measures the ability of a device to dissipate heat from the

surface of the chip to the top or bottom surface of the package. It is applicable for packages used with

external heat sinks. Constant temperature is applied to the surface in consideration and acts as a

boundary condition. This only applies to situations where all or nearly all of the heat is dissipated through

the surface in consideration.

Calculation for Heat Sink

For example, in a design implemented in an A2F200-FG484 package with 2.5 m/s airflow, the power

consumption value using the power calculator is 3.00 W. The user-dependent T_aand T_jare given as

follows:

T_J

T_A

=

100.00°C

70.00°C

From the datasheet:

_JA

_JC

=

17.00°C/W

8.28°C/W

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Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

T_J– T_A

------------------

_JA

100°C – 70°C

-----------------------------------

= 1.76 W

P =

=

17.00 W

EQ 6

The 1.76 W power is less than the required 3.00 W. The design therefore requires a heat sink, or the

airflow where the device is mounted should be increased. The design's total junction-to-air thermal

resistance requirement can be estimated by EQ 7:

T_J– T_A

------------------

P

100°C – 70°C

-----------------------------------

= 10.00°C/W

_JA(total)

=

3.00 W

EQ 7

EQ 8

Determining the heat sink's thermal performance proceeds as follows:

_JA(TOTAL)= _JC+ _CS+ _SA

where

_JA

=

0.37°C/W

Thermal resistance of the interface material between

the case and the heat sink, usually provided by the

thermal interface manufacturer

_SA

=

Thermal resistance of the heat sink in °C/W

_SA= _JA(TOTAL)– _JC– _CS

EQ 9

_SA= 13.33°C/W – 8.28°C/W – 0.37°C/W = 5.01°C/W

A heat sink with a thermal resistance of 5.01°C/W or better should be used. Thermal resistance of heat

sinks is a function of airflow. The heat sink performance can be significantly improved with increased

airflow.

Carefully estimating thermal resistance is important in the long-term reliability of an FPGA. Design

engineers should always correlate the power consumption of the device with the maximum allowable

power dissipation of the package selected for that device.

Note: The junction-to-air and junction-to-board thermal resistances are based on JEDEC standard

(JESD-51) and assumptions made in building the model. It may not be realized in actual

application and therefore should be used with a degree of caution. Junction-to-case thermal

resistance assumes that all power is dissipated through the case.

Temperature and Voltage Derating Factors

Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T_J= 85°C, worst-case VCC = 1.425 V)

Array

Junction Temperature (°C)

Voltage VCC

(V)

–40°C

0.86

0°C

0.91

0.86

0.83

25°C

0.93

0.88

0.85

70°C

0.98

0.93

0.90

85°C

1.00

0.95

0.91

100°C

1.02

1.425

1.500

1.575

0.81

0.96

0.78

0.93

Revision 10

2-9

SmartFusion DC and Switching Characteristics

Calculating Power Dissipation

Quiescent Supply Current

Table 2-8 • Power Supplies Configuration

Modes and Power

Supplies

Time Keeping mode

Standby mode

SoC mode

0 V

On*

0 V

3.3 V 0 V

0 V

N/A

Off

Reset Enable Disable

On Enable Enable

Enable Disable

3.3 V

1.5 V

N/A 3.3 V N/A

Note: *On means proper voltage is applied. Refer to Table 2-3 on page 2-3 for recommended operating conditions.

Table 2-9 • Quiescent Supply Current Characteristics

A2F060

A2F200

A2F500

1.5 V

3.3 V

1.5 V

3.3 V

1.5 V

3.3 V

Parameter

IDC1

Modes

SoC mode

Domain

3 mA

N/A

Domain

7 mA

N/A

Domain

16.5 mA

N/A

Domain

2 mA

10 µA

4 mA

10 µA

4 mA

10 µA

IDC2

Standby mode

IDC3

Time Keeping mode

Power per I/O Pin

Table 2-10 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Static Power

PDC7 (mW)

Dynamic Power PAC9

(µW/MHz)

VCCFPGAIOBx (V)

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

3.3

2.5

1.8

1.5

3.3

–

17.55

5.97

2.88

2.33

19.21

3.3 V PCI-X

Differential

LVDS

2.5

3.3

2.26

5.72

0.82

1.16

LVPECL

2-10

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Table 2-11 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to MSS I/O Banks

Static Power

PDC7 (mW)

Dynamic Power

PAC9 (µW/MHz)

VCCMSSIOBx (V)

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS / 3.3 V LVCMOS – Schmitt trigger

2.5 V LVCMOS

3.3

2.5

1.8

1.5

–

17.21

20.00

5.55

7.03

2.61

2.72

1.98

1.93

2.5 V LVCMOS – Schmitt trigger

1.8 V LVCMOS

1.8 V LVCMOS – Schmitt trigger

1.5 V LVCMOS (JESD8-11)

1.5 V LVCMOS (JESD8-11) – Schmitt trigger

Table 2-12 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings^*

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

VCCFPGAIOBx

(V)

Static Power

PDC8 (mW)

Dynamic Power

PAC10 (µW/MHz)

C_LOAD(pF)

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

35

10

3.3

2.5

1.8

1.5

3.3

–

475.66

270.50

152.17

104.44

202.69

3.3 V PCI-X

Differential

LVDS

–

2.5

3.3

7.74

88.26

LVPECL

19.54

164.99

Note: *Dynamic power consumption is given for standard load and software default drive strength and output slew.

Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings

Applicable to MSS I/O Banks

Static Power

PDC8 (mW)²

Dynamic Power

C_LOAD(pF)

VCCMSSIOBx (V)

PAC10 (µW/MHz)³

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

10

3.3

2.5

1.8

1.5

–

155.65

88.23

45.03

31.01

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

Revision 10

2-11

SmartFusion DC and Switching Characteristics

Power Consumption of Various Internal Resources

Table 2-14 • Different Components Contributing to Dynamic Power Consumption in SmartFusion cSoCs

Power Supply Device

Domain A2F060 A2F200 A2F500 Units

Parameter

PAC1

Definition

Name

VCC

Clock contribution of a Global Rib

Clock contribution of a Global Spine

1.5 V

3.39

1.14

1.15

3.40

1.83

1.15

5.05 µW/MHz

2.50 µW/MHz

1.15 µW/MHz

PAC2

PAC3

Clock contribution of a VersaTile

row

PAC4

PAC5

PAC6

PAC7

Clock contribution of a VersaTile

used as a sequential module

VCC

1.5 V

0.12

0.07

0.29

1.04

0.12

0.07

0.29

0.79

0.12 µW/MHz

0.07 µW/MHz

0.29 µW/MHz

0.79 µW/MHz

First contribution of a VersaTile

used as a sequential module

Second contribution of a VersaTile

used as a sequential module

Contribution of a VersaTile used as

a combinatorial module

PAC8

PAC9

Average contribution of a routing net

Contribution of an I/O input pin VCCxxxxIOBx/VCC See Table 2-10 and Table 2-11 on page 2-11

(standard dependent)

PAC10

PAC11

PAC12

Contribution of an I/O output pin VCCxxxxIOBx/VCC See Table 2-12 and Table 2-13 on page 2-11

(standard dependent)

Average contribution of a RAM

block during a read operation

VCC

1.5 V

25.00

µW/MHz

Average contribution of a RAM

block during a write operation

VCC

1.5 V

30.00

µW/MHz

PAC13

PAC15

Dynamic Contribution for PLL

VCC

1.5 V

2.60

µW/MHz

Contribution of NVM block during a

read operation (F < 33MHz)

358.00

PAC16

PAC17

1st contribution of NVM block during

a read operation (F > 33MHz)

VCC

1.5 V

12.88

4.80

mW

2nd contribution of NVM block

during a read operation (F > 33MHz)

µW/MHz

PAC18

Main Crystal Oscillator contribution

RC Oscillator contribution

VCCMAINXTAL

VCCRCOSC

VCC

3.3 V

1.5 V

3.3 V

1.98

3.30

3.00

8.25

mW

PAC19a

PAC19b

PAC20a

RC Oscillator contribution

Analog Block Dynamic Power

Contribution of the ADC

VCC33ADCx

PAC20b

PAC21

PAC22

PAC23

Analog Block Dynamic Power

Contribution of the ADC

VCC15ADCx

VCCLPXTAL

VCC

1.5 V

3.3 V

1.5 V

–

3.00

33.00

67.50

1.23

mW

µW

Low Power Crystal Oscillator

contribution

MSS Dynamic Power Contribution –

Running Drysthone at 100MHz¹

mW

Temperature Monitor Power

Contribution

See Table 2-94 on

page 2-78

2-12

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Table 2-14 • Different Components Contributing to Dynamic Power Consumption in SmartFusion cSoCs

Power Supply

Device

Parameter

Definition

Name Domain A2F060 A2F200 A2F500 Units

PAC24

Current Monitor Power Contribution See Table 2-93 on

page 2-77

–

1.03

0.70

0.58

1.02

36.30

mW

PAC25

PAC26

PAC27

PAC28

Notes:

ABPS Power Contribution

See Table 2-97 on

page 2-82

Sigma-Delta DAC Power

Contribution²

See Table 2-99 on

page 2-85

Comparator Power Contribution

See Table 2-98 on

page 2-84

Voltage Regulator Power

Contribution³

See Table 2-100 on

page 2-87

1. For a different use of MSS peripherals and resources, refer to SmartPower.

2. Assumes Input = Half Scale Operation mode.

3. Assumes 100 mA load on 1.5 V domain.

Table 2-15 • Different Components Contributing to the Static Power Consumption in SmartFusion cSoCs

Power Supply

Name

Device

Parameter

Definition

Domain A2F060 A2F200 A2F200 Units

PDC1

Core static power contribution in

SoC mode

VCC

1.5 V

11.10

33.00

23.70

33.00

37.95

33.00

mW

µW

PDC2

PDC3

PDC7

PDC8

PDC9

Device static power contribution in See Table 2-8 on

Standby Mode page 2-10

–

Device static power contribution in See Table 2-8 on

Time Keeping mode page 2-10

3.3 V

Static contribution per input pin VCCxxxxIOBx/VCC See Table 2-10 and Table 2-11 on page 2-11.

(standard dependent contribution)

Static contribution per output pin VCCxxxxIOBx/VCC See Table 2-12 and Table 2-13 on page 2-11.

(standard dependent contribution)

Static contribution per PLL

VCC

1.5 V

2.55

mW

Table 2-16 • eNVM Dynamic Power Consumption

Parameter Description

Condition

Idle

Min.

Typ.

795

Max.

Units

eNVMSystem eNVM array operating power

PNVMCTRL eNVM controller operating power

µA

Read operation

Erase

See Table 2-14 on page 2-12.

900

µA

Write

20

µW/MHz

Revision 10

2-13

SmartFusion DC and Switching Characteristics

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in the Libero SoC software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs/CCCs as well as the number and the frequency of each output clock

generated

•

The number of combinatorial and sequential cells used in the design

The internal clock frequencies

The number and the standard of I/O pins used in the design

The number of RAM blocks used in the design

The number of eNVM blocks used in the design

The analog block used in the design, including the temperature monitor, current monitor, ABPS,

sigma-delta DAC, comparator, low power crystal oscillator, RC oscillator and the main crystal

oscillator

•

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-17 on

page 2-18.

Enable rates of output buffers—guidelines are provided for typical applications in Table 2-18 on

page 2-18.

Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-18 on page 2-18.

Read rate to the eNVM blocks

The calculation should be repeated for each clock domain defined in the design.

Methodology

Total Power Consumption—P

TOTAL

SoC Mode, Standby Mode, and Time Keeping Mode.

P_TOTAL= P_STAT+ P_DYN

P_STATis the total static power consumption.

P_DYNis the total dynamic power consumption.

Total Static Power Consumption—P

SoC Mode

STAT

P_STAT= P_DC1+ (N_INPUTS* P_DC7) + (N_OUTPUTS* P_DC8) + (N_PLLS* P_DC9

)

N_INPUTSis the number of I/O input buffers used in the design.

N

_OUTPUTSis the number of I/O output buffers used in the design.

_PLLSis the number of PLLs available in the device.

N

Standby Mode

_STAT= P_DC2

P

Time Keeping Mode

P_STAT= P_DC3

Total Dynamic Power Consumption—P

DYN

SoC Mode

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL+ P_eNVM

P_XTL-OSC+ P_RC-OSC+ P_AB+ P_LPXTAL-OSC+ P_MSS

+

2-14

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Standby Mode

P_DYN= P_RC-OSC+ P_LPXTAL-OSC

Time Keeping Mode

P_DYN= P_LPXTAL-OSC

Global Clock Dynamic Contribution—P

CLOCK

SoC Mode

P_CLOCK= (P_AC1+ N_SPINE* P_AC2+ N_ROW* PAC3 + N_S-CELL* P_AC4) * F_CLK

N_SPINEis the number of global spines used in the user design—guidelines are provided in the

"Device Architecture" chapter of the SmartFusion FPGA Fabric User's Guide.

N

_ROWis the number of VersaTile rows used in the design—guidelines are provided in the "Device

Architecture" chapter of the SmartFusion FPGA Fabric User's Guide.

_CLKis the global clock signal frequency.

_S-CELLis the number of VersaTiles used as sequential modules in the design.

F

N

Standby Mode and Time Keeping Mode

P_CLOCK= 0 W

Sequential Cells Dynamic Contribution—P

S-CELL

SoC Mode

P_S-CELL= N_S-CELL* (P_AC5+ (₁/ 2) * P_AC6) * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design. When a multi-tile

sequential cell is used, it should be accounted for as 1.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-17 on page 2-18.

F_CLKis the global clock signal frequency.

Standby Mode and Time Keeping Mode

P_S-CELL= 0 W

Combinatorial Cells Dynamic Contribution—P

C-CELL

SoC Mode

P_C-CELL= N_C-CELL* (₁/ 2) * P_AC7* F_CLK

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-17 on page 2-18.

F

_CLKis the global clock signal frequency.

Standby Mode and Time Keeping Mode

_C-CELL= 0 W

P

Routing Net Dynamic Contribution—P

SoC Mode

NET

P_NET= (N_S-CELL+ N_C-CELL) * (₁/ 2) * P_AC8* F_CLK

N_S-CELLis the number VersaTiles used as sequential modules in the design.

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-17 on page 2-18.

F_CLKis the frequency of the clock driving the logic including these nets.

Revision 10

2-15

SmartFusion DC and Switching Characteristics

Standby Mode and Time Keeping Mode

P_NET= 0 W

I/O Input Buffer Dynamic Contribution—P

INPUTS

SoC Mode

P_INPUTS= N_INPUTS* (₂/ 2) * P_AC9* F_CLK

Where:

N

_INPUTSis the number of I/O input buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 2-17 on page 2-18.

_CLKis the global clock signal frequency.

F

Standby Mode and Time Keeping Mode

P_INPUTS= 0 W

I/O Output Buffer Dynamic Contribution—P

OUTPUTS

SoC Mode

P_OUTPUTS= N_OUTPUTS* (₂/ 2) * ₁* P_AC10* F_CLK

Where:

N_OUTPUTSis the number of I/O output buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 2-17 on page 2-18.

₁is the I/O buffer enable rate—guidelines are provided in Table 2-18 on page 2-18.

F_CLKis the global clock signal frequency.

Standby Mode and Time Keeping Mode

P_OUTPUTS= 0 W

FPGA Fabric SRAM Dynamic Contribution—P

MEMORY

SoC Mode

P_MEMORY= (N_BLOCKS* P_AC11* ₂* F_READ-CLOCK) + (N_BLOCKS* P_AC12* ₃* F_WRITE-CLOCK

)

Where:

N_BLOCKSis the number of RAM blocks used in the design.

F_READ-CLOCKis the memory read clock frequency.

₂is the RAM enable rate for read operations—guidelines are provided in Table 2-18 on

page 2-18.

₃the RAM enable rate for write operations—guidelines are provided in Table 2-18 on page 2-18.

F_WRITE-CLOCKis the memory write clock frequency.

Standby Mode and Time Keeping Mode

P_MEMORY= 0 W

PLL/CCC Dynamic Contribution—P

PLL

SoC Mode

P_PLL= P_AC13* F_CLKOUT

F_CLKINis the input clock frequency.

_CLKOUTis the output clock frequency.¹

F

Standby Mode and Time Keeping Mode

1.The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the

PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output

clock in the formula output clock by adding its corresponding contribution (P_AC14* F_CLKOUTproduct) to the total PLL

contribution.

2-16

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

P_PLL= 0 W

Embedded Nonvolatile Memory Dynamic Contribution—P

SoC Mode

eNVM

The eNVM dynamic power consumption is a piecewise linear function of frequency.

P_eNVM= N_eNVM-BLOCKS* ₄* P_AC15* F_READ-eNVMwhen F_READ-eNVM33 MHz,

P_eNVM= N_eNVM-BLOCKS* ₄*(P_AC16+ P_AC17* F_READ-eNVM) when F_READ-eNVM> 33 MHz

Where:

N_eNVM-BLOCKSis the number of eNVM blocks used in the design.

₄is the eNVM enable rate for read operations. Default is 0 (eNVM mainly in idle state).

F_READ-eNVMis the eNVM read clock frequency.

Standby Mode and Time Keeping Mode

P_eNVM= 0 W

Main Crystal Oscillator Dynamic Contribution—P

XTL-OSC

SoC Mode

P_XTL-OSC= P_AC18

Standby Mode

P_XTL-OSC= 0 W

Time Keeping Mode

P_XTL-OSC= 0 W

Low Power Oscillator Crystal Dynamic Contribution—P

LPXTAL-OSC

Operating, Standby, and Time Keeping Mode

P_LPXTAL-OSC= P_AC21

RC Oscillator Dynamic Contribution—P

RC-OSC

SoC Mode

P_RC-OSC= P_{AC19A +}P_AC19B

Standby Mode and Time Keeping Mode

P_RC-OSC= 0 W

Analog System Dynamic Contribution—P

AB

SoC Mode

P_AB= P_AC23* N_TM+ P_AC24* N_CM+ P_AC25* N_ABPS+ P_AC26* N_SDD+ P_AC27* N_COMP+ P_ADC* N_ADC

+ P_VR

Where:

N_CMis the number of current monitor blocks

N

_TMis the number of temperature monitor blocks

_SDDis the number of sigma-delta DAC blocks

N

N_ABPSis the number of ABPS blocks

_ADCis the number of ADC blocks

N

N_COMPis the number of comparator blocks

P_VR= P_AC28

P_ADC= P_AC20A+ P_AC20B

Revision 10

2-17

SmartFusion DC and Switching Characteristics

Microcontroller Subsystem Dynamic Contribution—P

MSS

SoC Mode

P_MSS= P_AC22

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that the net switches at half the clock frequency. Below are some

examples:

•

The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of the clock

frequency.

•

The average toggle rate of an 8-bit counter is 25%:

–

Bit 0 (LSB) = 100%

Bit 1 = 50%

Bit 2 = 25%

…

Bit 7 (MSB) = 0.78125%

Average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8.

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When

non-tristate output buffers are used, the enable rate should be 100%.

Table 2-17 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Toggle rate of VersaTile outputs

I/O buffer toggle rate

Guideline

10%

₁

₂

10%

Table 2-18 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

Guideline

₁

I/O output buffer enable rate

Toggle rate of the logic driving the

output buffer

₂

₃

₄

FPGA fabric SRAM enable rate for read

operations

12.5%

< 5%

FPGA fabric SRAM enable rate for write

operations

eNVM enable rate for read operations

2-18

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

User I/O Characteristics

Timing Model

I/O Module

(Non-Registered)

Combinational Cell

LVPECL (applicable to

FPGA /O bank, EMC pin)

Y

t_PD= 0.57 ns

t_PD= 0.49 ns

t

_DP= 1.53 ns

I/O Module

(Non-Registered)

Combinational Cell

Y

Output drive strength = 12 mA

High slew rate

_DP= 2.81 ns (FPGA I/O Bank, EMC pin)

LVTTL

t

t_PD= 0.89 ns

I/O Module

(Non-Registered)

Combinational Cell

I/O Module

(Registered)

Y

Output drive strength = 8 mA

High slew rate

LVTTL

t

_PY= 1.46 ns

t_DP= 3.87 ns (FPGA I/O Bank, EMC pin)

LVPECL

(Applicable

to FPGA

I/O Bank,

EMC pin)

t_PD= 0.51 ns

I/O Module

(Non-Registered)

D

Q

Combinational Cell

Y

Output drive strength = 4 mA

High slew rate

LVCMOS 1.5 V

t

_ICLKQ= 0.24 ns

t

_DP= 4.13 ns (FPGA I/O Bank, EMC pin)

t_PD= 0.48 ns

t_ISUD= 0.27 ns

Input LVTTL

Clock

I/O Module

Register Cell

(Registered)

Register Cell

Combinational Cell

Y

t

_PY= 0.81 ns (FPGA I/O Bank, EMC pin)

D

Q

D

Q

D

Q

LVTTL 3.3 V Output drive

strength = 12 mA High slew rate

I/O Module

(Non-Registered)

t_PD= 0.48 ns

t

_DP= 2.81 ns

(FPGA I/O Bank, EMC pin)

t_OCLKQ= 0.60 ns

_OSUD= 0.32 ns

t_CLKQ= 0.56 ns

t_SUD= 0.44 ns

t

_CLKQ= 0.56 ns

LVDS,

BLVDS,

M-LVDS

t

t_SUD= 0.44 ns

Input LVTTL

Clock

Input LVTTL

Clock

(Applicable for

FPGA I/O Bank,

EMC pin)

t_PY= 1.55 ns

t_PY= 0.81 ns

(FPGA I/O Bank, EMC pin)

Figure 2-2 • Timing Model

Operating Conditions: –1 Speed, Commercial Temperature Range (T_J= 85°C),

Worst Case VCC = 1.425 V

Revision 10

2-19

SmartFusion DC and Switching Characteristics

t

DIN

PY

D

Q

PAD

DIN

Y

CLK

To Array

I/O Interface

t

= MAX(t (R), t (F))

PY PY

PY

= MAX(t (R), t (F))

DIN

VIH

V

trip

VIL

PAD

VCC

50%

Y

GND

t

PY

(R)

(F)

VCC

50%

DIN

t

GND

t

DOUT

(R)

(F)

Figure 2-3 • Input Buffer Timing Model and Delays (example)

2-20

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

t_DOUT

D Q

t_DP

PAD

DOUT

CLK

Std

Load

D

From Array

t_DP= MAX(t_DP(R), t_DP(F))

t_DOUT= MAX(t_DOUT(R), t_DOUT(F))

I/O Interface

t_DOUT

(R)

t_DOUT

(F)

VCC

50%

VCC

D

0 V

50%

DOUT

PAD

0 V

VOH

V_trip

VOL

t_DP

(R)

t_DP

(F)

Figure 2-4 • Output Buffer Model and Delays (example)

Revision 10

2-21

SmartFusion DC and Switching Characteristics

t

EOUT

D

Q

CLK

t

, t , t , t , t , t

E

ZL ZH HZ LZ ZLS ZHS

EOUT

D

Q

PAD

DOUT

CLK

D

t

= MAX(t

(r), t (f))

EOUT

I/O Interface

EOUT

VCC

D

E

VCC

50%

t

50%

t

EOUT (F)

EOUT (R)

VCC

50%

ZH

50%

t

LZ

EOUT

PAD

t

ZL

VCCxxxxIOBx

HZ

90% VCCxxxxIOBx

V

trip

VOL

10% VCCxxxxIOBx

VCC

D

E

VCC

50%

t

EOUT (F)

EOUT (R)

VCC

50%

EOUT

PAD

50%

VOH

t

ZHS

t

ZLS

V

trip

VOL

Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)

2-22

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-19 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial

Conditions—Software Default Settings

Applicable to FPGA I/O Banks

1

VIL

Max.

VIH

Min.

V

VOL

VOH

I_OLI_OH

Drive Slew Min.

Max.

V

Max.

V

Min.

V

I/O Standard Strgth. Rate

V

mA mA

3.3 V LVTTL / 12 mA High –0.3

3.3 V LVCMOS

0.8

2

3.6

0.4

2.4

12 12

2.5 V LVCMOS 12 mA High –0.3

1.8 V LVCMOS 12 mA High –0.3

0.7

1.7

3.6

0.7

1.7

12 12

0.35 *

0.65*

0.45

VCCxxxxIOBx 12 12

– 0.45

VCCxxxxIOBx VCCxxxxIOBx

0.35 * 0.65*

VCCxxxxIOBx VCCxxxxIOBx

1.5 V LVCMOS 12 mA High –0.3

3.6

0.25 *

0.75*

12 12

VCCxxxxIOBx VCCxxxxIOBx

3.3 V PCI

3.3 V PCI-X

Notes:

Per PCI specifications

Per PCI-X specifications

1. Currents are measured at 85°C junction temperature.

2. Output slew rate can be extracted by the IBIS Models.

Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial

Conditions—Software Default Settings

Applicable to MSS I/O Banks

1

VIL

Max.

VIH

Min.

V

VOL

VOH

I_OLI_OH

Drive Slew Min.

Max.

V

Max.

V

Min.

V

I/O Standard Strgth. Rate

V

mA mA

3.3 V LVTTL / 8 mA High –0.3

3.3 V LVCMOS

0.8

2

3.6

0.4

2.4

8

2.5 V LVCMOS 8 mA High –0.3

1.8 V LVCMOS 4 mA High –0.3

0.7

1.7

3.6

0.7

1.7

8

4

8

4

0.35*

0.65*

0.45

VCCxxxxIOBx

– 0.45

VCCxxxxIOBx VCCxxxxIOBx

0.35* 0.65*

VCCxxxxIOBx VCCxxxxIOBx

1.5 V LVCMOS 2 mA High –0.3

3.6

0.25*

0.75*

2

VCCxxxxIOBx VCCxxxxIOBx

Notes:

1. Currents are measured at 85°C junction temperature.

2. Output slew rate can be extracted by the IBIS Models.

Revision 10

2-23

SmartFusion DC and Switching Characteristics

Table 2-21 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial Conditions in all I/O Bank Types

Commercial

I_IL

I_IH

µA

15

DC I/O Standards

µA

15

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

3.3 V PCI-X

Summary of I/O Timing Characteristics – Default I/O Software

Settings

Table 2-22 • Summary of AC Measuring Points Applicable to All I/O Bank Types

Standard

Measuring Trip Point (V_trip

)

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

1.4 V

1.2 V

0.90 V

0.75 V

0.285 * VCCxxxxIOBx (RR)

0.615 * VCCxxxxIOBx (FF)

0.285 * VCCxxxxIOBx (RR)

0.615 * VCCxxxxIOBx (FF)

Cross point

3.3 V PCI-X

LVDS

LVPECL

Cross point

Table 2-23 • I/O AC Parameter Definitions

Parameter

Parameter Definition

Data to pad delay through the output buffer

Pad to data delay through the input buffer

t_DP

t_PY

t_DOUT

t_EOUT

t_DIN

t_HZ

Data to output buffer delay through the I/O interface

Enable to output buffer tristate control delay through the I/O interface

Input buffer to data delay through the I/O interface

Enable to pad delay through the output buffer—High to Z

Enable to pad delay through the output buffer—Z to High

Enable to pad delay through the output buffer—Low to Z

Enable to pad delay through the output buffer—Z to Low

t_ZH

t_LZ

t_ZL

t_ZHS

t_ZLS

Enable to pad delay through the output buffer with delayed enable—Z to High

Enable to pad delay through the output buffer with delayed enable—Z to Low

2-24

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Worst Commercial-Case Conditions: T_J= 85°C, Worst Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx (per standard)

Applicable to FPGA I/O Banks, Assigned to EMC I/O Pins

I/O Standard

3.3 V LVTTL /

12 mA

High 35

–

0.50 2.81 0.03 0.81 0.32 2.86 2.23 2.55 2.82 4.58 3.94 ns

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

12 mA

High 35

–

0.50 2.73 0.03 1.03 0.32 2.88 2.69 2.62 2.70 4.60 4.41 ns

0.50 2.81 0.03 0.95 0.32 2.87 2.38 2.92 3.18 4.58 4.10 ns

0.50 3.24 0.03 1.12 0.32 3.30 2.79 3.10 3.27 5.02 4.50 ns

Per PCI spec High 10 25¹0.50 2.11 0.03 0.68 0.32 2.15 1.57 2.55 2.82 3.87 3.28 ns

3.3 V PCI-X

Per PCI-X

spec

High 10 25¹0.50 2.11 0.03 0.64 0.32 2.15 1.57 2.55 2.82 3.87 3.28 ns

LVDS

24 mA

High

–

0.50 1.53 0.03 1.55

0.50 1.46 0.03 1.46

–

ns

LVPECL

Notes:

1. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-39 for

connectivity. This resistor is not required during normal operation.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Worst Commercial-Case Conditions: T_J= 85°C, Worst Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx (per standard)

Applicable to MSS I/O Banks

I/O Standard

3.3 V LVTTL /

8 mA

High 10

–

0.18 1.92 0.07 0.78 1.09 0.18 1.96 1.55 1.83 2.04 ns

3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

Notes:

8 mA High 10

4 mA High 10

2 mA High 10

–

0.18 1.96 0.07 0.99 1.16 0.18 2.00 1.82 1.82 1.93 ns

0.18 2.31 0.07 0.91 1.37 0.18 2.35 2.27 1.84 1.87 ns

0.18 2.70 0.07 1.07 1.55 0.18 2.75 2.67 1.87 1.85 ns

1. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-39 for

connectivity. This resistor is not required during normal operation.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Revision 10

2-25

SmartFusion DC and Switching Characteristics

Detailed I/O DC Characteristics

Table 2-26 • Input Capacitance

Symbol

C_IN

Definition

Conditions

Min. Max. Units

Input capacitance

V_IN= 0, f = 1.0 MHz

8

pF

C_INCLK

Input capacitance on the clock pin

Table 2-27 • I/O Output Buffer Maximum Resistances¹

Applicable to FPGA I/O Banks

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

()²

100

50

()³

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

300

150

75

4 mA

6 mA

8 mA

50

12 mA

25

16 mA

17

50

24 mA

11

33

2.5 V LVCMOS

2 mA

100

50

200

100

50

4 mA

6 mA

8 mA

50

12 mA

25

16 mA

20

40

24 mA

11

22

1.8 V LVCMOS

2 mA

200

100

50

225

112

56

4 mA

6 mA

8 mA

50

56

12 mA

20

22

16 mA

20

22

1.5 V LVCMOS

2 mA

200

100

67

224

112

75

4 mA

6 mA

8 mA

33

37

12 mA

33

37

3.3 V PCI/PCI-X

Per PCI/PCI-X specification

25

75

Notes:

1. These maximum values are provided for information only. Minimum output buffer resistance values

depend on VCCxxxxIOBx, drive strength selection, temperature, and process. For board design

considerations and detailed output buffer resistances, use the corresponding IBIS models located on the

Microsemi SoC Products Group website at http://www.microsemi.com/soc/download/ibis/default.aspx

(also generated by the SoC Products Group Libero SoC toolset).

2.

3.

R

= (V

) / I

OLspec OLspec

(PULL-DOWN-MAX)

= (V

– V

) / I

(PULL-UP-MAX)

CCImax

OHspec OHspec

2-26

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Table 2-28 • I/O Output Buffer Maximum Resistances¹

Applicable to MSS I/O Banks

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

8mA

()²

()³

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

Notes:

50

150

100

112

224

8 mA

4 mA

100

200

2 mA

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCxxxxIOBx, drive strength selection, temperature, and process. For board design

considerations and detailed output buffer resistances, use the corresponding IBIS models located on the

SoC Products Group website at http://www.microsemi.com/soc/download/ibis/default.aspx.

2.

R

= (V

) / I

OLspec OLspec

(PULL-DOWN-MAX)

3.

R

= (V

– V

) / I

(PULL-UP-MAX)

CCImax

OHspec OHspec

Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

1

2

R_{(WEAK PULL-UP)}

R_{(WEAK PULL-DOWN)}

()

VCCxxxxIOBx

3.3 V

Min.

Max.

45 k

55 k

70 k

90 k

Min.

10 k

12 k

17 k

19 k

Max.

45 k

10 k

11 k

18 k

19 k

2.5 V

74 k

1.8 V

110 k

140 k

1.5 V

Notes:

1.

2.

R

= (VCCImax – VOHspec) / I

(WEAK PULL-UP-MAX)

(WEAK PULL-UP-MIN)

(WEAK PULL-DOWN-MIN)

= (VOLspec) / I

(WEAK PULL-DOWN-MAX)

Revision 10

2-27

SmartFusion DC and Switching Characteristics

Table 2-30 • I/O Short Currents I_OSH/I_OSL

Applicable to FPGA I/O Banks

Drive Strength

2 mA

I

_OSL(mA)^*

27

I_OSH(mA)^*

25

3.3 V LVTTL / 3.3 V LVCMOS

4 mA

27

25

6 mA

54

51

8 mA

54

51

12 mA

16 mA

24 mA

2 mA

109

127

181

18

103

132

268

16

2.5 V LVCMOS

4 mA

18

16

6 mA

37

32

8 mA

37

32

12 mA

16 mA

24 mA

2 mA

74

65

87

83

124

11

169

9

1.8 V LVCMOS

4 mA

22

17

6 mA

44

35

8 mA

51

45

12 mA

16 mA

2 mA

74

91

74

91

1.5 V LVCMOS

16

13

4 mA

33

25

6 mA

39

32

8 mA

55

66

12 mA

55

66

3.3 V PCI/PCI-X

Per PCI/PCI-X specification

109

103

Note: *T_J= 85°C.

Table 2-31 • I/O Short Currents I_OSH/I_OSL

Applicable to MSS I/O Banks

Drive Strength

8 mA

I

_OSL(mA)*

I_OSH(mA)*

3.3 V LVTTL / 3.3 V LVCMOS

2.5 V LVCMOS

54

37

22

16

51

32

17

13

8 mA

1.8 V LVCMOS

4 mA

1.5 V LVCMOS

2 mA

Note: *T_J= 85°C

2-28

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

The length of time an I/O can withstand I_{OSH OSL}

/I

events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 100°C, the short current condition would have to be sustained for more than 2200

operation hours to cause a reliability concern. The I/O design does not contain any short circuit

protection, but such protection would only be needed in extremely prolonged stress conditions.

Table 2-32 • Duration of Short Circuit Event before Failure

Temperature

–40°C

0°C

Time before Failure

> 20 years

5 years

25°C

70°C

85°C

2 years

100°C

6 months

Table 2-33 • Schmitt Trigger Input Hysteresis

Hysteresis Voltage Value (typical) for Schmitt Mode Input Buffers

Input Buffer Configuration Hysteresis Value (typical)

3.3 V LVTTL / LVCMOS / PCI / PCI-X (Schmitt trigger mode)

2.5 V LVCMOS (Schmitt trigger mode)

240 mV

140 mV

80 mV

60 mV

1.8 V LVCMOS (Schmitt trigger mode)

1.5 V LVCMOS (Schmitt trigger mode)

Table 2-34 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Buffer

Input Rise/Fall Time (min.) Input Rise/Fall Time (max.)

Reliability

LVTTL/LVCMOS

No requirement

10 ns *

20 years (100°C)

10 years (100°C)

LVDS/B-LVDS/

M-LVDS/LVPECL

Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the

noise is low, then the rise time and fall time of input buffers can be increased beyond the

maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board

noise. Microsemi SoC Products Group recommends signal integrity evaluation/characterization of

the system to ensure that there is no excessive noise coupling into input signals.

Revision 10

2-29

SmartFusion DC and Switching Characteristics

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer.

Table 2-35 • Minimum and Maximum DC Input and Output Levels

Applicable to FPGA I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

VIL

VIH

VOL

VOH I_OLI_OH

Min.

I_OSL

I_OSH

I_ILI_IH

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA¹

Max.

mA¹

Drive Strength

2 mA

V

mA mA

µA²µA²

15 15

10 10

–0.3

0.8

2

3.6

0.4

2.4

2

27

25

4 mA

4

6 mA

6

54

51

8 mA

8

54

51

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

109

127

181

103

132

268

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-36 • Minimum and Maximum DC Input and Output Levels

Applicable to MSS I/O Banks

3.3 V LVTTL /

3.3 V LVCMOS

VIL

VIH

VOL

VOH I_OLI_OH

Min.

I_OSL

I_OSH

I_ILI_IH

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA¹

Max.

mA¹

Drive Strength

8 mA

V

mA mA

µA²µA²

–0.3

0.8

2

3.6

0.4

2.4

8

54

51

15 15

Notes:

1. Currents are measured at 100°C junction temperature and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to VCCxxxxIOBx for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

35 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

35 pF for t_HZ/ t_LZ

R = 1 K

Test Point

Enable Path

Test Point

Datapath

35 pF

Figure 2-6 • AC Loading

Table 2-37 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

V

_REF(typ.) (V)

C_LOAD(pF)

0

3.3

1.4

–

35

Note: *Measuring point = V_trip.See Table 2-22 on page 2-24 for a complete table of trip points.

2-30

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Timing Characteristics

Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 3.0 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.39

0.32

0.39

0.32

0.39

0.32

0.39

0.32

0.39

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

9.39

7.83

6.79

5.65

5.49

4.58

5.30

4.42

5.05

4.21

t_ZHS

8.23

6.86

5.90

4.91

4.73

3.94

4.49

3.74

4.09

3.41

Units

ns

4 mA

Std.

–1

0.60

0.50

0.60

0.50

0.60

0.50

0.60

0.50

0.60

0.50

7.20 0.04 0.97

6.00 0.03 0.81

4.64 0.04 0.97

3.87 0.03 0.81

3.37 0.04 0.97

2.81 0.03 0.81

3.18 0.04 0.97

2.65 0.03 0.81

2.93 0.04 0.97

2.45 0.03 0.81

7.34 6.18 2.52 2.46

6.11 5.15 2.10 2.05

4.73 3.84 2.85 3.02

3.94 3.20 2.37 2.52

3.43 2.67 3.07 3.39

2.86 2.23 2.55 2.82

3.24 2.43 3.11 3.48

2.70 2.03 2.59 2.90

2.99 2.03 3.17 3.83

2.49 1.69 2.64 3.19

ns

8 mA

Std.

–1

ns

12 mA

16 mA

24 mA

Notes:

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-39 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 3.0 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.60

0.50

0.60

0.50

0.60

0.50

0.60

0.50

0.60

0.50

9.75 0.04 0.97 0.39

8.12 0.03 0.81 0.32

6.96 0.04 0.97 0.39

5.80 0.03 0.81 0.32

5.35 0.04 0.97 0.39

4.46 0.03 0.81 0.32

5.01 0.04 0.97 0.39

4.17 0.03 0.81 0.32

4.67 0.04 0.97 0.39

3.89 0.03 0.81 0.32

9.93

8.27

7.09

5.91

5.45

4.54

5.10

4.25

4.75

3.96

8.22 2.52 2.31 11.99 10.28

ns

6.85 2.10 1.93 9.99

5.85 2.84 2.87 9.15

4.88 2.37 2.39 7.62

4.58 3.06 3.23 7.51

3.82 2.55 2.69 6.26

8.57

7.91

6.59

6.64

5.53

6.36

5.30

6.34

5.28

8 mA

Std.

–1

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

4.30

3.11 3.32 7.16

3.58 2.59 2.77 5.97

4.28 3.16 3.66 6.81

3.57 2.64 3.05 5.68

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-40 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 3.0 V

Applicable to MSS I/O Banks

Drive

Strength

Speed

Grade

t_DOUT

0.22

t_DP

2.31

1.92

t_DIN

0.09

0.07

t_PY

t_PYS

1.30

1.09

t_EOUT

0.22

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

8 mA

Std.

–1

0.94

0.78

2.35

1.96

1.86

1.55

2.20

1.83

2.45

2.04

0.18

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Revision 10

2-31

SmartFusion DC and Switching Characteristics

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications.

Table 2-41 • Minimum and Maximum DC Input and Output Levels

Applicable to FPGA I/O Banks

2.5 V LVCMOS

VIL

VIH

VOL

VOH I_OLI_OH

Min.

I_OSL

I_OSH

I_ILI_IH

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA¹

Max.

mA¹

Drive Strength

2 mA

V

mA mA

µA²µA²

15 15

–0.3

0.7

1.7

2.7

0.7

1.7

2

4

6

8

2

4

6

8

18

16

4 mA

6 mA

37

32

8 mA

37

32

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

74

65

87

83

124

169

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-42 • Minimum and Maximum DC Input and Output Levels

Applicable to MSS I/O Banks

2.5 V LVCMOS

VIL

V_IH

VOL

VOH I_OLI_OH

Min.

I_OSL

I_OSH

I_ILI_IH

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA¹

Max.,

mA¹

Drive Strength

8 mA

V

mA mA

µA²µA²

–0.3

0.7

1.7

3.6

0.7

1.7

8

37

32

15 15

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to VCCxxxxIOBx for t_LZ/ t_ZL/ t_ZLS

R = 1 K

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

35 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

35 pF for t_HZ/ t_LZ

Test Point

35 pF

Enable Path

Figure 2-7 • AC Loading

Table 2-43 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

V

_REF(typ.) (V)

C_LOAD(pF)

35

0

2.5

1.2

–

* Measuring point = V_trip.See Table 2-22 on page 2-24 for a complete table of trip points.

2-32

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Timing Characteristics

Table 2-44 • 2.5 V LVCMOS High Slew

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 2.3 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.39

0.32

0.39

0.32

0.39

0.32

0.39

0.32

0.39

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

9.43

7.85

6.82

5.68

5.52

4.60

5.33

4.44

5.07

4.22

t_ZHS

10.15

8.46

6.91

5.76

5.29

4.41

4.94

4.12

4.37

3.64

Units

ns

4 mA

Std.

–1

0.55

0.46

0.55

0.46

0.60

0.50

0.60

0.50

0.60

0.50

8.10

6.75

4.85

4.04

3.28

2.73

3.09

2.57

2.95

2.46

0.04 1.23

0.03 1.03

0.04 1.23

0.03 1.03

0.04 1.23

0.03 1.03

0.04 1.23

0.03 1.03

0.04 1.23

0.03 1.03

7.37

6.14

4.76

3.97

3.46

2.88

3.27

2.72

3.01

2.51

8.10

6.75

4.85

4.04

3.23

2.69

2.88

2.40

2.31

1.93

2.54 2.17

2.12 1.81

2.90 2.83

2.42 2.36

3.15 3.24

2.62 2.70

3.20 3.35

2.67 2.79

3.27 3.76

2.73 3.13

ns

8 mA

Std.

–1

ns

12 mA

16 mA

24 mA

Notes:

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-45 • 2.5 V LVCMOS Low Slew

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 2.3 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.55

0.46

0.55

0.46

0.60

0.50

0.60

0.50

0.60

0.50

10.50 0.04 1.23 0.39

8.75 0.03 1.03 0.32

7.61 0.04 1.23 0.39

6.34 0.03 1.03 0.32

5.92 0.04 1.23 0.39

4.93 0.03 1.03 0.32

5.53 0.04 1.23 0.39

4.61 0.03 1.03 0.32

5.18 0.04 1.23 0.39

4.32 0.03 1.03 0.32

10.69 10.50 2.54 2.07 12.75 12.56

ns

8.91

7.46

6.22

5.79

4.83

5.40

4.50

5.28

4.40

8.75 2.12 1.73 10.62 10.47

8 mA

Std.

–1

7.19 2.81 2.66 9.52

5.99 2.34 2.22 7.93

5.45 3.04 3.06 7.85

4.54 2.53 2.55 6.54

5.09 3.09 3.16 7.46

4.24 2.58 2.64 6.22

5.14 3.27 3.64 7.34

9.25

7.71

7.51

6.26

7.14

5.95

7.20

6.00

12 mA

16 mA

24 mA

Std.

–1

Std.

–1

Std.

–1

4.29 2.72 3.03

6.11

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-46 • 2.5 V LVCMOS High Slew

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 3.0 V

Applicable to MSS I/O Banks

Drive

Strength

Speed

Grade

t_DOUT

0.22

t_DP

2.35

1.96

t_DIN

0.09

0.07

t_PY

t_PYS

1.39

1.16

t_EOUT

0.22

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

8 mA

Std.

–1

1.18

0.99

2.40

2.00

2.18

1.82

2.19 2.32

1.82 1.93

0.18

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Revision 10

2-33

SmartFusion DC and Switching Characteristics

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-47 • Minimum and Maximum DC Input and Output Levels

Applicable to FPGA I/O Banks

1.8 V

LVCMOS

VIL

Max.

VIH

Min.

V

VOL

VOH

I_OLI_OH

mA mA

I_OSL

I_OSH

I_ILI_IH

Drive

Strength

Min.

V

Max. Max.

Min.

V

Max.

mA¹

Max.

V

mA¹µA²µA²

2 mA

–0.3

0.35 *

0.65 *

1.9 0.45 VCCxxxxIOBx

– 0.45

2

11

22

44

51

74

9

15 15

VCCxxxxIOBx VCCxxxxIOBx

0.35 * 0.65 *

VCCxxxxIOBx VCCxxxxIOBx

0.35 * 0.65 *

VCCxxxxIOBx VCCxxxxIOBx

0.35 * 0.65 *

VCCxxxxIOBx VCCxxxxIOBx

0.35 * 0.65 *

VCCxxxxIOBx VCCxxxxIOBx

0.35 * 0.65 *

VCCxxxxIOBx VCCxxxxIOBx

4 mA

1.9 0.45 VCCxxxxIOBx

– 0.45

4

17

35

45

91

6 mA

1.9 0.45 VCCxxxxIOBx

– 0.45

6

8 mA

1.9 0.45 VCCxxxxIOBx

– 0.45

8

12 mA

16 mA

Notes:

1.9 0.45 VCCxxxxIOBx 12 12

– 0.45

1.9 0.45 VCCxxxxIOBx 16 16

– 0.45

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-48 • Minimum and Maximum DC Input and Output Levels

Applicable to MSS I/O Banks

1.8 V

LVCMOS

VIL

Max.

VIH

Min.

V

VOL

VOH

I_OLI_OHI_OSLI_OSHI_ILI_IH

Drive

Strength

Min.

V

Max. Max.

Min.

V

Max. Max.

V

mA mA mA¹mA¹µA²µA²

4 mA

–0.3

0.35 *

0.65 *

3.6 0.45 VCCxxxxIOBx

– 0.45

4

22

17

15 15

VCCxxxxIOBx VCCxxxxIOBx

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to VCCxxxxIOBx for t_LZ/ t_ZL/ t_ZLS

R = 1 K

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

35 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

35 pF for t_HZ/ t_LZ

Test Point

35 pF

Enable Path

Figure 2-8 • AC Loading

Table 2-49 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

V_REF(typ.) (V)

C_LOAD(pF)

0

1.8

0.9

–

35

* Measuring point = V_trip.See Table 2-22 on page 2-24 for a complete table of trip points.

2-34

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Timing Characteristics

Table 2-50 • 1.8 V LVCMOS High Slew

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 1.7 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.39

0.32

0.39

0.32

0.39

0.32

0.39

0.32

0.39

0.32

0.39

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

Std.

–1

0.60

0.50

0.60

0.50

0.60

0.50

0.60

0.50

0.60

0.50

0.60

0.50

11.06 0.04 1.14

8.61

7.17

5.53

4.61

3.99

3.32

3.76

3.13

3.44

2.87

3.44

2.87

11.06 2.61 1.59 10.67 13.12

ns

9.22

6.46

5.38

4.16

3.47

3.69

3.07

3.38

2.81

3.38

2.81

0.03 0.95

0.04 1.14

0.03 0.95

0.04 1.14

0.03 0.95

0.04 1.14

0.03 0.95

0.04 1.14

0.03 0.95

0.04 1.14

0.03 0.95

9.22

6.46

5.38

4.16

3.47

3.67

3.06

2.86

2.38

2.86

2.38

2.18 1.33

3.04 2.66

2.54 2.22

3.34 3.18

2.78 2.65

3.40 3.31

2.84 2.76

3.50 3.82

2.92 3.18

3.50 3.82

2.92 3.18

8.89

7.59

6.33

6.05

5.04

5.81

4.85

5.50

4.58

5.50

4.58

10.93

8.51

7.10

6.22

5.18

5.73

4.78

4.91

4.10

4.91

4.10

4 mA

Std.

–1

6 mA

Std.

–1

8 mA

Std.

–1

12 mA

16 mA

Notes:

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-51 • 1.8 V LVCMOS Low Slew

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 1.7 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

ns

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

–1

0.60

0.50

0.60

0.50

0.60

0.50

0.60

0.50

0.60

0.50

0.60

0.50

14.24 0.04 1.14 0.39 13.47 14.24 2.62 1.54 15.53 16.30

11.87 0.03 0.95 0.32

9.74 0.04 1.14 0.39

8.11 0.03 0.95 0.32

7.67 0.04 1.14 0.39

6.39 0.03 0.95 0.32

7.15 0.04 1.14 0.39

5.96 0.03 0.95 0.32

6.76 0.04 1.14 0.39

5.64 0.03 0.95 0.32

6.76 0.04 1.14 0.39

5.64 0.03 0.95 0.32

11.23 11.87 2.18 1.28 12.94 13.59

ns

Std.

–1

9.92

8.26

7.81

6.51

7.29

6.07

6.89

5.74

6.89

5.74

9.62 3.05 2.57 11.98 11.68

ns

8.02 2.54 2.14 9.98

7.24 3.34 3.08 9.87

6.03 2.79 2.56 8.23

6.75 3.41 3.21 9.34

5.62 2.84 2.68 7.79

6.75 3.50 3.70 8.95

5.62 2.92 3.08 7.46

6.75 3.50 3.70 8.95

5.62 2.92 3.08 7.46

9.74

9.30

7.75

8.80

7.34

8.81

7.34

8.81

7.34

ns

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

Std.

–1

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Revision 10

2-35

SmartFusion DC and Switching Characteristics

Table 2-52 • 1.8 V LVCMOS High Slew

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 1.7 V

Applicable to MSS I/O Banks

Drive

Speed

Strength

Grade

t_DOUT

0.22

t_DP

t_DIN

t_PYt_PYSt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

Units

ns

4 mA

Std.

2.77

2.31

0.09 1.09 1.64

0.07 0.91 1.37

0.22

0.18

2.82

2.35

2.72

2.27

2.21

1.84

2.25

1.87

–1

0.18

ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

2-36

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-53 • Minimum and Maximum DC Input and Output Levels

Applicable to FPGA I/O Banks

1.5 V

LVCMOS

VIL

Max.

VIH

Min.

V

VOL

VOH

I_OLI_OHI_OSLI_OSHI_ILI_IH

Drive

Strength

Min.

V

Max.

V

Max.

V

Min.

V

Max. Max.

V

mA mA mA¹mA¹µA²µA²

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–0.3

0.35 *

0.65 *

1.575

0.25*

0.75 *

2

16

33

39

55

13 15 15

25 15 15

32 15 15

66 15 15

VCCxxxxIOBx VCCxxxxIOBx

0.25* 0.75 *

VCCxxxxIOBx VCCxxxxIOBx

0.25* 0.75 *

VCCxxxxIOBx VCCxxxxIOBx

–

0.35* 0.65 *

4

0.3 VCCxxxxIOBx VCCxxxxIOBx

0.35 * 0.65 *

0.3 VCCxxxxIOBx VCCxxxxIOBx

0.35 * 0.65 *

0.3 VCCxxxxIOBx VCCxxxxIOBx

0.35 * 0.65 *

0.3 VCCxxxxIOBx VCCxxxxIOBx

–

6

–

0.25* VCC

0.75 *

VCCxxxxIOBx

8

–

0.25 *

0.75 *

12 12 55

VCCxxxxIOBx VCCxxxxIOBx

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Table 2-54 • Minimum and Maximum DC Input and Output Levels

Applicable to MSS I/O Banks

1.5 V

LVCMOS

VIL

Max.

VIH

Min.

V

VOL

VOH

I_OLI_OHI_OSLI_OSHI_ILI_IH

Drive

Strength

Min.

V

Max.

V

Max.

V

Min.

V

Max. Max.

µA

2

V

mA mA mA¹mA¹µA²

2 mA

–0.3

0.35 *

0.65 *

1.575

0.25 *

0.75 *

2

16

13 15 15

VCCxxxxIOBx VCCxxxxIOBx

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

R to VCCxxxxIOBx for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

35 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

35 pF for t_HZ/ t_LZ

R = 1 K

Test Point

Enable Path

Test Point

Datapath

35 pF

Figure 2-9 • AC Loading

Table 2-55 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

V_REF(typ.) (V)

C_LOAD(pF)

35

0

1.5

0.75

–

* Measuring point = V_trip.See Table 2-22 on page 2-24 for a complete table of trip points.

Revision 10

2-37

SmartFusion DC and Switching Characteristics

Timing Characteristics

Table 2-56 • 1.5 V LVCMOS High Slew

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 1.425 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Drive

Speed

Strength

Grade t_DOUT

t_DP

t_DIN

t_PY

t_EOUT

0.39

0.32

0.39

0.32

0.39

0.32

0.39

0.32

0.39

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 m

Std.

–1

0.60

0.50

0.60

0.50

0.60

0.50

0.60

0.50

0.60

0.50

7.79 0.04 1.34

6.49 0.03 1.12

4.95 0.04 1.34

4.13 0.03 1.12

4.36 0.04 1.34

3.64 0.03 1.12

3.89 0.04 1.34

3.24 0.03 1.12

3.89 0.04 1.34

3.24 0.03 1.12

6.43 7.79 3.19 2.59 8.49

5.36 6.49 2.66 2.16 7.08

4.61 4.96 3.53 3.19 6.67

3.85 4.13 2.94 2.66 5.56

4.34 4.36 3.60 3.34 6.40

3.62 3.64 3.00 2.78 5.33

3.96 3.34 3.72 3.92 6.02

3.30 2.79 3.10 3.27 5.02

3.96 3.34 3.72 3.92 6.02

3.30 2.79 3.10 3.27 5.02

9.85

8.21

7.02

5.85

6.42

5.35

5.40

4.50

5.40

4.50

ns

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

Std.

–1

Std.

–1

Std.

–1

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-57 • 1.5 V LVCMOS Low Slew

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 1.4 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Drive

Strength

Speed

Grade

t_DOUT

0.60

0.50

0.60

0.50

0.60

0.50

0.60

0.50

0.60

0.50

t_DP

t_DIN

t_PYt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Std.

–1

11.96 0.04 1.34 0.39 12.18 11.70 3.20 2.47 14.24 13.76

9.96 0.03 1.12 0.32 10.15 9.75 2.67 2.06 11.86 11.46

ns

Std.

–1

9.51 0.04 1.34 0.39

7.92 0.03 1.12 0.32

8.86 0.04 1.34 0.39

7.39 0.03 1.12 0.32

8.44 0.04 1.34 0.39

7.04 0.03 1.12 0.32

8.44 0.04 1.34 0.39

7.04 0.03 1.12 0.32

9.68 8.76 3.54 3.07 11.74 10.82

8.07 7.30 2.95 2.56 9.79 9.02

9.03 8.17 3.61 3.22 11.08 10.23

7.52 6.81 3.01 2.68 9.24 8.52

8.60 8.18 3.73 3.78 10.66 10.24

7.17 6.82 3.11 3.15 8.88 8.53

8.60 8.18 3.73 3.78 10.66 10.24

7.17 6.82 3.11 3.15 8.88 8.53

Std.

–1

Std.

–1

Std.

–1

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-58 • 1.5 V LVCMOS High Slew

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 3.0 V

Applicable to MSS I/O Banks

Drive

Strength

Speed

Grade

t_DOUT

0.22

t_DP

3.24

2.70

t_DIN

0.09

0.07

t_PY

t_PYS

1.86

1.55

t_EOUT

0.22

t_ZL

t_ZH

t_LZ

t_HZUnits

2 mA

Std.

–1

1.28

1.07

3.30

2.75

3.20

2.67

2.24 2.21

1.87 1.85

ns

0.18

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

2-38

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus

applications.

Table 2-59 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X

VIL

VIH

Max.

VOL

VOH I_OLI_OH

Min.

I_OSL

I_OSH

I_ILI_IH

Min.

V

Max.

V

Min.

V

Max.

V

Max.

mA¹

Max.

mA¹

Drive Strength

Per PCI specification

Notes:

V

mA mA

µA²µA²

Per PCI curves

15 15

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; SoC Products Group loadings

for enable path characterization are described in Figure 2-10.

R to VCCXXXXIOBX for t_LZ/ t_ZL/ t_ZLS

R to VCCXXXXIOBX for t_DP(F)

R = 25

Test Point

R = 1 k

R to GND for t_HZ/ t_ZH/ t_ZHS

R to GND for t_DP(R)

Test Point

Enable Path

10 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

10 pF for t_HZ/ t_LZ

Datapath

Figure 2-10 • AC Loading

AC loadings are defined per PCI/PCI-X specifications for the datapath; SoC Products Group loading for

tristate is described in Table 2-60.

Table 2-60 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V) Input High (V)

3.3

Measuring Point* (V)

V_REF(typ.) (V)

C_LOAD(pF)

0

0.285 * VCCxxxxIOBx for t_DP(R)

0.615 * VCCxxxxIOBx for t_DP(F)

–

10

* Measuring point = V_trip.See Table 2-22 on page 2-24 for a complete table of trip points.

Timing Characteristics

Table 2-61 • 3.3 V PCI

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 3.0 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Speed Grade t_DOUT

t_DP

2.54

2.11

t_DIN

0.04

0.03

t_PY

t_EOUT

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.64

3.87

t_ZHS

3.94

3.28

Units

Std.

–1

0.60

0.50

0.82

0.68

2.58

2.15

1.88

1.57

3.06

2.55

3.39

2.82

ns

0.32

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Table 2-62 • 3.3 V PCI-X

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCxxxxIOBx = 3.0 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Speed Grade t_DOUT

t_DP

2.54

2.11

t_DIN

0.04

0.03

t_PY

t_EOUT

0.39

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.64

3.87

t_ZHS

3.94

3.28

Units

ns

Std.

–1

0.60

0.50

0.77

0.64

2.58

2.15

1.88

1.57

3.06

2.55

3.39

2.82

0.32

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Revision 10

2-39

SmartFusion DC and Switching Characteristics

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by SoC Products Group Designer

software when the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no

support for bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-11. The

building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVPECL implementation because the output standard

specifications are different.

Along with LVDS I/O, SmartFusion cSoCs also support bus LVDS structure and multipoint LVDS

(M-LVDS) configuration (up to 40 nodes).

Bourns Part Number: CAT16-LV4F12

FPGA

OUTBUF_LVDS

P

N

P

N

165 

Z₀= 50 

140 

Z₀= 50 

INBUF_LVDS

+

–

100 

Figure 2-11 • LVDS Circuit Diagram and Board-Level Implementation

2-40

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Table 2-63 • LVDS Minimum and Maximum DC Input and Output Levels

DC Parameter

VCCFPGAIOBx

VOL

Description

Supply voltage

Min.

2.375

0.9

Typ.

2.5

Max.

2.625

1.25

1.6

Units

V

Output low voltage

1.075

1.425

0.91

V

VOH

Output high voltage

1.25

0.65

0

V

1

I_OL

Output lower current

1.16

2.925

15

mA

V

1

I_OH

Output high current

VI

Input voltage

2

I_IH

Input high leakage current

Input low leakage current

Differential output voltage

Output common mode voltage

Input common mode voltage

Input differential voltage

µA

mV

V

2

I_IL

15

V_ODIFF

V_OCM

V_ICM

250

1.125

0.05

100

350

1.25

350

450

1.375

2.35

V

V_IDIFF

Notes:

mV

1.

I

/I defined by V

/(resistor network).

OL OH

ODIFF

2. Currents are measured at 85°C junction temperature.

Table 2-64 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

Cross point

V_REF(typ.) (V)

1.075

1.325

–

* Measuring point = V_trip.See Table 2-22 on page 2-24 for a complete table of trip points.

Timing Characteristics

Table 2-65 • LVDS

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCFPGAIOBx = 2.3 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Speed Grade

t_DOUT

0.60

t_DP

1.83

1.53

t_DIN

0.04

0.03

t_PY

Units

ns

Std.

1.87

1.55

–1

0.50

ns

Notes:

1. For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for

derating values.

2. The above mentioned timing parameters correspond to 24mA drive strength.

Revision 10

2-41

SmartFusion DC and Switching Characteristics

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to

high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain

any combination of drivers, receivers, and transceivers. SoC Products Group LVDS drivers provide the

higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require

series terminations for better signal quality and to control voltage swing. Termination is also required at

both ends of the bus since the driver can be located anywhere on the bus. These configurations can be

implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.

Multipoint designs using SoC Products Group LVDS macros can achieve up to 200 MHz with a maximum

of 20 loads. A sample application is given in Figure 2-12. The input and output buffer delays are available

in the LVDS section in Table 2-65.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required

differential voltage, in worst-case commercial operating conditions, at the farthest receiver: R_S= 60 

and R_T= 70 , given Z₀= 50  (2") and Z_stub= 50  (~1.5").

Receiver

Transceiver

Driver

D

Receiver

Transceiver

EN

BIBUF_LVDS

R

T

R

T

+

-

+

-

+

-

+

-

+

-

R_SR_S

Z_stub

R_SR_S

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

...

Z₀

R_T

Z₀

Figure 2-12 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires

that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-13. The

building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVDS implementation because the output standard

specifications are different.

Bourns Part Number: CAT16-PC4F12

FPGA

P

N

OUTBUF_LVPECL

100 

Z₀= 50 

187 W

INBUF_LVPECL

+

–

100 

Z₀= 50 

N

Figure 2-13 • LVPECL Circuit Diagram and Board-Level Implementation

2-42

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Table 2-66 • Minimum and Maximum DC Input and Output Levels

DC Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

V

VCCFPGAIOBx Supply Voltage

3.0

3.3

3.6

VOL

Output Low Voltage

0.96

1.8

1.27

2.11

3.6

1.06

1.92

0

1.43

2.28

3.6

1.30

2.13

0

1.57

2.41

3.6

V

VOH

Output High Voltage

V

VIL, VIH

VODIFF

VOCM

VICM

Input Low, Input High Voltages

Differential Output Voltage

Output Common-Mode Voltage

Input Common-Mode Voltage

Input Differential Voltage

0

V

0.625

1.762

1.01

300

0.97

1.98

2.57

0.625

1.762

1.01

300

0.97

1.98

2.57

0.625

1.762

1.01

300

0.97

1.98

2.57

V

VIDIFF

mV

Table 2-67 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

V

_REF(typ.) (V)

1.64

1.94

Cross point

–

* Measuring point = V_trip.See Table 2-22 on page 2-24 for a complete table of trip points.

Timing Characteristics

Table 2-68 • LVPECL

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCFPGAIOBx = 3.0 V

Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins

Speed Grade

t_DOUT

0.60

t_DP

1.76

1.46

t_DIN

0.04

0.03

t_PY

Units

ns

Std.

1.76

1.46

–1

0.50

ns

Notes:

1. For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for

derating values.

2. The above mentioned timing parameters correspond to 24mA drive strength.

Revision 10

2-43

SmartFusion DC and Switching Characteristics

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Preset

Preset

L

D

DOUT

Data_out

PRE

F

PRE

Y

E

Core

Array

Data

Enable

CLK

D

Q

D

Q

C

DFN1E1P1

G

E

EOUT

B

A

H

I

PRE

J

D

Q

DFN1E1P1

K

Data Input I/O Register with:

Active High Enable

E

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

CLKBUF

INBUF

Postive-Edge Triggered

Figure 2-14 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

2-44

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Table 2-69 • Parameter Definition and Measuring Nodes

Measuring Nodes

Parameter Name

Parameter Definition

(from, to)*

H, DOUT

F, H

t_OCLKQ

t_OSUD

Clock-to-Q of the Output Data Register

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

F, H

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

G, H

t_OHE

G, H

t_OPRE2Q

t_OREMPRE

t_ORECPRE

t_OECLKQ

t_OESUD

t_OEHD

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

L, DOUT

L, H

H, EOUT

J, H

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

J, H

t_OESUE

t_OEHE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

K, H

t_OEPRE2Q

t_OEREMPRE

t_OERECPRE

t_ICLKQ

I, EOUT

I, H

A, E

t_ISUD

Data Setup Time for the Input Data Register

C, A

t_IHD

Data Hold Time for the Input Data Register

C, A

t_ISUE

Enable Setup Time for the Input Data Register

B, A

t_IHE

Enable Hold Time for the Input Data Register

B, A

t_IPRE2Q

t_IREMPRE

t_IRECPRE

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

D, E

D, A

* See Figure 2-14 on page 2-44 for more information.

Revision 10

2-45

SmartFusion DC and Switching Characteristics

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Clear

DOUT

FF

Data_out

Y

Core

D

Q

D

Q

Data

Array

CC

EE

DFN1E1C1

GG

EOUT

E

Enable

CLK

BB

AA

CLR

LL

HH

JJ

D

Q

CLR

DD

DFN1E1C1

KK

E

Data Input I/O Register with

Active High Enable

CLR

Active High Clear

Data Output Register and

Enable Output Register with

Active High Enable

Positive-Edge Triggered

Active High Clear

Positive-Edge Triggered

INBUF

CLKBUF

Figure 2-15 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

2-46

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Table 2-70 • Parameter Definition and Measuring Nodes

Measuring Nodes

Parameter Name

Parameter Definition

(from, to)*

HH, DOUT

FF, HH

t_OCLKQ

t_OSUD

Clock-to-Q of the Output Data Register

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

FF, HH

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

GG, HH

LL, DOUT

LL, HH

t_OHE

t_OCLR2Q

t_OREMCLR

t_ORECCLR

t_OECLKQ

t_OESUD

t_OEHD

LL, HH

HH, EOUT

JJ, HH

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

JJ, HH

t_OESUE

t_OEHE

KK, HH

II, EOUT

II, HH

t_OECLR2Q

t_OEREMCLR

t_OERECCLR

t_ICLKQ

II, HH

AA, EE

CC, AA

BB, AA

DD, EE

DD, AA

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IREMCLR

t_IRECCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

* See Figure 2-15 on page 2-46 for more information.

Revision 10

2-47

SmartFusion DC and Switching Characteristics

Input Register

t_ICKMPWHt_ICKMPWL

50%

CLK

t_IHD

t_ISUD

50%

1

0

Data

t_IREMPRE

t_IRECPRE

t_IWPRE

Enable

Preset

50%

t_IHE

t_ISUE

50%

t_IWCLR

t_IRECCLR

50%

t_IREMCLR

50%

Clear

t_IPRE2Q

50%

t_ICLKQ

50%

Out_1

t_ICLR2Q

Figure 2-16 • Input Register Timing Diagram

Timing Characteristics

Table 2-71 • Input Data Register Propagation Delays

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V

Parameter

t_ICLKQ

Description

–1

Std. Units

Clock-to-Q of the Input Data Register

0.24 0.29

0.27 0.32

0.00 0.00

0.38 0.45

0.00 0.00

0.46 0.55

0.00 0.00

0.23 0.27

0.00 0.00

0.23 0.27

0.22 0.22

0.36 0.36

0.32 0.32

ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width High for the Input Data Register

Clock Minimum Pulse Width Low for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9

for derating values.

2-48

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Output Register

t_OCKMPWHt_OCKMPWL

50%

CLK

t_OSUDt_OHD

50%

1

0

Data_out

t_OREMPRE

Enable

Preset

50%

t_OWPREt_ORECPRE

50%

t_OHE

50%

t_OSUE

t_OREMCLR

50%

t_ORECCLR

50%

t_OWCLR

50%

Clear

t_OPRE2Q

50%

t_OCLKQ

50%

DOUT

t_OCLR2Q

Figure 2-17 • Output Register Timing Diagram

Timing Characteristics

Table 2-72 • Output Data Register Propagation Delays

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V

Parameter

t_OCLKQ

Description

–1

Std. Units

Clock-to-Q of the Output Data Register

0.60 0.72

0.32 0.38

ns

t_OSUD

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

0.00 0.00

0.44 0.53

0.00 0.00

0.82 0.98

0.00 0.00

0.23 0.27

0.00 0.00

0.23 0.27

0.22 0.22

0.36 0.36

0.32 0.32

t_OSUE

Enable Setup Time for the Output Data Register

t_OHE

Enable Hold Time for the Output Data Register

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

t_OWPRE

t_OCKMPWH

t_OCKMPWL

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Asynchronous Clear Minimum Pulse Width for the Output Data Register

Asynchronous Preset Minimum Pulse Width for the Output Data Register

Clock Minimum Pulse Width High for the Output Data Register

Clock Minimum Pulse Width Low for the Output Data Register

Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on

page 2-9 for derating values.

Revision 10

2-49

SmartFusion DC and Switching Characteristics

Output Enable Register

t_OECKMPWHt_OECKMPWL

50%

CLK

t_{OESUD OEHD}

t

50% 50%

1

0

D_Enable

50%

Enable

Preset

t_OEWPRE

50%

t_OEREMPRE

50%

t_OERECPRE

50%

t_OESUEOEHE

t

t_OEREMCLR

50%

t_OEWCLRt_OERECCLR

50%

Clear

t_OECLR2Q

50%

t_OEPRE2Q

50%

t_OECLKQ

EOUT

Figure 2-18 • Output Enable Register Timing Diagram

Timing Characteristics

Table 2-73 • Output Enable Register Propagation Delays

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V

Parameter

t_OECLKQ

Description

–1

Std. Units

Clock-to-Q of the Output Enable Register

0.45 0.54

0.32 0.38

0.00 0.00

0.44 0.53

0.00 0.00

0.68 0.81

0.00 0.00

0.23 0.27

0.00 0.00

0.23 0.27

0.22 0.22

0.36 0.36

0.32 0.32

ns

t_OESUD

Data Setup Time for the Output Enable Register

t_OEHD

Data Hold Time for the Output Enable Register

t_OESUE

Enable Setup Time for the Output Enable Register

t_OEHE

Enable Hold Time for the Output Enable Register

t_OECLR2Q

t_OEPRE2Q

t_OEREMCLR

t_OERECCLR

t_OEREMPRE

t_OERECPRE

t_OEWCLR

t_OEWPRE

t_OECKMPWH

t_OECKMPWL

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Asynchronous Clear Minimum Pulse Width for the Output Enable Register

Asynchronous Preset Minimum Pulse Width for the Output Enable Register

Clock Minimum Pulse Width High for the Output Enable Register

Clock Minimum Pulse Width Low for the Output Enable Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

2-50

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

DDR Module Specifications

Input DDR Module

Input DDR

INBUF

A

D

Out_QF

(to core)

Data

FF1

B

E

Out_QR

(to core)

CLK

CLKBUF

FF2

C

CLR

INBUF

DDR_IN

Figure 2-19 • Input DDR Timing Model

Table 2-74 • Parameter Definitions

Parameter Name

Parameter Definition

Measuring Nodes (from, to)

t_DDRICLKQ1

t_DDRICLKQ2

t_DDRISUD

Clock-to-Out Out_QR

Clock-to-Out Out_QF

Data Setup Time of DDR input

Data Hold Time of DDR input

Clear-to-Out Out_QR

Clear-to-Out Out_QF

Clear Removal

B, D

B, E

A, B

C, D

C, E

C, B

t_DDRIHD

t_DDRICLR2Q1

t_DDRICLR2Q2

t_DDRIREMCLR

t_DDRIRECCLR

Clear Recovery

Revision 10

2-51

SmartFusion DC and Switching Characteristics

CLK

t_DDRISUD

6

t_DDRIHD

8

Data

CLR

1

2

3

4

5

7

9

t_DDRIRECCLR

t_DDRIREMCLR

t_DDRICLKQ1

t_DDRICLR2Q1

Out_QF

Out_QR

6

2

4

t_DDRICLKQ2

t_DDRICLR2Q2

7

3

5

Figure 2-20 • Input DDR Timing Diagram

Timing Characteristics

Table 2-75 • Input DDR Propagation Delays

Worst Commercial-Case Conditions: T_J= 85°C, Worst Case VCC = 1.425 V

Parameter

t_DDRICLKQ1

t_DDRICLKQ2

t_DDRISUD

Description

–1

Units

Clock-to-Out Out_QR for Input DDR

Clock-to-Out Out_QF for Input DDR

0.39

0.28

0.29

0.00

0.58

0.47

0.00

0.23

0.22

0.36

0.32

350

ns

Data Setup for Input DDR

ns

t_DDRIHD

Data Hold for Input DDR

ns

t_DDRICLR2Q1

t_DDRICLR2Q2

Asynchronous Clear-to-Out Out_QR for Input DDR

Asynchronous Clear-to-Out Out_QF for Input DDR

ns

t_DDRIREMCLR

t_DDRIRECCLR

t_DDRIWCLR

Asynchronous Clear Removal time for Input DDR

Asynchronous Clear Recovery time for Input DDR

Asynchronous Clear Minimum Pulse Width for Input DDR

Clock Minimum Pulse Width High for Input DDR

Clock Minimum Pulse Width Low for Input DDR

Maximum Frequency for Input DDR

ns

t_DDRICKMPWH

t_DDRICKMPWL

F_DDRIMAX

ns

MHz

Note: For derating values at specific junction temperature and voltage-supply levels, refer to Table 2-7 on page 2-9 for

derating values.

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Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Output DDR Module

Output DDR

A

B

Data_F

(from core)

X

FF1

Out

0

1

CLK

E

X

CLKBUF

C

X

OUTBUF

D

Data_R

(from core)

X

FF2

B

X

CLR

INBUF

C

X

DDR_OUT

Figure 2-21 • Output DDR Timing Model

Table 2-76 • Parameter Definitions

Parameter Name

t_DDROCLKQ

Parameter Definition

Measuring Nodes (from, to)

Clock-to-Out

B, E

C, E

C, B

A, B

D, B

A, B

D, B

t_DDROCLR2Q

t_DDROREMCLR

t_DDRORECCLR

t_DDROSUD1

Asynchronous Clear-to-Out

Clear Removal

Clear Recovery

Data Setup Data_F

Data Setup Data_R

Data Hold Data_F

Data Hold Data_R

t_DDROSUD2

t_DDROHD1

t_DDROHD2

Revision 10

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SmartFusion DC and Switching Characteristics

CLK

t

DDROHD2

DDROSUD2

4

9

5

Data_F

1

2

3

t

DDROHD1

DDROREMCLR

Data_R 6

CLR

7

8

10

11

t

DDRORECCLR

t

DDROREMCLR

t

DDROCLKQ

DDROCLR2Q

Out

7

2

8

3

9

4

10

Figure 2-22 • Output DDR Timing Diagram

Timing Characteristics

Table 2-77 • Output DDR Propagation Delays

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V

Parameter

t_DDROCLKQ

t_DDROSUD1

t_DDROSUD2

t_DDROHD1

Description

–1

Units

ns

Clock-to-Out of DDR for Output DDR

Data_F Data Setup for Output DDR

0.71

0.38

0.00

0.81

0.00

0.23

0.22

0.36

0.32

350

ns

Data_R Data Setup for Output DDR

Data_F Data Hold for Output DDR

ns

t_DDROHD2

Data_R Data Hold for Output DDR

ns

t_DDROCLR2Q

Asynchronous Clear-to-Out for Output DDR

ns

t_DDROREMCLR

t_DDRORECCLR

t_DDROWCLR1

t_DDROCKMPWH

t_DDROCKMPWL

F_DDOMAX

Asynchronous Clear Removal Time for Output DDR

Asynchronous Clear Recovery Time for Output DDR

Asynchronous Clear Minimum Pulse Width for Output DDR

Clock Minimum Pulse Width High for the Output DDR

Clock Minimum Pulse Width Low for the Output DDR

Maximum Frequency for the Output DDR

ns

MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

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Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

VersaTile Characteristics

VersaTile Specifications as a Combinatorial Module

The SmartFusion library offers all combinations of LUT-3 combinatorial functions. In this section, timing

characteristics are presented for a sample of the library. For more details, refer to the IGLOO/e, Fusion,

ProASIC3/E, and SmartFusion Macro Library Guide.

A

Y

INV

A

B

NOR2

OR2

Y

B

A

B

A

B

Y

AND2

Y

NAND2

XOR3

A

B

C

A

B

Y

XOR2

Y

A

B

C

A

MAJ3

0

Y

A

B

C

MUX2

Y

B

S

NAND3

1

Figure 2-23 • Sample of Combinatorial Cells

Revision 10

2-55

SmartFusion DC and Switching Characteristics

t_PD

A

B

NAND2 or

Any Combinatorial

Logic

Y

t_PD= MAX(t_PD(RR), t_PD(RF)

,

t_PD(FF), t_PD(FR)) where edges are

applicable for the particular

combinatorial cell

VCC

50%

A, B, C

GND

50%

VCC

50%

OUT

GND

VCC

t_PD

(FF)

(RR)

t_PD

(FR)

50%

t_PD

GND

(RF)

Figure 2-24 • Timing Model and Waveforms

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Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Timing Characteristics

Table 2-78 • Combinatorial Cell Propagation Delays

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V

Combinatorial Cell

INV

Equation

Y = !A

Parameter

t_PD

–1

Std.

0.49

0.57

0.59

0.90

0.85

1.07

0.62

0.68

Units

ns

0.41

0.48

0.49

0.75

0.71

0.89

0.51

0.57

AND2

Y = A · B

t_PD

ns

NAND2

OR2

Y = !(A · B)

Y = A + B

t_PD

ns

t_PD

ns

NOR2

Y = !(A + B)

Y = A B

Y = MAJ(A, B, C)

^{Y = A} B C

Y = A !S + B S

Y = A · B · C

t_PD

ns

XOR2

t_PD

ns

MAJ3

t_PD

ns

XOR3

t_PD

ns

MUX2

t_PD

ns

AND3

t_PD

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for

derating values.

VersaTile Specifications as a Sequential Module

The SmartFusion library offers a wide variety of sequential cells, including flip-flops and latches. Each

has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented

for a representative sample from the library. For more details, refer to the IGLOO/e, Fusion, ProASIC3/E,

and SmartFusion Macro Library Guide.

Data

CLK

Out

Data

Out

D

Q

D

Q

En

DFN1

DFN1E1

CLK

PRE

Data

Out

Q

D

Q

En

DFN1C1

DFI1E1P1

CLK

CLR

Figure 2-25 • Sample of Sequential Cells

Revision 10

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SmartFusion DC and Switching Characteristics

t_{CKMPWH CKMPWL}

t

50%

CLK

t_HD

t_SUD

50%

Data

EN

0

50%

t_RECPRE

50%

t_WPRE

t_REMPRE

50%

t_HE

50%

t_SUE

PRE

CLR

Out

t_REMCLR

50%

t_RECCLR

50%

t_WCLR

50%

t_PRE2Q

50%

t_CLR2Q

50%

t_CLKQ

Figure 2-26 • Timing Model and Waveforms

Timing Characteristics

Table 2-79 • Register Delays

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V

Parameter

t_CLKQ

Description

–1

Std.

0.67

0.52

0.00

0.55

0.00

0.49

0.00

0.27

0.00

0.27

0.22

0.32

0.36

Units

Clock-to-Q of the Core Register

0.56

0.44

0.00

0.46

0.00

0.41

0.00

0.23

0.00

0.23

0.22

0.32

0.36

ns

t_SUD

Data Setup Time for the Core Register

t_HD

Data Hold Time for the Core Register

t_SUE

Enable Setup Time for the Core Register

t_HE

Enable Hold Time for the Core Register

t_CLR2Q

t_PRE2Q

t_REMCLR

t_RECCLR

t_REMPRE

t_RECPRE

t_WCLR

Asynchronous Clear-to-Q of the Core Register

Asynchronous Preset-to-Q of the Core Register

Asynchronous Clear Removal Time for the Core Register

Asynchronous Clear Recovery Time for the Core Register

Asynchronous Preset Removal Time for the Core Register

Asynchronous Preset Recovery Time for the Core Register

Asynchronous Clear Minimum Pulse Width for the Core Register

Asynchronous Preset Minimum Pulse Width for the Core Register

Clock Minimum Pulse Width High for the Core Register

Clock Minimum Pulse Width Low for the Core Register

t_WPRE

t_CKMPWH

t_CKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

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Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Global Resource Characteristics

A2F200 Clock Tree Topology

Clock delays are device-specific. Figure 2-27 is an example of a global tree used for clock routing. The

global tree presented in Figure 2-27 is driven by a CCC located on the west side of the A2F200 device. It

is used to drive all D-flip-flops in the device.

Central

Global Rib

CCC

VersaTile

Rows

Global Spine

Figure 2-27 • Example of Global Tree Use in an A2F200 Device for Clock Routing

Global Tree Timing Characteristics

Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not

include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven

and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer

to the "Clock Conditioning Circuits" section on page 2-63. Table 2-80 through Table 2-82 on page 2-61

present minimum and maximum global clock delays for the SmartFusion cSoCs. Minimum and maximum

delays are measured with minimum and maximum loading.

Revision 10

2-59

SmartFusion DC and Switching Characteristics

Timing Characteristics

Table 2-80 • A2F500 Global Resource

Worst Commercial-Case Conditions: T_J= 85°C, VCC = 1.425 V

–1

Min.¹Max.²Min.¹Max.²Units

Std.

Parameter Description

t_RCKL

Input Low Delay for Global Clock

1.54

1.53

0.85

1.73

1.76

1.84

1.00

2.08

2.12

ns

t_RCKH

Input High Delay for Global Clock

t_RCKMPWH

t_RCKMPWL

t_RCKSW

Notes:

Minimum Pulse Width High for Global Clock

Minimum Pulse Width Low for Global Clock

Maximum Skew for Global Clock

0.23

0.28

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-7 on page 2-9 for derating

values.

Table 2-81 • A2F200 Global Resource

Worst Commercial-Case Conditions: T_J= 85°C, VCC = 1.425 V

–1

Std.

Parameter Description

Min.¹Max.²Min.¹Max.²Units

t_RCKL

Input Low Delay for Global Clock

0.74

0.76

0.85

0.99

1.05

0.88

0.91

1.00

1.19

1.26

ns

t_RCKH

Input High Delay for Global Clock

t_RCKMPWH

t_RCKMPWL

t_RCKSW

Notes:

Minimum Pulse Width High for Global Clock

Minimum Pulse Width Low for Global Clock

Maximum Skew for Global Clock

0.29

0.35

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-7 on page 2-9 for derating

values.

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Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Table 2-82 • A2F060 Global Resource

Worst Commercial-Case Conditions: T_J= 85°C, VCC = 1.425 V

–1

Std.

Parameter Description

Min.¹Max.²Min.¹Max.²Units

t_RCKL

Input Low Delay for Global Clock

0.75

0.72

0.85

0.96

0.98

0.90

0.86

1.00

1.15

1.17

ns

t_RCKH

Input High Delay for Global Clock

t_RCKMPWH

t_RCKMPWL

t_RCKSW

Notes:

Minimum Pulse Width High for Global Clock

Minimum Pulse Width Low for Global Clock

Maximum Skew for Global Clock

0.26

0.31

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage-supply levels, refer to Table 2-7 on page 2-9 for derating

values.

RC Oscillator

The table below describes the electrical characteristics of the RC oscillator.

RC Oscillator Characteristics

Table 2-83 • Electrical Characteristics of the RC Oscillator

Parameter

Description

Condition

Min. Typ. Max. Units

FRC

Operating

100

MHz

frequency

Accuracy

Temperature: –40°C to 100°C

Voltage: 3.3 V ± 5%

1

%

Output jitter

Period jitter (at 5 K cycles)

100

150

ps RMS

Cycle-to-cycle jitter (at 5 K cycles)

Period jitter (at 5 K cycles) with 1 KHz / 300

mV peak-to-peak noise on power supply

Cycle-to-cycle jitter (at 5 K cycles) with 1 KHz

/ 300 mV peak-to-peak noise on power

supply

150

ps RMS

Output duty cycle

50

1

%

IDYNRC Operating current 3.3 V domain

1.5 V domain

mA

2

Revision 10

2-61

SmartFusion DC and Switching Characteristics

Main and Lower Power Crystal Oscillator

The tables below describes the electrical characteristics of the main and low power crystal oscillator.

Table 2-84 • Electrical Characteristics of the Main Crystal Oscillator

Parameter

Description

Operating frequency

Condition

Using external crystal

Using ceramic resonator

Using RC Network

Min.

0.032

0.5

Typ.

Max.

20

8

Units

MHz

%

0.032

4

Output duty cycle

Output jitter

50

1

With 10 MHz crystal

RC

nsRMS

mA

IDYNXTAL Operating current

0.6

10

0.032–0.2

0.2–2.0

mA

2.0–20.0

mA

ISTBXTAL Standby current of crystal oscillator

PSRRXTAL Power supply noise tolerance

µA

0.5

Vp-p

V

VIHXTAL

Input logic level High

Input logic level Low

Startup time

90%

of

VCC

VILXTAL

10%

of

VCC

V

RC [Tested at 3.24Mhz]

300

500

8

550

3,000

12

µs

0.032–0.2 [Tested at 32KHz]

0.2–2.0 [Tested at 2MHz]

2.0–20.0 [Tested at 20MHz]

160

180

Table 2-85 • Electrical Characteristics of the Low Power Oscillator

Parameter Description Condition

Operating frequency

Min.

Typ.

Max.

Units

32

50

30

10

2

KHz

Output duty cycle

Output jitter

%

ns RMS

IDYNXTAL Operating current

32 KHz

µA

Vp-p

V

ISTBXTAL Standby current of crystal oscillator

PSRRXTAL Power supply noise tolerance

VIHXTAL Input logic level High

0.5

90% of VCC

VILXTAL

Input logic level Low

Startup time

10% of VCC

13

V

Test load used: 20 pF

Test load used: 30 pF

2.5

3.7

s

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Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Clock Conditioning Circuits

CCC Electrical Specifications

Timing Characteristics

Table 2-86 • SmartFusion CCC/PLL Specification

Parameter

Minimum

1.5

Typical

Maximum

350

Units

MHz

ps

Clock Conditioning Circuitry Input Frequency f_{IN_CCC}

Clock Conditioning Circuitry Output Frequency f_{OUT_CCC}

Delay Increments in Programmable Delay Blocks^2,3,4

0.75

350¹

160

Number of Programmable Values in Each

Programmable Delay Block

32

Input Period Jitter

1.5

ns

Acquisition Time

LockControl = 0

300

6.0

µs

LockControl = 1

ms

Tracking Jitter⁵

LockControl = 0

1.6

0.8

ns

%

LockControl = 1

Output Duty Cycle

48.5

0.6

5.15

5.56

Delay Range in Block: Programmable Delay 1^2,3

Delay Range in Block: Programmable Delay 2^2,3

Delay Range in Block: Fixed Delay^2,3

ns

0.025

2.2

6,7

CCC Output Peak-to-Peak Period Jitter F_{CCC_OUT}

Maximum Peak-to-Peak Period Jitter

SSO  4 SSO  8 SSO  16

SSO  2

FG/CS PQ FG/CS PQ FG/CS PQ FG/CS PQ

0.5% 1.6% 0.9% 1.6% 0.9% 1.6% 0.9% 1.8%

1.75% 3.5% 9.3% 9.3% 9.3% 17.9% 10.0% 17.9%

2.5% 5.2% 13.0% 13.0% 13.0% 25.0% 14.0% 25.0%

0.75 MHz to 50 MHz

50 MHz to 250 MHz

250 MHz to 350 MHz

Notes:

1. One of the CCC outputs (GLA0) is used as an MSS clock and is limited to 100 MHz (maximum) by software. Details

regarding CCC/PLL are in the "PLLs, Clock Conditioning Circuitry, and On-Chip Crystal Oscillators" chapter of the

SmartFusion Microcontroller Subsystem User's Guide.

2. This delay is a function of voltage and temperature. See Table 2-7 on page 2-9 for deratings.

3. T = 25°C, VCC = 1.5 V

J

4. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay

increments are available. Refer to the Libero SoC Online Help associated with the core for more information.

5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge.

Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.

6. Measurement done with LVTTL 3.3 V 12 mA I/O drive strength and High slew rate. VCC/VCCPLL = 1.425 V,

VCCI = 3.3V, 20 pF output load. All I/Os are placed outside of the PLL bank.

7. SSOs are outputs that are synchronous to a single clock domain and have their clock-to-out within ± 200 ps of each other.

8. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying

the VCO period by the % jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For

example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps.

Revision 10

2-63

SmartFusion DC and Switching Characteristics

Output Signal

T_{period_max}

T_{period_min}

Note: Peak-to-peak jitter measurements are defined by T_peak-to-peak= T_{period_max}– T_{period_min}

.

Figure 2-28 • Peak-to-Peak Jitter Definition

2-64

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

FPGA Fabric SRAM and FIFO Characteristics

FPGA Fabric SRAM

RAM4K9

RAM512X18

RADDR8

RD17

RD16

ADDRA11 DOUTA8

RADDR7

DOUTA7

DOUTA0

ADDRA10

ADDRA0

DINA8

RADDR0

RD0

DINA7

RW1

RW0

DINA0

WIDTHA1

WIDTHA0

PIPEA

PIPE

WMODEA

BLKA

WENA

REN

RCLK

CLKA

ADDRB11 DOUTB8

ADDRB10 DOUTB7

WADDR8

WADDR7

ADDRB0

DOUTB0

WADDR0

WD17

WD16

DINB8

DINB7

WD0

DINB0

WW1

WW0

WIDTHB1

WIDTHB0

PIPEB

WMODEB

BLKB

WEN

WCLK

WENB

CLKB

RESET

Figure 2-29 • RAM Models

Revision 10

2-65

SmartFusion DC and Switching Characteristics

Timing Waveforms

t

CYC

t

CKL

CKH

CLK

[R|W]ADDR

BLK

t

AH

AS

A

0

1

2

t

BKS

t

BKH

t

ENS

ENH

WEN

t

CKQ1

D

2

DOUT|RD

n

0

1

t

DOH1

Figure 2-30 • RAM Read for Pass-Through Output. Applicable to both RAM4K9 and RAM512x18.

t_CYC

t_CKH

t_CKL

CLK

[R|W]ADDR

BLK

t_ASt_AH

A₀

A₁

A₂

t_BKS

t_BKH

t_ENS

t_ENH

WEN

t_CKQ2

D_n

D₀

D₁

DOUT|RD

t_DOH2

Figure 2-31 • RAM Read for Pipelined Output Applicable to both RAM4K9 and RAM512x18.

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Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

t

CYC

t

CKL

CKH

CLK

[R|W]ADDR

BLK

t

AH

AS

A

0

1

2

t

BKS

ENS

t

BKH

t

ENH

WEN

t

DS

DH

DI

1

DIN|WD

DOUT|RD

0

D

2

n

Figure 2-32 • RAM Write, Output Retained. Applicable to both RAM4K9 and RAM512x18.

t

CYC

t

CKH

CKL

CLK

ADDR

BLK

t

AH

AS

A

2

0

1

t

BKS

t

BKH

ENS

WEN

DIN

t

DH

DS

DI

2

0

1

DOUT

D

DI

1

n

0

(pass-through)

DOUT

DI

D

DI

1

0

n

(pipelined)

Figure 2-33 • RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 only.

Revision 10

2-67

SmartFusion DC and Switching Characteristics

t

CYC

t

CKL

CKH

CLK

RESET

t

RSTBQ

D

DOUT|RD

m

n

Figure 2-34 • RAM Reset. Applicable to both RAM4K9 and RAM512x18.

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Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Timing Characteristics

Table 2-87 • RAM4K9

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V

Parameter

t_AS

Description

Address setup time

–1

Std. Units

0.25

0.00

0.15

0.10

0.24

0.02

0.19

0.00

1.81

2.39

0.91

0.30

0.00

0.17

0.12

0.28

0.02

0.22

0.00

2.18

2.87

1.09

0.26

ns

t_AH

Address hold time

t_ENS

t_ENH

t_BKS

t_BKH

t_DS

REN, WEN setup time

REN, WEN hold time

BLK setup time

BLK hold time

Input data (DIN) setup time

t_DH

Input data (DIN) hold time

t_CKQ1

Clock High to new data valid on DOUT (output retained, WMODE = 0)

Clock High to new data valid on DOUT (flow-through, WMODE = 1)

Clock High to new data valid on DOUT (pipelined)

t_CKQ2

1

t_C2CWWH

Address collision clk-to-clk delay for reliable write after write on same 0.23

address—applicable to rising edge

1

t_C2CRWH

Address collision clk-to-clk delay for reliable read access after write on same 0.34

address—applicable to opening edge

0.38

0.42

ns

1

t_C2CWRH

Address collision clk-to-clk delay for reliable write access after read on same 0.37

address— applicable to opening edge

t_RSTBQ

RESET Low to data out Low on DOUT (flow-through)

RESET Low to Data Out Low on DOUT (pipelined)

RESET removal

0.94

0.29

1.52

0.22

3.28

305

1.12

0.35

1.83

0.22

3.28

305

ns

t_REMRSTB

t_RECRSTB

ns

RESET recovery

ns

t_MPWRSTBRESET minimum pulse width

ns

t_CYC

Clock cycle time

ns

F_MAX

Notes:

Maximum clock frequency

MHz

1. For more information, refer to the Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based cSoCs and

FPGAs application note.

2. For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for

derating values.

Revision 10

2-69

SmartFusion DC and Switching Characteristics

Table 2-88 • RAM512X18

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V

Parameter

t_AS

Description

–1

Std.

0.30

0.00

0.11

0.07

0.22

0.00

2.63

1.09

0.43

Units

ns

Address setup time

0.25

0.00

0.09

0.06

0.19

0.00

2.19

0.91

t_AH

Address hold time

ns

t_ENS

REN, WEN setup time

REN, WEN hold time

Input data (WD) setup time

Input data (WD) hold time

ns

t_ENH

t_DS

ns

t_DH

ns

t_CKQ1

t_CKQ2

Clock High to new data valid on RD (output retained, WMODE = 0)

Clock High to new data valid on RD (pipelined)

ns

1

t_C2CRWH

Address collision clk-to-clk delay for reliable read access after write on same 0.38

address—applicable to opening edge

ns

1

t_C2CWRH

Address collision clk-to-clk delay for reliable write access after read on same 0.44

address—applicable to opening edge

0.50

ns

t_RSTBQ

RESET Low to data out Low on RD (flow-through)

RESET Low to data out Low on RD (pipelined)

RESET removal

0.94

0.29

1.52

0.22

3.28

305

1.12

0.35

1.83

0.22

3.28

305

ns

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

ns

RESET recovery

ns

RESET minimum pulse width

Clock cycle time

ns

F_MAX

Maximum clock frequency

MHz

Notes:

1. For more information, refer to the Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based cSoCs and

FPGAs application note.

2. For the derating values at specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for

derating values.

2-70

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

FIFO

FIFO4K18

RW2

RW1

RW0

RD17

RD16

WW2

WW1

WW0

RD0

ESTOP

FSTOP

FULL

AFULL

EMPTY

AEVAL11

AEVAL10

AEMPTY

AEVAL0

AFVAL11

AFVAL10

AFVAL0

REN

RBLK

RCLK

WD17

WD16

WD0

WEN

WBLK

WCLK

RPIPE

RESET

Figure 2-35 • FIFO Model

Revision 10

2-71

SmartFusion DC and Switching Characteristics

Timing Waveforms

t_CYC

RCLK

t_ENH

t_ENS

REN

t_BKS

t_BKH

RBLK

t_CKQ1

RD

D₁

D_n

D₀

D₂

(flow-through)

t_CKQ2

RD

(pipelined)

D_n

D₀

D₁

Figure 2-36 • FIFO Read

t_CYC

WCLK

t_ENS

t_ENH

WEN

t_BKS

t_BKH

WBLK

t_DS

t_DH

DI₁

DI₀

WD

Figure 2-37 • FIFO Write

2-72

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

RCLK/

WCLK

t_MPWRSTB

t_RSTCK

RESET

EMPTY

AEMPTY

FULL

t_RSTFG

t_RSTAF

t_RSTFG

t_RSTAF

AFULL

WA/RA

MATCH (A₀)

(Address Counter)

Figure 2-38 • FIFO Reset

t_CYC

RCLK

t_RCKEF

EMPTY

t_CKAF

AEMPTY

WA/RA

NO MATCH

Dist = AEF_TH

MATCH (EMPTY)

(Address Counter)

Figure 2-39 • FIFO EMPTY Flag and AEMPTY Flag Assertion

Revision 10

2-73

SmartFusion DC and Switching Characteristics

t_CYC

WCLK

FULL

t_WCKFF

t_CKAF

AFULL

WA/RA

NO MATCH

Dist = AFF_TH

MATCH (FULL)

(Address Counter)

Figure 2-40 • FIFO FULL Flag and AFULL Flag Assertion

WCLK

MATCH

WA/RA

NO MATCH

Dist = AEF_TH + 1

(EMPTY)

(Address Counter)

1st Rising

2nd Rising

Edge

After 1st

Write

Edge

After 1st

Write

RCLK

EMPTY

t_RCKEF

t_CKAF

AEMPTY

Figure 2-41 • FIFO EMPTY Flag and AEMPTY Flag Deassertion

RCLK

WA/RA

(Address Counter)

Dist = AFF_TH – 1

MATCH (FULL)

NO MATCH

1st Rising

NO MATCH

1st Rising

Edge

After 1st

Read

Edge

After 2nd

Read

WCLK

FULL

t_WCKF

t_CKAF

AFULL

Figure 2-42 • FIFO FULL Flag and AFULL Flag Deassertion

2-74

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Timing Characteristics

Table 2-89 • FIFO

Worst Commercial-Case Conditions: T_J= 85°C, VCC = 1.425 V

Parameter

t_ENS

Description

–1

Std.

1.68

0.02

0.19

0.00

0.22

0.00

2.87

1.09

2.09

1.99

7.54

2.06

7.47

1.12

0.35

1.83

0.22

3.28

305

Units

ns

REN, WEN Setup Time

1.40

0.02

0.19

0.00

0.19

0.00

2.39

0.91

1.74

1.66

6.29

1.72

6.22

0.94

0.29

1.52

0.22

3.28

305

t_ENH

REN, WEN Hold Time

ns

t_BKS

BLK Setup Time

ns

t_BKH

BLK Hold Time

ns

t_DS

Input Data (WD) Setup Time

ns

t_DH

Input Data (WD) Hold Time

ns

t_CKQ1

t_CKQ2

t_RCKEF

t_WCKFF

t_CKAF

t_RSTFG

t_RSTAF

t_RSTBQ

Clock High to New Data Valid on RD (flow-through)

Clock High to New Data Valid on RD (pipelined)

RCLK High to Empty Flag Valid

WCLK High to Full Flag Valid

ns

Clock HIGH to Almost Empty/Full Flag Valid

RESET Low to Empty/Full Flag Valid

RESET Low to Almost Empty/Full Flag Valid

RESET Low to Data Out Low on RD (flow-through)

RESET Low to Data Out Low on RD (pipelined)

RESET Removal

ns

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

ns

RESET Recovery

ns

RESET Minimum Pulse Width

Clock Cycle Time

ns

F_MAX

Maximum Frequency for FIFO

MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

Embedded Nonvolatile Memory Block (eNVM)

Electrical Characteristics

Table 2-90 describes the eNVM maximum performance.

Table 2-90 • eNVM Block Timing, Worst Commercial Case Conditions: T_J= 85°C, VCC = 1.425 V

A2F060

A2F200

A2F500

Parameter

Description

–1

Std.

–1

Std.

–1

Std. Units

t_FMAXCLKeNVMMaximum frequency for clock for the control logic – 5 80

cycles (5:1:1:1*)

80

50

50 MHz

t_FMAXCLKeNVMMaximum frequency for clock for the control logic – 6 100

80

100

80

100

80 MHz

cycles (6:1:1:1*)

Note: *6:1:1:1 indicates 6 cycles for the first access and 1 each for the next three accesses. 5:1:1:1 indicates 5 cycles

for the first access and 1 each for the next three accesses.

Revision 10

2-75

SmartFusion DC and Switching Characteristics

Embedded FlashROM (eFROM)

Electrical Characteristics

Table 2-91 describes the eFROM maximum performance

Table 2-91 • FlashROM Access Time, Worse Commercial Case Conditions: T_J= 85°C, VCC = 1.425 V

Parameter

t_CK2Q

Description

Clock to out per configuration*

Maximum Clock frequency

–1

Std.

32.98

15.00

Units

ns

28.68

15.00

F_max

MHz

JTAG 1532 Characteristics

JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to

the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O

Characteristics" section on page 2-19 for more details.

Timing Characteristics

Table 2-92 • JTAG 1532

Worst Commercial-Case Conditions: T_J= 85°C, Worst-Case VCC = 1.425 V

Parameter

t_DISU

Description

Test Data Input Setup Time

–1

Std.

0.77

1.53

0.77

1.53

9.20

30.67

21.85

0.00

0.31

TBD

Units

ns

0.67

1.33

0.67

1.33

8.00

26.67

19.00

0.00

0.27

TBD

t_DIHD

Test Data Input Hold Time

Test Mode Select Setup Time

Test Mode Select Hold Time

Clock to Q (data out)

ns

t_TMSSU

ns

t_TMDHD

ns

t_TCK2Q

ns

t_RSTB2Q

F_TCKMAX

t_TRSTREM

t_TRSTREC

t_TRSTMPW

Reset to Q (data out)

ns

TCK Maximum Frequency

ResetB Removal Time

ResetB Recovery Time

ResetB Minimum Pulse

MHz

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.

2-76

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Programmable Analog Specifications

Current Monitor

Unless otherwise noted, current monitor performance is specified at 25°C with nominal power supply

voltages, with the output measured using the internal voltage reference with the internal ADC in 12-bit

mode and 91 Ksps, after digital compensation. All results are based on averaging over 16 samples.

Table 2-93 • Current Monitor Performance Specification

Specification

Test Conditions

Min. Typical

Max.

Units

Input voltage range (for driving ADC

over full range)

0 – 48 0 – 50

1 – 51

mV

Analog gain

From the differential voltage across the

input pads to the ADC input

50

V/V

Input referred offset voltage

–40ºC to +100ºC

0

0.1

0.5

mV

Gain error

Slope of BFSL vs. 50 V/V

–40ºC to +100ºC

±0.1

±0.5

% nom.

Overall Accuracy

Peak error from ideal transfer function,

25°C

±(0.1 + ±(0.4 + mV plus

0.25%) 1.5%)

%

reading

Input referred noise

0 VDC input (no output averaging)

0 V to 12 VDC common-mode voltage

To 0.1% of final value (with ADC load)

From CM_STB (High)

0.3

0.4

0.5

mVrms

dB

Common-mode rejection ratio

Analog settling time

–86

–87

5

µs

pF

From ADC_START (High)

200

Input capacitance

8

Input biased current

CM[n] or TM[n] pad,

–40°C to +100°C over maximum input

voltage range (plus is into pad)

Strobe = 0; IBIAS on CM[n]

Strobe = 1; IBIAS on CM[n]

Strobe = 0; IBIAS on TM[n]

Strobe = 1; IBIAS on TM[n]

DC (0 – 10 KHz)

0

1

µA

dB

µA

2

1

Power supply rejection ratio

41

42

150

140

50

Incremental operational current VCC33A

monitor power supply current

requirements (per current monitor

instance, not including ADC or

VAREFx)

VCC33AP

VCC15A

Note: Under no condition should the TM pad ever be greater than 10 mV above the CM pad. This restriction is

applicable only if current monitor is used.

Revision 10

2-77

SmartFusion DC and Switching Characteristics

Temperature Monitor

Unless otherwise noted, temperature monitor performance is specified with a 2N3904 diode-connected

bipolar transistor from National Semiconductor or Infineon Technologies, nominal power supply voltages,

with the output measured using the internal voltage reference with the internal ADC in 12-bit mode and

62.5 Ksps. After digital compensation. Unless otherwise noted, the specifications pertain to conditions

where the SmartFusion cSoC and the sensing diode are at the same temperature.

Table 2-94 • Temperature Monitor Performance Specifications

Specification

Test Conditions

Min. Typical Max.

Units

°C

Input diode temperature range

–55

150

233.2

378.15

K

Temperature sensitivity

Intercept

2.5

0

mV/K

V

Extrapolated to 0K

Input referred temperature offset At 25°C (298.15K)

error

±1

1.5

°C

Gain error

Slope of BFSL vs. 2.5 mV/K

±1

±2

4

2.5

±3

% nom.

°C

Overall accuracy

Input referred noise

Output current

Peak error from ideal transfer function

At 25°C (298.15K) – no output averaging

Idle mode

°C rms

µA

100

10

Final measurement phases

µA

Analog settling time

Measured to 0.1% of final value, (with

ADC load)

From TM_STB (High)

5

µs

From ADC_START (High)

105

500

AT parasitic capacitance

pF

Power supply rejection ratio

DC (0–10 KHz)

1.2

0.7

°C/V

°C/°C

Input referred temperature

sensitivity error

Variation due to device temperature

(–40°C to +100°C). External temperature

sensor held constant.

0.005

0.008

Temperature monitor (TM)

operational power supply current

requirements (per temperature

monitor instance, not including ADC

or VAREFx)

VCC33A

VCC33AP

VCC15A

200

150

50

µA

Note: All results are based on averaging over 64 samples.

2-78

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

1

0

-1

-2

-3

-4

-5

-6

-7

1.00E -06

1.00E -05

1.00E -04

1.00E -03

1.00E -02

1.00E -01

1.00E+00

Capacitance (μF)

Figure 2-43 • Temperature Error Versus External Capacitance

Revision 10

2-79

SmartFusion DC and Switching Characteristics

Analog-to-Digital Converter (ADC)

Unless otherwise noted, ADC direct input performance is specified at 25°C with nominal power supply

voltages, with the output measured using the external voltage reference with the internal ADC in 12-bit

mode and 500 KHz sampling frequency, after trimming and digital compensation.

Table 2-95 • ADC Specifications

Specification

Test Conditions

Min. Typ. Max.

Units

Input voltage range (for driving ADC

over its full range)

2.56

V

Gain error

±0.4 ±0.7

%

–40ºC to +100ºC

Input referred offset voltage

Integral non-linearity (INL)

±1

±2

mV

–40ºC to +100ºC

RMS deviation from BFSL

12-bit mode

1.71

LSB

dB

10-bit mode

0.60 1.00

8-bit mode

0.2

2.4

0.33

Differential non-linearity (DNL)

12-bit mode

10-bit mode

0.80 0.94

8-bit mode

0.2

64

0.23

Signal to noise ratio

62

Effective number of bits (ENOB)

SINAD – 1.76 dB

–1 dBFS input

12-bit mode 10 KHz

12-bit mode 100 KHz

10-bit mode 10 KHz

10-bit mode 100 KHz

8-bit mode 10 KHz

8-bit mode 100 KHz

At –3 dB; –1 dBFS input

9.9

9.5

7.8

300

10

Bits

KHz

µs

--------------------------------------------

ENOB =

6.02 dB/bit

EQ 10

9.6

7.9

Full power bandwidth

Analog settling time

To 0.1% of final value (with 1 Kohm source

impedance and with ADC load)

2

Input capacitance

Switched capacitance (ADC sample

capacitor)

12

15

pF

Cs: Static capacitance (Figure 2-44 on page 2-81)

CM[n] input

5

2

7

pF

TM[n] input

ADC[n] input

pF

Input resistance

Rin: Series resistance (Figure 2-44)

K

M

Rsh: Shunt resistance, exclusive of

switched capacitance effects (Figure 2-44)

10

Note: All 3.3 V supplies are tied together and varied from 3.0 V to 3.6 V. 1.5 V supplies are held constant.

2-80

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Table 2-95 • ADC Specifications (continued)

Specification

Test Conditions

–40°C to +100°C

DC

Min. Typ. Max.

Units

µA

Input leakage current

1

Power supply rejection ratio

44

53

dB

ADC power supply operational current VCC33ADCx

2.5

2

mA

requirements

VCC15A

Note: All 3.3 V supplies are tied together and varied from 3.0 V to 3.6 V. 1.5 V supplies are held constant.

Rin

Cst

Csw

Rsh

Figure 2-44 • ADC Input Model

Table 2-96 • VAREF Stabilization Time

Required Settling Time for 8-Bit and

10-Bit Mode (ms)

Required Settling Time for 12-Bit

Mode (ms)

VAREF Capacitor Value (µF)

0.01

0.1

0.2

0.3

0.5

0.7

1

3

1

4

6

8

10

11

17

20

18

21

32

37

2.2

3.3

10

62

73

99

117

325

751

1557

275

635

1318

22

47

Revision 10

2-81

SmartFusion DC and Switching Characteristics

Analog Bipolar Prescaler (ABPS)

With the ABPS set to its high range setting (GDEC = 00), a hypothetical input voltage in the range –15.36

V to +15.36 V is scaled and offset by the ABPS input amplifier to match the ADC full range of 0 V to 2.56

V using a nominal gain of –0.08333 V/V. However, due to reliability considerations, the voltage applied to

the ABPS input should never be outside the range of –11.5 V to +14.4 V, restricting the usable ADC input

voltage to 2.238 V to 0.080 V and the corresponding 12-bit output codes to the range of 3581 to 128

(decimal), respectively.

Unless otherwise noted, ABPS performance is specified at 25°C with nominal power supply voltages,

with the output measured using the internal voltage reference with the internal ADC in 12-bit mode and

100 KHz sampling frequency, after trimming and digital compensation; and applies to all ranges.

Table 2-97 • ABPS Performance Specifications

Specification

Test Conditions

Min.

Typ.

±2.56

Max.

Units

Input voltage range (for driving ADC GDEC[1:0] = 11

V

over its full range)

GDEC[1:0] = 10

±5.12

GDEC[1:0] = 01

±10.24

See note 1

GDEC[1:0]

=

00 (limited by

maximum rating)

Analog gain (from input pad to ADC GDEC[1:0] = 11

–0.5

–0.25

–0.125

–0.0833

–0.4

V/V

%

input)

GDEC[1:0] = 10

GDEC[1:0] = 01

GDEC[1:0] = 00

Gain error

–2.8

0.7

–40ºC to +100ºC

Input referred offset voltage

GDEC[1:0] = 11

–0.4

%

–0.31

–1.00

–0.34

–0.90

–0.61

–1.05

–0.39

–1.06

53

–0.07

56

0.31

1.47

0.34

1.37

0.35

1.35

0.35

1.38

% FS*

dB

–40ºC to +100ºC

GDEC[1:0] = 10

–40ºC to +100ºC

GDEC[1:0] = 01

–40ºC to +100ºC

GDEC[1:0] = 00

–40ºC to +100ºC

SINAD

Non-linearity

RMS deviation from BFSL

0.5

% FS*

Note: *FS is full-scale error, defined as the difference between the actual value that triggers the transition to full-scale

and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error. Refer to the

Analog-to-Digital Converter chapter of the SmartFusion Programmable Analog User’s Guide for more

information.

2-82

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Table 2-97 • ABPS Performance Specifications (continued)

Specification

Test Conditions

Min.

Typ.

Max.

Units

Effective number of bits (ENOB)

GDEC[1:0] = 11

(±2.56 range), –1 dBFS input

12-bit mode 10 KHz

12-bit mode 100 KHz

10-bit mode 10 KHz

10-bit mode 100 KHz

8-bit mode 10 KHz

8-bit mode 100 KHz

–1 dBFS input

SINAD – 1.76 dB

--------------------------------------------

ENOB =

8.6

8.5

7.7

9.1

8.9

7.8

1

Bits

MHz

µs

6.02 dB/bit

EQ 11

Large-signal bandwidth

Analog settling time

To 0.1% of final value (with ADC

load)

10

Input resistance

1

M

Power supply rejection ratio

ABPS power supply current

requirements (not including ADC or

VAREFx)

DC (0–1 KHz)

ABPS_EN = 1 (operational mode)

VCC33A

38

40

dB

123

89

1

134

94

µA

VCC33AP

VCC15A

Note: *FS is full-scale error, defined as the difference between the actual value that triggers the transition to full-scale

and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error. Refer to the

Analog-to-Digital Converter chapter of the SmartFusion Programmable Analog User’s Guide for more

information.

Revision 10

2-83

SmartFusion DC and Switching Characteristics

Comparator

Unless otherwise specified, performance is specified at 25°C with nominal power supply voltages.

Table 2-98 • Comparator Performance Specifications

Specification

Test Conditions

Minimum

Min.

Typ. Max. Units

Input voltage range

0

V

Maximum

2.56

±1

Input offset voltage

Input bias current

HYS[1:0] = 00

(no hysteresis)

±3

mV

Comparator 1, 3, 5, 7, 9 (measured at 2.56 V)

Comparator 0, 2, 4, 6, 8 (measured at 2.56 V)

40

100

300

nA

150

Input resistance

10

50

M

dB

Power supply rejection ratio DC (0 – 10 KHz)

60

15

Propagation delay

100 mV overdrive

HYS[1:0] = 00

(no hysteresis)

18

ns

100 mV overdrive

HYS[1:0] = 10

(with hysteresis)

HYS[1:0] = 00 Typical (25°C)

25

0

30

±5

ns

Hysteresis

0

mV

(± refers to rising and falling

threshold shifts, respectively)

Across all corners (–40ºC to +100ºC)

HYS[1:0] = 01 Typical (25°C)

Across all corners (–40ºC to +100ºC)

HYS[1:0] = 10 Typical (25°C)

Across all corners (–40ºC to +100ºC)

HYS[1:0] = 11 Typical (25°C)

Across all corners (–40ºC to +100ºC)

±3

0

± 16 ±30

±36

±19

±12

± 31

±48

±54

±80 ± 105 ±190 mV

±80 ±194 mV

Comparator current

requirements

(per comparator)

VCC33A = 3.3 V (operational mode); COMP_EN = 1

VCC33A

VCC33AP

VCC15A

150

140

1

165

3

µA

2-84

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Analog Sigma-Delta Digital to Analog Converter (DAC)

Unless otherwise noted, sigma-delta DAC performance is specified at 25°C with nominal power supply

voltages, using the internal sigma-delta modulators with 16-bit inputs, HCLK = 100 MHz, modulator

inputs updated at a 100 KHz rate, in voltage output mode with an external 160 pF capacitor to ground,

after trimming and digital [pre-]compensation.

Table 2-99 • Analog Sigma-Delta DAC

Specification

Resolution

Test Conditions

Min.

Typ.

Max. Units

8

24

Bits

V

Output range

0 to 2.56

0 to 256

10

Current output mode

µA

K

M

V

Output Impedance

Output voltage compliance

Gain error

6

12

Current output mode

–40ºC to +100ºC

10

0–3.0

0–2.7

0–3.4

±2

V

Voltage output mode

A2F060: –40ºC to +100ºC

A2F200: –40ºC to +100ºC

A2F500: –40ºC to +100ºC

Current output mode

A2F060: –40ºC to +100ºC

A2F200: –40ºC to +100ºC

A2F500: –40ºC to +100ºC

DACBYTE0 = h’00 (8-bit)

–40ºC to +100ºC

0.3

1.2

0.3

1.2

0.3

0.25

1

%

±2

%

±5.3

±2

%

±2

%

±2

%

±5.3

±2

%

Output referred offset

±1

mV

µA

% FS*

µs

±2.5

±1

Current output mode

–40ºC to +100ºC

0.3

1

±2.5

0.3

0.4

Integral non-linearity

Differential non-linearity

Analog settling time

RMS deviation from BFSL

0.1

0.05

Refer to

Figure 2-45 on

page 2-86

Power supply rejection ratio

DC, full scale output

33

34

dB

Note: *FS is full-scale error, defined as the difference between the actual value that triggers the transition to full-scale

and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error. Refer to the

Analog-to-Digital Converter chapter of the SmartFusion Programmable Analog User’s Guide for more

information.

Revision 10

2-85

SmartFusion DC and Switching Characteristics

Table 2-99 • Analog Sigma-Delta DAC (continued)

Specification

Test Conditions

Min.

Typ.

Max. Units

Sigma-delta DAC power supply current Input = 0, EN = 1

requirements (not including VAREFx)

(operational mode)

VCC33SDDx

VCC15A

30

3

35

5

µA

Input = Half scale, EN = 1

(operational mode)

VCC33SDDx

VCC15A

160

33

165

35

µA

Input = Full scale, EN = 1

(operational mode)

VCC33SDDx

VCC15A

280

70

285

75

µA

Note: *FS is full-scale error, defined as the difference between the actual value that triggers the transition to full-scale

and the ideal analog full-scale transition value. Full-scale error equals offset error plus gain error. Refer to the

Analog-to-Digital Converter chapter of the SmartFusion Programmable Analog User’s Guide for more

information.

Sigma Delta DAC Settling Time

220

200

180

160

140

120

100

80

60

40

20

0

1

2

3

4

5

6

7

8

9

10 32 48 64 128 255

Input Code

Figure 2-45 • Sigma-Delta DAC Setting Time

2-86

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Voltage Regulator

Table 2-100 • Voltage Regulator

Symbol

V_OUT

Parameter

Test Conditions

Min.

Typ.

1.5

11

Max.

Unit

V

Output voltage

T_J= 25°C

1.425

1.575

V_OS

Output offset voltage T_J= 25°C

mV

mA

mV

mV/V

ICC33A Operation current

T_J= 25°C

I_LOAD= 1 mA

3.4

11

I_LOAD= 100 mA

I_LOAD= 0.5 A

21

V_OUT

Load regulation

Line regulation

T_J= 25°C

I_LOAD= 1 mA to 0.5 A

VCC33A = 2.97 V to 3.63 V

5.8

5.3

I

_LOAD= 1 mA

VCC33A = 2.97 V to 3.63 V

I_LOAD= 100 mA

5.3

mV/V

VCC33A = 2.97 V to 3.63 V

I_LOAD= 500mA

Dropout voltage¹

T_J= 25°C

I_LOAD= 1 mA

0.63

0.84

1.35

48

V

I_LOAD= 100 mA

I

_LOAD= 0.5 A

V

I_PTBASEPTBase current

I_LOAD= 1 mA

µA

mA

µs

I_LOAD= 100 mA

736

12

I

_LOAD= 0.5 A

Startup time²

200

Notes:

1. Dropout voltage is defined as the minimum VCC33A voltage. The parameter is specified with respect to the output

voltage. The specification represents the minimum input-to-output differential voltage required to maintain regulation.

2. Assumes 10 µF.

Revision 10

2-87

SmartFusion DC and Switching Characteristics

Typical Output Voltage

0.015

0.01

Load = 10 mA

Load = 100 mA

0.005

0

Load = 500 mA

-0.005

-0.01

-0.015

-0.02

-0.025

-40

-20

0

20

40

60

80

100

Temperature (°C)

Figure 2-46 • Typical Output Voltage

Load Regulation

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

-40

-20

0

20

40

60

80

100

Temperature (°C)

Figure 2-47 • Load Regulation

2-88

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Serial Peripheral Interface (SPI) Characteristics

This section describes the DC and switching of the SPI interface. Unless otherwise noted, all output

characteristics given for a 35 pF load on the pins and all sequential timing characteristics are related to

SPI_x_CLK. For timing parameter definitions, refer to Figure 2-48 on page 2-90.

Table 2-101 • SPI Characteristics

Commercial Case Conditions: T_J= 85ºC, VDD = 1.425 V, –1 Speed Grade

Symbol

Description and Condition

SPI_x_CLK minimum period

A2F060

A2F200

A2F500

Unit

sp1

SPI_x_CLK = PCLK/2

20

NA

40

20

ns

µs

SPI_x_CLK = PCLK/4

40

SPI_x_CLK = PCLK/8

80

SPI_x_CLK = PCLK/16

0.16

0.32

0.64

1.28

2.56

0.16

0.32

0.64

1.28

2.56

0.16

0.32

0.64

1.28

2.56

SPI_x_CLK = PCLK/32

SPI_x_CLK = PCLK/64

SPI_x_CLK = PCLK/128

SPI_x_CLK = PCLK/256

SPI_x_CLK minimum pulse width high

SPI_x_CLK = PCLK/2

sp2

10

NA

20

10

ns

µs

us

SPI_x_CLK = PCLK/4

20

SPI_x_CLK = PCLK/8

40

SPI_x_CLK = PCLK/16

0.08

0.16

0.32

0.64

1.28

0.08

0.16

0.32

0.64

1.28

0.08

0.16

0.32

0.64

1.28

SPI_x_CLK = PCLK/32

SPI_x_CLK = PCLK/64

SPI_x_CLK = PCLK/128

SPI_x_CLK = PCLK/256

SPI_x_CLK minimum pulse width low

SPI_x_CLK = PCLK/2

sp3

10

20

NA

20

10

20

ns

µs

ns

SPI_x_CLK = PCLK/4

SPI_x_CLK = PCLK/8

40

SPI_x_CLK = PCLK/16

0.08

0.16

0.32

0.64

1.28

4.7

0.08

0.16

0.32

0.64

1.28

4.7

0.08

0.16

0.32

0.64

1.28

4.7

SPI_x_CLK = PCLK/32

SPI_x_CLK = PCLK/64

SPI_x_CLK = PCLK/128

SPI_x_CLK = PCLK/256

SPI_x_CLK, SPI_x_DO, SPI_x_SS rise time (10%-90%) ¹

SPI_x_CLK, SPI_x_DO, SPI_x_SS fall time (10%-90%) ¹

sp4

sp5

3.4

Notes:

1. These values are provided for a load of 35 pF. For board design considerations and detailed output buffer resistances,

use the corresponding IBIS models located on the Microsemi SoC Products Group website:

http://www.microsemi.com/soc/download/ibis/default.aspx.

2. For allowable pclk configurations, refer to the Serial Peripheral Interface Controller section in the SmartFusion

Microcontroller Subsystem User’s Guide.

Revision 10

2-89

SmartFusion DC and Switching Characteristics

Table 2-101 • SPI Characteristics

Commercial Case Conditions: T_J= 85ºC, VDD = 1.425 V, –1 Speed Grade (continued)

Symbol

sp6

Description and Condition

Data from master (SPI_x_DO) setup time ²

Data from master (SPI_x_DO) hold time ²

SPI_x_DI setup time ²

A2F060

A2F200

A2F500

Unit

1

pclk cycles

sp7

sp8

sp9

SPI_x_DI hold time ²

Notes:

1. These values are provided for a load of 35 pF. For board design considerations and detailed output buffer resistances,

use the corresponding IBIS models located on the Microsemi SoC Products Group website:

http://www.microsemi.com/soc/download/ibis/default.aspx.

2. For allowable pclk configurations, refer to the Serial Peripheral Interface Controller section in the SmartFusion

Microcontroller Subsystem User’s Guide.

SP1

SP4

SP5

SP3

SP2

90%

10%

50% 50%

50%

SPI_x_CLK

SPO = 0

10%

SPI_x_CLK

SPO = 1

90%

SPI_x_SS

10%

SP4

10%

SP5

SP6

SP7

90%

MSB

50%

SPI_x_DO

SPI_x_DI

10%

SP8

SP9

SP5

SP4

50%

MSB

Figure 2-48 • SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1)

2-90

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

2

Inter-Integrated Circuit (I C) Characteristics

This section describes the DC and switching of the I^C interface. Unless otherwise noted, all output

characteristics given are for a 100 pF load on the pins. For timing parameter definitions, refer to Figure 2-

49 on page 2-92.

Table 2-102 • I²C Characteristics

Commercial Case Conditions: T_J= 85ºC, V_DD= 1.425 V, –1 Speed Grade

Parameter

Definition

Condition

Value

Unit

V_IL

Minimum input low voltage

–

SeeTable 2-36 on

page 2-30

–

Maximum input low voltage

Minimum input high voltage

Maximum input high voltage

Maximum output voltage low

Input current high

–

See Table 2-36

–

V

V_IH

–

V_OL

I_IL

I_OL= 8 mA

–

I_IH

Input current low

V_hyst

Hysteresis of Schmitt trigger

inputs

See Table 2-33 on

page 2-29

T_FALL

Fall time ²

VIHmin to VILMax, C_load= 400 pF

VIHmin to VILMax, C_load= 100 pF

VILMax to VIHmin, C_load= 400pF

VILMax to VIHmin, C_load= 100pF

VIN = 0, f = 1.0 MHz

15.0

4.0

ns

pF



T_RISE

Rise time ²

19.5

5.2

Cin

Pin capacitance

8.0

R_pull-up

Output buffer maximum pull-

down Resistance ¹

–

50

R_pull-downOutput buffer maximum pull-up

Resistance ¹

–

150



D_max

Maximum data rate

Fast mode

400

1

Kbps

t_LOW

Low period of I2C_x_SCL ³

High period of I2C_x_SCL ³

START hold time ³

–

pclk cycles

t_HIGH

1

t_HD;STA

t_SU;STA

t_HD;DAT

t_SU;DAT

Notes:

1

START setup time ³

DATA hold time ³

1

DATA setup time ³

1

1. These maximum values are provided for information only. Minimum output buffer resistance values depend on

VCCxxxxIOBx, drive strength selection, temperature, and process. For board design considerations and detailed output

buffer resistances, use the corresponding IBIS models located on the SoC Products Group website at

http://www.microsemi.com/soc/download/ibis/default.aspx.

2. These values are provided for a load of 100 pF and 400 pF. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located on the SoC Products Group website at

http://www.microsemi.com/soc/download/ibis/default.aspx.

2

3. For allowable Pclk configurations, refer to the Inter-Integrated Circuit (I C) Peripherals section in the SmartFusion

Microcontroller Subsystem User’s Guide.

Revision 10

2-91

SmartFusion DC and Switching Characteristics

Table 2-102 • I²C Characteristics

Commercial Case Conditions: T_J= 85ºC, V_DD= 1.425 V, –1 Speed Grade (continued)

Parameter

t_SU;STO

t_FILT

Definition

STOP setup time ³

Maximum spike width filtered

Condition

Value

1

Unit

pclk cycles

ns

–

50

Notes:

1. These maximum values are provided for information only. Minimum output buffer resistance values depend on

VCCxxxxIOBx, drive strength selection, temperature, and process. For board design considerations and detailed output

buffer resistances, use the corresponding IBIS models located on the SoC Products Group website at

http://www.microsemi.com/soc/download/ibis/default.aspx.

2. These values are provided for a load of 100 pF and 400 pF. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models located on the SoC Products Group website at

http://www.microsemi.com/soc/download/ibis/default.aspx.

2

3. For allowable Pclk configurations, refer to the Inter-Integrated Circuit (I C) Peripherals section in the SmartFusion

Microcontroller Subsystem User’s Guide.

SDA

T_RISE

t_LOW

T_FALL

SCL

t_HIGH

t_SU;STO

P

t_SU;DAT

t_SU;STA

t_HD;DAT

t_HD;STA

S

Figure 2-49 • I2C Timing Parameter Definition

2-92

Revision 10

3 – SmartFusion Development Tools

Designing with SmartFusion cSoCs involves three different types of design: FPGA design, embedded

design and analog design. These roles can be filled by three different designers, two designers or even a

single designer, depending on company structure and project complexity.

Types of Design Tools

Microsemi has developed design tools and flows to meet the needs of these three types of designers so

they can work together smoothly on a single project (Figure 3-1).

FPGA Design

Embedded Design

Software IDE

(SoftConsole, Keil, IAR)

MSS Configurator

MSS Configuration – Analog Configuration

Design Entry and IP Libraries

Drivers and Sample Projects

Application Development

Build Project

Simulation and Synthesis

Compile and Layout

Timing and Power Analysis

Hardware Debug

Simulation

Software Debug

Hardware Interfaces

FlashPro4, ULINK, J-LINK

Figure 3-1 • Three Design Roles

FPGA Design

Libero System-on-Chip (SoC) software is Microsemi’s comprehensive software toolset for designing with

all Microsemi FPGAs and cSoCs. Libero SoC includes industry-leading synthesis, simulation and debug

tools from Synopsys^®and Mentor Graphics^®, as well as innovative timing and power optimization and

analysis.

Revision 10

3-1

SmartFusion Development Tools

Embedded Design

Microsemi offers FREE SoftConsole Eclipse based IDE, which includes the GNU C/C++ compiler and

GDB debugger. Microsemi also offers evaluation versions of software from Keil and IAR, with full

versions available from respective suppliers.

Analog Design

The MSS configurator provides graphical configuration for current, voltage and temperature monitors,

sample sequencing setup and post-processing configuration, as well as DAC output.

The MSS configurator creates a bridge between the FPGA fabric and embedded designers so device

configuration can be easily shared between multiple developers.

The MSS configurator includes the following:

•

A simple configurator for the embedded designer to control the MSS peripherals and I/Os

A method to import and view a hardware configuration from the FPGA flow into the embedded

flow containing the memory map

•

Automatic generation of drivers for any peripherals or soft IP used in the system configuration

Comprehensive analog configuration for the programmable analog components

Creation of a standard MSS block to be used in SmartDesign for connection of FPGA fabric

designs and IP

Figure 3-2 • MSS Configurator

3-2

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

SmartFusion Ecosystem

The Microsemi SoC Products Group has a long history of supplying comprehensive FPGA development

tools and recognizes the benefit of partnering with industry leaders to deliver the optimum usability and

productivity to customers. Taking the same approach with processor development, Microsemi has

partnered with key industry leaders in the microcontroller space to provide the robust SmartFusion

ecosystem.

Microsemi is partnering with Keil and IAR to provide Software IDE support to SmartFusion system

designers. The result is a robust solution that can be easily adopted by developers who are already doing

embedded design. The learning path is straightforward for FPGA designers.

Support for the SoC Products Group device and ecosystem resources is represented in Figure 3-3.

Application Code

Middleware

Customer Secret Sauce

TCP/IP, HTTP, SMTP, DHCP, LCD

µC/OS-III, RTX, Unison, FreeRTOS

OS/RTOS

Drivers

Hardware

Abstraction

Layer

Microsemi CMSIS-based HAL

Figure 3-3 • SmartFusion Ecosystem

Figure 3-3 shows the SmartFusion stack with examples of drivers, RTOS, and middleware from

Microsemi and partners. By leveraging the SmartFusion stack, designers can decide at which level to

add their own customization to their design, thus speeding time to market and reducing overhead in the

design.

ARM

Because an ARM processor was chosen for SmartFusion cSoCs, Microsemi's customers can benefit

from the extensive ARM ecosystem. By building on Microsemi supplied hardware abstraction layer (HAL)

and drivers, third party vendors can easily port RTOS and middleware for the SmartFusion cSoC.

•

ARM Cortex-M Series Processors

ARM Cortex-M3 Processor Resource

ARM Cortex-M3 Technical Reference Manual

ARM Cortex-M3 Processor Software Development for ARM7TDMI Processor Programmers

White Paper

Revision 10

3-3

SmartFusion Development Tools

Compile and Debug

Microsemi's SoftConsole is a free Eclipse-based IDE that enables the rapid production of C and C++

executables for Microsemi FPGA and cSoCs using Cortex-M3, Cortex-M1 and Core8051s. For

SmartFusion support, SoftConsole includes the GNU C/C++ compiler and GDB debugger. Additional

examples can be found on the SoftConsole page:

•

Using UART with SmartFusion: SoftConsole Standalone Flow Tutorial

Design Files

Displaying POT Level with LEDs: Libero SoC and SoftConsole Flow Tutorial for SmartFusion

Design Files

–

•

–

IAR Embedded Workbench^®for ARM/Cortex is an integrated development environment for building and

debugging embedded ARM applications using assembler, C and C++. It includes a project manager,

editor, build and debugger tools with support for RTOS-aware debugging on hardware or in a simulator.

•

Designing SmartFusion cSoC with IAR Systems

IAR Embedded Workbench IDE User Guide for ARM

Download Evaluation or Kickstart version of IAR Embedded Workbench for ARM

Keil's Microcontroller Development Kit comes in two editions: MDK-ARM and MDK Basic. Both editions

feature µVision^®, the ARM Compiler, MicroLib, and RTX, but the MDK Basic edition is limited to 256K so

that small applications are more affordable.

•

Designing SmartFusion cSoC with Keil

Using Keil µVision and Microsemi SmartFusion cSoC

–

Programming file for use with this tutorial

•

Keil Microcontroller Development Kit for ARM Product Manuals

Download Evaluation version of Keil MDK-ARM

Software IDE

Website

SoftConsole

Vision IDE

www.keil.com

Embedded Workbench

www.iar.com

www.microsemi.com/soc

Free with Libero SoC

Free versions from SoC

Products Group

32 K code limited

Available from Vendor

Compiler

N/A

Full version

RealView C/C++

Vision Debugger

Vision Simulator

ULINK2 or ULINK-ME

Full version

IAR ARM Compiler

C-SPY Debugger

Yes

GNU GCC

GDB debug

No

Debugger

Instruction Set Simulator

Debug Hardware

FlashPro4

J-LINK or J-LINK Lite

Operating Systems

FreeRTOS™ is a portable, open source, royalty free, mini real-time kernel (a free-to-download and free-

to-deploy RTOS that can be used in commercial applications without any requirement to expose your

proprietary source code). FreeRTOS is scalable and designed specifically for small embedded systems.

This FreeRTOS version ported by Microsemi is 6.0.1. For more information, visit the FreeRTOS website:

www.freertos.org

•

SmartFusion Webserver Demo Using uIP and FreeRTOS

SmartFusion cSoC: Running Webserver, TFTP on IwIP TCP/IP Stack Application Note

3-4

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Emcraft Systems provides porting of the open-source U-boot firmware and uClinux™ kernel to the

SmartFusion cSoC, a Linux^®-based cross-development framework, and other complementary

components. Combined with the release of its A2F-Linux Evaluation Kit, this provides a low-cost platform

for evaluation and development of Linux (uClinux) on the Cortex-M3 CPU core of the Microsemi

SmartFusion cSoC.

•

Emcraft Linux on Microsemi's SmartFusion cSoC

Keil offers the RTX Real-Time Kernel as a royalty-free, deterministic RTOS designed for ARM and

Cortex-M devices. It allows you to create programs that simultaneously perform multiple functions and

helps to create applications which are better structured and more easily maintained.

•

The RTX Real-Time Kernel is included with MDK-ARM. Download the Evaluation version of Keil

MDK-ARM.

•

RTX source code is available as part of Keil/ARM Real-Time Library (RL-ARM), a group of tightly-

coupled libraries designed to solve the real-time and communication challenges of embedded

systems based on ARM-powered microcontroller devices. The RL-ARM library now supports

SmartFusion cSoCs and designers with additional key features listed in the "Middleware" section

on page 3-5.

Micrium supports SmartFusion cSoCs with the company's flagship µC/OS family, recognized for a variety

of features and benefits, including unparalleled reliability, performance, dependability, impeccable source

code and vast documentation. Micrium supports the following products for SmartFusion cSoCs and

continues to work with Microsemi on additional projects.

•

SmartFusion Quickstart Guide for Micrium µC/OS-III Examples

Design Files

–

µC/OS-III™, Micrium's newest RTOS, is designed to save time on your next embedded project and puts

greater control of the software in your hands.

RoweBots provides an ultra tiny Linux-compatible RTOS called Unison for SmartFusion. Unison consists

of a set of modular software components, which, like Linux, are either free or commercially licensed.

Unison offers POSIX^®and Linux compatibility with hard real-time performance, complete I/O modules

and an easily understood environment for device driver programming. Seamless integration with FPGA

and analog features are fast and easy.

•

Unison V4-based products include a free Unison V4 Linux and POSIX-compatible kernel with

serial I/O, file system, six demonstration programs, upgraded documentation and source code for

Unison V4, and free (for non-commercial use) Unison V4 TCP/IP server. Commercial license

upgrade is available for Unison V4 TCP/IP server with three demonstration programs, DHCP

client and source code.

•

Unison V5-based products include commercial Unison V5 Linux- and POSIX-compatible kernel

with serial I/O, file system, extensive feature set, full documentation, source code and more than

20 demonstration programs, Unison V5 TCP/IPv4 with extended feature set, sockets interface,

multiple network interfaces, PPP support, DHCP client, documentation, source code and six

demonstration programs, and multiple other features.

Middleware

Microsemi has ported both uIP and IwIP for Ethernet support as well as including TFTP file service.

•

SmartFusion Webserver Demo Using uIP and FreeRTOS

SmartFusion: Running Webserver, TFTP on IwIP TCP/IP Stack Application Note

The Keil/ARM Real-Time Library (RL-ARM)¹, in addition to RTX source, includes the following:

•

RL-TCPnet (TCP/IP) – The Keil RL-TCPnet library, supporting full TCP/IP and UDP protocols, is a

full networking suite specifically written for small ARM and Cortex-M processor-based

microcontrollers. TCPnet is now ported to and supports SmartFusion Cortex-M3. It is highly

optimized, has a small code footprint, and gives excellent performance, providing a wide range of

application level protocols and examples such as FTP, SNMP, SOAP and AJAX. An HTTP server

example of TCPnet working in a SmartFusion design is available.

1. The CAN and USB functions within RL-ARM are not supported for SmartFusion cSoC.

Revision 10

3-5

SmartFusion Development Tools

•

Flash File System (RL-Flash) allows your embedded applications to create, save, read, and

modify files in standard storage devices such as ROM, RAM, or FlashROM, using a standard

serial peripheral interface (SPI). Many ARM-based microcontrollers have a practical requirement

for a standard file system. With RL-FlashFS you can implement new features in embedded

applications such as data logging, storing program state during standby modes, or storing

firmware upgrades.

Micrium, in addition to µC/OS-III^®, offers the following support for SmartFusion cSoC:

•

µC/TCP-IP™ is a compact, reliable, and high-performance stack built from the ground up by

Micrium and has the quality, scalability, and reliability that translates into a rapid configuration of

network options, remarkable ease-of-use, and rapid time-to-market.

•

µC/Probe™ is one of the most useful tools in embedded systems design and puts you in the

driver's seat, allowing you to take charge of virtually any variable, memory location, and I/O port in

your embedded product, while your system is running.

References

PCB Files

A2F500 SmartFusion Development Kit PCB Files

www.microsemi.com/soc/download/rsc/?f=A2F500_DEV_KIT_BF

A2F200 SmartFusion Development Kit PCB Files

www.microsemi.com/soc/download/rsc/?f=A2F_DEV_KIT_BF

Application Notes

SmartFusion cSoC Board Design Guidelines

www.microsemi.com/soc/documents/A2F_AC359_AN.pdf

3-6

Revision 10

4 – SmartFusion Programming

SmartFusion cSoCs have three separate flash areas that can be programmed:

1. The FPGA fabric

2. The embedded nonvolatile memories (eNVMs)

3. The embedded flash ROM (eFROM)

There are essentially three methodologies for programming these areas:

1. In-system programming (ISP)

2. In-application programming (IAP)

a. A2F060 and A2F500: The FPGA fabric, eNVM, and eFROM

b. A2F200: Only the FPGA fabric and the eNVM

3. Pre-programming (non-ISP)

Programming, whether ISP or IAP methodologies are employed, can be done in two ways:

1. Securely using the on chip AES decryption logic

2. In plain text

In-System Programming

In-System Programming is performed with the aid of external JTAG programming hardware. Table 4-1

describes the JTAG programming hardware that will program a SmartFusion cSoC and Table 4-2 defines

the JTAG pins that provide the interface for the programming hardware.

Table 4-1 • Supported JTAG Programming Hardware

Program

FPGA

Program

eFROM

Program

eNVM

Dongle

Source

JTAG

SWD¹

SWV²

FlashPro3/4

SoC

Products

Group

Yes

No

Yes

ULINK Pro

ULINK2

Keil

IAR

Yes

Yes³

Yes

IAR J-Link

Notes:

1. SWD = ARM Serial Wire Debug

2. SWV = ARM Serial Wire Viewer

3. Planned support

Table 4-2 • JTAG Pin Descriptions

Pin Name

Description

JTAGSEL

TRSTB

TCK

ARM Cortex-M3 or FPGA test access port (TAP) controller selection

Test reset bar

Test clock

TMS

Test mode select

Test data input

Test data output

TDI

TDO

Revision 10

4-7

SmartFusion Programming

The JTAGSEL pin selects the FPGA TAP controller or the Cortex-M3 debug logic. When JTAGSEL is

asserted, the FPGA TAP controller is selected and the TRSTB input into the Cortex-M3 is held in a reset

state (logic 0), as depicted in Figure 4-1. Users should tie the JTAGSEL pin high externally.

Microsemi’s free Eclipse-based IDE, SoftConsole, has the ability to control the JTAGSEL pin directly with

the FlashPro4 programmer. Manual jumpers are provided on the evaluation and development kits to

allow manual selection of this function for the J-Link and ULINK debuggers.

Note: Standard ARM JTAG connectors do not have access to the JTAGSEL pin. SoftConsole

automatically selects the appropriate TAP controller using the CTXSELECT JTAG command.

When using SoftConsole, the state of JTAGSEL is a "don't care."

VJTAG (1.5 V to 3.3. V nominal)

TAP

JTAG_SEL

TRSTB

Controller

Cortex-M3

TRSTB

FPGA

Programming Control

FPGA TAP

Controller

Figure 4-1 • TRSTB Logic

In-Application Programming

In-application programming refers to the ability to reprogram the various flash areas under direct

supervision of the Cortex-M3.

Reprogramming the FPGA Fabric Using the Cortex-M3

In this mode, the Cortex-M3 is executing the programming algorithm on-chip. The IAP driver can be

incorporated into the design project and executed from eNVM or eSRAM. The SoC Products Group

provides working example projects for SoftConsole, IAR, and Keil development environments. These can

be downloaded via the SoC Products Group Firmware Catalog. The new bitstream to be programmed

into the FPGA can reside on the user’s printed circuit board (PCB) in a separate SPI flash memory.

Alternately, the user can modify the existing projects supplied by the SoC Products Group and, via

custom handshaking software, throttle the download of the new image and program the FPGA a piece at

a time in real time. A cost-effective and reliable approach would be to store the bitstream in an external

SPI flash. Another option is storing a redundant bitstream image in an external SPI flash and loading the

newest version into the FPGA only when receiving an IAP command. Since the FPGA I/Os are tristated

or held at predefined or last known state during FPGA programming, the user must use MSS I/Os to

interface to external memories. Since there are two SPI controllers in the MSS, the user can dedicate

one to an SPI flash and the other to the particulars of an application. The amount of flash memory

required to program the FPGA always exceeds the size of the eNVM block that is on-chip. The external

memory controller (EMC) cannot be used as an interface to a memory device for storage of a bitstream

because its I/O pads are FPGA I/Os; hence they are tristated when the FPGA is in a programming state.

The MSS resets itself after IAP of the FPGA fabric. This reset is internally asserted on MSS_RESETN by

the power supply monitor (PSM) and reset controller of the MSS.

4-8

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Re-Programming the eNVM Blocks Using the Cortex-M3

In this mode the Cortex-M3 is executing the eNVM programming algorithm from eSRAM. Since individual

pages (132 bytes) of the eNVM can be write-protected, the programming algorithm software can be

protected from inadvertent erasure. When reprogramming the eNVM, both MSS I/Os and FPGA I/Os are

available as interfaces for sourcing the new eNVM image. The SoC Products Group provides working

example projects for SoftConsole, IAR, and Keil development environments. These can be downloaded

via the SoC Products Group Firmware Catalog.

Alternately, the eNVM can be reprogrammed by the Cortex-M3 via the IAP driver. This is necessary when

using an encrypted image.

Secure Programming

For background, refer to the "Security in Low Power Flash Devices" chapter of the Fusion FPGA Fabric

User’s Guide on the SoC Products Group website. SmartFusion ISP behaves identically to Fusion ISP.

IAP of SmartFusion cSoCs is accomplished by using the IAP driver. Only the FPGA fabric and the eNVM

can be reprogrammed with the protection of security measures by using the IAP driver.

Typical Programming and Erase Times

Table 4-3 documents the typical programming and erase times for two components of SmartFusion

cSoCs, FPGA fabric and eNVM, using the SoC Products Group’s FlashPro hardware and software.

These times will be different for other ISP and IAP methods. The Program action in FlashPro software

includes erase, program, and verify to complete.

The typical programming (including erase) time per page of the eNVM is 8 ms.

Table 4-3 • Typical Programming and Erase Times

FPGA Fabric (seconds)

eNVM (seconds)

A2F200

A2F500

21

A2F200

A2F500

N/A

Erase

21

8

N/A

18

Program

Verify

15

26

9

16

26

42

References

User’s Guides

DirectC User’s Guide

www.microsemi.com/soc/documents/DirectC_UG.pdf

In-System Programming (ISP) of Microsemi’s Low-Power Flash Devices Using FlashPro4/3/3X

www.microsemi.com/soc/documents/LPF_AC386_AN.pdf

Programming Flash Devices HandBook

www.microsemi.com/soc/documents/Flash_Program_HBs.pdf

Application Notes on IAP Programming Technique

SmartFusion cSoC: Programming FPGA Fabric and eNVM Using In-Application Programming Interface

App Note

www.microsemi.com/soc/documents/A2F_AC362_AN.pdf

SmartFusion cSoC: Basic Bootloader and Field Upgrade eNVM Through IAP Interface App Note

www.microsemi.com/soc/documents/A2F_AC372_AN.pdf

Revision 10

4-9

5 – Pin Descriptions

Supply Pins

Name

Type

Description

GND

Ground Digital ground to the FPGA fabric, microcontroller subsystem and GPIOs

Ground Quiet analog ground to the 1.5 V circuitry of the first analog-to-digital converter (ADC)

Ground Quiet analog ground to the 1.5 V circuitry of the second ADC

Ground Quite analog ground to the 1.5 V circuitry of the third ADC

Ground Quiet analog ground to the 3.3 V circuitry of the first ADC

Ground Quiet analog ground to the 3.3 V circuitry of the second ADC

Ground Quiet analog ground to the 3.3 V circuitry of the third ADC

Ground Quiet analog ground to the analog front-end

GND15ADC0

GND15ADC1

GND15ADC2

GND33ADC0

GND33ADC1

GND33ADC2

GNDA

GNDAQ

Ground Quiet analog ground to the analog I/O of SmartFusion cSoCs

Ground Digital ground to the embedded nonvolatile memory (eNVM)

Ground Analog ground to the low power 32 KHz crystal oscillator circuitry

GNDENVM

GNDLPXTAL

GNDMAINXTAL Ground Analog ground to the main crystal oscillator circuitry

GNDQ

Ground Quiet digital ground supply voltage to input buffers of I/O banks. Within the package, the

GNDQ plane is decoupled from the simultaneous switching noise originated from the

output buffer ground domain. This minimizes the noise transfer within the package and

improves input signal integrity. GNDQ needs to always be connected on the board to

GND.

GNDRCOSC

GNDSDD0

GNDSDD1

GNDTM0

Ground Analog ground to the integrated RC oscillator circuit

Ground Analog ground to the first sigma-delta DAC

Ground Common analog ground to the second and third sigma-delta DACs

Ground Analog temperature monitor common ground for signal conditioning blocks SCB 0 and

SCB 1 (see information for pins "TM0" and "TM1" in the "Analog Front-End (AFE)"

section on page 5-14).

GNDTM1

Ground Analog temperature monitor common ground for signal conditioning block SCB 2 and

SBCB 3 (see information for pins "TM2" and "TM3" in the "Analog Front-End (AFE)"

section on page 5-14).

GNDTM2

Ground Analog temperature monitor common ground for signal conditioning block SCB4

GNDVAREF

Ground Analog ground reference used by the ADC. This pad should be connected to a quiet

analog ground.

VCC

Supply Digital supply to the FPGA fabric and MSS, nominally 1.5 V. VCC is also required for

powering the JTAG state machine, in addition to VJTAG. Even when a SmartFusion

cSoC is in bypass mode in a JTAG chain of interconnected devices, both VCC and

VJTAG must remain powered to allow JTAG signals to pass through the SmartFusion

cSoC.

Notes:

1. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A,

VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL.

2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC,

VCC15A, and VCC15ADCx.

3. For more details on VCCPLLx capacitor recommendations, refer to the application note AC359, SmartFusion cSoC

Board Design Guidelines, the "PLL Power Supply Decoupling Scheme" section.

Revision 10

5-1

Pin Descriptions

Name

Type

Description

VCC15A

Supply Clean analog 1.5 V supply to the analog circuitry. Always power this pin.

Supply Analog 1.5 V supply to the first ADC. Always power this pin.

Supply Analog 1.5 V supply to the second ADC. Always power this pin.

Supply Analog 1.5 V supply to the third ADC. Always power this pin.

VCC15ADC0

VCC15ADC1

VCC15ADC2

VCC33A

Supply Clean 3.3 V analog supply to the analog circuitry. VCC33A is also used to feed the

1.5 V voltage regulator for designs that do not provide an external supply to VCC. Refer

to the Voltage Regulator (VR), Power Supply Monitor (PSM), and Power Modes section

in the SmartFusion Microcontroller Subsystem User’s Guide for more information.

VCC33ADC0

VCC33ADC1

VCC33ADC2

VCC33AP

Supply Analog 3.3 V supply to the first ADC. If unused, Microsemi recommends connecting this

pin to a 3.3 V supply.¹

Supply Analog 3.3 V supply to the second ADC. If unused, Microsemi recommends connecting

this pin to a 3.3 V supply.¹

Supply Analog 3.3 V supply to the third ADC. If unused, Microsemi recommends connecting

this pin to a 3.3 V supply.¹

Supply Analog clean 3.3 V supply to the charge pump. To avoid high current draw, VCC33AP

should be powered up simultaneously with or after VCC33A. Can be pulled down if

unused.¹

VCC33N

Supply –3.3 V output from the voltage converter. A 2.2 µF capacitor must be connected from

this pin to GND. Analog charge pump capacitors are not needed if none of the analog

SCB features are used and none of the SDDs are used. In that case it should be left

unconnected.

VCC33SDD0

VCC33SDD1

VCCENVM

Supply Analog 3.3 V supply to the first sigma-delta DAC

Supply Common analog 3.3 V supply to the second and third sigma-delta DACs

Supply Digital 1.5 V power supply to the embedded nonvolatile memory blocks. To avoid high

current draw, VCC should be powered up before or simultaneously with VCCENVM.

VCCESRAM

Supply Digital 1.5 V power supply to the embedded SRAM blocks. Available only on the

208PQFP package. It should be connected to VCC (in other packages, it is internally

connected to VCC).

VCCFPGAIOB0

Supply Digital supply to the FPGA fabric I/O bank 0 (north FPGA I/O bank) for the output

buffers and I/O logic.

Each bank can have a separate VCCFPGAIO connection. All I/Os in a bank will run off

the same VCCFPGAIO supply. VCCFPGAIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V,

nominal voltage. Unused I/O banks should have their corresponding VCCFPGAIO pins

tied to GND.

VCCFPGAIOB1

Supply Digital supply to the FPGA fabric I/O bank 1 (east FPGA I/O bank) for the output buffers

and I/O logic.

Each bank can have a separate VCCFPGAIO connection. All I/Os in a bank will run off

the same VCCFPGAIO supply. VCCFPGAIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V,

nominal voltage. Unused I/O banks should have their corresponding VCCFPGAIO pins

tied to GND.

Notes:

1. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A,

VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL.

2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC,

VCC15A, and VCC15ADCx.

3. For more details on VCCPLLx capacitor recommendations, refer to the application note AC359, SmartFusion cSoC

Board Design Guidelines, the "PLL Power Supply Decoupling Scheme" section.

5-2

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Name

Type

Description

VCCFPGAIOB5

Supply Digital supply to the FPGA fabric I/O bank 5 (west FPGA I/O bank) for the output buffers

and I/O logic.

Each bank can have a separate VCCFPGAIO connection. All I/Os in a bank will run off

the same VCCFPGAIO supply. VCCFPGAIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V,

nominal voltage. Unused I/O banks should have their corresponding VCCFPGAIO pins

tied to GND.

VCCLPXTAL

Supply Analog supply to the low power 32 KHz crystal oscillator. Always power this pin.¹

Supply Analog supply to the main crystal oscillator circuit. Always power this pin.¹

VCCMAINXTAL

VCCMSSIOB2

Supply Supply voltage to the microcontroller subsystem I/O bank 2 (east MSS I/O bank) for the

output buffers and I/O logic.

Each bank can have a separate VCCMSSIO connection. All I/Os in a bank will run off

the same VCCMSSIO supply. VCCMSSIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal

voltage. Unused I/O banks should have their corresponding VCCMSSIO pins tied to

GND.

VCCMSSIOB4

Supply Supply voltage to the microcontroller subsystem I/O bank 4 (west MSS I/O bank) for the

output buffers and I/O logic.

Each bank can have a separate VCCMSSIO connection. All I/Os in a bank will run off

the same VCCMSSIO supply. VCCMSSIO can be 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal

voltage. Unused I/O banks should have their corresponding VCCMSSIO pins tied to

GND.

VCCPLLx

Supply Analog 1.5 V supply to the PLL. Always power this pin.

Supply Analog supply to the integrated RC oscillator circuit. Always power this pin.¹

Supply Analog ground for the PLL

VCCRCOSC

VCOMPLAx

VDDBAT

Supply External battery connection to the low power 32 KHz crystal oscillator (along with

VCCLPXTAL), RTC, and battery switchover circuit. Can be pulled down if unused.

Notes:

1. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A,

VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL.

2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC,

VCC15A, and VCC15ADCx.

3. For more details on VCCPLLx capacitor recommendations, refer to the application note AC359, SmartFusion cSoC

Board Design Guidelines, the "PLL Power Supply Decoupling Scheme" section.

Revision 10

5-3

Pin Descriptions

Name

Type

Description

VJTAG

Supply Digital supply to the JTAG controller

SmartFusion cSoCs have a separate bank for the dedicated JTAG pins. The JTAG pins

can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power

supply in a separate I/O bank gives greater flexibility in supply selection and simplifies

power supply and PCB design. If the JTAG interface is neither used nor planned to be

used, the V_JTAGpin together with the TRSTB pin could be tied to GND. Note that VCC

is required to be powered for JTAG operation; VJTAG alone is insufficient. If a

SmartFusion cSoC is in a JTAG chain of interconnected boards and it is desired to

power down the board containing the device, this can be done provided both VJTAG

and VCC to the device remain powered; otherwise, JTAG signals will not be able to

transition the device, even in bypass mode. See "JTAG Pins" section on page 5-10.

VPP

Supply Digital programming circuitry supply

SmartFusion cSoCs support single-voltage in-system programming (ISP) of the

configuration flash, embedded FlashROM (eFROM), and embedded nonvolatile

memory (eNVM).

For programming, VPP should be in the 3.3 V ± 5% range. During normal device

operation, VPP can be left floating or can be tied to any voltage between 0 V and 3.6 V.

When the VPP pin is tied to ground, it shuts off the charge pump circuitry, resulting in no

sources of oscillation from the charge pump circuitry. For proper programming, 0.01μF,

and 0.1μF to 1μF capacitors, (both rated at 16 V) are to be connected in parallel across

VPP and GND, and positioned as close to the FPGA pins as possible.

Notes:

1. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A,

VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL.

2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC,

VCC15A, and VCC15ADCx.

3. For more details on VCCPLLx capacitor recommendations, refer to the application note AC359, SmartFusion cSoC

Board Design Guidelines, the "PLL Power Supply Decoupling Scheme" section.

5-4

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

User-Defined Supply Pins

Polarity/

Name

Type Bus Size

Description

VAREF0

Input

1

Analog reference voltage for first ADC

The SmartFusion cSoC can be configured to generate a 2.56 V internal reference

that can be used by the ADC. While using the internal reference, the reference

voltage is output on the VAREFOUT pin for use as a system reference. If a

different reference voltage is required, it can be supplied by an external source

and applied to this pin. The valid range of values that can be supplied to the ADC

is 1.0 V to 3.3 V. When VAREF0 is internally generated, a bypass capacitor must

be connected from this pin to ground. The value of the bypass capacitor should be

between 3.3 µF and 22 µF, which is based on the needs of the individual designs.

The choice of the capacitor value has an impact on the settling time it takes the

VAREF0 signal to reach the required specification of 2.56 V to initiate valid

conversions by the ADC. If the lower capacitor value is chosen, the settling time

required for VAREF0 to achieve 2.56 V will be shorter than when selecting the

larger capacitor value. The above range of capacitor values supports the accuracy

specification of the ADC, which is detailed in the datasheet. Designers choosing

the smaller capacitor value will not obtain as much margin in the accuracy as that

achieved with a larger capacitor value. See the Analog-to-Digital Converter (ADC)

section in the SmartFusion Programmable Analog User’s Guide for more

information. The SoC Products Group recommends customers use 10 µF as the

value of the bypass capacitor. Designers choosing to use an external VAREF0

need to ensure that a stable and clean VAREF0 source is supplied to the VAREF0

pin before initiating conversions by the ADC. To use the internal voltage reference,

you must connect the VAREFOUT pin to the appropriate ADC VAREFx input—

either the VAREF0 or VAREF1 pin—on the PCB.

VAREF1

Input

Out

1

Analog reference voltage for second ADC

See "VAREF0" above for more information.

VAREF2

Analog reference voltage for third ADC

See "VAREF0" above for more.

VAREFOUT

Internal 2.56 V voltage reference output. Can be used to provide the two ADCs

with a unique voltage reference externally by connecting VAREFOUT to both

VAREF0 and VAREF1. To use the internal voltage reference, you must connect

the VAREFOUT pin to the appropriate ADC VAREFx input—either the VAREF0 or

VAREF1 pin—on the PCB.

Revision 10

5-5

Pin Descriptions

Global I/O Naming Conventions

Gmn (Gxxx) refers to Global I/Os. These Global I/Os are used to connect the input to global networks.

Global networks have high fanout and low skew. The naming convention for Global I/Os is as follows:

G = Global

m = Global pin location associated with each CCC on the device:

–

A (northwest corner)

B (northeast corner)

C (east middle)

D (southeast corner)

E (southwest corner)

F (west middle)

n = Global input MUX and pin number of the associated Global location m—A0, A1, A2, B0, B1, B2,

C0, C1, or C2.

Global (GL) I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct

access to the global network (spines). Additionally, the global I/Os can be used as regular I/Os, since

they have identical capabilities.

Unused GL pins are configured as inputs with pull-up resistors. See more detailed descriptions of global

I/O connectivity in the clocking resources chapter of the SmartFusion FPGA Fabric User’s Guide and the

clock conditioning circuitry chapter of the SmartFusion Microcontroller Subsystem User’s Guide.

All inputs labeled GC/GF are direct inputs into the quadrant clocks. The inputs to the global network are

multiplexed, and only one input can be used as a global input. For example, if GAA0 is used as a

quadrant global input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All

inputs labeled GC/GF are direct inputs into the chip-level globals, and the rest are connected to the

quadrant globals.

User Pins

Polarity/B

us Size

Name

Type

Description

GPIO_x

In/out

32

Microcontroller Subsystem (MSS) General Purpose I/O (GPIO). The MSS GPIO pin

functions as an input, output, tristate, or bidirectional buffer with configurable interrupt

generation and Schmitt trigger support. Input and output signal levels are compatible

with the I/O standard selected.

Unused GPIO pins are tristated and do not include pull-up or pull-down resistors.

During power-up, the used GPIO pins are tristated with no pull-up or pull-down

resistors until Sys boot configures them.

Some of these pins are also multiplexed with integrated peripherals in the MSS (SPI,

I²C, and UART). These pins are located in Bank-2 (GPIO_16 to GPIO_31) for A2F060,

A2F200, and A2F500 devices.

GPIOs can be routed to dedicated I/O buffers (MSSIOBUF) or in some cases to the

FPGA fabric interface through an IOMUX. This allows GPIO pins to be multiplexed as

either I/Os for the FPGA fabric, the ARM^®Cortex-M3 or for given integrated MSS

peripherals. The MSS peripherals are not multiplexed with each other; they are

multiplexed only with the GPIO block. For more information, see the General Purpose

I/O Block (GPIO) section in the SmartFusion Microcontroller Subsystem User’s Guide.

IO

In/out

FPGA user I/O

5-6

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

User I/O Naming Conventions

The naming convention used for each FPGA user I/O is Gmn/IOuxwByVz, where:

Gmn is only used for I/Os that also have CCC access—i.e., global pins. Refer to the "Global I/O Naming

Conventions" section on page 5-6.

u = I/O pair number in bank, starting at 00 from the northwest I/O bank and proceeding in a clockwise

direction.

x = P (positive) or N (negative) or S (single-ended) or R (regular, single-ended).

w = D (Differential Pair), P (Pair), or S (Single-Ended). D (Differential Pair) if both members of the pair

are bonded out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of

the pair are bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is

not bonded out. For Differential Pairs (D), adjacency for ball grid packages means only vertical or

horizontal. Diagonal adjacency does not meet the requirements for a true differential pair.

B = Bank

y = Bank number starting at 0 from northwest I/O bank and incrementing clockwise.

V = Reference voltage

z = VREF mini bank number.

The FPGA user I/O pin functions as an input, output, tristate or bidirectional buffer. Input and output

signal levels are compatible with the I/O standard selected. Unused I/O pins are disabled by Libero SoC

software and include a weak pull-up resistor. During power-up, the used I/O pins are tristated with no

pull-up or pull-down resistors until I/O enable (there is a delay after voltage stabilizes, and different I/O

banks power up sequentially to avoid a surge of ICCI).

Unused I/Os are configured as follows:

•

Output buffer is disabled (with tristate value of high impedance)

Input buffer is disabled (with tristate value of high impedance)

Weak pull-up is programmed

Some of these pins are also multiplexed with integrated peripherals in the MSS (Ethernet MAC and

external memory controller).

Unused MSS I/Os are neither weakly pulled-up nor weakly pulled-down. The Schmitt trigger is disabled.

Essentially, I/Os have the reset values as defined in Table 19-25 IOMUX_n_CR, in the SmartFusion

Microcontroller Subsystem User's Guide.

By default, during programming I/Os become tristated and weakly pulled up to VCCxxxxIOBx. You can

modify the I/O states during programming in FlashPro. For more details, refer to "Specifying I/O States

During Programming" on page 1-3. With the VCCI and VCC supplies continuously powered up, when the

device transitions from programming to operating mode, the I/Os are instantly configured to the desired

user configuration. For more information, see the SmartFusion FPGA User I/Os section in the

SmartFusion FPGA Fabric User’s Guide.

Revision 10

5-7

Pin Descriptions

Special Function Pins

Name

Type Polarity/Bus Size

Description

NC

No connect

This pin is not connected to circuitry within the device. These pins can

be driven to any voltage or can be left floating with no effect on the

operation of the device.

DC

Do not connect.

This pin should not be connected to any signals on the PCB. These

pins should be left unconnected.

LPXIN

In

1

Low power 32 KHz crystal oscillator.

Input from the 32 KHz oscillator. Pin for connecting a low power 32

KHz watch crystal. If not used, the LPXIN pin can be left floating. For

more information, see the PLLs, Clock Conditioning Circuitry, and On-

Chip Crystal Oscillators section in the SmartFusion Microcontroller

Subsystem User’s Guide.

LPXOUT

MAINXIN

Low power 32 KHz crystal oscillator.

Output to the 32 KHz oscillator. Pin for connecting a low power 32 KHz

watch crystal. If not used, the LPXOUT pin can be left floating. For

more information, see the PLLs, Clock Conditioning Circuitry, and On-

Chip Crystal Oscillators section in the SmartFusion Microcontroller

Subsystem User’s Guide.

Main crystal oscillator circuit.

Input to the crystal oscillator circuit. Pin for connecting an external

crystal, ceramic resonator, or RC network. When using an external

crystal or ceramic oscillator, external capacitors are also

recommended. Refer to documentation from the crystal oscillator

manufacturer for proper capacitor value.

If an external RC network or clock input is used, the RC components

are connected to the MAINXIN pin, with MAINXOUT left floating. When

the main crystal oscillator is not being used, MAINXIN and MAINXOUT

pins can be left floating.

For more information, see the PLLs, Clock Conditioning Circuitry, and

On-Chip Crystal Oscillators section in the SmartFusion Microcontroller

Subsystem User’s Guide.

MAINXOUT

Out

1

Main crystal oscillator circuit.

Output from the crystal oscillator circuit. Pin for connecting external

crystal or ceramic resonator. When using an external crystal or ceramic

oscillator, external capacitors are also recommended. Refer to

documentation from the crystal oscillator manufacturer for proper

capacitor value.

If an external RC network or clock input is used, the RC components

are connected to the MAINXIN pin, with MAINXOUT left floating. When

the main crystal oscillator is not being used, MAINXIN and MAINXOUT

pins can be left floating.

For more information, see the PLLs, Clock Conditioning Circuitry, and

On-Chip Crystal Oscillators section in the SmartFusion Microcontroller

Subsystem User’s Guide.

5-8

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Name

Type Polarity/Bus Size

Description

NCAP

1

Negative capacitor connection.

This is the negative terminal of the charge pump. A capacitor, with a

2.2 µF recommended value, is required to connect between PCAP and

NCAP. Analog charge pump capacitors are not needed if none of the

analog SCB features are used and none of the SDDs are used. In that

case it should be left unconnected.

PCAP

1

Positive Capacitor connection.

This is the positive terminal of the charge pump. A capacitor, with a 2.2

µF recommended value, is required to connect between PCAP and

NCAP. If this pin is not used, it must be left unconnected/floating. In this

case, no capacitor is needed. Analog charge pump capacitors are not

needed if none of the analog SCB features are used, and none of the

SDDs are used.

PTBASE

PTEM

1

Pass transistor base connection

This is the control signal of the voltage regulator. This pin should be

connected to the base of an external pass transistor used with the

1.5 V internal voltage regulator and can be floating if not used.

Pass transistor emitter connection.

This is the feedback input of the voltage regulator.

This pin should be connected to the emitter of an external pass

transistor used with the 1.5 V internal voltage regulator and can be

floating if not used.

MSS_RESET_N

Low

Low Reset signal which can be used as an external reset and can also

be used as a system level reset under control of the Cortex-M3

processor. MSS_RESET_N is an output asserted low after power-on

reset. The direction of MSS_RESET_N changes during the execution

of the Microsemi System Boot when chip-level reset is enabled. The

Microsemi System Boot reconfigures MSS_RESET_N to become a

reset input signal when chip-level reset is enabled. It has an internal

pull-up so it can be left floating. In the current software, the

MSS_RESET_N is modeled as an external input signal only.

PU_N

In

Low

Push-button is the connection for the external momentary switch used

to turn on the 1.5 V voltage regulator and can be floating if not used.

Revision 10

5-9

Pin Descriptions

JTAG Pins

SmartFusion cSoCs have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any

voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate,

even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the

SmartFusion cSoC part must be supplied to allow JTAG signals to transition the SmartFusion cSoC.

Isolating the JTAG power supply in a separate I/O bank gives greater flexibility with supply selection and

simplifies power supply and PCB design. If the JTAG interface is neither used nor planned to be used,

the VJTAG pin together with the TRSTB pin could be tied to GND.

Polarity/

Name

Type Bus Size

Description

JTAGSEL

In

1

JTAG controller selection

Depending on the state of the JTAGSEL pin, an external JTAG controller will either

see the FPGA fabric TAP/auxiliary TAP (High) or the Cortex-M3 JTAG debug

interface (Low).

The JTAGSEL pin should be connected to an external pull-up resistor such that the

default configuration selects the FPGA fabric TAP.

TCK

In

1

Test clock

Serial input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an

internal pull-up/-down resistor. If JTAG is not used, it is recommended to tie off TCK

to GND or V_JTAGthrough a resistor placed close to the FPGA pin. This prevents

JTAG operation in case TMS enters an undesired state.

Note that to operate at all V_JTAGvoltages, 500  to 1 k will satisfy the requirements.

Refer to Table 5-1 on page 5-11 for more information.

Can be left floating when unused.

Test data

TDI

In

1

Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal

weak pull-up resistor on the TDI pin.

TDO

TMS

Out

In

1

Test data

Serial output for JTAG boundary scan, ISP, and UJTAG usage.

HIGH

Test mode select

The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK, TDI, TDO,

TRST). There is an internal weak pull-up resistor on the TMS pin.

Can be left floating when unused.

Boundary scan reset pin

TRSTB

In

HIGH

The TRST pin functions as an active low input to asynchronously initialize (or reset)

the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST

pin. If JTAG is not used, an external pull-down resistor could be included to ensure

the TAP is held in reset mode. The resistor values must be chosen from Table 5-1 on

page 5-11 and must satisfy the parallel resistance value requirement. The values in

Table 5-1 on page 5-11 correspond to the resistor recommended when a single

device is used. The values correspond to the equivalent parallel resistor when

multiple devices are connected via a JTAG chain.

In critical applications, an upset in the JTAG circuit could allow entering an undesired

JTAG state. In such cases, it is recommended that you tie off TRST to GND through a

resistor placed close to the FPGA pin.

The TRSTB pin also resets the serial wire JTAG – debug port (SWJ-DP) circuitry

within the Cortex-M3.

Can be left floating when unused.

5-10

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Table 5-1 • Recommended Tie-Off Values for the TCK and TRST Pins

VJTAG

Tie-Off Resistance^{1, 2}

200  to 1 k

VJTAG at 3.3 V

VJTAG at 2.5 V

VJTAG at 1.8 V

VJTAG at 1.5 V

Notes:

200  to 1 k

500  to 1 k

1. The TCK pin can be pulled up/down.

2. The TRST pin can only be pulled down.

1. Equivalent parallel resistance if more than one device is on JTAG chain.

Revision 10

5-11

Pin Descriptions

Microcontroller Subsystem (MSS)

Polarity/

Name

Type

Bus Size

Description

External Memory Controller

EMC_ABx

Out

26

External memory controller address bus

Can also be used as an FPGA user I/O (see "IO" on page 5-6).

EMC_BYTENx

EMC_CLK

LOW/2

Rise

External memory controller byte enable

Can also be used as an FPGA user I/O (see "IO" on page 5-6).

Out

External memory controller clock

Can also be used as an FPGA user I/O (see "IO" on page 5-6).

EMC_CSx_N

EMC_DBx

Out

LOW/2

16

External memory controller chip selects

Can also be used as an FPGA User IO (see "IO" on page 5-6).

In/out

Out

External memory controller data bus

Can also be used as an FPGA user I/O (see "IO" on page 5-6).

EMC_OENx_N

EMC_RW_N

LOW/2

Level

External memory controller output enables

Can also be used as an FPGA User IO (see "IO" on page 5-6).

Out

External memory controller read/write. Read = High, write = Low.

Can also be used as an FPGA user I/O (see "IO" on page 5-6).

Inter-Integrated Circuit (I²C) Peripherals

I2C_0_SCL

I2C_0_SDA

I2C_1_SCL

I2C_1_SDA

In/out

1

I²C bus serial clock output. First I²C.

Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6).

I²C bus serial data input/output. First I²C.

Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6).

I²C bus serial clock output. Second I²C.

Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6).

I²C bus serial data input/output. Second I²C.

Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6).

Serial Peripheral Interface (SPI) Controllers

SPI_0_CLK

Out

1

Clock. First SPI.

Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6).

SPI_0_DI

In

Data input. First SPI.

Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6).

SPI_0_DO

SPI_0_SS

SPI_1_CLK

SPI_1_DI

Out

In

Data output. First SPI.

Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6).

Slave select (chip select). First SPI.

Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6).

Clock. Second SPI.

Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6).

Data input. Second SPI.

Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6).

5-12

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Polarity/

Bus Size

Name

Type

Description

SPI_1_DO

Out

1

Data output. Second SPI.

Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6).

SPI_1_SS

Out

1

Slave select (chip select). Second SPI.

Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6).

Universal Asynchronous Receiver/Transmitter (UART) Peripherals

UART_0_RXD

UART_0_TXD

UART_1_RXD

UART_1_TXD

In

Out

In

1

Receive data. First UART.

Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6).

Transmit data. First UART.

Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6).

Receive data. Second UART.

Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6).

Out

Transmit data. Second UART.

Can also be used as an MSS GPIO (see "GPIO_x" on page 5-6).

Ethernet MAC

MAC_CLK

In

Rise

High

Rise

1

Receive clock. 50 MHz ± 50 ppm clock source received from RMII PHY.

Can be left floating when unused.

MAC_CRSDV

MAC_MDC

MAC_MDIO

MAC_RXDx

Carrier sense/receive data valid for RMII PHY

Can also be used as an FPGA User IO (see "IO" on page 5-6).

Out

In/Out

In

RMII management clock

Can also be used as an FPGA User IO (see "IO" on page 5-6).

RMII management data input/output

Can also be used as an FPGA User IO (see "IO" on page 5-6).

2

Ethernet MAC receive data. Data recovered and decoded by PHY. The

RXD[0] signal is the least significant bit.

Can also be used as an FPGA User I/O (see "IO" on page 5-6).

MAC_RXER

In

HIGH

Ethernet MAC receive error. If MACRX_ER is asserted during reception,

the frame is received and status of the frame is updated with

MACRX_ER.

Can also be used as an FPGA user I/O (see "IO" on page 5-6).

MAC_TXDx

MAC_TXEN

Out

2

Ethernet MAC transmit data. The TXD[0] signal is the least significant

bit.

Can also be used as an FPGA user I/O (see "IO" on page 5-6).

HIGH

Ethernet MAC transmit enable. When asserted, indicates valid data for

the PHY on the TXD port.

Can also be used as an FPGA User I/O (see "IO" on page 5-6).

Revision 10

5-13

Pin Descriptions

Analog Front-End (AFE)

Associated With

Name

Type

Description

ADC/SDD

SCB

ABPS0

In

SCB 0 / active bipolar prescaler input 1.

ADC0

SCB0

See the Active Bipolar Prescaler (ABPS) section in the SmartFusion

Programmable Analog User’s Guide.

ABPS1

ABPS2

ABPS3

ABPS4

ABPS5

ABPS6

ABPS7

ABPS8

ABPS9

ADC0

In

SCB 0 / active bipolar prescaler Input 2

SCB 1 / active bipolar prescaler Input 1

SCB 1 / active bipolar prescaler Input 2

SCB 2 / active bipolar prescaler Input 1

SCB 2 / active bipolar prescaler Input 2

SCB 3 / active bipolar prescaler Input 1

SCB 3 / active bipolar prescaler input 2

SCB 4 / active bipolar prescaler input 1

SCB 4 / active bipolar prescaler input 2

ADC 0 direct input 0 / FPGA Input.

ADC0

ADC1

ADC2

ADC0

SCB0

SCB1

SCB2

SCB3

SCB4

SCB0

See the "Sigma-Delta Digital-to-Analog Converter (DAC)" section in

the SmartFusion Programmable Analog User’s Guide.

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

ADC8

ADC9

ADC10

ADC11

CM0

In

ADC 0 direct input 1 / FPGA input

ADC 0 direct input 2 / FPGA input

ADC 0 direct input 3 / FPGA input

ADC 1 direct input 0 / FPGA input

ADC 1 direct input 1 / FPGA input

ADC 1 direct input 2 / FPGA input

ADC 1 direct input 3 / FPGA input

ADC 2 direct input 0 / FPGA input

ADC 2 direct input 1 / FPGA input

ADC 2 direct input 2 / FPGA input

ADC 2 direct input 3 / FPGA input

SCB 0 / high side of current monitor / comparator

ADC0

ADC1

ADC2

ADC0

SCB0

SCB1

SCB2

SCB3

SCB4

N/A

SCB0

Positive input. See the Current Monitor section in the SmartFusion

Programmable Analog User’s Guide.

CM1

CM2

CM3

CM4

In

SCB 1 / high side of current monitor / comparator. Positive input.

SCB 2 / high side of current monitor / comparator. Positive input.

SCB 3 / high side of current monitor / comparator. Positive input.

SCB 4 / high side of current monitor / comparator. Positive input.

ADC0

ADC1

ADC2

SCB1

SCB2

SCB3

SCB4

Note: Unused analog inputs should be grounded. This aids in shielding and prevents an undesired coupling path.

5-14

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Associated With

Name

Type

Description

ADC/SDD

SCB

TM0

In

SCB 0 / low side of current monitor / comparator

ADC0

SCB0

Negative input / high side of temperature monitor. See the

Temperature Monitor section.

TM1

TM2

TM3

TM4

SDD0

In

SCB 1 / low side of current monitor / comparator. Negative input /

high side of temperature monitor.

ADC0

ADC1

ADC2

SDD0

SCB1

SCB2

SCB3

SCB4

N/A

SCB 2 / low side of current monitor / comparator. Negative input /

high side of temperature monitor.

In

SCB 3 low side of current monitor / comparator. Negative input / high

side of temperature monitor.

In

SCB 4 low side of current monitor / comparator. Negative input / high

side of temperature monitor.

Out

Output of SDD0

See the Sigma-Delta Digital-to-Analog Converter (DAC) section in

the SmartFusion Programmable Analog User’s Guide.

SDD1

SDD2

Out

Output of SDD1

Output of SDD2

SDD1

SDD2

N/A

Note: Unused analog inputs should be grounded. This aids in shielding and prevents an undesired coupling path.

Revision 10

5-15

Pin Descriptions

Analog Front-End Pin-Level Function Multiplexing

Table 5-2 describes the relationships between the various internal signals found in the analog front-end

(AFE) and how they are multiplexed onto the external package pins. Note that, in general, only one

function is available for those pads that have numerous functions listed. The exclusion to this rule is

when a comparator is used; the ADC can still convert either input side of the comparator.

Table 5-2 • Relationships Between Signals in the Analog Front-End

ADC

Dir.-In

Current Temp.

Channel Option Prescaler

Mon.

Compar.

LVTTL

SDD MUX

SDD

ABPS0 ADC0_CH1

ABPS1 ADC0_CH2

ABPS2 ADC0_CH5

ABPS3 ADC0_CH6

ABPS4 ADC1_CH1

ABPS5 ADC1_CH2

ABPS6 ADC1_CH5

ABPS7 ADC1_CH6

ABPS8 ADC2_CH1

ABPS9 ADC2_CH2

ABPS0_IN

ABPS1_IN

ABPS2_IN

ABPS3_IN

ABPS4_IN

ABPS5_IN

ABPS6_IN

ABPS7_IN

ABPS8_IN

ABPS9_IN

ADC0

ADC0_CH9

Yes

CMP1_P LVTTL0_IN

ADC1 ADC0_CH10 Yes

ADC2 ADC0_CH11 Yes

ADC3 ADC0_CH12 Yes

CMP1_N LVTTL1_IN SDDM0_OUT

CMP3_P LVTTL2_IN

CMP3_N LVTTL3_IN SDDM1_OUT

CMP5_P LVTTL4_IN

CMP5_N LVTTL5_IN SDDM2_OUT

CMP7_P LVTTL6_IN

CMP7_N LVTTL7_IN SDDM3_OUT

CMP9_P LVTTL8_IN

CMP9_N LVTTL9_IN SDDM4_OUT

LVTTL10_IN

ADC4

ADC1_CH9

Yes

ADC5 ADC1_CH10 Yes

ADC6 ADC1_CH11 Yes

ADC7 ADC1_CH12 Yes

ADC8

ADC2_CH9

Yes

ADC9 ADC2_CH10 Yes

ADC10 ADC2_CH11 Yes

ADC11 ADC2_CH12 Yes

LVTTL11_IN

CM0

CM1

CM2

CM3

CM4

ADC0_CH3

ADC0_CH7

ADC1_CH3

ADC1_CH7

ADC2_CH3

Yes

CM0_H

CM1_H

CM2_H

CM3_H

CM4_H

CMP0_P

CMP2_P

CMP4_P

CMP6_P

CMP8_P

SDD0 ADC0_CH15

SDD1 ADC1_CH15

Notes:

SDD0_OUT

SDD1_OUT

1. ABPSx_IN: Input to active bipolar prescaler channel x.

2. CMx_H/L: Current monitor channel x, high/low side.

3. TMx_IO: Temperature monitor channel x.

4. CMPx_P/N: Comparator channel x, positive/negative input.

5. LVTTLx_IN: LVTTL I/O channel x.

6. SDDMx_OUT: Output from sigma-delta DAC MUX channel x.

7. SDDx_OUT: Direct output from sigma-delta DAC channel x.

5-16

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Table 5-2 • Relationships Between Signals in the Analog Front-End

ADC Dir.-In Current Temp.

Channel Option Prescaler Mon. Mon.

SDD2 ADC2_CH15

Compar.

LVTTL

SDD MUX

SDD

SDD2_OUT

TM0

TM1

TM2

TM3

TM4

Notes:

ADC0_CH4

ADC0_CH8

ADC1_CH4

ADC1_CH8

ADC2_CH4

Yes

CM0_L TM0_IO CMP0_N

CM1_L TM1_IO CMP2_N

CM2_L TM2_IO CMP4_N

CM3_L TM3_IO CMP6_N

CM4_L TM4_IO CMP8_N

1. ABPSx_IN: Input to active bipolar prescaler channel x.

2. CMx_H/L: Current monitor channel x, high/low side.

3. TMx_IO: Temperature monitor channel x.

4. CMPx_P/N: Comparator channel x, positive/negative input.

5. LVTTLx_IN: LVTTL I/O channel x.

6. SDDMx_OUT: Output from sigma-delta DAC MUX channel x.

7. SDDx_OUT: Direct output from sigma-delta DAC channel x.

Revision 10

5-17

Pin Descriptions

Pin Assignment Tables

TQ144

144

1

144-Pin

TQFP

Note

For Package Manufacturing and Environmental

information, visit the Resource Center at

http://www.microsemi.com/soc/products/solutions/

package/docs.aspx.

5-18

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

TQ144

A2F060 Function

TQ144

Pin Number

37

A2F060 Function

VCC33AP

VCC33N

SDD0

1

VCCPLL0

VCOMPLA0

2

38

3

GNDQ

39

4

GFA2/IO42PDB5V0

GFB2/IO42NDB5V0

GFC2/IO41PDB5V0

IO41NDB5V0

VCC

40

GNDA

5

41

GNDAQ

ADC0

6

42

7

43

8

44

ADC1

9

GND

45

ADC2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

VCCFPGAIOB5

IO38PDB5V0

IO38NDB5V0

IO36PDB5V0

IO36NDB5V0

GND

46

ADC3

47

ADC4

48

ADC5

49

ADC6

50

ADC7

51

ADC8

GNDRCOSC

VCCRCOSC

52

ADC9

53

ADC10

MSS_RESET_N

GPIO_0/IO33RSB4V0

GPIO_1/IO32RSB4V0

GPIO_2/IO31RSB4V0

GPIO_3/IO30RSB4V0

GPIO_4/IO29RSB4V0

GND

54

NC

55

NC

56

NC

57

GND15ADC0

VCC15ADC0

GND33ADC0

VCC33ADC0

GND33ADC0

VAREF0

ABPS0

58

59

60

VCCMSSIOB4

VCC

61

62

GPIO_5/IO28RSB4V0

GPIO_6/IO27RSB4V0

GPIO_7/IO26RSB4V0

GPIO_8/IO25RSB4V0

VCCESRAM

63

64

ABPS1

65

CM0

66

TM0

67

GNDTM0

GNDAQ

GNDA

GNDSDD0

68

VCC33SDD0

VCC15A

69

70

GNDVAREF

VAREFOUT

PU_N

PCAP

71

NCAP

72

Revision 10

5-19

Pin Descriptions

TQ144

A2F060 Function

Pin Number

73

74

VCC33A

PTEM

75

PTBASE

76

SPI_0_DO/GPIO_16

SPI_0_DI/GPIO_17

SPI_0_CLK/GPIO_18

SPI_0_SS/GPIO_19

UART_0_RXD/GPIO_21

UART_0_TXD/GPIO_20

UART_1_RXD/GPIO_29

UART_1_TXD/GPIO_28

VCC

77

78

79

80

81

82

83

84

85

VCCMSSIOB2

GND

86

87

I2C_1_SDA/GPIO_30

I2C_1_SCL/GPIO_31

I2C_0_SDA/GPIO_22

I2C_0_SCL/GPIO_23

GNDENVM

88

89

90

91

92

VCCENVM

93

JTAGSEL

94

TCK

95

TDI

96

TMS

97

TDO

98

TRSTB

99

VJTAG

100

101

102

103

104

105

106

107

108

VDDBAT

VCCLPXTAL

LPXOUT

LPXIN

GNDLPXTAL

GNDMAINXTAL

MAINXOUT

MAINXIN

VCCMAINXTAL

5-20

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

TQ144

A2F060 Function

Pin Number

109

110

111

VPP

GNDQ

GCA1/IO20PDB0V0

GCA0/IO20NDB0V0

GCB1/IO19PDB0V0

GCB0/IO19NDB0V0

GCC1/IO18PDB0V0

GCC0/IO18NDB0V0

VCCFPGAIOB0

GND

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

VCC

IO14PDB0V0

IO14NDB0V0

IO13NSB0V0

IO11PDB0V0

IO11NDB0V0

IO09PDB0V0

IO09NDB0V0

VCCFPGAIOB0

GND

IO07PDB0V0

IO07NDB0V0

IO06PDB0V0

IO06NDB0V0

IO05PDB0V0

IO05NDB0V0

IO03PDB0V0

IO03NDB0V0

VCCFPGAIOB0

GND

VCC

IO01PDB0V0

IO01NDB0V0

IO00PDB0V0

IO00NDB0V0

GNDQ

Revision 10

5-21

Pin Descriptions

CS288

A1 Ball Pad Corner

21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

Note: Bottom view

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.microsemi.com/soc/products/solutions/package/docs.aspx.

5-22

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

CS288

No.

A2F060 Function

A2F200 Function

VCCFPGAIOB0

GNDQ

A2F500 Function

VCCFPGAIOB0

GNDQ

A1

A2

VCCFPGAIOB0

GNDQ

A3

EMC_CLK/IO00NDB0V0

EMC_CLK/GAA0/IO00NDB0V0

EMC_RW_N/GAA1/IO00PDB0V0

GND

EMC_CLK/GAA0/IO02NDB0V0

EMC_RW_N/GAA1/IO02PDB0V0

GND

A4

EMC_RW_N/IO00PDB0V0

A5

GND

A6

EMC_CS1_N/IO01PDB0V0

EMC_CS1_N/GAB1/IO01PDB0V0

EMC_CS0_N/GAB0/IO01NDB0V0

EMC_AB[0]/IO04NPB0V0

VCCFPGAIOB0

EMC_AB[4]/IO06NDB0V0

EMC_AB[8]/IO08NPB0V0

EMC_AB[14]/IO11NPB0V0

GND

EMC_CS1_N/GAB1/IO05PDB0V0

EMC_CS0_N/GAB0/IO05NDB0V0

EMC_AB[0]/IO06NPB0V0

VCCFPGAIOB0

EMC_AB[4]/IO10NDB0V0

EMC_AB[8]/IO13NPB0V0

EMC_AB[14]/IO15NPB0V0

GND

A7

EMC_CS0_N/IO01NDB0V0

A8

EMC_AB[0]/IO04NPB0V0

A9

VCCFPGAIOB0

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA10

AA11

AA12

AA13

EMC_AB[4]/IO06NDB0V0

EMC_AB[8]/IO08NPB0V0

EMC_AB[14]/IO11NPB0V0

GND

EMC_AB[18]/IO13NDB0V0

EMC_AB[24]/IO16NDB0V0

EMC_AB[25]/IO16PDB0V0

VCCFPGAIOB0

EMC_AB[20]/IO14NDB0V0

EMC_AB[21]/IO14PDB0V0

GNDQ

EMC_AB[18]/IO18NDB0V0

EMC_AB[24]/IO20NDB0V0

EMC_AB[25]/IO20PDB0V0

VCCFPGAIOB0

EMC_AB[20]/IO21NDB0V0

EMC_AB[21]/IO21PDB0V0

GNDQ

EMC_AB[24]/IO16NDB0V0

EMC_AB[25]/IO16PDB0V0

VCCFPGAIOB0

EMC_AB[20]/IO14NDB0V0

EMC_AB[21]/IO14PDB0V0

GNDQ

GND

ADC1

GNDAQ

GNDA

VCC33N

SDD0

ADC0

NC

ABPS1

GNDAQ

GNDA

VCC33N

SDD0

ABPS0

GNDTM0

NC

ABPS2

NC

VAREF0

NC

GND15ADC0

ADC9

ABPS1

ADC6

ABPS7

TM2

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

Revision 10

5-23

Pin Descriptions

CS288

A2F200 Function

ABPS4

No.

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

B1

A2F060 Function

A2F500 Function

ABPS4

NC

SDD1

GNDVAREF

VAREFOUT

PU_N

VCC33A

PTEM

GND

B21

C1

IO17PDB0V0

GBB2/IO20NDB1V0

EMC_DB[15]/GAA2/IO71PDB5V0

VCOMPLA

GBB2/IO27NDB1V0

EMC_DB[15]/GAA2/IO88PDB5V0

VCOMPLA0

EMC_DB[15]/IO45PDB5V0

VCOMPLA0

C3

C4

VCCPLL0

VCCPLL

VCCPLL0

C5

VCCFPGAIOB0

EMC_AB[1]/IO04PPB0V0

GND

VCCFPGAIOB0

EMC_AB[1]/IO04PPB0V0

GND

VCCFPGAIOB0

EMC_AB[1]/IO06PPB0V0

GND

C6

C7

C8

EMC_OEN0_N/IO03NDB0V0

EMC_AB[2]/IO05NDB0V0

EMC_AB[5]/IO06PDB0V0

VCCFPGAIOB0

EMC_AB[9]/IO08PPB0V0

EMC_AB[15]/IO11PPB0V0

EMC_AB[19]/IO13PDB0V0

GND

EMC_OEN0_N/IO03NDB0V0

EMC_AB[2]/IO05NDB0V0

EMC_AB[5]/IO06PDB0V0

VCCFPGAIOB0

EMC_AB[9]/IO08PPB0V0

EMC_AB[15]/IO11PPB0V0

EMC_AB[19]/IO13PDB0V0

GND

EMC_OEN0_N/IO08NDB0V0

EMC_AB[2]/IO09NDB0V0

EMC_AB[5]/IO10PDB0V0

VCCFPGAIOB0

EMC_AB[9]/IO13PPB0V0

EMC_AB[15]/IO15PPB0V0

EMC_AB[19]/IO18PDB0V0

GND

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C21

D1

EMC_AB[22]/IO15NDB0V0

EMC_AB[23]/IO15PDB0V0

NC

EMC_AB[22]/IO15NDB0V0

EMC_AB[23]/IO15PDB0V0

NC

EMC_AB[22]/IO19NDB0V0

EMC_AB[23]/IO19PDB0V0

VCCPLL1

NC

VCOMPLA1

IO17NDB0V0

GBA2/IO20PDB1V0

EMC_DB[14]/GAB2/IO71NDB5V0

VCCFPGAIOB5

GND

GBA2/IO27PDB1V0

EMC_DB[14]/GAB2/IO88NDB5V0

VCCFPGAIOB5

GND

EMC_DB[14]/IO45NDB5V0

VCCFPGAIOB5

GND

D3

D19

D21

E1

VCCFPGAIOB1

EMC_DB[13]/IO44PDB5V0

VCCFPGAIOB1

EMC_DB[13]/GAC2/IO70PDB5V0

VCCFPGAIOB1

EMC_DB[13]/GAC2/IO87PDB5V0

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

5-24

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

CS288

No.

A2F060 Function

EMC_DB[12]/IO44NDB5V0

GNDQ

A2F200 Function

EMC_DB[12]/IO70NDB5V0

GNDQ

A2F500 Function

EMC_DB[12]/IO87NDB5V0

GNDQ

E3

E5

E6

EMC_BYTEN[0]/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO07NDB0V0

EMC_BYTEN[1]/IO02PDB0V0 EMC_BYTEN[1]/GAC1/IO02PDB0V0 EMC_BYTEN[1]/GAC1/IO07PDB0V0

E7

E8

EMC_OEN1_N/IO03PDB0V0

EMC_AB[3]/IO05PDB0V0

EMC_AB[10]/IO09NDB0V0

EMC_AB[7]/IO07PDB0V0

EMC_AB[13]/IO10PDB0V0

EMC_AB[16]/IO12NDB0V0

EMC_AB[17]/IO12PDB0V0

GCC0/IO18NPB0V0

GCA1/IO20PPB0V0

GCC1/IO18PPB0V0

GCB2/IO22PPB1V0

IO21NDB1V0

EMC_OEN1_N/IO03PDB0V0

EMC_AB[3]/IO05PDB0V0

EMC_AB[10]/IO09NDB0V0

EMC_AB[7]/IO07PDB0V0

EMC_AB[13]/IO10PDB0V0

EMC_AB[16]/IO12NDB0V0

EMC_AB[17]/IO12PDB0V0

GCB0/IO27NDB1V0

GCB1/IO27PDB1V0

GCB2/IO24PDB1V0

GCA0/IO28NDB1V0

GCA1/IO28PDB1V0

VCCFPGAIOB5

EMC_OEN1_N/IO08PDB0V0

EMC_AB[3]/IO09PDB0V0

EMC_AB[10]/IO11NDB0V0

EMC_AB[7]/IO12PDB0V0

EMC_AB[13]/IO14PDB0V0

EMC_AB[16]/IO17NDB0V0

EMC_AB[17]/IO17PDB0V0

GCB0/IO34NDB1V0

GCB1/IO34PDB1V0

GCB2/IO33PDB1V0

GCA0/IO36NDB1V0

GCA1/IO36PDB1V0

VCCFPGAIOB5

E9

E10

E11

E12

E13

E14

E15

E16

E17

E19

E21

F1

VCCFPGAIOB5

F3

GFB2/IO42NDB5V0

GFA2/IO42PDB5V0

EMC_DB[11]/IO43PDB5V0

GND

GFB2/IO68NDB5V0

GFA2/IO68PDB5V0

EMC_DB[11]/IO69PDB5V0

GND

GFB2/IO85NDB5V0

GFA2/IO85PDB5V0

EMC_DB[11]/IO86PDB5V0

GND

F5

F6

F7

F8

NC

GFC1/IO66PPB5V0

VCCFPGAIOB0

GFC1/IO83PPB5V0

VCCFPGAIOB0

F9

VCCFPGAIOB0

F10

F11

F12

F13

F14

F15

F16

F17

F19

F21

G1

EMC_AB[11]/IO09PDB0V0

EMC_AB[6]/IO07NDB0V0

EMC_AB[12]/IO10NDB0V0

GND

EMC_AB[11]/IO09PDB0V0

EMC_AB[6]/IO07NDB0V0

EMC_AB[12]/IO10NDB0V0

GND

EMC_AB[11]/IO11PDB0V0

EMC_AB[6]/IO12NDB0V0

EMC_AB[12]/IO14NDB0V0

GND

GCB1/IO19PPB0V0

GNDQ

GCC1/IO26PPB1V0

GNDQ

GCC1/IO35PPB1V0

GNDQ

VCCFPGAIOB1

GCB0/IO19NPB0V0

IO23NDB1V0

IO24NDB1V0

IO33NDB1V0

GDB1/IO30PDB1V0

GDB0/IO30NDB1V0

IO67NDB5V0

GDB1/IO39PDB1V0

GDB0/IO39NDB1V0

IO84NDB5V0

GCA2/IO21PDB1V0

IO41NDB5V0

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

Revision 10

5-25

Pin Descriptions

CS288

A2F200 Function

GFC2/IO67PDB5V0

GFB1/IO65PDB5V0

EMC_DB[10]/IO69NDB5V0

GFC0/IO66NPB5V0

GCC0/IO26NPB1V0

GDA0/IO31NDB1V0

GDC1/IO29PDB1V0

GDC0/IO29NDB1V0

GND

No.

A2F060 Function

A2F500 Function

GFC2/IO84PDB5V0

GFB1/IO82PDB5V0

EMC_DB[10]/IO86NDB5V0

GFC0/IO83NPB5V0

GCC0/IO35NPB1V0

GDA0/IO40NDB1V0

GDC1/IO38PDB1V0

GDC0/IO38NDB1V0

GND

G3

GFC2/IO41PDB5V0

G5

NC

G6

EMC_DB[10]/IO43NDB5V0

G9

NC

G13

G16

G17

G19

G21

H1

GCA0/IO20NPB0V0

NC

IO22NPB1V0

GCC2/IO23PDB1V0

GND

EMC_DB[9]/IO40PPB5V0

EMC_DB[9]/GEC1/IO63PPB5V0

GND

EMC_DB[9]/GEC1/IO80PPB5V0

GND

H3

GND

H5

NC

GFB0/IO65NDB5V0

EMC_DB[7]/GEB1/IO62PDB5V0

GND

GFB0/IO82NDB5V0

EMC_DB[7]/GEB1/IO79PDB5V0

GND

H6

EMC_DB[7]/IO39PDB5V0

H8

GND

H9

VCC

H10

H11

H12

H13

H14

H16

H17

H19

H21

J1

GND

VCC

GND

VCC

GND

NC

GDA1/IO31PDB1V0

GDC2/IO32PPB1V0

VCCFPGAIOB1

GDB2/IO33PDB1V0

EMC_DB[4]/GEA0/IO61NPB5V0

EMC_DB[8]/GEC0/IO63NPB5V0

EMC_DB[1]/GEB2/IO59PDB5V0

EMC_DB[6]/GEB0/IO62NDB5V0

VCCFPGAIOB5

VCC

GDA1/IO40PDB1V0

GDC2/IO41PPB1V0

VCCFPGAIOB1

GDB2/IO42PDB1V0

EMC_DB[4]/GEA0/IO78NPB5V0

EMC_DB[8]/GEC0/IO80NPB5V0

EMC_DB[1]/GEB2/IO76PDB5V0

EMC_DB[6]/GEB0/IO79NDB5V0

VCCFPGAIOB5

VCC

NC

VCCFPGAIOB1

NC

EMC_DB[4]/IO38NPB5V0

J3

EMC_DB[8]/IO40NPB5V0

J5

EMC_DB[1]/IO36PDB5V0

J6

EMC_DB[6]/IO39NDB5V0

J7

VCCFPGAIOB5

VCC

J8

J9

GND

J10

J11

J12

VCC

GND

VCC

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

5-26

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

CS288

No.

A2F060 Function

A2F200 Function

A2F500 Function

J13

J14

J15

J16

J17

J19

J21

K1

GND

VCC

VPP

NC

IO32NPB1V0

IO41NPB1V0

NC

GNDQ

VCCMAINXTAL

NC

GDA2/IO33NDB1V0

GDA2/IO42NDB1V0

GND

K3

EMC_DB[5]/IO38PPB5V0

EMC_DB[5]/GEA1/IO61PPB5V0

EMC_DB[5]/GEA1/IO78PPB5V0

K5

EMC_DB[0]/IO36NDB5V0

EMC_DB[0]/GEA2/IO59NDB5V0

EMC_DB[0]/GEA2/IO76NDB5V0

K6

EMC_DB[3]/IO37PPB5V0

EMC_DB[3]/GEC2/IO60PPB5V0

EMC_DB[3]/GEC2/IO77PPB5V0

K8

GND

VCC

GND

VCC

GND

VCC

K9

K10

K11

K12

K13

K14

K16

K17

K19

K21

L1

GND

VCC

GND

VCC

GND

LPXOUT

GNDLPXTAL

GNDMAINXTAL

MAINXIN

GNDRCOSC

VCCFPGAIOB5

EMC_DB[2]/IO37NPB5V0

NC

LPXOUT

GNDLPXTAL

GNDMAINXTAL

MAINXIN

GNDRCOSC

VCCFPGAIOB5

EMC_DB[2]/IO60NPB5V0

GNDQ

LPXOUT

GNDLPXTAL

GNDMAINXTAL

MAINXIN

GNDRCOSC

VCCFPGAIOB5

EMC_DB[2]/IO77NPB5V0

GNDQ

L3

L5

L6

L8

VCC

L9

GND

L10

L12

L13

L14

L16

L17

VCC

GND

VCC

VCCLPXTAL

VDDBAT

VCCLPXTAL

VDDBAT

VCCLPXTAL

VDDBAT

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

Revision 10

5-27

Pin Descriptions

CS288

No.

L19

L21

M1

A2F060 Function

A2F200 Function

A2F500 Function

LPXIN

MAINXOUT

VCCRCOSC

M3

MSS_RESET_N

M5

GPIO_5/IO28RSB4V0

GPIO_5/IO42RSB4V0

GPIO_5/IO51RSB4V0

M6

GND

M8

GND

M9

VCC

M10

M11

M12

M13

M14

M16

M17

M19

M21

N1

GND

VCC

GND

VCC

GND

TMS

VJTAG

TDO

TRSTB

VCCMSSIOB4

N3

GND

N5

GPIO_4/IO29RSB4V0

GPIO_4/IO43RSB4V0

GPIO_4/IO52RSB4V0

N6

GPIO_8/IO25RSB4V0

GPIO_8/IO39RSB4V0

GPIO_8/IO48RSB4V0

N7

GPIO_9/IO24RSB4V0

GPIO_9/IO38RSB4V0

GPIO_9/IO47RSB4V0

N8

VCC

GND

VCC

GND

VCC

GND

N9

N10

N11

N12

N13

N14

N15

N16

N17

N19

N21

VCC

GND

VCC

GND

VCC

GND

TCK

TDI

GNDENVM

VCCENVM

GNDENVM

VCCENVM

GNDENVM

VCCENVM

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

5-28

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

CS288

No.

A2F060 Function

A2F200 Function

MAC_MDC/IO48RSB4V0

GPIO_7/IO40RSB4V0

GPIO_6/IO41RSB4V0

VCCMSSIOB4

GND

A2F500 Function

MAC_MDC/IO57RSB4V0

GPIO_7/IO49RSB4V0

GPIO_6/IO50RSB4V0

VCCMSSIOB4

GND

P1

P3

GPIO_0/IO33RSB4V0

GPIO_7/IO26RSB4V0

P5

GPIO_6/IO27RSB4V0

P6

VCCMSSIOB4

P8

GND

P9

VCC

P10

P11

P12

P13

P14

P16

P17

P19

P21

R1

GND

VCC

GND

VCC

GND

JTAGSEL

GND

JTAGSEL

I2C_0_SCL/GPIO_23

VCCMSSIOB2

GND

I2C_0_SCL/GPIO_23

VCCMSSIOB2

GND

I2C_0_SCL/GPIO_23

VCCMSSIOB2

GND

GPIO_2/IO31RSB4V0

GPIO_1/IO32RSB4V0

GPIO_3/IO30RSB4V0

GPIO_10/IO35RSB4V0

GNDA

MAC_MDIO/IO49RSB4V0

MAC_TXEN/IO52RSB4V0

MAC_TXD[0]/IO56RSB4V0

MAC_CRSDV/IO51RSB4V0

GNDA

MAC_MDIO/IO58RSB4V0

MAC_TXEN/IO61RSB4V0

MAC_TXD[0]/IO65RSB4V0

MAC_CRSDV/IO60RSB4V0

GNDA

R3

R5

R6

R9

R13

R16

R17

R19

R21

T1

GNDA

UART_1_RXD/GPIO_29

UART_1_TXD/GPIO_28

I2C_0_SDA/GPIO_22

I2C_1_SDA/GPIO_30

GND

UART_1_RXD/GPIO_29

UART_1_TXD/GPIO_28

I2C_0_SDA/GPIO_22

I2C_1_SDA/GPIO_30

GND

UART_1_RXD/GPIO_29

UART_1_TXD/GPIO_28

I2C_0_SDA/GPIO_22

I2C_1_SDA/GPIO_30

GND

T3

NC

MAC_TXD[1]/IO55RSB4V0

MAC_RXD[1]/IO53RSB4V0

MAC_RXER/IO50RSB4V0

CM1

MAC_TXD[1]/IO64RSB4V0

MAC_RXD[1]/IO62RSB4V0

MAC_RXER/IO59RSB4V0

CM1

T5

NC

T6

GPIO_11/IO34RSB4V0

NC

T7

T8

NC

ADC1

T9

NC

GND33ADC0

T10

T11

NC

VCC15ADC0

GND33ADC0

GND33ADC1

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

Revision 10

5-29

Pin Descriptions

CS288

A2F200 Function

VAREF1

No.

T12

T13

T14

T15

T16

T17

T19

T21

U1

A2F060 Function

A2F500 Function

VAREF1

VAREF0

ADC7

ADC4

TM0

TM3

SPI_1_SS/GPIO_27

VCCMSSIOB2

UART_0_RXD/GPIO_21

UART_0_TXD/GPIO_20

I2C_1_SCL/GPIO_31

NC

SPI_1_SS/GPIO_27

VCCMSSIOB2

UART_0_RXD/GPIO_21

UART_0_TXD/GPIO_20

I2C_1_SCL/GPIO_31

MAC_RXD[0]/IO54RSB4V0

VCCMSSIOB4

VCC33SDD0

VCC15A

SPI_1_SS/GPIO_27

VCCMSSIOB2

UART_0_RXD/GPIO_21

UART_0_TXD/GPIO_20

I2C_1_SCL/GPIO_31

MAC_RXD[0]/IO63RSB4V0

VCCMSSIOB4

VCC33SDD0

VCC15A

U3

VCCMSSIOB4

VCC33SDD0

VCC15A

U5

U6

U7

NC

ABPS3

U8

NC

ADC2

U9

NC

VCC33ADC0

GND15ADC1

VCC33ADC1

ADC7

VCC33ADC0

GND15ADC1

VCC33ADC1

ADC7

U10

U11

U12

U13

U14

U15

U16

U17

U19

U21

V1

GND15ADC0

VCC33ADC0

ADC10

ABPS0

ABPS6

GNDTM0

GNDTM1

SPI_1_CLK/GPIO_26

SPI_0_CLK/GPIO_18

SPI_0_SS/GPIO_19

GND

SPI_1_CLK/GPIO_26

SPI_0_CLK/GPIO_18

SPI_0_SS/GPIO_19

GND

SPI_1_CLK/GPIO_26

SPI_0_CLK/GPIO_18

SPI_0_SS/GPIO_19

GND

SPI_1_DO/GPIO_24

NC

SPI_1_DO/GPIO_24

MAC_CLK

SPI_1_DO/GPIO_24

MAC_CLK

V3

GNDSDD0

SPI_1_DI/GPIO_25

VCCMSSIOB2

PCAP

GNDSDD0

V19

V21

W1

W3

W4

W5

W6

SPI_1_DI/GPIO_25

VCCMSSIOB2

PCAP

SPI_1_DI/GPIO_25

VCCMSSIOB2

PCAP

NCAP

ADC2

CM0

ADC3

TM0

ADC4

TM1

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

5-30

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

CS288

No.

A2F060 Function

A2F200 Function

ADC0

A2F500 Function

ADC0

W7

W8

NC

ADC3

W9

NC

GND33ADC0

VCC15ADC1

GND33ADC1

ADC5

GND33ADC0

VCC15ADC1

GND33ADC1

ADC5

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W21

Y1

VCC15ADC0

GND33ADC0

ADC8

CM0

CM3

ADC5

CM2

NC

ABPS5

GNDAQ

NC

GNDAQ

VCC33SDD1

GNDSDD1

PTBASE

VCC33SDD1

GNDSDD1

PTBASE

NC

PTBASE

SPI_0_DI/GPIO_17

VCC33AP

SPI_0_DO/GPIO_16

SPI_0_DI/GPIO_17

VCC33AP

SPI_0_DO/GPIO_16

SPI_0_DI/GPIO_17

VCC33AP

SPI_0_DO/GPIO_16

Y21

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

Revision 10

5-31

Pin Descriptions

PQ208

208

1

208-Pin PQFP

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.microsemi.com/soc/products/solutions/package/docs.aspx.

5-32

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

PQ208

Pin Number

A2F200

VCCPLL

A2F500

1

VCCPLL0

2

VCOMPLA

VCOMPLA0

3

GNDQ

4

EMC_DB[15]/GAA2/IO71PDB5V0

EMC_DB[14]/GAB2/IO71NDB5V0

EMC_DB[13]/GAC2/IO70PDB5V0

EMC_DB[12]/IO70NDB5V0

VCC

GAA2/IO88PDB5V0

GAB2/IO88NDB5V0

GAC2/IO87PDB5V0

IO87NDB5V0

VCC

5

6

7

8

9

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

VCCFPGAIOB5

IO86PDB5V0

EMC_DB[11]/IO69PDB5V0

EMC_DB[10]/IO69NDB5V0

GFA2/IO68PSB5V0

GFA1/IO64PDB5V0

GFA0/IO64NDB5V0

EMC_DB[9]/GEC1/IO63PDB5V0

EMC_DB[8]/GEC0/IO63NDB5V0

EMC_DB[7]/GEB1/IO62PDB5V0

EMC_DB[6]/GEB0/IO62NDB5V0

EMC_DB[5]/GEA1/IO61PDB5V0

EMC_DB[4]/GEA0/IO61NDB5V0

VCC

IO86NDB5V0

GFA2/IO85PSB5V0

GFA1/IO81PDB5V0

GFA0/IO81NDB5V0

GEC1/IO80PDB5V0

GEC0/IO80NDB5V0

GEB1/IO79PDB5V0

GEB0/IO79NDB5V0

GEA1/IO78PDB5V0

GEA0/IO78NDB5V0

VCC

GND

VCCFPGAIOB5

GEC2/IO77PDB5V0

IO77NDB5V0

GEB2/IO76PDB5V0

GEA2/IO76NDB5V0

VCC

EMC_DB[3]/GEC2/IO60PDB5V0

EMC_DB[2]/IO60NDB5V0

EMC_DB[1]/GEB2/IO59PDB5V0

EMC_DB[0]/GEA2/IO59NDB5V0

VCC

GND

GNDRCOSC

VCCRCOSC

MSS_RESET_N

VCCESRAM

MAC_MDC/IO48RSB4V0

MAC_MDIO/IO49RSB4V0

MAC_MDC/IO57RSB4V0

MAC_MDIO/IO58RSB4V0

Revision 10

5-33

Pin Descriptions

PQ208

Pin Number

A2F200

A2F500

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

MAC_TXEN/IO52RSB4V0

MAC_TXEN/IO61RSB4V0

MAC_CRSDV/IO51RSB4V0

MAC_CRSDV/IO60RSB4V0

MAC_RXER/IO50RSB4V0

MAC_RXER/IO59RSB4V0

GND

VCCMSSIOB4

VCC

MAC_TXD[0]/IO56RSB4V0

MAC_TXD[0]/IO65RSB4V0

MAC_TXD[1]/IO55RSB4V0

MAC_TXD[1]/IO64RSB4V0

MAC_RXD[0]/IO54RSB4V0

MAC_RXD[1]/IO53RSB4V0

MAC_CLK

GNDSDD0

VCC33SDD0

VCC15A

PCAP

MAC_RXD[0]/IO63RSB4V0

MAC_RXD[1]/IO62RSB4V0

MAC_CLK

GNDSDD0

VCC33SDD0

VCC15A

PCAP

NCAP

VCC33AP

VCC33N

SDD0

VCC33AP

VCC33N

SDD0

GNDA

GNDAQ

ABPS0

ABPS1

CM0

TM0

GNDTM0

TM1

GNDTM0

TM1

CM1

ABPS3

ABPS2

ADC0

ADC1

ADC2

ADC3

VAREF0

GND33ADC0

VAREF0

GND33ADC0

5-34

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

PQ208

Pin Number

73

A2F200

VCC33ADC0

GND33ADC0

VCC15ADC0

GND15ADC0

GND15ADC1

VCC15ADC1

GND33ADC1

VCC33ADC1

GND33ADC1

VAREF1

A2F500

VCC33ADC0

GND33ADC0

VCC15ADC0

GND15ADC0

GND15ADC1

VCC15ADC1

GND33ADC1

VCC33ADC1

GND33ADC1

VAREF1

74

75

76

77

78

79

80

81

82

83

ADC7

84

ADC6

85

ADC5

86

ADC4

87

ABPS6

88

ABPS7

89

CM3

90

TM3

91

GNDTM1

TM2

GNDTM1

TM2

92

93

CM2

94

ABPS5

95

ABPS4

96

GNDAQ

97

GNDA

98

NC

99

GNDVAREF

VAREFOUT

PU_N

GNDVAREF

VAREFOUT

PU_N

100

101

102

103

104

105

106

107

108

VCC33A

PTEM

PTBASE

SPI_0_DO/GPIO_16

SPI_0_DI/GPIO_17

SPI_0_CLK/GPIO_18

SPI_0_SS/GPIO_19

SPI_0_DO/GPIO_16

SPI_0_DI/GPIO_17

SPI_0_CLK/GPIO_18

SPI_0_SS/GPIO_19

Revision 10

5-35

Pin Descriptions

PQ208

Pin Number

A2F200

UART_0_RXD/GPIO_21

UART_0_TXD/GPIO_20

UART_1_RXD/GPIO_29

UART_1_TXD/GPIO_28

VCC

A2F500

UART_0_RXD/GPIO_21

UART_0_TXD/GPIO_20

UART_1_RXD/GPIO_29

UART_1_TXD/GPIO_28

VCC

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

VCCMSSIOB2

GND

VCCMSSIOB2

GND

I2C_1_SDA/GPIO_30

I2C_1_SCL/GPIO_31

I2C_0_SDA/GPIO_22

I2C_0_SCL/GPIO_23

GNDENVM

I2C_1_SDA/GPIO_30

I2C_1_SCL/GPIO_31

I2C_0_SDA/GPIO_22

I2C_0_SCL/GPIO_23

GNDENVM

VCCENVM

JTAGSEL

TCK

TDI

TMS

TDO

TRSTB

VJTAG

VDDBAT

VCCLPXTAL

LPXOUT

VCCLPXTAL

LPXOUT

LPXIN

GNDLPXTAL

GNDMAINXTAL

MAINXOUT

GNDLPXTAL

GNDMAINXTAL

MAINXOUT

MAINXIN

VCCMAINXTAL

GND

VCCMAINXTAL

GND

VCC

VPP

VCCFPGAIOB1

GDA0/IO31NDB1V0

GDA1/IO31PDB1V0

GDC0/IO29NSB1V0

VCCFPGAIOB1

GDA0/IO40NDB1V0

GDA1/IO40PDB1V0

GDC0/IO38NSB1V0

5-36

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

PQ208

Pin Number

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

A2F200

GCA0/IO28NDB1V0

GCA1/IO28PDB1V0

VCCFPGAIOB1

A2F500

GCA0/IO36NDB1V0

GCA1/IO36PDB1V0

VCCFPGAIOB1

GND

VCC

IO25NDB1V0

IO30NDB1V0

GBC2/IO30PDB1V0

IO28NDB1V0

GCA2/IO28PDB1V0

GBB2/IO27NDB1V0

GBA2/IO27PDB1V0

GNDQ

GCC2/IO25PDB1V0

IO23NDB1V0

GCA2/IO23PDB1V0

GBC2/IO21PSB1V0

GBA2/IO20PSB1V0

GNDQ

VCCFPGAIOB0

GBA1/IO23PDB0V0

GBA0/IO23NDB0V0

VCCFPGAIOB0

GND

GBA1/IO19PDB0V0

GBA0/IO19NDB0V0

VCCFPGAIOB0

GND

VCC

EMC_AB[25]/IO16PDB0V0

EMC_AB[24]/IO16NDB0V0

EMC_AB[23]/IO15PDB0V0

EMC_AB[22]/IO15NDB0V0

EMC_AB[21]/IO14PDB0V0

EMC_AB[20]/IO14NDB0V0

EMC_AB[19]/IO13PDB0V0

EMC_AB[18]/IO13NDB0V0

EMC_AB[17]/IO12PDB0V0

EMC_AB[16]/IO12NDB0V0

VCCFPGAIOB0

IO21PDB0V0

IO21NDB0V0

IO20PDB0V0

IO20NDB0V0

IO19PDB0V0

IO19NDB0V0

IO18PDB0V0

IO18NDB0V0

IO17PDB0V0

IO17NDB0V0

VCCFPGAIOB0

GND

VCC

EMC_AB[15]/IO11PDB0V0

EMC_AB[14]/IO11NDB0V0

EMC_AB[13]/IO10PDB0V0

EMC_AB[12]/IO10NDB0V0

IO14PDB0V0

IO14NDB0V0

IO13PDB0V0

IO13NDB0V0

Revision 10

5-37

Pin Descriptions

PQ208

Pin Number

A2F200

EMC_AB[11]/IO09PDB0V0

EMC_AB[10]/IO09NDB0V0

EMC_AB[9]/IO08PDB0V0

EMC_AB[8]/IO08NDB0V0

EMC_AB[7]/IO07PDB0V0

EMC_AB[6]/IO07NDB0V0

VCCFPGAIOB0

A2F500

IO12PDB0V0

IO12NDB0V0

IO11PDB0V0

IO11NDB0V0

IO10PDB0V0

IO10NDB0V0

VCCFPGAIOB0

GND

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

GND

VCC

EMC_AB[5]/IO06PDB0V0

EMC_AB[4]/IO06NDB0V0

EMC_AB[3]/IO05PDB0V0

EMC_AB[2]/IO05NDB0V0

EMC_AB[1]/IO04PDB0V0

EMC_AB[0]/IO04NDB0V0

EMC_OEN1_N/IO03PDB0V0

EMC_OEN0_N/IO03NDB0V0

EMC_BYTEN[1]/GAC1/IO02PDB0V0

EMC_BYTEN[0]/GAC0/IO02NDB0V0

VCCFPGAIOB0

IO08PDB0V0

IO08NDB0V0

GAC1/IO07PDB0V0

GAC0/IO07NDB0V0

IO04PDB0V0

IO04NDB0V0

IO03PDB0V0

IO03NDB0V0

GAA1/IO02PDB0V0

GAA0/IO02NDB0V0

VCCFPGAIOB0

GND

VCC

EMC_CS1_N/GAB1/IO01PDB0V0

EMC_CS0_N/GAB0/IO01NDB0V0

EMC_RW_N/GAA1/IO00PDB0V0

EMC_CLK/GAA0/IO00NDB0V0

VCCFPGAIOB0

IO01PDB0V0

IO01NDB0V0

IO00PDB0V0

IO00NDB0V0

VCCFPGAIOB0

GNDQ

5-38

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

FG256

A1 Ball Pad Corner

1

7

6

4

5

3

2

16 15 14 13 12 11 10 9

8

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.microsemi.com/soc/products/solutions/package/docs.aspx.

Revision 10

5-39

Pin Descriptions

FG256

A2F200 Function

GND

No.

A2F060 Function

A2F500 Function

GND

A1

GND

A2

VCCFPGAIOB0

A3

EMC_AB[0]/IO04NDB0V0

EMC_AB[1]/IO04PDB0V0

GND

EMC_AB[0]/IO04NDB0V0

EMC_AB[1]/IO04PDB0V0

GND

EMC_AB[0]/IO06NDB0V0

EMC_AB[1]/IO06PDB0V0

GND

A4

A5

A6

EMC_AB[3]/IO05PDB0V0

EMC_AB[5]/IO06PDB0V0

VCCFPGAIOB0

EMC_AB[3]/IO05PDB0V0

EMC_AB[5]/IO06PDB0V0

VCCFPGAIOB0

EMC_AB[3]/IO09PDB0V0

EMC_AB[5]/IO10PDB0V0

VCCFPGAIOB0

A7

A8

A9

GND

A10

A11

A12

A13

A14

A15

A16

B1

EMC_AB[14]/IO11NDB0V0

EMC_AB[15]/IO11PDB0V0

GND

EMC_AB[14]/IO11NDB0V0

EMC_AB[15]/IO11PDB0V0

GND

EMC_AB[14]/IO15NDB0V0

EMC_AB[15]/IO15PDB0V0

GND

EMC_AB[20]/IO14NDB0V0

EMC_AB[24]/IO16NDB0V0

VCCFPGAIOB0

EMC_AB[20]/IO14NDB0V0

EMC_AB[24]/IO16NDB0V0

VCCFPGAIOB0

EMC_AB[20]/IO21NDB0V0

EMC_AB[24]/IO20NDB0V0

VCCFPGAIOB0

GND

EMC_DB[15]/IO45PDB5V0

GND

EMC_DB[15]/GAA2/IO71PDB5V0

GND

EMC_DB[15]/GAA2/IO88PDB5V0

GND

B2

B3

EMC_BYTEN[1]/IO02PDB0V0 EMC_BYTEN[1]/GAC1/IO02PDB0V0 EMC_BYTEN[1]/GAC1/IO07PDB0V0

B4

EMC_OEN0_N/IO03NDB0V0

EMC_OEN1_N/IO03PDB0V0

EMC_AB[2]/IO05NDB0V0

EMC_AB[4]/IO06NDB0V0

EMC_AB[9]/IO08PDB0V0

EMC_AB[12]/IO10NDB0V0

EMC_AB[13]/IO10PDB0V0

EMC_AB[16]/IO12NDB0V0

EMC_AB[18]/IO13NDB0V0

EMC_AB[21]/IO14PDB0V0

EMC_AB[25]/IO16PDB0V0

GND

EMC_OEN0_N/IO03NDB0V0

EMC_OEN1_N/IO03PDB0V0

EMC_AB[2]/IO05NDB0V0

EMC_AB[4]/IO06NDB0V0

EMC_AB[9]/IO08PDB0V0

EMC_AB[12]/IO10NDB0V0

EMC_AB[13]/IO10PDB0V0

EMC_AB[16]/IO12NDB0V0

EMC_AB[18]/IO13NDB0V0

EMC_AB[21]/IO14PDB0V0

EMC_AB[25]/IO16PDB0V0

GND

EMC_OEN0_N/IO08NDB0V0

EMC_OEN1_N/IO08PDB0V0

EMC_AB[2]/IO09NDB0V0

EMC_AB[4]/IO10NDB0V0

EMC_AB[9]/IO13PDB0V0

EMC_AB[12]/IO14NDB0V0

EMC_AB[13]/IO14PDB0V0

EMC_AB[16]/IO17NDB0V0

EMC_AB[18]/IO18NDB0V0

EMC_AB[21]/IO21PDB0V0

EMC_AB[25]/IO20PDB0V0

GND

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

C1

GNDQ

EMC_DB[14]/IO45NDB5V0

VCCPLL0

EMC_DB[14]/GAB2/IO71NDB5V0

VCCPLL

EMC_DB[14]/GAB2/IO88NDB5V0

VCCPLL0

C2

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

5-40

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

FG256

A2F200 Function

EMC_BYTEN[0]/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO02NDB0V0 EMC_BYTEN[0]/GAC0/IO07NDB0V0

No.

A2F060 Function

A2F500 Function

C3

C4

VCCFPGAIOB0

EMC_CS0_N/IO01NDB0V0

EMC_CS1_N/IO01PDB0V0

GND

VCCFPGAIOB0

EMC_CS0_N/GAB0/IO01NDB0V0

EMC_CS1_N/GAB1/IO01PDB0V0

GND

VCCFPGAIOB0

EMC_CS0_N/GAB0/IO05NDB0V0

EMC_CS1_N/GAB1/IO05PDB0V0

GND

C5

C6

C7

C8

EMC_AB[8]/IO08NDB0V0

EMC_AB[11]/IO09PDB0V0

VCCFPGAIOB0

EMC_AB[8]/IO08NDB0V0

EMC_AB[11]/IO09PDB0V0

VCCFPGAIOB0

EMC_AB[8]/IO13NDB0V0

EMC_AB[11]/IO11PDB0V0

VCCFPGAIOB0

C9

C10

C11

C12

C13

C14

C15

C16

D1

EMC_AB[17]/IO12PDB0V0

EMC_AB[19]/IO13PDB0V0

GND

EMC_AB[17]/IO12PDB0V0

EMC_AB[19]/IO13PDB0V0

GND

EMC_AB[17]/IO17PDB0V0

EMC_AB[19]/IO18PDB0V0

GND

GCC0/IO18NPB0V0

GCB0/IO19NDB0V0

GCB1/IO19PDB0V0

VCCFPGAIOB5

GBA2/IO20PPB1V0

GCA2/IO23PDB1V0

IO23NDB1V0

GBA2/IO27PPB1V0

GCA2/IO28PDB1V0

IO28NDB1V0

VCCFPGAIOB5

D2

VCOMPLA0

VCOMPLA

VCOMPLA0

D3

GND

D4

GNDQ

D5

EMC_CLK/IO00NDB0V0

EMC_RW_N/IO00PDB0V0

EMC_AB[6]/IO07NDB0V0

EMC_AB[7]/IO07PDB0V0

EMC_AB[10]/IO09NDB0V0

EMC_AB[22]/IO15NDB0V0

EMC_AB[23]/IO15PDB0V0

GNDQ

EMC_CLK/GAA0/IO00NDB0V0

EMC_RW_N/GAA1/IO00PDB0V0

EMC_AB[6]/IO07NDB0V0

EMC_AB[7]/IO07PDB0V0

EMC_AB[10]/IO09NDB0V0

EMC_AB[22]/IO15NDB0V0

EMC_AB[23]/IO15PDB0V0

GNDQ

EMC_CLK/GAA0/IO02NDB0V0

EMC_RW_N/GAA1/IO02PDB0V0

EMC_AB[6]/IO12NDB0V0

EMC_AB[7]/IO12PDB0V0

EMC_AB[10]/IO11NDB0V0

EMC_AB[22]/IO19NDB0V0

EMC_AB[23]/IO19PDB0V0

GNDQ

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

E1

GCC1/IO18PPB0V0

GCA0/IO20NDB0V0

GCA1/IO20PDB0V0

VCCFPGAIOB1

GBB2/IO20NPB1V0

GCB2/IO24PDB1V0

IO24NDB1V0

GBB2/IO27NPB1V0

GCB2/IO33PDB1V0

IO33NDB1V0

VCCFPGAIOB1

EMC_DB[13]/IO44PDB5V0

EMC_DB[12]/IO44NDB5V0

GFA2/IO42PDB5V0

EMC_DB[10]/IO43NPB5V0

EMC_DB[13]/GAC2/IO70PDB5V0

EMC_DB[12]/IO70NDB5V0

GFA2/IO68PDB5V0

EMC_DB[10]/IO69NPB5V0

EMC_DB[13]/GAC2/IO87PDB5V0

EMC_DB[12]/IO87NDB5V0

GFA2/IO85PDB5V0

EMC_DB[10]/IO86NPB5V0

E2

E3

E4

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

Revision 10

5-41

Pin Descriptions

FG256

A2F200 Function

GNDQ

No.

A2F060 Function

A2F500 Function

GNDQ

E5

GNDQ

GND

E6

GND

E7

VCCFPGAIOB0

GND

VCCFPGAIOB0

GND

VCCFPGAIOB0

GND

E8

E9

VCCFPGAIOB0

GND

VCCFPGAIOB0

GND

VCCFPGAIOB0

GND

E10

E11

E12

E13

E14

E15

E16

F1

VCCFPGAIOB0

GCB2/IO22PDB1V0

VCCFPGAIOB1

GCA2/IO21PDB1V0

GCC2/IO23PDB1V0

IO23NDB1V0

EMC_DB[9]/IO40PDB5V0

GND

VCCFPGAIOB0

GCA1/IO28PDB1V0

VCCFPGAIOB1

GCB1/IO27PDB1V0

GDC1/IO29PDB1V0

GDC0/IO29NDB1V0

EMC_DB[9]/GEC1/IO63PDB5V0

GND

VCCFPGAIOB0

GCA1/IO36PDB1V0

VCCFPGAIOB1

GCB1/IO34PDB1V0

GDC1/IO38PDB1V0

GDC0/IO38NDB1V0

EMC_DB[9]/GEC1/IO80PDB5V0

GND

F2

F3

GFB2/IO42NDB5V0

VCCFPGAIOB5

EMC_DB[11]/IO43PPB5V0

VCCFPGAIOB5

GND

GFB2/IO68NDB5V0

VCCFPGAIOB5

EMC_DB[11]/IO69PPB5V0

VCCFPGAIOB5

GND

GFB2/IO85NDB5V0

VCCFPGAIOB5

EMC_DB[11]/IO86PPB5V0

VCCFPGAIOB5

GND

F4

F5

F6

F7

F8

VCC

F9

GND

F10

F11

F12

F13

F14

F15

F16

G1

G2

G3

G4

G5

G6

VCC

GND

IO22NDB1V0

NC

GCA0/IO28NDB1V0

GNDQ

GCA0/IO36NDB1V0

GNDQ

IO21NDB1V0

GND

GCB0/IO27NDB1V0

GND

GCB0/IO34NDB1V0

GND

VCCENVM

EMC_DB[8]/IO40NDB5V0

EMC_DB[7]/IO39PDB5V0

EMC_DB[6]/IO39NDB5V0

GFC2/IO41PDB5V0

IO41NDB5V0

GND

EMC_DB[8]/GEC0/IO63NDB5V0

EMC_DB[7]/GEB1/IO62PDB5V0

EMC_DB[6]/GEB0/IO62NDB5V0

GFC2/IO67PDB5V0

IO67NDB5V0

EMC_DB[8]/GEC0/IO80NDB5V0

EMC_DB[7]/GEB1/IO79PDB5V0

EMC_DB[6]/GEB0/IO79NDB5V0

GFC2/IO84PDB5V0

IO84NDB5V0

GND

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

5-42

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

FG256

No.

A2F060 Function

A2F200 Function

A2F500 Function

G7

G8

VCC

GND

G9

VCC

G10

G11

G12

G13

G14

G15

G16

H1

GND

VCCFPGAIOB1

VPP

TRSTB

TMS

TCK

GNDENVM

GND

H2

EMC_DB[5]/IO38PPB5V0

EMC_DB[5]/GEA1/IO61PPB5V0

EMC_DB[5]/GEA1/IO78PPB5V0

H3

VCCFPGAIOB5

H4

EMC_DB[1]/IO36PDB5V0

EMC_DB[1]/GEB2/IO59PDB5V0

EMC_DB[1]/GEB2/IO76PDB5V0

H5

EMC_DB[0]/IO36NDB5V0

EMC_DB[0]/GEA2/IO59NDB5V0

EMC_DB[0]/GEA2/IO76NDB5V0

H6

VCCFPGAIOB5

H7

GND

H8

VCC

H9

GND

H10

H11

H12

H13

H14

H15

H16

J1

VCC

GND

VJTAG

TDO

TDI

JTAGSEL

GND

EMC_DB[4]/IO38NPB5V0

EMC_DB[4]/GEA0/IO61NPB5V0

EMC_DB[4]/GEA0/IO78NPB5V0

J2

EMC_DB[3]/IO37PDB5V0

EMC_DB[3]/GEC2/IO60PDB5V0

EMC_DB[3]/GEC2/IO77PDB5V0

J3

EMC_DB[2]/IO37NDB5V0

EMC_DB[2]/IO60NDB5V0

EMC_DB[2]/IO77NDB5V0

J4

GNDRCOSC

NC

GNDRCOSC

GNDQ

GND

GNDRCOSC

GNDQ

GND

J5

J6

GND

J7

VCC

J8

GND

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

Revision 10

5-43

Pin Descriptions

FG256

A2F200 Function

VCC

No.

A2F060 Function

A2F500 Function

VCC

J9

VCC

GND

J10

J11

J12

J13

J14

J15

J16

K1

GND

VCCMSSIOB2

I2C_0_SCL/GPIO_23

I2C_0_SDA/GPIO_22

I2C_1_SCL/GPIO_31

VCCMSSIOB2

I2C_1_SDA/GPIO_30

GPIO_1/IO32RSB4V0

GPIO_0/IO33RSB4V0

VCCMSSIOB4

MSS_RESET_N

VCCRCOSC

VCCMSSIOB2

I2C_0_SCL/GPIO_23

I2C_0_SDA/GPIO_22

I2C_1_SCL/GPIO_31

VCCMSSIOB2

I2C_1_SDA/GPIO_30

MAC_MDIO/IO49RSB4V0

MAC_MDC/IO48RSB4V0

VCCMSSIOB4

MSS_RESET_N

VCCRCOSC

VCCMSSIOB2

I2C_0_SCL/GPIO_23

I2C_0_SDA/GPIO_22

I2C_1_SCL/GPIO_31

VCCMSSIOB2

I2C_1_SDA/GPIO_30

MAC_MDIO/IO58RSB4V0

MAC_MDC/IO57RSB4V0

VCCMSSIOB4

MSS_RESET_N

VCCRCOSC

K2

K3

K4

K5

K6

VCCMSSIOB4

GND

VCCMSSIOB4

GND

VCCMSSIOB4

GND

K7

K8

VCC

K9

GND

K10

K11

K12

K13

K14

K15

K16

L1

VCC

GND

UART_0_RXD/GPIO_21

GND

UART_0_RXD/GPIO_21

GND

UART_0_RXD/GPIO_21

GND

UART_1_TXD/GPIO_28

UART_1_RXD/GPIO_29

UART_0_TXD/GPIO_20

GND

UART_1_TXD/GPIO_28

UART_1_RXD/GPIO_29

UART_0_TXD/GPIO_20

GND

UART_1_TXD/GPIO_28

UART_1_RXD/GPIO_29

UART_0_TXD/GPIO_20

GND

L2

GPIO_2/IO31RSB4V0

GPIO_3/IO30RSB4V0

GPIO_4/IO29RSB4V0

GPIO_9/IO24RSB4V0

GND

MAC_TXEN/IO52RSB4V0

MAC_CRSDV/IO51RSB4V0

MAC_RXER/IO50RSB4V0

MAC_CLK

MAC_TXEN/IO61RSB4V0

MAC_CRSDV/IO60RSB4V0

MAC_RXER/IO59RSB4V0

MAC_CLK

L3

L4

L5

L6

GND

L7

VCC

L8

GND

L9

VCC

L10

GND

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

5-44

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

FG256

No.

A2F060 Function

VCCMSSIOB2

SPI_1_DO/GPIO_24

SPI_1_SS/GPIO_27

SPI_1_CLK/GPIO_26

SPI_1_DI/GPIO_25

GND

A2F200 Function

VCCMSSIOB2

SPI_1_DO/GPIO_24

SPI_1_SS/GPIO_27

SPI_1_CLK/GPIO_26

SPI_1_DI/GPIO_25

GND

A2F500 Function

VCCMSSIOB2

SPI_1_DO/GPIO_24

SPI_1_SS/GPIO_27

SPI_1_CLK/GPIO_26

SPI_1_DI/GPIO_25

GND

L11

L12

L13

L14

L15

L16

M1

GPIO_5/IO28RSB4V0

GPIO_6/IO27RSB4V0

GPIO_7/IO26RSB4V0

GND

MAC_TXD[0]/IO56RSB4V0

MAC_TXD[1]/IO55RSB4V0

MAC_RXD[0]/IO54RSB4V0

GND

MAC_TXD[0]/IO65RSB4V0

MAC_TXD[1]/IO64RSB4V0

MAC_RXD[0]/IO63RSB4V0

GND

M2

M3

M4

M5

NC

ADC3

M6

NC

GND15ADC0

GND33ADC1

ADC4

GND15ADC0

GND33ADC1

ADC4

M7

GND33ADC0

ADC7

M8

M9

M10

M11

M12

M13

M14

M15

M16

N1

GNDTM0

GNDTM1

ADC6

TM2

ADC5

CM2

SPI_0_SS/GPIO_19

VCCMSSIOB2

SPI_0_CLK/GPIO_18

SPI_0_DI/GPIO_17

GPIO_8/IO25RSB4V0

VCCMSSIOB4

VCC15A

SPI_0_SS/GPIO_19

VCCMSSIOB2

SPI_0_CLK/GPIO_18

SPI_0_DI/GPIO_17

MAC_RXD[1]/IO53RSB4V0

VCCMSSIOB4

VCC15A

SPI_0_SS/GPIO_19

VCCMSSIOB2

SPI_0_CLK/GPIO_18

SPI_0_DI/GPIO_17

MAC_RXD[1]/IO62RSB4V0

VCCMSSIOB4

VCC15A

N2

N3

N4

VCC33AP

N5

NC

ABPS3

N6

ADC4

TM1

N7

NC

GND33ADC0

VCC33ADC1

ADC5

GND33ADC0

VCC33ADC1

ADC5

N8

VCC33ADC0

ADC8

N9

N10

N11

N12

CM0

CM3

GNDAQ

VAREFOUT

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

Revision 10

5-45

Pin Descriptions

FG256

A2F200 Function

GNDSDD1

VCC33SDD1

GND

No.

N13

N14

N15

N16

P1

A2F060 Function

A2F500 Function

GNDSDD1

VCC33SDD1

GND

NC

GND

SPI_0_DO/GPIO_16

GNDSDD0

VCC33SDD0

VCC33N

GNDA

SPI_0_DO/GPIO_16

GNDSDD0

VCC33SDD0

VCC33N

GNDA

SPI_0_DO/GPIO_16

GNDSDD0

VCC33SDD0

VCC33N

GNDA

P2

P3

P4

P5

GNDAQ

NC

GNDAQ

P6

CM1

P7

NC

ADC2

P8

NC

VCC15ADC0

ADC6

VCC15ADC0

ADC6

P9

ADC9

P10

P11

P12

P13

P14

P15

P16

R1

TM0

TM3

GNDA

VCCMAINXTAL

GNDLPXTAL

VDDBAT

PTEM

VCCMAINXTAL

GNDLPXTAL

VDDBAT

PTEM

VCCMAINXTAL

GNDLPXTAL

VDDBAT

PTEM

PTBASE

PCAP

PTBASE

PCAP

PTBASE

PCAP

R2

SDD0

R3

ADC0

ABPS0

R4

ADC3

TM0

R5

NC

ABPS2

R6

NC

ADC1

R7

NC

VCC33ADC0

VCC15ADC1

ADC7

VCC33ADC0

VCC15ADC1

ADC7

R8

VCC15ADC0

ADC10

ABPS1

NC

R9

R10

R11

R12

R13

R14

ABPS7

ABPS4

MAINXIN

MAINXOUT

LPXIN

MAINXIN

MAINXOUT

LPXIN

MAINXIN

MAINXOUT

LPXIN

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

5-46

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

FG256

No.

A2F060 Function

LPXOUT

VCC33A

NCAP

A2F200 Function

LPXOUT

VCC33A

NCAP

A2F500 Function

LPXOUT

VCC33A

NCAP

R15

R16

T1

T2

ADC1

ABPS1

T3

ADC2

CM0

T4

NC

GNDTM0

ADC0

GNDTM0

ADC0

T5

NC

T6

NC

VAREF0

T7

NC

GND33ADC0

GND15ADC1

VAREF1

GND33ADC0

GND15ADC1

VAREF1

T8

GND15ADC0

VAREF0

ABPS0

NC

T9

T10

T11

T12

T13

T14

T15

T16

ABPS6

ABPS5

NC

SDD1

GNDVAREF

GNDMAINXTAL

VCCLPXTAL

PU_N

GNDVAREF

GNDMAINXTAL

VCCLPXTAL

PU_N

GNDVAREF

GNDMAINXTAL

VCCLPXTAL

PU_N

Note: Shading denotes pins that do not have completely identical functions from density to density. For example, the

bank assignment can be different for an I/O, or the function might be available only on a larger density device.

Revision 10

5-47

Pin Descriptions

FG484

A1 Ball Pad Corner

22 21 20 19 18 17 16 15 14 13 12 11 10 9

8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

Note

For Package Manufacturing and Environmental information, visit the Resource Center at

http://www.microsemi.com/soc/products/solutions/package/docs.aspx.

5-48

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

FG484

Pin Number

A1

A2F200 Function

A2F500 Function

GND

NC

GND

NC

A2

A3

NC

A4

GND

A5

EMC_CS0_N/GAB0/IO01NDB0V0

EMC_CS0_N/GAB0/IO05NDB0V0

A6

EMC_CS1_N/GAB1/IO01PDB0V0

EMC_CS1_N/GAB1/IO05PDB0V0

A7

GND

A8

EMC_AB[0]/IO04NDB0V0

EMC_AB[0]/IO06NDB0V0

A9

EMC_AB[1]/IO04PDB0V0

EMC_AB[1]/IO06PDB0V0

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

AA1

AA2

AA3

AA4

AA5

AA6

AA7

AA8

AA9

AA10

AA11

AA12

AA13

AA14

GND

NC

EMC_AB[7]/IO07PDB0V0

EMC_AB[7]/IO12PDB0V0

GND

EMC_AB[12]/IO10NDB0V0

EMC_AB[12]/IO14NDB0V0

EMC_AB[13]/IO10PDB0V0

EMC_AB[13]/IO14PDB0V0

GND

NC

IO16NDB0V0

NC

IO16PDB0V0

GND

NC

GND

GPIO_4/IO43RSB4V0

GPIO_12/IO37RSB4V0

MAC_MDC/IO48RSB4V0

MAC_RXER/IO50RSB4V0

MAC_TXD[0]/IO56RSB4V0

ABPS0

GPIO_4/IO52RSB4V0

GPIO_12/IO46RSB4V0

MAC_MDC/IO57RSB4V0

MAC_RXER/IO59RSB4V0

MAC_TXD[0]/IO65RSB4V0

ABPS0

TM1

ADC1

GND15ADC1

GND33ADC1

CM3

GND15ADC1

GND33ADC1

CM3

GNDTM1

NC

ADC10

NC

ADC9

Note: Shading denotes pins that do not have completely identical functions from density to density. For

example, the bank assignment can be different for an I/O, or the function might be available only

on a larger density device.

Revision 10

5-49

Pin Descriptions

FG484

Pin Number

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AB1

A2F200 Function

A2F500 Function

NC

GND15ADC2

MAINXIN

MAINXOUT

LPXIN

LPXOUT

NC

SPI_1_CLK/GPIO_26

GND

AB2

GPIO_13/IO36RSB4V0

GPIO_13/IO45RSB4V0

AB3

GPIO_14/IO35RSB4V0

GPIO_14/IO44RSB4V0

AB4

GND

AB5

PCAP

AB6

NCAP

AB7

ABPS3

AB8

ADC3

AB9

GND15ADC0

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AB22

B1

VCC33ADC1

VAREF1

TM2

CM2

ABPS4

GNDAQ

GNDMAINXTAL

GNDLPXTAL

VCCLPXTAL

VDDBAT

PTBASE

NC

GND

EMC_DB[15]/GAA2/IO71PDB5V0

EMC_DB[15]/GAA2/IO88PDB5V0

B2

GND

B3

NC

B4

B5

VCCFPGAIOB0

B6

EMC_RW_N/GAA1/IO00PDB0V0

EMC_RW_N/GAA1/IO02PDB0V0

Note: Shading denotes pins that do not have completely identical functions from density to density. For

example, the bank assignment can be different for an I/O, or the function might be available only

on a larger density device.

5-50

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

FG484

Pin Number

B7

A2F200 Function

NC

A2F500 Function

IO04PPB0V0

VCCFPGAIOB0

B8

VCCFPGAIOB0

B9

EMC_BYTEN[0]/GAC0/IO02NDB0V0

EMC_AB[2]/IO05NDB0V0

EMC_AB[3]/IO05PDB0V0

EMC_AB[6]/IO07NDB0V0

EMC_AB[14]/IO11NDB0V0

EMC_AB[15]/IO11PDB0V0

VCCFPGAIOB0

EMC_BYTEN[0]/GAC0/IO07NDB0V0

EMC_AB[2]/IO09NDB0V0

EMC_AB[3]/IO09PDB0V0

EMC_AB[6]/IO12NDB0V0

EMC_AB[14]/IO15NDB0V0

EMC_AB[15]/IO15PDB0V0

VCCFPGAIOB0

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

C1

EMC_AB[18]/IO13NDB0V0

EMC_AB[19]/IO13PDB0V0

VCCFPGAIOB0

EMC_AB[18]/IO18NDB0V0

EMC_AB[19]/IO18PDB0V0

VCCFPGAIOB0

GBB0/IO18NDB0V0

GBB1/IO18PDB0V0

GND

GBB0/IO24NDB0V0

GBB1/IO24PDB0V0

GND

GBA2/IO20PDB1V0

EMC_DB[14]/GAB2/IO71NDB5V0

NC

GBA2/IO27PDB1V0

EMC_DB[14]/GAB2/IO88NDB5V0

NC

C2

C3

NC

C4

NC

IO01NDB0V0

C5

NC

IO01PDB0V0

C6

EMC_CLK/GAA0/IO00NDB0V0

NC

EMC_CLK/GAA0/IO02NDB0V0

IO03PPB0V0

C7

C8

NC

IO04NPB0V0

C9

EMC_BYTEN[1]/GAC1/IO02PDB0V0

EMC_OEN1_N/IO03PDB0V0

GND

EMC_BYTEN[1]/GAC1/IO07PDB0V0

EMC_OEN1_N/IO08PDB0V0

GND

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

VCCFPGAIOB0

EMC_AB[8]/IO08NDB0V0

EMC_AB[16]/IO12NDB0V0

EMC_AB[17]/IO12PDB0V0

EMC_AB[24]/IO16NDB0V0

EMC_AB[22]/IO15NDB0V0

EMC_AB[23]/IO15PDB0V0

GBA0/IO19NPB0V0

NC

EMC_AB[8]/IO13NDB0V0

EMC_AB[16]/IO17NDB0V0

EMC_AB[17]/IO17PDB0V0

EMC_AB[24]/IO20NDB0V0

EMC_AB[22]/IO19NDB0V0

EMC_AB[23]/IO19PDB0V0

GBA0/IO23NPB0V0

NC

Note: Shading denotes pins that do not have completely identical functions from density to density. For

example, the bank assignment can be different for an I/O, or the function might be available only

on a larger density device.

Revision 10

5-51

Pin Descriptions

FG484

Pin Number

C21

C22

D1

A2F200 Function

A2F500 Function

GBC2/IO30PDB1V0

GBB2/IO27NDB1V0

GND

GBC2/IO21PDB1V0

GBB2/IO20NDB1V0

GND

D2

EMC_DB[12]/IO70NDB5V0

EMC_DB[12]/IO87NDB5V0

EMC_DB[13]/GAC2/IO87PDB5V0

NC

D3

EMC_DB[13]/GAC2/IO70PDB5V0

D4

NC

D5

NC

D6

GND

D7

NC

IO00NPB0V0

D8

NC

GND

IO03NPB0V0

D9

GND

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

E1

EMC_OEN0_N/IO03NDB0V0

EMC_AB[10]/IO09NDB0V0

EMC_AB[11]/IO09PDB0V0

EMC_AB[9]/IO08PDB0V0

GND

EMC_OEN0_N/IO08NDB0V0

EMC_AB[10]/IO11NDB0V0

EMC_AB[11]/IO11PDB0V0

EMC_AB[9]/IO13PDB0V0

GND

GBC1/IO17PPB0V0

EMC_AB[25]/IO16PDB0V0

GND

GBC1/IO22PPB0V0

EMC_AB[25]/IO20PDB0V0

GND

GBA1/IO19PPB0V0

NC

GBA1/IO23PPB0V0

NC

IO21NDB1V0

GND

IO30NDB1V0

GND

GFC2/IO67PPB5V0

VCCFPGAIOB5

GFA2/IO68PDB5V0

GND

GFC2/IO84PPB5V0

VCCFPGAIOB5

GFA2/IO85PDB5V0

GND

E2

E3

E4

E5

NC

E6

GNDQ

E7

VCCFPGAIOB0

NC

VCCFPGAIOB0

IO00PPB0V0

E8

E9

NC

E10

E11

E12

VCCFPGAIOB0

EMC_AB[4]/IO06NDB0V0

EMC_AB[5]/IO06PDB0V0

VCCFPGAIOB0

EMC_AB[4]/IO10NDB0V0

EMC_AB[5]/IO10PDB0V0

Note: Shading denotes pins that do not have completely identical functions from density to density. For

example, the bank assignment can be different for an I/O, or the function might be available only

on a larger density device.

5-52

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

FG484

Pin Number

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

F1

A2F200 Function

VCCFPGAIOB0

GBC0/IO17NPB0V0

NC

A2F500 Function

VCCFPGAIOB0

GBC0/IO22NPB0V0

NC

VCCFPGAIOB0

NC

VCCFPGAIOB0

VCOMPLA1

IO25NPB1V0

GND

NC

GND

NC

VCCFPGAIOB1

IO22NDB1V0

GFB1/IO65PPB5V0

IO67NPB5V0

GFB2/IO68NDB5V0

VCCFPGAIOB1

IO32NDB1V0

GFB1/IO82PPB5V0

IO84NPB5V0

GFB2/IO85NDB5V0

F2

F3

F4

EMC_DB[10]/IO69NPB5V0

EMC_DB[10]/IO86NPB5V0

VCCFPGAIOB5

VCCPLL0

F5

VCCFPGAIOB5

F6

VCCPLL

F7

VCOMPLA

VCOMPLA0

F8

NC

F9

NC

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

G1

NC

EMC_AB[20]/IO14NDB0V0

EMC_AB[20]/IO21NDB0V0

EMC_AB[21]/IO21PDB0V0

GNDQ

EMC_AB[21]/IO14PDB0V0

GNDQ

NC

VCCPLL1

NC

VCCFPGAIOB1

IO23NDB1V0

NC

IO25PPB1V0

VCCFPGAIOB1

IO28NDB1V0

IO31PDB1V0

IO31NDB1V0

IO32PDB1V0

GND

NC

IO22PDB1V0

GND

G2

GFB0/IO65NPB5V0

EMC_DB[9]/GEC1/IO63PDB5V0

GFC1/IO66PPB5V0

GFB0/IO82NPB5V0

EMC_DB[9]/GEC1/IO80PDB5V0

GFC1/IO83PPB5V0

G3

G4

Note: Shading denotes pins that do not have completely identical functions from density to density. For

example, the bank assignment can be different for an I/O, or the function might be available only

on a larger density device.

Revision 10

5-53

Pin Descriptions

FG484

Pin Number

G5

A2F200 Function

A2F500 Function

EMC_DB[11]/IO69PPB5V0

EMC_DB[11]/IO86PPB5V0

G6

GNDQ

G7

NC

GND

G8

GND

G9

VCCFPGAIOB0

GND

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

G22

H1

GND

VCCFPGAIOB0

GND

VCCFPGAIOB0

GND

VCCFPGAIOB0

GNDQ

NC

IO26PDB1V0

IO26NDB1V0

GCA2/IO28PDB1V0

IO33NDB1V0

GCB2/IO33PDB1V0

GND

NC

GCA2/IO23PDB1V0

IO24NDB1V0

GCB2/IO24PDB1V0

GND

EMC_DB[7]/GEB1/IO62PDB5V0

EMC_DB[7]/GEB1/IO79PDB5V0

VCCFPGAIOB5

EMC_DB[8]/GEC0/IO80NDB5V0

GND

H2

VCCFPGAIOB5

H3

EMC_DB[8]/GEC0/IO63NDB5V0

H4

GND

GFC0/IO66NPB5V0

GFA1/IO64PDB5V0

GND

H5

GFC0/IO83NPB5V0

GFA1/IO81PDB5V0

GND

H6

H7

H8

VCC

H9

GND

H10

H11

H12

H13

H14

H15

H16

H17

H18

VCC

GND

VCC

GND

VCC

GND

VCCFPGAIOB1

IO25NDB1V0

GCC2/IO25PDB1V0

VCCFPGAIOB1

IO29NDB1V0

GCC2/IO29PDB1V0

Note: Shading denotes pins that do not have completely identical functions from density to density. For

example, the bank assignment can be different for an I/O, or the function might be available only

on a larger density device.

5-54

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

FG484

Pin Number

H19

H20

H21

H22

J1

A2F200 Function

GND

A2F500 Function

GND

GCC0/IO26NPB1V0

VCCFPGAIOB1

GCB0/IO27NDB1V0

GCC0/IO35NPB1V0

VCCFPGAIOB1

GCB0/IO34NDB1V0

EMC_DB[6]/GEB0/IO62NDB5V0

EMC_DB[6]/GEB0/IO79NDB5V0

J2

EMC_DB[5]/GEA1/IO61PDB5V0

EMC_DB[5]/GEA1/IO78PDB5V0

J3

EMC_DB[4]/GEA0/IO61NDB5V0

EMC_DB[4]/GEA0/IO78NDB5V0

J4

EMC_DB[3]/GEC2/IO60PPB5V0

EMC_DB[3]/GEC2/IO77PPB5V0

J5

VCCFPGAIOB5

J6

GFA0/IO64NDB5V0

GFA0/IO81NDB5V0

J7

VCCFPGAIOB5

J8

GND

J9

VCC

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J21

J22

K1

GND

VCC

GND

VCC

GND

VCC

GND

NC

IO37PDB1V0

VCCFPGAIOB1

GCA0/IO36NDB1V0

GCA1/IO36PDB1V0

GCC1/IO35PPB1V0

GCB1/IO34PDB1V0

GND

VCCFPGAIOB1

GCA0/IO28NDB1V0

GCA1/IO28PDB1V0

GCC1/IO26PPB1V0

GCB1/IO27PDB1V0

GND

K2

EMC_DB[0]/GEA2/IO59NDB5V0

EMC_DB[0]/GEA2/IO76NDB5V0

EMC_DB[1]/GEB2/IO76PDB5V0

IO74PPB5V0

EMC_DB[2]/IO77NPB5V0

IO75PDB5V0

GND

K3

EMC_DB[1]/GEB2/IO59PDB5V0

K4

NC

K5

EMC_DB[2]/IO60NPB5V0

K6

NC

K7

GND

VCC

GND

VCC

K8

VCC

K9

GND

K10

VCC

Note: Shading denotes pins that do not have completely identical functions from density to density. For

example, the bank assignment can be different for an I/O, or the function might be available only

on a larger density device.

Revision 10

5-55

Pin Descriptions

FG484

Pin Number

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

L1

A2F200 Function

A2F500 Function

GND

VCC

GND

VCC

GND

VCCFPGAIOB1

IO37NDB1V0

GDA1/IO40PDB1V0

GDA0/IO40NDB1V0

GDC1/IO38PDB1V0

GDC0/IO38NDB1V0

GND

NC

GDA1/IO31PDB1V0

GDA0/IO31NDB1V0

GDC1/IO29PDB1V0

GDC0/IO29NDB1V0

GND

NC

IO73PDB5V0

IO73NDB5V0

IO72PPB5V0

GND

L2

NC

L3

NC

L4

GND

L5

NC

IO74NPB5V0

IO75NDB5V0

VCCFPGAIOB5

GND

L6

NC

L7

VCCFPGAIOB5

L8

GND

L9

VCC

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

L21

L22

M1

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

GNDQ

GDA2/IO33NDB1V0

VCCFPGAIOB1

GDB1/IO30PDB1V0

GDB0/IO30NDB1V0

GDC2/IO32PDB1V0

NC

GDA2/IO42NDB1V0

VCCFPGAIOB1

GDB1/IO39PDB1V0

GDB0/IO39NDB1V0

GDC2/IO41PDB1V0

IO71PDB5V0

IO71NDB5V0

M2

NC

Note: Shading denotes pins that do not have completely identical functions from density to density. For

example, the bank assignment can be different for an I/O, or the function might be available only

on a larger density device.

5-56

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

FG484

Pin Number

M3

A2F200 Function

A2F500 Function

VCCFPGAIOB5

IO72NPB5V0

GNDQ

VCCFPGAIOB5

M4

NC

M5

GNDQ

M6

NC

IO68PDB5V0

GND

M7

GND

M8

VCC

M9

GND

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

M21

M22

N1

VCC

GND

VCC

GND

VCC

GND

VCCFPGAIOB1

NC

GDB2/IO33PDB1V0

GDB2/IO42PDB1V0

VJTAG

GND

VPP

IO32NDB1V0

GND

IO41NDB1V0

GND

N2

NC

IO70PDB5V0

IO70NDB5V0

VCCRCOSC

VCCFPGAIOB5

IO68NDB5V0

VCCFPGAIOB5

GND

N3

NC

N4

VCCRCOSC

VCCFPGAIOB5

NC

N5

N6

N7

VCCFPGAIOB5

GND

N8

N9

VCC

N10

N11

N12

N13

N14

N15

N16

GND

VCC

GND

VCC

GND

VCC

NC

GND

Note: Shading denotes pins that do not have completely identical functions from density to density. For

example, the bank assignment can be different for an I/O, or the function might be available only

on a larger density device.

Revision 10

5-57

Pin Descriptions

FG484

Pin Number

N17

N18

N19

N20

N21

N22

P1

A2F200 Function

A2F500 Function

NC

VCCFPGAIOB1

VCCENVM

GNDENVM

NC

GND

NC

IO69NDB5V0

P2

NC

IO69PDB5V0

P3

GNDRCOSC

P4

GND

P5

NC

P6

NC

P7

GND

P8

VCC

P9

GND

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

R1

VCC

GND

VCC

GND

VCC

GND

VCCFPGAIOB1

TDI

TCK

GND

TMS

TDO

TRSTB

MSS_RESET_N

R2

VCCFPGAIOB5

R3

GPIO_1/IO46RSB4V0

GPIO_1/IO55RSB4V0

R4

NC

R5

R6

NC

R7

NC

R8

GND

Note: Shading denotes pins that do not have completely identical functions from density to density. For

example, the bank assignment can be different for an I/O, or the function might be available only

on a larger density device.

5-58

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

FG484

Pin Number

R9

A2F200 Function

A2F500 Function

VCC

GND

VCC

GND

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

T1

VCC

GND

VCC

GND

VCC

JTAGSEL

NC

JTAGSEL

NC

VCCFPGAIOB1

NC

VCCFPGAIOB1

NC

GND

T2

VCCMSSIOB4

T3

GPIO_8/IO39RSB4V0

GPIO_11/IO57RSB4V0

GND

GPIO_8/IO48RSB4V0

GPIO_11/IO66RSB4V0

GND

T4

T5

T6

MAC_CLK

VCCMSSIOB4

VCC33SDD0

VCC15A

MAC_CLK

VCCMSSIOB4

VCC33SDD0

VCC15A

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

GNDAQ

GND33ADC0

ADC7

GND33ADC0

ADC7

NC

TM4

NC

VAREF2

VAREFOUT

VCCMSSIOB2

SPI_1_DO/GPIO_24

GND

VAREFOUT

VCCMSSIOB2

SPI_1_DO/GPIO_24

GND

NC

VCCMSSIOB2

GND

VCCMSSIOB2

GND

Note: Shading denotes pins that do not have completely identical functions from density to density. For

example, the bank assignment can be different for an I/O, or the function might be available only

on a larger density device.

Revision 10

5-59

Pin Descriptions

FG484

Pin Number

U1

A2F200 Function

GND

A2F500 Function

GND

U2

GPIO_5/IO42RSB4V0

GPIO_10/IO58RSB4V0

VCCMSSIOB4

MAC_RXD[1]/IO53RSB4V0

NC

GPIO_5/IO51RSB4V0

GPIO_10/IO67RSB4V0

VCCMSSIOB4

MAC_RXD[1]/IO62RSB4V0

NC

U3

U4

U5

U6

U7

VCC33AP

U8

VCC33N

U9

CM1

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

V1

VAREF0

GND33ADC1

ADC4

GND33ADC1

ADC4

NC

GNDTM2

NC

ADC11

GNDVAREF

VCC33SDD1

SPI_0_DO/GPIO_16

UART_0_RXD/GPIO_21

VCCMSSIOB2

I2C_1_SCL/GPIO_31

I2C_0_SCL/GPIO_23

GND

GNDVAREF

VCC33SDD1

SPI_0_DO/GPIO_16

UART_0_RXD/GPIO_21

VCCMSSIOB2

I2C_1_SCL/GPIO_31

I2C_0_SCL/GPIO_23

GND

GPIO_0/IO47RSB4V0

GPIO_6/IO41RSB4V0

GPIO_9/IO38RSB4V0

MAC_MDIO/IO49RSB4V0

MAC_RXD[0]/IO54RSB4V0

GND

GPIO_0/IO56RSB4V0

GPIO_6/IO50RSB4V0

GPIO_9/IO47RSB4V0

MAC_MDIO/IO58RSB4V0

MAC_RXD[0]/IO63RSB4V0

GND

V2

V3

V4

V5

V6

V7

SDD0

V8

ABPS1

V9

ADC2

V10

V11

V12

V13

V14

VCC33ADC0

ADC6

VCC33ADC0

ADC6

ADC5

ABPS5

NC

ADC8

Note: Shading denotes pins that do not have completely identical functions from density to density. For

example, the bank assignment can be different for an I/O, or the function might be available only

on a larger density device.

5-60

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

FG484

Pin Number

V15

V16

V17

V18

V19

V20

V21

V22

W1

A2F200 Function

A2F500 Function

GND33ADC2

NC

GND

SPI_0_DI/GPIO_17

SPI_1_DI/GPIO_25

SPI_0_DI/GPIO_17

SPI_1_DI/GPIO_25

UART_1_TXD/GPIO_28

I2C_0_SDA/GPIO_22

I2C_1_SDA/GPIO_30

GPIO_2/IO45RSB4V0

GPIO_7/IO40RSB4V0

GND

UART_1_TXD/GPIO_28

I2C_0_SDA/GPIO_22

I2C_1_SDA/GPIO_30

GPIO_2/IO54RSB4V0

GPIO_7/IO49RSB4V0

GND

W2

W3

W4

MAC_CRSDV/IO51RSB4V0

MAC_TXD[1]/IO55RSB4V0

NC

MAC_CRSDV/IO60RSB4V0

MAC_TXD[1]/IO64RSB4V0

SDD2

W5

W6

W7

GNDA

W8

TM0

W9

ABPS2

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

Y1

GND33ADC0

VCC15ADC1

ABPS6

GND33ADC0

VCC15ADC1

ABPS6

NC

CM4

NC

ABPS9

NC

VCC33ADC2

GNDA

PU_N

GNDSDD1

SPI_0_CLK/GPIO_18

GND

SPI_0_CLK/GPIO_18

GND

SPI_1_SS/GPIO_27

UART_1_RXD/GPIO_29

GPIO_3/IO44RSB4V0

VCCMSSIOB4

GPIO_15/IO34RSB4V0

MAC_TXEN/IO52RSB4V0

VCCMSSIOB4

GNDSDD0

SPI_1_SS/GPIO_27

UART_1_RXD/GPIO_29

GPIO_3/IO53RSB4V0

VCCMSSIOB4

GPIO_15/IO43RSB4V0

MAC_TXEN/IO61RSB4V0

VCCMSSIOB4

GNDSDD0

Y2

Y3

Y4

Y5

Y6

Note: Shading denotes pins that do not have completely identical functions from density to density. For

example, the bank assignment can be different for an I/O, or the function might be available only

on a larger density device.

Revision 10

5-61

Pin Descriptions

FG484

Pin Number

Y7

A2F200 Function

A2F500 Function

CM0

GNDTM0

ADC0

Y8

GNDTM0

Y9

ADC0

Y10

Y11

VCC15ADC0

ABPS7

VCC15ADC0

ABPS7

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

TM3

NC

ABPS8

NC

GND33ADC2

VCC15ADC2

VCCMAINXTAL

SDD1

NC

VCCMAINXTAL

SDD1

PTEM

VCC33A

SPI_0_SS/GPIO_19

VCCMSSIOB2

UART_0_TXD/GPIO_20

SPI_0_SS/GPIO_19

VCCMSSIOB2

UART_0_TXD/GPIO_20

Note: Shading denotes pins that do not have completely identical functions from density to density. For

example, the bank assignment can be different for an I/O, or the function might be available only

on a larger density device.

5-62

Revision 10

6 – Datasheet Information

List of Changes

The following table lists critical changes that were made in each revision of the SmartFusion datasheet.

Revision

Changes

Page

Revision 10

(January 2013)

The "SmartFusion cSoC Family Product Table" section has been updated to specify

that External Memory Controller support for A2F060-TQ144 is not available (SAR

41555).

II

The following Note was added to the "Package I/Os: MSS + FPGA I/Os" table (SAR

41027): "There are no LVTTL capable direct inputs available on A2F060 devices."

III

The "Product Ordering Codes" section has been updated to mention "Y" as "Blank"

mentioning "Device Does Not Include License to Implement IP Based on the

Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43218).

VI

Added a note to Table 2-3 • Recommended Operating Conditions5,6 (SAR 43428):

The programming temperature range supported is T_ambient= 0°C to 85°C.

2-3

Statements about the state of the I/Os during programming were updated in the 2-4, 5-7

following sections: "I/O Power-Up and Supply Voltage Thresholds for Power-On

Reset (Commercial and Industrial)" and "User I/O Naming Conventions" (SAR

43380).

In Table 2-4 • FPGA and Embedded Flash Programming, Storage and Operating

Limits, the upper value of temperature ranges was corrected from "Min." to "Max."

(SAR 41826).

2-4

Information for A2F200M3F-CS288 was added to Table 2-6 • Package Thermal

Resistance. The die size column was removed (SARs 41828, 42168).

2-7

Also added details for A2F200M3F-PQG208I (SAR 35728).

Added the following note to Table 2-65 • LVDS and Table 2-68 • LVPECL: "The above

mentioned timing parameters correspond to 24mA drive strength." (SAR 43457)

2-41,

2-43

The note in Table 2-86 • SmartFusion CCC/PLL Specification referring the reader to

SmartGen was revised to refer instead to the online help associated with the core

(SAR 34816).

2-63

The SRAM collision data in Table 2-87 • RAM4K9 and Table 2-88 • RAM512X18 was

updated (SAR 38583).

2-69,

2-70

The maximum input bias current for comparators 1, 3, 5, 7, and 9, in Table 2-98 •

Comparator Performance Specifications, was revised from 60 to 100 nA (SAR

36008).

2-84

Corrected the Start-up time unit from "ms" to "µs" in Table 2-100 • Voltage Regulator

(SAR 39395).

2-87

Added the "References" section for "SmartFusion Development Tools" (SAR 43460).

3-6

4-9

Updated the "References" section for Programming (SAR 43304). Added the

"Application Notes on IAP Programming Technique" section (SAR 43458).

Revision 10

6-1

Datasheet Information

Revision

Changes

Page

Revision 10

(continued)

A note was added to the "Supply Pins" table, referring to the SmartFusion cSoC

Board Design Guidelines application note for details on VCCPLLx capacitor

recommendations (SAR 42183).

5-1

In the "Supply Pins" section, the VPP capacitor value section has been modified to:

"For proper programming, 0.01μF, and 0.1μF to 1μF capacitors, (both rated at 16 V)

are to be connected in parallel across VPP and GND, and positioned as close to the

FPGA pins as possible." (SAR 43569).

5-1

In the "User Pins" section, added description ’These pins are located in Bank-2

(GPIO_16 to GPIO_31) for A2F060, A2F200, and A2F500 devices.’ for GPIO_x (SAR

28595).

5-6

5-8

Updated the MAINXIN and MAINXOUT pin descriptions in the "Special Function Pins"

section to read "If an external RC network or clock input is used, the RC components

are connected to the MAINXIN pin, with MAINXOUT left floating. When the main

crystal oscillator is not being used, MAINXIN and MAINXOUT pins can be left

floating." (SAR 42807).

Live at Power-Up (LAPU) has been replaced with ’Instant On’.

NA

II

Revision 9

The number of signal conditioning blocks (SCBs) for A2F500 in the "SmartFusion

(September 2012) cSoC Family Product Table" was corrected to 4. Previously it had incorrectly been

listed as 2 (SAR 39536).

The "Product Ordering Codes" section was revised to clarify that only one eNVM size

for each device is currently available (SAR 40333).

VI

Information pertaining to analog I/Os was added to the "Specifying I/O States During

Programming" section on page 1-3 (SAR 34836).

1-3

The formulas in the table notes for Table 2-29 • I/O Weak Pull-Up/Pull-Down

Resistances were corrected (SAR 34757).

2-27

2-43

2-59

Maximum values for VIL and VIH were corrected in LVPECL Table 2-66 • Minimum

and Maximum DC Input and Output Levels (SAR 37695).

Minimum pulse width High and Low values were added to the tables in the "Global

Tree Timing Characteristics" section. The maximum frequency for global clock

parameter was removed from these tables because a frequency on the global is only

an indication of what the global network can do. There are other limiters such as the

SRAM, I/Os, and PLL. SmartTime software should be used to determine the design

frequency (SAR 29270).

The temperature range for accuracy in Table 2-83 • Electrical Characteristics of the

RC Oscillator was changed from "0°C to 85°C" to "–40°C to 100°C" (SAR 33670). The

units for jitter were changed from ps to ps RMS (SAR 34270).

2-61

2-62

In Table 2-84 • Electrical Characteristics of the Main Crystal Oscillator, the output jitter

for the 10 MHz crystal was corrected from 50 ps RMS to 1 ns RS (SAR 32939).

Values for the startup time of VILXTAL were added (SAR 25248).

In Table 2-85 • Electrical Characteristics of the Low Power Oscillator, output jitter was

changed from 50 ps RMS to 30 ps RMS (SAR 32939). A value for ISTBXTAL standby

current was added (SAR 25249). Startup time for a test load of 30 pF was added

(SAR 27436).

6-2

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Revision

Changes

Page

Revision 9

(continued)

The following note was added to Table 2-86 • SmartFusion CCC/PLL Specification in

regard to delay increments in programmable delay blocks (SAR 34816):

2-63

"When the CCC/PLL core is generated by Microsemi core generator software, not all

delay values of the specified delay increments are available. Refer to SmartGen

online help for more information."

Figure 2-36 • FIFO Read and Figure 2-37 • FIFO Write have been added (SAR

34851).

2-72

4-8

Information regarding the MSS resetting itself after IAP of the FPGA fabric was added

to the "Reprogramming the FPGA Fabric Using the Cortex-M3" section (SAR 37970).

Instructions for unused VCC33ADCx pins were revised in "Supply Pins" (SAR 41137).

Libero IDE was changed to Libero SoC throughout the document (SAR 40264).

5-1

N/A

I, II

Revision 8

(March 2012)

In the "Analog Front-End (AFE)" section, the resolution for the first-order sigma delta

DAC was corrected from 12-bit to "8-bit, 16-bit, or 24-bit." The same correction was

made in the "SmartFusion cSoC Family Product Table" (SAR 36541).

The "SmartFusion cSoC Family Product Table" was revised to break out the features

by package as well as device.

II

The table now indicates that only one SPI is available for the PQ208 package in

A2F200 and A2F500, and in the TQ144 package for A2F060 (SAR 33477).

The EMC address bus size has been corrected to 26 bits (SAR 35664).

The "SmartFusion cSoC Device Status" table was revised to change the CS288

package for A2F200 and A2F500 from preliminary to production status (SAR 37811).

III

TQ144 package information for A2F060 was added to the "Package I/Os: MSS +

FPGA I/Os" table, "SmartFusion cSoC Device Status" table, "Product Ordering

Codes", and "Temperature Grade Offerings" table (SAR 36246).

III, VI

Table 1 • SmartFusion cSoC Package Sizes Dimensions is new (SAR 31178).

III

The Halogen-Free Packaging code (H) was removed from the "Product Ordering

Codes" table (SAR 34017).

VI

The "Specifying I/O States During Programming" section is new (SAR 34836).

1-3

The reference to guidelines for global spines and VersaTile rows, given in the "Global

Clock Dynamic Contribution—PCLOCK" section, was corrected to the "Device

Architecture" chapter in the SmartFusion FPGA Fabric User's Guide (SAR 34742).

2-15

The AC Loading figures in the "Single-Ended I/O Characteristics" section were

updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O

Software Settings" section (SAR 34891).

2-30,

2-24

The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 34799):

"It uses a 5 V–tolerant input buffer and push-pull output buffer."

2-32

2-69

In the SRAM "Timing Characteristics" tables, reference was made to a new

application note, Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-

Based cSoCs and FPGAs, which covers these cases in detail (SAR 34874).

The note for Table 2-93 • Current Monitor Performance Specification was modified to

include the statement that the restriction on the TM pad being no greater than 10 mV

above the CM pad.is applicable only if current monitor is used (SAR 26373).

2-77

The unit "FR" in Table 2-97 • ABPS Performance Specifications and Table 2-99 •

Analog Sigma-Delta DAC, used to designate full-scale error, was changed to "FS"

and clarified with a table note (SAR 35342).

2-82,

2-85

Revision 10

6-3

Datasheet Information

Revision

Changes

Page

Revision 8

(continued)

The description of "In-application programming (IAP)" methodology was changed to

state the difference for A2F060 and A2F500 compared to A2F200 (SAR 37808).

4-7

The "Global I/O Naming Conventions" section is new (SARs 28996, 31147). The 5-6, 5-6

description for IO "User Pins" was revised accordingly and moved out of the table and

into a new section: "User I/O Naming Conventions".

The descriptions for "MAINXIN" and "MAINXOUT" were revised to state how they

should be handled if using an external RC network or clock input (SAR 32594).

5-8

The description and type was revised for the "MSS_RESET_N" pin (SAR 34133).

The "TQ144" section and pin table for A2F060 are new (SAR 36246).

5-9

5-18

N/A

Revision 7

(August 2011)

The title of the datasheet was changed from SmartFusion Intelligent Mixed Signal

FPGAs to SmartFusion Customizable System-on-Chip (cSoC). Terminology

throughout was changed accordingly. The term cSoC defines a category of devices

that include at least FPGA fabric and a processor subsystem of some sort. It can also

include any of the following: analog, SerDes, ASIC blocks, customer specific IP, or

application-specific IP. SmartFusion is Microsemi’s first cSoC (SAR 33071).

The "SmartFusion cSoC Family Product Table" was revised to remove the note

stating that the A2F060 device is under definition and subject to change (SAR 33070).

A note was added for EMC, stating that it is not available on A2F500 for the PQ208

package (SAR 33041).

II

The "SmartFusion cSoC Device Status" table was revised. The status for A2F060

CS288 and FG256 moved from Advance to Preliminary. A2F200 PQ208 and A2F500

PQ208 moved from Advance to Production (SAR 33069).

III

The "Package I/Os: MSS + FPGA I/Os" table was revised. The number of direct

analog inputs for A2F060 packages increased from 6 to 11. The number of MSS I/Os

for the A2F060 FG256 package increased from 25 to 26 (SAR 33070). A note was

added stating that EMC is not available for the A2F500 PQ208 package (SAR 33041).

The note associated with the "SmartFusion cSoC System Architecture" diagram was

corrected from "Architecture for A2F500" to "Architecture for A2F200" (SAR 32578).

V

The Licensed DPA Logo was added to the "Product Ordering Codes" section. The

trademarked Licensed DPA Logo identifies that a product is covered by a DPA

counter-measures license from Cryptography Research (SAR 32151).

VI

The "Security" section and "Secure Programming" section were updated to clarify that 1-2, 4-9

although no existing security measures can give an absolute guarantee, SmartFusion

cSoCs implement the best security available in the industry (SAR 32865).

Storage temperature, T_STG, and junction temperature, T_J, were added to Table 2-1 •

Absolute Maximum Ratings (SAR 30863).

2-1

AC/DC characteristics for A2F060 were added to the "SmartFusion DC and Switching

Characteristics" chapter (SAR 33132). The following tables were updated:

2-12

2-13

2-75

Table 2-14 • Different Components Contributing to Dynamic Power Consumption in

SmartFusion cSoCs

Table 2-15 • Different Components Contributing to the Static Power Consumption in

SmartFusion cSoCs

Table 2-90 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C,

VCC = 1.425 V

2-85

2-89

Table 2-99 • Analog Sigma-Delta DAC

Table 2-101 • SPI Characteristics

6-4

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Revision

Changes

Page

Revision 7

(continued)

The following sentence was removed from the "I/O Power-Up and Supply Voltage

Thresholds for Power-On Reset (Commercial and Industrial)" section because it is

incorrect (SAR 31047):

2-4

"The many different supplies can power up in any sequence with minimized current

spikes or surges."

Table 2-8 • Quiescent Supply Current Characteristics was divided into two tables: one

for power supplies configurations and one for quiescent supply current. SoC mode

was added to both tables (SAR 26378) and VCOMPLAx was removed from Table 2-8

• Power Supplies Configuration (SAR 29591). Quiescent supply current values were

updated in Table 2-9 • Quiescent Supply Current Characteristics (SAR 33067).

2-10

2-14

The "Total Static Power Consumption—PSTAT" section was revised: "N_eNVM-BLOCKS

P_DC4" was removed from the equation for P_STAT(SAR 33067).

*

Table 2-14 • Different Components Contributing to Dynamic Power Consumption in

SmartFusion cSoCs and Table 2-15 • Different Components Contributing to the Static

Power Consumption in SmartFusion cSoCs were revised to reflect updates in the

SmartFusion power calculator (SARs 26405, 33067).

2-12,

2-13

Table 2-82 • A2F060 Global Resource is new (SAR 33132).

2-61

Output duty cycle was corrected to 50% in Table 2-83 • Electrical Characteristics of

the RC Oscillator. It was incorrectly noted as 1% previously. Operating current for 3.3

domain was added (SAR 32940).

Table 2-86 • SmartFusion CCC/PLL Specification was revised to add information and

measurements regarding CCC output peak-to-peak period jitter (SAR 32996).

2-63

The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics" 2-66 to

tables, Figure 2-38 • FIFO Reset, and the FIFO "Timing Waveforms" tables were

revised to ensure consistency with the software names (SAR 29991).

2-75

Table 2-90 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C,

VCC = 1.425 V was revised to correct the maximum frequencies (SAR 32410).

2-75

Table 2-96 • VAREF Stabilization Time was moved to the "SmartFusion DC and

Switching Characteristics" section from the SmartFusion Programmable Analog

User’s Guide because the information is extracted from characterization (SAR

24298).

2-81

2-84

The hysteresis section in Table 2-98 • Comparator Performance Specifications was

revised (SAR 33158).

The "SmartFusion Development Tools" was extensively updated (SAR 33216).

3-1

4-7

The text following Table 4-2 • JTAG Pin Descriptions was updated to add information

on control of the JTAGSEL pin. Manual jumpers on the evaluation and development

kits allow manual selection of this function for J-Link and ULINK debuggers (SAR

25592).

Revision 10

6-5

Datasheet Information

Revision

Changes

Page

Revision 7

(continued)

Usage instructions, such as how to handle the pin when unused, were added for the

following supply pins (SAR 29769):

5-2

through

5-3

"VCC15A"

"VCC15ADC0" through "VCC15ADC2"

"VCC33ADC0" through "VCC33ADC2"

"VCC33AP"

"VCC33ADC2"

"VCCLPXTAL"

"VCCMAINXTAL"

"VCCMSSIOB2"

"VCCPLLx"

"VCCRCOSC"

"VDDBAT"

The "IO" description was revised to clarify the definitions of u, I/O pair, and w,

differential pair (SAR 31147). Information on configuration of unused I/Os (including

unused MSS I/Os, SAR 26891) was added (SAR 32643).

5-6

Usage instructions were added for the following pins (SAR 29769):

5-9

through

5-13

"MSS_RESET_N"

"TCK"

"TMS"

"TRSTB"

"MAC_CLK"

Package names used in the "Pin Assignment Tables" section were revised to match

5-18

standards given in Package Mechanical Drawings (SAR 27395).

The pin assignments for A2F060 for "TQ144" and "FG256" have been revised due to

the device status change from advance to preliminary (SAR 33068).

5-18,

5-39

The "TQ144" and "FG256" pin assignment sections previously compared functions

between A2F060/A2F200 devices in one table and A2F200/A2F500 in a separate

table. Functions for all three devices have now been combined into one table for each

package (SAR 33072).

The "PQ208" pin table was revised for A2F500 to remove EMC functions, which are

not available for this device/package combination (SAR 33041).

5-32

III

Revision 6

(March 2011)

The "PQ208" package was added to product tables and "Product Ordering Codes" for

A2F200 and A2F500 (SAR 31005).

The "Package I/Os: MSS + FPGA I/Os" table was revised to add the CS288 package

for A2F060 and the PQ208 package for A2F200 and A2F500. A row was added for

shared analog inputs (SAR 31034).

III

The "SmartFusion cSoC Device Status" table was updated (SAR 31084).

III

VCCESRAM was added to Table 2-1 • Absolute Maximum Ratings, Table 2-3 • 2-1, 2-3,

Recommended Operating Conditions5,6, Table 2-8 • Power Supplies Configuration,

and the "Supply Pins" table (SAR 31035).

2-10, 5-1

The following note was removed from Table 2-8 • Power Supplies Configuration (SAR

30984):

2-10

"Current monitors and temperature monitors should not be used when Power-Down

and/or Sleep mode are required by the application."

6-6

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Revision

Changes

Page

Revision 6

(continued)

Dynamic power values were updated in the following tables. The table subtitles

changed where FPGA I/O banks were involved to note "I/O assigned to EMC I/O pins"

(SAR 30987).

2-10

2-11

Table 2-10 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software

Settings

Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software

Settings.

The "Timing Model" was updated (SAR 30986).

2-19

Values in the timing tables for the following sections were updated. Table subtitles

were updated for FPGA I/O banks to note "I/O assigned to EMC I/O pins" (SAR

30986).

2-23

2-26

"Overview of I/O Performance" section: Table 2-24, Table 2-25

"Detailed I/O DC Characteristics" section: Table 2-38, Table 2-39, Table 2-40,

Table 2-44, Table 2-45, Table 2-46, Table 2-50, Table 2-51, Table 2-52, Table 2-56,

Table 2-57, Table 2-58, Table 2-61, Table 2-62

"LVDS" section: Table 2-65

2-40

2-42

2-59

"LVPECL" section: Table 2-68

"Global Tree Timing Characteristics" section: Table 2-80, Table 2-81

The "PQ208" section and pin tables are new (SAR 31005).

5-32

5-40

Global clocks were removed from the A2F060 pin table for the "CS288" and "FG256"

packages, resulting in changed function names for affected pins (SAR 31033).

Revision 5

Table 2-2 • Analog Maximum Ratings was revised. The recommended CM[n] pad

2-2

2-9

(December 2010) voltage (relative to ground) was changed from –11 to –0.3 (SAR 28219).

Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays was revised

to change the values for 100ºC.

Power-down and Sleep modes, and all associated notes, were removed from

Table 2-8 • Power Supplies Configuration (SAR 29479). IDC3 and IDC4 were

renamed to IDC1 and IDC2 (SAR 29478). These modes are no longer supported. A

note was added to the table stating that current monitors and temperature monitors

should not be used when Power-down and/or Sleep mode are required by the

application.

2-10

The "Power-Down and Sleep Mode Implementation" section was deleted (SAR

29479).

N/A

Values for PAC9 and PAC10 for LVDS and LVPECL were revised in Table 2-10 •

Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings and

Table 2-12 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software

Settings*.

2-10,

2-11

Values for PAC1 through PAC4, PDC1, and PDC2 were added for A2F500 in

Table 2-14 • Different Components Contributing to Dynamic Power Consumption in

SmartFusion cSoCs and Table 2-15 • Different Components Contributing to the Static

Power Consumption in SmartFusion cSoCs

2-12,

2-13

The equation for "Total Dynamic Power Consumption—PDYN" in "SoC Mode" was

revised to add P_MSS. The "Microcontroller Subsystem Dynamic Contribution—PMSS"

section is new (SAR 29462).

2-14,

2-18

Information in Table 2-24 • Summary of I/O Timing Characteristics—Software Default

Settings (applicable to FPGA I/O banks) and Table 2-25 • Summary of I/O Timing

Characteristics—Software Default Settings (applicable to MSS I/O banks) was

updated.

2-25

Revision 10

6-7

Datasheet Information

Revision

Changes

Page

Revision 5

(continued)

Available values for the Std. speed were added to the timing tables from Table 2-38 • 2-31 to

3.3 V LVTTL / 3.3 V LVCMOS High Slew to Table 2-92 • JTAG 1532 (SAR 29331).

2-76

One or more values changed for the –1 speed in tables covering 3.3 V LVCMOS,

2.5 V LVCMOS, 1.8 V LVCMOS, 1.5 V LVCMOS, Combinatorial Cell Propagation

Delays, and A2F200 Global Resources.

Table 2-80 • A2F500 Global Resource is new.

2-60

2-75

Table 2-90 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C,

VCC = 1.425 V was revised (SAR 27585).

The programmable analog specifications tables were revised with updated 2-77 to

information.

2-87

Table 4-1 • Supported JTAG Programming Hardware was revised by adding a note to

indicate "planned support" for several of the items in the table.

4-7

The note on JTAGSEL in the "In-System Programming" section was revised to state

that SoftConsole selects the appropriate TAP controller using the CTXSELECT JTAG

command. When using SoftConsole, the state of JTAGSEL is a "don't care" (SAR

29261).

4-7

The "CS288" and "FG256" pin tables for A2F060 are new, comparing the A2F060

function with the A2F200 function (SAR 29353).

5-23

5-39

2-10

The "Handling When Unused" column was removed from the "FG256" pin table for

A2F200 and A2F500 (SAR 29691).

Revision 4

Table 2-8 • Power Supplies Configuration was revised. VCCRCOSC was moved to a

(September 2010) column of its own with new values. VCCENVM was added to the table. Standby mode

for VJTAG and VPP was changed from 0 V to N/A. "Disable" was changed to "Off" in

the eNVM column. The column for RCOSC was deleted.

The "Power-Down and Sleep Mode Implementation" section was revised to include

VCCROSC.

2-11

I

Revision 3

The "I/Os and Operating Voltage" section was revised to list "single 3.3 V power

(September 2010) supply with on-chip 1.5 V regulator" and "external 1.5 V is allowed" (SAR 27663).

The CS288 package was added to the "Package I/Os: MSS + FPGA I/Os" table (SAR III, VI, VI

27101), "Product Ordering Codes" table, and "Temperature Grade Offerings" table

(SAR 27044). The number of direct analog inputs for the FG256 package in A2F060

was changed from 8 to 6.

Two notes were added to the "SmartFusion cSoC Family Product Table" indicating

limitations for features of the A2F500 device:

II

Two PLLs are available in CS288 and FG484 (one PLL in FG256).

[ADCs, DACs, SCBs, comparators, current monitors, and bipolar high voltage

monitors are] Available on FG484 only. FG256 and CS288 packages offer the same

programmable analog capabilities as A2F200.

Table cells were merged in rows containing the same values for easier reading (SAR

24748).

The security feature option was added to the "Product Ordering Codes" table.

VI

6-8

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Revision

Changes

Page

Revision 3

(continued)

In Table 2-3 • Recommended Operating Conditions5,6, the VDDBAT recommended

operating range was changed from "2.97 to 3.63" to "2.7 to 3.63" (SAR 25246).

Recommended operating range was changed to "3.15 to 3.45" for the following

voltages:

2-3

VCC33A

VCC33ADCx

VCC33AP

VCC33SDDx

VCCMAINXTAL

VCCLPXTAL

Two notes were added to the table (SAR 27109):

1. The following 3.3 V supplies should be connected together while following proper

noise filtering practices: VCC33A, VCC33ADCx, VCC33AP, VCC33SDDx,

VCCMAINXTAL, and VCCLPXTAL.

2. The following 1.5 V supplies should be connected together while following proper

noise filtering practices: VCC, VCC15A, and VCC15ADCx.

In Table 2-3

•

Recommended Operating Conditions5,6, the description for

2-3

VCCLPXTAL was corrected to change "32 Hz" to "32 KHz" (SAR 27110).

The "Power Supply Sequencing Requirement" section is new (SAR 27178).

2-4

Table 2-8 • Power Supplies Configuration was revised to change most on/off entries

to voltages. Note 5 was added, stating that "on" means proper voltage is applied. The

values of 6 µA and 16 µA were removed for IDC1 and IDC2 for 3.3 V. A note was

added for IDC1 and IDC2: "Power mode and Sleep mode are consuming higher

current than expected in the current version of silicon. These specifications will be

updated when new version of the silicon is available" (SAR 27926).

2-10

The "Power-Down and Sleep Mode Implementation" section is new (SAR 27178).

2-11

2-63

A note was added to Table 2-86 • SmartFusion CCC/PLL Specification, pertaining to

f_{out_CCC}, stating that "one of the CCC outputs (GLA0) is used as an MSS clock and is

limited to 100 MHz (maximum) by software" (SAR 26388).

Table 2-90 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C,

VCC = 1.425 V was revised. Values were included for A2F200 and A2F500, for –1

and Std. speed grades. A note was added to define 6:1:1:1 and 5:1:1:1 (SAR 26166).

2-75

The units were corrected (mV instead of V) for input referred offset voltage,

GDEC[1:0] = 00 in Table 2-97 • ABPS Performance Specifications (SAR 25381).

2-82

2-87

2-88

4-7

The test condition values for operating current (ICC33A, typical) were changed in

Table 2-100 • Voltage Regulator (SAR 26465).

Figure 2-46 • Typical Output Voltage was revised to add legends for the three curves,

stating the load represented by each (SAR 25247).

The "SmartFusion Programming" chapter was moved to this document from the

SmartFusion Subsystem Microcontroller User’s Guide (SAR 26542). The "Typical

Programming and Erase Times" section was added to this chapter.

Figure 4-1 • TRSTB Logic was revised to change 1.5 V to "VJTAG (1.5 V to 3.3 V

nominal)" (SAR 24694).

4-8

Revision 10

6-9

Datasheet Information

Revision

Changes

Page

Revision 3

(continued)

Two notes were added to the "Supply Pins" table (SAR 27109):

5-1

1. The following supplies should be connected together while following proper noise

filtering practices: VCC33A, VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL,

and VCCLPXTAL.

2. The following 1.5 V supplies should be connected together while following proper

noise filtering practices: VCC, VCC15A, and VCC15ADCx.

The descriptions for the "VCC33N", "NCAP", and "PCAP" pins were revised to include 5-2, 5-9,

information on what to do if analog SCB features and SDDs are not used (SAR

26744).

5-9

Information was added to the "User Pins" table regarding tristating of used and

unused GPIO pins. The IO portion of the table was revised to state that unused I/O

pins are disabled by Libero IDE software and include a weak pull-up resistor (SAR

26890). Information was added regarding behavior of used I/O pins during power-up.

5-6

The type for "EMC_RW_N" was changed from In/out to Out (SAR 25113).

5-12

5-14

A note was added to the "Analog Front-End (AFE)" table stating that unused analog

inputs should be grounded (SAR 26744).

The "TQ144" section is new, with pin tables for A2F200 and A2F500 (SAR 27044).

5-18

5-39

The "FG256" pin table was replaced and now includes "Handling When Unused"

information (SAR 27709).

Revision 2

(May 2010)

Embedded nonvolatile flash memory (eNVM) was changed from "64 to 512 Kbytes" to

"128 to 512 Kbytes" in the "Microcontroller Subsystem (MSS)" section and

"SmartFusion cSoC Family Product Table" (SAR 26005).

I, II

The main oscillator range of values was changed to "32 KHz to 20 MHz" in the

"Microcontroller Subsystem (MSS)" section and the "SmartFusion cSoC Family

Product Table" (SAR 24906).

The value for t_PDwas changed from 50 ns to 15 ns for the high-speed voltage

comparators listed in the "Analog Front-End (AFE)" section (SAR 26005).

I

The number of PLLs for A2F200 was changed from 2 to 1 in the "SmartFusion cSoC

Family Product Table" (SAR 25093).

II

Values for direct analog input, total analog input, and total I/Os were updated for the

FG256 package, A2F060, in the "Package I/Os: MSS + FPGA I/Os" table. The Max.

column was removed from the table (SAR 26005).

III

The Speed Grade section of the "Product Ordering Codes" table was revised

(SAR 25257).

VI

Revision 1

(March 2010)

The "Product Ordering Codes" table was revised to add "blank" as an option for lead-

free packaging and application (junction temperature range).

VI

Table 2-3 • Recommended Operating Conditions5,6 was revised. Ta (ambient

temperature) was replaced with T_J(junction temperature).

2-3

PDC5 was deleted from Table 2-15 • Different Components Contributing to the Static

Power Consumption in SmartFusion cSoCs.

2-13

2-27

2-77

The formulas in the footnotes for Table 2-29 • I/O Weak Pull-Up/Pull-Down

Resistances were revised.

The values for input biased current were revised in Table 2-93 • Current Monitor

Performance Specification.

6-10

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Revision

Changes

Page

Revision 0

(March 2010)

The "Analog Front-End (AFE)" section was updated to change the throughput for 10-

bit mode from 600 Ksps to 550 Ksps.

I

The A2F060 device was added to product information tables.

N/A

VI

The "Product Ordering Codes" table was updated to removed Std. speed and add

speed grade 1. Pre-production was removed from the application ordering code

category.

The "SmartFusion cSoC Block Diagram" was revised.

IV

The "Datasheet Categories" section was updated, referencing the "SmartFusion 1-4, IV

cSoC Block Diagram" table, which is new.

The "VCCI" parameter was renamed to "VCCxxxxIOBx."

"Advanced I/Os" were renamed to "FPGA I/Os."

N/A

Generic pin names that represent multiple pins were standardized with a lower case x

as a placeholder. For example, VAREFx designates VAREF0, VAREF1, and VAREF2.

Modes were renamed as follows:

Operating mode was renamed to SoC mode.

32KHz Active mode was renamed to Standby mode.

Battery mode was renamed to Time Keeping mode.

Table entries have been filled with values as data has become available.

Table 2-1 • Absolute Maximum Ratings, Table 2-2 • Analog Maximum Ratings, and

Table 2-3 • Recommended Operating Conditions5,6 were revised extensively.

2-1

through

2-3

Device names were updated in Table 2-6 • Package Thermal Resistance.

Table 2-8 • Power Supplies Configuration was revised extensively.

2-7

2-10

2-11

Table 2-11 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software

Settings was revised extensively.

Removed "Example of Power Calculation."

N/A

Table 2-14 • Different Components Contributing to Dynamic Power Consumption in

SmartFusion cSoCs was revised extensively.

2-12

Table 2-15 • Different Components Contributing to the Static Power Consumption in

SmartFusion cSoCs was revised extensively.

2-13

The "Power Calculation Methodology" section was revised.

2-14

2-61

2-62

Table 2-83 • Electrical Characteristics of the RC Oscillator was revised extensively.

Table 2-85 • Electrical Characteristics of the Low Power Oscillator was revised

extensively.

The parameter t_RSTBQwas changed to T_C2CWRHin Table 2-87 • RAM4K9.

2-69

2-80

The 12-bit mode row for integral non-linearity was removed from Table 2-95 • ADC

Specifications. The typical value for 10-bit mode was revised. The table note was

punctuated correctly to make it clear.

Figure 37-34 • Write Access after Write onto Same Address, Figure 37-34 • Read

Access after Write onto Same Address, and Figure 37-34 • Write Access after Read

onto Same Address were deleted.

N/A

Table 2-100 • Voltage Regulator was revised extensively.

2-87

The "Serial Peripheral Interface (SPI) Characteristics" section and "Inter-Integrated

Circuit (I2C) Characteristics" section are new.

2-89,

2-91

Revision 10

6-11

Datasheet Information

Revision

Changes

Page

Revision 0

(continued)

"SmartFusion Development Tools" section was replaced with new content.

3-1

The pin description tables were revised by adding additional pins to reflect the pinout

for A2F500.

5-1

through

5-16

The descriptions for "GNDSDD1" and "VCC33SDD1" were revised.

The description for "VCC33A" was revised.

5-1, 5-2

5-2

The pin tables for the "FG256" and "FG484" were replaced with tables that compare

pin functions across densities for each package.

5-39

Draft B

The "Digital I/Os" section was renamed to the "I/Os and Operating Voltage" section

I

(December 2009) and information was added regarding digital and analog VCC.

The "SmartFusion cSoC Family Product Table" and "Package I/Os: MSS + FPGA

I/Os" section were revised.

II

The terminology for the analog blocks was changed to "programmable analog,"

consisting of two blocks: the analog front-end and analog compute engine. This is

reflected throughout the text and in the "SmartFusion cSoC Block Diagram".

IV

The "Product Ordering Codes" table was revised to add G as an ordering code for

eNVM size.

VI

Timing tables were populated with information that has become available for speed

grade –1.

N/A

All occurrences of the VMV parameter were removed.

N/A

2-2

The SDD[n] voltage parameter was removed from Table 2-2 • Analog Maximum

Ratings.

Table 36-4 • Flash Programming Limits – Retention, Storage and Operating

2-4

Temperature was replaced with Table 2-4

Programming, Storage and Operating Limits.

• FPGA and Embedded Flash

The "Thermal Characteristics" section was revised extensively.

Table 2-8 • Power Supplies Configuration was revised significantly.

2-7

2-10

2-12

Table 2-14 • Different Components Contributing to Dynamic Power Consumption in

SmartFusion cSoCs and Table 2-15 • Different Components Contributing to the Static

Power Consumption in SmartFusion cSoCs were updated.

Figure 2-2 • Timing Model was updated.

2-19

2-29

The temperature associated with the reliability for LVTTL/LVCMOS in Table 2-34 • I/O

Input Rise Time, Fall Time, and Related I/O Reliability was changed from 110º to

100º.

The values in Table 2-78 • Combinatorial Cell Propagation Delays were updated.

2-57

2-62

Table 2-85 • Electrical Characteristics of the Low Power Oscillator is new. Table 2-84 •

Electrical Characteristics of the Main Crystal Oscillator was revised.

Table 2-90 • eNVM Block Timing, Worst Commercial Case Conditions: TJ = 85°C,

VCC = 1.425 V and Table 2-91 • FlashROM Access Time, Worse Commercial Case

Conditions: TJ = 85°C, VCC = 1.425 V are new.

2-75

The performance tables in the "Programmable Analog Specifications" section were

revised, including new data available. Table 2-99 • Analog Sigma-Delta DAC is new.

2-77

4-15

The "256-Pin FBGA" table for A2F200 is new.

6-12

Revision 10

SmartFusion Customizable System-on-Chip (cSoC)

Datasheet Categories


型号：	A2F060M3G-1TQ208YI
厂家：	Microsemi
描述：	SmartFusion Customizable System-on-Chip (cSoC) 的SmartFusion可定制系统级芯片（ CSOC ）
文件：	总192页 (文件大小：11779K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A2F060M3G-1TQ208YI [MICROSEMI]

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