A3PE1500-1FGG208YES [MICROSEMI]

ProASIC3E Flash Family FPGAs with Optional Soft ARM Support; ProASIC3E闪存系列FPGA具有可选的软ARM支持


型号：	A3PE1500-1FGG208YES
厂家：	Microsemi
描述：	ProASIC3E Flash Family FPGAs with Optional Soft ARM Support ProASIC3E闪存系列FPGA具有可选的软ARM支持闪存
文件：	总162页 (文件大小：8630K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Revision 13

ProASIC3E Flash Family FPGAs

with Optional Soft ARM Support

Features and Benefits

Pro (Professional) I/O

•

700 Mbps DDR, LVDS-Capable I/Os

High Capacity

1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Bank-Selectable I/O Voltages—up to 8 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS

2.5 V / 5.0 V Input

•

600 k to 3 Million System Gates

108 to 504 kbits of True Dual-Port SRAM

Up to 620 User I/Os

Reprogrammable Flash Technology

•

Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS

Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II

•

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

•

Instant On Level 0 Support

Single-Chip Solution

Retains Programmed Design when Powered Off

•

I/O Registers on Input, Output, and Enable Paths

Hot-Swappable and Cold Sparing I/Os

Programmable Output Slew Rate and Drive Strength

Programmable Input Delay

Schmitt Trigger Option on Single-Ended Inputs

Weak Pull-Up/-Down

On-Chip User Nonvolatile Memory

•

1 kbit of FlashROM with Synchronous Interfacing

High Performance

•

350 MHz System Performance

3.3 V, 66 MHz 64-Bit PCI

IEEE 1149.1 (JTAG) Boundary Scan Test

Pin-Compatible Packages across the ProASIC 3E Family

In-System Programming (ISP) and Security

•

ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption via JTAG (IEEE 1532–compliant)

Clock Conditioning Circuit (CCC) and PLL

•

FlashLock Designed to Secure FPGA Contents

•

Six CCC Blocks, Each with an Integrated PLL

Configurable Phase-Shift, Multiply/Divide, Delay Capabilities

and External Feedback

Low Power

•

Core Voltage for Low Power

Support for 1.5-V-Only Systems

Low-Impedance Flash Switches

•

Wide Input Frequency Range (1.5 MHz to 350 MHz)

SRAMs and FIFOs

•

Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

High-Performance Routing Hierarchy

•

Segmented, Hierarchical Routing and Clock Structure

Ultra-Fast Local and Long-Line Network

Enhanced High-Speed, Very-Long-Line Network

High-Performance, Low-Skew Global Network

Architecture Supports Ultra-High Utilization

•

True Dual-Port SRAM (except ×18)

24 SRAM and FIFO Configurations with Synchronous Operation

up to 350 MHz

ARM^®Processor Support in ProASIC3E FPGAs

•

M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available

with or without Debug

Table 1-1 • ProASIC3E Product Family

ProASIC3E Devices

A3PE600

A3PE1500

A3PE3000

Cortex-M1 Devices

M1A3PE1500

M1A3PE3000

System Gates

600,000

13,824

108

1,500,000

3,000,000

VersaTiles (D-flip-flops)

RAM Kbits (1,024 bits)

4,608-Bit Blocks

38,400

270

75,264

504

112

FlashROM Kbits

Secure (AES) ISP

Yes

CCCs with Integrated PLLs

VersaNet Globals

I/O Banks

Maximum User I/Os

270

444

620

Package Pins

PQFP

FBGA

PQ208

FG256, FG484

PQ208

FG484, FG676

PQ208

FG324, FG484, FG896

Notes:

1. Refer to the Cortex-M1 product brief for more information.

2. The PQ208 package supports six CCCs and two PLLs.

3. Six chip (main) and three quadrant global networks are available.

4. For devices supporting lower densities, refer to the ProASIC3 Flash Family FPGAs datasheet.

January 2013

ProASIC3E Flash Family FPGAs

I/Os Per Package

ProASIC3E Devices

Cortex-M1 Devices ²

A3PE600

A3PE1500 ³

M1A3PE1500

I/O Types

A3PE3000 ³

M1A3PE3000

Package

PQ208

FG256

FG324

FG484

FG676

FG896

Notes:

147

165

–

147

–

147

–

221

341

–

110

168

–

270

–

135

–

280

444

–

139

222

–

620

310

1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3E FPGA Fabric User’s

Guide to ensure compliance with design and board migration requirements.

2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited as follows:

– SSTL3(I) and (II): up to 40 I/Os per north or south bank

– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank

– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank

4. FG256 and FG484 are footprint-compatible packages.

5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per

minibank (group of I/Os).

6. "G" indicates RoHS-compliant packages. Refer to the "ProASIC3E Ordering Information" on page III for the location of the "G"

in the part number.

Table 1-2 • ProASIC3E FPGAs Package Sizes Dimensions

Package

PQ208

28 × 28

784

FG256

17 × 17

289

FG324

19 × 19

361

FG484

23 × 23

529

FG676

27 × 27

729

FG896

31 × 31

961

Length × Width (mm\mm)

Nominal Area (mm²)

Pitch (mm)

0.5

1.0

Height (mm)

3.40

1.60

1.63

2.23

ProASIC3E Device Status

ProASIC3E Devices

Status

M1 ProASIC3E Devices

Status

A3PE600

Production

A3PE1500

A3PE3000

M1A3PE1500

M1A3PE3000

Production

Revision 13

ProASIC3E Flash Family FPGAs

ProASIC3E Ordering Information

A3PE3000

896

Application (Temperature Range)

Blank = Commercial (0°C to +70°C Ambient Temperature)

I = Industrial (–40°C to +85°C Ambient Temperature)

PP = Pre-Production

ES = Engineering Sample (Room Temperature Only)

Security Feature

Y = Device Includes License to Implement IP Based on the

Cryptography Research, Inc. (CRI) Patent Portfolio

Blank = Device Does Not Include License to Implement IP Based

on the Cryptography Research, Inc. (CRI) Patent Portfolio

Package Lead Count

Lead-Free Packaging

Blank = Standard Packaging

G = RoHS-Compliant (Green) Packaging

Package Type

PQ Plastic Quad Flat Pack (0.5 mm pitch)

FG Fine Pitch Ball Grid Array (1.0 mm pitch)

Speed Grade

1 = 15% Faster than Standard

2 = 25% Faster than Standard

Part Number

ProASIC3E Devices

A3PE600 = 600,000 System Gates

A3PE1500 = 1,500,000 System Gates

A3PE3000 = 3,000,000 System Gates

ProASIC3E Devices with Cortex-M1

M1A3PE1500

M1A3PE3000

1,500,000 System Gates

3,000,000 System Gates

Revision 13

III

ProASIC3E Flash Family FPGAs

Temperature Grade Offerings

Package

Cortex-M1 Devices

PQ208

A3PE600

A3PE1500

A3PE3000

M1A3PE1500

M1A3PE3000

C, I

–

C, I

–

C, I

–

FG256

FG324

–

C, I

–

FG484

C, I

–

C, I

–

FG676

FG896

–

C, I

Note: C = Commercial temperature range: 0°C to 70°C ambient temperature

I = Industrial temperature range: –40°C to 85°C ambient temperature

Speed Grade and Temperature Grade Matrix

Temperature Grade

Std.



–1



–2



C ¹

I ²



Notes:

1. C = Commercial temperature range: 0°C to 70°C ambient temperature

2. I = Industrial temperature range: –40°C to 85°C ambient temperature

References made to ProASIC3E devices also apply to ARM-enabled ProASIC3E devices. The ARM-enabled part numbers start with

M1 (Cortex-M1).

Contact your local Microsemi SoC Products Group representative for device availability:

http://www.microsemi.com/soc/contact/default.aspx.

Revision 13

ProASIC3E Flash Family FPGAs

Table of Contents

ProASIC3E Device Family Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

ProASIC3E DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82

Pin Descriptions and Packaging

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

User-Defined Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

Package Pin Assignments

PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8

FG324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16

FG676 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32

FG896 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

Revision 13

1 – ProASIC3E Device Family Overview

General Description

ProASIC3E, the third-generation family of Microsemi flash FPGAs, offers performance, density, and

features beyond those of the ProASIC^PLUS®family. Nonvolatile flash technology gives ProASIC3E

devices the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3E is

reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable

designers to create high-density systems using existing ASIC or FPGA design flows and tools.

ProASIC3E devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on six integrated phase-locked loops (PLLs). ProASIC3E devices have

up to three million system gates, supported with up to 504 kbits of true dual-port SRAM and up to 620

user I/Os.

Several ProASIC3E devices support the Cortex-M1 soft IP cores, and the ARM-Enabled devices have

Microsemi ordering numbers that begin with M1A3PE.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-

based FPGAs, flash-based ProASIC3E devices allow all functionality to be Instant On; no external boot

PROM is required. On-board security mechanisms prevent access to all the programming information

and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system

reprogramming to support future design iterations and field upgrades with confidence that valuable

intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the

industry-standard AES algorithm. The ProASIC3E family device architecture mitigates the need for ASIC

migration at higher user volumes. This makes the ProASIC3E family a cost-effective ASIC replacement

solution, especially for applications in the consumer, networking/ communications, computing, and

avionics markets.

Security

The nonvolatile, flash-based ProASIC3E devices do not require a boot PROM, so there is no vulnerable

external bitstream that can be easily copied. ProASIC3E devices incorporate FlashLock, which provides

a unique combination of reprogrammability and design security without external overhead, advantages

that only an FPGA with nonvolatile flash programming can offer.

ProASIC3E devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level

of protection in the FPGA industry for programmed intellectual property and configuration data. In

addition, all FlashROM data in ProASIC3E devices can be encrypted prior to loading, using the industry-

leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the

National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard.

ProASIC3E devices have a built-in AES decryption engine and a flash-based AES key that make them

the most comprehensive programmable logic device security solution available today. ProASIC3E

devices with AES-based security provide a high level of protection for secure, remote field updates over

public networks such as the Internet, and ensure that valuable IP remains out of the hands of system

overbuilders, system cloners, and IP thieves.

Security, built into the FPGA fabric, is an inherent component of the ProASIC3E family. The flash cells

are located beneath seven metal layers, and many device design and layout techniques have been used

to make invasive attacks extremely difficult. The ProASIC3E family, with FlashLock and AES security, is

unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected

with industry-standard security, making remote ISP possible. A ProASIC3E device provides the best

available security for programmable logic designs.

Revision 13

1-1

ProASIC3E Device Family Overview

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the

configuration data is an inherent part of the FPGA structure, and no external configuration data needs to

be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3E FPGAs

do not require system configuration components such as EEPROMs or microcontrollers to load device

configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system

reliability.

Instant On

Flash-based ProASIC3E devices support Level 0 of the Instant On classification standard. This feature

helps in system component initialization, execution of critical tasks before the processor wakes up, setup

and configuration of memory blocks, clock generation, and bus activity management. The Instant On

feature of flash-based ProASIC3E devices greatly simplifies total system design and reduces total

system cost, often eliminating the need for CPLDs and clock generation PLLs that are used for these

purposes in a system. In addition, glitches and brownouts in system power will not corrupt the

ProASIC3E device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be

reloaded when system power is restored. This enables the reduction or complete removal of the

configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from

the PCB design. Flash-based ProASIC3E devices simplify total system design and reduce cost and

design risk while increasing system reliability and improving system initialization time.

Firm Errors

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike

a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These

errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a

complete system failure. Firm errors do not exist in the configuration memory of ProASIC3E flash-based

FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3E FPGAs cannot be

altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in

the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and

correction (EDAC) circuitry built into the FPGA fabric.

Low Power

Flash-based ProASIC3E devices exhibit power characteristics similar to an ASIC, making them an ideal

choice for power-sensitive applications. ProASIC3E devices have only a very limited power-on current

surge and no high-current transition period, both of which occur on many FPGAs.

ProASIC3E devices also have low dynamic power consumption to further maximize power savings.

Advanced Flash Technology

The ProASIC3E family offers many benefits, including nonvolatility and reprogrammability through an

advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design

techniques are used to implement logic and control functions. The combination of fine granularity,

enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization

without compromising device routability or performance. Logic functions within the device are

interconnected through a four-level routing hierarchy.

1-2

Revision 13

ProASIC3E Flash Family FPGAs

Advanced Architecture

The proprietary ProASIC3E architecture provides granularity comparable to standard-cell ASICs. The

ProASIC3E device consists of five distinct and programmable architectural features (Figure 1-1 on

page 3):

•

FPGA VersaTiles

Dedicated FlashROM

Dedicated SRAM/FIFO memory

Extensive CCCs and PLLs

Pro I/O structure

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic

function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch

interconnections. The versatility of the ProASIC3E core tile as either a three-input lookup table (LUT)

equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile

capability is unique to the ProASIC family of third-generation architecture Flash FPGAs. VersaTiles are

connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the

device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is

possible for virtually any design.

CCC

RAM Block

4,608-Bit Dual-Port SRAM

or FIFO Block

Pro I/Os

VersaTile

RAM Block

4,608-Bit Dual-Port SRAM

or FIFO Block

User Nonvolatile

Charge Pumps

ISP AES Decryption

FlashROM

Figure 1-1 • ProASIC3E Device Architecture Overview

Revision 13

1-3

ProASIC3E Device Family Overview

VersaTiles

The ProASIC3E core consists of VersaTiles, which have been enhanced beyond the ProASIC^PLUS®core

tiles. The ProASIC3E VersaTile supports the following:

•

All 3-input logic functions—LUT-3 equivalent

Latch with clear or set

D-flip-flop with clear or set

Enable D-flip-flop with clear or set

Refer to Figure 1-2 for VersaTile configurations.

Enable D-Flip-Flop with Clear or Set

D-Flip-Flop with Clear or Set

LUT-3 Equivalent

Data

CLK

CLR

LUT-3

D-FF

CLK

D-FF

Enable

CLR

Figure 1-2 • VersaTile Configurations

User Nonvolatile FlashROM

ProASIC3E devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can

be used in diverse system applications:

•

Internet protocol addressing (wireless or fixed)

System calibration settings

Device serialization and/or inventory control

Subscription-based business models (for example, set-top boxes)

Secure key storage for secure communications algorithms

Asset management/tracking

Date stamping

Version management

The FlashROM is written using the standard ProASIC3E IEEE 1532 JTAG programming interface. The

core can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks, as in security keys stored in the FlashROM for a

user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be read

back either through the JTAG programming interface or via direct FPGA core addressing. Note that the

FlashROM can only be programmed from the JTAG interface and cannot be programmed from the

internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte

basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks

and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the

FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM

address define the byte.

The ProASIC3E development software solutions, Libero^®System-on-Chip (SoC) and Designer, have

extensive support for the FlashROM. One such feature is auto-generation of sequential programming

files for applications requiring a unique serial number in each part. Another feature allows the inclusion of

static data for system version control. Data for the FlashROM can be generated quickly and easily using

Libero SoC and Designer software tools. Comprehensive programming file support is also included to

allow for easy programming of large numbers of parts with differing FlashROM contents.

1-4

Revision 13

ProASIC3E Flash Family FPGAs

SRAM and FIFO

ProASIC3E devices have embedded SRAM blocks along their north and south sides. Each variable-

aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9,

1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be

configured with different bit widths on each port. For example, data can be sent through a 4-bit port and

read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port

(ROM emulation mode) using the UJTAG macro.

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM

block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width

and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and

Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control

unit contains the counters necessary for generation of the read and write address pointers. The

embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

ProASIC3E devices provide designers with very flexible clock conditioning capabilities. Each member of

the ProASIC3E family contains six CCCs, each with an integrated PLL.

The six CCC blocks are located at the four corners and the centers of the east and west sides.

To maximize user I/Os, only the center east and west PLLs are available in devices using the PQ208

package. However, all six CCC blocks are still usable; the four corner CCCs allow simple clock delay

operations as well as clock spine access.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

•

Wide input frequency range (f_{IN_CCC}) = 1.5 MHz to 350 MHz

Output frequency range (f_{OUT_CCC}) = 0.75 MHz to 350 MHz

Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns

2 programmable delay types for clock skew minimization

Clock frequency synthesis

Additional CCC specifications:

•

Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider

configuration.

•

Output duty cycle = 50% ± 1.5% or better

Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global

network used

•

Maximum acquisition time = 300 µs

Low power consumption of 5 mW

Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns

Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /

f_{OUT_CCC}

)

Global Clocking

ProASIC3E devices have extensive support for multiple clocking domains. In addition to the CCC and

PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant

global networks. The VersaNets can be driven by the CCC or directly accessed from the core via

multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid

distribution of high fanout nets.

Revision 13

1-5

ProASIC3E Device Family Overview

Pro I/Os with Advanced I/O Standards

The ProASIC3E family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V,

1.8 V, 2.5 V, and 3.3 V). ProASIC3E FPGAs support 19 different I/O standards, including single-ended,

differential, and voltage-referenced. The I/Os are organized into banks, with eight banks per device (two

per side). The configuration of these banks determines the I/O standards supported. Each I/O bank is

subdivided into VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8

to 18 I/Os. All the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a given

VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be able to use that

reference voltage.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

•

Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)

Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II)

ProASIC3E banks support M-LVDS with 20 multi-drop points.

Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card

in a powered-up system.

Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed

when the system is powered up, while the component itself is powered down, or when power supplies

are floating.

Specifying I/O States During Programming

You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for

PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.

Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have

limited display of Pin Numbers only.

1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during

programming.

2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator

window appears.

3. Click the Specify I/O States During Programming button to display the Specify I/O States During

Programming dialog box.

4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.

Select the I/Os you wish to modify (Figure 1-3 on page 1-7).

5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings

for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state

settings:

1 – I/O is set to drive out logic High

0 – I/O is set to drive out logic Low

Last Known State – I/O is set to the last value that was driven out prior to entering the

programming mode, and then held at that value during programming

Z -Tri-State: I/O is tristated

1-6

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ProASIC3E Flash Family FPGAs

Figure 1-3 • I/O States During Programming Window

6. Click OK to return to the FlashPoint – Programming File Generator window.

I/O States during programming are saved to the ADB and resulting programming files after

completing programming file generation.

Revision 13

1-7

2 – ProASIC3E DC and Switching Characteristics

General Specifications

DC and switching characteristics for –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA

specifications. Some restrictions might be added and will be reflected in future revisions of this

document. The –F speed grade is only supported in the commercial temperature range.

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any

other conditions beyond those listed under the Recommended Operating Conditions specified in

Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol

VCC

Parameter

DC core supply voltage

JTAG DC voltage

Limits

Units

–0.3 to 1.65

VJTAG

–0.3 to 3.75

VPUMP Programming voltage

–0.3 to 3.75

VCCPLL Analog power supply (PLL)

–0.3 to 1.65

–0.3 to 3.75

VCCI ²

VMV ²

DC I/O output buffer supply voltage

DC I/O input buffer supply voltage

I/O input voltage

–0.3 to 3.75

–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)

–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower

(when I/O hot-insertion mode is disabled)

T_STG

Storage temperature

Junction temperature

–65 to +150

+125

°C

T_J

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may

undershoot or overshoot according to the limits shown in Table 2-3 on page 2-2.

2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on

page 3-1 for further information.

3. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating

limits, refer to Table 2-2 on page 2-2.

Revision 13

2-1

ProASIC3E DC and Switching Characteristics

Table 2-2 • Recommended Operating Conditions ¹

Symbol

T_A

Parameter

Commercial

0 to +70

Industrial

–40 to +85

–40 to +100

1.425 to 1.575

1.4 to 3.6

Units

°C

Ambient temperature

Junction temperature

T_J

0 to +85

VCC

1.5 V DC core supply voltage

JTAG DC voltage

1.425 to 1.575

1.4 to 3.6

VJTAG

VPUMP

Programming voltage

Programming Mode²

Operation³

3.15 to 3.45

0 to 3.6

3.15 to 3.45

0 to 3.6

VCCPLL

Analog power supply (PLL)

1.425 to 1.575

1.7 to 1.9

1.425 to 1.575

1.7 to 1.9

VCCI and VMV ⁴1.5 V DC supply voltage

1.8 V DC supply voltage

2.5 V DC supply voltage

2.3 to 2.7

3.3 V DC supply voltage

3.0 to 3.6

3.0 V DC supply voltage⁵

2.7 to 3.6

LVDS/B-LVDS/M-LVDS differential I/O

LVPECL differential I/O

2.375 to 2.625

3.0 to 3.6

2.375 to 2.625

3.0 to 3.6

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. The programming temperature range supported is T = 0°C to 85°C.

ambient

3. VPUMP can be left floating during normal operation (not programming mode).

4. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-13 on page 2-16. VMV and VCCI should be at the same voltage within a given I/O bank.

VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on

page 3-1 for further information.

5. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi

recommends that the user follow best design practices using Microsemi’s timing and power simulation tools.

6. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.

Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature ¹

Programming Program Retention

Maximum Storage

Maximum Operating Junction

Temperature T_J(°C) ²

Product Grade

Commercial

Industrial

Cycles

(biased/unbiased) Temperature T_STG(°C) ²

500

20 years

110

100

500

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating

conditions and absolute limits.

2-2

Revision 13

ProASIC3E Flash Family FPGAs

Table 2-4 • Overshoot and Undershoot Limits ¹

Average VCCI–GND Overshoot or

Undershoot Duration

Maximum Overshoot/

Undershoot²

VCCI and VMV

as a Percentage of Clock Cycle²

2.7 V or less

10%

1.4 V

1.49 V

1.1 V

3 V

10%

1.19 V

0.79 V

0.88 V

0.45 V

0.54 V

3.3 V

3.6 V

Notes:

10%

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the

maximum overshoot/undershoot has to be reduced by 0.15 V.

3. This table does not provide PCI overshoot/undershoot limits.

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every ProASIC^®3E device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1

on page 2-4.

There are five regions to consider during power-up.

ProASIC3E I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

•

During programming, I/Os become tristated and weakly pulled up to VCCI.

JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

Revision 13

2-3

ProASIC3E DC and Switching Characteristics

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper

power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLXL exceed

brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on

page 2-4 for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25

V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down

Behavior of Low Power Flash Devices" chapter of the ProASIC3E FPGA Fabric User’s Guide for

information on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input buffer activation

VCC = VCCI + VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCC

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

buffers are ON.

I/Os are functional

Region 1: I/O Buffers are OFF

I/Os meet the entire datasheet

(except differential

and timer specifications for

speed, VIH / VIL, VOH / VOL,

etc.

but slower because VCCI

is below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

VCC = 1.425 V

Region 2: I/O buffers are ON.

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

I/Os are functional (except differential inputs)

but slower because VCCI / VCC are below

specification. For the same reason, input

buffers do not meet VIH / VIL levels, and

output buffers do not meet VOH / VOL levels.

Activation trip point:

= 0.85 V ± 0.25 V

Deactivation trip point:

= 0.75 V ± 0.25 V

Region 1: I/O buffers are OFF

VCCI

Activation trip point:

= 0.9 V ± 0.3 V

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

Deactivation trip point:

= 0.8 V ± 0.3 V

Figure 2-1 • I/O State as a Function of VCCI and VCC Voltage Levels

2-4

Revision 13

ProASIC3E Flash Family FPGAs

Thermal Characteristics

Introduction

The temperature variable in Designer software refers to the junction temperature, not the ambient

temperature. This is an important distinction because dynamic and static power consumption cause the

chip junction to be higher than the ambient temperature.

EQ 1 can be used to calculate junction temperature.

T_J= Junction Temperature = T + T_A

EQ 1

where:

T_A= Ambient Temperature

T = Temperature gradient between junction (silicon) and ambient T = _ja* P

_ja= Junction-to-ambient of the package. _janumbers are located in Table 2-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is _jcand the junction-to-ambient air thermal resistivity is

_ja. The thermal characteristics for _jaare shown for two air flow rates. The absolute maximum junction

temperature is 110°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation

allowed for an 896-pin FBGA package at commercial temperature and in still air.

Max. junction temp. (C) – Max. ambient temp. (C) 110C – 70C

Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------- = ---------------------------------- = 5.88 W

_ja(C/W)

13.6C/W

EQ 2

Table 2-5 • Package Thermal Resistivities

_ja

Package Type

Pin Count

_jc

8.0

3.8

Still Air

26.1

200 ft./min.

500 ft./min.

20.8

Units

Plastic Quad Flat Package (PQFP)

208

22.5

13.3

C/W

Plastic Quad Flat Package (PQFP) with

embedded heat spreader

16.2

11.9

Fine Pitch Ball Grid Array (FBGA)

256

484

676

896

3.8

3.2

2.4

26.9

20.5

16.4

13.6

22.8

17.0

13.0

10.4

21.5

15.9

12.0

9.4

C/W

Temperature and Voltage Derating Factors

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to T_J= 70°C, VCC = 1.425 V)

Junction Temperature (°C)

Array Voltage

VCC (V)

–40°C

0°C

0.92

0.88

0.85

25°C

0.95

0.90

0.87

70°C

1.00

0.95

0.92

85°C

1.02

0.97

0.93

100°C

1.425

0.87

1.04

0.98

0.95

1.500

0.83

1.575

0.80

Revision 13

2-5

ProASIC3E DC and Switching Characteristics

Calculating Power Dissipation

Quiescent Supply Current

Table 2-7 • Quiescent Supply Current Characteristics

A3PE600

A3PE1500

12 mA

A3PE3000

25 mA

Typical (25°C)

5 mA

30 mA

45 mA

Maximum (Commercial)

Maximum (Industrial)

Notes:

70 mA

150 mA

225 mA

105 mA

1. IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in

Table 2-8 and Table 2-9 on page 2-7.

2. –F speed grade devices may experience higher standby IDD of up to five times the standard IDD and higher I/O

leakage.

Power per I/O Pin

Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

VMV

(V)

Static Power

PDC2 (mW)¹

Dynamic Power

PAC9 (µW/MHz)²

Single-Ended

3.3 V LVTTL/LVCMOS

3.3 V LVTTL/LVCMOS – Schmitt trigger

3.3 V LVTTL/LVCMOS Wide Range³

3.3 V LVTTL/LVCMOS Wide Range – Schmitt trigger³

2.5 V LVCMOS

3.3

2.5

1.8

1.5

3.3

–

17.39

25.51

16.34

24.49

5.76

2.5 V LVCMOS – Schmitt trigger

1.8 V LVCMOS

7.16

2.72

1.8 V LVCMOS – Schmitt trigger

1.5 V LVCMOS (JESD8-11)

1.5 V LVCMOS (JESD8-11) – Schmitt trigger

3.3 V PCI

2.80

2.08

2.00

18.82

20.12

18.82

20.12

3.3 V PCI – Schmitt trigger

3.3 V PCI-X

3.3 V PCI-X – Schmitt trigger

Voltage-Referenced

3.3 V GTL

3.3

2.5

3.3

2.5

2.90

2.13

2.81

2.57

8.23

4.78

4.14

3.71

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

Notes:

1. PDC2 is the static power (where applicable) measured on VMV.

2. PAC9 is the total dynamic power measured on VCC and VMV.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.

2-6

Revision 13

ProASIC3E Flash Family FPGAs

Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings (continued)

VMV

(V)

Static Power

PDC2 (mW)¹

Dynamic Power

PAC9 (µW/MHz)²

HSTL (I)

1.5

2.5

3.3

0.17

1.38

3.21

2.03

4.48

9.26

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Differential

LVDS/B-LVDS/M-LVDS

LVPECL

2.5

3.3

2.26

5.71

1.50

2.17

Notes:

1. PDC2 is the static power (where applicable) measured on VMV.

2. PAC9 is the total dynamic power measured on VCC and VMV.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.

Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings

C_LOAD

(pF)

VCCI

(V)

Static Power

PDC3 (mW)²

Dynamic Power

PAC10 (µW/MHz)³

Single-Ended

3.3 V LVTTL/LVCMOS

3.3 V LVTTL/LVCMOS Wide Range⁴

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

3.3 V PCI

3.3

2.5

1.8

1.5

3.3

–

474.70

270.73

151.78

104.55

204.61

3.3 V PCI-X

Voltage-Referenced

3.3 V GTL

3.3

2.5

3.3

2.5

1.5

2.5

–

24.08

13.52

24.10

13.54

26.22

27.22

105.56

116.60

2.5 V GTL

3.3 V GTL+

–

2.5 V GTL+

–

HSTL (I)

7.08

13.88

16.69

25.91

HSTL (II)

SSTL2 (I)

SSTL2 (II)

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC3 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCC and VCCI.

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

Revision 13

2-7

ProASIC3E DC and Switching Characteristics

Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings (continued)

C_LOAD

(pF)

VCCI

(V)

Static Power

PDC3 (mW)²

Dynamic Power

PAC10 (µW/MHz)³

SSTL3 (I)

3.3

26.02

42.21

114.87

131.76

SSTL3 (II)

Differential

LVDS/B-LVDS/M-LVDS

LVPECL

–

2.5

3.3

7.70

89.62

19.42

168.02

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC3 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCC and VCCI.

4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

Power Consumption of Various Internal Resources

Table 2-10 • Different Components Contributing to the Dynamic Power Consumption in ProASIC3E Devices

Device-Specific Dynamic Contributions

(µW/MHz)

Parameter

PAC1

Definition

Clock contribution of a Global Rib

Clock contribution of a Global Spine

Clock contribution of a VersaTile row

A3PE600

12.77

A3PE1500

16.21

3.06

A3PE3000

19.7

PAC2

1.85

4.16

PAC3

0.88

PAC4

Clock contribution of a VersaTile used as a sequential

module

0.12

PAC5

PAC6

PAC7

First contribution of a VersaTile used as a sequential

module

0.07

0.29

0.70

Second contribution of a VersaTile used as a sequential

module

Contribution of a VersaTile used as a combinatorial

module

PAC8

Average contribution of a routing net

PAC9

Contribution of an I/O input pin (standard-dependent)

Contribution of an I/O output pin (standard-dependent)

See Table 2-8 on page 2-6.

See Table 2-9 on page 2-7

25.00

PAC10

PAC11

Average contribution of a RAM block during a read

operation

PAC12

Average contribution of a RAM block during a write

operation

30.00

PAC13

PAC14

Static PLL contribution

2.55 mW

2.60

Dynamic contribution for PLL

Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power

calculator or SmartPower in Libero SoC.

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Revision 13

ProASIC3E Flash Family FPGAs

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in the Libero SoC software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs as well as the number and the frequency of each output clock generated

The number of combinatorial and sequential cells used in the design

The internal clock frequencies

The number and the standard of I/O pins used in the design

The number of RAM blocks used in the design

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-11 on

page 2-11.

•

Enable rates of output buffers—guidelines are provided for typical applications in Table 2-12 on

page 2-11.

Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-12 on page 2-11. The calculation should be repeated for each clock domain defined in the

design.

Methodology

Total Power Consumption—P

TOTAL

P_TOTAL= P_STAT+ P_DYN

P_STATis the total static power consumption.

_DYNis the total dynamic power consumption.

Total Static Power Consumption—P

STAT

P_STAT= PDC1 + N_INPUTS* PDC2 + N_OUTPUTS* PDC3

N_INPUTSis the number of I/O input buffers used in the design.

N_OUTPUTSis the number of I/O output buffers used in the design.

Total Dynamic Power Consumption—P

DYN

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL

Global Clock Contribution—P

CLOCK

P_CLOCK= (PAC1 + N_SPINE* PAC2 + N_ROW* PAC3 + N_S-CELL* PAC4) * F_CLK

N_SPINEis the number of global spines used in the user design—guidelines are provided in the

"Spine Architecture" section of the Global Resources chapter in the ProASIC3E FPGA Fabric

User's Guide.

N_ROWis the number of VersaTile rows used in the design—guidelines are provided in the

"Spine Architecture" section of the Global Resources chapter in the ProASIC3E FPGA Fabric

User's Guide.

_CLKis the global clock signal frequency.

_S-CELLis the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—P

S-CELL

P_S-CELL= N_S-CELL* (PAC5 + ₁/ 2 * PAC6) * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design. When a

multi-tile sequential cell is used, it should be accounted for as 1.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on

page 2-11.

_CLKis the global clock signal frequency.

Revision 13

2-9

ProASIC3E DC and Switching Characteristics

Combinatorial Cells Contribution—P

C-CELL

P_C-CELL= N_C-CELL* ₁/ 2 * PAC7 * F_CLK

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on

page 2-11.

_CLKis the global clock signal frequency.

Routing Net Contribution—P

NET

P_NET= (N_S-CELL+ N_C-CELL) * ₁/ 2 * PAC8 * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design.

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on

page 2-11.

_CLKis the global clock signal frequency.

I/O Input Buffer Contribution—P

INPUTS

P_INPUTS= N_INPUTS* ₂/ 2 * PAC9 * F_CLK

N_INPUTSis the number of I/O input buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 2-11 on page 2-11.

_CLKis the global clock signal frequency.

I/O Output Buffer Contribution—P

OUTPUTS

P_OUTPUTS= N_OUTPUTS* ₂/ 2 * ₁* PAC10 * F_CLK

N_OUTPUTSis the number of I/O output buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 2-11 on page 2-11.

₁is the I/O buffer enable rate—guidelines are provided in Table 2-12 on page 2-11.

_CLKis the global clock signal frequency.

RAM Contribution—P

MEMORY

P_MEMORY= PAC11 * N_BLOCKS* F_READ-CLOCK* ₂+ PAC12 * N_BLOCK* F_WRITE-CLOCK* ₃

N_BLOCKSis the number of RAM blocks used in the design.

_READ-CLOCKis the memory read clock frequency.

₂is the RAM enable rate for read operations—guidelines are provided in Table 2-12 on

page 2-11.

_WRITE-CLOCKis the memory write clock frequency.

₃is the RAM enable rate for write operations—guidelines are provided in Table 2-12 on

page 2-11.

PLL Contribution—P

PLL

P_PLL= PAC13 + PAC14 * F_CLKOUT

F_CLKOUTis the output clock frequency.¹

1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the

PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output

clock in the formula by adding its corresponding contribution (PAC14 * F_CLKOUTproduct) to the total PLL contribution.

2-10

Revision 13

ProASIC3E Flash Family FPGAs

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are

some examples:

•

The average toggle rate of a shift register is 100% as all flip-flop outputs toggle at half of the clock

frequency.

•

The average toggle rate of an 8-bit counter is 25%:

–

Bit 0 (LSB) = 100%

Bit 1

Bit 2

…

= 50%

= 25%

Bit 7 (MSB) = 0.78125%

Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When

nontristate output buffers are used, the enable rate should be 100%.

Table 2-11 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Toggle rate of VersaTile outputs

I/O buffer toggle rate

Guideline

10%

₁

₂

10%

Table 2-12 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

I/O output buffer enable rate

Guideline

100%

₁

₂

₃

RAM enable rate for read operations

RAM enable rate for write operations

12.5%

Revision 13

2-11

ProASIC3E DC and Switching Characteristics

User I/O Characteristics

Timing Model

I/O Module

(Non-Registered)

Combinational Cell

LVPECL

t_PD= 0.56 ns

_PD= 0.49 ns

t_DP= 1.36 ns

I/O Module

(Non-Registered)

Combinational Cell

LVTTL/LVCMOS

Output drive strength = 12 mA

High slew rate

t_DP= 2.74 ns

t_PD= 0.87 ns

I/O Module

(Non-Registered)

Combinational Cell

I/O Module

(Registered)

LVTTL/LVCMOS

Output drive strength = 24 mA

High slew rate

t_DP= 2.39 ns

_PY= 1.22 ns

t_PD= 0.51 ns

LVPECL

I/O Module

(Non-Registered)

Combinational Cell

LVCMOS 1.5V

Output drive strength = 12 mA

High slew

_ICLKQ= 0.24 ns

_ISUD= 0.26 ns

_DP= 3.30 ns

_PD= 0.47 ns

Input LVTTL/LVCMOS

Clock

I/O Module

(Registered)

Combinational Cell

t_PY= 0.90 ns

GTL+ 3.3V

_DP= 1.53 ns

I/O Module

(Non-Registered)

t_PD= 0.47 ns

_CLKQ= 0.55 ns

_SUD= 0.43 ns

_CLKQ= 0.55 ns

_CLKQ= 0.59 ns

LVDS,

BLVDS,

M-LVDS

t_SUD= 0.43 ns

t_SUD= 0.31 ns

Input LVTTL/LVCMOS

Clock

Input LVTTL/LVCMOS

Clock

t_PY= 1.36 ns

_PY= 0.90 ns

t_PY= 0.90 ns

Figure 2-2 • Timing Model

Operating Conditions: –2 Speed, Commercial Temperature Range (T_J= 70°C), Worst-Case

VCC = 1.425 V

2-12

Revision 13

ProASIC3E Flash Family FPGAs

t_PY

t_DIN

PAD

DIN

CLK

To Array

I/O Interface

t_PY= MAX(t_PY(R), t_PY(F))

t_DIN= MAX(t_DIN(R), t_DIN(F))

VIH

Vtrip

VCC

PAD

VIL

50%

t_PY

(F)

GND

(R)

t_PYS

(F)

t_PYS

(R)

VCC

50%

DIN

t_DIN

(R)

GND

t_DIN

(F)

Figure 2-3 • Input Buffer Timing Model and Delays (example)

Revision 13

2-13

ProASIC3E DC and Switching Characteristics

t_DOUT

D Q

t_DP

PAD

DOUT

CLK

Std

Load

From Array

t_DP= MAX(t_DP(R), t_DP(F))

t_DOUT= MAX(t_DOUT(R), t_DOUT(F))

I/O Interface

t_DOUT

(R)

t_DOUT

(F)

VCC

50%

VCC

0 V

50%

DOUT

PAD

0 V

VOH

Vtrip

V_OL

Vtrip

t_DP

(R)

t_DP

(F)

Figure 2-4 • Output Buffer Model and Delays (example)

2-14

Revision 13

ProASIC3E Flash Family FPGAs

EOUT

CLK

, t , t , t , t , t

ZL ZH HZ LZ ZLS ZHS

EOUT

PAD

DOUT

CLK

= MAX(t

(r), t (f))

EOUT

I/O Interface

EOUT

VCC

50%

EOUT (F)

EOUT (R)

VCC

50%

EOUT

PAD

VCCI

90% VCCI

Vtrip

VOL

10% V

CCI

VCC

50%

EOUT (F)

EOUT (R)

VCC

50%

EOUT

PAD

50%

VOH

ZHS

ZLS

Vtrip

VOL

Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)

Revision 13

2-15

ProASIC3E DC and Switching Characteristics

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-13 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions

IOL³IOH³

Equivalent

Software

Default

VIL

VIH

VOL

VOH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Slew

Rate

I/O Standard Strength Option¹

mA mA

3.3 V LVTTL / 12 mA

3.3 V

LVCMOS

12 mA High –0.3

0.8

3.6

0.4

2.4

12 12

3.3 V

100 µA

0.8

0.7

0.2

VCCI – 0.2 0.1 0.1

LVCMOS

Wide Range

2.5 V

LVCMOS

12 mA

1.7

0.7

1.7

12 12

1.8 V

LVCMOS

12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6

0.45

VCCI – 0.45 12 12

1.5 V

12 mA High –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12

LVCMOS

3.3 V PCI

3.3 V PCI-X

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

Per PCI Specification

Per PCI-X Specification

20 mA²

35 mA

33 mA

8 mA

20 mA²High –0.3 VREF – 0.05 VREF + 0.05 3.6

35 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6

33 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6

0.4

–

20 20

35 35

33 33

–

0.6

–

0.6

–

8 mA

High –0.3 VREF – 0.1 VREF + 0.1 3.6

0.4

VCCI – 0.4

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

15 mA²

15 mA

18 mA

14 mA

21 mA

15 mA²High –0.3 VREF – 0.1 VREF + 0.1 3.6

15 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6

18 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6

14 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6

21 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6

0.4

0.54

0.35

0.7

VCCI – 0.4 15 15

VCCI – 0.62 15 15

VCCI – 0.43 18 18

VCCI – 1.1 14 14

VCCI – 0.9 21 21

0.5

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. Output drive strength is below JEDEC specification.

3. Currents are measured at 85°C junction temperature.

4. Output Slew Rates can be extracted from IBIS Models, located at

http://www.microsemi.com/soc/download/ibis/default.aspx.

2-16

Revision 13

ProASIC3E Flash Family FPGAs

Table 2-14 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

Commercial¹

Industrial²

IIL³

µA

IIH⁴

µA

IIL³

µA

IIH⁴

µA

DC I/O Standards

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

3.3 V PCI-X

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

1. Commercial range (0°C < T < 70°C)

2. Industrial range (–40°C < T < 85°C)

3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN <

VIL.

4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI.

Input current is larger when operating outside recommended ranges.

Revision 13

2-17

ProASIC3E DC and Switching Characteristics

Summary of I/O Timing Characteristics – Default I/O Software

Settings

Table 2-15 • Summary of AC Measuring Points

Input Reference Voltage Board Termination Measuring Trip Point

Standard

3.3 LVTTL

LVCMOS

(VREF_TYP)

Voltage (VTT_REF)

(Vtrip)

3.3

–

1.4 V

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

–

1.4 V

1.2 V

0.90 V

0.75 V

0.285 * VCCI (RR)

0.615 * VCCI (FF))

3.3 V PCI-X

–

0.285 * VCCI (RR)

0.615 * VCCI (FF)

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

0.8 V

1.0 V

0.75 V

1.25 V

1.5 V

–

1.2 V

1.5 V

0.75 V

1.25 V

1.485 V

–

VREF

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS

VREF

Cross point

LVPECL

–

Table 2-16 • I/O AC Parameter Definitions

Parameter

Definition

Data to Pad delay through the Output Buffer

t_DP

t_PY

Pad to Data delay through the Input Buffer with Schmitt trigger disabled

Data to Output Buffer delay through the I/O interface

t_DOUT

t_EOUT

t_DIN

t_PYS

t_HZ

Enable to Output Buffer Tristate Control delay through the I/O interface

Input Buffer to Data delay through the I/O interface

Pad to Data delay through the Input Buffer with Schmitt trigger enabled

Enable to Pad delay through the Output Buffer—High to Z

t_ZH

Enable to Pad delay through the Output Buffer—Z to High

t_LZ

Enable to Pad delay through the Output Buffer—Low to Z

t_ZL

Enable to Pad delay through the Output Buffer—Z to Low

t_ZHS

t_ZLS

Enable to Pad delay through the Output Buffer with delayed enable—Z to High

Enable to Pad delay through the Output Buffer with delayed enable—Z to Low

2-18

Revision 13

ProASIC3E Flash Family FPGAs

Table 2-17 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V

Equivalent

Software

Drive

Default

Strength

Drive

(mA)

Strength

Option)¹

I/O Standard

3.3 V LVTTL /

3.3 V LVCMOS

High 35

–

0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81

0.49 4.24 0.03 1.36 1.78 0.32 4.24 3.25 3.78 4.17 6.77 5.79

3.3 V LVCMOS 100 µA

Wide Range²

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

3.3 V PCI

–

High 35

–

0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28

0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98

0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37

Per PCI

spec

High 10 25 ³0.49 2.09 0.03 0.78 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16

3.3 V PCI-X

Per PCI-X

spec

–

High 10 25³0.49 2.09 0.03 0.78 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16

3.3 V GTL

2.5 V GTL

3.3 V GTL+

2.5 V GTL+

HSTL (I)

20 ⁴

–

High 10

High 20

High 30

25 0.45 1.55 0.03 2.19

25 0.45 1.59 0.03 1.83

25 0.45 1.53 0.03 1.19

25 0.45 1.65 0.03 1.13

50 0.49 2.37 0.03 1.59

25 0.49 2.26 0.03 1.59

50 0.49 1.59 0.03 1.00

25 0.49 1.62 0.03 1.00

50 0.49 1.72 0.03 0.93

25 0.49 1.54 0.03 0.93

–

0.32 1.52 1.55

0.32 1.61 1.59

0.32 1.56 1.53

0.32 1.68 1.57

0.32 2.42 2.35

0.32 2.30 2.03

0.32 1.62 1.38

0.32 1.65 1.32

0.32 1.75 1.37

0.32 1.57 1.25

–

3.19 3.22

3.28 3.26

3.23 3.20

3.35 3.24

4.09 4.02

3.97 3.70

3.29 3.05

3.32 2.99

3.42 3.04

3.24 2.92

HSTL (II)

15 ⁴

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

LVDS/B-LVDS/

M-LVDS

High

–

0.49 1.40 0.03 1.36

–

LVPECL

–

High

–

0.49 1.36 0.03 1.22

–

Notes:

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3V wide range as specified in the JESD8b specification.

3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-11 on page 2-37 for

connectivity. This resistor is not required during normal operation.

4. Output drive strength is below JEDEC specification.

5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5..

Revision 13

2-19

ProASIC3E DC and Switching Characteristics

Detailed I/O DC Characteristics

Table 2-18 • Input Capacitance

Symbol

C_IN

Definition

Conditions

Min. Max. Units

Input capacitance

VIN = 0, f = 1.0 MHz

C_INCLK

Input capacitance on the clock pin

Table 2-19 • I/O Output Buffer Maximum Resistances¹

Standard

Drive Strength

4 mA

R_PULL-DOWN()²

R_PULL-UP()³

3.3 V LVTTL / 3.3 V LVCMOS

100

300

150

8 mA

12 mA

16 mA

24 mA

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

100 µA

Same as regular

3.3 V LVCMOS

Same as regular

3.3 V LVCMOS

4 mA

8 mA

12 mA

16 mA

24 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

4 mA

6 mA

8 mA

12 mA

100

200

100

1.8 V LVCMOS

200

100

225

112

1.5 V LVCMOS

3.3 V PCI/PCI-X

200

100

224

112

Per PCI/PCI-X

specification

3.3 V GTL

2.5 V GTL

Notes:

20 mA ⁴

–

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCI, drive strength selection, temperature, and process. For board design

considerations and detailed output buffer resistances, use the corresponding IBIS models located on the

Microsemi SoC Products Group website at www.microsemi.com/soc/techdocs/models/ibis.html.

= (VOLspec) / IOLspec

(PULL-DOWN-MAX)

= (VCCImax – VOHspec) / IOHspec

(PULL-UP-MAX)

4. Output drive strength is below JEDEC specification.

2-20

Revision 13

ProASIC3E Flash Family FPGAs

Table 2-19 • I/O Output Buffer Maximum Resistances¹(continued)

Standard

3.3 V GTL+

2.5 V GTL+

HSTL (I)

Drive Strength

35 mA

_PULL-DOWN()²

R_PULL-UP()³

–

33 mA

–

8 mA

HSTL (II)

SSTL2 (I)

SSTL2 (II)

SSTL3 (I)

SSTL3 (II)

Notes:

15 mA ⁴

15 mA

18 mA

14 mA

21 mA

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance

values depend on VCCI, drive strength selection, temperature, and process. For board design

considerations and detailed output buffer resistances, use the corresponding IBIS models located on the

Microsemi SoC Products Group website at www.microsemi.com/soc/techdocs/models/ibis.html.

= (VOLspec) / IOLspec

(PULL-DOWN-MAX)

= (VCCImax – VOHspec) / IOHspec

(PULL-UP-MAX)

4. Output drive strength is below JEDEC specification.

Table 2-20 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

R(_{(WEAK PULL-UP)}

R_{(WEAK PULL-DOWN)}

()

VCCI

Min.

Max.

45 k

Min.

10 k

Max.

45 k

3.3 V

10 k

3.3 V (Wide

Range I/Os)

2.5 V

1.8 V

1.5 V

Notes:

11 k

18 k

19 k

55 k

70 k

90 k

12 k

17 k

19 k

74 k

110 k

140 k

= (VCCImax – VOHspec) / I

(WEAK PULL-UP-MAX)

(WEAK PULL-UP-MIN)

(WEAK PULL-DOWN-MIN)

= (VOLspec) / I

(WEAK PULL-DOWN-MAX)

Revision 13

2-21

ProASIC3E DC and Switching Characteristics

Table 2-21 • I/O Short Currents IOSH/IOSL

Drive Strength

4 mA

IOSH (mA)*

IOSL (mA)*

3.3 V LVTTL / 3.3 V LVCMOS

8 mA

12 mA

103

132

268

109

127

181

16 mA

24 mA

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

100 µA

Same as regular

3.3 V LVCMOS

Same as regular

3.3 V LVCMOS

4 mA

8 mA

12 mA

16 mA

24 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

4 mA

6 mA

8 mA

12 mA

169

124

1.8 V LVCMOS

1.5 V LVCMOS

Notes:

1. T = 100°C

2. Applicable to 3.3 V LVCMOS Wide Range. IOSL/IOSH dependent on the I/O buffer drive strength

selected for wide range applications. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide

range as specified in the JESD8b specification.

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 100°C, the short current condition would have to be sustained for more than six months

to cause a reliability concern. The I/O design does not contain any short circuit protection, but such

protection would only be needed in extremely prolonged stress conditions.

Table 2-22 • Duration of Short Circuit Event Before Failure

Temperature

–40°C

0°C

Time before Failure

> 20 years

5 years

25°C

70°C

85°C

2 years

100°C

6 months

2-22

Revision 13

ProASIC3E Flash Family FPGAs

Table 2-23 • Schmitt Trigger Input Hysteresis

Hysteresis Voltage Value (typ.) for Schmitt Mode Input Buffers

Input Buffer Configuration

Hysteresis Value (typ.)

240 mV

3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)

2.5 V LVCMOS (Schmitt trigger mode)

1.8 V LVCMOS (Schmitt trigger mode)

1.5 V LVCMOS (Schmitt trigger mode)

140 mV

80 mV

60 mV

Table 2-24 • I/O Input Rise Time, Fall Time, and Related I/O Reliability*

Input Rise/Fall Time

Input Buffer

(min.)

Input Rise/Fall Time (max.)

10 ns *

Reliability

LVTTL/LVCMOS

(Schmitt trigger disabled)

No requirement

20 years

(110°C)

LVTTL/LVCMOS

(Schmitt trigger enabled)

No requirement No requirement, but input noise 20 years

voltage cannot exceed Schmitt (110°C)

hysteresis.

HSTL/SSTL/GTL

No requirement

10 ns *

10 years

(100°C)

LVDS/B-LVDS/M-LVDS/

LVPECL

No requirement

10 ns *

10 years

(100°C)

Note: *For clock signals and similar edge-generating signals, refer to the "ProASIC3/E SSO and Pin

Placement Guidelines" chapter of the ProASIC3E FPGA Fabric User’s Guide. The maximum input

rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the

rise time and fall time of input buffers can be increased beyond the maximum value. The longer the

rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends

signal integrity evaluation/characterization of the system to ensure that there is no excessive noise

coupling into input signals.

Revision 13

2-23

ProASIC3E DC and Switching Characteristics

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is

supported as part of the 3.3 V LVTTL support.

Table 2-25 • Minimum and Maximum DC Input and Output Levels

3.3 V LVTTL /

3.3 V LVCMOS

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSL

IOSH

IIL¹IIH²

Min.

Max.

Min.,

Max.

mA³

Max.

mA³

Drive Strength

4 mA

mA mA

µA⁴µA⁴

10 10

–0.3

0.8

3.6

0.4

2.4

8 mA

12 mA

12 12

16 16

24 24

109

127

181

103

132

268

16 mA

24 mA

Notes:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V< VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN< VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

35 pF

Enable Path

35 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

35 pF for t_HZ/ t_LZ

Figure 2-6 • AC Loading

Table 2-26 • 3.3 V LVTTL / 3.3 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

_LOAD(pF)

3.3

1.4

–

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

2-24

Revision 13

ProASIC3E Flash Family FPGAs

Timing Characteristics

Table 2-27 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Drive

Speed

Strength

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.66 7.88 0.04 1.20 1.57 0.43 8.03 6.70 2.69 2.59 10.26 8.94

0.56 6.71 0.04 1.02 1.33 0.36 6.83 5.70 2.29 2.20 8.73

0.49 5.89 0.03 0.90 1.17 0.32 6.00 5.01 2.01 1.93 7.67

0.66 5.08 0.04 1.20 1.57 0.43 5.17 4.14 3.05 3.21 7.41

0.56 4.32 0.04 1.02 1.33 0.36 4.40 3.52 2.59 2.73 6.30

0.49 3.79 0.03 0.90 1.17 0.32 3.86 3.09 2.28 2.40 5.53

0.66 3.67 0.04 1.20 1.57 0.43 3.74 2.87 3.28 3.61 5.97

0.56 3.12 0.04 1.02 1.33 0.36 3.18 2.44 2.79 3.07 5.08

0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46

0.66 3.46 0.04 1.20 1.57 0.43 3.53 2.61 3.33 3.72 5.76

0.56 2.95 0.04 1.02 1.33 0.36 3.00 2.22 2.83 3.17 4.90

0.49 2.59 0.03 0.90 1.17 0.32 2.63 1.95 2.49 2.78 4.30

0.66 3.21 0.04 1.20 1.57 0.43 3.27 2.16 3.39 4.13 5.50

0.56 2.73 0.04 1.02 1.33 0.36 2.78 1.83 2.88 3.51 4.68

0.49 2.39 0.03 0.90 1.17 0.32 2.44 1.61 2.53 3.08 4.11

7.60

6.67

6.38

5.43

4.76

5.11

4.34

3.81

4.84

4.12

3.62

4.39

3.74

3.28

–2

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Notes:

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-28 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DINt_PYt_PYSt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.66 11.01 0.04 1.20 1.57 0.43 11.21 9.05 2.69 2.44 13.45 11.29

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

9.36 0.04 1.02 1.33 0.36

8.22 0.03 0.90 1.17 0.32

7.86 0.04 1.20 1.57 0.43

6.69 0.04 1.02 1.33 0.36

5.87 0.03 0.90 1.17 0.32

6.03 0.04 1.20 1.57 0.43

5.13 0.04 1.02 1.33 0.36

4.50 0.03 0.90 1.17 0.32

5.62 0.04 1.20 1.57 0.43

4.78 0.04 1.02 1.33 0.36

4.20 0.03 0.90 1.17 0.32

5.24 0.04 1.20 1.57 0.43

4.46 0.04 1.02 1.33 0.36

3.92 0.03 0.90 1.17 0.32

9.54

8.37

8.01

6.81

5.98

6.14

5.22

4.58

5.72

4.87

4.27

5.34

4.54

3.99

7.70 2.29 2.08 11.44 9.60

6.76 2.01 1.82 10.04 8.43

6.44 3.04 3.06 10.24 8.68

–2

8 mA

Std.

–1

5.48 2.58 2.61 8.71

4.81 2.27 2.29 7.65

5.02 3.28 3.47 8.37

4.27 2.79 2.95 7.12

3.75 2.45 2.59 6.25

4.72 3.32 3.58 7.96

4.02 2.83 3.04 6.77

3.53 2.48 2.67 5.94

4.69 3.39 3.96 7.58

3.99 2.88 3.37 6.44

3.50 2.53 2.96 5.66

7.38

6.48

7.26

6.17

5.42

6.96

5.92

5.20

6.93

5.89

5.17

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Revision 13

2-25

ProASIC3E DC and Switching Characteristics

3.3 V LVCMOS Wide Range

Table 2-29 • Minimum and Maximum DC Input and Output Levels

3.3 V

LVCMOS

Wide

Range

Equivalent

Software

Default

Drive

VIL

VIH

Max.

VOL

VOH

IOL IOH IOSL

IOSH IIL²IIH³

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

Strength Option¹

µA µA mA⁴

mA⁴µA⁵µA⁵

100 µA

Notes:

2 mA

4 mA

–0.3

0.8

3.6

0.2 VDD – 0.2 100 100

10 10

6 mA

8 mA

12 mA

16 mA

24 mA

0.2 VDD – 0.2 100 100 109

0.2 VDD – 0.2 100 100 127

0.2 VDD – 0.2 100 100 181

103

132

268

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN< VCCI. Input current is

larger when operating outside recommended ranges.

4. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

5. Currents are measured at 85°C junction temperature.

6. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

35 pF

Enable Path

35 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

35 pF for t_HZ/ t_LZ

Figure 2-7 • AC Loading

Table 2-30 • 3.3 V LVCMOS Wide Range AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

_LOAD(pF)

3.3

1.4

–

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

2-26

Revision 13

ProASIC3E Flash Family FPGAs

Timing Characteristics

Table 2-31 • 3.3 V LVCMOS Wide Range High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Equivalent

Software

Default

Drive

Strength

Speed

Strength Option¹

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZt_HZt_ZLSt_ZHSUnits

100 µA

Notes:

4 mA

8 mA

Std. 0.66 12.19 0.04 1.83 2.38 0.43 12.19 10.17 4.16 4.00 15.58 13.57 ns

–1

–2

0.56 10.37 0.04 1.55 2.02 0.36 10.37 8.66 3.54 3.41 13.26 11.54 ns

0.49 9.10 0.03 1.36 1.78 0.32 9.10 7.60 3.11 2.99 11.64 10.13 ns

Std. 0.66 7.85 0.04 1.83 2.38 0.43 7.85 6.29 4.71 4.97 11.24 9.68

–1

–2

0.56 6.68 0.04 1.55 2.02 0.36 6.68 5.35 4.01 4.22 9.57 8.24

0.49 5.86 0.03 1.36 1.78 0.32 5.86 4.70 3.52 3.71 8.40 7.23

12 mA

16 mA

24 mA

Std. 0.66 5.67 0.04 1.83 2.38 0.43 5.67 4.36 5.06 5.59 9.07 7.75

–1

–2

0.56 4.82 0.04 1.55 2.02 0.36 4.82 3.71 4.31 4.75 7.71 6.59

0.49 4.24 0.03 1.36 1.78 0.32 4.24 3.25 3.78 4.17 6.77 5.79

Std. 0.66 5.35 0.04 1.83 2.38 0.43 5.35 3.96 5.15 5.76 8.75 7.35

–1

–2

0.56 4.55 0.04 1.55 2.02 0.36 4.55 3.36 4.38 4.90 7.44 6.25

0.49 4.00 0.03 1.36 1.78 0.32 4.00 2.95 3.85 4.30 6.53 5.49

Std. 0.66 4.96 0.04 1.83 2.38 0.43 4.96 3.27 5.23 6.38 8.35 6.67

–1

–2

0.56 4.22 0.04 1.55 2.02 0.36 4.22 2.78 4.45 5.43 7.11 5.67

0.49 3.70 0.03 1.36 1.78 0.32 3.70 2.44 3.91 4.76 6.24 4.98

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. Software default selection highlighted in gray.

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Revision 13

2-27

ProASIC3E DC and Switching Characteristics

Table 2-32 • 3.3 V LVCMOS Wide Range Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Equivalent

Software

Default

Drive

Strength

Speed

Strength Option¹

Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZL

t_ZHt_LZt_HZt_ZLSt_ZHSUnits

100 µA

100µA

100 µA

Notes:

4 mA

8 mA

Std. 0.66 17.02 0.04 1.83 2.38 0.43 17.02 13.74 4.16 3.78 20.42 17.14 ns

–1

–2

0.56 14.48 0.04 1.55 2.02 0.36 14.48 11.69 3.54 3.21 17.37 14.58 ns

0.49 12.71 0.03 1.36 1.78 0.32 12.71 10.26 3.11 2.82 15.25 12.80 ns

Std. 0.66 12.16 0.04 1.83 2.38 0.43 12.16 9.78 4.70 4.74 15.55 13.17 ns

–1

–2

0.56 10.34 0.04 1.55 2.02 0.36 10.34 8.32 4.00 4.03 13.23 11.20 ns

0.49 9.08 0.03 1.36 1.78 0.32 9.08 7.30 3.51 3.54 11.61 9.84 ns

12 mA

16 mA

24 mA

Std. 0.66 9.32 0.04 1.83 2.38 0.43 9.32 7.62 5.06 5.36 12.71 11.02 ns

–1

–2

0.56 7.93 0.04 1.55 2.02 0.36 7.93 6.48 4.31 4.56 10.81 9.37

0.49 6.96 0.03 1.36 1.78 0.32 6.96 5.69 3.78 4.00 9.49 8.23

Std. 0.66 8.69 0.04 1.83 2.38 0.43 8.69 7.17 5.14 5.53 12.08 10.57 ns

–1

–2

0.56 7.39 0.04 1.55 2.02 0.36 7.39 6.10 4.37 4.71 10.28 8.99

0.49 6.49 0.03 1.36 1.78 0.32 6.49 5.36 3.83 4.13 9.02 7.89

Std. 0.66 8.11 0.04 1.83 2.38 0.43 8.11 7.13 5.23 6.13 11.50 10.52 ns

–1

–2

0.56 6.90 0.04 1.55 2.02 0.36 6.90 6.06 4.45 5.21 9.78 8.95

0.49 6.05 0.03 1.36 1.78 0.32 6.05 5.32 3.91 4.57 8.59 7.86

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. Software default selection highlighted in gray.

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

2-28

Revision 13

ProASIC3E Flash Family FPGAs

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications.

Table 2-33 • Minimum and Maximum DC Input and Output Levels

2.5 V

LVCMOS

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSL

IOSH

IIL¹IIH²

Drive

Strength

Min.

Max.

Min.

Max.

Max.,

Max.

mA³

Max.

mA³

mA mA

µA⁴µA⁴

10 10

4 mA

–0.3

0.7

1.7

3.6

0.7

1.7

8 mA

12 mA

16 mA

24 mA

Notes:

12 12

16 16

24 24

124

169

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

35 pF

Enable Path

35 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

35 pF for t_HZ/ t_LZ

Figure 2-8 • AC Loading

Table 2-34 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

_LOAD(pF)

2.5

1.2

–

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Revision 13

2-29

ProASIC3E DC and Switching Characteristics

Timing Characteristics

Table 2-35 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Speed

Strength Grade t_DOUTt_ZHSUnits

Drive

t_DP

t_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4 mA

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.82 0.04 1.51 1.66 0.43 8.13 8.82 2.72 2.29 10.37 11.05

7.50 0.04 1.29 1.41 0.36 6.92 7.50 2.31 1.95 8.82

6.58 0.03 1.13 1.24 0.32 6.07 6.58 2.03 1.71 7.74

5.27 0.04 1.51 1.66 0.43 5.27 5.27 3.10 3.03 7.50

4.48 0.04 1.29 1.41 0.36 4.48 4.48 2.64 2.58 6.38

3.94 0.03 1.13 1.24 0.32 3.93 3.94 2.32 2.26 5.60

3.74 0.04 1.51 1.66 0.43 3.81 3.49 3.37 3.49 6.05

3.18 0.04 1.29 1.41 0.36 3.24 2.97 2.86 2.97 5.15

2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52

3.53 0.04 1.51 1.66 0.43 3.59 3.12 3.42 3.62 5.83

3.00 0.04 1.29 1.41 0.36 3.06 2.65 2.91 3.08 4.96

2.63 0.03 1.13 1.24 0.32 2.68 2.33 2.56 2.71 4.35

3.26 0.04 1.51 1.66 0.43 3.32 2.48 3.49 4.11 5.56

2.77 0.04 1.29 1.41 0.36 2.83 2.11 2.97 3.49 4.73

2.44 0.03 1.13 1.24 0.32 2.48 1.85 2.61 3.07 4.15

9.40

8.25

7.51

6.38

5.61

5.73

4.87

4.28

5.35

4.55

4.00

4.72

4.01

3.52

–2

8 mA

Std.

–1

–2

12 mA

16 mA

24 mA

Notes:

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

2-30

Revision 13

ProASIC3E Flash Family FPGAs

Table 2-36 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DINt_PYt_PYSt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

4 mA

Std.

–1

0.66 12.00 0.04 1.51 1.66 0.43 12.23 11.61 2.72 2.20 14.46 13.85

0.56 10.21 0.04 1.29 1.41 0.36 10.40 9.88 2.31 1.87 12.30 11.78

–2

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.96 0.03 1.13 1.24 0.32

8.73 0.04 1.51 1.66 0.43

7.43 0.04 1.29 1.41 0.36

6.52 0.03 1.13 1.24 0.32

6.77 0.04 1.51 1.66 0.43

5.76 0.04 1.29 1.41 0.36

5.06 0.03 1.13 1.24 0.32

6.31 0.04 1.51 1.66 0.43

5.37 0.04 1.29 1.41 0.36

4.71 0.03 1.13 1.24 0.32

5.93 0.04 1.51 1.66 0.43

5.05 0.04 1.29 1.41 0.36

4.43 0.03 1.13 1.24 0.32

9.13

8.89

7.57

6.64

6.90

5.87

5.15

6.42

5.46

4.80

6.04

5.14

4.51

8.67 2.03 1.64 10.80 10.34

8.01 3.10 2.93 11.13 10.25

8 mA

Std.

–1

6.82 2.64 2.49 9.47

5.98 2.32 2.19 8.31

6.11 3.37 3.39 9.14

5.20 2.86 2.89 7.77

4.56 2.51 2.53 6.82

5.73 3.42 3.52 8.66

4.87 2.91 3.00 7.37

4.28 2.56 2.63 6.47

5.70 3.49 4.00 8.28

4.85 2.97 3.40 7.04

4.26 2.61 2.99 6.18

8.72

7.65

8.34

7.10

6.23

7.96

6.77

5.95

7.94

6.75

5.93

–2

12 mA

16 mA

24 mA

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Revision 13

2-31

ProASIC3E DC and Switching Characteristics

1.8 V LVCMOS

Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-37 • Minimum and Maximum DC Input and Output Levels

1.8 V

LVCMOS

VIL

VIH

VOL

VOH

IOL IOH

mA mA

IOSL

IOSH

IIL¹IIH²

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA³

Max.

mA³

µA⁴µA⁴

10 10

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI

3.6

0.45 VCCI – 0.45

4 mA

6 mA

–0.3 0.35 * VCCI 0.65 * VCCI 3.6

8 mA

–0.3 0.35 * VCCI 0.65 * VCCI

3.6

12 mA

16 mA

Notes:

0.45 VCCI – 0.45 12 12

0.45 VCCI – 0.45 16 16

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

35 pF

Enable Path

35 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

35 pF for t_HZ/ t_LZ

Figure 2-9 • AC Loading

Table 2-38 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

_LOAD(pF)

1.8

0.9

–

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

2-32

Revision 13

ProASIC3E Flash Family FPGAs

Timing Characteristics

Table 2-39 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DINt_PYt_PYSt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

Std.

–1

0.66 12.10 0.04 1.45 1.91 0.43

0.56 10.30 0.04 1.23 1.62 0.36

9.59 12.10 2.78 1.64 11.83 14.34

8.16 10.30 2.37 1.39 10.06 12.20

–2

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

9.04 0.03 1.08 1.42 0.32

7.05 0.04 1.45 1.91 0.43

6.00 0.04 1.23 1.62 0.36

5.27 0.03 1.08 1.42 0.32

4.52 0.04 1.45 1.91 0.43

3.85 0.04 1.23 1.62 0.36

3.38 0.03 1.08 1.42 0.32

4.12 0.04 1.45 1.91 0.43

3.51 0.04 1.23 1.62 0.36

3.08 0.03 1.08 1.42 0.32

3.80 0.04 1.45 1.91 0.43

3.23 0.04 1.23 1.62 0.36

2.83 0.03 1.08 1.42 0.32

3.80 0.04 1.45 1.91 0.43

3.23 0.04 1.23 1.62 0.36

2.83 0.03 1.08 1.42 0.32

7.16

6.20

5.28

4.63

4.47

3.80

3.33

4.20

3.57

3.14

3.87

3.29

2.89

3.87

3.29

2.89

9.04 2.08 1.22 8.83 10.71

4 mA

Std.

–1

7.05 3.25 2.86 8.44

6.00 2.76 2.44 7.18

5.27 2.43 2.14 6.30

4.52 3.57 3.47 6.70

3.85 3.04 2.95 5.70

3.38 2.66 2.59 5.00

3.99 3.63 3.62 6.43

3.40 3.09 3.08 5.47

2.98 2.71 2.71 4.81

3.09 3.73 4.24 6.10

2.63 3.18 3.60 5.19

2.31 2.79 3.16 4.56

3.09 3.73 4.24 6.10

2.63 3.18 3.60 5.19

2.31 2.79 3.16 4.56

9.29

7.90

6.94

6.76

5.75

5.05

6.23

5.30

4.65

5.32

4.53

3.98

5.32

4.53

3.98

–2

6 mA

Std.

–1

–2

8 mA

Std.

–1

–2

12 mA

16 mA

Notes:

Std.

–1

–2

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Revision 13

2-33

ProASIC3E DC and Switching Characteristics

Table 2-40 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Speed

Strength Grade t_DOUTt_ZHSUnits

Drive

t_DP

t_DINt_PYt_PYSt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

Std.

–1

0.66 15.84 0.04 1.45 1.91 0.43 15.65 15.84 2.78 1.58 17.89 18.07

0.56 13.47 0.04 1.23 1.62 0.36 13.31 13.47 2.37 1.35 15.22 15.37

0.49 11.83 0.03 1.08 1.42 0.32 11.69 11.83 2.08 1.18 13.36 13.50

0.66 11.39 0.04 1.45 1.91 0.43 11.60 10.76 3.26 2.77 13.84 12.99

–2

Std.

–1

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

9.69 0.04 1.23 1.62 0.36

8.51 0.03 1.08 1.42 0.32

8.97 0.04 1.45 1.91 0.43

7.63 0.04 1.23 1.62 0.36

6.70 0.03 1.08 1.42 0.32

8.35 0.04 1.45 1.91 0.43

7.10 0.04 1.23 1.62 0.36

6.24 0.03 1.08 1.42 0.32

7.94 0.04 1.45 1.91 0.43

6.75 0.04 1.23 1.62 0.36

5.93 0.03 1.08 1.42 0.32

7.94 0.04 1.45 1.91 0.43

6.75 0.04 1.23 1.62 0.36

5.93 0.03 1.08 1.42 0.32

9.87

8.66

9.14

7.77

6.82

8.50

7.23

6.35

8.09

6.88

6.04

8.09

6.88

6.04

9.15 2.77 2.36 11.77 11.05

8.03 2.43 2.07 10.33 9.70

8.10 3.57 3.36 11.37 10.33

–2

Std.

–1

6.89 3.04 2.86 9.67

6.05 2.66 2.51 8.49

8.79

7.72

–2

Std.

–1

7.59 3.64 3.52 10.74 9.82

6.45 3.10 3.00 9.14

5.66 2.72 2.63 8.02

8.35

7.33

–2

Std.

–1

7.56 3.74 4.11 10.32 9.80

6.43 3.18 3.49 8.78

5.65 2.79 3.07 7.71

8.33

7.32

–2

Std.

–1

7.56 3.74 4.11 10.32 9.80

6.43 3.18 3.49 8.78

5.65 2.79 3.07 7.71

8.33

7.32

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

2-34

Revision 13

ProASIC3E Flash Family FPGAs

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-41 • Minimum and Maximum DC Input and Output Levels

1.5 V

LVCMOS

VIL

VIH

VOL

VOH

IOL IOH IOSL IOSH IIL¹IIH²

Max. Max.

Drive

Strength

Min.

Max.

Min.

Max.

Min.

mA mA mA³

mA³µA⁴µA⁴

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

–0.3 0.30 * VCCI 0.7 * VCCI 3.6

0.25 * VCCI 0.75 * VCCI

10 10

0.25 * VCCI 0.75 * VCCI 12 12

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V< VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

35 pF

Enable Path

35 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

35 pF for t_HZ/ t_LZ

Figure 2-10 • AC Loading

Table 2-42 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

_LOAD(pF)

1.5

0.75

–

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Revision 13

2-35

ProASIC3E DC and Switching Characteristics

Timing Characteristics

Table 2-43 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Speed

Strength Grade t_DOUTt_ZHSUnits

Drive

t_DP

t_DINt_PYt_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

2 mA

4 mA

6 mA

8 mA

12 mA

Notes:

Std.

–1

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

0.66

0.56

0.49

8.53 0.04 1.70 2.14 0.43 7.26 8.53 3.39 2.79 9.50 10.77

7.26 0.04 1.44 1.82 0.36 6.18 7.26 2.89 2.37 8.08

6.37 0.03 1.27 1.60 0.32 5.42 6.37 2.53 2.08 7.09

5.41 0.04 1.70 2.14 0.43 5.22 5.41 3.75 3.48 7.45

4.60 0.04 1.44 1.82 0.36 4.44 4.60 3.19 2.96 6.34

4.04 0.03 1.27 1.60 0.32 3.89 4.04 2.80 2.60 5.56

4.80 0.04 1.70 2.14 0.43 4.89 4.75 3.83 3.67 7.13

4.09 0.04 1.44 1.82 0.36 4.16 4.04 3.26 3.12 6.06

3.59 0.03 1.27 1.60 0.32 3.65 3.54 2.86 2.74 5.32

4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74

3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73

3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03

4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74

3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73

3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03

9.16

8.04

7.65

6.50

5.71

6.98

5.94

5.21

5.86

4.98

4.37

5.86

4.98

4.37

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

Std.

–1

–2

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-44 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Drive

Speed

Strength Grade t_DOUT

t_DP

t_DINt_PYt_PYSt_EOUT

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHSUnits

2 mA

4 mA

6 mA

8 mA

12 mA

Std.

–1

0.66 14.11 0.04 1.70 2.14 0.43 14.37 13.14 3.40 2.68 16.61 15.37

0.56 12.00 0.04 1.44 1.82 0.36 12.22 11.17 2.90 2.28 14.13 13.08

0.49 10.54 0.03 1.27 1.60 0.32 10.73 9.81 2.54 2.00 12.40 11.48

0.66 11.23 0.04 1.70 2.14 0.43 11.44 9.87 3.77 3.36 13.68 12.10

–2

Std.

–1

0.56

0.49

9.55 0.04 1.44 1.82 0.36

8.39 0.03 1.27 1.60 0.32

9.73

8.54

8.39 3.21 2.86 11.63 10.29

7.37 2.81 2.51 10.21 9.04

–2

Std.

–1

0.66 10.45 0.04 1.70 2.14 0.43 10.65 9.24 3.84 3.55 12.88 11.48

0.56

0.49

8.89 0.04 1.44 1.82 0.36

7.81 0.03 1.27 1.60 0.32

9.06

7.95

7.86 3.27 3.02 10.96 9.76

6.90 2.87 2.65 9.62 8.57

–2

Std.

–1

0.66 10.02 0.04 1.70 2.14 0.43 10.20 9.23 3.97 4.22 12.44 11.47

0.56

0.49

8.52 0.04 1.44 1.82 0.36

7.48 0.03 1.27 1.60 0.32

8.68

7.62

7.85 3.38 3.59 10.58 9.75

6.89 2.97 3.15 9.29 8.56

–2

Std.

–1

0.66 10.02 0.04 1.70 2.14 0.43 10.20 9.23 3.97 4.22 12.44 11.47

0.56

0.49

8.52 0.04 1.44 1.82 0.36

7.48 0.03 1.27 1.60 0.32

8.68

7.62

7.85 3.38 3.59 10.58 9.75

6.89 2.97 3.15 9.29 8.56

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

2-36

Revision 13

ProASIC3E Flash Family FPGAs

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus

applications.

Table 2-45 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X

VIL

VIH

VOL

VOH IOL IOH

IOSL

IOSH

IIL¹IIH²

Min.

Max.

Min.

Max.

Min.

Max.

mA³

Max.

mA³

Drive Strength

Per PCI specification

Notes:

mA mA

µA⁴µA⁴

Per PCI curves

10 10

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V< VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN< VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; Microsemi loadings for enable

path characterization are described in Figure 2-11.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R to GND for t_HZ/ t_ZH/ t_ZHS

R to VCCI for t_DP(F)

R to GND for t_DP(R)

R = 25

Test Point

Datapath

R = 1 k

Test Point

Enable Path

10 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

10 pF for t_HZ/ t_LZ

Figure 2-11 • AC Loading

AC loadings are defined per PCI/PCI-X specifications for the datapath; Microsemi loading for tristate is

described in Table 2-46.

Table 2-46 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

C_LOAD(pF)

3.3

0.285 * VCCI for t_DP(R)

0.615 * VCCI for t_DP(F)

–

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Timing Characteristics

Table 2-47 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Speed

Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_PYS

1.67

1.42

1.25

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

Units

Std.

–1

2.81

2.39

2.09

1.05

0.89

0.78

2.86

2.43

2.13

2.00

1.70

1.49

3.28

2.79

2.45

3.61

3.07

2.70

5.09 4.23

4.33 3.60

3.80 3.16

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Revision 13

2-37

ProASIC3E DC and Switching Characteristics

Voltage-Referenced I/O Characteristics

3.3 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier

input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V.

Table 2-48 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL

VIL

VIH

VOL

VOH IOL IOH IOSL

IOSH

IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA¹

Max.

mA¹

mA mA

µA²µA²

20 mA³

–0.3 VREF – 0.05 VREF + 0.05

3.6

0.4

–

20 20

181

268

10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

VTT

GTL

Test Point

10 pF

Figure 2-12 • AC Loading

Table 2-49 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

_LOAD(pF)

VREF – 0.05

VREF + 0.05

0.8

1.2

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Timing Characteristics

Table 2-50 • 3.3 V GTL

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 0.8 V

Speed

Grade

Std.

–1

t_DOUT

0.60

0.51

0.45

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.27

3.63

3.19

t_ZHS

4.31

3.67

3.22

Units

2.08

1.77

1.55

2.93

2.50

2.19

2.04

1.73

1.52

2.08

1.77

1.55

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

2-38

Revision 13

ProASIC3E Flash Family FPGAs

2.5 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier

input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.

Table 2-51 • Minimum and Maximum DC Input and Output Levels

2.5 GTL

VIL

VIH

VOL

VOH IOL IOH

IOSL

IOSH

IIL IIH

Drive

Strength

Min.,

Max.

Min.

Max.

Min.

Max.

mA¹

Max.

mA¹

mA mA

µA²µA²

20 mA³

–0.3 VREF – 0.05 VREF + 0.05

3.6

0.4

–

20 20

124

169

10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

VTT

GTL

Test Point

10 pF

Figure 2-13 • AC Loading

Table 2-52 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

_LOAD(pF)

VREF – 0.05

VREF + 0.05

0.8

1.2

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Timing Characteristics

Table 2-53 • 2.5 V GTL

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V VREF = 0.8 V

Speed

Grade

Std.

–1

t_DOUT

0.60

0.51

0.45

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.40

3.74

3.28

t_ZHS

4.36

3.71

3.26

Units

2.13

1.81

1.59

2.46

2.09

1.83

2.16

1.84

1.61

2.13

1.81

1.59

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Revision 13

2-39

ProASIC3E DC and Switching Characteristics

3.3 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V.

Table 2-54 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL+

VIL

VIH

VOL

VOH IOL IOH

IOSL

IOSH

IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA¹

Max.

mA¹

mA mA

µA²µA²

35 mA

–0.3 VREF – 0.1 VREF + 0.1

3.6

0.6

–

35 35

181

268

10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

VTT

GTL+

Test Point

10 pF

Figure 2-14 • AC Loading

Table 2-55 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

_LOAD(pF)

VREF – 0.1

VREF + 0.1

1.0

1.5

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Timing Characteristics

Table 2-56 • 3.3 V GTL+

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V, VREF = 1.0 V

Speed

Grade

Std.

–1

t_DOUT

0.60

0.51

0.45

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.33

3.68

3.23

t_ZHS

4.29

3.65

3.20

Units

2.06

1.75

1.53

1.59

1.35

1.19

2.09

1.78

1.56

2.06

1.75

1.53

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

2-40

Revision 13

ProASIC3E Flash Family FPGAs

2.5 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.

Table 2-57 • Minimum and Maximum DC Input and Output Levels

2.5 V GTL+

VIL

VIH

VOL

VOH IOL IOH

IOSL

IOSH

IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA¹

Max.

mA¹

mA mA

µA²µA²

33 mA

–0.3 VREF – 0.1 VREF + 0.1

3.6

0.6

–

33 33

124

169

10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

VTT

GTL+

Test Point

10 pF

Figure 2-15 • AC Loading

Table 2-58 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

_LOAD(pF)

VREF – 0.1

VREF + 0.1

1.0

1.5

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Timing Characteristics

Table 2-59 • 2.5 V GTL+

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V, VREF = 1.0 V

Speed

Grade

Std.

–1

t_DOUT

0.60

0.51

0.45

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.48

3.81

3.35

t_ZHS

4.34

3.69

3.24

Units

2.21

1.88

1.65

1.51

1.29

1.13

2.25

1.91

1.68

2.10

1.79

1.57

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Revision 13

2-41

ProASIC3E DC and Switching Characteristics

HSTL Class I

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull

output buffer.

Table 2-60 • Minimum and Maximum DC Input and Output Levels

HSTL Class I

VIL

VIH

VOL

VOH

IOL IOH IOSL

IOSH

IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA¹

mA mA mA¹

µA²µA²

8 mA

–0.3 VREF – 0.1 VREF + 0.1 3.6

0.4

VCCI – 0.4

10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

VTT

HSTL

Class I

Test Point

20 pF

Figure 2-16 • AC Loading

Table 2-61 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring Point*

Input Low (V)

Input High (V)

(V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.1

VREF + 0.1

0.75

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Timing Characteristics

Table 2-62 • HSTL Class I

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = .4 V, VREF = 0.75 V

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.47

4.66

4.09

t_ZHS

5.38

4.58

4.02

Units

3.18

2.70

2.37

2.12

1.81

1.59

3.24

2.75

2.42

3.14

2.67

2.35

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

2-42

Revision 13

ProASIC3E Flash Family FPGAs

HSTL Class II

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull

output buffer.

Table 2-63 • Minimum and Maximum DC Input and Output Levels

HSTL Class II

VIL

VIH

VOL

VOH

IOL IOH IOSL

IOSH

Max.

IIL IIH

Drive

Strength

Min.

Max.

Min.

Max. Max.,

Min.

Max.

mA mA mA¹

mA¹µA²µA²

15 mA³

–0.3 VREF – 0.1 VREF + 0.1 3.6

0.4 VCCI – 0.4 15 15

10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

VTT

HSTL

Class II

Test Point

20 pF

Figure 2-17 • AC Loading

Table 2-64 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

C_LOAD(pF)

VREF – 0.1

VREF + 0.1

0.75

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Timing Characteristics

Table 2-65 • HSTL Class II

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.4 V, VREF = 0.75 V

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

5.32

4.52

3.97

t_ZHS

4.95

4.21

3.70

Units

3.02

2.57

2.26

2.12

1.81

1.59

3.08

2.62

2.30

2.71

2.31

2.03

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Revision 13

2-43

ProASIC3E DC and Switching Characteristics

SSTL2 Class I

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support

Class I. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-66 • Minimum and Maximum DC Input and Output Levels

SSTL2 Class I

VIL

VIH

VOL

VOH

IOL IOH IOSL

IOSH IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA mA mA¹

mA¹µA²µA²

15 mA

–0.3 VREF – 0.2 VREF + 0.2 3.6

0.54 VCCI – 0.62 15 15

10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

VTT

SSTL2

Class I

Test Point

30 pF

Figure 2-18 • AC Loading

Table 2-67 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.25

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Timing Characteristics

Table 2-68 • SSTL 2 Class I

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V, VREF = 1.25 V

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.40

3.74

3.29

t_ZHS

4.08

3.47

3.05

Units

2.13

1.81

1.59

1.33

1.14

1.00

2.17

1.84

1.62

1.85

1.57

1.38

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

2-44

Revision 13

ProASIC3E Flash Family FPGAs

SSTL2 Class II

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support

Class II. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-69 • Minimum and Maximum DC Input and Output Levels

SSTL2 Class II

VIL

VIH

VOL

VOH

IOL IOH IOSL

IOSH

Max.

IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA mA mA¹

mA¹µA²µA²

18 mA

–0.3 VREF – 0.2 VREF + 0.2 3.6

0.35 VCCI – 0.43 18 18

124

169

10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

VTT

SSTL2

Class II

Test Point

30 pF

Figure 2-19 • AC Loading

Table 2-70 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.25

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Timing Characteristics

Table 2-71 • SSTL 2 Class II

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 2.3 V, VREF = 1.25 V

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

2.17

1.84

1.62

t_PY

t_EOUT

1.33

1.14

1.00

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

t_ZHS

4.44

3.78

3.32

Units

0.66

0.56

0.49

0.04

0.03

0.43

0.36

0.32

2.21

1.88

1.65

1.77

1.51

1.32

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Revision 13

2-45

ProASIC3E DC and Switching Characteristics

SSTL3 Class I

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support

Class I. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-72 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class I

VIL

VIH

VOL

VOH

IOL IOH IOSL

Max.

IOSH IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA mA

mA¹

mA¹µA²µA²

14 mA

–0.3 VREF – 0.2 VREF + 0.2 3.6

0.7

VCCI – 1.1 14 14

10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

VTT

SSTL3

Class I

Test Point

30 pF

Figure 2-20 • AC Loading

Table 2-73 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.5

1.485

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Timing Characteristics

Table 2-74 • SSTL3 Class I

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V, VREF = 1.5 V

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.59

3.90

3.42

t_ZHS

4.07

3.46

3.04

Units

2.31

1.96

1.72

1.25

1.06

0.93

2.35

2.00

1.75

1.84

1.56

1.37

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

2-46

Revision 13

ProASIC3E Flash Family FPGAs

SSTL3 Class II

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support

Class II. This provides a differential amplifier input buffer and a push-pull output buffer.

Table 2-75 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class II

VIL

VIH

VOL

VOH

IOL IOH IOSL

IOSH IIL IIH

Drive

Strength

Min.

Max.

Min.

Max.

Min.

Max.

mA mA mA¹

mA¹µA²µA²

21 mA

–0.3 VREF – 0.2 VREF + 0.2

3.6

0.5

VCCI – 0.9 21 21

109

103

10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

VTT

SSTL3

Class II

Test Point

30 pF

Figure 2-21 • AC Loading

Table 2-76 • AC Waveforms, Measuring Points, and Capacitive Loads

Measuring

Input Low (V)

Input High (V)

Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

_LOAD(pF)

VREF – 0.2

VREF + 0.2

1.5

1.485

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Timing Characteristics

Table 2-77 • SSTL3 Class II

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V, VREF = 1.5 V

Speed

Grade

Std.

–1

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

t_EOUT

0.43

0.36

0.32

t_ZL

t_ZH

t_LZ

t_HZ

t_ZLS

4.34

3.69

3.24

t_ZHS

3.91

3.32

2.92

Units

2.07

1.76

1.54

1.25

1.06

0.93

2.10

1.79

1.57

1.67

1.42

1.25

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Revision 13

2-47

ProASIC3E DC and Switching Characteristics

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by the Designer software when the user

instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-22. The

building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVPECL implementation because the output standard

specifications are different.

Along with LVDS I/O, ProASIC3E also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)

configuration (up to 40 nodes).

Bourns Part Number: CAT16-LV4F12

FPGA

OUTBUF_LVDS

165 

Z₀= 50 

140 

Z₀= 50 

INBUF_LVDS

–

100 

Figure 2-22 • LVDS Circuit Diagram and Board-Level Implementation

2-48

Revision 13

ProASIC3E Flash Family FPGAs

Table 2-78 • LVDS Minimum and Maximum DC Input and Output Levels

DC Parameter

VCCI

Description

Supply Voltage

Min.

2.375

0.9

Typ.

2.5

Max.

2.625

1.25

1.6

Units

VOL

Output Low Voltage

1.075

1.425

0.91

VOH

Output High Voltage

1.25

0.65

IOL¹

Output Lower Current

1.16

2.925

IOH¹

Output High Current

Input Voltage

IIH²

Input High Leakage Current

Input Low Leakage Current

Differential Output Voltage

Output Common Mode Voltage

Input Common Mode Voltage

Input Differential Voltage ²

µA

IIL²

VODIFF

VOCM

VICM

VIDIFF

Notes:

250

1.125

0.05

100

350

1.25

350

450

1.375

2.35

1. IOL/ IOH defined by VODIFF/(Resistor Network).

2. Currents are measured at 85°C junction temperature.

Table 2-79 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

Cross point

VREF (typ.) (V)

1.075

1.325

–

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Revision 13

2-49

ProASIC3E DC and Switching Characteristics

Timing Characteristics

Table 2-80 • LVDS

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case

VCCI = 2.3 V

Speed Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

Units

Std.

–1

1.87

1.59

1.40

1.82

1.55

1.36

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for

derating values.

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to

high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain

any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive

current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series

terminations for better signal quality and to control voltage swing. Termination is also required at both

ends of the bus since the driver can be located anywhere on the bus. These configurations can be

implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations.

Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20

loads. A sample application is given in Figure 2-23. The input and output buffer delays are available in

the LVDS section in Table 2-80.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required

differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: R_S= 60  and

R_T= 70 , given Z₀= 50  (2") and Z_stub= 50  (~1.5").

Receiver

Transceiver

Driver

Receiver

Transceiver

BIBUF_LVDS

R_SR_S

Z_stub

R_SR_S

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

Z₀

Z_stub

...

Z₀

R_T

Z₀

Figure 2-23 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

2-50

Revision 13

ProASIC3E Flash Family FPGAs

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires

that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires

external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-24. The

building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three

board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver

resistors are different from those used in the LVDS implementation because the output standard

specifications are different.

Bourns Part Number: CAT16-PC4F12

FPGA

OUTBUF_LVPECL

100 

Z = 50 

INBUF_LVPECL

–

187 W

Z = 50 

100 

Figure 2-24 • LVPECL Circuit Diagram and Board-Level Implementation

Table 2-81 • Minimum and Maximum DC Input and Output Levels

DC Parameter

VCCI

Description

Supply Voltage

Min.

Max.

Min.

Max.

Min.

Max. Units

3.0

3.3

3.6

VOL

Output Low Voltage

0.96

1.8

1.27

2.11

3.6

1.06

1.92

1.43

2.28

3.6

1.30

2.13

1.57

2.41

3.6

VOH

Output High Voltage

VIL, VIH

VODIFF

VOCM

VICM

Input Low, Input High Voltages

Differential Output Voltage

Output Common-Mode Voltage

Input Common-Mode Voltage

Input Differential Voltage

0.625 0.97 0.625 0.97 0.625 0.97

1.762 1.98 1.762 1.98 1.762 1.98

1.01

300

2.57

1.01

300

2.57

1.01

300

2.57

VIDIFF

Table 2-82 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

1.64

1.94

Cross point

–

Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Timing Characteristics

Table 2-83 • LVPECL

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Speed Grade

t_DOUT

0.66

0.56

0.49

t_DP

t_DIN

0.04

0.03

t_PY

Units

Std.

–1

1.83

1.55

1.36

1.63

1.39

1.22

–2

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Revision 13

2-51

ProASIC3E DC and Switching Characteristics

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Preset

Preset

DOUT

Data_out

PRE

Core

Array

Data

Enable

CLK

DFN1E1P1

EOUT

PRE

DFN1E1P1

Data Input I/O Register with:

Active High Enable

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

CLKBUF

INBUF

Postive-Edge Triggered

Figure 2-25 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

2-52

Revision 13

ProASIC3E Flash Family FPGAs

Table 2-84 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

H, DOUT

F, H

Data Setup Time for the Output Data Register

Data Hold Time for the Output Data Register

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

t_OHD

F, H

t_OSUE

G, H

t_OHE

G, H

t_OPRE2Q

t_OREMPRE

t_ORECPRE

t_OECLKQ

t_OESUD

t_OEHD

L, DOUT

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

L, H

H, EOUT

J, H

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

J, H

t_OESUE

t_OEHE

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

K, H

I, EOUT

I, H

t_OEPRE2Q

t_OEREMPRE

t_OERECPRE

t_ICLKQ

I, H

A, E

t_ISUD

Data Setup Time for the Input Data Register

C, A

B, A

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

B, A

t_IPRE2Q

t_IREMPRE

t_IRECPRE

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

D, E

D, A

Note: *See Figure 2-25 on page 2-52 for more information.

Revision 13

2-53

ProASIC3E DC and Switching Characteristics

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Clear

DOUT

Data_out

Core

Data

Array

DFN1E1C1

EOUT

Enable

CLK

CLR

DFN1E1C1

Data Input I/O Register with

Active High Enable

CLR

Active High Clear

Positive-Edge Triggered

Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

INBUF

CLKBUF

Figure 2-26 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

2-54

Revision 13

ProASIC3E Flash Family FPGAs

Table 2-85 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

t_OSUD

Parameter Definition

Clock-to-Q of the Output Data Register

HH, DOUT

FF, HH

Data Setup Time for the Output Data Register

Data Hold Time for the Output Data Register

t_OHD

FF, HH

t_OSUE

Enable Setup Time for the Output Data Register

Enable Hold Time for the Output Data Register

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

GG, HH

LL, DOUT

LL, HH

t_OHE

t_OCLR2Q

t_OREMCLR

t_ORECCLR

t_OECLKQ

t_OESUD

t_OEHD

LL, HH

HH, EOUT

JJ, HH

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

JJ, HH

t_OESUE

t_OEHE

KK, HH

II, EOUT

t_OECLR2Q

t_OEREMCLR

t_OERECCLR

t_ICLKQ

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

II, HH

AA, EE

CC, AA

BB, AA

DD, EE

DD, AA

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IREMCLR

t_IRECCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Note: *See Figure 2-26 on page 2-54 for more information.

Revision 13

2-55

ProASIC3E DC and Switching Characteristics

Input Register

t_ICKMPWHt_ICKMPWL

50%

CLK

t_IHD

t_ISUD

50%

Data

t_IREMPRE

t_IRECPRE

t_IWPRE

Enable

Preset

50%

t_IHE

t_ISUE

50%

t_IWCLR

t_IRECCLR

50%

t_IREMCLR

50%

Clear

t_IPRE2Q

50%

t_ICLKQ

50%

Out_1

t_ICLR2Q

Figure 2-27 • Input Register Timing Diagram

Timing Characteristics

Table 2-86 • Input Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_ICLKQ

Description

–2

–1 Std. Units

Clock-to-Q of the Input Data Register

0.24 0.27 0.32

0.26 0.30 0.35

0.00 0.00 0.00

0.37 0.42 0.50

0.00 0.00 0.00

0.45 0.52 0.61

0.00 0.00 0.00

0.22 0.25 0.30

0.00 0.00 0.00

0.22 0.25 0.30

0.36 0.41 0.48

0.32 0.37 0.43

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ISUE

Enable Setup Time for the Input Data Register

t_IHE

Enable Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width High for the Input Data Register

Clock Minimum Pulse Width Low for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

2-56

Revision 13

ProASIC3E Flash Family FPGAs

Output Register

t_OCKMPWHt_OCKMPWL

50%

CLK

t_OSUDt_OHD

50%

Data_out

t_OREMPRE

Enable

Preset

50%

t_OWPREt_ORECPRE

50%

t_OHE

50%

t_OSUE

t_OREMCLR

50%

t_ORECCLR

50%

t_OWCLR

50%

Clear

t_OPRE2Q

50%

t_OCLKQ

50%

DOUT

t_OCLR2Q

Figure 2-28 • Output Register Timing Diagram

Timing Characteristics

Table 2-87 • Output Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_OCLKQ

Description

–2

–1 Std. Units

Clock-to-Q of the Output Data Register

0.59 0.67 0.79

0.31 0.36 0.42

0.00 0.00 0.00

0.44 0.50 0.59

0.00 0.00 0.00

0.80 0.91 1.07

0.00 0.00 0.00

0.22 0.25 0.30

0.00 0.00 0.00

0.22 0.25 0.30

0.36 0.41 0.48

0.32 0.37 0.43

t_OSUD

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OSUE

Enable Setup Time for the Output Data Register

t_OHE

Enable Hold Time for the Output Data Register

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

t_OWPRE

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Asynchronous Clear Minimum Pulse Width for the Output Data Register

Asynchronous Preset Minimum Pulse Width for the Output Data Register

t_OCKMPWHClock Minimum Pulse Width High for the Output Data Register

t_OCKMPWLClock Minimum Pulse Width Low for the Output Data Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Revision 13

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ProASIC3E DC and Switching Characteristics

Output Enable Register

t_OECKMPWHt_OECKMPWL

50%

CLK

t_{OESUD OEHD}

50% 50%

D_Enable

50%

Enable

Preset

t_OEWPRE

50%

t_OEREMPRE

t_OERECPRE

50%

t_OESUEOEHE

t_OEREMCLR

50%

t_OEWCLRt_OERECCLR

50%

Clear

t_OECLR2Q

50%

t_OEPRE2Q

50%

t_OECLKQ

EOUT

Figure 2-29 • Output Enable Register Timing Diagram

Timing Characteristics

Table 2-88 • Output Enable Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_OECLKQ

t_OESUD

Description

–2

–1 Std. Units

Clock-to-Q of the Output Enable Register

0.59 0.67 0.79

0.31 0.36 0.42

0.00 0.00 0.00

0.44 0.50 0.58

0.00 0.00 0.00

0.67 0.76 0.89

0.00 0.00 0.00

0.22 0.25 0.30

0.00 0.00 0.00

0.22 0.25 0.30

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

Enable Setup Time for the Output Enable Register

Enable Hold Time for the Output Enable Register

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

t_OEHD

t_OESUE

t_OEHE

t_OECLR2Q

t_OEPRE2Q

t_OEREMCLRAsynchronous Clear Removal Time for the Output Enable Register

t_OERECCLRAsynchronous Clear Recovery Time for the Output Enable Register

t_OEREMPREAsynchronous Preset Removal Time for the Output Enable Register

t_OERECPREAsynchronous Preset Recovery Time for the Output Enable Register

t_OEWCLR

t_OEWPRE

Asynchronous Clear Minimum Pulse Width for the Output Enable Register

Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30

t_OECKMPWHClock Minimum Pulse Width High for the Output Enable Register

t_OECKMPWLClock Minimum Pulse Width Low for the Output Enable Register

0.36 0.41 0.48

0.32 0.37 0.43

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

2-58

Revision 13

ProASIC3E Flash Family FPGAs

DDR Module Specifications

Input DDR Module

Input DDR

INBUF

Out_QF

(to core)

Data

FF1

Out_QR

(to core)

CLK

CLKBUF

FF2

CLR

INBUF

DDR_IN

Figure 2-30 • Input DDR Timing Model

Table 2-89 • Parameter Definitions

Parameter Name

Parameter Definition

Clock-to-Out Out_QR

Clock-to-Out Out_QF

Measuring Nodes (from, to)

t_DDRICLKQ1

t_DDRICLKQ2

t_DDRISUD

B, D

B, E

A, B

C, D

C, E

C, B

Data Setup Time of DDR input

Data Hold Time of DDR input

Clear-to-Out Out_QR

Clear-to-Out Out_QF

Clear Removal

t_DDRIHD

t_DDRICLR2Q1

t_DDRICLR2Q2

t_DDRIREMCLR

t_DDRIRECCLR

Clear Recovery

Revision 13

2-59

ProASIC3E DC and Switching Characteristics

CLK

t_DDRISUD

t_DDRIHD

Data

CLR

t_DDRIRECCLR

t_DDRIREMCLR

t_DDRICLKQ1

t_DDRICLR2Q1

Out_QF

Out_QR

t_DDRICLKQ2

t_DDRICLR2Q2

Figure 2-31 • Input DDR Timing Diagram

Timing Characteristics

Table 2-90 • Input DDR Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_DDRICLKQ1

t_DDRICLKQ2

t_DDRISUD

Description

–2

–1

Std. Units

Clock-to-Out Out_QR for Input DDR

Clock-to-Out Out_QF for Input DDR

Data Setup for Input DDR

0.39 0.44 0.52

0.27 0.31 0.37

0.28 0.32 0.38

0.00 0.00 0.00

0.57 0.65 0.76

0.46 0.53 0.62

0.00 0.00 0.00

0.22 0.25 0.30

0.36 0.41 0.48

0.32 0.37 0.43

t_DDRIHD

Data Hold for Input DDR

t_DDRICLR2Q1

t_DDRICLR2Q2

Asynchronous Clear to Out Out_QR for Input DDR

Asynchronous Clear-to-Out Out_QF for Input DDR

t_DDRIREMCLR

t_DDRIRECCLR

t_DDRIWCLR

Asynchronous Clear Removal Time for Input DDR

Asynchronous Clear Recovery Time for Input DDR

Asynchronous Clear Minimum Pulse Width for Input DDR

Clock Minimum Pulse Width High for Input DDR

Clock Minimum Pulse Width Low for Input DDR

Maximum Frequency for Input DDR

t_DDRICKMPWH

t_DDRICKMPWL

F_DDRIMAX

1404 1232 1048 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

2-60

Revision 13

ProASIC3E Flash Family FPGAs

Output DDR Module

Output DDR

Data_F

(from core)

FF1

Out

CLK

CLKBUF

OUTBUF

Data_R

(from core)

FF2

CLR

INBUF

DDR_OUT

Figure 2-32 • Output DDR Timing Model

Table 2-91 • Parameter Definitions

Parameter Name

t_DDROCLKQ

Parameter Definition

Clock-to-Out

Measuring Nodes (from, to)

B, E

C, E

C, B

A, B

D, B

A, B

D, B

t_DDROCLR2Q

t_DDROREMCLR

t_DDRORECCLR

t_DDROSUD1

Asynchronous Clear-to-Out

Clear Removal

Clear Recovery

Data Setup Data_F

Data Setup Data_R

Data Hold Data_F

Data Hold Data_R

t_DDROSUD2

t_DDROHD1

t_DDROHD2

Revision 13

2-61

ProASIC3E DC and Switching Characteristics

CLK

DDROHD2

DDROSUD2

Data_F

DDROHD1

DDROREMCLR

Data_R 6

CLR

DDRORECCLR

DDROREMCLR

DDROCLKQ

DDROCLR2Q

Out

Figure 2-33 • Output DDR Timing Diagram

Timing Characteristics

Table 2-92 • Output DDR Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_DDROCLKQ

t_DDROSUD1

t_DDROSUD2

t_DDROHD1

Description

–2

–1

Std. Units

Clock-to-Out of DDR for Output DDR

Data_F Data Setup for Output DDR

Data_R Data Setup for Output DDR

Data_F Data Hold for Output DDR

0.70 0.80 0.94

0.38 0.43 0.51

0.00 0.00 0.00

0.80 0.91 1.07

0.00 0.00 0.00

0.22 0.25 0.30

0.36 0.41 0.48

0.32 0.37 0.43

t_DDROHD2

Data_R Data Hold for Output DDR

t_DDROCLR2Q

Asynchronous Clear-to-Out for Output DDR

t_DDROREMCLR

t_DDRORECCLR

t_DDROWCLR1

Asynchronous Clear Removal Time for Output DDR

Asynchronous Clear Recovery Time for Output DDR

Asynchronous Clear Minimum Pulse Width for Output DDR

t_DDROCKMPWHClock Minimum Pulse Width High for the Output DDR

t_DDROCKMPWL

F_DDOMAX

Clock Minimum Pulse Width Low for the Output DDR

Maximum Frequency for the Output DDR

1404 1232 1048 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

2-62

Revision 13

ProASIC3E Flash Family FPGAs

VersaTile Characteristics

VersaTile Specifications as a Combinatorial Module

The ProASIC3E library offers all combinations of LUT-3 combinatorial functions. In this section, timing

characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO^®/e,

and ProASIC3/E Macro Library Guide.

INV

NOR2

OR2

AND2

NAND2

XOR3

XOR2

MAJ3

MUX2

NAND3

Figure 2-34 • Sample of Combinatorial Cells

Revision 13

2-63

ProASIC3E DC and Switching Characteristics

t_PD

NAND2 or

Any Combinatorial

Logic

t_PD= MAX(t_PD(RR), t_PD(RF), t_PD(FF), t_PD(FR)

)

where edges are applicable for the particular

combinatorial cell

VCC

50%

A, B, C

GND

50%

VCC

50%

OUT

GND

t_PD

(FF)

(RR)

VCC

OUT

t_PD

(FR)

50%

t_PD

GND

(RF)

Figure 2-35 • Timing Model and Waveforms

2-64

Revision 13

ProASIC3E Flash Family FPGAs

Timing Characteristics

Table 2-93 • Combinatorial Cell Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Combinatorial Cell

INV

Equation

Y = !A

Parameter

t_PD

–2

–1

Std.

0.54

0.63

0.65

0.99

0.93

1.17

0.68

0.75

Units

0.40

0.47

0.49

0.74

0.70

0.87

0.51

0.56

0.46

0.54

0.55

0.84

0.79

1.00

0.58

0.64

AND2

Y = A · B

t_PD

NAND2

OR2

Y = !(A · B)

Y = A + B

t_PD

NOR2

Y = !(A + B)

Y = A B

Y = MAJ(A , B, C)

^{Y = A} B C

Y = A !S + B S

Y = A · B · C

t_PD

XOR2

t_PD

MAJ3

t_PD

XOR3

t_PD

MUX2

t_PD

AND3

t_PD

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

VersaTile Specifications as a Sequential Module

The ProASIC3E library offers a wide variety of sequential cells, including flip-flops and latches. Each has

a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for

a representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E

Macro Library Guide.

Data

CLK

Out

Data

Out

DFN1

DFN1E1

CLK

PRE

Data

Out

DFN1C1

DFI1E1P1

CLK

CLR

Figure 2-36 • Sample of Sequential Cells

Revision 13

2-65

ProASIC3E DC and Switching Characteristics

t_{CKMPWH CKMPWL}

50%

CLK

t_HD

t_SUD

50%

Data

50%

t_RECPRE

50%

t_WPRE

t_REMPRE

t_HE

50%

t_SUE

PRE

CLR

Out

t_REMCLR

t_RECCLR

50%

t_WCLR

50%

t_PRE2Q

50%

t_CLR2Q

50%

t_CLKQ

Figure 2-37 • Timing Model and Waveforms

Timing Characteristics

Table 2-94 • Register Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_CLKQ

Description

–2

–1 Std. Units

Clock-to-Q of the Core Register

0.55 0.63 0.74

0.43 0.49 0.57

0.00 0.00 0.00

0.45 0.52 0.61

0.00 0.00 0.00

0.40 0.45 0.53

0.00 0.00 0.00

0.22 0.25 0.30

0.00 0.00 0.00

0.22 0.25 0.30

0.32 0.37 0.43

0.36 0.41 0.48

t_SUD

Data Setup Time for the Core Register

t_HD

Data Hold Time for the Core Register

t_SUE

Enable Setup Time for the Core Register

t_HE

Enable Hold Time for the Core Register

t_CLR2Q

t_PRE2Q

t_REMCLR

t_RECCLR

t_REMPRE

t_RECPRE

t_WCLR

Asynchronous Clear-to-Q of the Core Register

Asynchronous Preset-to-Q of the Core Register

Asynchronous Clear Removal Time for the Core Register

Asynchronous Clear Recovery Time for the Core Register

Asynchronous Preset Removal Time for the Core Register

Asynchronous Preset Recovery Time for the Core Register

Asynchronous Clear Minimum Pulse Width for the Core Register

Asynchronous Preset Minimum Pulse Width for the Core Register

Clock Minimum Pulse Width High for the Core Register

Clock Minimum Pulse Width Low for the Core Register

t_WPRE

t_CKMPWH

t_CKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

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Revision 13

ProASIC3E Flash Family FPGAs

Global Resource Characteristics

A3PE600 Clock Tree Topology

Clock delays are device-specific. Figure 2-38 is an example of a global tree used for clock routing. The

global tree presented in Figure 2-38 is driven by a CCC located on the west side of the A3PE600 device.

It is used to drive all D-flip-flops in the device.

Central

Global Rib

CCC

VersaTile

Rows

Global Spine

Figure 2-38 • Example of Global Tree Use in an A3PE600 Device for Clock Routing

Global Tree Timing Characteristics

Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not

include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven

and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer

to the "Clock Conditioning Circuits" section on page 2-69. Table 2-95 on page 2-68, Table 2-96 on

page 2-68, and Table 2-97 on page 2-68 present minimum and maximum global clock delays within the

device. Minimum and maximum delays are measured with minimum and maximum loading.

Revision 13

2-67

ProASIC3E DC and Switching Characteristics

Timing Characteristics

Table 2-95 • A3PE600 Global Resource

Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

–2

–1

Std.

Parameter

t_RCKL

Description

Input Low Delay for Global Clock

Input High Delay for Global Clock

Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

0.83 1.04 0.94 1.18 1.11 1.39

0.81 1.06 0.93 1.21 1.09 1.42

t_RCKH

t_RCKMPWHMinimum Pulse Width High for Global Clock

t_RCKMPWLMinimum Pulse Width Low for Global Clock

0.75

0.85

0.96

1.00

1.13

t_RCKSW

Maximum Skew for Global Clock

0.25

0.28

0.33

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-96 • A3PE1500 Global Resource

Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

–2

–1

Std.

Parameter

t_RCKL

Description

Input Low Delay for Global Clock

Input High Delay for Global Clock

Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

1.07 1.29 1.22 1.47 1.43 1.72

1.06 1.32 1.21 1.50 1.42 1.76

t_RCKH

t_RCKMPWHMinimum Pulse Width High for Global Clock

t_RCKMPWLMinimum Pulse Width Low for Global Clock

0.75

0.85

0.96

1.00

1.13

t_RCKSW

Maximum Skew for Global Clock

0.26

0.29

0.34

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-97 • A3PE3000 Global Resource

Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

–2

–1

Std.

Parameter

t_RCKL

Description

Input Low Delay for Global Clock

Input High Delay for Global Clock

Min.¹Max.²Min.¹Max.²Min.¹Max.²Units

1.41 1.62 1.60 1.85 1.88 2.17

1.40 1.66 1.59 1.89 1.87 2.22

t_RCKH

t_RCKMPWHMinimum Pulse Width High for Global Clock

t_RCKMPWLMinimum Pulse Width Low for Global Clock

0.75

0.85

0.96

1.00

1.13

t_RCKSW

Maximum Skew for Global Clock

0.26

0.29

0.35

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,

located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully

loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

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Revision 13

ProASIC3E Flash Family FPGAs

Clock Conditioning Circuits

CCC Electrical Specifications

Timing Characteristics

Table 2-98 • ProASIC3E CCC/PLL Specification

Parameter

Minimum

1.5

Typical

Maximum

350

Units

MHz

Clock Conditioning Circuitry Input Frequency f_{IN_CCC}

Clock Conditioning Circuitry Output Frequency f_{OUT_CCC}

Delay Increments in Programmable Delay Blocks ^{1, 2}

Serial Clock (SCLK) for Dynamic PLL⁴

0.75

350

160³

125

MHz

Number of Programmable Values in Each

Programmable Delay Block

Input Period Jitter

1.5

CCC Output Peak-to-Peak Period Jitter F_{CCC_OUT}

Max Peak-to-Peak Period Jitter

3 Global

1 Global

Network Used

Networks Used

0.70%

1.20%

2.00%

5.60%

300

0.75 MHz to 24 MHz

24 MHz to 100 MHz

100 MHz to 250 MHz

250 MHz to 350 MHz

0.50%

1.00%

1.75%

2.50%

Acquisition Time

Tracking Jitter ⁵

Output Duty Cycle

LockControl = 0

LockControl = 1

LockControl = 0

LockControl = 1

µs

6.0

1.6

0.8

48.5

0.6

51.5

Delay Range in Block: Programmable Delay 1 ^{1, 2}

Delay Range in Block: Programmable Delay 2 ^1,2

Delay Range in Block: Fixed Delay^1,4

Notes:

5.56

0.025

5.56

2.2

1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-5 for deratings

2. T = 25°C, VCC = 1.5 V.

3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay

increments are available. Refer to the Libero SoC Online Help for more information.

4. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction

temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock

edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter

parameter.

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ProASIC3E DC and Switching Characteristics

Output Signal

T_{period_max}

T_{period_min}

Note: Peak-to-peak jitter measurements are defined by T_peak-to-peak= T_{period_max}– T_{period_min}

Figure 2-39 • Peak-to-Peak Jitter Definition

2-70

Revision 13

ProASIC3E Flash Family FPGAs

Embedded SRAM and FIFO Characteristics

SRAM

RAM4K9

RAM512X18

RADDR8

RADDR7

RD17

RD16

ADDRA11 DOUTA8

DOUTA7

DOUTA0

ADDRA10

ADDRA0

DINA8

RADDR0

RD0

DINA7

RW1

RW0

DINA0

WIDTHA1

WIDTHA0

PIPEA

PIPE

WMODEA

BLKA

WENA

REN

RCLK

CLKA

ADDRB11 DOUTB8

ADDRB10 DOUTB7

WADDR8

WADDR7

ADDRB0

DOUTB0

WADDR0

WD17

WD16

DINB8

DINB7

WD0

DINB0

WW1

WW0

WIDTHB1

WIDTHB0

PIPEB

WMODEB

BLKB

WEN

WCLK

WENB

CLKB

RESET

Figure 2-40 • RAM Models

Revision 13

2-71

ProASIC3E DC and Switching Characteristics

Timing Waveforms

t_CYC

t_CKH

t_CKL

CLK

[R|W]ADDR

BLK

t_ASt_AH

A₀

A₁

A₂

t_BKS

t_BKH

t_ENS

t_ENH

WEN

t_CKQ1

D_n

D₀

D₁

D₂

DOUT|RD

t_DOH1

Figure 2-41 • RAM Read for Pass-Through Output. Applicable to Both RAM4K9 and RAM512x18.

t_CYC

t_CKH

t_CKL

CLK

[R|W]ADDR

BLK

t_ASt_AH

A₀

A₁

A₂

t_BKS

t_BKH

t_ENH

t_ENS

WEN

t_CKQ2

D_n

D₀

D₁

DOUT|RD

t_DOH2

Figure 2-42 • RAM Read for Pipelined Output. Applicable to Both RAM4K9 and RAM512x18.

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Revision 13

ProASIC3E Flash Family FPGAs

t_CYC

t_CKH

t_CKL

CLK

[R|W]ADDR

BLK

t_AS

t_AH

A₀

t_BKS

A₁

A₂

t_BKH

t_ENS

t_ENH

WEN

t_DS

t_DH

DI₁

DI₀

DIN|WD

DOUT|RD

D_n

D₂

Figure 2-43 • RAM Write, Output Retained. Applicable to Both RAM4K9 and RAM512x18.

t_CYC

t_CKH

t_CKL

CLK

ADDR

BLK

t_ASt_AH

A₀

t_BKS

A₁

A₂

t_BKH

t_ENS

WEN

DIN

t_DSt_DH

DI₁

DI₀

DI₂

DOUT

D_n

DI₀

DI₁

(pass-through)

DOUT

DI₀

D_n

DI₁

(pipelined)

Figure 2-44 • RAM Write, Output as Write Data. Applicable to RAM4K9 Only.

Revision 13

2-73

ProASIC3E DC and Switching Characteristics

t_CYC

t_CKH

t_CKL

CLK

RESET

t_RSTBQ

D_m

D_n

DOUT|RD

Figure 2-45 • RAM Reset. Applicable to Both RAM4K9 and RAM512x18.

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Revision 13

ProASIC3E Flash Family FPGAs

Timing Characteristics

Table 2-99 • RAM4K9

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_AS

Description

Address setup time

–2

–1 Std. Units

0.25 0.28 0.33

0.00 0.00 0.00

0.14 0.16 0.19

0.10 0.11 0.13

0.23 0.27 0.31

0.02 0.02 0.02

0.18 0.21 0.25

0.00 0.00 0.00

1.79 2.03 2.39

2.36 2.68 3.15

0.89 1.02 1.20

t_AH

Address hold time

t_ENS

t_ENH

t_BKS

t_BKH

t_DS

REN, WEN setup time

REN, WEN hold time

BLK setup time

BLK hold time

Input data (DIN) setup time

t_DH

Input data (DIN) hold time

t_CKQ1

Clock High to new data valid on DOUT (output retained, WMODE = 0)

Clock High to new data valid on DOUT (flow-through, WMODE = 1)

Clock High to new data valid on DOUT (pipelined)

t_CKQ2

t_C2CWWL

Address collision clk-to-clk delay for reliable write after write on same 0.33 0.28 0.25

address—Applicable to Closing Edge

t_C2CWWH

Address collision clk-to-clk delay for reliable write after write on same 0.30 0.26 0.23

address—Applicable to Rising Edge

t_C2CRWH

Address collision clk-to-clk delay for reliable read access after write on same 0.45 0.38 0.34

address—Applicable to Opening Edge

t_C2CWRH

Address collision clk-to-clk delay for reliable write access after read on same 0.49 0.42 0.37

address— Applicable to Opening Edge

t_RSTBQ

RESET Low to data out Low on DO (flow-through)

RESET Low to Data Out Low on DO (pipelined)

RESET removal

0.92 1.05 1.23

0.29 0.33 0.38

1.50 1.71 2.01

0.21 0.24 0.29

3.23 3.68 4.32

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET recovery

RESET minimum pulse width

Clock cycle time

F_MAX

Maximum frequency

310 272 231 MHz

Notes:

1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-

Based cSoCs and FPGAs.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Revision 13

2-75

ProASIC3E DC and Switching Characteristics

Table 2-100 • RAM512X18

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_AS

Description

–2

–1 Std. Units

Address setup time

0.25 0.28 0.33

0.00 0.00 0.00

0.18 0.20 0.24

0.06 0.07 0.08

0.18 0.21 0.25

0.00 0.00 0.00

2.16 2.46 2.89

0.90 1.02 1.20

t_AH

Address hold time

t_ENS

REN, WEN setup time

REN, WEN hold time

Input data (WD) setup time

Input data (WD) hold time

t_ENH

t_DS

t_DH

t_CKQ1

t_CKQ2

Clock High to new data valid on RD (output retained)

Clock High to new data valid on RD (pipelined)

t_C2CRWH

Address collision clk-to-clk delay for reliable read access after write on same 0.50 0.43 0.38

address—Applicable to Opening Edge

t_C2CWRH

Address collision clk-to-clk delay for reliable write access after read on same 0.59 0.50 0.44

address— Applicable to Opening Edge

t_RSTBQ

RESET Low to data out Low on RD (flow-through)

RESET Low to data out Low on RD (pipelined)

RESET removal

0.92 1.05 1.23

0.29 0.33 0.38

1.50 1.71 2.01

0.21 0.24 0.29

3.23 3.68 4.32

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET recovery

RESET minimum pulse width

Clock cycle time

F_MAX

Maximum frequency

310 272 231 MHz

Notes:

1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-

Based cSoCs and FPGAs.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

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Revision 13

ProASIC3E Flash Family FPGAs

FIFO

FIFO4K18

RW2

RW1

RW0

RD17

RD16

WW2

WW1

WW0

RD0

ESTOP

FSTOP

FULL

AFULL

EMPTY

AEVAL11

AEVAL10

AEMPTY

AEVAL0

AFVAL11

AFVAL10

AFVAL0

REN

RBLK

RCLK

WD17

WD16

WD0

WEN

WBLK

WCLK

RPIPE

RESET

Figure 2-46 • FIFO Model

Revision 13

2-77

ProASIC3E DC and Switching Characteristics

Timing Waveforms

t_CYC

RCLK

t_ENH

t_ENS

REN

t_BKS

t_BKH

RBLK

t_CKQ1

D₁

D_n

D₀

D₂

(flow-through)

t_CKQ2

D_n

D₀

D₁

(pipelined)

Figure 2-47 • FIFO Read

t_CYC

WCLK

t_ENS

t_ENH

WEN

t_BKS

t_BKH

WBLK

t_DS

t_DH

DI₁

DI₀

Figure 2-48 • FIFO Write

2-78

Revision 13

ProASIC3E Flash Family FPGAs

RCLK/

WCLK

t_MPWRSTB

t_RSTCK

RESET

EMPTY

AEMPTY

FULL

t_RSTFG

t_RSTAF

t_RSTFG

t_RSTAF

AFULL

WA/RA

MATCH (A₀)

(Address Counter)

Figure 2-49 • FIFO Reset

t_CYC

RCLK

t_RCKEF

EMPTY

t_CKAF

AEMPTY

WA/RA

NO MATCH

Dist = AEF_TH

MATCH (EMPTY)

(Address Counter)

Figure 2-50 • FIFO EMPTY Flag and AEMPTY Flag Assertion

Revision 13

2-79

ProASIC3E DC and Switching Characteristics

CYC

WCLK

FULL

WCKFF

CKAF

AFULL

WA/RA

NO MATCH

Dist = AFF_TH

MATCH (FULL)

(Address Counter)

Figure 2-51 • FIFO FULL Flag and AFULL Flag Assertion

WCLK

MATCH

WA/RA

NO MATCH

2nd Rising

Edge

After 1st

Write

NO MATCH

Dist = AEF_TH + 1

(Address Counter)

(EMPTY)

1st Rising

Edge

After 1st

Write

RCLK

EMPTY

RCKEF

CKAF

AEMPTY

Figure 2-52 • FIFO EMPTY Flag and AEMPTY Flag Deassertion

RCLK

WA/RA

(Address Counter)

Dist = AFF_TH – 1

MATCH (FULL)

1st Rising

NO MATCH

1st Rising

Edge

After 2nd

Read

NO MATCH

Edge

After 1st

Read

WCLK

FULL

WCKF

CKAF

AFULL

Figure 2-53 • FIFO FULL Flag and AFULL Flag Deassertion

2-80

Revision 13

ProASIC3E Flash Family FPGAs

Timing Characteristics

Table 2-101 • FIFO

Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

Parameter

t_ENS

Description

–2

–1

Std. Units

REN, WEN Setup Time

1.38 1.57 1.84

0.02 0.02 0.02

0.19 0.22 0.26

0.00 0.00 0.00

0.18 0.21 0.25

0.00 0.00 0.00

2.36 2.68 3.15

0.89 1.02 1.20

1.72 1.96 2.30

1.63 1.86 2.18

6.19 7.05 8.29

1.69 1.93 2.27

6.13 6.98 8.20

0.92 1.05 1.23

0.29 0.33 0.38

1.50 1.71 2.01

0.21 0.24 0.29

3.23 3.68 4.32

MHz

t_ENH

REN, WEN Hold Time

t_BKS

BLK Setup Time

t_BKH

BLK Hold Time

t_DS

Input Data (WD) Setup Time

t_DH

Input Data (WD) Hold Time

t_CKQ1

t_CKQ2

t_RCKEF

t_WCKFF

t_CKAF

t_RSTFG

t_RSTAF

t_RSTBQ

Clock High to New Data Valid on RD (pass-through)

Clock High to New Data Valid on RD (pipelined)

RCLK High to Empty Flag Valid

WCLK High to Full Flag Valid

Clock High to Almost Empty/Full Flag Valid

RESET Low to Empty/Full Flag Valid

RESET Low to Almost Empty/Full Flag Valid

RESET Low to Data Out Low on RD (pass-through)

RESET Low to Data Out Low on RD (pipelined)

RESET Removal

t_REMRSTB

t_RECRSTB

t_MPWRSTB

t_CYC

RESET Recovery

RESET Minimum Pulse Width

Clock Cycle Time

F_MAX

Maximum Frequency

310

272

231

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Revision 13

2-81

ProASIC3E DC and Switching Characteristics

Embedded FlashROM Characteristics

t_SU

CLK

t_HOLD

Address

A₀

A₁

t_CKQ2

D₀

t_CKQ2

D₁

D₀

Data

Figure 2-54 • Timing Diagram

Timing Characteristics

Table 2-102 • Embedded FlashROM Access Time

Parameter

t_SU

Description

Address Setup Time

–2

–1

Std.

Units

0.53

0.00

16.23

0.61

0.00

18.48

0.71

0.00

21.73

t_HOLD

t_CK2Q

Address Hold Time

Clock to Out

F_MAX

Maximum Clock Frequency

MHz

JTAG 1532 Characteristics

JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to

the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O

Characteristics" section on page 2-12 for more details.

Timing Characteristics

Table 2-103 • JTAG 1532

Commercial-Case Conditions: T_J= 70°C, VCC = 1.425 V

Parameter

t_DISU

Description

–2

–1

Std.

0.67

1.33

0.67

1.33

8.00

Units

Test Data Input Setup Time

Test Data Input Hold Time

Test Mode Select Setup Time

Test Mode Select Hold Time

Clock to Q (data out)

0.50 0.57

1.00 1.13

0.50 0.57

1.00 1.13

6.00 6.80

t_DIHD

t_TMSSU

t_TMDHD

t_TCK2Q

t_RSTB2Q

F_TCKMAX

t_TRSTREM

t_TRSTREC

t_TRSTMPW

Reset to Q (data out)

20.00 22.67 26.67

25.00 22.00 19.00

TCK Maximum Frequency

ResetB Removal Time

MHz

0.00 0.00

0.20 0.23

TBD TBD

0.00

0.27

TBD

ResetB Recovery Time

ResetB Minimum Pulse

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

2-82

Revision 13

3 – Pin Descriptions and Packaging

Supply Pins

GND

Ground supply voltage to the core, I/O outputs, and I/O logic.

GNDQ Ground (quiet)

Ground

Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is

decoupled from the simultaneous switching noise originated from the output buffer ground domain. This

minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always

be connected to GND on the board.

VCC

Core Supply Voltage

Supply voltage to the FPGA core, nominally 1.5 V. VCC is required for powering the JTAG state machine

in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices,

both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device.

VCCIBx

I/O Supply Voltage

Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to

eight I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a

separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V,

1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied

to GND.

VMVx

I/O Supply Voltage (quiet)

Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the

VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within

the package and improves input signal integrity. Each bank must have at least one VMV connection, and

no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to

provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.5 V, 1.8 V, 2.5 V, or

3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV

and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to

the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.).

VCCPLA/B/C/D/E/F

PLL Supply Voltage

Supply voltage to analog PLL, nominally 1.5 V.

When the PLLs are not used, the place-and-route tool automatically disables the unused PLLs to lower

power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Microsemi

recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from the

PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning Circuits in Low

Power Flash Devices and Mixed Signal FPGAs" chapter of the ProASIC3E FPGA Fabric User’s Guide

for a complete board solution for the PLL analog power supply and ground.

There are six VCCPLX pins on ProASIC3E devices.

VCOMPLA/B/C/D/E/F

PLL Ground

Ground to analog PLL power supplies. When the PLLs are not used, the place-and-route tool

automatically disables the unused PLLs to lower power consumption. The user should tie unused

VCCPLx and VCOMPLx pins to ground.

There are six VCOMPL pins (PLL ground) on ProASIC3E devices.

VJTAG

JTAG Supply Voltage

Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run

at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank

gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG

interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to

GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is

Revision 13

3-1

Pin Descriptions and Packaging

insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can

be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals

will not be able to transition the device, even in bypass mode.

Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent

filtering capacitors rather than supplying them from a common rail.

VPUMP

Programming Supply Voltage

For programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left

floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming

power supply voltage (VPUMP) range is listed in the datasheet.

When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of

oscillation from the charge pump circuitry.

For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in

parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.

Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent

filtering capacitors rather than supplying them from a common rail.

User-Defined Supply Pins

VREF

I/O Voltage Reference

Reference voltage for I/O minibanks. VREF pins are configured by the user from regular I/Os, and any

I/O in a bank, except JTAG I/Os, can be designated the voltage reference I/O. Only certain I/O standards

require a voltage reference—HSTL (I) and (II), SSTL2 (I) and (II), SSTL3 (I) and (II), and GTL/GTL+. One

VREF pin can support the number of I/Os available in its minibank.

User Pins

I/O

User Input/Output

The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are

compatible with the I/O standard selected.

During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC

supplies continuously powered up, when the device transitions from programming to operating mode, the

I/Os are instantly configured to the desired user configuration.

Unused I/Os are configured as follows:

•

Output buffer is disabled (with tristate value of high impedance)

Input buffer is disabled (with tristate value of high impedance)

Weak pull-up is programmed

Globals

GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the

global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have

identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.

See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power

Flash Devices and Mixed Signal FPGAs" chapter of the ProASIC3E FPGA Fabric User’s Guide. All

inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an

input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled

GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals.

The inputs to the global network are multiplexed, and only one input can be used as a global input.

Refer to the I/O Structure section of the ProASIC3E FPGA Fabric User’s Guide for an explanation of the

naming of global pins.

3-2

Revision 13

ProASIC3E Flash Family FPGAs

JTAG Pins

Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run

at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to

operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the

part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a

separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB

design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST

pin could be tied to GND.

TCK

Test Clock

Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-

up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor

placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state.

Note that to operate at all VJTAG voltages, 500 W to 1 k will satisfy the requirements. Refer to

Table 3-1 for more information.

Table 3-1 • Recommended Tie-Off Values for the TCK and TRST Pins

VJTAG

Tie-Off Resistance

200  to 1 k

500  to 1 k

VJTAG at 3.3 V

VJTAG at 2.5 V

VJTAG at 1.8 V

VJTAG at 1.5 V

Notes:

1. Equivalent parallel resistance if more than one device is on the JTAG chain

2. The TCK pin can be pulled up/down.

3. The TRST pin is pulled down.

TDI

Test Data Input

Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor

on the TDI pin.

TDO

Serial output for JTAG boundary scan, ISP, and UJTAG usage.

TMS Test Mode Select

Test Data Output

The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an

internal weak pull-up resistor on the TMS pin.

TRST

Boundary Scan Reset Pin

The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan

circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-

down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor

values must be chosen from Table 3-1 and must satisfy the parallel resistance value requirement. The

values in Table 3-1 correspond to the resistor recommended when a single device is used, and the

equivalent parallel resistor when multiple devices are connected via a JTAG chain.

In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In

such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA

pin.

Note that to operate at all VJTAG voltages, 500  to 1 k will satisfy the requirements.

Revision 13

3-3

Pin Descriptions and Packaging

Special Function Pins

No Connect

This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be

left floating with no effect on the operation of the device.

Do Not Connect

This pin should not be connected to any signals on the PCB. These pins should be left unconnected.

Packaging

Semiconductor technology is constantly shrinking in size while growing in capability and functional

integration. To enable next-generation silicon technologies, semiconductor packages have also evolved

to provide improved performance and flexibility.

Microsemi consistently delivers packages that provide the necessary mechanical and environmental

protection to ensure consistent reliability and performance. Microsemi IC packaging technology

efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible

enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition,

Microsemi offers a variety of packages designed to meet your most demanding application and economic

requirements for today's embedded and mobile systems.

A3PE1500-1FGG208YES [MICROSEMI]

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