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A3PN015ZVQ100 [MICROSEMI]

ProASIC3 nano Flash FPGAs; 纳米的ProASIC3快闪FPGA
A3PN015ZVQ100
型号： A3PN015ZVQ100
厂家： Microsemi    Microsemi
描述：

ProASIC3 nano Flash FPGAs
纳米的ProASIC3快闪FPGA
文件： 总114页 (文件大小：6102K)
中文：  中文翻译
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Revision 11  
ProASIC3 nano Flash FPGAs  
Advanced I/Os  
Features and Benefits  
•
•
•
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Bank-Selectable I/O Voltages—up to 4 Banks per Chip  
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /  
2.5 V / 1.8 V / 1.5 V  
Wide Range of Features  
•
•
•
10 k to 250 k System Gates  
Up to 36 kbits of True Dual-Port SRAM  
Up to 71 User I/Os  
•
Wide Range Power Supply Voltage Support per JESD8-B,  
Allowing I/Os to Operate from 2.7 V to 3.6 V  
I/O Registers on Input, Output, and Enable Paths  
Selectable Schmitt Trigger Inputs  
Reprogrammable Flash Technology  
•
•
•
•
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS  
Process  
Hot-Swappable and Cold-Sparing I/Os  
•
•
•
Instant On Level 0 Support  
†
•
•
•
•
Programmable Output Slew Rate and Drive Strength  
Single-Chip Solution  
Retains Programmed Design when Powered Off  
Weak Pull-Up/-Down  
IEEE 1149.1 (JTAG) Boundary Scan Test  
Pin-Compatible Packages across the ProASIC3 Family  
High Performance  
•
350 MHz System Performance  
Clock Conditioning Circuit (CCC) and PLL†  
In-System Programming (ISP) and Security  
•
•
Up to Six CCC Blocks, One with an Integrated PLL  
Configurable Phase Shift, Multiply/Divide, Delay  
Capabilities and External Feedback  
•
ISP Using On-Chip 128-Bit Advanced Encryption Standard  
†
(AES) Decryption via JTAG (IEEE 1532–compliant)  
®
•
Wide Input Frequency Range (1.5 MHz to 350 MHz)  
•
FlashLock Designed to Secure FPGA Contents  
Embedded Memory  
Low Power  
®
•
•
1 kbit of FlashROM User Nonvolatile Memory  
•
•
•
•
Low Power ProASIC 3 nano Products  
1.5 V Core Voltage for Low Power  
Support for 1.5 V-Only Systems  
Low-Impedance Flash Switches  
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM  
†
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)  
†
•
True Dual-Port SRAM (except ×18 organization)  
High-Performance Routing Hierarchy  
Enhanced Commercial Temperature Range  
•
Segmented, Hierarchical Routing and Clock Structure  
•
–20°C to +70°C  
Table 1 • ProASIC3 nano Devices  
ProASIC3 nano Devices  
ProASIC3 nano-Z Devices1  
System Gates  
A3PN010 A3PN0151 A3PN020  
A3PN060  
A3PN125  
A3PN250  
A3N250Z1  
A3PN030Z1,2 A3PN060Z1 A3PN125Z1  
10,000  
15,000  
20,000  
30,000  
60,000  
512  
1,536  
18  
125,000  
250,000  
Typical Equivalent Macrocells  
VersaTiles (D-flip-flops)  
86  
260  
–
128  
384  
–
172  
520  
–
256  
768  
–
1,024  
3,072  
36  
8
2,048  
6,144  
36  
8
2
RAM Kbits (1,024 bits)  
2
4,608-Bit Blocks  
–
–
–
–
4
FlashROM Kbits  
1
1
1
1
1
1
1
2
Secure (AES) ISP  
–
–
–
–
Yes  
1
Yes  
1
Yes  
1
2
Integrated PLL in CCCs  
–
–
–
–
VersaNet Globals  
4
4
4
6
18  
18  
2
18  
4
I/O Banks  
2
3
3
2
2
Maximum User I/Os (packaged device)  
Maximum User I/Os (Known Good Die)  
Package Pins  
34  
34  
49  
–
49  
52  
77  
83  
71  
71  
71  
68  
68  
71  
QFN  
VQFP  
QN48  
QN68  
QN68  
QN48, QN68  
VQ100  
VQ100  
VQ100  
VQ100  
Notes:  
1. Not recommended for new designs.  
2. A3PN030Z and smaller devices do not support this feature.  
3. For higher densities and support of additional features, refer to the ProASIC3 and ProASIC3E datasheets.  
† A3PN030 and smaller devices do not support this feature.  
January 2013  
I
© 2013 Microsemi Corporation  
I/Os Per Package  
ProASIC3 nano Devices  
A3PN010  
A3PN0151 A3PN020  
A3PN060  
A3PN125  
A3PN250  
ProASIC3 nano-Z Devices1  
A3PN030Z1 A3PN060Z1 A3PN125Z1 A3PN250Z1  
Known Good Die  
QN48  
34  
34  
–
–
–
52  
–
83  
34  
49  
77  
71  
–
71  
–
68  
–
QN68  
49  
–
49  
–
–
–
–
VQ100  
–
71  
71  
68  
Notes:  
1. Not recommended for new designs.  
2. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 FPGA Fabric User’s Guide  
to ensure compliance with design and board migration requirements.  
3. "G" indicates RoHS-compliant packages. Refer to "ProASIC3 nano Ordering Information" on page III for the location of the "G"  
in the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other  
packages are RoHS-compliant only.  
Table 2 • ProASIC3 nano FPGAs Package Sizes Dimensions  
Packages  
QN48  
6 x 6  
36  
QN68  
8 x 8  
64  
VQ100  
14 x 14  
196  
Length × Width (mm\mm)  
Nominal Area (mm2)  
Pitch (mm)  
0.4  
0.4  
0.5  
Height (mm)  
0.90  
0.90  
1.20  
ProASIC3 nano Device Status  
ProASIC3 nano Devices  
Status  
ProASIC3 nano-Z Devices  
Status  
A3PN010  
Production  
A3PN015  
A3PN020  
Not recommended for new designs.  
Production  
A3PN030Z  
A3PN060Z  
A3PN125Z  
A3PN250Z  
Not recommended for new designs.  
Not recommended for new designs.  
Not recommended for new designs.  
Not recommended for new designs.  
A3PN060  
A3PN125  
A3PN250  
Production  
Production  
Production  
II  
Revision 11  
ProASIC3 nano Flash FPGAs  
ProASIC3 nano Ordering Information  
_
A3PN250  
Z
1
VQ  
G
100  
Y
I
Application (Temperature Range)  
Blank = Commercial (0°C to +70°C Ambient Temperature)  
I = Industrial (–40°C to +85°C Ambient Temperature)  
PP= Pre-Production  
ES= Engineering Sample (Room Temperature Only)  
Security Feature  
Y = Device Includes License to Implement IP Based on the  
Cryptography Research, Inc. (CRI) Patent Portfolio  
Blank = Device Does Not Include License to Implement IP Based  
on the Cryptography Research, Inc. (CRI) Patent Portfolio  
Package Lead Count  
Lead-Free Packaging  
Blank = Standard Packaging  
G= RoHS-Compliant Packaging  
Package Type  
QN  
VQ  
Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)  
Very Thin Quad Flat Pack (0.5 mm pitch)  
=
=
DIELOT Known Good Die  
=
Speed Grade  
Blank = Standard  
1 = 15% Faster than Standard  
2 = 25% Faster than Standard  
Feature Grade  
Z = nano devices without enhanced features* (Not recommended for new designs)  
Blank = Standard  
Part Number  
ProASIC3 nano Devices  
A3PN010 = 10,000 System Gates  
A3PN015 = 15,000 System Gates (A3PN015 is not recommended for new designs)  
A3PN020 = 20,000 System Gates  
A3PN030 = 30,000 System Gates  
A3PN060 = 60,000 System Gates  
A3PN125 = 125,000 System Gates  
A3PN250 = 250,000 System Gates  
Note: *For the A3PN060, A3PN125, and A3PN250, the Z feature grade does not support the enhanced nano features of Schmitt  
trigger input, cold-sparing, and hot-swap I/O capability. The A3PN030 Z feature grade does not support Schmitt trigger input.  
For the VQ100, CS81, UC81, QN68, and QN48 packages, the Z feature grade and the N part number are not marked on the  
device.  
Devices Not Recommended For New Designs  
A3PN015, A3PN030Z, A3PN060Z, A3PN125Z, and A3PN250Z are not recommended for new designs.  
Device Marking  
Microsemi normally topside marks the full ordering part number on each device. There are some exceptions to this, such as some of  
the Z feature grade nano devices, the V2 designator for IGLOO devices, and packages where space is physically limited. Packages  
that have limited characters available are UC36, UC81, CS81, QN48, QN68, and QFN132. On these specific packages, a subset of  
the device marking will be used that includes the required legal information and as much of the part number as allowed by character  
limitation of the device. In this case, devices will have a truncated device marking and may exclude the applications markings, such  
as the I designator for Industrial Devices or the ES designator for Engineering Samples.  
Figure 1 on page 1-IV shows an example of device marking based on the AGL030V5-UCG81.  
Revision 11  
III  
The actual mark will vary by the device/package combination ordered.  
Country of Origin  
Date Code  
ACTELXXX  
Device Name  
(six characters)  
AGL030YWW  
UCG81XXXX  
XXXXXXXX  
Package  
Customer Mark  
(if applicable)  
Wafer Lot #  
Figure 1 •  
Example of Device Marking for Small Form Factor Packages  
ProASIC3 nano Products Available in the Z Feature Grade  
Devices  
A3PN030*  
QN48  
A3PN060*  
A3PN125*  
A3PN250*  
Packages  
–
–
–
–
–
–
QN68  
VQ100  
VQ100  
VQ100  
VQ100  
Note: *Not recommended for new designs.  
Temperature Grade Offerings  
ProASIC3 nano Devices  
A3PN010  
A3PN015* A3PN020  
A3PN060  
A3PN125  
A3PN250  
ProASIC3 nano-Z Devices*  
A3PN030Z* A3PN060Z* A3PN125Z* A3PN250Z*  
QN48  
QN68  
VQ100  
C, I  
–
–
C, I  
–
–
C, I  
–
C, I  
C, I  
C, I  
–
–
–
–
–
–
–
C, I  
C, I  
C, I  
Note: *Not recommended for new designs.  
C = Commercial temperature range: 0°C to 70°C ambient temperature  
I = Industrial temperature range: –40°C to 85°C ambient temperature  
Speed Grade and Temperature Grade Matrix  
Temperature Grade  
Std.  
C 1  
2
I
Notes:  
1. C = Commercial temperature range: 0°C to 70°C ambient temperature.  
2. I = Industrial temperature range: –40°C to 85°C ambient temperature.  
Contact your local Microsemi SoC Products Group representative for device availability:  
http://www.microsemi.com/soc/contact/default.aspx.  
IV  
Revision 11  
ProASIC3 nano Flash FPGAs  
Table of Contents  
ProASIC3 nano Device Overview  
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1  
ProASIC3 nano DC and Switching Characteristics  
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1  
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6  
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12  
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49  
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53  
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57  
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59  
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70  
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-71  
Pin Descriptions and Packaging  
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1  
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2  
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3  
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4  
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4  
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4  
Package Pin Assignments  
48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1  
68-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4  
100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8  
Datasheet Information  
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1  
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6  
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6  
Revision 11  
V
1 – ProASIC3 nano Device Overview  
General Description  
ProASIC3, the third-generation family of Microsemi flash FPGAs, offers performance, density, and  
features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 nano  
devices the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3  
nano devices are reprogrammable and offer time-to-market benefits at an ASIC-level unit cost. These  
features enable designers to create high-density systems using existing ASIC or FPGA design flows and  
tools.  
ProASIC3 nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well  
as clock conditioning circuitry based on an integrated phase-locked loop (PLL). A3PN030 and smaller  
devices do not have PLL or RAM support. ProASIC3 nano devices have up to 250,000 system gates,  
supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os.  
ProASIC3 nano devices increase the breadth of the ProASIC3 product line by adding new features and  
packages for greater customer value in high volume consumer, portable, and battery-backed markets.  
Added features include smaller footprint packages designed with two-layer PCBs in mind, low power,  
hot-swap capability, and Schmitt trigger for greater flexibility in low-cost and power-sensitive applications.  
Flash Advantages  
Reduced Cost of Ownership  
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-  
based FPGAs, flash-based ProASIC3 nano devices allow all functionality to be Instant On; no external  
boot PROM is required. On-board security mechanisms prevent access to all the programming  
information and enable secure remote updates of the FPGA logic. Designers can perform secure remote  
in-system reprogramming to support future design iterations and field upgrades with confidence that  
valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using  
the industry-standard AES algorithm. The ProASIC3 nano device architecture mitigates the need for  
ASIC migration at higher user volumes. This makes the ProASIC3 nano device a cost-effective ASIC  
replacement solution, especially for applications in the consumer, networking/communications,  
computing, and avionics markets.  
With a variety of devices under $1, ProASIC3 nano FPGAs enable cost-effective implementation of  
programmable logic and quick time to market.  
Security  
Nonvolatile, flash-based ProASIC3 nano devices do not require a boot PROM, so there is no vulnerable  
external bitstream that can be easily copied. ProASIC3 nano devices incorporate FlashLock, which  
provides a unique combination of reprogrammability and design security without external overhead,  
advantages that only an FPGA with nonvolatile flash programming can offer.  
ProASIC3 nano devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest  
level of protection in the FPGA industry for programmed intellectual property and configuration data. In  
addition, all FlashROM data in ProASIC3 nano devices can be encrypted prior to loading, using the  
industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was  
adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977  
DES standard. ProASIC3 nano devices have a built-in AES decryption engine and a flash-based AES  
key that make them the most comprehensive programmable logic device security solution available  
today. ProASIC3 nano devices with AES-based security provide a high level of protection for remote field  
updates over public networks such as the Internet, and are designed to ensure that valuable IP remains  
out of the hands of system overbuilders, system cloners, and IP thieves.  
Revision 11  
1-1  
ProASIC3 nano Device Overview  
Security, built into the FPGA fabric, is an inherent component of ProASIC3 nano devices. The flash cells  
are located beneath seven metal layers, and many device design and layout techniques have been used  
to make invasive attacks extremely difficult. ProASIC3 nano devices, with FlashLock and AES security,  
are unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is  
protected with industry-standard security, making remote ISP possible. A ProASIC3 nano device  
provides the best available security for programmable logic designs.  
Single Chip  
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the  
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to  
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3 nano  
FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load  
device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and  
system reliability.  
Instant On  
Microsemi flash-based ProASIC3 nano devices support Level 0 of the Instant On classification standard.  
This feature helps in system component initialization, execution of critical tasks before the processor  
wakes up, setup and configuration of memory blocks, clock generation, and bus activity management.  
The Instant On feature of flash-based ProASIC3 nano devices greatly simplifies total system design and  
reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs that are used  
for these purposes in a system. In addition, glitches and brownouts in system power will not corrupt the  
ProASIC3 nano device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to  
be reloaded when system power is restored. This enables the reduction or complete removal of the  
configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from  
the PCB design. Flash-based ProASIC3 nano devices simplify total system design and reduce cost and  
design risk while increasing system reliability and improving system initialization time.  
Firm Errors  
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike  
a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the  
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These  
errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a  
complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 nano flash-  
based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 nano FPGAs  
cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors  
occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection  
and correction (EDAC) circuitry built into the FPGA fabric.  
Low Power  
Flash-based ProASIC3 nano devices exhibit power characteristics similar to an ASIC, making them an  
ideal choice for power-sensitive applications. ProASIC3 nano devices have only a very limited power-on  
current surge and no high-current transition period, both of which occur on many FPGAs.  
ProASIC3 nano devices also have low dynamic power consumption to further maximize power savings.  
Advanced Flash Technology  
ProASIC3 nano devices offer many benefits, including nonvolatility and reprogrammability through an  
advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design  
techniques are used to implement logic and control functions. The combination of fine granularity,  
enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization  
without compromising device routability or performance. Logic functions within the device are  
interconnected through a four-level routing hierarchy.  
1-2  
Revision 11  
ProASIC3 nano Flash FPGAs  
Advanced Architecture  
The proprietary ProASIC3 nano architecture provides granularity comparable to standard-cell ASICs.  
The ProASIC3 nano device consists of five distinct and programmable architectural features (Figure 1-3  
to Figure 1-4 on page 1-4):  
•
•
•
•
•
FPGA VersaTiles  
Dedicated FlashROM  
Dedicated SRAM/FIFO memory  
Extensive CCCs and PLLs  
Advanced I/O structure  
Bank 1*  
I/Os  
VersaTile  
CCC-GL  
User Nonvolatile FlashROM  
Charge Pumps  
Bank 1  
Note: *Bank 0 for the A3PN030 device  
Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O Banks and No RAM  
(A3PN010 and A3PN030)  
Bank 1  
I/Os  
VersaTile  
CCC-GL  
User Nonvolatile FlashROM  
Charge Pumps  
Bank 1  
Figure 1-2 • ProASIC3 nano Architecture Overview with Three I/O Banks and No RAM (A3PN015 and  
A3PN020)  
Revision 11  
1-3  
ProASIC3 nano Device Overview  
Bank 0  
CCC  
RAM Block  
4,608-Bit Dual-Port  
SRAM or FIFO Block  
I/Os  
VersaTile  
ISP AES  
Decryption  
User Nonvolatile  
FlashROM  
Charge Pumps  
Bank 1  
Figure 1-3 • ProASIC3 nano Device Architecture Overview with Two I/O Banks (A3PN060 and A3PN125)  
Bank 0  
CCC  
RAM Block  
4,608-Bit Dual-Port  
SRAM or FIFO Block  
I/Os  
VersaTile  
ISP AES  
Decryption  
User Nonvolatile  
FlashROM  
Charge Pumps  
Bank 2  
Figure 1-4 • ProASIC3 nano Device Architecture Overview with Four I/O Banks (A3PN250)  
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic  
function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch  
interconnections. The versatility of the ProASIC3 nano core tile as either a three-input lookup table (LUT)  
equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile  
capability is unique to the ProASIC3 family of third-generation architecture flash FPGAs. VersaTiles are  
connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the  
device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is  
possible for virtually any design.  
1-4  
Revision 11  
ProASIC3 nano Flash FPGAs  
VersaTiles  
The ProASIC3 nano core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS®  
core tiles. The ProASIC3 nano VersaTile supports the following:  
•
•
•
•
All 3-input logic functions—LUT-3 equivalent  
Latch with clear or set  
D-flip-flop with clear or set  
Enable D-flip-flop with clear or set  
Refer to Figure 1-5 for VersaTile configurations.  
Enable D-Flip-Flop with Clear or Set  
D-Flip-Flop with Clear or Set  
LUT-3 Equivalent  
X1  
Data  
Y
Data  
CLK  
CLR  
Y
X2  
X3  
LUT-3  
Y
D-FF  
CLK  
D-FF  
Enable  
CLR  
Figure 1-5 • VersaTile Configurations  
User Nonvolatile FlashROM  
ProASIC3 nano devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM  
can be used in diverse system applications:  
•
•
•
•
•
•
•
•
Internet protocol addressing (wireless or fixed)  
System calibration settings  
Device serialization and/or inventory control  
Subscription-based business models (for example, set-top boxes)  
Secure key storage for secure communications algorithms  
Asset management/tracking  
Date stamping  
Version management  
The FlashROM is written using the standard ProASIC3 nano IEEE 1532 JTAG programming interface.  
The core can be individually programmed (erased and written), and on-chip AES decryption can be used  
selectively to securely load data over public networks (except in the A3PN030 and smaller devices), as in  
security keys stored in the FlashROM for a user design.  
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read  
back either through the JTAG programming interface or via direct FPGA core addressing. Note that the  
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the  
internal logic array.  
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte  
basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks  
and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the  
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM  
address define the byte.  
The ProASIC3 nano development software solutions, Libero® System-on-Chip (SoC) software and  
Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential  
programming files for applications requiring a unique serial number in each part. Another feature enables  
the inclusion of static data for system version control. Data for the FlashROM can be generated quickly  
and easily using Libero SoC and Designer software tools. Comprehensive programming file support is  
also included to allow for easy programming of large numbers of parts with differing FlashROM contents.  
Revision 11  
1-5  
ProASIC3 nano Device Overview  
SRAM and FIFO  
ProASIC3 nano devices (except the A3PN030 and smaller devices) have embedded SRAM blocks along  
their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available  
memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have  
independent read and write ports that can be configured with different bit widths on each port. For  
example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM  
blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro  
(except in A3PN030 and smaller devices).  
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM  
block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width  
and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and  
Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control  
unit contains the counters necessary for generation of the read and write address pointers. The  
embedded SRAM/FIFO blocks can be cascaded to create larger configurations.  
PLL and CCC  
Higher density ProASIC3 nano devices using either the two I/O bank or four I/O bank architectures  
provide the designer with very flexible clock conditioning capabilities. A3PN060, A3PN125, and  
A3PN250 contain six CCCs. One CCC (center west side) has a PLL. The A3PN030 and smaller devices  
use different CCCs in their architecture. These CCC-GLs contain a global MUX but do not have any  
PLLs or programmable delays.  
For devices using the six CCC block architecture, these six CCC blocks are located at the four corners  
and the centers of the east and west sides.  
All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay  
operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the  
FPGA core or from dedicated connections to the CCC block, which are located near the CCC.  
The CCC block has these key features:  
•
•
•
•
•
Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz  
Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz  
Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns  
2 programmable delay types for clock skew minimization  
Clock frequency synthesis (for PLL only)  
Additional CCC specifications:  
•
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider  
configuration (for PLL only).  
•
•
Output duty cycle = 50% ± 1.5% or better (for PLL only)  
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global  
network used (for PLL only)  
•
•
•
•
Maximum acquisition time = 300 µs (for PLL only)  
Low power consumption of 5 mW  
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only)  
Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /  
f
OUT_CCC) (for PLL only)  
Global Clocking  
ProASIC3 nano devices have extensive support for multiple clocking domains. In addition to the CCC  
and PLL support described above, there is a comprehensive global clock distribution network.  
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant  
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via  
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid  
distribution of high fanout nets.  
1-6  
Revision 11  
ProASIC3 nano Flash FPGAs  
I/Os with Advanced I/O Standards  
ProASIC3 nano FPGAs feature a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V,  
2.5 V, and 3.3 V).  
The I/Os are organized into banks, with two, three, or four banks per device. The configuration of these  
banks determines the I/O standards supported.  
Each I/O module contains several input, output, and enable registers. These registers allow the  
implementation of various single-data-rate applications for all versions of nano devices and double-data-  
rate applications for the A3PN060, A3PN125, and A3PN250 devices.  
ProASIC3 nano devices support LVTTL and LVCMOS I/O standards, are hot-swappable, and support  
cold-sparing and Schmitt trigger.  
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card  
in a powered-up system.  
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed  
when the system is powered up, while the component itself is powered down, or when power supplies  
are floating.  
Wide Range I/O Support  
ProASIC3 nano devices support JEDEC-defined wide range I/O operation. ProASIC3 nano supports the  
JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to  
3.6 V.  
Wider I/O range means designers can eliminate power supplies or power conditioning components from  
the board or move to less costly components with greater tolerances. Wide range eases I/O bank  
management and provides enhanced protection from system voltage spikes, while providing the flexibility  
to easily run custom voltage applications.  
Specifying I/O States During Programming  
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for  
PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.  
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have  
limited display of Pin Numbers only.  
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during  
programming.  
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator  
window appears.  
3. Click the Specify I/O States During Programming button to display the Specify I/O States During  
Programming dialog box.  
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.  
Select the I/Os you wish to modify (Figure 1-6 on page 1-8).  
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings  
for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state  
settings:  
1 – I/O is set to drive out logic High  
0 – I/O is set to drive out logic Low  
Last Known State – I/O is set to the last value that was driven out prior to entering the  
programming mode, and then held at that value during programming  
Revision 11  
1-7  
ProASIC3 nano Device Overview  
Z -Tri-State: I/O is tristated  
Figure 1-6 • I/O States During Programming Window  
6. Click OK to return to the FlashPoint – Programming File Generator window.  
I/O States During programming are saved to the ADB and resulting programming files after completing  
programming file generation.  
1-8  
Revision 11  
2 – ProASIC3 nano DC and Switching Characteristics  
General Specifications  
The Z feature grade does not support the enhanced nano features of Schmitt trigger input, cold-sparing,  
and hot-swap I/O capability. Refer to the "ProASIC3 nano Ordering Information" section on page III for  
more information.  
DC and switching characteristics for –F speed grade targets are based only on simulation.  
The characteristics provided for the –F speed grade are subject to change after establishing FPGA  
specifications. Some restrictions might be added and will be reflected in future revisions of this  
document. The –F speed grade is only supported in the commercial temperature range.  
Operating Conditions  
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.  
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.  
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any  
other conditions beyond those listed under the Recommended Operating Conditions specified in  
Table 2-2 on page 2-2 is not implied.  
Table 2-1 • Absolute Maximum Ratings  
Symbol  
VCC  
Parameter  
DC core supply voltage  
Limits  
–0.3 to 1.65  
–0.3 to 3.75  
–0.3 to 3.75  
–0.3 to 1.65  
–0.3 to 3.75  
–0.3 V to 3.6 V  
–65 to +150  
+125  
Units  
V
VJTAG  
VPUMP  
VCCPLL  
VCCI  
JTAG DC voltage  
V
Programming voltage  
Analog power supply (PLL)  
DC I/O output buffer supply voltage  
I/O input voltage  
V
V
V
VI  
V
1
TSTG  
Storage temperature  
°C  
°C  
1
TJ  
Junction temperature  
Notes:  
1. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating  
limits, refer to Table 2-2 on page 2-2.  
2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on  
page 3-1 for further information.  
3. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may  
undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.  
Revision 11  
2-1  
ProASIC3 nano DC and Switching Characteristics  
Table 2-2 • Recommended Operating Conditions 1, 2  
Extended  
Symbol  
TA  
Parameter  
Commercial  
Industrial  
–40 to +85 2  
–40 to +100  
Units  
°C  
°C  
V
Ambient temperature  
Junction temperature  
–20 to +70 2  
TJ  
–20 to +85  
VCC 3  
VJTAG  
VPUMP 4  
1.5 V DC core supply voltage  
JTAG DC voltage  
1.425 to 1.575 1.425 to 1.575  
1.4 to 3.6  
3.15 to 3.45  
0 to 3.6  
1.4 to 3.6  
3.15 to 3.45  
0 to 3.6  
V
Programming voltage  
Programming Mode4  
Operation 5  
V
V
VCCPLL 6 Analog power supply (PLL) 1.5 V DC core supply voltage 3 1.425 to 1.575 1.425 to 1.575  
V
VCCI and 1.5 V DC supply voltage  
VMV 7  
1.425 to 1.575 1.425 to 1.575  
V
1.8 V DC supply voltage  
2.5 V DC supply voltage  
3.3 V DC supply voltage  
1.7 to 1.9  
2.3 to 2.7  
3.0 to 3.6  
2.7 to 3.6  
1.7 to 1.9  
2.3 to 2.7  
3.0 to 3.6  
2.7 to 3.6  
V
V
V
V
3.3 V Wide Range supply voltage 8  
Notes:  
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.  
2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi  
recommends that the user follow best design practices using Microsemi’s timing and power simulation tools.  
3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O  
standard are given in Table 2-14 on page 2-16. VMV and VCCI should be at the same voltage within a given I/O bank.  
4. The programming temperature range supported is Tambient = 0°C to 85°C.  
5. VPUMP can be left floating during operation (not programming mode).  
6. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions and Packaging" chapter for further information.  
7. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions and Packaging" chapter for  
further information.  
8. 3.3 V Wide Range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.  
Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature1  
Product  
Grade  
Programming Program Retention  
Maximum Storage  
Maximum Operating  
Cycles  
(biased/unbiased) Temperature TSTG (°C) 2 Junction Temperature TJ (°C) 2  
Commercial  
Industrial  
Notes:  
500  
20 years  
20 years  
110  
110  
100  
100  
500  
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.  
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating  
conditions and absolute limits.  
2-2  
Revision 11  
ProASIC3 nano Flash FPGAs  
Table 2-4 • Overshoot and Undershoot Limits 1  
Average VCCI–GND Overshoot or Undershoot  
Maximum Overshoot/  
Undershoot 2  
VCCI and VMV  
Duration as a Percentage of Clock Cycle 2  
2.7 V or less  
10%  
5%  
1.4 V  
1.49 V  
1.1 V  
3 V  
10%  
5%  
1.19 V  
0.79 V  
0.88 V  
0.45 V  
0.54 V  
3.3 V  
3.6 V  
Notes:  
10%  
5%  
10%  
5%  
1. Based on reliability requirements at 85°C.  
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the  
maximum overshoot/undershoot has to be reduced by 0.15 V.  
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset  
(Commercial and Industrial)  
Sophisticated power-up management circuitry is designed into every ProASIC®3 device. These circuits  
ensure easy transition from the powered-off state to the powered-up state of the device. The many  
different supplies can power up in any sequence with minimized current spikes or surges. In addition, the  
I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1  
on page 2-4.  
There are five regions to consider during power-up.  
ProASIC3 I/Os are activated only if ALL of the following three conditions are met:  
1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).  
2. VCCI > VCC – 0.75 V (typical)  
3. Chip is in the operating mode.  
VCCI Trip Point:  
Ramping up: 0.6 V < trip_point_up < 1.2 V  
Ramping down: 0.5 V < trip_point_down < 1.1 V  
VCC Trip Point:  
Ramping up: 0.6 V < trip_point_up < 1.1 V  
Ramping down: 0.5 V < trip_point_down < 1 V  
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically  
built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:  
•
•
During programming, I/Os become tristated and weakly pulled up to VCCI.  
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O  
behavior.  
PLL Behavior at Brownout Condition  
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-  
up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout  
activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4  
for more details).  
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ±  
0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the  
"Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the ProASIC3 nano FPGA Fabric  
User’s Guide for information on clock and lock recovery.  
Revision 11  
2-3  
ProASIC3 nano DC and Switching Characteristics  
Internal Power-Up Activation Sequence  
1. Core  
2. Input buffers  
3. Output buffers, after 200 ns delay from input buffer activation  
VCC = VCCI + VT  
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)  
VCC  
VCC = 1.575 V  
Region 5: I/O buffers are ON  
Region 4: I/O  
Region 1: I/O Buffers are OFF  
and power supplies are within  
specification.  
buffers are ON.  
I/Os are functional  
I/Os meet the entire datasheet  
and timer specifications for  
but slower because VCCI  
is below specification. For the  
same reason, input buffers do  
speed, VIH / VIL , VOH / VOL , etc.  
not meet VIH / VIL levels, and output  
buffers do not meet VOH/VOL levels.  
VCC = 1.425 V  
Region 2: I/O buffers are ON.  
Region 3: I/O buffers are ON.  
I/Os are functional; I/O DC  
specifications are met,  
but I/Os are slower because  
the VCC is below specification.  
I/Os are functional but slower because  
VCCI / VCC are below specification.  
For the same reason, input  
buffers do not meet VIH / VIL levels, and  
output buffers do not meet VOH / VOL levels.  
Activation trip point:  
V = 0.85 V ± 0.25 V  
a
Deactivation trip point:  
Region 1: I/O buffers are OFF  
V
= 0.75 V ± 0.25 V  
d
VCCI  
Activation trip point:  
Min VCCI datasheet specification  
V = 0.9 V ± 0.3 V  
Deactivation trip point:  
voltage at a selected I/O  
standard; i.e., 1.425 V or 1.7 V  
or 2.3 V or 3.0 V  
a
V
= 0.8 V ± 0.3 V  
d
Figure 2-1 • I/O State as a Function of VCCI and VCC Voltage Levels  
2-4  
Revision 11  
ProASIC3 nano Flash FPGAs  
Thermal Characteristics  
Introduction  
The temperature variable in the Designer software refers to the junction temperature, not the ambient  
temperature. This is an important distinction because dynamic and static power consumption cause the  
chip junction to be higher than the ambient temperature.  
EQ 1 can be used to calculate junction temperature.  
TJ = Junction Temperature = T + TA  
EQ 1  
where:  
TA = Ambient Temperature  
T = Temperature gradient between junction (silicon) and ambient T = ja * P  
ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5.  
P = Power dissipation  
Package Thermal Characteristics  
The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is  
ja. The thermal characteristics for ja are shown for two air flow rates. The absolute maximum junction  
temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation  
allowed for a 484-pin FBGA package at commercial temperature and in still air.  
·
Max. junction temp. (C) – Max. ambient temp. (C) 100C – 70C  
Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------------------ =  
ja(C/W)  
= 1.463 W  
-------------------------------------  
20.5C/W  
EQ 2  
Table 2-5 • Package Thermal Resistivities  
ja  
Package Type  
Device  
Pin Count jc  
Still Air 200 ft./min. 500 ft./min. Units  
Quad Flat No Lead (QFN)  
All devices  
48  
68  
TBD  
TBD  
TBD  
10.0  
TBD  
TBD  
TBD  
35.3  
TBD  
TBD  
TBD  
29.4  
TBD  
TBD  
TBD  
27.1  
C/W  
C/W  
C/W  
C/W  
100  
100  
Very Thin Quad Flat Pack (VQFP)  
All devices  
Temperature and Voltage Derating Factors  
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays  
(normalized to TJ = 70°C, VCC = 1.425 V)  
Junction Temperature (°C)  
Array Voltage VCC (V)  
–40°C  
0.968  
0.888  
0.836  
–20°C  
0.973  
0.894  
0.841  
0°C  
25°C  
0.991  
0.910  
0.856  
70°C  
1.000  
0.919  
0.864  
85°C  
100°C  
1.425  
1.500  
1.575  
0.979  
0.899  
0.845  
1.006  
0.924  
0.870  
1.013  
0.930  
0.875  
Revision 11  
2-5  
ProASIC3 nano DC and Switching Characteristics  
Calculating Power Dissipation  
Quiescent Supply Current  
Table 2-7 • Quiescent Supply Current Characteristics  
A3PN010 A3PN015 A3PN020 A3PN060 A3PN125  
A3PN250  
3 mA  
Typical (25°C)  
600 µA  
5 mA  
1 mA  
5 mA  
8 mA  
1 mA  
5 mA  
8 mA  
2 mA  
10 mA  
15 mA  
2 mA  
10 mA  
15 mA  
Max. (Commercial)  
Max. (Industrial)  
20 mA  
30 mA  
8 mA  
Note: IDD includes VCC, VPUMP, and VCCI, currents.  
Power per I/O Pin  
Table 2-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings  
VCCI (V)  
Dynamic Power, PAC9 (µW/MHz)1  
Single-Ended  
3.3 V LVTTL / 3.3 V LVCMOS  
3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger  
3.3 V LVCMOS wide range2  
3.3 V LVCMOS wide range – Schmitt Trigger  
2.5 V LVCMOS  
3.3  
3.3  
3.3  
3.3  
2.5  
2.5  
1.8  
1.8  
1.5  
1.5  
16.45  
18.93  
16.45  
18.93  
4.73  
2.5 V LVCMOS – Schmitt Trigger  
1.8 V LVCMOS  
6.14  
1.68  
1.8 V LVCMOS – Schmitt Trigger  
1.5 V LVCMOS (JESD8-11)  
1.5 V LVCMOS (JESD8-11) – Schmitt Trigger  
Notes:  
1.80  
0.99  
0.96  
1. PAC9 is the total dynamic power measured on VCCI.  
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B  
specification.  
2-6  
Revision 11  
ProASIC3 nano Flash FPGAs  
Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1  
CLOAD (pF) 2  
VCCI (V) Dynamic Power, PAC10 (µW/MHz)3  
Single-Ended  
3.3 V LVTTL / 3.3 V LVCMOS  
3.3 V LVCMOS wide range4  
2.5 V LVCMOS  
10  
10  
10  
10  
10  
3.3  
3.3  
2.5  
1.8  
1.5  
162.01  
162.01  
91.96  
46.95  
32.22  
1.8 V LVCMOS  
1.5 V LVCMOS (JESD8-11)  
Notes:  
1. Dynamic power consumption is given for standard load and software default drive strength and output  
slew.  
2. Values for A3PN020, A3PN015, and A3PN010. A3PN060, A3PN125, and A3PN250 correspond to a  
default loading of 35 pF.  
3. PAC10 is the total dynamic power measured on VCCI.  
4. All LVCMOS3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B  
specification.  
Revision 11  
2-7  
ProASIC3 nano DC and Switching Characteristics  
Power Consumption of Various Internal Resources  
Table 2-10 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 nano Devices  
Device Specific Dynamic Contributions  
(µW/MHz)  
Parameter  
PAC1  
Definition  
Clock contribution of a Global Rib  
Clock contribution of a Global Spine  
Clock contribution of a VersaTile row  
11.03  
1.58  
11.03  
0.81  
9.3  
9.3  
0.4  
9.3  
0.4  
9.3  
0.4  
PAC2  
0.81  
PAC3  
0.81  
PAC4  
Clock contribution of a VersaTile used as a  
sequential module  
0.12  
0.07  
0.29  
0.29  
0.70  
PAC5  
PAC6  
PAC7  
First contribution of a VersaTile used as a  
sequential module  
Second contribution of a VersaTile used as a  
sequential module  
Contribution of a VersaTile used as a  
combinatorial Module  
PAC8  
PAC9  
Average contribution of a routing net  
Contribution of an I/O input pin  
(standard-dependent)  
See Table 2-8 on page 2-6.  
PAC10  
PAC11  
PAC12  
PAC13  
Contribution of an I/O output pin  
(standard-dependent)  
See Table 2-9 on page 2-7.  
Average contribution of a RAM block during a read  
operation  
25.00  
30.00  
2.60  
N/A  
Average contribution of a RAM block during a write  
operation  
N/A  
Dynamic contribution for PLL  
N/A  
Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power  
spreadsheet calculator or SmartPower tool in Libero SoC.  
Table 2-11 • Different Components Contributing to the Static Power Consumption in ProASIC3 nano Devices  
Device Specific Static Power (mW)  
Parameter  
PDC1  
Definition  
Array static power in Active mode  
Static PLL contribution 1  
See Table 2-7 on page 2-6.  
2.55 N/A  
See Table 2-7 on page 2-6.  
PDC4  
PDC5  
Bank quiescent power (VCCI-dependent)  
Notes:  
1. Minimum contribution of the PLL when running at lowest frequency.  
2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power spreadsheet  
calculator or SmartPower tool in Libero SoC.  
2-8  
Revision 11  
ProASIC3 nano Flash FPGAs  
Power Calculation Methodology  
This section describes a simplified method to estimate power consumption of an application. For more  
accurate and detailed power estimations, use the SmartPower tool in Libero SoC.  
The power calculation methodology described below uses the following variables:  
•
•
•
•
•
•
The number of PLLs as well as the number and the frequency of each output clock generated  
The number of combinatorial and sequential cells used in the design  
The internal clock frequencies  
The number and the standard of I/O pins used in the design  
The number of RAM blocks used in the design  
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-12 on  
page 2-11.  
•
•
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-13 on  
page 2-11.  
Read rate and write rate to the memory—guidelines are provided for typical applications in  
Table 2-13 on page 2-11. The calculation should be repeated for each clock domain defined in the  
design.  
Methodology  
Total Power Consumption—P  
TOTAL  
PTOTAL = PSTAT + PDYN  
PSTAT is the total static power consumption.  
DYN is the total dynamic power consumption.  
Total Static Power Consumption—P  
P
STAT  
PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3  
NINPUTS is the number of I/O input buffers used in the design.  
NOUTPUTS is the number of I/O output buffers used in the design.  
Total Dynamic Power Consumption—P  
DYN  
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL  
Global Clock Contribution—P  
CLOCK  
PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK  
NSPINE is the number of global spines used in the user design—guidelines are provided in the "Spine  
Architecture" section of the Global Resources chapter in the ProASIC3 nano FPGA Fabric User's  
Guide.  
NROW is the number of VersaTile rows used in the design—guidelines are provided in the "Spine  
Architecture" section of the Global Resources chapter in the ProASIC3 nano FPGA Fabric User's  
Guide.  
FCLK is the global clock signal frequency.  
NS-CELL is the number of VersaTiles used as sequential modules in the design.  
PAC1, PAC2, PAC3, and PAC4 are device-dependent.  
Sequential Cells Contribution—P  
S-CELL  
PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK  
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile  
sequential cell is used, it should be accounted for as 1.  
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11.  
FCLK is the global clock signal frequency.  
Revision 11  
2-9  
ProASIC3 nano DC and Switching Characteristics  
Combinatorial Cells Contribution—P  
C-CELL  
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK  
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.  
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11.  
FCLK is the global clock signal frequency.  
Routing Net Contribution—P  
NET  
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK  
NS-CELL is the number of VersaTiles used as sequential modules in the design.  
N
C-CELL is the number of VersaTiles used as combinatorial modules in the design.  
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11.  
CLK is the global clock signal frequency.  
I/O Input Buffer Contribution—P  
F
INPUTS  
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK  
NINPUTS is the number of I/O input buffers used in the design.  
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-12 on page 2-11.  
FCLK is the global clock signal frequency.  
I/O Output Buffer Contribution—P  
OUTPUTS  
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK  
NOUTPUTS is the number of I/O output buffers used in the design.  
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-12 on page 2-11.  
1 is the I/O buffer enable rate—guidelines are provided in Table 2-13 on page 2-11.  
FCLK is the global clock signal frequency.  
RAM Contribution—P  
MEMORY  
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3  
NBLOCKS is the number of RAM blocks used in the design.  
F
READ-CLOCK is the memory read clock frequency.  
2 is the RAM enable rate for read operations.  
WRITE-CLOCK is the memory write clock frequency.  
3 is the RAM enable rate for write operations—guidelines are provided in Table 2-13 on page 2-11.  
PLL Contribution—P  
F
PLL  
PPLL = PDC4 + PAC13 * FCLKOUT  
FCLKOUT is the output clock frequency.1  
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the  
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output  
clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.  
2-10  
Revision 11  
ProASIC3 nano Flash FPGAs  
Guidelines  
Toggle Rate Definition  
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the  
toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are  
some examples:  
•
The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the  
clock frequency.  
•
The average toggle rate of an 8-bit counter is 25%:  
–
–
–
–
–
–
Bit 0 (LSB) = 100%  
Bit 1  
Bit 2  
…
= 50%  
= 25%  
Bit 7 (MSB) = 0.78125%  
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8  
Enable Rate Definition  
Output enable rate is the average percentage of time during which tristate outputs are enabled. When  
nontristate output buffers are used, the enable rate should be 100%.  
Table 2-12 • Toggle Rate Guidelines Recommended for Power Calculation  
Component  
Definition  
Toggle rate of VersaTile outputs  
I/O buffer toggle rate  
Guideline  
10%  
1  
2  
10%  
Table 2-13 • Enable Rate Guidelines Recommended for Power Calculation  
Component  
Definition  
I/O output buffer enable rate  
Guideline  
100%  
1  
2  
3  
RAM enable rate for read operations  
RAM enable rate for write operations  
12.5%  
12.5%  
Revision 11  
2-11  
ProASIC3 nano DC and Switching Characteristics  
User I/O Characteristics  
Timing Model  
I/O Module  
(Non-Registered)  
Combinational Cell  
Combinational Cell  
Y
LVCMOS 2.5V Output Drive  
Strength = 8 mA High Slew Rate  
Y
t
= 0.56 ns  
t
= 0.49 ns  
PD  
PD  
t
= 2.25 ns  
DP  
I/O Module  
(Non-Registered)  
Combinational Cell  
Y
Output drive strength = 4 mA  
High slew rate  
LVTTL  
t
= 2.87 ns  
DP  
t
= 0.87 ns  
PD  
I/O Module  
(Non-Registered)  
Combinational Cell  
Y
I/O Module  
(Registered)  
Output drive strength = 8 mA  
High slew rate  
LVTTL  
t
= 1.04 ns  
PY  
t
= 2.21 ns  
DP  
t
= 0.51 ns  
PD  
I/O Module  
(Non-Registered)  
Input LVCMOS 2.5 V  
D
Q
Combinational Cell  
Y
Output drive strength = 2 mA  
High slew rate  
LVCMOS 1.5 V  
t
t
= 0.24 ns  
= 0.26 ns  
ICLKQ  
ISUD  
t
= 3.02 ns  
DP  
t
= 0.47 ns  
PD  
Input LVTTL  
Clock  
I/O Module  
Register Cell  
(Registered)  
Register Cell  
Combinational Cell  
Y
t
= 0.84 ns  
PY  
D
Q
D
Q
D
t
Q
LVTTL 3.3 V Output drive  
strength = 8 mA High slew rate  
I/O Module  
t
= 0.47 ns  
PD  
t
= 2.21 ns  
(Non-Registered)  
DP  
t
t
= 0.55 ns  
= 0.43 ns  
= 0.59 ns  
= 0.31 ns  
t
t
= 0.55 ns  
= 0.43 ns  
CLKQ  
OCLKQ  
CLKQ  
t
SUD  
LVCMOS 1.5 V  
OSUD  
SUD  
Input LVTTL  
Clock  
Input LVTTL  
Clock  
t
= 1.14 ns  
PY  
t
= 0.84 ns  
t
= 0.84 ns  
PY  
PY  
Figure 2-2 • Timing Model  
Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst Case  
VCC = 1.425 V, with Default Loading at 10 pF  
2-12  
Revision 11  
ProASIC3 nano Flash FPGAs  
tPY  
tDIN  
D
Q
PAD  
DIN  
Y
CLK  
To Array  
I/O Interface  
t
t
PY = MAX(tPY(R), tPY(F))  
DIN = MAX(tDIN(R), tDIN(F))  
VIH  
Vtrip  
Vtrip  
VIL  
PAD  
VCC  
50%  
50%  
Y
GND  
tPY  
(R)  
tPY  
(F)  
VCC  
50%  
50%  
DIN  
tDIN  
(R)  
GND  
tDIN  
(F)  
Figure 2-3 • Input Buffer Timing Model and Delays (example)  
Revision 11  
2-13  
ProASIC3 nano DC and Switching Characteristics  
tDOUT  
D Q  
tDP  
PAD  
DOUT  
CLK  
Std  
Load  
D
From Array  
tDP = MAX(tDP(R), tDP(F))  
tDOUT = MAX(tDOUT(R), tDOUT(F))  
I/O Interface  
tDOUT  
(R)  
tDOUT  
(F)  
VCC  
50%  
50%  
VCC  
D
0 V  
50%  
50%  
DOUT  
PAD  
0 V  
VOH  
Vtrip  
VOL  
Vtrip  
tDP  
(R)  
tDP  
(F)  
Figure 2-4 • Output Buffer Model and Delays (example)  
2-14  
Revision 11  
ProASIC3 nano Flash FPGAs  
t
EOUT  
D
Q
CLK  
t
, t , t , t , t , t  
E
ZL ZH HZ LZ ZLS ZHS  
EOUT  
D
Q
PAD  
DOUT  
CLK  
D
t
= MAX(t  
(r), t (f))  
EOUT  
I/O Interface  
EOUT  
EOUT  
VCC  
D
E
VCC  
50%  
t
50%  
t
EOUT (F)  
EOUT (R)  
VCC  
50%  
50%  
50%  
ZH  
50%  
t
LZ  
EOUT  
PAD  
t
t
t
ZL  
HZ  
VCCI  
90% VCCI  
Vtrip  
Vtrip  
VOL  
10% V  
CCI  
VCC  
D
E
VCC  
50%  
50%  
50%  
t
t
EOUT (F)  
EOUT (R)  
VCC  
50%  
EOUT  
PAD  
50%  
VOH  
t
ZHS  
t
ZLS  
Vtrip  
Vtrip  
VOL  
Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)  
Revision 11  
2-15  
ProASIC3 nano DC and Switching Characteristics  
Overview of I/O Performance  
Summary of I/O DC Input and Output Levels – Default I/O Software  
Settings  
Table 2-14 • Summary of Maximum and Minimum DC Input and Output Levels  
Applicable to Commercial and Industrial Conditions—Software Default Settings  
Equivalent  
Software  
VIL  
VIH  
VOL  
VOH  
IOL1 IOH1  
Default  
Drive  
Drive  
Strength Slew Min.  
Max  
V
Min.  
V
Max.  
V
Min.  
V
I/O Standard Strength Option2 Rate  
V
Max. V  
mA mA  
3.3 V LVTTL/ 8 mA  
3.3 V  
LVCMOS  
8 mA  
High –0.3  
High –0.3  
High –0.3  
0.8  
2
3.6  
3.6  
3.6  
0.4  
2.4  
8
8
3.3 V  
100 µA  
8 mA  
0.8  
0.7  
2
0.2  
VCCI – 0.2 100 100  
µA µA  
LVCMOS  
Wide Range  
2.5 V  
LVCMOS  
8 mA  
4 mA  
2 mA  
8 mA  
4 mA  
2 mA  
1.7  
0.7  
1.7  
8
4
2
8
4
2
1.8 V  
LVCMOS  
High –0.3 0.35 * VCCI 0.65 * VCCI 3.6  
0.45  
VCCI – 0.45  
1.5 V  
High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI  
LVCMOS  
Notes:  
1. Currents are measured at 85°C junction temperature.  
2. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive  
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.  
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.  
Table 2-15 • Summary of Maximum and Minimum DC Input Levels  
Applicable to Commercial and Industrial Conditions  
Commercial 1  
Industrial 2  
IIL 3  
IIH 4  
µA  
10  
IIL 3  
µA  
15  
IIH 4  
µA  
15  
DC I/O Standards  
3.3 V LVTTL / 3.3 V LVCMOS  
3.3 V LVCMOS Wide Range  
2.5 V LVCMOS  
µA  
10  
10  
10  
10  
10  
10  
15  
15  
10  
15  
15  
1.8 V LVCMOS  
10  
15  
15  
1.5 V LVCMOS  
10  
15  
15  
Notes:  
1. Commercial range (–20°C < T < 70°C)  
A
2. Industrial range (–40°C < T < 85°C)  
A
3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.  
4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is  
larger when operating outside recommended ranges.  
2-16  
Revision 11  
ProASIC3 nano Flash FPGAs  
Summary of I/O Timing Characteristics – Default I/O Software Settings  
Table 2-16 • Summary of AC Measuring Points  
Standard  
Measuring Trip Point (Vtrip)  
3.3 V LVTTL / 3.3 V LVCMOS  
3.3 V LVCMOS Wide Range  
2.5 V LVCMOS  
1.4 V  
1.4 V  
1.2 V  
1.8 V LVCMOS  
0.90 V  
0.75 V  
1.5 V LVCMOS  
Table 2-17 • I/O AC Parameter Definitions  
Parameter  
Parameter Definition  
Data to Pad delay through the Output Buffer  
Pad to Data delay through the Input Buffer  
tDP  
tPY  
tDOUT  
tEOUT  
tDIN  
tHZ  
Data to Output Buffer delay through the I/O interface  
Enable to Output Buffer Tristate Control delay through the I/O interface  
Input Buffer to Data delay through the I/O interface  
Enable to Pad delay through the Output Buffer—HIGH to Z  
Enable to Pad delay through the Output Buffer—Z to HIGH  
Enable to Pad delay through the Output Buffer—LOW to Z  
Enable to Pad delay through the Output Buffer—Z to LOW  
Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH  
Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW  
tZH  
tLZ  
tZL  
tZHS  
tZLS  
Revision 11  
2-17  
ProASIC3 nano DC and Switching Characteristics  
Table 2-18 • Summary of I/O Timing Characteristics—Software Default Settings (at 35 pF)  
STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V  
For A3PN060, A3PN125, and A3PN250  
I/O Standard  
3.3 V LVTTL /  
3.3 V LVCMOS  
8
8 mA High  
35  
35  
0.60 4.57 0.04 1.13 1.52 0.43 4.64 3.92 2.60 3.14  
0.60 6.78 0.04 1.57 2.18 0.43 6.78 5.72 3.72 4.35  
3.3 V LVCMOS  
Wide Range  
100 µA 8 mA High  
2.5 V LVCMOS  
1.8 V LVCMOS  
1.5 V LVCMOS  
Notes:  
8
4
2
8 mA High  
4 mA High  
2 mA High  
35  
35  
35  
0.60 4.94 0.04 1.43 1.63 0.43 4.71 4.94 2.60 2.98  
0.60 6.53 0.04 1.35 1.90 0.43 5.53 6.53 2.62 2.89  
0.60 7.86 0.04 1.56 2.14 0.43 6.45 7.86 2.66 2.83  
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive  
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.  
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.  
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Table 2-19 • Summary of I/O Timing Characteristics—Software Default Settings (at 10 pF)  
STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V  
For A3PN020, A3PN015, and A3PN010  
I/O Standard  
3.3 V LVTTL /  
3.3 V LVCMOS  
8
8 mA High  
10  
10  
0.60 2.73 0.04 1.13 1.52 0.43 2.77 2.23 2.60 3.14  
0.60 3.94 0.04 1.57 2.18 0.43 3.94 3.16 3.72 4.35  
3.3 V LVCMOS  
Wide Range  
100 µA 8 mA High  
2.5 V LVCMOS  
1.8 V LVCMOS  
1.5 V LVCMOS  
Notes:  
8
4
2
8 mA High  
4 mA High  
2 mA High  
10  
10  
10  
0.60 2.76 0.04 1.43 1.63 0.43 2.80 2.60 2.60 2.98  
0.60 3.22 0.04 1.35 1.90 0.43 3.24 3.22 2.62 2.89  
0.60 3.76 0.04 1.56 2.14 0.43 3.74 3.76 2.66 2.83  
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive  
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.  
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.  
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
2-18  
Revision 11  
ProASIC3 nano Flash FPGAs  
Detailed I/O DC Characteristics  
Table 2-20 • Input Capacitance  
Symbol  
CIN  
Definition  
Input capacitance  
Input capacitance on the clock pin  
Conditions  
Min. Max. Units  
VIN = 0, f = 1.0 MHz  
VIN = 0, f = 1.0 MHz  
8
8
pF  
pF  
CINCLK  
Table 2-21 • I/O Output Buffer Maximum Resistances 1  
RPULL-DOWN  
RPULL-UP  
Standard  
Drive Strength  
()2  
100  
100  
50  
()3  
3.3 V LVTTL / 3.3 V LVCMOS  
2 mA  
4 mA  
300  
300  
150  
150  
6 mA  
8 mA  
50  
3.3 V LVCMOS Wide Range  
2.5 V LVCMOS  
100 µA  
Same as equivalent  
software default drive  
2 mA  
4 mA  
6 mA  
8 mA  
2 mA  
4 mA  
2 mA  
100  
100  
50  
200  
200  
100  
100  
225  
112  
224  
50  
1.8 V LVCMOS  
200  
100  
200  
1.5 V LVCMOS  
Notes:  
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance  
values depend on VCCI, drive strength selection, temperature, and process. For board design  
considerations and detailed output buffer resistances, use the corresponding IBIS models, located at  
http://www.microsemi.com/soc/download/ibis/default.aspx.  
2.  
3.  
R
R
= (VOLspec) / IOLspec  
(PULL-DOWN-MAX)  
= (VCCImax – VOHspec) / IOHspec  
(PULL-UP-MAX)  
Table 2-22 • I/O Weak Pull-Up/Pull-Down Resistances  
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values  
1
2
R(WEAK PULL-UP)  
R(WEAK PULL-DOWN)  
()  
()  
VCCI  
Min.  
Max.  
45 K  
45 K  
55 K  
70 K  
90 K  
Min.  
10 K  
10 K  
12 K  
17 K  
19 K  
Max.  
45 K  
3.3 V  
10 K  
10 K  
11 K  
18 K  
19 K  
3.3 V (wide range I/Os)  
45 K  
2.5 V  
1.8 V  
1.5 V  
Notes:  
74 K  
110 K  
140 K  
1.  
2.  
R
R
= (VCCImax – VOHspec) / I  
(WEAK PULL-UP-MAX)  
(WEAK PULL-UP-MIN)  
= (VOLspec) / I  
(WEAK PULLDOWN-MAX)  
(WEAK PULLDOWN-MIN)  
Revision 11  
2-19  
ProASIC3 nano DC and Switching Characteristics  
Table 2-23 • I/O Short Currents IOSH/IOSL  
Drive Strength  
IOSL (mA)*  
IOSH (mA)*  
3.3 V LVTTL / 3.3 V LVCMOS  
2 mA  
4 mA  
25  
25  
51  
51  
27  
27  
54  
54  
6 mA  
8 mA  
3.3 V LVCMOS Wide Range  
2.5 V LVCMOS  
100 µA  
Same as equivalent software  
default drive  
2 mA  
4 mA  
6 mA  
8 mA  
2 mA  
4 mA  
2 mA  
16  
16  
32  
32  
9
18  
18  
37  
37  
11  
22  
16  
1.8 V LVCMOS  
17  
13  
1.5 V LVCMOS  
Note: *TJ = 100°C  
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The  
reliability data below is based on a 3.3 V, 8 mA I/O setting, which is the worst case for this type of  
analysis.  
For example, at 100°C, the short current condition would have to be sustained for more than six months  
to cause a reliability concern. The I/O design does not contain any short circuit protection, but such  
protection would only be needed in extremely prolonged stress conditions.  
Table 2-24 • Duration of Short Circuit Event before Failure  
Temperature  
–40°C  
–20°C  
0°C  
Time before Failure  
> 20 years  
> 20 years  
> 20 years  
> 20 years  
5 years  
25°C  
70°C  
85°C  
2 years  
100°C  
6 months  
2-20  
Revision 11  
ProASIC3 nano Flash FPGAs  
Table 2-25 • Schmitt Trigger Input Hysteresis  
Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers  
Input Buffer Configuration  
Hysteresis Value (typ.)  
240 mV  
3.3 V LVTTL / LVCMOS (Schmitt trigger mode)  
2.5 V LVCMOS (Schmitt trigger mode)  
1.8 V LVCMOS (Schmitt trigger mode)  
1.5 V LVCMOS (Schmitt trigger mode)  
140 mV  
80 mV  
60 mV  
Table 2-26 • I/O Input Rise Time, Fall Time, and Related I/O Reliability  
Input Buffer  
Input Rise/Fall Time (min.) Input Rise/Fall Time (max.)  
Reliability  
LVTTL/LVCMOS  
(Schmitt trigger  
disabled)  
No requirement  
No requirement  
10 ns *  
20 years (100°C)  
LVTTL/LVCMOS  
(Schmitt trigger  
enabled)  
No requirement, but input  
noise voltage cannot exceed  
Schmitt hysteresis  
20 years (100°C)  
Note: The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the  
noise is low, then the rise time and fall time of input buffers can be increased beyond the  
maximum value. The longer the rise/fall times, the more susceptible the input signal is to the  
board noise. Microsemi recommends signal integrity evaluation/characterization of the system to  
ensure that there is no excessive noise coupling into input signals.  
Revision 11  
2-21  
ProASIC3 nano DC and Switching Characteristics  
Single-Ended I/O Characteristics  
3.3 V LVTTL / 3.3 V LVCMOS  
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V  
applications. It uses an LVTTL input buffer and push-pull output buffer.  
Table 2-27 • Minimum and Maximum DC Input and Output Levels  
3.3 V LVTTL /  
3.3 V LVCMOS  
VIL  
VIH  
VOL  
VOH IOL IOH  
Min.  
IOSL  
IOSH  
IIL1 IIH2  
Min.  
V
Max.  
V
Min.  
V
Max.  
V
Max.  
V
Max.  
mA3  
Max.  
mA3  
Drive Strength  
2 mA  
V
mA mA  
µA4 µA4  
10 10  
10 10  
10 10  
10 10  
–0.3  
–0.3  
–0.3  
–0.3  
0.8  
0.8  
0.8  
0.8  
2
2
2
2
3.6  
3.6  
3.6  
3.6  
0.4  
0.4  
0.4  
0.4  
2.4  
2.4  
2.4  
2.4  
2
4
6
2
4
6
8
25  
25  
51  
51  
27  
27  
54  
54  
4 mA  
6 mA  
8 mA  
8
Notes:  
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.  
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is  
larger when operating outside recommended ranges.  
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.  
4. Currents are measured at 85°C junction temperature.  
5. Software default selection highlighted in gray.  
R to VCCI for tLZ / tZL / tZLS  
R = 1 k  
Test Point  
Datapath  
R to GND for tHZ / tZH / tZHS  
Test Point  
35 pF  
Enable Path  
35 pF for tZH / tZHS / tZL / tZLS  
35 pF for tHZ / tLZ  
Figure 2-6 • AC Loading  
Table 2-28 • 3.3 V LVTTL/LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads  
Input LOW (V)  
Input HIGH (V)  
Measuring Point* (V)  
CLOAD (pF)  
0
3.3  
1.4  
10  
Notes:  
1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points.  
2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.  
2-22  
Revision 11  
ProASIC3 nano Flash FPGAs  
Timing Characteristics  
Table 2-29 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V  
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250  
Drive  
Speed  
Strength  
Grade  
Std.  
–1  
tDOUT  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
tDP  
tDIN  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
tPY  
tPYS  
1.52  
1.29  
1.13  
1.52  
1.29  
1.13  
1.52  
1.29  
1.13  
1.52  
1.29  
1.13  
tEOUT  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
tZL  
tZH  
tLZ  
tHZ  
Units  
ns  
2 mA  
4 mA  
6 mA  
8 mA  
9.70  
8.26  
7.25  
9.70  
8.26  
7.25  
6.90  
5.87  
5.15  
6.90  
5.87  
5.15  
1.13  
0.96  
0.84  
1.13  
0.96  
0.84  
1.13  
0.96  
0.84  
1.13  
0.96  
0.84  
9.88  
8.40  
7.37  
9.88  
8.40  
7.37  
7.01  
5.97  
5.24  
7.01  
5.97  
5.24  
8.82  
7.50  
6.59  
8.82  
7.50  
6.59  
6.22  
5.29  
4.64  
6.22  
5.29  
4.64  
2.31  
1.96  
1.72  
2.31  
1.96  
1.72  
2.61  
2.22  
1.95  
2.61  
2.22  
1.95  
2.50  
2.13  
1.87  
2.50  
2.13  
1.87  
3.01  
2.56  
2.25  
3.01  
2.56  
2.25  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Table 2-30 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V  
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250  
Drive  
Strength  
Speed  
Grade  
tDOUT  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
tDP  
tDIN  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
tPY  
tPYS  
1.52  
1.29  
1.13  
1.52  
1.29  
1.13  
1.52  
1.29  
1.13  
1.52  
1.29  
1.13  
tEOUT  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
tZL  
tZH  
tLZ  
tHZ  
Units  
ns  
2 mA  
4 mA  
6 mA  
8 mA  
Notes:  
Std.  
–1  
7.19  
6.12  
5.37  
7.19  
6.12  
5.37  
4.57  
3.89  
3.41  
4.57  
3.89  
3.41  
1.13  
0.96  
0.84  
1.13  
0.96  
0.84  
1.13  
0.96  
0.84  
1.13  
0.96  
0.84  
7.32  
6.22  
5.46  
7.32  
6.22  
5.46  
4.64  
3.95  
3.47  
4.64  
3.95  
3.47  
6.40  
5.44  
4.78  
6.40  
5.44  
4.78  
3.92  
3.33  
2.93  
3.92  
3.33  
2.93  
2.30  
1.96  
1.72  
2.30  
1.96  
1.72  
2.60  
2.22  
1.95  
2.60  
2.22  
1.95  
2.62  
2.23  
1.96  
2.62  
2.23  
1.96  
3.14  
2.67  
2.34  
3.14  
2.67  
2.34  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
1. Software default selection highlighted in gray.  
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Revision 11  
2-23  
ProASIC3 nano DC and Switching Characteristics  
Table 2-31 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V  
Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010  
Drive  
Strength  
Speed  
Grade  
tDOUT  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
tDP  
tDIN  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
tPY  
tPYS  
1.52  
1.29  
1.13  
1.52  
1.29  
1.13  
1.52  
1.29  
1.13  
1.52  
1.29  
1.13  
tEOUT  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
tZL  
tZH  
tLZ  
tHZ  
Units  
ns  
2 mA  
4 mA  
6 mA  
8 mA  
Std.  
–1  
5.48  
4.66  
4.09  
5.48  
4.66  
4.09  
4.33  
3.69  
3.24  
4.33  
3.69  
3.24  
1.13  
0.96  
0.84  
1.13  
0.96  
0.84  
1.13  
0.96  
0.84  
1.13  
0.96  
0.84  
5.58  
4.74  
4.16  
5.58  
4.74  
4.16  
4.40  
3.75  
3.29  
4.40  
3.75  
3.29  
5.21  
4.43  
3.89  
5.21  
4.43  
3.89  
4.14  
3.52  
3.09  
4.14  
3.52  
3.09  
2.31  
1.96  
1.72  
2.31  
1.96  
1.72  
2.61  
2.22  
1.95  
2.61  
2.22  
1.95  
2.50  
2.13  
1.87  
2.50  
2.13  
1.87  
3.01  
2.56  
2.25  
3.01  
2.56  
2.25  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Table 2-32 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V  
Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010  
Drive  
Strength  
Speed  
Grade  
tDOUT  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
tDP  
tDIN  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
tPY  
tPYS  
1.52  
1.29  
1.13  
1.52  
1.29  
1.13  
1.52  
1.29  
1.13  
1.52  
129  
tEOUT  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
tZL  
tZH  
tLZ  
tHZ  
Units  
ns  
2 mA  
4 mA  
6 mA  
8 mA  
Notes:  
Std.  
–1  
3.56  
3.03  
2.66  
3.56  
3.03  
2.66  
2.73  
2.32  
2.04  
2.73  
2.32  
2.04  
1.13  
0.96  
0.84  
1.13  
0.96  
0.84  
1.13  
0.96  
0.84  
1.13  
0.96  
0.84  
3.62  
3.08  
2.70  
3.62  
3.08  
2.70  
2.77  
2.36  
2.07  
2.77  
2.36  
2.07  
3.03  
2.58  
2.26  
3.03  
2.58  
2.26  
2.23  
1.90  
1.67  
2.23  
1.90  
1.67  
2.30  
1.96  
1.72  
2.30  
1.96  
1.72  
2.60  
2.22  
1.95  
2.60  
2.22  
1.95  
2.62  
2.23  
1.96  
2.62  
2.23  
1.96  
3.14  
2.67  
2.34  
3.14  
2.67  
2.34  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
1.13  
ns  
1. Software default selection highlighted in gray.  
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
2-24  
Revision 11  
ProASIC3 nano Flash FPGAs  
3.3 V LVCMOS Wide Range  
Table 2-33 • Minimum and Maximum DC Input and Output Levels for 3.3 V LVCMOS Wide Range  
3.3 V LVCMOS Equivalent  
Wide Range  
Software  
Default  
Drive  
VIL  
VIH  
VOL  
VOH  
IOL IOH IIL1 IIH2  
Strength  
Min.  
V
Max.  
V
Min.  
V
Max.  
V
Max.  
V
Min.  
V
Drive Strength  
100 µA  
Option3  
mA mA µA4 µA4  
2 mA  
4 mA  
6 mA  
8 mA  
–0.3  
–0.3  
–0.3  
–0.3  
0.8  
0.8  
0.8  
0.8  
2
2
2
2
3.6  
3.6  
3.6  
3.6  
0.2  
0.2  
0.2  
0.2  
VDD – 0.2 100 100 10  
VDD – 0.2 100 100 10  
VDD – 0.2 100 100 10  
VDD – 0.2 100 100 10  
10  
10  
10  
10  
100 µA  
100 µA  
100 µA  
Notes:  
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.  
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is  
larger when operating outside recommended ranges.  
3. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive  
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.  
4. Currents are measured at 85°C junction temperature.  
5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V Wide Range, as specified in the JESD8-B specification.  
6. Software default selection highlighted in gray.  
Revision 11  
2-25  
ProASIC3 nano DC and Switching Characteristics  
Timing Characteristics  
Table 2-34 • 3.3 V LVCMOS Wide Range Low Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V  
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250  
Equivalent  
Software  
Default  
Drive  
Drive  
Strength  
Strength Speed  
Option1  
Grade tDOUT  
tDP  
tDIN  
tPY tPYS tEOUT  
tZL  
tZH  
tLZ  
tHZ Units  
100 µA  
100 µA  
100 µA  
100 µA  
Notes:  
2 mA  
Std.  
–1  
0.60 14.73 0.04 1.57 2.18 0.43 14.73 13.16 3.26 3.38  
0.51 12.53 0.04 1.33 1.85 0.36 12.53 11.19 2.77 2.87  
0.45 11.00 0.03 1.17 1.62 0.32 11.00 9.83 2.43 2.52  
0.60 14.73 0.04 1.57 2.18 0.43 14.73 13.16 3.26 3.38  
0.51 12.53 0.04 1.33 1.85 0.36 12.53 11.19 2.77 2.87  
0.45 11.00 0.03 1.17 1.62 0.32 11.00 9.83 2.43 2.52  
0.60 10.38 0.04 1.57 2.18 0.43 10.38 9.21 3.72 4.16  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
–2  
4 mA  
6 mA  
8 mA  
Std.  
–1  
–2  
Std.  
–1  
0.51  
0.45  
8.83 0.04 1.33 1.85 0.36  
7.75 0.03 1.17 1.62 0.32  
8.83 7.83 3.17 3.54  
7.75 6.88 2.78 3.11  
–2  
Std.  
–1  
0.60 10.38 0.04 1.57 2.18 0.43 10.38 9.21 3.72 4.16  
0.51  
0.45  
8.83 0.04 1.33 1.85 0.36  
7.75 0.03 1.17 1.62 0.32  
8.83 7.83 3.17 3.54  
7.75 6.88 2.78 3.11  
–2  
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive  
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.  
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
2-26  
Revision 11  
ProASIC3 nano Flash FPGAs  
Table 2-35 • 3.3 V LVCMOS Wide Range High Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V  
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250  
Equivalent  
Software  
Default  
Drive  
Drive  
Strength  
Strength Speed  
Option1  
Grade tDOUT  
tDP  
tDIN  
tPY tPYS tEOUT  
tZL  
tZH  
tLZ  
tHZ Units  
100 µA  
100 µA  
100 µA  
100 µA  
Notes:  
2 mA  
Std.  
–1  
0.60 10.83 0.04 1.57 2.18 0.43 10.83 9.48 3.25 3.56  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
0.51  
0.45  
9.22 0.04 1.33 1.85 0.36  
8.09 0.03 1.17 1.62 0.32  
9.22 8.06 2.77 3.03  
8.09 7.08 2.43 2.66  
–2  
4 mA  
6 mA  
8 mA  
Std.  
–1  
0.60 10.83 0.04 1.57 2.18 0.43 10.83 9.48 3.25 3.56  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
9.22 0.04 1.33 1.85 0.36  
8.09 0.03 1.17 1.62 0.32  
6.78 0.04 1.57 2.18 0.43  
5.77 0.04 1.33 1.85 0.36  
5.06 0.03 1.17 1.62 0.32  
6.78 0.04 1.57 2.18 0.43  
5.77 0.04 1.33 1.85 0.36  
5.06 0.03 1.17 1.62 0.32  
9.22 8.06 2.77 3.03  
8.09 7.08 2.43 2.66  
6.78 5.72 3.72 4.35  
5.77 4.87 3.16 3.70  
5.06 4.27 2.78 3.25  
6.78 5.72 3.72 4.35  
5.77 4.87 3.16 3.70  
5.06 4.27 2.78 3.25  
–2  
Std.  
–1  
–2  
Std.  
–1  
–2  
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive  
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.  
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
3. Software default selection highlighted in gray.  
Revision 11  
2-27  
ProASIC3 nano DC and Switching Characteristics  
Table 2-36 • 3.3 V LVCMOS Wide Range Low Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V  
Software Default Load at 35 pF for A3PN020, A3PN015, A3PN010  
Equivalent  
Software  
Default  
Drive  
Drive  
Strength  
Strength Speed  
Option1  
Grade tDOUT  
tDP  
tDIN  
tPY tPYS tEOUT  
tZL  
tZH  
tLZ  
tHZ Units  
100 µA  
100 µA  
100 µA  
100 µA  
Notes:  
2 mA  
Std.  
–1  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
8.20 0.04 1.57 2.18 0.43  
6.97 0.04 1.33 1.85 0.36  
6.12 0.03 1.17 1.62 0.32  
8.20 0.04 1.57 2.18 0.43  
6.97 0.04 1.33 1.85 0.36  
6.12 0.03 1.17 1.62 0.32  
6.42 0.04 1.57 2.18 0.43  
5.46 0.04 1.33 1.85 0.36  
4.79 0.03 1.17 1.62 0.32  
6.42 0.04 1.57 2.18 0.43  
5.46 0.04 1.33 1.85 0.36  
4.79 0.03 1.17 1.62 0.32  
8.20 7.68 3.26 3.38  
6.97 6.53 2.77 2.87  
6.12 5.73 2.43 2.52  
8.20 7.68 3.26 3.38  
6.97 6.53 2.77 2.87  
6.12 5.73 2.43 2.52  
6.42 6.05 3.72 4.16  
5.46 5.14 3.17 3.54  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
–2  
4 mA  
6 mA  
8 mA  
Std.  
–1  
–2  
Std.  
–1  
–2  
4.79 4.52 2.78  
3.11  
Std.  
–1  
6.42 6.05 3.72 4.16  
5.46 5.14 3.17 3.54  
–2  
4.79 4.52 2.78  
3.11  
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive  
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.  
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
2-28  
Revision 11  
ProASIC3 nano Flash FPGAs  
Table 2-37 • 3.3 V LVCMOS Wide Range High Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V  
Software Default Load at 35 pF for A3PN020, A3PN015, A3PN010  
Equivalent  
Software  
Default  
Drive  
Drive  
Strength  
Strength Speed  
Option1  
Grade tDOUT  
tDP  
tDIN  
tPY tPYS tEOUT  
tZL  
tZH  
tLZ  
tHZ Units  
100 µA  
100 µA  
100 µA  
100 µA  
Notes:  
2 mA  
Std.  
–1  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
5.23 0.04 1.57 2.18 0.43  
4.45 0.04 1.33 1.85 0.36  
3.90 0.03 1.17 1.62 0.32  
5.23 0.04 1.57 2.18 0.43  
4.45 0.04 1.33 1.85 0.36  
3.90 0.03 1.17 1.62 0.32  
3.94 0.04 1.57 2.18 0.43  
3.35 0.04 1.33 1.85 0.36  
2.94 0.03 1.17 1.62 0.32  
3.94 0.04 1.57 2.18 0.43  
3.35 0.04 1.33 1.85 0.36  
2.94 0.03 1.17 1.62 0.32  
5.23 4.37 3.25 3.56  
4.45 3.71 2.77 3.03  
3.90 3.26 2.43 2.66  
5.23 4.37 3.25 3.56  
4.45 3.71 2.77 3.03  
3.90 3.26 2.43 2.66  
3.94 3.16 3.72 4.35  
3.35 2.69 3.16 3.70  
2.94 2.36 2.78 3.25  
3.94 3.16 3.72 4.35  
3.35 2.69 3.16 3.70  
2.94 2.36 2.78 3.25  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
–2  
4 mA  
6 mA  
8 mA  
Std.  
–1  
–2  
Std.  
–1  
–2  
Std.  
–1  
–2  
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive  
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.  
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
3. Software default selection highlighted in gray.  
Revision 11  
2-29  
ProASIC3 nano DC and Switching Characteristics  
2.5 V LVCMOS  
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-  
purpose 2.5 V applications.  
Table 2-38 • Minimum and Maximum DC Input and Output Levels  
2.5 V LVCMOS  
VIL  
VIH  
VOL  
VOH IOL IOH  
Min.  
IOSL  
IOSH  
IIL1 IIH2  
µA4 µA4  
Min.  
V
Max.  
V
Min.  
V
Max.  
V
Max.  
V
Max.  
mA3  
Max.  
mA3  
Drive Strength  
2 mA  
V
mA mA  
–0.3  
–0.3  
–0.3  
–0.3  
0.7  
0.7  
0.7  
0.7  
1.7  
1.7  
1.7  
1.7  
3.6  
3.6  
3.6  
3.6  
0.7  
0.7  
0.7  
0.7  
1.7  
1.7  
1.7  
1.7  
2
2
16  
16  
32  
32  
18  
18  
37  
37  
10  
10  
10  
10  
10  
10  
10  
10  
4 mA  
4
4
6 mA  
6
6
8 mA  
8
8
Notes:  
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.  
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is  
larger when operating outside recommended ranges.  
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.  
4. Currents are measured at 85°C junction temperature.  
5. Software default selection highlighted in gray.  
R to VCCI for tLZ / tZL / tZLS  
R = 1 k  
Test Point  
Datapath  
R to GND for tHZ / tZH / tZHS  
Test Point  
35 pF  
Enable Path  
35 pF for tZH / tZHS / tZL / tZLS  
35 pF for tHZ / tLZ  
Figure 2-7 • AC Loading  
Table 2-39 • 2.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads  
Input LOW (V)  
Input HIGH (V)  
Measuring Point* (V)  
C
LOAD (pF)  
0
2.5  
1.2  
10  
Notes:  
1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points.  
2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.  
2-30  
Revision 11  
ProASIC3 nano Flash FPGAs  
Timing Characteristics  
Table 2-40 • 2.5 V LVCMOS Low Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V  
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250  
Drive  
Speed  
Strength  
Grade  
Std.  
–1  
tDOUT  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
tDP  
tDIN  
tPY  
tPYS  
1.63  
1.39  
1.22  
1.63  
1.39  
1.22  
1.63  
1.39  
1.22  
1.63  
1.39  
1.22  
tEOUT  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
tZL  
tZH  
tLZ  
tHZ  
Units  
ns  
2 mA  
4 mA  
6 mA  
8 mA  
11.29 0.04  
1.43  
1.22  
1.07  
1.43  
1.22  
1.07  
1.43  
1.22  
1.07  
1.43  
1.22  
1.07  
10.64 11.29 2.27  
2.29  
1.95  
1.71  
2.29  
1.95  
1.71  
2.89  
2.46  
2.16  
2.89  
2.46  
2.16  
9.61  
8.43  
0.04  
0.03  
9.05  
7.94  
9.61  
8.43  
1.93  
1.70  
ns  
–2  
ns  
Std.  
–1  
11.29 0.04  
10.64 11.29 2.27  
ns  
9.61  
8.43  
7.73  
6.57  
5.77  
7.73  
6.57  
5.77  
0.04  
0.03  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
9.05  
7.94  
7.70  
6.55  
5.75  
7.70  
6.55  
5.75  
9.61  
8.43  
7.73  
6.57  
5.77  
7.73  
6.57  
5.77  
1.93  
1.70  
2.60  
2.21  
1.94  
2.60  
2.21  
1.94  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Table 2-41 • 2.5 V LVCMOS High Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V  
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250  
Drive  
Strength  
Speed  
Grade  
tDOUT  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
tDP  
tDIN  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
tPY  
tPYS  
1.63  
1.39  
1.22  
1.63  
1.39  
1.22  
1.63  
1.39  
1.22  
1.63  
1.39  
1.22  
tEOUT  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
tZL  
tZH  
tLZ  
tHZ  
Units  
ns  
2 mA  
4 mA  
6 mA  
8 mA  
Notes:  
Std.  
–1  
8.38  
7.13  
6.26  
8.38  
7.13  
6.26  
4.94  
4.20  
3.69  
4.94  
4.20  
3.69  
1.43  
1.22  
1.07  
1.43  
1.22  
1.07  
1.43  
1.22  
1.07  
1.43  
1.22  
1.07  
7.36  
6.26  
5.50  
7.36  
6.26  
5.50  
4.71  
4.01  
3.52  
4.71  
4.01  
3.52  
8.38  
7.13  
6.26  
8.38  
7.13  
6.26  
4.94  
4.20  
3.69  
4.94  
4.20  
3.69  
2.27  
1.93  
1.69  
2.27  
1.93  
1.69  
2.60  
2.21  
1.94  
2.60  
2.21  
1.94  
2.37  
2.02  
1.77  
2.37  
2.02  
1.77  
2.98  
2.54  
2.23  
2.98  
2.54  
2.23  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
1. Software default selection highlighted in gray.  
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Revision 11  
2-31  
ProASIC3 nano DC and Switching Characteristics  
Table 2-42 • 2.5 V LVCMOS Low Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V  
Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010  
Drive  
Speed  
Strength  
Grade  
Std.  
–1  
tDOUT  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
tDP  
tDIN  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
tPY  
tPYS  
1.63  
1.39  
1.22  
1.63  
1.39  
1.22  
1.63  
1.39  
1.22  
1.63  
1.39  
1.22  
tEOUT  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
tZL  
tZH  
tLZ  
tHZ  
Units  
ns  
2 mA  
4 mA  
6 mA  
8 mA  
6.40  
5.45  
4.78  
6.40  
5.45  
4.78  
5.00  
4.26  
3.74  
5.00  
4.26  
3.74  
1.43  
1.22  
1.07  
1.43  
1.22  
1.07  
1.43  
1.22  
1.07  
1.43  
1.22  
1.07  
6.16  
5.24  
4.60  
6.16  
5.24  
4.60  
4.90  
4.17  
3.66  
4.90  
4.17  
3.66  
6.40  
5.45  
4.78  
6.40  
5.45  
4.78  
5.00  
4.26  
3.74  
5.00  
4.26  
3.74  
2.27  
1.93  
1.70  
2.27  
1.93  
1.70  
2.60  
2.21  
1.94  
2.60  
2.21  
1.94  
2.29  
1.95  
1.71  
2.29  
1.95  
1.71  
2.89  
2.46  
2.16  
2.89  
2.46  
2.16  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Table 2-43 • 2.5 V LVCMOS High Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V  
Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010  
Drive  
Strength  
Speed  
Grade  
tDOUT  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
tDP  
tDIN  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
tPY  
tPYS  
1.63  
1.39  
1.22  
1.63  
1.39  
1.22  
1.63  
1.39  
1.22  
1.63  
1.39  
1.22  
tEOUT  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
tZL  
tZH  
tLZ  
tHZ  
Units  
ns  
2 mA  
4 mA  
6 mA  
8 mA  
Notes:  
Std.  
–1  
3.70  
3.15  
2.77  
3.70  
3.15  
2.77  
2.76  
2.35  
2.06  
2.76  
2.35  
2.06  
1.43  
1.22  
1.07  
1.43  
1.22  
1.07  
1.43  
1.22  
1.07  
1.43  
1.22  
1.07  
3.66  
3.12  
2.74  
3.66  
3.12  
2.74  
2.80  
2.38  
2.09  
2.80  
2.38  
2.09  
3.70  
3.15  
2.77  
3.70  
3.15  
2.77  
2.60  
2.21  
1.94  
2.60  
2.21  
1.94  
2.27  
1.93  
1.69  
2.27  
1.93  
1.69  
2.60  
2.21  
1.94  
2.60  
2.21  
1.94  
2.37  
2.02  
1.77  
2.37  
2.02  
1.77  
2.98  
2.54  
2.23  
2.98  
2.54  
2.23  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
1. Software default selection highlighted in gray.  
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
2-32  
Revision 11  
ProASIC3 nano Flash FPGAs  
1.8 V LVCMOS  
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-  
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.  
Table 2-44 • Minimum and Maximum DC Input and Output Levels  
1.8 V LVCMOS  
VIL  
Max.  
VIH  
VOL  
VOH  
IOL IOH IOSL IOSH IIL1 IIH2  
Min.  
V
Min.  
V
Max.  
V
Max.  
V
Min.  
V
Max. Max.  
Drive Strength  
2 mA  
V
mA mA mA3 mA3 µA4 µA4  
–0.3 0.35 * VCCI 0.65 * VCCI  
–0.3 0.35 * VCCI 0.65 * VCCI  
3.6  
3.6  
0.45 VCCI – 0.45  
0.45 VCCI – 0.45  
2
4
2
4
9
11  
22  
10 10  
10 10  
4 mA  
17  
Notes:  
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.  
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is  
larger when operating outside recommended ranges.  
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.  
4. Currents are measured at 85°C junction temperature.  
5. Software default selection highlighted in gray.  
R to VCCI for tLZ / tZL / tZLS  
R = 1 k  
Test Point  
Datapath  
R to GND for tHZ / tZH / tZHS  
Test Point  
35 pF  
Enable Path  
35 pF for tZH / tZHS / tZL / tZLS  
35 pF for tHZ / tLZ  
Figure 2-8 • AC Loading  
Table 2-45 • 1.8 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads  
Input LOW (V)  
Input HIGH (V)  
Measuring Point* (V)  
C
LOAD (pF)  
0
1.8  
0.9  
10  
Notes:  
1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points.  
2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.  
Revision 11  
2-33  
ProASIC3 nano DC and Switching Characteristics  
Timing Characteristics  
Table 2-46 • 1.8 V LVCMOS Low Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V  
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250  
Drive  
Speed  
Strength  
Grade  
Std.  
–1  
tDOUT  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
tDP  
tDIN  
tPY  
tPYS  
1.90  
1.61  
1.42  
1.90  
1.61  
1.42  
tEOUT  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
tZL  
tZH  
tLZ  
tHZ  
Units  
ns  
2 mA  
15.36 0.04  
13.07 0.04  
11.47 0.03  
10.32 0.04  
1.35  
1.15  
1.01  
1.35  
1.15  
1.01  
13.46 15.36 2.23  
11.45 13.07 1.90  
10.05 11.47 1.67  
9.92 10.32 2.63  
1.78  
1.51  
1.33  
2.78  
2.37  
2.08  
ns  
–2  
ns  
4 mA  
Std.  
–1  
ns  
8.78  
7.71  
0.04  
0.03  
8.44  
7.41  
8.78  
7.71  
2.23  
1.96  
ns  
–2  
ns  
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Table 2-47 • 1.8 V LVCMOS High Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V  
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250  
Drive  
Strength  
Speed  
Grade  
tDOUT  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
tDP  
tDIN  
tPY  
tPYS  
1.90  
1.61  
1.42  
1.90  
1.61  
1.42  
tEOUT  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
tZL  
tZH  
tLZ  
tHZ  
Units  
ns  
2 mA  
4 mA  
Notes:  
Std.  
–1  
11.42 0.04  
1.35  
1.15  
1.01  
1.35  
1.15  
1.01  
8.65 11.42 2.23  
1.84  
1.57  
1.37  
2.89  
2.45  
2.15  
9.71  
8.53  
6.53  
5.56  
4.88  
0.04  
0.03  
0.04  
0.04  
0.03  
7.36  
6.46  
5.53  
4.70  
4.13  
9.71  
8.53  
6.53  
5.56  
4.88  
1.89  
1.66  
2.62  
2.23  
1.96  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
1. Software default selection highlighted in gray.  
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
2-34  
Revision 11  
ProASIC3 nano Flash FPGAs  
Table 2-48 • 1.8 V LVCMOS Low Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V  
Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010  
Drive  
Speed  
Strength  
Grade  
Std.  
–1  
tDOUT  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
tDP  
tDIN  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
tPY  
tPYS  
1.90  
1.61  
1.42  
1.90  
1.61  
1.42  
tEOUT  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
tZL  
tZH  
tLZ  
tHZ  
Units  
ns  
2 mA  
8.52  
7.25  
6.36  
6.59  
5.60  
4.92  
1.35  
1.15  
1.01  
1.35  
1.15  
1.01  
7.99  
6.80  
5.97  
6.44  
5.48  
4.81  
8.52  
7.25  
6.36  
6.59  
5.60  
4.92  
2.23  
1.90  
1.67  
2.63  
2.23  
1.96  
1.78  
1.51  
1.33  
2.78  
2.37  
2.08  
ns  
–2  
ns  
4 mA  
Std.  
–1  
ns  
ns  
–2  
ns  
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Table 2-49 • 1.8 V LVCMOS High Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V  
Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010  
Drive  
Strength  
Speed  
Grade  
tDOUT  
0.60  
0.51  
0.45  
0.60  
0.51  
0.45  
tDP  
tDIN  
0.04  
0.04  
0.03  
0.04  
0.04  
0.03  
tPY  
tPYS  
1.90  
1.61  
1.42  
1.90  
1.61  
1.42  
tEOUT  
0.43  
0.36  
0.32  
0.43  
0.36  
0.32  
tZL  
tZH  
tLZ  
tHZ  
Units  
ns  
2 mA  
4 mA  
Notes:  
Std.  
–1  
4.79  
4.08  
3.58  
3.22  
2.74  
2.40  
1.35  
1.15  
1.01  
1.35  
1.15  
1.01  
4.27  
3.63  
3.19  
3.24  
2.75  
2.42  
4.79  
4.08  
3.58  
3.22  
2.74  
2.40  
2.23  
1.89  
1.66  
2.62  
2.23  
1.95  
1.84  
1.57  
1.37  
2.89  
2.45  
2.15  
ns  
–2  
ns  
Std.  
–1  
ns  
ns  
–2  
ns  
1. Software default selection highlighted in gray.  
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Revision 11  
2-35  
ProASIC3 nano DC and Switching Characteristics  
1.5 V LVCMOS (JESD8-11)  
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-  
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.  
Table 2-50 • Minimum and Maximum DC Input and Output Levels  
1.5 V LVCMOS  
VIL  
Max.  
VIH  
Min.  
V
VOL  
VOH  
IOL IOH IOSL IOSH IIL1 IIH2  
Min.  
V
Max.  
V
Max.  
V
Min.  
V
Max. Max.  
Drive Strength  
2 mA  
V
mA mA mA3 mA3 µA4 µA4  
–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI  
2
2
13  
16  
10 10  
Notes:  
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.  
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is  
larger when operating outside recommended ranges.  
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.  
4. Currents are measured at 85°C junction temperature.  
5. Software default selection highlighted in gray.  
R to VCCI for tLZ / tZL / tZLS  
R = 1 k  
Test Point  
Datapath  
R to GND for tHZ / tZH / tZHS  
Test Point  
35 pF  
Enable Path  
35 pF for tZH / tZHS / tZL / tZLS  
35 pF for tHZ / tLZ  
Figure 2-9 • AC Loading  
Table 2-51 • 1.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads  
Input LOW (V)  
Input HIGH (V)  
Measuring Point* (V)  
C
LOAD (pF)  
0
1.5  
0.75  
10  
Notes:  
1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points.  
2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.  
2-36  
Revision 11  
ProASIC3 nano Flash FPGAs  
Timing Characteristics  
Table 2-52 • 1.5 V LVCMOS Low Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V  
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250  
Drive  
Speed  
Strength  
Grade  
Std.  
–1  
tDOUT  
0.60  
0.51  
0.45  
tDP  
tDIN  
tPY  
tPYS  
2.14  
1.82  
1.59  
tEOUT  
0.43  
0.36  
0.32  
tZL  
tZH  
tLZ  
tHZ  
Units  
ns  
2 mA  
12.58 0.04  
10.70 0.04  
1.56  
1.32  
1.16  
12.18 12.58 2.67  
10.36 10.70 2.27  
2.71  
2.31  
2.03  
ns  
–2  
9.39  
0.03  
9.09  
9.39  
1.99  
ns  
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Table 2-53 • 1.5 V LVCMOS High Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V  
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250  
Drive  
Strength  
Speed  
Grade  
tDOUT  
0.60  
0.51  
0.45  
tDP  
tDIN  
0.04  
0.04  
0.03  
tPY  
tPYS  
2.14  
1.82  
1.59  
tEOUT  
0.43  
0.36  
0.32  
tZL  
tZH  
tLZ  
tHZ  
Units  
ns  
2 mA  
Std.  
–1  
7.86  
6.68  
5.87  
1.56  
1.32  
1.16  
6.45  
5.49  
4.82  
7.86  
6.68  
5.87  
2.66  
2.26  
1.99  
2.83  
2.41  
2.12  
ns  
–2  
ns  
Notes:  
1. Software default selection highlighted in gray.  
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Table 2-54 • 1.5 V LVCMOS Low Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V  
Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010  
Drive  
Speed  
Strength  
Grade  
Std.  
–1  
tDOUT  
0.60  
0.51  
0.45  
tDP  
tDIN  
0.04  
0.04  
0.03  
tPY  
tPYS  
2.14  
1.82  
1.58  
tEOUT  
0.43  
0.36  
0.32  
tZL  
tZH  
tLZ  
tHZ  
Units  
ns  
2 mA  
8.01  
6.81  
5.98  
1.56  
1.32  
1.16  
8.03  
6.83  
6.00  
8.01  
6.81  
5.98  
2.67  
2.27  
2.10  
2.71  
2.31  
2.03  
ns  
–2  
ns  
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Table 2-55 • 1.5 V LVCMOS High Slew  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V  
Software Default Load at 10 pF for A3PN020, A3PN015, A3PN010  
Drive  
Strength  
Speed  
Grade  
tDOUT  
0.60  
0.51  
0.45  
tDP  
tDIN  
0.04  
0.04  
0.03  
tPY  
tPYS  
2.14  
1.82  
1.59  
tEOUT  
0.43  
0.36  
0.32  
tZL  
tZH  
tLZ  
tHZ  
Units  
ns  
2 mA  
Std.  
–1  
3.76  
3.20  
2.81  
1.52  
1.32  
1.16  
3.74  
3.18  
2.79  
3.76  
3.20  
2.81  
2.66  
2.26  
1.99  
2.83  
2.41  
2.12  
ns  
–2  
ns  
Notes:  
1. Software default selection highlighted in gray.  
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Revision 11  
2-37  
ProASIC3 nano DC and Switching Characteristics  
I/O Register Specifications  
Fully Registered I/O Buffers with Synchronous Enable and  
Asynchronous Preset  
Preset  
L
D
DOUT  
Data_out  
PRE  
F
PRE  
Y
E
Core  
Array  
Data  
Enable  
CLK  
D
Q
D
Q
C
DFN1E1P1  
DFN1E1P1  
G
E
E
EOUT  
B
A
H
I
PRE  
J
D
Q
DFN1E1P1  
K
Data Input I/O Register with:  
Active High Enable  
E
Active High Preset  
Positive-Edge Triggered  
Data Output Register and  
Enable Output Register with:  
Active High Enable  
Active High Preset  
INBUF  
INBUF  
CLKBUF  
Postive-Edge Triggered  
Figure 2-10 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset  
2-38  
Revision 11  
ProASIC3 nano Flash FPGAs  
Table 2-56 • Parameter Definition and Measuring Nodes  
Measuring Nodes  
(from, to)*  
Parameter Name  
tOCLKQ  
tOSUD  
Parameter Definition  
Clock-to-Q of the Output Data Register  
H, DOUT  
F, H  
Data Setup Time for the Output Data Register  
tOHD  
Data Hold Time for the Output Data Register  
F, H  
tOSUE  
Enable Setup Time for the Output Data Register  
Enable Hold Time for the Output Data Register  
Asynchronous Preset-to-Q of the Output Data Register  
Asynchronous Preset Removal Time for the Output Data Register  
Asynchronous Preset Recovery Time for the Output Data Register  
Clock-to-Q of the Output Enable Register  
G, H  
tOHE  
G, H  
tOPRE2Q  
tOREMPRE  
tORECPRE  
tOECLKQ  
tOESUD  
tOEHD  
L, DOUT  
L, H  
L, H  
H, EOUT  
J, H  
Data Setup Time for the Output Enable Register  
Data Hold Time for the Output Enable Register  
Enable Setup Time for the Output Enable Register  
Enable Hold Time for the Output Enable Register  
Asynchronous Preset-to-Q of the Output Enable Register  
Asynchronous Preset Removal Time for the Output Enable Register  
J, H  
tOESUE  
tOEHE  
K, H  
K, H  
tOEPRE2Q  
tOEREMPRE  
tOERECPRE  
tICLKQ  
I, EOUT  
I, H  
Asynchronous Preset Recovery Time for the Output Enable Register  
Clock-to-Q of the Input Data Register  
I, H  
A, E  
C, A  
C, A  
B, A  
B, A  
D, E  
D, A  
D, A  
tISUD  
Data Setup Time for the Input Data Register  
tIHD  
Data Hold Time for the Input Data Register  
tISUE  
Enable Setup Time for the Input Data Register  
tIHE  
Enable Hold Time for the Input Data Register  
tIPRE2Q  
tIREMPRE  
tIRECPRE  
Asynchronous Preset-to-Q of the Input Data Register  
Asynchronous Preset Removal Time for the Input Data Register  
Asynchronous Preset Recovery Time for the Input Data Register  
Note: *See Figure 2-10 on page 2-38 for more information.  
Revision 11  
2-39  
ProASIC3 nano DC and Switching Characteristics  
Fully Registered I/O Buffers with Synchronous Enable and  
Asynchronous Clear  
DOUT  
FF  
Data_out  
Y
Core  
D
Q
D
Q
Data  
Array  
CC  
EE  
DFN1E1C1  
DFN1E1C1  
GG  
EOUT  
E
E
Enable  
CLK  
CLR  
BB  
AA  
DD  
CLR  
LL  
HH  
JJ  
D
Q
CLR  
DFN1E1C1  
KK  
E
Data Input I/O Register with  
Active High Enable  
CLR  
Active High Clear  
Positive-Edge Triggered  
Data Output Register and  
Enable Output Register with  
Active High Enable  
Active High Clear  
Positive-Edge Triggered  
INBUF  
INBUF  
CLKBUF  
Figure 2-11 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear  
2-40  
Revision 11  
ProASIC3 nano Flash FPGAs  
Table 2-57 • Parameter Definition and Measuring Nodes  
Measuring Nodes  
(from, to)*  
Parameter Name  
tOCLKQ  
tOSUD  
Parameter Definition  
Clock-to-Q of the Output Data Register  
HH, DOUT  
FF, HH  
FF, HH  
GG, HH  
GG, HH  
LL, DOUT  
LL, HH  
LL, HH  
HH, EOUT  
JJ, HH  
Data Setup Time for the Output Data Register  
tOHD  
Data Hold Time for the Output Data Register  
tOSUE  
Enable Setup Time for the Output Data Register  
Enable Hold Time for the Output Data Register  
Asynchronous Clear-to-Q of the Output Data Register  
Asynchronous Clear Removal Time for the Output Data Register  
Asynchronous Clear Recovery Time for the Output Data Register  
Clock-to-Q of the Output Enable Register  
tOHE  
tOCLR2Q  
tOREMCLR  
tORECCLR  
tOECLKQ  
tOESUD  
tOEHD  
Data Setup Time for the Output Enable Register  
Data Hold Time for the Output Enable Register  
Enable Setup Time for the Output Enable Register  
Enable Hold Time for the Output Enable Register  
Asynchronous Clear-to-Q of the Output Enable Register  
Asynchronous Clear Removal Time for the Output Enable Register  
Asynchronous Clear Recovery Time for the Output Enable Register  
Clock-to-Q of the Input Data Register  
JJ, HH  
tOESUE  
tOEHE  
KK, HH  
KK, HH  
II, EOUT  
II, HH  
tOECLR2Q  
tOEREMCLR  
tOERECCLR  
tICLKQ  
II, HH  
AA, EE  
CC, AA  
CC, AA  
BB, AA  
BB, AA  
DD, EE  
DD, AA  
DD, AA  
tISUD  
Data Setup Time for the Input Data Register  
tIHD  
Data Hold Time for the Input Data Register  
tISUE  
Enable Setup Time for the Input Data Register  
tIHE  
Enable Hold Time for the Input Data Register  
tICLR2Q  
tIREMCLR  
tIRECCLR  
Asynchronous Clear-to-Q of the Input Data Register  
Asynchronous Clear Removal Time for the Input Data Register  
Asynchronous Clear Recovery Time for the Input Data Register  
Note: *See Figure 2-11 on page 2-40 for more information.  
Revision 11  
2-41  
ProASIC3 nano DC and Switching Characteristics  
Input Register  
tICKMPWH tICKMPWL  
50%  
50%  
50%  
50%  
50%  
50%  
50%  
CLK  
tIHD  
tISUD  
50%  
50%  
1
0
Data  
tIREMPRE  
tIRECPRE  
tIWPRE  
Enable  
Preset  
50%  
tIHE  
tISUE  
50%  
50%  
50%  
tIWCLR  
tIRECCLR  
50%  
tIREMCLR  
50%  
50%  
Clear  
tIPRE2Q  
50%  
50%  
tICLKQ  
50%  
Out_1  
tICLR2Q  
Figure 2-12 • Input Register Timing Diagram  
Timing Characteristics  
Table 2-58 • Input Data Register Propagation Delays  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V  
Parameter  
tICLKQ  
Description  
–2 –1 Std. Units  
0.24 0.27 0.32 ns  
0.26 0.30 0.35 ns  
0.00 0.00 0.00 ns  
0.45 0.52 0.61 ns  
0.45 0.52 0.61 ns  
0.00 0.00 0.00 ns  
0.22 0.25 0.30 ns  
0.00 0.00 0.00 ns  
0.22 0.25 0.30 ns  
0.22 0.25 0.30 ns  
0.22 0.25 0.30 ns  
0.36 0.41 0.48 ns  
0.32 0.37 0.43 ns  
Clock-to-Q of the Input Data Register  
tISUD  
Data Setup Time for the Input Data Register  
tIHD  
Data Hold Time for the Input Data Register  
tICLR2Q  
tIPRE2Q  
tIREMCLR  
tIRECCLR  
tIREMPRE  
tIRECPRE  
tIWCLR  
Asynchronous Clear-to-Q of the Input Data Register  
Asynchronous Preset-to-Q of the Input Data Register  
Asynchronous Clear Removal Time for the Input Data Register  
Asynchronous Clear Recovery Time for the Input Data Register  
Asynchronous Preset Removal Time for the Input Data Register  
Asynchronous Preset Recovery Time for the Input Data Register  
Asynchronous Clear Minimum Pulse Width for the Input Data Register  
Asynchronous Preset Minimum Pulse Width for the Input Data Register  
tIWPRE  
tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register  
tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register  
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
2-42  
Revision 11  
ProASIC3 nano Flash FPGAs  
Output Register  
tOCKMPWH tOCKMPWL  
50%  
50%  
50%  
50%  
50%  
50%  
50%  
CLK  
tOSUD tOHD  
50%  
50%  
1
0
Data_out  
tOREMPRE  
Enable  
Preset  
50%  
tOWPRE tORECPRE  
50%  
tOHE  
50%  
50%  
tOSUE  
tOREMCLR  
50%  
tORECCLR  
50%  
tOWCLR  
50%  
Clear  
tOPRE2Q  
50%  
tOCLKQ  
50%  
50%  
DOUT  
tOCLR2Q  
Figure 2-13 • Output Register Timing Diagram  
Timing Characteristics  
Table 2-59 • Output Data Register Propagation Delays  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V  
Parameter  
tOCLKQ  
Description  
–2  
–1 Std. Units  
Clock-to-Q of the Output Data Register  
0.59 0.67 0.79  
0.31 0.36 0.42  
0.00 0.00 0.00  
0.80 0.91 1.07  
0.80 0.91 1.07  
0.00 0.00 0.00  
0.22 0.25 0.30  
0.00 0.00 0.00  
0.22 0.25 0.30  
0.22 0.25 0.30  
0.22 0.25 0.30  
0.36 0.41 0.48  
0.32 0.37 0.43  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tOSUD  
Data Setup Time for the Output Data Register  
tOHD  
Data Hold Time for the Output Data Register  
tOCLR2Q  
tOPRE2Q  
tOREMCLR  
tORECCLR  
tOREMPRE  
tORECPRE  
tOWCLR  
Asynchronous Clear-to-Q of the Output Data Register  
Asynchronous Preset-to-Q of the Output Data Register  
Asynchronous Clear Removal Time for the Output Data Register  
Asynchronous Clear Recovery Time for the Output Data Register  
Asynchronous Preset Removal Time for the Output Data Register  
Asynchronous Preset Recovery Time for the Output Data Register  
Asynchronous Clear Minimum Pulse Width for the Output Data Register  
tOWPRE  
Asynchronous Preset Minimum Pulse Width for the Output Data Register  
tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register  
tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register  
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Revision 11  
2-43  
ProASIC3 nano DC and Switching Characteristics  
Output Enable Register  
tOECKMPWH tOECKMPWL  
50%  
50%  
50%  
50%  
50%  
50%  
50%  
CLK  
tOESUD OEHD  
t
50% 50%  
1
0
D_Enable  
50%  
Enable  
Preset  
tOEWPRE  
50%  
tOEREMPRE  
tOERECPRE  
50%  
50%  
tOESUEOEHE  
t
tOEREMCLR  
50%  
tOEWCLR tOERECCLR  
50%  
50%  
Clear  
tOECLR2Q  
50%  
tOEPRE2Q  
50%  
50%  
tOECLKQ  
EOUT  
Figure 2-14 • Output Enable Register Timing Diagram  
Timing Characteristics  
Table 2-60 • Output Enable Register Propagation Delays  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V  
Parameter  
tOECLKQ  
tOESUD  
Description  
–2  
–1 Std. Units  
Clock-to-Q of the Output Enable Register  
0.44 0.51 0.59 ns  
0.31 0.36 0.42 ns  
0.00 0.00 0.00 ns  
0.67 0.76 0.89 ns  
0.67 0.76 0.89 ns  
0.00 0.00 0.00 ns  
0.22 0.25 0.30 ns  
0.00 0.00 0.00 ns  
0.22 0.25 0.30 ns  
0.22 0.25 0.30 ns  
0.22 0.25 0.30 ns  
0.36 0.41 0.48 ns  
0.32 0.37 0.43 ns  
Data Setup Time for the Output Enable Register  
Data Hold Time for the Output Enable Register  
Asynchronous Clear-to-Q of the Output Enable Register  
Asynchronous Preset-to-Q of the Output Enable Register  
tOEHD  
tOECLR2Q  
tOEPRE2Q  
tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register  
tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register  
tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register  
tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register  
tOEWCLR  
tOEWPRE  
Asynchronous Clear Minimum Pulse Width for the Output Enable Register  
Asynchronous Preset Minimum Pulse Width for the Output Enable Register  
tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register  
tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register  
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
2-44  
Revision 11  
ProASIC3 nano Flash FPGAs  
DDR Module Specifications  
Input DDR Module  
Input DDR  
INBUF  
A
D
Out_QF  
(to core)  
Data  
FF1  
B
E
Out_QR  
(to core)  
CLK  
CLKBUF  
FF2  
C
CLR  
INBUF  
DDR_IN  
Figure 2-15 • Input DDR Timing Model  
Table 2-61 • Parameter Definitions  
Parameter Name  
tDDRICLKQ1  
tDDRICLKQ2  
tDDRISUD  
Parameter Definition  
Measuring Nodes (from, to)  
Clock-to-Out Out_QR  
Clock-to-Out Out_QF  
B, D  
B, E  
A, B  
A, B  
C, D  
C, E  
C, B  
C, B  
Data Setup Time of DDR input  
Data Hold Time of DDR input  
Clear-to-Out Out_QR  
Clear-to-Out Out_QF  
Clear Removal  
tDDRIHD  
tDDRICLR2Q1  
tDDRICLR2Q2  
tDDRIREMCLR  
tDDRIRECCLR  
Clear Recovery  
Revision 11  
2-45  
ProASIC3 nano DC and Switching Characteristics  
CLK  
tDDRISUD  
6
tDDRIHD  
8
Data  
CLR  
1
2
3
4
5
7
9
tDDRIRECCLR  
tDDRIREMCLR  
tDDRICLKQ1  
tDDRICLR2Q1  
Out_QF  
Out_QR  
6
2
4
tDDRICLKQ2  
tDDRICLR2Q2  
7
3
5
Figure 2-16 • Input DDR Timing Diagram  
Timing Characteristics  
Table 2-62 • Input DDR Propagation Delays  
Commercial-Case Conditions: TJ = 70°C, Worst Case VCC = 1.425 V  
Parameter  
tDDRICLKQ1  
tDDRICLKQ2  
tDDRISUD  
Description  
–2  
–1  
Std.  
0.37  
0.52  
0.38  
0.33  
0.00  
0.00  
0.62  
0.76  
0.00  
0.30  
0.30  
0.48  
0.43  
Units  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Clock-to-Out Out_QR for Input DDR  
Clock-to-Out Out_QF for Input DDR  
Data Setup for Input DDR (Fall)  
0.27  
0.39  
0.28  
0.25  
0.00  
0.00  
0.46  
0.57  
0.00  
0.22  
0.22  
0.36  
0.32  
0.31  
0.44  
0.32  
0.28  
0.00  
0.00  
0.53  
0.65  
0.00  
0.25  
0.25  
0.41  
0.37  
Data Setup for Input DDR (Rise)  
tDDRIHD  
Data Hold for Input DDR (Fall)  
Data Hold for Input DDR (Rise)  
tDDRICLR2Q1  
tDDRICLR2Q2  
Asynchronous Clear-to-Out Out_QR for Input DDR  
Asynchronous Clear-to-Out Out_QF for Input DDR  
tDDRIREMCLR Asynchronous Clear Removal time for Input DDR  
tDDRIRECCLR  
tDDRIWCLR  
Asynchronous Clear Recovery time for Input DDR  
Asynchronous Clear Minimum Pulse Width for Input DDR  
tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR  
tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR  
FDDRIMAX  
Maximum Frequency for Input DDR  
350.00 350.00 350.00 MHz  
Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.  
2-46  
Revision 11  
ProASIC3 nano Flash FPGAs  
Output DDR Module  
Output DDR  
A
B
Data_F  
(from core)  
X
X
FF1  
Out  
0
1
CLK  
E
X
CLKBUF  
C
X
OUTBUF  
D
Data_R  
(from core)  
X
FF2  
B
X
CLR  
INBUF  
C
X
DDR_OUT  
Figure 2-17 • Output DDR Timing Model  
Table 2-63 • Parameter Definitions  
Parameter Name  
tDDROCLKQ  
Parameter Definition  
Measuring Nodes (from, to)  
Clock-to-Out  
B, E  
C, E  
C, B  
C, B  
A, B  
D, B  
A, B  
D, B  
tDDROCLR2Q  
tDDROREMCLR  
tDDRORECCLR  
tDDROSUD1  
Asynchronous Clear-to-Out  
Clear Removal  
Clear Recovery  
Data Setup Data_F  
Data Setup Data_R  
Data Hold Data_F  
Data Hold Data_R  
tDDROSUD2  
tDDROHD1  
tDDROHD2  
Revision 11  
2-47  
ProASIC3 nano DC and Switching Characteristics  
CLK  
t
t
DDROHD2  
DDROSUD2  
4
9
5
Data_F  
1
2
3
t
t
DDROHD1  
DDROREMCLR  
Data_R 6  
CLR  
7
8
10  
11  
t
DDRORECCLR  
t
DDROREMCLR  
t
t
DDROCLKQ  
DDROCLR2Q  
Out  
7
2
8
3
9
4
10  
Figure 2-18 • Output DDR Timing Diagram  
Timing Characteristics  
Table 2-64 • Output DDR Propagation Delays  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V  
Parameter  
tDDROCLKQ  
tDDROSUD1  
tDDROSUD2  
tDDROHD1  
Description  
–2  
–1  
Std. Units  
Clock-to-Out of DDR for Output DDR  
Data_F Data Setup for Output DDR  
Data_R Data Setup for Output DDR  
Data_F Data Hold for Output DDR  
0.70  
0.38  
0.38  
0.00  
0.00  
0.80  
0.00  
0.22  
0.22  
0.36  
0.32  
0.80  
0.43  
0.43  
0.00  
0.00  
0.91  
0.00  
0.25  
0.25  
0.41  
0.37  
0.94  
0.51  
0.51  
0.00  
0.00  
1.07  
0.00  
0.30  
0.30  
0.48  
0.43  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tDDROHD2  
Data_R Data Hold for Output DDR  
tDDROCLR2Q  
Asynchronous Clear-to-Out for Output DDR  
tDDROREMCLR  
tDDRORECCLR  
tDDROWCLR1  
tDDROCKMPWH  
tDDROCKMPWL  
FDDOMAX  
Asynchronous Clear Removal Time for Output DDR  
Asynchronous Clear Recovery Time for Output DDR  
Asynchronous Clear Minimum Pulse Width for Output DDR  
Clock Minimum Pulse Width HIGH for the Output DDR  
Clock Minimum Pulse Width LOW for the Output DDR  
Maximum Frequency for the Output DDR  
350.00 350.00 350.00 MHz  
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
2-48  
Revision 11  
ProASIC3 nano Flash FPGAs  
VersaTile Characteristics  
VersaTile Specifications as a Combinatorial Module  
The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing  
characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO®/e,  
and ProASIC3/E Macro Library Guide.  
A
Y
Y
INV  
A
A
B
NOR2  
OR2  
Y
B
A
B
A
B
Y
AND2  
Y
NAND2  
A
B
C
A
B
Y
XOR3  
XOR2  
Y
A
B
C
A
MAJ3  
0
Y
A
B
C
MUX2  
Y
B
S
NAND3  
1
Figure 2-19 • Sample of Combinatorial Cells  
Revision 11  
2-49  
ProASIC3 nano DC and Switching Characteristics  
tPD  
A
B
NAND2 or  
Any Combinatorial  
Logic  
Y
tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)  
)
where edges are applicable for the particular  
combinatorial cell  
VCC  
50%  
50%  
A, B, C  
GND  
50%  
VCC  
50%  
OUT  
OUT  
GND  
VCC  
tPD  
tPD  
(RR)  
(FF)  
tPD  
(FR)  
50%  
50%  
tPD  
(RF)  
GND  
Figure 2-20 • Timing Model and Waveforms  
2-50  
Revision 11  
ProASIC3 nano Flash FPGAs  
Timing Characteristics  
Table 2-65 • Combinatorial Cell Propagation Delays  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V  
Combinatorial Cell  
INV  
Equation  
Y = !A  
Parameter  
tPD  
–2  
–1  
Std.  
0.54  
0.63  
0.63  
0.65  
0.65  
0.99  
0.93  
1.17  
0.68  
0.75  
Units  
ns  
0.40  
0.47  
0.47  
0.49  
0.49  
0.74  
0.70  
0.87  
0.51  
0.56  
0.46  
0.54  
0.54  
0.55  
0.55  
0.84  
0.79  
1.00  
0.58  
0.64  
AND2  
Y = A · B  
tPD  
ns  
NAND2  
OR2  
Y = !(A · B)  
Y = A + B  
tPD  
ns  
tPD  
ns  
NOR2  
Y = !(A + B)  
Y = A B  
Y = MAJ(A, B, C)  
Y = A B C  
Y = A !S + B S  
Y = A · B · C  
tPD  
ns  
XOR2  
tPD  
ns  
MAJ3  
tPD  
ns  
XOR3  
tPD  
ns  
MUX2  
tPD  
ns  
AND3  
tPD  
ns  
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for  
derating values.  
VersaTile Specifications as a Sequential Module  
The ProASIC3 library offers a wide variety of sequential cells, including flip-flops and latches. Each has a  
data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a  
representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E  
Macro Library Guide.  
Data  
CLK  
Out  
Data  
Out  
D
Q
D
Q
En  
DFN1  
DFN1E1  
CLK  
PRE  
Data  
Data  
Out  
Out  
Q
D
D
Q
En  
DFN1C1  
DFI1E1P1  
CLK  
CLK  
CLR  
Figure 2-21 • Sample of Sequential Cells  
Revision 11  
2-51  
ProASIC3 nano DC and Switching Characteristics  
tCKMPWH CKMPWL  
t
50%  
50%  
50%  
50%  
50%  
50%  
50%  
CLK  
tHD  
tSUD  
50%  
50%  
Data  
EN  
0
50%  
tRECPRE  
50%  
tWPRE  
tREMPRE  
tHE  
50%  
50%  
tSUE  
PRE  
CLR  
Out  
tREMCLR  
tRECCLR  
50%  
tWCLR  
50%  
50%  
tPRE2Q  
50%  
tCLR2Q  
50%  
50%  
tCLKQ  
Figure 2-22 • Timing Model and Waveforms  
Timing Characteristics  
Table 2-66 • Register Delays  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V  
Parameter  
tCLKQ  
Description  
–2  
–1 Std. Units  
Clock-to-Q of the Core Register  
0.55 0.63 0.74  
0.43 0.49 0.57  
0.00 0.00 0.00  
0.45 0.52 0.61  
0.00 0.00 0.00  
0.40 0.45 0.53  
0.40 0.45 0.53  
0.00 0.00 0.00  
0.22 0.25 0.30  
0.00 0.00 0.00  
0.22 0.25 0.30  
0.22 0.25 0.30  
0.22 0.25 0.30  
0.36 0.41 0.48  
0.32 0.37 0.43  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSUD  
Data Setup Time for the Core Register  
tHD  
Data Hold Time for the Core Register  
tSUE  
Enable Setup Time for the Core Register  
tHE  
Enable Hold Time for the Core Register  
tCLR2Q  
tPRE2Q  
tREMCLR  
tRECCLR  
tREMPRE  
tRECPRE  
tWCLR  
Asynchronous Clear-to-Q of the Core Register  
Asynchronous Preset-to-Q of the Core Register  
Asynchronous Clear Removal Time for the Core Register  
Asynchronous Clear Recovery Time for the Core Register  
Asynchronous Preset Removal Time for the Core Register  
Asynchronous Preset Recovery Time for the Core Register  
Asynchronous Clear Minimum Pulse Width for the Core Register  
Asynchronous Preset Minimum Pulse Width for the Core Register  
Clock Minimum Pulse Width HIGH for the Core Register  
Clock Minimum Pulse Width LOW for the Core Register  
tWPRE  
tCKMPWH  
tCKMPWL  
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
2-52  
Revision 11  
ProASIC3 nano Flash FPGAs  
Global Resource Characteristics  
A3PN250 Clock Tree Topology  
Clock delays are device-specific. Figure 2-23 is an example of a global tree used for clock routing. The  
global tree presented in Figure 2-23 is driven by a CCC located on the west side of the A3PN250 device.  
It is used to drive all D-flip-flops in the device.  
Central  
Global Rib  
CCC  
VersaTile  
Rows  
Global Spine  
Figure 2-23 • Example of Global Tree Use in an A3PN250 Device for Clock Routing  
Revision 11  
2-53  
ProASIC3 nano DC and Switching Characteristics  
Global Tree Timing Characteristics  
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not  
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven  
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer  
to the "Clock Conditioning Circuits" section on page 2-57. Table 2-67 to Table 2-72 on page 2-56 present  
minimum and maximum global clock delays within each device. Minimum and maximum delays are  
measured with minimum and maximum loading.  
Timing Characteristics  
Table 2-67 • A3PN010 Global Resource  
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V  
–2  
–1  
Std.  
Parameter Description  
tRCKL Input LOW Delay for Global Clock  
tRCKH Input HIGH Delay for Global Clock  
Min. 1 Max. 2 Min. 1 Max. 2 Min. 1 Max. 2 Units  
0.60  
0.62  
0.75  
0.85  
0.79  
0.84  
0.69  
0.70  
0.85  
0.96  
0.90 0.81 1.06  
0.96 0.82 1.12  
1.00  
ns  
ns  
ns  
ns  
ns  
tRCKMPWH Minimum Pulse Width HIGH for Global Clock  
tRCKMPWL Minimum Pulse Width LOW for Global Clock  
1.13  
tRCKSW  
Maximum Skew for Global Clock  
0.22  
0.26  
0.30  
Notes:  
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,  
located in a lightly loaded row (single element is connected to the global net).  
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully  
loaded row (all available flip-flops are connected to the global net in the row).  
3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Table 2-68 • A3PN015 Global Resource  
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V  
–2  
–1  
Std.  
Parameter Description  
tRCKL Input LOW Delay for Global Clock  
tRCKH Input HIGH Delay for Global Clock  
Min. 1 Max. 2 Min. 1 Max. 2 Min. 1 Max. 2 Units  
0.66 0.91 0.75 1.04 0.89 1.22  
0.67 0.96 0.77 1.10 0.90 1.29  
ns  
ns  
ns  
ns  
ns  
tRCKMPWH Minimum Pulse Width HIGH for Global Clock  
tRCKMPWL Minimum Pulse Width LOW for Global Clock  
0.75  
0.85  
0.85  
0.96  
1.00  
1.13  
tRCKSW  
Maximum Skew for Global Clock  
0.29  
0.33  
0.39  
Notes:  
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,  
located in a lightly loaded row (single element is connected to the global net).  
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully  
loaded row (all available flip-flops are connected to the global net in the row).  
3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.  
2-54  
Revision 11  
ProASIC3 nano Flash FPGAs  
Table 2-69 • A3PN020 Global Resource  
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V  
–2  
–1  
Std.  
Parameter Description  
tRCKL Input LOW Delay for Global Clock  
tRCKH Input HIGH Delay for Global Clock  
Min. 1 Max. 2 Min. 1 Max. 2 Min. 1 Max. 2 Units  
0.66 0.91 0.75 1.04 0.89 1.22  
0.67 0.96 0.77 1.10 0.90 1.29  
ns  
ns  
ns  
ns  
ns  
tRCKMPWH Minimum Pulse Width HIGH for Global Clock  
tRCKMPWL Minimum Pulse Width LOW for Global Clock  
0.75  
0.85  
0.85  
0.96  
1.00  
1.13  
tRCKSW  
Maximum Skew for Global Clock  
0.29  
0.33  
0.39  
Notes:  
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,  
located in a lightly loaded row (single element is connected to the global net).  
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully  
loaded row (all available flip-flops are connected to the global net in the row).  
3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Table 2-70 • A3PN060 Global Resource  
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V  
–2  
–1  
Std.  
Parameter Description  
tRCKL Input LOW Delay for Global Clock  
tRCKH Input HIGH Delay for Global Clock  
Min. 1 Max. 2 Min. 1 Max. 2 Min. 1 Max. 2 Units  
0.72 0.91 0.82 1.04 0.96 1.22  
0.71 0.94 0.81 1.07 0.96 1.26  
ns  
ns  
ns  
ns  
ns  
tRCKMPWH Minimum Pulse Width HIGH for Global Clock  
tRCKMPWL Minimum Pulse Width LOW for Global Clock  
0.75  
0.85  
0.85  
0.96  
1.00  
1.13  
tRCKSW  
Maximum Skew for Global Clock  
0.23  
0.26  
0.31  
Notes:  
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,  
located in a lightly loaded row (single element is connected to the global net).  
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully  
loaded row (all available flip-flops are connected to the global net in the row).  
3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Revision 11  
2-55  
ProASIC3 nano DC and Switching Characteristics  
Table 2-71 • A3PN125 Global Resource  
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V  
–2  
–1  
Std.  
Parameter Description  
tRCKL Input LOW Delay for Global Clock  
tRCKH Input HIGH Delay for Global Clock  
Min. 1 Max. 2 Min. 1 Max. 2 Min. 1 Max. 2 Units  
0.76 0.99 0.87 1.12 1.02 1.32  
0.76 1.02 0.87 1.17 1.02 1.37  
ns  
ns  
ns  
ns  
ns  
tRCKMPWH Minimum Pulse Width HIGH for Global Clock  
tRCKMPWL Minimum Pulse Width LOW for Global Clock  
0.75  
0.85  
0.85  
0.96  
1.00  
1.13  
tRCKSW  
Maximum Skew for Global Clock  
0.26  
0.30  
0.35  
Notes:  
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,  
located in a lightly loaded row (single element is connected to the global net).  
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully  
loaded row (all available flip-flops are connected to the global net in the row).  
3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Table 2-72 • A3PN250 Global Resource  
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V  
–2  
–1  
Std.  
Parameter Description  
tRCKL Input LOW Delay for Global Clock  
tRCKH Input HIGH Delay for Global Clock  
Min. 1 Max. 2 Min. 1 Max. 2 Min. 1 Max. 2 Units  
0.79 1.02 0.90 1.16 1.06 1.36  
0.78 1.04 0.88 1.18 1.04 1.39  
ns  
ns  
ns  
ns  
ns  
tRCKMPWH Minimum Pulse Width HIGH for Global Clock  
tRCKMPWL Minimum Pulse Width LOW for Global Clock  
0.75  
0.85  
0.85  
0.96  
1.00  
1.13  
tRCKSW  
Maximum Skew for Global Clock  
0.26  
0.30  
0.35  
Notes:  
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,  
located in a lightly loaded row (single element is connected to the global net).  
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully  
loaded row (all available flip-flops are connected to the global net in the row).  
3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-5 for derating values.  
2-56  
Revision 11  
ProASIC3 nano Flash FPGAs  
Clock Conditioning Circuits  
CCC Electrical Specifications  
Timing Characteristics  
Table 2-73 • ProASIC3 nano CCC/PLL Specification  
Parameter  
Minimum  
1.5  
Typical Maximum  
Units  
MHz  
MHz  
ps  
Clock Conditioning Circuitry Input Frequency fIN_CCC  
Clock Conditioning Circuitry Output Frequency fOUT_CCC  
Delay Increments in Programmable Delay Blocks 1,2  
350  
350  
0.75  
2003  
Number of Programmable Values in Each Programmable Delay  
Block  
32  
Serial Clock (SCLK) for Dynamic PLL 4,5  
Input Cycle-to-Cycle Jitter (peak magnitude)  
Acquisition Time  
125  
1.5  
MHz  
ns  
LockControl = 0  
300  
6.0  
µs  
LockControl = 1  
ms  
Tracking Jitter 7  
LockControl = 0  
1.6  
0.8  
ns  
ns  
%
LockControl = 1  
Output Duty Cycle  
48.5  
1.25  
51.5  
15.65  
Delay Range in Block: Programmable Delay  
11,2  
ns  
Delay Range in Block: Programmable Delay  
2 1,2  
Delay Range in Block: Fixed Delay 1,2  
0.025  
15.65  
ns  
ns  
2.2  
Max Peak-to-Peak Jitter Data 6,8,9  
6
VCO Output Peak-to-Peak Period Jitter FCCC_OUT  
SSO2  
0.50%  
1.00%  
2.50%  
SSO4  
0.50%  
3.00%  
4.00%  
SSO 8  
0.70%  
5.00%  
6.00%  
SSO 16  
1.00%  
0.75 MHz to 50MHz  
50 MHz to 250 MHz  
250 MHz to 350 MHz  
Notes:  
9.00%  
12.00%  
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-5 for deratings.  
2. T = 25°C, VCC = 1.5 V  
J
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay  
increments are available. Refer to the Libero SoC Online Help for more information.  
4. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction  
temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
5. The A3PN010, A3PN015, and A3PN020 devices do not support PLLs.  
6. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying  
the VCO period by the % jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For  
example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output divider settings.  
7. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock  
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter  
parameter.  
8. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.425 V, VCCI =  
3.3 , VQ/PQ/TQ type of packages, 20 pF load.  
9. SSOs are outputs that are synchronous to a single clock domain, and have their clock-to-out times within ± 200 ps of  
each other.  
Revision 11  
2-57  
ProASIC3 nano DC and Switching Characteristics  
Output Signal  
Tperiod_max  
Tperiod_min  
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min  
.
Figure 2-24 • Peak-to-Peak Jitter Definition  
2-58  
Revision 11  
ProASIC3 nano Flash FPGAs  
Embedded SRAM and FIFO Characteristics  
SRAM  
RAM4K9  
RAM512X18  
RADDR8  
RADDR7  
RD17  
RD16  
ADDRA11 DOUTA8  
DOUTA7  
DOUTA0  
ADDRA10  
ADDRA0  
DINA8  
RADDR0  
RD0  
DINA7  
RW1  
RW0  
DINA0  
WIDTHA1  
WIDTHA0  
PIPEA  
PIPE  
WMODEA  
BLKA  
WENA  
REN  
RCLK  
CLKA  
ADDRB11 DOUTB8  
ADDRB10 DOUTB7  
WADDR8  
WADDR7  
ADDRB0  
DOUTB0  
WADDR0  
WD17  
WD16  
DINB8  
DINB7  
WD0  
DINB0  
WW1  
WW0  
WIDTHB1  
WIDTHB0  
PIPEB  
WMODEB  
BLKB  
WEN  
WCLK  
WENB  
CLKB  
RESET  
RESET  
Figure 2-25 • RAM Models  
Revision 11  
2-59  
ProASIC3 nano DC and Switching Characteristics  
Timing Waveforms  
t
CYC  
t
t
CKL  
CKH  
CLK  
t
t
AH  
AS  
A
A
A
[R|W]ADDR  
BLK  
0
1
2
t
BKS  
t
BKH  
t
t
ENS  
ENH  
WEN  
t
CKQ1  
D
D
D
D
2
DOUT|RD  
n
0
1
t
DOH1  
Figure 2-26 • RAM Read for Pass-Through Output. Applicable to both RAM4K9 and RAM512x18.  
t
CYC  
t
t
CKL  
CKH  
CLK  
[R|W]ADDR  
BLK  
t
t
AH  
AS  
A
A
A
0
1
2
t
BKS  
t
BKH  
t
t
ENS  
ENH  
WEN  
t
CKQ2  
D
D
D
1
DOUT|RD  
n
0
t
DOH2  
Figure 2-27 • RAM Read for Pipelined Output. Applicable to both RAM4K9 and RAM512x18.  
2-60  
Revision 11  
ProASIC3 nano Flash FPGAs  
tCYC  
tCKH  
tCKL  
CLK  
[R|W]ADDR  
BLK  
tAS  
tAH  
A0  
tBKS  
A1  
A2  
tBKH  
tENS  
tENH  
WEN  
tDS  
tDH  
DI1  
DI0  
DIN|WD  
DOUT|RD  
Dn  
D2  
Figure 2-28 • RAM Write, Output Retained. Applicable to both RAM4K9 and RAM512x18.  
t
CYC  
t
t
CKH  
CKL  
CLK  
ADDR  
BLK  
t
t
AH  
AS  
A
A
A
2
0
1
t
t
BKS  
t
BKH  
ENS  
WEN  
DIN  
t
t
DH  
DS  
DI  
DI  
DI  
2
0
1
DOUT  
D
DI  
DI  
1
n
0
(pass-through)  
DOUT  
DI  
D
DI  
1
0
n
(pipelined)  
Figure 2-29 • RAM Write, Output as Write Data (WMODE = 1). Applicable to both RAM4K9 only.  
Revision 11  
2-61  
ProASIC3 nano DC and Switching Characteristics  
tCYC  
tCKH  
tCKL  
CLK  
RESET  
tRSTBQ  
Dm  
Dn  
DOUT|RD  
Figure 2-30 • RAM Reset. Applicable to both RAM4K9 and RAM512x18.  
2-62  
Revision 11  
ProASIC3 nano Flash FPGAs  
Timing Characteristics  
Table 2-74 • RAM4K9  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V  
Parameter  
tAS  
Description  
–2  
–1  
Std. Units  
Address Setup time  
0.25 0.28 0.33  
0.00 0.00 0.00  
0.14 0.16 0.19  
0.10 0.11 0.13  
0.23 0.27 0.31  
0.02 0.02 0.02  
0.18 0.21 0.25  
0.00 0.00 0.00  
1.79 2.03 2.39  
2.36 2.68 3.15  
0.89 1.02 1.20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAH  
Address Hold time  
tENS  
tENH  
tBKS  
tBKH  
tDS  
REN, WEN Setup time  
REN, WEN Hold time  
BLK Setup time  
BLK Hold time  
Input data (DIN) Setup time  
tDH  
Input data (DIN) Hold time  
tCKQ1  
Clock High to New Data Valid on DOUT (output retained, WMODE = 0)  
Clock High to New Data Valid on DOUT (flow-through, WMODE = 1)  
Clock High to New Data Valid on DOUT (pipelined)  
tCKQ2  
1
tC2CWWL  
Address collision clk-to-clk delay for reliable write after write on same 0.33 0.28 0.25  
address; applicable to closing edge  
1
tC2CWWH  
Address collision clk-to-clk delay for reliable write after write on same 0.30 0.26 0.23  
address; applicable to rising edge  
ns  
ns  
ns  
1
tC2CRWH  
Address collision clk-to-clk delay for reliable read access after write on same 0.45 0.38 0.34  
address; applicable to opening edge  
1
tC2CWRH  
Address collision clk-to-clk delay for reliable write access after read on same 0.49 0.42 0.37  
address; applicable to opening edge  
tRSTBQ  
RESET Low to Data Out Low on DOUT (flow through)  
RESET Low to Data Out Low on DOUT (pipelined)  
0.92 1.05 1.23  
0.92 1.05 1.23  
0.29 0.33 0.38  
1.50 1.71 2.01  
0.21 0.24 0.29  
3.23 3.68 4.32  
ns  
ns  
ns  
ns  
ns  
ns  
tREMRSTB RESET Removal  
tRECRSTB RESET Recovery  
tMPWRSTB RESET Minimum Pulse Width  
tCYC  
Clock Cycle time  
FMAX  
Notes:  
Maximum Frequency  
310 272  
231 MHz  
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-  
Based cSoCs and FPGAs.  
2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.  
Revision 11  
2-63  
ProASIC3 nano DC and Switching Characteristics  
Table 2-75 • RAM512X18  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V  
Parameter  
tAS  
Description  
–2  
–1 Std. Units  
Address setup time  
0.25 0.28 0.33 ns  
0.00 0.00 0.00 ns  
0.09 0.10 0.12 ns  
0.06 0.07 0.08 ns  
0.18 0.21 0.25 ns  
0.00 0.00 0.00 ns  
2.16 2.46 2.89 ns  
0.90 1.02 1.20 ns  
tAH  
Address hold time  
tENS  
REN, WEN setup time  
REN, WEN hold time  
Input data (WD) setup time  
Input data (WD) hold time  
tENH  
tDS  
tDH  
tCKQ1  
tCKQ2  
Clock High to new data valid on RD (output retained)  
Clock High to new data valid on RD (pipelined)  
1
tC2CRWH  
Address collision clk-to-clk delay for reliable read access after write on same 0.50 0.43 0.38 ns  
address; applicable to opening edge  
1
tC2CWRH  
Address collision clk-to-clk delay for reliable write access after read on same 0.59 0.50 0.44 ns  
address; applicable to opening edge  
tRSTBQ  
RESET LOW to data out LOW on RD (flow-through)  
RESET LOW to data out LOW on RD (pipelined)  
0.92 1.05 1.23 ns  
0.92 1.05 1.23 ns  
0.29 0.33 0.38 ns  
1.50 1.71 2.01 ns  
0.21 0.24 0.29 ns  
3.23 3.68 4.32 ns  
310 272 231 MHz  
tREMRSTB RESET removal  
tRECRSTB RESET recovery  
tMPWRSTB RESET minimum pulse width  
tCYC  
Clock cycle time  
FMAX  
Notes:  
Maximum frequency  
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-  
Based cSoCs and FPGAs.  
2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.  
2-64  
Revision 11  
ProASIC3 nano Flash FPGAs  
FIFO  
FIFO4K18  
RW2  
RW1  
RW0  
RD17  
RD16  
WW2  
WW1  
WW0  
RD0  
ESTOP  
FSTOP  
FULL  
AFULL  
EMPTY  
AEVAL11  
AEVAL10  
AEMPTY  
AEVAL0  
AFVAL11  
AFVAL10  
AFVAL0  
REN  
RBLK  
RCLK  
WD17  
WD16  
WD0  
WEN  
WBLK  
WCLK  
RPIPE  
RESET  
Figure 2-31 • FIFO Model  
Revision 11  
2-65  
ProASIC3 nano DC and Switching Characteristics  
Timing Waveforms  
tCYC  
RCLK  
tENH  
tENS  
REN  
tBKS  
tBKH  
RBLK  
tCKQ1  
RD  
D1  
Dn  
D0  
D2  
(flow-through)  
tCKQ2  
RD  
(pipelined)  
Dn  
D0  
D1  
Figure 2-32 • FIFO Read  
tCYC  
WCLK  
tENS  
tENH  
WEN  
tBKS  
tBKH  
WBLK  
tDS  
tDH  
DI1  
DI0  
WD  
Figure 2-33 • FIFO Write  
2-66  
Revision 11  
ProASIC3 nano Flash FPGAs  
RCLK/  
WCLK  
tMPWRSTB  
tRSTCK  
RESET  
EMPTY  
AEMPTY  
FULL  
tRSTFG  
tRSTAF  
tRSTFG  
tRSTAF  
AFULL  
WA/RA  
MATCH (A0)  
(Address Counter)  
Figure 2-34 • FIFO Reset  
tCYC  
RCLK  
tRCKEF  
EMPTY  
tCKAF  
AEMPTY  
WA/RA  
NO MATCH  
NO MATCH  
Dist = AEF_TH  
MATCH (EMPTY)  
(Address Counter)  
Figure 2-35 • FIFO EMPTY Flag and AEMPTY Flag Assertion  
Revision 11  
2-67  
ProASIC3 nano DC and Switching Characteristics  
tCYC  
WCLK  
FULL  
tWCKFF  
tCKAF  
AFULL  
WA/RA  
NO MATCH  
NO MATCH  
Dist = AFF_TH  
MATCH (FULL)  
(Address Counter)  
Figure 2-36 • FIFO FULL Flag and AFULL Flag Assertion  
WCLK  
MATCH  
WA/RA  
NO MATCH  
NO MATCH  
2nd Rising  
Edge  
After 1st  
Write  
NO MATCH  
NO MATCH  
Dist = AEF_TH + 1  
(Address Counter)  
(EMPTY)  
1st Rising  
Edge  
After 1st  
Write  
RCLK  
EMPTY  
t
RCKEF  
t
CKAF  
AEMPTY  
Figure 2-37 • FIFO EMPTY Flag and AEMPTY Flag Deassertion  
RCLK  
WA/RA  
(Address Counter)  
Dist = AFF_TH – 1  
MATCH (FULL)  
1st Rising  
NO MATCH  
NO MATCH  
1st Rising  
Edge  
After 2nd  
Read  
NO MATCH  
NO MATCH  
Edge  
After 1st  
Read  
WCLK  
FULL  
t
WCKF  
t
CKAF  
AFULL  
Figure 2-38 • FIFO FULL Flag and AFULL Flag Deassertion  
2-68  
Revision 11  
ProASIC3 nano Flash FPGAs  
Timing Characteristics  
Table 2-76 • FIFO  
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V  
Parameter  
tENS  
Description  
–2  
–1  
Std. Units  
REN, WEN Setup Time  
1.38 1.57 1.84  
0.02 0.02 0.02  
0.22 0.25 0.30  
0.00 0.00 0.00  
0.18 0.21 0.25  
0.00 0.00 0.00  
2.36 2.68 3.15  
0.89 1.02 1.20  
1.72 1.96 2.30  
1.63 1.86 2.18  
6.19 7.05 8.29  
1.69 1.93 2.27  
6.13 6.98 8.20  
0.92 1.05 1.23  
0.92 1.05 1.23  
0.29 0.33 0.38  
1.50 1.71 2.01  
0.21 0.24 0.29  
3.23 3.68 4.32  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
MHz  
tENH  
REN, WEN Hold Time  
tBKS  
BLK Setup Time  
tBKH  
BLK Hold Time  
tDS  
Input Data (WD) Setup Time  
tDH  
Input Data (WD) Hold Time  
tCKQ1  
tCKQ2  
tRCKEF  
tWCKFF  
tCKAF  
tRSTFG  
tRSTAF  
tRSTBQ  
Clock High to New Data Valid on RD (flow-through)  
Clock High to New Data Valid on RD (pipelined)  
RCLK High to Empty Flag Valid  
WCLK High to Full Flag Valid  
Clock High to Almost Empty/Full Flag Valid  
RESET LOW to Empty/Full Flag Valid  
RESET LOW to Almost Empty/Full Flag Valid  
RESET Low to Data Out Low on RD (flow-through)  
RESET Low to Data Out Low on RD (pipelined)  
RESET Removal  
tREMRSTB  
tRECRSTB  
tMPWRSTB  
tCYC  
RESET Recovery  
RESET Minimum Pulse Width  
Clock Cycle Time  
FMAX  
Maximum Frequency for FIFO  
310  
272  
231  
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.  
Revision 11  
2-69  
ProASIC3 nano DC and Switching Characteristics  
Embedded FlashROM Characteristics  
tSU  
tSU  
tSU  
CLK  
tHOLD  
tHOLD  
tHOLD  
Address  
A0  
A1  
tCKQ2  
D0  
tCKQ2  
tCKQ2  
D1  
D0  
Data  
Figure 2-39 • Timing Diagram  
Timing Characteristics  
Table 2-77 • Embedded FlashROM Access Time  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V  
Parameter  
tSU  
Description  
Address Setup Time  
–2  
–1  
Std.  
0.71  
Units  
0.53  
0.61  
0.00  
ns  
ns  
tHOLD  
tCK2Q  
Address Hold Time  
Clock to Out  
0.00  
0.00  
16.23  
15.00  
18.48  
15.00  
21.73  
15.00  
ns  
FMAX  
Maximum Clock Frequency  
MHz  
2-70  
Revision 11  
ProASIC3 nano Flash FPGAs  
JTAG 1532 Characteristics  
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to  
the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O  
Characteristics" section on page 2-12 for more details.  
Timing Characteristics  
Table 2-78 • JTAG 1532  
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V  
Parameter  
tDISU  
Description  
Test Data Input Setup Time  
Test Data Input Hold Time  
Test Mode Select Setup Time  
Test Mode Select Hold Time  
Clock to Q (data out)  
–2  
–1  
Std.  
0.71  
1.42  
0.71  
1.42  
8.52  
28.41  
17.00  
0.00  
0.28  
TBD  
Units  
ns  
0.53  
1.07  
0.53  
1.07  
6.39  
21.31  
23.00  
0.00  
0.21  
TBD  
0.60  
1.21  
0.60  
1.21  
7.24  
24.15  
20.00  
0.00  
0.24  
TBD  
tDIHD  
ns  
tTMSSU  
ns  
tTMDHD  
ns  
tTCK2Q  
ns  
tRSTB2Q  
FTCKMAX  
tTRSTREM  
tTRSTREC  
tTRSTMPW  
Reset to Q (data out)  
ns  
TCK Maximum Frequency  
ResetB Removal Time  
MHz  
ns  
ResetB Recovery Time  
ResetB Minimum Pulse  
ns  
ns  
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for  
derating values.  
Revision 11  
2-71  
ProASIC3 nano DC and Switching Characteristics  
2-72  
Revision 11  
3 – Pin Descriptions and Packaging  
Supply Pins  
GND  
Ground supply voltage to the core, I/O outputs, and I/O logic.  
GNDQ Ground (quiet)  
Ground  
Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is  
decoupled from the simultaneous switching noise originated from the output buffer ground domain. This  
minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always  
be connected to GND on the board.  
VCC  
Core Supply Voltage  
Supply voltage to the FPGA core, nominally 1.5 V. VCC is required for powering the JTAG state machine  
in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices,  
both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device.  
VCCIBx  
I/O Supply Voltage  
Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to  
eight I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a  
separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.5 V,  
1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied  
to GND.  
VMVx  
I/O Supply Voltage (quiet)  
Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the  
VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within  
the package and improves input signal integrity. Each bank must have at least one VMV connection, and  
no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to  
provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.5 V, 1.8 V, 2.5 V, or  
3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV  
and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to  
the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.).  
VCCPLA/B/C/D/E/F  
PLL Supply Voltage  
Supply voltage to analog PLL, nominally 1.5 V.  
When the PLLs are not used, the place-and-route tool automatically disables the unused PLLs to lower  
power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Microsemi  
recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from the  
PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning Circuits in Low  
Power Flash Devices and Mixed Signal FPGAs" chapter of the ProASIC3 nano Device Family User’s  
Guide for a complete board solution for the PLL analog power supply and ground.  
There is one VCCPLF pin on ProASIC3 nano devices.  
VCOMPLA/B/C/D/E/F  
PLL Ground  
Ground to analog PLL power supplies. When the PLLs are not used, the place-and-route tool  
automatically disables the unused PLLs to lower power consumption. The user should tie unused  
VCCPLx and VCOMPLx pins to ground.  
There is one VCOMPLF pin on ProASIC3 nano devices.  
VJTAG  
JTAG Supply Voltage  
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run  
at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank  
Revision 11  
3-1  
Pin Descriptions and Packaging  
gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG  
interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to  
GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is  
insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can  
be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals  
will not be able to transition the device, even in bypass mode.  
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent  
filtering capacitors rather than supplying them from a common rail.  
VPUMP  
Programming Supply Voltage  
ProASIC3 devices support single-voltage ISP of the configuration flash and FlashROM. For  
programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left  
floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming  
power supply voltage (VPUMP) range is listed in the datasheet.  
When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of  
oscillation from the charge pump circuitry.  
For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in  
parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.  
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent  
filtering capacitors rather than supplying them from a common rail.  
User Pins  
I/O  
User Input/Output  
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are  
compatible with the I/O standard selected.  
During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC  
supplies continuously powered up, when the device transitions from programming to operating mode, the  
I/Os are instantly configured to the desired user configuration.  
Unused I/Os are configured as follows:  
•
•
•
Output buffer is disabled (with tristate value of high impedance)  
Input buffer is disabled (with tristate value of high impedance)  
Weak pull-up is programmed  
GL  
Globals  
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the  
global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have  
identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.  
See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power  
Flash Devices and Mixed Signal FPGAs" chapter of the ProASIC3 nano Device Family User’s Guide. All  
inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an  
input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled  
GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals.  
The inputs to the global network are multiplexed, and only one input can be used as a global input.  
Refer to the I/O Structure chapter of the ProASIC3 nano Device Family User’s Guide for an explanation  
of the naming of global pins.  
3-2  
Revision 11  
ProASIC3 nano Flash FPGAs  
JTAG Pins  
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run  
at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to  
operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the  
part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a  
separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB  
design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST  
pin could be tied to GND.  
TCK  
Test Clock  
Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-  
up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor  
placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state.  
Note that to operate at all VJTAG voltages, 500 to 1 kwill satisfy the requirements. Refer to Table 3-1  
for more information.  
Table 3-1 • Recommended Tie-Off Values for the TCK and TRST Pins  
VJTAG  
Tie-Off Resistance  
200 to 1 k  
200 to 1 k  
500 to 1 k  
500 to 1 k  
VJTAG at 3.3 V  
VJTAG at 2.5 V  
VJTAG at 1.8 V  
VJTAG at 1.5 V  
Notes:  
1. Equivalent parallel resistance if more than one device is on the JTAG chain  
2. The TCK pin can be pulled up/down.  
3. The TRST pin is pulled down.  
TDI  
Test Data Input  
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor  
on the TDI pin.  
TDO  
Serial output for JTAG boundary scan, ISP, and UJTAG usage.  
TMS Test Mode Select  
Test Data Output  
The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an  
internal weak pull-up resistor on the TMS pin.  
TRST  
Boundary Scan Reset Pin  
The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan  
circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-  
down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor  
values must be chosen from Table 3-1 and must satisfy the parallel resistance value requirement. The  
values in Table 3-1 correspond to the resistor recommended when a single device is used, and the  
equivalent parallel resistor when multiple devices are connected via a JTAG chain.  
In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In  
such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA  
pin.  
Note that to operate at all VJTAG voltages, 500 W to 1 kW will satisfy the requirements.  
Revision 11  
3-3  
Pin Descriptions and Packaging  
Special Function Pins  
NC  
No Connect  
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be  
left floating with no effect on the operation of the device.  
DC  
Do Not Connect  
This pin should not be connected to any signals on the PCB. These pins should be left unconnected.  
Packaging  
Semiconductor technology is constantly shrinking in size while growing in capability and functional  
integration. To enable next-generation silicon technologies, semiconductor packages have also evolved  
to provide improved performance and flexibility.  
Microsemi consistently delivers packages that provide the necessary mechanical and environmental  
protection to ensure consistent reliability and performance. Microsemi IC packaging technology  
efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible  
enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition,  
Microsemi offers a variety of packages designed to meet your most demanding application and economic  
requirements for today's embedded and mobile systems.  
Related Documents  
User’s Guides  
ProASIC nano Device Family User’s Guide  
http://www.microsemi.com/soc/documents/PA3_nano_UG.pdf  
Packaging  
The following documents provide packaging information and device selection for low power flash  
devices.  
Product Catalog  
http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf  
Lists devices currently recommended for new designs and the packages available for each member of  
the family. Use this document or the datasheet tables to determine the best package for your design, and  
which package drawing to use.  
Package Mechanical Drawings  
http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf  
This document contains the package mechanical drawings for all packages currently or previously  
supplied by Microsemi. Use the bookmarks to navigate to the package mechanical drawings.  
Additional packaging materials: http://www.microsemi.com/soc/products/solutions/package/docs.aspx.  
3-4  
Revision 11  
4 – Package Pin Assignments  
48-Pin QFN  
Pin 1  
48  
1
Notes:  
1. This is the bottom view of the package.  
2. The die attach paddle of the package is tied to ground (GND).  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.  
Revision 11  
4-1  
Package Pin Assignments  
48-Pin QFN  
48-Pin QFN  
A3PN010  
A3PN010  
Pin Number  
Function  
GEC0/IO37RSB1  
IO36RSB1  
GEA0/IO34RSB1  
IO22RSB1  
GND  
Pin Number  
Function  
1
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
IO07RSB0  
2
IO06RSB0  
3
GDA0/IO05RSB0  
IO03RSB0  
4
5
GDC0/IO01RSB0  
IO12RSB1  
6
VCCIB1  
7
IO24RSB1  
IO33RSB1  
IO26RSB1  
IO32RSB1  
IO27RSB1  
IO29RSB1  
IO30RSB1  
IO31RSB1  
IO28RSB1  
IO25RSB1  
IO23RSB1  
VCC  
IO13RSB1  
8
IO15RSB1  
9
IO16RSB1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
IO18RSB1  
IO19RSB1  
IO20RSB1  
IO21RSB1  
VCCIB1  
IO17RSB1  
IO14RSB1  
TCK  
TDI  
TMS  
VPUMP  
TDO  
TRST  
VJTAG  
IO11RSB0  
IO10RSB0  
IO09RSB0  
IO08RSB0  
VCCIB0  
GND  
VCC  
4-2  
Revision 11  
ProASIC3 nano Flash FPGAs  
48-Pin QFN  
A3PN030Z  
48-Pin QFN  
A3PN030Z  
Pin Number  
Function  
IO82RSB1  
GEC0/IO73RSB1  
GEA0/IO72RSB1  
GEB0/IO71RSB1  
GND  
Pin Number  
Function  
IO25RSB0  
IO24RSB0  
IO22RSB0  
IO20RSB0  
IO18RSB0  
IO16RSB0  
IO14RSB0  
IO10RSB0  
IO08RSB0  
IO06RSB0  
IO04RSB0  
IO02RSB0  
IO00RSB0  
1
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
2
3
4
5
6
VCCIB1  
7
IO68RSB1  
IO67RSB1  
IO66RSB1  
IO65RSB1  
IO64RSB1  
IO62RSB1  
IO61RSB1  
IO60RSB1  
IO57RSB1  
IO55RSB1  
IO53RSB1  
VCC  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
VCCIB1  
IO46RSB1  
IO42RSB1  
TCK  
TDI  
TMS  
VPUMP  
TDO  
TRST  
VJTAG  
IO38RSB0  
GDB0/IO34RSB0  
GDA0/IO33RSB0  
GDC0/IO32RSB0  
VCCIB0  
GND  
VCC  
Revision 11  
4-3  
Package Pin Assignments  
68-Pin QFN  
Pin A1 Mark  
68  
1
Notes:  
1. This is the bottom view of the package.  
2. The die attach paddle of the package is tied to ground (GND).  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.  
4-4  
Revision 11  
ProASIC3 nano Flash FPGAs  
68-Pin QFN  
68-Pin QFN  
Pin Number A3PN015 Function  
Pin Number A3PN015 Function  
1
IO60RSB2  
IO54RSB2  
IO52RSB2  
IO50RSB2  
IO49RSB2  
GEC0/IO48RSB2  
GEA0/IO47RSB2  
VCC  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
TRST  
VJTAG  
2
3
IO17RSB0  
IO16RSB0  
GDA0/IO15RSB0  
GDC0/IO14RSB0  
IO13RSB0  
VCCIB0  
4
5
6
7
8
9
GND  
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
VCCIB2  
VCC  
IO46RSB2  
IO45RSB2  
IO44RSB2  
IO43RSB2  
IO42RSB2  
IO41RSB2  
IO40RSB2  
IO39RSB1  
IO37RSB1  
IO35RSB1  
IO33RSB1  
IO31RSB1  
IO30RSB1  
VCC  
IO12RSB0  
IO11RSB0  
IO09RSB0  
IO05RSB0  
IO00RSB0  
IO07RSB0  
IO03RSB0  
IO18RSB1  
IO20RSB1  
IO22RSB1  
IO24RSB1  
IO28RSB1  
NC  
GND  
GND  
NC  
VCCIB1  
IO32RSB1  
IO34RSB1  
IO36RSB1  
IO61RSB2  
IO58RSB2  
IO56RSB2  
IO63RSB2  
IO27RSB1  
IO25RSB1  
IO23RSB1  
IO21RSB1  
IO19RSB1  
TCK  
TDI  
TMS  
VPUMP  
TDO  
Revision 11  
4-5  
Package Pin Assignments  
68-Pin QFN  
68-Pin QFN  
A3PN020  
A3PN020  
Pin Number  
Function  
IO60RSB2  
IO54RSB2  
IO52RSB2  
IO50RSB2  
IO49RSB2  
GEC0/IO48RSB2  
GEA0/IO47RSB2  
VCC  
Pin Number  
Function  
1
36  
TDO  
2
37  
TRST  
3
38  
VJTAG  
4
39  
IO17RSB0  
IO16RSB0  
GDA0/IO15RSB0  
GDC0/IO14RSB0  
IO13RSB0  
VCCIB0  
5
40  
6
41  
7
42  
8
43  
9
GND  
44  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
VCCIB2  
45  
GND  
IO46RSB2  
IO45RSB2  
IO44RSB2  
IO43RSB2  
IO42RSB2  
IO41RSB2  
IO40RSB2  
IO39RSB1  
IO37RSB1  
IO35RSB1  
IO33RSB1  
IO31RSB1  
IO30RSB1  
VCC  
46  
VCC  
47  
IO12RSB0  
IO11RSB0  
IO09RSB0  
IO05RSB0  
IO00RSB0  
IO07RSB0  
IO03RSB0  
IO18RSB1  
IO20RSB1  
IO22RSB1  
IO24RSB1  
IO28RSB1  
NC  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
GND  
60  
GND  
VCCIB1  
61  
NC  
IO27RSB1  
IO25RSB1  
IO23RSB1  
IO21RSB1  
IO19RSB1  
TCK  
62  
IO32RSB1  
IO34RSB1  
IO36RSB1  
IO61RSB2  
IO58RSB2  
IO56RSB2  
IO63RSB2  
63  
64  
65  
66  
67  
TDI  
68  
TMS  
VPUMP  
4-6  
Revision 11  
ProASIC3 nano Flash FPGAs  
68-Pin QFN  
68-Pin QFN  
Pin Number A3PN030Z Function  
Pin Number A3PN030Z Function  
1
IO82RSB1  
IO80RSB1  
IO78RSB1  
IO76RSB1  
GEC0/IO73RSB1  
GEA0/IO72RSB1  
GEB0/IO71RSB1  
VCC  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
TRST  
VJTAG  
2
3
IO40RSB0  
IO37RSB0  
GDB0/IO34RSB0  
GDA0/IO33RSB0  
GDC0/IO32RSB0  
VCCIB0  
4
5
6
7
8
9
GND  
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
VCCIB1  
VCC  
IO68RSB1  
IO67RSB1  
IO66RSB1  
IO65RSB1  
IO64RSB1  
IO63RSB1  
IO62RSB1  
IO60RSB1  
IO58RSB1  
IO56RSB1  
IO54RSB1  
IO52RSB1  
IO51RSB1  
VCC  
IO31RSB0  
IO29RSB0  
IO28RSB0  
IO27RSB0  
IO25RSB0  
IO24RSB0  
IO22RSB0  
IO21RSB0  
IO19RSB0  
IO17RSB0  
IO15RSB0  
IO14RSB0  
VCCIB0  
GND  
GND  
VCC  
VCCIB1  
IO12RSB0  
IO10RSB0  
IO08RSB0  
IO06RSB0  
IO04RSB0  
IO02RSB0  
IO00RSB0  
IO50RSB1  
IO48RSB1  
IO46RSB1  
IO44RSB1  
IO42RSB1  
TCK  
TDI  
TMS  
VPUMP  
TDO  
Revision 11  
4-7  
Package Pin Assignments  
100-Pin VQFP  
100  
1
Note: This is the top view of the package.  
Note  
For Package Manufacturing and Environmental information, visit the Resource Center at  
http://www.microsemi.com/soc/products/solutions/package/docs.aspx.  
4-8  
Revision 11  
ProASIC3 nano Flash FPGAs  
100-Pin VQFP  
A3PN030Z  
100-Pin VQFP  
A3PN030Z  
100-Pin VQFP  
A3PN030Z  
Pin Number  
Function  
Pin Number  
Function  
IO51RSB1  
VCC  
Pin Number  
Function  
IO29RSB0  
IO28RSB0  
IO27RSB0  
IO26RSB0  
IO25RSB0  
IO24RSB0  
IO23RSB0  
IO22RSB0  
IO21RSB0  
IO20RSB0  
IO19RSB0  
IO18RSB0  
IO17RSB0  
IO16RSB0  
IO15RSB0  
IO14RSB0  
VCCIB0  
1
GND  
36  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
2
IO82RSB1  
IO81RSB1  
IO80RSB1  
IO79RSB1  
IO78RSB1  
IO77RSB1  
IO76RSB1  
GND  
37  
3
38  
GND  
4
39  
VCCIB1  
5
40  
IO49RSB1  
IO47RSB1  
IO46RSB1  
IO45RSB1  
IO44RSB1  
IO43RSB1  
IO42RSB1  
TCK  
6
41  
7
42  
8
43  
9
44  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
IO75RSB1  
IO74RSB1  
GEC0/IO73RSB1  
GEA0/IO72RSB1  
GEB0/IO71RSB1  
IO70RSB1  
IO69RSB1  
VCC  
45  
46  
47  
48  
TDI  
49  
TMS  
50  
NC  
51  
GND  
52  
VPUMP  
VCCIB1  
53  
NC  
GND  
IO68RSB1  
IO67RSB1  
IO66RSB1  
IO65RSB1  
IO64RSB1  
IO63RSB1  
IO62RSB1  
IO61RSB1  
IO60RSB1  
IO59RSB1  
IO58RSB1  
IO57RSB1  
IO56RSB1  
IO55RSB1  
IO54RSB1  
IO53RSB1  
IO52RSB1  
54  
TDO  
VCC  
55  
TRST  
IO12RSB0  
IO10RSB0  
IO08RSB0  
IO07RSB0  
IO06RSB0  
IO05RSB0  
IO04RSB0  
IO03RSB0  
IO02RSB0  
IO01RSB0  
IO00RSB0  
56  
VJTAG  
57  
IO41RSB0  
IO40RSB0  
IO39RSB0  
IO38RSB0  
IO37RSB0  
IO36RSB0  
GDB0/IO34RSB0  
GDA0/IO33RSB0  
GDC0/IO32RSB0  
VCCIB0  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
GND  
68  
VCC  
69  
IO31RSB0  
IO30RSB0  
70  
Revision 11  
4-9  
Package Pin Assignments  
100-Pin VQFP  
100-Pin VQFP  
A3PN060  
100-Pin VQFP  
A3PN060  
A3PN060  
Pin Number  
Function  
Pin Number  
Function  
IO61RSB1  
VCC  
Pin Number  
Function  
GBB2/IO27RSB0  
IO26RSB0  
1
GND  
36  
71  
2
GAA2/IO51RSB1  
IO52RSB1  
37  
72  
3
38  
GND  
73  
GBA2/IO25RSB0  
VMV0  
4
GAB2/IO53RSB1  
IO95RSB1  
39  
VCCIB1  
74  
5
40  
IO60RSB1  
IO59RSB1  
IO58RSB1  
IO57RSB1  
GDC2/IO56RSB1  
GDB2/IO55RSB1  
GDA2/IO54RSB1  
TCK  
75  
GNDQ  
6
GAC2/IO94RSB1  
IO93RSB1  
41  
76  
GBA1/IO24RSB0  
GBA0/IO23RSB0  
GBB1/IO22RSB0  
GBB0/IO21RSB0  
GBC1/IO20RSB0  
GBC0/IO19RSB0  
IO18RSB0  
7
42  
77  
8
IO92RSB1  
43  
78  
9
GND  
44  
79  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
GFB1/IO87RSB1  
GFB0/IO86RSB1  
VCOMPLF  
45  
80  
46  
81  
47  
82  
GFA0/IO85RSB1  
VCCPLF  
48  
TDI  
83  
IO17RSB0  
49  
TMS  
84  
IO15RSB0  
GFA1/IO84RSB1  
GFA2/IO83RSB1  
VCC  
50  
VMV1  
85  
IO13RSB0  
51  
GND  
86  
IO11RSB0  
52  
VPUMP  
87  
VCCIB0  
VCCIB1  
53  
NC  
88  
GND  
GEC1/IO77RSB1  
GEB1/IO75RSB1  
GEB0/IO74RSB1  
GEA1/IO73RSB1  
GEA0/IO72RSB1  
VMV1  
54  
TDO  
89  
VCC  
55  
TRST  
90  
IO10RSB0  
56  
VJTAG  
91  
IO09RSB0  
57  
GDA1/IO49RSB0  
GDC0/IO46RSB0  
GDC1/IO45RSB0  
GCC2/IO43RSB0  
GCB2/IO42RSB0  
GCA0/IO40RSB0  
GCA1/IO39RSB0  
GCC0/IO36RSB0  
GCC1/IO35RSB0  
VCCIB0  
92  
IO08RSB0  
58  
93  
GAC1/IO07RSB0  
GAC0/IO06RSB0  
GAB1/IO05RSB0  
GAB0/IO04RSB0  
GAA1/IO03RSB0  
GAA0/IO02RSB0  
IO01RSB0  
59  
94  
GNDQ  
60  
95  
GEA2/IO71RSB1  
GEB2/IO70RSB1  
GEC2/IO69RSB1  
IO68RSB1  
61  
96  
62  
97  
63  
98  
64  
99  
IO67RSB1  
65  
100  
IO00RSB0  
IO66RSB1  
66  
IO65RSB1  
67  
GND  
IO64RSB1  
68  
VCC  
IO63RSB1  
69  
IO31RSB0  
GBC2/IO29RSB0  
IO62RSB1  
70  
4-10  
Revision 11  
ProASIC3 nano Flash FPGAs  
100-Pin VQFP  
A3PN060Z  
100-Pin VQFP  
A3PN060Z  
100-Pin VQFP  
Pin  
Number  
Pin  
Number  
Pin  
Number  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
A3PN060Z  
GBB2/IO27RSB0  
IO26RSB0  
1
GND  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
IO61RSB1  
VCC  
2
GAA2/IO51RSB1  
IO52RSB1  
3
GND  
GBA2/IO25RSB0  
VMV0  
4
GAB2/IO53RSB1  
IO95RSB1  
VCCIB1  
5
IO60RSB1  
IO59RSB1  
IO58RSB1  
IO57RSB1  
GDC2/IO56RSB1  
GDB2/IO55RSB1  
GDA2/IO54RSB1  
TCK  
GNDQ  
6
GAC2/IO94RSB1  
IO93RSB1  
GBA1/IO24RSB0  
GBA0/IO23RSB0  
GBB1/IO22RSB0  
GBB0/IO21RSB0  
GBC1/IO20RSB0  
GBC0/IO19RSB0  
IO18RSB0  
7
8
IO92RSB1  
9
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
GFB1/IO87RSB1  
GFB0/IO86RSB1  
VCOMPLF  
GFA0/IO85RSB1  
VCCPLF  
TDI  
IO17RSB0  
TMS  
IO15RSB0  
GFA1/IO84RSB1  
GFA2/IO83RSB1  
VCC  
VMV1  
IO13RSB0  
GND  
IO11RSB0  
VPUMP  
VCCIB0  
VCCIB1  
NC  
GND  
GEC1/IO77RSB1  
GEB1/IO75RSB1  
GEB0/IO74RSB1  
GEA1/IO73RSB1  
GEA0/IO72RSB1  
VMV1  
TDO  
VCC  
TRST  
IO10RSB0  
VJTAG  
IO09RSB0  
GDA1/IO49RSB0  
GDC0/IO46RSB0  
GDC1/IO45RSB0  
GCC2/IO43RSB0  
GCB2/IO42RSB0  
GCA0/IO40RSB0  
GCA1/IO39RSB0  
GCC0/IO36RSB0  
GCC1/IO35RSB0  
VCCIB0  
IO08RSB0  
GAC1/IO07RSB0  
GAC0/IO06RSB0  
GAB1/IO05RSB0  
GAB0/IO04RSB0  
GAA1/IO03RSB0  
GAA0/IO02RSB0  
IO01RSB0  
GNDQ  
GEA2/IO71RSB1  
GEB2/IO70RSB1  
GEC2/IO69RSB1  
IO68RSB1  
IO67RSB1  
IO00RSB0  
IO66RSB1  
IO65RSB1  
GND  
IO64RSB1  
VCC  
IO63RSB1  
IO31RSB0  
GBC2/IO29RSB0  
IO62RSB1  
Revision 11  
4-11  
Package Pin Assignments  
100-Pin VQFP  
100-Pin VQFP  
A3PN125  
100-Pin VQFP  
A3PN125  
A3PN125  
Pin Number  
Function  
Pin Number  
Function  
IO93RSB1  
VCC  
Pin Number  
Function  
GBB2/IO43RSB0  
IO42RSB0  
1
GND  
36  
71  
2
GAA2/IO67RSB1  
IO68RSB1  
37  
72  
3
38  
GND  
73  
GBA2/IO41RSB0  
VMV0  
4
GAB2/IO69RSB1  
IO132RSB1  
39  
VCCIB1  
74  
5
40  
IO87RSB1  
IO84RSB1  
IO81RSB1  
IO75RSB1  
GDC2/IO72RSB1  
GDB2/IO71RSB1  
GDA2/IO70RSB1  
TCK  
75  
GNDQ  
6
GAC2/IO131RSB1  
IO130RSB1  
41  
76  
GBA1/IO40RSB0  
GBA0/IO39RSB0  
GBB1/IO38RSB0  
GBB0/IO37RSB0  
GBC1/IO36RSB0  
GBC0/IO35RSB0  
IO32RSB0  
7
42  
77  
8
IO129RSB1  
43  
78  
9
GND  
44  
79  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
GFB1/IO124RSB1  
GFB0/IO123RSB1  
VCOMPLF  
45  
80  
46  
81  
47  
82  
GFA0/IO122RSB1  
VCCPLF  
48  
TDI  
83  
IO28RSB0  
49  
TMS  
84  
IO25RSB0  
GFA1/IO121RSB1  
GFA2/IO120RSB1  
VCC  
50  
VMV1  
85  
IO22RSB0  
51  
GND  
86  
IO19RSB0  
52  
VPUMP  
87  
VCCIB0  
VCCIB1  
53  
NC  
88  
GND  
GEC0/IO111RSB1  
GEB1/IO110RSB1  
GEB0/IO109RSB1  
GEA1/IO108RSB1  
GEA0/IO107RSB1  
VMV1  
54  
TDO  
89  
VCC  
55  
TRST  
90  
IO15RSB0  
56  
VJTAG  
91  
IO13RSB0  
57  
GDA1/IO65RSB0  
GDC0/IO62RSB0  
GDC1/IO61RSB0  
GCC2/IO59RSB0  
GCB2/IO58RSB0  
GCA0/IO56RSB0  
GCA1/IO55RSB0  
GCC0/IO52RSB0  
GCC1/IO51RSB0  
VCCIB0  
92  
IO11RSB0  
58  
93  
IO09RSB0  
59  
94  
IO07RSB0  
GNDQ  
60  
95  
GAC1/IO05RSB0  
GAC0/IO04RSB0  
GAB1/IO03RSB0  
GAB0/IO02RSB0  
GAA1/IO01RSB0  
GAA0/IO00RSB0  
GEA2/IO106RSB1  
GEB2/IO105RSB1  
GEC2/IO104RSB1  
IO102RSB1  
61  
96  
62  
97  
63  
98  
64  
99  
IO100RSB1  
65  
100  
IO99RSB1  
66  
IO97RSB1  
67  
GND  
IO96RSB1  
68  
VCC  
IO95RSB1  
69  
IO47RSB0  
GBC2/IO45RSB0  
IO94RSB1  
70  
4-12  
Revision 11  
ProASIC3 nano Flash FPGAs  
100-Pin VQFP  
A3PN125Z  
100-Pin VQFP  
A3PN125Z  
100-Pin VQFP  
A3PN125Z  
Pin Number  
Function  
Pin Number  
Function  
IO93RSB1  
VCC  
Pin Number  
Function  
GBB2/IO43RSB0  
IO42RSB0  
1
GND  
36  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
2
GAA2/IO67RSB1  
IO68RSB1  
37  
3
38  
GND  
GBA2/IO41RSB0  
VMV0  
4
GAB2/IO69RSB1  
IO132RSB1  
39  
VCCIB1  
5
40  
IO87RSB1  
IO84RSB1  
IO81RSB1  
IO75RSB1  
GDC2/IO72RSB1  
GDB2/IO71RSB1  
GDA2/IO70RSB1  
TCK  
GNDQ  
6
GAC2/IO131RSB1  
IO130RSB1  
41  
GBA1/IO40RSB0  
GBA0/IO39RSB0  
GBB1/IO38RSB0  
GBB0/IO37RSB0  
GBC1/IO36RSB0  
GBC0/IO35RSB0  
IO32RSB0  
7
42  
8
IO129RSB1  
43  
9
GND  
44  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
GFB1/IO124RSB1  
GFB0/IO123RSB1  
VCOMPLF  
45  
46  
47  
GFA0/IO122RSB1  
VCCPLF  
48  
TDI  
IO28RSB0  
49  
TMS  
IO25RSB0  
GFA1/IO121RSB1  
GFA2/IO120RSB1  
VCC  
50  
VMV1  
IO22RSB0  
51  
GND  
IO19RSB0  
52  
VPUMP  
VCCIB0  
VCCIB1  
53  
NC  
GND  
GEC0/IO111RSB1  
GEB1/IO110RSB1  
GEB0/IO109RSB1  
GEA1/IO108RSB1  
GEA0/IO107RSB1  
VMV1  
54  
TDO  
VCC  
55  
TRST  
IO15RSB0  
56  
VJTAG  
IO13RSB0  
57  
GDA1/IO65RSB0  
GDC0/IO62RSB0  
GDC1/IO61RSB0  
GCC2/IO59RSB0  
GCB2/IO58RSB0  
GCA0/IO56RSB0  
GCA1/IO55RSB0  
GCC0/IO52RSB0  
GCC1/IO51RSB0  
VCCIB0  
IO11RSB0  
58  
IO09RSB0  
59  
IO07RSB0  
GNDQ  
60  
GAC1/IO05RSB0  
GAC0/IO04RSB0  
GAB1/IO03RSB0  
GAB0/IO02RSB0  
GAA1/IO01RSB0  
GAA0/IO00RSB0  
GEA2/IO106RSB1  
GEB2/IO105RSB1  
GEC2/IO104RSB1  
IO102RSB1  
61  
62  
63  
64  
IO100RSB1  
65  
IO99RSB1  
66  
IO97RSB1  
67  
GND  
IO96RSB1  
68  
VCC  
IO95RSB1  
69  
IO47RSB0  
GBC2/IO45RSB0  
IO94RSB1  
70  
Revision 11  
4-13  
Package Pin Assignments  
100-Pin VQFP  
100-Pin VQFP  
100-Pin VQFP  
Pin Number A3PN250 Function  
Pin Number A3PN250 Function  
Pin Number A3PN250 Function  
1
GND  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
VCC  
GND  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
GBA2/IO20RSB1  
VMV1  
2
GAA2/IO67RSB3  
IO66RSB3  
3
VCCIB2  
GNDQ  
4
GAB2/IO65RSB3  
IO64RSB3  
IO39RSB2  
IO38RSB2  
IO37RSB2  
GDC2/IO36RSB2  
GDB2/IO35RSB2  
GDA2/IO34RSB2  
GNDQ  
GBA1/IO19RSB0  
GBA0/IO18RSB0  
GBB1/IO17RSB0  
GBB0/IO16RSB0  
GBC1/IO15RSB0  
GBC0/IO14RSB0  
IO13RSB0  
5
6
GAC2/IO63RSB3  
IO62RSB3  
7
8
IO61RSB3  
9
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
GFB1/IO60RSB3  
GFB0/IO59RSB3  
VCOMPLF  
TCK  
IO12RSB0  
TDI  
IO11RSB0  
GFA0/IO57RSB3  
VCCPLF  
TMS  
IO10RSB0  
VMV2  
IO09RSB0  
GFA1/IO58RSB3  
GFA2/IO56RSB3  
VCC  
GND  
VCCIB0  
VPUMP  
GND  
NC  
VCC  
VCCIB3  
TDO  
IO08RSB0  
GFC2/IO55RSB3  
GEC1/IO54RSB3  
GEC0/IO53RSB3  
GEA1/IO52RSB3  
GEA0/IO51RSB3  
VMV3  
TRST  
IO07RSB0  
VJTAG  
IO06RSB0  
GDA1/IO33RSB1  
GDC0/IO32RSB1  
GDC1/IO31RSB1  
IO30RSB1  
GCB2/IO29RSB1  
GCA1/IO27RSB1  
GCA0/IO28RSB1  
GCC0/IO26RSB1  
GCC1/IO25RSB1  
VCCIB1  
GAC1/IO05RSB0  
GAC0/IO04RSB0  
GAB1/IO03RSB0  
GAB0/IO02RSB0  
GAA1/IO01RSB0  
GAA0/IO00RSB0  
GNDQ  
GNDQ  
GEA2/IO50RSB2  
GEB2/IO49RSB2  
GEC2/IO48RSB2  
IO47RSB2  
VMV0  
IO46RSB2  
IO45RSB2  
GND  
IO44RSB2  
VCC  
IO43RSB2  
IO24RSB1  
GBC2/IO23RSB1  
GBB2/IO22RSB1  
IO21RSB1  
IO42RSB2  
IO41RSB2  
IO40RSB2  
4-14  
Revision 11  
ProASIC3 nano Flash FPGAs  
100-Pin VQFP  
100-Pin VQFP  
100-Pin VQFP  
Pin Number A3PN250ZFunction  
Pin Number A3PN250ZFunction  
Pin Number A3PN250ZFunction  
1
GND  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
VCC  
GND  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
GBA2/IO20RSB1  
VMV1  
2
GAA2/IO67RSB3  
IO66RSB3  
3
VCCIB2  
GNDQ  
4
GAB2/IO65RSB3  
IO64RSB3  
IO39RSB2  
IO38RSB2  
IO37RSB2  
GDC2/IO36RSB2  
GDB2/IO35RSB2  
GDA2/IO34RSB2  
GNDQ  
GBA1/IO19RSB0  
GBA0/IO18RSB0  
GBB1/IO17RSB0  
GBB0/IO16RSB0  
GBC1/IO15RSB0  
GBC0/IO14RSB0  
IO13RSB0  
5
6
GAC2/IO63RSB3  
IO62RSB3  
7
8
IO61RSB3  
9
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
GFB1/IO60RSB3  
GFB0/IO59RSB3  
VCOMPLF  
TCK  
IO12RSB0  
TDI  
IO11RSB0  
GFA0/IO57RSB3  
VCCPLF  
TMS  
IO10RSB0  
VMV2  
IO09RSB0  
GFA1/IO58RSB3  
GFA2/IO56RSB3  
VCC  
GND  
VCCIB0  
VPUMP  
GND  
NC  
VCC  
VCCIB3  
TDO  
IO08RSB0  
GFC2/IO55RSB3  
GEC1/IO54RSB3  
GEC0/IO53RSB3  
GEA1/IO52RSB3  
GEA0/IO51RSB3  
VMV3  
TRST  
IO07RSB0  
VJTAG  
IO06RSB0  
GDA1/IO33RSB1  
GDC0/IO32RSB1  
GDC1/IO31RSB1  
IO30RSB1  
GCB2/IO29RSB1  
GCA1/IO27RSB1  
GCA0/IO28RSB1  
GCC0/IO26RSB1  
GCC1/IO25RSB1  
VCCIB1  
GAC1/IO05RSB0  
GAC0/IO04RSB0  
GAB1/IO03RSB0  
GAB0/IO02RSB0  
GAA1/IO01RSB0  
GAA0/IO00RSB0  
GNDQ  
GNDQ  
GEA2/IO50RSB2  
GEB2/IO49RSB2  
GEC2/IO48RSB2  
IO47RSB2  
VMV0  
IO46RSB2  
IO45RSB2  
GND  
IO44RSB2  
VCC  
IO43RSB2  
IO24RSB1  
GBC2/IO23RSB1  
GBB2/IO22RSB1  
IO21RSB1  
IO42RSB2  
IO41RSB2  
IO40RSB2  
Revision 11  
4-15  
5 – Datasheet Information  
List of Changes  
The following table lists critical changes that were made in each revision of the ProASIC3 nano  
datasheet.  
Revision  
Changes  
Page  
Revision 11  
(January 2013)  
The "ProASIC3 nano Ordering Information" section has been updated to mention "Y"  
as "Blank" mentioning "Device Does Not Include License to Implement IP Based on  
the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43219).  
1-III  
Added a Note stating "VMV pins must be connected to the corresponding VCCI pins. See  
the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information." to  
Table 2-1 • Absolute Maximum Ratings (SAR 38326).  
2-1  
Added a note to Table 2-2 · Recommended Operating Conditions 1, 2 (SAR 43646):  
The programming temperature range supported is Tambient = 0°C to 85°C.  
2-2  
The note in Table 2-73 • ProASIC3 nano CCC/PLL Specification referring the reader to  
SmartGen was revised to refer instead to the online help associated with the core  
(SAR 42570).  
2-57  
Figure 2-32 • FIFO Read and Figure 2-33 • FIFO Write are new (SAR 34847).  
2-66  
NA  
Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip  
(SoC) throughout the document (SAR 40288).  
Live at Power-Up (LAPU) has been replaced with ’Instant On’.  
Revision 10  
The "Security" section was modified to clarify that Microsemi does not support read-  
1-1  
(September 2012) back of programmed data.  
Revision 9  
The "In-System Programming (ISP) and Security" section and "Security" section were  
I, 1-1  
(March 2012)  
revised to clarify that although no existing security measures can give an absolute  
guarantee, Microsemi FPGAs implement the best security available in the industry  
(SAR 34668).  
Notes indicating that A3P015 is not recommended for new designs have been added  
(SAR 36761).  
I-IV  
Notes indicating that nano-Z devices are not recommended for use in new designs  
have been added. The "Devices Not Recommended For New Designs" section is new  
(SAR 36702).  
The Y security option and Licensed DPA Logo were added to the "ProASIC3 nano  
Ordering Information" section. The trademarked Licensed DPA Logo identifies that a  
product is covered by a DPA counter-measures license from Cryptography Research  
(SAR 34726).  
III  
Corrected the Commercial Temperature range to reflect a range of 0°C to 70°C  
instead of –20°C to 70°C in the "ProASIC3 nano Ordering Information", "Temperature  
Grade Offerings", and the "Speed Grade and Temperature Grade Matrix" sections  
(SAR 37097).  
III-IV  
The following sentence was removed from the "Advanced Architecture" section: "In  
addition, extensive on-chip programming circuitry enables rapid, single-voltage (3.3 V)  
programming of IGLOO nano devices via an IEEE 1532 JTAG interface" (SAR 34688).  
1-3  
1-7  
The "Specifying I/O States During Programming" section is new (SAR 34698).  
Revision 11  
5-1  
Datasheet Information  
Revision  
Changes  
Page  
Revision 9  
(continued)  
The reference to guidelines for global spines and VersaTile rows, given in the "Global  
Clock Contribution—PCLOCK" section, was corrected to the "Spine Architecture"  
section of the Global Resources chapter in the IProASIC3 nano FPGA Fabric  
User's Guide (SAR 34736).  
2-9  
Figure 2-3 has been modified for the DIN waveform; the Rise and Fall time label has  
been changed to tDIN (37114).  
2-13  
The notes regarding drive strength in the "Summary of I/O Timing Characteristics – 2-17,  
Default I/O Software Settings" section and "3.3 V LVCMOS Wide Range" section  
tables were revised for clarification. They now state that the minimum drive strength  
for the default software configuration when run in wide range is ±100 µA. The drive  
strength displayed in software is supported in normal range only. For a detailed I/V  
curve, refer to the IBIS models (SAR 34759).  
2-25  
The AC Loading figures in the "Single-Ended I/O Characteristics" section were  
updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O  
Software Settings" section (SAR 34888).  
2-22  
2-54  
Added values for minimum pulse width and removed the FRMAX row from Table 2-67  
through Table 2-72 in the "Global Tree Timing Characteristics" section. Use the through  
software to determine the FRMAX for the device you are using (SAR 36956).  
2-56  
Table 2-73 • ProASIC3 nano CCC/PLL Specification was updated. A note was added  
indicating that when the CCC/PLL core is generated by Microsemi core generator  
software, not all delay values of the specified delay increments are available (SAR  
34823).  
2-57  
The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics" 2-60,  
tables, Figure 2-34 • FIFO Reset, and the FIFO "Timing Characteristics" tables were  
revised to ensure consistency with the software names (SAR 35743).  
2-63,  
2-67,  
2-69  
Reference was made to a new application note, Simultaneous Read-Write Operations  
in Dual-Port SRAM for Flash-Based cSoCs and FPGAs, which covers these cases in  
detail (SAR 34871).  
The "Pin Descriptions and Packaging" chapter has been added (SAR 34772).  
3-1  
July 2010  
The versioning system for datasheets has been changed. Datasheets are assigned a  
revision number that increments each time the datasheet is revised. The "ProASIC3  
nano Device Status" table on page II indicates the status for each device in the device  
family.  
N/A  
Revision 8  
(April 2010)  
References to differential inputs were removed from the datasheet, since ProASIC3  
nano devices do not support differential inputs (SAR 21449).  
N/A  
The "ProASIC3 nano Device Status" table is new.  
II  
The JTAG DC voltage was revised in Table 2-2 • Recommended Operating  
Conditions 1, 2 (SAR 24052). The maximum value for VPUMP programming voltage  
(operation mode) was changed from 3.45 V to 3.6 V (SAR 25220).  
2-2  
The highest temperature in Table 2-6 • Temperature and Voltage Derating Factors for  
Timing Delays was changed to 100ºC.  
2-5  
2-6  
The typical value for A3PN010 was revised in Table 2-7 • Quiescent Supply Current  
Characteristics. The note was revised to remove the statement that values do not  
include I/O static contribution.  
5-2  
Revision 11  
ProASIC3 nano Flash FPGAs  
Revision  
Changes  
Page  
Revision 8  
(continued)  
The following tables were updated with available information:  
2-6  
through  
2-18  
Table 2-8 · Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software  
Settings; Table 2-9 · Summary of I/O Output Buffer Power (per pin) – Default I/O  
Software Settings1; Table 2-10 • Different Components Contributing to Dynamic  
Power Consumption in ProASIC3 nano Devices; Table 2-14 • Summary of Maximum  
and Minimum DC Input and Output Levels; Table 2-18 • Summary of I/O Timing  
Characteristics—Software Default Settings (at 35 pF); Table 2-19 • Summary of I/O  
Timing Characteristics—Software Default Settings (at 10 pF)  
Table 2-22 • I/O Weak Pull-Up/Pull-Down Resistances was revised to add wide range  
data and correct the formulas in the table notes (SAR 21348).  
2-19  
2-20  
The text introducing Table 2-24 • Duration of Short Circuit Event before Failure was  
revised to state six months at 100° instead of three months at 110° for reliability  
concerns. The row for 110° was removed from the table.  
Table 2-26 • I/O Input Rise Time, Fall Time, and Related I/O Reliability was revised to  
give values with Schmitt trigger disabled and enabled (SAR 24634). The temperature  
for reliability was changed to 100ºC.  
2-21  
2-22  
Table 2-33 • Minimum and Maximum DC Input and Output Levels for 3.3 V LVCMOS  
Wide Range and the timing tables in the "Single-Ended I/O Characteristics" section  
were updated with available information. The timing tables for 3.3 V LVCMOS wide  
range are new.  
The following sentence was deleted from the "2.5 V LVCMOS" section: "It uses a 5 V–  
tolerant input buffer and push-pull output buffer."  
2-30  
Values for tDDRISUD and FDDRIMAX were updated in Table 2-62 • Input DDR 2-46,  
Propagation Delays. Values for FDDOMAX were added to Table 2-64 • Output DDR  
Propagation Delays (SAR 23919).  
2-48  
Table 2-67 • A3PN010 Global Resource through Table 2-70 • A3PN060 Global  
Resource were updated with available information.  
2-54  
through  
2-55  
Table 2-73 • ProASIC3 nano CCC/PLL Specification was revised (SAR 79390).  
2-57  
Revision 11  
5-3  
Datasheet Information  
Revision  
Changes  
Page  
Revision 7 (Jan 2010) All product tables and pin tables were updated to show clearly that A3PN030 is  
N/A  
available only in the Z feature at this time, as A3PN030Z. The nano-Z feature  
grade devices are designated with a Z at the end of the part number.  
v0.7  
Product Brief Advance  
Packaging Advance  
v0.6  
The "68-Pin QFN" and "100-Pin VQFP" pin tables for A3PN030 were removed.  
Only the Z grade for A3PN030 is available at this time.  
N/A  
I
Revision 6 (Aug 2009) The note for A3PN030 in the "ProASIC3 nano Devices" table was revised. It  
states A3PN030 is available in the Z feature grade only.  
Product Brief Advance  
v0.6  
Packaging Advance  
v0.5  
The "68-Pin QFN" pin table for A3PN030 is new.  
3-7  
The "48-Pin QFN", "68-Pin QFN", and "100-Pin VQFP" pin tables for A3PN030Z 4-3, 4-7,  
are new.  
4-9  
4-11  
4-13  
4-15  
N/A  
1-7  
The "100-Pin VQFP" pin table for A3PN060Z is new.  
The "100-Pin VQFP" pin table for A3PN125Z is new  
The "100-Pin VQFP" pin table for A3PN250Z is new.  
Revision 5 (Mar 2009) All references to speed grade –F were removed from this document.  
Product Brief Advance  
v0.5  
The"I/Os with Advanced I/O Standards" section was revised to add definitions of  
hot-swap and cold-sparing.  
Revision 4 (Feb 2009) The "100-Pin VQFP" pin table for A3PN030 is new.  
3-10  
N/A  
I
Packaging Advance  
v0.4  
Revision 3 (Feb 2009) The "100-Pin QFN" section was removed.  
Packaging Advance  
v0.3  
Revision 2 (Nov 2008) The "ProASIC3 nano Devices" table was revised to change the maximum user  
I/Os for A3PN020 and A3PN030. The following table note was removed: "Six chip  
Product Brief Advance  
(main) and three quadrant global networks are available for A3PN060 and  
v0.4  
above."  
The QN100 package was removed for all devices.  
N/A  
III  
The "Device Marking" section is new.  
Revision 1 (Oct 2008) The A3PN030 device was added to product tables and replaces A3P030 entries  
I to IV  
that were formerly in the tables.  
Product Brief Advance  
v0.3  
The "Wide Range I/O Support" section is new.  
1-7  
II  
The "I/Os Per Package" table was updated to add the following information to  
table note 4: "For nano devices, the VQ100 package is offered in both leaded and  
RoHS-compliant versions. All other packages are RoHS-compliant only."  
The "ProASIC3 nano Products Available in the Z Feature Grade" section was  
updated to remove QN100 for A3PN250.  
IV  
The "General Description" section was updated to give correct information about  
number of gates and dual-port RAM for ProASIC3 nano devices.  
1-1  
5-4  
Revision 11  
ProASIC3 nano Flash FPGAs  
Revision  
Changes  
The device architecture figures, Figure 1-3 • ProASIC3 nano Device Architecture  
Page  
Revision 1 (cont’d)  
1-3  
Overview with Two I/O Banks (A3PN060 and A3PN125) through Figure 1-4 • through  
ProASIC3 nano Device Architecture Overview with Four I/O Banks (A3PN250),  
were revised. Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O  
Banks and No RAM (A3PN010 and A3PN030) is new.  
1-4  
The "PLL and CCC" section was revised to include information about CCC-GLs in  
A3PN020 and smaller devices.  
1-6  
2-2  
DC and Switching  
Characteristics  
Advance v0.2  
Table 2-2 • Recommended Operating Conditions 1, 2 was revised to add VMV to  
the VCCI row. The following table note was added: "VMV pins must be connected  
to the corresponding VCCI pins."  
The values in Table 2-7 • Quiescent Supply Current Characteristics were revised  
for A3PN010, A3PN015, and A3PN020.  
2-6  
A table note, "All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide 2-16, 2-18  
range, as specified in the JESD8-B specification," was added to Table 2-14 •  
Summary of Maximum and Minimum DC Input and Output Levels, Table 2-18 •  
Summary of I/O Timing Characteristics—Software Default Settings (at 35 pF),  
and Table 2-19 • Summary of I/O Timing Characteristics—Software Default  
Settings (at 10 pF).  
3.3 V LVCMOS Wide Range was added to Table 2-21 • I/O Output Buffer 2-19, 2-20  
Maximum Resistances 1 and Table 2-23 • I/O Short Currents IOSH/IOSL.  
Packaging Advance  
v0.2  
The "48-Pin QFN" pin diagram was revised.  
4-2  
Note 2 for the "48-Pin QFN", "68-Pin QFN", and "100-Pin VQFP" pin diagrams 4-2, 4-5,  
was added/changed to "The die attach paddle of the package is tied to ground  
(GND)."  
4-9  
4-9  
The "100-Pin VQFP" pin diagram was revised to move the pin IDs to the upper  
left corner instead of the upper right corner.  
Revision 11  
5-5  
Datasheet Information  
Datasheet Categories  
Categories  
In order to provide the latest information to designers, some datasheet parameters are published before  
data has been fully characterized from silicon devices. The data provided for a given device, as  
highlighted in the "ProASIC3 nano Device Status" table on page II, is designated as either "Product  
Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows:  
Product Brief  
The product brief is a summarized version of a datasheet (advance or production) and contains general  
product information. This document gives an overview of specific device and family information.  
Advance  
This version contains initial estimated information based on simulation, other products, devices, or speed  
grades. This information can be used as estimates, but not for production. This label only applies to the  
DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not  
been fully characterized.  
Preliminary  
The datasheet contains information based on simulation and/or initial characterization. The information is  
believed to be correct, but changes are possible.  
Production  
This version contains information that is considered to be final.  
Export Administration Regulations (EAR)  
The products described in this document are subject to the Export Administration Regulations (EAR).  
They could require an approved export license prior to export from the United States. An export includes  
release of product or disclosure of technology to a foreign national inside or outside the United States.  
Safety Critical, Life Support, and High-Reliability Applications  
Policy  
The products described in this advance status document may not have completed the Microsemi  
qualification process. Products may be amended or enhanced during the product introduction and  
qualification process, resulting in changes in device functionality or performance. It is the responsibility of  
each customer to ensure the fitness of any product (but especially a new product) for a particular  
purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications.  
Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating  
to life-support applications. A reliability report covering all of the SoC Products Group’s products is  
available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety  
of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for  
additional reliability information.  
5-6  
Revision 11  
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor  
solutions for: aerospace, defense and security; enterprise and communications; and industrial  
and alternative energy markets. Products include high-performance, high-reliability analog and  
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and  
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at  
www.microsemi.com.  
Microsemi Corporate Headquarters  
One Enterprise, Aliso Viejo CA 92656 USA  
Within the USA: +1 (949) 380-6100  
Sales: +1 (949) 380-6136  
© 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of  
Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.  
Fax: +1 (949) 215-4996  
51700111-11/01.13  

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