A40MX04-3PGG100M_技术文档

DS2316

Datasheet

40MX and 42MX FPGA

Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of

its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the

application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have

been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any

performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all

performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not

rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to

independently determine suitability of any products and to test and verify the same. The information provided by Microsemi

hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely

with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP

rights, whether with regard to such information itself or anything described by such information. Information provided in this

document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this

document or to any products and services at any time without notice.

Microsemi Corporate Headquarters

One Enterprise, Aliso Viejo,

CA 92656 USA

Within the USA: +1 (800) 713-4113

Outside the USA: +1 (949) 380-6100

Fax: +1 (949) 215-4996

Email: sales.support@microsemi.com

www.microsemi.com

About Microsemi

Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for

aerospace & defense, communications, data center and industrial markets. Products include high-performance and

radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products;

timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing

devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and

scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design

capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees

globally. Learn more at www.microsemi.com.

rights reserved. Microsemi and the

Microsemi logo are trademarks of

Microsemi Corporation. All other

trademarks and service marks are the

property of their respective owners.

5172136. 16.0 8/17

Contents

1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

Revision 16.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Revision 15.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Revision 14.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Revision 13.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Revision 12.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Revision 11.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Revision 10.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Revision 9.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Revision 6.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 40MX and 42MX FPGA Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1.1

2.1.2

2.1.3

2.1.4

High Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

High Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

HiRel Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ease of Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.2

2.3

2.4

2.5

2.6

2.7

Product Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Plastic Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ceramic Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Temperature Grade Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Speed Grade Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 40MX and 42MX FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2

MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2.1

3.2.2

3.2.3

3.2.4

3.2.5

Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Dual-Port SRAM Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Routing Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MultiPlex I/O Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3

3.4

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3.1

3.3.2

3.3.3

3.3.4

3.3.5

3.3.6

3.3.7

Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

User Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Power-Up/Down in Mixed-Voltage Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Transient Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.4.1

3.4.2

3.4.3

3.4.4

3.4.5

3.4.6

3.4.7

3.4.8

3.4.9

General Power Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Static Power Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Active Power Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Equivalent Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

C_EQValues for Microsemi MX FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Test Circuitry and Silicon Explorer II Probe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Design Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

IEEE Standard 1149.1 Boundary Scan Test (BST) Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . 19

JTAG Mode Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DS2316 Datasheet Revision 16.0

iii

3.4.10 TRST Pin and TAP Controller Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4.11 Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.5

3.6

Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.6.1

3.6.2

3.6.3

Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

User Guides and Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.7

3.8

3.9

5.0 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.7.1 5 V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.3 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.8.1 3.3 V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Mixed 5.0 V / 3.3 V Operating Conditions (for 42MX Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.9.1

3.9.2

3.9.3

3.9.4

3.9.5

Mixed 5.0V/3.3V Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Output Drive Characteristics for 5.0 V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Output Drive Characteristics for 3.3 V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Junction Temperature (T_J) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.10

Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.10.1 Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.10.2 Sequential Module Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.10.3 Sequential Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.10.4 Decode Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.10.5 SRAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.10.6 Dual-Port SRAM Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.10.7 Predictable Performance: Tight Delay Distributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.11

3.12

Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.11.1 Critical Nets and Typical Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.11.2 Long Tracks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.11.3 Timing Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.11.4 Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.11.5 PCI System Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.11.6 PCI Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4 Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

DS2316 Datasheet Revision 16.0

iv

Tables

Table 1

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

Table 8

Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Plastic Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ceramic Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Temperature Grade Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Speed Grade Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Voltage Support of MX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Fixed Capacitance Values for MX FPGAs (pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Device Configuration Options for Probe Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Test Access Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Supported BST Public Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Boundary Scan Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Absolute Maximum Ratings for 40MX Devices* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Absolute Maximum Ratings for 42MX Devices* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Absolute Maximum Ratings for 40MX Devices* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Absolute Maximum Ratings for 42MX Devices* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Absolute Maximum Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Mixed 5.0V/3.3V Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

DC Specification (5.0 V PCI Signaling) ^{. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27}

AC Specifications (5.0V PCI Signaling)^{* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28}

DC Specification (3.3 V PCI Signaling) ^{. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29}

AC Specifications for (3.3 V PCI Signaling)^{* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29}

Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

42MX Temperature and Voltage Derating Factors (Normalized to T_J= 25°C, VCCA = 5.0 V) . . . 40

40MX Temperature and Voltage Derating Factors(Normalized to TJ = 25°C, VCC = 5.0 V) . . . . . 41

42MX Temperature and Voltage Derating Factors(Normalized to TJ = 25°C, VCCA = 3.3 V) . . . . 41

40MX Temperature and Voltage Derating Factors (Normalized to TJ = 25°C, VCC = 3.3 V) . . . . 42

Clock Specification for 33 MHz PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Timing Parameters for 33 MHz PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

A40MX02 Timing Characteristics (Nominal 5.0 V Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

A40MX02 Timing Characteristics (Nominal 3.3 V Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

A40MX04 Timing Characteristics (Nominal 5.0 V Operation)

Table 9

Table 10

Table 11

Table 12

Table 13

Table 14

Table 15

Table 16

Table 17

Table 18

Table 19

Table 20

Table 21

Table 22

Table 23

Table 24

Table 25

Table 26

Table 27

Table 28

Table 29

Table 30

Table 31

Table 32

Table 33

Table 34

Table 35

Table 36

(Worst-Case Commercial Conditions, VCC = 4.75 V, T_J= 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . 48

A40MX04 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCC = 3.0 V, T_J= 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . 51

A42MX09 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) . . . . . . . . . . . . . . . . . . . . . . . . 54

A42MX09 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . 58

A42MX16 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) . . . . . . . . . . . . . . . . . . . . . . . . 62

A42MX16 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . 66

A42MX24 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) . . . . . . . . . . . . . . . . . . . . . . . . 69

A42MX24 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . 73

A42MX36 Timing Characteristics (Nominal 5.0 V Operation)

Table 37

Table 38

Table 39

Table 40

Table 41

Table 42

Table 43

Table 44

Table 45

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) . . . . . . . . . . . . . . . . . . . . . . . . 77

A42MX36 Timing Characteristics (Nominal 3.3 V Operation)

DS2316 Datasheet Revision 15.0

v

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . 81

Configuration of Unused I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

PL44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

PL68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

PQ 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

PQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

PQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

VQ80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

TQ176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

CQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

BG272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

PG132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

CQ172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Table 46

Table 47

Table 48

Table 49

Table 50

Table 51

Table 52

Table 53

Table 54

Table 55

Table 56

Table 57

Table 58

Table 59

Table 60

Table 61

Table 62

DS2316 Datasheet Revision 15.0

vi

Figures

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

42MX C-Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

42MX S-Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

A42MX24 and A42MX36 D-Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

A42MX36 Dual-Port SRAM Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

MX Routing Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Clock Networks of 42MX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Quadrant Clock Network of A42MX36 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

42MX I/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PCI Output Structure of A42MX24 and A42MX36 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Silicon Explorer II Setup with 40MX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Silicon Explorer II Setup with 42MX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

42MX IEEE 1149.1 Boundary Scan Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Device Selection Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Typical Output Drive Characteristics (Based Upon Measured Data) . . . . . . . . . . . . . . . . . . . . . . . 30

40MX Timing Model* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

42MX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

42MX Timing Model (Logic Functions Using Quadrant Clocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

42MX Timing Model (SRAM Functions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Module Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Flip-Flops and Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Input Buffer Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Output Buffer Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Decode Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

SRAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

42MX SRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

42MX SRAM Synchronous Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

42MX SRAM Asynchronous Read Operation—Type 1 (Read Address Controlled) . . . . . . . . . . . . 38

42MX SRAM Asynchronous Read Operation—Type 2 (Write Address Controlled) . . . . . . . . . . . . 39

42MX Junction Temperature and Voltage Derating Curves

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Figure 33

Figure 34

(Normalized to TJ = 25°C, VCCA = 5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

40MX Junction Temperature and Voltage Derating Curves

(Normalized to TJ = 25°C, VCC = 5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

42MX Junction Temperature and Voltage Derating Curves

(Normalized to TJ = 25°C, VCCA = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

40MX Junction Temperature and Voltage Derating Curves

Figure 35

Figure 36

Figure 37

(Normalized to TJ = 25°C, VCC = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

PL44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

PL68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

PQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

PQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

PQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

VQ80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

TQ176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

CQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 38

Figure 39

Figure 40

Figure 41

Figure 42

Figure 43

Figure 44

Figure 45

Figure 46

Figure 47

Figure 48

Figure 49

Figure 50

DS2316 Datasheet Revision 16.0

vii

Figure 51

Figure 52

Figure 53

BG272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

PG132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

CQ172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

DS2316 Datasheet Revision 16.0

viii

Revision History

1

Revision History

The revision history describes the changes that were implemented in the document. The changes are

listed by revision, starting with the most current publication.

1.1

1.2

Revision 16.0

Table 4, page 7 is edited in this revision to add the temperature grade, “I” for the column A42MX09 and

row PQFP144

Revision 15.0

The following is a summary of the changes in revision 15.0 (Published in December 2016) of this

document.

•

Table 15, page 23 is edited to add the footnote, VIH(Min) is 2.4V for A42MX36 family. This applies

only to VCCI of 5V and is not applicable to VCCI of 3.3V

Table 22, page 27 is edited to add the footnote, VIH(Min) is 2.4V for A42MX36 family. This applies

only to VCCI of 5V and is not applicable to VCCI of 3.3V

Table 23, page 27 is edited to add the footnote, VIH(Min) is 2.4V for A42MX36 family. This applies

only to VCCI of 5V and is not applicable to VCCI of 3.3V

1.3

Revision 14.0

The following is a summary of the changes in revision 14.0 of this document.

•

Added CQFP package information for A42MX16 device in Product Profile, page 3 and Ceramic

Device Resources, page 6 (SAR 79522).

Added Military (M) and MIL-STD-883 Class B (B) grades for CPGA 132 Package and added

Commercial (C), Military (M), and MIL-STD-883 Class B (B) grades for CQFP 172 Package in

Temperature Grade Offerings, page 7 (SAR 79519)

•

Changed Silicon Sculptor II to Silicon Sculptor in Programming, page 15 (SAR 38754)

Added Figure 53, page 160 CQ172 package (SAR 79522).

1.4

1.5

Revision 13.0

The following is a summary of the changes in revision 13.0 of this document.

•

Added Figure 42, page 99 PQ144 Package for A42MX09 device (SAR 69776)

Added Figure 52, page 155 PQ132 Package for A42MX09 device (SAR 69776)

Revision 12.0

The following is a summary of the changes in revision 12.0 of this document.

•

Added information on power-up behavior for A42MX24 and A42MX36 devices to the Power Supply,

page 15 (SAR 42096

Corrected the inadvertent mistake in the naming of the PL68 pin assignment table (SARs 48999,

49793)

1.6

1.7

Revision 11.0

The following is a summary of the changes in revision 11.0 of this document.

•

The FuseLock logo and accompanying text was removed from the User Security, page 14. This

marking is no longer used on Microsemi devices (PCN 0915)

The Development Tool Support, page 21 was updated (SAR 38512)

Revision 10.0

The following is a summary of the changes in revision 10.0 of this document.

DS2316 Datasheet Revision 16.0

1

Revision History

•

Ordering Information, page 5 was updated to include lead-free package ordering codes (SAR

21968)

The User Security, page 14 was revised to clarify that although no existing security measures can

give an absolute guarantee, Microsemi FPGAs implement the best security available in the industry

(SAR 34673)

•

The Transient Current, page 15 is new (SAR 36930).

Package names were revised according to standards established in Package Mechanical Drawings

(SAR 34774)

1.8

1.9

Revision 9.0

The following is a summary of the changes in revision 9.0 of this document

•

In Table 20, page 25, the limits in VI were changed from -0.5 to VCCI + 0.5 to -0.5 to VCCA + 0.5

In Table 22, page 27, V_OHwas changed from 3.7 to 2.4 for the min in industrial and military. V_IHhad V_CCI

and that was changed to VCCA

Revision 6.0

The following is a summary of the changes in revision 6.0 of this document.

•

The Ease of Integration, page 3 was updated

The Temperature Grade Offerings, page 7 is new

The Speed Grade Offerings, page 7 is new

The General Description, page 8 was updated

The MultiPlex I/O Modules, page 13 was updated

The User Security, page 14 was updated

Table 6, page 15 was updated

The Power Dissipation, page 16 was updated.

The Static Power Component, page 16 was updated

The Equivalent Capacitance, page 17 was updated

Figure 13, page 19 was updated

Table 10, page 20 was updated.

Figure 14, page 20 was updated.

Table 11, page 21 was updated.

DS2316 Datasheet Revision 16.0

2

40MX and 42MX FPGA Families

2

40MX and 42MX FPGA Families

2.1

Features

The following sections list out various features of the 40MX and 42MX FPGA family devices.

2.1.1

High Capacity

•

Single-Chip ASIC Alternative

3,000 to 54,000 System Gates

Up to 2.5 kbits Configurable Dual-Port SRAM

Fast Wide-Decode Circuitry

Up to 202 User-Programmable I/O Pins

2.1.2

High Performance

•

5.6 ns Clock-to-Out

250 MHz Performance

5 ns Dual-Port SRAM Access

100 MHz FIFOs

7.5 ns 35-Bit Address Decode

2.1.3

2.1.4

HiRel Features

•

Commercial, Industrial, Automotive, and Military Temperature Plastic Packages

Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages

QML Certification

Ceramic Devices Available to DSCC SMD

Ease of Integration

•

Mixed-Voltage Operation (5.0 V or 3.3 V for core and

I/Os), with PCI-Compliant I/Os

•

Up to 100% Resource Utilization and 100% Pin Locking

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Verification Capability with Silicon Explorer II

Low Power Consumption

IEEE Standard 1149.1 (JTAG) Boundary Scan Testing

2.2

Product Profile

The following table gives the features of the products.

Table 1 •

Product profile

A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36

Device

Capacity

System Gates

SRAM Bits

3,000

6,000

14,000

24,000

36,000

54,000

2,560

Logic Modules

Sequential

Combinatorial

Decode

348

336

624

608

954

912

24

1,230

1,184

24

295

547

Clock-to-Out

9.5 ns

5.6 ns

348

6.1 ns

624

6.1 ns

6.3 ns

SRAM Modules

(64x4 or 32x8)

10

Dedicated Flip-Flops

954

1,230

DS2316 Datasheet Revision 16.0

3

40MX and 42MX FPGA Families

Table 1 •

Product profile (continued)

A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36

Device

Maximum Flip-Flops 147

Clocks

273

1

516

2

928

2

1,410

2

1,822

6

1

User I/O (maximum) 57

69

104

140

176

Yes

202

Yes

PCI

Boundary Scan Test

(BST)

Packages (by pin

count)

PLCC

PQFP

VQFP

TQFP

CQFP

PBGA

CPGA

44, 68

100

80

44, 68, 84 84

84

100

80

100, 144, 100, 160, 160, 208 208, 240

160

100

176

208

100

176

172

176

208, 256

272

–

132

DS2316 Datasheet Revision 16.0

4

40MX and 42MX FPGA Families

2.3

Ordering Information

The following figure shows ordering information.All the following tables show plastic and ceramic device

resources, temperature and speed grade offerings.

Figure 1 • Ordering Information

_

PQ

G

100

1

A42MX16

ES

Application (Temperature Range)

Blank = Commercial (0 to +70°C)

I = Industrial (–40 to +85°C)

M = Military (–55 to +125°C)

B = MIL-STD-883

A = Automotive (–40 to +125°C)

Package Lead Count

Lead-Free Packaging

Blank = Standard Packaging

G = RoHS Compliant Packaging

Package Type

PL = Plastic Leaded Chip Carrier

PQ = Plastic Quad Flat Pack

TQ = Thin (1.4 mm) Quad Flat Pack

VQ = Very Thin (1.0 mm) Quad Flat Pack

BG = Plastic Ball Grid Array

CQ =Ceramic Quad Flat Pack

PG =Ceramic Pin Grid Array

Speed Grade

Blank = Standard Speed

–1 = Approximately 15% Faster than Standard

–2 = Approximately 25% Faster than Standard

–3 = Approximately 35% Faster than Standard

–F = Approximately 40% Slower than Standard

Part Number

A40MX02 = 3,000 System Gates

A40MX04 = 6,000 System Gates

A42MX09 = 14,000 System Gates

A42MX16 = 24,000 System Gates

A42MX24 = 36,000 System Gates

A42MX36 = 54,000 System Gates

DS2316 Datasheet Revision 16.0

5

40MX and 42MX FPGA Families

2.4

Plastic Device Resources

Table 2 •

Plastic Device Resources

User I/Os

PQFP PQFP PQFP PQFP PQFP

VQFP TQFP PBGA

PLCC PLCC PLCC 100-

44-Pin 68-Pin 84-Pin Pin

144-

160-

208-

240-

VQFP 100-

80-Pin Pin

176-

272-

Device

A40MX02 34

A40MX04 34

A42MX09

57

69

83

57

69

83

69

72

95

101

125

104

140

150

A42MX16

140

176

A42MX24

A42MX36

202

Note: Package Definitions: PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack,

TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array

2.5

Ceramic Device Resources

Table 3 •

Ceramic Device Resources

User I/Os

Device

CPGA 132-Pin CQFP 172-Pin CQFP 208-Pin CQFP 256-Pin

A42MX09 95

A42MX16

131

A42MX36

176

202

Note: Package Definitions: CQFP = Ceramic Quad Flat Pack

DS2316 Datasheet Revision 16.0

6

40MX and 42MX FPGA Families

2.6

Temperature Grade Offerings

Table 4 •

Temperature Grade Offerings

Package

PLCC 44

PLCC 68

PLCC 84

A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36

C, I, M

C, I, A, M C, I, M

C, I, A, M C, I, A, M C, I, M

C, I, M

PQFP 100 C, I, A, M C, I, A, M C, I, A, M C, I, M

PQFP 144

PQFP 160

PQFP 208

PQFP 240

VQFP 80

C, I

C, I, A, M C, I, M

C, I, A, M

C, I, A, M C, I, A, M C, I, A, M

C, I, A, M

C, I, A, M C, I, A, M

VQFP 100

TQFP 176

PBGA 272

CQFP 172

CQFP 208

CQFP 256

CPGA 132

C, I, A, M C, I, A, M

C, I, A, M C, I, A, M C, I, A, M

C, I, M

C, M, B

Note: C = Commercial

I = Industrial

A = Automotive

M = Military

B = MIL-STD-883 Class B

2.7

Speed Grade Offerings

Table 5 •

Speed Grade Offerings

– F

Std –1 –2 –3

C

I

P

A

M

B

P

Note: See the 40MX and 42MX Automotive Family FPGAs datasheet for details on automotive-grade MX

offerings.

Contact your local Microsemi Sales representative for device availability.

DS2316 Datasheet Revision 16.0

7

40MX and 42MX FPGAs

3

40MX and 42MX FPGAs

3.1

General Description

Microsemi's 40MX and 42MX families offer a cost-effective design solution at 5V. The MX devices are

single-chip solutions and provide high performance while shortening the system design and development

cycle. MX devices can integrate and consolidate logic implemented in multiple programmable array

logics (PALs), complex programmable logic devices (CPLDs), and FPGAs. Example applications include

high-speed controllers and address decoding, peripheral bus interfaces, digital signal processor (DSP),

and co-processor functions.

The MX device architecture is based on Microsemi’s patented antifuse technology implemented in a

0.45µm triple-metal CMOS process. With capacities ranging from 3,000 to 54,000 system gates,

the MX devices provide performance up to 250 MHz, are live on power-up and have one-fifth the standby

power consumption of comparable FPGAs. MX FPGAs provide up to 202 user I/Os and are available in a

wide variety of packages and speed grades.

A42MX24 and A42MX36 devices also feature multiPlex I/Os, which support mixed-voltage systems,

enable programmable peripheral component interconnect (PCI), deliver high-performance operation at

both 5.0V and 3.3V, and provide a low-power mode. The devices are fully compliant with the PCI local

bus specification

(version 2.1). They deliver 200 MHz on-chip operation and 6.1 ns clock-to-output performance.

The 42MX24 and 42MX36 devices include system-level features such as

IEEE Standard 1149.1 (JTAG) Boundary Scan Testing and fast wide-decode modules. In addition, the

A42MX36 device offers dual-port SRAM for implementing fast first in first out (FIFOs), last in first out

(LIFOs), and temporary data storage. The storage elements can efficiently address applications requiring

wide data path manipulation and can perform transformation functions such as those required for

telecommunications, networking, and DSP.

All MX devices are fully tested over automotive and military temperature ranges. In addition, the largest

member of the family, the A42MX36, is available in both CQ208 and CQ256 ceramic packages screened

to MIL-STD-883 levels. For easy prototyping and conversion from plastic to ceramic, the CQ208 and

PQ208 devices are pin-compatible.

3.2

MX Architectural Overview

The MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All

devices within these families are composed of logic modules, I/O modules, routing resources and clock

networks, which are the building blocks for fast logic designs. In addition, the A42MX36 device contains

embedded dual-port SRAM modules, which are optimized for high-speed data path functions such as

FIFOs, LIFOs and scratch pad memory. A42MX24 and A42MX36 also contain wide-decode modules.

3.2.1

Logic Modules

The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of

logic functions with efficient use of interconnect routing resources.(see the following figures).

The logic module can implement the four basic logic functions (NAND, AND, OR and NOR) in gates of

two, three, or four inputs. The logic module can also implement a variety of D-latches, exclusivity

functions, AND-ORs and OR-ANDs. No dedicated hard-wired latches or flip-flops are required in the

array; latches and flip-flops can be constructed from logic modules whenever required in the application.

DS2316 Datasheet Revision 16.0

8

40MX and 42MX FPGAs

Figure 2 • 42MX C-Module Implementation

The 42MX devices contain three types of logic modules: combinatorial (C-modules),

sequential (S-modules) and decode (D-modules). The following figure illustrates the combinatorial logic

module. The S-module, shown in Figure 4, page 10, implements the same combinatorial logic function

as the C-module while adding a sequential element. The sequential element can be configured as either

a D-flip-flop or a transparent latch. The S-module register can be bypassed so that it implements purely

combinatorial logic.

Figure 3 • 42MX C-Module Implementation

A0

B0

S0

D00

D01

D10

D11

Y

S1

A1

B1

DS2316 Datasheet Revision 16.0

9

40MX and 42MX FPGAs

Figure 4 • 42MX S-Module Implementation

D00

D01

D00

D01

D

Q

OUT

Q

OUT

Y

D10

S0

D11

S1

S0

D11

S1

GATE

CLR

Up to 7-Input Function Plus Latch

Up to 7-Input Function Plus D-Type Flip-Flop with Clear

D00

D01

D0

Y

OUT

Q

D10

D

Y

OUT

S0

D11

S1

D1

GATE

CLR

S

Up to 8-Input Function (Same as C-Module)

Up to 4-Input Function Plus Latch with Clear

A42MX24 and A42MX36 devices contain D-modules, which are arranged around the periphery of the

device. D-modules contain wide-decode circuitry, providing a fast, wide-input AND function similar to that

found in CPLD architectures (Figure 5, page 11). The D-module allows A42MX24 and A42MX36 devices

to perform wide-decode functions at speeds comparable to CPLDs and PALs. The output of the

D-module has a programmable inverter for active HIGH or LOW assertion. The D-module output is

hardwired to an output pin, and can also be fed back into the array to be incorporated into other logic.

3.2.2

Dual-Port SRAM Modules

The A42MX36 device contains dual-port SRAM modules that have been optimized for synchronous or

asynchronous applications. The SRAM modules are arranged in 256-bit blocks that can be configured as

32x8 or 64x4. SRAM modules can be cascaded together to form memory spaces of user-definable width

and depth. A block diagram of the A42MX36 dual-port SRAM block is shown in Figure 6, page 11.

The A42MX36 SRAM modules are true dual-port structures containing independent read and write ports.

Each SRAM module contains six bits of read and write addressing (RDAD[5:0] and WRAD[5:0],

respectively) for 64x4-bit blocks. When configured in byte mode, the highest order address bits (RDAD5

and WRAD5) are not used. The read and write ports of the SRAM block contain independent clocks

(RCLK and WCLK) with programmable polarities offering active HIGH or LOW implementation. The

SRAM block contains eight data inputs (WD[7:0]), and eight outputs (RD[7:0]), which are connected to

segmented vertical routing tracks.

The A42MX36 dual-port SRAM blocks provide an optimal solution for high-speed buffered applications

requiring FIFO and LIFO queues. The ACTgen Macro Builder within Microsemi's designer software

provides capability to quickly design memory functions with the SRAM blocks. Unused SRAM blocks can

be used to implement registers for other user logic within the design.

DS2316 Datasheet Revision 16.0

10

40MX and 42MX FPGAs

Figure 5 • A42MX24 and A42MX36 D-Module Implementation

7 Inputs

Hard-Wire t o I/O

Program mable

Invert er

Feedback to Array

Figure 6 • A42MX36 Dual-Port SRAM Block

Latches

WD[7:0]

[7:0]

[5:0]

RDAD[5:0]

SRAM Module

32 x 8 or 64 x 4 Port

Logic

Latches

Write

Port

Read

Logic

(256 Bit s)

[5:0]

WRAD[5:0]

Read

Lat ches

Logic

REN

MODE

BLKEN

WEN

RD[7:0]

RCLK

Write

Logic

Rout ing Tracks

WCLK

3.2.3

Routing Structure

The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O

modules. These routing tracks are metal interconnects that may be continuous or split into segments.

Varying segment lengths allow the interconnect of over 90% of design tracks to occur with only two

antifuse connections. Segments can be joined together at the ends using antifuses to increase their

lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four

antifuses.

3.2.3.1

3.2.3.2

Horizontal Routing

Horizontal routing tracks span the whole row length or are divided into multiple segments and are located

in between the rows of modules. Any segment that spans more than one-third of the row length is

considered a long horizontal segment. A typical channel is shown in Figure 7, page 12. Within horizontal

routing, dedicated routing tracks are used for global clock networks and for power and ground tie-off

tracks. Non-dedicated tracks are used for signal nets.

Vertical Routing

Another set of routing tracks run vertically through the module. There are three types of vertical tracks:

input, output, and long. Long tracks span the column length of the module, and can be divided into

multiple segments. Each segment in an input track is dedicated to the input of a particular module; each

segment in an output track is dedicated to the output of a particular module. Long segments are

uncommitted and can be assigned during routing.

Each output segment spans four channels (two above and two below), except near the top and bottom of

the array, where edge effects occur. Long vertical tracks contain either one or two segments. An example

of vertical routing tracks and segments is shown in Figure 7, page 12.

DS2316 Datasheet Revision 16.0

11

40MX and 42MX FPGAs

3.2.3.3

Antifuse Structures

An antifuse is a “normally open” structure. The use of antifuses to implement a programmable logic

device results in highly testable structures as well as efficient programming algorithms. There are no

pre-existing connections; temporary connections can be made using pass transistors. These temporary

connections can isolate individual antifuses to be programmed and individual circuit structures to be

tested, which can be done before and after programming. For instance, all metal tracks can be tested for

continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified.

Figure 7 • MX Routing Structure

Segmented

Horizontal

Routing

Logic

Modules

Antifuses

Vert ical Rout ing Tracks

3.2.4

Clock Networks

The 40MX devices have one global clock distribution network (CLK). A signal can be put on the CLK

network by being routed through the CLKBUF buffer.

In 42MX devices, there are two low-skew, high-fanout clock distribution networks, referred to as CLKA

and CLKB. Each network has a clock module (CLKMOD) that can select the source of the clock signal

from any of the following (Figure 8, page 13):

•

Externally from the CLKA pad, using CLKBUF buffer

Externally from the CLKB pad, using CLKBUF buffer

Internally from the CLKINTA input, using CLKINT buffer

Internally from the CLKINTB input, using CLKINT buffer

The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal

clock track are located in each horizontal routing channel.

Clock input pads in both 40MX and 42MX devices can also be used as normal I/Os, bypassing the clock

networks.

The A42MX36 device has four additional register control resources, called quadrant clock networks

(Figure 9, page 13). Each quadrant clock provides a local, high-fanout resource to the contiguous logic

modules within its quadrant of the device. Quadrant clock signals can originate from specific I/O pins or

from the internal array and can be used as a secondary register clock, register clear, or output enable.

DS2316 Datasheet Revision 16.0

12

40MX and 42MX FPGAs

Figure 8 • Clock Networks of 42MX Devices

CLKB

CLKINB

CLKINA

CLKA

From

Pads

S0

S1

Internal

Signal

CLKMOD

CLKO(17)

CLKO(16)

CLKO(15)

Clock

Drivers

CLKO(2)

CLKO(1)

Clock Tracks

Figure 9 • Quadrant Clock Network of A42MX36 Devices

QCLKA

QCLKC

Quad

Clock

Modul

Quad

Clock

Modul

QCLK1

QCLK3

QCLKD

QCLKB

*QCLK1IN

*QCLK3IN

S0 S1

S1 S0

Quad

Clock

Modul

Quad

Clock

Modul

QCLK2

QCLK4

*QCLK2IN

*QCLK4IN

S0 S1

S1 S0

Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.

3.2.5

MultiPlex I/O Modules

42MX devices feature Multiplex I/Os and support 5.0 V, 3.3 V, and mixed 3.3 V/5.0 V operations.

The MultiPlex I/O modules provide the interface between the device pins and the logic array. Figure 10,

page 14 is a block diagram of the 42MX I/O module. A variety of user functions, determined by a library

macro selection, can be implemented in the module. (See the Antifuse Macro Library Guide for more

information.) All 42MX I/O modules contain tristate buffers, with input and output latches that can be

configured for input, output, or bidirectional operation.

All 42MX devices contain flexible I/O structures, where each output pin has a dedicated output-enable

control (Figure 10, page 14). The I/O module can be used to latch input or output data, or both, providing

fast set-up time. In addition, the Designer software tools can build a D-type flip-flop using a C-module

combined with an I/O module to register input and output signals. See the Antifuse Macro Library Guide

for more details.

A42MX24 and A42MX36 devices also offer selectable PCI output drives, enabling 100% compliance with

version 2.1 of the PCI specification. For low-power systems, all inputs and outputs are turned off to

reduce current consumption to below 500 A.

To achieve 5.0 V or 3.3 V PCI-compliant output drives on A42MX24 and A42MX36 devices, a chip-wide

PCI fuse is programmed via the Device Selection Wizard in the Designer software (Figure 11, page 14).

When the PCI fuse is not programmed, the output drive is standard.

DS2316 Datasheet Revision 16.0

13

40MX and 42MX FPGAs

Designer software development tools provide a design library of I/O macro functions that can implement

all I/O configurations supported by the MX FPGAs.

Figure 10 • 42MX I/O Module

EN

Q

D

PAD

From Array

To Array

G/CLK*

Q

D

G/CLK*

Note: *Can be configured as a Latch or D Flip-Flop (Using C-Module)

Figure 11 • PCI Output Structure of A42MX24 and A42MX36 Devices

STD

Signal

Out put

PCI

Drive

PCI Enable

Fuse

3.3

Other Architectural Features

The following sections cover other architectural features of 40MX and 42MX FPGAs.

3.3.1

Performance

MX devices can operate with internal clock frequencies of 250 MHz, enabling fast execution of complex

logic functions. MX devices are live on power-up and do not require auxiliary configuration devices and

thus are an optimal platform to integrate the functionality contained in multiple programmable logic

devices. In addition, designs that previously would have required a gate array to meet performance can

be integrated into an MX device with improvements in cost and time-to-market. Using

timing-driven place-and-route (TDPR) tools, designers can achieve highly deterministic device

performance.

3.3.2

User Security

Microsemi FuseLock provides robust security against design theft. Special security fuses are hidden in

the fabric of the device and protect against unauthorized users attempting to access the programming

and/or probe interfaces. It is virtually impossible to identify or bypass these fuses without damaging the

device, making Microsemi antifuse FPGAs protected with the highest level of security available from both

invasive and noninvasive attacks.

Special security fuses in 40MX devices include the Probe Fuse and Program Fuse. The former disables

the probing circuitry while the latter prohibits further programming of all fuses, including the Probe Fuse.

In 42MX devices, there is the Security Fuse which, when programmed, both disables the probing circuitry

and prohibits further programming of the device.

DS2316 Datasheet Revision 16.0

14

40MX and 42MX FPGAs

3.3.3

Programming

Device programming is supported through the Silicon Sculptor series of programmers. Silicon Sculptor is

a compact, robust, single-site and multi-site device programmer for the PC. With standalone software,

Silicon Sculptor is designed to allow concurrent programming of multiple units from the same PC.

Silicon Sculptor programs devices independently to achieve the fastest programming times possible.

After being programmed, each fuse is verified to insure that it has been programmed correctly.

Furthermore, at the end of programming, there are integrity tests that are run to ensure no extra fuses

have been programmed. Not only does it test fuses (both programmed and non-programmed), Silicon

Sculptor also allows self-test to verify its own hardware extensively.

The procedure for programming an MX device using Silicon Sculptor is as follows:

1. Load the *.AFM file

2. Select the device to be programmed

3. Begin programming

When the design is ready to go to production, Microsemi offers device volume-programming services

either through distribution partners or via In-House Programming from the factory.

For more details on programming MX devices, see the AC225: Programming Antifuse Devices

application note and the Silicon Sculptor 3 Programmers User Guide.

3.3.4

Power Supply

MX devices are designed to operate in both 5.0V and 3.3V environments. In particular, 42MX devices

can operate in mixed 5.0 V/3.3 V systems. The following table describes the voltage support of MX

devices.

Table 6 •

Voltage Support of MX Devices

Device VCC VCCA VCCI Maximum Input Tolerance Nominal Output Voltage

40MX 5.0 V

3.3 V

5.5 V

3.6 V

5.0 V

3.3 V

5.0 V

3.3 V

42MX

5.0 V 5.0 V 5.5 V

3.3 V 3.3 V 3.6 V

5.0 V 3.3 V 5.5 V

For A42MX24 and A42MX36 devices the VCCA supply has to be monotonic during power up in order for

the POR to issue reset to the JTAG state machine correctly. For more information, see the AC291: 42MX

Family Devices Power-Up Behavior.

3.3.5

3.3.6

Power-Up/Down in Mixed-Voltage Mode

When powering up 42MX in mixed voltage mode (VCCA = 5.0 V and VCCI = 3.3 V), VCCA must be

greater than or equal to VCCI throughout the power-up sequence. If VCCI exceeds VCCA during

power-up, one of two things will happen:

•

The input protection diode on the I/Os will be forward biased

The I/Os will be at logical High

In either case, ICC rises to high levels. For power-down, any sequence with VCCA and VCCI can be

implemented.

Transient Current

Due to the simultaneous random logic switching activity during power-up, a transient current may appear

on the core supply (VCC). Customers must use a regulator for the VCC supply that can source a

minimum of 100 mA for transient current during power-up. Failure to provide enough power can prevent

the system from powering up properly and result in functional failure. However, there are no reliability

concerns, since transient current is distributed across the die instead of confined to a localized spot.

DS2316 Datasheet Revision 16.0

15

40MX and 42MX FPGAs

Since the transient current is not due to I/O switching, its value and duration are independent of the

VCCI.

3.3.7

Low Power Mode

42MX devices have been designed with a low power mode. This feature, activated with setting the

special LP pin to HIGH for a period longer than 800 ns, is particularly useful for battery-operated systems

where battery life is a primary concern. In this mode, the core of the device is turned off and the device

consumes minimal power with low standby current. In addition, all input buffers are turned off, and all

outputs and bidirectional buffers are tristated. Since the core of the device is turned off, the states of the

registers are lost. The device must be re-initialized when exiting low power mode. I/Os can be driven

during LP mode, and clock pins should be driven HIGH or LOW and should not float to avoid drawing

current. To exit LP mode, the LP pin must be pulled LOW for over

200 µs to allow for charge pumps to power up, and device initialization will begin.

3.4

Power Dissipation

The general power consumption of MX devices is made up of static and dynamic power and can be

expressed with the following equation.

3.4.1

General Power Equation



P = ICCstandby + ICCactive VCCI + IOL VOL N + IOH VCCI – VOH M

EQ 1

where:

•

ICCstandby is the current flowing when no inputs or outputs are changing.

ICCactive is the current flowing due to CMOS switching.

IOL, IOH are TTL sink/source currents.

VOL, VOH are TTL level output voltages.

N equals the number of outputs driving TTL loads to VOL.

M equals the number of outputs driving TTL loads to VOH.

Accurate values for N and M are difficult to determine because they depend on the family type, on design

details, and on the system I/O. The power can be divided into two components: static and active.

3.4.2

3.4.3

Static Power Component

The static power due to standby current is typically a small component of the overall power consumption.

Standby power is calculated for commercial, worst-case conditions. The static power dissipation by TTL

loads depends on the number of outputs driving, and on the DC load current. For instance, a 32-bit bus

sinking 4mA at 0.33V will generate 42mW with all outputs driving LOW, and 140mW with all outputs

driving HIGH. The actual dissipation will average somewhere in between, as I/Os switch states with time.

Active Power Component

Power dissipation in CMOS devices is usually dominated by the dynamic power dissipation.

Dynamic power consumption is frequency-dependent and is a function of the logic and the external I/O.

Active power dissipation results from charging internal chip capacitances of the interconnect,

unprogrammed antifuses, module inputs, and module outputs, plus external capacitances due to PC

board traces and load device inputs. An additional component of the active power dissipation is the totem

pole current in the CMOS transistor pairs. The net effect can be associated with an equivalent

capacitance that can be combined with frequency and voltage to represent active power dissipation.

The power dissipated by a CMOS circuit can be expressed by the equation:



PowerW = C_EQVCCA2 F1

EQ 2

DS2316 Datasheet Revision 16.0

16

40MX and 42MX FPGAs

where:

•

C_EQ= Equivalent capacitance expressed in picofarads (pF)

VCCA = Power supply in volts (V)

F = Switching frequency in megahertz (MHz)

3.4.4

3.4.5

Equivalent Capacitance

Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for

each circuit component of interest. Measurements have been made over a range of frequencies at a

fixed value of VCC. Equivalent capacitance is frequency-independent, so the results can be used over a

wide range of operating conditions. Equivalent capacitance values are shown below.

C_EQValues for Microsemi MX FPGAs

Modules (C_EQM)3.5

Input Buffers (C_EQI)6.9

Output Buffers (C_EQO)18.2

Routed Array Clock Buffer Loads (C_EQCR)1.4

To calculate the active power dissipated from the complete design, the switching frequency of each part

of the logic must be known. The equation below shows a piece-wise linear summation over all

components.

Power = VCCA²m  C_EQMf_m_modules+ n C_EQIf_n_inputs



 

+ p C_EQO+ C_L f_p_outputs+



0.5 q₁C_EQCRf_q1_{routed Clk1}+ r₁_f_q1_{routed Clk1}

+



0.5 q₂C_EQCRf_q2_{routed Clk2}+ r₂_f_q2_{routed Clk2}2

EQ 3

where:

m = Number of logic modules switching at frequency f_m

n = Number of input buffers switching at frequency f_n

p = Number of output buffers switching at frequency f_p

q₁= Number of clock loads on the first routed array clock

q₂= Number of clock loads on the second routed array clock

r₁= Fixed capacitance due to first routed array clock

r₂= Fixed capacitance due to second routed array clock

C_EQM= Equivalent capacitance of logic modules in pF

C_EQI= Equivalent capacitance of input buffers in pF

C_EQO= Equivalent capacitance of output buffers in pF

C_EQCR= Equivalent capacitance of routed array clock in pF

C_L= Output load capacitance in pF

f_m= Average logic module switching rate in MHz

f_n= Average input buffer switching rate in MHz

f_p= Average output buffer switching rate in MHz

f_q1= Average first routed array clock rate in MHz

DS2316 Datasheet Revision 16.0

17

40MX and 42MX FPGAs

f_q2= Average second routed array clock rate in MHz)

Table 7 • Fixed Capacitance Values for MX FPGAs (pF)

Device Type r1 routed_Clk1 r2 routed_Clk2

A40MX02

A40MX04

A42MX09

A42MX16

A42MX24

A42MX36

41.4

68.6

118

165

185

220

N/A

118

165

185

220

3.4.6

Test Circuitry and Silicon Explorer II Probe

MX devices contain probing circuitry that provides built-in access to every node in a design, via the use of

Silicon Explorer II. Silicon Explorer II is an integrated hardware and software solution that, in conjunction

with the Designer software, allows users to examine any of the internal nets of the device while it is

operating in a prototyping or a production system. The user can probe into an MX device without

changing the placement and routing of the design and without using any additional resources. Silicon

Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle

and providing a true representation of the device under actual functional situations.

Silicon Explorer II samples data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II

attaches to a PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer.

Silicon Explorer II allows designers to complete the design verification process at their desks and

reduces verification time from several hours per cycle to a few seconds.

Silicon Explorer II is used to control the MODE, DCLK, SDI and SDO pins in MX devices to select the

desired nets for debugging. The user simply assigns the selected internal nets in the Silicon Explorer II

software to the PRA/PRB output pins for observation. Probing functionality is activated when the MODE

pin is held HIGH.

Figure 12, page 18 illustrates the interconnection between Silicon Explorer II and 40MX devices, while

Figure 13, page 19 illustrates the interconnection between Silicon Explorer II and 42MX devices

To allow for probing capabilities, the security fuses must not be programmed. (See User Security,

page 14 for the security fuses of 40MX and 42MX devices). Table 8, page 19 summarizes the possible

device configurations for probing.

PRA and PRB pins are dual-purpose pins. When the “Reserve Probe Pin” is checked in the Designer

software, PRA and PRB pins are reserved as dedicated outputs for probing. If PRA and PRB pins are

required as user I/Os to achieve successful layout and “Reserve Probe Pin” is checked, the layout tool

will override the option and place user I/Os on PRA and PRB pins.

Figure 12 • Silicon Explorer II Setup with 40MX

16 Logic Analyzer Channels

40MX

Serial Connection

to Windows PC

MODE

SDI

DCLK

Silicon

Explorer II

SDO

PRA

PRB

DS2316 Datasheet Revision 16.0

18

40MX and 42MX FPGAs

Figure 13 • Silicon Explorer II Setup with 42MX

16 Logic Analyzer Channels

42MX

Serial Connection

to Windows PC

MODE

SDI

DCLK

Silicon

Explorer II

SDO

PRA

PRB

Table 8 •

Device Configuration Options for Probe Capability

Security Fuse(s) Programmed Mode PRA, PRB¹

SDI, SDO, DCLK¹

No

Yes

LOW User I/Os²

User I/Os²

HIGH Probe Circuit Outputs Probe Circuit Inputs

Probe Circuit Secured Probe Circuit Secured

1. Avoid using SDI, SDO, DCLK, PRA and PRB pins as input or bidirectional ports.Since

these pins are active during probing, input signals will not pass through these pins and may

cause contention.

2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode.

See the Pin Descriptions, page 85 for information on unused I/O pins

3.4.7

3.4.8

Design Consideration

It is recommended to use a series 70  termination resistor on every probe connector (SDI, SDO,

MODE, DCLK, PRA and PRB). The 70  series termination is used to prevent data transmission

corruption during probing and reading back the checksum.

IEEE Standard 1149.1 Boundary Scan Test (BST) Circuitry

42MX24 and 42MX36 devices are compatible with IEEE Standard 1149.1 (informally known as Joint

Testing Action Group Standard or JTAG), which defines a set of hardware architecture and mechanisms

for cost-effective board-level testing. The basic MX boundary-scan logic circuit is composed of the TAP

(test access port), TAP controller, test data registers and instruction register (Figure 14, page 20). This

circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and BYPASS)

and some optional instructions. Table 9, page 20 describes the ports that control JTAG testing, while

Table 10, page 20 describes the test instructions supported by these MX devices.

Each test section is accessed through the TAP, which has four associated pins: TCK (test clock input),

TDI and TDO (test data input and output), and TMS (test mode selector).

The TAP controller is a four-bit state machine. The '1's and '0's represent the values that must be present

at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the

instruction register or the data register is operating in that state.

The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals

for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset

state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for

five TCK cycles.

42MX24 and 42MX36 devices support three types of test data registers: bypass, device identification,

and boundary scan. The bypass register is selected when no other register needs to be accessed in a

device. This speeds up test data transfer to other devices in a test data path. The 32-bit device

identification register is a shift register with four fields (lowest significant byte (LSB), ID number, part

number and version). The boundary-scan register observes and controls the state of each I/O pin.

DS2316 Datasheet Revision 16.0

19

40MX and 42MX FPGAs

Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and

parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a

device into a boundary-scan register chain, which starts at the TDI pin and ends at the TDO pin. The

parallel ports are connected to the internal core logic tile and the input, output and control ports of an I/O

buffer to capture and load data into the register to control or observe the logic state of each I/O.

Figure 14 • 42MX IEEE 1149.1 Boundary Scan Circuitry

Boundary Scan Register

Output

MUX

TDO

Bypass

Register

Control Logic

JTAG

TMS

TCK

JTAG

TDI

Instruction

Decode

TAP Controller

Instruction

Register

Table 9 •

Test Access Port Descriptions

Description

Port

TMS

Serial input for the test logic control bits. Data is captured on the rising edge of the test logic

(Test Mode Select) clock (TCK).

TCK

Dedicated test logic clock used serially to shift test instruction, test data, and control inputs

(Test Clock Input) on the rising edge of the clock, and serially to shift the output data on the falling edge of the

clock. The maximum clock frequency for TCK is 20 MHz.

TDI

Serial input for instruction and test data. Data is captured on the rising edge of the test logic

clock.

(Test Data Input)

TDO

Serial output for test instruction and data from the test logic. TDO is set to an inactive drive

(Test Data Output) state (high impedance) when data scanning is not in progress.

Table 10 • Supported BST Public Instructions

IR Code Instruction

Instruction

(IR2.IR0) Type

Description

EXTEST

000

Mandatory Allows the external circuitry and board-level interconnections to be

tested by forcing a test pattern at the output pins and capturing test

results at the input pins.

SAMPLE/PRELOAD 001

Mandatory Allows a snapshot of the signals at the device pins to be captured

and examined during operation

HIGH Z

CLAMP

101

110

Optional

Tristates all I/Os to allow external signals to drive pins.

See the IEEE Standard 1149.1 specification.

Optional

Allows state of signals driven from component pins to be determined

from the Boundary-Scan Register. See the IEEE Standard 1149.1

specification for details.

BYPASS

111

Mandatory Enables the bypass register between the TDI and TDO pins. The

test data passes through the selected device to adjacent devices in

the test chain.

DS2316 Datasheet Revision 16.0

20

40MX and 42MX FPGAs

3.4.9

JTAG Mode Activation

The JTAG test logic circuit is activated in the Designer software by selecting Tools > Device Selection.

This brings up the Device Selection dialog box as shown in the following figure. The JTAG test logic

circuit can be enabled by clicking the “Reserve JTAG Pins” check box. The following table explains the

pins' behavior in either mode.

Figure 15 • Device Selection Wizard

Table 11 • Boundary Scan Pin Configuration and Functionality

Reserve JTAG Checked

Unchecked

TCK

BST input; must be terminated to logical HIGH or LOW to avoid floating User I/O

TDI, TMS

TDO

BST input; may float or be tied to HIGH

User I/O

BST output; may float or be connected to TDI of another device

3.4.10 TRST Pin and TAP Controller Reset

An active reset (TRST) pin is not supported; however, MX devices contain power-on circuitry that resets

the boundary scan circuitry upon power-up. Also, the TMS pin is equipped with an internal pull-up

resistor. This allows the TAP controller to remain in or return to the Test-Logic-Reset state when there is

no input or when a logical 1 is on the TMS pin. To reset the controller, TMS must be HIGH for at least five

TCK cycles.

3.4.11 Boundary Scan Description Language (BSDL) File

Conforming to the IEEE Standard 1149.1 requires that the operation of the various JTAG components be

documented. The BSDL file provides the standard format to describe the JTAG components that can be

used by automatic test equipment software. The file includes the instructions that are supported,

instruction bit pattern, and the boundary-scan chain order. For an in-depth discussion on BSDL files, see

the BSDL Files Format Description application note.

BSDL files are grouped into two categories - generic and device-specific. The generic files assign all user

I/Os as inouts. Device-specific files assign user I/Os as inputs, outputs or inouts.

Generic files for MX devices are available on the Microsemi SoC Product Group's website:

http://www.microsemi.com/soc/techdocs/models/bsdl.html.

3.5

Development Tool Support

The MX family of FPGAs is fully supported by Libero^®integrated design environment (IDE). Libero IDE is

a design management environment, seamlessly integrating design tools while guiding the user through

the design flow, managing all design and log files, and passing necessary design data among tools.

Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the

entire design in a single environment. Libero IDE includes SynplifyPro from Synopsys, ModelSim^®HDL

Simulator from Mentor Graphics^®and Viewdraw.

Libero IDE includes place-and-route and provides a comprehensive suite of backend support tools for

FPGA development, including timing-driven place-and-route, and a world-class integrated static timing

analyzer and constraints editor.

DS2316 Datasheet Revision 16.0

21

40MX and 42MX FPGAs

Additionally, the back-annotation flow is compatible with all the major simulators and the simulation

results can be cross-probed with Silicon Explorer II, Microsemi’s integrated verification and logic analysis

tool. Another tool included in the Libero software is the SmartGen macro builder, which easily creates

popular and commonly used logic functions for implementation into your schematic or HDL design.

Microsemi’s Libero software is compatible with the most popular FPGA design entry and verification tools

from companies such as Mentor Graphics, Synopsys, and Cadence design systems.

See the Libero IDE web content at www.microsemi.com/soc/products/software/libero/default.aspx for

further information on licensing and current operating system support.

3.6

Related Documents

The following sections give the list of related documents which can be refered for this datasheet.

3.6.1

Application Notes

•

AC278: BSDL Files Format Description

AC225: Programming Antifuse Devices

AC168: Implementation of Security in Microsemi Antifuse FPGAs

3.6.2

User Guides and Manuals

•

Antifuse Macro Library Guide

•

Silicon Sculptor Programmers User Guide

3.6.3

Miscellaneous

Libero IDE Flow Diagram

3.7

5.0 V Operating Conditions

The following tables show 5.0 V operating conditions.

Table 12 • Absolute Maximum Ratings for 40MX Devices*

Symbol Parameter

Limits

Units

VCC

VI

DC Supply Voltage

–0.5 to +7.0

V

Input Voltage

–0.5 to VCC+0.5 V

VO

Output Voltage

t_STG

Storage Temperature –65 to +150

°C

Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. Exposure to absolute maximum rated conditions for extended periods may affect device

reliability. Devices should not be operated outside the recommended operating conditions.

Table 13 • Absolute Maximum Ratings for 42MX Devices*

Symbol Parameter

VCCI DC Supply Voltage for I/Os –0.5 to +7.0

VCCA DC Supply Voltage for Array –0.5 to +7.0

Limits

Units

V

VI

Input Voltage

–0.5 to VCCI+0.5 V

–65 to +150 °C

VO

t_STG

Output Voltage

Storage Temperature

DS2316 Datasheet Revision 16.0

22

40MX and 42MX FPGAs

Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. Exposure to absolute maximum rated conditions for extended periods may affect device

reliability. Devices should not be operated outside the recommended operating conditions.

Table 14 • Recommended Operating Conditions

Parameter

Commercial Industrial Military

Units

Temperature Range* 0 to +70

–40 to +85 –55 to +125 °C

VCC (40MX)

VCCA (42MX)

VCCI (42MX)

4.75 to 5.25 4.5 to 5.5 4.5 to 5.5

V

4.75 to 5.25 4.5 to 5.5 4.5 to 5.5

Note: * Ambient temperature (T_A) is used for commercial and industrial grades; case temperature (T_C) is used

for military grades.

3.7.1

5 V TTL Electrical Specifications

The following tables show 5 V TTL electrical specifications.

Table 15 • 5V TTL Electrical Specifications

Commercial

Min. Max.

Commercial -F Industrial

Military

Symbol

Parameter

Min. Max.

Units

VOH¹

IOH = –10 mA 2.4

IOH = –4 mA

IOL = 10 mA

IOL = 6 mA

2.4

V

3.7

VOL¹

0.5

0.4

VIL

–0.3 0.8

VIH (40MX)

VIH (42MX)²

2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0

VCC + 0.3 V

VCCI + 0.3 V

2.0 VCCI +

0.3

2.0 VCCI +

0.3

2.0 VCCI +

0.3

2.0

IIL

VIN = 0.5 V

VIN = 2.7 V

–10

500

–10

500

–10

500

–10

500

µA

IIH

µA

ns

Input Transition

Time, T_Rand T_F

C_IOI/O

Capacitance

10

3

10

25

10

25

pF

Standby

A40MX02,

A40MX04

mA

Current, ICC³

A42MX09

A42MX16

5

25

mA

6

A42MX24,

A42MX36

20

Low power

42MX devices

0.5

ICC – 5.0

ICC – 5.0 mA

mode Standby only

Current

IIO, I/O source Can be derived from the IBIS model

sink current (http://www.microsemi.com/soc/techdocs/models/ibis.html)

DS2316 Datasheet Revision 16.0

23

40MX and 42MX FPGAs

1. Only one output tested at a time. VCC/VCCI = Min.

2. VIH(Min) is 2.4V for A42MX36 family. This applies only to VCCI of 5V and is not applicable to VCCI of 3.3V

3. All outputs unloaded. All inputs = VCC/VCCI or GND

3.8

3.3 V Operating Conditions

The following table shows 3.3 V operating conditions.

Table 16 • Absolute Maximum Ratings for 40MX Devices*

Symbol Parameter

Limits

Units

VCC

VI

DC Supply Voltage

–0.5 to +7.0

V

Input Voltage

–0.5 to VCC + 0.5 V

VO

Output Voltage

t_STG

Storage Temperature –65 to + 150

°C

Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. Exposure to absolute maximum rated conditions for extended periods may affect device

reliability. Devices should not be operated outside the recommended operating conditions.

Table 17 • Absolute Maximum Ratings for 42MX Devices*

Symbol Parameter

Limits

Units

VCCI

VCCA

VI

DC Supply Voltage for I/Os –0.5 to +7.0

DC Supply Voltage for Array –0.5 to +7.0

V

Input Voltage

–0.5 to VCCI+0.5 V

–65 to +150 °C

VO

Output Voltage

Storage Temperature

t_STG

Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. Exposure to absolute maximum rated conditions for extended periods may affect device

reliability. Devices should not be operated outside the recommended operating conditions.

Table 18 • Recommended Operating Conditions

Parameter

Commercial Industrial Military

Units

Temperature Range* 0 to +70

–40 to +85 –55 to +125 °C

VCC (40MX)

VCCA (42MX)

VCCI (42MX)

3.0 to 3.6

3.0 to 3.6 3.0 to 3.6

V

Note: *Ambient temperature (T_A) is used for commercial and industrial grades; case temperature (T_C) is used

for military grades.

All the following tables show various specifications and operating conditions of 40MX and 42MX FPGAs.

DS2316 Datasheet Revision 16.0

24

40MX and 42MX FPGAs

3.8.1

3.3 V LVTTL Electrical Specifications

Table 19 • 3.3V LVTTL Electrical Specifications

Commercial

Commercial -F

Min. Max.

2.15

Industrial

Min. Max.

2.4

Military

Min. Max.

2.4

Symbol

VOH¹

VOL¹

Parameter Min. Max.

Units

IOH = –4 mA 2.15

V

IOL = 6 mA

0.4

0.48

VIL

–0.3 0.8

VIH (40MX)

VIH (42MX)

IIL

2.0

VCC + 0.3 2.0

VCC + 0.3 2.0 VCC + 0.3 V

VCCI + 0.3 2.0 VCCI + 0.3 V

VCCI + 0.3 2.0

–10

500

–10

500

–10

500

–10

500

µA

ns

IIH

Input Transition

Time, T_Rand T_F

C_IOI/O

Capacitance

10

3

10

25

10

25

pF

Standby

A40MX02,

A40MX04

mA

Current, ICC²

A42MX09

A42MX16

5

25

mA

6

A42MX24,

A42MX36

15

Low-Power

42MX

0.5

ICC - 5.0

ICC - 5.0 mA

Mode Standby devices only

Current

IIO, I/O source Can be derived from the IBIS model (http://www.microsemi.com/soc/techdocs/models/ibis.html)

sink current

1. Only one output tested at a time. VCC/VCCI = Min.

2. All outputs unloaded. All inputs = VCC/VCCI or GND.

3.9

Mixed 5.0 V / 3.3 V Operating Conditions (for 42MX

Devices Only)

Table 20 • Absolute Maximum Ratings*

Symbol Parameter

VCCI DC Supply Voltage for I/Os –0.5 to +7.0

VCCA DC Supply Voltage for Array –0.5 to +7.0

Limits

Units

V

VI

Input Voltage

–0.5 to VCCA +0.5 V

–0.5 to VCCI + 0.5 V

–65 to +150 °C

VO

t_STG

Output Voltage

Storage Temperature

Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. Exposure to absolute maximum rated conditions for extended periods may affect device

DS2316 Datasheet Revision 16.0

25

40MX and 42MX FPGAs

reliability. Devices should not be operated outside the recommended operating conditions.

Table 21 • Recommended Operating Conditions

Parameter

Commercial Industrial Military

Units

Temperature Range* 0 to +70

–40 to +85 –55 to +125 °C

VCCA

VCCI

4.75 to 5.25 4.5 to 5.5 4.5 to 5.5

3.14 to 3.47 3.0 to 3.6 3.0 to 3.6

V

Note: *Ambient temperature (T_A) is used for commercial and industrial grades; case temperature (T_C) is used

for military grades.

DS2316 Datasheet Revision 16.0

26

40MX and 42MX FPGAs

3.9.1

Mixed 5.0V/3.3V Electrical Specifications

Table 22 • Mixed 5.0V/3.3V Electrical Specifications

Commercial

Min. Max.

Commercial –F Industrial

Military

Symbol

Parameter

Min. Max.

Units

VOH¹

IOH = –10 mA 2.4

IOH = –4 mA

IOL = 10 mA

IOL = 6 mA

2.4

V

2.4

VOL¹

0.5

0.4

VIL

VIH²

IL

–0.3 0.8

2.0 VCCA + 0.3 2.0 VCCA + 0.3 2.0 VCCA + 0.3 2.0 VCCA + 0.3 V

VIN = 0.5 V

VIN = 2.7 V

–10

500

–10

500

–10

500

–10

500

µA

ns

IH

Input Transition

Time, T_Rand T_F

C

_IOI/O Capacitance

10

5

10

25

10

25

10

25

pF

Standby Current,

ICC³

A42MX09

A42MX16

mA

6

A42MX24,

A42MX36

20

Low Power Mode

Standby Current

0.5

ICC – 5.0

ICC – 5.0 mA

IIO I/O source sink Can be derived from the IBIS model (http://www.microsemi.com/soc/techdocs/models/ibis.html)

current

1. Only one output tested at a time. VCCI = min.

2. VIH(Min) is 2.4V for A42MX36 family. This applies only to VCCI of 5V and is not applicable to VCCI of 3.3V

3. All outputs unloaded. All inputs = VCCI or GND

3.9.2

Output Drive Characteristics for 5.0 V PCI Signaling

MX PCI device I/O drivers were designed specifically for high-performance PCI systems. Figure 16,

page 30 shows the typical output drive characteristics of the MX devices. MX output drivers are

compliant with the PCI Local Bus Specification.

Table 23 • DC Specification (5.0 V PCI Signaling)¹

PCI

Min.

4.75

2.0

MX

Symbol Parameter

Condition

Max.

Min. Max.

4.75 5.25²

Units

V

VCCI

VIH³

VIL

Supply Voltage for I/Os

5.25

Input High Voltage

Input Low Voltage

VCC + 0.5 2.0

VCCI + 0.3

V

–0.5

0.8

70

–0.3 0.8

V

IIH

Input High Leakage Current VIN = 2.7 V

Input Low Leakage Current VIN=0.5 V

10

µA

V

IIL

–70

–10

VOH

Output High Voltage

IOUT = –2 mA

IOUT = –6 mA

2.4

3.84

VOL

Output Low Voltage

IOUT = 3 mA, 6 mA

0.55

0.33

V

DS2316 Datasheet Revision 16.0

27

40MX and 42MX FPGAs

Table 23 • DC Specification (5.0 V PCI Signaling)¹(continued)

PCI

MX

Symbol Parameter

Condition

Min.

Max.

10

Min. Max.

Units

pF

C_IN

Input Pin Capacitance

10

C_CLK

L_PIN

CLK Pin Capacitance

Pin Inductance

5

12

pF

20

< 8 nH⁴

nH

1. PCI Local Bus Specification, Version 2.1, Section 4.2.1.1.

2. Maximum rating for VCCI is –0.5 V to 7.0 V

3. VIH(Min) is 2.4V for A42MX36 family. This applies only to VCCI of 5V and is not applicable to VCCI of 3.3V.

4. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and

capacitance.

Table 24 • AC Specifications (5.0V PCI Signaling)^*

PCI

MX

Symbol Parameter

ICL Low Clamp Current

Condition

Min.

Max. Min. Max. Units

–5 < VIN  –1

–25 + (VIN +1) /0.015

–60 –10 mA

Slew (r) Output Rise Slew Rate 0.4 V to 2.4 V load

Slew (f) Output Fall Slew Rate 2.4 V to 0.4 V load

1

5

1.8 2.8

2.8 4.3

V/ns

Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.1.2.

DS2316 Datasheet Revision 16.0

28

40MX and 42MX FPGAs

3.9.3

Output Drive Characteristics for 3.3 V PCI Signaling

Table 25 • DC Specification (3.3 V PCI Signaling)¹

PCI

Min.

3.0

MX

Symbol Parameter

Condition

Max.

Min. Max.

3.0 3.6²

Units

VCCI

VIH

VIL

Supply Voltage for I/Os

Input High Voltage

Input Low Voltage

3.6

V

0.5

VCC + 0.5 0.5 VCCI + 0.3 V

–0.5

0.8

70

–0.3 0.8

10

V

IIH

Input High Leakage Current VIN = 2.7 V

Input Leakage Current

µA

V

IIL

–70

–10

VOH

VOL

Output High Voltage

Output Low Voltage

IOUT = –2 mA

0.9

5

3.3

IOUT = 3 mA,

6 mA

0.1

0.1 VCCI

V

C_IN

Input Pin Capacitance

CLK Pin Capacitance

Pin Inductance

10

12

20

10

pF

nH

C_CLK

L_PIN

10

< 8 nH³

1. PCI Local Bus Specification, Version 2.1, Section 4.2.2.1.

2. Maximum rating for VCCI is–0.5 V to 7.0V.

3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and

capacitance.

Table 26 • AC Specifications for (3.3 V PCI Signaling)^*

PCI

MX

Max.

Condition

Units

mA

Symbol Parameter

ICL Low Clamp Current

Min.

Max. Min.

–5 < VIN  –1

–25 + (VIN +1) /0.015

–60

–10

2.8

4.0

Slew (r) Output Rise Slew Rate 0.2 V to 0.6 V load

Slew (f) Output Fall Slew Rate 0.6 V to 0.2 V load

1

4

1.8

2.8

V/ns

Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.2.2.

DS2316 Datasheet Revision 16.0

29

40MX and 42MX FPGAs

Figure 16 • Typical Output Drive Characteristics (Based Upon Measured Data)

0.50

0.45

0.40

PCI IOL Maximum

0.35

0.30

0.25

0.20

MX PCI IOL

0.15

0.10

PCI IOL Minimum

0.05

0.00

0

1

2

3

4

5

6

–0.05

–0.10

–0.15

–0.20

PCI IOH Maximum

MX PCI IOH

PCI IOH Minimum

Voltage Out (V)

3.9.4

Junction Temperature (T_J)

The temperature variable in the Designer software refers to the junction temperature, not the ambient

temperature. This is an important distinction because the heat generated from dynamic power

consumption is usually hotter than the ambient temperature. The following equation can be used to

calculate junction temperature.

Junction Temperature = T

+ T_a1

EQ 4

where:

•

T_a= Ambient Temperature

T = Temperature gradient between junction (silicon) and ambient

T = _ja* P (2)

P = Power

_ja= Junction to ambient of package. _janumbers are located in Table 27, page 31.

3.9.5

Package Thermal Characteristics

The device junction-to-case thermal characteristic is _jc, and the junction-to-ambient air characteristic is

_ja. The thermal characteristics for _jaare shown with two different air flow rates.

The maximum junction temperature is 150C.

Maximum power dissipation for commercial- and industrial-grade devices is a function of _ja.

DS2316 Datasheet Revision 16.0

30

40MX and 42MX FPGAs

A sample calculation of the absolute maximum power dissipation allowed for a TQ176 package at

commercial temperature and still air is given in the following equation

Max  junction temp  C – Max  ambient temp  C

150C – 70C

28C  W

----------------------------------------------------------------------------------------------------------------------------------------------------

----------------------------------

= 2.86W

MaximumPowerAllowed =

=

_jaC  W

EQ 5

The maximum power dissipation for military-grade devices is a function of _jc. A sample calculation of the

absolute maximum power dissipation allowed for CQFP 208-pin package at military temperature and still

air is given in the following equation

Max  junction temp  C – Max  ambient temp  C

150C – 125C

6.3C  W

----------------------------------------------------------------------------------------------------------------------------------------------------

-------------------------------------

= 3.97W

MaximumPowerAllowed =

=

_jcC  W

EQ 6

Table 27 • Package Thermal Characteristics

_ja

1.0 m/s

2.5 m/s

Plastic Packages

Pin Count _jc

Still Air 200 ft/min. 500 ft/min. Units

Plastic Quad Flat Pack

100

144

160

208

240

12.0 27.8

23.4

22.8

22.5

22.3

24.5

21.0

18.9

19.9

31.9

21.2

21.1

20.8

22.0

19.4

17.6

18.0

29.4

°C/W

10.0 26.2

8.0

8.5

26.1

25.6

Plastic Leaded Chip Carrier 44

16.0 20.0

13.0 25.0

12.0 22.5

11.0 24.7

12.0 38.2

Plastic Leaded Chip Carrier 68

Plastic Leaded Chip Carrier 84

Thin Plastic Quad Flat Pack 176

Very Thin Plastic Quad Flat 80

Pack

Very Thin Plastic Quad Flat 100

Pack

10.0 35.3

29.4

14.9

27.1

13.9

°C/W

Plastic Ball Grid Array

Ceramic Packages

272

3.0

18.3

Ceramic Pin Grid Array

Ceramic Quad Flat Pack

132

208

256

4.8

2.0

25.0

22.0

20.0

20.6

19.8

16.5

18.7

18.0

15.0

°C/W

DS2316 Datasheet Revision 16.0

31

40MX and 42MX FPGAs

3.10 Timing Models

The following figures show various timing models.

Figure 17 • 40MX Timing Model*

Predicted

Routing

Delays

Input Delay

I/O Module

Internal Delays

Output Delay

I/O Module

t_INYL= 0.62 ns

t_IRD2= 2.59 ns

Logic Module

t_PD= 1.24 ns

t_DLH= 3.32 ns

_ENHZ= 7.92 ns

t

_RD1= 1.28 ns

t_IRD1= 2.09 ns

t_IRD4= 3.64 ns

t

t_RD2= 1.80 ns

t

_RD4= 2.33 ns

_RD8= 4.93 ns

t_CO= 1.24 ns

t

_IRD8= 5.73 ns

Array

Clock

t_CKH= 4.55 ns

FO = 128

F_MAX= 180 MHz

Note: Values are shown for 40MX –3 speed grade devices at 5.0 V worst-case commercial conditions.

Figure 18 • 42MX Timing Model

Input Delays

Internal Delays

Predicted

Routing

Delays

Output Delays

I/O Module

t

_IRD1= 2.0 ns¹

t_INYL= 0.8 ns

Combinatorial

Logic Module

t_DLH= 2.5 ns

t

_RD1= 0.7 ns

_RD2= 1.9 ns

D

Q

t_PD=1.2 ns

t_RD4= 1.4 ns

t_RD8= 2.3 ns

I/O Module

G

t_DLH= 2.5 ns

Sequential

t _NH= 0.0 ns

I

Logic Module

t_INSU= 0.3 ns

t_INGL= 1.3 ns

D

Q

D

G

Q

Comb.

Logic

Include

t_RD1= 0.70 ns

t

_ENHZ= 4.9 ns

t_OUTH= 0.00 ns

t_OUTSU= 0.3 ns

t

_SUD= 0.3 ns

_HD= 0.00 ns

CO = 1.3 ns

Array

Clocks

t_GLH= 2.6 ns

FO = 32

t

_CKH= 2.70 ns

F

_MAX= 296 MHz

t_LCO= 5.2 ns (light loads, pad-to-pad)

Note: 1. Input module predicted routing delay

Note: 2. Values are shown for A42MX09 –3 speed grade devices at 5.0 V worst-case commercial conditions.

DS2316 Datasheet Revision 16.0

32

40MX and 42MX FPGAs

Figure 19 • 42MX Timing Model (Logic Functions Using Quadrant Clocks)

Predicted

Routing

Delays

Internal Delays

Input Delays

Output Delays

I/O Module

t_INPY= 1.0 ns

t_IRD1= 2.0 ns

Combinatorial

Module

t_DLH= 2.6 ns

t_RD1= 0.9 ns

t_RD2= 1.3 ns

Q

D

G

t_PD=1.3 ns

t

_RD4= 2.0 ns

Decode

Module

t_INH= 0.0 ns

t_INSU= 0.5 ns

t_INGO= 1.4 ns

t_RDD= 0.3 ns

t_PDD= 1.6 ns

I/O Module

t

_DLH= 2.6 ns

Sequential

Logic Module

t_RD1= 0.9 ns

D

G

Q

D

Q

Comb.

Logic

Include

t_ENHZ= 5.3 ns

t_LH= 0.00 ns

t_LSU= 0.5 ns

t_GHL= 2.9 ns

t_CO= 1.3 ns

t_SUD= 3.0 ns

t_HD= 0.0 ns

Quadrant

Clocks

t

_CKH=3.03 ns¹

F

=180 MHz

MAX

Note: 1. Load-dependent

Note: 2. Values are shown for A42MX36 –3 speed grade devices at 5.0 V worst-case commercial conditions

DS2316 Datasheet Revision 16.0

33

40MX and 42MX FPGAs

Figure 20 • 42MX Timing Model (SRAM Functions)

Input Delays

I/O Module

t_INPY= 1 .0 ns

t_IRD1= 2.0 ns

D

G

Q

Predicted

Routing

Delays

I/O Module

t_DLH= 2.6 ns

t

_INSU= 0.5 ns

_INH= 0.0 ns

t_INGO= 1.4 ns

RD [7:0]

RDAD [5:0]

REN

WD [7:0]

t

_RD1= 0.9 ns

WRAD [5:0]

BLKEN

D

G

Q

WEN

WCLK

RCLK

t_ADSU= 1.6 ns

t_ADH= 0.0 ns

_WENSU= 2.7 ns

t_BENS= 2.8 ns

t

_ADSU= 1.6 ns

t_ADH= 0.0 ns

_RENSU= 0.6 ns

t_RCO= 3.4 ns

t_GHL= 2.9 ns

_LSU= 0.5 ns

t_LH= 0.0 ns

Array

Clocks

t

F_MAX= 167 MHz

Note: Values are shown for A42MX36 –3 speed grade devices at 5.0 V worst-case commercial conditions.

3.10.1 Parameter Measurement

The following figures show parameter measurement details.

Figure 21 • Output Buffer Delays

E

D

To AC test loads (shown below)

PAD

TRIBUFF

In

E

50% 50%

VOH

50% 50%

VCCI

50%

VOH

1.5 V

50%

1.5 V

PAD

VOL

PAD

GND

1.5 V

PAD

90%

10%

VOL

t_DLH

t_DHL

t_ENZL

t_ENLZ

t_ENHZ

t_ENZH

DS2316 Datasheet Revision 16.0

34

40MX and 42MX FPGAs

Figure 22 • AC Test Loads

Load 1

Load 2

(Used to measure propagation delay)

(Used to measure rising/falling edges)

VCCI

GND

To the output under test

R to VCCI for t_PLZ/ t_PZL

R to GND for t_PHZ/ t_PZH

R =1 k

35 pF

To the output under test

35 pF

Figure 23 • Input Buffer Delays

Y

PA D

INBUF

3 V

1.5 V 1.5 V

PAD

0 V

VCCI

50%

Y

GND

50%

t_INYH

t_INYL

Figure 24 • Module Delays

S

A

B

Y

S, A or B

50% 50%

50%

Y

t

PLH

PHL

t

50%

PHL

t

PLH

DS2316 Datasheet Revision 16.0

35

40MX and 42MX FPGAs

3.10.2 Sequential Module Timing Characteristics

The following figure shows sequential module timing characteristics.

Figure 25 • Flip-Flops and Latches

D

E

CLK

Y

PRE

CLR

(Positive Edge-Triggered)

t_HD

D*

t_SUD

t_A

t_WCLKA

G, CLK

t_SUENA

t_WCLK1

t_HENA

t_CO

E

Q

t_RS

PRE, CLR

t_WASYN

Note: *D represents all data functions involving A, B, and S for multiplexed flip-flops.

3.10.3 Sequential Timing Characteristics

The following figures show sequential timing characteristics.

Figure 26 • Input Buffer Latches

PA D

G

DATA

IBDL

CLK PA D

DATA

G

t_INH

INSU

t_INSU

t_HEXT

CLK

t_{SU EXT}

DS2316 Datasheet Revision 16.0

36

40MX and 42MX FPGAs

Figure 27 • Output Buffer Latches

D

G

PAD

OBDLHS

D

G

t

OUTSU

t

OUTH

3.10.4 Decode Module Timing

The following figure shows decode module timing.

Figure 28 • Decode Module Timing

A

B

C

D

E

F

Y

H

G

A–G, H

Y

50%

t_PHL

t_PLH

3.10.5 SRAM Timing Characteristics

The following figure shows SRAM timing characteristics.

Figure 29 • SRAM Timing Characteristics

Read Port

Write Port

WRAD [5:0]

BLKEN

WEN

RDAD [5:0]

LEW

RAM Array

32x8 or 64x4

(256 Bits)

REN

WCLK

RCLK

WD [7:0]

RD [7:0]

DS2316 Datasheet Revision 16.0

37

40MX and 42MX FPGAs

3.10.6 Dual-Port SRAM Timing Waveforms

The following figures show dual-port SRAM timing waveforms.

Figure 30 • 42MX SRAM Write Operation

t_RCKHL

WCLK

t_ADH

t_ADSU

Valid

WD[7:0]

WRAD[5:0]

t_WENSU

t_WENH

WEN

t_BENSU

Valid

t_BENH

BLKEN

Note: Identical timing for falling edge clock

Figure 31 • 42MX SRAM Synchronous Read Operation

t_CKHL

t_RCKHL

RCLK

REN

t_RENSU

t_RENH

t_ADSU

Valid

t_ADH

RDAD[5:0]

t_RCO

t_DOH

Old Data

New Data

RD[7:0]

Note: Identical timing for falling edge clock

Figure 32 • 42MX SRAM Asynchronous Read Operation—Type 1 (Read Address Controlled)

t_RDADV

RDAD[5:0]

RD[7:0]

ADDR1

ADDR2

t_RPD

t_DOH

Data 1

Data 2

DS2316 Datasheet Revision 16.0

38

40MX and 42MX FPGAs

Figure 33 • 42MX SRAM Asynchronous Read Operation—Type 2 (Write Address Controlled)

WEN

t_WENSU

t_WENH

WD[7:0]

WRAD[5:0]

BLKEN

Valid

t_ADH

tADSU

WCLK

t_RPD

t_DOH

Old Data

New Data

RD[7:0]

3.10.7 Predictable Performance: Tight Delay Distributions

Propagation delay between logic modules depends on the resistive and capacitive loading of the routing

tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as

the length of routing tracks, the number of interconnect elements, or the number of inputs increases.

From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout

(number of loads) driven by a module. Higher fanout usually requires some paths to have longer routing

tracks.

The MX FPGAs deliver a tight fanout delay distribution, which is achieved in two ways: by decreasing the

delay of the interconnect elements and by decreasing the number of interconnect elements per path.

Microsemi’s patented antifuse offers a very low resistive/capacitive interconnect. The antifuses,

fabricated in 0.45 µm lithography, offer nominal levels of 100  resistance and 7.0 fF capacitance per

antifuse.

MX fanout distribution is also tight due to the low number of antifuses required for each interconnect

path. The proprietary architecture limits the number of antifuses per path to a maximum of four, with

90 percent of interconnects using only two antifuses.

3.11

Timing Characteristics

Device timing characteristics fall into three categories: family-dependent, device-dependent, and design-

dependent. The input and output buffer characteristics are common to all MX devices. Internal routing

delays are device-dependent; actual delays are not determined until after place-and-route of the user's

design is complete. Delay values may then be determined by using the Designer software utility or by

performing simulation with post-layout delays.

3.11.1 Critical Nets and Typical Nets

Propagation delays are expressed only for typical nets, which are used for initial design performance

evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are

determined by net property assignment in Microsemi's Designer software prior to placement and routing.

Up to 6% of the nets in a design may be designated as critical.

DS2316 Datasheet Revision 16.0

39

40MX and 42MX FPGAs

3.11.2 Long Tracks

Some nets in the design use long tracks, which are special routing resources that span multiple rows,

columns, or modules. Long tracks employ three and sometimes four antifuse connections, which

increase capacitance and resistance, resulting in longer net delays for macros connected to long tracks.

Typically, up to 6 percent of nets in a fully utilized device require long tracks.

Long tracks add approximately a 3 ns to a 6 ns delay, which is represented statistically in higher fanout

(FO=8) routing delays in the data sheet specifications section, shown in Table 34, page 43.

3.11.3 Timing Derating

MX devices are manufactured with a CMOS process. Therefore, device performance varies according to

temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating

voltage, minimum operating temperature and best-case processing. Maximum timing parameters reflect

minimum operating voltage, maximum operating temperature and worst-case processing.

3.11.4 Temperature and Voltage Derating Factors

The following tables and figures show temperature and voltage derating factors for 40MX and 42MX

FPGAs.

Table 28 • 42MX Temperature and Voltage Derating Factors (Normalized to T_J=

25°C, VCCA = 5.0 V)

Temperature

42MX Voltage –55°C –40°C 0°C 25°C 70°C 85°C 125°C

4.50

4.75

5.00

5.25

5.50

0.93

0.88

0.85

0.84

0.83

0.95

0.90

0.87

0.86

0.85

1.05 1.09 1.25 1.29 1.41

1.00 1.03 1.18 1.22 1.34

0.96 1.00 1.15 1.18 1.29

0.95 0.97 1.12 1.14 1.28

0.94 0.96 1.10 1.13 1.26

Figure 34 • 42MX Junction Temperature and Voltage Derating Curves

(Normalized to TJ = 25°C, VCCA = 5.0 V)

1.50

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

–55°C

–40°C

0°C

25°C

70°C

85°C

125°C

4.50

4.75

5.00

5.25

5.50

Voltage

(V)

DS2316 Datasheet Revision 16.0

40

40MX and 42MX FPGAs

Note: This derating factor applies to all routing and propagation delays

Table 29 • 40MX Temperature and Voltage Derating Factors(Normalized to TJ =

25°C, VCC = 5.0 V)

Temperature

40MX Voltage –55°C –40°C 0°C 25°C 70°C 85°C 125°C

4.50

4.75

5.00

5.25

5.50

0.89

0.84

0.82

0.80

0.79

0.93

0.88

0.85

0.82

1.02 1.09 1.25 1.31 1.45

0.97 1.03 1.18 1.24 1.37

0.94 1.00 1.15 1.20 1.33

0.91 0.97 1.12 1.16 1.29

0.90 0.96 1.10 1.15 1.28

Figure 35 • 40MX Junction Temperature and Voltage Derating Curves (Normalized to TJ = 25°C, VCC = 5.0 V)

1.50

1.40

1.30

–55°C

1.20

1.10

–40°C

0°C

1.00

25°C

0.90

70°C

0.80

85°C

0.70

125°C

0.60

4.50

4.75

5.00

5.25

5.50

Voltage

(V)

Note: This derating factor applies to all routing and propagation delays

Table 30 • 42MX Temperature and Voltage Derating Factors(Normalized to TJ =

25°C, VCCA = 3.3 V)

Temperature

42MX Voltage –55°C –40°C 0°C 25°C 70°C 85°C 125°C

3.00

3.30

3.60

0.97

0.84

0.81

1.00

0.87

0.84

1.10 1.15 1.32 1.36 1.45

0.96 1.00 1.15 1.18 1.26

0.92 0.96 1.10 1.13 1.21

DS2316 Datasheet Revision 16.0

41

40MX and 42MX FPGAs

Figure 36 • 42MX Junction Temperature and Voltage Derating Curves

(Normalized to TJ = 25°C, VCCA = 3.3 V)

1.60

1.50

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.60

0.50

0.40

55°C

40°C

0°C

25°C

70°C

85°C

125°C

3.00

3.30

3.60

Voltage (V)

Note: This derating factor applies to all routing and propagation delays

Table 31 • 40MX Temperature and Voltage Derating Factors (Normalized to TJ =

25°C, VCC = 3.3 V)

Temperature

40MX Voltage –55°C –40°C 0°C 25°C 70°C 85°C 125°C

3.00

3.30

3.60

1.08

0.86

0.83

1.12

0.89

0.85

1.21 1.26 1.50 1.64 2.00

0.96 1.00 1.19 1.30 1.59

0.92 0.96 1.14 1.25 1.53

Figure 37 • 40MX Junction Temperature and Voltage Derating Curves (Normalized to TJ = 25°C, VCC = 3.3 V)

2.20

2.00

55˚C

1.80

40˚C

1.60

1.40

1.20

1.00

0.80

0.60

0˚C

25˚C

70˚C

85˚C

125˚C

3.00

3.30

3.60

Voltage (V)

Note: This derating factor applies to all routing and propagation delays

DS2316 Datasheet Revision 16.0

42

40MX and 42MX FPGAs

3.11.5 PCI System Timing Specification

The following tables list the critical PCI timing parameters and the corresponding timing parameters for

the MX PCI-compliant devices.

3.11.6 PCI Models

Microsemi provides synthesizable VHDL(VHSIC Hardware Description Language) and Verilog-HDL

models for a PCI Target interface, a PCI Target and Target+DMA Master interface. Contact the Microsemi

sales representative for more details.

Table 32 • Clock Specification for 33 MHz PCI

PCI

A42MX24 A42MX36

Symbol Parameter

Min. Max. Min. Max. Min. Max. Units

t_CYC

t_HIGH

t_LOW

CLK Cycle Time 30

4.0

1.9

4.0

1.9

ns

CLK High Time 11

CLK Low Time 11

Table 33 • Timing Parameters for 33 MHz PCI

PCI

A42MX24

A42MX36

Symbol Parameter

Min.

2

Max. Min. Max. Min. Max. Units

t_VAL

CLK to Signal Valid—Bused Signals

11

12

2.0 9.0

2.0 4.0

8.3¹

2.0

9.0

4.0

ns

t_VAL(PTP)CLK to Signal Valid—Point-to-Point

2 ²

t_ON

t_OFF

t_SU

Float to Active

Active to Float

2

28

8.3¹ns

Input Set-Up Time to CLK—Bused Signals 7

1.5

0

ns

t_SU(PTP)Input Set-Up Time to CLK—Point-to-Point 10, 12²

1.5

t_HInput Hold to CLK

0

1. TOFF is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional 10 ns.

2. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than do

bussed signals. GNT# has a setup of 10; REW# has a setup of 12.

3.11.6.1 Timing Characteristics

The following tables list the timing characteristics.

Table 34 • A40MX02 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCC = 4.75 V, T_J= 70°C)

–3 Speed

–2 Speed

–1 Speed

Std Speed –F Speed

Parameter / Description

Logic Module Propagation Delays

t_PD1Single Module

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

1.2

2.7

1.2

1.4

3.1

1.4

1.6

3.5

1.6

1.9

4.1

1.9

2.7

5.7

2.7

ns

t_PD2Dual-Module Macros

t_CO

Sequential Clock-to-Q

t_GOLatch G-to-Q

t_RS

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays¹

DS2316 Datasheet Revision 16.0

43

40MX and 42MX FPGAs

Table 34 • A40MX02 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCC = 4.75 V, T_J= 70°C) (continued)

–3 Speed

–2 Speed

–1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_RD1FO = 1 Routing Delay

t_RD2FO = 2 Routing Delay

t_RD3FO = 3 Routing Delay

t_RD4FO = 4 Routing Delay

t_RD8FO = 8 Routing Delay

Logic Module Sequential Timing²

1.3

1.8

2.3

2.9

4.9

1.5

2.1

2.7

3.3

5.7

1.7

2.4

3.0

3.7

6.5

2.0

2.8

3.6

4.4

7.6

2.8

3.9

5.0

6.1

ns

10.6 ns

t_SUDFlip-Flop (Latch)

3.1

3.5

0.0

3.5

0.0

3.8

5.6

4.0

0.0

4.0

0.0

4.3

6.3

4.7

0.0

4.7

0.0

5.0

7.5

6.6

0.0

6.6

0.0

7.0

10.4

ns

Data Input Set-Up

3

t_HD

Flip-Flop (Latch)

Data Input Hold

0.0

t_SUENFlip-Flop (Latch)

Enable Set-Up

3.1

A

t_HENAFlip-Flop (Latch) Enable

Hold

0.0

t_WCLFlip-Flop (Latch)

3.3

Clock Active Pulse Width

KA

t_WASFlip-Flop (Latch)

Asynchronous Pulse Width

YN

t_A

Flip-Flop Clock Input Period 4.8

f_MAXFlip-Flop (Latch) Clock

Frequency (FO = 128)

181

168

154

134

80

MHz

Input Module Propagation Delays

t_INYHPad-to-Y HIGH

0.7

0.6

0.8

0.7

0.9

0.8

1.1

1.0

1.5

1.3

ns

t_INYLPad-to-Y LOW

Input Module Predicted Routing Delays¹

t_IRD1FO = 1 Routing Delay

t_IRD2FO = 2 Routing Delay

t_IRD3FO = 3 Routing Delay

t_IRD4FO = 4 Routing Delay

t_IRD8FO = 8 Routing Delay

Global Clock Network

2.1

2.6

3.1

3.6

5.7

2.4

3.0

3.6

4.2

6.6

2.2

3.4

4.1

4.8

7.5

3.2

4.0

4.8

5.6

8.8

4.5

5.6

6.7

7.8

ns

12.4 ns

t_CKHInput Low to HIGH FO = 16

FO = 128

4.6

5.3

6.0

7.0

9.8

ns

t_CKLInput High to LOW FO = 16

FO = 128

4.8

5.6

6.3

7.4

10.4 ns

10.4

t_PWHMinimum Pulse

Width HIGH

FO = 16 2.2

FO = 128 2.4

2.6

2.7

2.9

3.1

3.4

3.6

4.8

5.1

ns

t_PWLMinimum Pulse

Width LOW

FO = 16 2.2

FO = 128 2.4

2.6

2.7

2.9

3.01

3.4

3.6

4.8

5.1

ns

DS2316 Datasheet Revision 16.0

44

40MX and 42MX FPGAs

Table 34 • A40MX02 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCC = 4.75 V, T_J= 70°C) (continued)

–3 Speed

–2 Speed

–1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_CKSMaximum Skew

FO = 16

FO = 128

0.4

0.5

0.6

0.5

0.7

0.6

0.8

1.2

ns

W

t_P

Minimum Period FO = 16 4.7

FO = 128 4.8

5.4

5.6

6.1

6.3

7.2

7.5

10.0

10.4

ns

f_MAXMaximum

Frequency

FO = 16

FO = 128

188

181

175

168

160

154

139

134

83

80

MHz

TTL Output Module Timing⁴

t_DLHData-to-Pad HIGH

3.3

4.0

3.7

4.7

7.9

5.9

0.02

3.8

4.6

4.3

5.4

9.1

6.8

0.02

4.3

5.1

7.2

8.6

8.0

ns

t_DHLData-to-Pad LOW

5.2

6.1

t_ENZHEnable Pad Z to HIGH

t_ENZLEnable Pad Z to LOW

t_ENHZEnable Pad HIGH to Z

t_ENLZEnable Pad LOW to Z

4.9

5.8

6.1

7.2

10.1 ns

17.1 ns

12.6 ns

0.04 ns/pF

10.4

7.7

12.2

9.0

d_TLHDelta LOW to

HIGH

0.03

d_THLDelta HIGH to

LOW

0.03

0.04

0.06 ns/pF

CMOS Output Module Timing⁴

t_DLHData-to-Pad HIGH

3.9

3.4

4.9

7.9

5.9

0.03

4.5

3.9

5.6

9.1

6.8

0.04

5.1

6.05

5.2

8.5

7.3

ns

t_DHLData-to-Pad LOW

4.4

t_ENZHEnable Pad Z to HIGH

t_ENZLEnable Pad Z to LOW

t_ENHZEnable Pad HIGH to Z

t_ENLZEnable Pad LOW to Z

4.4

5.2

6.4

7.5

10.5 ns

17.0 ns

12.6 ns

0.07 ns/pF

10.4

7.7

12.2

9.0

d_TLHDelta LOW to

HIGH

0.04

0.05

d_THLDelta HIGH to

LOW

0.02

0.03

0.04 ns/pF

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for

estimating device performance. Post-route timing analysis or simulation is required to determine actual performance

2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check

the hold time for this macro.

4. Delays based on 35pF loading

Table 35 • A40MX02 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCC = 3.0 V, T_J= 70°C)

–3 Speed

–2 Speed

–1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Propagation Delays

t_PD1

Single Module

1.7

2.0

2.3

2.7

3.7 ns

DS2316 Datasheet Revision 16.0

45

40MX and 42MX FPGAs

Table 35 • A40MX02 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCC = 3.0 V, T_J= 70°C) (continued)

–3 Speed

–2 Speed

–1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_PD2

t_CO

t_GO

t_RS

Dual-Module Macros

Sequential Clock-to-Q

Latch G-to-Q

3.7

1.7

4.3

2.0

4.9

2.3

5.7

2.7

8.0 ns

3.7 ns

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays¹

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

2.0

2.7

3.4

4.2

7.1

2.2

3.1

3.9

4.8

8.2

2.5

3.5

4.4

5.4

9.2

3.0

4.1

5.2

6.3

10.9

4.2 ns

5.7 ns

7.3 ns

8.9 ns

15.2 ns

Logic Module Sequential Timing²

t_SUD

Flip-Flop (Latch)

Data Input Set-Up

4.3

0.0

4.3

0.0

4.6

4.9

0.0

4.9

0.0

5.3

7.8

5.6

0.0

5.6

0.0

6.0

8.9

6.6

0.0

6.6

0.0

7.0

10.4

9.2

0.0

9.2

0.0

9.8

14.6

ns

3

t_HD

Flip-Flop (Latch)

Data Input Hold

t_SUENAFlip-Flop (Latch) Enable

Set-Up

t_HENAFlip-Flop (Latch) Enable

Hold

t_WCLKAFlip-Flop (Latch)

Clock Active Pulse Width

t_WASYNFlip-Flop (Latch)

Asynchronous Pulse Width

t_A

Flip-Flop Clock Input Period 6.8

f_MAX

Flip-Flop (Latch) Clock

Frequency (FO = 128)

109

101

92

80

48

MHz

Input Module Propagation Delays

t_INYH

t_INYL

Pad-to-Y HIGH

1.0

0.9

1.1

1.0

1.3

1.1

1.5

1.3

2.1 ns

1.9 ns

Pad-to-Y LOW

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

2.9

3.6

4.4

5.1

8.0

3.4

4.2

5.0

5.9

9.26

3.8

4.8

5.7

6.7

10.5

4.5

5.6

6.7

7.8

12.6

6.3 ns

7.8 ns

9.4 ns

11.0 ns

17.3 ns

Global Clock Network

t_CKH

Input LOW to

HIGH

FO = 16

FO =

6.4

7.4

8.3

9.8

13.7 ns

13.7

128

DS2316 Datasheet Revision 16.0

46

40MX and 42MX FPGAs

Table 35 • A40MX02 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCC = 3.0 V, T_J= 70°C) (continued)

–3 Speed

–2 Speed

–1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_CKL

t_PWH

t_PWL

Input HIGH to

LOW

FO = 16

FO =

128

6.7

7.8

8.8

10.4

14.5 ns

14.5

Minimum Pulse

Width HIGH

FO = 16 3.1

FO =

128

3.6

3.8

4.1

4.3

4.8

5.1

6.7

7.1

ns

3.3

Minimum Pulse

Width LOW

FO = 16 3.1

FO =

128

3.6

3.8

4.1

4.3

4.8

5.1

6.7

7.1

3.3

t_CKSWMaximum Skew FO = 16

0.6

0.8

0.6

0.9

0.7

1.0

0.8

1.2

1.2 ns

1.6

FO =

128

t_P

Minimum Period FO = 16 6.5

7.5

7.8

8.5

8.9

10.1

10.4

14.1

14.6

ns

FO =

128

6.8

f_MAX

Maximum

Frequency

FO = 16

FO =

113

109

105

101

96

92

83

80

50

48

MHz

128

TTL Output Module Timing⁴

t_DLH

Data-to-Pad

HIGH

4.7

5.4

6.1

7.2

10.0 ns

t_DHL

Data-to-Pad LOW

5.6

6.4

7.3

8.6

12.0 ns

11.3 ns

14.1 ns

23.9 ns

17.7 ns

0.06 ns/pF

t_ENZHEnable Pad Z to HIGH

t_ENZLEnable Pad Z to LOW

t_ENHZEnable Pad HIGH to Z

t_ENLZEnable Pad LOW to Z

5.2

6.0

6.8

8.1

6.6

7.6

8.6

10.1

17.1

12.6

0.04

11.1

8.2

12.8

9.5

14.5

10.7

0.04

d_TLH

Delta LOW to

HIGH

0.03

d_THL

Delta HIGH to

LOW

0.04

0.05

0.06

0.08 ns/pF

DS2316 Datasheet Revision 16.0

47

40MX and 42MX FPGAs

Table 35 • A40MX02 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCC = 3.0 V, T_J= 70°C) (continued)

–3 Speed

–2 Speed

–1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

CMOS Output Module Timing⁴

t_DLH

Data-to-Pad

HIGH

5.5

6.4

7.2

8.5

11.9 ns

t_DHL

Data-to-Pad LOW

4.8

5.5

6.2

7.3

10.2 ns

14.7 ns

23.9 ns

17.7 ns

0.10 ns/pF

t_ENZHEnable Pad Z to HIGH

t_ENZLEnable Pad Z to LOW

t_ENHZEnable Pad HIGH to Z

t_ENLZEnable Pad LOW to Z

4.7

5.5

6.2

7.3

6.8

7.9

8.9

10.5

17.1

12.6

0.07

11.1

8.2

12.8

9.5

14.5

10.7

0.06

d_TLH

Delta LOW to

HIGH

0.05

d_THL

Delta HIGH to

LOW

0.03

0.04

0.06 ns/pF

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for

estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check

the hold time for this macro

4. Delays based on 35 pF loading

Table 36 • A40MX04 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCC = 4.75 V, T_J= 70°C)

–3 Speed

–2 Speed

–1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Propagation Delays

t_PD1

t_PD2

t_CO

t_GO

t_RS

Single Module

1.2

2.3

1.2

1.4

3.1

1.4

1.6

3.5

1.6

1.9

4.1

1.9

2.7

5.7

2.7

ns

Dual-Module Macros

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays¹

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

1.2

1.9

2.4

2.9

5.0

1.6

2.2

2.8

3.4

5.8

1.8

2.5

3.2

3.9

6.6

2.1

2.9

3.7

4.5

7.8

3.0

4.1

5.2

6.3

ns

10.9 ns

Logic Module Sequential Timing²

t_SUD

Flip-Flop (Latch)

Data Input Set-Up

3.1

0.0

3.5

0.0

4.0

0.0

4.7

0.0

6.6

0.0

ns

3

t_HD

Flip-Flop (Latch)

Data Input Hold

DS2316 Datasheet Revision 16.0

48

40MX and 42MX FPGAs

Table 36 • A40MX04 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCC = 4.75 V, T_J= 70°C) (continued)

–3 Speed

–2 Speed

–1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_SUENAFlip-Flop (Latch)

Enable Set-Up

3.1

0.0

3.3

3.5

0.0

3.8

5.6

4.0

0.0

4.3

6.3

4.7

0.0

5.0

7.5

6.6

0.0

7.0

10.4

ns

t_HENA

Flip-Flop (Latch)

Enable Hold

t_WCLKAFlip-Flop (Latch)

Clock Active Pulse Width

t_WASYNFlip-Flop (Latch)

Asynchronous Pulse Width

t_A

Flip-Flop Clock Input Period 4.8

ns

f_MAX

Flip-Flop (Latch)

Clock Frequency

(FO = 128)

181

167

154

134

80

MHz

Input Module Propagation Delays

t_INYH

t_INYL

Pad-to-Y HIGH

Pad-to-Y LOW

0.7

0.6

0.8

0.7

0.9

0.8

1.1

1.0

1.5

1.3

ns

Input Module Predicted Routing Delays¹

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

2.1

2.6

3.1

3.6

5.7

2.4

3.0

3.6

4.2

6.6

2.2

3.4

4.1

4.8

7.5

3.2

4.0

4.8

5.6

8.8

4.5

5.6

6.7

7.8

ns

12.4 ns

Global Clock Network

t_CKH

t_CKL

t_PWH

t_PWL

t_CKSW

t_P

Input Low to HIGH FO = 16

4.6

5.3

6.0

7.0

9.8

ns

FO = 128

Input High to LOW FO = 16

FO = 128

4.8

5.6

6.3

7.4

10.4 ns

10.4

Minimum Pulse

Width HIGH

FO = 16 2.2

FO = 128 2.4

2.6

2.7

2.9

3.1

3.4

3.6

4.8

5.1

ns

Minimum Pulse

Width LOW

FO = 16 2.2

FO = 128 2.4

2.6

2.7

2.9

3.01

3.4

3.6

4.8

5.1

ns

Maximum Skew

FO = 16

0.4

0.5

0.6

0.5

0.7

0.6

0.8

1.2

ns

FO = 128

Minimum Period

FO = 16 4.7

FO = 128 4.8

5.4

5.6

6.1

6.3

7.2

7.5

10.0

10.4

ns

f_MAX

Maximum

Frequency

FO = 16

FO = 128

188

181

175

168

160

154

139

134

83

80

MHz

TTL Output Module Timing⁴

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

3.3

4.0

3.7

3.8

4.6

4.3

5.2

4.9

5.1

6.1

5.8

7.2

8.6

8.0

ns

t_DHL

t_ENZH

Enable Pad Z to HIGH

DS2316 Datasheet Revision 16.0

49

40MX and 42MX FPGAs

Table 36 • A40MX04 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCC = 4.75 V, T_J= 70°C) (continued)

–3 Speed

–2 Speed

–1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

Enable Pad Z to LOW

4.7

7.9

5.4

9.1

6.8

0.02

6.1

7.2

10.1 ns

17.1 ns

12.6 ns

0.04 ns/pF

Enable Pad HIGH to Z

Enable Pad LOW to Z

10.4

7.7

12.2

9.0

5.9

Delta LOW to

HIGH

0.02

0.03

d_THL

Delta HIGH to

LOW

0.03

0.04

0.06 ns/pF

DS2316 Datasheet Revision 16.0

50

40MX and 42MX FPGAs

Table 36 • A40MX04 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCC = 4.75 V, T_J= 70°C) (continued)

–3 Speed

–2 Speed

–1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

CMOS Output Module Timing¹

t_DLH

Data-to-Pad HIGH

3.9

3.4

4.9

7.9

5.9

0.03

4.5

3.9

5.6

9.1

6.8

0.04

5.1

6.05

5.2

8.5

7.3

ns

t_DHL

Data-to-Pad LOW

4.4

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

4.4

5.2

6.4

7.5

10.5 ns

17.0 ns

12.6 ns

0.07 ns/pF

10.4

7.7

12.2

9.0

Delta LOW to

HIGH

0.04

0.05

d_THL

Delta HIGH to

LOW

0.02

0.03

0.04 ns/pF

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for

estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the

hold time for this macro.

4. Delays based on 35 pF loading

Table 37 • A40MX04 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCC = 3.0 V, T_J= 70°C)

–3 Speed –2 Speed –1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Propagation Delays

t_PD1

t_PD2

t_CO

t_GO

t_RS

Single Module

1.7

3.7

1.7

2.0

4.3

2.0

2.3

4.9

2.3

2.7

5.7

2.7

3.7

8.0

3.7

ns

Dual-Module Macros

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays¹

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

1.9

2.7

3.4

4.1

7.1

2.2

3.1

3.9

4.8

8.1

2.5

3.5

4.4

5.4

9.2

3.0

4.1

5.2

6.3

10.9

4.2

5.7

7.3

8.9

ns

15.2 ns

Logic Module Sequential Timing²

t_SUD

Flip-Flop (Latch)

Data Input Set-Up

4.3

5.0

5.6

6.6

9.2

ns

3

t_HD

Flip-Flop (Latch) Data Input Hold 0.0

Flip-Flop (Latch) Enable Set-Up 4.3

0.0

5.0

0.0

5.6

0.0

6.6

0.0

9.2

ns

t_SUENA

DS2316 Datasheet Revision 16.0

51

40MX and 42MX FPGAs

Table 37 • A40MX04 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCC = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_HENA

Flip-Flop (Latch) Enable Hold

0.0

4.6

0.0

5.3

0.0

5.6

0.0

7.0

0.0

9.8

ns

t_WCLKA

Flip-Flop (Latch)

Clock Active Pulse Width

t_WASYNFlip-Flop (Latch)

Asynchronous Pulse Width

4.6

6.8

5.3

7.8

5.6

8.9

7.0

9.8

ns

t_A

Flip-Flop Clock Input Period

10.4

14.6

ns

f_MAX

Flip-Flop (Latch) Clock

Frequency

109

101

92

80

48

MHz

(FO = 128)

Input Module Propagation Delays

t_INYH

t_INYL

Pad-to-Y HIGH

Pad-to-Y LOW

1.0

0.9

1.1

1.0

1.3

1.1

1.5

1.3

2.1

1.9

ns

DS2316 Datasheet Revision 16.0

52

40MX and 42MX FPGAs

Table 37 • A40MX04 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCC = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Input Module Predicted Routing Delays1

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

2.9

3.6

4.4

5.1

8.0

3.3

4.2

5.0

5.9

9.3

3.8

4.8

5.7

6.7

10.5

4.5

5.6

6.7

7.8

12.4

6.3

7.8

9.4

ns

11.0 ns

17.2 ns

FO = 8 Routing

Delay

Global Clock Network

t_CKH

t_CKL

t_PWH

t_PWL

t_CKSW

t_P

Input LOW to HIGH FO = 16

6.4

7.4

8.4

9.9

13.8 ns

13.8

FO = 128

Input HIGH to LOW FO = 16

FO = 128

6.8

7.8

8.9

10.4

14.6 ns

14.6

Minimum Pulse

Width HIGH

FO = 16

FO = 128 3.3

3.1

3.6

3.8

4.1

4.3

4.8

5.1

6.7

7.1

ns

Minimum Pulse

Width LOW

FO = 16 3.1

FO = 128 3.3

3.6

3.8

4.1

4.3

4.8

5.1

6.7

7.1

ns

Maximum Skew

FO = 16

0.6

0.8

0.6

0.9

0.7

1.0

0.8

1.2

1.6

ns

FO = 128

Minimum Period

FO = 16

6.5

7.5

7.8

8.5

8.9

10.1

10.4

14.1

14.6

ns

FO = 128 6.8

f_MAX

Maximum

Frequency

FO = 16

FO = 128

113

109

105

101

96

92

83

80

50

48

MHz

TTL Output Module Timing⁴

t_DLH

Data-to-Pad HIGH

4.7

5.4

6.1

7.2

10.0 ns

12.0 ns

11.3 ns

14.1 ns

23.9 ns

17.7 ns

0.06 ns/pF

0.08 ns/pF

t_DHL

Data-to-Pad LOW

5.6

6.4

7.3

8.6

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

5.2

6.0

6.9

8.1

6.6

7.6

8.6

10.1

17.1

12.6

0.04

0.06

11.1

8.2

12.8

9.5

14.5

10.7

0.04

0.05

0.03

0.04

0.03

0.04

DS2316 Datasheet Revision 16.0

53

40MX and 42MX FPGAs

Table 37 • A40MX04 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCC = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

CMOS Output Module Timing⁴

t_DLH

Data-to-Pad HIGH

5.5

4.8

6.4

5.5

7.2

6.2

8.5

7.3

11.9

10.2

14.7

23.9

17.7

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

d_TLH

d_THL

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

Delta LOW to HIGH

Delta HIGH to LOW

4.7

5.5

6.2

7.3

6.8

7.9

8.9

10.5

17.1

12.6

0.07

0.04

11.1

8.2

12.8

9.5

14.5

10.7

0.06

0.04

0.05

0.03

0.05

0.03

0.10 ns/pF

0.06 ns/pF

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold

time for this macro.

4. Delays based on 35 pF loading.

Table 38 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C)

–3 Speed

–2 Speed –1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Propagation Delays¹

t_PD1

t_CO

t_GO

t_RS

Single Module

1.2

1.3

1.2

1.3

1.4

1.6

1.5

1.6

1.8

1.9

1.8

2.1

2.5 ns

2.7 ns

2.6 ns

2.9 ns

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

0.7

0.9

1.2

1.4

2.3

0.8

1.0

1.3

1.5

2.6

0.9

1.2

1.5

1.7

2.9

1.0

1.4

1.7

2.0

3.4

1.4 ns

1.9 ns

2.4 ns

2.9 ns

4.8 ns

Logic Module Sequential Timing^{3, 4}

t_SUD

Flip-Flop (Latch)

Data Input Set-Up

0.3

0.4

0.5

0.7

ns

t_HD

Flip-Flop (Latch) Data Input Hold 0.0

0.0

0.5

0.0

3.8

0.0

0.5

0.0

4.3

0.0

0.6

0.0

5.0

0.0

0.8

0.0

7.0

ns

t_SUENAFlip-Flop (Latch) Enable Set-Up 0.4

t_HENA

Flip-Flop (Latch) Enable Hold

0.0

3.4

t_WCLKAFlip-Flop (Latch) Clock Active

Pulse Width

DS2316 Datasheet Revision 16.0

54

40MX and 42MX FPGAs

Table 38 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) (continued)

–3 Speed

–2 Speed –1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_WASYNFlip-Flop (Latch) Asynchronous

Pulse Width

4.5

4.9

5.6

6.6

9.2

ns

t_A

Flip-Flop Clock Input Period

Input Buffer Latch Hold

Input Buffer Latch Set-Up

Output Buffer Latch Hold

3.5

0.0

0.3

0.0

0.3

3.8

0.0

0.3

0.0

0.3

4.3

0.0

0.4

0.0

0.4

5.1

0.0

0.4

0.0

0.4

7.1

0.0

0.6

0.0

0.6

ns

t_INH

t_INSU

t_OUTH

ns

t_OUTSUOutput Buffer Latch Set-Up

f_MAXFlip-Flop (Latch) Clock Frequency

ns

268

244

224

195

117 MHz

DS2316 Datasheet Revision 16.0

55

40MX and 42MX FPGAs

Table 38 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) (continued)

–3 Speed

–2 Speed –1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

t_INGH

t_INGL

Pad-to-Y HIGH

Pad-to-Y LOW

G to Y HIGH

G to Y LOW

1.0

0.8

1.3

1.2

0.9

1.4

1.3

1.0

1.6

1.2

1.9

2.2 ns

1.7 ns

2.7 ns

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

2.0

2.3

2.5

2.8

3.7

2.2

2.5

2.8

3.1

4.1

2.5

2.9

3.2

3.5

4.7

3.0

3.4

3.7

4.1

5.5

4.2 ns

4.7 ns

5.2 ns

5.7 ns

7.7 ns

Global Clock Network

t_CKHInput LOW to HIGH FO = 32

2.4

2.7

3.0

3.4

3.6

4.0

5.0 ns

5.5 ns

FO = 256

t_CKL

Input HIGH to LOW FO = 32

FO = 256

3.5

3.9

4.3

4.4

4.9

5.2

5.7

7.3 ns

8.0 ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse

Width HIGH

FO = 32

FO = 256 1.3

1.2

1.4

1.5

1.7

1.8

2.0

2.5

2.7

ns

Minimum Pulse

Width LOW

FO = 32 1.2

FO = 256 1.3

1.4

1.5

1.7

1.8

2.0

2.5

2.7

ns

Maximum Skew

FO = 32

FO = 256

0.3

0.4

0.5

0.6 ns

Input Latch

External Set-Up

FO = 32

FO = 256 0.0

0.0

ns

Input Latch

External Hold

FO = 32 2.3

FO = 256 2.2

FO = 32 3.4

FO = 256 3.7

2.6

2.4

3.0

3.3

3.5

3.9

4.9

5.5

ns

Minimum Period

3.7

4.1

4.0

4.5

4.7

5.2

7.8

8.6

ns

f_MAX

Maximum Frequency FO = 32

FO = 256

296

268

269

244

247

224

215

195

129 MHz

117 MHz

DS2316 Datasheet Revision 16.0

56

40MX and 42MX FPGAs

Table 38 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) (continued)

–3 Speed

–2 Speed –1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

TTL Output Module Timing⁵

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

2.5

2.9

2.6

2.9

4.9

5.3

2.6

2.7

3.2

2.9

3.2

5.4

5.9

2.9

3.1

3.6

3.3

3.7

6.2

6.7

3.3

3.6

4.3

3.9

4.3

7.3

7.9

3.8

5.1 ns

6.0 ns

5.5 ns

6.1 ns

10.2 ns

11.1 ns

5.3 ns

ns

G-to-Pad LOW

I/O Latch Set-Up

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

t_LH

I/O Latch Hold

ns

t_LCO

I/O Latch Clock-to-Out

(Pad-to-Pad), 64 Clock Loading

5.2

7.4

5.8

8.2

6.6

9.3

7.7

10.8 ns

t_ACO

Array Clock-to-Out

10.9

15.3 ns

(Pad-to-Pad), 64 Clock Loading

d_TLH

d_THL

Capacity Loading, LOW to HIGH

Capacity Loading, HIGH to LOW

0.03

0.04

0.03

0.04

0.03

0.04

0.05

0.06 ns/pF

0.07 ns/pF

DS2316 Datasheet Revision 16.0

57

40MX and 42MX FPGAs

Table 38 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) (continued)

–3 Speed

–2 Speed –1 Speed

Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

CMOS Output Module Timing⁵

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

2.4

2.9

2.7

2.9

4.9

5.3

4.2

2.7

3.2

2.9

3.2

5.4

5.9

4.6

3.1

3.6

3.3

3.7

6.2

6.7

5.2

3.6

4.3

3.9

4.3

7.3

7.9

6.1

5.1 ns

6.0 ns

5.5 ns

6.1 ns

10.2 ns

11.1 ns

8.6 ns

ns

G-to-Pad LOW

I/O Latch Set-Up

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

t_LH

I/O Latch Hold

ns

t_LCO

I/O Latch Clock-to-Out

(Pad-to-Pad), 64 Clock Loading

5.2

7.4

5.8

8.2

6.6

9.3

7.7

10.8 ns

t_ACO

Array Clock-to-Out (

10.9

15.3 ns

Pad-to-Pad), 64 Clock Loading

d_TLH

d_THL

Capacity Loading, LOW to HIGH

Capacity Loading, HIGH to LOW

0.03

0.04

0.03

0.04

0.03

0.04

0.05

0.06 ns/pF

0.07 ns/pF

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External

setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD

signal to the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading

Table 39 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Propagation Delays¹

t_PD1

t_CO

t_GO

t_RS

Single Module

1.6

1.8

1.7

2.0

1.8

2.0

1.9

2.2

2.1

2.3

2.1

2.5

2.7

2.5

2.9

3.5

3.8

3.5

4.1

ns

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

1.0

1.3

1.6

1.1

1.4

1.8

1.2

1.6

2.0

1.4

1.9

2.4

2.0

2.7

3.3

ns

DS2316 Datasheet Revision 16.0

58

40MX and 42MX FPGAs

Table 39 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

t_RD4FO = 4 Routing Delay

t_RD8FO = 8 Routing Delay

Logic Module Sequential Timing ^{3, 4}

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

1.9

3.2

2.1

3.6

2.4

4.1

2.9

4.8

4.0

6.7

ns

t_SUD

Flip-Flop (Latch) Data Input Set-Up 0.5

Flip-Flop (Latch) Data Input Hold 0.0

0.5

0.0

0.6

0.0

5.3

0.6

0.0

0.7

0.0

6.0

0.7

0.0

0.8

0.0

7.0

0.9

0.0

1.2

0.0

9.8

ns

t_HD

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

0.6

0.0

4.7

Flip-Flop (Latch)

Clock Active Pulse Width

t_WASYN

Flip-Flop (Latch)

6.2

6.9

7.8

9.2

12.9

ns

Asynchronous Pulse Width

t_A

Flip-Flop Clock Input Period

Input Buffer Latch Hold

5.0

0.0

0.3

0.0

0.3

5.6

0.0

0.3

0.0

0.3

6.2

0.0

0.3

0.0

0.3

7.1

0.0

0.4

0.0

0.4

9.9

0.0

0.6

0.0

0.6

ns

t_INH

ns

t_INSU

t_OUTH

t_OUTSU

f_MAX

Input Buffer Latch Set-Up

Output Buffer Latch Hold

Output Buffer Latch Set-Up

Flip-Flop (Latch) Clock Frequency

ns

161

146

135

117

70

MHz

DS2316 Datasheet Revision 16.0

59

40MX and 42MX FPGAs

Table 39 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Input Module Propagation Delays

t_INYH

t_INYL

t_INGH

t_INGL

Pad-to-Y HIGH

Pad-to-Y LOW

G to Y HIGH

G to Y LOW

1.5

1.2

1.8

1.6

1.3

2.0

1.8

1.4

2.3

2.17

1.7

3.0

2.4

3.7

ns

2.7

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

2.8

3.2

3.5

3.9

5.2

3.2

3.5

3.9

4.3

5.8

3.6

4.0

4.4

4.9

6.6

4.2

4.7

5.2

5.7

7.7

5.9

6.6

7.3

8.0

ns

10.8 ns

Global Clock Network

t_CKHInput LOW to HIGH

FO = 32

FO = 256

4.1

4.5

5.0

5.1

5.6

6.0

6.7

8.4

9.3

ns

t_CKL

Input HIGH to LOW

FO = 32

FO = 256

5.0

5.4

5.5

6.0

6.2

6.8

7.3

8.0

10.2

11.2

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse Width FO = 32

HIGH FO = 256

1.7

1.9

2.1

2.3

2.5

2.7

3.5

3.8

ns

Minimum Pulse Width FO = 32

1.7

1.9

2.1

2.3

2.5

2.7

3.5

3.8

ns

LOW

FO = 256

Maximum Skew

FO = 32

0.4

0.5

0.6

0.9

ns

FO = 256

Input Latch External

Set-Up

FO = 32

FO = 256

0.0

ns

Input Latch External

Hold

FO = 32

FO = 256

3.3

3.7

4.1

4.2

4.6

4.9

5.5

6.9

7.6

ns

Minimum Period

FO = 32

5.6

6.1

6.2

6.8

6.7

7.4

7.8

8.5

12.9

14.2

ns

FO = 256

f_MAX

Maximum Frequency FO = 32

FO = 256

177

161

146

148

135

129

117

77

70

MHz

DS2316 Datasheet Revision 16.0

60

40MX and 42MX FPGAs

Table 39 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

TTL Output Module Timing⁵

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.4

4.0

3.7

4.1

6.9

7.5

5.8

3.8

4.5

4.1

4.5

7.6

8.3

6.5

4.3

5.1

4.6

5.1

8.6

9.4

7.3

5.1

6.1

5.5

6.1

10.2

11.1

8.6

7.1

8.3

7.6

8.5

ns

14.2 ns

15.5 ns

12.0 ns

ns

G-to-Pad LOW

I/O Latch Set-Up

0.7

0.0

0.8

0.0

0.9

0.0

1.0

0.0

1.4

0.0

I/O Latch Hold

ns

t_LCO

I/O Latch Clock-to-Out

(Pad-to-Pad), 64 Clock Loading

8.7

9.7

10.9

15.4

12.9

18.1

18.0 ns

t_ACO

Array Clock-to-Out

12.2

13.5

25.3 ns

(Pad-to-Pad),64 Clock Loading

d_TLH

d_THL

Capacity Loading, LOW to HIGH

Capacity Loading, HIGH to LOW

0.00

0.09

0.00

0.10

0.00

0.10

0.01 ns/pF

0.10 ns/pF

DS2316 Datasheet Revision 16.0

61

40MX and 42MX FPGAs

Table 39 • A42MX09 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

CMOS Output Module Timing⁵

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.4

4.1

3.7

4.1

6.9

7.5

5.8

3.8

4.5

4.1

4.5

7.6

8.3

6.5

5.5

4.2

4.6

5.1

8.6

9.4

7.3

6.4

5.0

9.0

7.0

ns

5.5

7.6

6.1

8.5

10.2

11.1

8.6

14.2

15.5

12.0

G-to-Pad LOW

8.6

I/O Latch Set-Up

0.7

0.0

0.8

0.0

0.9

0.0

1.0

0.0

1.4

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out

(Pad-to-Pad), 64 Clock Loading

8.7

9.7

10.9

15.4

12.9

18.1

18.0

25.3

t_ACO

Array Clock-to-Out

(Pad-to-Pad),

12.2

13.5

ns

64 Clock Loading

d_TLH

d_THL

Capacity Loading, LOW to HIGH

Capacity Loading, HIGH to LOW

0.04

0.05

0.04

0.05

0.06

0.07

0.08 ns/pF

0.10 ns/pF

1. For dual-module macros, use t

+ t

, t + t

+ t

, or t

+ t

, whichever is appropriate.

PD1

RD1

PDn CO

RD1

PDn

PD1

RD1

SUD

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for

estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules

can be obtained from the Timer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External

setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external

PAD signal to the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

Table 40 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C)

–3 Speed –2 Speed

–1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Propagation Delays¹

t_PD1

t_CO

t_GO

t_RS

Single Module

1.4

1.6

1.5

1.6

1.5

1.7

1.8

1.7

2.0

2.1

2.0

2.3

2.8

3.0

2.8

3.3

ns

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

FO = 1 Routing Delay

FO = 2 Routing Delay

0.8

1.0

0.9

1.2

1.0

1.3

1.2

1.5

1.6

2.1

ns

DS2316 Datasheet Revision 16.0

62

40MX and 42MX FPGAs

Table 40 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) (continued)

–3 Speed –2 Speed

–1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_RD3

t_RD4

t_RD8

FO = 3 Routing Delay

1.3

1.6

2.6

1.4

1.7

2.9

1.6

2.0

3.2

1.9

2.3

3.8

2.7

3.2

5.3

ns

FO = 4 Routing Delay

FO = 8 Routing Delay

Logic Module Sequential Timing^3,4

t_SUD

Flip-Flop (Latch)

0.3

0.4

0.5

0.7

ns

Data Input Set-Up

t_HD

t_SUENAFlip-Flop (Latch) Enable Set-Up

t_HENAFlip-Flop (Latch) Enable Hold

t_WCLKAFlip-Flop (Latch)

Clock Active Pulse Width

t_WASYNFlip-Flop (Latch)

Asynchronous Pulse Width

Flip-Flop (Latch) Data Input Hold 0.0

0.0

0.8

0.0

3.8

0.0

0.9

0.0

4.3

0.0

1.0

0.0

5.0

0.0

1.4

0.0

7.1

ns

0.7

0.0

3.4

4.5

5.0

5.6

6.6

9.2

ns

t_A

Flip-Flop Clock Input Period

Input Buffer Latch Hold

Input Buffer Latch Set-Up

Output Buffer Latch Hold

6.8

0.0

0.5

0.0

0.5

7.6

0.0

0.5

0.0

0.5

8.6

0.0

0.6

0.0

0.6

10.1

0.0

0.7

0.0

0.7

14.1

0.0

1.0

0.0

1.0

ns

t_INH

t_INSU

t_OUTH

ns

t_OUTSUOutput Buffer Latch Set-Up

ns

f_MAX

Flip-Flop (Latch) Clock

Frequency

215

195

179

156

94

MHz

Input Module Propagation Delays

t_INYH

t_INYL

t_INGH

t_INGL

Pad-to-Y HIGH

Pad-to-Y LOW

G to Y HIGH

G to Y LOW

1.1

0.8

1.4

1.2

0.9

1.6

1.3

1.0

1.8

1.6

1.2

2.1

2.2

1.7

2.9

ns

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

1.8

2.1

2.3

2.6

3.6

2.0

2.3

2.6

3.0

4.0

2.3

2.6

3.0

3.3

4.6

2.7

3.1

3.5

3.9

5.4

4.0

4.3

4.9

5.4

7.5

ns

Global Clock Network

t_CKH

t_CKL

t_PWH

Input LOW to HIGH FO = 32

2.6

2.9

3.2

3.3

3.6

3.9

4.3

5.4

6.0

ns

FO = 384

Input HIGH to LOW FO = 32

FO = 384

3.8

4.5

4.2

5.0

4.8

5.6

6.6

7.8

9.2

ns

Minimum Pulse

Width HIGH

FO = 32

FO = 384

3.2

3.7

3.5

4.1

4.0

4.6

4.7

5.4

6.6

7.6

ns

DS2316 Datasheet Revision 16.0

63

40MX and 42MX FPGAs

Table 40 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) (continued)

–3 Speed –2 Speed

–1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_PWL

Minimum Pulse

Width LOW

FO = 32

FO = 384

3.2

3.7

3.5

4.1

4.0

4.6

4.7

5.4

6.6

7.6

ns

t_CKSW

Maximum Skew

FO = 32

FO = 384

0.3

0.4

0.5

0.7

ns

t_SUEXTInput Latch External FO = 32

Set-Up FO = 384

0.0

ns

t_HEXT

Input Latch External FO = 32

2.8

3.2

3.1

3.5

5.5

4.0

4.1

4.7

5.7

6.6

ns

Hold

FO = 384

t_P

Minimum Period

FO = 32

FO = 384

4.2

4.6

4.67

5.1

5.6

5.8

6.4

9.7

10.7

ns

f_MAX

Maximum Frequency FO = 32

FO = 384

237

215

195

198

179

172

156

103 MHz

94 MHz

DS2316 Datasheet Revision 16.0

64

40MX and 42MX FPGAs

Table 40 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) (continued)

–3 Speed –2 Speed

–1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

TTL Output Module Timing⁴

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

2.5

3.0

2.7

3.0

5.4

5.0

2.9

5.7

2.8

3.3

3.0

3.3

6.0

5.6

3.2

6.3

3.2

3.7

3.4

3.8

6.8

6.3

3.6

7.1

3.7

4.4

4.0

4.4

8.0

7.4

4.3

8.4

5.2 ns

6.1 ns

5.6 ns

6.2 ns

11.2 ns

10.4 ns

6.0 ns

11.9 ns

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

G-to-Pad LOW

t_LCO

I/O Latch Clock-to-Out

(Pad-to-Pad), 64 Clock Loading

t_ACO

d_TLH

d_THL

Array Clock-to-Out

(Pad-to-Pad), 64 Clock Loading

8.0

8.9

10.1

0.03

0.04

11.9

0.04

0.05

16.7 ns

Capacitive Loading, LOW to

HIGH

0.03

0.04

0.03

0.04

0.06 ns/pF

0.07 ns/pF

Capacitive Loading, HIGH to

LOW

DS2316 Datasheet Revision 16.0

65

40MX and 42MX FPGAs

Table 40 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) (continued)

–3 Speed –2 Speed

–1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

CMOS Output Module Timing⁵

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.2

2.5

2.7

3.0

5.4

5.0

5.1

5.7

3.6

2.7

3.0

3.3

6.0

5.6

6.3

4.0

3.1

3.4

3.8

6.8

6.3

6.4

7.1

4.7

3.6

4.0

4.4

8.0

7.4

7.5

8.4

6.6 ns

5.1 ns

5.6 ns

6.2 ns

11.2 ns

10.4 ns

10.5 ns

11.9 ns

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

G-to-Pad LOW

t_LCO

I/O Latch Clock-to-Out

(Pad-to-Pad), 64 Clock Loading

t_ACO

d_TLH

Array Clock-to-Out

(Pad-to-Pad), 64 Clock Loading

8.0

8.9

10.1

0.03

11.9

0.04

16.7 ns

Capacitive Loading, LOW to

HIGH

0.03

0.06 ns/pF

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, point and position whichever is

appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules

can be obtained from the Timer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External

setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD

signal to the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading

Table 41 • A42MX16 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Propagation Delays¹

t_PD1

t_CO

t_GO

t_RS

Single Module

1.9

2.0

1.9

2.2

2.1

2.2

2.1

2.4

2.5

2.4

2.8

3.0

2.8

3.3

4.0

4.2

4.0

4.6

ns

Sequential Clock-to-Q

Latch G-to-Q

Flip-Flop (Latch) Reset-to-Q

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD8

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

1.1

1.5

1.8

2.2

3.6

1.2

1.6

2.0

2.4

4.0

1.4

1.8

2.3

2.7

4.5

1.6

2.1

2.7

3.2

5.3

2.3

3.0

3.8

4.5

7.5

ns

DS2316 Datasheet Revision 16.0

66

40MX and 42MX FPGAs

Table 41 • A42MX16 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Sequential Timing^{3, 4}

t_SUD

Flip-Flop (Latch)

Data Input Set-Up

0.5

0.6

0.7

0.9

ns

t_HD

Flip-Flop (Latch) Data Input Hold 0.0

Flip-Flop (Latch) Enable Set-Up 1.0

0.0

1.1

0.0

5.3

0.0

1.2

0.0

6.0

0.0

1.4

0.0

7.1

0.0

2.0

0.0

9.9

ns

t_SUENA

t_HENA

t_WCLKA

Flip-Flop (Latch) Enable Hold

0.0

4.8

Flip-Flop (Latch)

Clock Active Pulse Width

t_WASYN

Flip-Flop (Latch)

6.2

6.9

7.9

9.2

12.9

ns

Asynchronous Pulse Width

t_A

Flip-Flop Clock Input Period

Input Buffer Latch Hold

9.5

0.0

0.7

0.0

0.7

10.6

0.0

0.8

0.0

0.8

12.0

0.0

14.1

0.0

19.8

0.0

1.4

0.0

1.4

ns

t_INH

ns

t_INSU

t_OUTH

t_OUTSU

f_MAX

Input Buffer Latch Set-Up

Output Buffer Latch Hold

Output Buffer Latch Set-Up

0.9

1.01

0.0

ns

0.0

0.89

1.01

ns

Flip-Flop (Latch) Clock

Frequency

129

117

108

94

56 MHz

Input Module Propagation Delays

t_INYH

t_INYL

t_INGH

t_INGL

Pad-to-Y HIGH

Pad-to-Y LOW

G to Y HIGH

G to Y LOW

1.5

1.1

2.0

1.6

1.3

2.2

1.9

1.4

2.5

2.2

1.7

2.9

3.1

2.4

4.1

ns

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO = 1 Routing

Delay

2.6

2.9

3.3

3.6

5.1

2.9

3.2

3.6

4.0

5.6

3.2

3.7

4.1

4.6

6.4

3.8

4.3

4.9

5.4

7.5

5.3

6.1

ns

FO = 2 Routing

Delay

FO = 3 Routing

Delay

6.8

FO = 4 Routing

Delay

7.6

FO = 8 Routing

Delay

10.5

Global Clock Network

t_CKH

t_CKL

t_PWH

Input LOW to HIGH FO = 32

4.4

4.8

5.3

5.5

6.0

6.5

7.1

9.0

9.9

ns

FO = 384

Input HIGH to LOW FO = 32

FO = 384

5.3

6.2

5.9

6.9

6.7

7.9

7.8

9.2

11.0

12.9

ns

Minimum Pulse

Width HIGH

FO = 32

FO = 384

5.7

6.6

6.3

7.4

7.1

8.3

8.4

9.8

11.8

13.7

ns

DS2316 Datasheet Revision 16.0

67

40MX and 42MX FPGAs

Table 41 • A42MX16 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse

Width LOW

FO = 32

FO = 384

5.3

6.2

5.9

6.9

6.7

7.9

7.8

9.2

11.0

12.9

ns

Maximum Skew

FO = 32

FO = 384

0.5

2.2

0.5

2.4

0.6

2.7

0.7

3.2

1.0

4.5

ns

Input Latch External FO = 32

Set-Up FO = 384

0.0

ns

Input Latch External FO = 32

Hold

3.9

4.5

4.3

4.9

5.6

5.7

6.6

8.0

9.2

ns

FO = 384

Minimum Period

FO = 32

FO = 384

7.0

7.7

7.8

8.6

8.4

9.3

9.7

10.7

16.2

17.8

ns

f_MAX

Maximum

Frequency

FO = 32

FO = 384

142

129

117

119

108

103

94

62 MHz

56 MHz

TTL Output Module Timing⁵

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

3.5

4.1

3.8

4.2

7.6

7.0

4.8

8.0

3.9

4.6

4.2

4.6

8.4

7.8

5.3

8.9

4.4

5.2

4.8

5.3

9.5

8.8

6.0

10.1

5.2

6.1

7.3

8.6

ns

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

5.6

7.8

6.2

8.7

11.2

10.4

7.2

15.7

14.5

10.0

16.7

t_GHL

G-to-Pad LOW

7.2

t_LCO

I/O Latch Clock-to-Out

11.9

(Pad-to-Pad), 64 Clock Loading

t_ACO

d_TLH

d_THL

Array Clock-to-Out

(Pad-to-Pad), 64 Clock Loading

11.3

0.04

0.05

12.5

0.04

0.05

14.2

0.05

0.06

16.7

0.06

0.07

23.3

ns

Capacitive Loading, LOW to

HIGH

0.08 ns/pF

0.10 ns/pF

Capacitive Loading, HIGH to

LOW

CMOS Output Module Timing⁵

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

4.5

3.4

3.8

4.2

7.6

7.0

7.1

8.0

5.0

3.8

4.2

4.6

8.4

7.8

7.9

8.9

5.6

4.3

4.8

5.3

9.5

8.8

8.9

10.1

6.6

9.3

7.1

7.8

8.7

ns

t_DHL

5.1

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

5.6

6.2

11.2

10.4

10.5

11.9

15.7 ns

14.5 ns

14.7 ns

16.7 ns

t_GHL

G-to-Pad LOW

t_LCO

I/O Latch Clock-to-Out

(Pad-to-Pad), 64 Clock Loading

DS2316 Datasheet Revision 16.0

68

40MX and 42MX FPGAs

Table 41 • A42MX16 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_ACO

d_TLH

d_THL

Array Clock-to-Out

(Pad-to-Pad),64 Clock Loading

11.3

0.04

0.05

12.5

0.04

0.05

14.2

0.05

0.06

16.7

0.06

0.07

23.3 ns

Capacitive Loading, LOW to

HIGH

0.08 ns/pF

0.10 ns/pF

Capacitive Loading, HIGH to

LOW

1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing ansalysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer utility.

4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External

setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD

signal to the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

Table 42 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Combinatorial Functions¹

t_PD

Internal Array Module Delay

Internal Decode Module Delay

1.2

1.4

1.3

1.6

1.5

1.8

2.1

2.5

3.0

ns

t_PDD

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

0.8

1.0

1.3

1.5

2.4

0.9

1.2

1.4

1.7

2.7

1.0

1.3

1.6

1.9

3.0

1.2

1.5

1.9

2.2

3.6

1.7

2.1

2.6

3.1

5.0

ns

Logic Module Sequential Timing^{3, 4}

t_CO

Flip-Flop Clock-to-Output

1.3

1.2

1.4

1.3

1.6

1.5

1.9

1.8

2.7

2.5

ns

t_GO

Latch Gate-to-Output

t_SUD

t_HD

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset-to-Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

0.3

0.0

0.4

0.0

0.4

0.0

0.5

0.0

0.7

0.0

t_RO

1.4

1.6

1.8

2.1

2.9

t_SUENA

t_HENA

t_WCLKA

0.4

0.0

3.3

0.5

0.0

3.7

0.5

0.0

4.2

0.6

0.0

4.9

0.8

0.0

6.9

Flip-Flop (Latch)

Clock Active Pulse Width

t_WASYN

Flip-Flop (Latch)

4.4

4.8

5.3

6.5

9.0

Asynchronous Pulse Width

ns

DS2316 Datasheet Revision 16.0

69

40MX and 42MX FPGAs

Table 42 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Input Module Propagation Delays

t_INPY

t_INGO

t_INH

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.0

1.3

1.1

1.4

1.3

1.6

1.5

1.9

2.1

2.6

ns

0.0

0.5

4.7

0.0

0.5

5.2

0.0

0.6

5.9

0.0

0.7

6.9

0.0

1.0

9.7

t_INSU

t_ILA

Input Latch Set-Up

Latch Active Pulse Width

DS2316 Datasheet Revision 16.0

70

40MX and 42MX FPGAs

Table 42 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

1.8

2.1

2.3

2.5

3.4

2.0

2.3

2.5

2.8

3.8

2.3

2.6

2.9

3.2

4.3

2.7

3.1

3.4

3.7

5.1

3.8

4.3

4.8

5.2

7.1

ns

Global Clock Network

t_CKHInput LOW to HIGH

FO = 32

FO = 486

2.6

2.9

3.2

3.3

3.6

3.9

4.3

5.4

5.9

ns

t_CKL

Input HIGH to LOW

FO = 32

FO = 486

3.7

4.3

4.1

4.7

4.6

5.4

6.3

7.6

8.8

ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse

Width HIGH

FO = 32

FO = 486 2.4

2.2

2.4

2.6

2.7

3.0

3.2

3.5

4.5

4.9

ns

Minimum Pulse

Width LOW

FO = 32 2.2

FO = 486 2.4

2.4

2.6

2.7

3.0

3.2

3.5

4.5

4.9

ns

Maximum Skew

FO = 32

FO = 486

0.5

0.6

0.7

0.8

1.1

ns

Input Latch External

Set-Up

FO = 32

FO = 486 0.0

0.0

ns

Input Latch External

Hold

FO = 32 2.8

FO = 486 3.3

FO = 32 4.7

FO = 486 5.1

3.1

3.7

3.5

4.2

4.1

4.9

5.7

6.9

ns

Minimum Period

5.2

5.7

6.2

6.5

7.1

10.9

11.9

ns

(1/f_MAX

)

DS2316 Datasheet Revision 16.0

71

40MX and 42MX FPGAs

Table 42 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

TTL Output Module Timing⁵

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

Data-to-Pad HIGH

Data-to-Pad LOW

2.4

2.8

2.5

2.8

5.2

4.8

2.9

2.7

3.2

2.8

3.1

5.7

5.3

3.2

3.1

3.6

3.2

3.5

6.5

6.0

3.6

4.2

3.8

4.2

7.6

7.1

4.3

5.1

5.9

5.3

5.9

ns

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

10.7 ns

9.9

6.0

ns

G-to-Pad LOW

I/O Latch Output Set-Up

I/O Latch Output Hold

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

t_LH

t_LCO

I/O Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

5.6

6.1

6.9

8.1

11.4 ns

t_ACO

Array Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

10.6

11.8

13.4

15.7

22.0 ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.04

0.03

0.04

0.03

0.04

0.03

0.05

0.04

0.07 ns/pF

0.06 ns/pF

DS2316 Datasheet Revision 16.0

72

40MX and 42MX FPGAs

Table 42 • A42MX24 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

CMOS Output Module Timing⁵

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.1

2.4

2.5

2.8

5.2

4.8

4.9

3.5

2.6

2.8

3.1

5.7

5.3

5.4

3.9

3.0

3.2

3.5

6.5

6.0

6.2

4.6

3.5

3.8

4.2

7.6

7.1

7.2

6.4

4.9

ns

5.3

5.8

10.7

9.9

10.1

G-to-Pad LOW

I/O Latch Set-Up

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

t_LH

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

5.5

6.1

6.9

8.1

11.3

22.0

t_ACO

Array Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

10.6

11.8

13.4

15.7

ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.04

0.03

0.04

0.03

0.04

0.03

0.05

0.04

0.07 ns/pF

0.06 ns/pF

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules

can be obtained from the Timer utility.

4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External

setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD

signal to the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading

Table 43 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Combinatorial Functions¹

t_PD

Internal Array Module Delay

2.0

1.1

1.8

2.2

2.1

2.5

3.0

3.4 ns

4.2 ns

t_PDD

Internal Decode Module Delay

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

1.7

2.0

1.1

1.5

1.8

1.3

1.6

2.0

2.3

3.7

1.4

1.8

2.2

2.6

4.2

1.7

2.1

2.6

3.1

5.0

2.3 ns

3.0 ns

3.7 ns

4.3 ns

7.0 ns

DS2316 Datasheet Revision 16.0

73

40MX and 42MX FPGAs

Table 43 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Sequential Timing^{3, 4}

t_CO

Flip-Flop Clock-to-Output

2.1

3.4

2.0

1.9

2.3

2.1

2.7

2.5

3.7 ns

3.4 ns

ns

t_GO

Latch Gate-to-Output

t_SUD

t_HD

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset-to-Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

0.4

0.0

0.5

0.0

0.6

0.0

0.7

0.0

0.9

0.0

ns

t_RO

2.0

2.2

2.5

2.9

4.1 ns

ns

t_SUENA

t_HENA

t_WCLKA

0.6

0.0

4.6

0.6

0.0

5.2

0.7

0.0

5.8

0.8

0.0

6.9

1.2

0.0

9.6

ns

Flip-Flop (Latch)

ns

Clock Active Pulse Width

t_WASYN

Flip-Flop (Latch)

6.1

6.8

7.7

9.0

12.6

Asynchronous Pulse Width

ns

Input Module Propagation Delays

t_INPY

t_INGO

t_INH

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.4

1.8

1.6

1.9

1.8

2.2

2.6

3.0 ns

3.6 ns

ns

0.0

0.7

6.5

0.0

0.7

7.3

0.0

0.8

8.2

0.0

1.0

9.7

0.0

t_INSU

t_ILA

Input Latch Set-Up

1.4

ns

Latch Active Pulse Width

13.5

ns

DS2316 Datasheet Revision 16.0

74

40MX and 42MX FPGAs

Table 43 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

2.6

2.9

3.2

3.5

4.8

2.9

3.2

3.6

3.9

5.3

3.2

3.6

4.0

4.4

6.1

3.8

4.3

4.8

5.2

7.1

5.3 ns

6.0 ns

6.6 ns

7.3 ns

10.0 ns

Global Clock Network

t_CKH

Input LOW to HIGH

FO = 32

FO = 486

4.4

4.8

5.3

5.5

6.0

6.5

7.1

9.1 ns

10.0 ns

t_CKL

Input HIGH to LOW

FO = 32

FO = 486

5.1

6.0

5.7

6.6

6.4

7.5

7.6

8.8

10.6 ns

12.4 ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

Minimum Pulse

Width HIGH

FO = 32

FO = 486 3.3

3.0

3.3

3.7

3.8

4.2

4.5

4.9

6.3

6.9

ns

Minimum Pulse

Width LOW

FO = 32 3.0

FO = 486 3.3

3.4

3.7

3.8

4.2

4.5

4.9

6.3

6.9

ns

Maximum Skew

FO = 32

FO = 486

0.8

1.0

1.1

1.6 ns

Input Latch External

Set-Up

FO = 32

FO = 486 0.0

0.0

ns

TTL Output Module Timing⁵

t_DLH

Data-to-Pad HIGH

Data-to-Pad LOW

3.4

4.0

3.6

3.9

7.2

6.7

4.8

3.8

4.4

4.0

4.4

8.0

7.5

5.3

4.3

5.0

4.5

5.0

9.1

8.5

6.0

5.0

5.9

5.3

5.8

10.7

9.9

7.2

7.1 ns

8.3 ns

7.4 ns

8.2 ns

14.9 ns

13.9 ns

10.0 ns

ns

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

G-to-Pad LOW

I/O Latch Output Set-Up

0.7

0.8

1.0

1.4

DS2316 Datasheet Revision 16.0

75

40MX and 42MX FPGAs

Table 43 • A42MX24 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

TTL Output Module Timing⁵

t_LH

I/O Latch Output Hold

0.0

ns

t_LCO

I/O Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

7.7

8.5

9.6

11.3

22.0

15.9 ns

t_ACO

Array Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

14.8

16.5

18.7

30.8 ns

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.05

0.04

0.05

0.04

0.06

0.05

0.07

0.06

0.10 ns/pF

0.08 ns/pF

CMOS Output Module Timing⁵

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

4.8

3.5

3.6

3.4

7.2

6.7

6.8

5.3

3.9

4.0

8.0

7.5

7.6

5.5

4.1

4.5

5.0

9.0

8.5

8.6

6.4

9.0 ns

6.8 ns

7.4 ns

8.2 ns

14.9 ns

13.9 ns

14.2 ns

ns

4.9

5.3

5.8

10.7

9.9

10.1

G-to-Pad LOW

I/O Latch Set-Up

0.7

0.0

0.7

0.0

0.8

0.0

1.0

0.0

1.4

0.0

t_LH

I/O Latch Hold

ns

t_LCO

I/O Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

7.7

8.5

9.6

11.3

22.0

15.9 ns

t_ACO

Array Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

14.8

16.5

18.7

30.8 ns

d_TLH

d_THL

t_HEXT

Capacitive Loading, LOW to HIGH

Capacitive Loading, HIGH to LOW

0.05

0.04

0.05

0.04

0.06

0.05

0.07

0.06

0.10 ns/pF

0.08 ns/pF

Input Latch External

Hold

FO = 32

3.9

4.3

5.2

4.9

5.8

5.7

6.9

8.1

9.6

ns

FO = 486 4.6

FO = 32 7.8

FO = 486 8.6

t_P

Minimum Period

8.7

9.5

10.4

10.8

11.9

18.2

19.9

ns

(1/f_MAX

)

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer utility.

4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External

setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD

signal to the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

DS2316 Datasheet Revision 16.0

76

40MX and 42MX FPGAs

Table 44 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Parameter / Description

Logic Module Combinatorial Functions¹

t_PD

Internal Array Module Delay

1.3

1.6

1.5

1.8

1.7

2.0

2.4

2.7

3.3

ns

t_PDD

Internal Decode Module Delay

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RDD

FO = 1 Routing Delay

FO = 2 Routing Delay

FO =3 Routing Delay

0.9

1.3

1.6

2.0

3.3

0.3

1.0

1.4

1.8

2.2

3.7

0.4

1.2

1.6

2.0

2.5

4.2

0.4

1.4

1.9

2.4

2.9

4.9

0.5

2.0

2.7

3.4

4.1

6.9

0.7

ns

FO = 4 Routing Delay

FO = 8 Routing Delay

Decode-to-Output Routing Delay

Logic Module Sequential Timing^{3, 4}

t_CO

t_GO

t_SUD

t_HD

t_RO

Flip-Flop Clock-to-Output

Latch Gate-to-Output

1.3

1.4

1.6

1.9

2.7

ns

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset-to-Output

0.3

0.0

0.3

0.0

0.4

0.0

0.5

0.0

0.7

0.0

1.6

1.7

2.0

2.3

3.2

t_SUENAFlip-Flop (Latch) Enable Set-Up 0.7

0.8

0.0

3.7

0.9

0.0

4.2

1.0

0.0

4.9

1.4

0.0

6.9

t_HENA

Flip-Flop (Latch) Enable Hold

0.0

3.3

t_WCLKAFlip-Flop (Latch) Clock Active

Pulse Width

t_WASYNFlip-Flop (Latch) Asynchronous 4.4

Pulse Width

4.8

5.5

6.4

9.0

ns

Synchronous SRAM Operations

t_RC

Read Cycle Time

6.8

3.4

7.5

3.8

8.5

4.3

10.0

5.0

14.0

7.0

ns

t_WC

Write Cycle Time

t_RCKHL

t_RCO

Clock HIGH/LOW Time

Data Valid After Clock

HIGH/LOW

3.4

3.8

4.3

5.0

7.0

t_ADSU

Address/Data Set-Up Time

1.6

1.8

2.0

2.4

3.4

ns

Synchronous SRAM Operations

t_ADHAddress/Data Hold Time

t_RENSURead Enable Set-Up

t_RENHRead Enable Hold

t_WENSUWrite Enable Set-Up

0.0

0.6

3.4

2.7

0.0

2.8

0.0

0.7

3.8

3.0

0.0

3.1

0.0

0.8

4.3

3.4

0.0

3.5

0.0

0.9

5.0

4.0

0.0

4.1

0.0

1.3

7.0

5.6

0.0

5.7

0.0

ns

t_WENH

t_BENS

t_BENH

Write Enable Hold

Block Enable Set-Up

Block Enable Hold

DS2316 Datasheet Revision 16.0

77

40MX and 42MX FPGAs

Table 44 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Asynchronous SRAM Operations

t_RPD

t_RDADVRead Address Valid

t_ADSUAddress/Data Set-Up Time

t_ADHAddress/Data Hold Time

Asynchronous Access Time

8.1

9.0

10.2

12.0

16.8 ns

8.8

1.6

0.0

9.8

1.8

0.0

0.7

11.1

2.0

0.0

0.8

13.0

2.4

18.2

3.4

ns

0.0

t_RENSUARead Enable Set-Up to Address 0.6

Valid

0.9

1.3

t_RENHARead Enable Hold

t_WENSUWrite Enable Set-Up

3.4

2.7

0.0

3.8

3.0

0.0

4.3

3.4

0.0

5.0

4.0

0.0

7.0

5.6

0.0

ns

t_WENH

t_DOH

Write Enable Hold

Data Out Hold Time

1.2

1.3

1.5

1.8

2.5

ns

Input Module Propagation Delays

t_INPY

t_INGO

t_INH

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.0

1.4

1.1

1.6

1.3

1.8

1.5

2.1

2.9

ns

0.0

0.5

4.7

0.0

0.5

5.2

0.0

0.6

5.9

0.0

0.7

6.9

0.0

1.0

9.7

t_INSU

Input Latch Set-Up

t_ILA

Latch Active Pulse Width

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO = 1 Routing

Delay

2.0

2.3

2.6

3.0

4.3

2.2

2.6

2.9

3.3

4.8

2.5

2.9

3.3

3.8

5.5

2.9

3.4

3.9

4.4

6.4

4.1

4.8

5.5

6.2

9.0

ns

FO = 2 Routing

Delay

FO = 3 Routing

Delay

FO = 4 Routing

Delay

FO = 8 Routing

Delay

Global Clock Network

t_CKHInput LOW to HIGH FO = 32

2.7

3.0

3.3

3.4

3.8

4.0

4.4

5.6

6.2

ns

FO = 635

t_CKL

Input HIGH to LOW FO = 32

FO = 635

3.8

4.9

4.2

5.4

4.8

6.1

5.6

7.2

7.8

10.1 ns

ns

t_PWH

t_PWL

t_CKSW

Minimum Pulse

Width HIGH

FO = 32

FO = 635 2.0

1.8

2.0

2.2

2.5

2.6

2.9

3.6

4.1

ns

Minimum Pulse

Width LOW

FO = 32 1.8

FO = 635 2.0

2.0

2.2

2.5

2.6

2.9

3.6

4.1

ns

Maximum Skew

FO = 32

FO = 635

0.8

0.9

1.0

1.4

ns

DS2316 Datasheet Revision 16.0

78

40MX and 42MX FPGAs

Table 44 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_SUEXT

t_HEXT

t_P

Input Latch External FO = 32

0.0

ns

Set-Up

FO = 635 0.0

Input Latch External FO = 32

2.8

3.2

3.7

3.6

4.2

4.9

5.9

6.9

ns

Hold

FO = 635 3.3

Minimum Period

FO = 32 5.5

FO = 635 6.0

Maximum Datapath FO = 32

Frequency FO = 635

TTL Output Module Timing⁵

6.1

6.6

7.2

7.6

8.3

12.7

13.8

ns

(1/f_MAX

)

f_MAX

180

166

164

151

139

131

121

79

73

MHz

t_DLH

Data-to-Pad HIGH

2.6

3.0

2.7

3.0

5.3

2.8

3.3

3.0

3.3

5.8

3.2

3.7

3.3

3.7

6.6

3.8

4.4

3.9

4.3

7.8

5.3

6.2

5.5

6.1

ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

10.9 ns

DS2316 Datasheet Revision 16.0

79

40MX and 42MX FPGAs

Table 44 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

TTL Output Module Timing⁵

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Enable Pad LOW to Z

G-to-Pad HIGH

4.9

2.9

5.5

3.3

6.2

3.7

7.3

4.4

10.2 ns

6.1

ns

G-to-Pad LOW

I/O Latch Output Set-Up

I/O Latch Output Hold

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

t_LCO

I/O Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

5.7

6.3

7.1

8.4

11.8 ns

t_ACO

d_TLH

d_THL

Array Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

7.8

8.6

9.8

11.5

0.10

16.1 ns

Capacitive Loading,

LOW to HIGH

0.07

0.08

0.09

0.14 ns/pF

Capacitive Loading,

HIGH to LOW

DS2316 Datasheet Revision 16.0

80

40MX and 42MX FPGAs

Table 44 • A42MX36 Timing Characteristics (Nominal 5.0 V Operation)

(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

CMOS Output Module Timing⁵

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

3.5

2.5

2.7

2.9

5.3

4.9

5.0

3.9

2.7

3.0

3.3

5.8

5.5

5.6

4.5

3.1

3.3

3.7

6.6

6.2

6.3

5.2

3.6

3.9

4.3

7.8

7.3

7.5

7.3

5.1

ns

5.5

6.1

10.9

10.2

10.4

G-to-Pad LOW

I/O Latch Set-Up

0.5

0.0

0.5

0.0

0.6

0.0

0.7

0.0

1.0

0.0

I/O Latch Hold

t_LCO

I/O Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

5.7

7.8

6.3

8.6

7.1

9.8

8.4

11.8

16.1

t_ACO

d_TLH

d_THL

Array Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

11.5

0.10

ns

Capacitive Loading,

LOW to HIGH

0.07

0.08

0.09

0.14 ns/pF

Capacitive Loading,

HIGH to LOW

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer utility.

4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External

setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD

signal to the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

Table 45 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Logic Module Combinatorial Functions¹

t_PD

Internal Array Module Delay

Internal Decode Module Delay

1.9

2.2

2.1

2.5

2.3

2.8

2.7

3.3

3.8 ns

4.7 ns

t_PDD

Logic Module Predicted Routing Delays²

t_RD1

t_RD2

t_RD3

t_RD4

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

1.3

1.8

2.3

2.8

1.5

2.0

2.5

3.1

1.7

2.3

2.8

3.5

2.0

2.7

3.4

4.1

2.7 ns

3.7 ns

4.7 ns

5.7 ns

DS2316 Datasheet Revision 16.0

81

40MX and 42MX FPGAs

Table 45 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

t_RD5FO = 8 Routing Delay

t_RDDDecode-to-Output Routing Delay

Logic Module Sequential Timing^{3, 4}

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

4.6

0.5

5.2

0.5

5.8

0.6

6.9

0.7

9.6 ns

1.0 ns

t_CO

Flip-Flop Clock-to-Output

1.8

2.0

2.3

2.7

3.7 ns

ns

t_GO

Latch Gate-to-Output

t_SUD

t_HD

Flip-Flop (Latch) Set-Up Time

Flip-Flop (Latch) Hold Time

Flip-Flop (Latch) Reset-to-Output

Flip-Flop (Latch) Enable Set-Up

Flip-Flop (Latch) Enable Hold

0.4

0.0

0.5

0.0

0.6

0.0

0.7

0.0

0.9

0.0

ns

t_RO

2.2

2.4

2.7

3.2

4.5 ns

ns

t_SUENA

t_HENA

t_WCLKA

1.0

0.0

4.6

1.1

0.0

5.2

1.2

0.0

5.8

1.4

0.0

6.9

2.0

0.0

9.6

ns

Flip-Flop (Latch)

ns

Clock Active Pulse Width

t_WASYN

Flip-Flop (Latch)

6.1

6.8

7.7

9.0

12.6

ns

Asynchronous Pulse Width

Synchronous SRAM Operations

t_RC

Read Cycle Time

9.5

4.8

10.5

5.3

11.9

6.0

14.0

7.0

19.6

9.8

ns

t_WC

Write Cycle Time

t_RCKHL

t_RCO

t_ADSU

Clock HIGH/LOW Time

Data Valid After Clock HIGH/LOW

Address/Data Set-Up Time

ns

4.8

5.3

6.0

7.0

9.8 ns

ns

2.3

2.5

2.8

3.4

4.8

DS2316 Datasheet Revision 16.0

82

40MX and 42MX FPGAs

Table 45 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Synchronous SRAM Operations

t_ADH

Address/Data Hold Time

Read Enable Set-Up

Read Enable Hold

0.0

0.9

4.8

3.8

0.0

3.9

0.0

1.0

5.3

4.2

0.0

4.3

0.0

1.1

6.0

4.8

0.0

4.9

0.0

1.3

7.0

5.6

0.0

5.7

0.0

1.8

9.8

7.8

0.0

8.0

0.0

ns

t_RENSU

t_RENH

t_WENSU

t_WENH

t_BENS

t_BENH

Write Enable Set-Up

Write Enable Hold

Block Enable Set-Up

Block Enable Hold

Asynchronous SRAM Operations

t_RPD

Asynchronous Access Time

Read Address Valid

11.3

12.6

14.3

16.8

23.5 ns

t_RDADV

t_ADSU

t_ADH

12.3

2.3

13.7

2.5

15.5

2.8

18.2

3.4

0.0

1.3

25.5

4.8

ns

Address/Data Set-Up Time

Address/Data Hold Time

0.0

t_RENSUARead Enable Set-Up to Address

Valid

0.9

1.0

1.1

1.8

t_RENHA

t_WENSU

t_WENH

t_DOH

Read Enable Hold

Write Enable Set-Up

Write Enable Hold

Data Out Hold Time

4.8

3.8

0.0

5.3

4.2

0.0

6.0

4.8

0.0

7.0

5.6

0.0

9.8

7.8

0.0

ns

1.8

2.0

2.1

2.5

3.5 ns

Input Module Propagation Delays

t_INPY

t_INGO

t_INH

Input Data Pad-to-Y

Input Latch Gate-to-Output

Input Latch Hold

1.4

2.0

1.6

2.2

1.8

2.5

2.1

2.9

3.0 ns

4.1 ns

ns

0.0

0.7

6.5

0.0

0.7

7.3

0.0

0.8

8.2

0.0

1.0

9.7

0.0

t_INSU

t_ILA

Input Latch Set-Up

1.4

ns

Latch Active Pulse Width

13.5

ns

DS2316 Datasheet Revision 16.0

83

40MX and 42MX FPGAs

Table 45 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Input Module Predicted Routing Delays²

t_IRD1

t_IRD2

t_IRD3

t_IRD4

t_IRD8

FO = 1 Routing Delay

FO = 2 Routing Delay

FO = 3 Routing Delay

FO = 4 Routing Delay

FO = 8 Routing Delay

2.8

3.2

3.7

4.2

6.1

3.1

3.5

4.1

4.6

6.8

3.5

4.1

4.7

5.3

7.7

4.1

4.8

5.5

6.2

9.0

5.7 ns

6.7 ns

7.7 ns

8.7 ns

12.6 ns

Global Clock Network

t_CKHInput LOW to HIGH

FO = 32

FO = 635

4.6

5.0

5.1

5.6

5.7

6.3

6.7

7.4

9.3 ns

10.3 ns

t_CKL

Input HIGH to LOW

FO = 32

FO = 635

5.3

6.8

5.9

7.6

6.7

8.6

7.8

10.1

11.0 ns

14.1 ns

t_PWH

t_PWL

t_CKSW

t_SUEXT

t_HEXT

t_P

Minimum Pulse

Width HIGH

FO = 32

FO = 635 2.8

2.5

2.7

3.1

3.5

3.6

4.1

5.1

5.7

ns

Minimum Pulse

Width LOW

FO = 32 2.5

FO = 635 2.8

2.7

3.1

3.5

3.6

4.1

5.1

5.7

ns

Maximum Skew

FO = 32

FO = 635

1.0

1.2

1.3

1.5

2.2 ns

Input Latch

External Set-Up

FO = 32

FO = 635 0.0

0.0

ns

Input Latch

External Hold

FO = 32 4.0

FO = 635 4.6

FO = 32 9.2

4.4

5.2

5.0

5.9

6.9

8.2

9.6

ns

Minimum Period

10.2

11.0

11.1

12.0

12.7

13.8

21.2

23.0

ns

(1/f_MAX

)

FO = 635 9.9

f_MAX

Maximum Datapath

Frequency

FO = 32

FO = 635

108

100

98

91

90

83

79

73

47

44

MHz

TTL Output Module Timing⁵

t_DLH

Data-to-Pad HIGH

3.6

4.2

3.7

4.1

7.34

4.0

4.6

4.2

4.6

8.2

4.5

5.2

4.7

5.2

9.3

5.3

6.2

5.5

6.1

10.9

7.4 ns

8.6 ns

7.7 ns

8.5 ns

15.3 ns

t_DHL

Data-to-Pad LOW

t_ENZH

t_ENZL

t_ENHZ

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

TTL Output Module Timing⁵

t_ENLZ

t_GLH

t_GHL

t_LSU

t_LH

Enable Pad LOW to Z

G-to-Pad HIGH

6.9

4.9

7.6

5.5

8.7

6.2

10.2

7.3

14.3 ns

10.2 ns

ns

G-to-Pad LOW

7.3

I/O Latch Output Set-Up

I/O Latch Output Hold

0.7

0.0

0.7

0.0

0.8

0.0

1.0

0.0

1.4

0.0

ns

t_LCO

I/O Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

7.9

8.8

10.0

11.8

16.5 ns

DS2316 Datasheet Revision 16.0

84

40MX and 42MX FPGAs

Table 45 • A42MX36 Timing Characteristics (Nominal 3.3 V Operation)

(Worst-Case Commercial Conditions, VCCA = 3.0 V, T_J= 70°C) (continued)

–3 Speed –2 Speed –1 Speed Std Speed –F Speed

Parameter / Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

t_ACO

Array Latch Clock-to-Out

10.9

12.1

13.7

16.1

22.5 ns

(Pad-to-Pad) 32 I/O

d_TLH

d_THL

Capacitive Loading, LOW to HIGH

0.10

0.11

0.12

0.14

0.20 ns/pF

Capacitive Loading, HIGH to LOW

CMOS Output Module Timing⁵

t_DLH

t_DHL

t_ENZH

t_ENZL

t_ENHZ

t_ENLZ

t_GLH

t_GHL

t_LSU

Data-to-Pad HIGH

Data-to-Pad LOW

Enable Pad Z to HIGH

Enable Pad Z to LOW

Enable Pad HIGH to Z

Enable Pad LOW to Z

G-to-Pad HIGH

4.9

3.4

3.7

4.1

7.4

6.9

7.0

5.5

3.8

4.1

4.6

8.2

7.6

7.8

6.2

4.3

4.7

5.2

9.3

8.7

8.9

7.3

10.3 ns

7.1 ns

7.7 ns

8.5 ns

15.3 ns

14.3 ns

14.6 ns

ns

5.1

5.5

6.1

10.9

10.2

10.4

G-to-Pad LOW

I/O Latch Set-Up

0.7

0.0

0.7

0.0

0.8

0.0

1.0

0.0

1.4

0.0

t_LH

I/O Latch Hold

ns

t_LCO

I/O Latch Clock-to-Out

(Pad-to-Pad) 32 I/O

7.9

8.8

10.0

11.8

16.5 ns

1. For dual-module macros, use t_PD1+ t_RD1+ t_PDn, t_CO+ t_RD1+ t_PDn, or t_PD1+ t_RD1+ t_SUD, whichever is appropriate.

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual performance.

3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be

obtained from the Timer utility.

4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External

setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external

PAD signal to the G input subtracts (adds) to the internal setup (hold) time.

5. Delays based on 35 pF loading.

3.12 Pin Descriptions

This section lists the pin descriptions for 40MX and 42MX series FPGAs.

CLK/A/B, I/O Global Clock

Clock inputs for clock distribution networks. CLK is for 40MX while CLKA and CLKB are for 42MX

devices. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an

I/O.

DCLK, I/ODiagnostic Clock

Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH.

This pin functions as an I/O when the MODE pin is LOW.

GND, Ground

Input LOW supply voltage.

I/O, Input/Output

DS2316 Datasheet Revision 16.0

85

40MX and 42MX FPGAs

Input, output, tristate or bidirectional buffer. Input and output levels are compatible with standard TTL and

CMOS specifications. Unused I/Os pins are configured by the Designer software as shown in Table 46,

page 86.

Table 46 • Configuration of Unused I/Os

Device

Configuration

A40MX02, A40MX04 Pulled LOW

A42MX09, A42MX16 Pulled LOW

A42MX24, A42MX36 Tristated

In all cases, it is recommended to tie all unused MX I/O pins to LOW on the board. This applies to all

dual-purpose pins when configured as I/Os as well.

LP, Low Power Mode

Controls the low power mode of all 42MX devices. The device is placed in the low power mode by

connecting the LP pin to logic HIGH. In low power mode, all I/Os are tristated, all input buffers are turned

OFF, and the core of the device is turned OFF. To exit the low power mode, the LP pin must be set to

LOW. The device enters the low power mode 800 ns after the LP pin is driven to a logic HIGH. It will

resume normal operation in 200 µs after the LP pin is driven to a logic LOW.

MODE, Mode

Controls the use of multifunction pins (DCLK, PRA, PRB, SDI, TDO). The MODE pin is held HIGH to

provide verification capability. The MODE pin should be terminated to GND through a 10k resistor so

that the MODE pin can be pulled HIGH when required.

NC, No Connection

This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be

left floating with no effect on the operation of the device.

PRA, I/O

PRB, I/OProbe A/B

The probe pin is used to output data from any user-defined design node within the device. Each

diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of

any signal path within the device. The probe pin can be used as a user-defined I/O when verification has

been completed. The pin's probe capabilities can be permanently disabled to protect programmed design

confidentiality. The probe pin is accessible when the MODE pin is HIGH. This pin functions as an I/O

when the MODE pin is LOW.

QCLKA/B/C/D, I/O Quadrant Clock

Quadrant clock inputs for A42MX36 devices. When not used as a register control signal, these pins can

function as user I/Os.

SDI, I/OSerial Data Input

Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is

HIGH. This pin functions as an I/O when the MODE pin is LOW.

SDO, I/OSerial Data Output

Serial data output for diagnostic probe and device programming. SDO is active when the MODE pin is

HIGH. This pin functions as an I/O when the MODE pin is LOW. SDO is available for 42MX devices only.

When Silicon Explorer II is being used, SDO will act as an output while the “checksum” command is run.

It will return to user I/O when “checksum” is complete.

DS2316 Datasheet Revision 16.0

86

40MX and 42MX FPGAs

TCK, I/O Test Clock

Clock signal to shift the boundary scan test (BST) data into the device. This pin functions as an I/O when

“Reserve JTAG” is not checked in the Designer Software. BST pins are only available in A42MX24 and

A42MX36 devices.

TDI, I/OTest Data In

Serial data input for BST instructions and test data. Data is shifted in on the rising edge of TCK. This pin

functions as an I/O when “Reserve JTAG” is not checked in the Designer Software. BST pins are only

available in A42MX24 and A42MX36 devices.

TDO, I/OTest Data Out

Serial data output for BST instructions and test data. This pin functions as an I/O when "Reserve JTAG"

is not checked in the Designer Software. BST pins are only available in A42MX24 and A42MX36

devices.

TMS, I/OTest Mode Select

The TMS pin controls the use of the IEEE 1149.1 boundary scan pins (TCK, TDI, TDO). In flexible mode

when the TMS pin is set to LOW, the TCK, TDI and TDO pins act as boundary scan pins. Once the

boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state

machine reaches the “logic reset” state. At this point, the boundary scan pins will be released and will

function as regular I/O pins. The “logic reset” state is reached 5 TCK cycles after the TMS pin is set to

HIGH. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications. IEEE JTAG

specification recommends a 10k pull-up resistor on the pin. BST pins are only available in A42MX24

and A42MX36 devices.

VCC, Supply Voltage

Input supply voltage for 40MX devices

VCCA, Supply Voltage

Supply voltage for an array in 42MX devices

VCCI, Supply Voltage

Supply voltage for I/Os in 42MX devices

WD, I/OWide Decode Output

When a wide decode module is used in a 42MX device; this pin can be used as a dedicated output from

the wide decode module. This direct connection eliminates additional interconnect delays associated

with regular logic modules. To implement the direct I/O connection, connect an output buffer of any type

to the output of the wide decode macro and place this output on one of the reserved WD pins.

DS2316 Datasheet Revision 16.0

87

Package Pin Assignments

4

Package Pin Assignments

The following figures and tables give the details of the package pin assignments.

Figure 38 • PL44

1

44

44-Pin

PLCC

Table 47 • PL44

PL44

Pin Number A40MX02 Function A40MX04 Function

1

I/O

2

I/O

3

VCC

I/O

VCC

I/O

4

5

I/O

6

I/O

7

I/O

8

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

GND

I/O

GND

I/O

VCC

I/O

VCC

I/O

VCC

I/O

VCC

I/O

DS2316 Datasheet Revision 16.0

88

Package Pin Assignments

Table 47 • PL44 (continued)

PL44

Pin Number A40MX02 Function A40MX04 Function

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

GND

I/O

GND

I/O

VCC

I/O

VCC

I/O

GND

CLK, I/O

MODE

VCC

SDI, I/O

DCLK, I/O

PRA, I/O

PRB, I/O

I/O

GND

CLK, I/O

MODE

VCC

SDI, I/O

DCLK, I/O

PRA, I/O

PRB, I/O

I/O

GND

I/O

GND

I/O

DS2316 Datasheet Revision 16.0

89

Package Pin Assignments

Figure 39 • PL68

1 68

68-Pin

PLCC

Table 48 • PL68

PL68

Pin Number A40MX02 Function A40MX04 Function

1

I/O

2

I/O

3

I/O

4

VCC

I/O

VCC

I/O

5

6

I/O

7

I/O

8

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

I/O

GND

I/O

GND

I/O

VCC

I/O

VCC

I/O

DS2316 Datasheet Revision 16.0

90

Package Pin Assignments

Table 48 • PL68 (continued)

PL68

Pin Number A40MX02 Function A40MX04 Function

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

I/O

VCC

I/O

VCC

I/O

GND

I/O

GND

I/O

VCC

I/O

VCC

I/O

GND

I/O

GND

I/O

CLK, I/O

I/O

CLK, I/O

I/O

MODE

VCC

SDI, I/O

DCLK, I/O

PRA, I/O

PRB, I/O

I/O

MODE

VCC

SDI, I/O

DCLK, I/O

PRA, I/O

PRB, I/O

I/O

DS2316 Datasheet Revision 16.0

91

Package Pin Assignments

Table 48 • PL68 (continued)

PL68

Pin Number A40MX02 Function A40MX04 Function

61

62

63

64

65

66

67

68

I/O

GND

I/O

GND

I/O

Figure 40 • PL84

1

84

84-Pin

PLCC

Table 49 • PL84

PL84

Pin Number A40MX04 Function A42MX09 Function A42MX16 Function A42MX24 Function

1

2

3

4

5

6

7

8

9

I/O

VCC

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

WD, I/O

GND

I/O

GND

I/O

WD, I/O

I/O

DS2316 Datasheet Revision 16.0

92

Package Pin Assignments

Table 49 • PL84 (continued)

PL84

Pin Number A40MX04 Function A42MX09 Function A42MX16 Function A42MX24 Function

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

NC

I/O

MODE

I/O

MODE

I/O

MODE

I/O

GND

I/O

VCCA

VCCI

I/O

VCCI

VCCA

I/O

VCCI

VCCA

I/O

VCC

I/O

GND

I/O

GND

I/O

GND

I/O

VCC

I/O

TMS, I/O

TDI, I/O

WD, I/O

I/O

WD, I/O

I/O

GND

I/O

VCCA

I/O

VCCA

I/O

VCCA

WD, I/O

I/O

VCC

I/O

DS2316 Datasheet Revision 16.0

93

Package Pin Assignments

Table 49 • PL84 (continued)

PL84

Pin Number A40MX04 Function A42MX09 Function A42MX16 Function A42MX24 Function

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

I/O

WD, I/O

I/O

GND

I/O

GND

I/O

GND

WD, I/O

SDO, TDO, I/O

I/O

SDO, I/O

I/O

SDO, I/O

I/O

GND

I/O

TCK, I/O

LP

I/O

LP

CLK, I/O

I/O

VCCA

VCCI

I/O

VCCA

VCCI

I/O

VCCA

VCCI

I/O

MODE

VCC

I/O

GND

I/O

GND

I/O

GND

I/O

SDI, I/O

DCLK, I/O

PRA, I/O

PRB, I/O

I/O

SDI, I/O

I/O

SDI, I/O

I/O

SDI, I/O

I/O

WD, I/O

PRA, I/O

I/O

PRA, I/O

I/O

PRA, I/O

I/O

GND

I/O

CLKA, I/O

DS2316 Datasheet Revision 16.0

94

Package Pin Assignments

Table 49 • PL84 (continued)

PL84

Pin Number A40MX04 Function A42MX09 Function A42MX16 Function A42MX24 Function

84

I/O

VCCA

Figure 41 • PQ100

100-Pin

PQFP

100

1

Table 50 • PQ 100

PQ100

Pin Number A40MX02 Function A40MX04 Function A42MX09 Function A42MX16 Function

1

NC

PRB, I/O

I/O

NC

PRB, I/O

I/O

2

DCLK, I/O

I/O

DCLK, I/O

I/O

3

4

MODE

I/O

MODE

I/O

5

6

I/O

7

I/O

8

I/O

9

I/O

GND

I/O

GND

I/O

10

11

12

13

14

15

16

17

18

I/O

GND

I/O

GND

I/O

VCCA

VCCI

I/O

VCCA

I/O

DS2316 Datasheet Revision 16.0

95

Package Pin Assignments

Table 50 • PQ 100 (continued)

PQ100

Pin Number A40MX02 Function A40MX04 Function A42MX09 Function A42MX16 Function

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

VCC

I/O

V_CC

I/O

NC

I/O

GND

I/O

VCC

I/O

NC

I/O

GND

I/O

GND

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

VCCA

I/O

VCCA

I/O

VCC

I/O

GND

I/O

GND

I/O

NC

I/O

SDO, I/O

I/O

SDO, I/O

I/O

DS2316 Datasheet Revision 16.0

96

Package Pin Assignments

Table 50 • PQ 100 (continued)

PQ100

Pin Number A40MX02 Function A40MX04 Function A42MX09 Function A42MX16 Function

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

VCC

I/O

VCC

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

LP

I/O

VCCA

VCCI

VCCA

I/O

VCCA

VCCI

VCCA

I/O

VCC

I/O

VCC

I/O

GND

I/O

GND

I/O

NC

I/O

NC

I/O

SDI, I/O

I/O

SDI, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

PRA, I/O

I/O

PRA, I/O

I/O

CLKA, I/O

VCCA

I/O

CLKA, I/O

VCCA

I/O

CLK, I/O

I/O

CLK, I/O

I/O

MODE

CLKB, I/O

DS2316 Datasheet Revision 16.0

97

Package Pin Assignments

Table 50 • PQ 100 (continued)

PQ100

Pin Number A40MX02 Function A40MX04 Function A42MX09 Function A42MX16 Function

93

94

95

96

97

98

99

100

VCC

I/O

VCC

PRB, I/O

I/O

PRB, I/O

I/O

NC

I/O

NC

I/O

GND

I/O

GND

I/O

NC

I/O

SDI, I/O

DCLK, I/O

PRA, I/O

SDI, I/O

DCLK, I/O

PRA, I/O

I/O

DS2316 Datasheet Revision 16.0

98

Package Pin Assignments

Figure 42 • PQ144

144

1

144-Pin

PQFP

Table 51 • PQ144

PQ144

Pin Number A42MX09 Function

1

2

3

4

5

I/O

MODE

I/O

DS2316 Datasheet Revision 16.0

99

Package Pin Assignments

Table 51 • PQ144 (continued)

PQ144

Pin Number A42MX09 Function

6

I/O

7

I/O

8

I/O

9

GNDQ

GNDI

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

I/O

VSV

VCC

VCCI

NC

I/O

GND

GNDI

NC

I/O

BININ

BINOUT

I/O

DS2316 Datasheet Revision 16.0

100

Package Pin Assignments

Table 51 • PQ144 (continued)

PQ144

Pin Number A42MX09 Function

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

I/O

GNDQ

GNDI

NC

I/O

VCC

VCCI

NC

I/O

GND

GNDI

I/O

SDO

I/O

GNDQ

DS2316 Datasheet Revision 16.0

101

Package Pin Assignments

Table 51 • PQ144 (continued)

PQ144

Pin Number A42MX09 Function

80

GNDI

NC

I/O

81

82

83

I/O

84

I/O

85

I/O

86

I/O

87

I/O

88

VKS

VPP

VCC

VCCI

NC

VSV

I/O

89

90

91

92

93

94

95

I/O

96

I/O

97

I/O

98

I/O

99

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

GND

GNDI

NC

I/O

SDI

I/O

GNDQ

DS2316 Datasheet Revision 16.0

102

Package Pin Assignments

Table 51 • PQ144 (continued)

PQ144

Pin Number A42MX09 Function

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

GNDI

NC

I/O

PROBA

I/O

CLKA

VCC

VCCI

NC

I/O

CLKB

I/O

PROBB

I/O

GND

GNDI

NC

I/O

DCLK

DS2316 Datasheet Revision 16.0

103

Package Pin Assignments

Figure 43 • PQ160

160

1

160-Pin

PQFP

Table 52 • PQ160

PQ160

Pin Number A42MX09 Function A42MX16 Function A42MX24 Function

1

I/O

2

DCLK, I/O

NC

DCLK, I/O

I/O

DCLK, I/O

I/O

3

4

I/O

WD, I/O

VCCI

I/O

5

I/O

6

NC

VCCI

I/O

7

I/O

8

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

NC

I/O

GND

NC

GND

I/O

GND

I/O

WD, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

VCCA

DS2316 Datasheet Revision 16.0

104

Package Pin Assignments

Table 52 • PQ160 (continued)

PQ160

Pin Number A42MX09 Function A42MX16 Function A42MX24 Function

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

CLKA, I/O

I/O

CLKA, I/O

I/O

CLKA, I/O

I/O

PRA, I/O

NC

PRA, I/O

I/O

PRA, I/O

WD, I/O

I/O

NC

I/O

WD, I/O

GND

WD, I/O

I/O

GND

NC

GND

I/O

NC

VCCI

I/O

VCCI

WD, I/O

SDI, I/O

I/O

SDI, I/O

I/O

SDI, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

NC

I/O

NC

VCCA

I/O

VCCA

I/O

VCCA

DS2316 Datasheet Revision 16.0

105

Package Pin Assignments

Table 52 • PQ160 (continued)

PQ160

Pin Number A42MX09 Function A42MX16 Function A42MX24 Function

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

VCCI

GND

VCCA

LP

VCCI

GND

VCCA

LP

VCCI

GND

VCCA

LP

I/O

TCK, I/O

I/O

GND

I/O

GND

I/O

GND

I/O

GND

NC

GND

I/O

GND

I/O

NC

I/O

NC

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

SDO, I/O

I/O

SDO, I/O

I/O

SDO, TDO, I/O

WD, I/O

I/O

NC

VCCI

I/O

VCCI

I/O

WD, I/O

GND

I/O

GND

NC

GND

I/O

DS2316 Datasheet Revision 16.0

106

Package Pin Assignments

Table 52 • PQ160 (continued)

PQ160

Pin Number A42MX09 Function A42MX16 Function A42MX24 Function

95

I/O

96

I/O

WD, I/O

I/O

97

I/O

98

VCCA

GND

NC

I/O

VCCA

GND

I/O

VCCA

GND

I/O

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

I/O

NC

I/O

WD, I/O

I/O

GND

NC

I/O

GND

I/O

GND

I/O

WD, I/O

I/O

NC

I/O

VCCI

I/O

VCCI

WD, I/O

I/O

NC

I/O

TDI, I/O

TMS, I/O

GND

I/O

GND

I/O

GND

I/O

NC

GND

I/O

GND

I/O

GND

I/O

NC

GND

I/O

GND

I/O

GND

I/O

DS2316 Datasheet Revision 16.0

107

Package Pin Assignments

Table 52 • PQ160 (continued)

PQ160

Pin Number A42MX09 Function A42MX16 Function A42MX24 Function

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

I/O

NC

I/O

VCCA

I/O

VCCA

I/O

NC

VCCI

GND

NC

I/O

VCCA

VCCI

GND

I/O

VCCA

VCCI

GND

I/O

GND

NC

I/O

GND

I/O

GND

I/O

NC

GND

I/O

VCCA

I/O

VCCA

I/O

GND

I/O

GND

I/O

MODE

GND

MODE

GND

MODE

GND

DS2316 Datasheet Revision 16.0

108

Package Pin Assignments

Figure 44 • PQ208

208

1

208-Pin PQFP

Table 53 • PQ208

PQ208

Pin Number A42MX16 Function A42MX24 Function A42MX36 Function

1

GND

NC

MODE

I/O

GND

VCCA

MODE

I/O

GND

VCCA

MODE

I/O

2

3

4

5

I/O

6

I/O

7

I/O

8

I/O

9

NC

I/O

10

11

12

13

14

15

16

17

18

19

20

I/O

NC

VCCA

I/O

VCCA

I/O

VCCA

I/O

DS2316 Datasheet Revision 16.0

109

Package Pin Assignments

Table 53 • PQ208 (continued)

PQ208

Pin Number A42MX16 Function A42MX24 Function A42MX36 Function

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

I/O

GND

I/O

GND

I/O

GND

I/O

GND

VCCI

VCCA

I/O

GND

VCCI

VCCA

I/O

GND

VCCI

VCCA

I/O

VCCA

I/O

VCCA

I/O

VCCA

I/O

NC

I/O

NC

GND

I/O

GND

TMS, I/O

TDI, I/O

I/O

GND

TMS, I/O

TDI, I/O

I/O

WD, I/O

DS2316 Datasheet Revision 16.0

110

Package Pin Assignments

Table 53 • PQ208 (continued)

PQ208

Pin Number A42MX16 Function A42MX24 Function A42MX36 Function

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

I/O

VCCI

NC

I/O

NC

I/O

GND

VCCA

NC

I/O

NC

I/O

WD, I/O

I/O

WD, I/O

I/O

VCCI

I/O

VCCI

I/O

QCLKA, I/O

WD, I/O

I/O

WD, I/O

I/O

WD, I/O

I/O

WD, I/O

I/O

GND

VCCA

VCCI

I/O

GND

VCCA

VCCI

I/O

WD, I/O

I/O

WD, I/O

I/O

QCLKB, I/O

I/O

WD, I/O

DS2316 Datasheet Revision 16.0

111

Package Pin Assignments

Table 53 • PQ208 (continued)

PQ208

Pin Number A42MX16 Function A42MX24 Function A42MX36 Function

95

NC

VCCI

I/O

96

I/O

97

I/O

98

VCCI

I/O

VCCI

I/O

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

I/O

WD, I/O

I/O

WD, I/O

I/O

SDO, I/O

I/O

SDO, TDO, I/O

I/O

SDO, TDO, I/O

I/O

GND

NC

I/O

GND

VCCA

I/O

GND

VCCA

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

TCK, I/O

LP

TCK, I/O

LP

VCCA

GND

VCCA

GND

VCCA

GND

DS2316 Datasheet Revision 16.0

112

Package Pin Assignments

Table 53 • PQ208 (continued)

PQ208

Pin Number A42MX16 Function A42MX24 Function A42MX36 Function

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

VCCI

VCCA

I/O

VCCI

VCCA

I/O

VCCI

VCCA

I/O

VCCA

I/O

VCCA

I/O

VCCA

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

SDI, I/O

I/O

SDI, I/O

I/O

SDI, I/O

I/O

WD, I/O

I/O

WD, I/O

I/O

VCCI

NC

VCCI

I/O

VCCI

I/O

NC

I/O

WD, I/O

DS2316 Datasheet Revision 16.0

113

Package Pin Assignments

Table 53 • PQ208 (continued)

PQ208

Pin Number A42MX16 Function A42MX24 Function A42MX36 Function

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

I/O

WD, I/O

I/O

WD, I/O

I/O

NC

I/O

QCLKD, I/O

I/O

WD, I/O

PRA, I/O

I/O

WD, I/O

PRA, I/O

I/O

PRA, I/O

I/O

CLKA, I/O

NC

CLKA, I/O

I/O

CLKA, I/O

I/O

NC

VCCI

VCCA

GND

I/O

VCCI

VCCA

GND

VCCA

GND

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

WD, I/O

I/O

WD, I/O

I/O

NC

I/O

NC

WD, I/O

I/O

WD, I/O

QCLKC, I/O

I/O

NC

I/O

NC

I/O

NC

I/O

VCCI

I/O

VCCI

WD, I/O

I/O

VCCI

WD, I/O

I/O

DS2316 Datasheet Revision 16.0

114

Package Pin Assignments

Table 53 • PQ208 (continued)

PQ208

Pin Number A42MX16 Function A42MX24 Function A42MX36 Function

206

207

208

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

Figure 45 • PQ240

240

1

•

240-Pin

PQFP

•

Note: This figure shows the 240-Pin PQFP Package top view.

Table 54 • PQ240

PQ240

Pin Number A42MX36 Function

1

I/O

2

DCLK, I/O

I/O

3

4

I/O

5

I/O

6

WD, I/O

VCCI

I/O

7

8

9

10

11

12

13

14

I/O

DS2316 Datasheet Revision 16.0

115

Package Pin Assignments

Table 54 • PQ240 (continued)

PQ240

Pin Number A42MX36 Function

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

QCLKC, I/O

I/O

WD, I/O

I/O

WD, I/O

I/O

PRB, I/O

I/O

CLKB, I/O

I/O

GND

VCCA

VCCI

I/O

CLKA, I/O

I/O

PRA, I/O

I/O

WD, I/O

I/O

QCLKD, I/O

I/O

WD, I/O

I/O

DS2316 Datasheet Revision 16.0

116

Package Pin Assignments

Table 54 • PQ240 (continued)

PQ240

Pin Number A42MX36 Function

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

VCCI

I/O

WD, I/O

I/O

SDI, I/O

I/O

VCCA

GND

I/O

VCCI

I/O

VCCA

I/O

VCCA

DS2316 Datasheet Revision 16.0

117

Package Pin Assignments

Table 54 • PQ240 (continued)

PQ240

Pin Number A42MX36 Function

89

VCCI

VCCA

LP

90

91

92

TCK, I/O

I/O

93

94

GND

I/O

95

96

I/O

97

I/O

98

I/O

99

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

I/O

VCCI

I/O

VCCA

GND

I/O

SDO, TDO, I/O

I/O

WD, I/O

DS2316 Datasheet Revision 16.0

118

Package Pin Assignments

Table 54 • PQ240 (continued)

PQ240

Pin Number A42MX36 Function

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

WD, I/O

I/O

VCCI

I/O

WD, I/O

I/O

QCLKB, I/O

I/O

WD, I/O

I/O

VCCI

VCCA

GND

I/O

WD, I/O

I/O

DS2316 Datasheet Revision 16.0

119

Package Pin Assignments

Table 54 • PQ240 (continued)

PQ240

Pin Number A42MX36 Function

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

WD, I/O

I/O

QCLKA, I/O

I/O

VCCI

I/O

WD, I/O

I/O

TDI, I/O

TMS, I/O

GND

VCCA

GND

I/O

VCCI

I/O

DS2316 Datasheet Revision 16.0

120

Package Pin Assignments

Table 54 • PQ240 (continued)

PQ240

Pin Number A42MX36 Function

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

I/O

VCCA

I/O

VCCA

VCCI

I/O

VCCA

I/O

VCCI

I/O

DS2316 Datasheet Revision 16.0

121

Package Pin Assignments

Table 54 • PQ240 (continued)

PQ240

Pin Number A42MX36 Function

237

238

239

240

GND

MODE

VCCA

GND

Figure 46 • VQ80

80

1

80-Pin

VQFP

Table 55 • VQ80

VQ80

Pin Number A40MX02 Function A40MX04 Function

1

I/O

NC

I/O

GND

I/O

GND

I/O

2

3

4

5

6

7

8

9

10

11

12

DS2316 Datasheet Revision 16.0

122

Package Pin Assignments

Table 55 • VQ80 (continued)

VQ80

Pin Number A40MX02 Function A40MX04 Function

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

VCC

I/O

NC

VCC

I/O

GND

I/O

VCC

I/O

NC

I/O

GND

I/O

VCC

I/O

VCC

I/O

GND

I/O

VCC

I/O

GND

I/O

DS2316 Datasheet Revision 16.0

123

Package Pin Assignments

Table 55 • VQ80 (continued)

VQ80

Pin Number A40MX02 Function A40MX04 Function

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

CLK, I/O

I/O

CLK, I/O

I/O

MODE

VCC

NC

MODE

VCC

I/O

NC

I/O

NC

I/O

SDI, I/O

DCLK, I/O

PRA, I/O

NC

SDI, I/O

DCLK, I/O

PRA, I/O

NC

PRB, I/O

I/O

PRB, I/O

I/O

GND

I/O

GND

I/O

VCC

I/O

VCC

I/O

DS2316 Datasheet Revision 16.0

124

Package Pin Assignments

Figure 47 • VQ100

100

1

100-Pin

VQFP

Table 56 • VQ100

VQ100

Pin Number A42MX09 Function A42MX16 Function

1

I/O

2

MODE

I/O

MODE

I/O

3

4

I/O

5

I/O

6

I/O

7

GND

I/O

GND

I/O

8

9

I/O

10

11

12

13

14

15

16

17

18

19

20

I/O

VCCA

VCCI

I/O

NC

VCCI

I/O

GND

DS2316 Datasheet Revision 16.0

125

Package Pin Assignments

Table 56 • VQ100 (continued)

VQ100

Pin Number A42MX09 Function A42MX16 Function

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

I/O

GND

I/O

GND

I/O

VCCA

I/O

VCCA

I/O

GND

I/O

GND

I/O

SDO, I/O

I/O

SDO, I/O

I/O

GND

I/O

GND

I/O

DS2316 Datasheet Revision 16.0

126

Package Pin Assignments

Table 56 • VQ100 (continued)

VQ100

Pin Number A42MX09 Function A42MX16 Function

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

I/O

LP

VCCA

VCCI

VCCA

I/O

VCCA

VCCI

VCCA

I/O

GND

I/O

GND

I/O

SDI, I/O

I/O

SDI, I/O

I/O

GND

I/O

GND

I/O

PRA, I/O

I/O

PRA, I/O

I/O

CLKA, I/O

VCCA

I/O

CLKA, I/O

VCCA

I/O

CLKB, I/O

I/O

CLKB, I/O

I/O

PRB, I/O

I/O

PRB, I/O

I/O

GND

DS2316 Datasheet Revision 16.0

127

Package Pin Assignments

Table 56 • VQ100 (continued)

VQ100

Pin Number A42MX09 Function A42MX16 Function

95

96

97

98

99

100

I/O

DCLK, I/O

Figure 48 • TQ176

176

1

176-Pin

TQFP

Table 57 • TQ176

TQ176

Pin Number A42MX09 Function A42MX16 Function A42MX24 Function

1

GND

MODE

I/O

GND

MODE

I/O

GND

MODE

I/O

2

3

4

I/O

5

I/O

6

I/O

7

I/O

8

NC

I/O

NC

I/O

9

I/O

10

11

12

NC

I/O

DS2316 Datasheet Revision 16.0

128

Package Pin Assignments

Table 57 • TQ176 (continued)

TQ176

Pin Number A42MX09 Function A42MX16 Function A42MX24 Function

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

NC

I/O

VCCA

I/O

VCCA

I/O

GND

NC

I/O

GND

I/O

GND

I/O

NC

GND

NC

VCCA

NC

VCCI

NC

I/O

GND

VCCI

VCCA

I/O

GND

VCCI

VCCA

I/O

VCCA

I/O

VCCA

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

GND

I/O

GND

I/O

GND

TMS, I/O

TDI, I/O

I/O

WD, I/O

DS2316 Datasheet Revision 16.0

129

Package Pin Assignments

Table 57 • TQ176 (continued)

TQ176

Pin Number A42MX09 Function A42MX16 Function A42MX24 Function

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

GND

VCCA

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

NC

I/O

VCCI

I/O

NC

I/O

GND

VCCA

I/O

NC

I/O

VCCI

I/O

WD, I/O

I/O

VCCI

I/O

WD, I/O

I/O

WD, I/O

I/O

GND

VCCA

WD, I/O

I/O

WD, I/O

I/O

VCCI

I/O

WD, I/O

I/O

DS2316 Datasheet Revision 16.0

130

Package Pin Assignments

Table 57 • TQ176 (continued)

TQ176

Pin Number A42MX09 Function A42MX16 Function A42MX24 Function

87

SDO, I/O

I/O

SDO, I/O

I/O

SDO, TDO, I/O

I/O

88

89

GND

I/O

GND

I/O

GND

I/O

90

91

I/O

92

I/O

93

I/O

94

I/O

95

I/O

96

NC

I/O

97

NC

I/O

98

I/O

99

I/O

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

I/O

NC

I/O

NC

I/O

GND

NC

GND

I/O

GND

I/O

NC

I/O

TCK, I/O

LP

VCCA

GND

VCCI

VCCA

NC

VCCA

GND

VCCI

VCCA

I/O

VCCA

GND

VCCI

VCCA

I/O

NC

I/O

NC

VCCA

I/O

VCCA

I/O

NC

I/O

DS2316 Datasheet Revision 16.0

131

Package Pin Assignments

Table 57 • TQ176 (continued)

TQ176

Pin Number A42MX09 Function A42MX16 Function A42MX24 Function

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

NC

I/O

NC

I/O

NC

I/O

GND

I/O

GND

I/O

GND

I/O

SDI, I/O

NC

SDI, I/O

I/O

SDI, I/O

I/O

WD, I/O

I/O

NC

VCCI

I/O

VCCI

I/O

NC

I/O

NC

I/O

WD, I/O

I/O

NC

I/O

NC

I/O

WD, I/O

PRA, I/O

I/O

NC

I/O

PRA, I/O

I/O

PRA, I/O

I/O

CLKA, I/O

VCCA

GND

I/O

CLKA, I/O

VCCA

GND

I/O

CLKA, I/O

VCCA

GND

I/O

CLKB, I/O

DS2316 Datasheet Revision 16.0

132

Package Pin Assignments

Table 57 • TQ176 (continued)

TQ176

Pin Number A42MX09 Function A42MX16 Function A42MX24 Function

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

I/O

PRB, I/O

NC

PRB, I/O

I/O

PRB, I/O

WD, I/O

I/O

NC

WD, I/O

I/O

NC

I/O

NC

I/O

NC

VCCI

I/O

VCCI

WD, I/O

I/O

NC

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

DCLK, I/O

I/O

Figure 49 • CQ208

208207206205204203202201200

164163162161160159158157

Pin #1

Index

1

2

3

4

5

6

7

8

156

155

154

153

152

151

150

149

A42MX36

208-Pin

CQFP

44

45

46

47

48

49

50

51

52

113

112

111

110

109

108

107

106

105

53 54 55 56 57 58 59 60 61

97 98 99 100101102103104

DS2316 Datasheet Revision 16.0

133

Package Pin Assignments

Table 58 • CQ208

CQ208

Pin Number A42MX36 Function

1

GND

VCCA

MODE

I/O

2

3

4

5

I/O

6

I/O

7

I/O

8

I/O

9

I/O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

I/O

VCCA

I/O

GND

I/O

GND

VCCI

VCCA

I/O

VCCA

I/O

DS2316 Datasheet Revision 16.0

134

Package Pin Assignments

Table 58 • CQ208 (continued)

CQ208

Pin Number A42MX36 Function

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

I/O

GND

TMS, I/O

TDI, I/O

I/O

WD, I/O

I/O

VCCI

I/O

QCLKA, I/O

WD, I/O

I/O

WD, I/O

I/O

DS2316 Datasheet Revision 16.0

135

Package Pin Assignments

Table 58 • CQ208 (continued)

CQ208

Pin Number A42MX36 Function

74

I/O

75

I/O

76

I/O

77

I/O

78

GND

VCCA

VCCI

I/O

79

80

81

82

I/O

83

I/O

84

I/O

85

WD, I/O

I/O

86

87

88

I/O

89

I/O

90

I/O

91

QCLKB, I/O

I/O

92

93

WD, I/O

I/O

94

95

96

I/O

97

I/O

98

VCCI

I/O

99

100

101

102

103

104

105

106

107

108

109

110

WD, I/O

I/O

TDO, I/O

I/O

GND

VCCA

I/O

DS2316 Datasheet Revision 16.0

136

Package Pin Assignments

Table 58 • CQ208 (continued)

CQ208

Pin Number A42MX36 Function

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

I/O

GND

I/O

TCK, I/O

LP

VCCA

GND

VCCI

VCCA

I/O

VCCA

I/O

DS2316 Datasheet Revision 16.0

137

Package Pin Assignments

Table 58 • CQ208 (continued)

CQ208

Pin Number A42MX36 Function

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

I/O

GND

I/O

GND

I/O

SDI, I/O

I/O

WD, I/O

I/O

VCCI

I/O

WD, I/O

I/O

QCLKD, I/O

I/O

WD, I/O

PRA, I/O

I/O

CLKA, I/O

I/O

VCCI

VCCA

GND

DS2316 Datasheet Revision 16.0

138

Package Pin Assignments

Table 58 • CQ208 (continued)

CQ208

Pin Number A42MX36 Function

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

I/O

CLKB, I/O

I/O

PRB, I/O

I/O

WD, I/O

I/O

WD, I/O

QCLKC, I/O

I/O

VCCI

WD, I/O

I/O

DCLK, I/O

I/O

DS2316 Datasheet Revision 16.0

139

Package Pin Assignments

Figure 50 • CQ256

256255254253252251250249248

200199198197196195194193

Pin #1

Index

1

2

3

4

5

6

7

8

192

191

190

189

188

187

186

185

A42MX36

256-Pin

CQFP

56

57

58

59

60

61

62

63

64

137

136

135

134

133

132

131

130

129

65 66 67 68 69 70 71 72 73

121122123124125126127128

Table 59 • CQ256

CQ256

Pin Number A42MX36 Function

1

NC

GND

I/O

GND

I/O

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

DS2316 Datasheet Revision 16.0

140

Package Pin Assignments

Table 59 • CQ256 (continued)

CQ256

Pin Number A42MX36 Function

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

I/O

VCCA

I/O

VCCA

VCCI

GND

VCCA

LP

TCK, I/O

I/O

GND

I/O

GND

I/O

DS2316 Datasheet Revision 16.0

141

Package Pin Assignments

Table 59 • CQ256 (continued)

CQ256

Pin Number A42MX36 Function

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

I/O

VCCA

GND

NC

I/O

SDO, TDO, I/O

I/O

WD, I/O

I/O

VCCI

I/O

WD, I/O

GND

WD, I/O

I/O

QCLKB, I/O

I/O

WD, I/O

I/O

VCCI

DS2316 Datasheet Revision 16.0

142

Package Pin Assignments

Table 59 • CQ256 (continued)

CQ256

Pin Number A42MX36 Function

96

VCCA

GND

I/O

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

I/O

WD, I/O

I/O

WD, I/O

I/O

QCLKA, I/O

I/O

GND

I/O

VCCI

I/O

WD, I/O

I/O

GND

NC

GND

I/O

DS2316 Datasheet Revision 16.0

143

Package Pin Assignments

Table 59 • CQ256 (continued)

CQ256

Pin Number A42MX36 Function

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

I/O

GND

I/O

VCCA

I/O

VCCA

VCCI

GND

I/O

GND

I/O

DS2316 Datasheet Revision 16.0

144

Package Pin Assignments

Table 59 • CQ256 (continued)

CQ256

Pin Number A42MX36 Function

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

VCCA

I/O

GND

I/O

MODE

VCCA

GND

NC

I/O

DCLK, I/O

I/O

WD, I/O

VCCI

I/O

GND

DS2316 Datasheet Revision 16.0

145

Package Pin Assignments

Table 59 • CQ256 (continued)

CQ256

Pin Number A42MX36 Function

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

I/O

QCLKC, I/O

I/O

WD, I/O

I/O

WD, I/O

I/O

PRB, I/O

I/O

CLKB, I/O

I/O

GND

VCCA

VCCI

I/O

CLKA, I/O

I/O

PRA, I/O

I/O

WD, I/O

I/O

QCLKD, I/O

I/O

WD, I/O

GND

DS2316 Datasheet Revision 16.0

146

Package Pin Assignments

Table 59 • CQ256 (continued)

CQ256

Pin Number A42MX36 Function

244

245

246

247

248

249

250

251

252

253

254

255

256

WD, I/O

I/O

VCCI

I/O

WD, I/O

I/O

SDI, I/O

I/O

GND

NC

Figure 51 • BG272

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

A

B

C

D

E

F

G

H

J

272-Pin PBGA

K

L

M

N

P

R

T

U

V

W

Y

Table 60 • BG272

BG272

Pin Number A42MX36 Function

A1

A2

A3

A4

A5

GND

I/O

WD, I/O

I/O

DS2316 Datasheet Revision 16.0

147

Package Pin Assignments

Table 60 • BG272 (continued)

BG272

Pin Number A42MX36 Function

A6

I/O

A7

WD, I/O

I/O

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

B1

I/O

CLKA

I/O

WD, I/O

I/O

GND

DCLK, I/O

I/O

B2

B3

B4

B5

I/O

B6

I/O

B7

WD, I/O

I/O

B8

B9

PRB, I/O

I/O

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

C1

I/O

WD, I/O

I/O

WD, I/O

I/O

WD, I/O

I/O

GND

I/O

C2

MODE

DS2316 Datasheet Revision 16.0

148

Package Pin Assignments

Table 60 • BG272 (continued)

BG272

Pin Number A42MX36 Function

C3

GND

I/O

C4

C5

WD, I/O

I/O

C6

C7

QCLKC, I/O

I/O

C8

C9

I/O

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

D1

CLKB

PRA, I/O

WD, I/O

I/O

QCLKD, I/O

I/O

WD, I/O

SDI, I/O

I/O

D2

I/O

D3

I/O

D4

I/O

D5

VCCI

I/O

D6

D7

I/O

D8

VCCA

WD, I/O

VCCI

I/O

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

VCCI

I/O

VCCI

I/O

VCCA

GND

I/O

DS2316 Datasheet Revision 16.0

149

Package Pin Assignments

Table 60 • BG272 (continued)

BG272

Pin Number A42MX36 Function

D20

E1

I/O

E2

I/O

E3

I/O

E4

VCCA

VCCI

I/O

E17

E18

E19

E20

F1

I/O

F2

I/O

F3

I/O

F4

VCCI

I/O

F17

F18

F19

F20

G1

I/O

G2

I/O

G3

I/O

G4

VCCI

I/O

G17

G18

G19

G20

H1

I/O

H2

I/O

H3

I/O

H4

VCCA

I/O

H17

H18

H19

H20

J1

I/O

J2

I/O

J3

I/O

J4

VCCI

DS2316 Datasheet Revision 16.0

150

Package Pin Assignments

Table 60 • BG272 (continued)

BG272

Pin Number A42MX36 Function

J9

GND

VCCA

I/O

J10

J11

J12

J17

J18

J19

J20

K1

I/O

K2

I/O

K3

I/O

K4

VCCI

GND

I/O

K9

K10

K11

K12

K17

K18

K19

K20

L1

VCCA

LP

I/O

L2

I/O

L3

VCCA

GND

VCCI

I/O

L4

L9

L10

L11

L12

L17

L18

L19

L20

M1

M2

M3

M4

M9

I/O

TCK, I/O

I/O

VCCI

GND

DS2316 Datasheet Revision 16.0

151

Package Pin Assignments

Table 60 • BG272 (continued)

BG272

Pin Number A42MX36 Function

M10

M11

M12

M17

M18

M19

M20

N1

GND

I/O

N2

I/O

N3

I/O

N4

VCCI

I/O

N17

N18

N19

N20

P1

I/O

P2

I/O

P3

I/O

P4

VCCA

I/O

P17

P18

P19

P20

R1

I/O

R2

I/O

R3

I/O

R4

VCCI

I/O

R17

R18

R19

R20

T1

I/O

T2

I/O

T3

I/O

T4

I/O

T17

T18

VCCA

I/O

DS2316 Datasheet Revision 16.0

152

Package Pin Assignments

Table 60 • BG272 (continued)

BG272

Pin Number A42MX36 Function

T19

T20

U1

I/O

U2

I/O

U3

I/O

U4

I/O

U5

VCCI

WD, I/O

I/O

U6

U7

U8

I/O

U9

WD, I/O

VCCA

VCCI

I/O

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

V1

I/O

QCLKB, I/O

I/O

VCCI

I/O

GND

I/O

V2

I/O

V3

GND

I/O

V4

V5

V6

I/O

V7

I/O

V8

WD, I/O

I/O

V9

V10

V11

V12

V13

V14

V15

I/O

WD, I/O

I/O

WD, I/O

DS2316 Datasheet Revision 16.0

153

Package Pin Assignments

Table 60 • BG272 (continued)

BG272

Pin Number A42MX36 Function

V16

V17

V18

V19

V20

W1

I/O

SDO, TDO, I/O

I/O

GND

I/O

W2

W3

W4

TMS, I/O

I/O

W5

W6

I/O

W7

I/O

W8

WD, I/O

I/O

W9

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

Y1

I/O

WD, I/O

I/O

WD, I/O

I/O

WD, I/O

GND

I/O

Y2

Y3

Y4

TDI, I/O

WD, I/O

I/O

Y5

Y6

Y7

QCLKA, I/O

I/O

Y8

Y9

I/O

Y10

Y11

Y12

I/O

DS2316 Datasheet Revision 16.0

154

Package Pin Assignments

Table 60 • BG272 (continued)

BG272

Pin Number A42MX36 Function

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

I/O

WD, I/O

GND

Figure 52 • PG132

1

2

3

4

5

6

7

8

9 10 11 12 13

A

B

C

D

B

C

D

E

F

E

F

132-Pin

CPGA

G

H

J

G

H

J

K

L

K

L

M

N

M

N

1

2

3

4

5

6

7

8

9 10 11 12 13

Orientation Pin

Table 61 • PG132

PG132

Pin Number A42MX09 Function

–

PMPOUT

I/O

B2

A1

B1

D3

C2

C1

D2

D1

E2

E1

F3

MODE

I/O

DS2316 Datasheet Revision 16.0

155

Package Pin Assignments

Table 61 • PG132 (continued)

PG132

Pin Number A42MX09 Function

F2

F1

G1

G4

H1

H2

H3

H4

J1

I/O

VSV

I/O

BININ

BINOUT

I/O

K1

L1

K2

M1

K3

L2

N1

L3

M2

N2

M3

L4

N3

M4

N4

M5

K6

N5

N6

L6

M6

M7

N7

N8

M8

L8

K8

N9

DS2316 Datasheet Revision 16.0

156

Package Pin Assignments

Table 61 • PG132 (continued)

PG132

Pin Number A42MX09 Function

N10

M10

N11

L10

M11

N12

M12

L11

I/O

SDO

I/O

VKS

VPP

N13

M13

K11

L12

L13

K13

H10

J12

J13

H11

H12

H13

G13

DS2316 Datasheet Revision 16.0

157

Package Pin Assignments

Table 61 • PG132 (continued)

PG132

Pin Number A42MX09 Function

G12

F13

F12

F11

F10

E13

D13

D12

C13

B13

D11

C12

A13

C11

B12

B11

C10

A12

A11

B10

D8

VSV

I/O

SDI

I/O

A10

C8

I/O

A9

I/O

B8

PRBA

I/O

A8

B7

CLKA

I/O

A7

B6

CLKB

I/O

A6

C6

PRBB

I/O

A5

D6

I/O

A4

I/O

B4

I/O

A3

I/O

C4

I/O

DS2316 Datasheet Revision 16.0

158

Package Pin Assignments

Table 61 • PG132 (continued)

PG132

Pin Number A42MX09 Function

B3

A2

C3

B5

E12

J2

I/O

DCLK

GNDA

GNDI

GNDQ

VCCA

VCCI

M9

B9

C5

E11

F4

J3

J11

L5

L9

C9

E3

K12

D7

G3

G10

L7

C7

G2

G11

K7

DS2316 Datasheet Revision 16.0

159

Package Pin Assignments

Figure 53 • CQ172

Table 62 • CQ172

CQ172

Pin Number A42MX16 Function

1

MODE

I/O

2

3

I/O

4

I/O

5

I/O

6

I/O

7

GND

I/O

8

9

I/O

10

11

12

13

14

15

16

17

18

19

20

I/O

VCC

I/O

GND

I/O

DS2316 Datasheet Revision 16.0

160

Package Pin Assignments

Table 62 • CQ172 (continued)

CQ172

Pin Number A42MX16 Function

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

I/O

GND

VCCI

VSV

I/O

VCC

I/O

GND

I/O

GND

I/O

BININ

BINOUT

I/O

VCCI

I/O

GND

I/O

DS2316 Datasheet Revision 16.0

161

Package Pin Assignments

Table 62 • CQ172 (continued)

CQ172

Pin Number A42MX16 Function

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

I/O

GND

VCC

I/O

GND

I/O

VCCI

I/O

SDO

I/O

DS2316 Datasheet Revision 16.0

162

Package Pin Assignments

Table 62 • CQ172 (continued)

CQ172

Pin Number A42MX16 Function

95

I/O

96

I/O

97

I/O

98

GND

I/O

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

I/O

GND

I/O

VKS

VPP

GND

VCCI

VSV

I/O

VCC

I/O

GND

I/O

GNDI

I/O

SDI

DS2316 Datasheet Revision 16.0

163

Package Pin Assignments

Table 62 • CQ172 (continued)

CQ172

Pin Number A42MX16 Function

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

I/O

VCCI

I/O

GND

I/O

PROBA

I/O

CLKA

VCC

GND

I/O

CLKB

I/O

PROBB

I/O

GND

I/O

VCCI

I/O

DS2316 Datasheet Revision 16.0

164

Package Pin Assignments

Table 62 • CQ172 (continued)

CQ172

Pin Number A42MX16 Function

169

170

171

I/O

DCLK

DS2316 Datasheet Revision 16.0

165


型号：	A40MX04-3PGG100M
厂家：	Microsemi
描述：	40MX and 42MX FPGA
文件：	总173页 (文件大小：2480K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A40MX04-3PGG100M [MICROSEMI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E