AGLN020V5-UCG100_技术文档

1 – IGLOO nano Device Overview

General Description

The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a

single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced

features.

The Flash*Freeze technology used in IGLOO nano devices enables entering and exiting an ultra-low

power mode that consumes nanoPower while retaining SRAM and register data. Flash*Freeze

technology simplifies power management through I/O and clock management with rapid recovery to

operation mode.

The Low Power Active capability (static idle) allows for ultra-low power consumption while the IGLOO

nano device is completely functional in the system. This allows the IGLOO nano device to control system

power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming

minimal power.

Nonvolatile flash technology gives IGLOO nano devices the advantage of being a secure, low power,

single-chip solution that is Instant On. The IGLOO nano device is reprogrammable and offers time-to-

market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

IGLOO nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGLN030 and smaller

devices have no PLL or RAM support. IGLOO nano devices have up to 250 k system gates, supported

with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os.

IGLOO nano devices increase the breadth of the IGLOO product line by adding new features and

packages for greater customer value in high volume consumer, portable, and battery-backed markets.

Features such as smaller footprint packages designed with two-layer PCBs in mind, power consumption

measured in nanoPower, Schmitt trigger, and bus hold (hold previous I/O state in Flash*Freeze mode)

functionality make these devices ideal for deployment in applications that require high levels of flexibility

and low cost.

Flash*Freeze Technology

The IGLOO nano device offers unique Flash*Freeze technology, allowing the device to enter and exit

ultra-low power Flash*Freeze mode. IGLOO nano devices do not need additional components to turn off

I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze

technology is combined with in-system programmability, which enables users to quickly and easily

upgrade and update their designs in the final stages of manufacturing or in the field. The ability of IGLOO

nano V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction in

power consumption, thus achieving the lowest total system power.

During Flash*Freeze mode, each I/O can be set to the following configurations: hold previous state,

tristate, HIGH, or LOW.

The availability of low power modes, combined with reprogrammability, a single-chip and single-voltage

solution, and small-footprint packages make IGLOO nano devices the best fit for portable electronics.

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IGLOO nano Device Overview

Flash Advantages

Low Power

Flash-based IGLOO nano devices exhibit power characteristics similar to those of an ASIC, making them

an ideal choice for power-sensitive applications. IGLOO nano devices have only a very limited power-on

current surge and no high-current transition period, both of which occur on many FPGAs.

IGLOO nano devices also have low dynamic power consumption to further maximize power savings;

power is reduced even further by the use of a 1.2 V core voltage.

Low dynamic power consumption, combined with low static power consumption and Flash*Freeze

technology, gives the IGLOO nano device the lowest total system power offered by any FPGA.

Security

Nonvolatile, flash-based IGLOO nano devices do not require a boot PROM, so there is no vulnerable

external bitstream that can be easily copied. IGLOO nano devices incorporate FlashLock, which provides

a unique combination of reprogrammability and design security without external overhead, advantages

that only an FPGA with nonvolatile flash programming can offer.

IGLOO nano devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest

level of security in the FPGA industry for programmed intellectual property and configuration data. In

addition, all FlashROM data in IGLOO nano devices can be encrypted prior to loading, using the

industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the

National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard.

IGLOO nano devices have a built-in AES decryption engine and a flash-based AES key that make them

the most comprehensive programmable logic device security solution available today. IGLOO nano

devices with AES-based security provide a high level of protection for remote field updates over public

networks such as the Internet, and are designed to ensure that valuable IP remains out of the hands of

system overbuilders, system cloners, and IP thieves.

Security, built into the FPGA fabric, is an inherent component of IGLOO nano devices. The flash cells are

located beneath seven metal layers, and many device design and layout techniques have been used to

make invasive attacks extremely difficult. IGLOO nano devices, with FlashLock and AES security, are

unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected

with industry-standard security, making remote ISP possible. An IGLOO nano device provides the best

available security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the

configuration data is an inherent part of the FPGA structure, and no external configuration data needs to

be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO nano

FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load

device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and

system reliability.

Instant On

Microsemi flash-based IGLOO nano devices support Level 0 of the Instant On classification standard.

This feature helps in system component initialization, execution of critical tasks before the processor

wakes up, setup and configuration of memory blocks, clock generation, and bus activity management.

The Instant On feature of flash-based IGLOO nano devices greatly simplifies total system design and

reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition,

glitches and brownouts in system power will not corrupt the IGLOO nano device's flash configuration,

and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored.

This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor,

brownout detection, and clock generator devices from the PCB design. Flash-based IGLOO nano

devices simplify total system design and reduce cost and design risk while increasing system reliability

and improving system initialization time.

IGLOO nano flash FPGAs enable the user to quickly enter and exit Flash*Freeze mode. This is done

almost instantly (within 1 µs) and the device retains configuration and data in registers and RAM. Unlike

SRAM-based FPGAs, the device does not need to reload configuration and design state from external

memory components; instead it retains all necessary information to resume operation immediately.

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IGLOO nano Low Power Flash FPGAs

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike

SRAM-based FPGAs, flash-based IGLOO nano devices allow all functionality to be Instant On; no

external boot PROM is required. On-board security mechanisms prevent access to all the programming

information and enable secure remote updates of the FPGA logic.

Designers can perform secure remote in-system reprogramming to support future design iterations and

field upgrades with confidence that valuable intellectual property cannot be compromised or copied.

Secure ISP can be performed using the industry-standard AES algorithm. The IGLOO nano device

architecture mitigates the need for ASIC migration at higher user volumes. This makes IGLOO nano

devices cost-effective ASIC replacement solutions, especially for applications in the consumer,

networking/communications, computing, and avionics markets.

With a variety of devices under $1, IGLOO nano FPGAs enable cost-effective implementation of

programmable logic and quick time to market.

Firm-Error Immunity

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike

a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These

errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a

complete system failure. Firm errors do not exist in the configuration memory of IGLOO nano flash-based

FPGAs. Once it is programmed, the flash cell configuration element of IGLOO nano FPGAs cannot be

altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in

the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and

correction (EDAC) circuitry built into the FPGA fabric.

Advanced Flash Technology

The IGLOO nano device offers many benefits, including nonvolatility and reprogrammability, through an

advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design

techniques are used to implement logic and control functions. The combination of fine granularity,

enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization

without compromising device routability or performance. Logic functions within the device are

interconnected through a four-level routing hierarchy.

IGLOO nano FPGAs utilize design and process techniques to minimize power consumption in all modes

of operation.

Advanced Architecture

The proprietary IGLOO nano architecture provides granularity comparable to standard-cell ASICs. The

IGLOO nano device consists of five distinct and programmable architectural features (Figure 1-3 on

page 1-5 to Figure 1-4 on page 1-5):

•

Flash*Freeze technology

FPGA VersaTiles

Dedicated FlashROM

Dedicated SRAM/FIFO memory^†

Extensive CCCs and PLLs^†

Advanced I/O structure

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic

function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch

interconnections. The versatility of the IGLOO nano core tile as either a three-input lookup table (LUT)

equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile

capability is unique to the ProASIC^®family of third-generation-architecture flash FPGAs. VersaTiles are

connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the

device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is

possible for virtually any design.

† The AGLN030 and smaller devices do not support PLL or SRAM.

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IGLOO nano Device Overview

Bank 1*

I/Os

VersaTile

CCC-GL

User Nonvolatile

FlashROM

Flash*Freeze

Technology

Charge

Pumps

Bank 1

Note: *Bank 0 for the AGLN030 device

Figure 1-1 • IGLOO Device Architecture Overview with Two I/O Banks and No RAM (AGLN010 and AGLN030)

Bank 1

I/Os

VersaTile

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

CCC-GL

Bank 1

Figure 1-2 • IGLOO Device Architecture Overview with Three I/O Banks and No RAM (AGLN015 and

AGLN020)

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IGLOO nano Low Power Flash FPGAs

.

Bank 0

CCC

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

I/Os

VersaTile

ISP AES

Decryption

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

Bank 1

Figure 1-3 • IGLOO Device Architecture Overview with Two I/O Banks (AGLN060, AGLN125)

Bank 0

CCC

RAM Block

4,608-Bit Dual-Port

SRAM or FIFO Block

I/Os

VersaTile

ISP AES

Decryption

User Nonvolatile

FlashRom

Flash*Freeze

Technology

Charge

Pumps

Bank 2

Figure 1-4 • IGLOO Device Architecture Overview with Four I/O Banks (AGLN250)

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IGLOO nano Device Overview

Flash*Freeze Technology

The IGLOO nano device has an ultra-low power static mode, called Flash*Freeze mode, which retains all

SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology

enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the

Flash*Freeze pin while all power supplies are kept at their original values. I/Os, global I/Os, and clocks

can still be driven and can be toggling without impact on power consumption, and the device retains all

core registers, SRAM information, and I/O states. I/Os can be individually configured to either hold their

previous state or be tristated during Flash*Freeze mode.

Alternatively, I/Os can be set to a specific state using weak pull-up or pull-down I/O attribute

configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device

consumes as little as 2 µW in this mode.

Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the power

management of the device.

The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide

when it is safe to transition to this mode. Refer to Figure 1-5 for an illustration of entering/exiting

Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode

usage is not planned.

IGLOO nano

FPGA

Flash*Freeze

Mode Control

Flash*Freeze Pin

Figure 1-5 • IGLOO nano Flash*Freeze Mode

VersaTiles

The IGLOO nano core consists of VersaTiles, which have been enhanced beyond the ProASIC^PLUS®

core tiles. The IGLOO nano VersaTile supports the following:

•

All 3-input logic functions—LUT-3 equivalent

Latch with clear or set

D-flip-flop with clear or set

Enable D-flip-flop with clear or set

Refer to Figure 1-6 for VersaTile configurations.

Enable D-Flip-Flop with Clear or Set

D-Flip-Flop with Clear or Set

LUT-3 Equivalent

X1

Data

Y

Data

CLK

CLR

Y

X2

X3

LUT-3

Y

D-FF

CLK

D-FF

Enable

CLR

Figure 1-6 • VersaTile Configurations

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IGLOO nano Low Power Flash FPGAs

User Nonvolatile FlashROM

IGLOO nano devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can

be used in diverse system applications:

•

Internet protocol addressing (wireless or fixed)

System calibration settings

Device serialization and/or inventory control

Subscription-based business models (for example, set-top boxes)

Secure key storage for secure communications algorithms

Asset management/tracking

Date stamping

Version management

The FlashROM is written using the standard IGLOO nano IEEE 1532 JTAG programming interface. The

core can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks (except in the AGLN030 and smaller devices), as

in security keys stored in the FlashROM for a user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be read

back either through the JTAG programming interface or via direct FPGA core addressing. Note that the

FlashROM can only be programmed from the JTAG interface and cannot be programmed from the

internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte

basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks

and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the

FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM

address define the byte.

The IGLOO nano development software solutions, Libero^®System-on-Chip (SoC) and Designer, have

extensive support for the FlashROM. One such feature is auto-generation of sequential programming

files for applications requiring a unique serial number in each part. Another feature enables the inclusion

of static data for system version control. Data for the FlashROM can be generated quickly and easily

using Microsemi Libero SoC and Designer software tools. Comprehensive programming file support is

also included to allow for easy programming of large numbers of parts with differing FlashROM contents.

SRAM and FIFO

IGLOO nano devices (except the AGLN030 and smaller devices) have embedded SRAM blocks along

their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available

memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have

independent read and write ports that can be configured with different bit widths on each port. For

example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM

blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro

(except in the AGLN030 and smaller devices).

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM

block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width

and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and

Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control

unit contains the counters necessary for generation of the read and write address pointers. The

embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

Higher density IGLOO nano devices using either the two I/O bank or four I/O bank architectures provide

designers with very flexible clock conditioning capabilities. AGLN060, AGLN125, and AGLN250 contain

six CCCs. One CCC (center west side) has a PLL. The AGLN030 and smaller devices use different

CCCs in their architecture (CCC-GL). These CCC-GLs contain a global MUX but do not have any PLLs

or programmable delays.

For devices using the six CCC block architecture, these are located at the four corners and the centers of

the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east CCC allow

simple clock delay operations as well as clock spine access.

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IGLOO nano Device Overview

The inputs of the six CCC blocks are accessible from the FPGA core or from dedicated connections to

the CCC block, which are located near the CCC.

The CCC block has these key features:

•

Wide input frequency range (f_{IN_CCC}) = 1.5 MHz up to 250 MHz

Output frequency range (f_{OUT_CCC}) = 0.75 MHz up to 250 MHz

2 programmable delay types for clock skew minimization

Clock frequency synthesis (for PLL only)

Additional CCC specifications:

•

Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider

configuration (for PLL only).

•

Output duty cycle = 50% ± 1.5% or better (for PLL only)

Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global

network used (for PLL only)

•

Maximum acquisition time is 300 µs (for PLL only)

Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only)

Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /

f

_{OUT_CCC}(for PLL only)

Global Clocking

IGLOO nano devices have extensive support for multiple clocking domains. In addition to the CCC and

PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant

global networks. The VersaNets can be driven by the CCC or directly accessed from the core via

multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid

distribution of high-fanout nets.

I/Os with Advanced I/O Standards

IGLOO nano FPGAs feature a flexible I/O structure, supporting a range of voltages (1.2 V, 1.2 V wide

range, 1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V).

The I/Os are organized into banks with two, three, or four banks per device. The configuration of these

banks determines the I/O standards supported.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of various single-data-rate applications for all versions of nano devices and double-data-

rate applications for the AGLN060, AGLN125, and AGLN250 devices.

IGLOO nano devices support LVTTL and LVCMOS I/O standards, are hot-swappable, and support cold-

sparing and Schmitt trigger.

Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card

in a powered-up system.

Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed

when the system is powered up, while the component itself is powered down, or when power supplies

are floating.

Wide Range I/O Support

IGLOO nano devices support JEDEC-defined wide range I/O operation. IGLOO nano devices support

both the JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of

2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to

1.575 V.

Wider I/O range means designers can eliminate power supplies or power conditioning components from

the board or move to less costly components with greater tolerances. Wide range eases I/O bank

management and provides enhanced protection from system voltage spikes, while providing the flexibility

to easily run custom voltage applications.

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Revision 17

IGLOO nano Low Power Flash FPGAs

Specifying I/O States During Programming

You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for

PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.

Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have

limited display of Pin Numbers only.

1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during

programming.

2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator

window appears.

3. Click the Specify I/O States During Programming button to display the Specify I/O States During

Programming dialog box.

4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.

Select the I/Os you wish to modify (Figure 1-7 on page 1-9).

5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings

for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state

settings:

1 – I/O is set to drive out logic High

0 – I/O is set to drive out logic Low

Last Known State – I/O is set to the last value that was driven out prior to entering the

programming mode, and then held at that value during programming

Z -Tri-State: I/O is tristated

Figure 1-7 • I/O States During Programming Window

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IGLOO nano Device Overview

6. Click OK to return to the FlashPoint – Programming File Generator window.

Note: I/O States During programming are saved to the ADB and resulting programming files after

completing programming file generation.

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Revision 17

2 – IGLOO nano DC and Switching Characteristics

General Specifications

The Z feature grade does not support the enhanced nano features of Schmitt trigger input, Flash*Freeze

bus hold (hold previous I/O state in Flash*Freeze mode), cold-sparing, and hot-swap I/O capability. Refer

to "IGLOO nano Ordering Information" on page III for more information.

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any

other conditions beyond those listed under the Recommended Operating Conditions specified in

Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol

VCC

Parameter

DC core supply voltage

Limits

–0.3 to 1.65

–0.3 to 3.75

–0.3 to 1.65

–0.3 to 3.75

–0.3 V to 3.6 V

–65 to +150

+125

Units

V

VJTAG

VPUMP

VCCPLL

VCCI

JTAG DC voltage

V

Programming voltage

Analog power supply (PLL)

DC I/O buffer supply voltage

I/O input voltage

V

VI¹

V

2

T_STG

Storage temperature

Junction temperature

°C

2

T_J

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may

undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.

2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating

limits, refer to Table 2-2 on page 2-2.

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IGLOO nano DC and Switching Characteristics

Table 2-2 • Recommended Operating Conditions ¹

Extended

Symbol

T_J

Parameter

Commercial

Industrial

–40 to +100²

1.425 to 1.575

1.14 to 1.575

1.4 to 3.6

Units

°C

V

Junction temperature

–20 to + 85²

1.425 to 1.575

1.14 to 1.575

1.4 to 3.6

VCC

1.5 V DC core supply voltage³

1.2 V–1.5 V wide range core voltage^4,5

JTAG DC voltage

V

VJTAG

V

VPUMP ⁶Programming voltage Programming mode

3.15 to 3.45

0 to 3.6

3.15 to 3.45

0 to 3.6

V

Operation

V

VCCPLL⁷Analog power supply 1.5 V DC core supply voltage³

1.425 to 1.575

1.14 to 1.575

1.425 to 1.575

1.14 to 1.575

V

(PLL)

1.2 V–1.5 V wide range core

V

supply voltage⁴

VCCI and 1.2 V DC supply voltage ⁴

1.14 to 1.26

1.14 to 1.575

1.425 to 1.575

1.7 to 1.9

1.14 to 1.26

1.14 to 1.575

1.425 to 1.575

1.7 to 1.9

V

VMV ^8,9

1.2 V DC wide range supply voltage ⁴

1.5 V DC supply voltage

1.8 V DC supply voltage

2.5 V DC supply voltage

3.3 V DC supply voltage

3.3 V DC wide range supply voltage ¹⁰

Notes:

2.3 to 2.7

3.0 to 3.6

2.7 to 3.6

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. Default Junction Temperature Range in the Libero SoC software is set to 0°C to +70°C for commercial, and -40°C to

+85°C for industrial. To ensure targeted reliability standards are met across the full range of junction temperatures,

Microsemi recommends using custom settings for temperature range before running timing and power analysis tools.

For more information regarding custom settings, refer to the New Project Dialog Box in the Libero Online Help.

®

3. For IGLOO nano V5 devices

4. For IGLOO nano V2 devices only, operating at VCCI VCC

5. IGLOO nano V5 devices can be programmed with the VCC core voltage at 1.5 V only. IGLOO nano V2 devices can be

programmed with the VCC core voltage at 1.2 V (with FlashPro4 only) or 1.5 V. If you are using FlashPro3 and want to

do in-system programming using 1.2 V, please contact the factory.

6.

V

can be left floating during operation (not programming mode).

PUMP

7. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions" chapter for further information.

8. VMV pins must be connected to the corresponding VCCI pins. See the Pin Descriptions chapter of the IGLOO nano

FPGA Fabric User’s Guide for further information.

9. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O

standard are given in Table 2-21 on page 2-19. VCCI should be at the same voltage within a given I/O bank.

10. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.

Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature¹

Product

Grade

Programming

Cycles

Program Retention

Maximum Storage

Maximum Operating Junction

Temperature T_J(°C) ²

(biased/unbiased) Temperature T_STG(°C) ²

Commercial

Industrial

Notes:

500

20 years

110

100

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating

conditions and absolute limits.

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IGLOO nano Low Power Flash FPGAs

Table 2-4 • Overshoot and Undershoot Limits ¹

Average VCCI–GND Overshoot or

Undershoot Duration

Maximum Overshoot/

Undershoot²

VCCI

as a Percentage of Clock Cycle²

2.7 V or less

10%

5%

1.4 V

1.49 V

1.1 V

3 V

10%

5%

1.19 V

0.79 V

0.88 V

0.45 V

0.54 V

3.3 V

3.6 V

Notes:

10%

5%

10%

5%

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the

maximum overshoot/undershoot has to be reduced by 0.15 V.

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every IGLOO nano device. These circuits

ensure easy transition from the powered-off state to the powered-up state of the device. The many

different supplies can power up in any sequence with minimized current spikes or surges. In addition, the

I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1

on page 2-4.

There are five regions to consider during power-up.

IGLOO nano I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 and Figure 2-2 on

page 2-5).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V

Ramping down (V5 devices): 0.5 V < trip_point_down < 1.1 V

Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V

Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V

VCC Trip Point:

Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V

Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V

Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V

Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically

built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

•

During programming, I/Os become tristated and weakly pulled up to VCCI.

JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

Revision 17

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IGLOO nano DC and Switching Characteristics

PLL Behavior at Brownout Condition

Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-

up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout

activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25

V for V5 devices, and 0.75 V ± 0.2 V for V2 devices), the PLL output lock signal goes LOW and/or the

output clock is lost. Refer to the "Brownout Voltage" section in the "Power-Up/-Down Behavior of Low

Power Flash Devices" chapter of the IGLOO nano FPGA Fabric User’s Guide for information on clock

and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input buffer activation

To make sure the transition from input buffers to output buffers is clean, ensure that there is no path

longer than 100 ns from input buffer to output buffer in your design.

VCC = VCCI + VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCC

VCC = 1.575 V

Region 4: I/O

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 1: I/O Buffers are OFF

buffers are ON.

I/Os are functional

I/Os meet the entire datasheet

but slower because VCCI

and timer specifications for

is below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

speed, VIH / VIL , VOH / VOL , etc.

buffers do not meet VOH/VOL levels.

VCC = 1.425 V

Region 2: I/O buffers are ON.

I/Os are functional but slower because

VCCI / VCC are below specification. For the

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

same reason, input buffers do not meet

VIH/VIL levels, and output buffers to not

meet VOH / VOL levels.

Activation trip point:

V_a= 0.85 V ± 0.25 V

Deactivation trip point:

V_d= 0.75 V ± 0.25 V

Region 1: I/O buffers are OFF

V_CCI

Activation trip point:

Min VCCI datasheet specification

V_a= 0.9 V ± 0.3 V

Deactivation trip point:

V_d= 0.8 V ± 0.3 V

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

2-4

Revision 17

IGLOO nano Low Power Flash FPGAs

VCC = VCCI + VT

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCC

V

= 1.575 V

CC

Region 5: I/O buffers are ON

and power supplies are within

specification.

Region 4: I/O

Region 1: I/O Buffers are OFF

buffers are ON.

I/Os are functional

I/Os meet the entire datasheet

but slower because V_CCI

and timer specifications for

speed, VIH / VIL , VOH / VOL , etc.

is below specification. For the

same reason, input buffers do not

meet VIH / VIL levels, and output

buffers do not meet VOH / VOL levels.

VCC = 1.14 V

Region 2: I/O buffers are ON.

I/Os are functional but slower because

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCCI / VCC are below specification. For the

same reason, input buffers do not meet

VIH / VIL levels, and output buffers do not

meet VOH/VOL levels.

Activation trip point:

V = 0.85 V ± 0.2 V

a

Deactivation trip point:

Region 1: I/O buffers are OFF

V

= 0.75 V ± 0.2 V

d

VCCI

Min VCCI datasheet specification

Activation trip point:

voltage at a selected I/O

standard; i.e., 1.14 V,1.425 V, 1.7 V,

2.3 V, or 3.0 V

V = 0.9 V ± 0.15 V

Deactivation trip point:

a

V

= 0.8 V ± 0.15 V

d

Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels

Revision 17

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IGLOO nano DC and Switching Characteristics

Thermal Characteristics

Introduction

The temperature variable in the Microsemi Designer software refers to the junction temperature, not the

ambient temperature. This is an important distinction because dynamic and static power consumption

cause the chip junction temperature to be higher than the ambient temperature.

EQ 1 can be used to calculate junction temperature.

T_J= Junction Temperature = T + T_A

EQ 1

where:

T_A= Ambient temperature

T = Temperature gradient between junction (silicon) and ambient T = _ja* P

_ja= Junction-to-ambient of the package. _janumbers are located in Figure 2-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is _jcand the junction-to-ambient air thermal resistivity is

_ja. The thermal characteristics for _jaare shown for two air flow rates. The maximum operating junction

temperature is 100°C. EQ 2 shows a sample calculation of the maximum operating power dissipation

allowed for a 484-pin FBGA package at commercial temperature and in still air.

Max. junction temp. (C) – Max. ambient temp. (C) 100C – 70C

------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------

Maximum Power Allowed =

=

= 1.46 W

EQ 2

_ja(C/W)

20.5°C/W

Table 2-5 • Package Thermal Resistivities

_ja

Count

200 ft./

min.

500 ft./

Package Type

_jc

Still Air

TBD

min.

TBD

27.1

Units

Chip Scale Package (CSP)

36

81

TBD

10.0

TBD

29.4

C/W

TBD

Quad Flat No Lead (QFN)

48

TBD

68

TBD

100

TBD

Very Thin Quad Flat Pack (VQFP)

35.3

Temperature and Voltage Derating Factors

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to T_J= 70°C,

VCC = 1.425 V)

For IGLOO nano V2 or V5 Devices, 1.5 V DC Core Supply Voltage

Junction Temperature (°C)

Array Voltage

VCC (V)

1.425

1.5

–40°C

0.947

0.875

0.821

–20°C

0.956

0.883

0.829

0°C

25°C

0.978

0.904

0.848

70°C

1.000

0.925

0.868

85°C

1.009

0.932

0.875

100°C

1.013

0.937

0.879

0.965

0.892

0.837

1.575

2-6

Revision 17

IGLOO nano Low Power Flash FPGAs

Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to T_J= 70°C,

VCC = 1.14 V)

For IGLOO nano V2, 1.2 V DC Core Supply Voltage

Junction Temperature (°C)

0°C 25°C 70°C

Array Voltage

VCC (V)

–40°C

0.968

0.863

0.792

–20°C

0.974

0.868

0.797

85°C

1.006

0.898

0.824

100°C

1.009

0.901

0.827

1.14

0.979

0.873

0.801

0.991

0.884

0.811

1.000

0.892

0.819

1.2

1.26

Calculating Power Dissipation

Quiescent Supply Current

Quiescent supply current (IDD) calculation depends on multiple factors, including operating voltages

(VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power mode usage.

Microsemi recommends using the Power Calculator and SmartPower software estimation tools to

evaluate the projected static and active power based on the user design, power mode usage, operating

voltage, and temperature.

Table 2-8 • Power Supply State per Mode

Power Supply Configurations

Modes/Power Supplies

Flash*Freeze

VCC

On

VCCPLL

VCCI

On

VJTAG

VPUMP

On/off/floating

Off

On

Off

On

Off

On

Sleep

Off

On

Shutdown

Off

No Flash*Freeze

Note: Off: Power Supply level = 0 V

On

On/off/floating

Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO nano Flash*Freeze Mode*

Core

Voltage

AGLN010 AGLN015 AGLN020 AGLN060 AGLN125 AGLN250 Units

Typical (25°C)

1.2 V

1.9

5.8

3.3

6

3.3

6

8

13

18

20

34

µA

1.5 V

10

Note: *IDD includes VCC, VPUMP, VCCI, VCCPLL, and VMV currents. Values do not include I/O static contribution,

which is shown in Table 2-13 on page 2-9 through Table 2-14 on page 2-9 and Table 2-15 on page 2-10

through Table 2-18 on page 2-11 (PDC6 and PDC7).

Revision 17

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IGLOO nano DC and Switching Characteristics

Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO nano Sleep Mode*

Core

Voltage AGLN010 AGLN015 AGLN020 AGLN060 AGLN125 AGLN250 Units

VCCI= 1.2 V (per bank) 1.2 V

Typical (25°C)

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

µA

VCCI

Typical (25°C)

=

1.5 V (per bank) 1.2 V /

1.5 V

VCCI = 1.8 V (per bank) 1.2 V /

Typical (25°C) 1.5 V

VCCI = 2.5 V (per bank) 1.2 V /

Typical (25°C) 1.5 V

VCCI = 3.3 V (per bank) 1.2 V /

Typical (25°C)

1.5 V

Note: *I_DD= N_BANKS* I_CCI

.

Table 2-11 • Quiescent Supply Current (IDD) Characteristics, IGLOO nano Shutdown Mode

Core Voltage AGLN010 AGLN015 AGLN020 AGLN060

1.2 V / 1.5 V

AGLN125

AGLN250

Units

Typical

(25°C)

0

µA

Table 2-12 • Quiescent Supply Current (IDD), No IGLOO nano Flash*Freeze Mode¹

Core

Voltage AGLN010 AGLN015 AGLN020 AGLN060 AGLN125 AGLN250 Units

ICCA Current²

Typical (25°C)

1.2 V

1.5 V

3.7

8

5

10

20

13

28

18

44

µA

14

ICCI or IJTAG Current

VCCI / VJTAG = 1.2 V (per

bank) Typical (25°C)

1.2 V

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

1.7

1.8

1.9

2.2

2.5

µA

VCCI / VJTAG = 1.5 V (per 1.2 V / 1.5 V

bank) Typical (25°C)

VCCI / VJTAG = 1.8 V (per 1.2 V / 1.5 V

bank) Typical (25°C)

VCCI / VJTAG = 2.5 V (per 1.2 V / 1.5 V

bank) Typical (25°C)

VCCI / VJTAG = 3.3 V (per 1.2 V / 1.5 V

bank) Typical (25°C)

Notes:

1. IDD = N

* ICCI + ICCA. JTAG counts as one bank when powered.

BANKS

2. Includes VCC, VCCPLL, and VPUMP currents.

2-8

Revision 17

IGLOO nano Low Power Flash FPGAs

Power per I/O Pin

Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

Applicable to IGLOO nano I/O Banks

Dynamic Power

VCCI (V)

PAC9 (µW/MHz) ¹

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger

3.3 V LVCMOS Wide Range²

3.3 V LVCMOS Wide Range – Schmitt Trigger

2.5 V LVCMOS

3.3

2.5

1.8

1.5

1.2

16.38

18.89

16.38

18.89

4.71

6.13

1.64

1.79

0.97

0.96

0.57

0.52

0.57

0.52

2.5 V LVCMOS – Schmitt Trigger

1.8 V LVCMOS

1.8 V LVCMOS – Schmitt Trigger

1.5 V LVCMOS (JESD8-11)

1.5 V LVCMOS (JESD8-11) – Schmitt Trigger

1.2 V LVCMOS³

1.2 V LVCMOS – Schmitt Trigger³

1.2 V LVCMOS Wide Range³

1.2 V LVCMOS Wide Range – Schmitt Trigger³

Notes:

1. PAC9 is the total dynamic power measured on V

.

CCI

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

3. Applicable to IGLOO nano V2 devices operating at VCCI  VCC.

Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings¹

Applicable to IGLOO nano I/O Banks

Dynamic Power

C_LOAD(pF)

VCCI (V)

PAC10 (µW/MHz)²

Single-Ended

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range³

2.5 V LVCMOS

5

3.3

2.5

1.8

1.5

1.2

107.98

61.24

31.28

21.50

15.22

1.8 V LVCMOS

1.5 V LVCMOS (JESD8-11)

1.2 V LVCMOS⁴

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PAC10 is the total dynamic power measured on VCCI.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

4. Applicable for IGLOO nano V2 devices operating at VCCI  VCC.

Revision 17

2-9

IGLOO nano DC and Switching Characteristics

Power Consumption of Various Internal Resources

Table 2-15 • Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices

For IGLOO nano V2 or V5 Devices, 1.5 V Core Supply Voltage

Device Specific Dynamic Power (µW/MHz)

Parameter

PAC1

Definition

AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010

Clock contribution of a Global Rib

Clock contribution of a Global Spine

4.421

2.704

4.493

1.976

1.504

0.153

2.700

1.982

1.511

0.153

0

PAC2

4.002

1.346

0.148

4.002

1.346

0.148

2.633

1.340

0.143

PAC3

Clock contribution of a VersaTile row 1.496

PAC4

Clock contribution of a VersaTile 0.152

used as a sequential module

PAC5

PAC6

PAC7

First contribution of a VersaTile used

as a sequential module

0.057

Second contribution of a VersaTile

used as a sequential module

0.207

0.17

0.7

Contribution of a VersaTile used as

a combinatorial module

PAC8

PAC9

Average contribution of a routing net

Contribution of an I/O input pin

(standard-dependent)

See Table 2-13 on page 2-9.

PAC10

PAC11

PAC12

PAC13

Contribution of an I/O output pin

(standard-dependent)

See Table 2-14.

Average contribution of a RAM block

during a read operation

25.00

30.00

2.70

N/A

Average contribution of a RAM block

during a write operation

Dynamic contribution for PLL

Table 2-16 • Different Components Contributing to the Static Power Consumption in IGLOO nano Devices

For IGLOO nano V2 or V5 Devices, 1.5 V Core Supply Voltage

Device -Specific Static Power (mW)

Parameter

PDC1

Definition

AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010

See Table 2-12 on page 2-8

Array static power in Active mode

PDC2

Array static power in Static (Idle)

mode

See Table 2-12 on page 2-8

PDC3

Array static power in Flash*Freeze

mode

See Table 2-9 on page 2-7

PDC4 ¹

PDC5

Static PLL contribution

1.84

N/A

Bank quiescent power

(VCCI-dependent)²

See Table 2-12 on page 2-8

Notes:

1. Minimum contribution of the PLL when running at lowest frequency.

2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet

calculator or the SmartPower tool in Libero SoC.

2-10

Revision 17

IGLOO nano Low Power Flash FPGAs

Table 2-17 • Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices

For IGLOO nano V2 Devices, 1.2 V Core Supply Voltage

Device-Specific Dynamic Power (µW/MHz)

Parameter

PAC1

Definition

AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010

Clock contribution of a Global Rib

Clock contribution of a Global Spine

Clock contribution of a VersaTile row

2.829

1.731

0.957

2.875

1.265

0.963

0.098

1.728

1.268

0.967

0.098

0

PAC2

2.562

0.862

0.094

2.562

0.862

0.094

1.685

0.858

0.091

PAC3

PAC4

Clock contribution of a VersaTile used 0.098

as a sequential module

PAC5

PAC6

PAC7

First contribution of a VersaTile used

as a sequential module

0.045

Second contribution of a VersaTile

used as a sequential module

0.186

0.11

Contribution of a VersaTile used as a

combinatorial module

PAC8

PAC9

Average contribution of a routing net

0.45

Contribution of an I/O input pin

(standard-dependent)

See Table 2-13 on page 2-9

PAC10

PAC11

PAC12

PAC13

Contribution of an I/O output pin

(standard-dependent)

See Table 2-14 on page 2-9

Average contribution of a RAM block

during a read operation

25.00

N/A

Average contribution of a RAM block

during a write operation

30.00

2.10

Dynamic contribution for PLL

Table 2-18 • Different Components Contributing to the Static Power Consumption in IGLOO nano Devices

For IGLOO nano V2 Devices, 1.2 V Core Supply Voltage

Device-Specific Static Power (mW)

Parameter

PDC1

Definition

AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010

See Table 2-12 on page 2-8

Array static power in Active mode

PDC2

Array static power in Static (Idle)

mode

See Table 2-12 on page 2-8

PDC3

Array static power in Flash*Freeze

mode

See Table 2-9 on page 2-7

PDC4 ¹

PDC5

Static PLL contribution

0.90

N/A

Bank quiescent power

(VCCI-dependent)²

See Table 2-12 on page 2-8

Notes:

1. Minimum contribution of the PLL when running at lowest frequency.

2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet

calculator or the SmartPower tool in Libero SoC.

Revision 17

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IGLOO nano DC and Switching Characteristics

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For more

accurate and detailed power estimations, use the SmartPower tool in Libero SoC software.

The power calculation methodology described below uses the following variables:

•

The number of PLLs as well as the number and the frequency of each output clock generated

The number of combinatorial and sequential cells used in the design

The internal clock frequencies

The number and the standard of I/O pins used in the design

The number of RAM blocks used in the design

Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-19 on

page 2-14.

•

Enable rates of output buffers—guidelines are provided for typical applications in Table 2-20 on

page 2-14.

Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-20 on page 2-14. The calculation should be repeated for each clock domain defined in the

design.

Methodology

Total Power Consumption—P

TOTAL

P_TOTAL= P_STAT+ P_DYN

P_STATis the total static power consumption.

_DYNis the total dynamic power consumption.

Total Static Power Consumption—P

P

STAT

P_STAT= (PDC1 or PDC2 or PDC3) + N_BANKS* PDC5

N_BANKSis the number of I/O banks powered in the design.

Total Dynamic Power Consumption—P

DYN

P_DYN= P_CLOCK+ P_S-CELL+ P_C-CELL+ P_NET+ P_INPUTS+ P_OUTPUTS+ P_MEMORY+ P_PLL

Global Clock Contribution—P

CLOCK

P_CLOCK= (PAC1 + N_SPINE* PAC2 + N_ROW* PAC3 + N_S-CELL* PAC4) * F_CLK

N_SPINEis the number of global spines used in the user design—guidelines are provided in

the "Spine Architecture" section of the IGLOO nano FPGA Fabric User's Guide.

N

_ROWis the number of VersaTile rows used in the design—guidelines are provided in the

"Spine Architecture" section of the IGLOO nano FPGA Fabric User's Guide.

_CLKis the global clock signal frequency.

_S-CELLis the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

F

N

Sequential Cells Contribution—P

S-CELL

P_S-CELL= N_S-CELL* (PAC5 + ₁/ 2 * PAC6) * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design. When a

multi-tile sequential cell is used, it should be accounted for as 1.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on

page 2-14.

F_CLKis the global clock signal frequency.

2-12

Revision 17

IGLOO nano Low Power Flash FPGAs

Combinatorial Cells Contribution—P

C-CELL

P_C-CELL= N_C-CELL* ₁/ 2 * PAC7 * F_CLK

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on

page 2-14.

F

_CLKis the global clock signal frequency.

Routing Net Contribution—P

NET

P_NET= (N_S-CELL+ N_C-CELL) * ₁/ 2 * PAC8 * F_CLK

N_S-CELLis the number of VersaTiles used as sequential modules in the design.

N_C-CELLis the number of VersaTiles used as combinatorial modules in the design.

₁is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on

page 2-14.

F_CLKis the global clock signal frequency.

I/O Input Buffer Contribution—P

INPUTS

P_INPUTS= N_INPUTS* ₂/ 2 * PAC9 * F_CLK

N_INPUTSis the number of I/O input buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14.

F

_CLKis the global clock signal frequency.

I/O Output Buffer Contribution—P

OUTPUTS

P_OUTPUTS= N_OUTPUTS* ₂/ 2 * ₁* PAC10 * F_CLK

N_OUTPUTSis the number of I/O output buffers used in the design.

₂is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14.

₁is the I/O buffer enable rate—guidelines are provided in Table 2-20 on page 2-14.

F

_CLKis the global clock signal frequency.

RAM Contribution—P

MEMORY

P_MEMORY= PAC11 * N_BLOCKS* F_READ-CLOCK* ₂+ PAC12 * N_BLOCK* F_WRITE-CLOCK* ₃

N_BLOCKSis the number of RAM blocks used in the design.

F

_READ-CLOCKis the memory read clock frequency.

₂is the RAM enable rate for read operations.

_WRITE-CLOCKis the memory write clock frequency.

F

₃is the RAM enable rate for write operations—guidelines are provided in Table 2-20 on

page 2-14.

PLL Contribution—P

PLL

P_PLL= PDC4 + PAC13 *F_CLKOUT

F_CLKOUTis the output clock frequency.¹

1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding

contribution (PAC13* FCLKOUT product) to the total PLL contribution.

Revision 17

2-13

IGLOO nano DC and Switching Characteristics

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the

toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are

some examples:

•

The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the

clock frequency.

•

The average toggle rate of an 8-bit counter is 25%:

–

Bit 0 (LSB) = 100%

Bit 1

Bit 2

…

= 50%

= 25%

Bit 7 (MSB) = 0.78125%

Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled. When

nontristate output buffers are used, the enable rate should be 100%.

Table 2-19 • Toggle Rate Guidelines Recommended for Power Calculation

Component

Definition

Toggle rate of VersaTile outputs

I/O buffer toggle rate

Guideline

10%

₁

₂

10%

Table 2-20 • Enable Rate Guidelines Recommended for Power Calculation

Component

Definition

I/O output buffer enable rate

Guideline

100%

₁

₂

₃

RAM enable rate for read operations

RAM enable rate for write operations

12.5%

2-14

Revision 17

IGLOO nano Low Power Flash FPGAs

User I/O Characteristics

Timing Model

I/O Module

(Non-Registered)

Combinational Cell

Y

Combinational Cell

Y

LVCMOS 2.5 V Output Drive

Strength = 8 mA High Slew Rate

t

= 1.18 ns

t

= 0.90 ns

PD

t

= 1.99 ns

DP

I/O Module

(Non-Registered)

Combinational Cell

Y

Output drive strength = 4 mA

High slew rate

LVTTL

t

= 2.35 ns

DP

t

= 1.60 ns

PD

I/O Module

(Non-Registered)

Combinational Cell

Y

I/O Module

(Registered)

Output drive strength = 8 mA

High slew rate

LVTTL

t

= 1.06 ns

PY

t

= 1.96 ns

DP

t

= 1.17 ns

PD

I/O Module

(Non-Registered)

Input LVCMOS 2.5 V

D

Q

Combinational Cell

Y

Output drive strength = 2 mA

High slew rate

LVCMOS 1.5 V

t

= 0.42 ns

= 0.47 ns

ICLKQ

ISUD

t

= 2.65 ns

DP

t

= 0.87 ns

PD

Input LVTTL

Clock

I/O Module

Register Cell

(Registered)

Register Cell

Combinational Cell

Y

t

= 0.85 ns

PY

D

Q

D

Q

D

t

Q

LVTTL 3.3 V Output drive

strength = 8 mA High slew rate

I/O Module

t

= 0.91 ns

PD

t

= 1.96 ns

(Non-Registered)

DP

t

= 0.89 ns

= 0.81 ns

= 1.00 ns

= 0.51 ns

CLKQ

SUD

t

= 0.89 ns

= 0.81 ns

OCLKQ

CLKQ

t

LVCMOS 1.5 V

OSUD

SUD

Input LVTTL

Clock

Input LVTTL

Clock

t

= 1.15 ns

PY

t

= 0.85 ns

t

= 0.85 ns

PY

Figure 2-3 • Timing Model

Operating Conditions: STD Speed, Commercial Temperature Range (T_J= 70°C), Worst-Case

VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices

Revision 17

2-15

IGLOO nano DC and Switching Characteristics

t_PY

t_DIN

D

Q

PAD

DIN

Y

CLK

To Array

I/O Interface

t

_PY= MAX(t_PY(R), t_PY(F))

_DIN= MAX(t_DIN(R), t_DIN(F))

VIH

Vtrip

VIL

PAD

VCC

50%

Y

GND

t_PY

(R)

t_PY

(F)

VCC

50%

DIN

t_DIN

(R)

GND

t_DIN

(F)

Figure 2-4 • Input Buffer Timing Model and Delays (example)

2-16

Revision 17

IGLOO nano Low Power Flash FPGAs

t_DOUT

D Q

t_DP

PAD

DOUT

CLK

Std

Load

D

From Array

t_DP= MAX(t_DP(R), t_DP(F))

t_DOUT= MAX(t_DOUT(R), t_DOUT(F))

I/O Interface

t_DOUT

(R)

t_DOUT

(F)

VCC

50%

VCC

D

0 V

50%

DOUT

PAD

0 V

VOH

Vtrip

V_OL

Vtrip

t_DP

(R)

t_DP

(F)

Figure 2-5 • Output Buffer Model and Delays (example)

Revision 17

2-17

IGLOO nano DC and Switching Characteristics

t

EOUT

D

Q

CLK

t

, t , t , t , t , t

E

ZL ZH HZ LZ ZLS ZHS

EOUT

D

Q

PAD

DOUT

CLK

D

t

= MAX(t

(r), t (f))

EOUT

I/O Interface

EOUT

VCC

D

E

VCC

50%

t

50%

t

EOUT (F)

EOUT (R)

VCC

50%

ZH

50%

t

LZ

EOUT

PAD

t

ZL

HZ

VCCI

90% VCCI

Vtrip

VOL

10% V

CCI

VCC

D

E

VCC

50%

t

EOUT (F)

EOUT (R)

VCC

50%

EOUT

PAD

50%

VOH

t

ZHS

t

ZLS

Vtrip

VOL

Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)

2-18

Revision 17

IGLOO nano Low Power Flash FPGAs

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions—Software Default Settings

Equivalent

Software

Default

VIL

VIH

VOL

VOH

IOL¹IOH¹

Drive

Slew Min.

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

I/O Standard

Strength Strength²Rate

V

mA mA

3.3 V LVTTL /

3.3 V LVCMOS

8 mA

High –0.3

0.8

2

3.6

0.4

2.4

8

3.3 V LVCMOS 100 µA

Wide Range³

0.8

0.7

2

0.2

VCCI – 0.2 100 100

µA µA

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

8 mA

4 mA

2 mA

8 mA

4 mA

2 mA

1 mA

1.7

0.7

1.7

8

4

2

1

8

4

2

1

High –0.3 0.35 * VCCI 0.65 * VCCI 3.6

0.45

VCCI – 0.45

High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI

1.2 V LVCMOS⁴1 mA

1.2 V LVCMOS 100 µA

Wide Range^4,5

High –0.3 0.3 * VCCI 0.7 * VCCI 3.6

0.1

VCCI – 0.1 100 100

µA µA

Notes:

1. Currents are measured at 85°C junction temperature.

2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.

4. Applicable to IGLOO nano V2 devices operating at VCCI VCC.

5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range, as specified in the JESD8-12 specification.

Table 2-22 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

Commercial¹

Industrial²

IIL ³

µA

10

IIH ⁴

µA

10

IIL ³

µA

15

IIH ⁴

µA

15

DC I/O Standards

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCOMS Wide Range

2.5 V LVCMOS

10

15

10

15

1.8 V LVCMOS

10

15

1.5 V LVCMOS

1.2 V LVCMOS⁵

1.2 V LVCMOS Wide Range⁵

10

15

10

15

10

15

Notes:

1. Commercial range (–20°C < T < 70°C)

A

2. Industrial range (–40°C < T < 85°C)

A

3.

I

is the input leakage current per I/O pin over recommended operating conditions, where VIH < VIN < VCCI. Input

IH

current is larger when operating outside recommended ranges.

4.

I

is the input leakage current per I/O pin over recommended operating conditions, where –0.3 V < VIN < VIL.

IL

5. Applicable to IGLOO nano V2 devices operating at VCCI VCC.

Revision 17

2-19

IGLOO nano DC and Switching Characteristics

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-23 • Summary of AC Measuring Points

Standard

Measuring Trip Point (Vtrip)

3.3 V LVTTL / 3.3 V LVCMOS

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

1.4 V

1.2 V

1.8 V LVCMOS

0.90 V

0.75 V

0.60 V

1.5 V LVCMOS

1.2 V LVCMOS

1.2 V LVCMOS Wide Range

Table 2-24 • I/O AC Parameter Definitions

Parameter

Parameter Definition

Data to Pad delay through the Output Buffer

t_DP

t_PY

Pad to Data delay through the Input Buffer

t_DOUT

t_EOUT

t_DIN

t_HZ

Data to Output Buffer delay through the I/O interface

Enable to Output Buffer Tristate Control delay through the I/O interface

Input Buffer to Data delay through the I/O interface

Enable to Pad delay through the Output Buffer—HIGH to Z

Enable to Pad delay through the Output Buffer—Z to HIGH

Enable to Pad delay through the Output Buffer—LOW to Z

t_ZH

t_LZ

t_ZL

Enable to Pad delay through the Output Buffer—Z to LOW

t_ZHS

t_ZLS

Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

2-20

Revision 17

IGLOO nano Low Power Flash FPGAs

Applies to IGLOO nano at 1.5 V Core Operating Conditions

Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings

STD Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 3.0 V

3.3 V LVTTL /

8 mA 8 mA High 5 pF 0.97 1.79 0.19 0.86 1.16 0.66 1.83 1.45 1.98 2.38 ns

3.3 V LVCMOS

3.3 V LVCMOS 100 µA 8 mA High 5 pF 0.97 2.56 0.19 1.20 1.66 0.66 2.57 2.02 2.82 3.31 ns

Wide Range²

2.5 V LVCMOS 8 mA 8 mA High 5 pF 0.97 1.81 0.19 1.10 1.24 0.66 1.85 1.63 1.97 2.26 ns

1.8 V LVCMOS 4 mA 4 mA High 5 pF 0.97 2.08 0.19 1.03 1.44 0.66 2.12 1.95 1.99 2.19 ns

1.5 V LVCMOS 2 mA 2 mA High 5 pF 0.97 2.39 0.19 1.19 1.52 0.66 2.44 2.24 2.02 2.15 ns

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the

IBIS models.

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 17

2-21

IGLOO nano DC and Switching Characteristics

Applies to IGLOO nano at 1.2 V Core Operating Conditions

Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings

STD Speed Grade, Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V,

Worst-Case VCCI = 3.0 V

3.3 V LVTTL /

8 mA 8 mA High 5 pF 1.55 2.31 0.26 0.97 1.36 1.10 2.34 1.90 2.43 3.14 ns

3.3 V LVCMOS

3.3 V LVCMOS 100 µA 8 mA High 5 pF 1.55 3.25 0.26 1.31 1.91 1.10 3.25 2.61 3.38 4.27 ns

Wide Range²

2.5 V LVCMOS 8 mA 8 mA High 5 pF 1.55 2.30 0.26 1.21 1.39 1.10 2.33 2.04 2.41 2.99 ns

1.8 V LVCMOS 4 mA 4 mA High 5 pF 1.55 2.49 0.26 1.13 1.59 1.10 2.53 2.34 2.42 2.81 ns

1.5 V LVCMOS 2 mA 2 mA High 5 pF 1.55 2.78 0.26 1.27 1.77 1.10 2.82 2.62 2.44 2.74 ns

1.2 V LVCMOS 1 mA 1 mA High 5 pF 1.55 3.50 0.26 1.56 2.27 1.10 3.37 3.10 2.55 2.66 ns

1.2 V LVCMOS 100 µA 1 mA High 5 pF 1.55 3.50 0.26 1.56 2.27 1.10 3.37 3.10 2.55 2.66 ns

Wide Range³

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is

±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to

the IBIS models..

2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification.

3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V side range as specified in the JESD8-12 specification.

4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-22

Revision 17

IGLOO nano Low Power Flash FPGAs

Detailed I/O DC Characteristics

Table 2-27 • Input Capacitance

Symbol

C_IN

Definition

Conditions

Min.

Max.

Units

pF

Input capacitance

Input capacitance on the clock pin

VIN = 0, f = 1.0 MHz

8

C_INCLK

pF

Table 2-28 • I/O Output Buffer Maximum Resistances ¹

R_PULL-DOWN

R_PULL-UP

Standard

Drive Strength

2 mA

()²

()³

3.3 V LVTTL / 3.3V LVCMOS

100

50

300

150

4 mA

6 mA

8 mA

50

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

100 µA

2 mA

Same as equivalent software default drive

100

50

200

100

225

112

224

315

4 mA

6 mA

8 mA

50

1.8 V LVCMOS

2 mA

200

100

200

315

4 mA

1.5 V LVCMOS

2 mA

1.2 V LVCMOS ⁴

1.2 V LVCMOS Wide Range ⁴

Notes:

1 mA

100 µA

1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend

on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer

resistances, use the corresponding IBIS models posted at http://www.microsemi.com/soc/download/ibis/default.aspx.

2.

R

= (VOLspec) / IOLspec

(PULL-DOWN-MAX)

3.

R

= (VCCImax – VOHspec) / I

(PULL-UP-MAX)

OHspec

4. Applicable to IGLOO nano V2 devices operating at VCCI  VCC.

Revision 17

2-23

IGLOO nano DC and Switching Characteristics

Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

R_{(WEAK PULL-UP)}¹() R_{(WEAK PULL-DOWN)}²()

Min.

VCCI

Max.

45 K

55 K

70 K

90 K

110 K

Min.

Max.

45 K

3.3 V

10 K

11 K

18 K

19 K

25 K

19 K

10 K

12 K

17 K

19 K

25 K

19 K

3.3 V (wide range I/Os)

45 K

2.5 V

74 K

1.8 V

110 K

140 K

150 K

1.5 V

1.2 V

1.2 V (wide range I/Os)

Notes:

1.

2.

R

= (VCCImax – VOHspec) / I

)

(WEAK PULL-UP-MAX)

(WEAK PULL-UP-MIN

= (VOLspec) / I

(WEAK PULL-DOWN-MAX)

(WEAK PULL-DOWN-MIN)

Table 2-30 • I/O Short Currents IOSH/IOSL

Drive Strength

IOSL (mA)*

IOSH (mA)*

3.3 V LVTTL / 3.3 V LVCMOS

2 mA

4 mA

6 mA

8 mA

25

51

27

54

3.3 V LVCMOS Wide Range

2.5 V LVCMOS

100 µA

2 mA

4 mA

6 mA

8 mA

2 mA

4 mA

2 mA

1 mA

100 µA

Same as equivalent software default drive

16

32

9

18

37

11

22

16

13

1.8 V LVCMOS

17

13

10

1.5 V LVCMOS

1.2 V LVCMOS

1.2 V LVCMOS Wide Range

Note: *T_J= 100°C

2-24

Revision 17

IGLOO nano Low Power Flash FPGAs

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 8 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 100°C, the short current condition would have to be sustained for more than six months

to cause a reliability concern. The I/O design does not contain any short circuit protection, but such

protection would only be needed in extremely prolonged stress conditions.

Table 2-31 • Duration of Short Circuit Event before Failure

Temperature

–40°C

–20°C

0°C

Time before Failure

> 20 years

5 years

25°C

70°C

85°C

2 years

100°C

6 months

Table 2-32 • Schmitt Trigger Input Hysteresis

Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers

Input Buffer Configuration

Hysteresis Value (typ.)

3.3 V LVTTL / LVCMOS (Schmitt trigger mode)

2.5 V LVCMOS (Schmitt trigger mode)

1.8 V LVCMOS (Schmitt trigger mode)

1.5 V LVCMOS (Schmitt trigger mode)

1.2 V LVCMOS (Schmitt trigger mode)

240 mV

140 mV

80 mV

60 mV

40 mV

Table 2-33 • I/O Input Rise Time, Fall Time, and Related I/O Reliability

Input Rise/Fall

Time (min.)

Input Rise/Fall Time

(max.)

Input Buffer

Reliability

LVTTL/LVCMOS (Schmitt trigger

disabled)

No requirement

10 ns *

20 years (100°C)

LVTTL/LVCMOS (Schmitt trigger

enabled)

No requirement

No requirement, but

input noise voltage

cannot exceed Schmitt

hysteresis.

20 years (100°C)

Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the

noise is low, then the rise time and fall time of input buffers can be increased beyond the

maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board

noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure

that there is no excessive noise coupling into input signals.

Revision 17

2-25

IGLOO nano DC and Switching Characteristics

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic (LVTTL) is a general purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer.

Table 2-34 • Minimum and Maximum DC Input and Output Levels

3.3 V LVTTL /

3.3 V LVCMOS

VIL

VIH

VOL

VOH IOL IOH

Min.

IOSL

IOSH

IIL ¹IIH ²

Drive

Strength

Min.

V

Max.

V

Min.

V

Max.

V

Max.

V

Max.

mA³

Max.

mA³

V

mA mA

µA⁴µA⁴

10 10

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3

0.8

2

3.6

0.4

2.4

2

4

6

8

2

25

51

27

54

4

6

8

1.

2.

I

is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.

is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input

IL

IH

current is larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

5 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-7 • AC Loading

Table 2-35 • 3.3 V LVTTL/LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C

_LOAD(pF)

0

3.3

1.4

5

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points.

2-26

Revision 17

IGLOO nano Low Power Flash FPGAs

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

STD

0.97 3.52 0.19 0.86 1.16

0.97 2.90 0.19 0.86 1.16

0.66 3.59 3.42 1.75 1.90

0.66 2.96 2.83 1.98 2.29

ns

4 mA

6 mA

8 mA

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

STD

0.97 2.16 0.19 0.86 1.16

0.97 1.79 0.19 0.86 1.16

0.66 2.20 1.80 1.75 1.99

0.66 1.83 1.45 1.98 2.38

ns

4 mA

6 mA

8 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 17

2-27

IGLOO nano DC and Switching Characteristics

Applies to 1.2 V DC Core Voltage

Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

STD

1.55 4.09 0.26 0.97 1.36

1.55 3.45 0.26 0.97 1.36

1.10 4.16 3.91 2.19 2.64

1.10 3.51 3.32 2.43 3.03

ns

4 mA

6 mA

8 mA

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-39 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

STD

1.55 2.68 0.26 0.97 1.36

1.55 2.31 0.26 0.97 1.36

1.10 2.72 2.26 2.19 2.74

1.10 2.34 1.90 2.43 3.14

ns

4 mA

6 mA

8 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-28

Revision 17

IGLOO nano Low Power Flash FPGAs

3.3 V LVCMOS Wide Range

Table 2-40 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range

3.3 V LVCMOS Equivalent

Wide Range¹

Software

Default

VIL

VIH

VOL

VOH

IOL

I_OHIIL ²IIH ³

Drive

Strength

Strength Min.

Max.

V

Min.

V

Max.

V

Max.

V

Min.

V

Option⁴

V

µA

µA µA⁵µA⁵

100 µA

Notes:

2 mA

–0.3

0.8

2

3.6

0.2

VCCI – 0.2 100

100

10

4 mA

6 mA

8 mA

1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V Wide Range, as specified in the JEDEC JESD8-B

specification.

2.

I

is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.

IL

3.

I

is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input

IH

current is larger when operating outside recommended ranges.

4. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

5. Currents are measured at 85°C junction temperature.

6. Software default selection is highlighted in gray.

Revision 17

2-29

IGLOO nano DC and Switching Characteristics

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Table 2-41 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Equivalent

Software

Default

Drive

Strength

Speed

Grade

Strength Option¹

t_DOUTt_DP

t_DIN

t_PY

t_PYS

t_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

100 µA

Notes:

2 mA

4 mA

6 mA

8 mA

STD

0.97

5.23 0.19 1.20 1.66

4.27 0.19 1.20 1.66

0.66 5.24 5.00 2.47 2.56

0.66 4.28 4.12 2.83 3.16

ns

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-42 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V

Equivalent

Software

Default

Drive

Strength

Speed

Grade

Strength Option¹

t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

100 µA

Notes:

2 mA

4 mA

6 mA

8 mA

STD

0.97

3.11 0.19 1.20 1.66

2.56 0.19 1.20 1.66

0.66 3.13 2.55 2.47 2.70

0.66 2.57 2.02 2.82 3.31

ns

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

3. Software default selection highlighted in gray.

2-30

Revision 17

IGLOO nano Low Power Flash FPGAs

Applies to 1.2 V DC Core Voltage

Table 2-43 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V

Equivalent

Software

Default

Drive

Strength

Speed

Grade

Strength Option¹

t_DOUTt_DP

t_DIN

t_PY

t_PYS

t_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

100 µA

Notes:

2 mA

4 mA

6 mA

8 mA

STD

1.55

6.01 0.26 1.31 1.91

5.02 0.26 1.31 1.91

1.10 6.01 5.66 3.02 3.49

1.10 5.02 4.76 3.38 4.10

ns

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-44 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V

Equivalent

Software

Default

Drive

Strength

Speed

Grade

Strength Option¹

t_DOUTt_DP

t_DIN

t_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

100 µA

Notes:

2 mA

4 mA

6 mA

8 mA

STD

1.55

3.82 0.26 1.31 1.91

3.25 0.26 1.31 1.91

1.10 3.82 3.15 3.01 3.65

1.10 3.25 2.61 3.38 4.27

ns

1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

3. Software default selection highlighted in gray.

Revision 17

2-31

IGLOO nano DC and Switching Characteristics

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general

purpose 2.5 V applications.

Table 2-45 • Minimum and Maximum DC Input and Output Levels

2.5 V

LVCMOS

VIL

VIH

VOL

VOH IOL IOH

IOSL

IOSH

IIL ¹IIH ²

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA³Max., mA³µA⁴µA⁴

2 mA

4 mA

6 mA

8 mA

Notes:

–0.3

0.7

1.7

3.6

0.7

1.7

2

16

32

18

37

10 10

4

6

8

1.

2.

I

is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.

is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input

IL

IH

current is larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

5 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-8 • AC Loading

Table 2-46 • 2.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C

_LOAD(pF)

0

2.5

1.2

5

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points.

2-32

Revision 17

IGLOO nano Low Power Flash FPGAs

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Table 2-47 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZHt_LZt_HZUnits

STD

0.97 4.13 0.19 1.10 1.24

0.97 3.39 0.19 1.10 1.24

0.66 4.01 4.13 1.73 1.74

0.66 3.31 3.39 1.98 2.19

ns

4 mA

8 mA

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-48 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

STD

0.97 2.19 0.19 1.10 1.24

0.97 1.81 0.19 1.10 1.24

0.66 2.23 2.11 1.72 1.80

0.66 1.85 1.63 1.97 2.26

ns

4 mA

6 mA

8 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 17

2-33

IGLOO nano DC and Switching Characteristics

Applies to 1.2 V DC Core Voltage

Table 2-49 • 2.5 LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

STD

1.55 4.61 0.26 1.21 1.39

1.55 3.86 0.26 1.21 1.39

1.10 4.55 4.61 2.15 2.43

1.10 3.82 3.86 2.41 2.89

ns

4 mA

6 mA

8 mA

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-50 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

STD

1.55 2.68 0.26 1.21 1.39

1.55 2.30 0.26 1.21 1.39

1.10 2.72 2.54 2.15 2.51

1.10 2.33 2.04 2.41 2.99

ns

4 mA

6 mA

8 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-34

Revision 17

IGLOO nano Low Power Flash FPGAs

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-51 • Minimum and Maximum DC Input and Output Levels

1.8 V

LVCMOS

VIL

Max.

VIH

VOL

VOH

IOL IOH

mA mA

IOSL

IOSH

IIL ¹I_IH ²

Drive

Strength

Min.

V

Min.

V

Max. Max.

Min.

V

Max.

mA³

Max.

mA³

V

µA⁴µA⁴

10 10

2 mA

4 mA

Notes:

–0.3 0.35 * VCCI 0.65 * VCCI 3.6

0.45 VCCI – 0.45

2

4

2

4

9

11

22

17

1.

2.

I

is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.

is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input

IL

IH

current is larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

5 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-9 • AC Loading

Table 2-52 • 1.8 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.8

0.9

5

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points.

Revision 17

2-35

IGLOO nano DC and Switching Characteristics

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Table 2-53 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZ

Units

ns

STD

0.97 5.44 0.19 1.03 1.44

0.97 4.44 0.19 1.03 1.44

0.66 5.25 5.44 1.69 1.35

0.66 4.37 4.44 1.99 2.11

4 mA

ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-54 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

STD

0.97 2.64 0.19 1.03 1.44

0.97 2.08 0.19 1.03 1.44

0.66 2.59 2.64 1.69 1.40

0.66 2.12 1.95 1.99 2.19

ns

4 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Applies to 1.2 V DC Core Voltage

Table 2-55 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PYt_PYSt_EOUTt_ZLt_ZHt_LZt_HZUnits

STD

1.55 5.92 0.26 1.13 1.59

1.55 4.91 0.26 1.13 1.59

1.10 5.72 5.92 2.11 1.95

1.10 4.82 4.91 2.42 2.73

ns

4 mA

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-56 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

STD

1.55 3.05 0.26 1.13 1.59

1.55 2.49 0.26 1.13 1.59

1.10 3.01 3.05 2.10 2.00

1.10 2.53 2.34 2.42 2.81

ns

4 mA

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-36

Revision 17

IGLOO nano Low Power Flash FPGAs

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-57 • Minimum and Maximum DC Input and Output Levels

1.5 V

LVCMOS

VIL

Max.

VIH

Min.

VOL

VOH

IOL IOH IOSL

IOSH IIL ¹IIH ²

Drive

Strength

Min.

V

Max.

V

Max.

V

Min.

V

Max.

V

mA mA mA³

mA³µA⁴µA⁴

2 mA

–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI

2

13

16

10 10

Notes:

1.

I is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.

IL

2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input

current is larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

5 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-10 • AC Loading

Table 2-58 • 1.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.5

0.75

5

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points.

Revision 17

2-37

IGLOO nano DC and Switching Characteristics

Timing Characteristics

Applies to 1.5 V DC Core Voltage

Table 2-59 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Drive Strength

Speed Grade t_DOUTt_DPt_DINt_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

ns

2 mA

STD 0.97 5.39 0.19 1.19 1.62

0.66 5.48 5.39 2.02 2.06

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-60 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

ns

STD 0.97 2.39 0.19 1.19 1.62

0.66 2.44 2.24 2.02 2.15

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Applies to 1.2 V DC Core Voltage

Table 2-61 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Drive Strength

Speed Grade t_DOUTt_DPt_DINt_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

ns

2 mA

STD 1.55 5.87 0.26 1.27 1.77

1.10 5.92 5.87 2.45 2.65

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-62 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V

Drive Strength

2 mA

Speed Grade t_DOUTt_DPt_DINt_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

ns

STD 1.55 2.78 0.26 1.27 1.77

1.10 2.82 2.62 2.44 2.74

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

2-38

Revision 17

IGLOO nano Low Power Flash FPGAs

1.2 V LVCMOS (JESD8-12A)

Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V

applications. It uses a 1.2 V input buffer and a push-pull output buffer.

Table 2-63 • Minimum and Maximum DC Input and Output Levels

1.2 V

LVCMOS

VIL

Max.

VIH

Min.

VOL

VOH

IOL IOH IOSL IOSH IIL ¹IIH ²

Drive

Strength

Min.

V

Max.

V

Max.

V

Min.

V

Max.

V

mA mA mA³

mA³µA⁴µA⁴

1 mA

–0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI

1

10

13

10 10

Notes:

1.

2.

I

is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.

is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input

IL

IH

current is larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Software default selection highlighted in gray.

R to VCCI for t_LZ/ t_ZL/ t_ZLS

R = 1 k

Test Point

Datapath

R to GND for t_HZ/ t_ZH/ t_ZHS

Test Point

5 pF

Enable Path

5 pF for t_ZH/ t_ZHS/ t_ZL/ t_ZLS

5 pF for t_HZ/ t_LZ

Figure 2-11 • AC Loading

Table 2-64 • 1.2 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V)

Input HIGH (V)

Measuring Point* (V)

C

_LOAD(pF)

0

1.2

0.6

5

Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points.

Timing Characteristics

Applies to 1.2 V DC Core Voltage

Table 2-65 • 1.2 V LVCMOS Low Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Drive Strength

Speed Grade t_DOUT

STD 1.55

t_DP

t_DINt_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

ns

1 mA

8.30 0.26 1.56 2.27

1.10 7.97 7.54 2.56 2.55

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-66 • 1.2 V LVCMOS High Slew

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Drive Strength

Speed Grade t_DOUTt_DPt_DINt_PY

t_PYSt_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

ns

1 mA

STD 1.55 3.50 0.26 1.56 2.27

1.10 3.37 3.10 2.55 2.66

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 17

2-39

IGLOO nano DC and Switching Characteristics

1.2 V LVCMOS Wide Range

Table 2-67 • Minimum and Maximum DC Input and Output Levels

1.2 V

LVCMOS

Wide

Range

VIL

Max.

VIH

Min.

VOL

VOH

IOL IOH

mA mA

IOSL

IOSH IIL ¹IIH ²

Max.

Drive

Strength

Min.

V

Max.

V

Max.

V

Min.

V

Max.

mA³

V

mA³

µA⁴µA⁴

1 mA

–0.3 0.3 * VCCI 0.7 * VCCI 3.6

0.1

VCCI – 0.1 100 100

10

13

10 10

Notes:

1.

2.

I

is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.

is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input

IL

IH

current is larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. ^{Applicable to IGLOO nano V2 devices operating at VCCI}VCC.

6. Software default selection highlighted in gray.

Timing Characteristics

Applies to 1.2 V DC Core Voltage

Table 2-68 • 1.2 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Equivalent

Software

Default

Drive

Strength

Speed

Grade

Strength Option¹

t_DOUTt_DP

t_DIN

t_PY

t_PYS

t_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

ns

100 µA

1 mA

STD

1.55 8.30 0.26 1.56 2.27

1.10 7.97 7.54 2.56 2.55

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Table 2-69 • 1.2 V LVCMOS Wide Range HIgh Slew – Applies to 1.2 V DC Core Voltage

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V

Equivalent

Software

Default

Drive

Strength

Speed

Grade

Strength Option¹

t_DOUTt_DP

t_DIN

t_PY

t_PYS

t_EOUTt_ZL

t_ZH

t_LZ

t_HZUnits

ns

100 µA

1 mA

STD

1.55 3.50 0.26 1.56 2.27

1.10 3.37 3.10 2.55 2.66

Notes:

1. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive

strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

3. Software default selection highlighted in gray.

2-40

Revision 17

IGLOO nano Low Power Flash FPGAs

I/O Register Specifications

Fully Registered I/O Buffers with Asynchronous Preset

Preset

Data

L

D

DOUT

Data_out

PRE

F

PRE

Y

E

Core

Array

D

Q

D

Q

C

DFN1P1

EOUT

H

I

CLK

A

PRE

J

D

Q

DFN1P1

Data Input I/O Register with:

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Preset

Postive-Edge Triggered

CLKBUF

INBUF

Figure 2-12 • Timing Model of Registered I/O Buffers with Asynchronous Preset

Revision 17

2-41

IGLOO nano DC and Switching Characteristics

Table 2-70 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

Parameter Definition

Clock-to-Q of the Output Data Register

H, DOUT

F, H

t_OSUD

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

F, H

t_OPRE2Q

t_OREMPRE

t_ORECPRE

t_OECLKQ

t_OESUD

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

L, DOUT

L, H

H, EOUT

J, H

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

t_OEHD

J, H

t_OEPRE2Q

t_OEREMPRE

t_OERECPRE

t_ICLKQ

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

I, EOUT

I, H

A, E

t_ISUD

Data Setup Time for the Input Data Register

C, A

t_IHD

Data Hold Time for the Input Data Register

C, A

t_IPRE2Q

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

D, E

t_IREMPRE

t_IRECPRE

D, A

Note: *See Figure 2-12 on page 2-41 for more information.

2-42

Revision 17

IGLOO nano Low Power Flash FPGAs

Fully Registered I/O Buffers with Asynchronous Clear

DOUT

FF

Data_out

Y

Core

D

Q

D

Q

Data

Array

CC

EE

DFN1C1

EOUT

CLR

LL

HH

CLK

CLR

AA

DD

JJ

D

Q

DFN1C1

Data Input I/O Register with

Active High Clear

CLR

Positive-Edge Triggered

Data Output Register and

Enable Output Register with

Active High Clear

Positive-Edge Triggered

INBUF

CLKBUF

Figure 2-13 • Timing Model of the Registered I/O Buffers with Asynchronous Clear

Revision 17

2-43

IGLOO nano DC and Switching Characteristics

Table 2-71 • Parameter Definition and Measuring Nodes

Measuring Nodes

(from, to)*

Parameter Name

t_OCLKQ

Parameter Definition

Clock-to-Q of the Output Data Register

HH, DOUT

FF, HH

LL, DOUT

LL, HH

HH, EOUT

JJ, HH

t_OSUD

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OCLR2Q

t_OREMCLR

t_ORECCLR

t_OECLKQ

t_OESUD

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Clock-to-Q of the Output Enable Register

Data Setup Time for the Output Enable Register

Data Hold Time for the Output Enable Register

t_OEHD

JJ, HH

t_OECLR2Q

t_OEREMCLR

t_OERECCLR

t_ICLKQ

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Clock-to-Q of the Input Data Register

II, EOUT

II, HH

AA, EE

CC, AA

DD, EE

DD, AA

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ICLR2Q

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

t_IREMCLR

t_IRECCLR

Note: *See Figure 2-13 on page 2-43 for more information.

2-44

Revision 17

IGLOO nano Low Power Flash FPGAs

Input Register

t_ICKMPWHt_ICKMPWL

50%

t_ISUD

50%

1

CLK

Data

t_IHD

50%

t_IWPRE

0

t_IREMPRE

t_IRECPRE

Preset

50%

t_IWCLR

t_IRECCLR

50%

t_IREMCLR

50%

Clear

t_IPRE2Q

50%

t_ICLKQ

50%

Out_1

t_ICLR2Q

Figure 2-14 • Input Register Timing Diagram

Timing Characteristics

1.5 V DC Core Voltage

Table 2-72 • Input Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_ICLKQ

Description

Std. Units

Clock-to-Q of the Input Data Register

0.42

0.47

0.00

0.79

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width HIGH for the Input Data Register

Clock Minimum Pulse Width LOW for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 17

2-45

IGLOO nano DC and Switching Characteristics

1.2 V DC Core Voltage

Table 2-73 • Input Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V

Description

Clock-to-Q of the Input Data Register

Parameter

t_ICLKQ

Std. Units

0.68

0.97

0.00

1.19

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_ISUD

Data Setup Time for the Input Data Register

t_IHD

Data Hold Time for the Input Data Register

t_ICLR2Q

t_IPRE2Q

t_IREMCLR

t_IRECCLR

t_IREMPRE

t_IRECPRE

t_IWCLR

Asynchronous Clear-to-Q of the Input Data Register

Asynchronous Preset-to-Q of the Input Data Register

Asynchronous Clear Removal Time for the Input Data Register

Asynchronous Clear Recovery Time for the Input Data Register

Asynchronous Preset Removal Time for the Input Data Register

Asynchronous Preset Recovery Time for the Input Data Register

Asynchronous Clear Minimum Pulse Width for the Input Data Register

Asynchronous Preset Minimum Pulse Width for the Input Data Register

Clock Minimum Pulse Width HIGH for the Input Data Register

Clock Minimum Pulse Width LOW for the Input Data Register

t_IWPRE

t_ICKMPWH

t_ICKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

2-46

Revision 17

IGLOO nano Low Power Flash FPGAs

Output Register

t

OCKMPWH OCKMPWL

50%

t

50%

CLK

t

OSUD OHD

50%

t

1

0

Data_out

Preset

t

OREMPRE

t

OWPRE

ORECPRE

50%

t

OREMCLR

t

ORECCLR

OWCLR

50%

Clear

t

OPRE2Q

50%

DOUT

t

OCLR2Q

t

OCLKQ

Figure 2-15 • Output Register Timing Diagram

Timing Characteristics

1.5 V DC Core Voltage

Table 2-74 • Output Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_OCLKQ

Description

Std. Units

Clock-to-Q of the Output Data Register

1.00

0.51

0.00

1.34

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_OSUD

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Asynchronous Clear Minimum Pulse Width for the Output Data Register

t_OWPRE

Asynchronous Preset Minimum Pulse Width for the Output Data Register

Clock Minimum Pulse Width HIGH for the Output Data Register

Clock Minimum Pulse Width LOW for the Output Data Register

t_OCKMPWH

t_OCKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 17

2-47

IGLOO nano DC and Switching Characteristics

1.2 V DC Core Voltage

Table 2-75 • Output Data Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V

Parameter

t_OCLKQ

Description

Clock-to-Q of the Output Data Register

Std. Units

1.52

1.15

0.00

1.96

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_OSUD

Data Setup Time for the Output Data Register

t_OHD

Data Hold Time for the Output Data Register

t_OCLR2Q

t_OPRE2Q

t_OREMCLR

t_ORECCLR

t_OREMPRE

t_ORECPRE

t_OWCLR

Asynchronous Clear-to-Q of the Output Data Register

Asynchronous Preset-to-Q of the Output Data Register

Asynchronous Clear Removal Time for the Output Data Register

Asynchronous Clear Recovery Time for the Output Data Register

Asynchronous Preset Removal Time for the Output Data Register

Asynchronous Preset Recovery Time for the Output Data Register

Asynchronous Clear Minimum Pulse Width for the Output Data Register

Asynchronous Preset Minimum Pulse Width for the Output Data Register

Clock Minimum Pulse Width HIGH for the Output Data Register

Clock Minimum Pulse Width LOW for the Output Data Register

t_OWPRE

t_OCKMPWH

t_OCKMPWL

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

2-48

Revision 17

IGLOO nano Low Power Flash FPGAs

Output Enable Register

t

OECKMPWH OECKMPWL

50%

CLK

t

OESUD OEHD

50%

0

1

D_Enable

t

OEWPRE

OEREMPRE

t

OERECPRE

50%

Preset

Clear

t

OERECCLR

OEREMCLR

OEWCLR

50%

t

OECLR2Q

OEPRE2Q

50%

EOUT

t

OECLKQ

Figure 2-16 • Output Enable Register Timing Diagram

Timing Characteristics

1.5 V DC Core Voltage

Table 2-76 • Output Enable Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.425 V

Parameter

t_OECLKQ

Description

Std. Units

Clock-to-Q of the Output Enable Register

0.75

0.51

0.00

1.13

0.00

0.24

0.00

0.24

0.19

0.31

0.28

ns

t_OESUD

Data Setup Time for the Output Enable Register

t_OEHD

Data Hold Time for the Output Enable Register

t_OECLR2Q

t_OEPRE2Q

t_OEREMCLR

t_OERECCLR

t_OEREMPRE

t_OERECPRE

t_OEWCLR

t_OEWPRE

Asynchronous Clear-to-Q of the Output Enable Register

Asynchronous Preset-to-Q of the Output Enable Register

Asynchronous Clear Removal Time for the Output Enable Register

Asynchronous Clear Recovery Time for the Output Enable Register

Asynchronous Preset Removal Time for the Output Enable Register

Asynchronous Preset Recovery Time for the Output Enable Register

Asynchronous Clear Minimum Pulse Width for the Output Enable Register

Asynchronous Preset Minimum Pulse Width for the Output Enable Register

t_OECKMPWHClock Minimum Pulse Width HIGH for the Output Enable Register

t_OECKMPWLClock Minimum Pulse Width LOW for the Output Enable Register

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

Revision 17

2-49

IGLOO nano DC and Switching Characteristics

1.2 V DC Core Voltage

Table 2-77 • Output Enable Register Propagation Delays

Commercial-Case Conditions: T_J= 70°C, Worst-Case VCC = 1.14 V

Parameter

t_OECLKQ

Description

Clock-to-Q of the Output Enable Register

Std. Units

1.10

1.15

0.00

1.65