AGLP030V5-FVQG128 [MICROSEMI]
Field Programmable Gate Array, 792 CLBs, 30000 Gates, 250MHz, 792-Cell, CMOS, PQFP128, 14 X 14 MM, 1 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, VQFP-128;
| 型号： | AGLP030V5-FVQG128 |
| 厂家： | 
Microsemi |
| 描述： | Field Programmable Gate Array, 792 CLBs, 30000 Gates, 250MHz, 792-Cell, CMOS, PQFP128, 14 X 14 MM, 1 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, VQFP-128 栅 |
| 文件： | 总122页 (文件大小：3945K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
v1.3
®
IGLOO PLUS Low-Power Flash FPGAs
with Flash*Freeze Technology
High-Performance Routing Hierarchy
Features and Benefits
A•dvSaegnmceendteId/O, Hierarchical Routing and Clock Structure
Low Power
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• 5 µW Power Consumption in Flash*Freeze Mode
• Low-Power Active FPGA Operation
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—4 Banks per Chip on All
®
IGLOO PLUS Devices
• Single-Ended
I/O
Standards:
LVTTL,
LVCMOS
• Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Configurable Hold Previous State, Tristate, HIGH, or LOW
State per I/O in Flash*Freeze Mode
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V
• Selectable Schmitt Trigger Inputs
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Easy Entry To / Exit From Ultra-Low-Power Flash*Freeze Mode
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/-Down
Feature Rich
• 30 k to 125 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 212 User I/Os
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Small-Footprint Packages across the IGLOO
PLUS Family
Clock Conditioning Circuit (CCC) and PLL†
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Six CCC Blocks, One with an Integrated PLL
• Configurable
Phase
Shift, Multiply/Divide,
Delay
Capabilities, and External Feedback
• Retains Programmed Design When Powered Off
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
In-System Programming (ISP) and Security
Embedded Memory
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
• 1 kbit of FlashROM User Nonvolatile Memory
†
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
®
†
• FlashLock to Secure FPGA Contents
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
†
• True Dual-Port SRAM (except ×18)
Table 1-1 • IGLOO PLUS Product Family
IGLOO PLUS Devices
AGLP030
AGLP060
60 k
512
1,584
10
AGLP125
125 k
1,024
3,120
16
System Gates
30 k
256
792
5
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM kbits (1,024 bits)
4,608-Bit Blocks
–
18
36
–
4
8
Secure (AES) ISP
–
Yes
1 k
1
Yes
1 k
FlashROM Bits
1 k
–
1
Integrated PLL in CCCs
1
2
VersaNet Globals
6
18
18
I/O Banks
4
4
4
Maximum User I/Os
120
157
212
Package Pins
CS
VQ
CS201, CS289
VQ128
CS201, CS289
VQ176
CS281, CS289
Notes:
1. AGLP060 in CS201 does not support the PLL.
2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.
†
The AGLP030 device does not support this feature.
December 2008
I
© 2009 Actel Corporation
1
I/Os Per Package
IGLOO PLUS Devices
Package
CS201
AGLP030
AGLP060
AGLP125
Single-Ended I/Os
120
–
157
–
–
212
212
–
CS281
CS289
120
101
–
157
–
VQ128
VQ176
137
–
Note: When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of
single-ended user I/Os available is reduced by one.
Table 1-2 • Package Dimensions
Package
CS201
8 × 8
64
CS281
10 × 10
100
CS289
14 × 14
196
VQ128
14 × 14
196
VQ176
20 × 20
400
Length × Width (mm/mm)
Nominal Area (mm2)
Pitch (mm)
0.5
0.5
0.8
0.4
0.4
Height (mm)
0.89
1.05
1.20
1.0
1.0
II
v1.3
IGLOO PLUS Low-Power Flash FPGAs
IGLOO PLUS Ordering Information
_
AGLP125
V2
CS
G
289
I
Application (Temperature Range)
Blank = Commercial (0°C to +70°C ambient temperature)
I = Industrial (–40°C to +85°C ambient temperature)
PP = Pre-Production
ES = Engineering Sample (room temperature only)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant Packaging
Package Type
=
=
CS
VQ
Chip Scale Package (0.5 mm and 0.8 mm pitches)
Very Thin Quad Flat Pack (0.4 mm pitch)
Speed Grade
F = 20% Slower than Standard*
Blank = Standard
Supply Voltage
2 = 1.2 V to 1.5 V
5 = 1.5 V only
Part Number
AGLP030 = 30,000 System Gates
AGLP060 = 60,000 System Gates
AGLP125 = 125,000 System Gates
Notes:
1. Marking information: IGLOO PLUS V2 devices do not have a V2 marking, but IGLOO PLUS V5 devices are marked
accordingly.
2. The DC and switching characteristics for the –F speed grade targets are based only on simulation.
The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only
supported in the Commercial temperature range.
3. "G" indicates RoHS-compliant packages.
v1.3
III
Temperature Grade Offerings
Package
CS201
CS281
CS289
VQ128
VQ176
Notes:
AGLP030
AGLP060
AGLP125
C, I
–
C, I
–
–
C, I
C, I
–
C, I
C, I
–
C, I
–
C, I
–
1. C = Commercial temperature range: 0°C to 70°C ambient temperature.
2. I = Industrial temperature range: –40°C to 85°C ambient temperature.
Speed Grade and Temperature Grade Matrix
Temperature Grade
–F 1
Std.
C 2
✓
✓
✓
3
I
–
Notes:
1. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only
supported in the Commercial temperature range.
2. C = Commercial temperature range: 0°C to 70°C ambient temperature.
3. I = Industrial temperature range: –40°C to 85°C ambient temperature.
Contact your local Actel representative for device availability:
http://www.actel.com/company/contact/default.aspx.
IV
v1.3
1 – IGLOO PLUS Device Family Overview
General Description
The IGLOO PLUS family of flash FPGAs, based on a 130 nm flash process, offers the lowest power
FPGA, a single-chip solution, small-footprint packages, reprogrammability, and an abundance of
advanced features.
The Flash*Freeze technology used in IGLOO PLUS devices enables entering and exiting an ultra-
low-power mode that consumes as little as 5 µW while retaining the design information, SRAM
content, registers, and I/O states. Flash*Freeze technology simplifies power management through
I/O and clock management with rapid recovery to operation mode.
The Low Power Active capability (static idle) allows for ultra-low-power consumption while the
IGLOO PLUS device is completely functional in the system. This allows the IGLOO PLUS device to
control system power management based on external inputs (e.g., scanning for keyboard stimulus)
while consuming minimal power.
Nonvolatile flash technology gives IGLOO PLUS devices the advantage of being a secure, low-
power, single-chip solution that is live at power-up (LAPU). IGLOO PLUS is reprogrammable and
offers time-to-market benefits at an ASIC-level unit cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
IGLOO PLUS devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well
as clock conditioning circuitry based on an integrated phase-locked loop (PLL). IGLOO PLUS devices
have up to 125 k system gates, supported with up to 36 kbits of true dual-port SRAM and up to 212
user I/Os. The AGLP030 devices have no PLL or RAM support.
Flash*Freeze Technology
The IGLOO PLUS device offers unique Flash*Freeze technology, allowing the device to enter and
exit ultra-low-power Flash*Freeze mode. IGLOO PLUS devices do not need additional components
to turn off I/Os or clocks while retaining the design information, SRAM content, registers, and I/O
states. Flash*Freeze technology is combined with in-system programmability, which enables users
to quickly and easily upgrade and update their designs in the final stages of manufacturing or in
the field. The ability of IGLOO PLUS V2 devices to support a wide range of core and I/O voltages
(1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total
system power.
During Flash*Freeze mode, each I/O can be set to the following configurations: hold previous state,
tristate, or set as HIGH or LOW.
The availability of low-power modes, combined with reprogrammability, a single-chip and single-
voltage solution, and availability of small-footprint, high-pin-count packages, make IGLOO PLUS
devices the best fit for portable electronics.
Flash Advantages
Low Power
IGLOO PLUS devices exhibit power characteristics similar to those of an ASIC, making them an ideal
choice for power-sensitive applications. IGLOO PLUS devices have only a very limited power-on
current surge and no high-current transition period, both of which occur on many FPGAs.
IGLOO PLUS devices also have low dynamic power consumption to further maximize power savings;
power is even further reduced by the use of a 1.2 V core voltage.
Low dynamic power consumption, combined with low static power consumption and Flash*Freeze
technology, gives the IGLOO PLUS device the lowest total system power offered by any FPGA.
v1.3
1-1
IGLOO PLUS Device Family Overview
Security
The nonvolatile, flash-based IGLOO PLUS devices do not require a boot PROM, so there is no
vulnerable external bitstream that can be easily copied. IGLOO PLUS devices incorporate FlashLock,
which provides a unique combination of reprogrammability and design security without external
overhead, advantages that only an FPGA with nonvolatile flash programming can offer.
IGLOO PLUS devices (except AGLP030) utilize a 128-bit flash-based lock and a separate AES key to
secure programmed intellectual property and configuration data. In addition, all FlashROM data in
IGLOO PLUS devices can be encrypted prior to loading, using the industry-leading AES-128
(FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of
Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOO PLUS devices
have a built-in AES decryption engine and a flash-based AES key that make them the most
comprehensive programmable logic device security solution available today. IGLOO PLUS devices
with AES-based security allow for secure, remote field updates over public networks such as the
Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system
cloners, and IP thieves. The contents of a programmed IGLOO PLUS device cannot be read back,
although secure design verification is possible.
Security, built into the FPGA fabric, is an inherent component of the IGLOO PLUS family. The flash
cells are located beneath seven metal layers, and many device design and layout techniques have
been used to make invasive attacks extremely difficult. The IGLOO PLUS family, with FlashLock and
AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your
valuable IP is protected and secure, making remote ISP possible. An IGLOO PLUS device provides
the most impenetrable security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,
the configuration data is an inherent part of the FPGA structure, and no external configuration
data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based
IGLOO PLUS FPGAs do not require system configuration components such as EEPROMs or
microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB
area, and increases security and system reliability.
The IGLOO PLUS devices can be operated with a 1.2 V or 1.5 V single-voltage supply for core and
I/Os, eliminating the need for additional supplies while minimizing total power consumption.
Live at Power-Up
The Actel flash-based IGLOO PLUS devices support Level 0 of the LAPU classification standard. This
feature helps in system component initialization, execution of critical tasks before the processor
wakes up, setup and configuration of memory blocks, clock generation, and bus activity
management. The LAPU feature of flash-based IGLOO PLUS devices greatly simplifies total system
design and reduces total system cost, often eliminating the need for CPLDs and clock generation
PLLs. In addition, glitches and brownouts in system power will not corrupt the IGLOO PLUS device's
flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when
system power is restored. This enables the reduction or complete removal of the configuration
PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB
design. Flash-based IGLOO PLUS devices simplify total system design and reduce cost and design
risk while increasing system reliability and improving system initialization time.
IGLOO PLUS flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done
almost instantly (within 1 µs), and the device retains configuration and data in registers and RAM.
Unlike SRAM-based FPGAs, the device does not need to reload configuration and design state from
external memory components; instead, it retains all necessary information to resume operation
immediately.
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike
SRAM-based FPGAs, flash-based IGLOO PLUS devices allow all functionality to be live at power-up;
no external boot PROM is required. On-board security mechanisms prevent access to all the
programming information and enable secure remote updates of the FPGA logic. Designers can
perform secure remote in-system reprogramming to support future design iterations and field
1-2
v1.3
IGLOO PLUS Low-Power Flash FPGAs
upgrades with confidence that valuable intellectual property cannot be compromised or copied.
Secure ISP can be performed using the industry-standard AES algorithm. The IGLOO PLUS family
device architecture mitigates the need for ASIC migration at higher user volumes. This makes the
IGLOO PLUS family a cost-effective ASIC replacement solution, especially for applications in the
consumer, networking/communications, computing, and avionics markets.
Firm-Error Immunity
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,
strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the
configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.
These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be
a complete system failure. Firm errors do not exist in the configuration memory of IGLOO PLUS
flash-based FPGAs. Once it is programmed, the flash cell configuration element of IGLOO PLUS
FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable
(or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by
using error detection and correction (EDAC) circuitry built into the FPGA fabric.
Advanced Flash Technology
The IGLOO PLUS family offers many benefits, including nonvolatility and reprogrammability,
through an advanced flash-based, 130 nm LVCMOS process with seven layers of metal. Standard
CMOS design techniques are used to implement logic and control functions. The combination of
fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very
high logic utilization without compromising device routability or performance. Logic functions
within the device are interconnected through a four-level routing hierarchy.
IGLOO PLUS family FPGAs utilize design and process techniques to minimize power consumption in
all modes of operation.
Advanced Architecture
The proprietary IGLOO PLUS architecture provides granularity comparable to standard-cell ASICs.
The IGLOO PLUS device consists of five distinct and programmable architectural features
(Figure 1-1 on page 1-4):
•
•
•
•
•
•
Flash*Freeze technology
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory†
Extensive CCCs and PLLs†
Advanced I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input
logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate
flash switch interconnections. The versatility of the IGLOO PLUS core tile as either a three-input
lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA
fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation-
architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy.
Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable
interconnect programming. Maximum core utilization is possible for virtually any design.
In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)
programming of IGLOO PLUS devices via an IEEE 1532 JTAG interface.
†
The AGLP030 device does not support PLL or SRAM.
v1.3
1-3
IGLOO PLUS Device Family Overview
Bank 0
CCC*
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block*
I/Os
VersaTile
ISP AES
Decryption*
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
Bank 2
* Not supported by AGLP030 devices
Figure 1-1 • IGLOO PLUS Device Architecture Overview with Four I/O Banks (AGLP030, AGLP060, and
AGLP125)
Flash*Freeze Technology
The IGLOO PLUS device has an ultra-low-power static mode, called Flash*Freeze mode, which
retains all SRAM and register information and can still quickly return to normal operation.
Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode
by activating the Flash*Freeze pin while all power supplies are kept at their original values. In
addition, I/Os and global I/Os can still be driven and can be toggling without impact on power
consumption, clocks can still be driven or can be toggling without impact on power consumption,
and the device retains all core registers, SRAM information, and I/O states. I/Os can be individually
configured to either hold their previous state or be tristated during Flash*Freeze mode.
Alternatively, they can be set to a certain state using weak pull-up or pull-down I/O attribute
configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device
consumes as little as 5 µW in this mode.
Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the
power management of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to
decide when it is safe to transition to this mode. Refer to Figure 1-2 for an illustration of
1-4
v1.3
IGLOO PLUS Low-Power Flash FPGAs
entering/exiting Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if
Flash*Freeze mode usage is not planned.
Actel
IGLOO PLUS
FPGA
Flash*Freeze
Mode Control
Flash*Freeze Pin
Figure 1-2 • IGLOO PLUS Flash*Freeze Mode
VersaTiles
The IGLOO PLUS core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS®
core tiles. The IGLOO PLUS VersaTile supports the following:
•
•
•
•
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-3 for VersaTile configurations.
Enable D-Flip-Flop with Clear or Set
D-Flip-Flop with Clear or Set
LUT-3 Equivalent
X1
Data
Y
Data
CLK
CLR
Y
X2
X3
LUT-3
Y
D-FF
CLK
D-FF
Enable
CLR
Figure 1-3 • VersaTile Configurations
User Nonvolatile FlashROM
Actel IGLOO PLUS devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The
FlashROM can be used in diverse system applications:
•
•
•
•
•
•
•
•
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard IGLOO PLUS IEEE 1532 JTAG programming interface.
The core can be individually programmed (erased and written), and on-chip AES decryption can be
used selectively to securely load data over public networks (except in AGLP030 devices), as in
security keys stored in the FlashROM for a user design.
v1.3
1-5
IGLOO PLUS Device Family Overview
The FlashROM can be programmed via the JTAG programming interface, and its contents can be
read back either through the JTAG programming interface or via direct FPGA core addressing. Note
that the FlashROM can only be programmed from the JTAG interface and cannot be programmed
from the internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-
byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8
banks and which of the 16 bytes within that bank are being read. The three most significant bits
(MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of
the FlashROM address define the byte.
The Actel IGLOO PLUS development software solutions, Libero® Integrated Design Environment
(IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation
of sequential programming files for applications requiring a unique serial number in each part.
Another feature allows the inclusion of static data for system version control. Data for the
FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools.
Comprehensive programming file support is also included to allow for easy programming of large
numbers of parts with differing FlashROM contents.
SRAM and FIFO
IGLOO PLUS devices (except AGLP030 devices) have embedded SRAM blocks along their north side.
Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are
256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write
ports that can be configured with different bit widths on each port. For example, data can be sent
through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized
via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in AGLP030
devices).
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the
SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The
FIFO width and depth are programmable. The FIFO also features programmable Almost Empty
(AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The
embedded FIFO control unit contains the counters necessary for generation of the read and write
address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
IGLOO PLUS devices provide designers with very flexible clock conditioning circuit (CCC)
capabilities. Each member of the IGLOO PLUS family contains six CCCs. One CCC (center west side)
has a PLL. The AGLP030 device does not have a PLL or CCCs; it contains only inputs to six globals.
The six CCC blocks are located at the four corners and the centers of the east and west sides. One
CCC (center west side) has a PLL.
The four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine
access.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
•
•
•
•
Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz
2 programmable delay types for clock skew minimization
Clock frequency synthesis (for PLL only)
Additional CCC specifications:
•
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output
divider configuration (for PLL only).
•
•
Output duty cycle = 50% 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single
global network used (for PLL only)
•
Maximum acquisition time is 300 µs (for PLL only)
1-6
v1.3
IGLOO PLUS Low-Power Flash FPGAs
•
•
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL
only)
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /
fOUT_CCC (for PLL only)
Global Clocking
IGLOO PLUS devices have extensive support for multiple clocking domains. In addition to the CCC
and PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three
quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the
core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for
rapid distribution of high-fanout nets.
v1.3
1-7
IGLOO PLUS Device Family Overview
I/Os with Advanced I/O Standards
The IGLOO PLUS family of FPGAs features a flexible I/O structure, supporting a range of voltages
(1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V). IGLOO PLUS FPGAs support many different I/O standards.
The I/Os are organized into four banks. All devices in IGLOO PLUS have four banks. The
configuration of these banks determines the I/O standards supported.
Each I/O module contains several input, output, and output enable registers.
Part Number and Revision Date
Part Number 51700102-001-3
Revised December 2008
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version
Changes in Current Version (v1.3)
Page
v1.2
(August 2008)
A note was added to Table 1-1 · IGLOO PLUS Product Family: "AGLP060 in
CS201 does not support the PLL."
I
Table 1-2 · Package Dimensions was updated to change the nominal size of
VQ176 from 100 to 400 mm2.
II
v1.1
(July 2008)
The VQ128 and VQ176 packages were added to Table 1-1 · IGLOO PLUS I to IV
Product Family, the "I/Os Per Package 1" table, Table 1-2 · Package
Dimensions, "IGLOO PLUS Ordering Information", and the "Temperature
Grade Offerings" table.
v1.0
(March 2008)
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of
core voltage support. The document was updated to change 1.2 V / 1.5 V to
1.2 V to 1.5 V.
N/A
1-8
v1.3
IGLOO PLUS Low-Power Flash FPGAs
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheets are published before data
has been fully characterized. Datasheets are designated as "Product Brief," "Advance,"
"Preliminary," and "Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains
general product information. This document gives an overview of specific device and family
information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or
speed grades. This information can be used as estimates, but not for production. This label only
applies to the DC and Switching Characteristics chapter of the datasheet and will only be used
when the data has not been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The
information is believed to be correct, but changes are possible.
Unmarked (production)
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations
(EAR). They could require an approved export license prior to export from the United States. An
export includes release of product or disclosure of technology to a foreign national inside or
outside the United States.
Actel Safety Critical, Life Support, and High-Reliability
Applications Policy
The Actel products described in this advance status document may not have completed Actel’s
qualification process. Actel may amend or enhance products during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the
responsibility of each customer to ensure the fitness of any Actel product (but especially a new
product) for a particular purpose, including appropriateness for safety-critical, life-support, and
other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability
exclusions relating to life-support applications. A reliability report covering all of Actel’s products is
available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also
offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your
local Actel sales office for additional reliability information.
v1.3
1-9
2 – IGLOO PLUS DC and Switching Characteristics
General Specifications
DC and switching characteristics for –F speed grade targets are based only on simulation.
The characteristics provided for the –F speed grade are subject to change after establishing
FPGA specifications. Some restrictions might be added and will be reflected in future revisions
of this document. The –F speed grade is only supported in the commercial temperature range.
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or
any other conditions beyond those listed under the Recommended Operating Conditions specified
in Table 2-2 on page 2-2 is not implied.
Table 2-1 • Absolute Maximum Ratings
Symbol
VCC
Parameter
DC core supply voltage
JTAG DC voltage
Limits
Units
–0.3 to 1.65
V
V
V
V
V
V
VJTAG
–0.3 to 3.75
VPUMP Programming voltage
–0.3 to 3.75
VCCPLL Analog power supply (PLL)
–0.3 to 1.65
–0.3 to 3.75
VCCI
VI
DC I/O buffer supply voltage
I/O input voltage
–0.3 V to 3.6 V (when I/O hot insertion mode is enabled)
–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower
(when I/O hot-insertion mode is disabled)
2
TSTG
Storage temperature
Junction temperature
–65 to +150
+125
°C
°C
2
TJ
Notes:
1. The device should be operated within the limits specified by the datasheet. During transitions, the input
signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.
2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for
recommended operating limits, refer to Table 2-2 on page 2-2.
Advance v0.4
2-1
IGLOO PLUS DC and Switching Characteristics
Table 2-2 • Recommended Operating Conditions 4
Symbol
Parameter
Commercial
0 to +70 6
0 to + 85
Industrial
–40 to +85 7
–40 to +100
Units
°C
°C
V
TA
TJ
Ambient temperature
Junction temperature 8
VCC
1.5 V DC core supply voltage 1
1.2 V–1.5 V wide range core voltage 2
JTAG DC voltage
1.425 to 1.575 1.425 to 1.575
1.14 to 1.575 1.14 to 1.575
3
V
VJTAG
1.4 to 3.6
3.15 to 3.45
0 to 3.45
1.4 to 3.6
3.15 to 3.45
0 to 3.45
V
5
VPUMP
Programming voltage
Programming mode
Operation
Analog power supply (PLL) 1.5 V DC core supply voltage1
V
V
9
VCCPLL
1.4 to 1.6
1.4 to 1.6
V
1.2 V–1.5 V wide range core 1.14 to 1.575 1.14 to 1.575
voltage 2
V
VCCI
1.2 V DC supply voltage 2
1.5 V DC supply voltage
1.8 V DC supply voltage
2.5 V DC supply voltage
3.3 V DC supply voltage
1.14 to 1.26
1.14 to 1.26
V
V
V
V
V
1.425 to 1.575 1.425 to 1.575
1.7 to 1.9
2.3 to 2.7
3.0 to 3.6
1.7 to 1.9
2.3 to 2.7
3.0 to 3.6
Notes:
1. For IGLOO® PLUS V5 devices
2. For IGLOO PLUS V2 devices only, operating at VCCI ≥ VCC
3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to
each I/O standard are given in Table 2-20 on page 2-19. VCCI should be at the same voltage within a given
I/O bank.
4. All parameters representing voltages are measured with respect to GND unless otherwise specified.
5. VPUMP can be left floating during operation (not programming mode).
6. Maximum TJ = 85°C.
7. Maximum TJ = 100°C.
8. To ensure targeted reliability standards are met across ambient and junction operating temperatures,
Actel recommends that the user follow best design practices using Actel’s timing and power simulation
tools.
9. VCCPLL pins should be tied to VCC pins. See Pin Descriptions for further information.
Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature 1
Program Retention
Maximum Storage
Maximum Operating Junction
Temperature TJ (°C) 2
Product Grade Programming Cycles (biased/unbiased) Temperature TSTG (°C) 2
Commercial
Industrial
Notes:
500
500
20 years
20 years
110
110
100
100
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device
operating conditions and absolute limits.
2-2
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Table 2-4 • Overshoot and Undershoot Limits 1
Average VCCI–GND Overshoot or
Undershoot Duration
Maximum Overshoot/
Undershoot2
VCCI
as a Percentage of Clock Cycle2
2.7 V or less
10%
5%
1.4 V
1.49 V
1.1 V
3 V
10%
5%
1.19 V
0.79 V
0.88 V
0.45 V
0.54 V
3.3 V
3.6 V
Notes:
10%
5%
10%
5%
1. Based on reliability requirements at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two
cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every IGLOO PLUS device. These
circuits ensure easy transition from the powered-off state to the powered-up state of the device.
The many different supplies can power up in any sequence with minimized current spikes or surges.
In addition, the I/O will be in a known state through the power-up sequence. The basic principle is
shown in Figure 2-1 on page 2-4.
There are five regions to consider during power-up.
IGLOO PLUS I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 and Figure 2-2 on
page 2-5).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V
Ramping down (V5 devices): 0.5 V < trip_point_down < 1.1 V
Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V
Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V
VCC Trip Point:
Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V
Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V
Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V
Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This
specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note
the following:
•
•
During programming, I/Os become tristated and weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
Advance v0.4
2-3
IGLOO PLUS DC and Switching Characteristics
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-
up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout
activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V
0.25 V for V5 devices, and 0.75 V 0.2 V for V2 devices), the PLL output lock signal goes LOW
and/or the output clock is lost. Refer to the "Brownout Voltage" section in the Power-Up/-Down
Behavior of Low-Power Flash Devices chapter of the ProASIC3 and ProASIC3E handbooks for
information on clock and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
To make sure the transition from input buffers to output buffers is clean, ensure that there is no
path longer than 100 ns from input buffer to output buffer in your design.
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 4: I/O
buffers are ON.
I/Os are functional
Region 1: I/O Buffers are OFF
I/Os meet the entire datasheet
and timer specifications for
speed, VIH/VIL , VOH/VOL , etc.
(except differential inputs)
but slower because VCCI is
below specification. For the
same reason, input buffers do not
meet VIH/VIL levels, and output
buffers do not meet VOH/VOL levels.
VCC = 1.425 V
Region 2: I/O buffers are ON.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
I/Os are functional (except differential inputs)
but slower because VCCI/VCC are below
specification. For the same reason, input
buffers do not meet VIH/VIL levels, and
output buffers do not meet VOH/VOL levels.
Activation trip point:
V
a = 0.85 V 0.25 V
Deactivation trip point:
d = 0.75 V 0.25 V
Region 1: I/O buffers are OFF
V
VCCI
Activation trip point:
Min VCCI datasheet specification
Va = 0.9 V 0.3 V
Deactivation trip point:
Vd = 0.8 V 0.3 V
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
2-4
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
VCC = VCCI + VT
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCC
V
CC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
Region 1: I/O Buffers are OFF
I/Os meet the entire datasheet
and timer specifications for
speed, VIH/VIL , VOH/VOL , etc.
but slower because VCCI is
below specification. For the
same reason, input buffers do not
meet VIH/VIL levels, and output
buffers do not meet VOH/VOL levels.
VCC = 1.14 V
Region 2: I/O buffers are ON.
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
I/Os are functional (except differential inputs)
but slower because VCCI/VCC are below
specification. For the same reason, input
buffers do not meet VIH/VIL levels, and
output buffers do not meet VOH/VOL levels.
Activation trip point:
Va = 0.85 V 0.2 V
Deactivation trip point:
Region 1: I/O buffers are OFF
Vd = 0.75 V 0.2 V
VCCI
Activation trip point:
Va = 0.9 V 0.15 V
Deactivation trip point:
Vd = 0.8 V 0.15 V
Min VCCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.14 V,1.425 V, 1.7 V,
2.3 V, or 3.0 V
Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
Advance v0.4
2-5
IGLOO PLUS DC and Switching Characteristics
Thermal Characteristics
Introduction
The temperature variable in the Actel Designer software refers to the junction temperature, not
the ambient temperature. This is an important distinction because dynamic and static power
consumption cause the chip junction temperature to be higher than the ambient temperature.
EQ 2-1 can be used to calculate junction temperature.
TJ = Junction Temperature = ∆T + TA
EQ 2-1
where:
TA = Ambient temperature
∆T = Temperature gradient between junction (silicon) and ambient ∆T = θja * P
θ
ja = Junction-to-ambient of the package. θja numbers are located in Figure 2-5.
P = Power dissipation
Package Thermal Characteristics
The device junction-to-case thermal resistivity is θjc and the junction-to-ambient air thermal
resistivity is θja. The thermal characteristics for θja are shown for two air flow rates. The maximum
operating junction temperature is 100°C. EQ 2-2 shows a sample calculation of the maximum
operating power dissipation allowed for a 484-pin FBGA package at commercial temperature and
in still air.
Max. junction temp. (° C) – Max. ambient temp. (° C)
100° C – 70° C
Maximum Power Allowed = ---------------------------------------------------------------------------------------------------------------------------------------- = -------------------------------------- = 1 . 4 6 W
θja(° C/W)
20.5°C/W
EQ 2-2
Table 2-5 • Package Thermal Resistivities
θja
Pin
Count
200 ft./
min.
500 ft./
min.
Package Type
θjc
Still Air
TBD
Units
C/W
C/W
C/W
Chip Scale Package (CSP)
201
281
289
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Temperature and Voltage Derating Factors
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C,
CC = 1.425 V)
V
For IGLOO PLUS V2 or V5 devices, 1.5 V DC Core Supply Voltage
Junction Temperature (°C)
Array Voltage
VCC (V)
1.425
1.5
–40°C
0.95
0.87
0.81
0°C
0.97
0.89
0.83
25°C
0.98
0.90
0.84
70°C
1.00
0.92
0.86
85°C
1.01
0.93
0.87
110°C
1.02
0.94
0.87
1.575
2-6
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C,
VCC = 1.14 V)
For IGLOO PLUS V2, 1.2 V DC Core Supply Voltage
Junction Temperature (°C)
Array Voltage
VCC (V)
1.14
1.2
–40°C
0.97
0.86
0.79
0°C
0.98
0.87
0.80
25°C
0.99
0.88
0.81
70°C
1.00
0.89
0.81
85°C
1.01
0.89
0.82
110°C
1.01
0.90
0.82
1.26
Calculating Power Dissipation
Quiescent Supply Current
Quiescent supply current (IDD) calculation depends on multiple factors, including operating
voltages (VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power mode
usage. Actel recommends using the Power Calculator and SmartPower software estimation tools to
evaluate the projected static and active power based on the user design, power mode usage,
operating voltage, and temperature.
Table 2-8 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Flash*Freeze Mode*
Core Voltage
1.2 V
AGLP030
AGLP060
AGLP125
Units
µA
Typical (25°C)
4
6
8
13
18
1.5 V
10
µA
* IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents.
Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Sleep Mode (VCC = 0 V)*
Core Voltage
AGLP030 AGLP060 AGLP125 Units
V
CCI/VJTAG = 1.2 V (per bank) Typical
1.2 V
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
µA
µA
µA
µA
µA
(25°C)
VCCI/VJTAG = 1.5 V (per bank) Typical
(25°C)
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
VCCI/VJTAG = 1.8 V (per bank) Typical
(25°C)
VCCI/VJTAG = 2.5 V (per bank) Typical
(25°C)
VCCI/VJTAG = 3.3 V (per bank) Typical
(25°C)
* IDD includes VCC, VPUMP, and VCCPLL currents.
Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Shutdown Mode (VCC
,
VCCI = 0 V)*
Core Voltage
AGLP030
AGLP060
AGLP125
Units
Typical (25°C)
1.2 V / 1.5 V
0
0
0
µA
* IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents.
Advance v0.4
2-7
IGLOO PLUS DC and Switching Characteristics
Table 2-11 • Quiescent Supply Current (IDD), No IGLOO PLUS Flash*Freeze Mode 1
Core Voltage AGLP030 AGLP060 AGLP125 Units
ICCA Current 2
Typical (25°C)
1.2 V
1.5 V
6
10
20
13
28
µA
µA
16
ICCI or IJTAG Current 3
VCCI / VJTAG = 1.2 V (per bank)
Typical (25°C)
1.2 V
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
1.7
1.8
1.9
2.2
2.5
µA
µA
µA
µA
µA
VCCI / VJTAG = 1.5 V (per bank)
Typical (25°C)
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
1.2 V / 1.5 V
VCCI / VJTAG = 1.8 V (per bank)
Typical (25°C)
VCCI / VJTAG = 2.5 V (per bank)
Typical (25°C)
VCCI / VJTAG = 3.3 V (per bank)
Typical (25°C)
Notes:
1. To calculate total device IDD, multiply the number of banks used by ICCI and add ICCA
contribution.
2. Includes VCC, VCCPLL, and VPUMP currents.
3. Per VCCI or VJTAG bank
Power per I/O Pin
Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Dynamic Power
VCCI (V)
PAC9 (µW/MHz) 1
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger
2.5 V LVCMOS
3.3
3.3
2.5
2.5
1.8
1.8
1.5
1.5
1.2
1.2
16.88
19.54
5.20
6.60
2.22
2.29
1.57
1.49
0.55
0.47
2.5 V LVCMOS – Schmitt Trigger
1.8 V LVCMOS
1.8 V LVCMOS – Schmitt Trigger
1.5 V LVCMOS (JESD8-11)
1.5 V LVCMOS (JESD8-11) – Schmitt Trigger
1.2 V LVCMOS 2
1.2 V LVCMOS 2 – Schmitt Trigger
Notes:
1. PAC9 is the total dynamic power measured on VCCI
2. Applicable to IGLOO PLUS V2 devices only.
.
2-8
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Table 2-13 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
Dynamic Power
PAC10 (µW/MHz)2
C
LOAD (pF)
VCCI (V)
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
5
5
5
5
5
3.3
2.5
1.8
1.5
1.2
128.60
72.14
36.94
25.65
15.22
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
1.2 V LVCMOS3
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output
slew.
2. PAC10 is the total dynamic power measured on VCCI
.
3. Applicable for IGLOO PLUS V2 devices only.
Power Consumption of Various Internal Resources
Table 2-14 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices
For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage
Device Specific Dynamic Power
(µW/MHz)
Parameter
PAC1
Definition
Clock contribution of a Global Rib
AGLP125 AGLP060 AGLP030
11.03
0.81
9.3
0.81
0.81
0.11
0.057
0.207
0.17
0.7
9.3
PAC2
Clock contribution of a Global Spine
0.41
PAC3
Clock contribution of a VersaTile row
PAC4
Clock contribution of a VersaTile used as a sequential module
First contribution of a VersaTile used as a sequential module
Second contribution of a VersaTile used as a sequential module
Contribution of a VersaTile used as a combinatorial module
Average contribution of a routing net
PAC5
PAC6
PAC7
PAC8
PAC9
Contribution of an I/O input pin (standard-dependent)
Contribution of an I/O output pin (standard-dependent)
Average contribution of a RAM block during a read operation
Average contribution of a RAM block during a write operation
Dynamic contribution for PLL
See Table 2-12 on page 2-8.
PAC10
PAC11
PAC12
PAC13
See Table 2-13.
25.00
30.00
2.70
Advance v0.4
2-9
IGLOO PLUS DC and Switching Characteristics
Table 2-15 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices
For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage
Device -Specific Static Power (mW)
Parameter
PDC1
Definition
AGLP125
AGLP060
AGLP030
Array static power in Active mode
Array static power in Static (Idle) mode
Array static power in Flash*Freeze mode
Static PLL contribution
See Table 2-11 on page 2-8
See Table 2-11 on page 2-8
See Table 2-8 on page 2-7
1.84
PDC2
PDC3
2
PDC4
PDC5
Bank quiescent power (VCCI-dependent)
See Table 2-11 on page 2-8
Notes:
1. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power
spreadsheet calculator or the SmartPower tool in Actel Libero® Integrated Design Environment (IDE).
2. Minimum contribution of the PLL when running at lowest frequency.
Table 2-16 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices
For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage
Device-Specific Dynamic Power
(µW/MHz)
Parameter
PAC1
Definition
Clock contribution of a Global Rib
AGLP125 AGLP060 AGLP030
7.07
0.52
5.96
0.52
5.96
0.26
PAC2
Clock contribution of a Global Spine
PAC3
Clock contribution of a VersaTile row
0.52
PAC4
Clock contribution of a VersaTile used as a sequential module
First contribution of a VersaTile used as a sequential module
Second contribution of a VersaTile used as a sequential module
Contribution of a VersaTile used as a combinatorial module
Average contribution of a routing net
0.07
0.045
0.186
0.11
PAC5
PAC6
PAC7
PAC8
0.45
PAC9
Contribution of an I/O input pin (standard-dependent)
Contribution of an I/O output pin (standard-dependent)
Average contribution of a RAM block during a read operation
Average contribution of a RAM block during a write operation
Dynamic contribution for PLL
See Table 2-12 on page 2-8
PAC10
PAC11
PAC12
PAC13
See Table 2-13 on page 2-9
25.00
30.00
2.10
2-10
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Table 2-17 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices
For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage
Device-Specific Static Power (mW)
Parameter
PDC1
Definition
AGLP125
AGLP060
AGLP030
Array static power in Active mode
Array static power in Static (Idle) mode
Array static power in Flash*Freeze mode
Static PLL contribution
See Table 2-11 on page 2-8
See Table 2-11 on page 2-8
See Table 2-8 on page 2-7
0.90
PDC2
PDC3
2
PDC4
PDC5
Bank quiescent power (VCCI-dependent)
See Table 2-11 on page 2-8
Notes:
1. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power
spreadsheet calculator or the SmartPower tool in Actel Libero IDE.
2. Minimum contribution of the PLL when running at lowest frequency.
Advance v0.4
2-11
IGLOO PLUS DC and Switching Characteristics
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For
more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE
software.
The power calculation methodology described below uses the following variables:
•
The number of PLLs as well as the number and the frequency of each output clock
generated
•
•
•
•
•
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-18 on
page 2-14.
•
•
Enable rates of output buffers—guidelines are provided for typical applications in
Table 2-19 on page 2-14.
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-19 on page 2-14. The calculation should be repeated for each clock domain defined
in the design.
Methodology
Total Power Consumption—P
TOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
PDYN is the total dynamic power consumption.
Total Static Power Consumption—P
STAT
PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5
NBANKS is the number of I/O banks powered in the design.
Total Dynamic Power Consumption—P
DYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—P
CLOCK
PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided
in Table 2-18 on page 2-14.
N
ROW is the number of VersaTile rows used in the design—guidelines are provided in
Table 2-18 on page 2-14.
CLK is the global clock signal frequency.
S-CELL is the number of VersaTiles used as sequential modules in the design.
AC1, PAC2, PAC3, and PAC4 are device-dependent.
F
N
P
Sequential Cells Contribution—P
S-CELL
PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a
multi-tile sequential cell is used, it should be accounted for as 1.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on
page 2-14.
FCLK is the global clock signal frequency.
2-12
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Combinatorial Cells Contribution—P
C-CELL
PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on
page 2-14.
FCLK is the global clock signal frequency.
Routing Net Contribution—P
NET
PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on
page 2-14.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution—P
INPUTS
PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-18 on page 2-14.
F
CLK is the global clock signal frequency.
I/O Output Buffer Contribution—P
OUTPUTS
POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-18 on page 2-14.
β1 is the I/O buffer enable rate—guidelines are provided in Table 2-19 on page 2-14.
F
CLK is the global clock signal frequency.
RAM Contribution—P
MEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3
NBLOCKS is the number of RAM blocks used in the design.
F
READ-CLOCK is the memory read clock frequency.
β2 is the RAM enable rate for read operations.
WRITE-CLOCK is the memory write clock frequency.
F
β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-19
on page 2-14.
PLL Contribution—P
PLL
PPLL = PDC4 + PAC13 *FCLKOUT
FCLKOUT is the output clock frequency.1
1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its
corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution.
Advance v0.4
2-13
IGLOO PLUS DC and Switching Characteristics
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.
If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency.
Below are some examples:
•
•
The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at
half of the clock frequency.
The average toggle rate of an 8-bit counter is 25%:
–
–
–
–
–
–
Bit 0 (LSB) = 100%
Bit 1
Bit 2
…
= 50%
= 25%
Bit 7 (MSB) = 0.78125%
Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled.
When nontristate output buffers are used, the enable rate should be 100%.
Table 2-18 • Toggle Rate Guidelines Recommended for Power Calculation
Component
Definition
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Guideline
10%
α1
α2
10%
Table 2-19 • Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
I/O output buffer enable rate
Guideline
100%
β1
β2
β3
RAM enable rate for read operations
RAM enable rate for write operations
12.5%
12.5%
2-14
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
User I/O Characteristics
Timing Model
I/O Module
(Non-Registered)
Combinational Cell
Y
Combinational Cell
Y
LVCMOS 2.5V Output Drive
Strength = 12 mA High Slew Rate
t
= 1.40 ns
t
= 0.89 ns
PD
PD
t
= 1.62 ns
DP
I/O Module
(Non-Registered)
Combinational Cell
Y
Output drive strength = 12 mA
High slew rate
LVTTL
t
= 1.62 ns
DP
t
= 1.98 ns
PD
I/O Module
(Non-Registered)
Combinational Cell
Y
I/O Module
(Registered)
Output drive strength = 8 mA
High slew rate
LVTTL
t
= 1.06 ns
PY
t
= 1.70 ns
DP
t
= 1.24 ns
PD
I/O Module
(Non-Registered)
Input LVCMOS 2.5 V
D
Q
Combinational Cell
Y
Output drive strength = 4 mA
High slew rate
LVCMOS 1.5 V
t
t
= 0.63 ns
ICLKQ
ISUD
t
= 2.07 ns
DP
t
= 0.86 ns
= 0.18 ns
PD
Input LVTTL
Clock
I/O Module
(Registered)
Register Cell
Register Cell
Combinational Cell
Y
t
= 0.85 ns
PY
D
Q
D
Q
D
t
Q
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate
I/O Module
t
= 0.87 ns
PD
t
= 1.62 ns
(Non-Registered)
DP
t
t
= 0.80 ns
= 0.84 ns
CLKQ
= 0.89 ns
= 0.18 ns
t
t
= 0.80 ns
= 0.84 ns
OCLKQ
CLKQ
SUD
t
LVCMOS 1.5 V
OSUD
SUD
Input LVTTL
Clock
Input LVTTL
Clock
t
= 1.15 ns
PY
t
= 0.85 ns
t
= 0.85 ns
PY
PY
Figure 2-3 • Timing Model
Operating Conditions: STD Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case
VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices
Advance v0.4
2-15
IGLOO PLUS DC and Switching Characteristics
tPY
tDIN
D
Q
PAD
DIN
Y
CLK
To Array
I/O Interface
tPY = MAX(tPY(R), tPY(F))
tDIN = MAX(tDIN(R), tDIN(F))
VIH
Vtrip
Vtrip
VCC
VIL
PAD
Y
50%
50%
GND
tPY
(R)
tPY
(F)
VCC
50%
50%
DIN
GND
tDOUT
(R)
tDOUT
(F)
Figure 2-4 • Input Buffer Timing Model and Delays (example)
2-16
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
tDOUT
D Q
tDP
PAD
DOUT
CLK
Std
Load
D
From Array
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
I/O Interface
tDOUT
tDOUT
(F)
VCC
(R)
50%
50%
D
0 V
VCC
50%
50%
DOUT
PAD
0 V
VOH
Vtrip
Vtrip
VOL
tDP
(R)
tDP
(F)
Figure 2-5 • Output Buffer Model and Delays (example)
Advance v0.4
2-17
IGLOO PLUS DC and Switching Characteristics
t
EOUT
D
Q
CLK
t , t , t , t , t , t
E
ZL ZH HZ LZ ZLS ZHS
EOUT
D
Q
PAD
DOUT
t
CLK
D
= MAX(t
(r), t
(f))
V
I/O Interface
EOUT
EOUT
EOUT
V
CC
D
E
CC
50%
50%
t
EOUT (F)
t
EOUT (R)
V
CC
50%
50%
50%
ZH
50%
t
LZ
EOUT
PAD
t
t
t
ZL
V
HZ
CCI
90% V
CCI
V
V
trip
trip
V
10% V
OL
CCI
V
CC
D
E
V
CC
50%
50%
t
t
EOUT (F)
EOUT (R)
V
CC
50%
50%
EOUT
PAD
50%
t
ZHS
t
V
ZLS
OH
V
V
trip
trip
V
OL
Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)
2-18
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
VIL
Max, V
VIH
Min, V
VOL
Max, V
0.4
VOH
Min, V
2.4
IOL IOH
mA mA
12 12
Drive
Slew
I/O Standard
Strength Rate Min, V
Max, V
3.3 V LVTTL /
3.3 V LVCMOS
12 mA High
–0.3
–0.3
0.8
2
3.6
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS2
Notes:
12 mA High
0.7
1.7
2.7
1.9
0.7
1.7
12 12
8 mA
4 mA
2 mA
High
High
High
–0.3 0.35 * VCCI 0.65 * VCCI
0.45
VCCI – 0.45
8
4
2
8
4
2
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
1.26
0.25 * VCCI 0.75 * VCCI
1. Currents are measured at 85°C junction temperature.
2. Applicable to IGLOO PLUS V2 devices operating at VCCI ≥ VCC
Table 2-21 • Summary of Maximum and Minimum DC Input Levels
Applicable to Commercial and Industrial Conditions
Commercial1
Industrial2
IIL
IIH
µA
10
10
10
10
10
IIL
µA
15
15
15
15
15
IIH
µA
15
15
15
15
15
DC I/O Standards
µA
10
10
10
10
10
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS3
Notes:
1. Commercial range (0°C < TA < 70°C)
2. Industrial range (–40°C < TA < 85°C)
3. Applicable to IGLOO PLUS V2 devices operating at VCCI ≥ VCC
Advance v0.4
2-19
IGLOO PLUS DC and Switching Characteristics
Summary of I/O Timing Characteristics – Default I/O Software Settings
Table 2-22 • Summary of AC Measuring Points
Standard
Measuring Trip Point (Vtrip
)
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.4 V
1.2 V
1.8 V LVCMOS
0.90 V
0.75 V
0.60 V
1.5 V LVCMOS
1.2 V LVCMOS
Table 2-23 • I/O AC Parameter Definitions
Parameter
Parameter Definition
Data to Pad delay through the Output Buffer
Pad to Data delay through the Input Buffer
tDP
tPY
tDOUT
tEOUT
tDIN
tHZ
Data to Output Buffer delay through the I/O interface
Enable to Output Buffer Tristate Control delay through the I/O interface
Input Buffer to Data delay through the I/O interface
Enable to Pad delay through the Output Buffer—HIGH to Z
Enable to Pad delay through the Output Buffer—Z to HIGH
Enable to Pad delay through the Output Buffer—LOW to Z
Enable to Pad delay through the Output Buffer—Z to LOW
Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH
Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW
tZH
tLZ
tZL
tZHS
tZLS
2-20
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings, STD Speed Grade,
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
3.3 V LVTTL /
12 mA High 5 pF
–
0.97 1.62 0.18 0.85 1.14 0.66 1.65 1.27 2.20 2.64 ns
3.3 V LVCMOS
2.5 V LVCMOS 12 mA High 5 pF
–
–
–
0.97 1.62 0.18 1.06 1.22 0.66 1.65 1.34 2.22 2.56 ns
0.97 1.82 0.18 0.99 1.43 0.66 1.85 1.53 2.29 2.54 ns
0.97 2.07 0.18 1.15 1.62 0.66 2.10 1.71 2.37 2.57 ns
1.8 V LVCMOS
1.5 V LVCMOS
Notes:
8 mA High 5 pF
4 mA High 5 pF
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings, STD Speed Grade,
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
3.3 V LVTTL /
12 mA High 5 pF
–
0.98 2.16 0.19 0.99 1.37 0.67 2.20 1.74 2.64 3.37 ns
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS2
Notes:
12 mA High 5 pF
8 mA High 5 pF
4 mA High 5 pF
2 mA High 5 pF
–
–
–
–
0.98 2.13 0.19 1.20 1.40 0.67 2.17 1.77 2.65 3.25 ns
0.98 2.25 0.19 1.12 1.60 0.67 2.30 1.92 2.70 3.15 ns
0.98 2.48 0.19 1.26 1.79 0.67 2.52 2.10 2.77 3.14 ns
0.98 2.68 0.19 1.56 2.34 0.67 2.73 2.24 2.53 2.67 ns
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
2. Applicable to IGLOO PLUS V2 devices operating at VCCI ≥ VCC
.
Advance v0.4
2-21
IGLOO PLUS DC and Switching Characteristics
Detailed I/O DC Characteristics
Table 2-26 • Input Capacitance
Symbol
CIN
Definition
Conditions
Min.
Max.
Units
pF
Input capacitance
VIN = 0, f = 1.0 MHz
VIN = 0, f = 1.0 MHz
8
8
CINCLK
Input capacitance on the clock pin
pF
Table 2-27 • I/O Output Buffer Maximum Resistances 1
RPULL-DOWN
RPULL-UP
Standard
3.3
Drive Strength
2 mA
(Ω) 2
(Ω) 3
V
LVTTL
/
3.3V
100
100
50
300
300
150
150
75
LVCMOS
4 mA
6 mA
8m A
50
12 mA
16 mA
2 mA
25
25
75
2.5 V LVCMOS
100
100
50
200
200
100
100
50
4 mA
6 mA
8 mA
50
12 mA
2 mA
25
1.8 V LVCMOS
1.5 V LVCMOS
200
100
50
225
112
56
4 mA
6 mA
8 mA
50
56
2 mA
200
100
TBD
224
112
TBD
4 mA
1.2 V LVCMOS
2 mA
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design considerations
and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at
http://www.actel.com/download/ibis/default.aspx.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
2-22
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Table 2-28 • I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
1
2
R(WEAK PULL-UP)
R(WEAK PULL-DOWN)
(Ω)
(Ω)
VCCI
Min.
10 k
11 k
18 k
19 k
TBD
Max.
45 k
55 k
70 k
90 k
TBD
Min.
Max.
45 k
3.3 V
2.5 V
1.8 V
1.5 V
1.2 V
Notes:
10 k
12 k
17 k
19 k
TBD
74 k
110 k
140 k
TBD
1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN)
2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN)
Table 2-29 • I/O Short Currents IOSH/IOSL
Drive Strength
IOSL (mA)*
IOSH (mA)*
3.3 V LVTTL / 3.3 V LVCMOS
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
2 mA
25
25
51
51
103
103
16
16
32
32
65
9
27
27
54
54
109
109
18
2.5 V LVCMOS
18
37
37
74
1.8 V LVCMOS
1.5 V LVCMOS
11
17
35
35
13
25
TBD
22
44
44
16
33
1.2 V LVCMOS
TBD
* TJ = 100°C
Advance v0.4
2-23
IGLOO PLUS DC and Switching Characteristics
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 110°C, the short current condition would have to be sustained for more than three
months to cause a reliability concern. The I/O design does not contain any short circuit protection,
but such protection would only be needed in extremely prolonged stress conditions.
Table 2-30 • Duration of Short Circuit Event before Failure
Temperature
–40°C
0°C
Time before Failure
> 20 years
> 20 years
> 20 years
5 years
25°C
70°C
85°C
2 years
100°C
110°C
6 months
3 months
Table 2-31 • Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (typ.)
240 mV
3.3 V LVTTL/LVCMOS (Schmitt trigger mode)
2.5 V LVCMOS (Schmitt trigger mode)
1.8 V LVCMOS (Schmitt trigger mode)
1.5 V LVCMOS (Schmitt trigger mode)
1.2 V LVCMOS (Schmitt trigger mode)
140 mV
80 mV
60 mV
40 mV
Table 2-32 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Rise/Fall Time Input Rise/Fall Time
Input Buffer
(min.)
(max.)
Reliability
LVTTL/LVCMOS (Schmitt trigger
disabled)
No requirement
10 ns *
20 years (100°C)
LVTTL/LVCMOS (Schmitt trigger
enabled)
No requirement
No requirement, but
input noise voltage
cannot exceed
20 years (100°C)
Schmitt hysteresis.
* The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the
noise is low, then the rise time and fall time of input buffers can be increased beyond the
maximum value. The longer the rise/fall times, the more susceptible the input signal is to the
board noise. Actel recommends signal integrity evaluation/characterization of the system to
ensure that there is no excessive noise coupling into input signals.
2-24
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer.
Table 2-33 • Minimum and Maximum DC Input and Output Levels
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL IIH
Drive
Strength
Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
Notes:
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0.8
0.8
0.8
0.8
0.8
0.8
2
2
2
2
2
2
3.6
3.6
3.6
3.6
3.6
3.6
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
2.4
2.4
2.4
2.4
2
4
6
2
25
25
27
27
10 10
10 10
10 10
10 10
10 10
10 10
4
6
51
54
8
8
51
54
12 12
16 16
103
103
109
109
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ/tZH/tZHS
Test Point
5 pF
Enable Path
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
Figure 2-7 • AC Loading
Table 2-34 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
CLOAD (pF)
0
3.3
1.4
5
* Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.
Advance v0.4
2-25
IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-35 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
STD
0.97 3.33 0.18 0.85 1.14
0.97 2.83 0.18 0.85 1.14
0.97 2.83 0.18 0.85 1.14
0.97 2.48 0.18 0.85 1.14
0.97 2.48 0.18 0.85 1.14
0.66 3.39 2.95 1.82 1.87
0.66 2.88 2.65 2.04 2.27
0.66 2.88 2.65 2.04 2.27
0.66 2.52 2.38 2.20 2.53
0.66 2.52 2.38 2.20 2.53
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
STD
0.97 1.84 0.18 0.85 1.14
0.97 1.70 0.18 0.85 1.14
0.97 1.70 0.18 0.85 1.14
0.97 1.62 0.18 0.85 1.14
0.97 1.62 0.18 0.85 1.14
0.66 1.88 1.43 1.81 1.98
0.66 1.73 1.32 2.04 2.38
0.66 1.73 1.32 2.04 2.38
0.66 1.65 1.27 2.20 2.64
0.66 1.65 1.27 2.20 2.64
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
2-26
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
STD
0.98 3.92 0.19 0.99 1.37
0.98 3.40 0.19 0.99 1.37
0.98 3.40 0.19 0.99 1.37
0.98 3.04 0.19 0.99 1.37
0.98 3.04 0.19 0.99 1.37
0.67 3.99 3.47 2.25 2.56
0.67 3.47 3.15 2.48 2.97
0.67 3.47 3.15 2.48 2.97
0.67 3.10 2.88 2.64 3.24
0.67 3.10 2.88 2.64 3.24
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
STD
0.98 2.39 0.19 0.99 1.37
0.98 2.24 0.19 0.99 1.37
0.98 2.24 0.19 0.99 1.37
0.98 2.16 0.19 0.99 1.37
0.98 2.16 0.19 0.99 1.37
0.67 2.43 1.91 2.24 2.68
0.67 2.28 1.80 2.48 3.10
0.67 2.28 1.80 2.48 3.10
0.67 2.20 1.74 2.64 3.37
0.67 2.20 1.74 2.64 3.37
ns
ns
ns
ns
ns
6 mA
8 mA
12 mA
16 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.4
2-27
IGLOO PLUS DC and Switching Characteristics
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.
Table 2-39 • Minimum and Maximum DC Input and Output Levels
2.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL
IIH
Drive
Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
–0.3
–0.3
–0.3
–0.3
–0.3
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
2.7
2.7
2.7
2.7
2.7
0.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
1.7
1.7
2
2
4
6
8
16
16
32
32
65
18
18
37
37
74
10 10
10 10
10 10
10 10
10 10
4
6
8
12 12
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ/tZH/tZHS
Test Point
5 pF
Enable Path
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
Figure 2-8 • AC Loading
Table 2-40 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
CLOAD (pF)
0
2.5
1.2
5
* Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.
2-28
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-41 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.97 3.80 0.18 1.06 1.22
0.97 3.21 0.18 1.06 1.22
0.97 3.21 0.18 1.06 1.22
0.97 2.80 0.18 1.06 1.22
0.66 3.87 3.47 1.80 1.70
0.66 3.27 3.11 2.05 2.17
0.66 3.27 3.11 2.05 2.17
0.66 2.85 2.79 2.22 2.48
ns
ns
ns
ns
6 mA
8 mA
12 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-42 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.97 1.90 0.18 1.06 1.22
0.97 1.73 0.18 1.06 1.22
0.97 1.73 0.18 1.06 1.22
0.97 1.62 0.18 1.06 1.22
0.66 1.93 1.57 1.79 1.77
0.66 1.76 1.42 2.04 2.25
0.66 1.76 1.42 2.04 2.25
0.66 1.65 1.34 2.22 2.56
ns
ns
ns
ns
6 mA
8 mA
12 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.4
2-29
IGLOO PLUS DC and Switching Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-43 • 2.5 LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.98 4.37 0.19 1.20 1.40
0.98 3.76 0.19 1.20 1.40
0.98 3.76 0.19 1.20 1.40
0.98 3.34 0.19 1.20 1.40
0.67 4.45 3.95 2.21 2.35
0.67 3.83 3.59 2.47 2.83
0.67 3.83 3.59 2.47 2.83
0.67 3.41 3.26 2.65 3.15
ns
ns
ns
ns
6 mA
8 mA
12 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-44 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Drive Strength
4 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.98 2.42 0.19 1.20 1.40
0.98 2.24 0.19 1.20 1.40
0.98 2.24 0.19 1.20 1.40
0.98 2.13 0.19 1.20 1.40
0.67 2.46 2.01 2.21 2.44
0.67 2.28 1.85 2.46 2.93
0.67 2.28 1.85 2.46 2.93
0.67 2.17 1.77 2.65 3.25
ns
ns
ns
ns
6 mA
8 mA
12 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
2-30
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.
Table 2-45 • Minimum and Maximum DC Input and Output Levels
1.8 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL IIH
Drive
Strength Min., V Max., V
Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
2 mA
4 mA
6 mA
8 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI
1.9
1.9
1.9
1.9
0.45
0.45
0.45
0.45
VCCI – 0.45
VCCI – 0.45
VCCI – 0.45
VCCI – 0.45
2
4
2
4
9
11
22
44
44
10 10
10 10
10 10
10 10
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI
17
35
35
6
6
8
8
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ/tZH/tZHS
Test Point
5 pF
Enable Path
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
Figure 2-9 • AC Loading
Table 2-46 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.8
0.9
5
* Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.
Advance v0.4
2-31
IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-47 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ
Units
ns
STD
STD
STD
STD
0.97 5.11 0.18 0.99 1.43
0.97 4.31 0.18 0.99 1.43
0.97 3.78 0.18 0.99 1.43
0.97 3.78 0.18 0.99 1.43
0.66 5.20 4.48 1.78 1.30
0.66 4.39 4.04 2.08 2.07
0.66 3.85 3.63 2.29 2.46
0.66 3.85 3.63 2.29 2.46
4 mA
ns
6 mA
ns
8 mA
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-48 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.97 2.21 0.18 0.99 1.43
0.97 1.97 0.18 0.99 1.43
0.97 1.82 0.18 0.99 1.43
0.97 1.82 0.18 0.99 1.43
0.66 2.25 1.86 1.78 1.35
0.66 2.01 1.64 2.08 2.15
0.66 1.85 1.53 2.29 2.54
0.66 1.85 1.53 2.29 2.54
ns
ns
ns
ns
4 mA
6 mA
8 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
2-32
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-49 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.98 5.61 0.19 1.12 1.60
0.98 4.80 0.19 1.12 1.60
0.98 4.25 0.19 1.12 1.60
0.98 4.25 0.19 1.12 1.60
0.67 5.71 4.96 2.18 1.87
0.67 4.89 4.50 2.49 2.67
0.67 4.33 4.09 2.71 3.06
0.67 4.33 4.09 2.71 3.06
ns
ns
ns
ns
4 mA
6 mA
8 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-50 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
STD
STD
0.98 2.66 0.19 1.12 1.60
0.98 2.41 0.19 1.12 1.60
0.98 2.25 0.19 1.12 1.60
0.98 2.25 0.19 1.12 1.60
0.67 2.71 2.27 2.18 1.92
0.67 2.46 2.04 2.49 2.75
0.67 2.30 1.92 2.70 3.15
0.67 2.30 1.92 2.70 3.15
ns
ns
ns
ns
4 mA
6 mA
8 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.4
2-33
IGLOO PLUS DC and Switching Characteristics
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-51 • Minimum and Maximum DC Input and Output Levels
1.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL IIH
Drive
Strength
Min.,
V
Max., V
Min., V Max., V Max., V
Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
2 mA
4 mA
Notes:
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
–0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
2
4
2
4
13
25
16
33
10 10
10 10
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ/tZH/tZHS
Test Point
5 pF
Enable Path
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
Figure 2-10 • AC Loading
Table 2-52 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.5
0.75
5
* Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.
2-34
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-53 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
0.97 5.47 0.18 1.15 1.62
0.97 4.82 0.18 1.15 1.62
0.66 5.57 4.89 2.13 2.02
0.66 4.91 4.42 2.37 2.47
ns
ns
4 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-54 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
0.97 2.27 0.18 1.15 1.62
0.97 2.07 0.18 1.15 1.62
0.66 2.31 1.85 2.13 2.11
0.66 2.10 1.71 2.37 2.57
ns
ns
4 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.4
2-35
IGLOO PLUS DC and Switching Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-55 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
0.98 5.94 0.19 1.26 1.79
0.98 5.28 0.19 1.26 1.79
0.67 6.05 5.36 2.53 2.58
0.67 5.38 4.88 2.78 3.04
ns
ns
4 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-56 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V
Drive Strength
2 mA
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
STD
STD
0.98 2.68 0.19 1.26 1.79
0.98 2.48 0.19 1.26 1.79
0.67 2.73 2.24 2.53 2.67
0.67 2.52 2.10 2.77 3.14
ns
ns
4 mA
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
2-36
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
1.2 V LVCMOS (JESD8-12A)
Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose
1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer.
Table 2-57 • Minimum and Maximum DC Input and Output Levels
1.2 V
LVCMOS
VIL
Max.,
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL IIH
Drive
Strength
Min.,
V
V
Min., V Max., V Max., V
Min., V mA mA Max., mA1 Max., mA1 µA2 µA2
2 mA
–0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI
2
2
TBD
TBD
10 10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
R to VCCI for tLZ/tZL/tZLS
R = 1 k
Test Point
Datapath
R to GND for tHZ/tZH/tZHS
Test Point
5 pF
Enable Path
35 pF for tZH/tZHS/tZL/tZLS
5 pF for tHZ/tLZ
Figure 2-11 • AC Loading
Table 2-58 • AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
C
LOAD (pF)
0
1.2
0.6
5
* Measuring point = Vtrip. See Table 2-22 on page 2-20 for a complete table of trip points.
Advance v0.4
2-37
IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
Applies to 1.2 V DC Core Voltage
Table 2-59 • 1.2 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Drive Strength
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
ns
2 mA
STD 0.98 8.28 0.19 1.56 2.34
0.67 3.24 2.76 3.00 3.25
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-60 • 1.2 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V
Drive Strength
Speed Grade tDOUT tDP tDIN tPY
tPYS tEOUT tZL
tZH
tLZ
tHZ Units
ns
2 mA
STD 0.98 2.68 0.19 1.56 2.34
0.67 2.73 2.24 2.53 2.67
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
2-38
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
I/O Register Specifications
Fully Registered I/O Buffers with Asynchronous Preset
Preset
Data
L
D
DOUT
EOUT
Data_out
PRE
F
PRE
DFN1P1
Y
E
Core
Array
D
Q
D
Q
C
DFN1P1
H
I
CLK
A
PRE
DFN1P1
J
D
Q
Data Input I/O Register with:
Active High Preset
Positive-Edge Triggered
Data Output Register and
Enable Output Register with:
Active High Preset
Postive-Edge Triggered
INBUF
CLKBUF
Figure 2-12 • Timing Model of Registered I/O Buffers with Asynchronous Preset
Advance v0.4
2-39
IGLOO PLUS DC and Switching Characteristics
Table 2-61 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
Parameter Definition
Clock-to-Q of the Output Data Register
H, DOUT
F, H
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
F, H
tOPRE2Q
tOREMPRE
tORECPRE
tOECLKQ
tOESUD
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
L, DOUT
L, H
L, H
H, EOUT
J, H
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
tOEHD
J, H
tOEPRE2Q
tOEREMPRE
tOERECPRE
tICLKQ
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
I, EOUT
I, H
I, H
A, E
tISUD
Data Setup Time for the Input Data Register
C, A
tIHD
Data Hold Time for the Input Data Register
C, A
tIPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
D, E
tIREMPRE
tIRECPRE
D, A
D, A
* See Figure 2-12 on page 2-39 for more information.
2-40
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Fully Registered I/O Buffers with Asynchronous Clear
DOUT
FF
Data_out
Y
Core
D
Q
D
Q
Data
Array
CC
EE
DFN1C1
DFN1C1
EOUT
CLR
CLR
LL
HH
CLK
CLR
AA
JJ
D
Q
DD
DFN1C1
Data Input I/O Register with
Active High Clear
CLR
Positive-Edge Triggered
Data Output Register and
Enable Output Register with
Active High Clear
Positive-Edge Triggered
INBUF
CLKBUF
Figure 2-13 • Timing Model of the Registered I/O Buffers with Asynchronous Clear
Advance v0.4
2-41
IGLOO PLUS DC and Switching Characteristics
Table 2-62 • Parameter Definition and Measuring Nodes
Measuring Nodes
(from, to)*
Parameter Name
tOCLKQ
Parameter Definition
Clock-to-Q of the Output Data Register
HH, DOUT
FF, HH
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
FF, HH
tOCLR2Q
tOREMCLR
tORECCLR
tOECLKQ
tOESUD
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Clock-to-Q of the Output Enable Register
LL, DOUT
LL, HH
LL, HH
HH, EOUT
JJ, HH
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
tOEHD
JJ, HH
tOECLR2Q
tOEREMCLR
tOERECCLR
tICLKQ
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Clock-to-Q of the Input Data Register
II, EOUT
II, HH
II, HH
AA, EE
CC, AA
CC, AA
DD, EE
DD, AA
DD, AA
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
tIREMCLR
tIRECCLR
* See Figure 2-13 on page 2-41 for more information.
2-42
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Input Register
tICKMPWH tICKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
tIHD
tISUD
50%
50%
tIWPRE
1
0
Data
tIREMPRE
tIRECPRE
Preset
50%
50%
50%
tIWCLR
tIRECCLR
50%
tIREMCLR
50%
50%
Clear
tIPRE2Q
50%
50%
tICLKQ
50%
Out_1
tICLR2Q
Figure 2-14 • Input Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-63 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tICLKQ
Description
Std. Units
Clock-to-Q of the Input Data Register
0.63
0.18
0.00
0.46
0.46
0.00
0.23
0.00
0.23
0.19
0.19
0.28
0.31
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
tIWPRE
tICKMPWH
tICKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.4
2-43
IGLOO PLUS DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-64 • Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Description
Clock-to-Q of the Input Data Register
Parameter
tICLKQ
Std. Units
0.99
0.29
0.00
0.68
0.68
0.00
0.24
0.00
0.24
0.19
0.19
0.28
0.31
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tISUD
Data Setup Time for the Input Data Register
tIHD
Data Hold Time for the Input Data Register
tICLR2Q
tIPRE2Q
tIREMCLR
tIRECCLR
tIREMPRE
tIRECPRE
tIWCLR
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width HIGH for the Input Data Register
Clock Minimum Pulse Width LOW for the Input Data Register
tIWPRE
tICKMPWH
tICKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.
2-44
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Output Register
t
t
OCKMPWH OCKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
t
t
OSUD OHD
50%
50%
1
0
Data_out
Preset
t
OREMPRE
t
t
ORECPRE
OWPRE
50%
50%
50%
t
t
OREMCLR
t
ORECCLR
OWCLR
50%
50%
50%
Clear
t
OPRE2Q
50%
50%
50%
DOUT
t
OCLR2Q
t
OCLKQ
Figure 2-15 • Output Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-65 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tOCLKQ
Description
Std. Units
Clock-to-Q of the Output Data Register
0.89
0.18
0.00
0.72
0.78
0.00
0.23
0.00
0.23
0.19
0.19
0.28
0.31
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width HIGH for the Output Data Register
Clock Minimum Pulse Width LOW for the Output Data Register
tOWPRE
tOCKMPWH
tOCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.4
2-45
IGLOO PLUS DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-66 • Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Description
Clock-to-Q of the Output Data Register
Parameter
tOCLKQ
Std. Units
1.37
0.22
0.00
1.05
1.14
0.00
0.24
0.00
0.24
0.19
0.19
0.28
0.31
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOSUD
Data Setup Time for the Output Data Register
tOHD
Data Hold Time for the Output Data Register
tOCLR2Q
tOPRE2Q
tOREMCLR
tORECCLR
tOREMPRE
tORECPRE
tOWCLR
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width HIGH for the Output Data Register
Clock Minimum Pulse Width LOW for the Output Data Register
tOWPRE
tOCKMPWH
tOCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.
2-46
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Output Enable Register
t
t
OECKMPWH OECKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
t
t
OESUD OEHD
50%
50%
0
1
D_Enable
t
t
OEWPRE
OEREMPRE
t
OERECPRE
50%
50%
50%
Preset
Clear
EOUT
t
t
t
OERECCLR
OEREMCLR
OEWCLR
50%
50%
50%
t
t
OECLR2Q
OEPRE2Q
50%
50%
50%
t
OECLKQ
Figure 2-16 • Output Enable Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-67 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tOECLKQ
Description
Std. Units
Clock-to-Q of the Output Enable Register
0.91
0.18
0.00
0.74
0.81
0.00
0.23
0.00
0.23
0.19
0.19
0.28
0.31
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOESUD
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
tOEHD
tOECLR2Q
tOEPRE2Q
tOEREMCLR
tOERECCLR
tOEREMPRE
tOERECPRE
tOEWCLR
tOEWPRE
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register
tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.4
2-47
IGLOO PLUS DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-68 • Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Description
Clock-to-Q of the Output Enable Register
Parameter
tOECLKQ
Std. Units
1.40
0.22
0.00
1.08
1.19
0.00
0.24
0.00
0.24
0.19
0.19
0.28
0.31
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOESUD
Data Setup Time for the Output Enable Register
tOEHD
Data Hold Time for the Output Enable Register
tOECLR2Q
tOEPRE2Q
tOEREMCLR
tOERECCLR
tOEREMPRE
tOERECPRE
tOEWCLR
tOEWPRE
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register
tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.
2-48
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The IGLOO PLUS library offers all combinations of LUT-3 combinatorial functions. In this section,
timing characteristics are presented for a sample of the library. For more details, refer to the
Fusion, IGLOO/e, and ProASIC3/ E Macro Library Guide.
A
Y
Y
INV
A
A
B
NOR2
OR2
Y
B
A
B
A
B
Y
AND2
Y
NAND2
A
B
C
A
B
Y
XOR3
XOR2
Y
A
B
C
A
MAJ3
0
Y
A
B
C
MUX2
Y
B
S
NAND3
1
Figure 2-17 • Sample of Combinatorial Cells
Advance v0.4
2-49
IGLOO PLUS DC and Switching Characteristics
t
PD
Fanout = 4
A
B
Net
Y
NAND2 or Any
Combinatorial
Logic
Length = 1 VersaTile
t
= MAX(t
, t
,
PD
PD(RR) PD(RF)
t
, t
) where edges are
PD(FF) PD(FR)
A
applicable for a particular
combinatorial cell
Net
Y
Y
NAND2 or Any
Combinatorial
Logic
Length = 1 VersaTile
B
A
Net
NAND2 or Any
Combinatorial
Logic
Length = 1 VersaTile
B
A
Net
Y
NAND2 or Any
Combinatorial
Logic
Length = 1 VersaTile
B
VCC
50%
50%
VCC
A, B, C
GND
50%
50%
OUT
OUT
GND
tPD
tPD
(FF)
(RR)
VCC
tPD
(FR)
50%
50%
tPD
GND
(RF)
Figure 2-18 • Timing Model and Waveforms
2-50
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-69 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Combinatorial Cell
INV
Equation
Y = !A
Parameter
tPD
Std.
0.72
0.86
0.87
0.89
0.90
1.35
1.33
1.98
1.24
1.40
Units
ns
AND2
Y = A · B
tPD
ns
NAND2
OR2
Y = !(A · B)
Y = A + B
tPD
ns
tPD
ns
NOR2
Y = !(A + B)
Y = A ⊕ B
Y = MAJ(A, B, C)
Y = A ⊕ B ⊕ C
Y = A !S + B S
Y = A · B · C
tPD
ns
XOR2
tPD
ns
MAJ3
tPD
ns
XOR3
tPD
ns
MUX2
AND3
tPD
ns
tPD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-70 • Combinatorial Cell Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Combinatorial Cell
INV
Equation
Y = !A
Parameter
tPD
Std.
1.27
1.47
1.52
1.51
1.57
2.28
2.39
3.50
2.21
2.50
Units
ns
AND2
Y = A · B
tPD
ns
NAND2
OR2
Y = !(A · B)
Y = A + B
tPD
ns
tPD
ns
NOR2
Y = !(A + B)
Y = A ⊕ B
Y = MAJ(A, B, C)
Y = A ⊕ B ⊕ C
Y = A !S + B S
Y = A · B · C
tPD
ns
XOR2
tPD
ns
MAJ3
tPD
ns
XOR3
tPD
ns
MUX2
AND3
tPD
ns
tPD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.
Advance v0.4
2-51
IGLOO PLUS DC and Switching Characteristics
VersaTile Specifications as a Sequential Module
The IGLOO PLUS library offers a wide variety of sequential cells, including flip-flops and latches.
Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are
presented for a representative sample from the library. For more details, refer to the Fusion,
IGLOO/e, and ProASIC3/E Macro Library Guide.
Data
CLK
Out
Data
Out
D
Q
D
Q
En
DFN1
DFN1E1
CLK
PRE
Data
Out
Data
Out
Q
D
D
Q
En
DFN1C1
DFI1E1P1
CLK
CLK
CLR
Figure 2-19 • Sample of Sequential Cells
2-52
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
t
t
CKMPWH CKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
t
HD
t
SUD
50%
50%
Data
EN
0
50%
t
t
RECPRE
WPRE
t
REMPRE
t
HE
50%
50%
50%
t
PRE
CLR
Out
SUE
t
t
t
REMCLR
RECCLR
WCLR
50%
50%
50%
t
PRE2Q
t
CLR2Q
50%
50%
50%
t
CLKQ
Figure 2-20 • Timing Model and Waveforms
Timing Characteristics
1.5 V DC Core Voltage
Table 2-71 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tCLKQ
Description
Std. Units
Clock-to-Q of the Core Register
0.80
0.84
0.00
0.73
0.00
0.62
0.60
0.00
0.23
0.00
0.24
0.30
0.30
0.56
0.56
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
tWPRE
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width HIGH for the Core Register
Clock Minimum Pulse Width LOW for the Core Register
tCKMPWH
tCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.4
2-53
IGLOO PLUS DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-72 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tCLKQ
Description
Std. Units
Clock-to-Q of the Core Register
1.40
1.35
0.00
1.29
0.00
0.89
0.87
0.00
0.24
0.00
0.24
0.46
0.46
0.95
0.95
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width HIGH for the Core Register
Clock Minimum Pulse Width LOW for the Core Register
tWPRE
tCKMPWH
tCKMPWL
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.
2-54
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Global Resource Characteristics
AGLP125 Clock Tree Topology
Clock delays are device-specific. Figure 2-21 is an example of a global tree used for clock routing.
The global tree presented in Figure 2-21 is driven by a CCC located on the west side of the AGLP125
device. It is used to drive all D-flip-flops in the device.
Central
Global Rib
CCC
VersaTile
Rows
Global Spine
Figure 2-21 • Example of Global Tree Use in an AGLP125 Device for Clock Routing
Advance v0.4
2-55
IGLOO PLUS DC and Switching Characteristics
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be
driven and conditioned internally by the CCC module. For more details on clock conditioning
capabilities, refer to the "Clock Conditioning Circuits" section on page 2-59. Table 2-73 to
Table 2-78 on page 2-58 present minimum and maximum global clock delays within each device.
Minimum and maximum delays are measured with minimum and maximum loading.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-73 • AGLP030 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Max.2
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
1.21
Units
ns
1.42
1.49
tRCKH
Input HIGH Delay for Global Clock
1.23
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.27
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-74 • AGLP060 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
1.32
Max.2
Units
ns
1.52
tRCKH
Input HIGH Delay for Global Clock
1.34
1.59
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.26
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
2-56
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Table 2-75 • AGLP125 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Std.
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
1.31
Max.2
Units
ns
1.66
tRCKH
Input HIGH Delay for Global Clock
1.29
1.72
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.43
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-76 • AGLP030 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
1.80
Max.2
Units
ns
2.09
tRCKH
Input HIGH Delay for Global Clock
1.88
2.27
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.39
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.
Advance v0.4
2-57
IGLOO PLUS DC and Switching Characteristics
Table 2-77 • AGLP060 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Max.2
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
2.02
Units
ns
2.30
2.46
tRCKH
Input HIGH Delay for Global Clock
2.09
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.37
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.
Table 2-78 • AGLP125 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Std.
Parameter
tRCKL
Description
Input LOW Delay for Global Clock
Min.1
2.08
Max.2
Units
ns
2.54
tRCKH
Input HIGH Delay for Global Clock
2.15
2.77
ns
tRCKMPWH
tRCKMPWL
tRCKSW
Minimum Pulse Width HIGH for Global Clock
Minimum Pulse Width LOW for Global Clock
Maximum Skew for Global Clock
ns
ns
0.62
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.
2-58
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-79 • IGLOO PLUS CCC/PLL Specification
For IGLOO PLUS V2 or V5 devices, 1.5 V DC Core Supply Voltage
Parameter
Min.
1.5
Typ.
Max.
250
Units
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Delay Increments in Programmable Delay Blocks 1, 2
Number of Programmable Values in Each Programmable Delay Block
Input Cycle-to-Cycle Jitter (peak magnitude)
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
0.75
250
360
32
100
1
MHz
ns
Max Peak-to-Peak Period Jitter
0.75 MHz to 24 MHz
1 Global External 3 Global
Network FB Used Networks
Used
0.50%
1.00%
2.50%
Used
0.70%
1.20%
2.75%
300
24 MHz to 100 MHz
100 MHz to 250 MHz
0.75%
1.50%
3.75%
Acquisition Time
LockControl = 0
µs
LockControl = 1
6.0
ms
Tracking Jitter
LockControl = 0
2.5
1.5
LockControl = 1
ns
%
ns
ns
ns
Output Duty Cycle
48.5
1.25
51.5
15.65
15.65
Delay Range in Block: Programmable Delay 1 1, 2, 3
Delay Range in Block: Programmable Delay 2 1, 2, 3
Delay Range in Block: Fixed Delay 1, 2
Notes:
0.025
3.5
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7
for deratings.
2. TJ = 25°C, VCC = 1.5 V
3. For definitions of Type 1 and Type 2, refer to the PLL Block Diagram in the Clock Conditioning Circuits in
IGLOO and ProASIC3 Devices chapter of the handbook.
4. The AGLP030 device does not support PLL.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL
input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by
the period jitter parameter.
Advance v0.4
2-59
IGLOO PLUS DC and Switching Characteristics
Table 2-80 • IGLOO PLUS CCC/PLL Specification
For IGLOO PLUS V2 Devices, 1.2 V DC Core Supply Voltage
Parameter
Min.
1.5
Typ.
Max.
160
Units
MHz
MHz
ps
Clock Conditioning Circuitry Input Frequency fIN_CCC
Clock Conditioning Circuitry Output Frequency fOUT_CCC
Delay Increments in Programmable Delay Blocks 1, 2
Number of Programmable Values in Each Programmable Delay Block
Input Cycle-to-Cycle Jitter (peak magnitude)
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
0.75
160
580
32
60
MHz
Max Peak-to-Peak Period Jitter
1 Global External 3 Global
Network FB Used Networks
Used
0.50%
1.00%
2.50%
Used
0.70%
1.20%
2.75%
0.75 MHz to 24 MHz
24 MHz to 100 MHz
0.75%
1.50%
3.75%
100 MHz to 160 MHz
Acquisition Time
LockControl = 0
300
6.0
µs
LockControl = 1
ms
Tracking Jitter
LockControl = 0
4
ns
ns
%
ns
ns
ns
LockControl = 1
3
Output Duty Cycle
48.5
2.3
51.5
20.86
20.86
Delay Range in Block: Programmable Delay 1 1, 2, 3
Delay Range in Block: Programmable Delay 2 1, 2, 3
Delay Range in Block: Fixed Delay 1, 2
Notes:
0.025
5.7
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7
for deratings.
2. TJ = 25°C, VCC = 1.2 V
3. For definitions of Type 1 and Type 2, refer to the PLL Block Diagram in the Clock Conditioning Circuits in
IGLOO and ProASIC3 Devices chapter of the handbook.
4. The AGLP030 device does not support PLL.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input
clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period
jitter parameter.
Output Signal
Tperiod_max
Tperiod_min
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min
.
Figure 2-22 • Peak-to-Peak Jitter Definition
2-60
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Embedded SRAM and FIFO Characteristics
SRAM
RAM4K9
RAM512X18
RADDR8
RD17
RD16
ADDRA11 DOUTA8
RADDR7
DOUTA7
DOUTA0
ADDRA10
ADDRA0
DINA8
RADDR0
RD0
DINA7
RW1
RW0
DINA0
WIDTHA1
WIDTHA0
PIPEA
PIPE
WMODEA
BLKA
WENA
REN
RCLK
CLKA
ADDRB11 DOUTB8
ADDRB10 DOUTB7
WADDR8
WADDR7
ADDRB0
DOUTB0
WADDR0
WD17
WD16
DINB8
DINB7
WD0
DINB0
WW1
WW0
WIDTHB1
WIDTHB0
PIPEB
WMODEB
BLKB
WENB
CLKB
WEN
WCLK
RESET
RESET
Figure 2-23 • RAM Models
Advance v0.4
2-61
IGLOO PLUS DC and Switching Characteristics
Timing Waveforms
tCYC
tCKH
tCKL
CLK
tAS tAH
A0
tBKS
A1
A2
ADD
BLK_B
WEN_B
DO
tBKH
tENS
tENH
tCKQ1
Dn
D0
D1
D2
tDOH1
Figure 2-24 • RAM Read for Pass-Through Output
tCYC
tCKH
tCKL
CLK
tAS tAH
A0
A1
A2
ADD
BLK_B
WEN_B
DO
tBKS
tBKH
tENH
tENS
tCKQ2
Dn
D0
D1
tDOH2
Figure 2-25 • RAM Read for Pipelined Output
2-62
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
tCYC
tCKH
tAH
tCKL
CLK
tAS
A0
A1
A2
ADD
BLK_B
WEN_B
DI
tBKS
tBKH
tENS
tENH
tDS
tDH
DI1
DI0
Dn
D2
DO
Figure 2-26 • RAM Write, Output Retained (WMODE = 0)
t
CYC
t
t
CKH
CKL
CLK
ADD
t
t
AH
AS
A
A
A
2
0
1
t
BKS
t
BKH
BLK_B
WEN_B
DI
t
ENS
t
t
DH
DS
DI
DI
DI
2
0
1
DO
D
DI
DI
1
n
0
(pass-through)
DO
DI
D
DI
1
0
n
(pipelined)
Figure 2-27 • RAM Write, Output as Write Data (WMODE = 1)
Advance v0.4
2-63
IGLOO PLUS DC and Switching Characteristics
CLK1
tAS tAH
ADD1
DI1
A0
tDS tDH
A1
D2
A3
D3
D1
tCCKH
CLK2
WEN_B1
WEN_B2
tAS tAH
A0
A0
D0
A4
D4
ADD2
DI2
tCKQ1
DO2
(pass-through)
Dn
Dn
D0
tCKQ2
DO2
(pipelined)
D0
Figure 2-28 • Write Access after Write onto Same Address
2-64
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
CLK1
tAS tAH
A0
tDS tDH
A2
D2
A3
D3
ADD1
D0
DI1
tWRO
CLK2
WEN_B1
WEN_B2
ADD2
tAS tAH
A1
A0
tCKQ1
A4
DO2
(pass-through)
Dn
D0
D1
tCKQ2
DO2
Dn
D0
(pipelined)
Figure 2-29 • Read Access after Write onto Same Address
Advance v0.4
2-65
IGLOO PLUS DC and Switching Characteristics
CLK1
t
t
AS
AH
A
t
A
A
t
ADD1
0
1
0
WEN_B1
CKQ1
CKQ1
DO1
(pass-through)
D
D
D
1
n
0
t
CKQ2
DO1
(pipelined)
D
D
0
n
t
CCKH
CLK2
t
t
AH
AS
ADD2
A
D
A
D
A
D
0
1
3
DI2
1
2
3
WEN_B2
Figure 2-30 • Write Access after Read onto Same Address
tCYC
tCKH
tCKL
CLK
RESET_B
DO
tRSTBQ
Dm
Dn
Figure 2-31 • RAM Reset
2-66
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-81 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
Std. Units
0.83 ns
0.16 ns
0.81 ns
0.16 ns
1.65 ns
0.16 ns
0.71 ns
0.36 ns
3.53 ns
3.06 ns
1.81 ns
TBD ns
Address setup time
tAH
Address hold time
tENS
REN_B, WEN_B setup time
tENH
tBKS
tBKH
tDS
REN_B, WEN_B hold time
BLK_B setup time
BLK_B hold time
Input data (DI) setup time
tDH
Input data (DI) hold time
tCKQ1
Clock HIGH to new data valid on DO (output retained, WMODE = 0)
Clock HIGH to new data valid on DO (flow-through, WMODE = 1)
Clock HIGH to new data valid on DO (pipelined)
Address collision clk-to-clk delay for reliable read access after write on same address
tCKQ2
tWRO
tCCKH
Address collision clk-to-clk delay for reliable write access after write/read on same TBD ns
address
tRSTBQ
RESET_B LOW to data out LOW on DO (flow-through)
RESET_B LOW to data out LOW on DO (pipelined)
RESET_B removal
2.06 ns
2.06 ns
0.61 ns
3.21 ns
0.68 ns
6.24 ns
160 MHz
tREMRSTB
tRECRSTB
RESET_B recovery
tMPWRSTB RESET_B minimum pulse width
tCYC
Clock cycle time
FMAX
Maximum frequency
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.4
2-67
IGLOO PLUS DC and Switching Characteristics
Table 2-82 • RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tAS
Description
Std. Units
0.83 ns
0.16 ns
0.73 ns
0.08 ns
0.71 ns
0.36 ns
4.21 ns
1.71 ns
TBD ns
Address setup time
tAH
Address hold time
tENS
REN_B, WEN_B setup time
REN_B, WEN_B hold time
Input data (DI) setup time
Input data (DI) hold time
tENH
tDS
tDH
tCKQ1
tCKQ2
tWRO
tCCKH
Clock HIGH to new data valid on DO (output retained, WMODE = 0)
Clock HIGH to new data valid on DO (pipelined)
Address collision clk-to-clk delay for reliable read access after write on same address
Address collision clk-to-clk delay for reliable write access after write/read on same TBD ns
address
tRSTBQ
RESET_B LOW to data out LOW on DO (flow-through)
RESET_B LOW to data out LOW on DO (pipelined)
RESET_B removal
2.06 ns
2.06 ns
0.61 ns
3.21 ns
0.68 ns
6.24 ns
160 MHz
tREMRSTB
tRECRSTB
RESET_B recovery
tMPWRSTB RESET_B minimum pulse width
tCYC
Clock cycle time
FMAX
Maximum frequency
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
2-68
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-83 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tAS
Description
Std. Units
Address setup time
1.53
0.29
1.50
0.29
3.05
0.29
1.33
0.66
6.61
5.72
3.38
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
Address hold time
tENS
REN_B, WEN_B setup time
tENH
tBKS
tBKH
tDS
REN_B, WEN_B hold time
BLK_B setup time
BLK_B hold time
Input data (DI) setup time
tDH
Input data (DI) hold time
tCKQ1
Clock HIGH to new data valid on DO (output retained, WMODE = 0)
Clock HIGH to new data valid on DO (flow-through, WMODE = 1)
Clock HIGH to new data valid on DO (pipelined)
tCKQ2
tWRO
tCCKH
Address collision clk-to-clk delay for reliable read access after write on same address TBD
Address collision clk-to-clk delay for reliable write access after write/read on same TBD
address
tRSTBQ
RESET_B LOW to data out LOW on DO (flow-through)
RESET_B LOW to data out LOW on DO (pipelined)
RESET_B removal
3.86
3.86
1.12
5.93
1.18
10.90
92
ns
ns
tREMRSTB
tRECRSTB
ns
RESET_B recovery
ns
tMPWRSTB RESET_B minimum pulse width
ns
tCYC
Clock cycle time
ns
FMAX
Maximum frequency
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.
Advance v0.4
2-69
IGLOO PLUS DC and Switching Characteristics
Table 2-84 • RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tAS
Description
Std. Units
Address setup time
1.53
0.29
1.36
0.15
1.33
0.66
7.88
3.20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
Address hold time
tENS
REN_B, WEN_B setup time
REN_B, WEN_B hold time
Input data (DI) setup time
Input data (DI) hold time
tENH
tDS
tDH
tCKQ1
tCKQ2
tWRO
tCCKH
Clock HIGH to new data valid on DO (output retained, WMODE = 0)
Clock HIGH to new data valid on DO (pipelined)
Address collision clk-to-clk delay for reliable read access after write on same address TBD
Address collision clk-to-clk delay for reliable write access after write/read on same TBD
address
tRSTBQ
RESET_B LOW to data out LOW on DO (flow through)
RESET_B LOW to data out LOW on DO (pipelined)
RESET_B removal
3.86
3.86
1.12
5.93
1.18
10.90
92
ns
ns
tREMRSTB
tRECRSTB
ns
RESET_B recovery
ns
tMPWRSTB RESET_B minimum pulse width
ns
tCYC
Clock cycle time
ns
FMAX
Maximum frequency
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.
2-70
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
FIFO
FIFO4K18
RW2
RW1
RW0
RD17
RD16
WW2
WW1
WW0
RD0
ESTOP
FSTOP
FULL
AFULL
EMPTY
AEVAL11
AEVAL10
AEMPTY
AEVAL0
AFVAL11
AFVAL10
AFVAL0
REN
RBLK
RCLK
WD17
WD16
WD0
WEN
WBLK
WCLK
RPIPE
RESET
Figure 2-32 • FIFO Model
Advance v0.4
2-71
IGLOO PLUS DC and Switching Characteristics
Timing Waveforms
RCLK/
WCLK
tMPWRSTB
tRSTCK
RESET_B
tRSTFG
EMPTY
tRSTAF
AEMPTY
FULL
tRSTFG
tRSTAF
AFULL
WA/RA
(Address Counter)
MATCH (A0)
Figure 2-33 • FIFO Reset
t
CYC
RCLK
t
RCKEF
EMPTY
tCKAF
AEMPTY
WA/RA
NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
(Address Counter)
Figure 2-34 • FIFO EMPTY Flag and AEMPTY Flag Assertion
2-72
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
tCYC
WCLK
FULL
tWCKFF
tCKAF
AFULL
WA/RA
NO MATCH
NO MATCH
Dist = AFF_TH
MATCH (FULL)
(Address Counter)
Figure 2-35 • FIFO FULL Flag and AFULL Flag Assertion
WCLK
MATCH
(EMPTY)
WA/RA
NO MATCH
NO MATCH
NO MATCH
NO MATCH
Dist = AEF_TH + 1
(Address Counter)
1st Rising
2nd Rising
Edge
After 1st
Write
Edge
After 1st
Write
RCLK
EMPTY
t
RCKEF
t
CKAF
AEMPTY
Figure 2-36 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
RCLK
WA/RA
(Address Counter)
Dist = AFF_TH – 1
MATCH (FULL)
NO MATCH
NO MATCH
1st Rising
NO MATCH
NO MATCH
1st Rising
Edge
After 1st
Read
Edge
After 2nd
Read
WCLK
FULL
tWCKF
tCKAF
AFULL
Figure 2-37 • FIFO FULL Flag and AFULL Flag Deassertion
Advance v0.4
2-73
IGLOO PLUS DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-85 • FIFO
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tENS
Description
Std.
1.99
0.16
0.30
0.00
0.76
0.25
3.33
1.80
3.53
3.35
12.85
3.48
12.72
2.02
2.02
0.61
3.21
0.68
6.24
160
Units
ns
REN_B, WEN_B Setup Time
REN_B, WEN_B Hold Time
BLK_B Setup Time
tENH
ns
tBKS
ns
tBKH
BLK_B Hold Time
ns
tDS
Input Data (DI) Setup Time
Input Data (DI) Hold Time
ns
tDH
ns
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock HIGH to New Data Valid on DO (flow-through)
Clock HIGH to New Data Valid on DO (pipelined)
RCLK HIGH to Empty Flag Valid
ns
ns
ns
WCLK HIGH to Full Flag Valid
ns
Clock HIGH to Almost Empty/Full Flag Valid
RESET_B LOW to Empty/Full Flag Valid
RESET_B LOW to Almost Empty/Full Flag Valid
RESET_B LOW to Data Out LOW on DO (flow-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B Removal
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
ns
Clock Cycle Time
ns
FMAX
Maximum Frequency for FIFO
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
2-74
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-86 • FIFO
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
tENS
Description
Std.
4.13
0.31
0.30
0.00
1.56
0.49
6.80
3.62
7.23
6.85
26.61
7.12
26.33
4.09
4.09
1.23
6.58
1.18
10.90
92
Units
ns
REN_B, WEN_B Setup Time
tENH
REN_B, WEN_B Hold Time
ns
tBKS
BLK_B Setup Time
ns
tBKH
BLK_B Hold Time
ns
tDS
Input Data (DI) Setup Time
ns
tDH
Input Data (DI) Hold Time
ns
tCKQ1
tCKQ2
tRCKEF
tWCKFF
tCKAF
tRSTFG
tRSTAF
tRSTBQ
Clock HIGH to New Data Valid on DO (flow-through)
Clock HIGH to New Data Valid on DO (pipelined)
RCLK HIGH to Empty Flag Valid
WCLK HIGH to Full Flag Valid
ns
ns
ns
ns
Clock HIGH to Almost Empty/Full Flag Valid
RESET_B LOW to Empty/Full Flag Valid
RESET_B LOW to Almost Empty/Full Flag Valid
RESET_B LOW to Data Out LOW on DO (flow-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B Removal
ns
ns
ns
ns
ns
tREMRSTB
tRECRSTB
tMPWRSTB
tCYC
ns
RESET_B Recovery
ns
RESET_B Minimum Pulse Width
Clock Cycle Time
ns
ns
FMAX
Maximum Frequency for FIFO
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.
Advance v0.4
2-75
IGLOO PLUS DC and Switching Characteristics
Embedded FlashROM Characteristics
tSU
tSU
tSU
CLK
tHOLD
tHOLD
tHOLD
Address
A0
A1
tCKQ2
D0
tCKQ2
tCKQ2
D1
D0
Data
Figure 2-38 • Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-87 • Embedded FlashROM Access Time
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
tSU
Description
Address Setup Time
Std.
0.57
0.00
33.14
15
Units
ns
tHOLD
tCK2Q
FMAX
Address Hold Time
ns
Clock to Out
ns
Maximum Clock Frequency
MHz
1.2 V DC Core Voltage
Table 2-88 • Embedded FlashROM Access Time
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
tSU
Description
Std.
0.59
0.00
52.04
10
Units
ns
Address Setup Time
Address Hold Time
Clock to Out
tHOLD
tCK2Q
FMAX
ns
ns
Maximum Clock Frequency
MHz
2-76
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays
to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O
Characteristics" section on page 2-15 for more details.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-89 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
tDISU
Description
Std.
1.00
2.00
1.00
2.00
8.00
25.00
15
Units
ns
Test Data Input Setup Time
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
tDIHD
ns
tTMSSU
ns
tTMDHD
tTCK2Q
ns
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (data out)
ns
TCK Maximum Frequency
ResetB Removal Time
MHz
ns
0.58
0.00
TBD
ResetB Recovery Time
ns
ResetB Minimum Pulse
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
1.2 V DC Core Voltage
Table 2-90 • JTAG 1532
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
tDISU
Description
Test Data Input Setup Time
Std.
1.50
3.00
1.50
3.00
11.00
30.00
9.00
1.18
0.00
TBD
Units
ns
tDIHD
Test Data Input Hold Time
Test Mode Select Setup Time
Test Mode Select Hold Time
Clock to Q (data out)
ns
tTMSSU
ns
tTMDHD
tTCK2Q
ns
ns
tRSTB2Q
FTCKMAX
tTRSTREM
tTRSTREC
tTRSTMPW
Reset to Q (data out)
ns
TCK Maximum Frequency
ResetB Removal Time
MHz
ns
ResetB Recovery Time
ns
ResetB Minimum Pulse
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Advance v0.4
2-77
IGLOO PLUS DC and Switching Characteristics
Part Number and Revision Date
Part Number 51700102-002-3
Revised October 2008
List of Changes
The following table lists critical changes that were made in the current version of the chapter.
Previous Version
Changes in Current Version (Advance v0.4)
Page
Advance v0.3
(July 2008)
Data was revised significantly in the following tables:
2-21,
2-30
Table 2-24 · Summary of I/O Timing Characteristics—Software Default Settings,
STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC
1.425 V, Worst-Case VCCI = 3.0 V,
=
Table 2-25 · Summary of I/O Timing Characteristics—Software Default Settings,
STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC
1.14 V, Worst-Case VCCI = 3.0 V
=
Table 2-43 · 2.5 LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Table 2-44 · 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Advance v0.2
(March 2008)
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of
core voltage support. The document was updated to change 1.2 V / 1.5 V to
1.2 V to 1.5 V.
N/A
N/A
2-2
Advance v0.1
(January 2008)
Tables have been updated to reflect default values in the software. The
default I/O capacitance is 5 pF. Tables have been updated to include the
LVCMOS 1.2 V I/O set.
Table note 3 was updated in Table 2-2 · Recommended Operating Conditions 4
to add the sentence, "VCCI should be at the same voltage within a given I/O
bank." References to table notes 5, 6, 7, and 8 were added. Reference to table
note 3 was removed from VPUMP Operation and placed next to VCC
.
Table 2-4 · Overshoot and Undershoot Limits 1 was revised to remove "as
measured on quiet I/Os" from the title. Table note 2 was revised to remove
"estimated SSO density over cycles." Table note 3 was deleted.
2-3
2-7
2-7
2-7
2-8
The table note for Table 2-8 · Quiescent Supply Current (IDD) Characteristics,
IGLOO PLUS Flash*Freeze Mode* to remove the sentence stating that values
do not include I/O static contribution.
The table note for Table 2-9 · Quiescent Supply Current (IDD) Characteristics,
IGLOO PLUS Sleep Mode (VCC = 0 V)* was updated to remove VJTAG and VCCI
and the statement that values do not include I/O static contribution.
The table note for Table 2-10 · Quiescent Supply Current (IDD) Characteristics,
IGLOO PLUS Shutdown Mode (VCC, VCCI = 0 V)* was updated to remove the
statement that values do not include I/O static contribution.
Note 2 of Table 2-11 · Quiescent Supply Current (IDD), No IGLOO PLUS
Flash*Freeze Mode 1 was updated to include VCCPLL. Table note 4 was deleted.
Table 2-12 · Summary of I/O Input Buffer Power (per pin) – Default I/O 2-8, 2-9
Software Settings and Table 2-13 · Summary of I/O Output Buffer Power (per
pin) – Default I/O Software Settings1 were updated to remove static power.
The table notes were updated to reflect that power was measured on VCCI
.
Table note 2 was added to Table 2-12 · Summary of I/O Input Buffer Power
(per pin) – Default I/O Software Settings.
2-78
Advance v0.4
IGLOO PLUS DC and Switching Characteristics
Previous Version
Changes in Current Version (Advance v0.4)
Page
Advance v0.1
(continued)
Table 2-15 · Different Components Contributing to the Static Power
Consumption in IGLOO PLUS Devices and Table 2-17 · Different Components
Contributing to the Static Power Consumption in IGLOO PLUS Devices were
updated to change the definition for PDC5 from bank static power to bank
quiescent power. Table subtitles were added for Table 2-15 · Different
Components Contributing to the Static Power Consumption in IGLOO PLUS
Devices, Table 2-16 · Different Components Contributing to Dynamic Power
Consumption in IGLOO PLUS Devices, and Table 2-17 · Different Components
Contributing to the Static Power Consumption in IGLOO PLUS Devices.
2-10,
2-11
The "Total Static Power Consumption—PSTAT" section was revised.
Table 2-31 · Schmitt Trigger Input Hysteresis is new.
2-12
2-24
Actel Safety Critical, Life Support, and High-Reliability
Applications Policy
The Actel products described in this advance status datasheet may not have completed Actel’s
qualification process. Actel may amend or enhance products during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the
responsibility of each customer to ensure the fitness of any Actel product (but especially a new
product) for a particular purpose, including appropriateness for safety-critical, life-support, and
other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability
exclusions relating to life-support applications. A reliability report covering all of Actel’s products is
available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also
offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your
local Actel sales office for additional reliability information.
Advance v0.4
2-79
IGLOO PLUS Packaging
3 – Package Pin Assignments
128-Pin VQFP
128
1
128-Pin
VQFP
Note: This is the bottom view of the package.
Figure 3-1 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
v1.5
3-1
Package Pin Assignments
128-Pin VQFP
Pin Number AGLP030 Function
128-Pin VQFP
128-Pin VQFP
Pin Number AGLP030 Function
Pin Number AGLP030 Function
1
IO119RSB3
IO118RSB3
IO117RSB3
IO115RSB3
IO116RSB3
IO113RSB3
IO114RSB3
GND
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
IO86RSB2
IO84RSB2
IO83RSB2
GND
73
74
GND
IO55RSB1
IO54RSB1
IO53RSB1
IO52RSB1
IO51RSB1
IO50RSB1
IO49RSB1
VCC
2
3
75
4
76
5
V
CCIB2
77
6
IO82RSB2
IO81RSB2
IO79RSB2
IO78RSB2
IO77RSB2
IO75RSB2
IO74RSB2
VCC
78
7
79
8
80
9
VCCIB3
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
IO112RSB3
IO111RSB3
IO110RSB3
IO109RSB3
GEC0/IO108RSB3
GEA0/IO107RSB3
GEB0/IO106RSB3
VCC
82
GDB0/IO48RSB1
GDA0/IO47RSB1
GDC0/IO46RSB1
IO45RSB1
IO44RSB1
IO43RSB1
IO42RSB1
VCCIB1
83
84
85
IO73RSB2
IO72RSB2
IO70RSB2
IO69RSB2
IO68RSB2
IO66RSB2
IO65RSB2
GND
86
87
88
89
IO104RSB3
IO103RSB3
IO102RSB3
IO101RSB3
IO100RSB3
IO99RSB3
GND
90
GND
91
IO40RSB1
IO41RSB1
IO39RSB1
IO38RSB1
IO37RSB1
IO36RSB1
IO35RSB0
IO34RSB0
IO33RSB0
IO32RSB0
IO30RSB0
IO28RSB0
IO27RSB0
VCCIB0
92
93
VCCIB2
94
IO63RSB2
IO61RSB2
IO59RSB2
TCK
95
96
VCCIB3
97
IO97RSB3
IO98RSB3
IO95RSB3
IO96RSB3
IO94RSB3
IO93RSB3
IO92RSB3
IO91RSB2
FF/IO90RSB2
IO89RSB2
IO88RSB2
98
TDI
99
TMS
100
101
102
103
104
105
106
107
108
VPUMP
TDO
TRST
IO58RSB1
VJTAG
GND
IO56RSB1
IO57RSB1
VCCIB1
IO26RSB0
IO25RSB0
IO23RSB0
3-2
v1.5
IGLOO PLUS Packaging
128-Pin VQFP
Pin Number AGLP030 Function
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
IO22RSB0
IO21RSB0
IO19RSB0
IO18RSB0
VCC
IO17RSB0
IO16RSB0
IO14RSB0
IO13RSB0
IO12RSB0
IO10RSB0
IO09RSB0
VCCIB0
GND
IO07RSB0
IO05RSB0
IO03RSB0
IO02RSB0
IO01RSB0
IO00RSB0
v1.5
3-3
Package Pin Assignments
176-Pin VQFP
176
1
176-Pin
VQFP
Note: This is the bottom view of the package.
Figure 3-2 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
3-4
v1.5
IGLOO PLUS Packaging
176-Pin VQFP
176-Pin VQFP
176-Pin VQFP
Pin Number AGLP060 Function
Pin Number AGLP060 Function
Pin Number AGLP060 Function
1
GAA2/IO156RSB3
IO155RSB3
GAB2/IO154RSB3
IO153RSB3
GAC2/IO152RSB3
GND
37
38
39
40
41
42
43
44
45
46
47
GND
72
73
IO87RSB2
IO86RSB2
IO85RSB2
IO84RSB2
GND
2
V
CCIB3
3
GEC1/IO116RSB3
GEB1/IO114RSB3
GEC0/IO115RSB3
GEB0/IO113RSB3
GEA1/IO112RSB3
GEA0/IO111RSB3
GEA2/IO110RSB2
NC
74
4
75
5
76
6
77
VCCIB2
7
VCCIB3
78
IO83RSB2
IO82RSB2
GDC2/IO80RSB2
IO81RSB2
GDA2/IO78RSB2
GDB2/IO79RSB2
NC
8
IO149RSB3
IO147RSB3
IO145RSB3
IO144RSB3
IO143RSB3
VCC
79
9
80
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
81
FF/GEB2/IO109RSB
2
82
83
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
GEC2/IO108RSB2
IO106RSB2
IO107RSB2
IO104RSB2
IO105RSB2
IO102RSB2
IO103RSB2
GND
84
IO141RSB3
GFC1/IO140RSB3
GFB1/IO138RSB3
GFB0/IO137RSB3
VCOMPLF
85
NC
86
TCK
87
TDI
88
TMS
89
VPUMP
GFA1/IO136RSB3
VCCPLF
90
TDO
91
TRST
VCCIB2
GFA0/IO135RSB3
GND
92
VJTAG
IO101RSB2
IO100RSB2
IO99RSB2
IO98RSB2
IO97RSB2
IO96RSB2
IO95RSB2
IO94RSB2
IO93RSB2
VCC
93
GDA1/IO76RSB1
GDC0/IO73RSB1
GDB1/IO74RSB1
GDC1/IO72RSB1
VCCIB1
VCCIB3
94
GFA2/IO134RSB3
GFB2/IO133RSB3
GFC2/IO132RSB3
IO131RSB3
IO130RSB3
IO129RSB3
IO127RSB3
IO126RSB3
IO125RSB3
IO123RSB3
IO122RSB3
IO121RSB3
IO119RSB3
95
96
97
98
GND
99
IO70RSB1
IO69RSB1
IO67RSB1
IO66RSB1
IO65RSB1
IO63RSB1
IO62RSB1
IO61RSB1
GCC2/IO60RSB1
100
101
102
103
104
105
106
107
IO92RSB2
IO91RSB2
IO90RSB2
IO89RSB2
IO88RSB2
v1.5
3-5
Package Pin Assignments
176-Pin VQFP
Pin Number AGLP060 Function
176-Pin VQFP
Pin Number AGLP060 Function
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
GCB2/IO59RSB1
GCA2/IO58RSB1
GCA0/IO57RSB1
GCA1/IO56RSB1
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
IO27RSB0
CCIB0
V
GND
IO26RSB0
IO25RSB0
IO24RSB0
IO23RSB0
IO22RSB0
IO21RSB0
IO20RSB0
IO19RSB0
IO18RSB0
VCC
VCCIB1
GND
GCB0/IO55RSB1
GCB1/IO54RSB1
GCC0/IO53RSB1
GCC1/IO52RSB1
IO51RSB1
IO50RSB1
VCC
IO48RSB1
IO17RSB0
IO16RSB0
IO15RSB0
IO14RSB0
IO13RSB0
IO12RSB0
IO11RSB0
IO10RSB0
IO09RSB0
VCCIB0
IO47RSB1
IO45RSB1
IO44RSB1
IO43RSB1
VCCIB1
GND
GBC2/IO40RSB1
IO39RSB1
GBB2/IO38RSB1
IO37RSB1
GND
GBA2/IO36RSB1
GBA1/IO35RSB0
NC
IO07RSB0
IO08RSB0
GAC1/IO05RSB0
IO06RSB0
GAB1/IO03RSB0
GAC0/IO04RSB0
GAB0/IO02RSB0
GAA1/IO01RSB0
GAA0/IO00RSB0
GBA0/IO34RSB0
NC
GBB1/IO33RSB0
NC
GBC1/IO31RSB0
GBB0/IO32RSB0
GBC0/IO30RSB0
IO29RSB0
IO28RSB0
3-6
v1.5
IGLOO PLUS Packaging
201-Pin CSP
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Note: This is the bottom view of the package.
Figure 3-3 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx.
v1.5
3-7
Package Pin Assignments
201-Pin CSP
Pin Number AGLP030 Function
201-Pin CSP
201-Pin CSP
Pin Number AGLP030 Function
Pin Number AGLP030 Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
B1
NC
C7
C8
IO23RSB0
IO19RSB0
IO28RSB0
IO32RSB0
IO35RSB0
NC
F6
F7
GND
VCC
IO04RSB0
IO06RSB0
IO09RSB0
IO11RSB0
IO13RSB0
IO17RSB0
IO18RSB0
IO24RSB0
IO26RSB0
IO27RSB0
IO31RSB0
NC
C9
F8
VCCIB0
C10
C11
C12
C13
C14
C15
D1
F9
VCCIB0
F10
F12
F13
F14
F15
G1
VCCIB0
NC
GND
NC
IO41RSB1
IO37RSB1
IO117RSB3
IO118RSB3
NC
IO40RSB1
IO38RSB1
NC
D2
G2
IO112RSB3
IO110RSB3
IO109RSB3
VCCIB3
GND
D3
G3
D4
GND
G4
NC
D5
IO01RSB0
IO03RSB0
IO10RSB0
IO21RSB0
IO25RSB0
IO30RSB0
IO33RSB0
GND
G6
NC
D6
G7
NC
D7
G8
VCC
B2
NC
D8
G9
GND
B3
IO08RSB0
IO05RSB0
IO07RSB0
IO15RSB0
IO14RSB0
IO16RSB0
IO20RSB0
IO22RSB0
IO34RSB0
IO29RSB0
NC
D9
G10
G12
G13
G14
G15
H1
GND
B4
D10
D11
D12
D13
D14
D15
E1
NC
B5
NC
B6
IO42RSB1
IO44RSB1
NC
B7
NC
B8
IO36RSB1
IO39RSB1
IO115RSB3
IO114RSB3
NC
B9
H2
GEB0/IO106RSB3
GEC0/IO108RSB3
NC
B10
B11
B12
B13
B14
B15
C1
H3
E2
H4
E3
H6
VCCIB3
GND
E4
NC
H7
NC
E12
E13
E14
E15
F1
NC
H8
VCC
NC
NC
H9
GND
NC
GDC0/IO46RSB1
GDB0/IO48RSB1
IO113RSB3
IO116RSB3
IO119RSB3
IO111RSB3
H10
H12
H13
H14
H15
J1
VCCIB1
C2
NC
IO54RSB1
GDA0/IO47RSB1
IO45RSB1
C3
GND
C4
IO00RSB0
IO02RSB0
IO12RSB0
F2
C5
F3
IO43RSB1
C6
F4
GEA0/IO107RSB3
3-8
v1.5
IGLOO PLUS Packaging
201-Pin CSP
201-Pin CSP
201-Pin CSP
Pin Number AGLP030 Function
Pin Number AGLP030 Function
Pin Number AGLP030 Function
J2
J3
IO105RSB3
IO104RSB3
IO102RSB3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
N1
GND
NC
P10
P11
P12
P13
P14
P15
R1
IO73RSB2
IO76RSB2
IO67RSB2
IO64RSB2
VPUMP
J4
IO79RSB2
IO77RSB2
IO72RSB2
IO70RSB2
IO61RSB2
IO59RSB2
GND
J6
VCCIB3
J7
GND
VCC
J8
TRST
J9
GND
NC
J10
J12
J13
J14
J15
K1
K2
K3
K4
K6
K7
K8
K9
K10
K12
K13
K14
K15
L1
VCCIB1
NC
R2
NC
R3
IO91RSB2
FF/IO90RSB2
IO89RSB2
IO83RSB2
IO82RSB2
IO85RSB2
IO78RSB2
IO69RSB2
IO62RSB2
IO60RSB2
TMS
NC
NC
R4
IO52RSB1
IO50RSB1
IO103RSB3
IO101RSB3
IO99RSB3
IO100RSB3
GND
IO55RSB1
IO56RSB1
NC
R5
R6
R7
N2
NC
R8
N3
GND
R9
N4
NC
R10
R11
R12
R13
R14
R15
N5
IO88RSB2
IO81RSB2
IO75RSB2
IO68RSB2
IO66RSB2
IO65RSB2
IO71RSB2
IO63RSB2
GND
VCCIB2
N6
VCCIB2
N7
VCCIB2
VCCIB1
N8
TDI
N9
TCK
NC
N10
N11
N12
N13
N14
N15
P1
IO57RSB1
IO49RSB1
IO53RSB1
IO96RSB3
IO98RSB3
IO95RSB3
IO94RSB3
NC
TDO
L2
VJTAG
L3
NC
L4
P2
NC
L12
L13
L14
L15
M1
M2
M3
P3
NC
NC
P4
NC
IO51RSB1
IO58RSB1
IO93RSB3
IO92RSB3
IO97RSB3
P5
IO87RSB2
IO86RSB2
IO84RSB2
IO80RSB2
IO74RSB2
P6
P7
P8
P9
v1.5
3-9
Package Pin Assignments
201-Pin CSP
Pin Number AGLP060 Function
201-Pin CSP
201-Pin CSP
Pin Number AGLP060 Function
Pin Number AGLP060 Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
B1
IO150RSB3
GAA0/IO00RSB0
GAC0/IO04RSB0
IO08RSB0
C7
C8
IO16RSB0
IO21RSB0
F6
F7
GND
VCC
C9
IO28RSB0
F8
VCCIB0
C10
C11
C12
C13
C14
C15
D1
GBB1/IO33RSB0
GBA1/IO35RSB0
GBB2/IO38RSB1
GND
F9
VCCIB0
IO11RSB0
F10
F12
F13
F14
F15
G1*
G2
VCCIB0
IO47RSB1
IO45RSB1
GCC1/IO52RSB1
GCA1/IO56RSB1
VCOMPLF
IO15RSB0
IO17RSB0
IO18RSB0
IO48RSB1
IO22RSB0
IO39RSB1
IO26RSB0
IO146RSB3
IO144RSB3
IO148RSB3
GND
IO29RSB0
D2
GFB0/IO137RSB3
GFC0/IO139RSB3
IO143RSB3
VCCIB3
GBC1/IO31RSB0
GBA2/IO36RSB1
IO41RSB1
D3
G3
D4
G4
D5
GAB0/IO02RSB0
GAC1/IO05RSB0
IO14RSB0
G6
NC
D6
G7
GND
IO151RSB3
GAB2/IO154RSB3
IO06RSB0
D7
G8
VCC
B2
D8
IO19RSB0
G9
GND
B3
D9
GBC0/IO30RSB0
GBB0/IO32RSB0
GBA0/IO34RSB0
GND
G10
G12
G13
G14
G15
H1*
H2
GND
B4
IO09RSB0
D10
D11
D12
D13
D14
D15
E1
IO50RSB1
GCB1/IO54RSB1
GCC2/IO60RSB1
GCA2/IO58RSB1
VCCPLF
B5
IO13RSB0
B6
IO10RSB0
B7
IO12RSB0
GBC2/IO40RSB1
IO51RSB1
B8
IO20RSB0
B9
IO23RSB0
IO44RSB1
GFA1/IO136RSB3
GFB1/IO138RSB3
NC
B10
B11
B12
B13
B14
B15
C1
IO25RSB0
IO142RSB3
IO149RSB3
IO153RSB3
GAC2/IO152RSB3
IO43RSB1
H3
IO24RSB0
E2
H4
IO27RSB0
E3
H6
VCCIB3
IO37RSB1
E4
H7
GND
IO46RSB1
E12
E13
E14
E15
F1
H8
VCC
IO42RSB1
IO49RSB1
H9
GND
IO155RSB3
GAA2/IO156RSB3
GND
GCC0/IO53RSB1
GCB0/IO55RSB1
IO141RSB3
GFC1/IO140RSB3
IO145RSB3
IO147RSB3
H10
H12
H13
H14
H15
J1
VCCIB1
C2
GCB2/IO59RSB1
GCA0/IO57RSB1
IO64RSB1
C3
C4
GAA1/IO01RSB0
GAB1/IO03RSB0
IO07RSB0
F2
C5
F3
IO62RSB1
C6
F4
GFA2/IO134RSB3
* Pin numbers G1 and H1 must be connected to ground because a PLL is not supported for AGLP060-CS/G201.
3-10
v1.5
IGLOO PLUS Packaging
201-Pin CSP
201-Pin CSP
201-Pin CSP
Pin Number AGLP060 Function
Pin Number AGLP060 Function
Pin Number AGLP060 Function
J2
J3
GFA0/IO135RSB3
GFB2/IO133RSB3
IO131RSB3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
N1
GND
IO125RSB3
IO98RSB2
P10
P11
P12
P13
P14
P15
R1
IO92RSB2
IO95RSB2
J4
IO86RSB2
J6
V
CCIB3
IO96RSB2
IO83RSB2
J7
GND
VCC
IO91RSB2
VPUMP
J8
IO89RSB2
TRST
J9
GND
IO82RSB2
IO118RSB3
GEB0/IO113RSB3
GEA2/IO110RSB2
J10
J12
J13
J14
J15
K1
K2
VCCIB1
GDA2/IO78RSB2
GND
R2
IO61RSB1
IO63RSB1
IO68RSB1
IO66RSB1
IO130RSB3
GFC2/IO132RSB3
IO127RSB3
IO129RSB3
GND
R3
GDA1/IO76RSB1
GDA0/IO77RSB1
GDB0/IO75RSB1
IO117RSB3
IO120RSB3
GND
R4
FF/GEB2/IO109RSB
2
R5
R6
GEC2/IO108RSB2
IO102RSB2
IO101RSB2
IO104RSB2
IO97RSB2
IO88RSB2
IO81RSB2
GDB2/IO79RSB2
TMS
R7
N2
R8
K3
K4
K6
N3
R9
N4
GEB1/IO114RSB3
IO107RSB2
IO100RSB2
IO94RSB2
R10
R11
R12
R13
R14
R15
N5
K7
K8
K9
K10
K12
K13
K14
K15
L1
VCCIB2
N6
VCCIB2
N7
VCCIB2
VCCIB1
N8
IO87RSB2
TDI
N9
IO85RSB2
TCK
IO65RSB1
N10
N11
N12
N13
N14
N15
P1
GDC2/IO80RSB2
IO90RSB2
IO67RSB1
IO69RSB1
IO84RSB2
IO70RSB1
GND
IO126RSB3
IO128RSB3
IO121RSB3
IO123RSB3
GDB1/IO74RSB1
GDC1/IO72RSB1
IO71RSB1
TDO
L2
VJTAG
L3
GEC0/IO115RSB3
GEC1/IO116RSB3
GEA0/IO111RSB3
GEA1/IO112RSB3
IO106RSB2
IO105RSB2
IO103RSB2
IO99RSB2
L4
P2
L12
L13
L14
L15
M1
M2
M3
P3
P4
P5
GDC0/IO73RSB1
IO122RSB3
IO124RSB3
IO119RSB3
P6
P7
P8
P9
IO93RSB2
v1.5
3-11
Package Pin Assignments
281-Pin CSP
19 18 17 16 1514 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Note: This is the bottom view of the package.
Figure 3-4 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx
3-12
v1.5
IGLOO PLUS Packaging
281-Pin CSP
281-Pin CSP
281-Pin CSP
Pin Number AGLP125 Function
Pin Number AGLP125 Function
Pin Number AGLP125 Function
A1
A2
GND
GAB0/IO02RSB0
GAC1/IO05RSB0
IO09RSB0
B18
B19
C1
VCCIB1
IO64RSB1
E13
E14
E15
E16
E18
E19
F1
IO48RSB0
GBB1/IO60RSB0
IO53RSB0
A3
GAB2/IO209RSB3
IO210RSB3
IO12RSB0
A4
C2
IO69RSB1
A5
IO13RSB0
C6
IO68RSB1
A6
IO15RSB0
C14
C18
C19
D1
IO47RSB0
IO71RSB1
A7
IO18RSB0
IO54RSB0
IO198RSB3
GND
A8
IO23RSB0
GBB2/IO65RSB1
IO206RSB3
IO208RSB3
GAA0/IO00RSB0
GAA1/IO01RSB0
IO10RSB0
F2
A9
IO25RSB0
F3
IO201RSB3
IO204RSB3
IO16RSB0
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
B1
VCCIB0
D2
F4
IO33RSB0
D4
F5
IO41RSB0
D5
F15
F16
F17
F18
F19
G1
IO50RSB0
IO43RSB0
D6
IO74RSB1
IO46RSB0
D7
IO17RSB0
IO72RSB1
IO55RSB0
D8
IO24RSB0
GND
IO56RSB0
D9
IO27RSB0
IO73RSB1
GBC1/IO58RSB0
GBA0/IO61RSB0
GND
D10
D11
D12
D13
D14
D15
D16
D18
D19
E1
GND
IO195RSB3
IO200RSB3
IO202RSB3
IO08RSB0
IO31RSB0
G2
IO40RSB0
G4
GAA2/IO211RSB3
VCCIB0
IO49RSB0
G5
B2
IO45RSB0
G7
GAC2/IO207RSB3
VCCIB0
B3
GAB1/IO03RSB0
GAC0/IO04RSB0
IO11RSB0
GBB0/IO59RSB0
GBA2/IO63RSB1
GBC2/IO67RSB1
IO66RSB1
G8
B4
G9
IO26RSB0
B5
G10
G11
G12
G13
G15
G16
G18
G19
H1
IO35RSB0
B6
GND
IO44RSB0
B7
IO21RSB0
IO203RSB3
IO205RSB3
IO07RSB0
VCCIB0
B8
IO22RSB0
E2
IO51RSB0
B9
IO28RSB0
E4
IO70RSB1
B10
B11
B12
B13
B14
B15
B16
B17
IO32RSB0
E5
IO06RSB0
IO75RSB1
IO36RSB0
E6
IO14RSB0
GCC0/IO80RSB1
GCB1/IO81RSB1
GFB0/IO191RSB3
IO196RSB3
GFC1/IO194RSB3
GFB1/IO192RSB3
VCCIB3
IO39RSB0
E7
IO20RSB0
IO42RSB0
E8
IO29RSB0
GND
E9
IO34RSB0
H2
IO52RSB0
E10
E11
E12
IO30RSB0
H4
GBC0/IO57RSB0
GBA1/IO62RSB0
IO37RSB0
H5
IO38RSB0
H7
v1.5
3-13
Package Pin Assignments
281-Pin CSP
Pin Number AGLP125 Function
281-Pin CSP
281-Pin CSP
Pin Number AGLP125 Function
Pin Number AGLP125 Function
H8
H9
VCC
VCCIB0
VCC
K15
K16
K18
K19
L1
IO89RSB1
GND
N4
N5
IO182RSB3
IO161RSB2
H10
H11
H12
H13
H15
H16
H18
H19
J1
IO88RSB1
N7
GEA2/IO164RSB2
V
CCIB0
VCC
VCCIB1
N8
VCCIB2
GFB2/IO187RSB3
IO185RSB3
GFC2/IO186RSB3
IO184RSB3
IO199RSB3
VCCIB3
N9
IO137RSB2
IO135RSB2
IO131RSB2
VCCIB2
VCCIB1
IO77RSB1
GCB0/IO82RSB1
GCA1/IO83RSB1
GCA2/IO85RSB1
VCOMPLF
L2
N10
N11
N12
N13
N15
N16
N18
N19
P1
L4
L5
L7
VPUMP
L8
IO117RSB2
IO96RSB1
L9
GND
J2
GFA0/IO189RSB3
VCCPLF
L10
L11
L12
L13
L15
L16
L18
L19
M1
M2
M4
M5
M7
M8
M9
M10
M11
M12
M13
M15
M16
M18
M19
N1
GND
IO98RSB1
J4
GND
IO94RSB1
J5
GFC0/IO193RSB3
GFA2/IO188RSB3
VCCIB3
VCCIB1
IO174RSB3
GND
J7
IO95RSB1
IO91RSB1
NC
P2
J8
P3
IO176RSB3
IO177RSB3
GEA0/IO165RSB3
IO111RSB2
IO108RSB2
GDC1/IO99RSB1
GND
J9
GND
P4
J10
J11
J12
J13
J15
J16
J18
J19
K1
GND
IO90RSB1
NC
P5
GND
P15
P16
P17
P18
P19
R1
VCCIB1
IO180RSB3
IO179RSB3
IO181RSB3
IO183RSB3
VCCIB3
GCC1/IO79RSB1
GCA0/IO84RSB1
GCB2/IO86RSB1
IO76RSB1
IO78RSB1
VCCIB3
IO97RSB1
IO173RSB3
IO172RSB3
GEC1/IO170RSB3
GEB1/IO168RSB3
IO154RSB2
IO149RSB2
IO146RSB2
IO138RSB2
IO134RSB2
IO132RSB2
IO130RSB2
IO118RSB2
IO112RSB2
VCC
R2
VCCIB2
R4
K2
GFA1/IO190RSB3
GND
VCC
R5
K4
VCCIB2
R6
K5
IO19RSB0
IO197RSB3
VCC
VCC
R7
K7
VCCIB1
R8
K8
IO122RSB2
IO93RSB1
IO92RSB1
NC
R9
K9
GND
R10
R11
R12
R13
R14
K10
K11
K12
K13
GND
GND
VCC
IO178RSB3
IO175RSB3
GCC2/IO87RSB1
N2
3-14
v1.5
IGLOO PLUS Packaging
281-Pin CSP
281-Pin CSP
Pin Number AGLP125 Function
Pin Number AGLP125 Function
R15
R16
R18
R19
T1
IO109RSB2
GDA1/IO103RSB1
GDB0/IO102RSB1
GDC0/IO100RSB1
IO171RSB3
GEC0/IO169RSB3
GEB0/IO167RSB3
IO157RSB2
IO158RSB2
IO148RSB2
IO145RSB2
IO143RSB2
GND
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
W1
IO133RSB2
IO127RSB2
IO123RSB2
IO120RSB2
GND
T2
IO113RSB2
GDA2/IO105RSB2
TDI
T4
T5
T6
VCCIB2
T7
TDO
T8
GND
T9
W2
FF/GEB2/IO163RSB2
IO155RSB2
IO152RSB2
IO150RSB2
IO147RSB2
IO142RSB2
IO139RSB2
IO136RSB2
VCCIB2
T10
T11
T12
T13
T14
T15
T16
T18
T19
U1
W3
IO129RSB2
IO126RSB2
IO125RSB2
IO116RSB2
GDC2/IO107RSB2
TMS
W4
W5
W6
W7
W8
W9
VJTAG
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
GDB1/IO101RSB1
IO160RSB2
GEA1/IO166RSB3
IO151RSB2
IO121RSB2
TRST
IO128RSB2
IO124RSB2
IO119RSB2
IO115RSB2
IO114RSB2
IO110RSB2
GDB2/IO106RSB2
TCK
U2
U6
U14
U18
U19
V1
GDA0/IO104RSB1
IO159RSB2
VCCIB3
V2
GND
V3
GEC2/IO162RSB2
IO156RSB2
IO153RSB2
GND
V4
V5
V6
V7
IO144RSB2
IO141RSB2
IO140RSB2
V8
V9
v1.5
3-15
Package Pin Assignments
289-Pin CSP
A1 Ball Pad Corner
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Note: This is the bottom view of the package.
Figure 3-5 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.actel.com/products/solutions/package/docs.aspx .
3-16
v1.5
IGLOO PLUS Packaging
289-Pin CSP
289-Pin CSP
289-Pin CSP
Pin Number AGLP030 Function
Pin Number AGLP030 Function
Pin Number AGLP030 Function
A1
A2
IO03RSB0
NC
C5
C6
VCCIB0
IO09RSB0
IO13RSB0
IO15RSB0
IO21RSB0
GND
E9
E10
E11
E12
E13
E14
E15
E16
E17
F1
IO22RSB0
IO26RSB0
A3
NC
C7
VCCIB0
A4
GND
C8
NC
A5
IO10RSB0
IO14RSB0
IO16RSB0
IO18RSB0
GND
C9
IO33RSB0
IO36RSB1
IO38RSB1
A6
C10
C11
C12
C13
C14
C15
C16
C17
D1
A7
IO29RSB0
NC
A8
VCCIB1
A9
NC
NC
A10
A11
A12
A13
A14
A15
A16
A17
B1
IO23RSB0
IO27RSB0
NC
NC
IO111RSB3
NC
GND
F2
IO34RSB0
NC
F3
IO116RSB3
NC
F4
VCCIB3
GND
NC
F5
IO117RSB3
NC
NC
D2
IO119RSB3
GND
F6
NC
D3
F7
NC
IO30RSB0
IO01RSB0
GND
D4
IO02RSB0
NC
F8
IO08RSB0
IO12RSB0
NC
D5
F9
B2
D6
NC
F10
F11
F12
F13
F14
F15
F16
F17
G1
B3
NC
D7
NC
NC
B4
NC
D8
GND
NC
B5
IO07RSB0
NC
D9
IO20RSB0
IO25RSB0
NC
NC
B6
D10
D11
D12
D13
D14
D15
D16
D17
E1
GND
B7
V
CCIB0
NC
B8
IO17RSB0
IO19RSB0
IO24RSB0
IO28RSB0
NC
IO37RSB1
IO41RSB1
IO110RSB3
GND
B9
GND
B10
B11
B12
B13
B14
B15
B16
B17
C1
IO32RSB0
IO35RSB0
NC
G2
V
CCIB0
NC
G3
IO113RSB3
NC
NC
G4
NC
V
CCIB3
G5
NC
NC
E2
IO114RSB3
IO115RSB3
IO118RSB3
IO05RSB0
NC
G6
NC
IO31RSB0
GND
E3
G7
GND
E4
G8
GND
NC
E5
G9
VCC
C2
IO00RSB0
IO04RSB0
NC
E6
G10
G11
G12
GND
C3
E7
IO06RSB0
IO11RSB0
GND
C4
E8
IO40RSB1
v1.5
3-17
Package Pin Assignments
289-Pin CSP
Pin Number AGLP030 Function
289-Pin CSP
289-Pin CSP
Pin Number AGLP030 Function
Pin Number AGLP030 Function
G13
G14
G15
G16
G17
H1
NC
IO39RSB1
IO44RSB1
NC
J17
K1
GDA0/IO47RSB1
GND
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
N1
IO98RSB3
IO93RSB3
IO97RSB3
NC
K2
GEB0/IO106RSB3
IO102RSB3
IO104RSB3
IO99RSB3
NC
K3
GND
K4
NC
NC
K5
IO71RSB2
NC
H2
GEC0/IO108RSB3
NC
K6
H3
K7
GND
IO63RSB2
NC
H4
IO112RSB3
NC
K8
GND
H5
K9
GND
IO57RSB1
NC
H6
IO109RSB3
GND
K10
K11
K12
K13
K14
K15
K16
K17
L1
GND
H7
GND
NC
H8
GND
NC
NC
H9
GND
NC
VCCIB1
H10
H11
H12
H13
H14
H15
H16
H17
J1
GND
NC
NC
GND
IO53RSB1
GND
N2
NC
NC
N3
IO95RSB3
IO96RSB3
GND
NC
IO49RSB1
IO103RSB3
IO101RSB3
NC
N4
IO45RSB1
N5
V
CCIB1
L2
N6
NC
GDB0/IO48RSB1
IO42RSB1
L3
N7
IO85RSB2
IO79RSB2
IO77RSB2
L4
GND
N8
NC
L5
NC
N9
J2
GEA0/IO107RSB3
L6
NC
N10
N11
N12
N13
N14
N15
N16
N17
P1
V
CCIB2
NC
J3
V
CCIB3
L7
GND
J4
IO105RSB3
NC
L8
GND
NC
J5
L9
VCC
IO59RSB2
NC
J6
NC
L10
L11
L12
L13
L14
L15
L16
L17
M1
M2
M3
GND
J7
VCC
GND
GND
J8
GND
IO58RSB1
IO54RSB1
IO56RSB1
IO55RSB1
IO94RSB3
NC
J9
GND
J10
J11
J12
J13
J14
J15
J16
GND
V
CCIB1
NC
VCC
P2
IO50RSB1
IO43RSB1
IO51RSB1
IO52RSB1
GDC0/IO46RSB1
NC
P3
GND
NC
P4
NC
NC
P5
NC
V
CCIB3
P6
IO87RSB2
IO80RSB2
IO100RSB3
P7
3-18
v1.5
IGLOO PLUS Packaging
289-Pin CSP
289-Pin CSP
Pin Number AGLP030 Function
Pin Number AGLP030 Function
P8
P9
GND
IO72RSB2
IO67RSB2
IO61RSB2
NC
T12
T13
T14
T15
T16
T17
U1
IO64RSB2
NC
P10
P11
P12
P13
P14
P15
P16
P17
R1
GND
NC
TDI
VCCIB2
TDO
NC
FF/IO90RSB2
GND
IO60RSB2
IO62RSB2
VJTAG
GND
U2
U3
NC
U4
IO88RSB2
IO86RSB2
IO82RSB2
GND
U5
R2
IO91RSB2
NC
U6
R3
U7
R4
NC
U8
IO75RSB2
IO73RSB2
IO68RSB2
IO66RSB2
GND
R5
NC
U9
R6
V
CCIB2
U10
U11
U12
U13
U14
U15
U16
U17
R7
IO83RSB2
IO78RSB2
IO74RSB2
IO70RSB2
GND
R8
R9
NC
R10
R11
R12
R13
R14
R15
R16
R17
T1
NC
NC
NC
TCK
NC
VPUMP
NC
NC
TMS
TRST
IO92RSB3
IO89RSB2
NC
T2
T3
T4
GND
T5
NC
T6
IO84RSB2
IO81RSB2
IO76RSB2
T7
T8
T9
VCCIB2
T10
T11
IO69RSB2
IO65RSB2
v1.5
3-19
Package Pin Assignments
289-Pin CSP
Pin Number AGLP060 Function
289-Pin CSP
289-Pin CSP
Pin Number AGLP060 Function
Pin Number AGLP060 Function
A1
A2
GAB1/IO03RSB0
NC
C5
C6
VCCIB0
IO09RSB0
IO13RSB0
IO15RSB0
IO21RSB0
GND
E9
E10
E11
E12
E13
E14
E15
E16
E17
F1
IO22RSB0
IO26RSB0
A3
NC
C7
VCCIB0
A4
GND
C8
NC
A5
IO10RSB0
IO14RSB0
IO16RSB0
IO18RSB0
GND
C9
GBB1/IO33RSB0
GBA2/IO36RSB1
GBB2/IO38RSB1
A6
C10
C11
C12
C13
C14
C15
C16
C17
D1
A7
IO29RSB0
NC
A8
VCCIB1
A9
NC
IO44RSB1
GFC1/IO140RSB3
IO142RSB3
A10
A11
A12
A13
A14
A15
A16
A17
B1
IO23RSB0
IO27RSB0
NC
NC
GND
F2
GBA0/IO34RSB0
IO39RSB1
IO150RSB3
IO151RSB3
GND
F3
IO149RSB3
NC
F4
VCCIB3
GND
F5
GAB2/IO154RSB3
IO153RSB3
NC
NC
D2
F6
NC
D3
F7
GBC0/IO30RSB0
GAA1/IO01RSB0
GND
D4
GAB0/IO02RSB0
NC
F8
IO08RSB0
IO12RSB0
NC
D5
F9
B2
D6
NC
F10
F11
F12
F13
F14
F15
F16
F17
G1
B3
NC
D7
NC
NC
B4
NC
D8
GND
NC
B5
IO07RSB0
NC
D9
IO20RSB0
IO25RSB0
NC
GBC2/IO40RSB1
GND
B6
D10
D11
D12
D13
D14
D15
D16
D17
E1
B7
V
CCIB0
IO43RSB1
IO46RSB1
IO45RSB1
GFC0/IO139RSB3
GND
B8
IO17RSB0
IO19RSB0
IO24RSB0
IO28RSB0
VCCIB0
NC
B9
GND
B10
B11
B12
B13
B14
B15
B16
B17
C1
GBB0/IO32RSB0
GBA1/IO35RSB0
IO37RSB1
IO42RSB1
G2
G3
IO144RSB3
IO145RSB3
IO146RSB3
IO148RSB3
GND
NC
G4
NC
VCCIB3
G5
NC
E2
IO147RSB3
GAC2/IO152RSB3
GAA2/IO156RSB3
GAC1/IO05RSB0
NC
G6
GBC1/IO31RSB0
GND
E3
G7
E4
G8
GND
IO155RSB3
GAA0/IO00RSB0
GAC0/IO04RSB0
NC
E5
G9
VCC
C2
E6
G10
G11
G12
GND
C3
E7
IO06RSB0
GND
C4
E8
IO11RSB0
IO48RSB1
3-20
v1.5
IGLOO PLUS Packaging
289-Pin CSP
289-Pin CSP
289-Pin CSP
Pin Number AGLP060 Function
Pin Number AGLP060 Function
Pin Number AGLP060 Function
G13
G14
G15
G16
G17
H1
IO41RSB1
IO47RSB1
IO49RSB1
IO50RSB1
GND
J17
K1
GCA1/IO56RSB1
GND
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
N1
IO122RSB3
GEB0/IO113RSB3
GEB1/IO114RSB3
NC
K2
GFA0/IO135RSB3
GFB2/IO133RSB3
IO128RSB3
IO123RSB3
IO125RSB3
GND
K3
K4
NC
VCOMPLF
K5
IO90RSB2
NC
H2
GFB0/IO137RSB3
NC
K6
H3
K7
IO83RSB2
NC
H4
IO141RSB3
IO143RSB3
GFB1/IO138RSB3
GND
K8
GND
H5
K9
GND
GDA1/IO76RSB1
GDA0/IO77RSB1
IO71RSB1
IO69RSB1
H6
K10
K11
K12
K13
K14
K15
K16
K17
L1
GND
H7
GND
H8
GND
IO64RSB1
IO61RSB1
IO66RSB1
IO65RSB1
GND
H9
GND
VCCIB1
H10
H11
H12
H13
H14
H15
H16
H17
J1
GND
IO119RSB3
IO120RSB3
GEC0/IO115RSB3
GEA0/IO111RSB3
GND
GND
N2
GCC1/IO52RSB1
IO51RSB1
GCA0/IO57RSB1
N3
GCC2/IO60RSB1
GFA2/IO134RSB3
GFC2/IO132RSB3
IO127RSB3
GND
N4
N5
V
CCIB1
L2
N6
NC
GCA2/IO58RSB1
GCC0/IO53RSB1
VCCPLF
L3
N7
IO104RSB2
IO98RSB2
L4
N8
L5
IO121RSB3
GEC1/IO116RSB3
GND
N9
IO96RSB2
J2
GFA1/IO136RSB3
VCCIB3
L6
N10
N11
N12
N13
N14
N15
N16
N17
P1
VCCIB2
J3
L7
NC
J4
IO131RSB3
IO130RSB3
IO129RSB3
VCC
L8
GND
NC
J5
L9
VCC
GDB2/IO79RSB2
NC
J6
L10
L11
L12
L13
L14
L15
L16
L17
M1
M2
M3
GND
J7
GND
GND
J8
GND
GDC1/IO72RSB1
GDB1/IO74RSB1
GDB0/IO75RSB1
GDC0/IO73RSB1
IO118RSB3
IO117RSB3
GND
J9
GND
J10
J11
J12
J13
J14
J15
J16
GND
VCCIB1
VCC
IO70RSB1
IO68RSB1
IO67RSB1
IO126RSB3
P2
GCB2/IO59RSB1
GCB1/IO54RSB1
IO62RSB1
IO63RSB1
GCB0/IO55RSB1
P3
P4
NC
P5
NC
VCCIB3
P6
IO106RSB2
IO99RSB2
IO124RSB3
P7
v1.5
3-21
Package Pin Assignments
289-Pin CSP
Pin Number AGLP060 Function
289-Pin CSP
Pin Number AGLP060 Function
P8
P9
GND
IO91RSB2
IO86RSB2
IO81RSB2
NC
T12
T13
T14
T15
T16
T17
U1
IO82RSB2
NC
P10
P11
P12
P13
P14
P15
P16
P17
R1
GND
NC
TDI
V
CCIB2
NC
TDO
FF/GEB2/IO109RSB2
GND
GDA2/IO78RSB2
U2
GDC2/IO80RSB2
U3
NC
VJTAG
U4
IO107RSB2
IO105RSB2
IO101RSB2
GND
GND
U5
R2
GEA2/IO110RSB2
U6
R3
NC
NC
NC
U7
R4
U8
IO94RSB2
IO92RSB2
IO87RSB2
IO85RSB2
GND
R5
U9
R6
V
CCIB2
U10
U11
U12
U13
U14
U15
U16
U17
R7
IO102RSB2
IO97RSB2
IO93RSB2
IO89RSB2
GND
R8
R9
NC
R10
R11
R12
R13
R14
R15
R16
R17
T1
NC
NC
NC
TCK
NC
VPUMP
NC
NC
TMS
TRST
GEA1/IO112RSB3
GEC2/IO108RSB2
NC
T2
T3
T4
GND
T5
NC
T6
IO103RSB2
IO100RSB2
IO95RSB2
T7
T8
T9
VCCIB2
T10
T11
IO88RSB2
IO84RSB2
3-22
v1.5
IGLOO PLUS Packaging
289-Pin CSP
289-Pin CSP
289-Pin CSP
Pin Number AGLP125 Function
Pin Number AGLP125 Function
Pin Number AGLP125 Function
A1
A2
GAB1/IO03RSB0
IO11RSB0
IO08RSB0
GND
C5
C6
VCCIB0
IO17RSB0
IO23RSB0
IO27RSB0
IO33RSB0
GND
E9
E10
E11
E12
E13
E14
E15
E16
E17
F1
IO32RSB0
IO36RSB0
A3
C7
VCCIB0
A4
C8
IO56RSB0
A5
IO19RSB0
IO24RSB0
IO26RSB0
IO30RSB0
GND
C9
GBB1/IO60RSB0
GBA2/IO63RSB1
GBB2/IO65RSB1
A6
C10
C11
C12
C13
C14
C15
C16
C17
D1
A7
IO43RSB0
IO45RSB0
IO50RSB0
IO52RSB0
GND
A8
VCCIB1
A9
IO73RSB1
GFC1/IO194RSB3
IO196RSB3
A10
A11
A12
A13
A14
A15
A16
A17
B1
IO35RSB0
IO38RSB0
IO40RSB0
IO42RSB0
GND
F2
GBA0/IO61RSB0
IO68RSB1
IO204RSB3
IO205RSB3
GND
F3
IO202RSB3
F4
VCCIB3
F5
GAB2/IO209RSB3
IO208RSB3
IO14RSB0
IO20RSB0
IO25RSB0
IO29RSB0
IO51RSB0
IO53RSB0
GBC2/IO67RSB1
GND
IO48RSB0
IO54RSB0
GBC0/IO57RSB0
GAA1/IO01RSB0
GND
D2
F6
D3
F7
D4
GAB0/IO02RSB0
IO07RSB0
IO10RSB0
IO18RSB0
GND
F8
D5
F9
B2
D6
F10
F11
F12
F13
F14
F15
F16
F17
G1
B3
IO06RSB0
IO13RSB0
IO15RSB0
IO21RSB0
D7
B4
D8
B5
D9
IO34RSB0
IO41RSB0
IO47RSB0
IO55RSB0
GND
B6
D10
D11
D12
D13
D14
D15
D16
D17
E1
B7
V
CCIB0
IO75RSB1
IO71RSB1
IO77RSB1
GFC0/IO193RSB3
GND
B8
IO28RSB0
IO31RSB0
IO37RSB0
IO39RSB0
B9
B10
B11
B12
B13
B14
B15
B16
B17
C1
GBB0/IO59RSB0
GBA1/IO62RSB0
IO66RSB1
IO70RSB1
G2
V
CCIB0
G3
IO198RSB3
IO203RSB3
IO201RSB3
IO206RSB3
GND
IO44RSB0
IO46RSB0
G4
V
CCIB3
G5
IO49RSB0
E2
IO200RSB3
GAC2/IO207RSB3
GAA2/IO211RSB3
GAC1/IO05RSB0
IO12RSB0
G6
GBC1/IO58RSB0
GND
E3
G7
E4
G8
GND
IO210RSB3
GAA0/IO00RSB0
GAC0/IO04RSB0
IO09RSB0
E5
G9
VCC
C2
E6
G10
G11
G12
GND
C3
E7
IO16RSB0
GND
C4
E8
IO22RSB0
IO72RSB1
v1.5
3-23
Package Pin Assignments
289-Pin CSP
Pin Number AGLP125 Function
289-Pin CSP
289-Pin CSP
Pin Number AGLP125 Function
Pin Number AGLP125 Function
G13
G14
G15
G16
G17
H1
IO64RSB1
IO69RSB1
IO78RSB1
IO76RSB1
GND
J17
K1
GCA1/IO83RSB1
GND
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
N1
IO172RSB3
GEB0/IO167RSB3
GEB1/IO168RSB3
IO159RSB2
K2
GFA0/IO189RSB3
GFB2/IO187RSB3
IO179RSB3
IO175RSB3
IO177RSB3
GND
K3
K4
IO161RSB2
VCOMPLF
K5
IO135RSB2
H2
GFB0/IO191RSB3
IO195RSB3
IO197RSB3
IO199RSB3
GFB1/IO192RSB3
GND
K6
IO128RSB2
H3
K7
IO121RSB2
H4
K8
GND
IO113RSB2
H5
K9
GND
GDA1/IO103RSB1
GDA0/IO104RSB1
IO97RSB1
H6
K10
K11
K12
K13
K14
K15
K16
K17
L1
GND
H7
GND
H8
GND
IO88RSB1
IO94RSB1
IO95RSB1
IO93RSB1
GND
IO96RSB1
H9
GND
VCCIB1
H10
H11
H12
H13
H14
H15
H16
H17
J1
GND
IO180RSB3
IO178RSB3
GEC0/IO169RSB3
GEA0/IO165RSB3
GND
GND
N2
GCC1/IO79RSB1
IO74RSB1
GCA0/IO84RSB1
N3
GCC2/IO87RSB1
GFA2/IO188RSB3
GFC2/IO186RSB3
IO182RSB3
GND
N4
N5
V
CCIB1
L2
N6
IO156RSB2
IO148RSB2
IO144RSB2
IO137RSB2
GCA2/IO85RSB1
GCC0/IO80RSB1
VCCPLF
L3
N7
L4
N8
L5
IO173RSB3
GEC1/IO170RSB3
GND
N9
J2
GFA1/IO190RSB3
VCCIB3
L6
N10
N11
N12
N13
N14
N15
N16
N17
P1
VCCIB2
J3
L7
IO119RSB2
IO111RSB2
GDB2/IO106RSB2
IO109RSB2
GND
J4
IO185RSB3
IO183RSB3
IO181RSB3
VCC
L8
GND
J5
L9
VCC
J6
L10
L11
L12
L13
L14
L15
L16
L17
M1
M2
M3
GND
J7
GND
J8
GND
GDC1/IO99RSB1
GDB1/IO101RSB1
GDB0/IO102RSB1
GDC0/IO100RSB1
IO174RSB3
IO171RSB3
GND
J9
GND
J10
J11
J12
J13
J14
J15
J16
GND
VCCIB1
VCC
IO98RSB1
IO92RSB1
IO91RSB1
IO184RSB3
P2
GCB2/IO86RSB1
GCB1/IO81RSB1
IO90RSB1
IO89RSB1
GCB0/IO82RSB1
P3
P4
IO160RSB2
IO157RSB2
IO154RSB2
IO152RSB2
P5
V
CCIB3
P6
IO176RSB3
P7
3-24
v1.5
IGLOO PLUS Packaging
289-Pin CSP
289-Pin CSP
Pin Number AGLP125 Function
Pin Number AGLP125 Function
P8
P9
GND
T12
T13
T14
T15
T16
T17
U1
IO124RSB2
IO122RSB2
GND
IO132RSB2
IO125RSB2
IO126RSB2
IO112RSB2
P10
P11
P12
P13
P14
P15
P16
P17
R1
IO115RSB2
TDI
VCCIB2
TDO
IO108RSB2
GDA2/IO105RSB2
GDC2/IO107RSB2
VJTAG
FF/GEB2/IO163RSB2
GND
U2
U3
IO151RSB2
IO149RSB2
IO146RSB2
IO142RSB2
GND
U4
GND
U5
R2
GEA2/IO164RSB2
IO158RSB2
U6
R3
U7
R4
IO155RSB2
U8
IO138RSB2
IO136RSB2
IO133RSB2
IO129RSB2
GND
R5
IO150RSB2
U9
R6
V
CCIB2
U10
U11
U12
U13
U14
U15
U16
U17
R7
IO145RSB2
IO141RSB2
IO134RSB2
IO130RSB2
GND
R8
R9
IO123RSB2
IO120RSB2
IO117RSB2
TCK
R10
R11
R12
R13
R14
R15
R16
R17
T1
IO118RSB2
IO116RSB2
IO114RSB2
IO110RSB2
TMS
VPUMP
TRST
GEA1/IO166RSB3
GEC2/IO162RSB2
IO153RSB2
GND
T2
T3
T4
T5
IO147RSB2
IO143RSB2
IO140RSB2
IO139RSB2
T6
T7
T8
T9
VCCIB2
T10
T11
IO131RSB2
IO127RSB2
v1.5
3-25
Package Pin Assignments
Part Number and Revision Date
Part Number 51700102-003-5
Revised January 2009
List of Changes
The following table lists critical changes that were made in the current version of the chapter.
Previous Version
Changes in Current Version (v1.5)
Page
v1.4
(August 2008)
The "201-Pin CSP" pin table was revised to add a note regarding pins G1 and
H1.
3-10
v1.3
The "128-Pin VQFP" package drawing and pin table are new.
The "176-Pin VQFP" package drawing and pin table are new.
The "281-Pin CSP" package drawing is new.
3-1
3-4
(June 2008)
v1.2
3-12
3-13
3-16
(June 2008)
The "281-Pin CSP" table for the AGLP125 device is new.
The "289-Pin CSP" package drawing was incorrect. The graphic was showing
the CS281 mechanical drawing and not the CS289 mechanical drawing. This
has now been corrected.
v1.1
The "289-Pin CSP" table for the AGLP030 device is new.
3-17
(June 2008)
v1.0
The "289-Pin CSP" table for the AGLP060 device is new.
The "289-Pin CSP" table for the AGLP125 device is new.
3-20
3-23
(January 2008)
3-26
v1.5
IGLOO PLUS Packaging
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheets are published before data
has been fully characterized. Datasheets are designated as "Product Brief," "Advance,"
"Preliminary," and "Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains
general product information. This document gives an overview of specific device and family
information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or
speed grades. This information can be used as estimates, but not for production. This label only
applies to the DC and Switching Characteristics chapter of the datasheet and will only be used
when the data has not been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The
information is believed to be correct, but changes are possible.
Unmarked (production)
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations
(EAR). They could require an approved export license prior to export from the United States. An
export includes release of product or disclosure of technology to a foreign national inside or
outside the United States.
Actel Safety Critical, Life Support, and High-Reliability
Applications Policy
The Actel products described in this advance status document may not have completed Actel’s
qualification process. Actel may amend or enhance products during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the
responsibility of each customer to ensure the fitness of any Actel product (but especially a new
product) for a particular purpose, including appropriateness for safety-critical, life-support, and
other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability
exclusions relating to life-support applications. A reliability report covering all of Actel’s products is
available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also
offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your
local Actel sales office for additional reliability information.
v1.5
3-27
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
Actel is the leader in low-power and mixed-signal FPGAs and offers the most comprehensive portfolio of
system and power management solutions. Power Matters. Learn more at www.actel.com.
Actel Corporation
Actel Europe Ltd.
Actel Japan
Actel Hong Kong
2061 Stierlin Court
Mountain View, CA
94043-4655 USA
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Camberley Surrey GU17 9AB
United Kingdom
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Tokyo 150 Japan
Phone 650.318.4200
Fax 650.318.4600
Phone +81.03.3445.7671
Fax +81.03.3445.7668
Phone +852 2185 6460
Fax +852 2185 6488
Phone +44 (0) 1276 609 300
Fax +44 (0) 1276 607 540
http://jp.actel.com
www.actel.com.cn
51700102-005-8/1.09
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