AX250-1CQ208M [MICROSEMI]

Field Programmable Gate Array, 2816 CLBs, 250000 Gates, 763MHz, 4224-Cell, CMOS, CQFP208;


型号：	AX250-1CQ208M
厂家：	Microsemi
描述：	Field Programmable Gate Array, 2816 CLBs, 250000 Gates, 763MHz, 4224-Cell, CMOS, CQFP208 栅
文件：	总262页 (文件大小：13015K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Revision 18

Axcelerator Family FPGAs

– Voltage-Referenced I/O Standards: GTL+, HSTL Class 1,

SSTL2 Class 1 and 2, SSTL3 Class 1 and 2

– Registered I/Os

– Hot-Swap Compliant I/Os (except PCI)

– Programmable Slew Rate and Drive Strength on Outputs

– Programmable Delay and Weak Pull-Up/Pull-Down Circuits

on Inputs

Embedded Memory:

– Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4, x9, x18,

x36 Organizations Available)

– Independent, Width-Configurable Read and Write Ports

– Programmable Embedded FIFO Control Logic

Segmentable Clock Resources

Embedded Phase-Locked Loop:

– 14-200 MHz Input Range

– Frequency Synthesis Capabilities up to 1 GHz

Deterministic, User-Controllable Timing

Unique In-System Diagnostic and Debug Capability with

Microsemi Silicon Explorer II

Boundary-Scan Testing Compliant with IEEE Standard 1149.1

(JTAG)

FuseLock™ Programming Technology Protects Against

Reverse Engineering and Design Theft

Leading-Edge Performance

•

350+ MHz System Performance

500+ MHz Internal Performance

High-Performance Embedded FIFOs

700 Mb/s LVDS Capable I/Os

Specifications

•

Up to 2 Million Equivalent System Gates

Up to 684 I/Os

Up to 10,752 Dedicated Flip-Flops

Up to 295 kbits Embedded SRAM/FIFO

Manufactured on Advanced 0.15 μm CMOS Antifuse Process

Technology, 7 Layers of Metal

•

Features

•

Single-Chip, Nonvolatile Solution

Up to 100% Resource Utilization with 100% Pin Locking

1.5 V Core Voltage for Low Power

Footprint Compatible Packaging

Flexible, Multi-Standard I/Os:

•

– 1.5 V, 1.8 V, 2.5 V, 3.3 V Mixed Voltage Operation

– Bank-Selectable I/Os – 8 Banks per Chip

– Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V PCI,

and 3.3 V PCI-X

– Differential I/O Standards: LVPECL and LVDS

Table 1 • Axcelerator Family Product Profile

Device

AX125

125,000

82,000

AX250

250,000

154,000

AX500

500,000

286,000

AX1000

1,000,000

612,000

AX2000

2,000,000

1,060,000

Capacity (in Equivalent System Gates)

Typical Gates

Modules

Combinatorial (C-cells)

Maximum Flip-Flops

Embedded RAM/FIFO

Number of Core RAM Blocks

Total Bits of Core RAM

Clocks (Segmentable)

Hardwired

672

1,408

2,816

2,688

5,376

6,048

12,096

10,752

21,504

1,344

18,432

55,296

73,728

165,888

294,912

Routed

PLLs

I/Os

I/O Banks

Maximum User I/Os

Maximum LVDS Channels

Total I/O Registers

168

248

124

744

336

516

684

168

258

342

504

1,008

1,548

2,052

Package

208

729

484, 676, 896

352

256, 324

256, 484

208, 352

484, 676

208, 352

896, 1152

256, 352

624

March 2012

Axcelerator Family FPGAs

Ordering Information

AX1000

896

Application

Blank =Commercial (0 to +70° C)

PP =Pre-Production

I =Industrial (-40 to +85° C)

M =Military (-55 to +125° C)

Package Lead Count

Lead-Free Packaging

Blank = Standard Packaging

G= RoHS-Compliant Packaging

Package Type

BG Ball Grid Array (1.27mm pitch)

FG Fine Ball Grid Array (1.0mm pitch)

PQ Plastic Quad Flat Pack (0.5mm pitch)

CQ Ceramic Quad Flat Pack (0.5mm pitch)

CG Ceramic Column Grid Array

Speed Grade

Blank Standard Speed

Approximately 15% Faster than Standard

Approximately 25% Faster than Standard

Part Number

AX125 = 125,000 Equivalent System Gates

AX250 = 250,000 Equivalent System Gates

AX500 = 500,000 Equivalent System Gates

AX1000 = 1,000,000 Equivalent System Gates

AX2000 = 2,000,000 Equivalent System Gates

Device Resources

User I/Os (Including Clock Buffers)

Package

PQ208

CQ208

CQ256

FG256

FG324

CQ352

FG484

CG624

FG676

BG729

FG896

FG1152

AX125

AX250

115

–

AX500

115

–

AX1000

AX2000

–

136

–

138

168

–

138

–

198

248

–

198

317

–

198

317

418

516

–

198

–

418

–

336

–

586

684

–

Note: The FG256, FG324, and FG484 are footprint compatible with one another. The FG676, FG896, and FG1152 are also footprint

compatible with one another.

Revision 18

Axcelerator Family FPGAs

Axcelerator Family Device Status

Axcelerator^®Devices

Status

AX125

Production

AX250

AX500

AX1000

AX2000

Temperature Grade Offerings

Package

PQ208

CQ208

CQ256

FG256

FG324

CQ352

FG484

CG624

FG676

BG729

FG896

FG1152

AX125

AX250

AX500

AX1000

AX2000

–

C, I, M

–

C, I

–

C, I, M

–

C, I, M

–

C, I, M

–

C, I, M

–

C = Commercial

I = Industrial

M = Military

Speed Grade and Temperature Grade Matrix

Temperature Grade

Std

–1

–2

–

C = Commercial

I = Industrial

M = Military

Revision 18

iii

Axcelerator Family FPGAs

Packaging Data

Refer to the following documents located on the Microsemi SoC Products Group website for additional packaging information.

Package Mechanical Drawings

Package Thermal Characteristics and Weights

Hermatic Package Mechanical Information

Contact your local Microsemi representative for device availability.

Revision 18

Axcelerator Family FPGAs

Table of Contents

General Description

Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

Detailed Specifications

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Voltage-Referenced I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43

Differential Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50

Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54

Routing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61

Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66

Axcelerator Clock Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-75

Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-86

Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-106

Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-110

Package Pin Assignments

BG729 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

FG324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21

FG676 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37

FG896 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52

FG1152 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-71

PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-84

CQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89

CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94

CQ352 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-98

CG624 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

Revision 18

1 – General Description

Axcelerator devices offer high performance at densities of up to two million equivalent system gates.

Based upon the Microsemi AX architecture, Axcelerator has several system-level features such as

embedded SRAM (with complete FIFO control logic), PLLs, segmentable clocks, chip-wide highway

routing, and carry logic.

Device Architecture

AX architecture, derived from the highly-successful SX-A sea-of-modules architecture, has been

designed for high performance and total logic module utilization (Figure 1-1). Unlike in traditional FPGAs,

the entire floor of the Axcelerator device is covered with a grid of logic modules, with virtually no chip

area lost to interconnect elements or routing.

Programmable Interconnect Element

The Axcelerator family uses a patented metal-to-metal antifuse programmable interconnect element that

resides between the upper two layers of metal (Figure 1-2 on page 1-2). This completely eliminates the

channels of routing and interconnect resources between logic modules (as implemented on traditional

FPGAs) and enables the efficient sea-of-modules architecture. The antifuses are normally open circuit

and, when programmed, form a permanent, passive, low-impedance connection, leading to the fastest

signal propagation in the industry. In addition, the extremely small size of these interconnect elements

gives the Axcelerator family abundant routing resources.

The very nature of Microsemi's nonvolatile antifuse technology provides excellent protection against

design pirating and cloning (FuseLock technology). Typical cloning attempts are impossible (even if the

security fuse is left unprogrammed) as no bitstream or programming file is ever downloaded or stored in

the device. Reverse engineering is virtually impossible due to the difficulty of trying to distinguish

between programmed and unprogrammed antifuses and also due to the programming methodology of

antifuse devices (see "Security" on page 2-108).

Routing

Switch

Matrix

Logic Block

Sea-of-Modules

Architecture

Traditional FPGA

Architecture

Logic

Modules

Figure 1-1 • Sea-of-Modules Comparison

Revision 18

1-1

General Description

Figure 1-2 • Axcelerator Family Interconnect Elements

Logic Modules

Microsemi's Axcelerator family provides two types of logic modules: the register cell (R-cell) and the

combinatorial cell (C-cell). The Axcelerator device can implement more than 4,000 combinatorial

functions of up to five inputs (Figure 1-3).

FCI

A[1:0]

PSET

CLR

B[1:0]

C-cell

D[3:0]

CLK

CFN

(Positive Edge Triggered)

R-Cell

FCO

C-Cell

Figure 1-3 • AX C-Cell and R-Cell

The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and active-low enable

control signals (Figure 1-3). The R-cell registers feature programmable clock polarity selectable on a

functions into the FPGA) while conserving valuable clock resources. The clock source for the R-cell can

be chosen from the hardwired clocks, routed clocks, or internal logic.

1-2

Revision 18

Axcelerator Family FPGAs

Two C-cells, a single R-cell, two Transmit (TX), and two Receive (RX) routing buffers form a Cluster,

while two Clusters comprise a SuperCluster (Figure 1-4). Each SuperCluster also contains an

independent Buffer (B) module, which supports buffer insertion on high-fanout nets by the place-and-

route tool, minimizing system delays while improving logic utilization.

C C R

Figure 1-4 • AX SuperCluster

The logic modules within the SuperCluster are arranged so that two combinatorial modules are side-by-

side, giving a C–C–R – C–C–R pattern to the SuperCluster. This C–C–R pattern enables efficient

implementation (minimum delay) of two-bit carry logic for improved arithmetic performance (Figure 1-5

on page 1-3).

FCI

DCOUT

C-Cell

Carry Logic

FCO

Figure 1-5 • AX 2-Bit Carry Logic

The AX architecture is fully fracturable, meaning that if one or more of the logic modules in a

SuperCluster are used by a particular signal path, the other logic modules are still available for use by

other paths.

At the chip level, SuperClusters are organized into core tiles, which are arrayed to build up the full chip.

For example, the AX1000 is composed of a 3x3 array of nine core tiles. Surrounding the array of core

tiles are blocks of I/O Clusters and the I/O bank ring (Table 1-1). Each core tile consists of an array of 336

SuperClusters and four SRAM blocks (176 SuperClusters and three SRAM blocks for the AX250).

Table 1-1 • Number of Core Tiles per Device

Device

AX125

AX250

AX500

AX1000

AX2000

Number of Core Tiles

1 regular tile

4 smaller tiles

4 regular tiles

9 regular tiles

16 regular tiles

Revision 18

1-3

General Description

The SRAM blocks are arranged in a column on the west side of the tile (Figure 1-6 on page 1-4).

SuperCluster

RAMC SC

SC RD SC

RAM/

FIFO

RAMC SC

SC RD SC

RAM/

FIFO

RAMC SC

SC RD SC

RAMC SC

SC RD SC

RAM/

FIFO

Chip Layout

RAMC SC

SC RD SC

RAMC SC

SC RD SC

Core Tile

RAM/

FIFO

RAMC SC

SC RD SC

I/O Structure

See Figure 7

Figure 1-6 • AX Device Architecture (AX1000 shown)

Embedded Memory

As mentioned earlier, each core tile has either three (in a smaller tile) or four (in the regular tile)

embedded SRAM blocks along the west side, and each variable-aspect-ratio SRAM block is 4,608 bits in

size. Available memory configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or 4kx1 bits. The

individual blocks have separate read and write ports that can be configured with different bit widths on

each port. For example, data can be written in by eight and read out by one.

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM

block to be configured as a synchronous FIFO without using core logic modules. The FIFO width and

depth are programmable. The FIFO also features programmable ALMOST-EMPTY (AEMPTY) and

ALMOST-FULL (AFULL) flags in addition to the normal EMPTY and FULL flags. In addition to the flag

logic, the embedded FIFO control unit also contains the counters necessary for the generation of the

read and write address pointers as well as control circuitry to prevent metastability and erroneous

operation. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

I/O Logic

The Axcelerator family of FPGAs features a flexible I/O structure, supporting a range of mixed voltages

with its bank-selectable I/Os: 1.5V, 1.8V, 2.5V, and 3.3V. In all, Axcelerator FPGAs support at least 14

different I/O standards (single-ended, differential, voltage-referenced). The I/Os are organized into

banks, with eight banks per device (two per side). The configuration of these banks determines the I/O

standards supported (see "User I/Os" on page 2-11 for more information). All I/O standards are available

in each bank.

Each I/O module has an input register (InReg), an output register (OutReg), and an enable register

(EnReg) (Figure 1-7 on page 1-5). An I/O Cluster includes two I/O modules, four RX modules, two TX

modules, and a buffer (B) module.

1-4

Revision 18

Axcelerator Family FPGAs

I/O Module

InReg

OutReg

EnReg

RAM/

FIFO

I/O

I/O Cluster

Module

RX RX

RAM/

FIFO

RAM/

FIFO

CoreTile

RAM/

FIFO

Figure 1-7 • I/O Cluster Arrangement

Routing

The AX hierarchical routing structure ties the logic modules, the embedded memory blocks, and the I/O

modules together (Figure 1-8 on page 1-6). At the lowest level, in and between SuperClusters, there are

three local routing structures: FastConnect, DirectConnect, and CarryConnect routing. DirectConnects

provide the highest performance routing inside the SuperClusters by connecting a C-cell to the adjacent

R-cell. DirectConnects do not require an antifuse to make the connection and achieve a signal

propagation time of less than 0.1 ns.

FastConnects provide high-performance, horizontal routing inside the SuperCluster and vertical routing

to the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect

path, delivering a maximum routing delay of 0.4 ns.

CarryConnects are used for routing carry logic between adjacent SuperClusters. They connect the FCO

output of one two-bit, C-cell carry logic to the FCI input of the two-bit, C-cell carry logic of the

SuperCluster below it. CarryConnects do not require an antifuse to make the connection and achieve a

signal propagation time of less than 0.1 ns.

The next level contains the core tile routing. Over the SuperClusters within a core tile, both vertical and

horizontal tracks run across rows or columns, respectively. At the chip level, vertical and horizontal tracks

extend across the full length of the device, both north-to-south and east-to-west. These tracks are

composed of highway routing that extend the entire length of the device (segmented at core tile

boundaries) as well as segmented routing of varying lengths.

Revision 18

1-5

General Description

Figure 1-8 • AX Routing Structures

Global Resources

Each family member has three types of global signals available to the designer: HCLK, CLK, and

GCLR/GPSET. There are four hardwired clocks (HCLK) per device that can directly drive the clock input

of each R-cell. Each of the four routed clocks (CLK) can drive the clock, clear, preset, or enable pin of an

R-cell or any input of a C-cell (Figure 1-3 on page 1-2).

Global clear (GCLR) and global preset (GPSET) drive the clear and preset inputs of each R-cell as well

as each I/O Register on a chip-wide basis at power-up.

Each HCLK and CLK has an associated analog PLL (a total of eight per chip). Each embedded PLL can

be used for clock delay minimization, clock delay adjustment, or clock frequency synthesis. The PLL is

capable of operating with input frequencies ranging from 14 MHz to 200 MHz and can generate output

frequencies between 20 MHz and 1 GHz. The clock can be either divided or multiplied by factors ranging

from 1 to 64. Additionally, multiply and divide settings can be used in any combination as long as the

resulting clock frequency is between 20 MHz and 1 GHz. Adjacent PLLs can be cascaded to create

complex frequency combinations.

The PLL can be used to introduce either a positive or a negative clock delay of up to 3.75 ns in 250 ps

increments. The reference clock required to drive the PLL can be derived from three sources: external

input pad (either single-ended or differential), internal logic, or the output of an adjacent PLL.

Low Power (LP) Mode

The AX architecture was created for high-performance designs but also includes a low power mode

(activated via the LP pin). When the low power mode is activated, I/O banks can be disabled (inputs

disabled, outputs tristated), and PLLs can be placed in a power-down mode. All internal register states

are maintained in this mode. Furthermore, individual I/O banks can be configured to opt out of the LP

mode, thereby giving the designer access to critical signals while the rest of the chip is in low power

mode.

The power can be further reduced by providing an external voltage source (V_PUMP) to the device to

bypass the internal charge pump (See "Low Power Mode" on page 2-106 for more information).

1-6

Revision 18

Axcelerator Family FPGAs

Design Environment

The Axcelerator family of FPGAs is fully supported by both Microsemi's Libero^®Integrated Design

Environment and Designer FPGA Development software. Libero IDE is an integrated design manager

that seamlessly integrates design tools while guiding the user through the design flow, managing all

design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows

users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a

single environment (see the Libero IDE Flow diagram located on the Microsemi SoC Products Group

website). Libero IDE includes Synplify^®Actel Edition (AE) from Synplicity^®, ViewDraw^®AE from Mentor

Graphics^®, ModelSim^®HDL Simulator from Mentor Graphics, WaveFormer Lite™ AE from

SynaptiCAD^®, and Designer software from Microsemi.

Designer software is a place-and-route tool and provides a comprehensive suite of backend support

tools for FPGA development. The Designer software includes the following:

•

Timer – a world-class integrated static timing analyzer and constraints editor which support

timing-driven place-and-route

•

NetlistViewer – a design netlist schematic viewer

ChipPlanner – a graphical floorplanner viewer and editor

SmartPower – allows the designer to quickly estimate the power consumption of a design

PinEditor – a graphical application for editing pin assignments and I/O attributes

I/O Attribute Editor – displays all assigned and unassigned I/O macros and their attributes in a

spreadsheet format

With the Designer software, a user can lock the design pins before layout while minimally impacting the

results of place-and-route. Additionally, Microsemi’s back-annotation flow is compatible with all the major

simulators and the simulation results can be cross-probed with Silicon Explorer II, Microsemi’s integrated

verification and logic analysis tool. Another tool included in the Designer software is the SmartGen core

generator, which easily creates popular and commonly used logic functions for implementation into your

schematic or HDL design.

Designer software is compatible with the most popular FPGA design entry and verification tools from

EDA vendors, such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The

Designer software is available for both the Windows and UNIX operating systems.

Programming

Programming support is provided through Silicon Sculptor II, a single-site programmer driven via a PC-

based GUI. In addition, BP Microsystems offers multi-site programmers that provide qualified support for

Microsemi devices. Factory programming is available for high-volume production needs.

In-System Diagnostic and Debug Capabilities

The Axcelerator family of FPGAs includes internal probe circuitry, allowing the designer to dynamically

observe and analyze any signal inside the FPGA without disturbing normal device operation (Figure 1-9).

Axcelerator FPGAs

16 Pin

Connection

TDI

TCK

TMS

TDO

Serial

Connection

Silicon Explorer II

PRA

PRB

22 Pin

Connection

CH3/PRC

CH4/PRD

Additional 14 Channels

(Logic Analyzer)

Figure 1-9 • Probe Setup

Revision 18

1-7

General Description

Up to four individual signals can be brought out to dedicated probe pins (PRA/B/C/D) on the device. The

probe circuitry is accessed and controlled via Silicon Explorer II, Microsemi's integrated verification and

logic analysis tool that attaches to the serial port of a PC and communicates with the FPGA via the JTAG

port (See "Silicon Explorer II Probe Interface" on page 2-109).

Summary

Microsemi’s Axcelerator family of FPGAs extends the successful SX-A architecture, adding embedded

RAM/FIFOs, PLLs, and high-speed I/Os. With the support of a suite of robust software tools, design

engineers can incorporate high gate counts and fixed pins into an Axcelerator design yet still achieve

high performance and efficient device utilization.

Related Documents

Application Notes

Simultaneous Switching Noise and Signal Integrity

http://www.microsemi.com/soc/documents/SSN_AN.pdf

Axcelerator Family PLL and Clock Management

http://www.microsemi.com/soc/documents/AX_PLL_AN.pdf

Implementation of Security in Actel Antifuse FPGAs

http://www.microsemi.com/soc/documents/Antifuse_Security_AN.pdf

User’s Guides and Manuals

Antifuse Macro Library Guide

http://www.microsemi.com/soc/documents/libguide_UG.pdf

SmartGen, FlashROM, Analog System Builder, and Flash Memory System Builder

http://www.microsemi.com/soc/documents/genguide_ug.pdf

Silicon Sculptor II User’s Guide

http://www.microsemi.com/soc/documents/silisculptII_sculpt3_ug.pdf

White Paper

Design Security in Nonvolatile Flash and Antifuse FPGAs

http://www.microsemi.com/soc/documents/DesignSecurity_WP.pdf

Understanding Actel Antifuse Device Security

http://www.microsemi.com/soc/documents/DesignSecurity_WP.pdf

Miscellaneous

Libero IDE flow diagram

http://www.microsemi.com/soc/products/tools/libero/flow.html

1-8

Revision 18

2 – Detailed Specifications

Operating Conditions

Table 2-1 lists the absolute maximum ratings of Axcelerator devices. Stresses beyond the ratings may

cause permanent damage to the device. Exposure to Absolute Maximum rated conditions for extended

periods may affect device reliability. Devices should not be operated outside the recommendations in

Table 2-2.

Table 2-1 • Absolute Maximum Ratings

Symbol

VCCA

VCCI

VREF

Parameter

Limits

Units

DC Core Supply Voltage

DC I/O Supply Voltage

DC I/O Reference Voltage

Input Voltage

–0.3 to 1.7

–0.3 to 3.75

–0.5 to 4.1

–0.5 to 3.75

–60 to +150

–0.3 to 3.75

Output Voltage

TSTG

Storage Temperature

°C

VCCDA* Supply Voltage for Differential I/Os

Note: * Should be the maximum of all VCCI.

Table 2-2 • Recommended Operating Conditions

Parameter Range

Commercial

0 to +70

Industrial

–40 to +85

Military

–55 to +125

1.425 to 1.575

1.71 to 1.89

2.375 to 2.625

3.0 to 3.6

Units

°C

Ambient Temperature (T_A)¹

1.5 V Core Supply Voltage

1.5 V I/O Supply Voltage

1.8 V I/O Supply Voltage

2.5 V I/O Supply Voltage

3.3 V I/O Supply Voltage

VCCDA Supply Voltage

VPUMP Supply Voltage

Notes:

1.425 to 1.575

1.71 to 1.89

2.375 to 2.625

3.0 to 3.6

1.425 to 1.575

1.71 to 1.89

2.375 to 2.625

3.0 to 3.6

1. Ambient temperature (T ) is used for commercial and industrial grades; case temperature (T ) is used for

military grades.

2. T max = 125°C

Power-Up/Down Sequence

All Axcelerator I/Os are tristated during power-up until normal device operating conditions are reached,

when I/Os enter user mode. VCCDA should be powered up before (or coincidentally with) VCCA and

VCCI to ensure the behavior of user I/Os at system start-up. Conversely, VCCDA should be powered

down after (or coincidentally with) VCCA and VCCI. Note that VCCI and VCCA can be powered up in any

sequence with respect to each other, provided the requirement with respect to VCCDA is satisfied.

Revision 18

2-1

Detailed Specifications

Calculating Power Dissipation

Table 2-3 • Standby Current

ICCA

ICCDA

ICCBANK

ICCPLL

ICCCP¹

Standby Current

per

Standby Current,

Charge Pump

Standby

Standby Current,

I/O Bank

Standby

Current

Current Differential 2.5 V

3.3 V

VCCI

Bypassed IIH, IIL,

per PLL Active Mode

IOZ²Units

Device

Temperature

Typical at 25°C

70°C

(Core)

1.5

I/O

1.5

VCCI

0.2

0.5

0.6

AX125

0.3

0.75

0.8

1.5

0.4

0.9

0.2

0.3

0.4

0.3

0.4

0.3

0.4

0.3

0.4

0.3

0.4

0.01

±0.01

0.01

0.2

85°C

125°C

0.5

AX250

AX500

Typical at 25°C

70°C

1.5

1.4

0.25

0.8

1.3

0.4

0.2

0.01

0.2

85°C

125°C

1.8

0.75

1.5

1.9

2.5

1.25

0.5

Typical at 25°C

70°C

1.4

0.2

0.01

0.2

85°C

125°C

180

7.5

1.75

0.5

1.5

0.2

0.5

AX1000 Typical at 25°C

1.5

0.01

0.2

70°C

85°C

120

200

3.4

125°C

1.6

1.5

0.2

0.5

AX2000 Typical at 25°C

0.7

1.5

0.01

0.2

70°C

160

200

500

85°C

125°C

1.5

0.5

Notes:

1. ICCCP Active is the ICCDA or the Internal Charge Pump current. ICCCP Bypassed mode is the External Charge Pump

current IIH (VPUMP pin).

2. IIH, IIL, or IOZ values are measured with inputs at the same level as VCCI for IIH and GND for IIL and IOZ.

2-2

Revision 18

Axcelerator Family FPGAs

Table 2-4 • Default CLOAD/VCCI

_LOAD(pF)

PLOAD

(mw/MHz)

VCCI (V)

P10 (mw/MHz) PI/O (mW/MHz)*

Single-Ended without VREF

LVTTL 24 mA High Slew

LVTTL 16 mA High Slew

LVTTL 12 mA High Slew

LVTTL 8 mA High Slew

LVTTL 24 mA Low Slew

LVTTL 16 mA Low Slew

LVTTL 12 mA Low Slew

LVTTL 8 mA Low Slew

LVCMOS – 25

3.3

2.5

1.8

1.5

3.3

381.2

218.8

113.4

78.8

267.5

225.1

165.9

130.3

169.2

150.8

138.6

118.7

148.0

73.4

648.7

606.3

547.1

511.5

550.4

532.0

519.8

499.9

366.8

186.8

128.3

327.4

271.8

LVCMOS – 18

LVCMOS – 15 (JESD8-11)

PCI

49.5

108.9

218.5

162.9

PCI-X

Single-Ended with VREF

HSTL-I

1.5

2.5

3.3

2.5

3.3

–

40.9

171.2

147.8

327.2

288.4

61.5

40.9

171.2

147.8

327.2

288.4

61.5

SSTL2-I

SSTL2-II

SSTL3-I

SSTL3-II

GTLP – 25

GTLP – 33

68.5

Differential

LVPECL – 33

N/A

3.3

2.5

–

260.6

145.8

260.6

145.8

LVDS – 25

Note: *P_I/O= P10 + C_LOAD* VCC_I²

Revision 18

2-3

Detailed Specifications

Table 2-5 • Different Components Contributing to the Total Power Consumption in Axcelerator Devices

Device Specific Value (in µW/MHz)

Component

Definition

Core tile HCLK power component

R-cell power component

AX125 AX250 AX500 AX1000 AX2000

P10

P11

0.2

4.5

0.2

4.5

0.2

130

0.2

216

0.2

HCLK signal power dissipation

Core tile RCLK power component

R-cell power component

13.5

130

0.3

1.6

1.4

216

0.3

6.5

0.3

6.5

1.6

1.4

RCLK signal power dissipation

19.5

1.6

Power dissipation due to the switching activity on the R-cell 1.6

Power dissipation due to the switching activity on the C-cell 1.4

1.6

1.4

Power component associated with the input voltage

Power component associated with the output voltage

See table Per pin contribution

Power component associated with the read operation in the 25

RAM block

P12

P13

Power component associated with the write operation in 30

the RAM block

Core PLL power component

1.5

Ptotal = Pdc + Pac

P_dc

P_ac

ICCA * VCCA

P_HCLK+ P_CLK+ P_R-cells+ P_C-cells+ P_inputs+ P_outputs+ P_memory+ P_PLL

P_HCLK= (P1 + P2 * s + P3 * sqrt[s]) * Fs

the number of R-cells clocked by this clock

the clock frequency

PCLK = (P4 + P5 * s + P6 * sqrt[s]) * Fs

the number of R-cells clocked by this clock

the clock frequency

PR-cells = P7 * ms * Fs

the number of R-cells switching at each Fs cycle

the clock frequency

PC-cells = P8 * mc * Fs

the number of C-cells switching at each Fs cycle

the clock frequency

Pinputs = P9 * pi * Fpi

the number of inputs

F_pi

the average input frequency

2-4

Revision 18

Axcelerator Family FPGAs

Poutputs = PI/O * po * Fpo

C_loadthe output load (technology dependent)

VCCI = the output voltage (technology dependent)

the number of outputs

F_po

the average output frequency

Pmemory = P11 * Nblock * FRCLK + P12 * Nblock * FWCLK

N_block= the number of RAM/FIFO blocks (1 block = 4k)

F_RCLK= the read-clock frequency of the memory

F_WCLK= the write-clock frequency of the memory

PPLL = P13 * FCLK

F_RefCLK= the clock frequency of the clock input of the PLL

F_CLK

= the clock frequency of the first clock output of the PLL

Power Estimation Example

This example employs an AX1000 shift-register design with 1,080 R-cells, one C-cell, one reset input,

and one LVTTL 12 mA output, with high slew.

This design uses one HCLK at 100 MHz.

1,080 (in a shift register - 100% of R-cells are toggling at each clock cycle)

100 MHz

1080

=> P_HCLK= (P1 + P2 * s + P3 * sqrt[s]) * Fs = 79 mW

and Fs = 100 MHz

=> P_R-cells= P7 * ms * Fs = 173 mW

1 (1 C-cell in this shift-register)

and Fs = 100 MHz

=> P_C-cells= P8 * mc * Fs = 0.14 mW

F_pi~ 0 MHz

and pi= 1 (1 reset input => this is why F_pi=0)

=> P_inputs= P9 * pi * F_pi= 0 mW

F_po= 50 MHz

and po = 1

=> P_outputs= P_I/O* po * F_po= 27.10 mW

No RAM/FIFO in this shift-register

=> P_memory= 0 mW

No PLL in this shift-register

=> P_PLL= 0 mW

P_ac= P_HCLK+ P_CLK+ P_R-cells+ P_C-cells+ P_inputs+ P_outputs+ P_memory+ P_PLL= 276 mW

P_dc= 7.5mA * 1.5V = 11.25 mW

P_total= P_dc+ P_ac= 11.25 mW + 276mW = 290.30 mW

Revision 18

2-5

Detailed Specifications

Thermal Characteristics

Introduction

The temperature variable in Microsemi’s Designer software refers to the junction temperature, not the

ambient temperature. This is an important distinction because dynamic and static power consumption

cause the chip junction temperature to be higher than the ambient temperature. EQ 1 can be used to

calculate junction temperature.

T_J= Junction Temperature = ΔT + T_a

EQ 1

Where:

T_a= Ambient Temperature

ΔT

Temperature gradient between junction (silicon) and ambient

ΔT = θ_ja* P

EQ 2

Where:

= Power

θ_ja= Junction to ambient of package. θ_janumbers are located under Table 2-6 on page 2-7.

Package Thermal Characteristics

The device junction-to-case thermal characteristic is θ_jc, and the junction-to-ambient air characteristic is

θ_ja. The thermal characteristics for θ_jaare shown with two different air flow rates. θ_jcvalues are provided

for reference. The absolute maximum junction temperature is 125°C.

The maximum power dissipation allowed for commercial- and industrial-grade devices is a function of θ_ja.

A sample calculation of the absolute maximum power dissipation allowed for an 896-pin FBGA package

at commercial temperature and still air is as follows:

Max. junction temp. (°C) – Max. ambient temp. (°C) 125°C – 70°C

Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------------------------- = --------------------------------------- = 4.04 W

θ_ja(°C/W)

13.6°C/W

2-6

Revision 18

Axcelerator Family FPGAs

The maximum power dissipation allowed for Military temperature and Mil-Std 883B devices is specified

as a function of θ_jc.

Table 2-6 • Package Thermal Characteristics

Package Type

Pin Count

180

θ_jc

N/A

8.0

2.2

3.0

3.2

2.4

1.8

2.0

6.5

θ_jaStill Air θ_ja1.0m/s θ_ja2.5m/s Units

Chip Scale Package (CSP)

Plastic Quad Flat Pack (PQFP)

Plastic Ball Grid Array (PBGA)

Fine Pitch Ball Grid Array (FBGA)

Ceramic Quad Flat Pack (CQFP)¹

Ceramic Column Grid Array (CCGA)²

Notes:

57.8

51.0

23.5

10.6

22.8

22.1

17.0

13.0

10.4

8.9

20.9

9.6

°C/W

208

729

13.7

26.6

25.8

20.5

16.4

13.6

12.0

256

21.5

20.9

15.9

12.0

9.4

324

484

676

896

1152

208

7.9

19.8

16.1

8.5

18.0

14.7

352

17.9

8.9

624

for the 208-pin and 352-pin CQFP refers to the thermal resistance between the junction and the

bottom of the package.

for the 624-pin CCGA refers to the thermal resistance between the junction and the top surface of the

package. Thermal resistance from junction to board (θ ) for CCGA 624 package is 3.4°C/W.

Timing Characteristics

Axcelerator devices are manufactured in a CMOS process, therefore, device performance varies

according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum

operating voltage, minimum operating temperature, and best-case processing. Maximum timing

parameters reflect minimum operating voltage, maximum operating temperature, and worst-case

processing. The derating factors shown in Table 2-7 should be applied to all timing data contained within

this datasheet.

Table 2-7 • Temperature and Voltage Timing Derating Factors

(Normalized to Worst-Case Commercial, T_J= 70°C, VCCA = 1.425V)

Junction Temperature

VCCA

1.4 V

–55°C

0.83

0.82

0.78

0.74

0.73

–40°C

0.86

0.84

0.80

0.76

0.75

0°C

0.91

0.90

0.85

0.81

0.80

25°C

0.96

0.94

0.89

0.85

0.84

70°C

1.02

1.00

0.95

0.90

0.89

85°C

1.05

1.04

0.98

0.94

0.92

125°C

1.15

1.13

1.07

1.02

1.01

1.425 V

1.5 V

1.575 V

1.6 V

Notes:

1. The user can set the junction temperature in Designer software to be any integer value in the range of –

55°C to 175°C.

2. The user can set the core voltage in Designer software to be any value between 1.4V and 1.6V.

All timing numbers listed in this datasheet represent sample timing characteristics of Axcelerator devices.

Actual timing delay values are design-specific and can be derived from the Timer tool in Microsemi’s

Designer software after place-and-route.

Revision 18

2-7

Detailed Specifications

Timing Model

I/O Module

(Nonregistered)

Carry Chain

t_PY= 2.24 ns

Combinatorial

Cell

Combinatorial

Cell

I/O

LVPECL

FCO

_PDC= 0.57 ns

t_CCY= 0.61 ns

I/O Module

(Registered)

I/O Module

(Nonregistered)

_RD2= 0.53 ns

Combinatorial

Cell

_DP= 1.66 ns

Buffer

Module

Buffer

Module

t_PY= 2.99 ns

LVPECL

LVTTL

Output Drive

Strength = 4 (24 mA)

High Slew Rate

t_BFPD= 0.12 ns

t_PD= 0.74 ns

_BFPD= 0.12 ns

t_RD1= 0.45 ns

t_RD2= 0.53 ns

_RD3= 0.56 ns

t_ICKLQ= 0.67 ns

t_SUD= 0.23 ns

Hardwired Clock

t_HCKH= 3.03 ns

_MAX(external) = 350 MHz

Combinatorial

Cell

_RD1= 0.45 ns

I/O Module

F_MAX(internal) = 870 MHz

t_IOCLKY= 0.67 ns

t_SUD= 0.23 ns

_RCO= 0.67 ns

t_SUD= 0.23 ns

Buffer

Module

t_PY= 1.13 ns

I/O Module

(Non- registered)

GTL + 3.3 V

t_BPFD= 0.12 ns

t_PD= 0.74 ns

_RCO= 0.67 ns

LVDS

t_RCKL= 3.08 ns

t_SUD= 0.23 ns

F_MAX(external) = 350 MHz

F_MAX(internal) = 870 MHz

Routed Clock

t_DP= 1.80 ns

Hardwired or

Routed Clock

t_HCKL= 3.02 ns

_RCKL= 3.08 ns

Note: Worst case timing data for the AX1000, –2 speed grade

Figure 2-1 • Worst Case Timing Data

Hardwired Clock – Using LVTTL 24 mA High Slew Clock I/O

External Setup

= (t_DP+ t_RD2+ t_SUD)– t_HCKL

= (1.72 + 0.53 + 0.23) – 3.02 = –0.54 ns

Clock-to-Out (Pad-to-Pad)

= t_HCKL+ t_RCO+ t_RD1+ t_PY

= 3.02 + 0.67 + 0.45 + 2.99 = 7.13 ns

Routed Clock – Using LVTTL 24 mA High Slew Clock I/O

External Setup

= (t_DP+ t_RD2+ t_SUD)– t_RCKH

= (1.72 + 0.53 + 0.23) – 3.13 = –0.65 ns

Clock-to-Out (Pad-to-Pad)

= t_RCKH+ t_RCO+ t_RD1+ t_PY

= 3.13 + 0.67 + 0.45 + 3.03 = 7.24 ns

2-8

Revision 18

Axcelerator Family FPGAs

I/O Specifications

Pin Descriptions

Supply Pins

GND

Ground

Low supply voltage.

VCCA

Supply Voltage

Supply voltage for array (1.5V). See "Operating Conditions" on page 2-1 for more information.

VCCIBx Supply Voltage

Supply voltage for I/Os. Bx is the I/O Bank ID – 0 to 7. See "Operating Conditions" on page 2-1 for more

information.

VCCDA

Supply Voltage

Supply voltage for the I/O differential amplifier and JTAG and probe interfaces. See "Operating

Conditions" on page 2-1 for more information. VCCDA should be tied to 3.3V.

VCCPLA/B/C/D/E/F/G/H

Supply Voltage

PLL analog power supply (1.5V) for internal PLL. There are eight in each device. VCCPLA supports the

PLL associated with global resource HCLKA, VCCPLB supports the PLL associated with global resource

HCLKB, etc. The PLL analog power supply pins should be connected to 1.5V whether PLL is used or not.

VCOMPLA/B/C/D/E/F/G/H Supply Voltage

Compensation reference signals for internal PLL. There are eight in each device. VCOMPLA supports

the PLL associated with global resource HCLKA, VCOMPLE supports the PLL associated with global

resource CLKE, etc. (see Figure 2-2 on page 2-9 for correct external connection to the supply). The

VCOMPLX pins should be left floating if PLL is not used.

VPUMP

Supply Voltage (External Pump)

In the low power mode, VPUMP will be used to access an external charge pump (if the user desires to

bypass the internal charge pump to further reduce power). The device starts using the external charge

pump when the voltage level on VPUMP reaches VIH¹. In normal device operation, when using the

internal charge pump, VPUMP should be tied to GND.

Axcelerator Chip

250 Ω

1.5 V Supply

VCCPLX

10 μf

0.1 μf

VCOMPLX

Figure 2-2 • VCCPLX and VCOMPLX Power Supply Connect

1. When V_PUMP= V_IH, it shuts off the internal charge pump. See "Low Power Mode" on page 2-106.

Revision 18

2-9

Detailed Specifications

User-Defined Supply Pins

VREF

Supply Voltage

Reference voltage for I/O banks. VREF pins are configured by the user from regular I/O pins; VREF pins

are not in fixed locations. There can be one or more VREF pins in an I/O bank.

Global Pins

HCLKA/B/C/D

Dedicated (Hardwired) Clocks A, B, C and D

These pins are the clock inputs for sequential modules or north PLLs. Input levels are compatible with all

supported I/O standards. There is a P/N pin pair for support of differential I/O standards. Single-ended

clock I/Os can only be assigned to the P side of a paired I/O. This input is directly wired to each R-cell

and offers clock speeds independent of the number of R-cells being driven. When the HCLK pins are

unused, it is recommended that they are tied to ground.

CLKE/F/G/H

Routed Clocks E, F, G, and H

These pins are clock inputs for clock distribution networks or south PLLs. Input levels are compatible with

all supported I/O standards. There is a P/N pin pair for support of differential I/O standards. Single-ended

clock I/Os can only be assigned to the P side of a paired I/O. The clock input is buffered prior to clocking

the R-cells. When the CLK pins are unused, Microsemi recommends that they are tied to ground.

JTAG/Probe Pins

PRA/B/C/D

Probe A, B, C and D

The Probe pins are used to output data from any user-defined design node within the device (controlled

with Silicon Explorer II). These independent diagnostic pins can be used to allow real-time diagnostic

output of any signal path within the device. The pins’ probe capabilities can be permanently disabled to

protect programmed design confidentiality. The probe pins are of LVTTL output levels.

TCK

Test clock input for JTAG boundary-scan testing and diagnostic probe (Silicon Explorer II).

TDI Test Data Input

Test Clock

Serial input for JTAG boundary-scan testing and diagnostic probe. TDI is equipped with an internal 10 kΩ

pull-up resistor.

TDO

Serial output for JTAG boundary-scan testing.

TMS Test Mode Select

Test Data Output

The TMS pin controls the use of the IEEE 1149.1 boundary-scan pins (TCK, TDI, TDO, TRST). TMS is

^{equipped with an internal 10 k}Ω pull-up resistor.

TRST

Boundary Scan Reset Pin

The TRST pin functions as an active-low input to asynchronously initialize or reset the boundary scan

^{circuit. The TRST pin is equipped with a 10 k}Ω pull-up resistor.

Special Functions

Low Power Pin

The LP pin controls the low power mode of Axcelerator devices. The device is placed in the low power

mode by connecting the LP pin to logic high. To exit the low power mode, the LP pin must be set Low.

Additionally, the LP pin must be set Low during chip powering-up or chip powering-down operations. See

"Low Power Mode" on page 2-106 for more details.

No Connection

This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be

left floating with no effect on the operation of the device.

2-10

Revision 18

Axcelerator Family FPGAs

User I/Os

Introduction

The Axcelerator family features a flexible I/O structure, supporting a range of mixed voltages (1.5 V,

1.8 V, 2.5 V, and 3.3 V) with its bank-selectable I/Os. Table 2-8 on page 2-12 contains the I/O standards

supported by the Axcelerator family, and Table 2-10 on page 2-12 compares the features of the different

I/O standards.

Each I/O provides programmable slew rates, drive strengths, and weak pull-up and weak pull-down

circuits. The slew rate setting is effective for both rising and falling edges.

I/O standards, except 3.3 V PCI and 3.3 V PCI-X, are capable of hot insertion. 3.3 V PCI and 3.3 V PCI-

X are 5 V tolerant with the aid of an external resistor.

The input buffer has an optional user-configurable delay element. The element can reduce or eliminate

the hold time requirement for input signals registered within the I/O cell. The value for the delay is set on

a bank-wide basis. Note that the delay WILL be a function of process variations as well as temperature

and voltage changes.

Each I/O includes three registers: an input (InReg), an output (OutReg), and an enable register (EnReg).

I/Os are organized into banks, and there are eight banks per device—two per side (Figure 2-6 on

page 2-18). Each I/O bank has a common VCCI, the supply voltage for its I/Os.

For voltage-referenced I/Os, each bank also has a common reference-voltage bus, VREF. While VREF

must have a common voltage for an entire I/O bank, its location is user-selectable. In other words, any

user I/O in the bank can be selected to be a VREF.

The location of the VREF pin should be selected according to the following rules:

•

Any pin that is assigned as a VREF can control a maximum of eight user I/O pad locations in each

direction (16 total maximum) within the same I/O bank.

•

I/O pad locations listed as no connects are counted as part of the 16 maximum. In many cases,

this leads to fewer than eight user I/O package pins in each direction being controlled by a VREF

pin.

•

Dedicated I/O pins such as GND and VCCI are counted as part of the 16.

The two user I/O pads immediately adjacent on each side of the VREF pin (four in total) may only

be used as inputs. The exception is when there is a VCCI/GND pair separating the VREF pin and

the user I/O pad location.

•

The user does not need to assign VREF pins for OUTBUF and TRIBUF. VREF pins are needed

only for input and bidirectional I/Os.

The differential amplifier supply voltage VCCDA should be connected to 3.3 V.

A user can gain access to the various I/O standards in three ways:

•

Instantiate specific library macros that represent the desired specific standard.

Use generic I/O macros and then use Designer’s PinEditor to specify the desired I/O standards

(please note that this is not applicable to differential standards).

•

A combination of the first two methods.

Refer to the I/O Features in Axcelerator Family Devices application note and the Antifuse Macro Library

Guide for more details.

2. Do not use an external resister to pull the I/O above V_CCIfor a higher logic “1” voltage level. The desired higher logic “1”

voltage level will be degraded due to a small I/O current, which exists when the I/O is pulled up above V_CCI

Revision 18

2-11

Detailed Specifications

Table 2-8 • I/O Standards Supported by the Axcelerator Family

Input/Output Supply

Voltage (VCCI)

Input Reference

Voltage (VREF)

Board Termination

Voltage (VTT)

I/O Standard

LVTTL

3.3

2.5

1.8

1.5

3.3

2.5

1.5

3.3

2.5

3.3

N/A

1.0

N/A

1.2

LVCMOS 2.5 V

LVCMOS 1.8 V

LVCMOS 1.5 V (JDEC8-11)

3.3V PCI/PCI-X

GTL+ 3.3 V

GTL+ 2.5 V^*

1.0

1.2

HSTL Class 1

SSTL3 Class 1 and II

SSTL2 Class1 and II

LVDS

0.75

1.5

0.75

1.5

1.25

N/A

1.25

N/A

LVPECL

Note: *2.5 V GTL+ is not supported across the full military temperature range.

Table 2-9 • Supply Voltages

VCCA

1.5 V

VCCI

1.5 V

1.8 V

2.5 V

3.3 V

Input Tolerance

3.3 V

Output Drive Level

1.5 V

1.8 V

2.5 V

3.3 V

Table 2-10 • I/O Features Comparison

Clamp

Diode

Hot

Insertion

5 V

Tolerance

Input

Buffer

Output

Buffer

I/O Assignment

LVTTL

Yes

Yes¹

Yes^{1, 2}

Enabled/Disabled

3.3 V PCI, 3.3 V PCI-X

LVCMOS 2.5 V

Yes

LVCMOS 1.8 V

LVCMOS 1.5 V (JESD8-11)

Voltage-Referenced Input Buffer

Differential, LVDS/LVPECL, Input

Differential, LVDS/LVPECL, Output

Notes:

Enabled

Disabled

Disabled³

Enabled⁴

1. Can be implemented with an IDT bus switch.

2. Can be implemented with an external resistor.

3. The OE input of the output buffer must be deasserted permanently (handled by software).

4. The OE input of the output buffer must be asserted permanently (handled by software).

2-12

Revision 18

Axcelerator Family FPGAs

5 V Tolerance

There are two schemes to achieve 5 V tolerance:

1. 3.3 V PCI and 3.3 V PCI-X are the only I/O standards that directly allow 5 V tolerance. To

implement this, an internal clamp diode between the input pad and the VCCI pad is enabled so

that the voltage at the input pin is clamped, as shown in EQ 3:

Vinput = VCCI + Vdiode = 3.3 V + 0.7 V = 4.0 V

EQ 3

The internal VCCI clamp diode is only enabled while the device is powered on, so the voltage at the input

will not be clamped if the VCCI or VCCA are powered off. An external series resistor (~100 Ω) is required

between the input pin and the 5 V signal source to limit the current to less than 20 mA (Figure 2-3). The

100 Ω resistor was chosen to meet the input Tr/Tf requirement (Table 2-19 on page 2-21). The GND

clamp diode is available for all I/O standards and always enabled.

Non-Microsemi Part

Mirosemi FPGA

3.3 V 3.3 V

5 V

VCCI

clamp

diode

ext

GND

Clamp

Diode

Figure 2-3 • Use of an External Resistor for 5 V Tolerance

2. 5 V tolerance can also be achieved with 3.3 V I/O standards (3.3 V PCI, 3.3 V PCI-X, and LVTTL)

using a bus-switch product (e.g. IDTQS32X2384). This will convert the 5 V signal to a 3.3 V signal

with minimum delay (Figure 2-4).

3.3 V

20X

5 V

3.3 V

Figure 2-4 • Bus Switch IDTQS32X2384

Simultaneous Switching Outputs (SSO)

When multiple output drivers switch simultaneously, they induce a voltage drop in the chip/package

power distribution. This simultaneous switching momentarily raises the ground voltage within the device

relative to the system ground. This apparent shift in the ground potential to a non-zero value is known as

simultaneous switching noise (SSN) or more commonly, ground bounce.

SSN becomes more of an issue in high pin count packages and when using high performance devices

such as the Axcelerator family. Based upon testing, Microsemi recommends that users not exceed eight

simultaneous switching outputs (SSO) per each VCCI/GND pair. To ease this potential burden on

designers, Microsemi has designed all of the Axcelerator BGAs³to not exceed this limit with the

exception of the CS180, which has an I/O to VCCI/GND pair ratio of nine to one.

Please refer to the Simultaneous Switching Noise and Signal Integrity application note for more

information.

3. The user should note that in Bank 8 of both AX1000-FG484 and AX500-FG484, there are local violations of this 8:1 ratio.

Revision 18

2-13

Detailed Specifications

I/O Banks and Compatibility

Since each I/O bank has its own user-assigned input reference voltage (VREF) and an input/output

supply voltage (VCCI), only I/Os with compatible standards can be assigned to the same bank.

Table 2-11 shows the compatible I/O standards for a common VREF (for voltage-referenced standards).

Similarly, Table 2-12 shows compatible standards for a common VCCI.

Table 2-11 • Compatible I/O Standards for Different VREF Values

VREF

1.5 V

Compatible Standards

SSTL 3 (Class I and II)

SSTL 2 (Class I and II)

GTL+ (2.5V and 3.3V Outputs)

HSTL (Class I)

1.25 V

1.0 V

0.75 V

Table 2-12 • Compatible I/O Standards for Different VCCI Values

VCCI¹

3.3 V

2.5 V

1.8 V

1.5 V

Notes:

Compatible Standards

LVTTL, PCI, PCI-X, LVPECL, GTL+ 3.3 V

VREF

1.0

SSTL 3 (Class I and II), LVTTL, PCI, LVPECL

LVCMOS 2.5 V, GTL+ 2.5 V, LVDS²

LVCMOS 2.5 V, SSTL 2 (Classes I and II), LVDS²

LVCMOS 1.8 V

1.5

1.0

1.25

N/A

0.75

LVCMOS 1.5 V, HSTL Class I

1. VCCI is used for both inputs and outputs

2. VCCI tolerance is ±5%

2-14

Revision 18

Axcelerator Family FPGAs

Table 2-13 summarizes the different combinations of voltages and I/O standards that can be used

together in the same I/O bank.

Table 2-13 • Legal I/O Usage Matrix

I/O Standard

LVTTL 3.3 V (VREF=1.0 V)

–

LVTTL 3.3 V(VREF=1.5 V)

LVCMOS 2.5 V (VREF=1.0 V)

LVCMOS 2.5 V (VREF=1.25V)

LVCMOS1.8 V

–

LVCMOS1.5 V (VREF = 1.75 V) (JESD8-11)

3.3 V PCI/PCI-X (VREF = 1.0 V)

3.3 V PCI/PCI-X (VREF= 1.5 V)

GTL + (3.3 V)

–

GTL + (2.5 V)

–

HSTL Class I

–

SSTL2 Class I & II

–

SSTL3 Class I & II

–

LVDS (VREF = 1.0 V)

LVDS (VREF = 1.25 V)

LVPECL (VREF = 1.0 V)

LVPECL (VREF = 1.5 V)

Notes:

–

1. Note that GTL+ 2.5 V is not supported across the full military temperature range.

2. A "✓" indicates whether standards can be used within a bank at the same time.

Examples:

a) LVTTL can be used with 3.3V PCI and GTL+ (3.3V), when V

= 1.0V (GTL+ requirement).

REF

b) LVTTL can be used with 3.3V PCI and SSTL3 Class I and II, when V

= 1.5V (SSTL3 requirement).

REF

Note that two I/O standards are compatible if:

•

Their VCCI values are identical.

Their VREF standards are identical (if applicable).

For example, if LVTTL 3.3 V (VREF= 1.0 V) is used, then the other available (i.e. compatible) I/O

standards in the same bank are LVTTL 3.3 V PCI/PCI-X, GTL+, and LVPECL.

Also note that when multiple I/O standards are used within a bank, the voltage tolerance will be limited to

the minimum tolerance of all I/O standards used in the bank.

Revision 18

2-15

Detailed Specifications

I/O Clusters

Each I/O cluster incorporates two I/O modules, four RX modules, two TX modules, and a buffer module.

In turn, each I/O module contains one Input Register (InReg), one Output Register (OutReg), and one

Enable Register (EnReg) (Figure 2-5).

I/O Cluster

P PAD

EnReg

Routed Input Track

OEP

Routed Input Track

DIN YOUT

OutReg

DIN YOUT

UOP

UIP

Routed Input Track

Output Track

Routed Input Track

Output Track

I/O

Slew Rate

Drive Strength

Programmable Delay

InReg

DCIN

VREF

N PAD

Routed Input Track

EnReg

DIN YOUT

Routed Input Track

OEN

UON

Routed Input Track

Output Track

OutReg

DIN YOUT

Routed Input Track

Output Track

I/O

Slew Rate

Drive Strength

Programmable Delay

InReg

UIN

DCIN

VREF

Figure 2-5 • I/O Cluster Interface

Using an I/O Register

To access the I/O registers, registers must be instantiated in the netlist and then connected to the I/Os.

Usage of each I/O register (register combining) is individually controlled and can be selected/deselected

using the PinEditor tool in the Designer software. I/O register combining can also be controlled at the

device level, affecting all I/Os. Please note, the I/O register option is deselected by default in any given

design.⁴

In addition, Designer software provides a global option to enable/disable the usage of registers in the

I/Os. This option is design-specific. The setting for each individual I/O overrides this global option.

Furthermore, the global set fuse option in the Designer software, when checked, causes all I/O registers

to output logic High at device power-up.

4. Please note that register combining for multi fanout nets is not supported.

2-16

Revision 18

Axcelerator Family FPGAs

Using the Weak Pull-Up and Pull-Down Circuits

Each Axcelerator I/O comes with a weak pull-up/down circuit (on the order of 10 kΩ). These are weak

transistors with the gates tied on, so the on resistance of the transistor emulates a resistor. The weak

pull-up and pull-down is active only when the device is powered up, and they must be biased to be on.

When the rails are coming up, they are not biased fully, so they do not behave as resistors until the

voltage is at sufficient levels to bias the transistors. The key is they really are transistors; they are not

traces of poly silicon, which is another way to do an on-chip resistor (those take much more room). I/O

macros are provided for combinations of pull up/down for LVTTL, LVCMOS (2.5 V, 1.8 V, and 1.5 V)

standards. These macros can be instantiated if a keeper circuit for any input buffer is required.

Customizing the I/O

•

A five-bit programmable input delay element is associated with each I/O. The value of this delay is

set on a bank-wide basis (Table 2-14). It is optional for each input buffer within the bank (i.e. the

user can enable or disable the delay element for the I/O). When the input buffer drives a register

within the I/O, the delay element is activated by default to ensure a zero hold-time. The default

setting for this property can be set in Designer. When the input buffer does not drive a register, the

delay element is deactivated to provide higher performance. Again, this can be overridden by

changing the default setting for this property in Designer.

•

The slew-rate value for the LVTTL output buffer can be programmed and can be set to either slow

or fast.

The drive strength value for LVTTL output buffers can be programmed as well. There are four

different drive strength values – 8 mA, 12 mA, 16 mA, or 24 mA – that can be specified in

Designer.⁵

Table 2-14 • Bank-Wide Delay Values

Bits Setting

Delay (ns)

Bits Setting

Delay (ns)

2.01

2.13

2.19

2.3

0.54

0.65

0.71

0.83

0.9

2.38

2.49

2.55

2.67

2.75

2.87

2.93

3.04

3.12

3.23

3.29

3.41

1.01

1.08

1.19

1.27

1.39

1.45

1.56

1.64

1.75

1.81

1.93

Note: Delay values are approximate and will vary with process, temperature, and voltage.

5. These values are minimum drive strengths.

Revision 18

2-17

Detailed Specifications

Using the Differential I/O Standards

Differential I/O macros should be instantiated in the netlist. The settings for these I/O standards cannot

be changed inside Designer. Note that there are no tristated or bidirectional I/O buffers for differential

standards.

Using the Voltage-Referenced I/O Standards

Using these I/O standards is similar to that of single-ended I/O standards. Their settings can be changed

in Designer.

Using DDR (Double Data Rate)

In Double Data Rate mode, new data is present on every transition of the clock signal. Clock and data

lines have identical bandwidth and signal integrity requirements, making it very efficient for implementing

very high-speed systems.

To implement a DDR, users need to:

1. Instantiate an input buffer (with the required I/O standard)

2. Instantiate the DDR_REG macro (Figure 2-6)

3. Connect the output from the Input buffer to the input of the DDR macro

PSET

CLK

CLR

Figure 2-6 • DDR Register

Macros for Specific I/O Standards

There are different macro types for any I/O standard or feature that determine the required VCCI and

VREF voltages for an I/O. The generic buffer macros require the LVTTL standard with slow slew rate and

24 mA-drive strength. LVTTL can support high slew rate but this should only be used for critical signals.

Most of the macro symbols represent variations of the six generic symbol types:

•

CLKBUF: Clock Buffer

HCLKBUF: Hardwired Clock Buffer

INBUF: Input Buffer

OUTBUF: Output Buffer

TRIBUF: Tristate Buffer

BIBUF: Bidirectional Buffer

Other macros include the following:

•

Differential I/O standard macros: The LVDS and LVPECL macros either have a pair of differential

inputs (e.g. INBUF_LVDS) or a pair of differential outputs (e.g. OUTBUF_LVPECL).

•

Pull-up and pull-down variations of the INBUF, BIBUF, and TRIBUF macros. These are available

only with TTL and LVCMOS thresholds. They can be used to model the behavior of the pull-up

and pull-down resistors available in the architecture. Whenever an input pin is left unconnected,

the output pin will either go high or low rather than unknown. This allows users to leave inputs

unconnected without having the negative effect on simulation of propagating unknowns.

•

DDR_REG macro. It can be connected to any I/O standard input buffers (i.e. INBUF) to

implement a double data rate register. Designer software will map it to the I/O module in the same

way it maps the other registers to the I/O module.

2-18

Revision 18

Axcelerator Family FPGAs

Table 2-15, Table 2-16, and Table 2-17 list all the available macro names differentiated by I/O standard,

type, slew rate, and drive strength.

Table 2-15 • Macros for Single-Ended I/O Standards

Standard

VCCI

Macro Names

LVTTL

3.3 V

CLKBUF, HCLKBUF INBUF, OUTBUF,

OUTBUF_S_8, OUTBUF_S_12, OUTBUF_S_16, OUTBUF_S_24,

OUTBUF_H_8, OUTBUF_H_12, OUTBUF_H_16, OUTBUF_H_24,

TRIBUF, TRIBUF_S_8, TRIBUF_S_12, TRIBUF_S_16, TRIBUF_S_24,

TRIBUF_H_8, TRIBUF_H_12, TRIBUF_H_16, TRIBUF_H_24,

BIBUF, BIBUF_S_8, BIBUF_S_12, BIBUF_S_16, BIBUF_S_24,

BIBUF_H_8, BIBUF_H_12, BIBUF_H_16, BIBUF_H_24

3.3 V PCI

3.3 V

2.5 V

1.8 V

1.5 V

CLKBUF_PCI, HCLKBUF_PCI, INBUF_PCI, OUTBUF_PCI,

TRIBUF_PCI, BIBUF_PCI

3.3 V PCI-X

LVCMOS25

LVCMOS18

CLKBUF_PCI-X, HCLKBUF_PCI-X, INBUF_PCI-X, OUTBUF_PCI-X,

TRIBUF_PCI-X, BIBUF_PCI-X

CLKBUF_LVCMOS25, HCLKBUF_LVCMOS25, INBUF_LVCMOS25,

OUTBUF_LVCMOS25, TRIBUF_LVCMOS25, BIBUF_LVCMOS25

CLKBUF_LVCMOS18, HCLKBUF_LVCMOS18, INBUF_LVCMOS18,

OUTBUF_LVCMOS18, TRIBUF_LVCMOS18, BIBUF_LVCMOS18

LVCMOS15

(JESD8-11)

CLKBUF_LVCMOS15, HCLKBUF_LVCMOS15, INBUF_LVCMOS15,

OUTBUF_LVCMOS15, TRIBUF_LVCMOS15, BIBUF_LVCMOS15

Table 2-16 • I/O Macros for Differential I/O Standards

Standard

LVPECL

LVDS

VCCI

Macro Names

3.3 V CLKBUF_LVPECL, HCLKBUF_LVPECL, INBUF_LVPECL, OUTBUF_LVPECL

2.5 V CLKBUF_LVDS, HCLKBUF_LVDS, INBUF_LVDS, OUTBUF_LVDS

Table 2-17 • I/O Macros for Voltage-Referenced I/O Standards

Standard

VCCI VREF

Macro Names

GTL+

3.3 V 1.0 V CLKBUF_GTP33, HCLKBUF_GTP33, INBUF_GTP33,

OUTBUF_GTP33, TRIBUF_GTP33, BIBUF_GTP33

GTL+

2.5 V 1.0 V CLKBUF_GTP25, HCLKBUF_GTP25, INBUF_GTP25,

OUTBUF_GTP25, TRIBUF_GTP25, BIBUF_GTP25

SSTL2 Class I 2.5 V 1.25 V CLKBUF_SSTL2_I, HCLKBUF_SSTL2_I, INBUF_SSTL2_I,

OUTBUF_SSTL2_I, TRIBUF_SSTL2_I, BIBUF_SSTL2_I

SSTL2 Class II 2.5 V 1.25 V CLKBUF_SSTL2_II, HCLKBUF_SSTL2_II, INBUF_SSTL2_II,

OUTBUF_SSTL2_II, TRIBUF_SSTL2_II, BIBUF_SSTL2_II

SSTL3 Class I 3.3 V 1.5 V CLKBUF_SSTL3_I, HCLKBUF_SSTL3_I, INBUF_SSTL3_I,

OUTBUF_SSTL3_I, TRIBUF_SSTL3_I, BIBUF_SSTL3_I

SSTL3 Class II 3.3 V 1.5 V CLKBUF_SSTL3_II, HCLKBUF_SSTL3_II, INBUF_SSTL3_II,

OUTBUF_SSTL3_II, TRIBUF_SSTL3_II, BIBUF_SSTL3_II

HSTL Class I

1.5 V 0.75 V CLKBUF_HSTL_I, HCLKBUF_HSTL_I, INBUF_HSTL_I,

OUTBUF_HSTL_I, TRIBUF_HSTL_I, BIBUF_HSTL_I

Revision 18

2-19

Detailed Specifications

User I/O Naming Conventions

Due to the complex and flexible nature of the Axcelerator family’s user I/Os, a naming scheme is used to

show the details of the I/O. The naming scheme explains to which bank an I/O belongs, as well as the

pairing and pin polarity for differential I/Os (Figure 2-7).

GND

VCCDA

Corner1

I/O BANK 0

I/O BANK 1

Corner2

VCCI7

GND

VCCI2

GND

VCCA

GND

VCCA

GND

VCCDA

GND

VCCDA

AX125

VCCI6

GND

VCCI3

GND

VCCA

GND

VCCA

GND

VCCDA

GND

VCCDA

Corner4

I/O BANK 5

I/O BANK 4

Corner3

Figure 2-7 • I/O Bank and Dedicated Pin Layout

IOxxXBxFx

Examples:

IO12PB1F1 is the positive pin of the thirteenth pair of the

first I/O bank (IOB NE). IO12PB1 combined

with IO12NB1 form a differential pair.

For those I/Os that can be employed

either as a user I/O or as a special

function, the following nomenclature

is used:

IOxxXBxFx/special_function_name

IOxxPB1Fx/xCLKx this pin can be configured as a clock

input or as a user I/O.

Pair number in the

bank, starting at 00,

clockwise from IOB NW

P - Positive Pin/ N - Negative Pin

Bank I/D 0 through 7,

clockwise from IOB NW

Fx refers to an

unimplemented feature

and can be ignored.

Figure 2-8 • General Naming Schemes

2-20

Revision 18

Axcelerator Family FPGAs

I/O Standard Electrical Specifications

Table 2-18 • Input Capacitance

Symbol

C_IN

Parameter

Input Capacitance

Input Capacitance on HCLK and RCLK Pin

Conditions

Min. Max. Units

VIN = 0, f = 1.0 MHz

C_INCLK

Table 2-19 • I/O Input Rise Time and Fall Time*

Input Buffer

LVTTL

Input Rise/Fall Time (min.)

Input Rise/Fall Time (max.)

No Requirement

50 ns

LVCMOS 2.5V

LVCMOS 1.8V

LVCMOS 1.5V

PCI

PCIX

GTL+

HSTL

SSTL2

HSTL3

LVDS

LVPECL

Note: *Input Rise/Fall time applies to all inputs, be it clock or data. Inputs have to ramp up/down linearly,

in a monotonic way. Glitches or a plateau may cause double clocking. They must be avoided. For

output rise/fall time, refer to the IBIS models for extraction.

INBUF

PAD

Input High

VTRIP

0 V

VCCA

50%

t_DP

(Rising)

t_DP

GND

(Falling)

Figure 2-9 • Input Buffer Delays

Revision 18

2-21

Detailed Specifications

OUT Pad

TRIBUF

To AC Test Loads (shown below)

VCCA

50%

VCCA

50%

VOH

VTRIP

50%

GND

10%

GND

90%

VCCI / VTT

VTRIP

VTT

Out

VTRIP

VOH

VTRIP

Out

VOL

t_PY

VTT

ENHZ

ENZH

Out

)

DLH

DHL

t_ENZL

t_ENLZ

GND / VTT

Figure 2-10 • Output Buffer Delays

2-22

Revision 18

Axcelerator Family FPGAs

I/O Module Timing Characteristics

Output Register

OutReg

Input Register

PRE/CLR

InReg

Output Enable Register

PRE/CLR

EnReg

PRE/CLR

CLK

(Routed or

Hardwired)

Figure 2-11 • Timing Model

t_SUD

t_HD

CLK

t_CPWHLt_CPWLH

t_ICLKQ

t_HASYNt_REASYN

t_CLR

t_WASYN

CLR

t_HASYN

t_REASYN

t_PRESET

t_WASYN

PRESET

t_HE

t_SUE

Figure 2-12 • Input Register Timing Characteristics

Revision 18

2-23

Detailed Specifications

t_SUD

t_HD

CLK

t_CPWHLt_CPWLH

t_OCLKQ

t_HASYNt_REASYN

t_CLR

t_WASYN

CLR

t_HASYN

t_REASYN

t_PRESET

t_WASYN

PRESET

t_HE

t_SUE

Figure 2-13 • Output Register Timing Characteristics

t_SUD

t_HD

CLK

t_CPWHLt_CPWLH

t_OCLKQ

t_HASYNt_REASYN

t_CLR

t_WASYN

CLR

t_HASYN

t_REASYN

t_PRESET

t_WASYN

PRESET

t_HE

t_SUE

Figure 2-14 • Output Enable Register Timing Characteristics

2-24

Revision 18

Axcelerator Family FPGAs

3.3 V LVTTL

Low-Voltage Transistor-Transistor Logic is a general purpose standard (EIA/JESD) for 3.3 V applications.

It uses an LVTTL input buffer and push-pull output buffer.

Table 2-20 • DC Input and Output Levels

VIL

VIH

VOL

Max., V

0.4

VOH

Min., V

2.4

IOL

IOH

–24

Min., V

Max., V

Min., V

Max., V

–0.3

0.8

2.0

3.6

AC Loadings

R to VCCI for t_plz/ t_pzl

R to GND for t_phz/ t_pzh

R=1k

Test Point

for tristate

Test Point

for t_pd

35 pF for t_pzh/ t_pzl

35 pF

t_phz/ t_plz

5 pF for

Figure 2-15 • AC Test Loads

Table 2-21 • AC Waveforms, Measuring Points, and Capacitive Load

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ) (V)

C_load(pF)

3.0

1.40

N/A

Note: * Measuring Point = VTRIP

Revision 18

2-25

Detailed Specifications

Timing Characteristics

Table 2-22 • 3.3 V LVTTL I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

LVTTL Output Drive Strength = 1 (8 mA) / Low Slew Rate

t_DP

Input Buffer

1.68

14.28

15.25

1.92

16.27

17.37

2.26

t_PY

Output Buffer

19.13 ns

20.42 ns

t_ENZL

Enable to Pad Delay through the Output Buffer—Z to

Low

t_ENZH

t_ENLZ

t_ENHZ

Enable to Pad Delay through the Output Buffer—Z to

High

14.26

1.56

1.95

16.24

1.57

1.96

19.09 ns

Enable to Pad Delay through the Output Buffer—Low

to Z

1.58

1.97

Enable to Pad Delay through the Output Buffer—High

to Z

t_IOCLKQ

t_IOCLKY

Sequential Clock-to-Q for the I/O Input Register

0.67

0.77

0.90

Clock-to-output Y for the I/O Output Register and the

I/O Enable Register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

039

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

2-26

Revision 18

Axcelerator Family FPGAs

Table 2-22 • 3.3 V LVTTL I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C (continued)

–2 Speed –1 Speed Std Speed

Min. Max. Min. Max. Min. Max. Units

Parameter

Description

LVTTL Output Drive Strength = 2 (12 mA) / Low Slew Rate

t_DP

Input Buffer

1.68

12.14

12.43

1.92

13.83

14.16

2.26

t_PY

Output Buffer

16.26 ns

16.65 ns

t_ENZL

Enable to Pad Delay through the Output Buffer—Z to

Low

t_ENZH

t_ENLZ

t_ENHZ

Enable to Pad Delay through the Output Buffer—Z to

High

12.17

1.73

2.22

13.86

1.74

2.23

16.30 ns

Enable to Pad Delay through the Output Buffer—Low

to Z

1.75

2.24

Enable to Pad Delay through the Output Buffer—High

to Z

t_IOCLKQ

t_IOCLKY

Sequential Clock-to-Q for the I/O Input Register

0.67

0.77

0.90

Clock-to-output Y for the I/O Output Register and the

I/O Enable Register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.38

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

Revision 18

2-27

Detailed Specifications

Table 2-22 • 3.3 V LVTTL I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C (continued)

–2 Speed –1 Speed Std Speed

Min. Max. Min. Max. Min. Max. Units

Parameter

Description

LVTTL Output Drive Strength =3 (16 mA) / Low Slew Rate

t_DP

Input Buffer

1.68

11.03

11.42

1.92

12.56

13.01

2.26

t_PY

Output Buffer

14.77 ns

15.29 ns

t_ENZL

Enable to Pad Delay through the Output Buffer—Z to

Low

t_ENZH

t_ENLZ

t_ENHZ

Enable to Pad Delay through the Output Buffer—Z to

High

11.04

1.86

2.50

12.58

1.88

2.51

14.79 ns

Enable to Pad Delay through the Output Buffer—Low

to Z

1.88

2.52

Enable to Pad Delay through the Output Buffer—High

to Z

t_IOCLKQ

t_IOCLKY

Sequential Clock-to-Q for the I/O Input Register

0.67

0.77

0.90

Clock-to-output Y for the I/O Output Register and the

I/O Enable Register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

2-28

Revision 18

Axcelerator Family FPGAs

Table 2-22 • 3.3 V LVTTL I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C (continued)

–2 Speed –1 Speed Std Speed

Min. Max. Min. Max. Min. Max. Units

Parameter

Description

LVTTL Output Drive Strength = 4 (24 mA) / Low Slew Rate

t_DP

Input Buffer

1.68

10.45

10.61

1.92

11.90

12.08

2.26

t_PY

Output Buffer

13.99 ns

14.21 ns

t_ENZL

Enable to Pad Delay through the Output Buffer—Z to

Low

t_ENZH

t_ENLZ

t_ENHZ

Enable to Pad Delay through the Output Buffer—Z to

High

10.47

1.92

2.57

11.93

1.94

2.58

14.02 ns

Enable to Pad Delay through the Output Buffer—Low

to Z

1.94

2.59

Enable to Pad Delay through the Output Buffer—High

to Z

t_IOCLKQ

t_IOCLKY

Sequential Clock-to-Q for the I/O Input Register

0.67

0.77

0.90

Clock-to-output Y for the I/O Output Register and the

I/O Enable Register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

Revision 18

2-29

Detailed Specifications

Table 2-22 • 3.3 V LVTTL I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C (continued)

–2 Speed –1 Speed Std Speed

Min. Max. Min. Max. Min. Max. Units

Parameter

Description

LVTTL Output Drive Strength = 1 (8 mA) / High Slew Rate

t_DP

Input Buffer

1.68

4.23

4.64

1.92

4.81

5.28

2.26

5.66

6.21

t_PY

Output Buffer

t_ENZL

Enable to Pad Delay through the Output Buffer—Z to

Low

t_ENZH

t_ENLZ

t_ENHZ

Enable to Pad Delay through the Output Buffer—Z to

High

4.23

1.89

2.01

4.81

1.91

2.02

5.66

1.91

2.03

Enable to Pad Delay through the Output Buffer—Low

to Z

Enable to Pad Delay through the Output Buffer—High

to Z

t_IOCLKQ

t_IOCLKY

Sequential Clock-to-Q for the I/O Input Register

0.67

0.77

0.90

Clock-to-output Y for the I/O Output Register and the

I/O Enable Register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

2-30

Revision 18

Axcelerator Family FPGAs

Table 2-22 • 3.3 V LVTTL I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C (continued)

–2 Speed –1 Speed Std Speed

Min. Max. Min. Max. Min. Max. Units

Parameter

Description

LVTTL Output Drive Strength = 2 (12 mA) / High Slew Rate

t_DP

Input Buffer

1.68

3.30

3.74

1.92

3.76

4.26

2.26

4.42

5.00

t_PY

Output Buffer

t_ENZL

Enable to Pad Delay through the Output Buffer—Z to

Low

t_ENZH

t_ENLZ

t_ENHZ

Enable to Pad Delay through the Output Buffer—Z to

High

3.06

1.89

2.29

3.49

1.91

2.30

4.10

1.91

2.31

Enable to Pad Delay through the Output Buffer—Low

to Z

Enable to Pad Delay through the Output Buffer—High

to Z

t_IOCLKQ

t_IOCLKY

Sequential Clock-to-Q for the I/O Input Register

0.67

0.77

0.90

Clock-to-output Y for the I/O Output Register and the

I/O Enable Register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

Revision 18

2-31

Detailed Specifications

Table 2-22 • 3.3 V LVTTL I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C (continued)

–2 Speed –1 Speed Std Speed

Min. Max. Min. Max. Min. Max. Units

Parameter

Description

LVTTL Output Drive Strength =3 (16 mA) / High Slew Rate

t_DP

Input Buffer

1.68

3.12

3.54

1.92

3.56

4.04

2.26

4.18

4.75

t_PY

Output Buffer

t_ENZL

Enable to Pad Delay through the Output Buffer—Z to

Low

t_ENZH

t_ENLZ

t_ENHZ

Enable to Pad Delay through the Output Buffer—Z to

High

2.78

1.91

2.58

3.17

1.93

2.59

3.72

1.93

2.60

Enable to Pad Delay through the Output Buffer—Low

to Z

Enable to Pad Delay through the Output Buffer—High

to Z

t_IOCLKQ

t_IOCLKY

Sequential Clock-to-Q for the I/O Input Register

0.67

0.77

0.90

Clock-to-output Y for the I/O Output Register and the

I/O Enable Register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

2-32

Revision 18

Axcelerator Family FPGAs

Table 2-22 • 3.3 V LVTTL I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C (continued)

–2 Speed –1 Speed Std Speed

Min. Max. Min. Max. Min. Max. Units

Parameter

Description

LVTTL Output Drive Strength = 4 (24mA) / High Slew Rate

t_DP

Input Buffer

1.68

2.99

2.49

1.92

3.41

2.51

2.26

4.01

2.51

t_PY

Output Buffer

t_ENZL

Enable to Pad Delay through the Output Buffer—Z to

Low

t_ENZH

t_ENLZ

t_ENHZ

Enable to Pad Delay through the Output Buffer—Z to

High

2.59

1.91

3.56

2.95

1.93

4.06

3.46

1.93

4.77

Enable to Pad Delay through the Output Buffer—Low

to Z

Enable to Pad Delay through the Output Buffer—High

to Z

t_IOCLKQ

t_IOCLKY

Sequential Clock-to-Q for the I/O Input Register

0.67

0.77

0.90

Clock-to-output Y for the I/O Output Register and the

I/O Enable Register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

Revision 18

2-33

Detailed Specifications

2.5 V LVCMOS

Low-Voltage Complementary Metal-Oxide Semiconductor for 2.5 V is an extension of the LVCMOS

standard (JESD8-5) used for general-purpose 2.5 V applications. It uses a 3.3 V tolerant CMOS input

buffer and a push-pull output buffer.

Table 2-23 • DC Input and Output Levels

VIL

VIH

VOL

Max., V

0.4

VOH

Min., V

2.0

IOL

IOH

–12

Min., V

Max., V

Min., V

Max., V

-0.3

0.7

1.7

3.6

AC Loadings

R to VCCI for t_plz/ t_pzl

R to GND for t_phz/ t_pzh

R=1k

Test Point

for tristate

Test Point

for t_pd

35 pF for t_pzh/ t_pzl

35 pF

t_phz/ t_plz

5 pF for

Figure 2-16 • AC Test Loads

Table 2-24 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ) (V)

C_load(pF)

2.5

1.25

N/A

Note: * Measuring Point = VTRIP

2-34

Revision 18

Axcelerator Family FPGAs

Timing Characteristics

Table 2-25 • 2.5V LVCMOS I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 2.3 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Min. Max. Units

Parameter

Description

Min.

Max.

Min.

Max.

LVCMOS25 I/O Module Timing

t_DP

Input Buffer

1.95

3.29

2.48

2.22

3.74

2.50

2.61

4.40

2.51

t_PY

Output Buffer

t_ENZL

Enable to Pad Delay through the Output

Buffer—Z to Low

t_ENZH

Enable to Pad Delay through the Output

Buffer—Z to High

2.48

5.74

6.60

0.67

2.50

6.54

7.51

0.77

2.51

7.69

8.83

0.90

t_ENLZ

Enable to Pad Delay through the Output

Buffer—Low to Z

t_ENHZ

Enable to Pad Delay through the Output

Buffer—High to Z

t_IOCLKQ

t_IOCLKY

Sequential Clock-to-Q for the I/O Input

Clock-to-output Y for the I/O Output Register

and the I/O Enable Register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

Revision 18

2-35

Detailed Specifications

1.8 V LVCMOS

Low-Voltage Complementary Metal-Oxide Semiconductor for 1.8 V is an extension of the LVCMOS

standard (JESD8-5) used for general-purpose 1.8 V applications. It uses a 3.3 V tolerant CMOS input

buffer and a push-pull output buffer.

Table 2-26 • DC Input and Output Levels

VIL

VIH

VOL

Max., V

0.2

VOH

Min., V

IOL

IOH

Min., V

Max., V

0.2 VCCI

Min., V

Max., V

–0.3

0.7 VCCI

3.6

VCCI – 0.2

8 mA

–8 mA

AC Loadings

R to VCCI for t_plz/ t_pzl

R to GND for t_phz/ t_pzh

R=1k

Test Point

for tristate

Test Point

for t_pd

35 pF for t_pzh/ t_pzl

35 pF

t_phz/ t_plz

5 pF for

Figure 2-17 • AC Test Loads

Table 2-27 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ) (V)

C_load(pF)

1.8

0.5 VCCI

N/A

Note: * Measuring Point = VTRIP

2-36

Revision 18

Axcelerator Family FPGAs

Timing Characteristics

Table 2-28 • 1.8V LVCMOS I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 1.7 V, TJ = 70°C

–2 Speed –1 Speed

Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max. Units

LVCMOS18 Output Module Timing

t_DP

Input Buffer

3.26

4.55

2.82

3.71

5.18

2.83

4.37

6.09

2.84

t_PY

Output Buffer

t_ENZL

Enable to Pad Delay through the Output

Buffer—Z to Low

t_ENZH

Enable to Pad Delay through the Output

Buffer—Z to High

3.43

6.01

6.73

0.67

3.45

6.85

7.67

0.77

3.46

8.05

9.01

0.90

t_ENLZ

Enable to Pad Delay through the Output

Buffer—Low to Z

t_ENHZ

Enable to Pad Delay through the Output

Buffer—High to Z

t_IOCLKQ

t_IOCLKY

Sequential Clock-to-Q for the I/O Input

Clock-to-output

for the I/O Output

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

Revision 18

2-37

Detailed Specifications

1.5 V LVCMOS (JESD8-11)

Low-Voltage Complementary Metal-Oxide Semiconductor for 1.5 V is an extension of the LVCMOS

standard (JESD8-5) used for general-purpose 1.5 V applications. It uses a 3.3 V tolerant CMOS input

buffer and a push-pull output buffer.

Table 2-29 • DC Input and Output Levels

VIL

VIH

VOL

Max., V

0.4

VOH

Min., V

IOL

IOH

Min., V

Max., V

0.35 VCCI

Min., V

Max., V

–0.3

0.65 VCCI

3.6

VCCI – 0.4

8 mA

–8 mA

AC Loadings

R to VCCI for t_plz/ t_pzl

R to GND for t_phz/ t_pzh

R=1k

Test Point

for tristate

Test Point

for t_pd

35 pF for t_pzh/ t_pzl

35 pF

t_phz/ t_plz

5 pF for

Table 2-30 • AC Test Loads

Table 2-31 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ) (V)

C_load(pF)

1.5

0.5V_CCI

N/A

Note: * Measuring Point = VTRIP

2-38

Revision 18

Axcelerator Family FPGAs

Timing Characteristics

Table 2-32 • 1.5V LVCMOS I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 1.4 V, TJ = 70°C

–2 Speed

–1 Speed

Std Speed

Parameter

Description

Min. Max.

Min.

Max. Min.

Max.

Units

LVCMOS15 (JESD8-11) I/O Module Timing

t_DP

Input Buffer

3.59

6.05

3.31

4.09

4.81

8.10

3.34

t_PY

Output Buffer

6.89

3.34

t_ENZL

Enable to Pad Delay through the Output

Buffer—Z to Low

t_ENZH

Enable to Pad Delay through the Output

Buffer—Z to High

4.56

6.37

6.94

0.67

4.58

7.25

7.90

0.77

4.59

8.52

9.29

0.90

t_ENLZ

Enable to Pad Delay through the Output

Buffer—Low to Z

t_ENHZ

Enable to Pad Delay through the Output

Buffer—High to Z

t_IOCLKQ

t_IOCLKY

Sequential Clock-to-Q for the I/O Input

Clock-to-output

Y for the I/O Output

t_SUD

Data Input Set-Up

0.23

0.26

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

0.00

t_HE

Enable Input Hold

0.00

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.15

0.00

0.27

0.17

0.00

0.31

0.00

0.23

t_PRESET

0.23

Revision 18

2-39

Detailed Specifications

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for both 33 MHz and 66 MHz PCI

bus applications. It uses an LVTTL input buffer and a push-pull output buffer. The input and output buffers

are 5 V tolerant with the aid of external components. Axcelerator 3.3 V PCI and 3.3 V PCI-X buffers are

compliant with the PCI Local Bus Specification Rev. 2.1.

The PCI Compliance Specification requires the clamp diodes to be able to withstand for 11 ns, –3.5 V in

undershoot, and 7.1 V in overshoot.

Table 2-33 • DC Input and Output Levels

VIL

Max., V

0.3 VCCI

0.35 VCCI 0.5 VCCI VCCI + 0.5

VIH

VOL

VOH

IOL

IOH

Min., V

–0.3

Min., V

Max., V

Min., V

PCI

0.5 VCCI VCCI + 0.5

(per PCI specification)

PCI-X

–0.5

AC Loadings

R to VCCI for t_pl

R to GND for t_ph

R = 25

R = 1k

Test Point

for tristate

R to VCCI for t_plz/ t_pzl

R to GND for t_phz/ t_pzh

Test point for data

10 pF

35 pF for t_pzl/ t_pzh

5 pF for t_phz/ t_plz

GND

Figure 2-18 • AC Test Loads

Table 2-34 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V) Input High (V) Measuring Point* (V)

(Per PCI Spec and PCI-X Spec)

VREF (typ) (V)

N/A

C_load(pF)

Note: * Measuring Point = VTRIP

2-40

Revision 18

Axcelerator Family FPGAs

Timing Characteristics

Table 2-35 • 3.3 V PCI I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed

Max. Min. Max.

Std Speed

Parameter

Description

Min.

Max. Units

3.3 V PCI Output Module Timing

t_DP

Input Buffer

1.57

1.91

1.61

1.79

2.18

1.62

2.10

2.56

1.63

t_PY

Output Buffer

t_ENZL

Enable to Pad Delay through the Output

Buffer—Z to Low

t_ENZH

Enable to Pad Delay through the Output

Buffer—Z to High

1.45

2.55

3.52

0.67

1.47

2.90

4.01

0.77

1.47

3.41

4.72

0.90

t_ENLZ

Enable to Pad Delay through the Output

Buffer—Low to Z

t_ENHZ

Enable to Pad Delay through the Output

Buffer—High to Z

t_IOCLKQ

t_IOCLKY

Sequential Clock-to-Q for the I/O Input

Clock-to-output Y for the I/O Output Register

and the I/O Enable Register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

Revision 18

2-41

Detailed Specifications

Table 2-36 • 3.3 V PCI-X I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Max. Min. Max. Units

Parameter

Description

Min.

Max.

Min.

3.3 V PCI-X Output Module Timing

t_DP

Input Buffer

1.57

2.10

1.61

1.79

2.40

1.62

2.10

2.82

1.63

t_PY

Output Buffer

t_ENZL

Enable to Pad Delay through the Output

Buffer—Z to Low

t_ENZH

Enable to Pad Delay through the Output

Buffer—Z to High

1.59

2.65

3.11

0.67

1.60

3.02

3.55

0.77

1.61

3.55

4.17

0.90

t_ENLZ

Enable to Pad Delay through the Output

Buffer—Low to Z

t_ENHZ

Enable to Pad Delay through the Output

Buffer—High to Z

t_IOCLKQ

t_IOCLKY

Sequential Clock-to-Q for the I/O Input

Clock-to-output

for the I/O Output

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

2-42

Revision 18

Axcelerator Family FPGAs

Voltage-Referenced I/O Standards

GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It requires a differential

amplifier input buffer and an Open Drain output buffer. The VCCI pin should be connected to 2.5 V or

3.3 V. Note that 2.5 V GTL+ is not supported across the full military temperature range.

Table 2-37 • DC Input and Output Levels

VIL

VIH

VOL

Max., V

0.6

VOH

Min., V

IOL

IOH

Min., V

Max., V

Min., V

Max., V

N/A

VREF – 0.1

VREF + 0.1

N/A

AC Loadings

VTT

Test Point

10 pF

Figure 2-19 • AC Test Loads

Table 2-38 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ) (V)

C_load(pF)

VREF – 0.2

VREF + 0.2

VREF

1.0

Note: * Measuring Point = VTRIP

Timing Characteristics

Table 2-39 • 2.5 V GTL+ I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 2.3 V, T_J= 70°C

–2 Speed –1 Speed

Max. Min. Max.

Std Speed

Parameter

Description

Min.

Max.

Units

2.5 V GTL+ I/O Module Timing

t_DP

Input Buffer

1.71

1.13

0.67

1.95

1.29

0.77

2.29

1.52

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the I/O output register and

the I/O enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

Revision 18

2-43

Detailed Specifications

Table 2-40 • 3.3 V GTL+ I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Min. Max.

Parameter

Description

Min.

Max.

Min.

Max.

Units

3.3 V GTL+I/O Module Timing

t_DP

Input Buffer

1.71

1.13

0.67

1.95

1.29

0.77

2.29

1.52

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the I/O output register and

the I/O enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

2-44

Revision 18

Axcelerator Family FPGAs

HSTL Class I

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). The

Axcelerator devices support Class I. This requires a differential amplifier input buffer and a push-pull

output buffer.

Table 2-41 • DC Input and Output Levels

VIL VIH

VOL

Max., V

0.4

VOH

IOL

IOH

-8

Min., V

Max., V

VREF – 0.1

Min., V

VREF + 0.1

Max., V

Min., V

-0.3

3.6

VCC – 0.4

AC Loadings

VTT

Test Point

20 pF

Figure 2-20 • AC Test Loads

Table 2-42 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ) (V)

C_load(pF)

VREF –0.5

VREF + 0.5

VREF

0.75

Note: * Measuring Point = VTRIP

Timing Characteristics

Table 2-43 • 1.5 V HSTL Class I I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 1.425 V, T_J= 70°C

–2 Speed –1 Speed Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

1.5 V HSTL Class I I/O Module Timing

t_DP

Input Buffer

1.80

4.90

0.67

2.05

5.58

0.77

2.41

6.56

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the I/O output register

and the I/O enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

Revision 18

2-45

Detailed Specifications

SSTL2

Stub Series Terminated Logic for 2.5 V is a general-purpose 2.5 V memory bus standard (JESD8-9). The

Axcelerator devices support both classes of this standard. This requires a differential amplifier input

buffer and a push-pull output buffer.

Class I

Table 2-44 • DC Input and Output Levels

VIL VIH

VOL

VOH

Min., V

IOL

7.6

IOH

Min., V

Max., V

VREF – 0.2

Min., V

VREF + 0.2

Max., V

–0.3

3.6

VREF – 0.57

VREF + 0.57

–7.6

AC Loadings

VTT

Test Point

30 pF

Figure 2-21 • AC Test Loads

Table 2-45 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ) (V)

C_load(pF)

VREF – 0.75

VREF + 0.75

VREF

1.25

Note: * Measuring Point = VTRIP

Timing Characteristics

Table 2-46 • 2.5 V SSTL2 Class I I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 2.3 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max. Units

2.5 V SSTL2 Class I I/O Module Timing

t_DP

Input Buffer

1.83

2.39

0.67

2.08

2.72

0.77

2.45

3.20

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the I/O output register

and the I/O enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

2-46

Revision 18

Axcelerator Family FPGAs

Class II

Table 2-47 • DC Input and Output Levels

VIL

VIH

VOL

VOH

Min,. V

IOL

IOH

Min., V

Max., V

Min., V

Max., V

-0.3

VREF – 0.2

VREF + 0.2

3.6

VREF – 0.8

VREF + 0.8

15.2

-15.2

AC Loadings

Test Point

30 pF

Figure 2-22 • AC Test Loads

Table 2-48 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ) (V)

_load(pF)

VREF – 0.75

VREF + 0.75

VREF

1.25

Note: * Measuring Point = V_trip

Timing Characteristics

Table 2-49 • 2.5 V SSTL2 Class II I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 2.3 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Min. Max. Units

Parameter

Description

Min.

Max.

Min.

Max.

2.5 V SSTL2 Class II I/O Module Timing

t_DP

Input Buffer

1.89

2.39

0.67

2.16

2.72

0.77

2.53

3.20

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the I/O output register and

the I/O enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

Revision 18

2-47

Detailed Specifications

SSTL3

Stub Series Terminated Logic for 3.3 V is a general-purpose 3.3 V memory bus standard (JESD8-8). The

Axcelerator devices support both classes of this standard. This requires a differential amplifier input

buffer and a push-pull output buffer.

Class I

Table 2-50 • DC Input and Output Levels

VIL VIH

VOL

VOH

Min., V

IOL

IOH

–8

Min., V

Max., V

VREF – 0.2

Min., V

Max., V

-0.3

VREF +0.2

3.6

VREF – 0.6

VREF + 0.6

AC Loadings

VTT

Test Point

30 pF

Figure 2-23 • AC Test Loads

Table 2-51 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ) (V)

C_load(pF)

VREF – 1.0

VREF + 1.0

VREF

1.50

Note: *Measuring Point = VTRIP

Timing Characteristics

Table 2-52 • 3.3 V SSTL3 Class I I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

3.3 V SSTL3 Class I I/O Module Timing

t_DP

Input Buffer

1.78

2.17

0.67

2.03

2.47

0.77

2.39

2.91

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the I/O output register and

the I/O enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

2-48

Revision 18

Axcelerator Family FPGAs

Class II

Table 2-53 • DC Input and Output Levels

VIL

VIH

VOL

VOH

Min., V

IOL

IOH

–16

Min., V

Max., V

Min., V

Max., V

-0.3

VREF – 0.2

VREF + 0.2

3.6

VREF – 0.8

VREF + 0.8

AC Loadings

Test Point

30 pF

Figure 2-24 • AC Test Loads

Table 2-54 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ) (V)

_load(pF)

VREF – 1.0

VREF + 1.0

VREF

1.50

Note: * Measuring Point = VTRIP

Timing Characteristics

Table 2-55 • 3.3 V SSTL3 Class II I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Min. Max.

Parameter

Description

Min.

Max.

Min.

Max.

Units

3.3 V SSTL3 Class II I/O Module Timing

t_DP

Input Buffer

1.85

2.17

0.67

2.10

2.47

0.77

2.47

2.91

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the I/O output register

and the I/O enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

Revision 18

2-49

Detailed Specifications

Differential Standards

Physical Implementation

Implementing differential I/O standards requires the configuration of a pair of external I/O pads, resulting

in a single internal signal. To facilitate construction of the differential pair, a single I/O Cluster contains the

resources for a pair of I/Os. Configuration of the I/O Cluster as a differential pair is handled by Designer

software when the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

support for bidirectional I/Os or tristates with these standards.

LVDS

Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires

that one data bit is carried through two signal lines, so two pins are needed. It also requires an external

resistor termination. The voltage swing between these two signal lines is approximately 350 mV.

FPGA

OUTBUF_LVDS

165 Ω

ZO = 50 Ω

INBUF_LVDS

140 Ω

100 Ω

–

Figure 2-25 • LVDS Board-Level Implementation

The LVDS circuit consists of a differential driver connected to a terminated receiver through a constant-

impedance transmission line. The receiver is a wide-common-mode-range differential amplifier. The

common-mode range is from 0.2 V to 2.2 V for a differential input with 400 mV swing.

To implement the driver for the LVDS circuit, drivers from two adjacent I/O cells are used to generate the

differential signals (note that the driver is not a current-mode driver). This driver provides a nominal

constant current of 3.5 mA. When this current flows through a 100 Ω termination resistor on the receiver

side, a voltage swing of 350 mV is developed across the resistor. The direction of the current flow is

controlled by the data fed to the driver.

An external-resistor network (three resistors) is needed to reduce the voltage swing to about 350 mV.

Therefore, four external resistors are required, three for the driver and one for the receiver.

Table 2-56 • DC Input and Output Levels

DC Parameter

VCCI¹

Description

Supply Voltage

Min.

2.375

1.25

0.9

Typ.

2.5

Max.

2.625

1.6

Units

VOH

Output High Voltage

1.425

1.075

350

VOL

Output Low Voltage

1.25

450

VODIFF

VOCM

Differential Output Voltage

Output Common Mode Voltage

Input Common Mode Voltage

250

1.125

0.2

1.25

1.375

2.2

VICM2

Notes:

1. ±5%

2. Differential input voltage = ±350 mV.

2-50

Revision 18

Axcelerator Family FPGAs

Table 2-57 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

1.2 – 0.125

Input High (V)

Measuring Point* (V)

1.2 + 0.125

1.2

Note: * Measuring Point = VTRIP

Timing Characteristics

Table 2-58 • LVDS I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 2.3 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max. Units

LVDS Output Module Timing

t_DP

Input Buffer

1.80

2.32

0.67

2.05

2.64

0.77

2.41

3.11

0.90

t_PY

Output Buffer

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the I/O output register and

the I/O enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

Revision 18

2-51

Detailed Specifications

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires

that one data bit is carried through two signal lines. Like LVDS, two pins are needed. It also requires

external resistor termination. The voltage swing between these two signal lines is approximately 850 mV.

FPGA

OUTBUF_LVPECL

100 Ω

ZO = 50 Ω

187Ω

ZO = 50 Ω

–

INBUF_LVPECL

100 Ω

Figure 2-26 • LVPECL Board-Level Implementation

The LVPECL circuit is similar to the LVDS scheme. It requires four external resistors, three for the driver

and one for the receiver. The values for the three driver resistors are different from that of LVDS since the

output voltage levels are different. Please note that the VOH levels are 200 mV below the standard

LVPECL levels.

Table 2-59 • DC Input and Output Levels

Min.

Typ.

Max.

DC Parameter

VCCI

Min.

Max.

Min.

Max.

Min.

Max.

Units

3.3

3.6

VOH

1.8

0.96

1.49

0.86

0.3

2.11

1.27

1.92

1.06

1.49

0.86

0.3

2.28

1.43

2.13

1.3

2.41

1.57

VOL

VIH

2.72

1.49

0.86

0.3

2.72

VIL

2.125

Differential Input

Voltage

Table 2-60 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

1.6 – 0.3

Input High (V)

Measuring Point* (V)

1.6 + 0.3

1.6

Note: * Measuring Point = VTRIP

2-52

Revision 18

Axcelerator Family FPGAs

Timing Characteristics

Table 2-61 • LVPECL I/O Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max. Units

LVPECL Output Module Timing

t_DP

Input Buffer

1.66

2.24

0.67

1.89

2.55

0.77

2.22

t_PY

Output Buffer

3.00

0.90

t_ICLKQ

t_OCLKQ

Clock-to-Q for the I/O input register

Clock-to-Q for the IO output register and

the I/O enable register

t_SUD

Data Input Set-Up

0.23

0.26

0.00

0.27

0.30

0.00

0.31

0.35

0.00

t_SUE

Enable Input Set-Up

t_HD

Data Input Hold

t_HE

Enable Input Hold

t_CPWHL

t_CPWLH

t_WASYN

t_REASYN

t_HASYN

t_CLR

Clock Pulse Width High to Low

Clock Pulse Width Low to High

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Asynchronous Clear-to-Q

Asynchronous Preset-to-Q

0.39

0.37

0.39

0.37

0.39

0.37

0.13

0.00

0.23

0.15

0.00

0.27

0.17

0.00

0.31

t_PRESET

Revision 18

2-53

Detailed Specifications

Module Specifications

C-Cell

Introduction

The C-cell is one of the two logic module types in the AX architecture. It is the combinatorial logic

resource in the Axcelerator device. The AX architecture implements a new combinatorial cell that is an

extension of the C-cell implemented in the SX-A family. The main enhancement of the new C-cell is the

addition of carry-chain logic.

The C-cell can be used in a carry-chain mode to construct arithmetic functions. If carry-chain logic is not

required, it can be disabled.

The C-cell features the following (Figure 2-27):

•

Eight-input MUX (data: D0-D3, select: A0, A1, B0, B1). User signals can be routed to any one of

these inputs. Any of the C-cell inputs (D0-D3, A0, A1, B0, B1) can be tied to one of the four routed

clocks (CLKE/F/G/H).

•

Inverter (DB input) can be used to drive a complement signal of any of the inputs to the C-cell.

A carry input and a carry output. The carry input signal of the C-cell is the carry output from the C-

cell directly to the north.

•

Carry connect for carry-chain logic with a signal propagation time of less than 0.1 ns.

A hardwired connection (direct connect) to the adjacent R-cell (Register Cell) for all C-cells on the

east side of a SuperCluster with a signal propagation time of less than 0.1 ns.

This layout of the C-cell (and the C-cell Cluster) enables the implementation of over 4,000 functions of up

to five bits. For example, two C-cells can be used together to implement a four-input XOR function in a

single cell delay.

The carry-chain configuration is handled automatically for the user with Microsemi's extensive macro

library (please see the Antifuse Macro Library Guide for a complete listing of available Axcelerator

macros).

FCI

CFN

D1 D3 B0 B1

0 1

D0 D2

Figure 2-27 • C-Cell

FCO

2-54

Revision 18

Axcelerator Family FPGAs

Timing Model and Waveforms

CCA

50%

A, B, D, FCI

GND

50%

CCA

50%

Y, FCO

GND

t_PD, t_PDC

CCA

Y, FCO

50%

t_PD, t_PDC

50%

GND

_PD, t_PDC

Figure 2-28 • C-Cell Timing Model and Waveforms

Timing Characteristics

Table 2-62 • C-Cell

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Max. Units

Parameter

Description

Min. Max. Min. Max. Min.

C-Cell Propagation Delays

t_PD

Any input to output Y

0.74

0.57

0.95

0.61

0.08

0.84

0.64

1.09

0.69

0.09

0.99

0.76

1.28

0.82

0.11

t_PDC

t_PDB

t_CCY

t_CC

Any input to carry chain output (FCO)

Any input through DB when one input is used

Input to carry chain (FCI) to Y

Input to carry chain (FCI) to carry chain output

(FCO)

Revision 18

2-55

Detailed Specifications

Carry-Chain Logic

The Axcelerator dedicated carry-chain logic offers a very compact solution for implementing arithmetic

functions without sacrificing performance.

To implement the carry-chain logic, two C-cells in a Cluster are connected together so the FCO (i.e. carry

out) for the two bits is generated in a carry look-ahead scheme to achieve minimum propagation delay

from the FCI (i.e. carry in) into the two-bit Cluster. The two-bit carry logic is shown in Figure 2-29.

The FCI of one C-cell pair is driven by the FCO of the C-cell pair immediately above it. Similarly, the FCO

of one C-cell pair, drives the FCI input of the C-cell pair immediately below it (Figure 1-4 on page 1-3 and

Figure 2-30 on page 2-57).

The carry-chain logic is selected via the CFN input. When carry logic is not required, this signal is

deasserted to save power. Again, this configuration is handled automatically for the user through

Microsemi's macro library.

The signal propagation delay between two C-cells in the carry-chain sequence is 0.1 ns.

DCOUT

Figure 2-29 • Axcelerator’s Two-Bit Carry Logic

2-56

Revision 18

Axcelerator Family FPGAs

FCI₁

R-cell1

DCIN

C-cell2

DCOUT

C-cell1

FCO₂

FCI₃

DCOUT

DCIN

FCO₄

FCI₅

n-2

Clusters

FCI_(2n-1)

R-celln

CDIN

C-cell

(2n-1)

C-cell2n

DCOUT

FCO_2n

Note: The carry-chain sequence can end on either C-cell.

Figure 2-30 • Carry-Chain Sequencing of C-Cells

Timing Characteristics

Refer to Table 2-62 on page 2-55 for more information on carry-chain timing.

Revision 18

2-57

Detailed Specifications

R-Cell

Introduction

The R-cell, the sequential logic resource of the Axcelerator devices, is the second logic module type in

the AX family architecture. It includes clock inputs for all eight global resources of the Axcelerator

architecture as well as global presets and clears (Figure 2-31).

The main features of the R-cell include the following:

•

Direct connection to the adjacent logic module through the hardwired connection DCIN. DCIN is

driven by the DCOUT of an adjacent C-cell via the Direct-Connect routing resource, providing a

connection with less than 0.1 ns of routing delay.

•

The R-cell can be used as a standalone flip-flop. It can be driven by any C-cell or I/O modules

through the regular routing structure (using DIN as a routable data input). This gives the option of

using the R-Cell as a 2:1 MUXed flip-flop as well.

•

Provision of data enable-input (S0).

Independent active-low asynchronous clear (CLR).

Independent active-low asynchronous preset (PSET). If both CLR and PSET are low, CLR has

higher priority.

•

Clock can be driven by any of the following (CKP selects clock polarity):

–

One of the four high performance hardwired fast clocks (HCLKs)

One of the four routed clocks (CLKs)

User signals

•

Global power-on clear (GCLR) and preset (GPSET), which drive each flip-flop on a chip-wide

basis.

–

When the Global Set Fuse option in the Designer software is unchecked (by default),

GCLR = 0 and GPSET = 1 at device power-up. When the option is checked, GCLR = 1 and

GPSET = 0. Both pins are pulled High when the device is in user mode. Refer to the

"Simulation Support for GCLR/GPSET in Axcelerator" section of the Antifuse Macro Library

Guide for information on simulation support for GCLR and GPSET.

•

S0, S1, PSET, and CLR can be driven by routed clocks CLKE/F/G/H or user signals.

DIN and S1 can be driven by user signals.

As with the C-cell, the configuration of the R-cell to perform various functions is handled automatically for

the user through Microsemi's extensive macro library (see the Antifuse Macro Library Guide for a

complete listing of available AX macros).

DIN(user signals)

DCIN

HCLKA/B/C/D

CLKE/F/G/H

Internal Logic

Figure 2-31 • R-Cell

2-58

Revision 18

Axcelerator Family FPGAs

Timing Models and Waveforms

t_SUD

t_HD

CLK

t_CPWHLt_CPWLH

t_RCO

t_HASYNt_REASYN

t_CLR

t_WASYN

CLR

t_HASYN

t_REASYN

t_PRESET

t_WASYN

PRESET

t_HE

t_SUE

Figure 2-32 • R-Cell Delays

Timing Characteristics

Table 2-63 • R-Cell

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

R-Cell Propagation Delays

t_RCO

Sequential Clock-to-Q

0.67

0.36

0.34

0.00

0.67

0.77

0.36

0.34

0.00

0.77

0.90

0.36

0.34

0.00

0.90

t_CLR

Asynchronous Clear-to-Q

t_PRESET

t_SUD

Asynchronous Preset-to-Q

Flip-Flop Data Input Set-Up

Flip-Flop Enable Input Set-Up

Flip-Flop Data Input Hold

t_SUE

t_HD

t_HE

Flip-Flop Enable Input Hold

Asynchronous Pulse Width

Asynchronous Recovery Time

Asynchronous Removal Time

Clock Pulse Width High to Low

Clock Pulse Width Low to High

t_WASYN

t_REASYN

t_HASYN

t_CPWHL

t_CPWLH

0.48

0.23

0.36

0.27

0.36

0.31

0.36

Revision 18

2-59

Detailed Specifications

Buffer Module

Introduction

An additional resource inside each SuperCluster is the Buffer (B) module (Figure 1-4 on page 1-3). When

a fanout constraint is applied to a design, the synthesis tool inserts buffers as needed. The buffer module

has been added to the AX architecture to avoid logic duplication resulting from the hard fanout

constraints. The router utilizes this logic resource to save area and reduce loading and delays on

medium-to-high-fanout nets.

Timing Models and Waveforms

OUT

Figure 2-33 • Buffer Module Timing Model

VCCA

50%

GND

VCCA

50%

OUT

GND

t_BFPD

Figure 2-34 • Buffer Module Waveform

Timing Characteristics

Table 2-64 • Buffer Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed Std Speed

Min. Max. Min. Max. Min. Max.

Parameter

Buffer Module Propagation Delays

t_BFPDAny input to output Y

Description

Units

0.12

0.14

0.16

2-60

Revision 18

Axcelerator Family FPGAs

Routing Specifications

Routing Resources

The routing structure found in Axcelerator devices enables any logic module to be connected to any

other logic module while retaining high performance. There are multiple paths and routing resources that

can be used to route one logic module to another, both within a SuperCluster and elsewhere on the chip.

There are four primary types of routing within the AX architecture: DirectConnect, CarryConnect,

FastConnect, and Vertical and Horizontal Routing.

DirectConnect

DirectConnects provide a high-speed connection between an R-cell and its adjacent C-cell (Figure 2-35).

This connection can be made from DCOUT of the C-cell to DCIN of the R-cell by configuring of the S1

line of the R-cell. This provides a connection that does not require an antifuse and has a delay of less

than 0.1 ns.

Figure 2-35 • DirectConnect and CarryConnect

CarryConnect

CarryConnects are used to build carry chains for arithmetic functions (Figure 2-35). The FCO output of

the right C-cell of a two-C-cell Cluster drives the FCI input of the left C-cell in the two-C-cell Cluster

immediately below it. This pattern continues down both sides of each SuperCluster column.

Similar to the DirectConnects, CarryConnects can be built without an antifuse connection. This

connection has a delay of less than 0.1 ns from the FCO of one two-C-cell cluster to the FCI of the two-

C-cell cluster immediately below it (see the "Carry-Chain Logic" section on page 2-56 for more

information).

FastConnect

For high-speed routing of logic signals, FastConnects can be used to build a short distance connection

using a single antifuse (Figure 2-36 on page 2-62). FastConnects provide a maximum delay of 0.3 ns.

The outputs of each logic module connect directly to the Output Tracks within a SuperCluster. Signals on

the Output Tracks can then be routed through a single antifuse connection to drive the inputs of logic

modules either within one SuperCluster or in the SuperCluster immediately below it.

Revision 18

2-61

Detailed Specifications

Vertical and Horizontal Routing

Vertical and Horizontal Tracks provide both local and long distance routing (Figure 2-37 on page 2-62).

These tracks are composed of both short-distance, segmented routing and across-chip routing tracks

(segmented at core tile boundaries). The short-distance, segmented routing resources can be

concatenated through antifuse connections to build longer routing tracks.

These short-distance routing tracks can be used within and between SuperClusters or between modules

of non-adjacent SuperClusters. They can be connected to the Output Tracks and to any logic module

input (R-cell, C-cell, Buffer, and TX module).

The across-chip horizontal and vertical routing provides long-distance routing resources. These

resources interface with the rest of the routing structures through the RX and TX modules (Figure 2-37).

The RX module is used to drive signals from the across-chip horizontal and vertical routing to the Output

Tracks within the SuperCluster. The TX module is used to drive vertical and horizontal across-chip

routing from either short-distance horizontal tracks or from Output Tracks. The TX module can also be

used to drive signals from vertical across-chip tracks to horizontal across-chip tracks and vice versa.

Figure 2-36 • FastConnect Routing

Figure 2-37 • Horizontal and Vertical Tracks

2-62

Revision 18

Axcelerator Family FPGAs

Timing Characteristics

Table 2-65 • AX125 Predicted Routing Delays

Worst-Case Commercial Conditions VCCA = 1.425 V, T_J= 70°C

–2 Speed

Typical

–1 Speed

Typical

Std Speed

Parameter

Description

Typical

Units

Predicted Routing Delays

t_DC

DirectConnect Routing Delay, FO1

0.11

0.35

0.38

0.43

0.48

0.55

0.64

0.79

0.88

1.49

2.32

0.12

0.39

0.40

0.43

0.48

0.55

0.62

0.72

0.89

0.99

1.69

2.63

0.15

0.46

0.47

0.51

0.57

0.64

0.73

0.85

1.05

1.17

1.99

3.10

t_FC

FastConnect Routing Delay, FO1

Routing delay for FO1

Routing delay for FO2

Routing delay for FO3

Routing delay for FO4

Routing delay for FO5

Routing delay for FO6

Routing delay for FO7

Routing delay for FO8

Routing delay for FO16

Routing delay for FO32

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RD6

t_RD7

t_RD8

t_RD16

t_RD32

Table 2-66 • AX250 Predicted Routing Delays

Worst-Case Commercial Conditions VCCA = 1.425 V, T_J= 70°C

–2 Speed

Typical

–1 Speed

Typical

Std Speed

Typical

Parameter

Description

Units

Predicted Routing Delays

t_DC

DirectConnect Routing Delay, FO1

0.11

0.35

0.39

0.41

0.48

0.56

0.60

0.84

0.90

1.00

2.17

3.55

0.12

0.39

0.45

0.46

0.55

0.63

0.68

0.96

1.02

1.13

2.46

4.03

0.15

0.46

0.53

0.54

0.64

0.75

0.80

1.13

1.20

1.33

2.89

4.74

t_FC

FastConnect Routing Delay, FO1

Routing delay for FO1

Routing delay for FO2

Routing delay for FO3

Routing delay for FO4

Routing delay for FO5

Routing delay for FO6

Routing delay for FO7

Routing delay for FO8

Routing delay for FO16

Routing delay for FO32

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RD6

t_RD7

t_RD8

t_RD16

t_RD32

Revision 18

2-63

Detailed Specifications

Table 2-67 • AX500 Predicted Routing Delays

Worst-Case Commercial Conditions VCCA = 1.425 V, T_J= 70°C

–2 Speed

Typical

–1 Speed

Typical

Std Speed

Typical

Parameter

Description

Units

Predicted Routing Delays

t_DC

DirectConnect Routing Delay, FO1

0.11

0.35

0.39

0.41

0.48

0.56

0.60

0.84

0.90

1.00

2.17

3.55

0.12

0.39

0.45

0.46

0.55

0.63

0.68

0.96

1.02

1.13

2.46

4.03

0.15

0.46

0.53

0.54

0.64

0.75

0.80

1.13

1.20

1.33

2.89

4.74

t_FC

FastConnect Routing Delay, FO1

Routing delay for FO1

Routing delay for FO2

Routing delay for FO3

Routing delay for FO4

Routing delay for FO5

Routing delay for FO6

Routing delay for FO7

Routing delay for FO8

Routing delay for FO16

Routing delay for FO32

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RD6

t_RD7

t_RD8

t_RD16

t_RD32

Table 2-68 • AX1000 Predicted Routing Delays

Worst-Case Commercial Conditions VCCA = 1.425 V, T_J= 70°C

–2 Speed

Typical

–1 Speed

Std Speed

Typical

Parameter

Description

Typical

Units

Predicted Routing Delays

t_DC

DirectConnect Routing Delay, FO1

0.12

0.35

0.45

0.53

0.56

0.63

0.73

0.99

1.02

1.48

2.57

4.24

0.13

0.39

0.51

0.60

0.63

0.71

0.82

1.13

1.15

1.68

2.91

4.81

0.15

0.46

0.60

0.71

0.74

0.84

0.97

1.32

1.36

1.97

3.42

5.65

t_FC

FastConnect Routing Delay, FO1

Routing delay for FO1

Routing delay for FO2

Routing delay for FO3

Routing delay for FO4

Routing delay for FO5

Routing delay for FO6

Routing delay for FO7

Routing delay for FO8

Routing delay for FO16

Routing delay for FO32

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RD6

t_RD7

t_RD8

t_RD16

t_RD32

2-64

Revision 18

Axcelerator Family FPGAs

Table 2-69 • AX2000 Predicted Routing Delays

Worst-Case Commercial Conditions VCCA = 1.425 V, T_J= 70°C

–2 Speed

Typical

–1 Speed

Typical

Std Speed

Parameter

Description

Typical

Units

Predicted Routing Delays

t_DC

DirectConnect Routing Delay, FO1

0.12

0.35

0.50

0.59

0.70

0.76

0.98

1.48

1.65

1.73

2.58

4.24

0.13

0.39

0.56

0.67

0.80

0.87

1.11

1.68

1.87

1.96

2.92

4.81

0.15

0.46

0.66

0.79

0.94

1.02

1.31

1.97

2.20

2.31

3.44

5.65

t_FC

FastConnect Routing Delay, FO1

Routing delay for FO1

Routing delay for FO2

Routing delay for FO3

Routing delay for FO4

Routing delay for FO5

Routing delay for FO6

Routing delay for FO7

Routing delay for FO8

Routing delay for FO16

Routing delay for FO32

t_RD1

t_RD2

t_RD3

t_RD4

t_RD5

t_RD6

t_RD7

t_RD8

t_RD16

t_RD32

Revision 18

2-65

Detailed Specifications

Global Resources

One of the most important aspects of any FPGA architecture is its global resources or clocks. The

Axcelerator family provides the user with flexible and easy-to-use global resources, without the

limitations normally found in other FPGA architectures.

The AX architecture contains two types of global resources, the HCLK (hardwired clock) and CLK (routed

clock). Every Axcelerator device is provided with four HCLKs and four CLKs for a total of eight clocks,

regardless of device density.

Hardwired Clocks

The hardwired (HCLK) is a low-skew network that can directly drive the clock inputs of all sequential

modules (R-cells, I/O registers, and embedded RAM/FIFOs) in the device with no antifuse in the path. All

four HCLKs are available everywhere on the chip.

Timing Characteristics

Table 2-70 • AX125 Dedicated (Hardwired) Array Clock Networks

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed

–1 Speed

Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Dedicated (Hardwired) Array Clock Networks

t_HCKL

t_HCKH

t_HPWH

t_HPWL

t_HCKSW

t_HP

Input Low to High

3.02

3.03

3.44

3.46

4.05

4.06

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.58

0.52

0.65

0.59

0.77

0.69

0.06

870

0.07

763

0.08

649

Minimum Period

1.15

1.31

1.54

t_HMAX

Maximum Frequency

MHz

Table 2-71 • AX250 Dedicated (Hardwired) Array Clock Networks

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Dedicated (Hardwired) Array Clock Networks

t_HCKL

t_HCKH

t_HPWH

t_HPWL

t_HCKSW

t_HP

Input Low to High

2.57

2.61

2.93

2.97

3.45

3.50

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.58

0.52

0.65

0.59

0.77

0.69

0.06

870

0.07

763

0.08

649

Minimum Period

1.15

1.31

1.54

t_HMAX

Maximum Frequency

MHz

2-66

Revision 18

Axcelerator Family FPGAs

Table 2-72 • AX500 Dedicated (Hardwired) Array Clock Networks

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Dedicated (Hardwired) Array Clock Networks

t_HCKL

t_HCKH

t_HPWH

t_HPWL

t_HCKSW

t_HP

Input Low to High

2.35

2.44

2.68

2.79

3.15

3.27

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.58

0.52

0.65

0.59

0.77

0.69

0.06

870

0.07

763

0.08

649

Minimum Period

1.15

1.31

1.54

t_HMAX

Maximum Frequency

MHz

Table 2-73 • AX1000 Dedicated (Hardwired) Array Clock Networks

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Dedicated (Hardwired) Array Clock Networks

t_HCKL

t_HCKH

t_HPWH

t_HPWL

t_HCKSW

t_HP

Input Low to High

3.02

3.03

3.44

3.46

4.05

4.06

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.58

0.52

0.65

0.59

0.77

0.69

0.06

870

0.07

763

0.08

649

Minimum Period

1.15

1.31

1.54

t_HMAX

Maximum Frequency

MHz

Table 2-74 • AX2000 Dedicated (Hardwired) Array Clock Networks

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Dedicated (Hardwired) Array Clock Networks

t_HCKL

t_HCKH

t_HPWH

t_HPWL

t_HCKSW

t_HP

Input Low to High

3.02

3.03

3.44

3.46

4.05

4.06

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.58

0.52

0.65

0.59

0.77

0.69

0.06

870

0.07

763

0.08

649

Minimum Period

1.15

1.31

1.54

t_HMAX

Maximum Frequency

MHz

Revision 18

2-67

Detailed Specifications

Routed Clocks

The routed clock (CLK) is a low-skew network that can drive the clock inputs of all sequential modules in

the device (logically equivalent to the HCLK), but has the added flexibility in that it can drive the S0

(Enable), S1, PSET, and CLR input of a register (R-cells and I/O registers) as well as any of the inputs of

any C-cell in the device. This allows CLKs to be used not only as clocks, but also for other global signals

or high fanout nets. All four CLKs are available everywhere on the chip.

Timing Characteristics

Table 2-75 • AX125 Routed Array Clock Networks

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Routed Array Clock Networks

t_RCKL

t_RCKH

t_RPWH

t_RPWL

t_RCKSW

t_RP

Input Low to High

3.08

3.13

3.50

3.56

4.12

4.19

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.57

0.52

0.64

0.59

0.75

0.69

0.35

870

0.39

763

0.46

649

Minimum Period

1.15

1.31

1.54

t_RMAX

Maximum Frequency

MHz

Table 2-76 • AX250 Routed Array Clock Networks

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Routed Array Clock Networks

t_RCKL

t_RCKH

t_RPWH

t_RPWL

t_RCKSW

t_RP

Input Low to High

2.52

2.59

2.87

2.95

3.37

3.47

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.57

0.52

0.64

0.59

0.75

0.69

0.35

870

0.39

763

0.46

649

Minimum Period

1.15

1.31

1.54

t_RMAX

Maximum Frequency

MHz

2-68

Revision 18

Axcelerator Family FPGAs

Table 2-77 • AX500 Routed Array Clock Networks

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Routed Array Clock Networks

t_RCKL

t_RCKH

t_RPWH

t_RPWL

t_RCKSW

t_RP

Input Low to High

2.31

2.44

2.63

2.78

3.09

3.27

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.57

0.52

0.64

0.59

0.75

0.69

0.35

870

0.39

763

0.46

649

Minimum Period

1.15

1.31

1.54

t_RMAX

Maximum Frequency

MHz

Table 2-78 • AX1000 Routed Array Clock Networks

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Routed Array Clock Networks

t_RCKL

t_RCKH

t_RPWH

t_RPWL

t_RCKSW

t_RP

Input Low to High

3.08

3.13

3.50

3.56

4.12

4.19

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.57

0.52

0.64

0.59

0.75

0.69

0.35

870

0.39

763

0.46

649

Minimum Period

1.15

1.31

1.54

t_RMAX

Maximum Frequency

MHz

Table 2-79 • AX2000 Routed Array Clock Networks

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Routed Array Clock Networks

t_RCKL

t_RCKH

t_RPWH

t_RPWL

t_RCKSW

t_RP

Input Low to High

3.08

3.13

3.50

3.56

4.12

4.19

Input High to Low

Minimum Pulse Width High

Minimum Pulse Width Low

Maximum Skew

0.57

0.52

0.64

0.59

0.75

0.69

0.35

870

0.39

763

0.46

649

Minimum Period

1.15

1.31

1.54

t_RMAX

Maximum Frequency

MHz

Revision 18

2-69

Detailed Specifications

Global Resource Distribution

At the root of each global resource is a PLL. There are two groups of four PLLs for every device. One

group, located at the center of the north edge (in the I/O ring) of the chip, sources the four HCLKs. The

second group, located at the center of the south edge (again in the I/O ring), sources the four CLKs

(Figure 2-38).

Regardless of the type of global resource, HCLK or CLK, each of the eight resources reach the

ClockTileDist (CTD) Cluster located at the center of every core tile with zero skew. From the

ClockTileDist Cluster, all four HCLKs and four CLKs are distributed through the core tile (Figure 2-39).

PLL

P N

PLL Cluster

HCLKA HCLKB HCLKC HCLKD

CLKE

CLKF CLKG

CLKH

PLL Cluster

PLL

P N

PLL

P N

PLL

Figure 2-38 • PLL Group

HCLK

CLK

PLL Group

ClockTileDist Cluster

PLL Group

Figure 2-39 • Example of HCLK and CLK Distributions on the AX2000

2-70

Revision 18

Axcelerator Family FPGAs

The ClockTileDist Cluster contains an HCLKMux (HM) module for each of the four HCLK trees and a

CLKMux (CM) module for each of the CLK trees. The HCLK branches then propagate horizontally

through the middle of the core tile to HCLKColDist (HD) modules in every SuperCluster column. The CLK

branches propagate vertically through the center of the core tile to CLKRowDist (RD) modules in every

SuperCluster row. Together, the HCLK and CLK branches provide for a low-skew global fanout within the

core tile (Figure 2-40 and Figure 2-41).

Figure 2-40 • CTD, CD, and HD Module Layout

Figure 2-41 • HCLK and CLK Distribution within a Core Tile

Revision 18

2-71

Detailed Specifications

The HM and CM modules can select between:

•

The HCLK or CLK source respectively

A local signal routed on generic routing resources

This allows each core tile to have eight clocks independent of the other core tiles in the device.

Both HCLK and CLK are segmentable, meaning that individual branches of the global resource can be

used independently.

Like the HM and CM modules, the HD and RD modules can select between:

•

The HCLK or CLK source from the HM or CM module respectively

A local signal routed on generic routing resources

The AX architecture is capable of supporting a large number of local clocks—24 segments per HCLK

driving north-south and 28 segments per CLK driving east-west per core tile.

Microsemi's Designer software’s place-and-route takes advantage of the segmented clock structure

found in Axcelerator devices by turning off any unused clock segments. This results in not only better

performance but also lower power consumption.

Global Resource Access Macros

Global resources can be driven by one of three sources: external pad(s), an internal net, or the output of

a PLL. These connections can be made by using one of three types of macros: CLKBUF, CLKINT, and

PLLCLK.

CLKBUF and HCLKBUF

CLKBUF (HCLKBUF) is used to drive a CLK (HCLK) from external pads. These macros can be used

either generically or with the specific I/O standard desired (e.g. CLKBUF_LVCMOS25, HCLKBUF_LVDS,

etc.) (Figure 2-42).

Clock

Network

CLKBUF

HCLKBUF

Figure 2-42 • CLKBUF and HCLKBUF

Package pins CLKEP and CLKEN are associated with CLKE; package pins HCLKAP and HCLKAN are

associated with HCLKA, etc.

Note that when CLKBUF (HCLKBUF) is used with a single-ended I/O standard, it must be tied to the

P-pad of the CLK (HCLK) package pin. In this case, the CLK (HCLK) N-pad can be used for user signals.

CLKINT and HCLKINT

CLKINT (HCLKINT) is used to access the CLK (HCLK) resource internally from the user signals

(Figure 2-43).

Clock

Network

Logic

CLKINT

HCLKINT

Figure 2-43 • CLKINT and HCLKINT

2-72

Revision 18

Axcelerator Family FPGAs

PLLRCLK and PLLHCLK

PLLRCLK (PLLHCLK) is used to drive global resource CLK (HCLK) from a PLL (Figure 2-44).

Clock

Network

RefCLK

PLL

CLK1

CLK2

PLLRCLK

PLLHCLK

Figure 2-44 • PLLRCLK and PLLHCLK

Using Global Resources with PLLs

Each global resource has an associated PLL at its root. For example, PLLA can drive HCLKA, PLLE can

drive CLKE, etc. (Figure 2-45).

HCLKAP

HCLKA

Network

RefCLK

CLK1

CLK2

PLLA

HCLKAN

PLLHCLK

Figure 2-45 • Example of HCLKA Driven from a PLL with External Clock Source

In addition, each clock pin of the package can be used to drive either its associated global resource or

PLL. For example, package pins CLKEP and CLKEN can drive either the RefCLK input of PLLE or

CLKE.

There are two macros required when interfacing the embedded PLLs with the global resources: PLLINT

and PLLOUT.

PLLINT

This macro is used to drive the RefCLK input of the PLL internally from user signals.

PLLOUT

This macro is used to connect either the CLK1 or CLK2 output of a PLL to the regular routing network

(Figure 2-46).

PLLINT

PLLHCLK

HCLKA

Network

CLK1

CLK2

RefCLK

PLLA

Logic

PLLOUT

Figure 2-46 • Example of PLLINT and PLLOUT Usage

Revision 18

2-73

Detailed Specifications

Implementation Example:

Figure 2-47 shows a complex clock distribution example. The reference clock (RefCLK) of PLLE is being

sourced from non-clock signal pins (INBUF to PLLINT). The CLK1 output of PLLE is being fed to the

RefCLK input of PLLF. The CLK2 output of PLLE is driving logic (via PLLOUT). In turn, this logic is driving

the global resource CLKE. PLLF is driving both CLKF and CLKG global resources.

Non-Clock

Pins

INBUF

PLLINT

PLLRCLK

RefCLK

CLK1

CLK2

PLLE

CLKINT

PLLOUT

Logic

CLKE

PLLRCLK

CLKF

RefCLK

PLLF

CLK1

CLK2

CLKG

PLLRCLK

Figure 2-47 • Complex Clock Distribution Example

2-74

Revision 18

Axcelerator Family FPGAs

Axcelerator Clock Management System

Introduction

Each member of the Axcelerator family⁶contains eight phase-locked loop (PLL) blocks which perform

the following functions:

•

Programmable Delay (32 steps of 250 ps)

Clock Skew Minimization

Clock Frequency Synthesis

Each PLL has the following key features:

•

Input Frequency Range – 14 to 200 MHz

Output Frequency Range – 20 MHz to 1 GHz

Output Duty Cycle Range – 45% to 55%

Maximum Long-Term Jitter – 1% or 100ps (whichever is greater)

Maximum Short-Term Jitter – 50ps + 1% of Output Frequency

Maximum Acquisition Time (lock) – 20µs

Physical Implementation

The eight PLL blocks are arranged in two groups of four. One group is located in the center of the

northern edge of the chip, while the second group is centered on the southern edge. The northern group

is associated with the four HCLK networks (e.g. PLLA can drive HCLKA), while the southern group is

associated with the four CLK networks (e.g. PLLE can drive CLKE).

Each PLL cell is connected to two I/O pads and a PLL Cluster that interfaces with the FPGA core.

Figure 2-48 illustrates a PLL block. The VCCPLL pin should be connected to a 1.5V power supply

through a 250 Ω resistor. Furthermore, 0.1 μF and 10 μF decoupling capacitors should be connected

across the VCCPLL and VCOMPPLL pins.

DIVJ

Lock

PowerDown

RefCLK

Delay Line

/i Delay

Match

CLK1

CLK2

PLL

/j Delay

Match

FBMuxSel

DelayLine

DIVJ

LowFreq

Osc

Figure 2-48 • PLL Block Diagram

Note: The VCOMPPLL pin should never be grounded (Figure 2-2 on page 2-9)!

The I/O pads associated with the PLL can also be configured for regular I/O functions except when it is

used as a clock buffer. The I/O pads can be configured in all the modes available to the regular I/O pads

in the same I/O bank. In particular, the [H]CLKxP pad can be configured as a differential pair,

6. AX2000-CQ256 does not support operation of the phase-locked loops. This is in order to support full pin compatibility with

RTAX2000S/SL-CQ256.

Revision 18

2-75

Detailed Specifications

single-ended, or voltage-referenced standard. The [H]CLKxN pad can only be used as a differential pair

with [H]CLKxP.

The block marked “/i Delay Match” is a fixed delay equal to that of the i divider. The “/j Delay Match” block

has the same function as its j divider counterpart.

Functional Description

Figure 2-48 on page 2-75 illustrates a block diagram of the PLL. The PLL contains two dividers, i and j,

that allow frequency scaling of the clock signal:

•

The i divider in the feedback path allows multiplication of the input clock by integer factors ranging

from 1 to 64, and the resultant frequency is available at the output of the PLL block.

The j divider divides the PLL output by integer factors ranging from 1 to 64, and the divided clock

is available at CLK1.

The two dividers together can implement any combination of multiplication and division up to a

maximum frequency of 1 GHz on CLK1. Both the CLK1 and CLK2 outputs have a fixed 50/50

duty cycle.

•

The output frequencies of the two clocks are given by the following formulas (f_REFis the reference

clock frequency):

f_CLK1= f_REF* (DividerI) / (DividerJ)

f_CLK2= f_REF* (DividerI)

EQ 4

EQ 5

•

CLK2 provides the PLL output directly—without division

The input and output frequency ranges are selected by LowFreq and Osc(2:0), respectively. These

functions and their possible values are detailed in Table 2-80 on page 2-77.

The delay lines shown in Figure 2-48 on page 2-75 are programmable. The feedback clock path can be

delayed (using the five DelayLine bits) relative to the reference clock (or vice versa) by up to 3.75 ns in

increments of 250 ps. Table 2-80 on page 2-77 describes the usage of these bits. The delay increments

are independent of frequency, so this results in phase changes that vary with frequency. The delay value

is highly dependent on V_CCand the speed grade.

Figure 2-49 is a logical diagram of the various control signals to the PLL and shows how the PLL

interfaces with the global and routing networks of the FPGA. Note that not all signals are user-

accessible. These non-user-accessible signals are used by the place-and-route tool to control the

configuration of the PLL. The user gains access to these control signals either based upon the

connections built in the user's design or through the special macros (Table 2-84 on page 2-81) inserted

into the design. For example, connecting the macro PLLOUT to CLK2 will control the OUTSEL signal.

ROOTSEL

REFSEL

CLKINT

CLK1 (PLLn-1)

[H]CLKINT

RefCLK

CLK1

CLK2

[H]CLK

[H]CLKxP

PLLSEL

PLL

I/O

Core net

CLK net

CLK Out

(Routed net out pin)

FBINT

[H]CLKxN

OUTSEL

FBMuxSEL

To PLLn+1

Note: Not all signals are available to the user.

Figure 2-49 • PLL Logical Interface

2-76

Revision 18

Axcelerator Family FPGAs

Table 2-80 • PLL Interface Signals

User

Type Accessible

Allowable

Values

Signal Name

RefCLK

Function

Input

Yes

Reference Clock for the PLL

Feedback port for the PLL

PLL power down control

PLL powered down

PLL active

PowerDown

DIVI[5:0]

DIVJ[5:0]

Input

Yes

1 to 64, in

unsigned binary

notation offset by

-1

Sets value for feedback divider (multiplier)

Sets value for CLK1 divider

LowFreq

Osc[2:0]

Input

Yes

Input frequency range selector

50–200 MHz

14–50 MHz

Output frequency range selector

400–1000 MHZ

XX0

001

200–400 MHZ

011

100–200 MHZ

101

50–100 MHZ

111

20–50 MHZ

DelayLine[4:0] Input

Yes

–15 to +15

Clock Delay (positive/negative) in increments

(increments), in of 250 ps, with maximum value of ± 3.75 ns

signed-and-

magnitudebinary

representation

FBMuxSel

REFSEL

OUTSEL

PLLSEL

Input

Selects the source for the feedback input

Selects the source for the reference clock

Selects the source for the routed net output

ROOTSEL & PLLSEL are used to select the

source of the global clock network

ROOTSEL

Lock

Input

Yes

Output

High value indicates PLL has locked

PLL clock output

CLK1

CLK2

PLL clock output

Note: If the input RefClk is taken outside its operating range, the outputs Lock, CLK1 and CLK2 are

indeterminate.

Revision 18

2-77

Detailed Specifications

PLL Configurations

The following rules apply to the different PLL inputs and outputs:

Reference Clock

The RefCLK can be driven by (Figure 2-50):

1. Global routed clocks (CLKE/F/G/H) or user-created clock network

2. CLK1 output of an adjacent PLL

3. [H]CLKxP (single-ended or voltage-referenced)

4. [H]CLKxP/[H]CLKxN pair (differential modes like LVPECL or LVDS)

Feedback Clock

The feedback clock can be driven by (Figure 2-51 on page 2-78):

1. Global routed clocks (CLKE/F/G/H) or user-created clock network

2. External [H]CLKxP/N I/O pad(s) from the adjacent PLL cell

3. An internal signal from the PLL block

Regular, LVPECL, or LVDS IOPAD

Non-clock

INBUF

Pins

RefCLK

PLL

Any macro from the core, except HCLK nets

RefCLK

PLL

Logic

For cascading

CLK1 RefCLK

PLL

Figure 2-50 • Reference Clock Connections

PLLOUT/PLLRCLK

PLL

Any macro except HCLK macros

PLL

Figure 2-51 • Feedback Clock Connections

2-78

Revision 18

Axcelerator Family FPGAs

CLK1 and CLK2

Both PLL outputs, CLK1 and CLK2, can be used to drive a global resource, an adjacent PLL RefCLK

input, or a net in the FPGA core. Not all drive combinations are possible (Table 2-81).

Table 2-81 • PLL General Connections Rules

CLK1

CLK2

HCLK

CLK

HCLK

Routed net output

HCLK

Routed net output

HCLK

NONE

CLK

HCLK

NONE

CLK

Note: The PLL outputs remain Low when REFCLK is constant (either Low or High).

Restrictions on CLK1 and CLK2

•

When both are driving global resources, they must be driving the same type of global resource

(i.e. either HCLK or CLK).

•

Only one can drive a routed net at any given time.

Table 2-82 and Table 2-83 specify all the possible CLK1 and CLK2 connections for the north and south

PLLs. HCLK1 and HCLK2 are used to denote the different HCLK networks when two are being driven at

the same time by a single PLL (Note that HCLK1 is the primary clock resource associated with the PLL,

and HCLK2 is the clock resource associated with the adjacent PLL). Likewise, CLK1 and CLK2 are used

to denote the different CLK networks when two are being driven at the same time by a single PLL

(Figure 2-48 on page 2-75).

Table 2-82 • North PLL Connections

CLK1

CLK2

HCLK1

Routed net

Unused

HCLK1

HCLK2

HCLK1

HCLK2

Routed net

HCLK2

Both HCLK1 and routed net

Unused

HCLK2

Unused

HCLK1

Unused

Routed net

Both HCLK1 and routed net

Unused

Routed net

HCLK1

Routed net

Unused

Both HCLK1 and HCLK2

Both HCLK1 and routed net

Both HCLK2 and routed net

HCLK1, HCLK2, and routed net

Routed net

Unused

Unusable

HCLK1

Unused

Unusable

Note: Designer software currently does not support all of these connections. Only exclusive connections

where one output connects to a single net are supported at this time (e.g.CLK1 driving HCLK1,

and HCLK2 is not supported).

Revision 18

2-79

Detailed Specifications

Table 2-83 • South PLL Connections

CLK1

CLK2

CLK1

Routed net

Unused

CLK1

CLK2

CLK1

CLK2

Routed net

CLK2

Both CLK1 and routed net

Unused

CLK2

Unused

CLK1

Unused

Routed net

Both CLK1 and routed net

Unused

Routed net

CLK1

Routed net

Unused

Both CLK1 and CLK2

Both CLK1 and routed net

Both CLK2 and routed net

CLK1, CLK2, and routed net

Routed net

Unused

Unusable

CLK1

Unused

Unusable

Note: Designer software currently does not support all of these connections. Only exclusive connections

where one output connects to a single net are supported at this time (e.g., CLK1 driving both

CLK1 and CLK2 is not supported).

2-80

Revision 18

Axcelerator Family FPGAs

Special PLL Macros

Table 2-84 shows the macros used to connect the RefCLK input and CLK1 and CLK2 outputs using the

different routing resources.

Table 2-84 • PLL Special Macros

Macro Name

PLLINT

Usage

Connects RefCLK to a regular routed net or a pad.

Connects CLK1 or CLK2 to the CLK network.

Connects CLK1 or CLK2 to the HCLK network.

Connects CLK1 or CLK2 to a regular routed net.

PLLRCLK

PLLHCLK

PLLOUT

Table 2-85 • Electrical Specifications

Parameter

Value

Notes

Lowest input frequency

Frequency Ranges

Reference Frequency (min.)

Reference Frequency (max.)

OSC Frequency (min.)

OSC Frequency (max.)

Jitter

14 MHz

200 MHz

20 MHz

1 GHz

Highest input frequency

Lowest output frequency

Highest output frequency

Long-Term Jitter (max.)

Percentage of period, low reference clock

frequencies

Long-Term Jitter (max.)

Short-Term Jitter (max.)

100ps

High reference clock frequencies

50ps+1% Percentage of output frequency

Acquisition Time (lock) from Cold Start

Acquisition Time (max.)*

400 cycles Period of low reference clock frequencies

Acquisition Time (max.)*

1.5 µs

High reference clock frequencies

Power Consumption

Analog Supply Current (low freq.)

Analog Supply Current (high freq.)

Digital Supply Current (low freq.)

Digital Supply Current (high freq.)

Duty Cycle

200 µA

Current at minimum oscillator frequency

Frequency-dependent current

0.5 µA/MHz Current at maximum oscillator frequency, unloaded

1 µA/MHz Frequency-dependent current

Minimum Output Duty Cycle

Maximum Output Duty Cycle

45%

55%

Note: *The lock bit remains Low until RefCLK reaches the minimum input frequency.

Revision 18

2-81

Detailed Specifications

User Flow

There are two methods of including a PLL in a design:

•

The recommended method of using a PLL is to create custom PLL blocks using Microsemi's

macro generator, SmartGen, that can be instantiated in a design.

The alternative method is to instantiate one of the generic library primitives (PLL or PLLFB) into

either a schematic or HDL netlist, using inverters for polarity control and tying all unused address

and data bits to ground.

Timing Model

Lock

CLK1

t_PCLK

CLK

CLK2

Note: t_PCLKis the delay in the clock signal

Figure 2-52 • PLL Model

2-82

Revision 18

Axcelerator Family FPGAs

Sample Implementations

Frequency Synthesis

Figure 2-53 illustrates an example where the PLL is used to multiply a 155.5 MHz external clock up to

622 MHz. Note that the same PLL schematic could use an external 350 MHz clock, which is divided

down to 155 MHz by the FPGA internal logic.

Figure 2-54 illustrates the PLL using both dividers to synthesize a 133 MHz output clock from a 155 MHz

input reference clock. The input frequency of 155 MHz is multiplied by 6 and divided by 7, giving a CLK1

output frequency of 132.86 MHz. When dividers are used, a given ratio can be generated in multiple

ways, allowing the user to stay within the operating frequency ranges of the PLL.

DividerJ

Power-Down

Lock

RefCLK

/i Delay

Match

Delay Line

155.5 MHz

CLK1

PLL

CLK2

/j Delay

Match

622 MHz

FBMuxSel

DelayLine

DividerI

LowFreq

Osc

Figure 2-53 • Using the PLL 155.5 MHz In, 622 MHz Out

Adjustable Clock Delay

Figure 2-55 illustrates using the PLL to delay the reference clock by employing one of the adjustable

delay lines. In this case, the output clock is delayed relative to the reference clock. Delaying the

reference clock relative to the output clock is accomplished by using the delay line in the feedback path.

Revision 18

2-83

Detailed Specifications

DividerJ

Power-Down

RefCLK

Lock

Delay Line

/i Delay

Match

155 MHz

132.8 MHz

CLK1

155 MHz

930 MHz

PLL

Yes

Delay Line

CLK2

/j Delay

Match

FBMuxSel

DelayLine

LowFreq

Osc

DividerI

Figure 2-54 • Using the PLL 155 MHz In, 133 MHz Out

DividerJ

PowerDown

RefCLK

Lock

/i Delay

Match

Delay Line

133 MHz

CLK1

PLL

CLK2

/j Delay

Match

133 MHz

FBMuxSel

DelayLine

DividerI

LowFreq

Osc

Figure 2-55 • Using the PLL Delaying the Reference Clock

2-84

Revision 18

Axcelerator Family FPGAs

Clock Skew Minimization

Figure 2-56 indicates how feedback from the clock network can be used to create minimal skew between

the distributed clock network and the input clock. The input clock is fed to the reference clock input of the

PLL. The output clock (CLK2) feeds a routed clock network. The feedback input to the PLL uses a clock

input delayed by a routing network. The PLL then adjusts the phase of the input clock to match the

delayed clock, thus providing nearly zero effective skew between the two clocks. Refer to the Axcelerator

Family PLL and Clock Management application note for more information.

DividerJ

Power-Down

Lock

RefCLK

Input Clock

/i Delay

Match

Delay Line

133 MHz

CLK1

CLK2

133 MHz

PLL

/i Delay

Match

133 MHz

LowFreq

FBMuxSel DelayLine

DividerI

Osc

SET

CLR

Clock Network

Figure 2-56 • Using the PLL for Clock Deskewing

Revision 18

2-85

Detailed Specifications

Embedded Memory

The AX architecture provides extensive, high-speed memory resources to the user. Each 4,608 bit block

of RAM contains its own embedded FIFO controller, allowing the user to configure each block as either

RAM or FIFO.

To meet the needs of high performance designs, the memory blocks operate in synchronous mode for

both read and write operations. However, the read and write clocks are completely independent, and

each may operate up to and above 500 MHz.

No additional core logic resources are required to cascade the address and data buses when cascading

different RAM blocks. Dedicated routing runs along each column of RAM to facilitate cascading.

The AX memory block includes dedicated FIFO control logic to generate internal addresses and external

flag logic (FULL, EMPTY, AFULL, AEMPTY). Since read and write operations can occur asynchronously

to one another, special control circuitry is included to prevent metastability, overflow, and underflow. A

block diagram of the memory module is illustrated in Figure 2-57.

During RAM operation, read (RA) and write (WA) addresses are sourced by user logic and the FIFO

controller is ignored. In FIFO mode, the internal addresses are generated by the FIFO controller and

routed to the RAM array by internal MUXes. Enables with programmable polarity are provided to create

upper address bits for cascading up to 16 memory blocks. When cascading memory blocks, the bussed

signals WA, WD, WEN, RA, RD, and REN are internally linked to eliminate external routing congestion.

RD [(N-1):0]

RA [K:0]

REN

RCLK

WD [(M-1):0]

WA [J:0]

WEN

WCLK

PIPE

RW [2:0]

WW [2:0]

Figure 2-57 • Axcelerator Memory Module

2-86

Revision 18

Axcelerator Family FPGAs

RAM

Each memory block consists of 4,608 bits that can be organized as 128x36, 256x18, 512x9, 1kx4, 2kx2,

or 4kx1 and are cascadable to create larger memory sizes. This allows built-in bus width conversion

(Table 2-86). Each block has independent read and write ports which enable simultaneous read and write

operations.

Table 2-86 • Memory Block WxD Options

Data-word (in bits)

Depth

4,096

2,048

1,024

512

Address Bus

RA/WA[11:0]

RA/WA[10:0]

RA/WA[9:0]

RA/WA[8:0]

RA/WA[7:0]

RA/WA[6:0]

Data Bus

RD/WD[0]

RD/WD[1:0]

RD/WD[3:0]

RD/WD[8:0]

RD/WD[17:0]

RD/WD[35:0]

256

128

Clocks

The RCLK and the WCLK have independent source polarity selection and can be sourced by any global

or local signal.

RAM Configurations

The AX architecture allows the read side and write side of RAMs to be organized independently, allowing

for bus conversion. For example, the write side can be set to 256x18 and the read side to 512x9.

Both the write width and read width for the RAM blocks can be specified independently and changed

dynamically with the WW (write width) and RW (read width) pins. The D x W different configurations are:

128 x 36, 256 x 18, 512 x 9, 1k x 4, 2k x 2, and 4k x 1. The allowable RW and WW values are shown in

Table 2-87.

Table 2-87 • Allowable RW and WW Values

RW(2:0)

000

WW(2:0)

000

D x W

4k x 1

001

2k x 2

010

1k x 4

011

512 x 9

256 x 18

128 x 36

reserved

100

101

11x

When widths of one, two, and four are selected, the ninth bit is unused. For example, when writing nine-

bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit

value are addressable for read operations. The ninth bit is not accessible. Conversely, when writing four-

bit values and reading nine-bit values, the ninth bit of a read operation will be undefined.

Revision 18

2-87

Detailed Specifications

Note that the RAM blocks employ little-endian byte order for read and write operations.

Table 2-88 • RAM Signal Description

Signal

WCLK

WA[J:0]

Direction

Input

Description

Write clock (can be active on either edge).

Input

Write address bus.The value J is dependent on the RAM configuration and the

number of cascaded memory blocks. The valid range for J is from 6 to15.

WD[M-1:0] Input

Write data bus. The value M is dependent on the RAM configuration and can

be 1, 2, 4, 9, 18, or 36.

RCLK

Input

Read clock (can be active on either edge).

RA[K:0]

Read address bus. The value K is dependent on the RAM configuration and

the number of cascaded memory blocks. The valid range for K is from 6 to 15.

RD[N-1:0] Output

Read data bus. The value N is dependent on the RAM configuration and can

be 1, 2, 4, 9, 18, or 36.

REN

Input

Read enable. When this signal is valid on the active edge of the clock, data at

location RA will be driven onto RD.

WEN

Write enable. When this signal is valid on the active edge of the clock, WD data

will be written at location WA.

RW[2:0]

WW[2:0]

Pipe

Input

Width of the read operation dataword.

Width of the write operation dataword.

Sets the pipe option to be on or off.

Modes of Operation

There are two read modes and one write mode:

•

Read Nonpipelined (synchronous – one clock edge)

Read Pipelined (synchronous – two clock edges)

Write (synchronous – one clock edge)

In the standard read mode, new data is driven onto the RD bus in the clock cycle immediately following

RA and REN valid. The read address is registered on the read-port active-clock edge and data appears

at read-data after the RAM access time. Setting the PIPE to OFF enables this mode.

The pipelined mode incurs an additional clock delay from address to data, but enables operation at a

much higher frequency. The read-address is registered on the read-port active-clock edge, and the read

data is registered and appears at RD after the second read clock edge. Setting the PIPE to ON enables

this mode.

On the write active-clock edge, the write data are written into the SRAM at the write address when WEN

is high. The setup time of the write address, write enables, and write data are minimal with respect to the

write clock.

Write and read transfers are described with timing requirements beginning in the "Timing Characteristics"

section on page 2-89.

2-88

Revision 18

Axcelerator Family FPGAs

Timing Characteristics

WCLK

WEN

RCLK

REN

Figure 2-58 • SRAM Model

t_WCKH

t_WCKP

t_WCKL

WCLK

t_WxxSU

t_WxxHD

WA<11:0>, WD<35:0>, WEN<4:0>

Figure 2-59 • RAM Write Timing Waveforms

t_RCKH

t_RCKL

t_RCKP

RCLK

t_RxxSU

t_RxxHD

RA<11:0>, REN<4:0>

t_RCK2RD1

t_RCK2RD2

RD <35:0>

Figure 2-60 • RAM Read Timing Waveforms

Revision 18

2-89

Detailed Specifications

Table 2-89 • One RAM Block

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Parameter

Write Mode

t_WDASU

t_WDAHD

t_WADSU

t_WADHD

t_WENSU

t_WENHD

t_WCKH

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Write Data Setup vs. WCLK

Write Data Hold vs. WCLK

1.08

0.22

1.08

0.00

1.08

0.22

1.23

0.25

1.23

0.00

1.23

0.25

1.45

0.30

1.45

0.00

1.45

0.30

Write Address Setup vs. WCLK

Write Address Hold vs. WCLK

Write Enable Setup vs. WCLK

Write Enable Hold vs. WCLK

WCLK Minimum High Pulse Width

WCLK Minimum Low Pulse Width

WCLK Minimum Period

0.75

0.88

1.63

0.75

0.88

1.63

0.75

0.88

1.63

t_WCLK

t_WCKP

Read Mode

t_RADSU

Read Address Setup vs. RCLK

Read Address Hold vs. RCLK

Read Enable Setup vs. RCLK

Read Enable Hold vs. RCLK

RCLK-to-OUT (Pipelined)

0.81

0.00

0.81

0.00

1.32

2.16

0.92

0.00

0.92

0.00

1.51

2.46

1.08

0.00

1.08

0.00

1.77

2.90

t_RADHD

t_RENSU

t_RENHD

t_RCK2RD1

t_RCK2RD2

t_RCLKH

RCLK-to-OUT (Non-Pipelined)

RCLK Minimum High Pulse Width

RCLK Minimum Low Pulse Width

RCLK Minimum Period

0.77

0.93

1.70

0.77

0.93

1.70

0.77

0.93

1.70

t_RCLKL

t_RCKP

Note: Timing data for this single block RAM has a depth of 4,096. For all other combinations, use Microsemi’s timing

software.

2-90

Revision 18

Axcelerator Family FPGAs

Table 2-90 • Two RAM Blocks Cascaded

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed Std Speed

Parameter

Write Mode

t_WDASU

t_WDAHD

t_WADSU

t_WADHD

t_WENSU

t_WENHD

t_WCKH

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Write Data Setup vs. WCLK

Write Data Hold vs. WCLK

1.39

0.00

1.39

0.00

1.39

0.00

1.59

0.00

1.59

0.00

1.59

0.00

1.87

0.00

1.87

0.00

1.87

0.00

Write Address Setup vs. WCLK

Write Address Hold vs. WCLK

Write Enable Setup vs. WCLK

Write Enable Hold vs. WCLK

WCLK Minimum High Pulse Width

WCLK Minimum Low Pulse Width

WCLK Minimum Period

0.75

1.76

2.51

0.75

1.76

2.51

0.75

1.76

2.51

t_WCLK

t_WCKP

Read Mode

t_RADSU

Read Address Setup vs. RCLK

Read Address Hold vs. RCLK

Read Enable Setup vs. RCLK

Read Enable Hold vs. RCLK

RCLK-To-OUT (Pipelined)

1.71

0.00

1.71

0.00

1.43

2.26

1.94

0.00

1.94

0.00

1.63

2.58

2.28

0.00

2.28

0.00

1.92

3.03

t_RADHD

t_RENSU

t_RENHD

t_RCK2RD1

t_RCK2RD2

t_RCLKH

RCLK-To-OUT (Non-Pipelined)

RCLK Minimum High Pulse Width

RCLK Minimum Low Pulse Width

RCLK Minimum Period

0.73

1.89

2.62

0.73

1.89

2.62

0.73

1.89

2.62

t_RCLKL

t_RCKP

Note: Timing data for these two cascaded RAM blocks uses a depth of 8,192. For all other combinations, use

Microsemi’s timing software.

Revision 18

2-91

Detailed Specifications

Table 2-91 • Four RAM Blocks Cascaded

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Parameter

Write Mode

t_WDASU

t_WDAHD

t_WADSU

t_WADHD

t_WENSU

t_WENHD

t_WCKH

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Write Data Setup vs. WCLK

Write Data Hold vs. WCLK

2.37

0.00

2.37

0.00

2.37

0.00

2.70

0.00

2.70

0.00

2.70

0.00

3.17

0.00

3.17

0.00

3.17

0.00

Write Address Setup vs. WCLK

Write Address Hold vs. WCLK

Write Enable Setup vs. WCLK

Write Enable Hold vs. WCLK

WCLK Minimum High Pulse Width

WCLK Minimum Low Pulse Width

WCLK Minimum Period

0.75

2.51

3.26

0.75

2.51

3.26

0.75

2.51

3.26

t_WCLK

t_WCKP

Read Mode

t_RADSU

Read Address Setup vs. RCLK

Read Address Hold vs. RCLK

Read Enable Setup vs. RCLK

Read Enable Hold vs. RCLK

RCLK-To-OUT (Pipelined)

3.08

0.00

3.08

0.00

2.36

2.83

3.51

0.00

3.51

0.00

2.69

3.23

4.13

0.00

4.13

0.00

3.16

3.79

t_RADHD

t_RENSU

t_RENHD

t_RCK2RD1

t_RCK2RD2

t_RCLKH

RCLK-To-OUT (Non-Pipelined)

RCLK Minimum High Pulse Width

RCLK Minimum Low Pulse Width

RCLK Minimum Period

0.73

2.96

3.69

0.73

2.96

3.69

0.73

2.96

3.69

t_RCLKL

t_RCKP

Note: Timing data for these four cascaded RAM blocks uses a depth of 16,384. For all other combinations, use

Microsemi’s timing software.

2-92

Revision 18

Axcelerator Family FPGAs

Table 2-92 • Eight RAM Blocks Cascaded

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Parameter

Write Mode

t_WDASU

t_WDAHD

t_WADSU

t_WADHD

t_WENSU

t_WENHD

t_WCKH

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Write Data Setup vs. WCLK

Write Data Hold vs. WCLK

5.78

0.00

5.78

0.00

5.78

0.00

6.58

0.00

6.58

0.00

6.58

0.00

7.74

0.00

7.74

0.00

7.74

0.00

Write Address Setup vs. WCLK

Write Address Hold vs. WCLK

Write Enable Setup vs. WCLK

Write Enable Hold vs. WCLK

WCLK Minimum High Pulse Width

WCLK Minimum Low Pulse Width

WCLK Minimum Period

0.75

5.13

5.88

0.75

5.13

5.88

0.75

5.13

5.88

t_WCLK

t_WCKP

Read Mode

t_RADSU

Read Address Setup vs. RCLK

Read Address Hold vs. RCLK

Read Enable Setup vs. RCLK

Read Enable Hold vs. RCLK

RCLK-To-OUT (Pipelined)

6.75

0.00

6.75

0.00

3.39

4.93

7.69

0.00

7.69

0.00

3.86

5.62

9.04

0.00

9.04

0.00

4.54

6.61

t_RADHD

t_RENSU

t_RENHD

t_RCK2RD1

t_RCK2RD2

t_RCLKH

RCLK-To-OUT (Non-Pipelined)

RCLK Minimum High Pulse Width

RCLK Minimum Low Pulse Width

RCLK Minimum Period

0.73

5.77

6.50

0.73

5.77

6.50

0.73

5.77

6.50

t_RCLKL

t_RCKP

Note: Timing data for these eight cascaded RAM blocks uses a depth of 32,768. For all other combinations, use

Microsemi’s timing software.

Revision 18

2-93

Detailed Specifications

Table 2-93 • Sixteen RAM Blocks Cascaded

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Min. Max. Units

Parameter

Write Mode

t_WDASU

t_WDAHD

t_WADSU

t_WADHD

t_WENSU

t_WENHD

t_WCKH

Description

Min.

Max.

Min.

Max.

Write Data Setup vs. WCLK

Write Data Hold vs. WCLK

16.54

0.00

18.84

0.00

22.15

0.00

22.15

0.00

Write Address Setup vs. WCLK

Write Address Hold vs. WCLK

Write Enable Setup vs. WCLK

Write Enable Hold vs. WCLK

WCLK Minimum High Pulse Width

WCLK Minimum Low Pulse Width

WCLK Minimum Period

16.54

0.00

18.84

0.00

16.54

0.00

18.84

0.00

22.15

0.00

0.75

13.40

14.15

0.75

13.40

14.15

0.75

13.40

14.15

t_WCLK

t_WCKP

Read Mode

t_RADSU

Read Address Setup vs. RCLK

Read Address Hold vs. RCLK

Read Enable Setup vs. RCLK

Read Enable Hold vs. RCLK

RCLK-To-OUT (Pipelined)

18.13

0.00

20.65

0.00

24.27

0.00

t_RADHD

t_RENSU

18.13

0.00

20.65

0.00

24.27

0.00

t_RENHD

t_RCK2RD1

t_RCK2RD2

t_RCLKH

12.08

12.83

13.76

14.62

16.17

17.18

RCLK-To-OUT (Non-Pipelined)

RCLK Minimum High Pulse Width

RCLK Minimum Low Pulse Width

RCLK Minimum Period

0.73

14.41

15.14

0.73

14.41

15.14

0.73

14.41

15.14

t_RCLKL

t_RCKP

Note: Timing data for these sixteen cascaded RAM blocks uses a depth of 65,536. For all other combinations, use

Microsemi’s timing software.

2-94

Revision 18

Axcelerator Family FPGAs

FIFO

Every memory block has its own embedded FIFO controller. Each FIFO block has one read port and one

write port. This embedded FIFO controller uses no internal FPGA logic and features:

•

Glitch-free FIFO Flags

Gray-code address counters/pointers to prevent metastability problems

Overflow and underflow control

Both ports are configurable in various sizes from 4k x 1 to 128 x 36, similar to the RAM block size. Each

port is fully synchronous.

Read and write operations can be completely independent. Data on the appropriate WD pins are written

to the FIFO on every active WCLK edge as long as WEN is high. Data is read from the FIFO and output

on the appropriate RD pins on every active RCLK edge as long as REN is asserted.

The FIFO block offers programmable almost-empty (AEMPTY) and almost-full (AFULL) flags as well as

EMPTY and FULL flags (Figure 2-61):

•

The FULL flag is synchronous to WCLK. It allows the FIFO to inhibit writing when full.

The EMPTY flag is synchronous to RCLK. It allows the FIFO to inhibit reading at the empty

condition.

Gray code counters are used to prevent metastability problems associated with flag logic. The depth of

the FIFO is dependent on the data width and the number of memory blocks used to create the FIFO. The

write operations to the FIFO are synchronous with respect to the WCLK, and the read operations are

synchronous with respect to the RCLK.

The FIFO block may be reset to the empty state.

RD [n-1:0]

WD [n-1:0]

RCLK

WCLK

RAM

RA [J:0]

WA [J:0]

REN

WEN

DEPTH[3:0]

FREN

CNT 16

FULL

AFULL

AFVAL

AEVAL

AEMPTY

EMPTY

CNT 16

FWEN

CLR

Figure 2-61 • Axcelerator RAM with Embedded FIFO Controller

Revision 18

2-95

Detailed Specifications

FIFO Flag Logic

The FIFO is user configurable into various DEPTHs and WIDTHs. Figure 2-62 shows the FIFO address

counter details.

•

Bits 11 to 5 are active for all modes.

As the data word size is reduced, more least-significant bits are added to the address.

As the number of cascaded blocks increases, the number of significant bits in the address

increases.

For example, if four blocks are cascaded as a 1kx16 FIFO with each block having a 1kx4 aspect ratio,

bits 11 to 2 of the address will be used to specify locations within each RAM block, whereas bits 13 and

12 will be used to specify the RAM block.

FIFO Address Counters

Mode when

Active

Counter

Bits

FIFO Address

Alignment of

Threshold bits

R/W EN[3]

R/W EN[2]

Cas 16 blks

Cas 8 blks

CNTR [15]

activate

AEVAL/AFVAL[7]

AEVAL/AFVAL[6]

CNTR [14]

activate

[15:W]

Cas 4 blks

Cas 2 blks

CNTR [13]

activate

R/W EN[1]

R/W EN[0]

AEVAL/AFVAL[5]

AEVAL/AFVAL[4]

[14:W]

[13:W]

[12:W]

CNTR [12]

activate

4kx1

128x36 256x18

512x9

1kx4

2kx2

R/W ADD[11:8]

R/W ADD[7:5]

AEVAL/AFVAL[3:0]

not compared

by 36

CNTR [11:5]

always active

[11:5]

[11:4]

[11:3]

by 18

by 9

CNTR [4]

activate

R/W ADD[4]

not compared

[11:2]

CNTR [3]

activate

[11:1]

R/W ADD[3]

R/W ADD[2]

[11:0]

by 4

by 2

by 1

CNTR [2]

activate

CNTR [1]

activate

R/W ADD[1]

R/W ADD[0]

CNTR [0]

activate

Variable Active Address Space

CNTR [15:0]

>> REN [4:0], RAD [11:0]

>> WEN [4:0], WAD [11:0]

Note: Inactive counter bits are set to zero.

Figure 2-62 • FIFO Address Counters

The AFULL and AEMPTY flag threshold values are programmable. The threshold values are AFVAL and

AEVAL, respectively. Although the trigger threshold for each flag is defined with eight bits, the effective

number of threshold bits in the comparison depends on the configuration. The effective number of

threshold bits corresponds to the range of active bits in the FIFO address space (Table 2-94).

Table 2-94 • FIFO Flag Logic

Inactive

AEVAL/AFVAL Bits

Inactive DIFF

Bits (set to 0)

Mode

DIFF Comparison to AFVAL/AEVAL

DIFF[11:8] withAE/FVAL[3:0]

DIFF[12:8] withAE/FVAL[4:0]

DIFF[13:8] withAE/FVAL[5:0]

DIFF[14:8] withAE/FVAL[6:0]

DIFF[15:8] withAE/FVAL[7:0]

Non-cascade

[7:4]

[7:5]

[7:6]

[7]

[15:12]

[15:13]

[15:14]

[15]

Cascade 2 blocks

Cascade 4 blocks

Cascade 8 blocks

Cascade 16 blocks

None

2-96

Revision 18

Axcelerator Family FPGAs

Figure 2-63 illustrates flag generation.

ALMOST EMPTY and ALMOST FULL Logic

AEMPTY

AEVAL [7:0], GND [7:0] (MSB....LSB)

WCNTR

[15:0]

WCLK

RCLK

X>=Y

(16 bit)

DIFF [15:0]

RCNTR

[15:0]

AFULL

AFVAL [7:0], GND [7:0] (MSB....LSB)

Figure 2-63 • ALMOST-EMPTY and ALMOST-FULL Logic

The Verilog codes for the flags are:

assign AF = (DIFF[15:0] >={AFVAL[7:0],8'b00000000})?1:0;

assign AE = ({AEVAL[7:0],8'b00000000}>=DIFF[15:0])?1:0;

The number of DIFF-bits active depends on the configuration depth and width (Table 2-95).

Table 2-95 • Number of Available Configuration Bits

Number of Blocks

Block DxW

1x1

Number of AEVAL/AFVAL Bits

1x2

2x1

1x4

2x2

4x1

1x8

2x4

4x2

8x1

1x16

2x8

4x4

8x2

16x1

The active-high CLR pin is used to reset the FIFO to the empty state, which sets FULL and AFULL low,

and EMPTY and AEMPTY high.

Assuming that the EMPTY flag is not set, new data is read from the FIFO when REN is valid on the active

edge of the clock. Write and read transfers are described with timing requirements in "Timing

Characteristics" on page 2-100.

Revision 18

2-97

Detailed Specifications

Glitch Elimination

An analog filter is added to each FIFO controller to guarantee glitch-free FIFO-flag logic.

Overflow and Underflow Control

The counter MSB keeps track of the difference between the read address (RA) and the write address

(WA). The EMPTY flag is set when the read and write addresses are equal. To prevent underflow, the

write address is double-sampled by the read clock prior to comparison with the read address (part A in

Figure 2-64). To prevent overflow, the read address is double-sampled by the write clock prior to

comparison to the write address (part B in Figure 2-64).

FULL

EMPTY

RCLK

WCLK

Figure 2-64 • Overflow and Underflow Control

FIFO Configurations

Unlike the RAM, the FIFO's write width and read width cannot be specified independently. For the FIFO,

the write and read widths must be the same. The WIDTH pins are used to specify one of six allowable

word widths, as shown in Table 2-96.

Table 2-96 • FIFO Width Configurations

WIDTH(2:0)

000

W x D

1 x 4k

001

2 x 2k

010

4 x 1k

011

9 x 512

18 x 256

36 x 128

reserved

100

101

11x

The DEPTH pins allow RAM cells to be cascaded to create larger FIFOs. The four pins allow depths of 2,

4, 8, and 16 to be specified. Table 2-86 on page 2-87 describes the FIFO depth options for various data

width and memory blocks.

Interface

Figure 2-65 on page 2-99 shows a logic block diagram of the Axcelerator FIFO module.

Cascading FIFO Blocks

FIFO blocks can be cascaded to create deeper FIFO functions. When building larger FIFO blocks, if the

word width can be fractured in a multi-bit FIFO, the fractured word configuration is recommended over a

cascaded configuration. For example, 256x36 can be configured as two blocks of 256x18. This should be

taken into account when building the FIFO blocks manually. However, when using SmartGen, the user

only needs to specify the depth and width of the necessary FIFO blocks. SmartGen automatically

configures these blocks to optimize performance.

2-98

Revision 18

Axcelerator Family FPGAs

Clock

As with RAM configuration, the RCLK and WCLK pins have independent polarity selection.

RD [35:0]

FULL

DEPTH [3:0]

WIDTH [2:0]

PIPE

FREN

EMPTY

AFULL

RCLK

AEVAL [7:0]

AEMPTY

AFVAL [7:0]

WD [35:0]

FWEN

WCLK

CLR

Figure 2-65 • FIFO Block Diagram

Table 2-97 • FIFO Signal Description

Signal

WCLK

FWEN

Direction

Input

Description

Write clock (active either edge).

Input

FIFO write enable. When this signal is asserted, the WD bus data is

latched into the FIFO, and the internal write counters are incremented.

WD[N-1:0]

FULL

Input

Write data bus. The value N is dependent on the RAM configuration and

can be 1, 2, 4, 9, 18, or 36.

Output

Active high signal indicating that the FIFO is FULL. When this signal is

set, additional write requests are ignored.

AFULL

AFVAL

RCLK

Output

Input

Active high signal indicating that the FIFO is AFULL.

8-bit input defining the AFULL value of the FIFO.

Read clock (active either edge).

Input

FREN

Input

FIFO read enable.

RD[N-1:0]

Output

Read data bus. The value N is dependent on the RAM configuration and

can be 1, 2, 4, 9, 18, or 36.

EMPTY

Output

Empty flag indicating that the FIFO is EMPTY. When this signal is

asserted, attempts to read the FIFO will be ignored.

AEMPTY

AEVAL

PIPE

Output

Input

Active high signal indicating that the FIFO is AEMPTY.

8-bit input defining the almost-empty value of the FIFO.

Sets the pipe option on or off.

CLR

Active high clear input.

DEPTH

Determines the depth of the FIFO and the number of FIFOs to be

cascaded.

WIDTH

Input

Determines the width of the dataword/FIFO, and the number of the

FIFOs to be cascaded.

Revision 18

2-99

Timing Characteristics

AEMPTY

EMPTY

AFULL

FULL

FWEN

FREN

WCLK

RCLK

Clr

Figure 2-66 • FIFO Model

t_WCKH

t_WCKP

t_WCKL

WCLK

t_WSU

t_WHD

WD<35:0>, FWEN

t_CLR2HF

CLR

t_CK2xF

t_CLR2xF

EMPTY, AEMPTY, AFULL, FULL

Figure 2-67 • FIFO Write Timing

Axcelerator Family FPGAs

t_RCKH

t_RCKL

t_RCKP

RCLK

FREN

t_RSUt_RHD

t_RCK2RD1

t_RCK2RD2

RD <35:0>

CLR

t_CLRHF

t_CLR2xF

t_CK2xF

EMPTY, AEMPTY, AFULL, FULL

Figure 2-68 • FIFO Read Timing

Revision 18

2-101

Detailed Specifications

Table 2-98 • One FIFO Block

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

FIFO Module Timing

t_WSU

Write Setup

11.40

0.22

0.75

0.88

12.98

0.25

0.75

0.88

15.26

0.30

0.75

0.88

t_WHD

Write Hold

t_WCKH

t_WCKL

t_WCKP

t_RSU

WCLK High

WCLK Low

Minimum WCLK Period

Read Setup

1.63

1.70

1.63

1.70

1.63

1.70

11.63

0.00

0.77

0.93

13.25

0.00

0.77

0.93

15.58

0.00

0.77

0.93

t_RHD

Read Hold

t_RCKH

t_RCKL

RCLK High

RCLK Low

t_RCKP

Minimum RCLK period

Clear High

t_CLRHF

t_CLR2FF

t_CLR2AF

t_CK2FF

t_CK2AF

t_RCK2RD1

t_RCK2RD2

0.00

1.92

4.39

2.13

5.04

1.32

2.16

0.00

2.18

5.00

2.42

5.75

1.51

2.46

0.00

2.57

5.88

2.85

6.75

1.77

2.90

Clear-to-flag (EMPTY/FULL)

Clear-to-flag (AEMPTY/AFULL)

Clock-to-flag (EMPTY/FULL)

Clock-to-flag (AEMPTY/AFULL)

RCLK-To-OUT (Pipelined)

RCLK-To-OUT (Non-Pipelined)

Note: Timing data for this single block FIFO has a depth of 4,096. For all other combinations, use Microsemi’s timing

software.

2-102

Revision 18

Axcelerator Family FPGAs

Table 2-99 • Two FIFO Blocks Cascaded

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

FIFO Module Timing

t_WSU

Write Setup

13.75

0.00

0.75

1.76

15.66

0.00

0.75

1.76

18.41

0.00

0.75

1.76

t_WHD

Write Hold

WCLK High

WCLK Low

t_WCKH

t_WCKL

t_WCKP

t_RSU

Minimum WCLK Period

Read Setup

2.51

2.62

2.51

2.62

2.51

2.62

14.33

0.00

0.73

1.89

16.32

0.00

0.73

1.89

19.19

0.00

0.73

1.89

t_RHD

Read Hold

t_RCKH

t_RCKL

RCLK High

RCLK Low

t_RCKP

Minimum RCLK period

Clear High

t_CLRHF

t_CLR2FF

t_CLR2AF

t_CK2FF

t_CK2AF

t_RCK2RD1

t_RCK2RD2

0.00

1.92

4.39

2.13

5.04

1.43

2.26

0.00

2.18

5.00

2.42

5.75

1.63

2.58

0.00

2.57

5.88

2.85

6.75

1.92

3.03

Clear-to-flag (EMPTY/FULL)

Clear-to-flag (AEMPTY/AFULL)

Clock-to-flag (EMPTY/FULL)

Clock-to-flag (AEMPTY/AFULL)

RCLK-To-OUT (Pipelined)

RCLK-To-OUT (Nonpipelined)

Note: Timing data for these two cascaded FIFO blocks uses a depth of 8,192. For all other combinations, use

Microsemi’s timing software.

Revision 18

2-103

Detailed Specifications

Table 2-100 • Four FIFO Blocks Cascaded

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

FIFO Module Timing

t_WSU

Write Setup

14.60

0.00

0.75

2.51

16.63

0.00

0.75

2.51

19.55

0.00

0.75

2.51

t_WHD

Write Hold

WCLK High

WCLK Low

t_WCKH

t_WCKL

t_WCKP

t_RSU

Minimum WCLK Period

Read Setup

3.26

3.69

3.26

3.69

3.26

3.69

15.27

0.00

0.73

2.96

17.39

0.00

0.73

2.96

20.44

0.00

0.73

2.96

t_RHD

Read Hold

t_RCKH

t_RCKL

RCLK High

RCLK Low

t_RCKP

Minimum RCLK period

Clear High

t_CLRHF

t_CLR2FF

t_CLR2AF

t_CK2FF

t_CK2AF

t_RCK2RD1

t_RCK2RD2

0.00

1.92

4.39

2.13

5.04

2.36

2.83

0.00

2.18

5.00

2.42

5.75

2.69

3.23

0.00

2.57

5.88

2.85

6.75

3.16

3.79

Clear-to-flag (EMPTY/FULL)

Clear-to-flag (AEMPTY/AFULL)

Clock-to-flag (EMPTY/FULL)

Clock-to-flag (AEMPTY/AFULL)

RCLK-To-OUT (Pipelined)

RCLK-To-OUT (Nonpipelined)

Note: Timing data for these four cascaded FIFO blocks uses a depth of 16,384. For all other combinations, use

Microsemi’s timing software.

2-104

Revision 18

Axcelerator Family FPGAs

Table 2-101 • Eight FIFO Blocks Cascaded

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed

Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

FIFO Module Timing

t_WSU

Write Setup

15.46

0.00

0.75

5.13

17.61

0.00

0.75

5.13

20.70

0.00

0.75

5.13

t_WHD

Write Hold

WCLK High

WCLK Low

t_WCKH

t_WCKL

t_WCKP

t_RSU

Minimum WCLK Period

Read Setup

5.88

6.50

5.88

6.50

5.88

6.50

16.22

0.00

0.73

5.77

18.47

0.00

0.73

5.77

21.72

0.00

0.73

5.77

t_RHD

Read Hold

t_RCKH

t_RCKL

RCLK High

RCLK Low

t_RCKP

Minimum RCLK period

Clear High

t_CLRHF

t_CLR2FF

t_CLR2AF

t_CK2FF

t_CK2AF

t_RCK2RD1

t_RCK2RD2

0.00

1.92

4.39

2.13

5.04

3.39

4.93

0.00

2.18

5.00

2.42

5.75

3.86

5.62

0.00

2.57

5.88

2.85

6.75

4.54

6.61

Clear-to-flag (EMPTY/FULL)

Clear-to-flag (AEMPTY/AFULL)

Clock-to-flag (EMPTY/FULL)

Clock-to-flag (AEMPTY/AFULL)

RCLK-To-OUT (Pipelined)

RCLK-To-OUT (Nonpipelined)

Note: Timing data for these eight cascaded FIFO blocks uses a depth of 32,768. For all other combinations, use

Microsemi’s timing software.

Revision 18

2-105

Detailed Specifications

Table 2-102 • Sixteen FIFO Blocks Cascaded

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, T_J= 70°C

–2 Speed –1 Speed Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

FIFO Module Timing

t_WSU

Write Setup

16.32

0.00

18.60

0.00

21.86

0.00

t_WHD

Write Hold

WCLK High

WCLK Low

t_WCKH

t_WCKL

t_WCKP

t_RSU

0.75

13.40

Minimum WCLK Period

Read Setup

14.15

15.14

14.15

15.14

14.15

15.14

17.16

0.00

19.54

0.00

22.97

0.00

t_RHD

Read Hold

t_RCKH

t_RCKL

RCLK High

0.73

RCLK Low

14.41

t_RCKP

Minimum RCLK period

Clear High

t_CLRHF

t_CLR2FF

t_CLR2AF

t_CK2FF

t_CK2AF

t_RCK2RD1

t_RCK2RD2

0.00

1.92

0.00

2.18

0.00

2.57

Clear-to-flag (EMPTY/FULL)

Clear-to-flag (AEMPTY/AFULL)

Clock-to-flag (EMPTY/FULL)

Clock-to-flag (AEMPTY/AFULL)

RCLK-To-OUT (Pipelined)

RCLK-To-OUT (Nonpipelined)

4.39

5.00

5.88

2.13

2.42

2.85

5.04

5.75

6.75

12.08

12.83

13.76

14.62

16.17

17.18

Note: Timing data for these sixteen cascaded FIFO blocks uses a depth of 65,536. For all other combinations, use

Microsemi’s timing software.

Building RAM and FIFO Modules

RAM and FIFO modules can be generated and included in a design in two different ways:

•

Using the SmartGen Core Generator where the user defines the depth and width of the

FIFO/RAM, and then instantiates this block into the design (refer to the SmartGen, FlashROM,

Analog System Builder, and Flash Memory System Builder User’s Guide for more information).

•

The alternative is to instantiate the RAM/FIFO blocks manually, using inverters for polarity control

and tying all unused data bits to ground.

Other Architectural Features

Low Power Mode

Although designed for high performance, the AX architecture also allows the user to place the device into

a low power mode. Each I/O bank in an Axcelerator device can be configured individually, when in low

power mode, to tristate all outputs, disable inputs, or both. The low power mode is activated by asserting

the LP pin, which is grounded in normal operation.

While in the low power mode, the device is still fully functional and all internal logic states are preserved.

This allows a user to disable all but a few signals and operate the part in a low-frequency, watchdog

2-106

Revision 18

Axcelerator Family FPGAs

mode if desired. Please note, if the I/O bank is not disabled, differential I/Os belonging to the I/O bank will

still consume normal power, even when operating in the low power mode.

The Axcelerator device will resume normal operation 10μs after the LP pin is pulled Low.

To further reduce power consumption, the internal charge pump can be bypassed and an external power

supply voltage can be used instead. This saves the internal charge-pump operating current, resulting in

no DC current draw. The Axcelerator family devices have a dedicated "V_PUMP" pin that can be used to

access an external charge pump device. In normal chip operation, when using the internal charge pump,

V_PUMPshould be tied to GND. When the voltage level on V_PUMPis set to 3.3V, the internal charge pump

is turned off, and the V_PUMPvoltage will be used as the charge pump voltage. Adequate voltage

regulation (i.e. high drive, low output impedance, and good decoupling) should be used at V_PUMP

In addition, any PLL in use can be powered down to further reduce power consumption. This can be

done with the PowerDown pin driven Low. Driving this pin High restarts the PLL with the output clock(s)

being stable once lock is restored.

JTAG

Axcelerator offers a JTAG interface that is compliant with the IEEE 1149.1 standard. The user can

employ the JTAG interface for probing a design and performing any JTAG Public Instructions as defined

in the Table 2-103.

Table 2-103 • JTAG Instruction Code

Instruction (IR4:IR0)

Extest

Binary Code

00000

Preload / Sample

Intest

00001

00010

USERCODE

IDCODE

00011

00100

HIGHZ

01110

CLAMP

01111

Diagnostic

Reserved

Bypass

10000

All others

11111

Interface

The interface consists of four inputs: Test Mode Select (TMS), Test Data In (TDI), Test Clock (TCK), TAP

Controller Reset (TRST), and an output, Test Data Out (TDO). TMS, TDI, and TRST have on-chip pull-up

resistors.

TRST

TRST (Test-Logic Reset) is an active-low, asynchronous reset signal to the TAP controller. The TRST

input can be used to reset the Test Access Port (TAP) Controller to the TRST state. The TAP Controller

can be held at this state permanently by grounding the TRST pin. To hold the JTAG TAP controller in the

TRST state, it is recommended to connect TRST to ground via a 1 kΩ resistor.

There is an optional internal pull-up resistor available for the TRST input that can be set by the user at

programming. Care should be exercised when using this option in combination with an external tie-off to

ground.

An on-chip power-on-reset (POWRST) circuit is included. POWRST has the same function as "TRST,"

but it only occurs at power-up or during recovery from a VCCA and/or VCCDA voltage drop.

Revision 18

2-107

Detailed Specifications

TDO

TDO is normally tristated, and it is active only when the TAP controller is in the "Shift_DR" state or

"Shift_IR" state. The least significant bit of the selected register (i.e. IR or DR) is clocked out to TDO first

by the falling edge of TCK.

TAP Controller

The TAP Controller is compliant with the IEEE Standard 1149.1. It is a state machine of 16 states that

controls the Instruction Register (IR) and the Data Registers (such as BSR, IDCODE, USRCODE,

BYPASS, etc.). The TAP Controller steps into one of the states depending on the sequence of TMS at

the rising edges of TCK.

Instruction Register (IR)

The IR has five bits (IR4 to IR0). At the TRST state, IR is reset to IDCODE. Each time when IR is

selected, it goes through "select IR-Scan," "Capture-IR," "Shift-IR," all the way through "Update-IR."

When there is no test error, the first five data bits coming out of TDO during the "Shift-IR" will be "10111".

If a test error occurs, the last three bits will contain one to three zeroes corresponding to negatively

asserted signals: "TDO_ERRORB," "PROBA_ERRORB," and "PROBB_ERRORB." The error(s) will be

erased when the TAP is at the "Update-IR" or the TRST state. When in user mode start-up sequence, if

the micro-probe has not been used, the "PROBA_ERRORB" is used as a "Power-up done successfully"

flag.

Data Registers (DRs)

Data registers are distributed throughout the chip. They store testing/programming vectors. The MSB of

a data register is connected to TDI, while the LSB is connected to TDO. There are different types of data

registers. Descriptions of the main registers are as follow:

1. IDCODE:

The IDCODE is a 20-bit hard coded JTAG Silicon Signature. It is a hardwired device ID code,

which contains the Microsemi identity, part number, and version number in a specific JTAG

format.

2. USERCODE:

The USERCODE is a 33-bit programmable register. However, only 20 bits are allocated to use as

JTAG Silicon Signature. It is a supplementary identity code for the user to program information to

distinguish different programmed parts. USERCODE fuses will read out as "zeroes" when not

programmed, so only the "1" bits need to be programmed.

3. Boundary-Scan Register (BSR):

Each I/O contains three Boundary-Scan Cells. Each cell has a shift register bit, a latch, and two

MUXes. The boundary-scan cells are used for the Output-enable (E), Output (O), and Input (I)

registers. The bit order of the boundary-scan cells for each of them is E-O-I. The boundary-scan

cells are then chained serially to form the Boundary-Scan Register (BSR). The length of the BSR

is the number of I/Os in the die multiplied by three.

4. Bypass Register (BYR):

This is the "1-bit" register. It is used to shorten the TDI-TDO serial chain in board-level testing to

only one bit per device not being tested. It is also selected for all "reserved" or unused

instructions.

Probing

Internal activities of the JTAG interface can be observed via the Silicon Explorer II probes: "PRA," "PRB,"

"PRC," and "PRD."

Special Fuses

Security

Microsemi antifuse FPGAs, with FuseLock technology, offer the highest level of design security available

in a programmable logic device. Since antifuse FPGAs are live-at power-up, there is no bitstream that

can be intercepted, and no bitstream or programming data is ever downloaded to the device during

power-up, thus protecting against device cloning. In addition, special security fuses are hidden

2-108

Revision 18

Axcelerator Family FPGAs

throughout the fabric of the device and may be programmed by the user to thwart attempts to reverse

engineer the device by attempting to exploit either the programming or probing interfaces. Both invasive

and noninvasive attacks against an Axcelerator device that access or bypass these security fuses will

destroy access to the rest of the device. (refer to the Design Security in Nonvolatile Flash and Antifuse

FPGAs white paper).

Look for this symbol to ensure your valuable IP is protected with highest level of security in the industry.

™

Figure 2-69 • FuseLock Logo

To ensure maximum security in Axcelerator devices, it is recommended that the user program the device

security fuse (SFUS). When programmed, the Silicon Explorer II testing probes are disabled to prevent

internal probing, and the programming interface is also disabled. All JTAG public instructions are still

accessible by the user.

For more information, refer to the Implementation of Security in Actel Antifuse FPGAs application note.

Global Set Fuse

The Global Set Fuse determines if all R-cells and I/O registers (InReg, OutReg, and EnReg) are either

cleared or preset by driving the GCLR and GPSET inputs of all R-cells and I/O Registers (Figure 2-31 on

page 2-58). Default setting is to clear all registers (GCLR = 0 and GPSET =1) at device power-up. When

the GBSETFUS option is checked during FUSE file generation, all registers are preset (GCLR = 1 and

GPSET= 0). A local CLR or PRESET will take precedence over this setting. Both pins are pulled High

during normal device operation. For use details, see the Libero IDE online help.

Silicon Explorer II Probe Interface

Silicon Explorer II is an integrated hardware and software solution that, in conjunction with the Designer

tools, allows users to examine any of the internal nets (except I/O registers) of the device while it is

operating in a prototype or a production system. The user can probe up to four nodes at a time without

changing the placement and routing of the design and without using any additional device resources.

Highlighted nets in Designer’s ChipPlanner can be accessed using Silicon Explorer II in order to observe

their real time values.

Silicon Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the

debug cycle. In addition, Silicon Explorer II does not require relayout or additional MUXes to bring signals

out to external pins, which is necessary when using programmable logic devices from other suppliers. By

eliminating multiple place-and-route program cycles, the integrity of the design is maintained throughout

the debug process.

Each member of the Axcelerator family has four external pads: PRA, PRB, PRC, and PRD. These can be

used to bring out four probe signals from the Axcelerator device (note that the AX125 only has two probe

signals that can be observed: PRA and PRB). Each core tile has up to two probe signals. To disallow

probing, the SFUS security fuse in the silicon signature has to be programmed (see "Special Fuses" on

page 2-108).

Silicon Explorer II connects to the host PC using a standard serial port connector. Connections to the

circuit board are achieved using a nine-pin D-Sub connector (Figure 1-9 on page 1-7). Once the design

has been placed-and-routed, and the Axcelerator device has been programmed, Silicon Explorer II can

be connected and the Explorer software can be launched.

Silicon Explorer II comes with an additional optional PC hosted tool that emulates an 18-channel logic

analyzer. Four channels are used to monitor four internal nodes, and 14 channels are available to probe

external signals. The software included with the tool provides the user with an intuitive interface that

allows for easy viewing and editing of signal waveforms.

Revision 18

2-109

Detailed Specifications

Programming

Device programming is supported through the Silicon Sculptor II, a single-site, robust and compact

device programmer for the PC. Up to four Silicon Sculptor IIs can be daisy-chained and controlled from a

single PC host. With standalone software for the PC, Silicon Sculptor II is designed to allow concurrent

programming of multiple units from the same PC when daisy-chained.

Silicon Sculptor II programs devices independently to achieve the fastest programming times possible.

Each fuse is verified by Silicon Sculptor II to ensure correct programming. Furthermore, at the end of

programming, there are integrity tests that are run to ensure that programming was completed properly.

Not only does it test programmed and nonprogrammed fuses, Silicon Sculptor II also provides a self-test

to test its own hardware extensively.

Programming an Axcelerator device using Silicon Sculptor II is similar to programming any other antifuse

device. The procedure is as follows:

1. Load the *.AFM file.

2. Select the device to be programmed.

3. Begin programming.

When the design is ready to go to production, Microsemi offers device volume-programming services

either through distribution partners or via our In-House Programming Center.

In addition, BP Microsystems offers multi-site programmers that provide qualified support for Axcelerator

devices.

For more details on programming the Axcelerator devices, please refer to the Silicon Sculptor II User’s

Guide.

2-110

Revision 18

Axcelerator Family FPGAs

Revision 18

2-111

3 – Package Pin Assignments

BG729

A1 Ball Pad Corner

27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.microsemi.com/soc/products/rescenter/package/index.html.

Revision 18

3-1

Package Pin Assignments

BG729

AX1000 Function

Bank 0

Number

AX1000 Function

IO18NB0F1

Number

AX1000 Function

IO36NB1F3

IO36PB1F3

IO37NB1F3

IO37PB1F3

IO38NB1F3

IO38PB1F3

IO39NB1F3

IO39PB1F3

IO40NB1F3

IO40PB1F3

IO41NB1F4

IO41PB1F4

IO42NB1F4

IO42PB1F4

IO43NB1F4

IO43PB1F4

IO44NB1F4

IO44PB1F4

IO45NB1F4

IO45PB1F4

IO46NB1F4

IO46PB1F4

IO47NB1F4

IO47PB1F4

IO48NB1F4

IO48PB1F4

IO49NB1F4

IO49PB1F4

IO50NB1F4

IO50PB1F4

IO51NB1F4

IO51PB1F4

IO52NB1F4

IO52PB1F4

IO53NB1F4

IO53PB1F4

IO54NB1F5

Number

C10

H15

G15

C17

C16

B18

B17

A18

A17

H16

G16

B19

A19

C19

C18

D18

D17

H17

G17

F17

E17

B20

A20

C21

C20

H18

G18

F18

E18

D20

D19

A22

A21

B22

B21

F19

E19

F20

IO00NB0F0

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO03NB0F0

IO03PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO07NB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO09NB0F0

IO09PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17NB0F1

IO17PB0F1

IO18PB0F1

IO19NB0F1

E11

F11

G12

H12

D11

D10

A10

IO19PB0F1

IO20NB0F1

IO20PB0F1

IO21NB0F1

IO21PB0F1

IO22NB0F2

IO22PB0F2

IO23NB0F2

B11

B10

G13

H13

C12

C11

E12

D12

E13

F13

G14

H14

A12

B12

C13

D13

F14

E14

IO23PB0F2

IO24NB0F2

IO24PB0F2

IO25NB0F2

IO25PB0F2

IO26NB0F2

IO26PB0F2

IO27NB0F2

IO27PB0F2

IO28NB0F2

G10

H10

IO28PB0F2

IO29NB0F2

IO29PB0F2

IO30NB0F2/HCLKAN

IO30PB0F2/HCLKAP

IO31NB0F2/HCLKBN

IO31PB0F2/HCLKBP

Bank 1

E10

F10

G11

H11

IO32NB1F3/HCLKCN

IO32PB1F3/HCLKCP

IO33NB1F3/HCLKDN

IO33PB1F3/HCLKDP

IO34NB1F3

C14

B14

D16

D15

B16

A16

E15

F15

IO34PB1F3

IO35NB1F3

IO35PB1F3

3-2

Revision 18

Axcelerator Family FPGAs

BG729

AX1000 Function

IO54PB1F5

IO55NB1F5

IO55PB1F5

IO56NB1F5

IO56PB1F5

IO57NB1F5

IO57PB1F5

IO58NB1F5

IO58PB1F5

IO59NB1F5

IO59PB1F5

IO60NB1F5

IO60PB1F5

IO61NB1F5

IO61PB1F5

IO62NB1F5

IO62PB1F5

IO63NB1F5

IO63PB1F5

Bank 2

Number

AX1000 Function

IO72PB2F6

IO73NB2F6

IO73PB2F6

IO74NB2F7

IO74PB2F7

IO75NB2F7

IO75PB2F7

IO76NB2F7

IO76PB2F7

IO77NB2F7

IO77PB2F7

IO78NB2F7

IO78PB2F7

IO79NB2F7

IO79PB2F7

IO80NB2F7

IO80PB2F7

IO81NB2F7

IO81PB2F7

IO82NB2F7

IO82PB2F7

IO83NB2F7

IO83PB2F7

IO84NB2F7

IO84PB2F7

IO85NB2F8

IO85PB2F8

IO86NB2F8

IO86PB2F8

IO87NB2F8

IO87PB2F8

IO88NB2F8

IO88PB2F8

IO89NB2F8

IO89PB2F8

IO90NB2F8

IO90PB2F8

Number

AX1000 Function

Number

N25

N24

N27

N26

P26

E20

E21

D21

H19

G19

D22

C22

B23

A23

D23

C23

G21

G20

E23

E22

F22

F21

H20

J19

J23

H24

H23

L21

K21

G27

F27

K23

K22

H26

H25

K25

K24

J26

IO91NB2F8

IO91PB2F8

IO92NB2F8

IO92PB2F8

IO93NB2F8

IO93PB2F8

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

P27

N19

N20

P23

P22

Bank 3

IO96NB3F9

IO96PB3F9

IO97NB3F9

IO97PB3F9

P25

P24

R26

R27

P21

P20

R24

R25

T26

T27

T24

T25

R20

R21

R23

R22

U26

U27

U24

U25

R19

P19

V26

V27

T23

T22

J25

M20

L20

J27

IO98NB3F9

IO98PB3F9

IO99NB3F9

IO99PB3F9

H27

L23

L22

L25

L24

N21

M21

K27

K26

M23

M22

M25

M24

L27

L26

M27

M26

N23

N22

IO100NB3F9

IO100PB3F9

IO101NB3F9

IO101PB3F9

IO102NB3F9

IO102PB3F9

IO103NB3F9

IO103PB3F9

IO104NB3F9

IO104PB3F9

IO105NB3F9

IO105PB3F9

IO106NB3F9

IO106PB3F9

IO107NB3F10

IO107PB3F10

IO108NB3F10

IO108PB3F10

IO64NB2F6

IO64PB2F6

IO65NB2F6

IO65PB2F6

IO66NB2F6

IO66PB2F6

IO67NB2F6

IO67PB2F6

IO68NB2F6

IO68PB2F6

IO69NB2F6

IO69PB2F6

IO70NB2F6

IO70PB2F6

IO71NB2F6

IO71PB2F6

IO72NB2F6

J21

H21

F24

F23

F26

F25

E26

E25

J22

H22

G24

G23

K20

J20

G26

G25

J24

Revision 18

3-3

Package Pin Assignments

BG729

AX1000 Function

IO109NB3F10

IO109PB3F10

IO110NB3F10

IO110PB3F10

IO111NB3F10

IO111PB3F10

IO112NB3F10

IO112PB3F10

IO113NB3F10

IO113PB3F10

IO114NB3F10

IO114PB3F10

IO115NB3F10

IO115PB3F10

IO116NB3F10

IO116PB3F10

IO117NB3F10

IO117PB3F10

IO118NB3F11

IO118PB3F11

IO119NB3F11

IO119PB3F11

IO120NB3F11

IO120PB3F11

IO121NB3F11

IO121PB3F11

IO122NB3F11

IO122PB3F11

IO123NB3F11

IO123PB3F11

IO124NB3F11

IO124PB3F11

IO125NB3F11

IO125PB3F11

IO126NB3F11

IO126PB3F11

IO127NB3F11

Number

AX1000 Function

IO127PB3F11

IO128NB3F11

IO128PB3F11

Bank 4

Number

AX1000 Function

IO145PB4F13

Number

V24

V25

AC27

Y20

AD19

AC18

AB18

Y17

IO146NB4F13

T20

W19

IO146PB4F13

T21

IO147NB4F13

W26

W27

U22

IO129NB4F12

IO129PB4F12

IO130NB4F12

IO130PB4F12

IO131NB4F12

IO131PB4F12

IO132NB4F12

IO132PB4F12

IO133NB4F12

IO133PB4F12

IO134NB4F12

IO134PB4F12

IO135NB4F12

IO135PB4F12

IO136NB4F12

IO136PB4F12

IO137NB4F12

IO137PB4F12

IO138NB4F12

IO138PB4F12

IO139NB4F13

IO139PB4F13

IO140NB4F13

IO140PB4F13

IO141NB4F13

IO141PB4F13

IO142NB4F13

IO142PB4F13

IO143NB4F13

IO143PB4F13

IO144NB4F13

IO144PB4F13

IO145NB4F13

AA20

Y21

IO147PB4F13

AA17

AF19

AF20

AC17

AB17

AE18

AE19

AA16

Y16

IO148NB4F13

AB22

AB23

AC22

AC23

AD23

AD24

AF23

AE23

AC21

AB21

AC20

AB20

AD21

AD22

Y19

IO148PB4F13

U23

IO149NB4F13

Y26

IO149PB4F13

Y27

IO150NB4F13

U20

IO150PB4F13

U21

IO151NB4F13

W24

W25

V22

IO151PB4F13

IO152NB4F14

AG18

AG19

AC16

AB16

AF17

AF18

AB15

AC15

AE16

AE17

Y15

IO152PB4F14

V23

IO153NB4F14

Y24

IO153PB4F14

Y25

IO154NB4F14

V20

IO154PB4F14

V21

IO155NB4F14

AA26

AA27

W22

W23

AA24

AA25

W20

W21

AB26

AB27

Y22

IO155PB4F14

AA19

AE21

AE22

AF21

AF22

AG22

AG23

Y18

IO156NB4F14

IO156PB4F14

IO157NB4F14

IO157PB4F14

AA15

AG16

AG17

AF15

AF16

AD14

AD15

IO158NB4F14

IO158PB4F14

IO159NB4F14/CLKEN

IO159PB4F14/CLKEP

IO160NB4F14/CLKFN

IO160PB4F14/CLKFP

Bank 5

AA18

AE20

AD20

AG20

AG21

AC19

AB19

AD18

Y23

AB24

AB25

AA22

AA23

AC26

IO161NB5F15/CLKGN

IO161PB5F15/CLKGP

IO162NB5F15/CLKHN

IO162PB5F15/CLKHP

IO163NB5F15

AE14

AE15

AC13

AD13

Y14

3-4

Revision 18

Axcelerator Family FPGAs

BG729

AX1000 Function

IO163PB5F15

IO164NB5F15

IO164PB5F15

IO165NB5F15

IO165PB5F15

IO166NB5F15

IO166PB5F15

IO167NB5F15

IO167PB5F15

IO168NB5F15

IO168PB5F15

IO169NB5F15

IO169PB5F15

IO170NB5F15

IO170PB5F15

IO171NB5F16

IO171PB5F16

IO172NB5F16

IO172PB5F16

IO173NB5F16

IO173PB5F16

IO174NB5F16

IO174PB5F16

IO175NB5F16

IO175PB5F16

IO176NB5F16

IO176PB5F16

IO177NB5F16

IO177PB5F16

IO178NB5F16

IO178PB5F16

IO179NB5F16

IO179PB5F16

IO180NB5F16

IO180PB5F16

IO181NB5F17

IO181PB5F17

Number

AX1000 Function

IO182NB5F17

IO182PB5F17

IO183NB5F17

IO183PB5F17

IO184NB5F17

IO184PB5F17

IO185NB5F17

IO185PB5F17

IO186NB5F17

IO186PB5F17

IO187NB5F17

IO187PB5F17

IO188NB5F17

IO188PB5F17

IO189NB5F17

IO189PB5F17

IO190NB5F17

IO190PB5F17

IO191NB5F17

IO191PB5F17

IO192NB5F17

IO192PB5F17

Bank 6

Number

AX1000 Function

Number

AA4

AA5

AB1

AC1

AA14

AE13

AF13

AF12

AG12

AD12

AE12

Y13

AF7

AG7

AD7

AE7

AC7

AC8

AF6

AG6

AB7

AB8

IO200NB6F18

IO200PB6F18

IO201NB6F18

IO201PB6F18

IO202NB6F18

IO202PB6F18

IO203NB6F19

IO203PB6F19

IO204NB6F19

IO204PB6F19

IO205NB6F19

IO205PB6F19

IO206NB6F19

IO206PB6F19

IO207NB6F19

IO207PB6F19

IO208NB6F19

IO208PB6F19

IO209NB6F19

IO209PB6F19

IO210NB6F19

IO210PB6F19

IO211NB6F19

IO211PB6F19

IO212NB6F19

IO212PB6F19

IO213NB6F19

IO213PB6F19

IO214NB6F20

IO214PB6F20

IO215NB6F20

IO215PB6F20

IO216NB6F20

IO216PB6F20

IO217NB6F20

IO217PB6F20

IO218NB6F20

AA3

AA2

AB2

AA13

AD11

AE11

AG11

AF11

AB11

AC11

AF10

AG10

AD10

AE10

Y12

AA9

AD6

AE6

AB6

AC6

AF5

AG5

AA6

AA7

AA1

AA12

AB10

AC10

AF9

AA8

IO193NB6F18

IO193PB6F18

IO194NB6F18

IO194PB6F18

IO195NB6F18

IO195PB6F18

IO196NB6F18

IO196PB6F18

IO197NB6F18

IO197PB6F18

IO198NB6F18

IO198PB6F18

IO199NB6F18

IO199PB6F18

AG9

AD9

AB5

AC5

AC2

AC3

AC4

AD4

AE9

Y11

AA11

AF8

AG8

AD8

AE8

AB9

AB3

AB4

AC9

Y10

AA10

Revision 18

3-5

Package Pin Assignments

BG729

AX1000 Function

IO218PB6F20

IO219NB6F20

IO219PB6F20

IO220NB6F20

IO220PB6F20

IO221NB6F20

IO221PB6F20

IO222NB6F20

IO222PB6F20

IO223NB6F20

IO223PB6F20

IO224NB6F20

IO224PB6F20

Bank 7

Number

AX1000 Function

IO236PB7F22

IO237NB7F22

IO237PB7F22

IO238NB7F22

IO238PB7F22

IO239NB7F22

IO239PB7F22

IO240NB7F22

IO240PB7F22

IO241NB7F22

IO241PB7F22

IO242NB7F22

IO242PB7F22

IO243NB7F22

IO243PB7F22

IO244NB7F22

IO244PB7F22

IO245NB7F22

IO245PB7F22

IO246NB7F22

IO246PB7F22

IO247NB7F23

IO247PB7F23

IO248NB7F23

IO248PB7F23

IO249NB7F23

IO249PB7F23

IO250NB7F23

IO250PB7F23

IO251NB7F23

IO251PB7F23

IO252NB7F23

IO252PB7F23

IO253NB7F23

IO253PB7F23

IO254NB7F23

IO254PB7F23

Number

AX1000 Function

IO255NB7F23

IO255PB7F23

IO256NB7F23

IO256PB7F23

IO257NB7F23

IO257PB7F23

Number

Dedicated I/O

GND

A25

A26

A27

AC24

AE1

AE2

AE25

AE26

AE27

AE3

AE5

AF1

AF2

AF25

AF26

AF27

AF3

AG1

AG2

AG25

AG26

AG27

AG3

IO225NB7F21

IO225PB7F21

IO226NB7F21

IO226PB7F21

IO227NB7F21

IO227PB7F21

IO228NB7F21

IO228PB7F21

IO229NB7F21

IO229PB7F21

IO230NB7F21

IO230PB7F21

IO231NB7F21

IO231PB7F21

IO232NB7F21

IO232PB7F21

IO233NB7F21

IO233PB7F21

IO234NB7F21

IO234PB7F21

IO235NB7F21

IO235PB7F21

IO236NB7F22

B25

B26

3-6

Revision 18

Axcelerator Family FPGAs

BG729

AX1000 Function

GND

Number

AX1000 Function

GND

GND/LP

Number

AX1000 Function

Number

B27

R11

R12

R13

R14

R15

R16

R17

T11

T12

T13

T14

T15

T16

T17

U11

U12

U13

U14

U15

U16

U17

VCCA

K11

K17

K18

L10

VCCA

C25

C26

C27

VCCA

L18

VCCA

U10

U18

V10

V11

VCCA

E27

L11

L12

L13

L14

L15

L16

L17

M11

M12

M13

M14

M15

M16

M17

N11

N12

N13

N14

N15

N16

N17

P11

P12

P13

P14

P15

P16

P17

VCCA

V17

V18

A13

J13

VCCA

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

VCCPLH

VCCDA

VCCIB0

B15

C15

AG14

AF14

AB13

AG13

A11

AB12

AC12

AC25

AD16

AD17

E16

PRA

J14

D14

V14

AB14

PRB

PRC

PRD

TCK

E24

F12

TDI

TDO

F16

TMS

TRST

VCCA

K14

P10

P18

W14

AA21

AD5

G22

K10

Revision 18

3-7

Package Pin Assignments

BG729

AX1000 Function

VCCIB0

VCCIB1

VCCIB2

VCCIB3

VCCIB4

Number

AX1000 Function

VCCIB4

Number

W17

W18

AE4

AF4

AG4

V12

V13

W10

W11

W12

AD1

AD2

AD3

R10

T10

VCCIB4

J10

VCCIB5

J11

VCCIB5

J12

VCCIB5

K12

K13

A24

B24

C24

J16

VCCIB5

VCCIB6

J17

VCCIB6

J18

VCCIB6

K15

K16

D25

D26

D27

K19

L19

VCCIB6

VCCIB7

M18

M19

N18

AD25

AD26

AD27

R18

T18

T19

U19

V19

AE24

AF24

AG24

V15

V16

W16

VCCIB7

M10

VCCIB7

N10

B13

A14

A15

J15

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

AG15

W15

AC14

W13

D24

3-8

Revision 18

Axcelerator Family FPGAs

FG256

A1 Ball Pad Corner

16 15 14 13 12 11 10

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.microsemi.com/soc/products/rescenter/package/index.html.

Revision 18

3-9

Package Pin Assignments

FG256-Pin FBGA

AX125 Function

Bank 0

Number

AX125 Function

IO20NB2F2

IO20PB2F2

IO21NB2F2

IO21PB2F2

IO22NB2F2

IO22PB2F2

IO23NB2F2

IO23PB2F2

IO25NB2F2

IO25PB2F2

IO26NB2F2

IO26PB2F2

IO27NB2F2

IO27PB2F2

IO28NB2F2

IO28PB2F2

IO29NB2F2

IO29PB2F2

Bank 3

Number

AX125 Function

IO41PB3F3

Number

F15

L14

IO01NB0F0

E15

C16

B16

H13

G13

E16

D16

H15

G15

H14

G14

G16

F16

Bank 4

IO01PB0F0

IO42NB4F4

N12

N13

T14

R14

T15

R12

R13

P11

P12

T11

T12

T13

IO03NB0F0

IO42PB4F4

IO03PB0F0

IO43NB4F4

IO04NB0F0

IO43PB4F4

IO04PB0F0

IO44PB4F4

IO06NB0F0

IO45NB4F4

IO06PB0F0

IO45PB4F4

IO07NB0F0/HCLKAN

IO07PB0F0/HCLKAP

IO08NB0F0/HCLKBN

IO08PB0F0/HCLKBP

Bank 1

IO46NB4F4

IO46PB4F4

IO47PB4F4

IO48NB4F4

IO48PB4F4

IO09NB1F1/HCLKCN

IO09PB1F1/HCLKCP

IO10NB1F1/HCLKDN

IO10PB1F1/HCLKDP

IO12NB1F1

C10

K15

K16

J16

IO49NB4F4/CLKEN

IO49PB4F4/CLKEP

IO50NB4F4/CLKFN

IO50PB4F4/CLKFP

Bank 5

R10

B11

B10

A13

A12

B13

B12

C12

C11

A15

B14

C15

C14

D13

D12

H16

IO12PB1F1

IO30NB3F3

IO30PB3F3

IO31NB3F3

IO31PB3F3

IO33NB3F3

IO33PB3F3

IO35NB3F3

IO35PB3F3

IO36PB3F3

IO37NB3F3

IO37PB3F3

IO39NB3F3

IO39PB3F3

IO40NB3F3

IO40PB3F3

IO41NB3F3

K13

J13

IO51NB5F5/CLKGN

IO51PB5F5/CLKGP

IO52NB5F5/CLKHN

IO52PB5F5/CLKHP

IO54NB5F5

IO13NB1F1

IO13PB1F1

K14

J14

IO14NB1F1

IO14PB1F1

L15

L16

P16

N16

M16

P15

R16

N15

M15

M13

L13

M14

IO15NB1F1

IO54PB5F5

IO15PB1F1

IO55NB5F5

IO16NB1F1

IO55PB5F5

IO16PB1F1

IO56NB5F5

IO17NB1F1

IO56PB5F5

IO17PB1F1

IO57NB5F5

Bank 2

IO57PB5F5

IO18NB2F2

F13

E13

F14

E14

IO58NB5F5

IO18PB2F2

IO58PB5F5

IO19NB2F2

IO59NB5F5

IO19PB2F2

IO59PB5F5

3-10

Revision 18

Axcelerator Family FPGAs

FG256-Pin FBGA

AX125 Function

Bank 6

Number

AX125 Function

IO81NB7F7

IO81PB7F7

IO82NB7F7

IO82PB7F7

IO83NB7F7

IO83PB7F7

Number

AX125 Function

Number

M12

P13

GND

GND/LP

IO60NB6F6

IO60PB6F6

IO61NB6F6

IO61PB6F6

IO63NB6F6

IO63PB6F6

IO64NB6F6

IO64PB6F6

IO65NB6F6

IO65PB6F6

IO67NB6F6

IO67PB6F6

IO69NB6F6

IO69PB6F6

IO70NB6F6

IO70PB6F6

IO71NB6F6

IO71PB6F6

Bank 7

R15

Dedicated I/O

VCCDA

GND

T16

A16

B15

A11

R11

D15

E12

PRA

PRB

PRC

F11

PRD

TCK

G10

H10

TDI

TDO

TMS

IO72NB7F7

IO72PB7F7

IO73NB7F7

IO73PB7F7

IO74NB7F7

IO74PB7F7

IO75NB7F7

IO75PB7F7

IO76NB7F7

IO77NB7F7

IO77PB7F7

IO78NB7F7

IO78PB7F7

IO79NB7F7

IO79PB7F7

TRST

VCCA

D14

F10

J10

G11

K10

H11

J11

L11

K11

Revision 18

3-11

Package Pin Assignments

FG256-Pin FBGA

AX125 Function

VCCA

Number

L10

AX125 Function

VCCIB4

Number

M11

VCCA

VCCIB4

VCCA

VCCIB5

VCCA

VCCIB5

VCCA

VCCIB5

VCCA

P14

VCCIB6

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

VCCPLH

VCCDA

V_CCDA

VCCIB6

A10

D10

P10

N11

VCCIB7

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

D11

T10

N10

C13

VCCDA

VCCIB0

VCCIB1

VCCIB2

VCCIB3

VCCIB4

J15

N14

A14

E10

E11

F12

G12

H12

J12

K12

L12

M10

3-12

Revision 18

Axcelerator Family FPGAs

FG256

AX250 Function

Bank 0

Number

AX250 Function

IO32NB2F2

IO32PB2F2

IO33NB2F2

IO33PB2F2

IO35NB2F2

IO35PB2F2

IO36NB2F2

IO36PB2F2

IO38NB2F2

IO38PB2F2

IO39NB2F2

IO39PB2F2

IO40NB2F2

IO40PB2F2

IO43NB2F2

IO43PB2F2

IO44NB2F2

IO44PB2F2

Bank 3

Number

AX250 Function

IO61PB3F3

Bank 4

Number

C16

B16

F15

E15

H13

G13

E16

D16

H15

G15

H14

G14

G16

F16

K15

K16

J16

L14

IO01NB0F0

IO01PB0F0

IO62NB4F4

IO62PB4F4

N12

N13

T14

R14

T15

R12

R13

P11

P12

T11

T12

T13

IO03NB0F0

IO03PB0F0

IO63NB4F4

IO05NB0F0

IO63PB4F4

IO05PB0F0

IO66PB4F4

IO07NB0F0

IO67NB4F4

IO07PB0F0

IO67PB4F4

IO12NB0F0/HCLKAN

IO12PB0F0/HCLKAP

IO13NB0F0/HCLKBN

IO13PB0F0/HCLKBP

Bank 1

IO69NB4F4

IO69PB4F4

IO70PB4F4

IO73NB4F4

IO73PB4F4

IO14NB1F1/HCLKCN

IO14PB1F1/HCLKCP

IO15NB1F1/HCLKDN

IO15PB1F1/HCLKDP

IO17NB1F1

C10

IO74NB4F4/CLKEN

IO74PB4F4/CLKEP

IO75NB4F4/CLKFN

IO75PB4F4/CLKFP

Bank 5

R10

B11

B10

A13

A12

B13

B12

C12

C11

A15

B14

C15

C14

D13

D12

H16

IO17PB1F1

IO45NB3F3

IO45PB3F3

IO46NB3F3

IO46PB3F3

IO52NB3F3

IO52PB3F3

IO54NB3F3

IO54PB3F3

IO55PB3F3

IO56NB3F3

IO56PB3F3

IO58NB3F3

IO58PB3F3

IO59NB3F3

IO59PB3F3

IO61NB3F3

K13

J13

IO76NB5F5/CLKGN

IO76PB5F5/CLKGP

IO77NB5F5/CLKHN

IO77PB5F5/CLKHP

IO79NB5F5

IO19NB1F1

IO19PB1F1

K14

J14

IO21NB1F1

IO21PB1F1

L15

L16

P16

N16

M16

P15

R16

N15

M15

M13

L13

M14

IO23NB1F1

IO79PB5F5

IO23PB1F1

IO81NB5F5

IO26NB1F1

IO81PB5F5

IO26PB1F1

IO83NB5F5

IO27NB1F1

IO83PB5F5

IO27PB1F1

IO85NB5F5

Bank 2

IO85PB5F5

IO29NB2F2

F13

E13

F14

E14

IO88NB5F5

IO29PB2F2

IO88PB5F5

IO30NB2F2

IO89NB5F5

IO30PB2F2

IO89PB5F5

Revision 18

3-13

Package Pin Assignments

FG256

AX250 Function

Bank 6

Number

AX250 Function

IO117NB7F7

IO117PB7F7

IO118NB7F7

IO118PB7F7

IO119NB7F7

IO119PB7F7

Number

AX250 Function

GND

Number

M12

P13

IO91NB6F6

IO91PB6F6

IO92NB6F6

IO92PB6F6

IO94NB6F6

IO94PB6F6

IO97NB6F6

IO97PB6F6

IO98NB6F6

IO98PB6F6

IO100NB6F6

IO100PB6F6

IO102NB6F6

IO102PB6F6

IO103NB6F6

IO103PB6F6

IO104NB6F6

IO104PB6F6

Bank 7

GND

R15

GND

Dedicated I/O

GND

VCCDA

GND

T16

GND/LP

PRA

A16

B15

PRB

PRC

D15

E12

PRD

TCK

D14

F10

TDI

F11

TDO

TMS

G10

H10

TRST

VCCA

IO107NB7F7

IO107PB7F7

IO108NB7F7

IO108PB7F7

IO111NB7F7

IO111PB7F7

IO112NB7F7

IO112PB7F7

IO113NB7F7

IO114NB7F7

IO114PB7F7

IO115NB7F7

IO115PB7F7

IO116NB7F7

IO116PB7F7

G11

H11

J11

J10

K10

K11

L10

L11

3-14

Revision 18

Axcelerator Family FPGAs

FG256

AX250 Function

VCCA

Number

AX250 Function

VCCIB4

Number

M11

VCCA

VCCIB4

VCCA

P14

VCCIB5

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

VCCPLH

VCCDA

VCCIB0

VCCIB1

VCCIB2

VCCIB3

VCCIB4

VCCIB5

A10

D10

P10

N11

VCCIB6

VCCIB7

A11

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

C13

D11

T10

N10

A14

J15

N14

R11

E10

E11

F12

G12

H12

J12

K12

L12

M10

Revision 18

3-15

Package Pin Assignments

FG324

A1 Ball Pad Corner

18 17 16 15 14 13 12 11 10

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.microsemi.com/soc/products/rescenter/package/index.html.

3-16

Revision 18

Axcelerator Family FPGAs

FG324

AX125 Function

FG324

Number

AX125 Function

Bank 0

IO00NB0F0

AX125 Function

Number

R18

P18

N15

M15

M16

M17

P16

N16

R17

P17

N14

M14

U18

T18

IO16PB1F1

IO17NB1F1

IO17PB1F1

C15

E14

E13

IO33NB3F3

IO33PB3F3

IO34NB3F3

IO34PB3F3

IO35NB3F3

IO35PB3F3

IO36NB3F3

IO36PB3F3

IO37NB3F3

IO37PB3F3

IO38NB3F3

IO38PB3F3

IO39NB3F3

IO39PB3F3

IO40NB3F3

IO40PB3F3

IO41NB3F3

IO41PB3F3

B10

IO00PB0F0

IO01NB0F0

Bank 2

IO01PB0F0

IO18NB2F2

IO18PB2F2

IO19NB2F2

IO19PB2F2

IO20NB2F2

IO20PB2F2

IO21NB2F2

IO21PB2F2

IO22NB2F2

IO22PB2F2

IO23NB2F2

IO23PB2F2

IO24NB2F2

IO24PB2F2

IO25NB2F2

IO25PB2F2

IO26NB2F2

IO26PB2F2

IO27NB2F2

IO27PB2F2

IO28NB2F2

IO28PB2F2

IO29NB2F2

IO29PB2F2

G14

F14

D16

D15

C18

B18

D17

C17

F17

E17

G16

F16

E18

D18

G18

F18

H17

G17

J16

IO02NB0F0

IO02PB0F0

IO03NB0F0

IO03PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

R16

T17

IO07NB0F0/HCLKAN

IO07PB0F0/HCLKAP

IO08NB0F0/HCLKBN

IO08PB0F0/HCLKBP

Bank 1

P13

P14

Bank 4

IO42NB4F4

IO42PB4F4

T13

T14

U15

T15

U13

U14

V15

V16

V13

V14

V12

U12

V10

V11

T10

T11

IO09NB1F1/HCLKCN

IO09PB1F1/HCLKCP

IO10NB1F1/HCLKDN

IO10PB1F1/HCLKDP

IO11NB1F1

D11

D10

C12

C11

A15

A14

B14

B13

A17

A16

D13

D12

C14

C13

B16

IO43NB4F4

IO43PB4F4

H16

J18

IO44NB4F4

IO44PB4F4

IO11PB1F1

H18

K17

J17

IO45NB4F4

IO12NB1F1

IO45PB4F4

IO12PB1F1

IO46NB4F4

IO13NB1F1

Bank 3

IO46PB4F4

IO13PB1F1

IO30NB3F3

IO30PB3F3

IO31NB3F3

IO31PB3F3

IO32NB3F3

IO32PB3F3

N18

M18

L18

K18

L16

L17

IO47NB4F4

IO14NB1F1

IO47PB4F4

IO14PB1F1

IO48NB4F4

IO15NB1F1

IO48PB4F4

IO15PB1F1

IO49NB4F4/CLKEN

IO49PB4F4/CLKEP

IO16NB1F1

Revision 18

3-17

Package Pin Assignments

FG324

AX125 Function

FG324

Number

AX125 Function

IO50NB4F4/CLKFN

IO50PB4F4/CLKFP

Bank 5

AX125 Function

IO83PB7F7

Dedicated I/O

IO66PB6F6

IO67NB6F6

IO67PB6F6

IO68NB6F6

IO68PB6F6

IO69NB6F6

IO69PB6F6

IO70NB6F6

IO70PB6F6

IO71NB6F6

IO71PB6F6

U10

VCCDA

GND

IO51NB5F5/CLKGN

IO51PB5F5/CLKGP

IO52NB5F5/CLKHN

IO52PB5F5/CLKHP

IO53NB5F5

A18

B17

C16

IO53PB5F5

IO54NB5F5

IO54PB5F5

E16

F13

IO55NB5F5

IO55PB5F5

Bank 7

IO72NB7F7

IO72PB7F7

IO73NB7F7

IO73PB7F7

IO74NB7F7

IO74PB7F7

IO75NB7F7

IO75PB7F7

IO76NB7F7

IO76PB7F7

IO77NB7F7

IO77PB7F7

IO78NB7F7

IO78PB7F7

IO79NB7F7

IO79PB7F7

IO80NB7F7

IO80PB7F7

IO81NB7F7

IO81PB7F7

IO82NB7F7

IO82PB7F7

IO83NB7F7

G12

IO56NB5F5

IO56PB5F5

H10

H11

IO57NB5F5

IO57PB5F5

IO58NB5F5

IO58PB5F5

J10

J11

IO59NB5F5

IO59PB5F5

Bank 6

IO60NB6F6

IO60PB6F6

K10

K11

IO61NB6F6

IO61PB6F6

IO62NB6F6

L10

L11

IO62PB6F6

IO63NB6F6

IO63PB6F6

IO64NB6F6

M12

N13

IO64PB6F6

IO65NB6F6

IO65PB6F6

IO66NB6F6

R14

3-18

Revision 18

Axcelerator Family FPGAs

FG324

AX125 Function

FG324

AX125 Function

FG324

Number

AX125 Function

Number

GND

GND/LP

T16

VCCA

R12

R13

VCCA

U17

VCCA

R15

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

VCCPLH

VCCDA

VCCIB0

VCCIB1

VCCIB2

VCCIB3

VCCIB4

V18

T12

B11

E11

R11

P12

A10

A11

A12

A13

U16

V17

PRA

PRB

PRC

PRD

TCK

P10

R10

D14

E10

B12

F15

TDI

TDO

TMS

TRST

VCCA

K16

P15

G15

H14

H15

E15

G10

G11

J14

J15

F10

F11

F12

G13

H13

J13

K13

L13

M13

N10

N11

N12

H12

K14

K15

J12

L14

L15

K12

L12

N17

M10

M11

Revision 18

3-19

Package Pin Assignments

FG324

AX125 Function

VCCIB5

Number

VCCIB5

VCCIB6

VCCIB7

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

C10

E12

U11

P11

B15

3-20

Revision 18

Axcelerator Family FPGAs

FG484

A1 Ball Pad Corner

22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.microsemi.com/soc/products/rescenter/package/index.html.

Revision 18

3-21

Package Pin Assignments

FG484

AX250 Function

Bank 0

FG484

Pin Number AX250 Function

FG484

Pin Number AX250 Function

IO34PB2F2

Pin Number

D22

J18

IO17NB1F1

IO17PB1F1

IO18NB1F1

IO18PB1F1

IO19NB1F1

IO19PB1F1

IO20NB1F1

IO20PB1F1

IO21NB1F1

IO21PB1F1

IO22NB1F1

IO22PB1F1

IO23NB1F1

IO23PB1F1

IO24NB1F1

IO24PB1F1

IO25NB1F1

IO25PB1F1

IO26NB1F1

IO26PB1F1

IO27NB1F1

IO27PB1F1

B14

B13

A14

A13

A16

A15

B16

B15

C17

C16

F15

F14

D16

D15

E16

E15

F18

F17

D18

E17

G16

G15

IO00NB0F0

IO35NB2F2

IO35PB2F2

IO36NB2F2

IO36PB2F2

IO37NB2F2

IO37PB2F2

IO38NB2F2

IO38PB2F2

IO39NB2F2

IO39PB2F2

IO40NB2F2

IO40PB2F2

IO41NB2F2

IO41PB2F2

IO42NB2F2

IO42PB2F2

IO43NB2F2

IO43PB2F2

IO44NB2F2

IO44PB2F2

IO00PB0F0

H18

G21

F21

IO01NB0F0

IO01PB0F0

IO02NB0F0

K19

J19

IO02PB0F0

IO03NB0F0

J20

IO03PB0F0

H20

L16

IO04NB0F0

IO04PB0F0

K16

J21

IO05NB0F0

IO05PB0F0

H21

L17

IO06NB0F0

IO06PB0F0

K17

J22

IO07NB0F0

IO07PB0F0

H22

L18

IO08NB0F0

IO08PB0F0

K18

L20

IO09NB0F0

IO09PB0F0

K20

IO10NB0F0

Bank 3

IO10PB0F0

Bank 2

IO45NB3F3

IO45PB3F3

IO46NB3F3

IO46PB3F3

IO47NB3F3

IO47PB3F3

IO48NB3F3

IO48PB3F3

IO49NB3F3

IO49PB3F3

IO50NB3F3

IO50PB3F3

IO51NB3F3

IO51PB3F3

M19

L19

IO11NB0F0

B10

A10

E11

E10

D12

D11

IO28NB2F2

IO28PB2F2

IO29NB2F2

IO29PB2F2

IO30NB2F2

IO30PB2F2

IO31NB2F2

IO31PB2F2

IO32NB2F2

IO32PB2F2

IO33NB2F2

IO33PB2F2

IO34NB2F2

F19

E19

J16

IO11PB0F0

M21

L21

IO12NB0F0/HCLKAN

IO12PB0F0/HCLKAP

IO13NB0F0/HCLKBN

IO13PB0F0/HCLKBP

Bank 1

H16

E20

D20

J17

N17

M17

N18

N19

N16

M16

N20

M20

P21

N21

IO14NB1F1/HCLKCN

IO14PB1F1/HCLKCP

IO15NB1F1/HCLKDN

IO15PB1F1/HCLKDP

IO16NB1F1

F13

F12

E14

E13

C13

C12

H17

G20

F20

H19

G19

E22

IO16PB1F1

3-22

Revision 18

Axcelerator Family FPGAs

FG484

AX250 Function

FG484

Pin Number AX250 Function

IO69PB4F4

FG484

Pin Number AX250 Function

Pin Number

IO52NB3F3

IO52PB3F3

IO53NB3F3

IO53PB3F3

IO54NB3F3

IO54PB3F3

IO55NB3F3

IO55PB3F3

IO56NB3F3

IO56PB3F3

IO57NB3F3

IO57PB3F3

IO58NB3F3

IO58PB3F3

IO59NB3F3

IO59PB3F3

IO60NB3F3

IO60PB3F3

IO61NB3F3

IO61PB3F3

P18

P19

R20

P20

T21

R21

R17

P17

U20

T20

T18

R18

U19

T19

R16

P16

W20

V20

U18

V19

AA17

AB14

AB15

Y14

IO87NB5F5

IO87PB5F5

IO88NB5F5

IO88PB5F5

IO89NB5F5

IO89PB5F5

IO70NB4F4

IO70PB4F4

IO71NB4F4

IO71PB4F4

W14

AA14

AA15

AA13

AB13

V12

IO72NB4F4

IO72PB4F4

Bank 6

IO73NB4F4

IO90NB6F6

IO90PB6F6

IO91NB6F6

IO91PB6F6

IO92NB6F6

IO92PB6F6

IO93NB6F6

IO93PB6F6

IO94NB6F6

IO94PB6F6

IO95NB6F6

IO95PB6F6

IO96NB6F6

IO96PB6F6

IO97NB6F6

IO97PB6F6

IO98NB6F6

IO98PB6F6

IO99NB6F6

IO99PB6F6

IO100NB6F6

IO100PB6F6

IO101NB6F6

IO101PB6F6

IO102NB6F6

IO102PB6F6

IO103NB6F6

IO103PB6F6

IO104NB6F6

IO73PB4F4

IO74NB4F4/CLKEN

IO74PB4F4/CLKEP

IO75NB4F4/CLKFN

IO75PB4F4/CLKFP

Bank 5

V13

W11

W12

IO76NB5F5/CLKGN

IO76PB5F5/CLKGP

IO77NB5F5/CLKHN

IO77PB5F5/CLKHP

IO78NB5F5

U10

U11

V10

AA9

AA10

AB9

AB10

AA7

AA8

IO78PB5F5

Bank 4

IO79NB5F5

IO62NB4F4

IO62PB4F4

IO63NB4F4

IO63PB4F4

IO64NB4F4

IO64PB4F4

IO65NB4F4

IO65PB4F4

IO66NB4F4

IO66PB4F4

IO67NB4F4

IO67PB4F4

IO68NB4F4

IO68PB4F4

IO69NB4F4

T15

T16

IO79PB5F5

IO80NB5F5

W17

V17

IO80PB5F5

IO81NB5F5

V15

IO81PB5F5

V16

IO82NB5F5

AB5

AB6

AA5

AA6

Y19

IO82PB5F5

W18

AB18

AB19

W15

W16

U14

U15

AA16

IO83NB5F5

IO83PB5F5

IO84NB5F5

IO84PB5F5

IO85NB5F5

IO85PB5F5

IO86NB5F5

IO86PB5F5

Revision 18

3-23

Package Pin Assignments

FG484

AX250 Function

IO104PB6F6

IO105NB6F6

IO105PB6F6

IO106NB6F6

IO106PB6F6

Bank 7

FG484

Pin Number AX250 Function

FG484

Pin Number AX250 Function

Pin Number

IO122NB7F7

GND

IO122PB7F7

IO123NB7F7

IO123PB7F7

K10

K11

K12

K13

Dedicated I/O

VCCDA

GND

IO107NB7F7

IO107PB7F7

IO108NB7F7

IO108PB7F7

IO109NB7F7

IO109PB7F7

IO110NB7F7

IO110PB7F7

IO111NB7F7

IO111PB7F7

IO112NB7F7

IO112PB7F7

IO113NB7F7

IO113PB7F7

IO114NB7F7

IO114PB7F7

IO115NB7F7

IO115PB7F7

IO116NB7F7

IO116PB7F7

IO117NB7F7

IO117PB7F7

IO118NB7F7

IO118PB7F7

IO119NB7F7

IO119PB7F7

IO120NB7F7

IO120PB7F7

IO121NB7F7

IO121PB7F7

L10

L11

A11

A12

L12

L13

L22

A21

A22

AA1

AA2

AA21

AA22

AB1

AB11

AB12

AB2

AB21

AB22

M10

M11

M12

M13

M22

N10

N11

N12

N13

P14

R15

B21

B22

C20

U16

V18

D19

W19

E18

Y20

G18

H15

GND/LP

A17

A18

J14

3-24

Revision 18

Axcelerator Family FPGAs

FG484

AX250 Function

FG484

Pin Number AX250 Function

FG484

Pin Number AX250 Function

Pin Number

G11

F11

T12

U12

A19

G22

PRA

PRB

PRC

AA11

AA12

AA18

AA19

AA4

AB16

AB17

AB4

AB7

AB8

B11

B12

B17

B18

B19

PRD

K21

K22

N22

P22

R19

R22

TCK

TDI

TDO

TMS

TRST

VCCA

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

G17

J10

J11

T22

J12

J13

U21

U22

K14

L14

V21

V22

M14

C10

C11

C14

C15

C18

C19

W21

W22

Y10

Y11

Y12

Y13

Y15

Y16

Y17

Y18

N14

P10

P11

P12

P13

D21

U17

F10

D13

G13

U13

T14

W10

E21

F22

Revision 18

3-25

Package Pin Assignments

FG484

AX250 Function

VCCPLH

VCCDA

FG484

Pin Number AX250 Function

Pin Number

R14

AA3

AB3

R10

R11

T10

D14

VCCIB4

VCCIB5

VCCDA

F16

G12

VCCIB5

VCCDA

VCCIB5

VCCDA

VCCIB5

VCCDA

M18

T11

T17

VCCIB6

VCCDA

VCCIB6

VCCDA

VCCIB6

VCCDA

VCCIB6

VCCDA

V14

VCCIB6

VCCDA

VCCIB7

VCCIB0

VCCIB1

VCCIB2

VCCIB3

VCCIB4

VCCIB7

H10

H11

VCCIB7

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

D10

G10

E12

G14

W13

T13

V11

A20

B20

H12

H13

H14

C21

C22

J15

K15

L15

M15

N15

P15

Y21

Y22

AA20

AB20

R12

R13

D17

3-26

Revision 18

Axcelerator Family FPGAs

FG484

AX500 Function

Bank 0

Number

AX500 Function

IO19NB0F1/HCLKAN

IO19PB0F1/HCLKAP

IO20NB0F1/HCLKBN

IO20PB0F1/HCLKBP

Bank 1

Number

AX500 Function

Number

E11

E10

D12

D11

IO37PB1F3

IO38NB1F3

IO38PB1F3

IO39NB1F3

IO39PB1F3

IO40NB1F3

IO40PB1F3

IO41NB1F3

IO41PB1F3

F17

IO00NB0F0

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO03NB0F0

IO03PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO07NB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO18NB0F1

IO18PB0F1

D18

E17

E21

D21

E20

IO21NB1F2/HCLKCN

IO21PB1F2/HCLKCP

IO22NB1F2/HCLKDN

IO22PB1F2/HCLKDP

IO24NB1F2

F13

F12

E14

E13

A14

A13

B14

B13

C15

A16

A15

B16

B15

D16

D15

A18

A17

F15

F14

C17

C16

E16

E15

B18

B17

B19

A19

C19

C18

F18

D20

G16

G15

Bank 2

IO24PB1F2

IO42NB2F4

IO42PB2F4

IO43NB2F4

IO43PB2F4

IO44NB2F4

IO44PB2F4

IO45NB2F4

IO45PB2F4

IO46NB2F4

IO46PB2F4

IO47NB2F4

IO47PB2F4

IO48NB2F4

IO48PB2F4

IO49NB2F4

IO49PB2F4

IO50NB2F4

IO50PB2F4

IO51NB2F4

IO51PB2F4

IO52NB2F5

IO52PB2F5

IO53NB2F5

IO53PB2F5

IO54NB2F5

F19

E19

J16

H16

E22

D22

H19

G19

G22

F22

J17

H17

G20

F20

J18

H18

G21

F21

K19

J19

J21

H21

J20

H20

J22

IO25NB1F2

IO25PB1F2

IO26NB1F2

IO27NB1F2

IO27PB1F2

IO28NB1F2

IO28PB1F2

IO29NB1F2

IO29PB1F2

IO30NB1F2

IO30PB1F2

IO31NB1F2

IO31PB1F2

IO32NB1F3

IO32PB1F3

IO33NB1F3

IO33PB1F3

IO34NB1F3

B10

A10

B12

B11

C13

C12

IO34PB1F3

IO35NB1F3

IO35PB1F3

IO36NB1F3

IO36PB1F3

IO37NB1F3

Revision 18

3-27

Package Pin Assignments

FG484

AX500 Function

IO54PB2F5

IO55NB2F5

IO55PB2F5

IO56NB2F5

IO56PB2F5

IO58NB2F5

IO58PB2F5

IO59NB2F5

IO59PB2F5

IO60NB2F5

IO60PB2F5

IO61NB2F5

IO61PB2F5

IO62NB2F5

IO62PB2F5

Bank 3

Number

AX500 Function

IO72PB3F6

IO73PB3F6

IO74NB3F7

IO74PB3F7

IO75NB3F7

IO75PB3F7

IO76NB3F7

IO76PB3F7

IO77NB3F7

IO77PB3F7

IO78NB3F7

IO78PB3F7

IO79NB3F7

IO79PB3F7

IO80NB3F7

IO80PB3F7

IO81NB3F7

IO81PB3F7

IO82NB3F7

IO82PB3F7

IO83NB3F7

IO83PB3F7

Bank 4

Number

AX500 Function

IO90NB4F8

Number

H22

L17

K17

K21

K22

L20

K20

L18

K18

M21

L21

L16

K16

M19

L19

P20

R19

V21

U21

V22

U22

U20

T20

R17

P17

W21

W22

T18

R18

W20

V20

U19

T19

U18

V19

R16

P16

Y17

Y18

IO90PB4F8

IO91NB4F8

V15

IO91PB4F8

V16

IO92PB4F8

AB17

Y15

IO93NB4F8

IO93PB4F8

Y16

IO94NB4F9

AA16

AA17

AB14

AB15

W15

W16

AA13

AB13

AA14

AA15

Y14

IO94PB4F9

IO95NB4F9

IO95PB4F9

IO96NB4F9

IO96PB4F9

IO97NB4F9

IO97PB4F9

IO98NB4F9

IO63NB3F6

IO63PB3F6

IO64NB3F6

IO64PB3F6

IO65NB3F6

IO65PB3F6

IO66NB3F6

IO66PB3F6

IO67NB3F6

IO67PB3F6

IO68NB3F6

IO68PB3F6

IO69NB3F6

IO69PB3F6

IO70NB3F6

IO70PB3F6

IO71NB3F6

IO71PB3F6

IO72NB3F6

N16

M16

P22

N22

N20

M20

P21

N21

N18

N19

T22

R22

N17

M17

T21

R21

P18

P19

R20

IO98PB4F9

IO100NB4F9

IO100PB4F9

W14

Y12

IO101NB4F9

IO101PB4F9

Y13

IO102NB4F9

AA11

AA12

V12

IO102PB4F9

IO84NB4F8

IO84PB4F8

IO85NB4F8

IO85PB4F8

IO86NB4F8

IO86PB4F8

IO87NB4F8

IO87PB4F8

IO88NB4F8

IO88PB4F8

IO89NB4F8

IO89PB4F8

AB18

AB19

T15

IO103NB4F9/CLKEN

IO103PB4F9/CLKEP

IO104NB4F9/CLKFN

IO104PB4F9/CLKFP

Bank 5

V13

W11

W12

T16

AA18

AA19

W17

V17

IO105NB5F10/CLKGN

IO105PB5F10/CLKGP

IO106NB5F10/CLKHN

IO106PB5F10/CLKHP

IO107NB5F10

IO107PB5F10

IO108NB5F10

U10

U11

Y19

V10

Y10

Y11

AA9

W18

U14

U15

3-28

Revision 18

Axcelerator Family FPGAs

FG484

AX500 Function

IO108PB5F10

IO110NB5F10

IO110PB5F10

IO111NB5F10

IO111PB5F10

IO112NB5F10

IO113NB5F10

IO113PB5F10

IO114NB5F11

IO114PB5F11

IO115NB5F11

IO115PB5F11

IO116NB5F11

IO116PB5F11

IO117NB5F11

IO117PB5F11

IO118NB5F11

IO118PB5F11

IO119NB5F11

IO119PB5F11

IO120NB5F11

IO120PB5F11

IO121NB5F11

IO121PB5F11

IO122NB5F11

IO122PB5F11

IO123NB5F11

IO123PB5F11

IO124NB5F11

IO124PB5F11

IO125NB5F11

IO125PB5F11

Bank 6

Number

AX500 Function

IO127NB6F12

IO127PB6F12

IO128NB6F12

IO128PB6F12

IO129NB6F12

IO129PB6F12

IO130NB6F12

IO130PB6F12

IO131NB6F12

IO131PB6F12

IO132NB6F12

IO132PB6F12

IO133NB6F12

IO134NB6F12

IO134PB6F12

IO135NB6F12

IO135PB6F12

IO136NB6F13

IO136PB6F13

IO138NB6F13

IO138PB6F13

IO139NB6F13

IO139PB6F13

IO140NB6F13

IO140PB6F13

IO141NB6F13

IO141PB6F13

IO142NB6F13

IO142PB6F13

IO143NB6F13

IO143PB6F13

IO144NB6F13

IO144PB6F13

IO145NB6F13

IO145PB6F13

Number

AX500 Function

Number

AA10

AB9

AB10

IO146NB6F13

IO146PB6F13

Bank 7

IO147NB7F14

IO147PB7F14

IO148NB7F14

IO148PB7F14

IO149NB7F14

IO149PB7F14

IO150NB7F14

IO150PB7F14

IO151NB7F14

IO151PB7F14

IO152NB7F14

IO152PB7F14

IO153NB7F14

IO153PB7F14

IO154NB7F14

IO154PB7F14

IO155NB7F14

IO155PB7F14

IO156NB7F14

IO156PB7F14

IO157NB7F14

IO157PB7F14

IO158NB7F15

IO158PB7F15

IO159NB7F15

IO159PB7F15

IO160NB7F15

IO160PB7F15

IO161NB7F15

IO161PB7F15

IO162NB7F15

IO162PB7F15

AB7

AA7

AA8

AB5

AB6

AA5

AA6

AA4

AB4

IO126NB6F12

IO126PB6F12

Revision 18

3-29

Package Pin Assignments

FG484

AX500 Function

IO163NB7F15

IO163PB7F15

IO164NB7F15

IO164PB7F15

IO165NB7F15

IO165PB7F15

IO166NB7F15

IO166PB7F15

IO167NB7F15

IO167PB7F15

Dedicated I/O

VCCDA

GND

Number

AX500 Function

GND

Number

AX500 Function

GND

Number

E18

W19

Y20

GND

G18

H15

GND

GND/LP

J14

AB8

AB16

C10

C11

C14

G11

F11

T12

U12

K10

K11

K12

K13

PRA

PRB

GND

A11

A12

L10

L11

L12

L13

L22

PRC

GND

PRD

GND

TCK

GND

A21

A22

AA1

AA2

AA21

AA22

AB1

AB11

AB12

AB2

AB21

AB22

TDI

GND

TDO

GND

TMS

GND

M10

M11

M12

M13

M22

N10

N11

N12

N13

P14

TRST

VCCA

GND

G17

J10

J11

J12

J13

GND

K14

GND

L14

GND

B21

B22

C20

R15

M14

GND

U16

N14

GND

D19

V18

P10

3-30

Revision 18

Axcelerator Family FPGAs

FG484

AX500 Function

VCCA

Number

AX500 Function

VCCIB2

VCCIB3

VCCIB4

VCCIB5

VCCIB6

VCCIB7

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

Number

AX500 Function

Number

P11

P12

P13

C22

J15

K15

L15

M15

N15

P15

Y21

Y22

AA20

AB20

R12

R13

R14

AA3

AB3

R10

R11

VCOMPLG

VCOMPLH

VPUMP

V11

VCCA

D17

VCCA

U17

F10

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

VCCPLH

VCCDA

VCCIB0

VCCIB1

VCCIB2

D13

G13

U13

T14

W10

T10

D14

F16

G12

M18

T11

T17

V14

H10

H11

A20

B20

H12

H13

H14

C21

D10

G10

E12

G14

W13

T13

Revision 18

3-31

Package Pin Assignments

FG484

AX1000 Function

Bank 0

Number

AX1000 Function

IO29NB0F2

Number

AX1000 Function

IO51PB1F4

IO52NB1F4

IO52PB1F4

IO57NB1F5

IO57PB1F5

IO60NB1F5

IO60PB1F5

IO61NB1F5

IO61PB1F5

IO63NB1F5

IO63PB1F5

Bank 2

Number

B12

B11

E11

E10

D12

D11

D22

E16

E15

E21

D21

G16

G15

D18

E17

E20

D20

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17NB0F1

IO17PB0F1

IO18NB0F1

IO18PB0F1

IO19NB0F1

IO19PB0F1

IO20NB0F1

IO20PB0F1

IO21NB0F1

IO21PB0F1

IO22NB0F2

IO22PB0F2

IO23NB0F2

IO23PB0F2

IO26NB0F2

IO26PB0F2

B10

A10

A14

A13

IO29PB0F2

IO30NB0F2/HCLKAN

IO30PB0F2/HCLKAP

IO31NB0F2/HCLKBN

IO31PB0F2/HCLKBP

Bank 1

IO32NB1F3/HCLKCN

IO32PB1F3/HCLKCP

IO33NB1F3/HCLKDN

IO33PB1F3/HCLKDP

IO34NB1F3

F13

F12

E14

E13

C13

C12

B14

B13

A16

A15

C15

A18

A17

B16

B15

B18

B17

B19

A19

C19

C18

F15

F14

D16

D15

C17

C16

E22

IO34PB1F3

IO64NB2F6

IO64PB2F6

IO67NB2F6

IO67PB2F6

IO68NB2F6

IO68PB2F6

IO70NB2F6

IO70PB2F6

IO74NB2F7

IO74PB2F7

IO75NB2F7

IO75PB2F7

IO79NB2F7

IO79PB2F7

IO80NB2F7

IO80PB2F7

IO84NB2F7

IO84PB2F7

IO85NB2F8

IO85PB2F8

IO86NB2F8

IO86PB2F8

IO87NB2F8

F18

F17

F19

E19

J16

H16

J17

H17

J18

H18

G20

F20

H19

G19

L16

K16

L17

K17

G21

F21

G22

F22

J20

IO37NB1F3

IO37PB1F3

IO38NB1F3

IO38PB1F3

IO40NB1F3

IO42NB1F4

IO42PB1F4

IO43NB1F4

IO43PB1F4

IO44NB1F4

IO44PB1F4

IO45NB1F4

IO45PB1F4

IO46NB1F4

IO46PB1F4

IO48NB1F4

IO48PB1F4

IO49NB1F4

IO49PB1F4

IO50NB1F4

IO50PB1F4

IO51NB1F4

3-32

Revision 18

Axcelerator Family FPGAs

FG484

AX1000 Function

IO87PB2F8

IO88NB2F8

IO88PB2F8

IO89NB2F8

IO89PB2F8

IO90NB2F8

IO90PB2F8

IO91NB2F8

IO91PB2F8

IO93NB2F8

IO93PB2F8

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

Bank 3

Number

AX1000 Function

IO106PB3F9

IO107NB3F10

IO107PB3F10

IO110NB3F10

IO110PB3F10

IO113NB3F10

IO113PB3F10

IO114NB3F10

IO114PB3F10

IO116PB3F10

IO117NB3F10

IO117PB3F10

IO118NB3F11

IO118PB3F11

IO121NB3F11

IO121PB3F11

IO124NB3F11

IO124PB3F11

IO127NB3F11

IO127PB3F11

Bank 4

Number

AX1000 Function

Number

H20

L18

K18

K19

J19

J21

H21

J22

H22

K21

K22

L20

K20

M21

L21

P17

T21

R21

V22

U22

V21

U21

P18

P19

R19

U20

T20

T18

R18

U19

T19

R16

P16

W21

W22

IO142PB4F13

IO143NB4F13

V20

W15

W16

AA18

AA19

U14

IO143PB4F13

IO144NB4F13

IO144PB4F13

IO145NB4F13

IO145PB4F13

U15

IO146NB4F13

Y15

IO146PB4F13

Y16

IO147NB4F13

AB18

AB19

Y14

IO147PB4F13

IO149NB4F13

IO149PB4F13

W14

AA16

AA17

AA14

AA15

AB14

AB15

AA13

AB13

Y12

IO150NB4F13

IO150PB4F13

IO152NB4F14

IO96NB3F9

IO96PB3F9

IO97NB3F9

IO97PB3F9

IO98NB3F9

IO98PB3F9

IO99NB3F9

IO99PB3F9

IO100NB3F9

IO100PB3F9

IO101NB3F9

IO101PB3F9

IO103NB3F9

IO103PB3F9

IO104NB3F9

IO104PB3F9

IO105NB3F9

IO105PB3F9

IO106NB3F9

N16

M16

M19

L19

IO152PB4F14

IO154NB4F14

IO154PB4F14

IO155NB4F14

P22

N22

N20

M20

N17

M17

P21

N21

R20

P20

N18

N19

T22

R22

R17

IO155PB4F14

IO129PB4F12

IO132NB4F12

IO132PB4F12

IO133NB4F12

IO133PB4F12

IO135NB4F12

IO135PB4F12

IO138NB4F12

IO138PB4F12

IO139NB4F13

IO139PB4F13

IO140NB4F13

IO140PB4F13

IO142NB4F13

AB17

Y19

W18

W17

V17

T15

T16

Y17

Y18

V15

V16

U18

V19

W20

IO158NB4F14

IO158PB4F14

Y13

IO159NB4F14/CLKEN

IO159PB4F14/CLKEP

IO160NB4F14/CLKFN

IO160PB4F14/CLKFP

Bank 5

V12

V13

W11

W12

IO161NB5F15/CLKGN

IO161PB5F15/CLKGP

IO162NB5F15/CLKHN

IO162PB5F15/CLKHP

IO163NB5F15

U10

U11

V10

Y10

Y11

AA11

IO163PB5F15

IO167NB5F15

Revision 18

3-33

Package Pin Assignments

FG484

AX1000 Function

IO167PB5F15

IO169NB5F15

IO169PB5F15

IO170NB5F15

IO170PB5F15

IO171NB5F16

IO171PB5F16

IO172NB5F16

IO172PB5F16

IO173NB5F16

IO173PB5F16

IO174NB5F16

IO174PB5F16

IO175NB5F16

IO175PB5F16

IO176NB5F16

IO176PB5F16

IO177NB5F16

IO177PB5F16

IO178NB5F16

IO178PB5F16

IO179NB5F16

IO179PB5F16

IO180NB5F16

IO180PB5F16

IO181NB5F17

IO181PB5F17

IO184NB5F17

IO187NB5F17

IO187PB5F17

IO188NB5F17

IO188PB5F17

IO192NB5F17

IO192PB5F17

Bank 6

Number

AX1000 Function

IO194NB6F18

IO194PB6F18

IO195NB6F18

IO195PB6F18

IO200NB6F18

IO200PB6F18

IO201NB6F18

IO201PB6F18

IO203NB6F19

IO204NB6F19

IO204PB6F19

IO205NB6F19

IO205PB6F19

IO208NB6F19

IO208PB6F19

IO209NB6F19

IO209PB6F19

IO212NB6F19

IO212PB6F19

IO214NB6F20

IO214PB6F20

IO215NB6F20

IO215PB6F20

IO216NB6F20

IO216PB6F20

IO217NB6F20

IO217PB6F20

IO219NB6F20

IO219PB6F20

IO220NB6F20

IO220PB6F20

IO221NB6F20

IO221PB6F20

IO222NB6F20

IO222PB6F20

Number

AX1000 Function

IO223NB6F20

IO223PB6F20

IO224NB6F20

IO224PB6F20

Bank 7

Number

AA12

AA9

AA10

AB9

AB10

IO225NB7F21

IO225PB7F21

IO226NB7F21

IO226PB7F21

IO228NB7F21

IO228PB7F21

IO229NB7F21

IO229PB7F21

IO230NB7F21

IO230PB7F21

IO231NB7F21

IO231PB7F21

IO232NB7F21

IO232PB7F21

IO233NB7F21

IO233PB7F21

IO234NB7F21

IO234PB7F21

IO235NB7F21

IO235PB7F21

IO236NB7F22

IO236PB7F22

IO237NB7F22

IO237PB7F22

IO241NB7F22

IO241PB7F22

IO242NB7F22

IO242PB7F22

IO243NB7F22

IO243PB7F22

AA7

AA8

AB5

AB6

AA5

AA6

AA4

AB4

AB7

3-34

Revision 18

Axcelerator Family FPGAs

FG484

AX1000 Function

IO246NB7F22

IO246PB7F22

IO250NB7F23

IO250PB7F23

IO253NB7F23

IO253PB7F23

IO254NB7F23

IO254PB7F23

IO257NB7F23

IO257PB7F23

Number

AX1000 Function

GND

Number

AX1000 Function

Number

E18

GND

W19

Y20

GND

G18

H15

GND

GND/LP

PRA

J14

G11

F11

T12

U12

PRB

K10

K11

K12

K13

PRC

PRD

Dedicated I/O

TCK

VCCDA

GND

TDI

TDO

A11

A12

L10

L11

L12

L13

L22

TMS

TRST

VCCA

G17

J10

J11

J12

J13

A21

A22

AA1

AA2

AA21

AA22

AB1

AB11

AB12

AB2

AB21

AB22

M10

M11

M12

M13

M22

N10

N11

N12

N13

P14

K14

L14

M14

N14

P10

P11

P12

P13

B21

B22

C20

R15

U16

D19

V18

U17

Revision 18

3-35

Package Pin Assignments

FG484

AX1000 Function

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

VCCPLH

VCCDA

VCCIB0

VCCIB1

VCCIB2

Number

AX1000 Function

VCCIB2

VCCIB3

VCCIB4

VCCIB5

VCCIB6

VCCIB7

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

Number

AX1000 Function

VCOMPLG

VCOMPLH

VPUMP

Number

F10

C22

J15

K15

L15

M15

N15

P15

Y21

Y22

AA20

AB20

R12

R13

R14

AA3

AB3

R10

R11

V11

D13

G13

U13

T14

W10

T10

AB16

AB8

C10

C11

C14

D14

D17

F16

G12

M18

T11

T17

V14

H10

H11

A20

B20

H12

H13

H14

C21

D10

G10

E12

G14

W13

T13

3-36

Revision 18

Axcelerator Family FPGAs

FG676

A1 Ball Pad Corner

7 6 2 1

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.microsemi.com/soc/products/rescenter/package/index.html.

Revision 18

3-37

Package Pin Assignments

FG676

AX500 Function

Bank 0

Number

AX500 Function

IO17NB0F1

Number

AX500 Function

IO34NB1F3

IO34PB1F3

IO35NB1F3

IO35PB1F3

IO36NB1F3

IO36PB1F3

IO37NB1F3

IO37PB1F3

IO38NB1F3

IO38PB1F3

IO39NB1F3

IO39PB1F3

IO40NB1F3

IO40PB1F3

IO41NB1F3

IO41PB1F3

Bank 2

Number

F12

G12

C12

C11

A12

B12

C13

B13

D20

C20

D21

C21

D22

C22

F19

E19

B23

A23

E21

E20

D23

C23

D25

C25

IO00NB0F0

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO03NB0F0

IO03PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO07NB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO09NB0F0

IO09PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17PB0F1

IO18NB0F1

IO18PB0F1

IO19NB0F1/HCLKAN

IO19PB0F1/HCLKAP

IO20NB0F1/HCLKBN

IO20PB0F1/HCLKBP

Bank 1

IO21NB1F2/HCLKCN

IO21PB1F2/HCLKCP

IO22NB1F2/HCLKDN

IO22PB1F2/HCLKDP

IO23NB1F2

C15

C14

A15

B15

F15

G15

B16

A16

A18

A17

D16

E16

F16

G16

C18

C17

B19

B18

D19

C19

F17

E17

B20

A20

B22

B21

IO23PB1F2

IO24NB1F2

IO24PB1F2

F10

IO25NB1F2

IO42NB2F4

IO42PB2F4

IO43NB2F4

IO43PB2F4

IO44NB2F4

IO44PB2F4

IO45NB2F4

IO45PB2F4

IO46NB2F4

IO46PB2F4

IO47NB2F4

IO47PB2F4

IO48NB2F4

IO48PB2F4

IO49NB2F4

IO49PB2F4

IO50NB2F4

IO50PB2F4

G24

G23

G26

F26

F25

E25

J21

J22

H25

G25

K23

J23

J24

H24

K21

K22

K25

J25

IO25PB1F2

IO26NB1F2

IO26PB1F2

IO27NB1F2

IO27PB1F2

D10

E10

IO28NB1F2

IO28PB1F2

IO29NB1F2

F11

G11

D11

E11

B10

C10

A10

IO29PB1F2

IO30NB1F2

IO30PB1F2

IO31NB1F2

IO31PB1F2

IO32NB1F3

IO32PB1F3

IO33NB1F3

IO33PB1F3

3-38

Revision 18

Axcelerator Family FPGAs

FG676

AX500 Function

IO51NB2F4

IO51PB2F4

IO52NB2F5

IO52PB2F5

IO53NB2F5

IO53PB2F5

IO54NB2F5

IO54PB2F5

IO55NB2F5

IO55PB2F5

IO56NB2F5

IO56PB2F5

IO57NB2F5

IO57PB2F5

IO58NB2F5

IO58PB2F5

IO59NB2F5

IO59PB2F5

IO60NB2F5

IO60PB2F5

IO61NB2F5

IO61PB2F5

IO62NB2F5

IO62PB2F5

Bank 3

Number

AX500 Function

IO68NB3F6

IO68PB3F6

IO69NB3F6

IO69PB3F6

IO70NB3F6

IO70PB3F6

IO71NB3F6

IO71PB3F6

IO72NB3F6

IO72PB3F6

IO73NB3F6

IO73PB3F6

IO74NB3F7

IO74PB3F7

IO75NB3F7

IO75PB3F7

IO76NB3F7

IO76PB3F7

IO77NB3F7

IO77PB3F7

IO78NB3F7

IO78PB3F7

IO79NB3F7

IO79PB3F7

IO80NB3F7

IO80PB3F7

IO81NB3F7

IO81PB3F7

IO82NB3F7

IO82PB3F7

IO83NB3F7

IO83PB3F7

Bank 4

Number

AX500 Function

Number

AE23

AE24

AC21

AC22

AF22

AF23

AD22

AD23

AC19

AC20

AE21

AE22

AA17

AA18

AD20

AD21

AF20

AF21

AE19

AE20

AC17

AC18

AD18

AD19

AA16

Y16

L20

L21

K26

J26

V26

U26

IO85NB4F8

IO85PB4F8

IO86NB4F8

IO86PB4F8

IO87NB4F8

IO87PB4F8

IO88NB4F8

IO88PB4F8

IO89NB4F8

IO89PB4F8

IO90NB4F8

IO90PB4F8

IO91NB4F8

IO91PB4F8

IO92NB4F8

IO92PB4F8

IO93NB4F8

IO93PB4F8

IO94NB4F9

IO94PB4F9

IO95NB4F9

IO95PB4F9

IO96NB4F9

IO96PB4F9

IO97NB4F9

IO97PB4F9

IO98NB4F9

IO98PB4F9

IO99NB4F9

IO99PB4F9

IO100NB4F9

IO100PB4F9

IO101NB4F9

IO101PB4F9

IO102NB4F9

V25

U25

L23

L22

L24

K24

M20

M21

L26

L25

M23

M22

M26

M25

N22

N23

N24

M24

N20

N21

P25

N25

Y25

W25

W24

V24

V23

U23

T21

T20

AA26

Y26

AA24

Y24

Y23

W23

V21

U21

AB25

AA25

AC26

AB26

AC24

AB24

AB23

AA23

AA22

Y22

IO63NB3F6

IO63PB3F6

IO64NB3F6

IO64PB3F6

IO65NB3F6

IO65PB3F6

IO66NB3F6

IO66PB3F6

IO67NB3F6

IO67PB3F6

T26

R26

R24

P24

P20

P21

T25

R25

T23

R23

AE17

AE18

AC16

AB16

AF17

AF18

AA15

Y15

AE26

AD26

IO84NB4F8

IO84PB4F8

AB21

AA21

AC15

Revision 18

3-39

Package Pin Assignments

FG676

AX500 Function

IO102PB4F9

Number

AX500 Function

IO119PB5F11

IO120NB5F11

IO120PB5F11

IO121NB5F11

IO121PB5F11

IO122NB5F11

IO122PB5F11

IO123NB5F11

IO123PB5F11

IO124NB5F11

IO124PB5F11

IO125NB5F11

IO125PB5F11

Bank 6

Number

AX500 Function

IO136PB6F13

IO137NB6F13

IO137PB6F13

IO138NB6F13

IO138PB6F13

IO139NB6F13

IO139PB6F13

IO140NB6F13

IO140PB6F13

IO141NB6F13

IO141PB6F13

IO142NB6F13

IO142PB6F13

IO143NB6F13

IO143PB6F13

IO144NB6F13

IO144PB6F13

IO145NB6F13

IO145PB6F13

IO146NB6F13

IO146PB6F13

Bank 7

Number

AB15

AE16

AF16

AE14

AE15

AE6

AE5

AF5

AF4

AE4

AC5

AC6

AD4

AD5

AB6

AB7

AE3

AF3

IO103NB4F9/CLKEN

IO103PB4F9/CLKEP

IO104NB4F9/CLKFN

IO104PB4F9/CLKFP

Bank 5

IO105NB5F10/CLKGN

IO105PB5F10/CLKGP

IO106NB5F10/CLKHN

IO106PB5F10/CLKHP

IO107NB5F10

IO107PB5F10

AE12

AE13

AE11

AF11

Y12

AA13

AC12

AB12

AC10

AC11

AF9

IO108NB5F10

IO108PB5F10

IO109NB5F10

IO109PB5F10

IO126NB6F12

IO126PB6F12

IO127NB6F12

IO127PB6F12

IO128NB6F12

IO128PB6F12

IO129NB6F12

IO129PB6F12

IO130NB6F12

IO130PB6F12

IO131NB6F12

IO131PB6F12

IO132NB6F12

IO132PB6F12

IO133NB6F12

IO133PB6F12

IO134NB6F12

IO134PB6F12

IO135NB6F12

IO135PB6F12

IO136NB6F13

AB3

AC3

AA2

AB2

AC2

AD2

IO110NB5F10

IO110PB5F10

AF10

Y11

IO111NB5F10

IO111PB5F10

AA12

AE9

IO112NB5F10

IO112PB5F10

AE10

AC9

AA1

IO113NB5F10

IO147NB7F14

IO147PB7F14

IO148NB7F14

IO148PB7F14

IO149NB7F14

IO149PB7F14

IO150NB7F14

IO150PB7F14

IO151NB7F14

IO151PB7F14

IO152NB7F14

IO152PB7F14

IO153NB7F14

IO113PB5F10

AD9

AA3

IO114NB5F11

AF6

IO114PB5F11

AF7

IO115NB5F11

AA10

AB10

AE7

IO115PB5F11

IO116NB5F11

IO116PB5F11

AE8

IO117NB5F11

AD7

IO117PB5F11

AD8

IO118NB5F11

AC7

IO118PB5F11

AC8

IO119NB5F11

AD6

3-40

Revision 18

Axcelerator Family FPGAs

FG676

AX500 Function

IO153PB7F14

IO154NB7F14

IO154PB7F14

IO155NB7F14

IO155PB7F14

IO156NB7F14

IO156PB7F14

IO157NB7F14

IO157PB7F14

IO158NB7F15

IO158PB7F15

IO159NB7F15

IO159PB7F15

IO160NB7F15

IO160PB7F15

IO161NB7F15

IO161PB7F15

IO162NB7F15

IO162PB7F15

IO163NB7F15

IO163PB7F15

IO164NB7F15

IO164PB7F15

IO165NB7F15

IO165PB7F15

IO166NB7F15

IO166PB7F15

IO167NB7F15

IO167PB7F15

Number

AX500 Function

GND

Number

AX500 Function

Number

AC23

AC4

AD24

AD3

AE2

AE25

AF1

AF13

AF14

AF19

AF26

AF8

GND

L11

L12

L13

L14

L15

L16

L17

M10

M11

M12

M13

M14

M15

M16

M17

B25

B26

C24

N10

N11

N12

N13

N14

N15

N16

N17

N26

G20

H19

H26

J18

K10

K11

K12

K13

K14

K15

K16

K17

L10

P10

P11

P12

P13

P14

P15

P16

P17

P26

Dedicated I/O

GND

A13

A14

A19

A26

Revision 18

3-41

Package Pin Assignments

FG676

AX500 Function

GND

GND/LP

Number

AX500 Function

Number

AX500 Function

Number

R10

R11

R12

R13

R14

R15

R16

R17

T10

T11

T12

T13

T14

T15

T16

T17

U10

U11

U12

U13

U14

U15

U16

U17

V18

A22

A24

A25

D13

D14

D17

D18

AA11

AA19

AA20

AA4

AA5

D26

AA6

AA7

AA8

AA9

E18

E23

E24

E26

AB1

AB11

AB17

AB18

AB19

AB20

AB8

AB9

F18

F20

F21

F22

F23

F24

AC1

AC13

AC14

AC25

AD1

AD11

AD16

AD25

AE1

W19

W26

G21

G22

H21

H22

H23

AF2

Y20

AF25

B11

B24

A11

A21

C16

3-42

Revision 18

Axcelerator Family FPGAs

FG676

AX500 Function

Number

AX500 Function

VCCA

VCCDA

Number

AX500 Function

Number

AD10

AD13

AD17

J10

J11

J12

J13

J14

J15

J16

J17

K18

VCCDA

VCCIB0

VCCIB1

VCCIB2

VCCIB3

P22

R20

R21

R22

B17

D24

E14

T22

T24

U22

U24

V22

P23

G10

L18

M18

H10

H11

H12

H13

W21

W22

Y21

N18

P18

G17

G18

G19

H14

H15

H16

H17

H18

H20

J19

R18

T18

PRA

PRB

PRC

PRD

TCK

TDI

E13

B14

Y14

AD14

U18

V10

V11

V12

V13

V14

V15

V16

V17

J20

TDO

TMS

TRST

VCCA

K19

K20

L19

AB4

AF24

M19

N19

P19

R19

AB22

AB5

C26

Revision 18

3-43

Package Pin Assignments

FG676

AX500 Function

VCCIB3

VCCIB4

VCCIB5

VCCIB6

VCCIB7

Number

AX500 Function

VCCIB7

Number

T19

U19

U20

V19

V20

W20

W14

W15

W16

W17

W18

Y17

Y18

Y19

W10

W11

W12

W13

Y10

VCCIB7

VCCPLA

E12

VCCPLB

F13

VCCPLC

VCCPLD

VCCPLE

E15

G14

AF15

AA14

AF12

AB13

D12

G13

D15

F14

VCCPLF

VCCPLG

VCCPLH

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

AD15

AB14

AD12

Y13

E22

3-44

Revision 18

Axcelerator Family FPGAs

FG676

AX1000 Function

Bank 0

FG676

AX1000 Function

IO21PB0F1

FG676

Pin Number

C10

AX1000 Function

Pin Number

F17

IO48NB1F4

IO48PB1F4

IO49NB1F4

IO49PB1F4

IO50NB1F4

IO50PB1F4

IO51NB1F4

IO51PB1F4

IO52NB1F4

IO52PB1F4

IO54NB1F5

IO54PB1F5

IO55NB1F5

IO55PB1F5

IO56NB1F5

IO56PB1F5

IO57NB1F5

IO57PB1F5

IO58NB1F5

IO58PB1F5

IO59NB1F5

IO59PB1F5

IO60NB1F5

IO60PB1F5

IO62NB1F5

IO62PB1F5

IO63NB1F5

IO63PB1F5

IO00NB0F0

IO00PB0F0

IO02NB0F0

IO02PB0F0

IO03NB0F0

IO03PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO07NB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO16NB0F1

IO16PB0F1

IO18NB0F1

IO18PB0F1

IO19NB0F1

IO19PB0F1

IO20NB0F1

IO20PB0F1

IO21NB0F1

IO22NB0F2

F11

E17

A22

A21

E18

F18

IO22PB0F2

G11

IO24NB0F2

D11

IO24PB0F2

E11

IO26NB0F2

C12

IO26PB0F2

C11

D19

C19

D20

C20

B22

B21

D21

C21

F19

IO28NB0F2

F12

IO28PB0F2

G12

A12

IO30NB0F2/HCLKAN

IO30PB0F2/HCLKAP

IO31NB0F2/HCLKBN

IO31PB0F2/HCLKBP

Bank 1

B12

C13

B13

IO32NB1F3/HCLKCN

IO32PB1F3/HCLKCP

IO33NB1F3/HCLKDN

IO33PB1F3/HCLKDP

IO35NB1F3

C15

C14

A15

B15

B16

A16

F15

G15

F16

G16

A18

A17

C18

C17

D16

E16

D18

D17

B19

B18

B20

A20

E19

B23

A23

D22

C22

B24

A24

E21

E20

D23

C23

F21

F10

IO35PB1F3

IO36NB1F3

IO36PB1F3

IO38NB1F3

IO38PB1F3

IO40NB1F3

IO40PB1F3

IO41NB1F4

IO41PB1F4

F20

IO42NB1F4

Bank 2

A10

D10

E10

B10

IO42PB1F4

IO64NB2F6

IO64PB2F6

IO65NB2F6

IO65PB2F6

IO66NB2F6

IO66PB2F6

IO67NB2F6

H21

G21

G22

F22

F24

F23

E24

IO44NB1F4

IO44PB1F4

IO45NB1F4

IO45PB1F4

IO46NB1F4

IO46PB1F4

Revision 18

3-45

Package Pin Assignments

FG676

AX1000 Function

IO88PB2F8

IO89NB2F8

IO89PB2F8

IO90NB2F8

IO90PB2F8

IO91NB2F8

IO91PB2F8

IO92NB2F8

IO92PB2F8

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

Bank 3

FG676

AX1000 Function

IO110NB3F10

IO110PB3F10

IO112NB3F10

IO112PB3F10

IO113NB3F10

IO113PB3F10

IO114NB3F10

IO114PB3F10

IO115NB3F10

IO115PB3F10

IO116NB3F10

IO116PB3F10

IO118NB3F11

IO118PB3F11

IO119NB3F11

IO119PB3F11

IO120NB3F11

IO120PB3F11

IO121NB3F11

IO121PB3F11

IO122NB3F11

IO122PB3F11

IO123NB3F11

IO123PB3F11

IO124NB3F11

IO124PB3F11

IO125NB3F11

IO125PB3F11

IO126NB3F11

IO126PB3F11

IO127NB3F11

IO127PB3F11

IO128NB3F11

IO128PB3F11

Bank 4

AX1000 Function

IO67PB2F6

IO68NB2F6

IO68PB2F6

IO69NB2F6

IO69PB2F6

IO70NB2F6

IO70PB2F6

IO71NB2F6

IO71PB2F6

IO72NB2F6

IO72PB2F6

IO73NB2F6

IO73PB2F6

IO74NB2F7

IO74PB2F7

IO75NB2F7

IO75PB2F7

IO76NB2F7

IO76PB2F7

IO77NB2F7

IO77PB2F7

IO78NB2F7

IO78PB2F7

IO80NB2F7

IO80PB2F7

IO81NB2F7

IO81PB2F7

IO82NB2F7

IO82PB2F7

IO83NB2F7

IO83PB2F7

IO84NB2F7

IO84PB2F7

IO86NB2F8

IO86PB2F8

IO88NB2F8

Pin Number

M22

Pin Number

T21

E23

H23

H22

D25

C25

G24

G23

F25

E25

G26

F26

E26

D26

J21

J22

J24

H24

K23

J23

H25

G25

K25

J25

K21

K22

K26

J26

L24

K24

L23

L22

L20

L21

L26

L25

M23

M26

T20

M25

V23

M20

U23

M21

Y25

N24

W25

V21

M24

N22

U21

N23

W24

V24

N20

N21

AA26

Y26

P25

N25

AC26

AB26

AB25

AA25

W22

V22

IO98NB3F9

IO98PB3F9

IO99NB3F9

IO99PB3F9

IO100NB3F9

IO100PB3F9

IO101NB3F9

IO101PB3F9

IO102NB3F9

IO102PB3F9

IO103NB3F9

IO103PB3F9

IO105NB3F9

IO105PB3F9

IO106NB3F9

IO106PB3F9

IO107NB3F10

IO107PB3F10

IO108NB3F10

IO108PB3F10

IO109NB3F10

IO109PB3F10

P20

P21

R24

P24

R22

P22

T26

R26

R21

R20

T25

R25

V26

U26

T23

R23

U24

T24

U22

T22

V25

U25

Y23

W23

AA24

Y24

AE26

AD26

Y21

W21

AD25

AC25

AB23

AA23

AC24

AB24

AA22

Y22

IO129NB4F12

AB21

3-46

Revision 18

Axcelerator Family FPGAs

FG676

AX1000 Function

IO129PB4F12

IO131NB4F12

IO131PB4F12

IO132NB4F12

IO132PB4F12

IO133NB4F12

IO133PB4F12

IO134NB4F12

IO134PB4F12

IO135NB4F12

IO135PB4F12

IO137NB4F12

IO137PB4F12

IO139NB4F13

IO139PB4F13

IO140NB4F13

IO140PB4F13

IO141NB4F13

IO141PB4F13

IO143NB4F13

IO143PB4F13

IO144NB4F13

IO144PB4F13

IO145NB4F13

IO145PB4F13

IO146NB4F13

IO146PB4F13

IO147NB4F13

IO147PB4F13

IO148NB4F13

IO148PB4F13

IO149NB4F13

IO149PB4F13

IO151NB4F13

IO151PB4F13

IO153NB4F14

FG676

AX1000 Function

IO153PB4F14

FG676

Pin Number

AA21

AD22

AD23

AE23

AE24

AB20

AA20

AC21

AC22

AF22

AF23

AB19

AA19

AC19

AC20

AE21

AE22

AD20

AD21

AB17

AB18

AE19

AE20

AC17

AC18

AD18

AD19

AA17

AA18

AF20

AF21

AA16

Y16

Pin Number

AE18

AF17

AX1000 Function

Pin Number

AA10

AB10

AD7

AD8

AC7

AC8

AA9

IO177NB5F16

IO177PB5F16

IO179NB5F16

IO179PB5F16

IO180NB5F16

IO180PB5F16

IO181NB5F17

IO181PB5F17

IO183NB5F17

IO183PB5F17

IO184NB5F17

IO184PB5F17

IO185NB5F17

IO185PB5F17

IO187NB5F17

IO187PB5F17

IO188NB5F17

IO188PB5F17

IO189NB5F17

IO189PB5F17

IO190NB5F17

IO190PB5F17

IO191NB5F17

IO191PB5F17

IO192NB5F17

IO192PB5F17

IO154NB4F14

IO154PB4F14

AF18

IO155NB4F14

AA15

Y15

IO155PB4F14

IO157NB4F14

AC15

AB15

AE16

AF16

IO157PB4F14

IO159NB4F14/CLKEN

IO159PB4F14/CLKEP

IO160NB4F14/CLKFN

IO160PB4F14/CLKFP

Bank 5

AB9

AD6

AE6

AE14

AE15

AE5

AF5

IO161NB5F15/CLKGN

IO161PB5F15/CLKGP

IO162NB5F15/CLKHN

IO162PB5F15/CLKHP

IO163NB5F15

AE12

AE13

AE11

AF11

AC12

AB12

Y12

AA8

AB8

AC5

AC6

AD4

AD5

AB6

IO163PB5F15

IO165NB5F15

IO165PB5F15

AA13

Y11

AB7

IO167NB5F15

AF4

IO167PB5F15

AA12

AF9

AE4

IO168NB5F15

AE3

IO168PB5F15

AF10

AB11

AA11

AE9

AF3

IO169NB5F15

AA6

IO169PB5F15

AA7

IO171NB5F16

Bank 6

IO171PB5F16

AE10

AC10

AC11

AE7

IO193NB6F18

IO193PB6F18

IO194NB6F18

IO194PB6F18

IO195NB6F18

IO195PB6F18

IO196NB6F18

IO196PB6F18

IO197NB6F18

IO173NB5F16

AA5

AB3

AC3

IO173PB5F16

IO174NB5F16

IO174PB5F16

AE8

IO175NB5F16

AC9

AA4

AC2

AD2

AC16

AB16

AE17

IO175PB5F16

AD9

IO176NB5F16

AF6

IO176PB5F16

AF7

Revision 18

3-47

Package Pin Assignments

FG676

AX1000 Function

IO217PB6F20

IO218NB6F20

IO218PB6F20

IO219NB6F20

IO219PB6F20

IO220NB6F20

IO220PB6F20

IO221NB6F20

IO221PB6F20

IO223NB6F20

IO223PB6F20

Bank 7

FG676

AX1000 Function

IO241NB7F22

IO241PB7F22

IO242NB7F22

IO242PB7F22

IO243NB7F22

IO243PB7F22

IO244NB7F22

IO244PB7F22

IO245NB7F22

IO245PB7F22

IO247NB7F23

IO247PB7F23

IO248NB7F23

IO248PB7F23

IO249NB7F23

IO249PB7F23

IO250NB7F23

IO250PB7F23

IO251NB7F23

IO251PB7F23

IO253NB7F23

IO253PB7F23

IO254NB7F23

IO254PB7F23

IO255NB7F23

IO255PB7F23

IO256NB7F23

IO256PB7F23

IO257NB7F23

IO257PB7F23

AX1000 Function

IO197PB6F18

IO198NB6F18

IO198PB6F18

IO199NB6F18

IO199PB6F18

IO200NB6F18

IO200PB6F18

IO201NB6F18

IO201PB6F18

IO202NB6F18

IO202PB6F18

IO203NB6F19

IO203PB6F19

IO204NB6F19

IO204PB6F19

IO205NB6F19

IO205PB6F19

IO206NB6F19

IO206PB6F19

IO207NB6F19

IO207PB6F19

IO208NB6F19

IO208PB6F19

IO209NB6F19

IO209PB6F19

IO211NB6F19

IO211PB6F19

IO212NB6F19

IO212PB6F19

IO213NB6F19

IO213PB6F19

IO214NB6F20

IO214PB6F20

IO215NB6F20

IO215PB6F20

IO217NB6F20

Pin Number

AD1

AE1

AA2

AB2

AA3

AB1

AC1

IO225NB7F21

IO225PB7F21

IO226NB7F21

IO226PB7F21

IO227NB7F21

IO227PB7F21

IO229NB7F21

IO229PB7F21

IO231NB7F21

IO231PB7F21

IO232NB7F21

IO232PB7F21

IO233NB7F21

IO233PB7F21

IO235NB7F21

IO235PB7F21

IO236NB7F22

IO236PB7F22

IO237NB7F22

IO237PB7F22

IO238NB7F22

IO238PB7F22

IO240NB7F22

IO240PB7F22

AA1

Dedicated I/O

GND

A13

A14

A19

A26

3-48

Revision 18

Axcelerator Family FPGAs

FG676

AX1000 Function

GND

FG676

AX1000 Function

GND

FG676

Pin Number

L12

AX1000 Function

Pin Number

R12

R13

R14

R15

R16

R17

T10

GND

GND/LP

GND

AC23

AC4

AD24

AD3

AE2

AE25

AF1

AF13

AF14

AF19

AF26

AF8

GND

L13

GND

L14

GND

L15

GND

L16

GND

L17

GND

M10

M11

M12

M13

M14

M15

M16

M17

GND

T11

GND

T12

GND

T13

GND

T14

GND

T15

GND

T16

GND

T17

GND

B25

B26

C24

GND

U10

U11

U12

U13

U14

U15

U16

U17

V18

GND

N10

N11

N12

N13

N14

N15

N16

N17

N26

GND

G20

GND

H19

H26

GND

J18

GND

P10

P11

W19

W26

GND

K10

K11

GND

P12

P13

P14

P15

P16

P17

P26

R10

R11

GND

K12

K13

K14

K15

K16

K17

L10

GND

Y20

GND

A25

AC13

AC14

AF2

AF25

GND

L11

GND

Revision 18

3-49

Package Pin Assignments

FG676

AX1000 Function

VCCA

FG676

AX1000 Function

VCCIB0

VCCIB1

VCCIB2

VCCIB3

VCCIB4

AX1000 Function

Pin Number

G10

D13

D14

E13

B14

Y14

AD14

VCCA

U18

PRA

VCCA

PRB

VCCA

V10

H10

H11

H12

H13

PRC

VCCA

V11

PRD

VCCA

V12

TCK

VCCA

V13

TDI

VCCA

V14

TDO

VCCA

V15

G17

G18

G19

H14

H15

H16

H17

H18

H20

J19

TMS

VCCA

V16

TRST

VCCA

V17

AB4

AF24

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

VCCPLH

VCCDA

E12

F13

E15

C26

J10

J11

J12

J13

J14

J15

J16

J17

K18

G14

AF15

AA14

AF12

AB13

A11

J20

K19

K20

L19

AB22

AB5

AD10

AD11

AD13

AD16

AD17

M19

N19

P19

R19

T19

L18

M18

U19

U20

V19

V20

W20

W14

W15

W16

W17

N18

B11

B17

P18

C16

D24

E14

R18

T18

P23

3-50

Revision 18

Axcelerator Family FPGAs

FG676

AX1000 Function

VCCIB4

FG676

AX1000 Function

VCOMPLH

Pin Number

W18

Y17

Y18

Y19

W10

W11

W12

W13

Pin Number

Y13

VCCIB4

VPUMP

E22

VCCIB4

VCCIB5

Y10

VCCIB5

VCCIB6

VCCIB7

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

D12

G13

D15

F14

AD15

AB14

AD12

Revision 18

3-51

Package Pin Assignments

FG896

A1 Ball Pad Corner

30 29 28 2726 25 24 23 22 21 20 1918 17 16 1514 13 12 11 10 9 8 7 6 5 4 3 2 1

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.microsemi.com/soc/products/rescenter/package/index.html.

3-52

Revision 18

Axcelerator Family FPGAs

FG896

AX1000 Function

Bank 0

Number

AX1000 Function

IO17NB0F1

Number

AX1000 Function

Number

A17

B17

D18

C18

H17

J17

B11

B10

D11

E11

C12

C11

F12

G12

D12

E12

H13

J13

IO34NB1F3

IO34PB1F3

IO35NB1F3

IO35PB1F3

IO36NB1F3

IO36PB1F3

IO37NB1F3

IO37PB1F3

IO38NB1F3

IO38PB1F3

IO39NB1F3

IO39PB1F3

IO40NB1F3

IO40PB1F3

IO41NB1F4

IO41PB1F4

IO42NB1F4

IO42PB1F4

IO43NB1F4

IO43PB1F4

IO44NB1F4

IO44PB1F4

IO45NB1F4

IO45PB1F4

IO46NB1F4

IO46PB1F4

IO47NB1F4

IO47PB1F4

IO48NB1F4

IO48PB1F4

IO49NB1F4

IO49PB1F4

IO50NB1F4

IO50PB1F4

IO51NB1F4

IO00NB0F0

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO03NB0F0

IO03PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO07NB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO09NB0F0

IO09PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17PB0F1

IO18NB0F1

IO18PB0F1

IO19NB0F1

IO19PB0F1

IO20NB0F1

B19

A19

H18

J18

IO20PB0F1

IO21NB0F1

IO21PB0F1

IO22NB0F2

B20

A20

C20

C19

E20

E19

F18

G18

A22

A21

F20

F19

D21

D20

D22

C22

A25

A24

H19

G19

C24

C23

G20

H20

F21

IO22PB0F2

IO23NB0F2

A12

A11

F13

G13

B13

B12

E14

E13

B14

A14

H14

J14

IO23PB0F2

IO24NB0F2

IO24PB0F2

IO25NB0F2

IO25PB0F2

IO26NB0F2

IO26PB0F2

IO27NB0F2

H10

G10

IO27PB0F2

IO28NB0F2

IO28PB0F2

IO29NB0F2

B15

A15

C14

D14

E15

D15

E10

F10

D10

IO29PB0F2

IO30NB0F2/HCLKAN

IO30PB0F2/HCLKAP

IO31NB0F2/HCLKBN

IO31PB0F2/HCLKBP

Bank 1

F11

G11

A10

IO32NB1F3/HCLKCN

IO32PB1F3/HCLKCP

IO33NB1F3/HCLKDN

IO33PB1F3/HCLKDP

E17

E16

C17

D17

H12

H11

Revision 18

3-53

Package Pin Assignments

FG896

AX1000 Function

IO51PB1F4

IO52NB1F4

IO52PB1F4

IO53NB1F4

IO53PB1F4

IO54NB1F5

IO54PB1F5

IO55NB1F5

IO55PB1F5

IO56NB1F5

IO56PB1F5

IO57NB1F5

IO57PB1F5

IO58NB1F5

IO58PB1F5

IO59NB1F5

IO59PB1F5

IO60NB1F5

IO60PB1F5

IO61NB1F5

IO61PB1F5

IO62NB1F5

IO62PB1F5

IO63NB1F5

IO63PB1F5

Bank 2

Number

AX1000 Function

IO68PB2F6

IO69NB2F6

IO69PB2F6

IO70NB2F6

IO70PB2F6

IO71NB2F6

IO71PB2F6

IO72NB2F6

IO72PB2F6

IO73NB2F6

IO73PB2F6

IO74NB2F7

IO74PB2F7

IO75NB2F7

IO75PB2F7

IO76NB2F7

IO76PB2F7

IO77NB2F7

IO77PB2F7

IO78NB2F7

IO78PB2F7

IO79NB2F7

IO79PB2F7

IO80NB2F7

IO80PB2F7

IO81NB2F7

IO81PB2F7

IO82NB2F7

IO82PB2F7

IO83NB2F7

IO83PB2F7

IO84NB2F7

IO84PB2F7

IO85NB2F8

IO85PB2F8

Number

AX1000 Function

IO86NB2F8

IO86PB2F8

IO87NB2F8

IO87PB2F8

IO88NB2F8

IO88PB2F8

IO89NB2F8

IO89PB2F8

IO90NB2F8

IO90PB2F8

IO91NB2F8

IO91PB2F8

IO92NB2F8

IO92PB2F8

IO93NB2F8

IO93PB2F8

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

Bank 3

Number

E21

F22

E22

B25

B24

D24

D23

F23

E23

H21

G21

D25

C25

F24

E24

D26

C26

G23

G22

B27

A27

F25

E25

H23

H22

K24

F27

E27

J26

N28

N27

P29

P30

P25

P24

P28

P27

P22

P23

R26

P26

R24

R25

R29

R30

R22

R23

T27

R27

J25

H27

G27

J28

H28

G28

F28

L23

L24

L26

K26

M25

L25

K27

J27

M27

L27

K30

K29

M23

M24

M28

L28

N26

M26

N25

N24

N22

N23

M29

L29

IO96NB3F9

IO96PB3F9

IO97NB3F9

IO97PB3F9

IO98NB3F9

IO98PB3F9

IO99NB3F9

IO99PB3F9

IO100NB3F9

IO100PB3F9

IO101NB3F9

IO101PB3F9

IO102NB3F9

IO102PB3F9

T29

T30

U29

U30

T22

T23

U26

T26

U24

T24

V28

U28

U23

U22

IO64NB2F6

IO64PB2F6

IO65NB2F6

IO65PB2F6

IO66NB2F6

IO66PB2F6

IO67NB2F6

IO67PB2F6

IO68NB2F6

K23

J23

J24

H24

H26

H25

G26

G25

K25

3-54

Revision 18

Axcelerator Family FPGAs

FG896

AX1000 Function

IO103NB3F9

IO103PB3F9

IO104NB3F9

IO104PB3F9

IO105NB3F9

IO105PB3F9

IO106NB3F9

IO106PB3F9

IO107NB3F10

IO107PB3F10

IO108NB3F10

IO108PB3F10

IO109NB3F10

IO109PB3F10

IO110NB3F10

IO110PB3F10

IO111NB3F10

IO111PB3F10

IO112NB3F10

IO112PB3F10

IO113NB3F10

IO113PB3F10

IO114NB3F10

IO114PB3F10

IO115NB3F10

IO115PB3F10

IO116NB3F10

IO116PB3F10

IO117NB3F10

IO117PB3F10

IO118NB3F11

IO118PB3F11

IO119NB3F11

IO119PB3F11

IO120NB3F11

Number

AX1000 Function

IO120PB3F11

IO121NB3F11

IO121PB3F11

IO122NB3F11

IO122PB3F11

IO123NB3F11

IO123PB3F11

IO124NB3F11

IO124PB3F11

IO125NB3F11

IO125PB3F11

IO126NB3F11

IO126PB3F11

IO127NB3F11

IO127PB3F11

IO128NB3F11

IO128PB3F11

Bank 4

Number

AX1000 Function

Number

AC21

AK24

AK25

AE21

AE22

AG23

AG24

AF22

AF23

AJ23

AJ24

AD19

AD20

AG21

AG22

AE19

AE20

AF20

AF21

AC19

AC20

AH22

AH23

AC18

AB18

AK21

AJ21

AE18

AD18

AJ20

AK20

AG19

AG20

AH19

AH20

V27

U27

Y24

IO137PB4F12

IO138NB4F12

IO138PB4F12

IO139NB4F13

IO139PB4F13

IO140NB4F13

IO140PB4F13

IO141NB4F13

IO141PB4F13

IO142NB4F13

IO142PB4F13

IO143NB4F13

IO143PB4F13

IO144NB4F13

IO144PB4F13

IO145NB4F13

IO145PB4F13

IO146NB4F13

IO146PB4F13

IO147NB4F13

IO147PB4F13

IO148NB4F13

IO148PB4F13

IO149NB4F13

IO149PB4F13

IO150NB4F13

IO150PB4F13

IO151NB4F13

IO151PB4F13

IO152NB4F14

IO152PB4F14

IO153NB4F14

IO153PB4F14

IO154NB4F14

IO154PB4F14

AB25

AA25

AC26

AB26

AG28

AF28

AB23

AA23

AF27

AE27

AD25

AC25

AE26

AD26

AC24

AB24

W29

V29

Y28

W28

V25

U25

W26

V26

W24

V24

Y27

W27

V23

V22

AA29

Y29

Y25

IO129NB4F12

IO129PB4F12

IO130NB4F12

IO130PB4F12

IO131NB4F12

IO131PB4F12

IO132NB4F12

IO132PB4F12

IO133NB4F12

IO133PB4F12

IO134NB4F12

IO134PB4F12

IO135NB4F12

IO135PB4F12

IO136NB4F12

IO136PB4F12

IO137NB4F12

AD23

AC23

AK26

AK27

AF24

AF25

AG25

AG26

AD22

AC22

AE23

AE24

AH24

AH25

AJ25

AJ26

AD21

W25

AB27

AA27

Y23

W23

AA26

Y26

AC28

AB28

AE29

AD29

AE28

AD28

AD27

AC27

AA24

Revision 18

3-55

Package Pin Assignments

FG896

AX1000 Function

IO155NB4F14

Number

AX1000 Function

IO172NB5F16

IO172PB5F16

IO173NB5F16

IO173PB5F16

IO174NB5F16

IO174PB5F16

IO175NB5F16

IO175PB5F16

IO176NB5F16

IO176PB5F16

IO177NB5F16

IO177PB5F16

IO178NB5F16

IO178PB5F16

IO179NB5F16

IO179PB5F16

IO180NB5F16

IO180PB5F16

IO181NB5F17

IO181PB5F17

IO182NB5F17

IO182PB5F17

IO183NB5F17

IO183PB5F17

IO184NB5F17

IO184PB5F17

IO185NB5F17

IO185PB5F17

IO186NB5F17

IO186PB5F17

IO187NB5F17

IO187PB5F17

IO188NB5F17

IO188PB5F17

IO189NB5F17

Number

AX1000 Function

IO189PB5F17

IO190NB5F17

IO190PB5F17

IO191NB5F17

IO191PB5F17

IO192NB5F17

IO192PB5F17

Bank 6

Number

AC17

AB17

AK19

AJ19

AE17

AD17

AJ17

AJ18

AG18

AH18

AG16

AG17

AK9

AK10

AE12

AE13

AG9

AG10

AE11

AF11

AH8

AH9

AC12

AD12

AJ7

AD9

AH6

AG6

AG5

AH5

AC8

AC9

IO155PB4F14

IO156NB4F14

IO156PB4F14

IO157NB4F14

IO157PB4F14

IO158NB4F14

IO158PB4F14

IO159NB4F14/CLKEN

IO159PB4F14/CLKEP

IO160NB4F14/CLKFN

IO160PB4F14/CLKFP

Bank 5

IO193NB6F18

IO193PB6F18

IO194NB6F18

IO194PB6F18

IO195NB6F18

IO195PB6F18

IO196NB6F18

IO196PB6F18

IO197NB6F18

IO197PB6F18

IO198NB6F18

IO198PB6F18

IO199NB6F18

IO199PB6F18

IO200NB6F18

IO200PB6F18

IO201NB6F18

IO201PB6F18

IO202NB6F18

IO202PB6F18

IO203NB6F19

IO203PB6F19

IO204NB6F19

IO204PB6F19

IO205NB6F19

IO205PB6F19

IO206NB6F19

AB7

AC7

AD5

AE5

AB6

AC6

AE4

AF4

AA8

AB8

AF3

AG3

AC4

AD4

AB5

AC5

IO161NB5F15/CLKGN

IO161PB5F15/CLKGP

IO162NB5F15/CLKHN

IO162PB5F15/CLKHP

IO163NB5F15

AG14

AG15

AG13

AH13

AE14

AD14

AJ12

AJ13

AB14

AC15

AK11

AK12

AB13

AC14

AH11

AH12

AD13

AC13

AJ10

AJ11

AJ8

AF9

AF10

AE9

AE10

AC11

AD11

AK6

IO163PB5F15

IO164NB5F15

IO164PB5F15

IO165NB5F15

AK7

IO165PB5F15

AF8

IO166NB5F15

AG8

AG7

AH7

AC10

AD10

AJ5

IO166PB5F15

IO167NB5F15

AA7

AD3

AE3

IO167PB5F15

IO168NB5F15

IO168PB5F15

IO169NB5F15

AJ6

AA6

IO169PB5F15

AE7

IO170NB5F15

AE8

AA5

IO170PB5F15

AF6

IO171NB5F16

AG11

AG12

AF7

IO171PB5F16

AD8

AA4

3-56

Revision 18

Axcelerator Family FPGAs

FG896

AX1000 Function

IO206PB6F19

IO207NB6F19

IO207PB6F19

IO208NB6F19

IO208PB6F19

IO209NB6F19

IO209PB6F19

IO210NB6F19

IO210PB6F19

IO211NB6F19

IO211PB6F19

IO212NB6F19

IO212PB6F19

IO213NB6F19

IO213PB6F19

IO214NB6F20

IO214PB6F20

IO215NB6F20

IO215PB6F20

IO216NB6F20

IO216PB6F20

IO217NB6F20

IO217PB6F20

IO218NB6F20

IO218PB6F20

IO219NB6F20

IO219PB6F20

IO220NB6F20

IO220PB6F20

IO221NB6F20

IO221PB6F20

IO222NB6F20

IO222PB6F20

IO223NB6F20

IO223PB6F20

Number

AX1000 Function

IO224NB6F20

IO224PB6F20

Bank 7

Number

AX1000 Function

Number

AB4

AB3

AC3

IO241NB7F22

IO241PB7F22

IO242NB7F22

IO242PB7F22

IO243NB7F22

IO243PB7F22

IO244NB7F22

IO244PB7F22

IO245NB7F22

IO245PB7F22

IO246NB7F22

IO246PB7F22

IO247NB7F23

IO247PB7F23

IO248NB7F23

IO248PB7F23

IO249NB7F23

IO249PB7F23

IO250NB7F23

IO250PB7F23

IO251NB7F23

IO251PB7F23

IO252NB7F23

IO252PB7F23

IO253NB7F23

IO253PB7F23

IO254NB7F23

IO254PB7F23

IO255NB7F23

IO255PB7F23

IO256NB7F23

IO256PB7F23

IO257NB7F23

IO257PB7F23

IO225NB7F21

IO225PB7F21

IO226NB7F21

IO226PB7F21

IO227NB7F21

IO227PB7F21

IO228NB7F21

IO228PB7F21

IO229NB7F21

IO229PB7F21

IO230NB7F21

IO230PB7F21

IO231NB7F21

IO231PB7F21

IO232NB7F21

IO232PB7F21

IO233NB7F21

IO233PB7F21

IO234NB7F21

IO234PB7F21

IO235NB7F21

IO235PB7F21

IO236NB7F22

IO236PB7F22

IO237NB7F22

IO237PB7F22

IO238NB7F22

IO238PB7F22

IO239NB7F22

IO239PB7F22

IO240NB7F22

IO240PB7F22

AA2

AA1

Dedicated I/O

Revision 18

3-57

Package Pin Assignments

FG896

AX1000 Function

GND

Number

AX1000 Function

GND

Number

AX1000 Function

GND

Number

A13

A18

AK18

AK2

AK23

AK29

AK8

M13

M14

M15

M16

M17

M18

M19

A23

A29

AA10

AA21

AA28

AA3

B22

B29

B30

N12

N13

N14

N15

N16

N17

N18

N19

N30

P12

P13

P14

P15

P16

P17

P18

P19

R12

R13

R14

R15

R16

R17

R18

R19

R28

AB2

AB22

AB29

AB9

C10

C15

C16

C21

C28

AC1

AC30

AE25

AE6

D27

D28

AF26

AF5

AG27

AG4

AH10

AH15

AH16

AH21

AH28

AH3

AJ1

E26

H30

J22

J29

K10

K21

K28

AJ2

AJ22

AJ29

AJ30

AJ9

L11

L20

M12

AK13

3-58

Revision 18

Axcelerator Family FPGAs

FG896

AX1000 Function

GND

Number

AX1000 Function

Number

AX1000 Function

Number

AJ4

AK14

AK15

AK16

AK17

AK22

AK4

AK5

B16

B18

B21

B23

B26

T12

T13

T14

T15

T16

T17

T18

T19

T28

GND

GND/LP

W19

Y11

Y20

A16

A26

AA30

AB1

U12

U13

U14

U15

U16

U17

U18

U19

AB30

AC2

AC29

AD1

AD2

AD30

AE1

C27

AE15

AE16

AE2

V12

V13

V14

V15

V16

V17

V18

V19

V30

W12

W13

W14

W15

W16

W17

W18

D29

D30

AE30

AF1

AF2

AF29

AF30

AG1

AG2

AG29

AG30

AH27

AH4

AJ14

AJ15

AJ16

AJ27

E29

E30

F15

F16

F29

F30

G29

G30

H29

J30

Revision 18

3-59

Package Pin Assignments

FG896

AX1000 Function

Number

AX1000 Function

VCCA

Number

AX1000 Function

VCCDA

VCCIB0

VCCIB1

VCCIB2

Number

N20

P11

AF19

C13

VCCA

L30

M30

N29

VCCA

P20

VCCA

R11

D13

D19

VCCA

R20

T11

VCCA

T20

E18

F26

G16

T25

W30

VCCA

U11

VCCA

U20

V11

VCCA

Y30

G15

D16

AB16

AF16

VCCA

V20

PRA

VCCA

W11

W20

Y12

PRB

VCCA

PRC

VCCA

J10

J11

J12

K11

K12

K13

K14

K15

A28

B28

J19

J20

J21

K16

K17

K18

K19

K20

C29

C30

K22

L21

PRD

VCCA

Y13

TCK

VCCA

Y14

TDI

VCCA

Y15

TDO

VCCA

Y16

TMS

VCCA

Y17

TRST

VCCA

Y18

AD6

AH26

E28

VCCA

Y19

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

VCCPLH

VCCDA

G14

H15

G17

J16

L12

L13

L14

L15

L16

L17

L18

L19

M11

M20

N11

AH17

AC16

AH14

AD15

AD24

AD7

AF12

AF13

AF15

AF18

3-60

Revision 18

Axcelerator Family FPGAs

FG896

AX1000 Function

VCCIB2

VCCIB3

VCCIB4

VCCIB5

Number

AX1000 Function

VCCIB5

Number

L22

M21

AK3

AA9

AH1

AH2

T10

U10

V10

W10

VCCIB6

M22

VCCIB6

N21

VCCIB6

P21

VCCIB6

R21

VCCIB6

AA22

AH29

AH30

T21

VCCIB6

Y10

U21

VCCIB6

V21

VCCIB7

W21

W22

Y21

VCCIB7

L10

Y22

VCCIB7

AA16

AA17

AA18

AA19

AA20

AB19

AB20

AB21

AJ28

AK28

AA11

AA12

AA13

AA14

AA15

AB10

AB11

AB12

AJ3

VCCIB7

M10

VCCIB7

N10

P10

R10

F14

J15

VCCIB7

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

F17

H16

AF17

AD16

AF14

AB15

G24

Revision 18

3-61

Package Pin Assignments

FG896

AX2000 Function

Bank 0

Number

AX2000 Function

IO19NB0F1

Number

AX2000 Function

Bank 1

Number

D11

E11

IO00NB0F0

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO07NB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO09NB0F0

IO09PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17NB0F1

IO17PB0F1

IO18NB0F1

IO18PB0F1

IO19PB0F1

IO43NB1F4/HCLKCN

IO43PB1F4/HCLKCP

IO44NB1F4/HCLKDN

IO44PB1F4/HCLKDP

IO45NB1F4

IO45PB1F4

E17

E16

C17

D17

A16

B16

H17

J17

IO20PB0F1

IO21NB0F1

H12

H11

A10

IO21PB0F1

IO23NB0F2

IO23PB0F2

IO25NB0F2

F12

G12

B11

B10

D12

E12

C12

C11

A12

A11

F13

G13

H13

J13

B13

B12

E14

E13

B14

A14

H14

J14

B15

A15

C14

D14

E15

D15

IO47NB1F4

IO47PB1F4

IO25PB0F2

IO26NB0F2

IO48NB1F4

IO48PB1F4

A17

B17

H18

J18

IO26PB0F2

IO27NB0F2

IO49NB1F4

IO49PB1F4

IO27PB0F2

IO28NB0F2

IO51NB1F4

IO51PB1F4

F18

G18

B18

D18

C18

H19

G19

B19

A19

E20

E19

C20

C19

B20

A20

F20

F19

A22

A21

D21

D20

G20

IO28PB0F2

IO30NB0F2

IO52NB1F4

IO53NB1F4

IO53PB1F4

IO30PB0F2

IO31NB0F2

IO31PB0F2

IO55NB1F5

IO55PB1F5

IO33NB0F2

IO33PB0F2

IO56NB1F5

IO56PB1F5

H10

G10

IO34NB0F3

IO34PB0F3

IO57NB1F5

IO57PB1F5

IO37NB0F3

IO37PB0F3

IO58NB1F5

IO58PB1F5

E10

F10

F11

G11

IO38NB0F3

IO38PB0F3

IO59NB1F5

IO59PB1F5

IO39NB0F3

IO39PB0F3

IO61NB1F5

IO61PB1F5

IO40NB0F3

IO40PB0F3

IO62NB1F5

IO62PB1F5

D10

IO41NB0F3/HCLKAN

IO41PB0F3/HCLKAP

IO42NB0F3/HCLKBN

IO42PB0F3/HCLKBP

IO63NB1F5

IO63PB1F5

IO65NB1F6

3-62

Revision 18

Axcelerator Family FPGAs

FG896

AX2000 Function

IO65PB1F6

IO66NB1F6

IO66PB1F6

IO67NB1F6

IO67PB1F6

IO68NB1F6

IO68PB1F6

IO69NB1F6

IO69PB1F6

IO70NB1F6

IO70PB1F6

IO71NB1F6

IO71PB1F6

IO73NB1F6

IO73PB1F6

IO74NB1F6

IO74PB1F6

IO75NB1F6

IO75PB1F6

IO76NB1F7

IO76PB1F7

IO78NB1F7

IO78PB1F7

IO79NB1F7

IO79PB1F7

IO80NB1F7

IO80PB1F7

IO81NB1F7

IO81PB1F7

IO82NB1F7

IO82PB1F7

IO83NB1F7

IO83PB1F7

IO84NB1F7

IO84PB1F7

Number

AX2000 Function

IO85NB1F7

IO85PB1F7

Bank 2

Number

AX2000 Function

Number

D30

L26

H20

B23

B21

H21

G21

D22

C22

A25

A24

F22

E22

F21

E21

C24

C23

D24

D23

H23

H22

B25

B24

B26

A26

F23

E23

D25

C25

G23

G22

B27

A27

F24

E24

D26

C26

F25

E25

IO102PB2F9

IO103NB2F9

IO103PB2F9

IO104NB2F9

IO105NB2F9

IO105PB2F9

IO106NB2F9

IO106PB2F9

IO107NB2F10

IO107PB2F10

IO109NB2F10

IO109PB2F10

IO110NB2F10

IO110PB2F10

IO111NB2F10

IO111PB2F10

IO112NB2F10

IO112PB2F10

IO113NB2F10

IO113PB2F10

IO114NB2F10

IO114PB2F10

IO115NB2F10

IO115PB2F10

IO117NB2F10

IO117PB2F10

IO118NB2F11

IO119NB2F11

IO119PB2F11

IO121NB2F11

IO121PB2F11

IO122NB2F11

IO122PB2F11

IO123NB2F11

IO123PB2F11

K26

F29

M25

L25

IO86NB2F8

IO86PB2F8

IO87NB2F8

IO87PB2F8

IO88NB2F8

IO88PB2F8

IO89NB2F8

IO89PB2F8

IO90NB2F8

IO90PB2F8

IO91NB2F8

IO91PB2F8

IO92NB2F8

IO92PB2F8

IO93NB2F8

IO93PB2F8

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

IO96NB2F9

IO96PB2F9

IO97NB2F9

IO97PB2F9

IO98NB2F9

IO98PB2F9

IO99NB2F9

IO99PB2F9

IO100NB2F9

IO100PB2F9

IO101PB2F9

IO102NB2F9

G26

G25

K23

J23

J24

H24

E29

D29

F27

E27

H26

H25

G28

F28

J26

J25

H27

G27

H29

G29

G30

F30

K25

K24

J28

H28

L23

L24

K27

J27

J30

E30

K30

K29

M23

M24

M27

L27

M28

L28

N22

N23

M29

L29

N26

M26

M30

L30

N28

N27

N25

N24

N29

P22

P23

P25

P24

P28

P27

R26

P26

Revision 18

3-63

Package Pin Assignments

FG896

AX2000 Function

IO124NB2F11

IO124PB2F11

IO125NB2F11

IO125PB2F11

IO127NB2F11

IO127PB2F11

IO128NB2F11

IO128PB2F11

Bank 3

Number

AX2000 Function

IO145NB3F13

IO145PB3F13

IO146NB3F13

IO146PB3F13

IO147NB3F13

IO147PB3F13

IO148NB3F13

IO148PB3F13

IO149NB3F13

IO149PB3F13

IO150NB3F14

IO150PB3F14

IO151NB3F14

IO152NB3F14

IO152PB3F14

IO153NB3F14

IO153PB3F14

IO154NB3F14

IO154PB3F14

IO155NB3F14

IO155PB3F14

IO156NB3F14

IO156PB3F14

IO157NB3F14

IO157PB3F14

IO158NB3F14

IO158PB3F14

IO159NB3F14

IO159PB3F14

IO160NB3F14

IO160PB3F14

IO161NB3F15

IO161PB3F15

IO162NB3F15

IO162PB3F15

Number

AX2000 Function

IO163NB3F15

IO163PB3F15

IO164NB3F15

IO164PB3F15

IO165NB3F15

IO165PB3F15

IO166NB3F15

IO166PB3F15

IO167NB3F15

IO167PB3F15

IO168NB3F15

IO168PB3F15

IO169NB3F15

IO169PB3F15

IO170NB3F15

IO170PB3F15

Bank 4

Number

P29

P30

R22

R23

R24

R25

R29

R30

W24

V24

AC26

AB26

AE28

AD28

AC24

AB24

AG28

AF28

AE26

AD26

AD25

AC25

AF27

AE27

AB23

AA23

W27

W28

Y28

Y27

Y30

W30

Y25

IO129NB3F12

IO129PB3F12

IO130NB3F12

IO130PB3F12

IO131NB3F12

IO131PB3F12

IO132NB3F12

IO132PB3F12

IO133NB3F12

IO133PB3F12

IO135NB3F12

IO135PB3F12

IO136NB3F12

IO136PB3F12

IO137NB3F12

IO137PB3F12

IO138NB3F12

IO138PB3F12

IO139NB3F13

IO139PB3F13

IO141NB3F13

IO141PB3F13

IO142NB3F13

IO142PB3F13

IO143NB3F13

IO143PB3F13

T27

R27

T29

T30

T22

T23

U26

T26

U24

T24

U23

U22

U29

U30

V28

U28

V27

U27

V25

U25

V23

V22

W29

V29

W26

V26

W25

AA29

Y29

AC29

AA26

Y26

Y23

W23

AB30

AA30

AB27

AA27

AC28

AB28

AA24

Y24

IO171NB4F16

IO171PB4F16

IO172NB4F16

IO172PB4F16

IO173NB4F16

IO173PB4F16

IO174NB4F16

IO174PB4F16

IO175NB4F16

IO175PB4F16

IO176NB4F16

IO176PB4F16

IO177NB4F16

IO177PB4F16

IO178NB4F16

IO178PB4F16

IO179PB4F16

IO180NB4F16

AG29

AG30

AF24

AF25

AG25

AG26

AJ25

AJ26

AK26

AK27

AE23

AE24

AH24

AH25

AD23

AC23

AJ27

AG23

AF29

AF30

AB25

AA25

AE30

AD30

AE29

AD29

AD27

AC27

3-64

Revision 18

Axcelerator Family FPGAs

FG896

AX2000 Function

IO180PB4F16

IO181NB4F17

IO181PB4F17

IO182NB4F17

IO182PB4F17

IO183NB4F17

IO183PB4F17

IO184NB4F17

IO184PB4F17

IO185NB4F17

IO185PB4F17

IO187NB4F17

IO187PB4F17

IO188NB4F17

IO188PB4F17

IO189PB4F17

IO190NB4F17

IO190PB4F17

IO191NB4F17

IO191PB4F17

IO192NB4F17

IO192PB4F17

IO195NB4F18

IO195PB4F18

IO196NB4F18

IO196PB4F18

IO197NB4F18

IO197PB4F18

IO198NB4F18

IO198PB4F18

IO199NB4F18

IO199PB4F18

IO200NB4F18

IO200PB4F18

IO201NB4F18

Number

AX2000 Function

IO201PB4F18

Number

AX2000 Function

Number

AH11

AH12

AC13

AD13

AE12

AE13

AG11

AG12

AK11

AK12

AC12

AD12

AE11

AF11

AJ10

AJ11

AC11

AD11

AK9

AG24

AK24

AK25

AD22

AC22

AF22

AF23

AE21

AE22

AJ23

AJ24

AH22

AH23

AD21

AC21

AK22

AF20

AF21

AG21

AG22

AE19

AE20

AK21

AJ21

AD19

AD20

AJ20

AK20

AC19

AC20

AG19

AG20

AH19

AH20

AK19

AJ19

AC18

AB18

AE18

AD18

AJ17

AJ18

AE17

AD17

AK17

AC17

AB17

AJ16

AK16

AG18

AH18

AG16

AG17

IO225NB5F21

IO225PB5F21

IO226NB5F21

IO226PB5F21

IO227NB5F21

IO227PB5F21

IO228NB5F21

IO228PB5F21

IO229NB5F21

IO229PB5F21

IO230NB5F21

IO230PB5F21

IO232NB5F21

IO232PB5F21

IO233NB5F21

IO233PB5F21

IO234NB5F21

IO234PB5F21

IO236NB5F22

IO236PB5F22

IO237NB5F22

IO237PB5F22

IO238NB5F22

IO238PB5F22

IO239NB5F22

IO239PB5F22

IO240NB5F22

IO240PB5F22

IO242NB5F22

IO242PB5F22

IO243NB5F22

IO243PB5F22

IO244NB5F22

IO244PB5F22

IO245NB5F23

IO202NB4F18

IO202PB4F18

IO206NB4F19

IO206PB4F19

IO207NB4F19

IO207PB4F19

IO208NB4F19

IO208PB4F19

IO209NB4F19

IO210NB4F19

IO210PB4F19

IO211NB4F19

IO211PB4F19

IO212NB4F19/CLKEN

IO212PB4F19/CLKEP

IO213NB4F19/CLKFN

IO213PB4F19/CLKFP

Bank 5

IO214NB5F20/CLKGN

IO214PB5F20/CLKGP

IO215NB5F20/CLKHN

IO215PB5F20/CLKHP

IO216NB5F20

AG14

AG15

AG13

AH13

AB14

AC15

AK15

AJ15

AE14

AD14

AK14

AJ14

AB13

AC14

AJ12

AJ13

AK10

AG9

AG10

AF9

AF10

AH8

IO216PB5F20

IO217NB5F20

AH9

IO217PB5F20

AC10

AD10

AE9

IO218NB5F20

IO218PB5F20

IO219NB5F20

AE10

AJ7

IO219PB5F20

IO222NB5F20

AJ8

IO222PB5F20

AK6

IO223NB5F21

AK7

IO223PB5F21

AF8

Revision 18

3-65

Package Pin Assignments

FG896

AX2000 Function

IO245PB5F23

IO246NB5F23

IO246PB5F23

IO247NB5F23

IO247PB5F23

IO248NB5F23

IO249NB5F23

IO249PB5F23

IO250NB5F23

IO250PB5F23

IO251NB5F23

IO251PB5F23

IO252NB5F23

IO252PB5F23

IO253NB5F23

IO253PB5F23

IO254NB5F23

IO254PB5F23

IO255NB5F23

IO255PB5F23

IO256NB5F23

IO256PB5F23

Bank 6

Number

AX2000 Function

IO263NB6F24

IO263PB6F24

IO264NB6F24

IO264PB6F24

IO265NB6F24

IO265PB6F24

IO266NB6F24

IO266PB6F24

IO267NB6F25

IO267PB6F25

IO268NB6F25

IO268PB6F25

IO269NB6F25

IO269PB6F25

IO270NB6F25

IO270PB6F25

IO271NB6F25

IO271PB6F25

IO272NB6F25

IO272PB6F25

IO273NB6F25

IO273PB6F25

IO274NB6F25

IO274PB6F25

IO275NB6F25

IO275PB6F25

IO277NB6F25

IO277PB6F25

IO278NB6F26

IO278PB6F26

IO279NB6F26

IO279PB6F26

IO280NB6F26

IO280PB6F26

IO281NB6F26

Number

AX2000 Function

IO281PB6F26

IO282NB6F26

IO282PB6F26

IO284NB6F26

IO284PB6F26

IO285NB6F26

IO285PB6F26

IO286NB6F26

IO286PB6F26

IO287NB6F26

IO287PB6F26

IO288NB6F26

IO288PB6F26

IO290NB6F27

IO290PB6F27

IO291NB6F27

IO291PB6F27

IO292NB6F27

IO292PB6F27

IO293NB6F27

IO293PB6F27

IO294NB6F27

IO294PB6F27

IO296NB6F27

IO296PB6F27

IO298NB6F27

IO298PB6F27

IO299NB6F27

IO299PB6F27

Bank 7

Number

AG8

AD8

AD9

AG7

AH7

AK5

AJ5

AD3

AE3

AB6

AC6

AD1

AE1

AA8

AB8

AB5

AC5

AB3

AC3

AC2

AD2

AJ6

AC8

AC9

AH6

AG6

AF6

AF7

AG2

AG1

AE7

AE8

AG5

AH5

AJ4

AA7

AA4

AB4

AA6

AB1*

AE2*

AK4

IO257NB6F24

IO257PB6F24

IO258NB6F24

IO258PB6F24

IO259NB6F24

IO259PB6F24

IO260NB6F24

IO260PB6F24

IO261NB6F24

IO261PB6F24

IO262NB6F24

IO262PB6F24

AE4

AF4

AB7

AC7

AD5

AE5

AF1

AF2

AF3

AG3

AC4

AD4

AA5

AA2

AA1

IO300NB7F28

IO300PB7F28

IO302NB7F28

IO302PB7F28

IO303NB7F28

3-66

Revision 18

Axcelerator Family FPGAs

FG896

AX2000 Function

IO303PB7F28

IO304NB7F28

IO304PB7F28

IO306NB7F28

IO306PB7F28

IO307NB7F28

IO307PB7F28

IO308NB7F28

IO308PB7F28

IO309NB7F28

IO309PB7F28

IO310NB7F29

IO310PB7F29

IO311NB7F29

IO311PB7F29

IO312NB7F29

IO312PB7F29

IO313NB7F29

IO313PB7F29

IO315NB7F29

IO315PB7F29

IO316NB7F29

IO316PB7F29

IO317NB7F29

IO317PB7F29

IO318NB7F29

IO318PB7F29

IO320NB7F29

IO320PB7F29

IO321NB7F30

IO321PB7F30

IO322NB7F30

IO322PB7F30

IO323NB7F30

IO323PB7F30

Number

AX2000 Function

IO324NB7F30

IO324PB7F30

IO326NB7F30

IO326PB7F30

IO327NB7F30

IO327PB7F30

IO328NB7F30

IO328PB7F30

IO329NB7F30

IO329PB7F30

IO330NB7F30

IO330PB7F30

IO331NB7F30

IO331PB7F30

IO332NB7F31

IO332PB7F31

IO333NB7F31

IO333PB7F31

IO334NB7F31

IO334PB7F31

IO335NB7F31

IO335PB7F31

IO336NB7F31

IO336PB7F31

IO337NB7F31

IO337PB7F31

IO338NB7F31

IO338PB7F31

IO339NB7F31

IO339PB7F31

IO340NB7F31

IO340PB7F31

IO341NB7F31

IO341PB7F31

Number

AX2000 Function

Number

GND

A13

A18

G1*

K2*

A23

A29

AA10

AA21

AA28

AA3

AB2

AB22

AB29

AB9

AC1

AC30

AE25

AE6

AF26

AF5

AG27

AG4

AH10

AH15

AH16

AH21

AH28

AH3

AJ1

AJ2

AJ22

AJ29

AJ30

AJ9

Dedicated I/O

AK13

Revision 18

3-67

Package Pin Assignments

FG896

AX2000 Function

GND

Number

AX2000 Function

GND

Number

AX2000 Function

GND

Number

AK18

AK2

AK23

AK29

AK8

M13

M14

M15

M16

M17

M18

M19

T12

T13

T14

T15

T16

T17

T18

T19

T28

B22

B29

B30

N12

N13

N14

N15

N16

N17

N18

N19

N30

P12

P13

P14

P15

P16

P17

P18

P19

R12

R13

R14

R15

R16

R17

R18

R19

R28

U12

U13

U14

U15

U16

U17

U18

U19

C10

C15

C16

C21

C28

D27

D28

V12

V13

V14

V15

V16

V17

V18

V19

V30

W12

W13

W14

W15

W16

W17

W18

E26

H30

J22

J29

K10

K21

K28

L11

L20

M12

3-68

Revision 18

Axcelerator Family FPGAs

FG896

AX2000 Function

GND

Number

AX2000 Function

VCCA

Number

AX2000 Function

Number

G16

T25

W19

Y11

Y20

U11

U20

V11

VCCDA

VCCIB0

VCCIB1

VCCIB2

VCCIB3

GND

VCCA

GND

VCCA

GND/LP

PRA

VCCA

V20

W11

W20

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

AD24

AD7

AE15

AE16

AF12

AF13

AF15

AF18

AF19

AH27

AH4

C13

C27

G15

D16

AB16

AF16

VCCA

PRB

VCCA

J10

PRC

VCCA

J11

PRD

VCCA

J12

TCK

VCCA

K11

K12

K13

K14

K15

A28

B28

J19

TDI

VCCA

TDO

VCCA

TMS

VCCA

TRST

VCCA

AD6

AH26

E28

VCCA

VCCDA

J20

L12

L13

L14

L15

L16

L17

L18

L19

M11

M20

N11

N20

P11

P20

R11

R20

T11

T20

J21

K16

K17

K18

K19

K20

C29

C30

K22

L21

L22

M21

M22

N21

P21

R21

AA22

AH29

D13

D19

E18

F15

F16

F26

Note: *Not routed on the same package layer and to adjacent LGA pads as its differential pair complement.

Recommended to be used as a single-ended I/O.

Revision 18

3-69

Package Pin Assignments

FG896

AX2000 Function

VCCIB3

VCCIB4

VCCIB5

VCCIB6

Number

AX2000 Function

VCCIB6

Number

AH30

T21

Y10

VCCIB6

U21

VCCIB6

V21

VCCIB7

W21

W22

Y21

VCCIB7

L10

Y22

VCCIB7

AA16

AA17

AA18

AA19

AA20

AB19

AB20

AB21

AJ28

AK28

AA11

AA12

AA13

AA14

AA15

AB10

AB11

AB12

AJ3

VCCIB7

M10

VCCIB7

N10

P10

R10

G14

H15

G17

J16

VCCIB7

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

VCCPLH

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

AH17

AC16

AH14

AD15

F14

J15

F17

H16

AF17

AD16

AF14

AB15

G24

AK3

AA9

AH1

AH2

T10

U10

V10

W10

3-70

Revision 18

Axcelerator Family FPGAs

FG1152

A1 Ball Pad Corner

34 33 32 31 3029 282726 25 2423 2221 20 1918 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.microsemi.com/soc/products/rescenter/package/index.html.

Revision 18

3-71

Package Pin Assignments

FG1152

AX2000 Function

Bank 0

Number

AX2000 Function

IO17NB0F1

IO17PB0F1

IO18NB0F1

IO18PB0F1

IO19NB0F1

IO19PB0F1

IO20NB0F1

IO20PB0F1

IO21NB0F1

IO21PB0F1

IO22NB0F2

IO22PB0F2

IO23NB0F2

IO23PB0F2

IO24NB0F2

IO24PB0F2

IO25NB0F2

IO25PB0F2

IO26NB0F2

IO26PB0F2

IO27NB0F2

IO27PB0F2

IO28NB0F2

IO28PB0F2

IO29NB0F2

IO29PB0F2

IO30NB0F2

IO30PB0F2

IO31NB0F2

IO31PB0F2

IO32NB0F2

IO32PB0F2

IO33NB0F2

IO33PB0F2

IO34NB0F3

Number

AX2000 Function

IO34PB0F3

Number

F12

F11

E11

E10

F13

G13

A10

D14

A15

B15

B16

A16

G16

G15

D16

C16

K16

L16

D17

C17

E16

F16

G17

F17

IO00NB0F0

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO03NB0F0

IO03PB0F0

IO04NB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO07NB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO09NB0F0

IO09PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO35NB0F3

IO35PB0F3

H10

IO36NB0F3

IO36PB0F3

IO37NB0F3

IO37PB0F3

IO38NB0F3

K14

K13

B11

B10

C12

C11

A12

A11

H14

J14

D13

D12

F14

G14

E14

E13

B13

B12

C14

C13

H15

J15

A14

B14

K15

L15

D15

IO38PB0F3

IO39NB0F3

IO39PB0F3

K10

J10

IO40NB0F3

IO40PB0F3

IO41NB0F3/HCLKAN

IO41PB0F3/HCLKAP

IO42NB0F3/HCLKBN

IO42PB0F3/HCLKBP

Bank 1

F10

G10

IO43NB1F4/HCLKCN

IO43PB1F4/HCLKCP

IO44NB1F4/HCLKDN

IO44PB1F4/HCLKDP

IO45NB1F4

G19

G18

E19

F19

C18

D18

A18

B18

K19

L19

C19

D19

K20

L20

A19

B19

H20

J11

K11

K12

J12

G11

H11

G12

H12

IO45PB1F4

IO46NB1F4

IO46PB1F4

IO47NB1F4

IO47PB1F4

IO48NB1F4

IO48PB1F4

IO49NB1F4

H13

J13

IO49PB1F4

IO50NB1F4

IO50PB1F4

IO51NB1F4

3-72

Revision 18

Axcelerator Family FPGAs

FG1152

AX2000 Function

IO51PB1F4

IO52NB1F4

IO52PB1F4

IO53NB1F4

IO53PB1F4

IO54NB1F5

IO54PB1F5

IO55NB1F5

IO55PB1F5

IO56NB1F5

IO56PB1F5

IO57NB1F5

IO57PB1F5

IO58NB1F5

IO58PB1F5

IO59NB1F5

IO59PB1F5

IO60NB1F5

IO60PB1F5

IO61NB1F5

IO61PB1F5

IO62NB1F5

IO62PB1F5

IO63NB1F5

IO63PB1F5

IO64NB1F6

IO64PB1F6

IO65NB1F6

IO65PB1F6

IO66NB1F6

IO66PB1F6

IO67NB1F6

IO67PB1F6

IO68NB1F6

IO68PB1F6

Number

AX2000 Function

IO69NB1F6

IO69PB1F6

IO70NB1F6

IO70PB1F6

IO71NB1F6

IO71PB1F6

IO72NB1F6

IO72PB1F6

IO73NB1F6

IO73PB1F6

IO74NB1F6

IO74PB1F6

IO75NB1F6

IO75PB1F6

IO76NB1F7

IO76PB1F7

IO77NB1F7

IO77PB1F7

IO78NB1F7

IO78PB1F7

IO79NB1F7

IO79PB1F7

IO80NB1F7

IO80PB1F7

IO81NB1F7

IO81PB1F7

IO82NB1F7

IO82PB1F7

IO83NB1F7

IO83PB1F7

IO84NB1F7

IO84PB1F7

IO85NB1F7

IO85PB1F7

Bank 2

Number

AX2000 Function

Number

J20

B20

A20

F20

E20

B21

A21

K21

J21

C27

C26

H24

G24

H23

G23

B28

A28

E26

E25

F26

F25

K25

K24

D27

D26

B29

A29

D28

C28

H25

G25

F27

E27

J25

IO86NB2F8

IO86PB2F8

IO87NB2F8

IO87PB2F8

IO88NB2F8

IO88PB2F8

IO89NB2F8

IO89PB2F8

IO90NB2F8

IO90PB2F8

IO91NB2F8

IO91PB2F8

IO92NB2F8

IO92PB2F8

IO93NB2F8

IO93PB2F8

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

IO96NB2F9

IO96PB2F9

IO97NB2F9

IO97PB2F9

IO98NB2F9

IO98PB2F9

IO99NB2F9

IO99PB2F9

IO100NB2F9

IO100PB2F9

IO101NB2F9

IO101PB2F9

IO102NB2F9

IO102PB2F9

IO103NB2F9

J28

J27

M25

L25

L26

K26

G31

F31

H29

G29

K28

K27

J30

D21

C21

G22

G21

E22

E21

D22

C22

B23

A23

H22

H21

C24

C23

F23

F22

B24

A24

J22

H30

L28

L27

K29

J29

K31

J31

J32

H32

M27

M26

L30

K30

N25

N26

M29

L29

L33

L32

K34

K33

N28

J24

D29

C29

H26

G26

F28

E28

H27

G27

K22

B25

A25

K23

J23

F24

E24

Revision 18

3-73

Package Pin Assignments

FG1152

AX2000 Function

IO103PB2F9

IO104NB2F9

IO104PB2F9

IO105NB2F9

IO105PB2F9

IO106NB2F9

IO106PB2F9

IO107NB2F10

IO107PB2F10

IO108NB2F10

IO108PB2F10

IO109NB2F10

IO109PB2F10

IO110NB2F10

IO110PB2F10

IO111NB2F10

IO111PB2F10

IO112NB2F10

IO112PB2F10

IO113NB2F10

IO113PB2F10

IO114NB2F10

IO114PB2F10

IO115NB2F10

IO115PB2F10

IO116NB2F10

IO116PB2F10

IO117NB2F10

IO117PB2F10

IO118NB2F11

IO118PB2F11

IO119NB2F11

IO119PB2F11

IO120NB2F11

IO120PB2F11

Number

AX2000 Function

IO121NB2F11

IO121PB2F11

IO122NB2F11

IO122PB2F11

IO123NB2F11

IO123PB2F11

IO124NB2F11

IO124PB2F11

IO125NB2F11

IO125PB2F11

IO126NB2F11

IO126PB2F11

IO127NB2F11

IO127PB2F11

IO128NB2F11

IO128PB2F11

Bank 3

Number

AX2000 Function

IO138NB3F12

IO138PB3F12

IO139NB3F13

IO139PB3F13

IO140NB3F13

IO140PB3F13

IO141NB3F13

IO141PB3F13

IO142NB3F13

IO142PB3F13

IO143NB3F13

IO143PB3F13

IO144NB3F13

IO144PB3F13

IO145NB3F13

IO145PB3F13

IO146NB3F13

IO146PB3F13

IO147NB3F13

IO147PB3F13

IO148NB3F13

IO148PB3F13

IO149NB3F13

IO149PB3F13

IO150NB3F14

IO150PB3F14

IO151NB3F14

IO151PB3F14

IO152NB3F14

IO152PB3F14

IO153NB3F14

IO153PB3F14

IO154NB3F14

IO154PB3F14

IO155NB3F14

Number

M28

M34

L34

P27

N27

M32

M31

P25

P26

N33

M33

P29

N29

P30

N30

R24

R25

P31

N31

R28

P28

P32

N32

R30

R29

P34

P33

R27

R26

R34

R33

T24

T25

T33

T34

T27

T26

T30

T29

U28

T28

T31

T32

U24

U25

U33

U34

U26

U27

U31

U32

Y29

W29

Y27

W27

AA33

Y33

Y25

Y24

AA31

Y31

AA28

Y28

AA34

Y34

AA26

Y26

AA29

AA30

AB30

AB29

AB32

AA32

AB27

AA27

AC31

AB31

AD33

AC33

AC28

AB28

AB25

AA25

AD32

AC32

AD29

IO129NB3F12

IO129PB3F12

IO130NB3F12

IO130PB3F12

IO131NB3F12

IO131PB3F12

IO132NB3F12

IO132PB3F12

IO133NB3F12

IO133PB3F12

IO134NB3F12

IO134PB3F12

IO135NB3F12

IO135PB3F12

IO136NB3F12

IO136PB3F12

IO137NB3F12

IO137PB3F12

V29

U29

V31

V32

V24

V25

W28

V28

W26

V26

W33

V33

W25

W24

W31

W32

Y30

W30

3-74

Revision 18

Axcelerator Family FPGAs

FG1152

AX2000 Function

IO155PB3F14

IO156NB3F14

IO156PB3F14

IO157NB3F14

IO157PB3F14

IO158NB3F14

IO158PB3F14

IO159NB3F14

IO159PB3F14

IO160NB3F14

IO160PB3F14

IO161NB3F15

IO161PB3F15

IO162NB3F15

IO162PB3F15

IO163NB3F15

IO163PB3F15

IO164NB3F15

IO164PB3F15

IO165NB3F15

IO165PB3F15

IO166NB3F15

IO166PB3F15

IO167NB3F15

IO167PB3F15

IO168NB3F15

IO168PB3F15

IO169NB3F15

IO169PB3F15

IO170NB3F15

IO170PB3F15

Bank 4

Number

AX2000 Function

IO172PB4F16

IO173NB4F16

IO173PB4F16

IO174NB4F16

IO174PB4F16

IO175NB4F16

IO175PB4F16

IO176NB4F16

IO176PB4F16

IO177NB4F16

IO177PB4F16

IO178NB4F16

IO178PB4F16

IO179NB4F16

IO179PB4F16

IO180NB4F16

IO180PB4F16

IO181NB4F17

IO181PB4F17

IO182NB4F17

IO182PB4F17

IO183NB4F17

IO183PB4F17

IO184NB4F17

IO184PB4F17

IO185NB4F17

IO185PB4F17

IO186NB4F17

IO186PB4F17

IO187NB4F17

IO187PB4F17

IO188NB4F17

IO188PB4F17

IO189NB4F17

IO189PB4F17

Number

AX2000 Function

Number

AH22

AH23

AJ23

AJ24

AG21

AG22

AP23

AP24

AN22

AN23

AM23

AL23

AF21

AF22

AL22

AM22

AE21

AE22

AJ21

AJ22

AK21

AK22

AM21

AL21

AE20

AD20

AN21

AP21

AP20

AN20

AN19

AP19

AG20

AF20

AL19

AC29

AE30

AD30

AC26

AB26

AH33

AG33

AD27

AC27

AG32

AF32

AG31

AF31

AF29

AE29

AE28

AD28

AG30

AF30

AE26

AD26

AJ30

AH30

AG28

AF28

AF27

AE27

AH29

AG29

AD25

AC25

AH27

AJ27

AJ28

AL27

AL28

AM28

AM29

AG25

AG26

AK26

AK27

AF25

AE25

AP28

AN28

AJ25

AJ26

AM26

AM27

AF24

AE24

AH24

AH25

AG23

AG24

AL25

AL26

AP25

AP26

AK24

AK25

AF23

AE23

AN24

AM24

IO190NB4F17

IO190PB4F17

IO191NB4F17

IO191PB4F17

IO192NB4F17

IO192PB4F17

IO193NB4F18

IO193PB4F18

IO194NB4F18

IO194PB4F18

IO195NB4F18

IO195PB4F18

IO196NB4F18

IO196PB4F18

IO197NB4F18

IO197PB4F18

IO198NB4F18

IO198PB4F18

IO199NB4F18

IO199PB4F18

IO200NB4F18

IO200PB4F18

IO201NB4F18

IO201PB4F18

IO202NB4F18

IO202PB4F18

IO203NB4F19

IO203PB4F19

IO204NB4F19

IO204PB4F19

IO205NB4F19

IO205PB4F19

IO206NB4F19

IO206PB4F19

IO207NB4F19

IO171NB4F16

IO171PB4F16

IO172NB4F16

AP29

AN29

AH26

Revision 18

3-75

Package Pin Assignments

FG1152

AX2000 Function

IO207PB4F19

Number

AX2000 Function

IO224PB5F21

IO225NB5F21

IO225PB5F21

IO226NB5F21

IO226PB5F21

IO227NB5F21

IO227PB5F21

IO228NB5F21

IO228PB5F21

IO229NB5F21

IO229PB5F21

IO230NB5F21

IO230PB5F21

IO231NB5F21

IO231PB5F21

IO232NB5F21

IO232PB5F21

IO233NB5F21

IO233PB5F21

IO234NB5F21

IO234PB5F21

IO235NB5F22

IO235PB5F22

IO236NB5F22

IO236PB5F22

IO237NB5F22

IO237PB5F22

IO238NB5F22

IO238PB5F22

IO239NB5F22

IO239PB5F22

IO240NB5F22

IO240PB5F22

IO241NB5F22

IO241PB5F22

Number

AX2000 Function

IO242NB5F22

IO242PB5F22

IO243NB5F22

IO243PB5F22

IO244NB5F22

IO244PB5F22

IO245NB5F23

IO245PB5F23

IO246NB5F23

IO246PB5F23

IO247NB5F23

IO247PB5F23

IO248NB5F23

IO248PB5F23

IO249NB5F23

IO249PB5F23

IO250NB5F23

IO250PB5F23

IO251NB5F23

IO251PB5F23

IO252NB5F23

IO252PB5F23

IO253NB5F23

IO253PB5F23

IO254NB5F23

IO254PB5F23

IO255NB5F23

IO255PB5F23

IO256NB5F23

IO256PB5F23

Bank 6

Number

AL20

AG19

AF19

AN18

AP18

AE19

AD19

AL18

AM18

AJ20

AK20

AJ18

AJ19

AP14

AK13

AK14

AE15

AF15

AG14

AG15

AJ13

AJ14

AM13

AM14

AE14

AF14

AN12

AP12

AG13

AH13

AL12

AL13

AE13

AF13

AN11

AP11

AM11

AM12

AJ11

AG11

AG12

AL9

IO208NB4F19

IO208PB4F19

IO209NB4F19

AL10

AM8

AM9

AH10

AJ10

AF10

AF11

AJ9

IO209PB4F19

IO210NB4F19

IO210PB4F19

IO211NB4F19

IO211PB4F19

IO212NB4F19/CLKEN

IO212PB4F19/CLKEP

IO213NB4F19/CLKFN

IO213PB4F19/CLKFP

Bank 5

AK9

AN7

AP7

AL7

IO214NB5F20/CLKGN

IO214PB5F20/CLKGP

IO215NB5F20/CLKHN

IO215PB5F20/CLKHP

IO216NB5F20

AJ16

AJ17

AJ15

AK15

AD16

AE17

AM17

AL17

AG16

AF16

AM16

AL16

AP16

AN16

AN15

AP15

AD15

AE16

AL14

AL15

AN14

AL8

AE10

AE11

AK8

AJ8

IO216PB5F20

IO217NB5F20

AH8

AH9

AN6

AP6

AG9

AG10

AJ7

IO217PB5F20

IO218NB5F20

IO218PB5F20

IO219NB5F20

IO219PB5F20

IO220NB5F20

AJ12

AH11

AH12

AK10

AK11

AE12

AF12

AN10

AP10

IO220PB5F20

AK7

AL6

IO221NB5F20

IO221PB5F20

AM6

IO222NB5F20

IO222PB5F20

IO257NB6F24

IO257PB6F24

IO258NB6F24

IO258PB6F24

AG6

AH6

AD9

AE9

IO223NB5F21

IO223PB5F21

IO224NB5F21

3-76

Revision 18

Axcelerator Family FPGAs

FG1152

AX2000 Function

IO259NB6F24

IO259PB6F24

IO260NB6F24

IO260PB6F24

IO261NB6F24

IO261PB6F24

IO262NB6F24

IO262PB6F24

IO263NB6F24

IO263PB6F24

IO264NB6F24

IO264PB6F24

IO265NB6F24

IO265PB6F24

IO266NB6F24

IO266PB6F24

IO267NB6F25

IO267PB6F25

IO268NB6F25

IO268PB6F25

IO269NB6F25

IO269PB6F25

IO270NB6F25

IO270PB6F25

IO271NB6F25

IO271PB6F25

IO272NB6F25

IO272PB6F25

IO273NB6F25

IO273PB6F25

IO274NB6F25

IO274PB6F25

IO275NB6F25

IO275PB6F25

IO276NB6F25

Number

AX2000 Function

IO276PB6F25

IO277NB6F25

IO277PB6F25

IO278NB6F26

IO278PB6F26

IO279NB6F26

IO279PB6F26

IO280NB6F26

IO280PB6F26

IO281NB6F26

IO281PB6F26

IO282NB6F26

IO282PB6F26

IO283NB6F26

IO283PB6F26

IO284NB6F26

IO284PB6F26

IO285NB6F26

IO285PB6F26

IO286NB6F26

IO286PB6F26

IO287NB6F26

IO287PB6F26

IO288NB6F26

IO288PB6F26

IO289NB6F27

IO289PB6F27

IO290NB6F27

IO290PB6F27

IO291NB6F27

IO291PB6F27

IO292NB6F27

IO292PB6F27

IO293NB6F27

IO293PB6F27

Number

AX2000 Function

Number

V10

V11

AF7

AG7

AH3

AH4

AH5

AJ5

AD2

AC4

AC3

AA8

AA9

AB5

AB6

Y10

Y11

AB3

AB4

IO294NB6F27

IO294PB6F27

IO295NB6F27

IO295PB6F27

IO296NB6F27

IO296PB6F27

IO297NB6F27

IO297PB6F27

IO298NB6F27

IO298PB6F27

IO299NB6F27

IO299PB6F27

AE6

AF6

AF5

AG5

AD8

AE8

AF3

AG3

AC10

AD10

AD7

AE7

AD5

AE5

AE4

AF4

AB9

AC9

AC6

AD6

AB8

AC8

AE1

AE2

AA10

AB10

AB7

AC7

AD1

AA7

AC2

AC1

Bank 7

IO300NB7F28

IO300PB7F28

IO301NB7F28

IO301PB7F28

IO302NB7F28

IO302PB7F28

IO303NB7F28

IO303PB7F28

IO304NB7F28

IO304PB7F28

IO305NB7F28

IO305PB7F28

IO306NB7F28

IO306PB7F28

IO307NB7F28

IO307PB7F28

IO308NB7F28

IO308PB7F28

IO309NB7F28

IO309PB7F28

IO310NB7F29

IO310PB7F29

U10

U11

AA5

AA6

W10

W11

AA3

AA4

AA1

AA2

T11

T10

Revision 18

3-77

Package Pin Assignments

FG1152

AX2000 Function

IO311NB7F29

IO311PB7F29

IO312NB7F29

IO312PB7F29

IO313NB7F29

IO313PB7F29

IO314NB7F29

IO314PB7F29

IO315NB7F29

IO315PB7F29

IO316NB7F29

IO316PB7F29

IO317NB7F29

IO317PB7F29

IO318NB7F29

IO318PB7F29

IO319NB7F29

IO319PB7F29

IO320NB7F29

IO320PB7F29

IO321NB7F30

IO321PB7F30

IO322NB7F30

IO322PB7F30

IO323NB7F30

IO323PB7F30

IO324NB7F30

IO324PB7F30

IO325NB7F30

IO325PB7F30

IO326NB7F30

IO326PB7F30

IO327NB7F30

IO327PB7F30

IO328NB7F30

Number

AX2000 Function

IO328PB7F30

IO329NB7F30

IO329PB7F30

IO330NB7F30

IO330PB7F30

IO331NB7F30

IO331PB7F30

IO332NB7F31

IO332PB7F31

IO333NB7F31

IO333PB7F31

IO334NB7F31

IO334PB7F31

IO335NB7F31

IO335PB7F31

IO336NB7F31

IO336PB7F31

IO337NB7F31

IO337PB7F31

IO338NB7F31

IO338PB7F31

IO339NB7F31

IO339PB7F31

IO340NB7F31

IO340PB7F31

IO341NB7F31

IO341PB7F31

Dedicated I/O

GND

Number

AX2000 Function

GND

Number

R10

R11

A33

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AB1

M10

AB13

AB22

AB34

AC12

AC23

AC30

AC5

P10

AD11

AD24

AD31

AD4

AE3

AE32

AF2

AF33

AG1

A13

AG27

AG34

AG8

GND

A22

A27

GND

AH28

AH7

GND

A31

A32

AJ29

AJ6

N10

GND

3-78

Revision 18

Axcelerator Family FPGAs

FG1152

AX2000 Function

GND

Number

AX2000 Function

GND

Number

AX2000 Function

Number

AK12

AK17

AK18

AK23

AK30

AK5

AN34

AN4

AN9

AP13

AP2

AP22

AP27

AP3

AP31

AP32

AP33

AP4

AP8

GND

D11

D24

D31

D32

D33

D34

AL1

AL11

AL2

AL24

AL3

E12

E17

E18

E23

E30

AL31

AL32

AL33

AL34

AL4

B26

AM1

F29

F30

AM10

AM15

AM2

B31

B32

B33

B34

G28

AM20

AM25

AM3

H34

AM31

AM32

AM33

AM34

AM4

C10

C15

J33

K32

L11

L24

L31

C20

C25

AN1

AN2

AN26

AN3

C31

C32

C33

C34

M12

M23

M30

AN31

AN32

AN33

Revision 18

3-79

Package Pin Assignments

FG1152

AX2000 Function

GND

Number

AX2000 Function

GND

GND/LP

Number

AX2000 Function

Number

U19

U20

U21

U30

A26

AB2

N13

N22

N34

P14

P15

P16

P17

P18

P19

P20

P21

R14

R15

R16

R17

R18

R19

R20

R21

AB33

AC34

AD3

V14

V15

V16

V17

V18

V19

V20

V21

V30

AD34

AE31

AE33

AE34

AF1

AF34

AG2

AG4

AH1

AH2

W14

W15

W16

W17

W18

W19

W20

W21

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

AH31

AH32

AH34

AJ1

AJ2

AJ3

R32

T14

T15

T16

T17

T18

T19

T20

T21

U14

U15

U16

U17

U18

AJ31

AJ32

AJ33

AJ34

AJ4

AL29

AM19

AM7

AN13

AN17

AN25

AN27

AN8

Y32

A17

AP17

3-80

Revision 18

Axcelerator Family FPGAs

FG1152

AX2000 Function

Number

AX2000 Function

PRB

Number

AX2000 Function

Number

PRA

AP9

B17

B22

B27

F18

AD18

AH18

VCCA

T22

PRC

U13

U22

V13

V22

W13

W22

Y13

Y22

AF26

AF9

AG17

AG18

AH14

AH15

AH17

AH20

AH21

AK29

AK6

E15

E29

PRD

VCCA

TCK

VCCA

TDI

VCCA

D10

D20

D23

D25

TDO

L10

VCCA

TMS

VCCA

TRST

VCCA

AA13

AA22

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

AF8

AK28

G30

VCCA

VCCDA

VCCIB0

F32

F33

F34

G32

G33

G34

H31

H33

J34

N14

N15

N16

N17

N18

N19

N20

N21

P13

F15

F21

G20

H17

H18

H28

J18

R31

V34

W34

J17

P22

V27

R13

R22

T13

Revision 18

3-81

Package Pin Assignments

FG1152

AX2000 Function

VCCIB0

VCCIB1

VCCIB2

VCCIB3

Number

AX2000 Function

VCCIB3

VCCIB4

VCCIB5

Number

AX2000 Function

VCCIB6

VCCIB7

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

VCCPLH

VCOMPLA

VCOMPLB

VCOMPLC

Number

AA24

AB23

AB24

AC24

AK31

AK32

AK33

AK34

V23

AA11

AA12

AB11

AB12

AC11

AK1

AK2

AK3

AK4

V12

W12

Y12

L12

L13

L14

M13

M14

M15

M16

M17

A30

B30

C30

D30

L21

L22

L23

M18

M19

M20

M21

M22

E31

E32

E33

E34

M24

N23

N24

P23

P24

R23

T23

U23

AA23

W23

Y23

AC18

AC19

AC20

AC21

AC22

AD21

AD22

AD23

AL30

AM30

AN30

AP30

AC13

AC14

AC15

AC16

AC17

AD12

AD13

AD14

AL5

M11

N11

N12

P11

P12

R12

T12

U12

J16

K17

J19

L18

AK19

AE18

AK16

AF17

H16

L17

AM5

AN5

AP5

H19

3-82

Revision 18

Axcelerator Family FPGAs

FG1152

AX2000 Function

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

Number

K18

AH19

AF18

AH16

AD17

J26

Revision 18

3-83

Package Pin Assignments

PQ208

208

208-Pin PQFP

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.microsemi.com/soc/products/rescenter/package/index.html.

3-84

Revision 18

Axcelerator Family FPGAs

PQ208

AX250 Function

PQ208

Number

AX250 Function

Bank 0

IO02NB0F0

AX250 Function

Number

IO43PB2F2

IO44NB2F2

IO44PB2F2

134

131

133

IO76PB5F5/CLKGP

IO77NB5F5/CLKHN

IO77PB5F5/CLKHP

IO78NB5F5

IO78PB5F5

IO86NB5F5

IO87NB5F5

IO87PB5F5

IO88NB5F5

IO88PB5F5

IO89NB5F5

IO89PB5F5

Bank 6

197

198

199

191

192

185

186

IO03NB0F0

IO03PB0F0

Bank 3

IO12NB0F0/HCLKAN

IO12PB0F0/HCLKAP

IO13NB0F0/HCLKBN

IO13PB0F0/HCLKBP

Bank 1

IO45NB3F3

IO45PB3F3

IO46NB3F3

IO46PB3F3

IO48NB3F3

IO48PB3F3

IO50NB3F3

IO50PB3F3

IO55NB3F3

IO55PB3F3

IO57NB3F3

IO57PB3F3

IO59NB3F3

IO59PB3F3

IO60NB3F3

IO60PB3F3

IO61NB3F3

IO61PB3F3

127

129

126

128

122

123

120

121

116

117

114

115

110

111

108

109

106

107

IO14NB1F1/HCLKCN

IO14PB1F1/HCLKCP

IO15NB1F1/HCLKDN

IO15PB1F1/HCLKDP

IO16NB1F1

180

181

174

175

170

171

165

166

161

162

159

160

IO91NB6F6

IO91PB6F6

IO92NB6F6

IO92PB6F6

IO93NB6F6

IO93PB6F6

IO94PB6F6

IO96NB6F6

IO96PB6F6

IO101NB6F6

IO101PB6F6

IO102PB6F6

IO103NB6F6

IO103PB6F6

IO105NB6F6

IO105PB6F6

IO106NB6F6

IO106PB6F6

Bank 7

IO16PB1F1

IO24NB1F1

IO24PB1F1

IO26NB1F1

IO26PB1F1

IO27NB1F1

IO27PB1F1

Bank 2

IO29NB2F2

151

153

152

154

148

146

147

144

145

139

140

141

137

138

132

Bank 4

IO29PB2F2

IO62NB4F4

IO62PB4F4

100

103

101

102

IO30NB2F2

IO30PB2F2

IO63NB4F4

IO31PB2F2

IO63PB4F4

IO32NB2F2

IO64NB4F4

IO32PB2F2

IO64PB4F4

IO34NB2F2

IO72NB4F4

IO34PB2F2

IO72PB4F4

IO39NB2F2

IO74NB4F4/CLKEN

IO74PB4F4/CLKEP

IO75NB4F4/CLKFN

IO75PB4F4/CLKFP

Bank 5

IO39PB2F2

IO107NB7F7

IO107PB7F7

IO108NB7F7

IO108PB7F7

IO110NB7F7

IO40PB2F2

IO41NB2F2

IO41PB2F2

IO43NB2F2

IO76NB5F5/CLKGN

Revision 18

3-85

Package Pin Assignments

PQ208

AX250 Function

PQ208

AX250 Function

Number

AX250 Function

IO110PB7F7

IO112NB7F7

IO112PB7F7

IO117NB7F7

IO117PB7F7

IO119NB7F7

IO119PB7F7

IO121PB7F7

IO122NB7F7

IO122PB7F7

IO123NB7F7

IO123PB7F7

Dedicated I/O

VCCDA

Number

GND

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

VCCPLH

VCCIB0

187

178

176

GND

113

119

125

136

143

150

155

164

169

173

194

196

201

208

184

183

GND

193

200

163

172

135

149

112

124

GND

VCCIB0

GND

VCCIB1

GND

VCCIB1

GND

VCCIB2

GND

VCCIB2

GND

VCCIB3

VCCDA

GND

VCCIB3

VCCDA

GND/LP

PRA

VCCIB4

VCCDA

VCCIB4

VCCDA

PRB

VCCIB5

VCCDA

PRC

VCCIB5

VCCDA

105

130

157

167

182

202

104

PRD

VCCIB6

VCCDA

TCK

205

204

203

206

207

VCCIB6

VCCDA

TDI

VCCIB7

VCCDA

TDO

VCCIB7

VCCDA

TMS

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

190

188

179

177

VCCDA

TRST

VCCA

VCCPLA

GND

156

GND

158

GND

118

142

168

195

189

GND

3-86

Revision 18

Axcelerator Family FPGAs

PQ208

AX500 Function

Bank 0

Number

AX500 Function

IO61PB2F5

Number

AX500 Function

Number

134

131

133

IO105PB5F10/CLKGP

IO106NB5F10/CLKHN

IO106PB5F10/CLKHP

IO107NB5F10

IO107PB5F10

IO119NB5F11

IO121NB5F11

IO121PB5F11

IO123NB5F11

IO123PB5F11

IO125NB5F11

IO125PB5F11

Bank 6

IO03NB0F0

198

199

197

191

192

185

186

IO62NB2F5

IO62PB2F5

IO03PB0F0

IO04NB0F0

Bank 3

IO19NB0F1/HCLKAN

IO19PB0F1/HCLKAP

IO20NB0F1/HCLKBN

IO20PB0F1/HCLKBP

Bank 1

IO63NB3F6

IO63PB3F6

127

129

126

128

122

123

120

121

116

117

114

115

110

111

108

109

106

107

IO64NB3F6

IO64PB3F6

IO66NB3F6

IO66PB3F6

IO21NB1F2/HCLKCN

IO21PB1F2/HCLKCP

IO22NB1F2/HCLKDN

IO22PB1F2/HCLKDP

IO23NB1F2

180

181

174

175

170

171

165

166

161

162

159

160

IO68NB3F6

IO68PB3F6

IO77NB3F7

IO77PB3F7

IO127NB6F12

IO127PB6F12

IO128NB6F12

IO128PB6F12

IO129NB6F12

IO129PB6F12

IO130PB6F12

IO132NB6F12

IO132PB6F12

IO141NB6F13

IO141PB6F13

IO142PB6F13

IO143NB6F13

IO143PB6F13

IO145NB6F13

IO145PB6F13

IO146NB6F13

IO146PB6F13

Bank 7

IO23PB1F2

IO79NB3F7

IO79PB3F7

IO37NB1F3

IO37PB1F3

IO81NB3F7

IO81PB3F7

IO39NB1F3

IO39PB1F3

IO82NB3F7

IO82PB3F7

IO41NB1F3

IO41PB1F3

IO83NB3F7

IO83PB3F7

Bank 2

IO43NB2F4

151

153

152

154

148

146

147

144

145

139

140

141

137

138

132

Bank 4

IO43PB2F4

IO84PB4F8

103

100

101

102

IO44NB2F4

IO85NB4F8

IO86NB4F8

IO86PB4F8

IO44PB2F4

IO45PB2F4

IO46NB2F4

IO87NB4F8

IO87PB4F8

IO46PB2F4

IO48NB2F4

IO101NB4F9

IO101PB4F9

IO103NB4F9/CLKEN

IO103PB4F9/CLKEP

IO104NB4F9/CLKFN

IO104PB4F9/CLKFP

Bank 5

IO48PB2F4

IO57NB2F5

IO57PB2F5

IO147NB7F14

IO147PB7F14

IO148NB7F14

IO148PB7F14

IO150NB7F14

IO58PB2F5

IO59NB2F5

IO59PB2F5

IO61NB2F5

IO105NB5F10/CLKGN

Revision 18

3-87

Package Pin Assignments

PQ208

AX500 Function

IO150PB7F14

IO152NB7F14

IO152PB7F14

IO161NB7F15

IO161PB7F15

IO163NB7F15

IO163PB7F15

IO165PB7F15

IO166NB7F15

IO166PB7F15

IO167NB7F15

IO167PB7F15

Dedicated I/O

V_CCDA

Number

AX500 Function

GND

Number

AX500 Function

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

VCCPLH

VCCIB0

Number

187

178

176

GND

113

119

125

143

136

150

155

164

169

173

194

196

201

208

184

183

GND

200

193

172

163

149

135

124

112

GND

VCCIB0

GND

VCCIB1

GND

VCCIB1

GND

VCCIB2

GND

VCCIB2

GND

VCCIB3

V_CCDA

GND

VCCIB3

V_CCDA

GND/LP

PRA

VCCIB4

V_CCDA

VCCIB4

V_CCDA

PRB

VCCIB5

V_CCDA

PRC

VCCIB5

V_CCDA

105

130

157

167

182

202

104

PRD

VCCIB6

V_CCDA

TCK

205

204

203

206

207

VCCIB6

V_CCDA

TDI

VCCIB7

V_CCDA

TDO

VCCIB7

V_CCDA

TMS

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

190

188

179

177

V_CCDA

TRST

VCCA

VCCPLA

GND

118

142

156

168

195

189

158

GND

3-88

Revision 18

Axcelerator Family FPGAs

CQ208

156

155

154

153

Pin 1

Ceramic

Tie Bar

208-Pin CQFP

108

107

106

105

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.microsemi.com/soc/products/rescenter/package/index.html.

Revision 18

3-89

Package Pin Assignments

CQ208

AX250 Function

Bank 0

Number

AX250 Function

IO43PB2F2

IO44NB2F2

IO44PB2F2

Bank 3

Number

AX250 Function

IO76PB5F5/CLKGP

IO77NB5F5/CLKHN

IO77PB5F5/CLKHP

IO78NB5F5

IO78PB5F5

IO86NB5F5

IO87NB5F5

IO87PB5F5

IO88NB5F5

IO88PB5F5

IO89NB5F5

IO89PB5F5

Bank 6

Number

134

131

133

IO02NB0F0

197

198

199

191

192

185

186

IO03NB0F0

IO03PB0F0

IO12NB0F0/HCLKAN

IO12PB0F0/HCLKAP

IO13NB0F0/HCLKBN

IO13PB0F0/HCLKBP

Bank 1

IO45NB3F3

IO45PB3F3

IO46NB3F3

IO46PB3F3

IO48NB3F3

IO48PB3F3

IO50NB3F3

IO50PB3F3

IO55NB3F3

IO55PB3F3

IO57NB3F3

IO57PB3F3

IO59NB3F3

IO59PB3F3

IO60NB3F3

IO60PB3F3

IO61NB3F3

IO61PB3F3

Bank 4

127

129

126

128

122

123

120

121

116

117

114

115

110

111

108

109

106

107

IO14NB1F1/HCLKCN

IO14PB1F1/HCLKCP

IO15NB1F1/HCLKDN

IO15PB1F1/HCLKDP

IO16NB1F1

180

181

174

175

170

171

165

166

161

162

159

160

IO91NB6F6

IO91PB6F6

IO92NB6F6

IO92PB6F6

IO93NB6F6

IO93PB6F6

IO94PB6F6

IO96NB6F6

IO96PB6F6

IO101NB6F6

IO101PB6F6

IO102PB6F6

IO103NB6F6

IO103PB6F6

IO105NB6F6

IO105PB6F6

IO106NB6F6

IO106PB6F6

Bank 7

IO16PB1F1

IO24NB1F1

IO24PB1F1

IO26NB1F1

IO26PB1F1

IO27NB1F1

IO27PB1F1

Bank 2

IO29NB2F2

151

153

152

154

148

146

147

144

145

139

140

141

137

138

132

IO29PB2F2

IO62NB4F4

IO62PB4F4

IO63NB4F4

IO63PB4F4

IO64NB4F4

IO64PB4F4

IO72NB4F4

IO72PB4F4

IO74NB4F4/CLKEN

IO74PB4F4/CLKEP

IO75NB4F4/CLKFN

IO75PB4F4/CLKFP

Bank 5

100

103

101

102

IO30NB2F2

IO30PB2F2

IO31PB2F2

IO32NB2F2

IO32PB2F2

IO34NB2F2

IO34PB2F2

IO39NB2F2

IO39PB2F2

IO107NB7F7

IO107PB7F7

IO108NB7F7

IO108PB7F7

IO110NB7F7

IO40PB2F2

IO41NB2F2

IO41PB2F2

IO43NB2F2

IO76NB5F5/CLKGN

3-90

Revision 18

Axcelerator Family FPGAs

CQ208

AX250 Function

IO110PB7F7

IO112NB7F7

IO112PB7F7

IO117NB7F7

IO117PB7F7

IO119NB7F7

IO119PB7F7

IO121PB7F7

IO122NB7F7

IO122PB7F7

IO123NB7F7

IO123PB7F7

Dedicated I/O

GND

Number

AX250 Function

GND

Number

AX250 Function

Number

200

163

172

135

149

112

124

194

196

201

208

184

183

VCCIB0

VCCIB1

GND

VCCIB1

GND/LP

PRA

VCCIB2

PRB

VCCIB3

PRC

VCCIB3

PRD

VCCIB4

TCK

205

204

203

206

207

VCCIB4

TDI

VCCIB5

TDO

VCCIB5

TMS

VCCIB6

TRST

VCCIB6

VCCA

VCCDA

VCCIB0

VCCIB7

GND

VCCIB7

GND

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

VCCPLH

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

189

187

178

176

GND

118

142

156

168

195

GND

190

188

179

177

GND

104

113

119

125

136

143

150

155

164

169

173

GND

105

130

157

167

182

202

193

GND

158

GND

Revision 18

3-91

Package Pin Assignments

CQ208

AX500 Function

Bank 0

Number

AX500 Function

IO61PB2F5

Number

AX500 Function

IO105PB5F10/CLKGP

IO106NB5F10/CLKHN

IO106PB5F10/CLKHP

IO107NB5F10

IO107PB5F10

IO119NB5F11

IO121NB5F11

IO121PB5F11

IO123NB5F11

IO123PB5F11

IO125NB5F11

IO125PB5F11

Bank 6

Number

134

131

133

IO03NB0F0

198

199

197

191

192

185

186

IO62NB2F5

IO62PB2F5

IO03PB0F0

IO04NB0F0

Bank 3

IO19NB0F1/HCLKAN

IO19PB0F1/HCLKAP

IO20NB0F1/HCLKBN

IO20PB0F1/HCLKBP

Bank 1

IO63NB3F6

IO63PB3F6

127

129

126

128

122

123

120

121

116

117

114

115

110

111

108

109

106

107

IO64NB3F6

IO64PB3F6

IO66NB3F6

IO66PB3F6

IO21NB1F2/HCLKCN

IO21PB1F2/HCLKCP

IO22NB1F2/HCLKDN

IO22PB1F2/HCLKDP

IO23NB1F2

180

181

174

175

170

171

165

166

161

162

159

160

IO68NB3F6

IO68PB3F6

IO77NB3F7

IO77PB3F7

IO127NB6F12

IO127PB6F12

IO128NB6F12

IO128PB6F12

IO129NB6F12

IO129PB6F12

IO130PB6F12

IO132NB6F12

IO132PB6F12

IO141NB6F13

IO141PB6F13

IO142PB6F13

IO143NB6F13

IO143PB6F13

IO145NB6F13

IO145PB6F13

IO146NB6F13

IO146PB6F13

Bank 7

IO23PB1F2

IO79NB3F7

IO79PB3F7

IO37NB1F3

IO37PB1F3

IO81NB3F7

IO81PB3F7

IO39NB1F3

IO39PB1F3

IO82NB3F7

IO82PB3F7

IO41NB1F3

IO41PB1F3

IO83NB3F7

IO83PB3F7

Bank 2

IO43NB2F4

151

153

152

154

148

146

147

144

145

139

140

141

137

138

132

Bank 4

IO43PB2F4

IO84PB4F8

103

100

101

102

IO44NB2F4

IO85NB4F8

IO86NB4F8

IO86PB4F8

IO44PB2F4

IO45PB2F4

IO46NB2F4

IO87NB4F8

IO87PB4F8

IO46PB2F4

IO48NB2F4

IO101NB4F9

IO101PB4F9

IO103NB4F9/CLKEN

IO103PB4F9/CLKEP

IO104NB4F9/CLKFN

IO104PB4F9/CLKFP

Bank 5

IO48PB2F4

IO57NB2F5

IO57PB2F5

IO147NB7F14

IO147PB7F14

IO148NB7F14

IO148PB7F14

IO150NB7F14

IO58PB2F5

IO59NB2F5

IO59PB2F5

IO61NB2F5

IO105NB5F10/CLKGN

3-92

Revision 18

Axcelerator Family FPGAs

CQ208

AX500 Function

IO150PB7F14

IO152NB7F14

IO152PB7F14

IO161NB7F15

IO161PB7F15

IO163NB7F15

IO163PB7F15

IO165PB7F15

IO166NB7F15

IO166PB7F15

IO167NB7F15

IO167PB7F15

Dedicated I/O

VCCDA

GND

Number

AX500 Function

GND

Number

AX500 Function

Number

200

163

172

135

149

112

124

173

194

196

201

208

184

183

VCCIB0

VCCIB1

GND

VCCIB1

GND

VCCIB2

GND/LP

PRA

VCCIB2

VCCIB3

PRB

VCCIB3

PRC

VCCIB4

PRD

VCCIB4

TCK

205

204

203

206

207

VCCIB5

TDI

VCCIB5

TDO

VCCIB6

TMS

VCCIB6

TRST

VCCIB7

VCCA

VCCDA

VCCIB0

VCCIB7

GND

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

VCCPLH

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

189

187

178

176

GND

118

142

156

168

195

GND

190

188

179

177

GND

104

113

119

125

136

143

150

155

164

169

GND

105

130

157

167

182

202

193

GND

158

GND

Revision 18

3-93

Package Pin Assignments

CQ256

192

191

190

189

Pin 1

Ceramic

Tie Bar

256-Pin CQFP

132

131

130

129

Note

For Package Manufacturing and Environmental information, visit the Resource center at

http://www.microsemi.com/soc/products/solutions/package/docs.aspx.

3-94

Revision 18

Axcelerator Family FPGAs

CQ256

AX2000 Function

Bank 0

Number

AX2000 Function

IO87PB2F8

Number

AX2000 Function

Number

188

186

IO149PB3F13

Bank 3

137

IO01NB0F0

248

249

246

247

242

243

240

241

IO89PB2F8

IO01PB0F0

Bank 2

IO165NB3F15

IO167NB3F15

IO167PB3F15

Bank 4

135

133

134

IO04NB0F0

IO107NB2F10

IO107PB2F10

IO110NB2F10

IO110PB2F10

IO111NB2F10

IO111PB2F10

IO112NB2F10

IO112PB2F10

IO113NB2F10

IO113PB2F10

IO114NB2F10

IO114PB2F10

IO115NB2F10

IO115PB2F10

IO117NB2F10

IO117PB2F10

Bank 3

184

185

180

181

178

179

174

175

172

173

168

169

166

167

162

163

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO181NB4F17

IO181PB4F17

IO182NB4F17

IO182PB4F17

IO183NB4F17

IO183PB4F17

IO184NB4F17

IO184PB4F17

IO190NB4F17

IO190PB4F17

IO192NB4F17

IO192PB4F17

Bank 4

124

125

122

123

118

119

116

117

112

113

110

111

IO08NB0F0

IO08PB0F0

Bank 0

IO37NB0F3

234

235

232

233

228

229

IO37PB0F3

IO41NB0F3/HCLKAN

IO41PB0F3/HCLKAP

IO42NB0F3/HCLKBN

IO42PB0F3/HCLKBP

Bank 1 -

IO43NB1F4/HCLKCN

IO43PB1F4/HCLKCP

IO44NB1F4/HCLKDN

IO44PB1F4/HCLKDP

Bank 1

220

221

216

217

IO212NB4F19/CLKEN

IO212PB4F19/CLKEP

IO213NB4F19/CLKFN

IO213PB4F19/CLKFP

Bank 5

104

105

100

101

IO139NB3F13

IO139PB3F13

IO141NB3F13

IO141PB3F13

IO142NB3F13

IO142PB3F13

IO145NB3F13

IO145PB3F13

IO146NB3F13

IO146PB3F13

IO147NB3F13

IO147PB3F13

IO148NB3F13

IO148PB3F13

IO149NB3F13

158

159

154

155

152

153

148

149

146

147

140

141

142

143

136

IO65NB1F6

210

211

208

209

199

204

205

202

203

197

198

IO65PB1F6

IO69NB1F6

IO214NB5F20/CLKGN

IO214PB5F20/CLKGP

IO215NB5F20/CLKHN

IO215PB5F20/CLKHP

Bank 5

IO69PB1F6

IO70NB1F6

IO71NB1F6

IO71PB1F6

IO73NB1F6

IO236NB5F22

IO236PB5F22

IO238NB5F22

IO238PB5F22

IO240NB5F22

IO240PB5F22

IO73PB1F6

IO74NB1F6

IO74PB1F6

Bank 2

IO87NB2F8

187

Revision 18

3-95

Package Pin Assignments

CQ256

AX2000 Function

IO242NB5F22

IO242PB5F22

IO243NB5F22

IO243PB5F22

IO244NB5F22

IO244PB5F22

Bank 6

Number

AX2000 Function

IO315PB7F29

IO316NB7F29

IO316PB7F29

IO317NB7F29

IO317PB7F29

IO318NB7F29

IO318PB7F29

IO320NB7F29

IO320PB7F29

Bank 7

Number

AX2000 Function

GND

PRA

Number

121

128

129

132

139

145

151

157

161

165

171

177

183

190

192

193

201

207

213

219

225

231

239

245

256

227

226

IO257PB6F24

IO258NB6F24

IO258PB6F24

Bank 6

IO341NB7F31

IO341PB7F31

Dedicated I/O

GND

IO279NB6F26

IO279PB6F26

IO280NB6F26

IO280PB6F26

IO281NB6F26

IO281PB6F26

IO282NB6F26

IO282PB6F26

IO284NB6F26

IO284PB6F26

IO285NB6F26

IO285PB6F26

IO286NB6F26

IO286PB6F26

IO287NB6F26

IO287PB6F26

Bank 7 9

GND

103

109

115

GND

PRB

GND

PRC

IO310NB7F29

IO310PB7F29

IO311NB7F29

IO311PB7F29

IO312NB7F29

IO312PB7F29

IO315NB7F29

GND

PRD

GND

TCK

253

252

250

254

255

GND

TDI

GND

TDO

GND

TMS

GND

TRST

VCCA

GND

3-96

Revision 18

Axcelerator Family FPGAs

CQ256

AX2000 Function

VCCA

Number

AX2000 Function

VCCDA

VCCIB0

VCCIB1

VCCIB2

VCCIB3

VCCIB4

VCCIB5

VCCIB6

VCCIB7

VPUMP

Number

224

236

237

251

230

244

200

206

218

164

176

182

138

144

156

102

114

120

VCCA

108

127

131

150

170

189

191

212

238

VCCA

VCCDA

106

107

126

130

160

194

196

214

215

222

223

195

Revision 18

3-97

Package Pin Assignments

CQ352

264

263

262

261

Pin 1

Ceramic

Tie Bar

223

222

221

220

219

218

217

216

215

352-Pin CQFP

180

179

178

177

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.microsemi.com/soc/products/rescenter/package/index.html.

3-98

Revision 18

Axcelerator Family FPGAs

CQ352

AX250 Function

Bank 0

Number

AX250 Function

IO24NB1F1

IO24PB1F1

IO25NB1F1

IO25PB1F1

IO27NB1F1

IO27PB1F1

Bank 2

Number

AX250 Function

Bank 3

IO45NB3F3

Number

275

276

271

272

269

270

IO00NB0F0

341

342

343

337

338

335

336

331

332

325

326

323

324

319

320

313

314

217

218

219

220

213

214

211

212

207

208

205

206

201

202

199

200

195

196

193

194

187

188

189

190

183

184

181

182

179

180

IO00PB0F0

IO45PB3F3

IO46NB3F3

IO46PB3F3

IO47NB3F3

IO47PB3F3

IO48NB3F3

IO48PB3F3

IO49NB3F3

IO49PB3F3

IO51NB3F3

IO51PB3F3

IO52NB3F3

IO52PB3F3

IO53NB3F3

IO53PB3F3

IO54NB3F3

IO54PB3F3

IO55NB3F3

IO55PB3F3

IO56NB3F3

IO56PB3F3

IO57NB3F3

IO57PB3F3

IO59NB3F3

IO59PB3F3

IO60NB3F3

IO60PB3F3

IO61NB3F3

IO61PB3F3

IO01NB0F0

IO02NB0F0

IO02PB0F0

IO04NB0F0

IO04PB0F0

IO29NB2F2

IO29PB2F2

IO30NB2F2

IO30PB2F2

IO31NB2F2

IO31PB2F2

IO33NB2F2

IO33PB2F2

IO34NB2F2

IO34PB2F2

IO35NB2F2

IO35PB2F2

IO36NB2F2

IO36PB2F2

IO37NB2F2

IO37PB2F2

IO38NB2F2

IO38PB2F2

IO39NB2F2

IO39PB2F2

IO41NB2F2

IO41PB2F2

IO42NB2F2

IO42PB2F2

IO43NB2F2

IO43PB2F2

IO44NB2F2

IO44PB2F2

261

262

259

260

255

256

249

250

253

254

247

248

243

244

241

242

237

238

235

236

231

232

229

230

225

226

223

224

IO06NB0F0

IO06PB0F0

IO08NB0F0

IO08PB0F0

IO10NB0F0

IO10PB0F0

IO12NB0F0/HCLKAN

IO12PB0F0/HCLKAP

IO13NB0F0/HCLKBN

IO13PB0F0/HCLKBP

Bank 1

IO14NB1F1/HCLKCN

IO14PB1F1/HCLKCP

IO15NB1F1/HCLKDN

IO15PB1F1/HCLKDP

IO16NB1F1

305

306

299

300

289

290

295

296

287

288

283

284

277

278

281

282

IO16PB1F1

IO17NB1F1

IO17PB1F1

IO18NB1F1

IO18PB1F1

IO20NB1F1

IO20PB1F1

IO22NB1F1

Bank 4

IO22PB1F1

IO62NB4F4

IO62PB4F4

IO64NB4F4

172

173

166

IO23NB1F1

IO23PB1F1

Revision 18

3-99

Package Pin Assignments

CQ352

AX250 Function

IO64PB4F4

Number

AX250 Function

IO85PB5F5

IO86NB5F5

IO86PB5F5

IO87NB5F5

IO87PB5F5

IO89NB5F5

IO89PB5F5

Bank 6

Number

AX250 Function

IO106NB6F6

IO106PB6F6

Bank 7

Number

167

170

171

164

165

160

161

158

159

154

155

152

153

146

147

142

143

136

137

105

IO65NB4F4

IO65PB4F4

IO66NB4F4

IO107NB7F7

IO107PB7F7

IO108NB7F7

IO108PB7F7

IO109NB7F7

IO109PB7F7

IO110NB7F7

IO110PB7F7

IO111NB7F7

IO111PB7F7

IO113NB7F7

IO113PB7F7

IO114NB7F7

IO114PB7F7

IO115NB7F7

IO115PB7F7

IO116NB7F7

IO116PB7F7

IO117NB7F7

IO117PB7F7

IO118NB7F7

IO118PB7F7

IO119NB7F7

IO119PB7F7

IO121NB7F7

IO121PB7F7

IO123NB7F7

IO123PB7F7

IO66PB4F4

IO67NB4F4

IO67PB4F4

IO68NB4F4

IO68PB4F4

IO90PB6F6

IO91NB6F6

IO91PB6F6

IO92NB6F6

IO92PB6F6

IO93NB6F6

IO93PB6F6

IO95NB6F6

IO95PB6F6

IO96NB6F6

IO96PB6F6

IO97NB6F6

IO97PB6F6

IO98NB6F6

IO98PB6F6

IO99NB6F6

IO99PB6F6

IO100NB6F6

IO100PB6F6

IO101NB6F6

IO101PB6F6

IO103NB6F6

IO103PB6F6

IO104NB6F6

IO104PB6F6

IO105NB6F6

IO105PB6F6

IO70NB4F4

IO70PB4F4

IO72NB4F4

IO72PB4F4

IO73NB4F4

IO73PB4F4

IO74NB4F4/CLKEN

IO74PB4F4/CLKEP

IO75NB4F4/CLKFN

IO75PB4F4/CLKFP

Bank 5

IO76NB5F5/CLKGN

IO76PB5F5/CLKGP

IO77NB5F5/CLKHN

IO77PB5F5/CLKHP

IO78NB5F5

128

129

122

123

112

113

118

119

110

111

106

107

100

101

104

IO78PB5F5

IO79NB5F5

IO79PB5F5

IO80NB5F5

IO80PB5F5

IO82NB5F5

IO82PB5F5

Dedicated I/O

IO84NB5F5

GND

IO84PB5F5

IO85NB5F5

3-100

Revision 18

Axcelerator Family FPGAs

CQ352

AX250 Function

GND

Number

AX250 Function

GND

Number

AX250 Function

Number

348

347

350

351

240

246

252

258

264

265

274

280

286

292

298

310

322

330

334

340

345

352

TDI

TDO

TMS

TRST

VCCA

VCCDA

102

114

150

162

175

191

209

233

251

263

279

291

329

339

103

109

115

121

133

145

151

157

163

169

176

177

186

192

198

204

210

216

222

228

234

117

130

131

148

174

268

294

307

308

327

328

312

311

135

134

349

116

132

149

178

221

266

293

309

PRA

PRB

PRC

PRD

TCK

Revision 18

3-101

Package Pin Assignments

CQ352

AX250 Function

VCCDA

VCCIB0

VCCIB1

VCCIB2

VCCIB3

VCCIB4

VCCIB5

VCCIB6

VCCIB7

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

Number

AX250 Function

VCCPLG

Number

346

321

333

344

273

285

297

227

239

245

257

185

197

203

215

144

156

168

126

124

318

316

304

302

141

139

127

125

267

VCCPLH

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

108

120

317

315

303

301

140

138

3-102

Revision 18

Axcelerator Family FPGAs

CQ352

AX500 Function

Bank 0

Number

AX500 Function

IO35NB1F3

IO35PB1F3

IO37NB1F3

IO37PB1F3

IO41NB1F3

IO41PB1F3

Bank 2

Number

AX500 Function

Bank 3

IO63NB3F6

Number

275

276

271

272

269

270

IO00PB0F0

343

341

342

337

338

335

336

331

332

325

326

323

324

319

320

313

314

217

218

219

220

213

214

207

208

211

212

205

206

201

202

199

200

193

194

195

196

189

190

187

188

183

184

181

182

179

180

IO03NB0F0

IO63PB3F6

IO64NB3F6

IO64PB3F6

IO65NB3F6

IO65PB3F6

IO67NB3F6

IO67PB3F6

IO68NB3F6

IO68PB3F6

IO69NB3F6

IO69PB3F6

IO71NB3F6

IO71PB3F6

IO73NB3F6

IO73PB3F6

IO75NB3F7

IO75PB3F7

IO76NB3F7

IO76PB3F7

IO77NB3F7

IO77PB3F7

IO79NB3F7

IO79PB3F7

IO80NB3F7

IO80PB3F7

IO81NB3F7

IO81PB3F7

IO83NB3F7

IO83PB3F7

IO03PB0F0

IO05NB0F0

IO05PB0F0

IO07NB0F0

IO07PB0F0

IO43NB2F4

IO43PB2F4

IO45NB2F4

IO45PB2F4

IO47NB2F4

IO47PB2F4

IO49NB2F4

IO49PB2F4

IO50NB2F4

IO50PB2F4

IO51NB2F4

IO51PB2F4

IO53NB2F5

IO53PB2F5

IO54NB2F5

IO54PB2F5

IO55NB2F5

IO55PB2F5

IO57NB2F5

IO57PB2F5

IO58NB2F5

IO58PB2F5

IO59NB2F5

IO59PB2F5

IO61NB2F5

IO61PB2F5

IO62NB2F5

IO62PB2F5

261

262

259

260

255

256

253

254

247

248

249

250

243

244

241

242

237

238

235

236

231

232

229

230

225

226

223

224

IO09NB0F0

IO09PB0F0

IO15NB0F1

IO15PB0F1

IO17NB0F1

IO17PB0F1

IO19NB0F1/HCLKAN

IO19PB0F1/HCLKAP

IO20NB0F1/HCLKBN

IO20PB0F1/HCLKBP

Bank 1

IO21NB1F2/HCLKCN

IO21PB1F2/HCLKCP

IO22NB1F2/HCLKDN

IO22PB1F2/HCLKDP

IO23NB1F2

305

306

299

300

289

290

295

296

287

288

283

284

281

282

277

278

IO23PB1F2

IO24NB1F2

IO24PB1F2

IO25NB1F2

IO25PB1F2

IO27NB1F2

IO27PB1F2

IO29NB1F2

Bank 4

IO29PB1F2

IO85NB4F8

IO85PB4F8

IO87NB4F8

172

173

170

IO31NB1F2

IO31PB1F2

Revision 18

3-103

Package Pin Assignments

CQ352

AX500 Function

IO87PB4F8

Number

AX500 Function

IO119PB5F11

IO121NB5F11

IO121PB5F11

IO123NB5F11

IO123PB5F11

IO125NB5F11

IO125PB5F11

Bank 6

Number

AX500 Function

IO146NB6F13

IO146PB6F13

Bank 7

Number

171

166

167

164

165

160

161

158

159

154

155

146

147

152

153

142

143

136

137

101

IO89NB4F8

IO89PB4F8

IO94NB4F9

IO147NB7F14

IO147PB7F14

IO148NB7F14

IO148PB7F14

IO149NB7F14

IO149PB7F14

IO151NB7F14

IO151PB7F14

IO152NB7F14

IO152PB7F14

IO153NB7F14

IO153PB7F14

IO155NB7F14

IO155PB7F14

IO157NB7F14

IO157PB7F14

IO159NB7F15

IO159PB7F15

IO160NB7F15

IO160PB7F15

IO161NB7F15

IO161PB7F15

IO163NB7F15

IO163PB7F15

IO165NB7F15

IO165PB7F15

IO167NB7F15

IO167PB7F15

Dedicated I/O

GND

IO94PB4F9

IO95NB4F9

IO95PB4F9

IO97NB4F9

IO97PB4F9

IO126PB6F12

IO127NB6F12

IO127PB6F12

IO129NB6F12

IO129PB6F12

IO131NB6F12

IO131PB6F12

IO133NB6F12

IO133PB6F12

IO134NB6F12

IO134PB6F12

IO135NB6F12

IO135PB6F12

IO137NB6F13

IO137PB6F13

IO138NB6F13

IO138PB6F13

IO139NB6F13

IO139PB6F13

IO141NB6F13

IO141PB6F13

IO142NB6F13

IO142PB6F13

IO143NB6F13

IO143PB6F13

IO145NB6F13

IO145PB6F13

IO99NB4F9

IO99PB4F9

IO100NB4F9

IO100PB4F9

IO101NB4F9

IO101PB4F9

IO103NB4F9/CLKEN

IO103PB4F9/CLKEP

IO104NB4F9/CLKFN

IO104PB4F9/CLKFP

Bank 5

IO105NB5F10/CLKGN

IO105PB5F10/CLKGP

IO106NB5F10/CLKHN

IO106PB5F10/CLKHP

IO107NB5F10

IO107PB5F10

IO114NB5F11

IO114PB5F11

IO115NB5F11

IO115PB5F11

IO116NB5F11

IO116PB5F11

IO117NB5F11

IO117PB5F11

IO119NB5F11

128

129

122

123

118

119

112

113

110

111

106

107

104

105

100

GND

3-104

Revision 18

Axcelerator Family FPGAs

CQ352

AX500 Function

GND

Number

AX500 Function

GND

GND/LP

Number

AX500 Function

Number

348

347

350

351

240

246

252

258

264

265

274

280

286

292

298

310

322

330

334

340

345

352

TDI

TDO

TMS

TRST

VCCA

VCCDA

102

114

150

162

175

191

209

233

251

263

279

291

329

339

103

109

115

121

133

145

151

157

163

169

176

177

186

192

198

204

210

216

222

228

234

117

130

131

148

174

268

294

307

308

327

328

312

311

135

134

349

116

132

149

178

221

266

293

309

PRA

PRB

PRC

PRD

TCK

Revision 18

3-105

Package Pin Assignments

CQ352

AX500 Function

VCCDA

VCCIB0

VCCIB1

VCCIB2

VCCIB3

VCCIB4

VCCIB5

VCCIB6

VCCIB7

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

Number

AX500 Function

VCCPLG

Number

346

321

333

344

273

285

297

227

239

245

257

185

197

203

215

144

156

168

126

124

318

316

304

302

141

139

127

125

267

VCCPLH

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

108

120

317

315

303

301

140

138

3-106

Revision 18

Axcelerator Family FPGAs

CQ352

AX1000 Function

Bank 0

Number

AX1000 Function

IO60NB1F5

IO60PB1F5

IO61NB1F5

IO61PB1F5

IO63NB1F5

IO63PB1F5

Bank 2

Number

AX1000 Function

Bank 3

IO96NB3F9

Number

275

276

271

272

269

270

IO02NB0F0

341

342

343

337

338

331

332

335

336

325

326

323

324

319

320

313

314

217

218

219

220

213

214

211

212

207

208

205

206

199

200

201

202

195

196

193

194

189

190

183

184

187

188

181

182

179

180

IO02PB0F0

IO96PB3F9

IO97NB3F9

IO03PB0F0

IO04NB0F0

IO97PB3F9

IO04PB0F0

IO99NB3F9

IO08NB0F0

IO99PB3F9

IO08PB0F0

IO64NB2F6

IO64PB2F6

IO67NB2F6

IO67PB2F6

IO68NB2F6

IO68PB2F6

IO69NB2F6

IO69PB2F6

IO74NB2F7

IO74PB2F7

IO75NB2F7

IO75PB2F7

IO76NB2F7

IO76PB2F7

IO77NB2F7

IO77PB2F7

IO78NB2F7

IO78PB2F7

IO79NB2F7

IO79PB2F7

IO82NB2F7

IO82PB2F7

IO83NB2F7

IO83PB2F7

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

259

260

261

262

255

256

253

254

249

250

247

248

243

244

241

242

237

238

235

236

231

232

229

230

225

226

223

224

IO108NB3F10

IO108PB3F10

IO109NB3F10

IO109PB3F10

IO111NB3F10

IO111PB3F10

IO112NB3F10

IO112PB3F10

IO113NB3F10

IO113PB3F10

IO115NB3F10

IO115PB3F10

IO116NB3F10

IO116PB3F10

IO117NB3F10

IO117PB3F10

IO124NB3F11

IO124PB3F11

IO125NB3F11

IO125PB3F11

IO127NB3F11

IO127PB3F11

IO128NB3F11

IO128PB3F11

Bank 4

IO09NB0F0

IO09PB0F0

IO24NB0F2

IO24PB0F2

IO25NB0F2

IO25PB0F2

IO30NB0F2/HCLKAN

IO30PB0F2/HCLKAP

IO31NB0F2/HCLKBN

IO31PB0F2/HCLKBP

Bank 1

IO32NB1F3/HCLKCN

IO32PB1F3/HCLKCP

IO33NB1F3/HCLKDN

IO33PB1F3/HCLKDP

IO38NB1F3

305

306

299

300

295

296

287

288

289

290

281

282

283

284

277

278

IO38PB1F3

IO54NB1F5

IO54PB1F5

IO55NB1F5

IO55PB1F5

IO56NB1F5

IO56PB1F5

IO57NB1F5

IO57PB1F5

IO130NB4F12

IO130PB4F12

IO131NB4F12

172

173

170

IO59NB1F5

IO59PB1F5

Revision 18

3-107

Package Pin Assignments

CQ352

AX1000 Function

IO131PB4F12

Number

AX1000 Function

IO187PB5F17

IO188NB5F17

IO188PB5F17

IO190NB5F17

IO190PB5F17

IO192NB5F17

IO192PB5F17

Bank 6

Number

AX1000 Function

IO224NB6F20

IO224PB6F20

Bank 7

Number

171

166

167

164

165

160

161

158

159

154

155

152

153

146

147

142

143

136

137

100

101

IO132NB4F12

IO132PB4F12

IO133NB4F12

IO225NB7F21

IO225PB7F21

IO226NB7F21

IO226PB7F21

IO237NB7F22

IO237PB7F22

IO238NB7F22

IO238PB7F22

IO240NB7F22

IO240PB7F22

IO241NB7F22

IO241PB7F22

IO242NB7F22

IO242PB7F22

IO244NB7F22

IO244PB7F22

IO245NB7F22

IO245PB7F22

IO246NB7F22

IO246PB7F22

IO249NB7F23

IO249PB7F23

IO250NB7F23

IO250PB7F23

IO256NB7F23

IO256PB7F23

IO257NB7F23

IO257PB7F23

Dedicated I/O

GND

IO133PB4F12

IO134NB4F12

IO134PB4F12

IO136NB4F12

IO136PB4F12

IO193PB6F18

IO194NB6F18

IO194PB6F18

IO196NB6F18

IO196PB6F18

IO197NB6F18

IO197PB6F18

IO198NB6F18

IO198PB6F18

IO203NB6F19

IO203PB6F19

IO204NB6F19

IO204PB6F19

IO205NB6F19

IO205PB6F19

IO206NB6F19

IO206PB6F19

IO207NB6F19

IO207PB6F19

IO208NB6F19

IO208PB6F19

IO211NB6F19

IO211PB6F19

IO212NB6F19

IO212PB6F19

IO223NB6F20

IO223PB6F20

IO137NB4F12

IO137PB4F12

IO138NB4F12

IO138PB4F12

IO153NB4F14

IO153PB4F14

IO159NB4F14/CLKEN

IO159PB4F14/CLKEP

IO160NB4F14/CLKFN

IO160PB4F14/CLKFP

Bank 5

IO161NB5F15/CLKGN

IO161PB5F15/CLKGP

IO162NB5F15/CLKHN

IO162PB5F15/CLKHP

IO167NB5F15

128

129

122

123

118

119

110

111

112

113

104

105

106

107

IO167PB5F15

IO183NB5F17

IO183PB5F17

IO184NB5F17

IO184PB5F17

IO185NB5F17

IO185PB5F17

IO186NB5F17

IO186PB5F17

GND

IO187NB5F17

GND

3-108

Revision 18

Axcelerator Family FPGAs

CQ352

AX1000 Function

GND

Number

AX1000 Function

GND

Number

AX1000 Function

Number

240

246

252

258

264

265

274

280

286

292

298

310

322

330

334

340

345

352

VCCA

102

114

150

162

175

191

209

233

251

263

279

291

329

339

VCCA

103

109

115

121

133

145

151

157

163

169

176

177

186

192

198

204

210

216

222

228

234

VCCA

130

131

174

268

307

308

312

311

135

134

349

348

347

350

351

VCCDA

116

117

132

148

149

178

221

266

293

294

309

327

328

PRA

PRB

PRC

PRD

TCK

TDI

TDO

TMS

TRST

VCCA

Revision 18

3-109

Package Pin Assignments

CQ352

AX1000 Function

VCCDA

VCCIB0

VCCIB1

VCCIB2

VCCIB3

VCCIB4

VCCIB5

VCCIB6

VCCIB7

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

Number

AX1000 Function

VCCPLG

Number

346

321

333

344

273

285

297

227

239

245

257

185

197

203

215

144

156

168

126

124

318

316

304

302

141

139

127

125

267

VCCPLH

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

108

120

317

315

303

301

140

138

3-110

Revision 18

Axcelerator Family FPGAs

CQ352

AX2000 Function

Bank 0

Number

AX2000 Function

IO71NB1F6

IO71PB1F6

Number

AX2000 Function

Bank 3

IO129NB3F12

Number

277

278

269

270

271

272

IO01NB0F0

341

342

343

337

338

335

336

331

332

325

326

323

324

319

320

313

314

219

220

217

218

213

214

211

212

205

206

207

208

199

200

201

202

193

194

195

196

189

190

183

184

187

188

181

182

179

180

IO01PB0F0

IO73NB1F6

IO73PB1F6

IO129PB3F12

IO132NB3F12

IO132PB3F12

IO137NB3F12

IO137PB3F12

IO139NB3F13

IO139PB3F13

IO141NB3F13

IO141PB3F13

IO142NB3F13

IO142PB3F13

IO145NB3F13

IO145PB3F13

IO146NB3F13

IO146PB3F13

IO147NB3F13

IO147PB3F13

IO148NB3F13

IO148PB3F13

IO149NB3F13

IO149PB3F13

IO161NB3F15

IO161PB3F15

IO163NB3F15

IO163PB3F15

IO165NB3F15

IO165PB3F15

IO167NB3F15

IO167PB3F15

IO02PB0F0

IO04NB0F0

IO74NB1F6

IO74PB1F6

IO04PB0F0

IO05NB0F0

Bank 2

IO05PB0F0

IO87NB2F8

IO87PB2F8

261

262

255

256

259

260

253

254

249

250

247

248

243

244

241

242

237

238

235

236

231

232

229

230

225

226

223

224

IO08NB0F0

IO08PB0F0

IO88NB2F8

IO88PB2F8

IO37NB0F3

IO37PB0F3

IO89NB2F8

IO89PB2F8

IO38NB0F3

IO38PB0F3

IO91NB2F8

IO91PB2F8

IO41NB0F3/HCLKAN

IO41PB0F3/HCLKAP

IO42NB0F3/HCLKBN

IO42PB0F3/HCLKBP

Bank 1

IO99NB2F9

IO99PB2F9

IO100NB2F9

IO100PB2F9

IO107NB2F10

IO107PB2F10

IO110NB2F10

IO110PB2F10

IO111NB2F10

IO111PB2F10

IO112NB2F10

IO112PB2F10

IO113NB2F10

IO113PB2F10

IO114NB2F10

IO114PB2F10

IO115NB2F10

IO115PB2F10

IO117NB2F10

IO117PB2F10

IO43NB1F4/HCLKCN

IO43PB1F4/HCLKCP

IO44NB1F4/HCLKDN

IO44PB1F4/HCLKDP

IO48NB1F4

305

306

299

300

295

296

283

284

289

290

287

288

275

276

281

282

IO48PB1F4

IO65NB1F6

IO65PB1F6

IO66NB1F6

IO66PB1F6

IO68NB1F6

IO68PB1F6

IO69NB1F6

Bank 4

IO69PB1F6

IO181NB4F17

IO181PB4F17

IO182NB4F17

172

173

170

IO70NB1F6

IO70PB1F6

Revision 18

3-111

Package Pin Assignments

CQ352

AX2000 Function

IO182PB4F17

Number

AX2000 Function

IO240PB5F22

IO242NB5F22

IO242PB5F22

IO243NB5F22

IO243PB5F22

IO244NB5F22

IO244PB5F22

Bank 6

Number

AX2000 Function

IO296NB6F27

IO296PB6F27

Bank 7

Number

171

166

167

164

165

160

161

158

159

154

155

152

153

146

147

142

143

136

137

101

IO183NB4F17

IO183PB4F17

IO184NB4F17

IO300NB7F28

IO300PB7F28

IO303NB7F28

IO303PB7F28

IO310NB7F29

IO310PB7F29

IO311NB7F29

IO311PB7F29

IO312NB7F29

IO312PB7F29

IO315NB7F29

IO315PB7F29

IO316NB7F29

IO316PB7F29

IO317NB7F29

IO317PB7F29

IO318NB7F29

IO318PB7F29

IO320NB7F29

IO320PB7F29

IO334NB7F31

IO334PB7F31

IO335NB7F31

IO335PB7F31

IO338NB7F31

IO338PB7F31

IO341NB7F31

IO341PB7F31

Dedicated I/O

GND

IO184PB4F17

IO185NB4F17

IO185PB4F17

IO190NB4F17

IO190PB4F17

IO257PB6F24

IO258NB6F24

IO258PB6F24

IO261NB6F24

IO261PB6F24

IO262NB6F24

IO262PB6F24

IO265NB6F24

IO265PB6F24

IO279NB6F26

IO279PB6F26

IO280NB6F26

IO280PB6F26

IO281NB6F26

IO281PB6F26

IO282NB6F26

IO282PB6F26

IO284NB6F26

IO284PB6F26

IO285NB6F26

IO285PB6F26

IO286NB6F26

IO286PB6F26

IO287NB6F26

IO287PB6F26

IO294NB6F27

IO294PB6F27

IO191NB4F17

IO191PB4F17

IO192NB4F17

IO192PB4F17

IO207NB4F19

IO207PB4F19

IO212NB4F19/CLKEN

IO212PB4F19/CLKEP

IO213NB4F19/CLKFN

IO213PB4F19/CLKFP

Bank 5

IO214NB5F20/CLKGN

IO214PB5F20/CLKGP

IO215NB5F20/CLKHN

IO215PB5F20/CLKHP

IO217NB5F20

128

129

122

123

118

119

110

111

112

113

104

105

106

107

100

IO217PB5F20

IO236NB5F22

IO236PB5F22

IO237NB5F22

IO237PB5F22

IO238NB5F22

IO238PB5F22

IO239NB5F22

IO239PB5F22

GND

IO240NB5F22

GND

3-112

Revision 18

Axcelerator Family FPGAs

CQ352

AX2000 Function

GND

Number

AX2000 Function

GND

Number

AX2000 Function

Number

150

162

175

191

209

233

251

263

279

291

329

339

240

246

252

258

264

265

274

280

286

292

298

310

322

330

334

340

345

352

312

311

135

134

349

348

347

350

351

VCCA

GND

VCCA

GND

VCCA

GND

VCCA

GND

VCCA

GND

VCCA

GND

VCCA

GND

VCCA

GND

VCCA

GND

VCCA

GND

VCCA

GND

VCCDA

GND

103

109

115

121

133

145

151

157

163

169

176

177

186

192

198

204

210

216

222

228

234

GND

116

117

130

131

132

148

149

174

178

221

266

268

293

294

307

308

309

327

328

GND

PRA

PRB

PRC

PRD

TCK

TDI

TDO

TMS

TRST

VCCA

102

114

Revision 18

3-113

Package Pin Assignments

CQ352

AX2000 Function

VCCDA

VCCIB0

VCCIB1

VCCIB2

VCCIB3

VCCIB4

VCCIB5

VCCIB6

VCCIB7

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

Number

AX2000 Function

VCCPLG

Number

346

321

333

344

273

285

297

227

239

245

257

185

197

203

215

144

156

168

126

124

318

316

304

302

141

139

127

125

267

VCCPLH

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

108

120

317

315

303

301

140

138

3-114

Revision 18

Axcelerator Family FPGAs

CG624

25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

7 6

5 4 3 2 1

Note

For Package Manufacturing and Environmental information, visit Resource center at

http://www.microsemi.com/soc/products/rescenter/package/index.html.

Revision 18

3-115

Package Pin Assignments

CG624

AX1000 Function

Bank 0

Number

AX1000 Function

IO23NB0F2

Number

AX1000 Function

IO42NB1F4

IO42PB1F4

IO43NB1F4

IO43PB1F4

IO44NB1F4

IO44PB1F4

IO45NB1F4

IO45PB1F4

IO46NB1F4

IO46PB1F4

IO47NB1F4

IO48NB1F4

IO48PB1F4

IO49NB1F4

IO49PB1F4

IO50NB1F4

IO50PB1F4

IO51NB1F4

IO51PB1F4

IO52NB1F4

IO52PB1F4

IO53NB1F4

IO53PB1F4

IO54NB1F5

IO54PB1F5

IO55NB1F5

IO55PB1F5

IO56NB1F5

IO56PB1F5

IO58NB1F5

IO58PB1F5

IO60NB1F5

IO60PB1F5

IO62NB1F5

IO62PB1F5

IO63NB1F5

Number

E11

F11

G21

G20

A16

A15

A20

A19

B17

B16

G17

H17

A17

C19

C18

B20

B19

H20

H19

A22

A21

C21

C20

B22

B21

J18

IO00NB0F0

IO00PB0F0

IO02NB0F0

IO02PB0F0

IO04NB0F0

IO04PB0F0

IO06NB0F0

IO06PB0F0

IO07PB0F0

IO08NB0F0

IO08PB0F0

IO09PB0F0

IO10NB0F0

IO10PB0F0

IO11NB0F0

IO11PB0F0

IO12NB0F1

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO14NB0F1

IO14PB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17NB0F1

IO17PB0F1

IO18NB0F1

IO18PB0F1

IO20NB0F1

IO20PB0F1

IO21NB0F1

IO21PB0F1

IO22NB0F2

IO22PB0F2

IO23PB0F2

IO24NB0F2

IO24PB0F2

IO25PB0F2

B12

H11

G11

C11

IO26NB0F2

IO26PB0F2

IO27NB0F2

IO27PB0F2

IO28NB0F2

J13

K13

F10

IO28PB0F2

IO29NB0F2

D10

IO29PB0F2

IO30NB0F2/HCLKAN

IO30PB0F2/HCLKAP

IO31NB0F2/HCLKBN

IO31PB0F2/HCLKBP

Bank 1

G13

G12

C13

C12

IO32NB1F3/HCLKCN

IO32PB1F3/HCLKCP

IO33NB1F3/HCLKDN

IO33PB1F3/HCLKDP

IO34NB1F3

G15

G14

B14

B13

G16

H16

C17

B18

H18

H15

H13

E15

F15

D14

C14

D16

D15

F16

IO34PB1F3

IO35NB1F3

J19

IO35PB1F3

D18

D17

F20

F19

E17

F17

D20

D19

E18

F18

G19

IO36NB1F3

IO36PB1F3

D12

D11

B11

B10

A11

A10

H10

IO37NB1F3

IO38NB1F3

IO38PB1F3

IO39NB1F3

IO39PB1F3

IO40NB1F3

IO40PB1F3

IO41NB1F4

3-116

Revision 18

Axcelerator Family FPGAs

CG624

AX1000 Function

IO63PB1F5

Bank 2

Number

AX1000 Function

IO84NB2F7

IO84PB2F7

IO86NB2F8

IO86PB2F8

IO87NB2F8

IO87PB2F8

IO88NB2F8

IO88PB2F8

IO89NB2F8

IO90NB2F8

IO90PB2F8

IO91NB2F8

IO91PB2F8

IO92NB2F8

IO92PB2F8

IO93PB2F8

IO94NB2F8

IO94PB2F8

IO95NB2F8

IO95PB2F8

Bank 3

Number

AX1000 Function

Number

R23

P23

G18

M20

M21

E25

D25

L24

K24

G24

F24

J25

IO105NB3F9

IO105PB3F9

IO106NB3F9

IO106PB3F9

IO107NB3F10

IO108NB3F10

IO108PB3F10

IO109NB3F10

IO109PB3F10

IO110NB3F10

IO110PB3F10

IO112NB3F10

IO112PB3F10

IO113NB3F10

IO113PB3F10

IO114NB3F10

IO114PB3F10

IO116NB3F10

IO116PB3F10

IO117NB3F10

IO117PB3F10

IO118NB3F11

IO118PB3F11

IO120NB3F11

IO120PB3F11

IO122NB3F11

IO122PB3F11

IO124NB3F11

IO124PB3F11

IO126NB3F11

IO126PB3F11

IO128NB3F11

IO128PB3F11

IO64NB2F6

IO64PB2F6

IO65NB2F6

IO65PB2F6

IO66NB2F6

IO66PB2F6

IO67NB2F6

IO67PB2F6

IO68NB2F6

IO68PB2F6

IO70NB2F6

IO70PB2F6

IO71NB2F6

IO71PB2F6

IO72NB2F6

IO72PB2F6

IO74NB2F7

IO74PB2F7

IO75NB2F7

IO75PB2F7

IO76NB2F7

IO76PB2F7

IO77NB2F7

IO77PB2F7

IO78NB2F7

IO78PB2F7

IO79NB2F7

IO79PB2F7

IO80NB2F7

IO80PB2F7

IO82NB2F7

IO82PB2F7

IO83NB2F7

IO83PB2F7

M17

G22

J21

R19

R20

AB24

R25

P25

J20

L23

K20

F23

E23

L18

K18

E24

D24

H23

G23

L19

K19

J22

U25

T25

G25

F25

L25

K25

J24

U24

U23

T24

R24

Y25

H24

J23

W25

V23

N24

M24

N25

M25

V24

AA24

Y24

H22

N23

M23

N17

N16

L22

K22

M19

M18

N19

N18

L21

L20

P18

P17

N22

M22

AB25

AA25

T20

IO96NB3F9

IO96PB3F9

IO97NB3F9

IO97PB3F9

IO98NB3F9

IO98PB3F9

IO99NB3F9

IO100NB3F9

IO100PB3F9

IO101NB3F9

IO101PB3F9

IO102NB3F9

IO102PB3F9

IO104NB3F9

IO104PB3F9

T18

R18

N20

P24

P20

P19

P21

T22

W24

R22

P22

U19

T19

V20

U20

R21

W22

W23

V22

U22

Y23

AA23

V21

U21

Y22

Y21

Bank 4

IO129NB4F12

IO129PB4F12

W20

Y20

Revision 18

3-117

Package Pin Assignments

CG624

AX1000 Function

IO131NB4F12

IO131PB4F12

IO133NB4F12

IO133PB4F12

IO135NB4F12

IO135PB4F12

IO137NB4F12

IO137PB4F12

IO138NB4F12

IO138PB4F12

IO139NB4F13

IO139PB4F13

IO140NB4F13

IO140PB4F13

IO141NB4F13

IO141PB4F13

IO142NB4F13

IO142PB4F13

IO143NB4F13

IO143PB4F13

IO144PB4F13

IO145NB4F13

IO145PB4F13

IO146NB4F13

IO146PB4F13

IO147NB4F13

IO147PB4F13

IO148PB4F13

IO149NB4F13

IO149PB4F13

IO150NB4F13

IO150PB4F13

IO151NB4F13

IO151PB4F13

IO152NB4F14

IO152PB4F14

Number

AX1000 Function

IO153NB4F14

Number

AX1000 Function

IO173PB5F16

IO174NB5F16

IO174PB5F16

IO175NB5F16

IO175PB5F16

IO177NB5F16

IO177PB5F16

IO178NB5F16

IO178PB5F16

IO179NB5F16

IO179PB5F16

IO180NB5F16

IO180PB5F16

IO181NB5F17

IO181PB5F17

IO182NB5F17

IO182PB5F17

IO183NB5F17

IO183PB5F17

IO184NB5F17

IO185NB5F17

IO185PB5F17

IO186NB5F17

IO186PB5F17

IO187NB5F17

IO187PB5F17

IO188NB5F17

IO189NB5F17

IO189PB5F17

IO191NB5F17

IO191PB5F17

IO192NB5F17

IO192PB5F17

Bank 6

Number

V19

W19

Y15

Y16

Y11

AB10

AB11

AC9

AE9

AA8

IO153PB4F14

Y18

IO155NB4F14

V15

Y19

IO155PB4F14

V16

W18

IO156NB4F14

AB14

AB15

AE14

AC18

AC15

AC19

W14

W15

AC13

AD13

V18

IO156PB4F14

Y17

IO157NB4F14

AA17

AB19

AB18

AA19

U18

IO157PB4F14

IO158NB4F14

IO158PB4F14

Y10

W10

IO159NB4F14/CLKEN

IO159PB4F14/CLKEP

IO160NB4F14/CLKFN

IO160PB4F14/CLKFP

Bank 5

AC20

AC21

AD17

AD18

AD21

AD22

AB17

AC17

AE22

AE15

AE16

AD19

AD20

AD15

AD16

AE21

AD14

AC14

AE19

AE20

V17

AD9

AD10

AE10

AE11

AD7

AD8

AB9

AE6

AE7

AE4

AE5

AA9

IO161NB5F15/CLKGN

IO161PB5F15/CLKGP

IO162NB5F15/CLKHN

IO162PB5F15/CLKHP

IO163NB5F15

W13

Y13

AC12

AD12

IO163PB5F15

V10

V11

T13

U13

V13

W11

W12

AB6

AA6

IO164NB5F15

IO164PB5F15

IO165NB5F15

IO165PB5F15

IO167NB5F15

IO167PB5F15

IO168NB5F15

AD5

AD6

AC5

AC6

AB7

AC7

IO168PB5F15

IO169NB5F15

IO169PB5F15

IO171NB5F16

IO171PB5F16

W17

IO172NB5F16

AB8

AC8

AA11

AB16

W16

IO172PB5F16

IO193NB6F18

IO193PB6F18

IO173NB5F16

3-118

Revision 18

Axcelerator Family FPGAs

CG624

AX1000 Function

IO194NB6F18

IO194PB6F18

IO195NB6F18

IO195PB6F18

IO197NB6F18

IO197PB6F18

IO198NB6F18

IO199NB6F18

IO199PB6F18

IO200NB6F18

IO200PB6F18

IO201NB6F18

IO201PB6F18

IO202NB6F18

IO203NB6F19

IO203PB6F19

IO204NB6F19

IO204PB6F19

IO205NB6F19

IO205PB6F19

IO206NB6F19

IO206PB6F19

IO207NB6F19

IO207PB6F19

IO208NB6F19

IO208PB6F19

IO209NB6F19

IO209PB6F19

IO210NB6F19

IO211NB6F19

IO211PB6F19

IO212NB6F19

IO212PB6F19

IO213NB6F19

IO213PB6F19

IO215NB6F20

Number

AX1000 Function

IO215PB6F20

IO216NB6F20

IO216PB6F20

IO217NB6F20

IO217PB6F20

IO219NB6F20

IO219PB6F20

IO220NB6F20

IO220PB6F20

IO221NB6F20

IO221PB6F20

IO223NB6F20

IO223PB6F20

IO224NB6F20

IO224PB6F20

Bank 7

Number

AX1000 Function

Number

AA3

IO237NB7F22

IO237PB7F22

IO238NB7F22

IO239NB7F22

IO239PB7F22

IO240NB7F22

IO241NB7F22

IO241PB7F22

IO242NB7F22

IO243NB7F22

IO243PB7F22

IO244NB7F22

IO244PB7F22

IO245NB7F22

IO245PB7F22

IO246NB7F22

IO246PB7F22

IO247NB7F23

IO247PB7F23

IO248NB7F23

IO249NB7F23

IO249PB7F23

IO251NB7F23

IO251PB7F23

IO253NB7F23

IO253PB7F23

IO255NB7F23

IO255PB7F23

IO257NB7F23

IO257PB7F23

AA1

AB1

IO225NB7F21

IO225PB7F21

IO226PB7F21

IO227NB7F21

IO227PB7F21

IO229NB7F21

IO229PB7F21

IO230NB7F21

IO230PB7F21

IO231NB7F21

IO231PB7F21

IO232NB7F21

IO232PB7F21

IO233NB7F21

IO233PB7F21

IO234NB7F21

IO234PB7F21

IO235NB7F21

IO235PB7F21

IO236NB7F22

N10

AA2

AB2

Dedicated I/O

GND

A18

A24

A25

Revision 18

3-119

Package Pin Assignments

CG624

AX1000 Function

GND

Number

AX1000 Function

GND/LP

GND

Number

AX1000 Function

GND

Number

AA10

AA16

AA18

AA21

AA5

AB22

AB4

AC10

AC16

AC23

AC3

AD1

AD2

AD24

AD25

AE1

AE18

AE2

AE24

AE25

AE8

V25

GND

H21

H25

K21

K23

GND

A14

AA20

AB13

AD4

AE12

F21

G10

F13

A13

AB12

AE13

L11

L12

L13

L14

L15

M11

M12

M13

M14

M15

N11

N12

N13

N14

N15

P11

P12

P13

P14

P15

R11

R12

R13

R14

R15

T21

T23

PRA

PRB

PRC

PRD

TCK

TDI

TDO

TMS

TRST

VCCA

AB20

F22

J17

B24

K10

K11

K15

K16

L10

L16

R10

R16

T10

T11

T15

T16

B25

C10

C16

C23

D22

E10

E16

E21

3-120

Revision 18

Axcelerator Family FPGAs

CG624

AX1000 Function

VCCA

Number

AX1000 Function

VCCIB2

VCCIB3

VCCIB4

VCCIB5

VCCIB6

VCCIB7

Number

AX1000 Function

Number

U17

D23

E22

K17

L17

VCCIB7

VCCA

VCCIB7

VCCDA

VCCIB0

VCCIB1

VCCIB2

A12

AA13

AA15

AA7

AC11

AD11

AE17

B15

C15

VCCIB7

M10

E12

J12

M16

AA22

AB23

AC24

AC25

P16

R17

T17

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

VCCPLH

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

E14

H14

Y14

U14

Y12

U12

F12

H12

F14

J14

AB21

AC22

AD23

AE23

T14

D13

E13

E19

AA14

V14

AA12

V12

E20

N21

U15

U16

AB5

AC4

AD3

AE3

T12

W21

J10

J11

U10

U11

AA4

AB3

AC1

AC2

P10

K12

A23

B23

C22

D21

J15

J16

K14

C24

C25

Revision 18

3-121

Package Pin Assignments

CG624

AX2000 Function

CG624

AX2000 Function

Number

AX2000 Function

Bank 0

IO27NB0F2

IO27PB0F2

H10

IO51NB1F4

IO51PB1F4

IO52NB1F4

IO55NB1F5

IO55PB1F5

IO56NB1F5

IO56PB1F5

IO57NB1F5

IO57PB1F5

IO58NB1F5

IO58PB1F5

IO59NB1F5

IO61NB1F5

IO61PB1F5

IO62NB1F5

IO62PB1F5

IO63NB1F5

IO65NB1F6

IO66PB1F6

IO67NB1F6

IO67PB1F6

IO68NB1F6

IO68PB1F6

IO69NB1F6

IO69PB1F6

IO70NB1F6

IO70PB1F6

IO71PB1F6

IO73NB1F6

IO74NB1F6

IO74PB1F6

IO75NB1F6

E15

F15

A17

G16

H16

A20

A19

D16

D15

A22

A21

F16

G17

H17

B17

B16

H18

C17

B18

J18

IO00NB0F0

IO00PB0F0

IO01NB0F0

IO01PB0F0

IO02NB0F0

IO02PB0F0

IO04PB0F0

IO05NB0F0

IO05PB0F0

IO06NB0F0

IO06PB0F0

IO11NB0F0

IO11PB0F0

IO12PB0F1

IO13NB0F1

IO13PB0F1

IO15NB0F1

IO15PB0F1

IO16NB0F1

IO16PB0F1

IO17NB0F1

IO17PB0F1

IO18NB0F1

IO18PB0F1

IO19NB0F1

IO19PB0F1

IO20PB0F1

IO23NB0F2

IO23PB0F2

IO26NB0F2

IO26PB0F2

D7*

E7*

IO28NB0F2

IO28PB0F2

IO30NB0F2

B11

B10

E11

F11

D12

D11

A11

A10

J13

K13

H11

G11

B12

G13

G12

C13

C12

IO30PB0F2

IO31NB0F2

IO31PB0F2

IO33NB0F2

IO33PB0F2

IO34NB0F3

IO34PB0F3

IO37NB0F3

IO37PB0F3

IO38NB0F3

E9*

D8*

IO38PB0F3

IO40PB0F3

IO41NB0F3/HCLKAN

IO41PB0F3/HCLKAP

IO42NB0F3/HCLKBN

IO42PB0F3/HCLKBP

Bank 1

J19

D10

B20

B19

E17

F17

B22

B21

G18

G19

C19

C18

D18

IO43NB1F4/HCLKCN

IO43PB1F4/HCLKCP

IO44NB1F4/HCLKDN

IO44PB1F4/HCLKDP

IO45NB1F4

G15

G14

B14

B13

H13

D14

C14

A16

A15

H15

IO47NB1F4

F10

IO47PB1F4

IO48NB1F4

C11*

B8*

IO48PB1F4

IO49PB1F4

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Recommended to be used as

a single-ended I/O.

Recommended to be used as

a single-ended I/O.

Recommended to be used as

a single-ended I/O.

3-122

Revision 18

Axcelerator Family FPGAs

CG624

AX2000 Function

CG624

AX2000 Function

CG624

Number

AX2000 Function

Number

IO75PB1F6

IO76NB1F7

IO76PB1F7

IO79NB1F7

IO79PB1F7

IO80NB1F7

IO80PB1F7

IO81NB1F7

IO81PB1F7

IO82NB1F7

IO82PB1F7

IO85NB1F7

IO85PB1F7

D17

C21

C20

H20

H19

E18

F18

G21

G20

F20

F19

D20*

D19*

IO99PB2F9

IO100NB2F9

IO100PB2F9

IO103PB2F9

IO105NB2F9

IO105PB2F9

IO106NB2F9

IO106PB2F9

IO107NB2F10

IO107PB2F10

IO109NB2F10

IO109PB2F10

IO110NB2F10

IO110PB2F10

IO111NB2F10

IO111PB2F10

IO112NB2F10

IO112PB2F10

IO113NB2F10

IO115NB2F10

IO115PB2F10

IO117NB2F10

IO117PB2F10

IO118NB2F11

IO121NB2F11

IO121PB2F11

IO122NB2F11

IO122PB2F11

IO123NB2F11

IO123PB2F11

IO124NB2F11

IO124PB2F11

K19

E25

D25

K20

M19

M18

J24

IO127NB2F11

IO127PB2F11

IO128NB2F11

IO128PB2F11

P18

P17

N25

M25

Bank 3

IO129NB3F12

IO130PB3F12

IO131NB3F12

IO133NB3F12

IO133PB3F12

IO138NB3F12

IO138PB3F12

IO139NB3F13

IO139PB3F13

IO141NB3F13

IO142NB3F13

IO142PB3F13

IO143PB3F13

IO145NB3F13

IO145PB3F13

IO146NB3F13

IO146PB3F13

IO147NB3F13

IO147PB3F13

IO148NB3F13

IO148PB3F13

IO149NB3F13

IO153NB3F14

IO153PB3F14

IO154NB3F14

IO154PB3F14

IO157NB3F14

N20

P24

P21

P20

P19

R23

P23

R22

P22

R19

R25

P25

R21

T18

R18

T24

R24

T20

R20

U25

T25

T22

U19

T19

Y25

W25

V20

H24

L23*

N16*

L22

K22

G25

F25

L21

L20

L24

K24

N17

M20

M21

N19

N18

J25

Bank 2

IO86NB2F8

IO86PB2F8

IO87NB2F8

IO87PB2F8

IO88NB2F8

IO88PB2F8

IO89NB2F8

IO89PB2F8

IO91NB2F8

IO91PB2F8

IO92NB2F8

IO92PB2F8

IO96NB2F9

IO96PB2F9

IO97NB2F9

IO97PB2F9

IO98PB2F9

IO99NB2F9

F23

E23

H23

G23

E24

D24

M17*

G22*

J22

H22

L18

K18

G24

F24

J21

N24

M24

L25

K25

N22

M22

N23

M23

J20

J23

L19

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Recommended to be used as

a single-ended I/O.

Recommended to be used as

a single-ended I/O.

Recommended to be used as

a single-ended I/O.

Revision 18

3-123

Package Pin Assignments

CG624

AX2000 Function

CG624

AX2000 Function

Number

AX2000 Function

IO157PB3F14

IO158NB3F14

IO158PB3F14

IO160PB3F14

IO161NB3F15

IO161PB3F15

IO162NB3F15

IO162PB3F15

IO163NB3F15

IO163PB3F15

IO164NB3F15

IO164PB3F15

IO166NB3F15

IO167NB3F15

IO167PB3F15

IO168NB3F15

IO168PB3F15

IO169NB3F15

IO169PB3F15

IO170NB3F15

IO170PB3F15

Bank 4

Number

U20

AB25

AA25

W24

U24

IO177PB4F16

IO182NB4F17

IO182PB4F17

IO183PB4F17

IO184NB4F17

IO184PB4F17

IO185NB4F17

IO185PB4F17

IO187PB4F17

IO188NB4F17

IO188PB4F17

IO189PB4F17

IO191NB4F17

IO191PB4F17

IO192PB4F17

IO195PB4F18

IO196NB4F18

IO197NB4F18

IO197PB4F18

IO198NB4F18

IO198PB4F18

IO199NB4F18

IO199PB4F18

IO200NB4F18

IO201NB4F18

IO201PB4F18

IO202NB4F18

IO202PB4F18

IO206NB4F19

IO206PB4F19

IO207NB4F19

IO207PB4F19

AB18

V19

IO208PB4F19

IO209NB4F19

W16

AE14

V15

W19

IO210NB4F19

AC19

AB17

AC17

AD19

AD20

AC18

Y17

IO210PB4F19

V16

IO211NB4F19

AD14

AC14

W14

W15

AC13

AD13

U23

IO211PB4F19

AA24

Y24

IO212NB4F19/CLKEN

IO212PB4F19/CLKEP

IO213NB4F19/CLKFN

IO213PB4F19/CLKFP

Bank 5

V22

U22

V23

AA17

AE22

W18

V24

IO214NB5F20/CLKGN

IO214PB5F20/CLKGP

IO215NB5F20/CLKHN

IO215PB5F20/CLKHP

IO216NB5F20

W13

Y13

AB24

V21

V18

AC12

AD12

U13

U21

U18

Y23

AE21

AB16

AD17

AD18

V17

AA23

W22*

W23*

Y22

IO216PB5F20

V13

IO217NB5F20

AE10

AE11

W11

W12

AA11

Y11

IO217PB5F20

IO218NB5F20

Y21

W17

IO218PB5F20

AE19

AE20

AC15

AD15

AD16

Y15

IO222NB5F20

IO171NB4F16

IO171PB4F16

IO172NB4F16

IO172PB4F16

IO173NB4F16

IO173PB4F16

IO174NB4F16

IO176NB4F16

IO176PB4F16

IO177NB4F16

AC20*

AC21*

W20

IO222PB5F20

IO223PB5F21

AE9

AE6

AE7

Y10

IO225NB5F21

Y20

IO225PB5F21

AD21

AD22

AA19

Y18

IO226NB5F21

Y16

IO226PB5F21

W10

T13

AB14

AB15

AE15

AE16

IO227PB5F21

IO228NB5F21

AB10

AB11

AD9

Y19

IO228PB5F21

AB19

IO229NB5F21

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Recommended to be used as

a single-ended I/O.

Recommended to be used as

a single-ended I/O.

Recommended to be used as

a single-ended I/O.

3-124

Revision 18

Axcelerator Family FPGAs

CG624

AX2000 Function

CG624

Number

AX2000 Function

IO256PB5F23

Bank 6

AX2000 Function

Number

IO229PB5F21

IO230NB5F21

IO233NB5F21

IO233PB5F21

IO234NB5F21

IO234PB5F21

IO236NB5F22

IO238NB5F22

IO238PB5F22

IO239NB5F22

IO239PB5F22

IO240NB5F22

IO242NB5F22

IO242PB5F22

IO243NB5F22

IO243PB5F22

IO244NB5F22

IO246NB5F23

IO246PB5F23

IO247NB5F23

IO247PB5F23

IO250NB5F23

IO250PB5F23

IO251NB5F23

IO251PB5F23

IO252NB5F23

IO252PB5F23

IO253NB5F23

IO253PB5F23

IO254NB5F23

IO254PB5F23

IO256NB5F23

AD10

V11

AD7

AD8

AA6*

IO284NB6F26

IO284PB6F26

IO285NB6F26

IO285PB6F26

IO286NB6F26

IO286PB6F26

IO287NB6F26

IO287PB6F26

IO288NB6F26

IO290NB6F27

IO291NB6F27

IO291PB6F27

IO292NB6F27

IO292PB6F27

IO293NB6F27

IO293PB6F27

IO294NB6F27

IO296NB6F27

IO296PB6F27

IO298NB6F27

IO298PB6F27

IO299NB6F27

IO299PB6F27

IO257NB6F24

IO257PB6F24

IO258NB6F24

IO258PB6F24

IO259NB6F24

IO259PB6F24

IO260NB6F24

IO260PB6F24

IO262NB6F24

IO262PB6F24

IO263NB6F24

IO263PB6F24

IO268NB6F25

IO268PB6F25

IO269PB6F25

IO272NB6F25

IO272PB6F25

IO273NB6F25

IO273PB6F25

IO274NB6F25

IO274PB6F25

IO275NB6F25

IO275PB6F25

IO277NB6F25

IO278NB6F26

IO278PB6F26

IO279PB6F26

IO280NB6F26

IO281NB6F26

IO281PB6F26

AA3

V10

AC9

AA2

AB2

V6*

W4*

AE4

AE5

AB9

AA9

AD5

AD6

AB8

AC8

AB7

AC7

AA8

Bank 7

IO300NB7F28

IO300PB7F28

IO302NB7F28

IO304NB7F28

IO304PB7F28

IO308NB7F28

IO309NB7F28

IO309PB7F28

P9*

N6*

AC5

AC6

AA1

AB1

AB6*

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Recommended to be used as

a single-ended I/O.

Recommended to be used as

a single-ended I/O.

Recommended to be used as

a single-ended I/O.

Revision 18

3-125

Package Pin Assignments

CG624

AX2000 Function

CG624

AX2000 Function

Number

AX2000 Function

IO310NB7F29

IO310PB7F29

IO311NB7F29

IO311PB7F29

IO313NB7F29

IO316NB7F29

IO316PB7F29

IO317NB7F29

IO317PB7F29

IO318NB7F29

IO318PB7F29

IO320NB7F29

IO321NB7F30

IO321PB7F30

IO323NB7F30

IO323PB7F30

IO324NB7F30

IO324PB7F30

IO327NB7F30

IO327PB7F30

IO328NB7F30

IO328PB7F30

IO329NB7F30

IO329PB7F30

IO331PB7F30

IO332NB7F31

IO332PB7F31

IO333NB7F31

IO333PB7F31

IO334NB7F31

IO334PB7F31

IO335NB7F31

Number

N10

IO335PB7F31

IO337NB7F31

IO338NB7F31

IO338PB7F31

IO339NB7F31

IO339PB7F31

IO340NB7F31

IO340PB7F31

IO341NB7F31

IO341PB7F31

GND

AE1

AE18

AE2

AE24

AE25

AE8

G4*

G3*

B24

B25

C10

C16

C23

Dedicated I/O

GND

A18

A24

D22

A25

E10

E16

E21

AA10

AA16

AA18

AA21

AA5

AB22

AB4

H21

H25

K21

K23

AC10

AC16

AC23

AC3

AD1

AD2

AD24

AD25

L11

L12

L13

L14

L15

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Recommended to be used as

a single-ended I/O.

Recommended to be used as

a single-ended I/O.

Recommended to be used as

a single-ended I/O.

3-126

Revision 18

Axcelerator Family FPGAs

CG624

AX2000 Function

CG624

AX2000 Function

CG624

Number

AX2000 Function

Number

AD11

AD4

AE12

AE17

B15

C15

GND

PRA

PRB

PRC

PRD

TCK

M11

M12

M13

M14

M15

N11

N12

N13

N14

N15

P11

P12

P13

P14

P15

R11

R12

R13

R14

R15

T21

T23

TDI

VCCDA

VCCIB0

VCCIB1

VCCIB2

TDO

TMS

TRST

VCCA

VCCDA

AB20

F22

J17

D13

E13

E19

F21

G10

K10

K11

K15

K16

L10

L16

R10

R16

T10

T11

T15

T16

U17

N21

W21

J10

J11

K12

A23

B23

C22

D21

J15

A12

A14

AA13

AA15

AA20

AA7

AB13

AC11

V25

F13

A13

AB12

AE13

J16

K14

C24

C25

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Recommended to be used as

a single-ended I/O.

Recommended to be used as

a single-ended I/O.

Recommended to be used as

a single-ended I/O.

Revision 18

3-127

Package Pin Assignments

CG624

AX2000 Function

Number

AX2000 Function

VCCIB2

VCCIB3

VCCIB4

VCCIB5

VCCIB6

Number

D23

E22

VCCIB6

VCCIB7

K17

VCCIB7

L17

VCCIB7

M16

AA22

AB23

AC24

AC25

P16

VCCIB7

M10

E12

J12

E14

H14

Y14

U14

Y12

U12

F12

H12

F14

J14

AA14

V14

AA12

V12

E20

VCCPLA

VCCPLB

VCCPLC

VCCPLD

VCCPLE

VCCPLF

VCCPLG

VCCPLH

VCOMPLA

VCOMPLB

VCOMPLC

VCOMPLD

VCOMPLE

VCOMPLF

VCOMPLG

VCOMPLH

VPUMP

R17

T17

AB21

AC22

AD23

AE23

T14

U15

U16

AB5

AC4

AD3

AE3

T12

U10

U11

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

AA4

AB3

AC1

AC2

P10

Recommended to be used as

a single-ended I/O.

Note: *Not routed on the same

package layer and to adjacent

LGA pads as its differential

pair complement.

Recommended to be used as

a single-ended I/O.

3-128

Revision 18

4 – Datasheet Information

List of Changes

The following table lists critical changes that were made in the current version of the document.

Revision

Changes

Page

Revision 18

(March 2012)

Table 2-1 • Absolute Maximum Ratings was updated to correct the maximum

DC core supply voltage (VCCA) from 1.6 V to 1.7 V (SAR 36786). The

maximum input voltage (VI) was corrected from 3.75 V to 4.1 V (SAR 35419).

2-1

Values for tristate leakage current IOZ, and IIH and IIL were added to Table 2-3

• Standby Current (SARs 35774, 32021).

2-2

2-9

Figure 2-2 • VCCPLX and VCOMPLX Power Supply Connect was updated to

correct the units for the resistance from "W" to Ω (SAR 36415).

In the Introduction to the "User I/Os" section, the following sentence was added

to clarify the slew rate setting (SAR 34943):

2-11

The slew rate setting is effective for both rising and falling edges.

Figure 2-3 • Use of an External Resistor for 5 V Tolerance was revised to show

the VCCI and GND clamp diodes. The explanatory text above the figure was

revised as well (SAR 34942).

2-13

EQ 3 for 5 V tolerance was corrected to change Vdiode from 0.6 V to 0.7 V

(SAR 36786).

2-13

2-17

Additional information was added to the "Using the Weak Pull-Up and Pull-Down

Circuits" section to clarify how the weak pull-up and pull-down resistors are

physically implemented (SAR 34945).

The description for the C_INCLKparameter in Table 2-18 • Input Capacitance was

changed from "Input capacitance on clock pin" to "Input capacitance on HCLK

and RCLK pin" (SAR 34944).

2-21

Table 2-19 • I/O Input Rise Time and Fall Time* is new (SAR 34942).

2-21

The minimum VIL for 1.5 V LVCMOS and PCI was corrected from –0.5 to –0.3 in

Table 2-29 • DC Input and Output Levels and Table 2-33 • DC Input and Output

Levels (SAR 34358).

2-38, 2-40

Support for simulating the GCLR/ GPSET feature in the Axcelerator Family was

added in Libero software v9.0 SPI1. Reference to the section explaining this in

the Antifuse Macro Library Guide was added to the "R-Cell" section (SAR

26413).

2-58

The enable signal in Figure 2-32 • R-Cell Delays was corrected to show it is

active low rather than active high (SAR 34946).

2-59

iii

Revision 17

The versioning system for datasheets has been changed. Datasheets are

(September 2011) assigned a revision number that increments each time the datasheet is revised.

The "Axcelerator Family Device Status" table indicates the status for each

device in the device family.

The "Features" section, "Programmable Interconnect Element" section, and i, 1-1, 2-108

"Security" section were revised to clarify that although no existing security

measures can give an absolute guarantee, Microsemi FPGAs implement the

best security available in the industry (SAR 32865).

Revision 18

4-1

Datasheet Information

Revision

Changes

Page

Revision 17

(continued)

The C180 package was removed from product tables and the "Package Pin

Assignments" section (PDN 0909).

3-1

Package names used in the"Axcelerator Family Product Profile" and "Package

Pin Assignments" section were revised to match standards given in Package

Mechanical Drawings (SAR 27395).

i, 3-1

2-11

The "Introduction" section for "User I/Os" was updated as follows:

"The user does not need to assign VREF pins for OUTBUF and TRIBUF. VREF

pins are needed only for input and bidirectional I/Os" (SARs 24181, 24309).

Power values in Table 2-4 • Default CLOAD/VCCI were updated to reflect those

of SmartPower (SAR 33945).

2-3

Two parameter names were corrected in Figure 2-10 • Output Buffer Delays.

One occurrence of t_ENLZwas changed to t_ENZLand one occurrence of t_ENHZ

was changed to t_ENZH(SAR 33890).

2-22

The "Timing Model" section was updated with new timing values. Timing tables 2-8, 2-26 to

in the "I/O Specifications" section were updated to include enable paths. Values

in the timing tables in the "Voltage-Referenced I/O Standards" section and

"Differential Standards" section were updated. Table 2-63 • R-Cell was updated

(SAR 33945).

2-53

Figure 2-11 • Timing Model was replaced (SAR 33043).

2-23

2-90 to 2-106

2-108

The timing tables for "RAM" and "FIFO" were updated (SAR 33945).

"Data Registers (DRs)" values were modified for IDCODE and USERCODE

(SARs 18257, 26406).

The package diagram for the "CQ208" package was incorrect and has been

replaced with the correct diagram (SARs 23865, 26345).

3-89

N/A

Revision 16

(v2.8, Oct. 2009)

The datasheet was updated to include AX2000-CQ2526 information.

MIL-STD-883 Class B is no longer supported by Axcelerator FPGAs and as a

result was removed.

N/A

A footnote was added to the "Introduction" in the "Axcelerator Clock

Management System" section.

2-75

Revision 15

(v2.7, Nov. 2008)

RoHS-compliant information was added to the "Ordering Information".

ACTgen was changed to SmartGen because ACTgen is obsolete.

N/A

2-3

Revision 14

(v2.6)

In Table 2-4, the units for the P_LOAD, P₁₀, and P_I/Owere updated from mW/MHz

to mW/MHz.

In the "Pin Descriptions"section, the HCLK and CLK descriptions were updated

to include tie-off information.

2-9

The "Global Resource Distribution" section was updated.

The " CG624" table was updated.

2-70

3-116

2-1

Revision 13

(v2.5)

A note was added to Table 2-2.

In the "Package Thermal Characteristics", the temperature was changed from

150°C to 125°C.

2-6

4-2

Revision 18

Axcelerator Family FPGAs

Revision

Changes

Page

Revision 12

(v2.4)

Revised ordering information and timing data to reflect phase out of –3 speed

grade options.

Table 2-3 was updated.

Revision 11

(v2.3)

The "Packaging Data" section is new.

Table 2-2 was updated.

2-1

2-9

2-10

2-11

1-2

2-1

2-3

2-4

2-7

2-8

"VCCDA Supply Voltage" was updated.

"PRA/B/C/D Probe A, B, C and D" was updated.

The "User I/Os" was updated.

Figure 1-3 was updated.

Revision 10

(v2.2)

Table 2-2 was updated.

The "Power-Up/Down Sequence" section was updated.

Table 2-4 was updated.

Table 2-5 was updated.

The "Timing Characteristics" section was added.

Table 2-7 was updated.

Figure 2-1 was updated.

The External Setup and Clock-to-Out (Pad-to-Pad) equations in the "Hardwired

Clock – Using LVTTL 24 mA High Slew Clock I/O" section were updated.

The External Setup and Clock-to-Out (Pad-to-Pad) in the "Routed Clock – Using

LVTTL 24 mA High Slew Clock I/O" section were updated.

2-8

The "Global Pins" section was updated.

The "User I/Os" section was updated.

Table 2-17 was updated.

2-10

2-11

2-19

2-20

2-24

Figure 2-8 was updated.

Figure 2-13 and Figure 2-14 were updated.

The following timing parameters were renamed in I/O timing characteristic 2-26 to 2-52

tables from Table 2-22 to Table 2-60:

t_IOCLKQ> t_ICLKQ

t_IOCLKY> t_OCLKQ

Timing numbers were updated from Table 2-22 to Table 2-78.

The "R-Cell" section was updated.

Figure 2-59 was updated.

2-26 to 2-69

2-58

2-89

Figure 2-60 was updated.

2-89

Figure 2-67 was updated.

2-100

Figure 2-68 was updated.

2-101

Table 2-89 to Table 2-93 were updated.

Table 2-98 to Table 2-102 were updated.

2-90 to 2-94

2-102 to

2-106

Revision 18

4-3

Datasheet Information

Revision

Changes

Page

Revision 10

(continued)

The "TRST" section was updated.

2-107

The "Global Set Fuse" section was added.

2-109

3-52

A footnote was added to "FG896" for the AX2000 regarding pins AB1, AE2, G1,

and K2.

Pinouts for the AX250, AX500, and AX1000 were added for "CQ352".

Pinout for the AX1000 was added for "CG624".

Table 2-79 was updated.

3-98

3-115

2-69

2-106

Revision 9

(v2.1)

The "Low Power Mode" section was updated.

Table 1 has been updated.

Revision 8

(v2.0)

The "Ordering Information" section has been updated.

The "Device Resources" section has been updated.

The "Temperature Grade Offerings" section is new.

The "Speed Grade and Temperature Grade Matrix" section has been updated.

Table 2-9 has been updated.

iii

2-12

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-9

Table 2-10 has been updated.

Table 2-1 has been updated.

Table 2-2 has been updated.

Table 2-3 has been updated.

Table 2-4 has been updated.

Table 2-5 has been updated.

The "Power Estimation Example" section has been updated.

The "Thermal Characteristics" section has been updated.

The "Package Thermal Characteristics" section has been updated.

The "Timing Characteristics" section has been updated.

The "Pin Descriptions" section has been updated.

Timing numbers have been updated from the "3.3 V LVTTL" section to the 2-25 to 2-59

"Timing Characteristics" section. Many AC Loads were updated as well.

Timing characteristics for the "Hardwired Clocks" and "Routed Clocks" sections

were updated.

2-66, 2-68

Table 2-89 to Table 2-92 and Table 2-98 to Table 2-99 were updated.

2-90 to 2-93,

2-102 to

2-103

The following sections were updated:

2-106 to

2-110

"Low Power Mode", "Interface", "Data Registers (DRs)", "Security", "Silicon

Explorer II Probe Interface", and "Programming"

In the "PQ208" (AX500) section, pins 2, 52, and 156 changed from V_CCDAto

V_CCA. For pins 170 and 171, the I/O names refer to pair 23 instead of 24.

3-84

4-4

Revision 18

Axcelerator Family FPGAs

Revision

Changes

Page

Revision 8

(continued)

The following changes were made in the "FG676"(AX500) section:

3-37

AE2, AE25

AF2, AF25

AB4, AF24, C1, C26

AD15

Change from NC to GND.

Changed from GND to NC

Changed from V_CCDAto V_CCA

Change from V_CCDAto V_COMPLE

Changed from V_COMPLEto V_CCDA

AD17

In the "FG896" (AX2000) section, the AK28 changed from VCCIB5 to VCCIB4.

The "CQ352" and "CG624" sections are new.

All I/O FIFO capability was removed.

Table 1 was updated.

3-52

3-98, 3-115

n/a

Revision 7

(Advance v1.6)

Figure 1-9 was updated.

1-7

Figure 2-5 was updated.

2-16

3-21

2-2

The "Using an I/O Register" section was updated.

The AX250 and AX1000 descriptions were added to the "FG484"section.

Table 2-3 was updated.

Revision 6

(Advance v1.5)

Figure 2-1 was updated.

2-8

Figure 2-48 was updated.

2-75

2-82

3-84

Figure 2-52 was updated.

Revision 5

(Advance v1.4)

In the "PQ208" table, pin 196 was missing, but it has been added in this version

with a function of GND.

The following pins in the "FG484" table for AX500 were changed:

Pin G7 is GND/LP

3-21

Pins AB8, C10, C11, C14, AB16 are NC.

The "FG676" table was updated.

3-37

Revision 4

(Advance v1.3)

The "Device Resources" section was updated for the CS180.

The "Programmable Interconnect Element" and Figure 1-2 are new.

The "CS180" table is new.

1-1 and 1-2

3-1

The "PQ208" tables for the AX500 were updated. The following pins were not

3-84

defined in the previous version:

GND 21

IO106PB5F10/CLKHP 71

GND 136

Revision 3

(Advance v1.2)

Table 1, "Ordering Information", "Device Resources", and the Product Plan table

were updated.

i, ii

The following figures and tables were updated:

1-2

1-6

2-2

Figure 1-3

Figure 1-8 (new)

Table 2-3

2-9

2-12

2-23

Figure 2-2

Table 2-8

Figure 2-11

The "Design Environment" section was updated.

1-7

2-6

The "Package Thermal Characteristics" was updated.

Revision 18

4-5

Datasheet Information

Revision

Changes

Page

Revision 3

(continued)

The timing characteristics tables from pages 2-26 to 2-60 were updated.

2-26 to 2-60

The "Global Resources" section was updated.

2-66

The timing characteristics tables from pages 2-102 to 2-103 were updated.

2-102 to

2-103

The "PQ208", "FG256", and "FG324" tables are new.

3-9,3-16, 3-84

4-6

Revision 18

Axcelerator Family FPGAs

Datasheet Categories

AX250-1CQ208M [MICROSEMI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E