EDI81256C55FM [MICROSEMI]

Standard SRAM, CDFP28, CERAMIC, DFP-28;


型号：	EDI81256C55FM
厂家：	Microsemi
描述：	Standard SRAM, CDFP28, CERAMIC, DFP-28 CD 静态存储器内存集成电路
文件：	总7页 (文件大小：137K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EDI81256C

HI-RELIABILITY PRODUCT

256Kx1 High Speed Monolithic SRAM CMOS

FEATURES

The EDI88128CS is a high speed, high performance, megabit

density Monolithic CMOS Static RAM organized as 128Kx8.

■ 128Kx8 bit CMOS Static

■ Random Access Memory

The device has eight bi-directional input-output lines to provide

simultaneous access to all bits in a word. An automatic power

down feature permits the on-chip circuitry to enter a very low

standbymode andbe brought backintooperationat a speedequal

to the address access time.

• Fast Access Times of 35, 45, 55ns

• Data Retention Function (LP)

• TTL Compatible Inputs and Outputs

• Fully Static, No Clocks

■ JEDEC Approved Pinouts

A Low Power version with 2V Data Retention (EDI88128LPS) is

also available for battery back-up opperation. Military product is

available compliant of MIL-PRF-38535.

• 24 pin Ceramic DIP (Package 3)

• 28 pad Ceramic LCC (Package 14)

• 28 lead Ceramic Flatpack (Package 79)

■ Single +5V (±10%) Supply Operation

FIG. 1 PIN CONFIGURATION

24 DIP

28 FLATPACK

TOP VIEW

PIN DESCRIPTION

TOP VIEW

Data Input

Data Output

28 VCC

AØ

24 VCC

27 A17

26 A16

25 A15

23 A17

22 A16

21 A15

A0-17

Address Inputs

Write Enable

Chip Select

A14

A13

A12

A11

A10

A14

A13

A12

A11

A10

VCC

VSS

Power (+5V ±10%)

Ground

Not Connected

WE 13

SS 14

BLOCK DIAGRAM

28 CLCC

TOP VIEW

Memory Array

Address

Buffer

Address

Decoder

I/O

Circuits

Ø-17

A16

A15

A14

A13

A12

A11

A10

July 1996 Rev. 8

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI81256C

TRUTH TABLE

ABSOLUTE MAXIMUM RATINGS

Parameter

Unit

Mode

Output

High Z

Power

Icc², Icc3

Icc1

Standby

Output Deselect

Read

Voltage on any pin relative to Vss

-0.5 to 7.0

High Z

Data Out

Data In

Operating Temperature TA (Ambient)

Commercial

Icc1

0 to +70

-40 to +85

-55 to +125

-65 to +150

°C

Write

Icc1

Industrial

Military

RECOMMENDED OPERATING CONDITIONS

Storage Temperature, Plastic

Power Dissipation

Output Current

Junction Temperature, T^J

NOTE:

Stress greater than those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions greater than those indi-

cated in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

Parameter

Symbol

VCC

Min

4.5

Typ

5.0

Max

5.5

Unit

Supply Voltage

Input High Voltage

Input Low Voltage

°C

VSS

175

VIH

2.2

-0.3

—

6.0

+0.8

V^IL

CAPACITANCE

(TA = +25°C)

Max

Parameter

Symbol

Condition

Unit

LCC, DIP,

Flatpack

Address Lines

Data Lines

IN = Vcc or Vss, f = 1.0MHz

C^D/Q

VOUT = Vcc or Vss, f = 1.0MHz

These parameters are sampled, not 100% tested.

DC CHARACTERISTICS

(VCC= 5V, TA = -55°C to +125°C)

Parameter

Symbol

Conditions

Units

Min

-5

Typ

—

Max

Input Leakage Current

ILI

VIN = 0V to VCC

120

µA

Output Leakage Current

ILO

VI/O = 0V to VCC

-5

Operating Power Supply Current

Standby (TTL) Power Supply Current

ICC1

ICC2

WE, CS = VIL, II/O = 0mA, Min Cycle

CS ≥ VIH, VIN ≤ VIL, VIN ≥ VIH

—

2.4

CS ≥ VCC -0.2V

Full Standby Power Supply Current

ICC3

VIN ≥ Vcc -0.2V or VIN ≤ 0.2V

0.5

—

1.5

0.4

—

Output Low Voltage

Output High Voltage

VOL

V^OH

IOL = 8.0mA

IOH = -4.0mA

NOTE: DC test conditions: V^IL= 0.3V, VIH = Vcc -0.3V

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI81256C

AC CHARACTERISTICS – READ CYCLE

(VCC = 5.0V, VSS = 0V, TA = 0°C to +70°C)

Symbol

35ns

45ns

55ns

Parameter

JEDEC

tAVAV

tAVQV

tELQV

tELQX

tEHQZ

Alt.

tRC

tAA

tACS

tCLZ

tCHZ

tOH

tPU

tPD

Min

Max

Min

Max

Min

Max

Units

Read Cycle Time

Address Access Time

Chip Enable Access Time

Chip Enable to Output in Low Z (1)

Chip Disable to Output in High Z (1)

Output Hold from Address Change

Chip Enable to Power Up (1)

Chip Enable to Power Down (1)

tAVQX

tELICCH

tEHICCL

1. This parameter is guaranteed by design but not tested.

AC CHARACTERISTICS – WRITE CYCLE

(VCC = 5.0V, VSS = 0V, TA = 0°C to +70°C)

Symbol

JEDEC

35ns

45ns

55ns

Parameter

Alt.

Min

Max

Min

Max

Min

Max

Units

Write Cycle Time

Chip Enable to End of Write

tAVAV

tWC

tELWH

tELEH

tCW

Address Setup Time

Address Valid to End of Write

Write Pulse Width

tAVWL

tAVEL

tAS

tAVWH

tAVEH

tAW

tWLWH

tWLEH

tWP

Write Recovery Time

Data Hold Time

tWHAX

tEHAX

tWR

tWHDX

tEHDX

tDH

Write to Output in High Z (1)

Data to Write Time

tWLQZ

tWHZ

tDVWH

tDVEH

tDW

Output Active from End of Write (1)

tWHQX

tWLZ

1. This parameter is guaranteed by design but not tested.

AC TEST CONDITIONS

Figure 1

Figure 2

Input Pulse Levels

VSS to 3.0V

Vcc

Input Rise and Fall Times

Input and Output Timing Levels

Output Load

5ns

1.5V

480Ω

Figure 1

NOTE: For t^EHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)

30pF

5pF

255Ω

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI81256C

FIG. 2

TIMING WAVEFORM - READ CYCLE

t_AVAV

ADDRESS

t_AVAV

t_EHICCL

t_ELQV

t_ELQX

ADDRESS

DATA I/O

ADDRESS 1

ADDRESS 2

t_EHQZ

HIGH Z

DATA I/O

Icc

DATA VALID

t_AVQV

t_AVQX

t_ELICCH

DATA 1

DATA 2

READ CYCLE 2 (WE HIGH)

READ CYCLE 1 (WE HIGH; OE, CS LOW)

FIG. 3

WRITE CYCLE - WE CONTROLLED

t_AVAV

ADDRESS

t_AVWH

t_ELWH

t_WHAX

t_AVWL

t_WLWH

t_DVWH

t_WHDX

DATA IN

DATA VALID

t_WHQX

t_WLQZ

HIGH Z

DATA OUT

WRITE CYCLE 1, WE CONTROLLED

FIG. 4

WRITE CYCLE - CS CONTROLLED

t_AVAV

ADDRESS

WS32K32-XHX

t_AVEH

t_ELEH

t_EHAX

t_AVEL

t_WLEH

t_DVEH

t_EHDX

DATA IN

DATA VALID

HIGH Z

DATA OUT

WRITE CYCLE 2, CS CONTROLLED

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI81256C

DATA RETENTION CHARACTERISTICS (EDI81256LP ONLY)

(TA = -55°C to +125°C)

Characteristic

Sym

Conditions

Min

Typ

Max

Units

Low Power Version only

Data Retention Voltage

VDD

ICCDR

TCDR

T^R

VDD = 2.0V

–

500

–

µA

Data Retention Quiescent Current

Chip Disable to Data Retention Time (1)

Operation Recovery Time (1)

CS ≥ VDD -0.2V

VIN ≥ VDD -0.2V

or VIN ≤ 0.2V

–

TAVAV*

–

NOTE:

1. Parameter guaranteed by design, but not tested.

* Read Cycle Time

FIG. 5

DATA RETENTION - CS CONTROLLED

^{Data Retention M}W^odeS32K32-XHX

4.5V

Vcc

t_CDR

t_R

CS = VDD -0.2V

DATA RETENTION, CS CONTROLLED

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI81256C

PACKAGE 3: 24 PIN SIDEBRAZED CERAMIC DIP (300 mils wide)

1.280

MAX

Pin 1 Indicator

0.060

0.015

0.175

0.125

0.200

MAX

0.320

0.290

0.023

0.014

0.100

TYP

0.098

MAX

11 x 0.100 = 1.100

ALL DIMENSIONS ARE IN INCHES

PACKAGE 14: 28 PAD CERAMIC LCC

0.120

0.060

0.095

0.075

0.050

TYP

0.050

TYP

0.560

0.540

0.028

0.022

0.360

0.340

ALL DIMENSIONS ARE IN INCHES

PACKAGE 79: 28 PIN CERAMIC FLATPACK

0.740

MAX

0.006

0.003

0.370

0.250

0.420

0.380

0.180

MIN

1.00 TYP

Pin 1

0.045

0.026

0.019

0.015

0.045

MAX

0.130

0.100

0.050

BSC

ALL DIMENSIONS ARE IN INCHES

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

EDI81256C

ORDERING INFORMATION

EDI 8 8 128 CS X X X

WHITE ELECTRONIC DESIGNS

SRAM

ORGANIZATION, 128Kx8

TECHNOLOGY:

C = CMOS Standard Power

LP = Low Power

ACCESS TIME (ns)

PACKAGE TYPE:

C = 32 lead Sidebrazed DIP, 300 mil (Package 3)

F = 32 lead Ceramic Flatpack (Package 79)

L = 32 pad Ceramic LCC (Package 14)

DEVICE GRADE:

B = MIL-STD-883 Compliant

M= Military Screened

I = Industrial

C = Commercial

-55°C to +125°C

-40°C to +85°C

0°C to +70°C

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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