EDI88130CS15FI [MICROSEMI]
Standard SRAM, 128KX8, 15ns, CMOS, CDFP32, CERAMIC, FP-32;
| 型号： | EDI88130CS15FI |
| 厂家： | 
Microsemi |
| 描述： | Standard SRAM, 128KX8, 15ns, CMOS, CDFP32, CERAMIC, FP-32 CD 静态存储器 |
| 文件： | 总9页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI88130CS
HI-RELIABILITY PRODUCT
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
The EDI88130CS is a high speed, high performance, 128Kx8 bits
monolithic Static RAM.
■ Access Times of 15*, 17, 20, 25, 35, 45, 55ns
■ Battery Back-up Operation
• 2V Data Retention (EDI88130LPS)
An additional chip enable line provides system memory security
during power down in non-battery backed up systems and memory
banking in high speed battery backed systems where large mul-
tiple pages of memory are required.
■ CS1, CS2 & OE Functions for Bus Control
■ Inputs and Outputs Directly TTL Compatible
■ Organized as 128Kx8
The EDI88130CS has eight bi-directional input-output lines to
provide simultaneous access to all bits in a word.
■ Commercial, Industrial and Military Temperature Ranges
■ Thru-hole and Surface Mount Packages JEDEC Pinout
A low power version, EDI88130LPS, offers a 2V data retention
function for battery back-up applications.
• 32 pin Sidebrazed Ceramic DIP, 400 mil (Package 102)
• 32 pin Sidebrazed Ceramic DIP, 600 mil (Package 9)
• 32 lead Ceramic SOJ (Package 140)
Military product is available compliant to MIL-PRF-38535.
*
15ns access time is advanced information, contact factory for availability.
• 32 pad Ceramic Quad LCC (Package 12)
• 32 pad Ceramic LCC (Package 141)
• 32 lead Ceramic Flatpack (Package 142)
■ Single +5V (±10%) Supply Operation
FIG. 1 PIN CONFIGURATION
32 DIP
32 SOJ
32 CLCC
32 FLATPACK
PIN DESCRIPTION
32 QUAD LCC
TOP VIEW
I/O0-7
A0-16
WE
Data Inputs/Outputs
Address Inputs
Write Enable
TOP VIEW
4
3
2
1
32
31 30
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2 10
A1 11
AØ 12
I/OØ 13
I/O1 14
I/O2 15
1
2
3
4
5
6
7
8
9
32 VCC
CS1, CS2
OE
Chip Selects
31 A15
30 CS2
29 WE
28 A13
27 A8
5
6
29
28
27
26
25
24
23
22
21
A
7
6
5
4
3
2
1
0
0
WE
Output Enable
Power (+5V ±10%)
Ground
A
A
A
A
A
13
VCC
7
A
8
8
A
9
VSS
26 A9
9
A
11
NC
Not Connected
25 A11
24 OE
23 A10
22 CS1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
10
11
12
13
A
OE
10
CS
I/O
A
A
BLOCK DIAGRAM
A
1
I/O
7
Memory Array
14
15
16
17 18
19
20
V
SS 16
Address
Buffer
Address
Decoder
I/O
Circuits
A
Ø-16
I/OØ-7
WE
CS
1
CS2
OE
1
February 2000 Rev. 9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88130CS
TRUTH TABLE
ABSOLUTE MAXIMUM RATINGS
OE
X
X
H
L
X
CS1
H
X
L
L
CS2
X
L
H
H
WE
Mode
Standby
Standby
Output Deselect
Read
Output
High Z
High Z
High Z
Data Out
Data In
Power
Icc2, Icc3
Icc2, Icc3
Icc1
Parameter
Unit
V
Voltage on any pin relative to Vss
Operating Temperature TA (Ambient)
Industrial
-0.2 to 7.0
X
X
H
H
L
-40 to +85
-55 to +125
-65 to +150
1.7
°C
°C
°C
W
Military
Icc1
Storage Temperature, Ceramic
Power Dissipation
L
H
Write
Icc1
Output Current
Junction Temperature, TJ
40
175
mA
°C
CAPACITANCE
(TA = +25°C)
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indi-
cated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Max
CSOJ,DIP,
Unit
Parameter
Symbol
Condition
LCC
Flatpack
Address Lines
Data Lines
CI
V
IN = Vcc or Vss, f = 1.0MHz
6
8
12
14
pF
pF
CO
V
OUT = Vcc or Vss, f = 1.0MHz
RECOMMENDED OPERATING CONDITIONS
These parameters are sampled, not 100% tested.
Parameter
Symbol
VCC
VSS
VIH
VIL
Min
4.5
0
2.2
-0.5
Typ
5.0
0
—
—
Max
5.5
0
Vcc +0.5
+0.8
Unit
V
V
V
V
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
DC CHARACTERISTICS
(VCC = 5V, TA = -55°C to +125°C)
Parameter
Symbol
Conditions
Units
Min
—
—
—
—
—
—
—
—
—
—
—
2.4
Typ
—
—
Max
Input Leakage Current
Output Leakage Current
ILI
ILO
VIN = 0V to VCC
VI/O = 0V to VCC
±5
±10
300
225
200
25
60
10
15
5
µA
µA
(15-17ns)
(20ns)
(25-55ns)
(17-55ns)
(15ns)
CS (17-55ns)
CS (15ns)
LPS
mA
mA
mA
mA
mA
mA
mA
mA
V
Operating Power Supply Current
ICC1
ICC2
WE, CS1 = VIL, II/O = 0mA, CS2 = VIH
CS1 ≥ VIH and/or CS2 ≤ VIL,
VIN ≥ VIH or ≤ VIL
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
3
CS1 ≥ VCC -0.2V and/or CS2 ≤ 0.2V
ICC3
—
—
—
—
VIN ≥ Vcc -0.2V or VIN ≤ 0.2V
IOL = 8.0mA
Output Low Voltage
Output High Voltage
VOL
VOH
0.4
—
IOH = -4.0mA
V
AC TEST CONDITIONS
Figure 1
Figure 2
Input Pulse Levels
VSS to 3.0V
3ns
1.5V
Figure 1
Vcc
Vcc
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
480Ω
480Ω
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
Q
Q
30pF
5pF
255Ω
255Ω
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
2
EDI88130CS
AC CHARACTERISTICS – READ CYCLE (15 to 20ns)
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Symbol
15ns*
17ns
20ns
Parameter
JEDEC
tAVAV
tAVQV
tE1LQV
Alt.
tRC
tAA
Min
Max
Min
Max
Min
Max
Units
ns
Read Cycle Time
15
17
20
Address Access Time
Chip Enable Access Time
15
17
20
ns
tACS
tACS
15
15
17
17
20
20
ns
ns
tE2HQV
Chip Enable to Output in Low Z (1)
Chip Disable to Output in Low Z (1)
tE1LQX
tE2HQX
tCLZ
tCLZ
5
5
5
5
5
5
ns
ns
tE1HQZ
tE2LQZ
tCHZ
tCHZ
6
6
7
7
8
8
ns
ns
Output Hold from Address Change
Output Enable to Output Valid
tAVQX
tGLQV
tGLQX
tGHQZ
tOH
tOE
3
0
3
0
3
0
ns
ns
ns
ns
6
5
6
6
7
8
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
Chip Enable to Power Up (1)
tOLZ
tOHZ
tE1LICCH
tE2HICCH
tPU
tPU
0
0
0
0
0
0
ns
ns
Chip Enable to Power Down (1)
tE1HICCL
tE2LICCL
tPD
tPD
15
15
17
17
20
20
ns
ns
1. This parameter is guaranteed by design but not tested.
* 15ns access time is advanced information, contact factory for availability.
AC CHARACTERISTICS – READ CYCLE (25 to 55ns)
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Symbol
25ns
35ns
45ns
55ns
Parameter
JEDEC
tAVAV
tAVQV
tE1LQV
Alt.
tRC
Min
Max
Min
Max
Min
Max
Min
Max
Units
Read Cycle Time
25
35
45
55
ns
ns
ns
ns
Address Access Time
Chip Enable Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
tAA
25
25
25
35
35
35
45
45
45
55
55
55
tACS
tACS
tE2HQV
tE1LQX
tE2HQX
tCLZ
tCLZ
5
5
5
5
5
5
5
5
ns
ns
Chip Disable to Output in Low Z (1)
tE1HQZ
tE2LQZ
tCHZ
tCHZ
10
10
15
15
20
20
20
20
ns
ns
Output Hold from Address Change
Output Enable to Output Valid
tAVQX
tGLQV
tGLQX
tGHQZ
tOH
tOE
0
0
0
0
0
0
0
0
ns
ns
ns
ns
10
10
15
15
20
20
25
20
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
Chip Enable to Power Up (1)
tOLZ
tOHZ
tE1LICCH
tE2HICCH
tPU
tPU
0
0
0
0
0
0
0
0
ns
ns
Chip Enable to Power Down (1)
tE1HICCL
tE2LICCL
tPD
tPD
25
25
35
35
45
45
55
55
ns
ns
1. This parameter is guaranteed by design but not tested.
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88130CS
AC CHARACTERISTICS – WRITE CYCLE (15 to 20ns)
(VCC = 5.0V, VSS = 0V, TA = 0°C to +70°C)
Symbol
JEDEC
15ns*
17ns
20ns
Parameter
Alt.
Min
Max
Min
Max
Min
Max
Units
Write Cycle Time
Chip Enable to End of Write
tAVAV
tWC
15
17
20
ns
tE1LWH
tE1LE1H
tE2HWH
tE2HE2L
tCW
tCW
tCW
tCW
12
12
12
12
13
13
13
13
15
15
15
15
ns
ns
ns
ns
Address Setup Time
tAVWL
tAVE1L
tAVE2H
tAS
tAS
tAS
0
0
0
0
0
0
0
0
0
ns
ns
ns
Address Valid to End of Write
Write Pulse Width
tAVWH
tAW
12
13
15
ns
tWLWH
tWLE1H
tWLE2L
tWP
tWP
tWP
12
12
12
13
13
13
15
15
15
ns
ns
ns
Write Recovery Time
Data Hold Time
tWHAX
tE1HAX
tE2LAX
tWHDX
tE1HDX
tE2LDX
tWR
tWR
tWR
tDH
tDH
tDH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
Write to Output in High Z (1)
Data to Write Time
tWLQZ
tWHZ
0
7
0
8
0
8
ns
tDVWH
tDVE1H
tDVE2L
tDW
tDW
tDW
7
7
7
8
8
8
10
10
10
ns
ns
ns
Output Active from End of Write (1)
tWHQX
tWLZ
3
3
3
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE (25 to 55ns)
(VCC = 5.0V, VSS = 0V, TA = 0°C to +70°C)
Symbol
JEDEC
tAVAV
tE1LWH
tE1LE1H
tE2HWH
tE2HE2L
25ns
35ns
45ns
55ns
Parameter
Write Cycle Time
Chip Enable to End of Write
Alt.
tWC
tCW
tCW
tCW
tCW
Min
25
20
Max
Min
35
25
Max
Min
45
35
Max
Min
55
45
Max
Units
ns
ns
ns
ns
ns
16
16
20
20
25
25
40
40
16
20
25
40
Address Setup Time
tAVWL
tAVE1L
tAVE2H
tAS
tAS
tAS
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
Address Valid to End of Write
Write Pulse Width
tAVWH
tAVEH
tWLWH
tWLE1H
tWLE2L
tAW
tAW
tWP
tWP
tWP
20
20
20
20
20
25
25
30
30
30
35
35
30
30
30
45
45
35
35
35
ns
ns
ns
ns
ns
Write Recovery Time
Data Hold Time
tWHAX
tE1HAX
tE2LAX
tWHDX
tE1HDX
tE2LDX
tWR
tWR
tWR
tDH
tDH
tDH
0
0
0
0
0
0
0
0
0
0
0
0
5
5
5
0
0
0
5
5
5
0
0
0
ns
ns
ns
ns
ns
ns
Write to Output in High Z (1)
Data to Write Time
tWLQZ
tWHZ
0
10
0
13
0
15
0
20
ns
tDVWH
tDVE1H
tDVE2L
tDW
tDW
tDW
15
15
15
20
20
20
20
20
20
25
25
25
ns
ns
ns
Output Active from End of Write (1)
tWHQX
tWLZ
3
3
3
3
ns
1. This parameter is guaranteed by design but not tested.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
4
EDI88130CS
tAVAV
FIG. 2 TIMING WAVEFORM - READ CYCLES
ADDRESS
tAVQV
CS
1
tE1LQV
tE1HQZ
tE1HICCL
tE1LQX
tE1LICCH
Icc
tAVAV
tE2LICCL
tE2HQV
ADDRESS
DATA I/O
ADDRESS 1
ADDRESS 2
CS
2
tE2HICCH
tE2HQX
tAVQV
tAVQX
OE
tGLQV
tGLQX
tGHQZ
DATA 1
DATA 2
DATA I/O
READ CYCLE 2 (CS1 AND/OR CS2 CONTROLLED, WE HIGH)
READ CYCLE 1 (WE HIGH; OE, CS LOW)
FIG. 3 WRITE CYCLE 1
tAVAV
ADDRESS
tAVWH
tWLWH
tWHAX
tAVWL
WE
CS1
CS2
tE1LWH
tE2HWH
tDVWH
tWHDX
DATA IN
tWLQZ
tWHQX
DATA OUT
WRITE CYCLE 1 - LATE WRITE, WE CONTROLLED
FIG. 4 WRITE CYCLES 2
WRITE CYCLES 3
tAVAV
tAVAV
ADDRESS
ADDRESS
WS32K32-XHX
tAVE2H
tAVE1L
tE2HE2L
tE2LAX
tE1LE1H
tE1HAX
WE
WE
CS
1
CS1
CS
2
CS2
tDVE1H
tDVE2L
tE1HDX
tE2LDX
DATA I/O
DATA I/O
WRITE CYCLE 2 - EARLY WRITE, CS
1
CONTROLLED
WRITE CYCLE 3 - EARLY WRITE, CS
2
CONTROLLED
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88130CS
DATA RETENTION CHARACTERISTICS (EDI88130LPS ONLY)
(TA = -55°C to +125°C)
Characteristic
Sym
Conditions
Min
Typ
Max
Units
Low Power Version only
Data Retention Voltage
VDD
ICCDR
TCDR
TR
VDD = 2.0V
CS1 ≥ VDD -0.2V and/or CS2 ≥ VSS +0.2V
VIN ≥ VDD -0.2V
2
–
0.5
–
–
2
–
–
V
mA
ns
Data Retention Quiescent Current
Chip Disable to Data Retention Time (1)
Operation Recovery Time (1)
–
0
or VIN ≤ 0.2V
TAVAV*
–
ns
NOTE:
1. Parameter guaranteed by design, but not tested.
* Read Cycle Time
FIG. 5
DATA RETENTION - CS1 CONTROLLED
Data Retention MWodeS32K32-XHX
4.5V
4.5V
Vcc
V
DD
tCDR
tR
CS
2
CS2 ≤ 0.2V
DATA RETENTION, CS2 CONTROLLED
FIG. 6
DATA RETENTION - CS2 CONTROLLED
Data Retention Mode
WS32K32-XHX
4.5V
4.5V
Vcc
V
DD
tCDR
tR
CS2
CS2 ≤ 0.2V
DATA RETENTION, CS2 CONTROLLED
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
6
EDI88130CS
PACKAGE 12: 32 PIN CERAMIC QUAD LCC
0.120
0.060
0.020 X 45
REF.
0.028
0.022
0.050
BSC.
0.560
0.540
0.055
0.045
0.040 X 45
REF.
0.458
0.442
ALL DIMENSIONS ARE IN INCHES
PACKAGE 9: 32 PIN SIDEBRAZED CERAMIC DIP (600 mils wide)
1.616
1.584
0.620
0.600
0.060
0.040
Pin 1 Indicator
0.175
0.125
0.155
0.115
0.600
NOM
0.020
0.016
0.100
TYP
0.061
0.017
15 x 0.100 = 1.500
ALL DIMENSIONS ARE IN INCHES
PACKAGE 102: 32 PIN SIDEBRAZED CERAMIC DIP (400 mils wide)
1.616
1.584
0.420
0.400
0.060
0.040
Pin 1 Indicator
0.175
0.125
0.155
0.115
0.020
0.016
0.100
TYP
0.400
NOM
0.061
0.017
15 x 0.100 = 1.500
ALL DIMENSIONS ARE IN INCHES
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88130CS
PACKAGE 140: 32 LEAD CERAMIC SOJ
0.108
0.088
0.840
0.820
0.040
0.030
0.050
TYP
0.440
0.430
0.379
REF
0.155
0.120
ALL DIMENSIONS ARE IN INCHES
PACKAGE 141: 32 PAD CERAMIC LCC
0.096
0.080
0.028
0.022
0.840
0.820
0.050
TYP
0.405
0.395
ALL DIMENSIONS ARE IN INCHES
PACKAGE 142: 32 PIN CERAMIC FLATPACK
0.830
0.810
0.007
0.003
0.370
0.250
1.00 RE
0.290
0.270
0.420
0.400
0.040
0.030
Pin 1
0.019
0.015
0.045
0.020
0.116
0.100
0.050
TYP
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
8
EDI88130CS
ORDERING INFORMATION
EDI 8 8 130 CS X X X
WHITE ELECTRONIC DESIGNS
SRAM
ORGANIZATION, 128Kx8
(130 = Dual CS)
TECHNOLOGY:
CS = CMOS Standard Power (5V)
LPS = Low Power
ACCESS TIME (ns)
PACKAGE TYPE:
C = 32 lead Sidebrazed DIP, 600 mil (Package 9)
F = 32 lead Ceramic Flatpack (Package 142)
L = 32 pad Ceramic LCC (Package 141)
L32 = 32 pad Ceramic Quad LCC (Package 12)
N = 32 lead Ceramic SOJ (Package 140)
T = 32 lead Sidebrazed DIP, 400 mil (Package 102)
DEVICE GRADE:
B = MIL-STD-883 Compliant
M= Military Screened
I = Industrial
C = Commercial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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