EX128-CSG128A [MICROSEMI]
Field Programmable Gate Array,;
| 型号： | EX128-CSG128A |
| 厂家： | 
Microsemi |
| 描述： | Field Programmable Gate Array, 时钟 栅 可编程逻辑 |
| 文件： | 总52页 (文件大小：2722K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Revision 5
ex Automotive Family FPGAs
•
•
Live on Power-Up
Specifications
No Power-Up/Down Sequence Required for Supply
Voltages
•
•
•
•
3,000 to 12,000 Available System Gates
Maximum 512 Flip-Flops (Using CC Macros)
0.22 μm CMOS Process Technology
•
Configurable Weak Resistor Pull-Up or Pull-Down for
Tristated Outputs during Power-Up
Up to 132 User-Programmable I/O Pins
•
•
•
Individual Output Slew-Rate Control
2.5 V and 3.3 V I/Os
Software Design Support with Designer and Libero®
Features
Integrated Design Environment (IDE) Tools
•
250 MHz Internal Performance, Low-Power Antifuse
FPGA
•
•
•
Up to 100% Resource Utilization with 100% Pin Locking
Deterministic Timing
•
•
Advanced Small-Footprint Packages
Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
Pin-to-Pin Compatibility with eX Commercial- and
Industrial-Grade Devices
•
•
Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
•
•
•
Hot-Swap Compliant I/Os
Single-Chip Solution
Nonvolatile
FuseLock™ Secure Programming Technology Designed
to Prevent Reverse Engineering and Design Theft
Product Profile
Device
eX64
eX128
eX256
Capacity
3,000
2,000
6,000
4,000
12,000
8,000
System Gates
Typical Gates
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
64
128
128
256
256
512
Combinatorial Cells
Maximum User I/Os
128
84
256
100
512
132
Global Clocks
Hardwired
Routed
1
2
1
2
1
2
Speed Grades*
Std.
A
Std.
A
Std.
A
Temperature Grades*
Package (by pin count)
TQ
CS
64, 100
49, 128
64, 100
49, 128
100
128, 180
Note: * The eX family is also offered in commercial and industrial temperature grades with –F, –P, and Std. speed grades. Refer to
the eX Family FPGAs datasheet for more details.
October 2012
i
© 2012 Microsemi Corporation
Ordering Information
eX128
TQ
G
100
A
Application (Ambient Temperature Range)
A = Automotive (-40°C to 125°C)
Blank = Commercial (0°C to 70°C)
I = Industrial (-40°C to 85°C)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
=
TQ Thin Quad Flat Pack (1.4mm pitch)
=
CS Chip-Scale Package (0.8mm pitch)
Speed Grade
Blank= Standard Speed
P= Approximately 30% Faster than Standard
F= Approximately 40% Slower than Standard
Part Number
eX64 64 Dedicated Flip-Flops (3,000 System Gates)
=
eX128 = 128 Dedicated Flip-Flops (6,000 System Gates)
eX256 = 256 Dedicated Flip-Flops (12,000 System Gates)
Note: Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded based
on characterization across the recommended operating conditions. A-grade parts are not tested at extended temperatures. If
testing to ensure guaranteed operation at extended temperatures is required, please contact your local Microsemi SoC
Products Group Sales office to discuss testing options available.
Plastic Device Resources
User I/Os (Including Clock Buffers)
Device
eX64
TQ 64
41
TQ100
56
CS49
36
CS128
84
CS180
–
–
eX128
eX256
46
70
36
100
–
81
–
100
132
Note: Package Definitions:TQ = Thin Quad Flat Pack, CS = Chip Scale Package
Speed Grade and Temperature Grade Matrix
Std.
A
✓
Note: Refer to the eX Family FPGAs datasheet for more details on commercial- and industrial-grade offerings.
Contact your local Microsemi SoC Products Group representative for device availability.
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Revision 5
ex Automotive Family FPGAs
Table of Contents
ex Automotive Family FPGAs
ex Automotive Family FPGAs
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
eX Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
2.5 V LVCMOS2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
3.3 V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
CEQ Values for eX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
eX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
eX Family Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
Package Pin Assignments
TQ64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
TQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
CS49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
CS128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
CS180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Revision 5
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1 – ex Automotive Family FPGAs
General Description
Based on a 0.22 µm CMOS process technology, the eX family of FPGAs is a low-cost solution for low-
power, high-performance designs. With the automotive temperature grade support (–40ºC to 125ºC), the
eX devices can address many in-cabin telematics and automobile interconnect applications. The low-
power attributes inherent in antifuse technology make the eX devices ideal for designers who are looking
to integrate low-density, power-sensitive automotive applications into a programmable logic solution,
enabling quick time-to-market.
eX Family Architecture
The eX family is implemented on a high-voltage twin-well CMOS process using 0.22 µm design rules.
The eX family architecture uses a “sea-of-modules” structure where the entire floor of the device is
covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing.
Interconnection among these logic modules is achieved using Microsemi’s patented metal-to-metal
programmable antifuse interconnect elements. The antifuse interconnect is made up of a combination of
amorphous silicon and dielectric material with barrier metals and has an "on" state resistance of 25 Ω
with a capacitance of 1.0 fF for low-signal impedance. The antifuses are normally open circuit and, when
programmed, form a permanent low-impedance connection. The eX family provides two types of logic
modules, the register cell (R-cell) and the combinatorial cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable
(using the S0 and S1 lines) control signals (Figure 1-1). The R-cell registers feature programmable clock
polarity selectable on a register-by-register basis. This provides additional flexibility while allowing
mapping of synthesized functions into the eX FPGA. The clock source for the R-cell can be chosen from
either the hardwired clock or the routed clock.
The C-cell implements a range of combinatorial functions up to five inputs (Figure 1-2 on page 1-2).
Inclusion of the DB input and its associated inverter function enables the implementation of more than
4,000 combinatorial functions in the eX architecture in a single module.
Two C-cells can be combined together to create a flip-flop to imitate an R-cell via the use of the CC
macro. This is particularly useful when implementing nontiming-critical paths and when the design
engineer is running out of R-cells. For more information about the CC macro, refer to the Maximizing
Logic Utilization in eX, SX and SX-A FPGA Devices Using CC Macros application note.
Routed
Data Input
S1
S0
PSET
DirectConnect
Input
D
Q
Y
HCLK
CLKA,
CLKB,
Internal Logic
CLR
CKS
CKP
Figure 1-1 • R-Cell
Revision 5
1-1
ex Automotive Family FPGAs
Module Organization
C-cell and R-cell logic modules are arranged into horizontal banks called Clusters, each of which
contains two C-cells and one R-cell in a C-R-C configuration.
Clusters are further organized into modules called SuperClusters for improved design efficiency and
device performance, as shown in Figure 1-3 on page 1-3. Each SuperCluster is a two-wide grouping of
Clusters.
Routing Resources
Clusters and SuperClusters can be connected through the use of two innovative local routing resources
called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of
modules within Clusters and SuperClusters (Figure 1-4 on page 1-3). This routing architecture also
dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest
possible performance.
DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring
R-cell in a given SuperCluster. DirectConnect uses a hardwired signal path requiring no programmable
interconnection to achieve its fast signal propagation time of less than 0.1 ns.
FastConnect enables horizontal routing between any two logic modules within a given SuperCluster and
vertical routing with the SuperCluster immediately below it. Only one programmable connection is used
in a FastConnect path, delivering maximum pin-to-pin propagation of 0.6 ns.
In addition to DirectConnect and FastConnect, the architecture makes use of two globally oriented
routing resources, known as segmented routing and high-drive routing. Microsemi’s segmented routing
structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact
combination of track lengths and antifuses within each path is chosen by the fully automatic place-and-
route software to minimize signal propagation delays.
D0
D1
Y
D2
D3
Sa
Sb
DB
A0 B0
A1 B1
Figure 1-2 • C-Cell
1-2
Revision 5
ex Automotive Family FPGAs
R-Cell
C-Cell
Routed
Data Input
D0
D1
S1
S0
PSET
CLR
Y
D2
D3
DirectConnect
Input
Q
D
Y
Sb
Sa
HCLK
CLKA,
DB
CLKB,
Internal Logic
CKS
CKP
A0 B0
A1 B1
Cluster
Cluster
SuperCluster
Figure 1-3 • Cluster Organization
DirectConnect
• No antifuses
• 0.1 ns routing delay
SuperClusters
FastConnect
• One antifuse
• 0.6 ns routing delay
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Figure 1-4 • DirectConnect and FastConnect for SuperClusters
Revision 5
1-3
ex Automotive Family FPGAs
Clock Resources
eX’s high-drive routing structure provides three clock networks. The first clock, called HCLK, is hardwired
from the HCLK buffer to the clock select MUX in each R-cell. HCLK cannot be connected to
combinational logic. This provides a dedicated propagation path for the clock signal for the automotive-
grade eX devices. The hardwired clock is tuned to provide a clock skew of less than 0.1 ns worst case. If
not used, the HCLK pin must be tied Low or High and must not be left floating. Figure 1-5 describes the
clock circuit used for the constant load HCLK.
HCLK does not function until the fourth clock cycle each time the device is powered up to prevent false
output levels due to any possible slow power-on-reset signal and fast start-up clock circuit. To activate
HCLK from the first cycle, the TRST pin must be reserved in the Designer software and the pin must be
tied to GND on the board. (See the "TRST, I/O Boundary Scan Reset Pin" on page 1-29).
The remaining two clocks (CLKA, CLKB) are global routed clock networks that can be sourced from
external pins or from internal logic signals (via the CLKINT routed clock buffer) within the eX device.
CLKA and CLKB may be connected to sequential cells or to combinational logic. If CLKA or CLKB is
sourced from internal logic signals, the external clock pin cannot be used for any other input and must be
tied Low or High and must not float. Figure 1-6 describes the CLKA and CLKB circuit used in eX devices.
Table 1-1 describes the possible connections of the routed clock networks, CLKA and CLKB.
Unused clock pins must not be left floating and must be tied to High or Low.
Constant Load
Clock Network
HCLKBUF
Figure 1-5 • eX HCLK Clock Pad
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
Figure 1-6 • eX Routed Clock Buffer
Table 1-1 • Connections of Routed Clock Networks, CLKA and CLKB
Module
C-Cell
Pins
A0, A1, B0 and B1
CLKA, CLKB, S0, S1, PSET, and CLR
EN
R-Cell
I/O Cell
1-4
Revision 5
ex Automotive Family FPGAs
Other Architectural Features
Performance
The combination of the various architectural features enables automotive-grade eX devices to operate
with internal clock frequencies at 250 MHz for fast execution of complex logic functions.
Automotive-grade eX devices are the optimal platforms upon which to integrate in-cabin telematics and
automobile interconnect applications previously only contained in ASICs or gate arrays.
eX devices meet the performance goals of gate arrays, and, at the same time, present significant
improvements in cost and time to market. Using timing-driven place-and-route tools, designers can
achieve highly deterministic device performance.
User Security
The FuseLock advantage is designed to prevent unauthorized users from being able to read back the
contents of a Microsemi antifuse FPGA. In addition to the inherent strengths of the architecture, there is
a special Security Fuse inside the eX device that is intended to disable the probing circuitry and prohibit
further programming of the device. This Fuse cannot be accessed or bypassed without destroying
access to the rest of the device, making Microsemi antifuse FPGAs highly resistant to both invasive and
more subtle noninvasive attacks.
Look for this symbol to ensure your valuable IP is protected with industry-standard security.
FuseLock
Figure 1-7 • FuseLock
For more information, refer to the Implementation of Security in Actel Antifuse FPGAs application note.
I/O Modules
Each I/O on an eX device can be configured as an input, an output, a tristate output, or a bidirectional
pin. I/O cells in eX devices do not contain embedded latches or flip-flops and can be inferred directly from
HDL code. The device can easily interface with any other device in the system, which in turn enables
parallel design of system components and reduces overall design time.
All unused I/Os are configured as tristate outputs by Designer software, for maximum flexibility when
designing new boards or migrating existing designs. However, it is still recommended to tie all unused I/O
pins to GND on the board. Each I/O module has an available pull-up or pull-down resistor of
approximately 50 kΩ that can configure the I/O in a known state during power-up. Just shortly before
VCCA reaches 2.5 V, the resistors are disabled and the I/Os will be controlled by user logic.
Table 1-2 describes the I/O features of eX devices. For more information on I/Os, refer to the Microsemi
eX, SX-A, and RT54SX-S I/Os application note.
The automotive eX devices support I/O operation at 2.5 V and 3.3 V.
Revision 5
1-5
ex Automotive Family FPGAs
The detailed description of the I/O pins in eX automotive devices can be found in "Pin Descriptions" on
page 1-28.
Table 1-2 • I/O Features
Function
Description
Input Buffer Threshold • 3.3 V LVTTL
Selection
•
2.5 V LVCMOS2
Nominal Output Drive
•
•
3.3 V LVTTL
2.5 V LVCMO 2
Output Buffer
“Hot-Swap” Capability
•
•
•
I/O on an unpowered device does not sink current
Can be used for “cold sparing”
Selectable on an individual I/O basis
Individually selectable low-slew option
Power-Up
Individually selectable pull-ups and pull-downs during power-up (default is to
power-up in tristate)
Enables deterministic power-up of device
VCCA and VCCI can be powered in any order
Hot Swapping
eX I/Os are configured to be hot-swappable. During power-up/down (or partial up/down), all I/Os are
tristated, provided VCCA ramps up within a diode drop of VCCI. VCCA and VCCI do not have to be
stable during power-up/down, and they do not require a specific power-up or power-down sequence in
order to avoid damage to the eX devices. In addition, all outputs can be programmed to have a weak
resistor pull-up or pull-down for tristate output at power-up. After the eX device is plugged into an
electrically active system, the device will not degrade the reliability of or cause damage to the host
system. The device's output pins are driven to a high impedance state until normal chip operating
conditions are reached. Please see the application note, Microsemi SX-A and RT54SX-S Devices in Hot-
Swap and Cold-Sparing Applications, which also applies to eX devices, for more information on hot
swapping.
Power Requirements
Power consumption is extremely low for the automotive-grade eX devices due to the low capacitance of
the antifuse interconnects. The antifuse architecture does not require active circuitry to hold a charge (as
do SRAM or EPROM), making it the lowest-power FPGA architecture available today.
1-6
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ex Automotive Family FPGAs
Figure 1-8 through Figure 1-11 on page 1-8 show some sample power characteristics of eX devices.
Notes:
1. Device filled with 16-bit counters.
2. VCCA, VCCI = 2.7 V, device tested at room temperature.
Figure 1-8 • eX Dynamic Power Consumption – High Frequency
80
70
60
50
40
30
20
10
0
eX64
eX128
eX256
0
10
20
30
40
50
Frequency (MHz)
Notes:
1. Device filled with 16-bit counters.
2. VCCA, VCCI = 2.7 V, device tested at room temperature.
Figure 1-9 • eX Dynamic Power Consumption – Low Frequency
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180
160
140
120
100
80
32-bit Decoder
8 x 8-bit Counters
SDRAM Controller
60
40
20
0
0
25
50
75
100
125
150
175
200
Frequency (MHz)
Figure 1-10 • Total Dynamic Power (mW)
12
10
8
5% DC
10% DC
15% DC
6
4
2
0
0
10
20
30
40
50
60
Frequency (MHz)
Figure 1-11 • System Power at 5%, 10%, and 15% Duty Cycle
1-8
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ex Automotive Family FPGAs
Boundary Scan Testing (BST)
All eX devices are IEEE 1149.1 compliant. eX devices offer superior diagnostic and testing capabilities by
providing Boundary Scan Testing (BST) and probing capabilities. These functions are controlled through
the special test pins (TMS, TDI, TCK, TDO and TRST). The functionality of each pin is defined by two
available modes, Dedicated and Flexible, and is described in Table 1-3. In the dedicated test mode,
TCK, TDI, and TDO are dedicated pins and cannot be used as regular I/Os. In flexible mode (default
mode), TMS should be set High through a pull-up resistor of 10 kΩ. TMS can be pulled Low to initiate the
test sequence.
Table 1-3 • Boundary Scan Pin Functionality
Dedicated Test Mode
Flexible Mode
TCK, TDI, TDO are dedicated BST pins
TCK, TDI, TDO are flexible and may be used as I/Os
No need for pull-up resistor for TMS and TDI Use a pull-up resistor of 10 kΩ on TMS
Dedicated Test Mode
In Dedicated mode, all JTAG pins are reserved for BST; designers cannot use them as regular I/Os. An
internal pull-up resistor is automatically enabled on both TMS and TDI pins, and the TMS pin will function
as defined in the IEEE 1149.1 (JTAG) specification.
To select Dedicated mode, users need to reserve the JTAG pins in Designer software by checking the
"Reserve JTAG" box in "Device Selection Wizard" (Figure 1-12). JTAG pins comply with LVTTL/TTL I/O
specification regardless of whether they are used as a user I/O or a JTAG I/O. Refer to the "3.3 V LVTTL
Electrical Specifications" on page 1-16 for detailed specifications.
Figure 1-12 • Device Selection Wizard
Flexible Mode
In Flexible mode, TDI, TCK and TDO may be used as either user I/Os or as JTAG input pins. The internal
resistors on the TMS and TDI pins are disabled in flexible JTAG mode, and an external 10 kΩ pull-
resistor to VCCI is required on the TMS pin.
To select the Flexible mode, users need to uncheck the "Reserve JTAG" box in "Device Selection
Wizard" in the Designer software. The functionality of TDI, TCK, and TDO pins is controlled by the BST
TAP controller. The TAP controller receives two control inputs; TMS and TCK. Upon power-up, the TAP
controller enters the Test-Logic-Reset state. In this state, TDI, TCK, and TDO function as user I/Os. The
TDI, TCK, and TDO pins are transformed from user I/Os into BST pins when the TMS pin is Low at the
first rising edge of TCK. The TDI, TCK, and TDO pins return to user I/Os when TMS is held High for at
least five TCK cycles.
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Table 1-4 describes the different configuration requirements of BST pins and their functionality in
different modes.
Table 1-4 • Boundary Scan Pin Configurations and Functions
Mode
Designer "Reserve JTAG" Selection
TAP Controller State
Any
Dedicated (JTAG)
Flexible (User I/O)
Flexible (JTAG)
Checked
Unchecked
Unchecked
Test-Logic-Reset
Any EXCEPT Test-Logic-Reset
TRST Pin
The TRST pin functions as a dedicated Boundary-Scan Reset pin when the "Reserve JTAG Test Reset"
option is selected as shown in Figure 1-12. An internal pull-up resistor is permanently enabled on the
TRST pin in this mode. It is recommended to connect this pin to GND in normal operation to keep the
JTAG state controller in the Test-Logic-Reset state. When JTAG is being used, it can be left floating or be
driven High.
When the "Reserve JTAG Test Reset" option is not selected, this pin will function as a regular I/O. If
unused as an I/O in the design, it will be configured as a tristated output.
JTAG Instructions
Table 1-5 lists the supported instructions with the corresponding IR codes for eX devices.
Table 1-5 • JTAG Instruction Code
Instructions (IR4: IR0)
EXTEST
Binary Code
00000
SAMPLE / PRELOAD
INTEST
00001
00010
USERCODE
IDCODE
00011
00100
HIGHZ
01110
CLAMP
01111
Diagnostic
10000
BYPASS
11111
Reserved
All others
Table 1-6 lists the codes returned after executing the IDCODE instruction for eX devices. Note that bit 0
is always "1." Bits 11-1 are always "02F," which is Microsemi's manufacturer code.
Table 1-6 • IDCODE for eX Devices
Device
eX64
Revision
Bits 31-28
Bits 27-12
40B2, 42B2
40B0, 42B0
40B5, 42B5
40B2, 42B2
40B0, 42B0
40B5, 42B5
0
0
0
1
1
1
8
9
eX128
eX256
eX64
9
A
B
B
eX128
eX256
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Programming
Device programming is supported through Silicon Sculptor series of programmers. In particular, Silicon
Sculptor II is a compact, robust, single-site and multi-site device programmer for the PC.
With standalone software, Silicon Sculptor II allows concurrent programming of multiple units from the
same PC, ensuring the fastest programming times possible. Each fuse is subsequently verified by Silicon
Sculptor II to insure correct programming. In addition, integrity tests ensure that no extra fuses are
programmed. Silicon Sculptor II also provides extensive hardware self-testing capability.
The procedure for programming an eX device using Silicon Sculptor II is as follows:
1. Load the *.AFM file
2. Select the device to be programmed
3. Begin programming
When the design is ready to go to production, Microsemi offers device volume-programming services
either through distribution partners or via in-house programming from the factory.
For more details on programming eX Automotive devices, please refer to the Programming Antifuse
Devices and the Silicon Sculptor II User's Guides.
Probing Capabilities
Automotive-grade eX devices provide internal probing capability that is accessed with the JTAG pins.
The Silicon Explorer II Diagnostic hardware is used to control the TDI, TCK, TMS, and TDO pins to select
the desired nets for debugging. The user assigns the selected internal nets in the Silicon Explorer II
software to the PRA/PRB output pins for observation. Probing functionality is activated when the BST
pins are in JTAG mode and the TRST pin is driven High or left floating. If the TRST pin is held Low, the
TAP controller will remain in the Test-Logic-Reset state, so no probing can be performed. The Silicon
Explorer II automatically places the device into JTAG mode, but the user must drive the TRST pin High or
allow the internal pull-up resistor to pull TRST High.
When you select the "Reserve Probe" box, as shown in Figure 1-12 on page 1-9, the Designer software
reserves the PRA and PRB pins as dedicated outputs for probing. This "reserve" option is merely a
guideline. If the Designer software requires that the PRA and PRB pins be user I/Os to achieve
successful layout, the tool will use these pins for user I/Os. If you assign user I/Os to the PRA and PRB
pins and select the "Reserve Probe" option, Designer Layout will override the option and place user
I/Os on those pins.
To allow for probing capabilities, the security fuse must not be programmed. Programming the security
fuse will disable the probe circuitry. Table 1-7 on page 1-12 summarizes the possible device
configurations for probing once the device leaves the "Test-Logic-Reset" JTAG state.
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Silicon Explorer II Probe
Silicon Explorer II is an integrated hardware and software solution that, in conjunction with Designer
software tools, allows users to examine any of the internal nets of the device while it is operating in a
prototype or a production system. The user can probe into an eX device via the PRA and PRB pins
without changing the placement and routing of the design and without using any additional resources.
Silicon Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the
debug cycle.
Silicon Explorer II does not require relayout or additional MUXes to bring signals out to an external pin,
which is necessary when using programmable logic devices from other suppliers.
Silicon Explorer II samples data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II
attaches to a PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer.
Silicon Explorer II allows designers to complete the design verification process at their desks and
reduces verification time from several hours per cycle to a few seconds.
The Silicon Explorer II tool uses the boundary scan ports (TDI, TCK, TMS and TDO) to select the desired
nets for verification. The selected internal nets are assigned to the PRA/PRB pins for observation.
Figure 1-13 illustrates the interconnection between Silicon Explorer II and the automotive-grade eX
device to perform in-circuit verification.
Design Considerations
The TDI, TCK, TDO, PRA, and PRB pins should not be used as input or bidirectional ports. Since these
pins are active during probing, critical signals input through these pins are not available while probing. In
addition, the Security Fuse should not be programmed because doing so disables the probe circuitry. It is
recommended to use a 70Ω series termination resistor on every probe connector (TDI, TCK, TMS, TDO,
PRA, PRB). The 70 Ω series termination is used to prevent data transmission corruption during probing
and reading back the checksum.
Table 1-7 • Device Configuration Options for Probe Capability (TRST pin reserved)
JTAG
Mode
Security Fuse
Programmed
TRST1
Low
Low
High
High
–
PRA, PRB2
User I/O3
User I/O3
TDI, TCK, TDO2
Probing Unavailable
User I/O3
Dedicated
Flexible
Dedicated
Flexible
–
No
No
No
No
Yes
Probe Circuit Outputs
Probe Circuit Outputs
Probe Circuit Secured
Probe Circuit Inputs
Probe Circuit Inputs
Probe Circuit Secured
Notes:
1. If TRST pin is not reserved, the device behaves according to TRST = High in the table.
2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are
active during probing, input signals will not pass through these pins and may cause contention.
3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are
automatically tristated by Designer software.
1-12
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16 Pin
Connection
eX FPGAs
TDI
TCK
TMS
TDO
Serial
Silicon Explorer II
Connection
PRA
PRB
22 Pin
Connection
Additional 16 Channels
(Logic Analyzer)
Figure 1-13 • Silicon Explorer II Probe Setup
Development Tool Support
The automotive-grade eX family of FPGAs is fully supported by both the Libero® Integrated Design
Environment (IDE) and Designer FPGA Development software. Libero IDE is a design management
environment, seamlessly integrating design tools while guiding the user through the design flow,
managing all design and log files, and passing necessary design data among tools. Libero IDE allows
users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a
single environment. Libero IDE includes Synplify® for Actel from Synplicity®, ViewDraw® for Actel from
Mentor Graphics®, ModelSim® HDL Simulator from Mentor Graphics, WaveFormer Lite™ from
SynaptiCAD®, and Designer software from Microsemi. Refer to the Libero IDE flow (located on the
Microsemi SoC Products Group website) diagram for more information.
Designer software is a place-and-route tool and provides a comprehensive suite of backend support
tools for FPGA development. The Designer software includes timing-driven place-and-route, and a
world-class integrated static timing analyzer and constraints editor. With the Designer software, a user
can select and lock package pins while only minimally impacting the results of place-and-route.
Additionally, the back-annotation flow is compatible with all the major simulators and the simulation
results can be cross-probed with Silicon Explorer II, Microsemi’s integrated verification and logic analysis
tool. Another tool included in the Designer software is the SmartGen core builder, which easily creates
popular and commonly used logic functions for implementation into your schematic or HDL design.
Designer software is compatible with the most popular FPGA design entry and verification tools from
companies such as Mentor Graphics, Synplicity, Synopsys®, and Cadence Design Systems. The
Designer software is available for both the Windows and UNIX operating systems.
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Related Documents
Datasheet
eX Family FPGAs
www.microsemi.com/soc/documents/eX_DS.pdf
Application Notes
Maximizing Logic Utilization in eX, SX and SX-A FPGA Devices Using CC Macros
www.microsemi.com/soc/documents/CC_Macro_AN.pdf
Implementation of Security in Actel Antifuse FPGAs
www.microsemi.com/soc/documents/Antifuse_Security_AN.pdf
Microsemi eX, SX-A, and RT54SX-S I/Os
www.microsemi.com/soc/documents/antifuseIO_AN.pdf
Microsemi SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications
www.microsemi.com/soc/documents/HotSwapColdSparing_AN.pdf
Design for Low Power in Actel Antifuse FPGAs
www.microsemi.com/soc/documents/Low_Power_AN.pdf
Programming Antifuse Devices
www.microsemi.com/soc/documents/AntifuseProgram_AN.pdf
User Guides
Silicon Sculptor II User's Guide
www.microsemi.com/soc/techdocs/manuals/default.asp#programmers
Miscellaneous
Libero IDE flow
www.microsemi.com/soc/products/tools/libero/flow.html
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Operating Conditions
Table 1-8 • Absolute Maximum Ratings*
Symbol
VCCI
VCCA
VI
Parameter
Limits
Units
V
DC Supply Voltage for I/Os
DC Supply Voltage for Array
Input Voltage
–0.3 to +4.0
–0.3 to +3.0
V
–0.5 to VCCI + 0.5
–0.5 to +VCCI
–65 to +150
V
VO
Output Voltage
V
TSTG
Tj
Storage Temperature
Maximum Junction Temperature
°C
°C
–65 to +150
Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Exposure to temperatures between absolute maximum and recommended operating conditions for extended
periods may affect device reliability. Devices should not be operated outside the Recommended Operating
Conditions.
Table 1-9 • Recommended Operating Conditions
Parameter
Automotive
–40 to +125
2.3 to 2.7
Units
°C
Temperature Range (Tj)
2.5 V Power Supply Range
(VCCA, VCCI)
V
3.3 V Power Supply Range (VCCI)
3.0 to 3.6
V
Note: Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been
guard banded based on characterization across the recommended operating conditions. A-grade parts are not
tested at extended temperatures. If testing to ensure guaranteed operation at extended temperatures is
required, contact your local Microsemi SoC Products Group Sales office to discuss testing options available.
Table 1-10 • Typical Automotive-Grade eX Standby Current at 25°C
VCCA= 2.5 V
VCCI = 2.5 V
VCCA = 2.5 V
VCCI = 3.3 V
Product
eX64
397 µA
696 µA
698 µA
497 µA
795 µA
796 µA
eX128
eX256
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2.5 V LVCMOS2 Electrical Specifications
Automotive
Symbol
VOH
VOL
Parameter
Min.
Max.
Units
V
VCCI = MIN, VI = VIH or VIL
VCCI = MIN, VI = VIH or VIL
Input Low Voltage, VOUT ≤ VOL(max)
Input High Voltage, VOUT ≥ VOH(min)
Input Leakage Current, VIN = VCCI or GND
Tristate Output Leakage Current, VOUT = Tristate
Input Transition Time tR, tF
(IOH = –1 mA)
(IOL= 1 mA)
2.0
0.4
0.7
V
VIL
V
VIH
1.7
–20
–20
V
IIL / IIH
IOZ
20
20
10
10
25
µA
µA
ns
pF
mA
2
tR, tF1,
CIN
Input Capacitance
ICC3
Standby Current
IV Curve
Notes:
Can be derived from the IBIS model at www.microsemi.com/soc/download/ibis/default.aspx.
1.
t is the transition time from 0.7 V to 1.7 V.
R
2. t is the transition time from 1.7 V to 0.7 V.
F
3. ICC = ICCI + ICCA
3.3 V LVTTL Electrical Specifications
Automotive
Symbol
VOH
Parameter
Min.
Max.
Units
V
VCCI = MIN, VI = VIH or VIL
VCCI = MIN, VI = VIH or VIL
Input Low Voltage, VOUT ≤ VOL(max)
Input High Voltage, VOUT ≥ VOH(min)
Input Leakage Current, VIN = VCCI or GND
Tristate Output Leakage Current, VOUT = Tristate
Input Transition Time tR, tF
(IOH = –3.5 mA)
(IOL= 3.5 mA)
2.4
VOL
0.4
0.8
V
VIL
V
VIH
2.0
–20
–20
V
IIL / IIH
IOZ
20
20
10
10
35
µA
µA
ns
pF
mA
tR, tF1,2
CIN
Input Capacitance
ICC3
IV Curve
Notes:
Standby Current
Can be derived from the IBIS model at www.microsemi.com/soc/download/ibis/default.aspx.
1.
t is the transition time from 0.8 V to 2.0 V.
R
2. t is the transition time from 2.0 V to 0.8 V.
F
3. ICC = ICCI + ICCA
4. JTAG pins comply with LVTTL/TTL I/O specification regardless of whether they are used as a user I/O or a JTAG I/O.
1-16
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5 V Tolerance of 3.3 V LVTTL I/Os Using a Tristate Buffer
Input: 3.3 V LVTTL I/Os are 5-V-input tolerant only if the non-PCI mode is used (no clamp diode).
Output: To configure an eX device to drive 5 V with VCCI = 3.3 V, users can utilize an Open Drain
configuration of the I/O cell with an array inverter cell and an external pull-up resistor to 5 V. The
recommended configuration is illustrated in Figure 1-14. The I/O configuration must be set to LVTTL to
disable the PCI clamp diode. For the recommended resistor value in a specific application, please
contact Microsemi SoC Products Group Technical Support. For more details, refer to the Design Tips
section of the Microsemi eX, SX-A and RT54SX-S I/Os application note.
Actel Open Drain Configuration
5 V
User Internal Signal
E
PAD
TRIBUFF
Figure 1-14 • Open-Drain Configuration for eX
Power Dissipation
Power consumption for eX devices can be divided into two components: static and dynamic.
Static Power Component
The power due to standby current is typically a small component of the overall power. Typical standby
current for eX devices is listed in Table 1-10 on page 1-15. For example, the typical static power for
eX128 at 3.3 V VCCI is:
ICC * VCCA = 795 µA x 2.5 V = 1.99 mW
EQ 1
Dynamic Power Component
Power dissipation in CMOS devices is usually dominated by the dynamic power dissipation. This
component is frequency-dependent and a function of the logic and the external I/O. Dynamic power
dissipation results from charging internal chip capacitance. An additional component of the dynamic
power dissipation is the totem pole current in the CMOS transistor pairs. The net effect can be associated
with an equivalent capacitance that can be combined with frequency and voltage to represent dynamic
power dissipation.
Dynamic power dissipation = CEQ * VCCA2 x F
EQ 2
where:
CEQ = Equivalent capacitance
F
= switching frequency
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ex Automotive Family FPGAs
Equivalent capacitance is calculated by measuring ICCA at a specified frequency and voltage for each
circuit component of interest. Measurements have been made over a range of frequencies at a fixed
value of VCCA. Equivalent capacitance is frequency-independent, so the results can be used over a wide
range of operating conditions. Equivalent capacitance values are shown below.
CEQ Values for eX Devices
Combinatorial modules (Ceqcm)
1.70 pF
1.70 pF
1.30 pF
7.40 pF
1.05 pF
Sequential modules (Ceqsm)
Input buffers (Ceqi)
Output buffers (Ceqo)
Routed array clocks (Ceqcr)
The variable and fixed capacitance of other device components must also be taken into account when
estimating the dynamic power dissipation.
Table 1-11 shows the capacitance of the clock components of eX devices.
Table 1-11 • Capacitance of Clock Components of eX Devices
eX64
eX128
0.85 pF
eX256
0.85 pF
Dedicated array clock – variable (Ceqhv)
Dedicated array clock – fixed (Ceqhf)
Routed array clock A (r1)
0.85 pF
18.00 pF
23.00 pF
23.00 pF
20.00 pF
28.00 pF
28.00 pF
25.00 pF
35.00 pF
35.00 pF
Routed array clock B (r2)
The estimation of the dynamic power dissipation is a piece-wise linear summation of the power
dissipation of each component.
Dynamic power dissipation
= VCCA2 * [(mc * Ceqcm * fmC)Comb Modules + (ms * Ceqsm * fmS)Seq Modules + (n * Ceqi * fn)Input Buffers
+
(0.5 * (q1 * Ceqcr * fq1) + (r1 * fq1))RCLKA + (0.5 * (q2 * Ceqcr * fq2) + (r2 * fq2))RCLKB + (0.5 * (s1 * Ceqhv
* fs1)+(Ceqhf * fs1))HCLK] + VCCI2 * [(p * (Ceqo + CL) * fp)Output Buffers
where:
]
mc
ms
n
= Number of combinatorial cells switching at frequency fm, typically 20% of C-cells
= Number of sequential cells switching at frequency fm, typically 20% of R-cells
= Number of input buffers switching at frequency fn, typically number of inputs / 4
= Number of output buffers switching at frequency fp, typically number of outputs / 4
= Number of R-cells driven by routed array clock A
= Number of R-cells driven by routed array clock B
= Fixed capacitance due to routed array clock A
p
q1
q2
r1
r2
s1
= Fixed capacitance due to routed array clock B
= Number of R-cells driven by dedicated array clock
Ceqcm = Equivalent capacitance of combinatorial modules
Ceqsm = Equivalent capacitance of sequential modules
Ceqi
= Equivalent capacitance of input buffers
Ceqcr = Equivalent capacitance of routed array clocks
Ceqhv = Variable capacitance of dedicated array clock
Ceqhf = Fixed capacitance of dedicated array clock
Ceqo = Equivalent capacitance of output buffers
CL
fmc
fms
fn
= Average output loading capacitance, typically 10pF
= Average C-cell switching frequency, typically F/10
= Average R-cell switching frequency, typically F/10
= Average input buffer switching frequency, typically F/5
= Average output buffer switching frequency, typically F/5
= Frequency of routed clock A
fp
fq1
fq2
fs1
= Frequency of routed clock B
= Frequency of dedicated array clock
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The eX, SX-A and RTSX-S Power Calculator can be used to estimate the total power dissipation (static
and dynamic) of eX devices and can be found at
www.microsemi.com/soc/techdocs/calculators.aspx.
Junction Temperature
The temperature variable in the Designer software refers to the junction temperature, not the ambient
temperature. This is an important distinction because the heat generated from dynamic power
consumption is usually hotter than the ambient temperature. EQ , shown below, can be used to calculate
junction temperature. Please refer to Table 1-9 on page 1-15 for the recommended operating conditions.
Junction Temperature = ΔT + Ta(1)
EQ 3
Where:
Ta = Ambient Temperature
ΔT = Temperature gradient between junction (silicon) and ambient = θja * P
P = Power
θja = Junction to ambient of package. θja numbers are located in the "Package Thermal Characteristics"
on page 1-19.
Package Thermal Characteristics
The device junction-to-case thermal characteristic is θjc, and the junction-to-ambient air characteristic is
θja. The thermal characteristics for θja are shown with two different air flow rates. θjc is provided for reference.
The maximum junction temperature is 150°C.
The maximum power dissipation allowed for eX devices is a function of θja. A sample calculation of the
absolute maximum power dissipation allowed for a TQFP 100-pin package at automotive temperature
and still air is as follows:
Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C – 125°C
------------------------------------------------------------------------------------------------------------------------------------------ ----------------------------------------
Maximum Power Allowed =
=
= 0.746 W
θja(°C/W)
33.5°C/W
Table 1-12 • Package Thermal Characteristics
θja
θja 1.0 m/s
36.3
Package Type
Pin Count
64
θjc
Still Air
42.4
θja 2.5 m/s
34.0
Units
°C/W
°C/W
°C/W
°C/W
°C/W
Thin Quad Flat Pack
Thin Quad Flat Pack
Chip-Scale Package
Chip-Scale Package
Chip-Scale Package
12.0
14.0
100
33.5
27.4
25.0
49
72.2
59.5
54.1
128
54.1
44.6
40.6
180
57.8
47.6
43.3
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ex Automotive Family FPGAs
eX Timing Model
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
Combinatorial
Cell
t
t
= 0.5 ns
= 0.7 ns
I/O Module
I/O Module
IRD1
IRD2
t
= 1.3 ns
INYH
t
= 4.9 ns
DHL
t
= 1.1 ns
PD
t
t
t
= 0.6 ns
RD1
= 1.1 ns
RD4
= 1.9 ns
RD8
I/O Module
Register
Cell
t
= 4.0 ns
ENZL
D
Q
t
t
t
RD1
= 0.8 ns
= 0.6 ns
SUD
HD
= 0.0 ns
t
= 4.9 ns
DHL
Routed
Clock
t
= 2.3 ns
RCKH
t
= 1.0 ns
(100% Load)
RCO
I/O Module
Register
Cell
I/O Module
t
= 1.3 ns
t
= 4.0 ns
INYH
ENZL
t
= 0.5 ns
= 0.8 ns
IRD1
D
Q
t
t
t
RD1
= 0.6 ns
SUD
= 0.0 ns
HD
t
= 4.9 ns
DHL
Hardwired
Clock
t
t
RCO
= 1.8 ns
= 1.0 ns
HCKH
Note: *Values shown for eX128, worst-case automotive conditions (2.3 V VCCA, 3.3 V VCCI, 35 pF Pad Load).
Figure 1-15 • eX Timing Model
Hardwired Clock
External Setup = tINYH + tIRD1 + tSUD – tHCKH = 1.3 + 0.5 + 0.8 – 1.8 = 0.8 ns
Clock-to-Out (Pad-to-Pad), typical = tHCKH + tRCO + tRD1 + tDHL = 1.8 + 1.0 + 0.6 + 4.9 = 8.3 ns
Routed Clock
External Setup = tINYH + tIRD2 + tSUD – tRCKH = 1.3 + 0.7 + 0.8 – 2.3 = 0.5 ns
Clock-to-Out (Pad-to-Pad), typical = tRCKH + tRCO + tRD1 + tDHL = 2.3 + 1.0 + 0.6 + 4.9 = 8.8 ns
1-20
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Output Buffer Delays
E
D
PAD To AC test loads (shown below)
TRIBUFF
VCC
VCC
50%
VCC
50% 50%
VCC
In
50%
50%
VOH
1.5 V
GND
1.5 V
50%
GND
10%
En
GND
90%
En
VOH
Out
Out
1.5 V
1.5 V
Out
GND
VOL
VOL
tENZL
tDHL
tDLH
tENZH
tENHZ
tENLZ
Table 1-13 • Output Buffer Delays
AC Test Loads
Load 3
(Used to measure disable delays)
Load 1
(used to measure
propagation delay)
Load 2
(Used to measure enable delays)
GND
GND
VCC
VCC
To the output
under test
R to VCC for tPLZ
R to GND for tPHZ
R = 1 kΩ
R to VCC for tPZL
R to GND for tPHZ
R = 1 kΩ
35 pF
To the output
under test
To the output
under test
35 pF
5 pF
Figure 1-16 • AC Test Loads
Revision 5
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Input Buffer Delays
Y
PAD
INBUF
3 V
1.5 V 1.5 V
VCC
In
0 V
Out
50%
50%
GND
tINY
tINY
Table 1-14 • Input Buffer Delays
C-Cell Delays
S
A
B
Y
VCC
50%
VCC
50%
S, A, or B
50%
GND
50%
Out
GND
tPD
50%
tPD
tPD
GND
tPD
Out
VCC
50%
Table 1-15 • C-Cell Delays
1-22
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Cell Timing Characteristics
D
Q
PRESET
CLR
CLK
(Positive edge triggered)
tHD
D
tSUD
CLK
tHPWH
tRPWH
tHP
tHPWL, tRPWL
tRCO
Q
tPRESET
tCLR
tWASYN
CLR
PRESET
Figure 1-17 • Flip-Flops
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ex Automotive Family FPGAs
Timing Characteristics
Timing characteristics for eX devices fall into three categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer characteristics are common to all eX family members.
Internal routing delays are device-dependent. Design dependency means actual delays are not
determined until after placement and routing of the user’s design are complete. Delay values may then
be determined by using the Timer tool in the Designer software or performing simulation with post-layout
delays.
Table 1-17 on page 1-25 lists sample timing characteristics for automotive eX devices.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which are used for initial design performance
evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are
determined by net property assignment prior to placement and routing. Up to six percent of the nets in a
design may be designated as critical.
Long Tracks
Some nets in the design use long tracks. Long tracks are special routing resources that span multiple
rows, columns, or modules. Long tracks employ three to five antifuse connections. This increases
capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically,
no more than six percent of nets in a fully utilized device require long tracks. Long tracks contribute
approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout
routing delays.
Timing Derating
eX devices are manufactured with a CMOS process. Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating
voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating temperature, and worst-case processing.
Temperature and Voltage Derating Factors
Table 1-16 • Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, TJ = 125°C, VCCA = 2.3 V)
Junction Temperature (TJ)
VCCA
2.3
–55
0.70
0.65
0.61
–40
0.70
0.66
0.62
0
25
70
85
125
1.00
0.93
0.88
0.77
0.72
0.67
0.78
0.73
0.69
0.88
0.83
0.78
0.91
0.85
0.80
2.5
2.7
1-24
Revision 5
ex Automotive Family FPGAs
eX Family Timing Characteristics
Table 1-17 • eX Family Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, TJ = 125°C)
‘Std.’ Speed
Parameter
Description
Min.
Max.
Units
C-Cell Propagation Delays1
tPD
Internal Array Module
1.1
ns
Predicted Routing Delays2
tDC
FO = 1 Routing Delay, DirectConnect
0.1
0.6
0.6
0.7
0.9
1.1
1.9
2.8
ns
ns
ns
ns
ns
ns
ns
ns
tFC
FO = 1 Routing Delay, FastConnect
FO = Routing Delay
tRD1
tRD2
FO = 2 Routing Delay
FO = 3 Routing Delay
FO = 4 Routing Delay
FO = 8 Routing Delay
FO = 12 Routing Delay
tRD3
tRD4
tRD8
tRD12
R-Cell Timing
tRCO
Sequential Clock-to-Q
1.0
0.9
1.0
ns
ns
ns
ns
ns
ns
ns
ns
tCLR
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Hold Time
tPRESET
tSUD
0.8
0.0
2.2
0.6
0.6
tHD
tWASYN
tRECASYN
tHASYN
2.5 V Input Module Propagation Delays
tINYH
tINYL
Input Data Pad-to-Y High
Input Data Pad-to-Y Low
1.1
1.4
ns
ns
3.3 V Input Module Propagation Delays
tINYH
tINYL
Input Data Pad-to-Y High
Input Data Pad-to-Y Low
1.3
1.6
ns
ns
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
0.5
0.7
0.9
ns
ns
ns
1. For dual-module macros, use t + t
+ t
, t
+ t
+ t
or t
+ t
+ t
, whichever is appropriate.
PD
RD1
PDn RCO
RD1
PDn
PD1
RD1
SUD
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
performance.
3. Clock skew improves as the clock network becomes more heavily loaded.
4. Delays based on 35 pF loading.
Revision 5
1-25
ex Automotive Family FPGAs
Table 1-17 • eX Family Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, TJ = 125°C)
‘Std.’ Speed
Parameter
tIRD4
Description
Min.
Max.
Units
ns
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
1.1
1.9
2.8
tIRD8
ns
tIRD12
ns
Dedicated (Hardwired) Array Clock Networks
tHCKH
Input Low to High
(Pad to R-Cell Input)
1.8
1.8
ns
ns
tHCKL
Input High to Low
(Pad to R-Cell Input)
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
2.0
2.0
ns
ns
0.1
ns
Minimum Period
4.0
ns
fHMAX
Maximum Frequency
250
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input Low to High (Light Load)
(Pad to R-Cell Input)
1.6
1.6
1.9
1.9
2.3
2.3
ns
ns
ns
ns
ns
ns
Input High to Low (Light Load)
(Pad to R-Cell Input)
Input Low to High (50% Load)
(Pad to R-Cell Input)
Input High to Low (50% Load)
(Pad to R-Cell Input)
Input Low to High (100% Load)
(Pad to R-Cell Input)
Input High to Low (100% Load)
(Pad to R-Cell Input)
tRPWH
Min. Pulse Width High
2.0
2.0
ns
ns
ns
ns
ns
tRPWL
Min. Pulse Width Low
3
3
3
tRCKSW
tRCKSW
tRCKSW
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
0.3
0.2
0.1
2.5 V LVCMOS2 Output Module Timing4 (VCCI = 2.3 V)
tDLH
Data-to-Pad Low to High
Data-to-Pad High to Low
5.9
6.3
ns
ns
tDHL
Notes:
1. For dual-module macros, use t + t
+ t
, t
+ t
+ t
or t
+ t
+ t
, whichever is appropriate.
PD
RD1
PDn RCO
RD1
PDn
PD1
RD1
SUD
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
performance.
3. Clock skew improves as the clock network becomes more heavily loaded.
4. Delays based on 35 pF loading.
1-26
Revision 5
ex Automotive Family FPGAs
Table 1-17 • eX Family Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, TJ = 125°C)
‘Std.’ Speed
Parameter
tDHLS
tENZL
Description
Min.
Max.
20.8
4.5
Units
ns
Data-to-Pad High to Low—Low Slew
Enable-to-Pad, Z to L
ns
tENZLS
tENZH
tENLZ
Enable-to-Pad Z to L—Low Slew
Enable-to-Pad, Z to H
21.2
6.1
ns
ns
Enable-to-Pad, L to Z
3.8
ns
tENHZ
dTLH
Enable-to-Pad, H to Z
7.1
ns
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
Delta Delay vs. Load High to Low—Low Slew
0.058
0.028
0.090
ns/pF
ns/pF
ns/pF
dTHL
dTHLS
3.3 V LVTTL Output Module Timing1 (VCCI = 3.0 V)
tDLH
Data-to-Pad Low to High
5.0
4.9
ns
ns
tDHL
Data-to-Pad High to Low
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
dTLH
Data-to-Pad High to Low—Low Slew
Enable-to-Pad, Z to L
17.4
4.0
ns
ns
Enable-to-Pad Z to L—Low Slew
Enable-to-Pad, Z to H
17.4
5.0
ns
ns
Enable-to-Pad, L to Z
5.0
ns
Enable-to-Pad, H to Z
4.8
ns
Delta Delay vs. Load Low to High
Delta Delay vs. Load High to Low
Delta Delay vs. Load High to Low—Low Slew
0.038
0.028
0.090
ns/pF
ns/pF
ns/pF
dTHL
dTHLS
Notes:
1. For dual-module macros, use t + t
+ t
, t
+ t
+ t
or t
+ t
+ t
, whichever is appropriate.
PD
RD1
PDn RCO
RD1
PDn
PD1
RD1
SUD
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
performance.
3. Clock skew improves as the clock network becomes more heavily loaded.
4. Delays based on 35 pF loading.
Revision 5
1-27
ex Automotive Family FPGAs
Pin Descriptions
CLKA/B
Routed Clock A and B
These pins are clock inputs for clock distribution networks. Input levels are compatible with LVTTL and
LVCMOS specifications. The clock input is buffered prior to clocking the R-cells. If not used, this pin must
be set Low or High on the board. It must not be left floating.
GND
Ground
Low supply voltage.
HCLK
Dedicated (Hardwired) Array Clock
This pin is the clock input for sequential modules. Input levels are compatible with LVTTL and LVCMOS
specifications. This input is directly wired to each R-cell and offers clock speeds independent of the
number of R-cells being driven. If not used, this pin must be set Low or High on the board. It must not be
left floating.
I/O
Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output levels are
compatible with LVTTL and LVCMOS specifications. Unused I/O pins are automatically tristated by the
Designer software. It is recommended to tie unused I/Os to Low on the board. This also applies to dual-
purpose pins when configured as I/Os.
NC
No Connection
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
PRA/PRB, I/O
Probe A/B
The Probe pin is used to output data from any user-defined design node within the device. This
diagnostic pin can be used independently or in conjunction with the other probe pin to allow real-time
diagnostic output of any signal path within the device. The Probe pin can be employed as a user-defined
I/O when verification has been completed. The pin’s probe capabilities can be permanently disabled to
protect programmed design confidentiality.
TCK, I/O
Test Clock
Test clock input for diagnostic probe and device programming. In flexible mode, TCK becomes active
when the TMS pin is set Low (refer to Table 1-3 on page 1-9). This pin functions as an I/O when the
boundary scan state machine reaches the “logic reset” state.
TDI, I/O
Test Data Input
Serial input for boundary scan testing and diagnostic probe. In flexible mode, TDI is active when the TMS
pin is set Low (refer to Table 1-3 on page 1-9). This pin functions as an I/O when the boundary scan state
machine reaches the “logic reset” state.
TDO, I/O
Test Data Output
Serial output for boundary scan testing. In flexible mode, TDO is active when the TMS pin is set Low
(refer to Table 1-3 on page 1-9). This pin functions as an I/O when the boundary scan state machine
reaches the "logic reset" state. When Silicon Explorer is being used, TDO will act as an output when the
"checksum" command is run. It will return to a user I/O when "checksum" is complete.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1 boundary scan pins (TCK, TDI, TDO, TRST). In flexible
mode, when the TMS pin is set Low, the TCK, TDI, and TDO pins are boundary scan pins (refer to
Table 1-3 on page 1-9). Once the boundary scan pins are in test mode, they will remain in that mode until
the internal boundary scan state machine reaches the “logic reset” state. At this point, the boundary scan
pins will be released and will function as regular I/O pins. The “logic reset” state is reached five TCK
cycles after the TMS pin is set High. In dedicated test mode, TMS functions as specified in the IEEE
1149.1 specifications.
1-28
Revision 5
ex Automotive Family FPGAs
TRST, I/O
Boundary Scan Reset Pin
Once it is configured as the JTAG Reset pin, the TRST pin functions as an active-low input to
asynchronously initialize or reset the boundary scan circuit. The TRST pin is equipped with an internal
pull-up resistor. This pin functions as an I/O when the “Reserve JTAG Reset Pin” is not selected in the
Designer software.
VCCI
Supply Voltage
Supply voltage for I/Os.
VCCA
Supply Voltage
Supply voltage for Array.
Revision 5
1-29
2 – Package Pin Assignments
TQ64
64
1
TQ64
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/rescenter/package/index.html.
Revision 5
2-1
Package Pin Assignments
TQ64
TQ64
eX64
eX64
eX128
eX128
Pin Number
Function
GND
TDI, I/O
I/O
Function
Pin Number
33
Function
GND
I/O
Function
1
GND
TDI, I/O
I/O
GND
I/O
2
34
3
35
I/O
I/O
4
TMS
GND
VCCI
I/O
TMS
GND
VCCI
I/O
36
VCCA
VCCI
I/O
VCCA
VCCI
I/O
5
37
6
38
7
39
I/O
I/O
8
I/O
I/O
40
NC
I/O
9
NC
I/O
41
NC
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
I/O
42
I/O
I/O
TRST, I/O
I/O
TRST, I/O
I/O
43
I/O
I/O
44
VCCA
GND
GND
I/O
VCCA
GND
GND
I/O
NC
I/O
45
GND
I/O
GND
I/O
46
47
I/O
I/O
48
I/O
I/O
I/O
I/O
49
I/O
I/O
I/O
I/O
50
I/O
I/O
VCCI
I/O
VCCI
I/O
51
I/O
I/O
52
VCCI
I/O
VCCI
I/O
PRB, I/O
VCCA
GND
I/O
PRB, I/O
VCCA
GND
I/O
53
54
I/O
I/O
55
CLKA
CLKB
VCCA
GND
PRA, I/O
I/O
CLKA
CLKB
VCCA
GND
PRA, I/O
I/O
56
HCLK
I/O
HCLK
I/O
57
58
I/O
I/O
59
I/O
I/O
60
I/O
I/O
61
VCCI
I/O
VCCI
I/O
I/O
I/O
62
I/O
I/O
63
I/O
I/O
TDO, I/O
TDO, I/O
64
TCK, I/O
TCK, I/O
2-2
Revision 5
ex Automotive Family FPGAs
TQ100
100
1
TQ100
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/rescenter/package/index.html.
Revision 5
2-3
ex Automotive Family FPGAs
TQ100
TQ100
eX64
eX128
eX256
eX64
eX128
eX256
Pin Number
Function
GND
TDI, I/O
NC
Function
Function
Pin Number
36
Function
GND
NC
Function
Function
1
GND
TDI, I/O
NC
GND
TDI, I/O
I/O
GND
NC
GND
NC
2
37
3
38
I/O
I/O
I/O
4
NC
NC
I/O
39
HCLK
I/O
HCLK
I/O
HCLK
I/O
5
NC
NC
I/O
40
6
I/O
I/O
I/O
41
I/O
I/O
I/O
7
TMS
VCCI
GND
NC
TMS
VCCI
GND
I/O
TMS
VCCI
GND
I/O
42
I/O
I/O
I/O
8
43
I/O
I/O
I/O
9
44
VCCI
I/O
VCCI
I/O
VCCI
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
45
NC
I/O
I/O
46
I/O
I/O
I/O
I/O
I/O
I/O
47
I/O
I/O
I/O
NC
I/O
I/O
48
I/O
I/O
I/O
I/O
I/O
I/O
49
TDO, I/O
NC
TDO, I/O
I/O
TDO, I/O
I/O
NC
I/O
I/O
50
TRST, I/O
NC
TRST, I/O
I/O
TRST, I/O
I/O
51
GND
NC
GND
NC
GND
I/O
52
I/O
I/O
I/O
53
NC
NC
I/O
NC
I/O
I/O
54
NC
NC
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
55
I/O
I/O
I/O
56
I/O
I/O
I/O
NC
I/O
I/O
57
VCCA
VCCI
NC
VCCA
VCCI
I/O
VCCA
VCCI
I/O
NC
NC
I/O
58
NC
NC
I/O
59
I/O
I/O
I/O
60
I/O
I/O
I/O
I/O
I/O
I/O
61
NC
I/O
I/O
I/O
I/O
I/O
62
I/O
I/O
I/O
I/O
I/O
I/O
63
NC
I/O
I/O
I/O
I/O
I/O
64
I/O
I/O
I/O
I/O
I/O
I/O
65
NC
I/O
I/O
I/O
I/O
I/O
66
I/O
I/O
I/O
I/O
I/O
I/O
67
VCCA
GND
GND
I/O
VCCA
GND
GND
I/O
VCCA
GND
GND
I/O
I/O
I/O
I/O
68
PRB, I/O
VCCA
PRB, I/O
VCCA
PRB, I/O
VCCA
69
70
Revision 5
2-4
ex Automotive Family FPGAs
TQ100
eX64
eX128
eX256
Pin Number
71
Function
Function
Function
I/O
I/O
I/O
I/O
I/O
72
NC
73
NC
NC
I/O
74
NC
NC
I/O
75
NC
NC
I/O
76
NC
I/O
I/O
77
I/O
I/O
I/O
78
I/O
I/O
I/O
79
I/O
I/O
I/O
80
I/O
I/O
I/O
81
I/O
I/O
I/O
82
VCCI
I/O
VCCI
I/O
VCCI
I/O
83
84
I/O
I/O
I/O
85
I/O
I/O
I/O
86
I/O
I/O
I/O
87
CLKA
CLKB
NC
CLKA
CLKB
NC
CLKA
CLKB
NC
88
89
90
VCCA
GND
PRA, I/O
I/O
VCCA
GND
PRA, I/O
I/O
VCCA
GND
PRA, I/O
I/O
91
92
93
94
I/O
I/O
I/O
95
I/O
I/O
I/O
96
I/O
I/O
I/O
97
I/O
I/O
I/O
98
I/O
I/O
I/O
99
I/O
I/O
I/O
100
TCK, I/O
TCK, I/O
TCK, I/O
Revision 5
2-5
Package Pin Assignments
CS49
A1 Ball Pad Corner
1
2
3
5
6
7
4
A
B
C
D
E
F
G
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/rescenter/package/index.html.
2-6
Revision 5
ex Automotive Family FPGAs
CS49
eX64
CS49
eX128
eX64
eX128
Pin Number
A1
Function
Function
Pin Number
D5
Function
Function
I/O
I/O
I/O
VCCA
I/O
VCCA
I/O
A2
I/O
D6
A3
I/O
I/O
D7
I/O
I/O
A4
I/O
I/O
E1
I/O
I/O
A5
VCCA
I/O
VCCA
I/O
E2
TRST, I/O
VCCI
GND
I/O
TRST, I/O
VCCI
GND
I/O
A6
E3
A7
I/O
I/O
E4
B1
TCK, I/O
I/O
TCK, I/O
I/O
E5
B2
E6
I/O
I/O
B3
I/O
I/O
E7
VCCI
I/O
VCCI
I/O
B4
PRA, I/O
CLKA
I/O
PRA, I/O
CLKA
I/O
F1
B5
F2
I/O
I/O
B6
F3
I/O
I/O
B7
GND
I/O
GND
I/O
F4
I/O
I/O
C1
F5
HCLK
I/O
HCLK
I/O
C2
TDI, I/O
VCCI
GND
CLKB
VCCA
I/O
TDI, I/O
VCCI
GND
CLKB
VCCA
I/O
F6
C3
F7
TDO, I/O
I/O
TDO, I/O
I/O
C4
G1
G2
G3
G4
G5
G6
G7
C5
I/O
I/O
C6
I/O
I/O
C7
PRB, I/O
VCCA
I/O
PRB, I/O
VCCA
I/O
D1
I/O
I/O
D2
TMS
GND
GND
TMS
GND
GND
D3
I/O
I/O
D4
Revision 5
2-7
Package Pin Assignments
CS128
A1 Ball Pad Corner
2
3
4
5
6
8
12
1
7
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/rescenter/package/index.html.
2-8
Revision 5
ex Automotive Family FPGAs
CS128
CS128
eX64
Pin Number Function
eX128
Function
eX256
Function
eX64
Pin Number Function
eX128
Function
eX256
Function
A1
A2
I/O
TCK, I/O
VCCI
I/O
I/O
TCK, I/O
VCCI
I/O
I/O
TCK, I/O
VCCI
I/O
C12
D1
I/O
NC
I/O
I/O
I/O
I/O
A3
D2
I/O
I/O
I/O
A4
D3
I/O
I/O
I/O
A5
I/O
I/O
I/O
D4
I/O
I/O
I/O
A6
VCCA
I/O
VCCA
I/O
VCCA
I/O
D5
I/O
I/O
I/O
A7
D6
GND
I/O
GND
I/O
GND
I/O
A8
I/O
I/O
I/O
D7
A9
VCCI
I/O
VCCI
I/O
VCCI
I/O
D8
GND
I/O
GND
I/O
GND
I/O
A10
A11
A12
B1
D9
I/O
I/O
I/O
D10
D11
D12
E1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TMS
I/O
TMS
I/O
TMS
I/O
VCCI
NC
VCCI
I/O
VCCI
I/O
B2
B3
I/O
I/O
I/O
E2
VCCI
I/O
VCCI
I/O
VCCI
I/O
B4
I/O
I/O
I/O
E3
B5
I/O
I/O
I/O
E4
GND
GND
I/O
GND
GND
I/O
GND
GND
I/O
B6
PRA, I/O
CLKB
I/O
PRA, I/O
CLKB
I/O
PRA, I/O
CLKB
I/O
E9
B7
E10
E11
E12
F1
B8
GND
VCCA
NC
GND
VCCA
I/O
GND
VCCA
I/O
B9
I/O
I/O
I/O
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
F2
NC
I/O
I/O
F3
NC
I/O
I/O
I/O
I/O
I/O
F4
I/O
I/O
I/O
TDI, I/O
I/O
TDI, I/O
I/O
TDI, I/O
I/O
F9
GND
NC
GND
I/O
GND
I/O
F10
F11
F12
G1
G2
G3
G4
G9
G10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA
I/O
CLKA
I/O
CLKA
I/O
NC
I/O
I/O
TRST, I/O
I/O
TRST, I/O
I/O
TRST, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
NC
GND
GND
I/O
GND
GND
I/O
NC
I/O
I/O
NC
I/O
I/O
Revision 5
2-9
Package Pin Assignments
CS128
CS128
eX64
eX128
Function
eX256
Function
eX64
Pin Number Function
eX128
Function
eX256
Function
Pin Number Function
G11
G12
H1
H2
H3
H4
H9
H10
H11
H12
J1
I/O
NC
I/O
I/O
I/O
I/O
K8
K9
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
K10
K11
K12
L1
I/O
I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
TDO, I/O
I/O
VCCI
GND
I/O
VCCI
GND
I/O
VCCI
GND
I/O
I/O
I/O
I/O
L2
I/O
I/O
I/O
VCCI
VCCA
NC
VCCI
VCCA
I/O
VCCI
VCCA
I/O
L3
NC
I/O
I/O
L4
I/O
I/O
I/O
L5
I/O
I/O
I/O
NC
NC
VCCA
I/O
L6
I/O
I/O
I/O
J2
I/O
I/O
L7
I/O
I/O
I/O
J3
VCCI
I/O
VCCI
I/O
VCCI
I/O
L8
I/O
I/O
I/O
J4
L9
I/O
I/O
I/O
J5
I/O
I/O
I/O
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
I/O
I/O
I/O
J6
I/O
I/O
I/O
NC
I/O
I/O
J7
GND
I/O
GND
I/O
GND
I/O
VCCI
GND
I/O
VCCI
GND
I/O
VCCI
GND
I/O
J8
J9
GND
I/O
GND
I/O
GND
I/O
J10
J11
J12
K1
K2
K3
K4
K5
K6
K7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
VCCA
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
HCLK
PRB, I/O
HCLK
PRB, I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
2-10
Revision 5
ex Automotive Family FPGAs
CS180
A1 Ball Pad Corner
12
1
2
3
4
5
6
7
9 10
14
13
8
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Note
For Package Manufacturing and Environmental information, visit the Resource Center at
http://www.microsemi.com/soc/products/rescenter/package/index.html.
Revision 5
2-11
Package Pin Assignments
CS180
CS180
CS180
CS180
eX256
Pin Number Function
eX256
Pin Number Function
eX256
Pin Number Function
eX256
Pin Number Function
A1
A2
I/O
I/O
C6
C7
I/O
PRA, I/O
CLKB
I/O
E11
E12
E13
E14
F1
I/O
I/O
H14
J1
I/O
I/O
A3
GND
NC
C8
VCCI
I/O
J2
GND
I/O
A4
C9
J3
A5
NC
C10
C11
C12
C13
C14
D1
I/O
I/O
J4
VCCI
GND
I/O
A6
NC
I/O
F2
I/O
J5
A7
NC
GND
I/O
F3
VCCI
I/O
J10
J11
J12
J13
J14
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
L1
A8
NC
F4
VCCI
VCCA
I/O
A9
NC
I/O
F5
GND
GND
I/O
A10
A11
A12
A13
A14
B1
NC
I/O
F10
F11
F12
F13
F14
G1
NC
D2
I/O
I/O
I/O
D3
TDI, I/O
I/O
GND
VCCA
I/O
I/O
I/O
D4
VCCA
I/O
I/O
D5
I/O
I/O
D6
I/O
VCCA
I/O
VCCI
I/O
B2
I/O
D7
CLKA
I/O
G2
B3
TCK, I/O
VCCI
I/O
D8
G3
I/O
I/O
B4
D9
I/O
G4
I/O
I/O
B5
D10
D11
D12
D13
D14
E1
I/O
G5
I/O
GND
I/O
B6
I/O
I/O
G10
G11
G12
G13
G14
H1
GND
I/O
B7
VCCA
I/O
I/O
GND
I/O
B8
I/O
I/O
B9
I/O
I/O
I/O
I/O
B10
B11
B12
B13
B14
C1
C2
VCCI
I/O
I/O
VCCA
I/O
I/O
E2
I/O
I/O
I/O
E3
I/O
H2
I/O
I/O
I/O
E4
I/O
H3
TRST, I/O
I/O
L2
I/O
I/O
E5
I/O
H4
L3
I/O
I/O
E6
I/O
H5
GND
GND
I/O
L4
I/O
TMS
I/O
E7
GND
I/O
H10
H11
H12
H13
L5
I/O
C3
C4
C5
E8
L6
I/O
I/O
E9
GND
I/O
I/O
L7
PRB, I/O
HCLK
I/O
E10
I/O
L8
2-12
Revision 5
ex Automotive Family FPGAs
CS180
CS180
eX256
Pin Number Function
eX256
Pin Number Function
L9
L10
L11
L12
L13
L14
M1
I/O
I/O
N14
P1
I/O
I/O
I/O
P2
I/O
TDO, I/O
I/O
P3
I/O
P4
NC
NC
NC
NC
NC
NC
NC
NC
GND
I/O
I/O
P5
I/O
P6
M2
I/O
P7
M3
I/O
P8
M4
I/O
P9
M5
I/O
P10
P11
P12
P13
M6
I/O
M7
I/O
M8
I/O
M9
I/O
M10
M11
M12
M13
M14
N1
I/O
I/O
I/O
VCCI
I/O
I/O
N2
GND
I/O
N3
N4
I/O
N5
I/O
N6
I/O
N7
I/O
N8
VCCA
I/O
N9
N10
N11
N12
N13
I/O
I/O
I/O
I/O
Revision 5
2-13
3 – Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Revision
Changes
Page
Revision 5
(October 2012)
The datasheet was updated for Microsemi, including hyperlinks to the Microsemi
SoC Products Group website. The versioning system has been changed.
Datasheets are assigned a revision number that increments each time the
datasheet is revised.
All
The "Features" section and "User Security" section were updated to clarify that
although no existing security measures can give an absolute guarantee,
Microsemi FPGAs implement industry standard security (SAR 34676).
i, 1-5
i, 2-1
ii
Package names used in the product profile tables and "Package Pin Assignments"
section section were revised to match standards given in Package Mechanical
Drawings (SAR 34778).
v3.2
(June 2006)
The "Ordering Information" section was updated to include RoHS information. The
TQFP measurement was also updated.
The "Dedicated Test Mode" section was updated.
1-9
1-16
ii
Note 4 was added to the"3.3 V LVTTL Electrical Specifications" table.
A note was added to the "Ordering Information" section.
v3.1
(April 2006)
The Junction temperature was added to Table 1-8 • Absolute Maximum Ratings*.
The note was changed in Table 1-9 • Recommended Operating Conditions.
1-15
1-15
1-16
The IOH and IOL values were updated in the "3.3 V LVTTL Electrical
Specifications" table.
The "5 V Tolerance of 3.3 V LVTTL I/Os Using a Tristate Buffer" section is new.
1-17
1-15
A reference to Table 1-9 • Recommended Operating Conditions was added to the
"Junction Temperature".
v3.0
(June 2004)
The "Speed Grade and Temperature Grade Matrix" table is new.
Table 1-2 • I/O Features was updated.
ii
1-6
Table 1-9 • Recommended Operating Conditions was updated.
The "CEQ Values for eX Devices" section is new.
The "Package Thermal Characteristics" section was updated.
Table 1-14 • Input Buffer Delays was updated.
1-15
1-18
1-19
1-22
1-20
1-28
Figure 1-15 • eX Timing Model was updated.
The "Pin Descriptions" section was updated.
Revision 5
3-1
Datasheet Information
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before
data has been fully characterized from silicon devices. The data provided is designated as either
"Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as
follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general
product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production. This label only applies to the
DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not
been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is
believed to be correct, but changes are possible.
Production
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The product described in this datasheet is subject to the Export Administration Regulations (EAR). They
could require an approved export license prior to export from the United States. An export includes
release of product or disclosure of technology to a foreign national inside or outside the United States.
3-2
Revision 5
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo CA 92656 USA
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Fax: +1 (949) 215-4996
51700017-5/10.12
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