JCUFCMEN15 [MICROSEMI]

PECL Output Clock Oscillator, 15MHz Nom, ROHS COMPLIANT, HERMETIC SEALED, J-LEADE, CERAMIC, SOJ-6;
JCUFCMEN15
型号: JCUFCMEN15
厂家: Microsemi    Microsemi
描述:

PECL Output Clock Oscillator, 15MHz Nom, ROHS COMPLIANT, HERMETIC SEALED, J-LEADE, CERAMIC, SOJ-6

文件: 总10页 (文件大小:200K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
J-Type  
Voltage Controlled Crystal Oscillator  
Product is compliant to RoHS directive  
and fully compatible with lead free assembly  
Features  
Output Frequencies from 1.024 MHz to 170.000 MHz  
+3.3 or +5.0 volt options  
Small 14mm x 9mm J-type Package  
CMOS or PECL Outputs  
Low phase noise and custom options  
0/70° C or –40/85° C operating temperature  
Tri-State output (CMOS) Enable/Disable (PECL)  
Applications  
Clock Smoothing  
The J-type Voltage Controlled Crystal Oscillator  
Frequency Translation  
SONET, SDH, ATM, DSLAM, ADM  
Description  
The J-type voltage controlled crystal oscillator  
expands VI’s advanced VCXO performance  
capabilities while adhering to a package footprint  
compatible with the industry-common J-lead package.  
The J-type VCXO is a quartz stabilized square wave  
generator with either a CMOS output for driving  
CMOS/TTL loads or a PECL output. The device is  
packaged in a 6 pin J-lead ceramic package and is  
hermetically sealed with a grounded conductive lid.  
Table of Contents  
Page 2- 6 -- CMOS  
Page 7- 11 -- PECL  
The first section of this data sheet covers the  
performance/packaging/tape and reel/ordering  
information for the CMOS version and then the  
information for the PECL option follows.  
Vectron International 267 Lowell Rd. Hudson, NH 03051  
Tel:1-88-VECTRON-1  
e-mail: vectron@vectron.com  
J-Type Voltage Controlled Crystal Oscillator  
Table 1. Pin Out Information for the CMOS output Option  
6
5
4
Pin  
Symbol  
Function  
1
2
VC  
VCXO Control Voltage  
TTL logic low disables output.  
Tri-State1  
TOP VIEW  
TTL logic high, or no connect, enables output.  
3
4
5
GND  
Output  
CMOS/TTL  
select1,2  
VCC  
Case and Electrical Ground  
1
VCXO Output  
TTL logic low optimizes symmetry for CMOS.  
TTL logic high, or NC, optimizes symmetry for TTL  
2
3
6
Power Supply Voltage (5.0 V or 3.3 V ±10%)  
1. Standard option. Tri-State can be connected to pin 5 and CMOS/TTL select would be on pin 2.  
2. Output is HCMOS. For frequencies >12MHz, this option optimizes symmetry for either CMOS or TTL thresholds. Ground this pin  
for frequencies < 12MHz.  
Table 2. Electrical Performance @ 25°C for the CMOS output option  
Parameter  
Supply Voltage 1, +5 volt option  
+3.3 volt option  
Symbol  
Minimum  
4.5  
Typical Maximum Units  
5.0  
3.3  
5.5  
3.6  
V
V
3.0  
Supply Current  
10mA + 0.25mA per MHz, typical  
Center Frequency, see ordering information  
Operating Temperature, see ordering info  
Absolute Pull Range over the operating  
temperature range, aging and power supply  
Vc= 0.5 to 4.5 or 0.3 to 3.0 V  
see ordering information for options  
Gain Transfer  
FN  
TOP  
APR  
1.024  
77.760  
MHz  
°C  
ppm  
0/70, -40/85  
±50 to ±100  
KV  
Positive  
(Frequency vs. Control Voltage)  
Output Level High2  
VOH  
VOL  
tR/ tF  
SYM  
IL  
0.8*Vcc  
-
-
V
V
ns  
%
uA  
kHz  
ps  
ps  
Output Level Low2  
0.1*Vcc  
5
Output Rise/Fall Time2  
Duty Cycle3, see ordering info  
Input Leakage  
45/55 or 40/60  
±1  
-
Control Voltage Modulation Bandwidth  
RMS Jitter, 77.760MHz  
RMS Jitter, 77.760MHz, 12kHz to 20MHz  
Maximum Control Voltage  
Maximum Supply Voltage  
BW  
-
10  
3
<0.5  
0
VDD  
7
V
Storage Temperature  
Soldering Temp./Time  
TS  
TLS  
-55  
-
-
-
125  
240/10  
°C  
°C/s  
1. Power supply bypass is required and a 0.1uF in parallel with a 0.01uF high frequency capacitor is recommended.  
2. Figure 1 defines these parameters. Figure 2 illustrates the load used to test devices.  
3. Duty cycle is defined as on-time versus period at 1.4 V for TTL, and 2.5 V for CMOS (5volt supply) and at 1.65 V for CMOS (3.3  
volt operation)  
TF  
TR  
IDD  
650  
Ohm  
80%  
50%  
20%  
6
1
2
5
3
+
-
4
VDD  
.01µF  
.1µF  
IC  
VC  
On Time  
15pF  
1.8k  
Ohm  
+
-
Period  
Figure 1. Output Waveform  
Figure 2. Output Test Conditions (25±5°C)  
for 5 volt devices, 15pF cap only for 3.3V.  
Vectron International 267 Lowell Rd. Hudson, NH 03051 Tel:1-88-VECTRON-1  
e-mail vectron@vectron.com  
2
J-Type Voltage Controlled Crystal Oscillator  
Qualification Conformance  
The CMOS J-type family has undergone the following Mil-Std qualification:  
Table 3. Environmental Compliance  
Parameter  
Conditions  
Mechanical Shock  
Mechanical Vibration  
Solderability  
Gross and Fine Leak  
Resistance to Solvents  
MIL-STD-883, Method 2002  
MIL-STD-883, Method 2007  
MIL-STD-883, Method 2003  
MIL-STD-883, Method 1014  
MIL-STD-883, Method 2015  
Handling Precautions  
Although ESD protection circuitry has been designed into the the J-type, proper precautions should be  
taken when handling and mounting. VI employs a human body model and a charged-device model  
(CDM) for ESD susceptibility testing and design protection evaluation. ESD thresholds are dependent on  
the circuit parameters used to define the model. Although no industry wide standard has been adopted  
for the CDM, a standard HBM of resistance = 1.5Kohms and capacitance = 100pF is widely used and  
therefore can be used for comparison purposes.  
Table 4. ESD Ratings  
Model  
Minimum  
1500 V  
1500 V  
Human Body Model (HBM)  
Charged Device Model (CDM)  
Reflow Profile (IPC/JEDEC J-STD-020C)  
Parameter  
Symbol  
Value  
PreHeat Time  
t S  
60 sec Min, 180 sec Max  
3 oC/sec Max  
Ramp Up  
R UP  
t L  
Time Above 217 oC  
Time To Peak Temperature  
Time At 260 oC  
60 sec Min, 150 sec Max  
480 sec Max  
t AMB-P  
t P  
20 sec Min, 40 sec Max  
6 oC/sec Max  
Ramp Down  
R DN  
t L  
t P  
260  
R UP  
217  
200  
R DN  
150  
t S  
t AMB-P  
25  
Time (sec)  
Vectron International 267 Lowell Rd. Hudson, NH 03051 Tel:1-88-VECTRON-1  
e-mail vectron@vectron.com  
3
J-Type Voltage Controlled Crystal Oscillator  
Figure 4. Outline Diagram  
Dimensions are in  
inches and (millimeters)  
0.118  
(3.00)  
0.030  
(0.077)  
0.200  
(5.08)  
0.100  
(2.54)  
0.346  
(8.80)  
Figure 5. Suggested Pad Layout  
Vectron International 267 Lowell Rd. Hudson, NH 03051 Tel:1-88-VECTRON-1  
e-mail vectron@vectron.com  
4
J-Type Voltage Controlled Crystal Oscillator  
J
I
G
C
D
F
B
A
L
E
K
H
Bottom Holes for TRU  
and VCO Products Only  
Figure 6. Tape Reel Drawing for CMOS and PECL output option  
Table 5. Tape and Reel Dimensions (mm)  
Tape Dimensions  
Reel Dimensions  
# Per  
Reel  
200  
Product  
A
B
C
D
E
F
G
H
I
J
K
L
J-Type  
24  
11.5  
1.5  
4
12  
1.78  
21  
13  
100  
5
25  
330  
Table 6. Ordering Information for the CMOS output version (add frequency)  
Operating  
Package  
Supply  
Voltage  
(V)  
Tri-State  
Specials  
VCXO  
Type  
APR  
Output/ Duty  
Cycle  
Temp.  
( °C )  
(ppm)  
Min/Max  
Standard  
6 pin  
VCXO  
0/70  
TTL/  
Tri State  
on pin 2  
C
D
U
L
G
C
L
A
J
T
N
5V±10%  
±50  
±80  
J
Ceramic  
SOJ  
CMOS  
45/55%1  
CMOS  
45/55%2  
-40/ 85  
N
3.3±10%  
±10%  
linear  
VCXO  
CMOS  
H
K
±100  
40/60%3  
1. Output is CMOS and symmetry is tested at TTL and CMOS thresholds.  
2. Output is CMOS and symmetry is tested at CMOS threshold. This option is used for 3.3 V operation.  
3. Output is CMOS and symmetry is tested at CMOS thresholds. This option is required for 3.3V, frequencies  
>51.840MHz.  
4. Note: Not all combinations are possible.  
Example: JDUGCKTN 77.76 = 3.3 volt, VCXO@77.760, ±50 ppm APR, 0/70°C,  
40/60% Symmetry, CMOS, Tri-State on pin 2.  
Vectron International 267 Lowell Rd. Hudson, NH 03051 Tel:1-88-VECTRON-1  
e-mail vectron@vectron.com  
5
J-Type Voltage Controlled Crystal Oscillator  
Table 7. Standard Frequencies, in MHz, for CMOS output option  
1.024  
3.686  
1.544  
4.000  
2.000  
4.032  
2.048  
4.096  
3.088  
4.434  
3.580  
5.000  
6.144  
6.176  
6.312  
6.400  
8.000  
8.192  
8.448  
10.000  
15.360  
20.000  
30.000  
40.000  
62.208  
12.000  
15.440  
20.480  
32.000  
40.960  
65.536  
12.288  
16.000  
24.000  
32.768  
44.736  
77.760  
12.352  
16.384  
24.576  
34.368  
50.000  
155.5201  
13.000  
18.432  
24.704  
35.328  
51.840  
14.318  
19.440  
27.000  
38.880  
52.000  
1. Uses a PLL multiplier, jitter is 25ps rms typical vs 3ps typical for a HFF design  
Other frequencies available upon request.  
Table 8. Pin Out Information for the PECL output option  
6
5
4
Pin  
Symbol  
Function  
1
2
3
4
5
6
VC  
VCXO Control Voltage  
N/C or E/D2  
GND  
No Connect or Output Disable  
Case and Electrical Ground  
VCXO Output  
TOP VIEW  
Output  
COutput  
VCC  
1
2
3
VCXO Complementary Output  
Power Supply Voltage (5.0 V or 3.3 V ±10%)  
. By setting OD high, the outputs are disabled and OUT is held low while Complementary OUT is held high. Output is enabled if E/D  
< VCC-1.6V,  
2. See ordering information for enable/disable option.  
Table 9. Electrical Performance @ 25°C for the PECL output option  
Parameter  
Supply Voltage 1, +5 volt option  
+3.3 volt option  
Symbol  
Minimum  
4.5  
Typical  
5.0  
Maximum  
5.5  
Units  
V
V
3.0  
3.3  
3.6  
Supply Current  
frequency dependent  
Center Frequency, see ordering information  
Operating Temperature, see ordering info  
Absolute Pull Range over the operating  
temperature range, aging and power supply.  
Vc= 0.5 to 4.5 or 0.3 to 3.0  
see ordering information for options  
Gain Transfer  
FN  
TOP  
APR  
15  
170  
MHz  
°C  
ppm  
0/70, -40/85  
±32, ±50  
KV  
Positive  
(Frequency vs. Control Voltage)  
Output Level High2  
VOH  
VOL  
Vcc-1.025  
Vcc-1.810  
-
-
Vcc-0.880  
Vcc-1.620  
V
V
Output Level Low2  
Output Logic Levels for -40 to 85°C Operation  
Output Level High2  
VOH  
VOL  
tR/tf  
SYM  
IL  
Vcc-1.085  
Vcc-1.830  
Vcc-0.880  
Vcc-1.555  
1
V
V
ns  
Output Level Low2  
Output Rise and Fall Time2  
Duty Cycle3, see ordering info  
Input Leakage  
45/55  
0.1  
%
mA  
pS  
kHz  
<1  
RMS Jitter, 12kHz to 20 MHz, P option (HFF)  
Control Voltage Modulation Bandwidth  
Maximum Control Voltage  
Maximum Supply Voltage  
Storage Temperature  
BW  
10  
0
VDD  
7
125  
V
°C  
°C/s  
TS  
TLS  
-55  
-
-
-
Soldering Temp./Time  
240/10  
1. Power supply bypass is required and a 0.1uF in parallel with a 0.01uF high frequency capacitor is recommended.  
2. Transition times are measured from 20% to 80% of a full 10K ECL level swing.  
Vectron International 267 Lowell Rd. Hudson, NH 03051 Tel:1-88-VECTRON-1  
e-mail vectron@vectron.com  
6
J-Type Voltage Controlled Crystal Oscillator  
VCC-2  
+
-
TF  
TR  
ICC  
50  
50  
80%  
50%  
20%  
6
1
2
5
+
-
VCC  
.1µF  
.01µF  
3
4
.01µF  
On Time  
Period  
Figure 7. Output Waveform  
Figure 8. Output Test Conditions (25±5°C)  
VC  
6
Control Voltage =  
0.5 to 4.5V (+5V supply)  
0.3 to 3.3V (+3.3V supply)  
VCC  
Output  
1
5
Control Voltage  
Output  
4
Ground  
Vcc- 2 V  
(Standard PECL termination)  
3
Figure 9. PECL Operation  
44.736MHz  
8kHz  
Loop Filter  
J-type  
44.736MHz  
φ and Freq  
Detector  
Divide by 5592  
Figure 10. Typical Frequency Translation Diagram  
155.52MHz  
155.52MHz  
Loop Filter  
J-type  
155.520MHz  
φ and Freq  
Detector  
Vectron International 267 Lowell Rd. Hudson, NH 03051 Tel:1-88-VECTRON-1  
e-mail vectron@vectron.com  
7
J-Type Voltage Controlled Crystal Oscillator  
Figure 11. Typical Clock Smoothing Diagram  
Figure 12. Outline Diagram  
Dimensions are in  
inches and (millimeters)  
0.118  
(3.00)  
0.030  
(0.077)  
0.200  
(5.08)  
0.100  
(2.54)  
0.346  
(8.80)  
Figure 13. Suggested Pad Layout  
Vectron International 267 Lowell Rd. Hudson, NH 03051 Tel:1-88-VECTRON-1  
e-mail vectron@vectron.com  
8
J-Type Voltage Controlled Crystal Oscillator  
J
I
G
C
D
F
B
A
L
E
K
H
Bottom Holes for TRU  
and VCO Products Only  
Figure 14. Tape Reel Drawing for CMOS and PECL output option  
Table 10. Tape and Reel Dimensions (mm)  
Tape Dimensions  
Reel Dimensions  
# Per  
Reel  
200  
Product  
A
B
C
D
E
F
G
H
I
J
K
L
J-Type  
24  
11.5  
1.5  
4
12  
1.78  
21  
13  
100  
5
25  
330  
Vectron International 267 Lowell Rd. Hudson, NH 03051 Tel:1-88-VECTRON-1  
e-mail vectron@vectron.com  
9
J-Type Voltage Controlled Crystal Oscillator  
Table 11. Ordering Information for PECL output option (add frequency)  
Operating  
Package  
Supply  
Voltage  
(V)  
Enable/  
Disable  
Specials  
VCXO  
Type  
APR  
Output/ Duty  
Cycle  
Temp.  
( °C )  
(ppm)  
Min/Max  
6 pin  
Ceramic  
SOJ  
VCXO  
0/70  
PECL  
45/55%  
None  
Standard  
C
D
U
L
F
C
L
M
U
E
N
P
R
T
5V±10%  
±32  
J
-40/ 85  
Enable/  
Disable  
on pin 2  
6pS rms  
jitter  
G
3.3±10%  
±10%  
linear  
VCXO  
±20ppm  
stability  
VCXO  
±50  
12ps rms  
jitter  
M
20ps  
rms  
jitter  
1. Note: Not all combinations are possible.  
Example: JDUGLMEP 77.76 = 3.3 volt, VCXO @ 77.760MHz, ±50 ppm, APR,  
-40/85°C, PECL, Enable/Disable on pin 2, 6ps rms jitter.  
Table 12. Standard Frequencies, in MHz  
77.760  
82.944  
155.52  
Other frequencies available upon request.  
For Additional Information, Please Contact:  
USA: Vectron International 267 Lowell Rd, Hudson, NH 03051 Tel: 1-88-  
VECTRON-1 Fax: 1-888-FAX-VECTRON  
EUROPE: In Denmark, Finland, Ireland, Israel, Norway, Spain, UK: Tel: 44 (0) 1703  
766 288 Fax: 44 (0) 1703 766 822  
In Austria,Belgium,France,Germany,Italy,  
Luxenburg,Netherlands,Sweden,Switzerland:Tel: 49(0)7263 6480 Fax:49(0)7263  
6196  
ASIA: In China, Taiwan, Japan: Tel: 01 603 598 0070 Fax: 01 603 598 0075  
In Korea, Singapore, Australia, India: Tel: 01 203 853 4433 Fax: 01 203 853 1423  
www.vectron.com  
Vectron International reserves the right to make changes to the product(s) and/ or information contained herein without notice. No liability is assumed  
as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.  
REVISION DATE: 10/2/07  
Vectron International 267 Lowell Rd. Hudson, NH 03051 Tel:1-88-VECTRON-1  
e-mail vectron@vectron.com  
10  

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